1 /* 2 * Copyright (c) 2023 Benjamin Björnsson <benjamin.bjornsson@gmail.com> 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32C0_CLOCK_H_ 7 #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32C0_CLOCK_H_ 8 9 #include "stm32_common_clocks.h" 10 11 /** Bus clocks */ 12 #define STM32_CLOCK_BUS_IOP 0x034 13 #define STM32_CLOCK_BUS_AHB1 0x038 14 #define STM32_CLOCK_BUS_APB1 0x03c 15 #define STM32_CLOCK_BUS_APB1_2 0x040 16 17 #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_IOP 18 #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1_2 19 20 /** Domain clocks */ 21 /* RM0490, §5.4.21/22 Clock configuration register (RCC_CCIPRx) */ 22 23 /** System clock */ 24 /* defined in stm32_common_clocks.h */ 25 /** Fixed clocks */ 26 /* Low speed clocks defined in stm32_common_clocks.h */ 27 #define STM32_SRC_HSI (STM32_SRC_LSI + 1) 28 #define STM32_SRC_HSE (STM32_SRC_HSI + 1) 29 /** Peripheral bus clock */ 30 #define STM32_SRC_PCLK (STM32_SRC_HSE + 1) 31 32 /** @brief RCC_CCIPR register offset */ 33 #define CCIPR_REG 0x54 34 35 /** @brief RCC_CSR1 register offset */ 36 #define CSR1_REG 0x5C 37 38 /** @brief RCC_CFGRx register offset */ 39 #define CFGR1_REG 0x08 40 41 /** @brief Device domain clocks selection helpers */ 42 /** CCIPR devices */ 43 #define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG) 44 #define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG) 45 #define I2C2_I2S1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 14, CCIPR_REG) 46 #define ADC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 30, CCIPR_REG) 47 /** CSR1 devices */ 48 #define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CSR1_REG) 49 50 /** CFGR1 devices */ 51 #define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 24, CFGR1_REG) 52 #define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 28, CFGR1_REG) 53 #define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 16, CFGR1_REG) 54 #define MCO2_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 20, CFGR1_REG) 55 56 /* MCO prescaler : division factor */ 57 #define MCO_PRE_DIV_1 0 58 #define MCO_PRE_DIV_2 1 59 #define MCO_PRE_DIV_4 2 60 #define MCO_PRE_DIV_8 3 61 #define MCO_PRE_DIV_16 4 62 #define MCO_PRE_DIV_32 5 63 #define MCO_PRE_DIV_64 6 64 #define MCO_PRE_DIV_128 7 65 66 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32C0_CLOCK_H_ */ 67
