1 /*
2 * Copyright (c) 2019 Mohamed ElShahawi (extremegtx@hotmail.com)
3 * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #define DT_DRV_COMPAT espressif_esp32_uart
9
10 /* Include esp-idf headers first to avoid redefining BIT() macro */
11 /* TODO: include w/o prefix */
12 #ifdef CONFIG_SOC_SERIES_ESP32
13 #include <esp32/rom/ets_sys.h>
14 #include <esp32/rom/gpio.h>
15 #include <soc/dport_reg.h>
16 #elif defined(CONFIG_SOC_SERIES_ESP32S2)
17 #include <esp32s2/rom/ets_sys.h>
18 #include <esp32s2/rom/gpio.h>
19 #include <soc/dport_reg.h>
20 #elif defined(CONFIG_SOC_SERIES_ESP32S3)
21 #include <esp32s3/rom/ets_sys.h>
22 #include <esp32s3/rom/gpio.h>
23 #include <zephyr/dt-bindings/clock/esp32s3_clock.h>
24 #elif defined(CONFIG_SOC_SERIES_ESP32C2)
25 #include <esp32c2/rom/ets_sys.h>
26 #include <esp32c2/rom/gpio.h>
27 #include <zephyr/dt-bindings/clock/esp32c2_clock.h>
28 #elif defined(CONFIG_SOC_SERIES_ESP32C3)
29 #include <esp32c3/rom/ets_sys.h>
30 #include <esp32c3/rom/gpio.h>
31 #include <zephyr/dt-bindings/clock/esp32c3_clock.h>
32 #elif defined(CONFIG_SOC_SERIES_ESP32C6)
33 #include <esp32c6/rom/ets_sys.h>
34 #include <esp32c6/rom/gpio.h>
35 #include <zephyr/dt-bindings/clock/esp32c6_clock.h>
36 #endif
37 #ifdef CONFIG_UART_ASYNC_API
38 #include <zephyr/drivers/dma.h>
39 #include <zephyr/drivers/dma/dma_esp32.h>
40 #include <hal/uhci_ll.h>
41 #endif
42 #include <soc/uart_struct.h>
43 #include <hal/uart_ll.h>
44 #include <hal/uart_hal.h>
45 #include <hal/uart_types.h>
46 #include <esp_clk_tree.h>
47 #include <zephyr/drivers/pinctrl.h>
48
49 #include <soc/uart_reg.h>
50 #include <zephyr/device.h>
51 #include <soc.h>
52 #include <zephyr/drivers/uart.h>
53
54 #if defined(CONFIG_SOC_SERIES_ESP32C2) || \
55 defined(CONFIG_SOC_SERIES_ESP32C3) || \
56 defined(CONFIG_SOC_SERIES_ESP32C6)
57 #include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
58 #else
59 #include <zephyr/drivers/interrupt_controller/intc_esp32.h>
60 #endif
61
62 #include <zephyr/drivers/clock_control.h>
63 #include <errno.h>
64 #include <zephyr/sys/util.h>
65 #include <esp_attr.h>
66 #include <zephyr/logging/log.h>
67
68 LOG_MODULE_REGISTER(uart_esp32, CONFIG_UART_LOG_LEVEL);
69
70 #if defined(CONFIG_SOC_SERIES_ESP32C2) || \
71 defined(CONFIG_SOC_SERIES_ESP32C3) || \
72 defined(CONFIG_SOC_SERIES_ESP32C6)
73 #define ISR_HANDLER isr_handler_t
74 #else
75 #define ISR_HANDLER intr_handler_t
76 #endif
77
78 struct uart_esp32_config {
79 const struct device *clock_dev;
80 const struct pinctrl_dev_config *pcfg;
81 const clock_control_subsys_t clock_subsys;
82 int irq_source;
83 int irq_priority;
84 int irq_flags;
85 bool tx_invert;
86 bool rx_invert;
87 #if CONFIG_UART_ASYNC_API
88 const struct device *dma_dev;
89 uint8_t tx_dma_channel;
90 uint8_t rx_dma_channel;
91 #endif
92 };
93
94 #if CONFIG_UART_ASYNC_API
95 struct uart_esp32_async_data {
96 struct k_work_delayable tx_timeout_work;
97 const uint8_t *tx_buf;
98 size_t tx_len;
99 struct k_work_delayable rx_timeout_work;
100 uint8_t *rx_buf;
101 uint8_t *rx_next_buf;
102 size_t rx_len;
103 size_t rx_next_len;
104 size_t rx_timeout;
105 volatile size_t rx_counter;
106 size_t rx_offset;
107 uart_callback_t cb;
108 void *user_data;
109 };
110 #endif
111
112 /* driver data */
113 struct uart_esp32_data {
114 struct uart_config uart_config;
115 uart_hal_context_t hal;
116 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
117 uart_irq_callback_user_data_t irq_cb;
118 void *irq_cb_data;
119 #endif
120 #if CONFIG_UART_ASYNC_API
121 struct uart_esp32_async_data async;
122 uhci_dev_t *uhci_dev;
123 const struct device *uart_dev;
124 #endif
125 };
126
127 #define UART_FIFO_LIMIT (UART_LL_FIFO_DEF_LEN)
128 #define UART_TX_FIFO_THRESH (CONFIG_UART_ESP32_TX_FIFO_THRESH)
129 #define UART_RX_FIFO_THRESH (CONFIG_UART_ESP32_RX_FIFO_THRESH)
130
131 #if CONFIG_UART_INTERRUPT_DRIVEN || CONFIG_UART_ASYNC_API
132 static void uart_esp32_isr(void *arg);
133 #endif
134
uart_esp32_poll_in(const struct device * dev,unsigned char * p_char)135 static int uart_esp32_poll_in(const struct device *dev, unsigned char *p_char)
136 {
137 struct uart_esp32_data *data = dev->data;
138 int inout_rd_len = 1;
139
140 if (uart_hal_get_rxfifo_len(&data->hal) == 0) {
141 return -1;
142 }
143
144 uart_hal_read_rxfifo(&data->hal, p_char, &inout_rd_len);
145
146 return 0;
147 }
148
uart_esp32_poll_out(const struct device * dev,unsigned char c)149 static void uart_esp32_poll_out(const struct device *dev, unsigned char c)
150 {
151 struct uart_esp32_data *data = dev->data;
152 uint32_t written;
153
154 /* Wait for space in FIFO */
155 while (uart_hal_get_txfifo_len(&data->hal) == 0) {
156 ; /* Wait */
157 }
158
159 /* Send a character */
160 uart_hal_write_txfifo(&data->hal, &c, 1, &written);
161 }
162
uart_esp32_err_check(const struct device * dev)163 static int uart_esp32_err_check(const struct device *dev)
164 {
165 struct uart_esp32_data *data = dev->data;
166 uint32_t mask = uart_hal_get_intsts_mask(&data->hal);
167 uint32_t err = mask & (UART_INTR_PARITY_ERR | UART_INTR_FRAM_ERR);
168
169 return err;
170 }
171
172 #ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
173
uart_esp32_get_standard_baud(uint32_t calc_baud)174 static uint32_t uart_esp32_get_standard_baud(uint32_t calc_baud)
175 {
176 const uint32_t standard_bauds[] = {9600, 14400, 19200, 38400, 57600,
177 74880, 115200, 230400, 460800, 921600};
178 int num_bauds = ARRAY_SIZE(standard_bauds);
179 uint32_t baud = calc_baud;
180
181 /* Find the standard baudrate within 0.1% range. If no close
182 * value is found, input is returned.
183 */
184 for (int i = 0; i < num_bauds; i++) {
185 float range = (float)abs(calc_baud - standard_bauds[i]) / standard_bauds[i];
186
187 if (range < 0.001f) {
188 baud = standard_bauds[i];
189 break;
190 }
191 }
192
193 return baud;
194 }
195
uart_esp32_config_get(const struct device * dev,struct uart_config * cfg)196 static int uart_esp32_config_get(const struct device *dev, struct uart_config *cfg)
197 {
198 struct uart_esp32_data *data = dev->data;
199 uart_parity_t parity;
200 uart_stop_bits_t stop_bit;
201 uart_word_length_t data_bit;
202 uart_hw_flowcontrol_t hw_flow;
203 uart_sclk_t src_clk;
204 uint32_t sclk_freq;
205 uint32_t calc_baud;
206
207 uart_hal_get_sclk(&data->hal, &src_clk);
208 esp_clk_tree_src_get_freq_hz((soc_module_clk_t)src_clk,
209 ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &sclk_freq);
210
211 uart_hal_get_baudrate(&data->hal, &calc_baud, sclk_freq);
212 cfg->baudrate = uart_esp32_get_standard_baud(calc_baud);
213
214 uart_hal_get_parity(&data->hal, &parity);
215 switch (parity) {
216 case UART_PARITY_DISABLE:
217 cfg->parity = UART_CFG_PARITY_NONE;
218 break;
219 case UART_PARITY_EVEN:
220 cfg->parity = UART_CFG_PARITY_EVEN;
221 break;
222 case UART_PARITY_ODD:
223 cfg->parity = UART_CFG_PARITY_ODD;
224 break;
225 default:
226 return -ENOTSUP;
227 }
228
229 uart_hal_get_stop_bits(&data->hal, &stop_bit);
230 switch (stop_bit) {
231 case UART_STOP_BITS_1:
232 cfg->stop_bits = UART_CFG_STOP_BITS_1;
233 break;
234 case UART_STOP_BITS_1_5:
235 cfg->stop_bits = UART_CFG_STOP_BITS_1_5;
236 break;
237 case UART_STOP_BITS_2:
238 cfg->stop_bits = UART_CFG_STOP_BITS_2;
239 break;
240 default:
241 return -ENOTSUP;
242 }
243
244 uart_hal_get_data_bit_num(&data->hal, &data_bit);
245 switch (data_bit) {
246 case UART_DATA_5_BITS:
247 cfg->data_bits = UART_CFG_DATA_BITS_5;
248 break;
249 case UART_DATA_6_BITS:
250 cfg->data_bits = UART_CFG_DATA_BITS_6;
251 break;
252 case UART_DATA_7_BITS:
253 cfg->data_bits = UART_CFG_DATA_BITS_7;
254 break;
255 case UART_DATA_8_BITS:
256 cfg->data_bits = UART_CFG_DATA_BITS_8;
257 break;
258 default:
259 return -ENOTSUP;
260 }
261
262 uart_hal_get_hw_flow_ctrl(&data->hal, &hw_flow);
263 switch (hw_flow) {
264 case UART_HW_FLOWCTRL_DISABLE:
265 cfg->flow_ctrl = UART_CFG_FLOW_CTRL_NONE;
266 break;
267 case UART_HW_FLOWCTRL_CTS_RTS:
268 cfg->flow_ctrl = UART_CFG_FLOW_CTRL_RTS_CTS;
269 break;
270 default:
271 return -ENOTSUP;
272 }
273
274 if (uart_hal_is_mode_rs485_half_duplex(&data->hal)) {
275 cfg->flow_ctrl = UART_CFG_FLOW_CTRL_RS485;
276 }
277
278 return 0;
279 }
280 #endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
281
uart_esp32_configure(const struct device * dev,const struct uart_config * cfg)282 static int uart_esp32_configure(const struct device *dev, const struct uart_config *cfg)
283 {
284 const struct uart_esp32_config *config = dev->config;
285 struct uart_esp32_data *data = dev->data;
286 uart_sclk_t src_clk;
287 uint32_t sclk_freq;
288
289 int ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
290
291 if (ret < 0) {
292 return ret;
293 }
294
295 if (!device_is_ready(config->clock_dev)) {
296 return -ENODEV;
297 }
298
299 clock_control_on(config->clock_dev, config->clock_subsys);
300
301 uart_hal_set_sclk(&data->hal, UART_SCLK_DEFAULT);
302 uart_hal_set_rxfifo_full_thr(&data->hal, UART_RX_FIFO_THRESH);
303 uart_hal_set_txfifo_empty_thr(&data->hal, UART_TX_FIFO_THRESH);
304 uart_hal_rxfifo_rst(&data->hal);
305 uart_hal_txfifo_rst(&data->hal);
306
307 switch (cfg->parity) {
308 case UART_CFG_PARITY_NONE:
309 uart_hal_set_parity(&data->hal, UART_PARITY_DISABLE);
310 break;
311 case UART_CFG_PARITY_EVEN:
312 uart_hal_set_parity(&data->hal, UART_PARITY_EVEN);
313 break;
314 case UART_CFG_PARITY_ODD:
315 uart_hal_set_parity(&data->hal, UART_PARITY_ODD);
316 break;
317 default:
318 return -ENOTSUP;
319 }
320
321 switch (cfg->stop_bits) {
322 case UART_CFG_STOP_BITS_1:
323 uart_hal_set_stop_bits(&data->hal, UART_STOP_BITS_1);
324 break;
325 case UART_CFG_STOP_BITS_1_5:
326 uart_hal_set_stop_bits(&data->hal, UART_STOP_BITS_1_5);
327 break;
328 case UART_CFG_STOP_BITS_2:
329 uart_hal_set_stop_bits(&data->hal, UART_STOP_BITS_2);
330 break;
331 default:
332 return -ENOTSUP;
333 }
334
335 switch (cfg->data_bits) {
336 case UART_CFG_DATA_BITS_5:
337 uart_hal_set_data_bit_num(&data->hal, UART_DATA_5_BITS);
338 break;
339 case UART_CFG_DATA_BITS_6:
340 uart_hal_set_data_bit_num(&data->hal, UART_DATA_6_BITS);
341 break;
342 case UART_CFG_DATA_BITS_7:
343 uart_hal_set_data_bit_num(&data->hal, UART_DATA_7_BITS);
344 break;
345 case UART_CFG_DATA_BITS_8:
346 uart_hal_set_data_bit_num(&data->hal, UART_DATA_8_BITS);
347 break;
348 default:
349 return -ENOTSUP;
350 }
351
352 uart_hal_set_mode(&data->hal, UART_MODE_UART);
353
354 switch (cfg->flow_ctrl) {
355 case UART_CFG_FLOW_CTRL_NONE:
356 uart_hal_set_hw_flow_ctrl(&data->hal, UART_HW_FLOWCTRL_DISABLE, 0);
357 break;
358 case UART_CFG_FLOW_CTRL_RTS_CTS:
359 uart_hal_set_hw_flow_ctrl(&data->hal, UART_HW_FLOWCTRL_CTS_RTS, 10);
360 break;
361 case UART_CFG_FLOW_CTRL_RS485:
362 uart_hal_set_mode(&data->hal, UART_MODE_RS485_HALF_DUPLEX);
363 break;
364 default:
365 return -ENOTSUP;
366 }
367
368 uart_hal_get_sclk(&data->hal, &src_clk);
369 esp_clk_tree_src_get_freq_hz((soc_module_clk_t)src_clk,
370 ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &sclk_freq);
371 uart_hal_set_baudrate(&data->hal, cfg->baudrate, sclk_freq);
372
373 uart_hal_set_rx_timeout(&data->hal, 0x16);
374
375 if (config->tx_invert) {
376 uart_hal_inverse_signal(&data->hal, UART_SIGNAL_TXD_INV);
377 }
378
379 if (config->rx_invert) {
380 uart_hal_inverse_signal(&data->hal, UART_SIGNAL_RXD_INV);
381 }
382 return 0;
383 }
384
385 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
386
uart_esp32_fifo_fill(const struct device * dev,const uint8_t * tx_data,int len)387 static int uart_esp32_fifo_fill(const struct device *dev, const uint8_t *tx_data, int len)
388 {
389 struct uart_esp32_data *data = dev->data;
390 uint32_t written = 0;
391
392 if (len < 0) {
393 return 0;
394 }
395
396 uart_hal_write_txfifo(&data->hal, tx_data, len, &written);
397 return written;
398 }
399
uart_esp32_fifo_read(const struct device * dev,uint8_t * rx_data,const int len)400 static int uart_esp32_fifo_read(const struct device *dev, uint8_t *rx_data, const int len)
401 {
402 struct uart_esp32_data *data = dev->data;
403 const int num_rx = uart_hal_get_rxfifo_len(&data->hal);
404 int read = MIN(len, num_rx);
405
406 if (!read) {
407 return 0;
408 }
409
410 uart_hal_read_rxfifo(&data->hal, rx_data, &read);
411 return read;
412 }
413
uart_esp32_irq_tx_enable(const struct device * dev)414 static void uart_esp32_irq_tx_enable(const struct device *dev)
415 {
416 struct uart_esp32_data *data = dev->data;
417
418 uart_hal_clr_intsts_mask(&data->hal, UART_INTR_TXFIFO_EMPTY);
419 uart_hal_ena_intr_mask(&data->hal, UART_INTR_TXFIFO_EMPTY);
420 }
421
uart_esp32_irq_tx_disable(const struct device * dev)422 static void uart_esp32_irq_tx_disable(const struct device *dev)
423 {
424 struct uart_esp32_data *data = dev->data;
425
426 uart_hal_disable_intr_mask(&data->hal, UART_INTR_TXFIFO_EMPTY);
427 }
428
uart_esp32_irq_tx_ready(const struct device * dev)429 static int uart_esp32_irq_tx_ready(const struct device *dev)
430 {
431 struct uart_esp32_data *data = dev->data;
432
433 return (uart_hal_get_txfifo_len(&data->hal) > 0 &&
434 uart_hal_get_intr_ena_status(&data->hal) & UART_INTR_TXFIFO_EMPTY);
435 }
436
uart_esp32_irq_rx_disable(const struct device * dev)437 static void uart_esp32_irq_rx_disable(const struct device *dev)
438 {
439 struct uart_esp32_data *data = dev->data;
440
441 uart_hal_disable_intr_mask(&data->hal, UART_INTR_RXFIFO_FULL);
442 uart_hal_disable_intr_mask(&data->hal, UART_INTR_RXFIFO_TOUT);
443 }
444
uart_esp32_irq_tx_complete(const struct device * dev)445 static int uart_esp32_irq_tx_complete(const struct device *dev)
446 {
447 struct uart_esp32_data *data = dev->data;
448
449 return uart_hal_is_tx_idle(&data->hal);
450 }
451
uart_esp32_irq_rx_ready(const struct device * dev)452 static int uart_esp32_irq_rx_ready(const struct device *dev)
453 {
454 struct uart_esp32_data *data = dev->data;
455
456 return (uart_hal_get_rxfifo_len(&data->hal) > 0);
457 }
458
uart_esp32_irq_err_enable(const struct device * dev)459 static void uart_esp32_irq_err_enable(const struct device *dev)
460 {
461 struct uart_esp32_data *data = dev->data;
462
463 /* enable framing, parity */
464 uart_hal_ena_intr_mask(&data->hal, UART_INTR_FRAM_ERR);
465 uart_hal_ena_intr_mask(&data->hal, UART_INTR_PARITY_ERR);
466 }
467
uart_esp32_irq_err_disable(const struct device * dev)468 static void uart_esp32_irq_err_disable(const struct device *dev)
469 {
470 struct uart_esp32_data *data = dev->data;
471
472 uart_hal_disable_intr_mask(&data->hal, UART_INTR_FRAM_ERR);
473 uart_hal_disable_intr_mask(&data->hal, UART_INTR_PARITY_ERR);
474 }
475
uart_esp32_irq_is_pending(const struct device * dev)476 static int uart_esp32_irq_is_pending(const struct device *dev)
477 {
478 return uart_esp32_irq_rx_ready(dev) || uart_esp32_irq_tx_ready(dev);
479 }
480
uart_esp32_irq_update(const struct device * dev)481 static int uart_esp32_irq_update(const struct device *dev)
482 {
483 struct uart_esp32_data *data = dev->data;
484
485 uart_hal_clr_intsts_mask(&data->hal, UART_INTR_RXFIFO_FULL);
486 uart_hal_clr_intsts_mask(&data->hal, UART_INTR_RXFIFO_TOUT);
487 uart_hal_clr_intsts_mask(&data->hal, UART_INTR_TXFIFO_EMPTY);
488
489 return 1;
490 }
491
uart_esp32_irq_callback_set(const struct device * dev,uart_irq_callback_user_data_t cb,void * cb_data)492 static void uart_esp32_irq_callback_set(const struct device *dev, uart_irq_callback_user_data_t cb,
493 void *cb_data)
494 {
495 struct uart_esp32_data *data = dev->data;
496
497 data->irq_cb = cb;
498 data->irq_cb_data = cb_data;
499
500 #if defined(CONFIG_UART_EXCLUSIVE_API_CALLBACKS)
501 data->async.cb = NULL;
502 data->async.user_data = NULL;
503 #endif
504 }
505
506 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
507
508 #ifdef CONFIG_UART_ASYNC_API
509
uart_esp32_async_timer_start(struct k_work_delayable * work,size_t timeout)510 static inline void uart_esp32_async_timer_start(struct k_work_delayable *work, size_t timeout)
511 {
512 if ((timeout != SYS_FOREVER_US) && (timeout != 0)) {
513 LOG_DBG("Async timer started for %d us", timeout);
514 k_work_reschedule(work, K_USEC(timeout));
515 }
516 }
517
518 #endif
519 #if CONFIG_UART_ASYNC_API || CONFIG_UART_INTERRUPT_DRIVEN
520
uart_esp32_irq_rx_enable(const struct device * dev)521 static void uart_esp32_irq_rx_enable(const struct device *dev)
522 {
523 struct uart_esp32_data *data = dev->data;
524
525 uart_hal_clr_intsts_mask(&data->hal, UART_INTR_RXFIFO_FULL);
526 uart_hal_clr_intsts_mask(&data->hal, UART_INTR_RXFIFO_TOUT);
527 uart_hal_ena_intr_mask(&data->hal, UART_INTR_RXFIFO_FULL);
528 uart_hal_ena_intr_mask(&data->hal, UART_INTR_RXFIFO_TOUT);
529 }
530
uart_esp32_isr(void * arg)531 static void uart_esp32_isr(void *arg)
532 {
533 const struct device *dev = (const struct device *)arg;
534 struct uart_esp32_data *data = dev->data;
535 uint32_t uart_intr_status = uart_hal_get_intsts_mask(&data->hal);
536
537 if (uart_intr_status == 0) {
538 return;
539 }
540 uart_hal_clr_intsts_mask(&data->hal, uart_intr_status);
541
542 #if CONFIG_UART_INTERRUPT_DRIVEN
543 /* Verify if the callback has been registered */
544 if (data->irq_cb) {
545 data->irq_cb(dev, data->irq_cb_data);
546 }
547 #endif
548
549 #if CONFIG_UART_ASYNC_API
550 if (uart_intr_status & UART_INTR_RXFIFO_FULL) {
551 data->async.rx_counter++;
552 uart_esp32_async_timer_start(&data->async.rx_timeout_work, data->async.rx_timeout);
553 }
554 #endif
555 }
556
557 #endif
558
559 #if CONFIG_UART_ASYNC_API
uart_esp32_dma_rx_done(const struct device * dma_dev,void * user_data,uint32_t channel,int status)560 static void IRAM_ATTR uart_esp32_dma_rx_done(const struct device *dma_dev, void *user_data,
561 uint32_t channel, int status)
562 {
563 const struct device *uart_dev = user_data;
564 const struct uart_esp32_config *config = uart_dev->config;
565 struct uart_esp32_data *data = uart_dev->data;
566 struct uart_event evt = {0};
567 unsigned int key = irq_lock();
568
569 /* If the receive buffer is not complete we reload the DMA at current buffer position and
570 * let the timeout callback handle the notifications
571 */
572 if (data->async.rx_counter != data->async.rx_len) {
573 dma_reload(config->dma_dev, config->rx_dma_channel, 0,
574 (uint32_t)data->async.rx_buf + data->async.rx_counter,
575 data->async.rx_len - data->async.rx_counter);
576 dma_start(config->dma_dev, config->rx_dma_channel);
577 data->uhci_dev->pkt_thres.thrs = data->async.rx_len - data->async.rx_counter;
578 irq_unlock(key);
579 return;
580 }
581
582 /*Notify RX_RDY*/
583 evt.type = UART_RX_RDY;
584 evt.data.rx.buf = data->async.rx_buf;
585 evt.data.rx.len = data->async.rx_counter - data->async.rx_offset;
586 evt.data.rx.offset = data->async.rx_offset;
587
588 if (data->async.cb && evt.data.rx.len) {
589 data->async.cb(data->uart_dev, &evt, data->async.user_data);
590 }
591
592 data->async.rx_offset = 0;
593 data->async.rx_counter = 0;
594
595 /*Release current buffer*/
596 evt.type = UART_RX_BUF_RELEASED;
597 evt.data.rx_buf.buf = data->async.rx_buf;
598 if (data->async.cb) {
599 data->async.cb(uart_dev, &evt, data->async.user_data);
600 }
601
602 /*Load next buffer and request another*/
603 data->async.rx_buf = data->async.rx_next_buf;
604 data->async.rx_len = data->async.rx_next_len;
605 data->async.rx_next_buf = NULL;
606 data->async.rx_next_len = 0U;
607 evt.type = UART_RX_BUF_REQUEST;
608 if (data->async.cb) {
609 data->async.cb(uart_dev, &evt, data->async.user_data);
610 }
611
612 /*Notify RX_DISABLED when there is no buffer*/
613 if (!data->async.rx_buf) {
614 evt.type = UART_RX_DISABLED;
615 if (data->async.cb) {
616 data->async.cb(uart_dev, &evt, data->async.user_data);
617 }
618 } else {
619 /*Reload DMA with new buffer*/
620 dma_reload(config->dma_dev, config->rx_dma_channel, 0, (uint32_t)data->async.rx_buf,
621 data->async.rx_len);
622 dma_start(config->dma_dev, config->rx_dma_channel);
623 data->uhci_dev->pkt_thres.thrs = data->async.rx_len;
624 }
625
626 irq_unlock(key);
627 }
628
uart_esp32_dma_tx_done(const struct device * dma_dev,void * user_data,uint32_t channel,int status)629 static void IRAM_ATTR uart_esp32_dma_tx_done(const struct device *dma_dev, void *user_data,
630 uint32_t channel, int status)
631 {
632 const struct device *uart_dev = user_data;
633 struct uart_esp32_data *data = uart_dev->data;
634 struct uart_event evt = {0};
635 unsigned int key = irq_lock();
636
637 k_work_cancel_delayable(&data->async.tx_timeout_work);
638
639 evt.type = UART_TX_DONE;
640 evt.data.tx.buf = data->async.tx_buf;
641 evt.data.tx.len = data->async.tx_len;
642 if (data->async.cb) {
643 data->async.cb(uart_dev, &evt, data->async.user_data);
644 }
645
646 /* Reset TX Buffer */
647 data->async.tx_buf = NULL;
648 data->async.tx_len = 0U;
649 irq_unlock(key);
650 }
651
uart_esp32_async_tx_abort(const struct device * dev)652 static int uart_esp32_async_tx_abort(const struct device *dev)
653 {
654 const struct uart_esp32_config *config = dev->config;
655 struct uart_esp32_data *data = dev->data;
656 struct uart_event evt = {0};
657 int err = 0;
658 unsigned int key = irq_lock();
659
660 k_work_cancel_delayable(&data->async.tx_timeout_work);
661
662 err = dma_stop(config->dma_dev, config->tx_dma_channel);
663 if (err) {
664 LOG_ERR("Error stopping Tx DMA (%d)", err);
665 goto unlock;
666 }
667
668 evt.type = UART_TX_ABORTED;
669 evt.data.tx.buf = data->async.tx_buf;
670 evt.data.tx.len = data->async.tx_len;
671
672 if (data->async.cb) {
673 data->async.cb(dev, &evt, data->async.user_data);
674 }
675
676 unlock:
677 irq_unlock(key);
678 return err;
679 }
680
uart_esp32_async_tx_timeout(struct k_work * work)681 static void uart_esp32_async_tx_timeout(struct k_work *work)
682 {
683 struct k_work_delayable *dwork = k_work_delayable_from_work(work);
684 struct uart_esp32_async_data *async =
685 CONTAINER_OF(dwork, struct uart_esp32_async_data, tx_timeout_work);
686 struct uart_esp32_data *data = CONTAINER_OF(async, struct uart_esp32_data, async);
687
688 uart_esp32_async_tx_abort(data->uart_dev);
689 }
690
uart_esp32_async_rx_timeout(struct k_work * work)691 static void uart_esp32_async_rx_timeout(struct k_work *work)
692 {
693 struct k_work_delayable *dwork = k_work_delayable_from_work(work);
694 struct uart_esp32_async_data *async =
695 CONTAINER_OF(dwork, struct uart_esp32_async_data, rx_timeout_work);
696 struct uart_esp32_data *data = CONTAINER_OF(async, struct uart_esp32_data, async);
697 struct uart_event evt = {0};
698 unsigned int key = irq_lock();
699
700 evt.type = UART_RX_RDY;
701 evt.data.rx.buf = data->async.rx_buf;
702 evt.data.rx.len = data->async.rx_counter - data->async.rx_offset;
703 evt.data.rx.offset = data->async.rx_offset;
704
705 if (data->async.cb && evt.data.rx.len) {
706 data->async.cb(data->uart_dev, &evt, data->async.user_data);
707 }
708
709 data->async.rx_offset = data->async.rx_counter;
710 k_work_cancel_delayable(&data->async.rx_timeout_work);
711 irq_unlock(key);
712 }
713
uart_esp32_async_callback_set(const struct device * dev,uart_callback_t callback,void * user_data)714 static int uart_esp32_async_callback_set(const struct device *dev, uart_callback_t callback,
715 void *user_data)
716 {
717 struct uart_esp32_data *data = dev->data;
718
719 if (!callback) {
720 return -EINVAL;
721 }
722
723 data->async.cb = callback;
724 data->async.user_data = user_data;
725
726 #if defined(CONFIG_UART_EXCLUSIVE_API_CALLBACKS)
727 data->irq_cb = NULL;
728 data->irq_cb_data = NULL;
729 #endif
730
731 return 0;
732 }
733
uart_esp32_async_tx(const struct device * dev,const uint8_t * buf,size_t len,int32_t timeout)734 static int uart_esp32_async_tx(const struct device *dev, const uint8_t *buf, size_t len,
735 int32_t timeout)
736 {
737 const struct uart_esp32_config *config = dev->config;
738 struct uart_esp32_data *data = dev->data;
739 struct dma_config dma_cfg = {0};
740 struct dma_block_config dma_blk = {0};
741 struct dma_status dma_status = {0};
742 int err = 0;
743 unsigned int key = irq_lock();
744
745 if (config->tx_dma_channel == 0xFF) {
746 LOG_ERR("Tx DMA channel is not configured");
747 err = -ENOTSUP;
748 goto unlock;
749 }
750
751 err = dma_get_status(config->dma_dev, config->tx_dma_channel, &dma_status);
752 if (err) {
753 LOG_ERR("Unable to get Tx status (%d)", err);
754 goto unlock;
755 }
756
757 if (dma_status.busy) {
758 LOG_ERR("Tx DMA Channel is busy");
759 err = -EBUSY;
760 goto unlock;
761 }
762
763 data->async.tx_buf = buf;
764 data->async.tx_len = len;
765
766 dma_cfg.channel_direction = MEMORY_TO_PERIPHERAL;
767 dma_cfg.dma_callback = uart_esp32_dma_tx_done;
768 dma_cfg.user_data = (void *)dev;
769 dma_cfg.dma_slot = ESP_GDMA_TRIG_PERIPH_UHCI0;
770 dma_cfg.block_count = 1;
771 dma_cfg.head_block = &dma_blk;
772 dma_blk.block_size = len;
773 dma_blk.source_address = (uint32_t)buf;
774
775 err = dma_config(config->dma_dev, config->tx_dma_channel, &dma_cfg);
776 if (err) {
777 LOG_ERR("Error configuring Tx DMA (%d)", err);
778 goto unlock;
779 }
780
781 uart_esp32_async_timer_start(&data->async.tx_timeout_work, timeout);
782
783 err = dma_start(config->dma_dev, config->tx_dma_channel);
784 if (err) {
785 LOG_ERR("Error starting Tx DMA (%d)", err);
786 goto unlock;
787 }
788
789 unlock:
790 irq_unlock(key);
791 return err;
792 }
793
uart_esp32_async_rx_enable(const struct device * dev,uint8_t * buf,size_t len,int32_t timeout)794 static int uart_esp32_async_rx_enable(const struct device *dev, uint8_t *buf, size_t len,
795 int32_t timeout)
796 {
797 const struct uart_esp32_config *config = dev->config;
798 struct uart_esp32_data *data = dev->data;
799 struct dma_config dma_cfg = {0};
800 struct dma_block_config dma_blk = {0};
801 struct dma_status dma_status = {0};
802 int err = 0;
803 struct uart_event evt = {0};
804
805 if (config->rx_dma_channel == 0xFF) {
806 LOG_ERR("Rx DMA channel is not configured");
807 return -ENOTSUP;
808 }
809
810 err = dma_get_status(config->dma_dev, config->rx_dma_channel, &dma_status);
811 if (err) {
812 LOG_ERR("Unable to get Rx status (%d)", err);
813 return err;
814 }
815
816 if (dma_status.busy) {
817 LOG_ERR("Rx DMA Channel is busy");
818 return -EBUSY;
819 }
820
821 unsigned int key = irq_lock();
822
823 data->async.rx_buf = buf;
824 data->async.rx_len = len;
825 data->async.rx_timeout = timeout;
826
827 dma_cfg.channel_direction = PERIPHERAL_TO_MEMORY;
828 dma_cfg.dma_callback = uart_esp32_dma_rx_done;
829 dma_cfg.user_data = (void *)dev;
830 dma_cfg.dma_slot = ESP_GDMA_TRIG_PERIPH_UHCI0;
831 dma_cfg.block_count = 1;
832 dma_cfg.head_block = &dma_blk;
833 dma_blk.block_size = len;
834 dma_blk.dest_address = (uint32_t)data->async.rx_buf;
835
836 err = dma_config(config->dma_dev, config->rx_dma_channel, &dma_cfg);
837 if (err) {
838 LOG_ERR("Error configuring Rx DMA (%d)", err);
839 goto unlock;
840 }
841
842 /*
843 * Enable interrupt on first receive byte so we can start async timer
844 */
845 uart_hal_set_rxfifo_full_thr(&data->hal, 1);
846 uart_esp32_irq_rx_enable(dev);
847
848 err = dma_start(config->dma_dev, config->rx_dma_channel);
849 if (err) {
850 LOG_ERR("Error starting Rx DMA (%d)", err);
851 goto unlock;
852 }
853
854 data->uhci_dev->pkt_thres.thrs = len;
855
856 /**
857 * Request next buffer
858 */
859 evt.type = UART_RX_BUF_REQUEST;
860 if (data->async.cb) {
861 data->async.cb(dev, &evt, data->async.user_data);
862 }
863
864 unlock:
865 irq_unlock(key);
866 return err;
867 }
868
uart_esp32_async_rx_buf_rsp(const struct device * dev,uint8_t * buf,size_t len)869 static int uart_esp32_async_rx_buf_rsp(const struct device *dev, uint8_t *buf, size_t len)
870 {
871 struct uart_esp32_data *data = dev->data;
872
873 data->async.rx_next_buf = buf;
874 data->async.rx_next_len = len;
875
876 return 0;
877 }
878
uart_esp32_async_rx_disable(const struct device * dev)879 static int uart_esp32_async_rx_disable(const struct device *dev)
880 {
881 const struct uart_esp32_config *config = dev->config;
882 struct uart_esp32_data *data = dev->data;
883 unsigned int key = irq_lock();
884 int err = 0;
885 struct uart_event evt = {0};
886
887 k_work_cancel_delayable(&data->async.rx_timeout_work);
888
889 if (!data->async.rx_len) {
890 err = -EINVAL;
891 goto unlock;
892 }
893
894 err = dma_stop(config->dma_dev, config->rx_dma_channel);
895 if (err) {
896 LOG_ERR("Error stopping Rx DMA (%d)", err);
897 goto unlock;
898 }
899
900 /*If any bytes have been received notify RX_RDY*/
901 evt.type = UART_RX_RDY;
902 evt.data.rx.buf = data->async.rx_buf;
903 evt.data.rx.len = data->async.rx_counter - data->async.rx_offset;
904 evt.data.rx.offset = data->async.rx_offset;
905
906 if (data->async.cb && evt.data.rx.len) {
907 data->async.cb(data->uart_dev, &evt, data->async.user_data);
908 }
909
910 data->async.rx_offset = 0;
911 data->async.rx_counter = 0;
912
913 /* Release current buffer*/
914 evt.type = UART_RX_BUF_RELEASED;
915 evt.data.rx_buf.buf = data->async.rx_buf;
916
917 if (data->async.cb) {
918 data->async.cb(dev, &evt, data->async.user_data);
919 }
920
921 data->async.rx_len = 0;
922 data->async.rx_buf = NULL;
923
924 /*Release next buffer*/
925 if (data->async.rx_next_len) {
926 evt.type = UART_RX_BUF_RELEASED;
927 evt.data.rx_buf.buf = data->async.rx_next_buf;
928 if (data->async.cb) {
929 data->async.cb(dev, &evt, data->async.user_data);
930 }
931
932 data->async.rx_next_len = 0;
933 data->async.rx_next_buf = NULL;
934 }
935
936 /*Notify UART_RX_DISABLED*/
937 evt.type = UART_RX_DISABLED;
938 if (data->async.cb) {
939 data->async.cb(dev, &evt, data->async.user_data);
940 }
941
942 unlock:
943 irq_unlock(key);
944 return err;
945 }
946
947 #endif /* CONFIG_UART_ASYNC_API */
948
uart_esp32_init(const struct device * dev)949 static int uart_esp32_init(const struct device *dev)
950 {
951 struct uart_esp32_data *data = dev->data;
952 int ret = uart_esp32_configure(dev, &data->uart_config);
953
954 if (ret < 0) {
955 LOG_ERR("Error configuring UART (%d)", ret);
956 return ret;
957 }
958
959 #if CONFIG_UART_INTERRUPT_DRIVEN || CONFIG_UART_ASYNC_API
960 const struct uart_esp32_config *config = dev->config;
961
962 ret = esp_intr_alloc(config->irq_source,
963 ESP_PRIO_TO_FLAGS(config->irq_priority) |
964 ESP_INT_FLAGS_CHECK(config->irq_flags),
965 (ISR_HANDLER)uart_esp32_isr,
966 (void *)dev,
967 NULL);
968 if (ret < 0) {
969 LOG_ERR("Error allocating UART interrupt (%d)", ret);
970 return ret;
971 }
972 #endif
973 #if CONFIG_UART_ASYNC_API
974 if (config->dma_dev) {
975 if (!device_is_ready(config->dma_dev)) {
976 LOG_ERR("DMA device is not ready");
977 return -ENODEV;
978 }
979
980 clock_control_on(config->clock_dev, (clock_control_subsys_t)ESP32_UHCI0_MODULE);
981 uhci_ll_init(data->uhci_dev);
982 uhci_ll_set_eof_mode(data->uhci_dev, UHCI_RX_IDLE_EOF | UHCI_RX_LEN_EOF);
983 uhci_ll_attach_uart_port(data->uhci_dev, uart_hal_get_port_num(&data->hal));
984 data->uart_dev = dev;
985
986 k_work_init_delayable(&data->async.tx_timeout_work, uart_esp32_async_tx_timeout);
987 k_work_init_delayable(&data->async.rx_timeout_work, uart_esp32_async_rx_timeout);
988 }
989 #endif
990 return 0;
991 }
992
993 static DEVICE_API(uart, uart_esp32_api) = {
994 .poll_in = uart_esp32_poll_in,
995 .poll_out = uart_esp32_poll_out,
996 .err_check = uart_esp32_err_check,
997 #ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
998 .configure = uart_esp32_configure,
999 .config_get = uart_esp32_config_get,
1000 #endif
1001 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
1002 .fifo_fill = uart_esp32_fifo_fill,
1003 .fifo_read = uart_esp32_fifo_read,
1004 .irq_tx_enable = uart_esp32_irq_tx_enable,
1005 .irq_tx_disable = uart_esp32_irq_tx_disable,
1006 .irq_tx_ready = uart_esp32_irq_tx_ready,
1007 .irq_rx_enable = uart_esp32_irq_rx_enable,
1008 .irq_rx_disable = uart_esp32_irq_rx_disable,
1009 .irq_tx_complete = uart_esp32_irq_tx_complete,
1010 .irq_rx_ready = uart_esp32_irq_rx_ready,
1011 .irq_err_enable = uart_esp32_irq_err_enable,
1012 .irq_err_disable = uart_esp32_irq_err_disable,
1013 .irq_is_pending = uart_esp32_irq_is_pending,
1014 .irq_update = uart_esp32_irq_update,
1015 .irq_callback_set = uart_esp32_irq_callback_set,
1016 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
1017 #if CONFIG_UART_ASYNC_API
1018 .callback_set = uart_esp32_async_callback_set,
1019 .tx = uart_esp32_async_tx,
1020 .tx_abort = uart_esp32_async_tx_abort,
1021 .rx_enable = uart_esp32_async_rx_enable,
1022 .rx_buf_rsp = uart_esp32_async_rx_buf_rsp,
1023 .rx_disable = uart_esp32_async_rx_disable,
1024 #endif /*CONFIG_UART_ASYNC_API*/
1025 };
1026
1027 #if CONFIG_UART_ASYNC_API
1028 #define ESP_UART_DMA_INIT(n) \
1029 .dma_dev = ESP32_DT_INST_DMA_CTLR(n, tx), \
1030 .tx_dma_channel = ESP32_DT_INST_DMA_CELL(n, tx, channel), \
1031 .rx_dma_channel = ESP32_DT_INST_DMA_CELL(n, rx, channel)
1032
1033 #define ESP_UART_UHCI_INIT(n) \
1034 .uhci_dev = COND_CODE_1(DT_INST_NODE_HAS_PROP(n, dmas), (&UHCI0), (NULL))
1035
1036 #else
1037 #define ESP_UART_DMA_INIT(n)
1038 #define ESP_UART_UHCI_INIT(n)
1039 #endif
1040
1041 #define ESP32_UART_INIT(idx) \
1042 \
1043 PINCTRL_DT_INST_DEFINE(idx); \
1044 \
1045 static const DRAM_ATTR struct uart_esp32_config uart_esp32_cfg_port_##idx = { \
1046 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(idx)), \
1047 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx), \
1048 .clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(idx, offset), \
1049 .irq_source = DT_INST_IRQ_BY_IDX(idx, 0, irq), \
1050 .irq_priority = DT_INST_IRQ_BY_IDX(idx, 0, priority), \
1051 .irq_flags = DT_INST_IRQ_BY_IDX(idx, 0, flags), \
1052 .tx_invert = DT_INST_PROP_OR(idx, tx_invert, false), \
1053 .rx_invert = DT_INST_PROP_OR(idx, rx_invert, false), \
1054 ESP_UART_DMA_INIT(idx)}; \
1055 \
1056 static struct uart_esp32_data uart_esp32_data_##idx = { \
1057 .uart_config = {.baudrate = DT_INST_PROP(idx, current_speed), \
1058 .parity = DT_INST_ENUM_IDX_OR(idx, parity, UART_CFG_PARITY_NONE), \
1059 .stop_bits = DT_INST_ENUM_IDX_OR(idx, stop_bits, \
1060 UART_CFG_STOP_BITS_1), \
1061 .data_bits = DT_INST_ENUM_IDX_OR(idx, data_bits, \
1062 UART_CFG_DATA_BITS_8), \
1063 .flow_ctrl = MAX(COND_CODE_1(DT_INST_PROP(idx, hw_rs485_hd_mode), \
1064 (UART_CFG_FLOW_CTRL_RS485), \
1065 (UART_CFG_FLOW_CTRL_NONE)), \
1066 COND_CODE_1(DT_INST_PROP(idx, hw_flow_control), \
1067 (UART_CFG_FLOW_CTRL_RTS_CTS), \
1068 (UART_CFG_FLOW_CTRL_NONE)))}, \
1069 .hal = \
1070 { \
1071 .dev = (uart_dev_t *)DT_INST_REG_ADDR(idx), \
1072 }, \
1073 ESP_UART_UHCI_INIT(idx)}; \
1074 \
1075 DEVICE_DT_INST_DEFINE(idx, uart_esp32_init, NULL, &uart_esp32_data_##idx, \
1076 &uart_esp32_cfg_port_##idx, PRE_KERNEL_1, \
1077 CONFIG_SERIAL_INIT_PRIORITY, &uart_esp32_api);
1078
1079 DT_INST_FOREACH_STATUS_OKAY(ESP32_UART_INIT);
1080
