1 2 /***************************************************************************//** 3 * \file tviibe_remaps.h 4 * 5 * \brief 6 * Remaps IP defines for Traveo II B-E device compatibility with CAT1A IP headers. 7 * 8 * NOTE: This file should only be included for TVIIBE device builds, and is not 9 * designed to be used with PSoC6 or other platforms. 10 ******************************************************************************** 11 * \copyright 12 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 13 * an affiliate of Cypress Semiconductor Corporation. 14 * 15 * SPDX-License-Identifier: Apache-2.0 16 * 17 * Licensed under the Apache License, Version 2.0 (the "License"); 18 * you may not use this file except in compliance with the License. 19 * You may obtain a copy of the License at 20 * 21 * http://www.apache.org/licenses/LICENSE-2.0 22 * 23 * Unless required by applicable law or agreed to in writing, software 24 * distributed under the License is distributed on an "AS IS" BASIS, 25 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 26 * See the License for the specific language governing permissions and 27 * limitations under the License. 28 *******************************************************************************/ 29 30 #ifndef _TVIIBE_REMAPS_H_ 31 #define _TVIIBE_REMAPS_H_ 32 33 /* The first section of remaps for TVIIBE512K, TVIIBE1M, and TVIIBE2M devices (SRSSv2) */ 34 #if defined(CY_DEVICE_SERIES_CYT2B6) || defined(CY_DEVICE_SERIES_CYT2B7) || defined(CY_DEVICE_SERIES_CYT2B9) 35 36 /******************************************************************************* 37 * SRSS 38 *******************************************************************************/ 39 /* SRSSv2 remaps for what is generated in a TVII generated header file */ 40 #define SRSS_PWR_HIBERNATE_MASK_HIBPIN_Pos SRSS_V2_PWR_HIBERNATE_MASK_HIBPIN_Pos 41 #define SRSS_PWR_HIBERNATE_MASK_HIBPIN_Msk SRSS_V2_PWR_HIBERNATE_MASK_HIBPIN_Msk 42 #define SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Pos SRSS_V2_PWR_HIBERNATE_POLARITY_HIBPIN_Pos 43 #define SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Msk SRSS_V2_PWR_HIBERNATE_POLARITY_HIBPIN_Msk 44 #define SRSS_PWR_HIBERNATE_MASK_HIBALARM_Msk SRSS_V2_PWR_HIBERNATE_MASK_HIBALARM_Msk 45 #define SRSS_PWR_HIBERNATE_MASK_HIBALARM_Pos SRSS_V2_PWR_HIBERNATE_MASK_HIBALARM_Pos 46 #define SRSS_PWR_HIBERNATE_MASK_HIBWDT_Msk SRSS_V2_PWR_HIBERNATE_MASK_HIBWDT_Msk 47 #define SRSS_PWR_LVD_CTL_HVLVD1_EN_HT_Msk SRSS_V2_PWR_LVD_CTL_HVLVD1_EN_HT_Msk 48 #define SRSS_PWR_LVD_CTL_HVLVD1_EN_HT_Pos SRSS_V2_PWR_LVD_CTL_HVLVD1_EN_HT_Pos 49 #define SRSS_PWR_LVD_CTL_HVLVD1_EN_HT_Msk SRSS_V2_PWR_LVD_CTL_HVLVD1_EN_HT_Msk 50 #define SRSS_PWR_LVD_CTL_HVLVD1_EN_HT_Pos SRSS_V2_PWR_LVD_CTL_HVLVD1_EN_HT_Pos 51 #define SRSS_PWR_LVD_CTL2_HVLVD2_EN_HT_Msk SRSS_V2_PWR_LVD_CTL2_HVLVD2_EN_HT_Msk 52 #define SRSS_PWR_LVD_CTL2_HVLVD2_EN_HT_Pos SRSS_V2_PWR_LVD_CTL2_HVLVD2_EN_HT_Pos 53 #define SRSS_PWR_LVD_CTL_HVLVD1_TRIPSEL_HT_Msk SRSS_V2_PWR_LVD_CTL_HVLVD1_TRIPSEL_HT_Msk 54 #define SRSS_PWR_LVD_CTL_HVLVD1_TRIPSEL_HT_Pos SRSS_V2_PWR_LVD_CTL_HVLVD1_TRIPSEL_HT_Pos 55 #define SRSS_PWR_LVD_CTL2_HVLVD2_TRIPSEL_HT_Msk SRSS_V2_PWR_LVD_CTL2_HVLVD2_TRIPSEL_HT_Msk 56 #define SRSS_PWR_LVD_CTL2_HVLVD2_TRIPSEL_HT_Pos SRSS_V2_PWR_LVD_CTL2_HVLVD2_TRIPSEL_HT_Pos 57 #define SRSS_PWR_LVD_STATUS_HVLVD1_OUT_Msk SRSS_V2_PWR_LVD_STATUS_HVLVD1_OUT_Msk 58 #define SRSS_PWR_LVD_STATUS_HVLVD1_OUT_Pos SRSS_V2_PWR_LVD_STATUS_HVLVD1_OUT_Pos 59 #define SRSS_PWR_LVD_STATUS2_HVLVD2_OUT_Msk SRSS_V2_PWR_LVD_STATUS2_HVLVD2_OUT_Msk 60 #define SRSS_PWR_LVD_STATUS2_HVLVD2_OUT_Pos SRSS_V2_PWR_LVD_STATUS2_HVLVD2_OUT_Pos 61 #define SRSS_SRSS_INTR_HVLVD1_Msk SRSS_V2_SRSS_INTR_HVLVD1_Msk 62 #define SRSS_SRSS_INTR_HVLVD1_Pos SRSS_V2_SRSS_INTR_HVLVD1_Pos 63 #define SRSS_SRSS_INTR_HVLVD2_Msk SRSS_V2_SRSS_INTR_HVLVD2_Msk 64 #define SRSS_SRSS_INTR_HVLVD2_Pos SRSS_V2_SRSS_INTR_HVLVD2_Pos 65 #define SRSS_SRSS_INTR_SET_HVLVD1_Msk SRSS_V2_SRSS_INTR_SET_HVLVD1_Msk 66 #define SRSS_SRSS_INTR_SET_HVLVD1_Pos SRSS_V2_SRSS_INTR_SET_HVLVD1_Pos 67 #define SRSS_SRSS_INTR_SET_HVLVD2_Msk SRSS_V2_SRSS_INTR_SET_HVLVD2_Msk 68 #define SRSS_SRSS_INTR_SET_HVLVD2_Pos SRSS_V2_SRSS_INTR_SET_HVLVD2_Pos 69 #define SRSS_SRSS_INTR_MASK_HVLVD1_Msk SRSS_V2_SRSS_INTR_MASK_HVLVD1_Msk 70 #define SRSS_SRSS_INTR_MASK_HVLVD1_Pos SRSS_V2_SRSS_INTR_MASK_HVLVD1_Pos 71 #define SRSS_SRSS_INTR_MASK_HVLVD2_Msk SRSS_V2_SRSS_INTR_MASK_HVLVD2_Msk 72 #define SRSS_SRSS_INTR_MASK_HVLVD2_Pos SRSS_V2_SRSS_INTR_MASK_HVLVD2_Pos 73 #define SRSS_PWR_LVD_CTL_HVLVD1_EDGE_SEL_Msk SRSS_V2_PWR_LVD_CTL_HVLVD1_EDGE_SEL_Msk 74 #define SRSS_PWR_LVD_CTL_HVLVD1_EDGE_SEL_Pos SRSS_V2_PWR_LVD_CTL_HVLVD1_EDGE_SEL_Pos 75 #define SRSS_PWR_LVD_CTL_HVLVD2_EDGE_SEL_Msk SRSS_V2_PWR_LVD_CTL_HVLVD2_EDGE_SEL_Msk 76 #define SRSS_PWR_LVD_CTL_HVLVD2_EDGE_SEL_Pos SRSS_V2_PWR_LVD_CTL_HVLVD2_EDGE_SEL_Pos 77 #define SRSS_PWR_LVD_CTL2_HVLVD2_EDGE_SEL_Msk SRSS_V2_PWR_LVD_CTL2_HVLVD2_EDGE_SEL_Msk 78 #define SRSS_PWR_LVD_CTL2_HVLVD2_EDGE_SEL_Pos SRSS_V2_PWR_LVD_CTL2_HVLVD2_EDGE_SEL_Pos 79 #define SRSS_PWR_LVD_CTL2_HVLVD2_ACTION_Msk SRSS_V2_PWR_LVD_CTL2_HVLVD2_ACTION_Msk 80 #define SRSS_PWR_LVD_CTL2_HVLVD2_ACTION_Pos SRSS_V2_PWR_LVD_CTL2_HVLVD2_ACTION_Pos 81 #define SRSS_PWR_LVD_CTL_HVLVD1_ACTION_Msk SRSS_V2_PWR_LVD_CTL_HVLVD1_ACTION_Msk 82 #define SRSS_PWR_LVD_CTL_HVLVD1_ACTION_Pos SRSS_V2_PWR_LVD_CTL_HVLVD1_ACTION_Pos 83 #define SRSS_PWR_LVD_CTL_HVLVD1_DPSLP_EN_HT_Msk SRSS_V2_PWR_LVD_CTL_HVLVD1_DPSLP_EN_HT_Msk 84 #define SRSS_PWR_LVD_CTL_HVLVD1_DPSLP_EN_HT_Pos SRSS_V2_PWR_LVD_CTL_HVLVD1_DPSLP_EN_HT_Pos 85 #define SRSS_PWR_LVD_CTL2_HVLVD2_DPSLP_EN_HT_Msk SRSS_V2_PWR_LVD_CTL2_HVLVD2_DPSLP_EN_HT_Msk 86 #define SRSS_PWR_LVD_CTL2_HVLVD2_DPSLP_EN_HT_Pos SRSS_V2_PWR_LVD_CTL2_HVLVD2_DPSLP_EN_HT_Pos 87 #define SRSS_CLK_SELECT_PUMP_SEL_Msk SRSS_V2_CLK_SELECT_PUMP_SEL_Msk 88 #define SRSS_CLK_SELECT_PUMP_SEL_Pos SRSS_V2_CLK_SELECT_PUMP_SEL_Pos 89 #define SRSS_CLK_SELECT_PUMP_DIV_Msk SRSS_V2_CLK_SELECT_PUMP_DIV_Msk 90 #define SRSS_CLK_SELECT_PUMP_DIV_Pos SRSS_V2_CLK_SELECT_PUMP_DIV_Pos 91 #define SRSS_RES_CAUSE2_RESET_CSV_HF_Msk SRSS_V2_RES_CAUSE2_RESET_CSV_HF_Msk 92 #define SRSS_RES_CAUSE2_RESET_CSV_HF_Pos SRSS_V2_RES_CAUSE2_RESET_CSV_HF_Pos 93 #define SRSS_CLK_SELECT_PUMP_ENABLE_Msk SRSS_V2_CLK_SELECT_PUMP_ENABLE_Msk 94 #define SRSS_CLK_SELECT_PUMP_ENABLE_Pos SRSS_V2_CLK_SELECT_PUMP_ENABLE_Pos 95 #define SRSS_PWR_CTL2_BGREF_LPMODE_Msk SRSS_V2_PWR_CTL2_BGREF_LPMODE_Msk 96 #define SRSS_PWR_CTL2_BGREF_LPMODE_Pos SRSS_V2_PWR_CTL2_BGREF_LPMODE_Pos 97 #define SRSS_RES_CAUSE2_RESET_CSV_HF_Pos SRSS_V2_RES_CAUSE2_RESET_CSV_HF_Pos 98 #define SRSS_RES_CAUSE2_RESET_CSV_HF_Msk SRSS_V2_RES_CAUSE2_RESET_CSV_HF_Msk 99 #define SRSS_PWR_HIBERNATE_TOKEN_Msk SRSS_V2_PWR_HIBERNATE_TOKEN_Msk 100 #define SRSS_PWR_HIBERNATE_TOKEN_Pos SRSS_V2_PWR_HIBERNATE_TOKEN_Pos 101 #define SRSS_PWR_HIBERNATE_UNLOCK_Pos SRSS_V2_PWR_HIBERNATE_UNLOCK_Pos 102 #define SRSS_PWR_HIBERNATE_UNLOCK_Msk SRSS_V2_PWR_HIBERNATE_UNLOCK_Msk 103 #define SRSS_PWR_HIBERNATE_FREEZE_Msk SRSS_V2_PWR_HIBERNATE_FREEZE_Msk 104 #define SRSS_PWR_HIBERNATE_FREEZE_Pos SRSS_V2_PWR_HIBERNATE_FREEZE_Pos 105 #define SRSS_PWR_HIBERNATE_HIBERNATE_Msk SRSS_V2_PWR_HIBERNATE_HIBERNATE_Msk 106 #define SRSS_PWR_HIBERNATE_HIBERNATE_Pos SRSS_V2_PWR_HIBERNATE_HIBERNATE_Pos 107 #define SRSS_CLK_SELECT_LFCLK_SEL_Msk SRSS_V2_CLK_SELECT_LFCLK_SEL_Msk 108 #define SRSS_CLK_SELECT_LFCLK_SEL_Pos SRSS_V2_CLK_SELECT_LFCLK_SEL_Pos 109 #define SRSS_RES_CAUSE2_RESET_CSV_REF_Msk SRSS_V2_RES_CAUSE2_RESET_CSV_REF_Msk 110 #define SRSS_RES_CAUSE2_RESET_CSV_REF_Pos SRSS_V2_RES_CAUSE2_RESET_CSV_REF_Pos 111 #define SRSS_CLK_ROOT_SELECT_ENABLE_Msk SRSS_V2_CLK_ROOT_SELECT_ENABLE_Msk 112 #define SRSS_CLK_ROOT_SELECT_ENABLE_Pos SRSS_V2_CLK_ROOT_SELECT_ENABLE_Pos 113 #define SRSS_CLK_ROOT_SELECT_ROOT_MUX_Msk SRSS_V2_CLK_ROOT_SELECT_ROOT_MUX_Msk 114 #define SRSS_CLK_ROOT_SELECT_ROOT_MUX_Pos SRSS_V2_CLK_ROOT_SELECT_ROOT_MUX_Pos 115 #define SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk SRSS_V2_CLK_ROOT_SELECT_ROOT_DIV_Msk 116 #define SRSS_CLK_ROOT_SELECT_ROOT_DIV_Pos SRSS_V2_CLK_ROOT_SELECT_ROOT_DIV_Pos 117 #define SRSS_PWR_CTL2_LINREG_DIS_Msk SRSS_V2_PWR_CTL2_LINREG_DIS_Msk 118 #define SRSS_PWR_CTL2_LINREG_DIS_Pos SRSS_V2_PWR_CTL2_LINREG_DIS_Pos 119 #define SRSS_PWR_CTL2_DPSLP_REG_DIS_Msk SRSS_V2_PWR_CTL2_DPSLP_REG_DIS_Msk 120 #define SRSS_PWR_CTL2_DPSLP_REG_DIS_Pos SRSS_V2_PWR_CTL2_DPSLP_REG_DIS_Pos 121 #define SRSS_CLK_ILO0_CONFIG_ENABLE_Msk SRSS_V2_CLK_ILO0_CONFIG_ENABLE_Msk 122 #define SRSS_CLK_ILO0_CONFIG_ENABLE_Pos SRSS_V2_CLK_ILO0_CONFIG_ENABLE_Pos 123 #define SRSS_CLK_ILO0_CONFIG_ILO0_BACKUP_Msk SRSS_V2_CLK_ILO0_CONFIG_ILO0_BACKUP_Msk 124 #define SRSS_CLK_ILO0_CONFIG_ILO0_BACKUP_Pos SRSS_V2_CLK_ILO0_CONFIG_ILO0_BACKUP_Pos 125 #define SRSS_CLK_ILO1_CONFIG_ENABLE_Msk SRSS_V2_CLK_ILO1_CONFIG_ENABLE_Msk 126 #define SRSS_CLK_ILO1_CONFIG_ENABLE_Pos SRSS_V2_CLK_ILO1_CONFIG_ENABLE_Pos 127 #define SRSS_CLK_ECO_CONFIG_ECO_EN_Msk SRSS_V2_CLK_ECO_CONFIG_ECO_EN_Msk 128 #define SRSS_CLK_ECO_CONFIG_ECO_EN_Pos SRSS_V2_CLK_ECO_CONFIG_ECO_EN_Pos 129 #define SRSS_CLK_ECO_CONFIG2_WDTRIM_Pos SRSS_V2_CLK_ECO_CONFIG2_WDTRIM_Pos 130 #define SRSS_CLK_ECO_CONFIG2_WDTRIM_Msk SRSS_V2_CLK_ECO_CONFIG2_WDTRIM_Msk 131 #define SRSS_CLK_ECO_CONFIG2_ATRIM_Pos SRSS_V2_CLK_ECO_CONFIG2_ATRIM_Pos 132 #define SRSS_CLK_ECO_CONFIG2_ATRIM_Msk SRSS_V2_CLK_ECO_CONFIG2_ATRIM_Msk 133 #define SRSS_CLK_ECO_CONFIG2_FTRIM_Msk SRSS_V2_CLK_ECO_CONFIG2_FTRIM_Msk 134 #define SRSS_CLK_ECO_CONFIG2_FTRIM_Pos SRSS_V2_CLK_ECO_CONFIG2_FTRIM_Pos 135 #define SRSS_CLK_ECO_CONFIG2_RTRIM_Pos SRSS_V2_CLK_ECO_CONFIG2_RTRIM_Pos 136 #define SRSS_CLK_ECO_CONFIG2_RTRIM_Msk SRSS_V2_CLK_ECO_CONFIG2_RTRIM_Msk 137 #define SRSS_CLK_ECO_CONFIG2_GTRIM_Pos SRSS_V2_CLK_ECO_CONFIG2_GTRIM_Pos 138 #define SRSS_CLK_ECO_CONFIG2_GTRIM_Msk SRSS_V2_CLK_ECO_CONFIG2_GTRIM_Msk 139 #define SRSS_CLK_ECO_CONFIG_AGC_EN_Pos SRSS_V2_CLK_ECO_CONFIG_AGC_EN_Pos 140 #define SRSS_CLK_ECO_CONFIG_AGC_EN_Msk SRSS_V2_CLK_ECO_CONFIG_AGC_EN_Msk 141 #define SRSS_PWR_CTL_LPM_READY_Msk SRSS_V2_PWR_CTL_LPM_READY_Msk 142 #define SRSS_PWR_CTL_LPM_READY_Pos SRSS_V2_PWR_CTL_LPM_READY_Pos 143 #define SRSS_CLK_ECO_STATUS_ECO_OK_Msk SRSS_V2_CLK_ECO_STATUS_ECO_OK_Msk 144 #define SRSS_CLK_ECO_STATUS_ECO_OK_Pos SRSS_V2_CLK_ECO_STATUS_ECO_OK_Pos 145 #define SRSS_CLK_ECO_STATUS_ECO_READY_Msk SRSS_V2_CLK_ECO_STATUS_ECO_READY_Msk 146 #define SRSS_CLK_ECO_STATUS_ECO_READY_Pos SRSS_V2_CLK_ECO_STATUS_ECO_READY_Pos 147 #define SRSS_CLK_ECO_PRESCALE_ECO_DIV_ENABLED_Msk SRSS_V2_CLK_ECO_PRESCALE_ECO_DIV_ENABLED_Msk 148 #define SRSS_CLK_ECO_PRESCALE_ECO_DIV_ENABLED_Pos SRSS_V2_CLK_ECO_PRESCALE_ECO_DIV_ENABLED_Pos 149 #define SRSS_CLK_ECO_PRESCALE_ECO_INT_DIV_Pos SRSS_V2_CLK_ECO_PRESCALE_ECO_INT_DIV_Pos 150 #define SRSS_CLK_ECO_PRESCALE_ECO_INT_DIV_Msk SRSS_V2_CLK_ECO_PRESCALE_ECO_INT_DIV_Msk 151 #define SRSS_CLK_ECO_PRESCALE_ECO_INT_DIV_Msk SRSS_V2_CLK_ECO_PRESCALE_ECO_INT_DIV_Msk 152 #define SRSS_CLK_ECO_PRESCALE_ECO_INT_DIV_Pos SRSS_V2_CLK_ECO_PRESCALE_ECO_INT_DIV_Pos 153 #define SRSS_CLK_ECO_PRESCALE_ECO_FRAC_DIV_Pos SRSS_V2_CLK_ECO_PRESCALE_ECO_FRAC_DIV_Pos 154 #define SRSS_CLK_ECO_PRESCALE_ECO_FRAC_DIV_Msk SRSS_V2_CLK_ECO_PRESCALE_ECO_FRAC_DIV_Msk 155 #define SRSS_PWR_SSV_CTL_OVDVDDD_ENABLE_Msk SRSS_V2_PWR_SSV_CTL_OVDVDDD_ENABLE_Msk 156 #define SRSS_PWR_SSV_CTL_OVDVDDD_ENABLE_Pos SRSS_V2_PWR_SSV_CTL_OVDVDDD_ENABLE_Pos 157 #define SRSS_CLK_ECO_CONFIG_ECO_DIV_ENABLE_Msk SRSS_V2_CLK_ECO_CONFIG_ECO_DIV_ENABLE_Msk 158 #define SRSS_CLK_ECO_CONFIG_ECO_DIV_ENABLE_Pos SRSS_V2_CLK_ECO_CONFIG_ECO_DIV_ENABLE_Pos 159 #define SRSS_PWR_SSV_CTL_OVDVDDA_ENABLE_Msk SRSS_V2_PWR_SSV_CTL_OVDVDDA_ENABLE_Msk 160 #define SRSS_PWR_SSV_CTL_OVDVDDA_ENABLE_Pos SRSS_V2_PWR_SSV_CTL_OVDVDDA_ENABLE_Pos 161 #define SRSS_CLK_ECO_CONFIG_ECO_DIV_DISABLE_Msk SRSS_V2_CLK_ECO_CONFIG_ECO_DIV_DISABLE_Msk 162 #define SRSS_CLK_ECO_CONFIG_ECO_DIV_DISABLE_Pos SRSS_V2_CLK_ECO_CONFIG_ECO_DIV_DISABLE_Pos 163 #define SRSS_CLK_IMO_CONFIG_ENABLE_Msk SRSS_V2_CLK_IMO_CONFIG_ENABLE_Msk 164 #define SRSS_CLK_IMO_CONFIG_ENABLE_Pos SRSS_V2_CLK_IMO_CONFIG_ENABLE_Pos 165 #define SRSS_CLK_DSI_SELECT_DSI_MUX_Pos SRSS_V2_CLK_DSI_SELECT_DSI_MUX_Pos 166 #define SRSS_CLK_DSI_SELECT_DSI_MUX_Msk SRSS_V2_CLK_DSI_SELECT_DSI_MUX_Msk 167 #define SRSS_PWR_SSV_CTL_OVDVCCD_ENABLE_Msk SRSS_V2_PWR_SSV_CTL_OVDVCCD_ENABLE_Msk 168 #define SRSS_PWR_SSV_CTL_OVDVCCD_ENABLE_Pos SRSS_V2_PWR_SSV_CTL_OVDVCCD_ENABLE_Pos 169 #define SRSS_CLK_PATH_SELECT_PATH_MUX_Pos SRSS_V2_CLK_PATH_SELECT_PATH_MUX_Pos 170 #define SRSS_CLK_PATH_SELECT_PATH_MUX_Msk SRSS_V2_CLK_PATH_SELECT_PATH_MUX_Msk 171 #define SRSS_PWR_SSV_CTL_OVDVDDD_VSEL_Msk SRSS_V2_PWR_SSV_CTL_OVDVDDD_VSEL_Msk 172 #define SRSS_PWR_SSV_CTL_OVDVDDD_VSEL_Pos SRSS_V2_PWR_SSV_CTL_OVDVDDD_VSEL_Pos 173 #define SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk SRSS_V2_CLK_FLL_CONFIG_FLL_ENABLE_Msk 174 #define SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Pos SRSS_V2_CLK_FLL_CONFIG_FLL_ENABLE_Pos 175 #define SRSS_CLK_FLL_STATUS_LOCKED_Msk SRSS_V2_CLK_FLL_STATUS_LOCKED_Msk 176 #define SRSS_CLK_FLL_STATUS_LOCKED_Pos SRSS_V2_CLK_FLL_STATUS_LOCKED_Pos 177 #define SRSS_CLK_FLL_CONFIG3_BYPASS_SEL_Msk SRSS_V2_CLK_FLL_CONFIG3_BYPASS_SEL_Msk 178 #define SRSS_CLK_FLL_CONFIG3_BYPASS_SEL_Pos SRSS_V2_CLK_FLL_CONFIG3_BYPASS_SEL_Pos 179 #define SRSS_CLK_FLL_CONFIG4_CCO_ENABLE_Msk SRSS_V2_CLK_FLL_CONFIG4_CCO_ENABLE_Msk 180 #define SRSS_CLK_FLL_CONFIG4_CCO_ENABLE_Pos SRSS_V2_CLK_FLL_CONFIG4_CCO_ENABLE_Pos 181 #define SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV_Msk SRSS_V2_CLK_FLL_CONFIG_FLL_OUTPUT_DIV_Msk 182 #define SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV_Pos SRSS_V2_CLK_FLL_CONFIG_FLL_OUTPUT_DIV_Pos 183 #define SRSS_CLK_FLL_CONFIG_FLL_MULT_Msk SRSS_V2_CLK_FLL_CONFIG_FLL_MULT_Msk 184 #define SRSS_CLK_FLL_CONFIG_FLL_MULT_Pos SRSS_V2_CLK_FLL_CONFIG_FLL_MULT_Pos 185 #define SRSS_CLK_FLL_CONFIG_FLL_MULT_Pos SRSS_V2_CLK_FLL_CONFIG_FLL_MULT_Pos 186 #define SRSS_CLK_FLL_CONFIG_FLL_MULT_Msk SRSS_V2_CLK_FLL_CONFIG_FLL_MULT_Msk 187 #define SRSS_PWR_SSV_CTL_OVDVDDA_VSEL_Msk SRSS_V2_PWR_SSV_CTL_OVDVDDA_VSEL_Msk 188 #define SRSS_PWR_SSV_CTL_OVDVDDA_VSEL_Pos SRSS_V2_PWR_SSV_CTL_OVDVDDA_VSEL_Pos 189 #define SRSS_PWR_SSV_CTL_OVDVDDA_VSEL_Pos SRSS_V2_PWR_SSV_CTL_OVDVDDA_VSEL_Pos 190 #define SRSS_PWR_SSV_CTL_OVDVDDA_VSEL_Msk SRSS_V2_PWR_SSV_CTL_OVDVDDA_VSEL_Msk 191 #define SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV_Msk SRSS_V2_CLK_FLL_CONFIG2_FLL_REF_DIV_Msk 192 #define SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV_Pos SRSS_V2_CLK_FLL_CONFIG2_FLL_REF_DIV_Pos 193 #define SRSS_PWR_SSV_CTL_OVDVDDA_ACTION_Msk SRSS_V2_PWR_SSV_CTL_OVDVDDA_ACTION_Msk 194 #define SRSS_PWR_SSV_CTL_OVDVDDA_ACTION_Pos SRSS_V2_PWR_SSV_CTL_OVDVDDA_ACTION_Pos 195 #define SRSS_CLK_FLL_CONFIG2_LOCK_TOL_Msk SRSS_V2_CLK_FLL_CONFIG2_LOCK_TOL_Msk 196 #define SRSS_CLK_FLL_CONFIG2_LOCK_TOL_Pos SRSS_V2_CLK_FLL_CONFIG2_LOCK_TOL_Pos 197 #define SRSS_PWR_SSV_CTL_BODVDDD_ENABLE_Msk SRSS_V2_PWR_SSV_CTL_BODVDDD_ENABLE_Msk 198 #define SRSS_PWR_SSV_CTL_BODVDDD_ENABLE_Pos SRSS_V2_PWR_SSV_CTL_BODVDDD_ENABLE_Pos 199 #define SRSS_PWR_SSV_CTL_BODVDDA_ENABLE_Msk SRSS_V2_PWR_SSV_CTL_BODVDDA_ENABLE_Msk 200 #define SRSS_PWR_SSV_CTL_BODVDDA_ENABLE_Pos SRSS_V2_PWR_SSV_CTL_BODVDDA_ENABLE_Pos 201 #define SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Msk SRSS_V2_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Msk 202 #define SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Pos SRSS_V2_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Pos 203 #define SRSS_PWR_SSV_CTL_BODVCCD_ENABLE_Msk SRSS_V2_PWR_SSV_CTL_BODVCCD_ENABLE_Msk 204 #define SRSS_PWR_SSV_CTL_BODVCCD_ENABLE_Pos SRSS_V2_PWR_SSV_CTL_BODVCCD_ENABLE_Pos 205 #define SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Msk SRSS_V2_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Msk 206 #define SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Pos SRSS_V2_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Pos 207 #define SRSS_PWR_SSV_CTL_BODVDDD_VSEL_Msk SRSS_V2_PWR_SSV_CTL_BODVDDD_VSEL_Msk 208 #define SRSS_PWR_SSV_CTL_BODVDDD_VSEL_Pos SRSS_V2_PWR_SSV_CTL_BODVDDD_VSEL_Pos 209 #define SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT_Msk SRSS_V2_CLK_FLL_CONFIG3_SETTLING_COUNT_Msk 210 #define SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT_Pos SRSS_V2_CLK_FLL_CONFIG3_SETTLING_COUNT_Pos 211 #define SRSS_PWR_SSV_CTL_BODVDDA_VSEL_Msk SRSS_V2_PWR_SSV_CTL_BODVDDA_VSEL_Msk 212 #define SRSS_PWR_SSV_CTL_BODVDDA_VSEL_Pos SRSS_V2_PWR_SSV_CTL_BODVDDA_VSEL_Pos 213 #define SRSS_CLK_FLL_CONFIG4_CCO_FREQ_Msk SRSS_V2_CLK_FLL_CONFIG4_CCO_FREQ_Msk 214 #define SRSS_CLK_FLL_CONFIG4_CCO_FREQ_Pos SRSS_V2_CLK_FLL_CONFIG4_CCO_FREQ_Pos 215 #define SRSS_PWR_SSV_CTL_BODVDDA_ACTION_Msk SRSS_V2_PWR_SSV_CTL_BODVDDA_ACTION_Msk 216 #define SRSS_PWR_SSV_CTL_BODVDDA_ACTION_Pos SRSS_V2_PWR_SSV_CTL_BODVDDA_ACTION_Pos 217 #define SRSS_CLK_FLL_CONFIG4_CCO_RANGE_Msk SRSS_V2_CLK_FLL_CONFIG4_CCO_RANGE_Msk 218 #define SRSS_CLK_FLL_CONFIG4_CCO_RANGE_Pos SRSS_V2_CLK_FLL_CONFIG4_CCO_RANGE_Pos 219 #define SRSS_PWR_SSV_STATUS_BODVDDD_OK_Msk SRSS_V2_PWR_SSV_STATUS_BODVDDD_OK_Msk 220 #define SRSS_PWR_SSV_STATUS_BODVDDD_OK_Pos SRSS_V2_PWR_SSV_STATUS_BODVDDD_OK_Pos 221 #define SRSS_PWR_SSV_STATUS_BODVDDA_OK_Msk SRSS_V2_PWR_SSV_STATUS_BODVDDA_OK_Msk 222 #define SRSS_PWR_SSV_STATUS_BODVDDA_OK_Pos SRSS_V2_PWR_SSV_STATUS_BODVDDA_OK_Pos 223 #define SRSS_PWR_SSV_STATUS_BODVCCD_OK_Msk SRSS_V2_PWR_SSV_STATUS_BODVCCD_OK_Msk 224 #define SRSS_PWR_SSV_STATUS_BODVCCD_OK_Pos SRSS_V2_PWR_SSV_STATUS_BODVCCD_OK_Pos 225 #define SRSS_CLK_FLL_STATUS_CCO_READY_Msk SRSS_V2_CLK_FLL_STATUS_CCO_READY_Msk 226 #define SRSS_CLK_FLL_STATUS_CCO_READY_Pos SRSS_V2_CLK_FLL_STATUS_CCO_READY_Pos 227 #define SRSS_CLK_PLL_CONFIG_ENABLE_Msk SRSS_V2_CLK_PLL_CONFIG_ENABLE_Msk 228 #define SRSS_CLK_PLL_CONFIG_ENABLE_Pos SRSS_V2_CLK_PLL_CONFIG_ENABLE_Pos 229 #define SRSS_CLK_PLL_STATUS_LOCKED_Msk SRSS_V2_CLK_PLL_STATUS_LOCKED_Msk 230 #define SRSS_CLK_PLL_STATUS_LOCKED_Pos SRSS_V2_CLK_PLL_STATUS_LOCKED_Pos 231 #define SRSS_CLK_PLL_STATUS_UNLOCK_OCCURRED_Msk SRSS_V2_CLK_PLL_STATUS_UNLOCK_OCCURRED_Msk 232 #define SRSS_CLK_PLL_STATUS_UNLOCK_OCCURRED_Pos SRSS_V2_CLK_PLL_STATUS_UNLOCK_OCCURRED_Pos 233 #define SRSS_CLK_PLL_CONFIG_BYPASS_SEL_Msk SRSS_V2_CLK_PLL_CONFIG_BYPASS_SEL_Msk 234 #define SRSS_CLK_PLL_CONFIG_BYPASS_SEL_Pos SRSS_V2_CLK_PLL_CONFIG_BYPASS_SEL_Pos 235 #define SRSS_PWR_SSV_STATUS_OVDVDDD_OK_Msk SRSS_V2_PWR_SSV_STATUS_OVDVDDD_OK_Msk 236 #define SRSS_PWR_SSV_STATUS_OVDVDDD_OK_Pos SRSS_V2_PWR_SSV_STATUS_OVDVDDD_OK_Pos 237 #define SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV_Pos SRSS_V2_CLK_PLL_CONFIG_FEEDBACK_DIV_Pos 238 #define SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV_Msk SRSS_V2_CLK_PLL_CONFIG_FEEDBACK_DIV_Msk 239 #define SRSS_PWR_SSV_STATUS_OVDVDDA_OK_Msk SRSS_V2_PWR_SSV_STATUS_OVDVDDA_OK_Msk 240 #define SRSS_PWR_SSV_STATUS_OVDVDDA_OK_Pos SRSS_V2_PWR_SSV_STATUS_OVDVDDA_OK_Pos 241 #define SRSS_PWR_SSV_STATUS_OVDVDDA_OK_Pos SRSS_V2_PWR_SSV_STATUS_OVDVDDA_OK_Pos 242 #define SRSS_PWR_SSV_STATUS_OVDVDDA_OK_Msk SRSS_V2_PWR_SSV_STATUS_OVDVDDA_OK_Msk 243 #define SRSS_PWR_SSV_STATUS_OVDVCCD_OK_Msk SRSS_V2_PWR_SSV_STATUS_OVDVCCD_OK_Msk 244 #define SRSS_PWR_SSV_STATUS_OVDVCCD_OK_Pos SRSS_V2_PWR_SSV_STATUS_OVDVCCD_OK_Pos 245 #define SRSS_CLK_PLL_CONFIG_REFERENCE_DIV_Pos SRSS_V2_CLK_PLL_CONFIG_REFERENCE_DIV_Pos 246 #define SRSS_CLK_PLL_CONFIG_REFERENCE_DIV_Msk SRSS_V2_CLK_PLL_CONFIG_REFERENCE_DIV_Msk 247 #define SRSS_PWR_CTL2_LINREG_LPMODE_Msk SRSS_V2_PWR_CTL2_LINREG_LPMODE_Msk 248 #define SRSS_PWR_CTL2_LINREG_LPMODE_Pos SRSS_V2_PWR_CTL2_LINREG_LPMODE_Pos 249 #define SRSS_CLK_PLL_CONFIG_OUTPUT_DIV_Pos SRSS_V2_CLK_PLL_CONFIG_OUTPUT_DIV_Pos 250 #define SRSS_CLK_PLL_CONFIG_OUTPUT_DIV_Msk SRSS_V2_CLK_PLL_CONFIG_OUTPUT_DIV_Msk 251 #define SRSS_PWR_CTL2_PORBOD_LPMODE_Msk SRSS_V2_PWR_CTL2_PORBOD_LPMODE_Msk 252 #define SRSS_PWR_CTL2_PORBOD_LPMODE_Pos SRSS_V2_PWR_CTL2_PORBOD_LPMODE_Pos 253 #define SRSS_PWR_CTL2_REFVBUF_DIS_Msk SRSS_V2_PWR_CTL2_REFVBUF_DIS_Msk 254 #define SRSS_PWR_CTL2_REFVBUF_DIS_Pos SRSS_V2_PWR_CTL2_REFVBUF_DIS_Pos 255 #define SRSS_PWR_CTL2_LINREG_OK_Msk SRSS_V2_PWR_CTL2_LINREG_OK_Msk 256 #define SRSS_PWR_CTL2_LINREG_OK_Pos SRSS_V2_PWR_CTL2_LINREG_OK_Pos 257 #define SRSS_CLK_PLL_CONFIG_PLL_LF_MODE_Pos SRSS_V2_CLK_PLL_CONFIG_PLL_LF_MODE_Pos 258 #define SRSS_CLK_PLL_CONFIG_PLL_LF_MODE_Msk SRSS_V2_CLK_PLL_CONFIG_PLL_LF_MODE_Msk 259 260 #define SRSS_CLK_PLL_CONFIG_BYPASS_SEL_Msk SRSS_V2_CLK_PLL_CONFIG_BYPASS_SEL_Msk 261 #define SRSS_CLK_PLL_CONFIG_BYPASS_SEL_Pos SRSS_V2_CLK_PLL_CONFIG_BYPASS_SEL_Pos 262 #define SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE_Msk SRSS_V2_CLK_CAL_CNT1_CAL_COUNTER_DONE_Msk 263 #define SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE_Pos SRSS_V2_CLK_CAL_CNT1_CAL_COUNTER_DONE_Pos 264 #define SRSS_CLK_CAL_CNT1_CAL_COUNTER1_Msk SRSS_V2_CLK_CAL_CNT1_CAL_COUNTER1_Msk 265 #define SRSS_CLK_CAL_CNT1_CAL_COUNTER1_Pos SRSS_V2_CLK_CAL_CNT1_CAL_COUNTER1_Pos 266 #define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL0_Pos SRSS_V2_CLK_OUTPUT_SLOW_SLOW_SEL0_Pos 267 #define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL0_Msk SRSS_V2_CLK_OUTPUT_SLOW_SLOW_SEL0_Msk 268 #define SRSS_CLK_OUTPUT_FAST_FAST_SEL0_Pos SRSS_V2_CLK_OUTPUT_FAST_FAST_SEL0_Pos 269 #define SRSS_CLK_OUTPUT_FAST_FAST_SEL0_Msk SRSS_V2_CLK_OUTPUT_FAST_FAST_SEL0_Msk 270 #define SRSS_CLK_OUTPUT_FAST_PATH_SEL0_Pos SRSS_V2_CLK_OUTPUT_FAST_PATH_SEL0_Pos 271 #define SRSS_CLK_OUTPUT_FAST_PATH_SEL0_Msk SRSS_V2_CLK_OUTPUT_FAST_PATH_SEL0_Msk 272 #define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL0_Pos SRSS_V2_CLK_OUTPUT_FAST_HFCLK_SEL0_Pos 273 #define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL0_Msk SRSS_V2_CLK_OUTPUT_FAST_HFCLK_SEL0_Msk 274 #define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL1_Pos SRSS_V2_CLK_OUTPUT_SLOW_SLOW_SEL1_Pos 275 #define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL1_Msk SRSS_V2_CLK_OUTPUT_SLOW_SLOW_SEL1_Msk 276 #define SRSS_CLK_OUTPUT_FAST_FAST_SEL1_Pos SRSS_V2_CLK_OUTPUT_FAST_FAST_SEL1_Pos 277 #define SRSS_CLK_OUTPUT_FAST_FAST_SEL1_Msk SRSS_V2_CLK_OUTPUT_FAST_FAST_SEL1_Msk 278 #define SRSS_CLK_OUTPUT_FAST_PATH_SEL1_Pos SRSS_V2_CLK_OUTPUT_FAST_PATH_SEL1_Pos 279 #define SRSS_CLK_OUTPUT_FAST_PATH_SEL1_Msk SRSS_V2_CLK_OUTPUT_FAST_PATH_SEL1_Msk 280 #define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL1_Pos SRSS_V2_CLK_OUTPUT_FAST_HFCLK_SEL1_Pos 281 #define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL1_Msk SRSS_V2_CLK_OUTPUT_FAST_HFCLK_SEL1_Msk 282 #define SRSS_CLK_CAL_CNT2_CAL_COUNTER2_Msk SRSS_V2_CLK_CAL_CNT2_CAL_COUNTER2_Msk 283 #define SRSS_CLK_CAL_CNT2_CAL_COUNTER2_Pos SRSS_V2_CLK_CAL_CNT2_CAL_COUNTER2_Pos 284 285 /* SRSS.CLK_TIMER_CTL */ 286 #define SRSS_CLK_TIMER_CTL_TIMER_SEL_Pos SRSS_V2_CLK_TIMER_CTL_TIMER_SEL_Pos 287 #define SRSS_CLK_TIMER_CTL_TIMER_SEL_Msk SRSS_V2_CLK_TIMER_CTL_TIMER_SEL_Msk 288 #define SRSS_CLK_TIMER_CTL_TIMER_HF0_DIV_Pos SRSS_V2_CLK_TIMER_CTL_TIMER_HF0_DIV_Pos 289 #define SRSS_CLK_TIMER_CTL_TIMER_HF0_DIV_Msk SRSS_V2_CLK_TIMER_CTL_TIMER_HF0_DIV_Msk 290 #define SRSS_CLK_TIMER_CTL_TIMER_DIV_Pos SRSS_V2_CLK_TIMER_CTL_TIMER_DIV_Pos 291 #define SRSS_CLK_TIMER_CTL_TIMER_DIV_Msk SRSS_V2_CLK_TIMER_CTL_TIMER_DIV_Msk 292 #define SRSS_CLK_TIMER_CTL_ENABLE_Pos SRSS_V2_CLK_TIMER_CTL_ENABLE_Pos 293 #define SRSS_CLK_TIMER_CTL_ENABLE_Msk SRSS_V2_CLK_TIMER_CTL_ENABLE_Msk 294 295 #define WDT_CTL_ENABLED_Pos WDT_V2_CTL_ENABLED_Pos 296 #define WDT_CTL_ENABLED_Msk WDT_V2_CTL_ENABLED_Msk 297 #define WDT_CTL_ENABLE_Pos WDT_V2_CTL_ENABLE_Pos 298 #define WDT_CTL_ENABLE_Msk WDT_V2_CTL_ENABLE_Msk 299 #define WDT_CNT_CNT_Msk WDT_V2_CNT_CNT_Msk 300 #define WDT_CNT_CNT_Pos WDT_V2_CNT_CNT_Pos 301 #define WDT_INTR_MASK_WDT_Msk WDT_V2_INTR_MASK_WDT_Msk 302 #define WDT_INTR_WDT_Pos WDT_V2_INTR_WDT_Pos 303 #define WDT_INTR_WDT_Msk WDT_V2_INTR_WDT_Msk 304 #define WDT_LOCK_WDT_LOCK_Pos WDT_V2_LOCK_WDT_LOCK_Pos 305 #define WDT_LOCK_WDT_LOCK_Msk WDT_V2_LOCK_WDT_LOCK_Msk 306 #define WDT_CONFIG_LOWER_ACTION_Msk WDT_V2_CONFIG_LOWER_ACTION_Msk 307 #define WDT_CONFIG_LOWER_ACTION_Pos WDT_V2_CONFIG_LOWER_ACTION_Pos 308 #define WDT_CONFIG_UPPER_ACTION_Msk WDT_V2_CONFIG_UPPER_ACTION_Msk 309 #define WDT_CONFIG_UPPER_ACTION_Pos WDT_V2_CONFIG_UPPER_ACTION_Pos 310 #define WDT_CONFIG_WARN_ACTION_Msk WDT_V2_CONFIG_WARN_ACTION_Msk 311 #define WDT_CONFIG_WARN_ACTION_Pos WDT_V2_CONFIG_WARN_ACTION_Pos 312 #define WDT_CONFIG_AUTO_SERVICE_Msk WDT_V2_CONFIG_AUTO_SERVICE_Msk 313 #define WDT_CONFIG_AUTO_SERVICE_Pos WDT_V2_CONFIG_AUTO_SERVICE_Pos 314 #define WDT_CONFIG_DPSLP_PAUSE_Msk WDT_V2_CONFIG_DPSLP_PAUSE_Msk 315 #define WDT_CONFIG_DPSLP_PAUSE_Pos WDT_V2_CONFIG_DPSLP_PAUSE_Pos 316 #define WDT_CONFIG_HIB_PAUSE_Msk WDT_V2_CONFIG_HIB_PAUSE_Msk 317 #define WDT_CONFIG_HIB_PAUSE_Pos WDT_V2_CONFIG_HIB_PAUSE_Pos 318 #define WDT_CONFIG_DEBUG_RUN_Msk WDT_V2_CONFIG_DEBUG_RUN_Msk 319 #define WDT_CONFIG_DEBUG_RUN_Pos WDT_V2_CONFIG_DEBUG_RUN_Pos 320 #define WDT_SERVICE_SERVICE_Msk WDT_V2_SERVICE_SERVICE_Msk 321 #define WDT_SERVICE_SERVICE_Pos WDT_V2_SERVICE_SERVICE_Pos 322 323 324 #define MCWDT_CTR_CTL_ENABLE_Msk MCWDT_CTR_V2_CTL_ENABLE_Msk 325 #define MCWDT_CTR_CTL_ENABLE_Pos MCWDT_CTR_V2_CTL_ENABLE_Pos 326 #define MCWDT_CTR2_CTL_ENABLE_Msk MCWDT_V2_CTR2_CTL_ENABLE_Msk 327 #define MCWDT_CTR2_CTL_ENABLE_Pos MCWDT_V2_CTR2_CTL_ENABLE_Pos 328 #define MCWDT_LOCK_MCWDT_LOCK_Msk MCWDT_V2_LOCK_MCWDT_LOCK_Msk 329 #define MCWDT_LOCK_MCWDT_LOCK_Pos MCWDT_V2_LOCK_MCWDT_LOCK_Pos 330 #define MCWDT_CTR2_CONFIG_BITS_Msk MCWDT_V2_CTR2_CONFIG_BITS_Msk 331 #define MCWDT_CTR2_CONFIG_BITS_Pos MCWDT_V2_CTR2_CONFIG_BITS_Pos 332 #define MCWDT_CTR_CNT_CNT_Msk MCWDT_CTR_V2_CNT_CNT_Msk 333 #define MCWDT_CTR_CNT_CNT_Pos MCWDT_CTR_V2_CNT_CNT_Pos 334 #define MCWDT_CTR2_CNT_CNT2_Msk MCWDT_V2_CTR2_CNT_CNT2_Msk 335 #define MCWDT_CTR2_CNT_CNT2_Pos MCWDT_V2_CTR2_CNT_CNT2_Pos 336 #define MCWDT_SERVICE_CTR0_SERVICE_Msk MCWDT_V2_SERVICE_CTR0_SERVICE_Msk 337 #define MCWDT_SERVICE_CTR0_SERVICE_Pos MCWDT_V2_SERVICE_CTR0_SERVICE_Pos 338 #define MCWDT_SERVICE_CTR1_SERVICE_Msk MCWDT_V2_SERVICE_CTR1_SERVICE_Msk 339 #define MCWDT_SERVICE_CTR1_SERVICE_Pos MCWDT_V2_SERVICE_CTR1_SERVICE_Pos 340 #define MCWDT_CTR_CONFIG_LOWER_ACTION_Pos MCWDT_CTR_V2_CONFIG_LOWER_ACTION_Pos 341 #define MCWDT_CTR_CONFIG_LOWER_ACTION_Msk MCWDT_CTR_V2_CONFIG_LOWER_ACTION_Msk 342 #define MCWDT_CTR_CONFIG_UPPER_ACTION_Pos MCWDT_CTR_V2_CONFIG_UPPER_ACTION_Pos 343 #define MCWDT_CTR_CONFIG_UPPER_ACTION_Msk MCWDT_CTR_V2_CONFIG_UPPER_ACTION_Msk 344 #define MCWDT_CTR_CONFIG_WARN_ACTION_Pos MCWDT_CTR_V2_CONFIG_WARN_ACTION_Pos 345 #define MCWDT_CTR_CONFIG_WARN_ACTION_Msk MCWDT_CTR_V2_CONFIG_WARN_ACTION_Msk 346 #define MCWDT_CTR_CONFIG_AUTO_SERVICE_Pos MCWDT_CTR_V2_CONFIG_AUTO_SERVICE_Pos 347 #define MCWDT_CTR_CONFIG_AUTO_SERVICE_Msk MCWDT_CTR_V2_CONFIG_AUTO_SERVICE_Msk 348 #define MCWDT_CTR_CONFIG_SLEEPDEEP_PAUSE_Pos MCWDT_CTR_V2_CONFIG_SLEEPDEEP_PAUSE_Pos 349 #define MCWDT_CTR_CONFIG_SLEEPDEEP_PAUSE_Msk MCWDT_CTR_V2_CONFIG_SLEEPDEEP_PAUSE_Msk 350 #define MCWDT_CTR_CONFIG_DEBUG_RUN_Pos MCWDT_CTR_V2_CONFIG_DEBUG_RUN_Pos 351 #define MCWDT_CTR_CONFIG_DEBUG_RUN_Msk MCWDT_CTR_V2_CONFIG_DEBUG_RUN_Msk 352 #define MCWDT_CTR2_CONFIG_ACTION_Pos MCWDT_V2_CTR2_CONFIG_ACTION_Pos 353 #define MCWDT_CTR2_CONFIG_ACTION_Msk MCWDT_V2_CTR2_CONFIG_ACTION_Msk 354 #define MCWDT_CTR2_CONFIG_SLEEPDEEP_PAUSE_Pos MCWDT_V2_CTR2_CONFIG_SLEEPDEEP_PAUSE_Pos 355 #define MCWDT_CTR2_CONFIG_SLEEPDEEP_PAUSE_Msk MCWDT_V2_CTR2_CONFIG_SLEEPDEEP_PAUSE_Msk 356 #define MCWDT_CTR2_CONFIG_DEBUG_RUN_Pos MCWDT_V2_CTR2_CONFIG_DEBUG_RUN_Pos 357 #define MCWDT_CTR2_CONFIG_DEBUG_RUN_Msk MCWDT_V2_CTR2_CONFIG_DEBUG_RUN_Msk 358 359 #define MCWDT_CPU_SELECT_CPU_SEL_Msk MCWDT_V2_CPU_SELECT_CPU_SEL_Msk 360 #define MCWDT_CPU_SELECT_CPU_SEL_Pos MCWDT_V2_CPU_SELECT_CPU_SEL_Pos 361 #define MCWDT_CTR_LOWER_LIMIT_LOWER_LIMIT_Msk MCWDT_CTR_V2_LOWER_LIMIT_LOWER_LIMIT_Msk 362 #define MCWDT_CTR_LOWER_LIMIT_LOWER_LIMIT_Pos MCWDT_CTR_V2_LOWER_LIMIT_LOWER_LIMIT_Pos 363 #define MCWDT_CTR_UPPER_LIMIT_UPPER_LIMIT_Msk MCWDT_CTR_V2_UPPER_LIMIT_UPPER_LIMIT_Msk 364 #define MCWDT_CTR_UPPER_LIMIT_UPPER_LIMIT_Pos MCWDT_CTR_V2_UPPER_LIMIT_UPPER_LIMIT_Pos 365 #define MCWDT_CTR_WARN_LIMIT_WARN_LIMIT_Msk MCWDT_CTR_V2_WARN_LIMIT_WARN_LIMIT_Msk 366 #define MCWDT_CTR_WARN_LIMIT_WARN_LIMIT_Pos MCWDT_CTR_V2_WARN_LIMIT_WARN_LIMIT_Pos 367 368 #define MCWDT_INTR_MASKED_CTR0_INT_Msk MCWDT_V2_INTR_MASKED_CTR0_INT_Msk 369 #define MCWDT_INTR_MASKED_CTR1_INT_Msk MCWDT_V2_INTR_MASKED_CTR1_INT_Msk 370 #define MCWDT_INTR_MASKED_CTR2_INT_Msk MCWDT_V2_INTR_MASKED_CTR2_INT_Msk 371 372 /******************************************************************************* 373 * BACKUP 374 *******************************************************************************/ 375 /* BACKUP.CTL */ 376 #define BACKUP_CTL_WCO_EN_Pos BACKUP_V2_CTL_WCO_EN_Pos 377 #define BACKUP_CTL_WCO_EN_Msk BACKUP_V2_CTL_WCO_EN_Msk 378 #define BACKUP_CTL_CLK_SEL_Pos BACKUP_V2_CTL_CLK_SEL_Pos 379 #define BACKUP_CTL_CLK_SEL_Msk BACKUP_V2_CTL_CLK_SEL_Msk 380 #define BACKUP_CTL_PRESCALER_Pos BACKUP_V2_CTL_PRESCALER_Pos 381 #define BACKUP_CTL_PRESCALER_Msk BACKUP_V2_CTL_PRESCALER_Msk 382 #define BACKUP_CTL_WCO_BYPASS_Pos BACKUP_V2_CTL_WCO_BYPASS_Pos 383 #define BACKUP_CTL_WCO_BYPASS_Msk BACKUP_V2_CTL_WCO_BYPASS_Msk 384 #define BACKUP_CTL_VDDBAK_CTL_Pos BACKUP_V2_CTL_VDDBAK_CTL_Pos 385 #define BACKUP_CTL_VDDBAK_CTL_Msk BACKUP_V2_CTL_VDDBAK_CTL_Msk 386 #define BACKUP_CTL_VBACKUP_MEAS_Pos BACKUP_V2_CTL_VBACKUP_MEAS_Pos 387 #define BACKUP_CTL_VBACKUP_MEAS_Msk BACKUP_V2_CTL_VBACKUP_MEAS_Msk 388 #define BACKUP_CTL_EN_CHARGE_KEY_Pos BACKUP_V2_CTL_EN_CHARGE_KEY_Pos 389 #define BACKUP_CTL_EN_CHARGE_KEY_Msk BACKUP_V2_CTL_EN_CHARGE_KEY_Msk 390 /* BACKUP.RTC_RW */ 391 #define BACKUP_RTC_RW_READ_Pos BACKUP_V2_RTC_RW_READ_Pos 392 #define BACKUP_RTC_RW_READ_Msk BACKUP_V2_RTC_RW_READ_Msk 393 #define BACKUP_RTC_RW_WRITE_Pos BACKUP_V2_RTC_RW_WRITE_Pos 394 #define BACKUP_RTC_RW_WRITE_Msk BACKUP_V2_RTC_RW_WRITE_Msk 395 /* BACKUP.CAL_CTL */ 396 #define BACKUP_CAL_CTL_CALIB_VAL_Pos BACKUP_V2_CAL_CTL_CALIB_VAL_Pos 397 #define BACKUP_CAL_CTL_CALIB_VAL_Msk BACKUP_V2_CAL_CTL_CALIB_VAL_Msk 398 #define BACKUP_CAL_CTL_CALIB_SIGN_Pos BACKUP_V2_CAL_CTL_CALIB_SIGN_Pos 399 #define BACKUP_CAL_CTL_CALIB_SIGN_Msk BACKUP_V2_CAL_CTL_CALIB_SIGN_Msk 400 #define BACKUP_CAL_CTL_CAL_SEL_Pos BACKUP_V2_CAL_CTL_CAL_SEL_Pos 401 #define BACKUP_CAL_CTL_CAL_SEL_Msk BACKUP_V2_CAL_CTL_CAL_SEL_Msk 402 #define BACKUP_CAL_CTL_CAL_OUT_Pos BACKUP_V2_CAL_CTL_CAL_OUT_Pos 403 #define BACKUP_CAL_CTL_CAL_OUT_Msk BACKUP_V2_CAL_CTL_CAL_OUT_Msk 404 /* BACKUP.STATUS */ 405 #define BACKUP_STATUS_RTC_BUSY_Pos BACKUP_V2_STATUS_RTC_BUSY_Pos 406 #define BACKUP_STATUS_RTC_BUSY_Msk BACKUP_V2_STATUS_RTC_BUSY_Msk 407 #define BACKUP_STATUS_WCO_OK_Pos BACKUP_V2_STATUS_WCO_OK_Pos 408 #define BACKUP_STATUS_WCO_OK_Msk BACKUP_V2_STATUS_WCO_OK_Msk 409 /* BACKUP.RTC_TIME */ 410 #define BACKUP_RTC_TIME_RTC_SEC_Pos BACKUP_V2_RTC_TIME_RTC_SEC_Pos 411 #define BACKUP_RTC_TIME_RTC_SEC_Msk BACKUP_V2_RTC_TIME_RTC_SEC_Msk 412 #define BACKUP_RTC_TIME_RTC_MIN_Pos BACKUP_V2_RTC_TIME_RTC_MIN_Pos 413 #define BACKUP_RTC_TIME_RTC_MIN_Msk BACKUP_V2_RTC_TIME_RTC_MIN_Msk 414 #define BACKUP_RTC_TIME_RTC_HOUR_Pos BACKUP_V2_RTC_TIME_RTC_HOUR_Pos 415 #define BACKUP_RTC_TIME_RTC_HOUR_Msk BACKUP_V2_RTC_TIME_RTC_HOUR_Msk 416 #define BACKUP_RTC_TIME_CTRL_12HR_Pos BACKUP_V2_RTC_TIME_CTRL_12HR_Pos 417 #define BACKUP_RTC_TIME_CTRL_12HR_Msk BACKUP_V2_RTC_TIME_CTRL_12HR_Msk 418 #define BACKUP_RTC_TIME_RTC_DAY_Pos BACKUP_V2_RTC_TIME_RTC_DAY_Pos 419 #define BACKUP_RTC_TIME_RTC_DAY_Msk BACKUP_V2_RTC_TIME_RTC_DAY_Msk 420 /* BACKUP.RTC_DATE */ 421 #define BACKUP_RTC_DATE_RTC_DATE_Pos BACKUP_V2_RTC_DATE_RTC_DATE_Pos 422 #define BACKUP_RTC_DATE_RTC_DATE_Msk BACKUP_V2_RTC_DATE_RTC_DATE_Msk 423 #define BACKUP_RTC_DATE_RTC_MON_Pos BACKUP_V2_RTC_DATE_RTC_MON_Pos 424 #define BACKUP_RTC_DATE_RTC_MON_Msk BACKUP_V2_RTC_DATE_RTC_MON_Msk 425 #define BACKUP_RTC_DATE_RTC_YEAR_Pos BACKUP_V2_RTC_DATE_RTC_YEAR_Pos 426 #define BACKUP_RTC_DATE_RTC_YEAR_Msk BACKUP_V2_RTC_DATE_RTC_YEAR_Msk 427 /* BACKUP.ALM1_TIME */ 428 #define BACKUP_ALM1_TIME_ALM_SEC_Pos BACKUP_V2_ALM1_TIME_ALM_SEC_Pos 429 #define BACKUP_ALM1_TIME_ALM_SEC_Msk BACKUP_V2_ALM1_TIME_ALM_SEC_Msk 430 #define BACKUP_ALM1_TIME_ALM_SEC_EN_Pos BACKUP_V2_ALM1_TIME_ALM_SEC_EN_Pos 431 #define BACKUP_ALM1_TIME_ALM_SEC_EN_Msk BACKUP_V2_ALM1_TIME_ALM_SEC_EN_Msk 432 #define BACKUP_ALM1_TIME_ALM_MIN_Pos BACKUP_V2_ALM1_TIME_ALM_MIN_Pos 433 #define BACKUP_ALM1_TIME_ALM_MIN_Msk BACKUP_V2_ALM1_TIME_ALM_MIN_Msk 434 #define BACKUP_ALM1_TIME_ALM_MIN_EN_Pos BACKUP_V2_ALM1_TIME_ALM_MIN_EN_Pos 435 #define BACKUP_ALM1_TIME_ALM_MIN_EN_Msk BACKUP_V2_ALM1_TIME_ALM_MIN_EN_Msk 436 #define BACKUP_ALM1_TIME_ALM_HOUR_Pos BACKUP_V2_ALM1_TIME_ALM_HOUR_Pos 437 #define BACKUP_ALM1_TIME_ALM_HOUR_Msk BACKUP_V2_ALM1_TIME_ALM_HOUR_Msk 438 #define BACKUP_ALM1_TIME_ALM_HOUR_EN_Pos BACKUP_V2_ALM1_TIME_ALM_HOUR_EN_Pos 439 #define BACKUP_ALM1_TIME_ALM_HOUR_EN_Msk BACKUP_V2_ALM1_TIME_ALM_HOUR_EN_Msk 440 #define BACKUP_ALM1_TIME_ALM_DAY_Pos BACKUP_V2_ALM1_TIME_ALM_DAY_Pos 441 #define BACKUP_ALM1_TIME_ALM_DAY_Msk BACKUP_V2_ALM1_TIME_ALM_DAY_Msk 442 #define BACKUP_ALM1_TIME_ALM_DAY_EN_Pos BACKUP_V2_ALM1_TIME_ALM_DAY_EN_Pos 443 #define BACKUP_ALM1_TIME_ALM_DAY_EN_Msk BACKUP_V2_ALM1_TIME_ALM_DAY_EN_Msk 444 /* BACKUP.ALM1_DATE */ 445 #define BACKUP_ALM1_DATE_ALM_DATE_Pos BACKUP_V2_ALM1_DATE_ALM_DATE_Pos 446 #define BACKUP_ALM1_DATE_ALM_DATE_Msk BACKUP_V2_ALM1_DATE_ALM_DATE_Msk 447 #define BACKUP_ALM1_DATE_ALM_DATE_EN_Pos BACKUP_V2_ALM1_DATE_ALM_DATE_EN_Pos 448 #define BACKUP_ALM1_DATE_ALM_DATE_EN_Msk BACKUP_V2_ALM1_DATE_ALM_DATE_EN_Msk 449 #define BACKUP_ALM1_DATE_ALM_MON_Pos BACKUP_V2_ALM1_DATE_ALM_MON_Pos 450 #define BACKUP_ALM1_DATE_ALM_MON_Msk BACKUP_V2_ALM1_DATE_ALM_MON_Msk 451 #define BACKUP_ALM1_DATE_ALM_MON_EN_Pos BACKUP_V2_ALM1_DATE_ALM_MON_EN_Pos 452 #define BACKUP_ALM1_DATE_ALM_MON_EN_Msk BACKUP_V2_ALM1_DATE_ALM_MON_EN_Msk 453 #define BACKUP_ALM1_DATE_ALM_EN_Pos BACKUP_V2_ALM1_DATE_ALM_EN_Pos 454 #define BACKUP_ALM1_DATE_ALM_EN_Msk BACKUP_V2_ALM1_DATE_ALM_EN_Msk 455 /* BACKUP.ALM2_TIME */ 456 #define BACKUP_ALM2_TIME_ALM_SEC_Pos BACKUP_V2_ALM2_TIME_ALM_SEC_Pos 457 #define BACKUP_ALM2_TIME_ALM_SEC_Msk BACKUP_V2_ALM2_TIME_ALM_SEC_Msk 458 #define BACKUP_ALM2_TIME_ALM_SEC_EN_Pos BACKUP_V2_ALM2_TIME_ALM_SEC_EN_Pos 459 #define BACKUP_ALM2_TIME_ALM_SEC_EN_Msk BACKUP_V2_ALM2_TIME_ALM_SEC_EN_Msk 460 #define BACKUP_ALM2_TIME_ALM_MIN_Pos BACKUP_V2_ALM2_TIME_ALM_MIN_Pos 461 #define BACKUP_ALM2_TIME_ALM_MIN_Msk BACKUP_V2_ALM2_TIME_ALM_MIN_Msk 462 #define BACKUP_ALM2_TIME_ALM_MIN_EN_Pos BACKUP_V2_ALM2_TIME_ALM_MIN_EN_Pos 463 #define BACKUP_ALM2_TIME_ALM_MIN_EN_Msk BACKUP_V2_ALM2_TIME_ALM_MIN_EN_Msk 464 #define BACKUP_ALM2_TIME_ALM_HOUR_Pos BACKUP_V2_ALM2_TIME_ALM_HOUR_Pos 465 #define BACKUP_ALM2_TIME_ALM_HOUR_Msk BACKUP_V2_ALM2_TIME_ALM_HOUR_Msk 466 #define BACKUP_ALM2_TIME_ALM_HOUR_EN_Pos BACKUP_V2_ALM2_TIME_ALM_HOUR_EN_Pos 467 #define BACKUP_ALM2_TIME_ALM_HOUR_EN_Msk BACKUP_V2_ALM2_TIME_ALM_HOUR_EN_Msk 468 #define BACKUP_ALM2_TIME_ALM_DAY_Pos BACKUP_V2_ALM2_TIME_ALM_DAY_Pos 469 #define BACKUP_ALM2_TIME_ALM_DAY_Msk BACKUP_V2_ALM2_TIME_ALM_DAY_Msk 470 #define BACKUP_ALM2_TIME_ALM_DAY_EN_Pos BACKUP_V2_ALM2_TIME_ALM_DAY_EN_Pos 471 #define BACKUP_ALM2_TIME_ALM_DAY_EN_Msk BACKUP_V2_ALM2_TIME_ALM_DAY_EN_Msk 472 /* BACKUP.ALM2_DATE */ 473 #define BACKUP_ALM2_DATE_ALM_DATE_Pos BACKUP_V2_ALM2_DATE_ALM_DATE_Pos 474 #define BACKUP_ALM2_DATE_ALM_DATE_Msk BACKUP_V2_ALM2_DATE_ALM_DATE_Msk 475 #define BACKUP_ALM2_DATE_ALM_DATE_EN_Pos BACKUP_V2_ALM2_DATE_ALM_DATE_EN_Pos 476 #define BACKUP_ALM2_DATE_ALM_DATE_EN_Msk BACKUP_V2_ALM2_DATE_ALM_DATE_EN_Msk 477 #define BACKUP_ALM2_DATE_ALM_MON_Pos BACKUP_V2_ALM2_DATE_ALM_MON_Pos 478 #define BACKUP_ALM2_DATE_ALM_MON_Msk BACKUP_V2_ALM2_DATE_ALM_MON_Msk 479 #define BACKUP_ALM2_DATE_ALM_MON_EN_Pos BACKUP_V2_ALM2_DATE_ALM_MON_EN_Pos 480 #define BACKUP_ALM2_DATE_ALM_MON_EN_Msk BACKUP_V2_ALM2_DATE_ALM_MON_EN_Msk 481 #define BACKUP_ALM2_DATE_ALM_EN_Pos BACKUP_V2_ALM2_DATE_ALM_EN_Pos 482 #define BACKUP_ALM2_DATE_ALM_EN_Msk BACKUP_V2_ALM2_DATE_ALM_EN_Msk 483 /* BACKUP.INTR */ 484 #define BACKUP_INTR_ALARM1_Pos BACKUP_V2_INTR_ALARM1_Pos 485 #define BACKUP_INTR_ALARM1_Msk BACKUP_V2_INTR_ALARM1_Msk 486 #define BACKUP_INTR_ALARM2_Pos BACKUP_V2_INTR_ALARM2_Pos 487 #define BACKUP_INTR_ALARM2_Msk BACKUP_V2_INTR_ALARM2_Msk 488 #define BACKUP_INTR_CENTURY_Pos BACKUP_V2_INTR_CENTURY_Pos 489 #define BACKUP_INTR_CENTURY_Msk BACKUP_V2_INTR_CENTURY_Msk 490 /* BACKUP.INTR_SET */ 491 #define BACKUP_INTR_SET_ALARM1_Pos BACKUP_V2_INTR_SET_ALARM1_Pos 492 #define BACKUP_INTR_SET_ALARM1_Msk BACKUP_V2_INTR_SET_ALARM1_Msk 493 #define BACKUP_INTR_SET_ALARM2_Pos BACKUP_V2_INTR_SET_ALARM2_Pos 494 #define BACKUP_INTR_SET_ALARM2_Msk BACKUP_V2_INTR_SET_ALARM2_Msk 495 #define BACKUP_INTR_SET_CENTURY_Pos BACKUP_V2_INTR_SET_CENTURY_Pos 496 #define BACKUP_INTR_SET_CENTURY_Msk BACKUP_V2_INTR_SET_CENTURY_Msk 497 /* BACKUP.INTR_MASK */ 498 #define BACKUP_INTR_MASK_ALARM1_Pos BACKUP_V2_INTR_MASK_ALARM1_Pos 499 #define BACKUP_INTR_MASK_ALARM1_Msk BACKUP_V2_INTR_MASK_ALARM1_Msk 500 #define BACKUP_INTR_MASK_ALARM2_Pos BACKUP_V2_INTR_MASK_ALARM2_Pos 501 #define BACKUP_INTR_MASK_ALARM2_Msk BACKUP_V2_INTR_MASK_ALARM2_Msk 502 #define BACKUP_INTR_MASK_CENTURY_Pos BACKUP_V2_INTR_MASK_CENTURY_Pos 503 #define BACKUP_INTR_MASK_CENTURY_Msk BACKUP_V2_INTR_MASK_CENTURY_Msk 504 /* BACKUP.INTR_MASKED */ 505 #define BACKUP_INTR_MASKED_ALARM1_Pos BACKUP_V2_INTR_MASKED_ALARM1_Pos 506 #define BACKUP_INTR_MASKED_ALARM1_Msk BACKUP_V2_INTR_MASKED_ALARM1_Msk 507 #define BACKUP_INTR_MASKED_ALARM2_Pos BACKUP_V2_INTR_MASKED_ALARM2_Pos 508 #define BACKUP_INTR_MASKED_ALARM2_Msk BACKUP_V2_INTR_MASKED_ALARM2_Msk 509 #define BACKUP_INTR_MASKED_CENTURY_Pos BACKUP_V2_INTR_MASKED_CENTURY_Pos 510 #define BACKUP_INTR_MASKED_CENTURY_Msk BACKUP_V2_INTR_MASKED_CENTURY_Msk 511 /* BACKUP.PMIC_CTL */ 512 #define BACKUP_PMIC_CTL_UNLOCK_Pos BACKUP_V2_PMIC_CTL_UNLOCK_Pos 513 #define BACKUP_PMIC_CTL_UNLOCK_Msk BACKUP_V2_PMIC_CTL_UNLOCK_Msk 514 #define BACKUP_PMIC_CTL_POLARITY_Pos BACKUP_V2_PMIC_CTL_POLARITY_Pos 515 #define BACKUP_PMIC_CTL_POLARITY_Msk BACKUP_V2_PMIC_CTL_POLARITY_Msk 516 #define BACKUP_PMIC_CTL_PMIC_EN_OUTEN_Pos BACKUP_V2_PMIC_CTL_PMIC_EN_OUTEN_Pos 517 #define BACKUP_PMIC_CTL_PMIC_EN_OUTEN_Msk BACKUP_V2_PMIC_CTL_PMIC_EN_OUTEN_Msk 518 #define BACKUP_PMIC_CTL_PMIC_ALWAYSEN_Pos BACKUP_V2_PMIC_CTL_PMIC_ALWAYSEN_Pos 519 #define BACKUP_PMIC_CTL_PMIC_ALWAYSEN_Msk BACKUP_V2_PMIC_CTL_PMIC_ALWAYSEN_Msk 520 #define BACKUP_PMIC_CTL_PMIC_EN_Pos BACKUP_V2_PMIC_CTL_PMIC_EN_Pos 521 #define BACKUP_PMIC_CTL_PMIC_EN_Msk BACKUP_V2_PMIC_CTL_PMIC_EN_Msk 522 /* BACKUP.RESET */ 523 #define BACKUP_RESET_RESET_Pos BACKUP_V2_RESET_RESET_Pos 524 #define BACKUP_RESET_RESET_Msk BACKUP_V2_RESET_RESET_Msk 525 /* BACKUP.BREG */ 526 #define BACKUP_BREG_BREG_Pos BACKUP_V2_BREG_BREG_Pos 527 #define BACKUP_BREG_BREG_Msk BACKUP_V2_BREG_BREG_Msk 528 529 530 #elif defined(CY_DEVICE_TVIIBE4M) 531 /* SRSSv3 remaps for what is generated in a TVII generated header file */ 532 533 /******************************************************************************* 534 * SRSS 535 *******************************************************************************/ 536 /* SRSS 3 Additions for TVII Generated Header file */ 537 #define SRSS_PWR_HIBERNATE_MASK_HIBPIN_Pos SRSS_V3_PWR_HIBERNATE_MASK_HIBPIN_Pos 538 #define SRSS_PWR_HIBERNATE_MASK_HIBPIN_Msk SRSS_V3_PWR_HIBERNATE_MASK_HIBPIN_Msk 539 #define SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Pos SRSS_V3_PWR_HIBERNATE_POLARITY_HIBPIN_Pos 540 #define SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Msk SRSS_V3_PWR_HIBERNATE_POLARITY_HIBPIN_Msk 541 #define SRSS_PWR_HIBERNATE_MASK_HIBALARM_Msk SRSS_V3_PWR_HIBERNATE_MASK_HIBALARM_Msk 542 #define SRSS_PWR_HIBERNATE_MASK_HIBALARM_Pos SRSS_V3_PWR_HIBERNATE_MASK_HIBALARM_Pos 543 #define SRSS_PWR_HIBERNATE_MASK_HIBWDT_Msk SRSS_V3_PWR_HIBERNATE_MASK_HIBWDT_Msk 544 #define SRSS_PWR_LVD_CTL_HVLVD1_EN_HT_Msk SRSS_V3_PWR_LVD_CTL_HVLVD1_EN_HT_Msk 545 #define SRSS_PWR_LVD_CTL_HVLVD1_EN_HT_Pos SRSS_V3_PWR_LVD_CTL_HVLVD1_EN_HT_Pos 546 #define SRSS_PWR_LVD_CTL_HVLVD1_EN_HT_Msk SRSS_V3_PWR_LVD_CTL_HVLVD1_EN_HT_Msk 547 #define SRSS_PWR_LVD_CTL_HVLVD1_EN_HT_Pos SRSS_V3_PWR_LVD_CTL_HVLVD1_EN_HT_Pos 548 #define SRSS_PWR_LVD_CTL2_HVLVD2_EN_HT_Msk SRSS_V3_PWR_LVD_CTL2_HVLVD2_EN_HT_Msk 549 #define SRSS_PWR_LVD_CTL2_HVLVD2_EN_HT_Pos SRSS_V3_PWR_LVD_CTL2_HVLVD2_EN_HT_Pos 550 #define SRSS_PWR_LVD_CTL_HVLVD1_TRIPSEL_HT_Msk SRSS_V3_PWR_LVD_CTL_HVLVD1_TRIPSEL_HT_Msk 551 #define SRSS_PWR_LVD_CTL_HVLVD1_TRIPSEL_HT_Pos SRSS_V3_PWR_LVD_CTL_HVLVD1_TRIPSEL_HT_Pos 552 #define SRSS_PWR_LVD_CTL2_HVLVD2_TRIPSEL_HT_Msk SRSS_V3_PWR_LVD_CTL2_HVLVD2_TRIPSEL_HT_Msk 553 #define SRSS_PWR_LVD_CTL2_HVLVD2_TRIPSEL_HT_Pos SRSS_V3_PWR_LVD_CTL2_HVLVD2_TRIPSEL_HT_Pos 554 #define SRSS_PWR_LVD_STATUS_HVLVD1_OUT_Msk SRSS_V3_PWR_LVD_STATUS_HVLVD1_OUT_Msk 555 #define SRSS_PWR_LVD_STATUS_HVLVD1_OUT_Pos SRSS_V3_PWR_LVD_STATUS_HVLVD1_OUT_Pos 556 #define SRSS_PWR_LVD_STATUS2_HVLVD2_OUT_Msk SRSS_V3_PWR_LVD_STATUS2_HVLVD2_OUT_Msk 557 #define SRSS_PWR_LVD_STATUS2_HVLVD2_OUT_Pos SRSS_V3_PWR_LVD_STATUS2_HVLVD2_OUT_Pos 558 #define SRSS_SRSS_INTR_HVLVD1_Msk SRSS_V3_SRSS_INTR_HVLVD1_Msk 559 #define SRSS_SRSS_INTR_HVLVD1_Pos SRSS_V3_SRSS_INTR_HVLVD1_Pos 560 #define SRSS_SRSS_INTR_HVLVD2_Msk SRSS_V3_SRSS_INTR_HVLVD2_Msk 561 #define SRSS_SRSS_INTR_HVLVD2_Pos SRSS_V3_SRSS_INTR_HVLVD2_Pos 562 #define SRSS_SRSS_INTR_SET_HVLVD1_Msk SRSS_V3_SRSS_INTR_SET_HVLVD1_Msk 563 #define SRSS_SRSS_INTR_SET_HVLVD1_Pos SRSS_V3_SRSS_INTR_SET_HVLVD1_Pos 564 #define SRSS_SRSS_INTR_SET_HVLVD2_Msk SRSS_V3_SRSS_INTR_SET_HVLVD2_Msk 565 #define SRSS_SRSS_INTR_SET_HVLVD2_Pos SRSS_V3_SRSS_INTR_SET_HVLVD2_Pos 566 #define SRSS_SRSS_INTR_MASK_HVLVD1_Msk SRSS_V3_SRSS_INTR_MASK_HVLVD1_Msk 567 #define SRSS_SRSS_INTR_MASK_HVLVD1_Pos SRSS_V3_SRSS_INTR_MASK_HVLVD1_Pos 568 #define SRSS_SRSS_INTR_MASK_HVLVD2_Msk SRSS_V3_SRSS_INTR_MASK_HVLVD2_Msk 569 #define SRSS_SRSS_INTR_MASK_HVLVD2_Pos SRSS_V3_SRSS_INTR_MASK_HVLVD2_Pos 570 #define SRSS_PWR_LVD_CTL_HVLVD1_EDGE_SEL_Msk SRSS_V3_PWR_LVD_CTL_HVLVD1_EDGE_SEL_Msk 571 #define SRSS_PWR_LVD_CTL_HVLVD1_EDGE_SEL_Pos SRSS_V3_PWR_LVD_CTL_HVLVD1_EDGE_SEL_Pos 572 #define SRSS_PWR_LVD_CTL_HVLVD2_EDGE_SEL_Msk SRSS_V3_PWR_LVD_CTL_HVLVD2_EDGE_SEL_Msk 573 #define SRSS_PWR_LVD_CTL_HVLVD2_EDGE_SEL_Pos SRSS_V3_PWR_LVD_CTL_HVLVD2_EDGE_SEL_Pos 574 #define SRSS_PWR_LVD_CTL2_HVLVD2_EDGE_SEL_Msk SRSS_V3_PWR_LVD_CTL2_HVLVD2_EDGE_SEL_Msk 575 #define SRSS_PWR_LVD_CTL2_HVLVD2_EDGE_SEL_Pos SRSS_V3_PWR_LVD_CTL2_HVLVD2_EDGE_SEL_Pos 576 #define SRSS_PWR_LVD_CTL2_HVLVD2_ACTION_Msk SRSS_V3_PWR_LVD_CTL2_HVLVD2_ACTION_Msk 577 #define SRSS_PWR_LVD_CTL2_HVLVD2_ACTION_Pos SRSS_V3_PWR_LVD_CTL2_HVLVD2_ACTION_Pos 578 #define SRSS_PWR_LVD_CTL_HVLVD1_ACTION_Msk SRSS_V3_PWR_LVD_CTL_HVLVD1_ACTION_Msk 579 #define SRSS_PWR_LVD_CTL_HVLVD1_ACTION_Pos SRSS_V3_PWR_LVD_CTL_HVLVD1_ACTION_Pos 580 #define SRSS_PWR_LVD_CTL_HVLVD1_DPSLP_EN_HT_Msk SRSS_V3_PWR_LVD_CTL_HVLVD1_DPSLP_EN_HT_Msk 581 #define SRSS_PWR_LVD_CTL_HVLVD1_DPSLP_EN_HT_Pos SRSS_V3_PWR_LVD_CTL_HVLVD1_DPSLP_EN_HT_Pos 582 #define SRSS_PWR_LVD_CTL2_HVLVD2_DPSLP_EN_HT_Msk SRSS_V3_PWR_LVD_CTL2_HVLVD2_DPSLP_EN_HT_Msk 583 #define SRSS_PWR_LVD_CTL2_HVLVD2_DPSLP_EN_HT_Pos SRSS_V3_PWR_LVD_CTL2_HVLVD2_DPSLP_EN_HT_Pos 584 #define SRSS_CLK_SELECT_PUMP_SEL_Msk SRSS_V3_CLK_SELECT_PUMP_SEL_Msk 585 #define SRSS_CLK_SELECT_PUMP_SEL_Pos SRSS_V3_CLK_SELECT_PUMP_SEL_Pos 586 #define SRSS_CLK_SELECT_PUMP_DIV_Msk SRSS_V3_CLK_SELECT_PUMP_DIV_Msk 587 #define SRSS_CLK_SELECT_PUMP_DIV_Pos SRSS_V3_CLK_SELECT_PUMP_DIV_Pos 588 #define SRSS_RES_CAUSE2_RESET_CSV_HF_Msk SRSS_V3_RES_CAUSE2_RESET_CSV_HF_Msk 589 #define SRSS_RES_CAUSE2_RESET_CSV_HF_Pos SRSS_V3_RES_CAUSE2_RESET_CSV_HF_Pos 590 #define SRSS_CLK_SELECT_PUMP_ENABLE_Msk SRSS_V3_CLK_SELECT_PUMP_ENABLE_Msk 591 #define SRSS_CLK_SELECT_PUMP_ENABLE_Pos SRSS_V3_CLK_SELECT_PUMP_ENABLE_Pos 592 #define SRSS_PWR_CTL2_BGREF_LPMODE_Msk SRSS_V3_PWR_CTL2_BGREF_LPMODE_Msk 593 #define SRSS_PWR_CTL2_BGREF_LPMODE_Pos SRSS_V3_PWR_CTL2_BGREF_LPMODE_Pos 594 #define SRSS_RES_CAUSE2_RESET_CSV_HF_Pos SRSS_V3_RES_CAUSE2_RESET_CSV_HF_Pos 595 #define SRSS_RES_CAUSE2_RESET_CSV_HF_Msk SRSS_V3_RES_CAUSE2_RESET_CSV_HF_Msk 596 #define SRSS_PWR_HIBERNATE_TOKEN_Msk SRSS_V3_PWR_HIBERNATE_TOKEN_Msk 597 #define SRSS_PWR_HIBERNATE_TOKEN_Pos SRSS_V3_PWR_HIBERNATE_TOKEN_Pos 598 #define SRSS_PWR_HIBERNATE_UNLOCK_Pos SRSS_V3_PWR_HIBERNATE_UNLOCK_Pos 599 #define SRSS_PWR_HIBERNATE_UNLOCK_Msk SRSS_V3_PWR_HIBERNATE_UNLOCK_Msk 600 #define SRSS_PWR_HIBERNATE_FREEZE_Msk SRSS_V3_PWR_HIBERNATE_FREEZE_Msk 601 #define SRSS_PWR_HIBERNATE_FREEZE_Pos SRSS_V3_PWR_HIBERNATE_FREEZE_Pos 602 #define SRSS_PWR_HIBERNATE_HIBERNATE_Msk SRSS_V3_PWR_HIBERNATE_HIBERNATE_Msk 603 #define SRSS_PWR_HIBERNATE_HIBERNATE_Pos SRSS_V3_PWR_HIBERNATE_HIBERNATE_Pos 604 #define SRSS_CLK_SELECT_LFCLK_SEL_Msk SRSS_V3_CLK_SELECT_LFCLK_SEL_Msk 605 #define SRSS_CLK_SELECT_LFCLK_SEL_Pos SRSS_V3_CLK_SELECT_LFCLK_SEL_Pos 606 #define SRSS_RES_CAUSE2_RESET_CSV_REF_Msk SRSS_V3_RES_CAUSE2_RESET_CSV_REF_Msk 607 #define SRSS_RES_CAUSE2_RESET_CSV_REF_Pos SRSS_V3_RES_CAUSE2_RESET_CSV_REF_Pos 608 #define SRSS_CLK_ROOT_SELECT_ENABLE_Msk SRSS_V3_CLK_ROOT_SELECT_ENABLE_Msk 609 #define SRSS_CLK_ROOT_SELECT_ENABLE_Pos SRSS_V3_CLK_ROOT_SELECT_ENABLE_Pos 610 #define SRSS_CLK_ROOT_SELECT_ROOT_MUX_Msk SRSS_V3_CLK_ROOT_SELECT_ROOT_MUX_Msk 611 #define SRSS_CLK_ROOT_SELECT_ROOT_MUX_Pos SRSS_V3_CLK_ROOT_SELECT_ROOT_MUX_Pos 612 #define SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk SRSS_V3_CLK_ROOT_SELECT_ROOT_DIV_Msk 613 #define SRSS_CLK_ROOT_SELECT_ROOT_DIV_Pos SRSS_V3_CLK_ROOT_SELECT_ROOT_DIV_Pos 614 #define SRSS_CLK_ROOT_SELECT_DIRECT_MUX_Msk SRSS_V3_CLK_ROOT_SELECT_DIRECT_MUX_Msk 615 #define SRSS_CLK_ROOT_SELECT_DIRECT_MUX_Pos SRSS_V3_CLK_ROOT_SELECT_DIRECT_MUX_Pos 616 #define SRSS_PWR_CTL2_LINREG_DIS_Msk SRSS_V3_PWR_CTL2_LINREG_DIS_Msk 617 #define SRSS_PWR_CTL2_LINREG_DIS_Pos SRSS_V3_PWR_CTL2_LINREG_DIS_Pos 618 #define SRSS_PWR_CTL2_DPSLP_REG_DIS_Msk SRSS_V3_PWR_CTL2_DPSLP_REG_DIS_Msk 619 #define SRSS_PWR_CTL2_DPSLP_REG_DIS_Pos SRSS_V3_PWR_CTL2_DPSLP_REG_DIS_Pos 620 #define SRSS_CLK_ILO0_CONFIG_ENABLE_Msk SRSS_V3_CLK_ILO0_CONFIG_ENABLE_Msk 621 #define SRSS_CLK_ILO0_CONFIG_ENABLE_Pos SRSS_V3_CLK_ILO0_CONFIG_ENABLE_Pos 622 #define SRSS_CLK_ILO0_CONFIG_ILO0_BACKUP_Msk SRSS_V3_CLK_ILO0_CONFIG_ILO0_BACKUP_Msk 623 #define SRSS_CLK_ILO0_CONFIG_ILO0_BACKUP_Pos SRSS_V3_CLK_ILO0_CONFIG_ILO0_BACKUP_Pos 624 #define SRSS_CLK_ILO1_CONFIG_ENABLE_Msk SRSS_V3_CLK_ILO1_CONFIG_ENABLE_Msk 625 #define SRSS_CLK_ILO1_CONFIG_ENABLE_Pos SRSS_V3_CLK_ILO1_CONFIG_ENABLE_Pos 626 #define SRSS_CLK_ECO_CONFIG_ECO_EN_Msk SRSS_V3_CLK_ECO_CONFIG_ECO_EN_Msk 627 #define SRSS_CLK_ECO_CONFIG_ECO_EN_Pos SRSS_V3_CLK_ECO_CONFIG_ECO_EN_Pos 628 #define SRSS_CLK_ECO_CONFIG2_WDTRIM_Pos SRSS_V3_CLK_ECO_CONFIG2_WDTRIM_Pos 629 #define SRSS_CLK_ECO_CONFIG2_WDTRIM_Msk SRSS_V3_CLK_ECO_CONFIG2_WDTRIM_Msk 630 #define SRSS_CLK_ECO_CONFIG2_ATRIM_Pos SRSS_V3_CLK_ECO_CONFIG2_ATRIM_Pos 631 #define SRSS_CLK_ECO_CONFIG2_ATRIM_Msk SRSS_V3_CLK_ECO_CONFIG2_ATRIM_Msk 632 #define SRSS_CLK_ECO_CONFIG2_FTRIM_Msk SRSS_V3_CLK_ECO_CONFIG2_FTRIM_Msk 633 #define SRSS_CLK_ECO_CONFIG2_FTRIM_Pos SRSS_V3_CLK_ECO_CONFIG2_FTRIM_Pos 634 #define SRSS_CLK_ECO_CONFIG2_RTRIM_Pos SRSS_V3_CLK_ECO_CONFIG2_RTRIM_Pos 635 #define SRSS_CLK_ECO_CONFIG2_RTRIM_Msk SRSS_V3_CLK_ECO_CONFIG2_RTRIM_Msk 636 #define SRSS_CLK_ECO_CONFIG2_GTRIM_Pos SRSS_V3_CLK_ECO_CONFIG2_GTRIM_Pos 637 #define SRSS_CLK_ECO_CONFIG2_GTRIM_Msk SRSS_V3_CLK_ECO_CONFIG2_GTRIM_Msk 638 #define SRSS_CLK_ECO_CONFIG_AGC_EN_Pos SRSS_V3_CLK_ECO_CONFIG_AGC_EN_Pos 639 #define SRSS_CLK_ECO_CONFIG_AGC_EN_Msk SRSS_V3_CLK_ECO_CONFIG_AGC_EN_Msk 640 #define SRSS_PWR_CTL_LPM_READY_Msk SRSS_V3_PWR_CTL_LPM_READY_Msk 641 #define SRSS_PWR_CTL_LPM_READY_Pos SRSS_V3_PWR_CTL_LPM_READY_Pos 642 #define SRSS_CLK_ECO_STATUS_ECO_OK_Msk SRSS_V3_CLK_ECO_STATUS_ECO_OK_Msk 643 #define SRSS_CLK_ECO_STATUS_ECO_OK_Pos SRSS_V3_CLK_ECO_STATUS_ECO_OK_Pos 644 #define SRSS_CLK_ECO_STATUS_ECO_READY_Msk SRSS_V3_CLK_ECO_STATUS_ECO_READY_Msk 645 #define SRSS_CLK_ECO_STATUS_ECO_READY_Pos SRSS_V3_CLK_ECO_STATUS_ECO_READY_Pos 646 #define SRSS_CLK_ECO_PRESCALE_ECO_DIV_ENABLED_Msk SRSS_V3_CLK_ECO_PRESCALE_ECO_DIV_ENABLED_Msk 647 #define SRSS_CLK_ECO_PRESCALE_ECO_DIV_ENABLED_Pos SRSS_V3_CLK_ECO_PRESCALE_ECO_DIV_ENABLED_Pos 648 #define SRSS_CLK_ECO_PRESCALE_ECO_INT_DIV_Pos SRSS_V3_CLK_ECO_PRESCALE_ECO_INT_DIV_Pos 649 #define SRSS_CLK_ECO_PRESCALE_ECO_INT_DIV_Msk SRSS_V3_CLK_ECO_PRESCALE_ECO_INT_DIV_Msk 650 #define SRSS_CLK_ECO_PRESCALE_ECO_INT_DIV_Msk SRSS_V3_CLK_ECO_PRESCALE_ECO_INT_DIV_Msk 651 #define SRSS_CLK_ECO_PRESCALE_ECO_INT_DIV_Pos SRSS_V3_CLK_ECO_PRESCALE_ECO_INT_DIV_Pos 652 #define SRSS_CLK_ECO_PRESCALE_ECO_FRAC_DIV_Pos SRSS_V3_CLK_ECO_PRESCALE_ECO_FRAC_DIV_Pos 653 #define SRSS_CLK_ECO_PRESCALE_ECO_FRAC_DIV_Msk SRSS_V3_CLK_ECO_PRESCALE_ECO_FRAC_DIV_Msk 654 #define SRSS_PWR_SSV_CTL_OVDVDDD_ENABLE_Msk SRSS_V3_PWR_SSV_CTL_OVDVDDD_ENABLE_Msk 655 #define SRSS_PWR_SSV_CTL_OVDVDDD_ENABLE_Pos SRSS_V3_PWR_SSV_CTL_OVDVDDD_ENABLE_Pos 656 #define SRSS_CLK_ECO_CONFIG_ECO_DIV_ENABLE_Msk SRSS_V3_CLK_ECO_CONFIG_ECO_DIV_ENABLE_Msk 657 #define SRSS_CLK_ECO_CONFIG_ECO_DIV_ENABLE_Pos SRSS_V3_CLK_ECO_CONFIG_ECO_DIV_ENABLE_Pos 658 #define SRSS_PWR_SSV_CTL_OVDVDDA_ENABLE_Msk SRSS_V3_PWR_SSV_CTL_OVDVDDA_ENABLE_Msk 659 #define SRSS_PWR_SSV_CTL_OVDVDDA_ENABLE_Pos SRSS_V3_PWR_SSV_CTL_OVDVDDA_ENABLE_Pos 660 #define SRSS_CLK_ECO_CONFIG_ECO_DIV_DISABLE_Msk SRSS_V3_CLK_ECO_CONFIG_ECO_DIV_DISABLE_Msk 661 #define SRSS_CLK_ECO_CONFIG_ECO_DIV_DISABLE_Pos SRSS_V3_CLK_ECO_CONFIG_ECO_DIV_DISABLE_Pos 662 #define SRSS_CLK_IMO_CONFIG_ENABLE_Msk SRSS_V3_CLK_IMO_CONFIG_ENABLE_Msk 663 #define SRSS_CLK_IMO_CONFIG_ENABLE_Pos SRSS_V3_CLK_IMO_CONFIG_ENABLE_Pos 664 #define SRSS_CLK_DSI_SELECT_DSI_MUX_Pos SRSS_V3_CLK_DSI_SELECT_DSI_MUX_Pos 665 #define SRSS_CLK_DSI_SELECT_DSI_MUX_Msk SRSS_V3_CLK_DSI_SELECT_DSI_MUX_Msk 666 #define SRSS_PWR_SSV_CTL_OVDVCCD_ENABLE_Msk SRSS_V3_PWR_SSV_CTL_OVDVCCD_ENABLE_Msk 667 #define SRSS_PWR_SSV_CTL_OVDVCCD_ENABLE_Pos SRSS_V3_PWR_SSV_CTL_OVDVCCD_ENABLE_Pos 668 #define SRSS_CLK_PATH_SELECT_PATH_MUX_Pos SRSS_V3_CLK_PATH_SELECT_PATH_MUX_Pos 669 #define SRSS_CLK_PATH_SELECT_PATH_MUX_Msk SRSS_V3_CLK_PATH_SELECT_PATH_MUX_Msk 670 #define SRSS_PWR_SSV_CTL_OVDVDDD_VSEL_Msk SRSS_V3_PWR_SSV_CTL_OVDVDDD_VSEL_Msk 671 #define SRSS_PWR_SSV_CTL_OVDVDDD_VSEL_Pos SRSS_V3_PWR_SSV_CTL_OVDVDDD_VSEL_Pos 672 #define SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk SRSS_V3_CLK_FLL_CONFIG_FLL_ENABLE_Msk 673 #define SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Pos SRSS_V3_CLK_FLL_CONFIG_FLL_ENABLE_Pos 674 #define SRSS_CLK_FLL_STATUS_LOCKED_Msk SRSS_V3_CLK_FLL_STATUS_LOCKED_Msk 675 #define SRSS_CLK_FLL_STATUS_LOCKED_Pos SRSS_V3_CLK_FLL_STATUS_LOCKED_Pos 676 #define SRSS_CLK_FLL_CONFIG3_BYPASS_SEL_Msk SRSS_V3_CLK_FLL_CONFIG3_BYPASS_SEL_Msk 677 #define SRSS_CLK_FLL_CONFIG3_BYPASS_SEL_Pos SRSS_V3_CLK_FLL_CONFIG3_BYPASS_SEL_Pos 678 #define SRSS_CLK_FLL_CONFIG4_CCO_ENABLE_Msk SRSS_V3_CLK_FLL_CONFIG4_CCO_ENABLE_Msk 679 #define SRSS_CLK_FLL_CONFIG4_CCO_ENABLE_Pos SRSS_V3_CLK_FLL_CONFIG4_CCO_ENABLE_Pos 680 #define SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV_Msk SRSS_V3_CLK_FLL_CONFIG_FLL_OUTPUT_DIV_Msk 681 #define SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV_Pos SRSS_V3_CLK_FLL_CONFIG_FLL_OUTPUT_DIV_Pos 682 #define SRSS_CLK_FLL_CONFIG_FLL_MULT_Msk SRSS_V3_CLK_FLL_CONFIG_FLL_MULT_Msk 683 #define SRSS_CLK_FLL_CONFIG_FLL_MULT_Pos SRSS_V3_CLK_FLL_CONFIG_FLL_MULT_Pos 684 #define SRSS_CLK_FLL_CONFIG_FLL_MULT_Pos SRSS_V3_CLK_FLL_CONFIG_FLL_MULT_Pos 685 #define SRSS_CLK_FLL_CONFIG_FLL_MULT_Msk SRSS_V3_CLK_FLL_CONFIG_FLL_MULT_Msk 686 #define SRSS_PWR_SSV_CTL_OVDVDDA_VSEL_Msk SRSS_V3_PWR_SSV_CTL_OVDVDDA_VSEL_Msk 687 #define SRSS_PWR_SSV_CTL_OVDVDDA_VSEL_Pos SRSS_V3_PWR_SSV_CTL_OVDVDDA_VSEL_Pos 688 #define SRSS_PWR_SSV_CTL_OVDVDDA_VSEL_Pos SRSS_V3_PWR_SSV_CTL_OVDVDDA_VSEL_Pos 689 #define SRSS_PWR_SSV_CTL_OVDVDDA_VSEL_Msk SRSS_V3_PWR_SSV_CTL_OVDVDDA_VSEL_Msk 690 #define SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV_Msk SRSS_V3_CLK_FLL_CONFIG2_FLL_REF_DIV_Msk 691 #define SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV_Pos SRSS_V3_CLK_FLL_CONFIG2_FLL_REF_DIV_Pos 692 #define SRSS_PWR_SSV_CTL_OVDVDDA_ACTION_Msk SRSS_V3_PWR_SSV_CTL_OVDVDDA_ACTION_Msk 693 #define SRSS_PWR_SSV_CTL_OVDVDDA_ACTION_Pos SRSS_V3_PWR_SSV_CTL_OVDVDDA_ACTION_Pos 694 #define SRSS_CLK_FLL_CONFIG2_LOCK_TOL_Msk SRSS_V3_CLK_FLL_CONFIG2_LOCK_TOL_Msk 695 #define SRSS_CLK_FLL_CONFIG2_LOCK_TOL_Pos SRSS_V3_CLK_FLL_CONFIG2_LOCK_TOL_Pos 696 #define SRSS_PWR_SSV_CTL_BODVDDD_ENABLE_Msk SRSS_V3_PWR_SSV_CTL_BODVDDD_ENABLE_Msk 697 #define SRSS_PWR_SSV_CTL_BODVDDD_ENABLE_Pos SRSS_V3_PWR_SSV_CTL_BODVDDD_ENABLE_Pos 698 #define SRSS_PWR_SSV_CTL_BODVDDA_ENABLE_Msk SRSS_V3_PWR_SSV_CTL_BODVDDA_ENABLE_Msk 699 #define SRSS_PWR_SSV_CTL_BODVDDA_ENABLE_Pos SRSS_V3_PWR_SSV_CTL_BODVDDA_ENABLE_Pos 700 #define SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Msk SRSS_V3_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Msk 701 #define SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Pos SRSS_V3_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Pos 702 #define SRSS_PWR_SSV_CTL_BODVCCD_ENABLE_Msk SRSS_V3_PWR_SSV_CTL_BODVCCD_ENABLE_Msk 703 #define SRSS_PWR_SSV_CTL_BODVCCD_ENABLE_Pos SRSS_V3_PWR_SSV_CTL_BODVCCD_ENABLE_Pos 704 #define SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Msk SRSS_V3_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Msk 705 #define SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Pos SRSS_V3_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Pos 706 #define SRSS_PWR_SSV_CTL_BODVDDD_VSEL_Msk SRSS_V3_PWR_SSV_CTL_BODVDDD_VSEL_Msk 707 #define SRSS_PWR_SSV_CTL_BODVDDD_VSEL_Pos SRSS_V3_PWR_SSV_CTL_BODVDDD_VSEL_Pos 708 #define SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT_Msk SRSS_V3_CLK_FLL_CONFIG3_SETTLING_COUNT_Msk 709 #define SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT_Pos SRSS_V3_CLK_FLL_CONFIG3_SETTLING_COUNT_Pos 710 #define SRSS_PWR_SSV_CTL_BODVDDA_VSEL_Msk SRSS_V3_PWR_SSV_CTL_BODVDDA_VSEL_Msk 711 #define SRSS_PWR_SSV_CTL_BODVDDA_VSEL_Pos SRSS_V3_PWR_SSV_CTL_BODVDDA_VSEL_Pos 712 #define SRSS_CLK_FLL_CONFIG4_CCO_FREQ_Msk SRSS_V3_CLK_FLL_CONFIG4_CCO_FREQ_Msk 713 #define SRSS_CLK_FLL_CONFIG4_CCO_FREQ_Pos SRSS_V3_CLK_FLL_CONFIG4_CCO_FREQ_Pos 714 #define SRSS_PWR_SSV_CTL_BODVDDA_ACTION_Msk SRSS_V3_PWR_SSV_CTL_BODVDDA_ACTION_Msk 715 #define SRSS_PWR_SSV_CTL_BODVDDA_ACTION_Pos SRSS_V3_PWR_SSV_CTL_BODVDDA_ACTION_Pos 716 #define SRSS_CLK_FLL_CONFIG4_CCO_RANGE_Msk SRSS_V3_CLK_FLL_CONFIG4_CCO_RANGE_Msk 717 #define SRSS_CLK_FLL_CONFIG4_CCO_RANGE_Pos SRSS_V3_CLK_FLL_CONFIG4_CCO_RANGE_Pos 718 #define SRSS_PWR_SSV_STATUS_BODVDDD_OK_Msk SRSS_V3_PWR_SSV_STATUS_BODVDDD_OK_Msk 719 #define SRSS_PWR_SSV_STATUS_BODVDDD_OK_Pos SRSS_V3_PWR_SSV_STATUS_BODVDDD_OK_Pos 720 #define SRSS_PWR_SSV_STATUS_BODVDDA_OK_Msk SRSS_V3_PWR_SSV_STATUS_BODVDDA_OK_Msk 721 #define SRSS_PWR_SSV_STATUS_BODVDDA_OK_Pos SRSS_V3_PWR_SSV_STATUS_BODVDDA_OK_Pos 722 #define SRSS_PWR_SSV_STATUS_BODVCCD_OK_Msk SRSS_V3_PWR_SSV_STATUS_BODVCCD_OK_Msk 723 #define SRSS_PWR_SSV_STATUS_BODVCCD_OK_Pos SRSS_V3_PWR_SSV_STATUS_BODVCCD_OK_Pos 724 #define SRSS_CLK_FLL_STATUS_CCO_READY_Msk SRSS_V3_CLK_FLL_STATUS_CCO_READY_Msk 725 #define SRSS_CLK_FLL_STATUS_CCO_READY_Pos SRSS_V3_CLK_FLL_STATUS_CCO_READY_Pos 726 #define SRSS_CLK_PLL_CONFIG_ENABLE_Msk SRSS_V3_CLK_PLL_CONFIG_ENABLE_Msk 727 #define SRSS_CLK_PLL_CONFIG_ENABLE_Pos SRSS_V3_CLK_PLL_CONFIG_ENABLE_Pos 728 #define SRSS_CLK_PLL_STATUS_LOCKED_Msk SRSS_V3_CLK_PLL_STATUS_LOCKED_Msk 729 #define SRSS_CLK_PLL_STATUS_LOCKED_Pos SRSS_V3_CLK_PLL_STATUS_LOCKED_Pos 730 #define SRSS_CLK_PLL_STATUS_UNLOCK_OCCURRED_Msk SRSS_V3_CLK_PLL_STATUS_UNLOCK_OCCURRED_Msk 731 #define SRSS_CLK_PLL_STATUS_UNLOCK_OCCURRED_Pos SRSS_V3_CLK_PLL_STATUS_UNLOCK_OCCURRED_Pos 732 #define SRSS_CLK_PLL_CONFIG_BYPASS_SEL_Msk SRSS_V3_CLK_PLL_CONFIG_BYPASS_SEL_Msk 733 #define SRSS_CLK_PLL_CONFIG_BYPASS_SEL_Pos SRSS_V3_CLK_PLL_CONFIG_BYPASS_SEL_Pos 734 #define SRSS_PWR_SSV_STATUS_OVDVDDD_OK_Msk SRSS_V3_PWR_SSV_STATUS_OVDVDDD_OK_Msk 735 #define SRSS_PWR_SSV_STATUS_OVDVDDD_OK_Pos SRSS_V3_PWR_SSV_STATUS_OVDVDDD_OK_Pos 736 #define SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV_Pos SRSS_V3_CLK_PLL_CONFIG_FEEDBACK_DIV_Pos 737 #define SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV_Msk SRSS_V3_CLK_PLL_CONFIG_FEEDBACK_DIV_Msk 738 #define SRSS_PWR_SSV_STATUS_OVDVDDA_OK_Msk SRSS_V3_PWR_SSV_STATUS_OVDVDDA_OK_Msk 739 #define SRSS_PWR_SSV_STATUS_OVDVDDA_OK_Pos SRSS_V3_PWR_SSV_STATUS_OVDVDDA_OK_Pos 740 #define SRSS_PWR_SSV_STATUS_OVDVDDA_OK_Pos SRSS_V3_PWR_SSV_STATUS_OVDVDDA_OK_Pos 741 #define SRSS_PWR_SSV_STATUS_OVDVDDA_OK_Msk SRSS_V3_PWR_SSV_STATUS_OVDVDDA_OK_Msk 742 #define SRSS_PWR_SSV_STATUS_OVDVCCD_OK_Msk SRSS_V3_PWR_SSV_STATUS_OVDVCCD_OK_Msk 743 #define SRSS_PWR_SSV_STATUS_OVDVCCD_OK_Pos SRSS_V3_PWR_SSV_STATUS_OVDVCCD_OK_Pos 744 #define SRSS_CLK_PLL_CONFIG_REFERENCE_DIV_Pos SRSS_V3_CLK_PLL_CONFIG_REFERENCE_DIV_Pos 745 #define SRSS_CLK_PLL_CONFIG_REFERENCE_DIV_Msk SRSS_V3_CLK_PLL_CONFIG_REFERENCE_DIV_Msk 746 #define SRSS_PWR_CTL2_LINREG_LPMODE_Msk SRSS_V3_PWR_CTL2_LINREG_LPMODE_Msk 747 #define SRSS_PWR_CTL2_LINREG_LPMODE_Pos SRSS_V3_PWR_CTL2_LINREG_LPMODE_Pos 748 #define SRSS_CLK_PLL_CONFIG_OUTPUT_DIV_Pos SRSS_V3_CLK_PLL_CONFIG_OUTPUT_DIV_Pos 749 #define SRSS_CLK_PLL_CONFIG_OUTPUT_DIV_Msk SRSS_V3_CLK_PLL_CONFIG_OUTPUT_DIV_Msk 750 #define SRSS_PWR_CTL2_PORBOD_LPMODE_Msk SRSS_V3_PWR_CTL2_PORBOD_LPMODE_Msk 751 #define SRSS_PWR_CTL2_PORBOD_LPMODE_Pos SRSS_V3_PWR_CTL2_PORBOD_LPMODE_Pos 752 #define SRSS_PWR_CTL2_REFVBUF_DIS_Msk SRSS_V3_PWR_CTL2_REFVBUF_DIS_Msk 753 #define SRSS_PWR_CTL2_REFVBUF_DIS_Pos SRSS_V3_PWR_CTL2_REFVBUF_DIS_Pos 754 #define SRSS_PWR_CTL2_LINREG_OK_Msk SRSS_V3_PWR_CTL2_LINREG_OK_Msk 755 #define SRSS_PWR_CTL2_LINREG_OK_Pos SRSS_V3_PWR_CTL2_LINREG_OK_Pos 756 #define SRSS_CLK_PLL_CONFIG_PLL_LF_MODE_Pos SRSS_V3_CLK_PLL_CONFIG_PLL_LF_MODE_Pos 757 #define SRSS_CLK_PLL_CONFIG_PLL_LF_MODE_Msk SRSS_V3_CLK_PLL_CONFIG_PLL_LF_MODE_Msk 758 #define SRSS_PWR_REGHC_CTL_REGHC_MODE_Msk SRSS_V3_PWR_REGHC_CTL_REGHC_MODE_Msk 759 #define SRSS_PWR_REGHC_CTL_REGHC_MODE_Pos SRSS_V3_PWR_REGHC_CTL_REGHC_MODE_Pos 760 #define SRSS_PWR_REGHC_CTL_REGHC_MODE_Msk SRSS_V3_PWR_REGHC_CTL_REGHC_MODE_Msk 761 #define SRSS_PWR_REGHC_CTL_REGHC_MODE_Pos SRSS_V3_PWR_REGHC_CTL_REGHC_MODE_Pos 762 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_DRV_VOUT_Msk SRSS_V3_PWR_REGHC_CTL_REGHC_PMIC_DRV_VOUT_Msk 763 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_DRV_VOUT_Pos SRSS_V3_PWR_REGHC_CTL_REGHC_PMIC_DRV_VOUT_Pos 764 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_DRV_VOUT_Pos SRSS_V3_PWR_REGHC_CTL_REGHC_PMIC_DRV_VOUT_Pos 765 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_DRV_VOUT_Msk SRSS_V3_PWR_REGHC_CTL_REGHC_PMIC_DRV_VOUT_Msk 766 #define SRSS_PWR_REGHC_CTL_REGHC_VADJ_Msk SRSS_V3_PWR_REGHC_CTL_REGHC_VADJ_Msk 767 #define SRSS_PWR_REGHC_CTL_REGHC_VADJ_Pos SRSS_V3_PWR_REGHC_CTL_REGHC_VADJ_Pos 768 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_USE_LINREG_Msk SRSS_V3_PWR_REGHC_CTL_REGHC_PMIC_USE_LINREG_Msk 769 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_USE_LINREG_Pos SRSS_V3_PWR_REGHC_CTL_REGHC_PMIC_USE_LINREG_Pos 770 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_CTL_OUTEN_Msk SRSS_V3_PWR_REGHC_CTL_REGHC_PMIC_CTL_OUTEN_Msk 771 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_CTL_OUTEN_Pos SRSS_V3_PWR_REGHC_CTL_REGHC_PMIC_CTL_OUTEN_Pos 772 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_CTL_POLARITY_Msk SRSS_V3_PWR_REGHC_CTL_REGHC_PMIC_CTL_POLARITY_Msk 773 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_CTL_POLARITY_Pos SRSS_V3_PWR_REGHC_CTL_REGHC_PMIC_CTL_POLARITY_Pos 774 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_INEN_Msk SRSS_V3_PWR_REGHC_CTL_REGHC_PMIC_STATUS_INEN_Msk 775 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_INEN_Pos SRSS_V3_PWR_REGHC_CTL_REGHC_PMIC_STATUS_INEN_Pos 776 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_POLARITY_Msk SRSS_V3_PWR_REGHC_CTL_REGHC_PMIC_STATUS_POLARITY_Msk 777 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_POLARITY_Pos SRSS_V3_PWR_REGHC_CTL_REGHC_PMIC_STATUS_POLARITY_Pos 778 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_WAIT_Msk SRSS_V3_PWR_REGHC_CTL_REGHC_PMIC_STATUS_WAIT_Msk 779 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_WAIT_Pos SRSS_V3_PWR_REGHC_CTL_REGHC_PMIC_STATUS_WAIT_Pos 780 #define SRSS_PWR_REGHC_CTL_REGHC_CONFIGURED_Msk SRSS_V3_PWR_REGHC_CTL_REGHC_CONFIGURED_Msk 781 #define SRSS_PWR_REGHC_CTL_REGHC_CONFIGURED_Pos SRSS_V3_PWR_REGHC_CTL_REGHC_CONFIGURED_Pos 782 #define SRSS_PWR_REGHC_CTL2_REGHC_EN_Msk SRSS_V3_PWR_REGHC_CTL2_REGHC_EN_Msk 783 #define SRSS_PWR_REGHC_CTL2_REGHC_EN_Pos SRSS_V3_PWR_REGHC_CTL2_REGHC_EN_Pos 784 #define SRSS_PWR_REGHC_CTL2_REGHC_PMIC_STATUS_TIMEOUT_Msk SRSS_V3_PWR_REGHC_CTL2_REGHC_PMIC_STATUS_TIMEOUT_Msk 785 #define SRSS_PWR_REGHC_CTL2_REGHC_PMIC_STATUS_TIMEOUT_Pos SRSS_V3_PWR_REGHC_CTL2_REGHC_PMIC_STATUS_TIMEOUT_Pos 786 #define SRSS_PWR_REGHC_STATUS_REGHC_ENABLED_Msk SRSS_V3_PWR_REGHC_STATUS_REGHC_ENABLED_Msk 787 #define SRSS_PWR_REGHC_STATUS_REGHC_ENABLED_Pos SRSS_V3_PWR_REGHC_STATUS_REGHC_ENABLED_Pos 788 #define SRSS_PWR_REGHC_STATUS_REGHC_PMIC_STATUS_OK_Msk SRSS_V3_PWR_REGHC_STATUS_REGHC_PMIC_STATUS_OK_Msk 789 #define SRSS_PWR_REGHC_STATUS_REGHC_PMIC_STATUS_OK_Pos SRSS_V3_PWR_REGHC_STATUS_REGHC_PMIC_STATUS_OK_Pos 790 #define SRSS_PWR_REGHC_STATUS_REGHC_SEQ_BUSY_Msk SRSS_V3_PWR_REGHC_STATUS_REGHC_SEQ_BUSY_Msk 791 #define SRSS_PWR_REGHC_STATUS_REGHC_SEQ_BUSY_Pos SRSS_V3_PWR_REGHC_STATUS_REGHC_SEQ_BUSY_Pos 792 #define SRSS_PWR_REGHC_CTL4_REGHC_PMIC_VADJ_DIS_Msk SRSS_V3_PWR_REGHC_CTL4_REGHC_PMIC_VADJ_DIS_Msk 793 #define SRSS_PWR_REGHC_CTL4_REGHC_PMIC_VADJ_DIS_Pos SRSS_V3_PWR_REGHC_CTL4_REGHC_PMIC_VADJ_DIS_Pos 794 #define SRSS_PWR_REGHC_CTL4_REGHC_PMIC_DPSLP_Msk SRSS_V3_PWR_REGHC_CTL4_REGHC_PMIC_DPSLP_Msk 795 #define SRSS_PWR_REGHC_CTL4_REGHC_PMIC_DPSLP_Pos SRSS_V3_PWR_REGHC_CTL4_REGHC_PMIC_DPSLP_Pos 796 #define SRSS_PWR_REGHC_STATUS_REGHC_OCD_OK_Msk SRSS_V3_PWR_REGHC_STATUS_REGHC_OCD_OK_Msk 797 #define SRSS_PWR_REGHC_STATUS_REGHC_OCD_OK_Pos SRSS_V3_PWR_REGHC_STATUS_REGHC_OCD_OK_Pos 798 #define SRSS_PWR_REGHC_STATUS_REGHC_CKT_OK_Msk SRSS_V3_PWR_REGHC_STATUS_REGHC_CKT_OK_Msk 799 #define SRSS_PWR_REGHC_STATUS_REGHC_CKT_OK_Pos SRSS_V3_PWR_REGHC_STATUS_REGHC_CKT_OK_Pos 800 801 #define SRSS_CLK_PLL_CONFIG_BYPASS_SEL_Msk SRSS_V3_CLK_PLL_CONFIG_BYPASS_SEL_Msk 802 #define SRSS_CLK_PLL_CONFIG_BYPASS_SEL_Pos SRSS_V3_CLK_PLL_CONFIG_BYPASS_SEL_Pos 803 #define SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE_Msk SRSS_V3_CLK_CAL_CNT1_CAL_COUNTER_DONE_Msk 804 #define SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE_Pos SRSS_V3_CLK_CAL_CNT1_CAL_COUNTER_DONE_Pos 805 #define SRSS_CLK_CAL_CNT1_CAL_COUNTER1_Msk SRSS_V3_CLK_CAL_CNT1_CAL_COUNTER1_Msk 806 #define SRSS_CLK_CAL_CNT1_CAL_COUNTER1_Pos SRSS_V3_CLK_CAL_CNT1_CAL_COUNTER1_Pos 807 #define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL0_Pos SRSS_V3_CLK_OUTPUT_SLOW_SLOW_SEL0_Pos 808 #define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL0_Msk SRSS_V3_CLK_OUTPUT_SLOW_SLOW_SEL0_Msk 809 #define SRSS_CLK_OUTPUT_FAST_FAST_SEL0_Pos SRSS_V3_CLK_OUTPUT_FAST_FAST_SEL0_Pos 810 #define SRSS_CLK_OUTPUT_FAST_FAST_SEL0_Msk SRSS_V3_CLK_OUTPUT_FAST_FAST_SEL0_Msk 811 #define SRSS_CLK_OUTPUT_FAST_PATH_SEL0_Pos SRSS_V3_CLK_OUTPUT_FAST_PATH_SEL0_Pos 812 #define SRSS_CLK_OUTPUT_FAST_PATH_SEL0_Msk SRSS_V3_CLK_OUTPUT_FAST_PATH_SEL0_Msk 813 #define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL0_Pos SRSS_V3_CLK_OUTPUT_FAST_HFCLK_SEL0_Pos 814 #define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL0_Msk SRSS_V3_CLK_OUTPUT_FAST_HFCLK_SEL0_Msk 815 #define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL1_Pos SRSS_V3_CLK_OUTPUT_SLOW_SLOW_SEL1_Pos 816 #define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL1_Msk SRSS_V3_CLK_OUTPUT_SLOW_SLOW_SEL1_Msk 817 #define SRSS_CLK_OUTPUT_FAST_FAST_SEL1_Pos SRSS_V3_CLK_OUTPUT_FAST_FAST_SEL1_Pos 818 #define SRSS_CLK_OUTPUT_FAST_FAST_SEL1_Msk SRSS_V3_CLK_OUTPUT_FAST_FAST_SEL1_Msk 819 #define SRSS_CLK_OUTPUT_FAST_PATH_SEL1_Pos SRSS_V3_CLK_OUTPUT_FAST_PATH_SEL1_Pos 820 #define SRSS_CLK_OUTPUT_FAST_PATH_SEL1_Msk SRSS_V3_CLK_OUTPUT_FAST_PATH_SEL1_Msk 821 #define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL1_Pos SRSS_V3_CLK_OUTPUT_FAST_HFCLK_SEL1_Pos 822 #define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL1_Msk SRSS_V3_CLK_OUTPUT_FAST_HFCLK_SEL1_Msk 823 #define SRSS_CLK_CAL_CNT2_CAL_COUNTER2_Msk SRSS_V3_CLK_CAL_CNT2_CAL_COUNTER2_Msk 824 #define SRSS_CLK_CAL_CNT2_CAL_COUNTER2_Pos SRSS_V3_CLK_CAL_CNT2_CAL_COUNTER2_Pos 825 826 827 828 #define WDT_CTL_ENABLED_Pos WDT_V3_CTL_ENABLED_Pos 829 #define WDT_CTL_ENABLED_Msk WDT_V3_CTL_ENABLED_Msk 830 #define WDT_CTL_ENABLE_Pos WDT_V3_CTL_ENABLE_Pos 831 #define WDT_CTL_ENABLE_Msk WDT_V3_CTL_ENABLE_Msk 832 #define WDT_CNT_CNT_Msk WDT_V3_CNT_CNT_Msk 833 #define WDT_CNT_CNT_Pos WDT_V3_CNT_CNT_Pos 834 #define WDT_INTR_MASK_WDT_Msk WDT_V3_INTR_MASK_WDT_Msk 835 #define WDT_INTR_WDT_Pos WDT_V3_INTR_WDT_Pos 836 #define WDT_INTR_WDT_Msk WDT_V3_INTR_WDT_Msk 837 #define WDT_LOCK_WDT_LOCK_Pos WDT_V3_LOCK_WDT_LOCK_Pos 838 #define WDT_LOCK_WDT_LOCK_Msk WDT_V3_LOCK_WDT_LOCK_Msk 839 #define WDT_CONFIG_LOWER_ACTION_Msk WDT_V3_CONFIG_LOWER_ACTION_Msk 840 #define WDT_CONFIG_LOWER_ACTION_Pos WDT_V3_CONFIG_LOWER_ACTION_Pos 841 #define WDT_CONFIG_UPPER_ACTION_Msk WDT_V3_CONFIG_UPPER_ACTION_Msk 842 #define WDT_CONFIG_UPPER_ACTION_Pos WDT_V3_CONFIG_UPPER_ACTION_Pos 843 #define WDT_CONFIG_WARN_ACTION_Msk WDT_V3_CONFIG_WARN_ACTION_Msk 844 #define WDT_CONFIG_WARN_ACTION_Pos WDT_V3_CONFIG_WARN_ACTION_Pos 845 #define WDT_CONFIG_AUTO_SERVICE_Msk WDT_V3_CONFIG_AUTO_SERVICE_Msk 846 #define WDT_CONFIG_AUTO_SERVICE_Pos WDT_V3_CONFIG_AUTO_SERVICE_Pos 847 #define WDT_CONFIG_DPSLP_PAUSE_Msk WDT_V3_CONFIG_DPSLP_PAUSE_Msk 848 #define WDT_CONFIG_DPSLP_PAUSE_Pos WDT_V3_CONFIG_DPSLP_PAUSE_Pos 849 #define WDT_CONFIG_HIB_PAUSE_Msk WDT_V3_CONFIG_HIB_PAUSE_Msk 850 #define WDT_CONFIG_HIB_PAUSE_Pos WDT_V3_CONFIG_HIB_PAUSE_Pos 851 #define WDT_CONFIG_DEBUG_RUN_Msk WDT_V3_CONFIG_DEBUG_RUN_Msk 852 #define WDT_CONFIG_DEBUG_RUN_Pos WDT_V3_CONFIG_DEBUG_RUN_Pos 853 #define WDT_SERVICE_SERVICE_Msk WDT_V3_SERVICE_SERVICE_Msk 854 #define WDT_SERVICE_SERVICE_Pos WDT_V3_SERVICE_SERVICE_Pos 855 856 857 #define MCWDT_CTR_CTL_ENABLE_Msk MCWDT_CTR_V3_CTL_ENABLE_Msk 858 #define MCWDT_CTR_CTL_ENABLE_Pos MCWDT_CTR_V3_CTL_ENABLE_Pos 859 #define MCWDT_CTR2_CTL_ENABLE_Msk MCWDT_V3_CTR2_CTL_ENABLE_Msk 860 #define MCWDT_CTR2_CTL_ENABLE_Pos MCWDT_V3_CTR2_CTL_ENABLE_Pos 861 #define MCWDT_LOCK_MCWDT_LOCK_Msk MCWDT_V3_LOCK_MCWDT_LOCK_Msk 862 #define MCWDT_LOCK_MCWDT_LOCK_Pos MCWDT_V3_LOCK_MCWDT_LOCK_Pos 863 #define MCWDT_CTR2_CONFIG_BITS_Msk MCWDT_V3_CTR2_CONFIG_BITS_Msk 864 #define MCWDT_CTR2_CONFIG_BITS_Pos MCWDT_V3_CTR2_CONFIG_BITS_Pos 865 #define MCWDT_CTR_CNT_CNT_Msk MCWDT_CTR_V3_CNT_CNT_Msk 866 #define MCWDT_CTR_CNT_CNT_Pos MCWDT_CTR_V3_CNT_CNT_Pos 867 #define MCWDT_CTR2_CNT_CNT2_Msk MCWDT_V3_CTR2_CNT_CNT2_Msk 868 #define MCWDT_CTR2_CNT_CNT2_Pos MCWDT_V3_CTR2_CNT_CNT2_Pos 869 #define MCWDT_SERVICE_CTR0_SERVICE_Msk MCWDT_V3_SERVICE_CTR0_SERVICE_Msk 870 #define MCWDT_SERVICE_CTR0_SERVICE_Pos MCWDT_V3_SERVICE_CTR0_SERVICE_Pos 871 #define MCWDT_SERVICE_CTR1_SERVICE_Msk MCWDT_V3_SERVICE_CTR1_SERVICE_Msk 872 #define MCWDT_SERVICE_CTR1_SERVICE_Pos MCWDT_V3_SERVICE_CTR1_SERVICE_Pos 873 #define MCWDT_CTR_CONFIG_LOWER_ACTION_Pos MCWDT_CTR_V3_CONFIG_LOWER_ACTION_Pos 874 #define MCWDT_CTR_CONFIG_LOWER_ACTION_Msk MCWDT_CTR_V3_CONFIG_LOWER_ACTION_Msk 875 #define MCWDT_CTR_CONFIG_UPPER_ACTION_Pos MCWDT_CTR_V3_CONFIG_UPPER_ACTION_Pos 876 #define MCWDT_CTR_CONFIG_UPPER_ACTION_Msk MCWDT_CTR_V3_CONFIG_UPPER_ACTION_Msk 877 #define MCWDT_CTR_CONFIG_WARN_ACTION_Pos MCWDT_CTR_V3_CONFIG_WARN_ACTION_Pos 878 #define MCWDT_CTR_CONFIG_WARN_ACTION_Msk MCWDT_CTR_V3_CONFIG_WARN_ACTION_Msk 879 #define MCWDT_CTR_CONFIG_AUTO_SERVICE_Pos MCWDT_CTR_V3_CONFIG_AUTO_SERVICE_Pos 880 #define MCWDT_CTR_CONFIG_AUTO_SERVICE_Msk MCWDT_CTR_V3_CONFIG_AUTO_SERVICE_Msk 881 #define MCWDT_CTR_CONFIG_SLEEPDEEP_PAUSE_Pos MCWDT_CTR_V3_CONFIG_SLEEPDEEP_PAUSE_Pos 882 #define MCWDT_CTR_CONFIG_SLEEPDEEP_PAUSE_Msk MCWDT_CTR_V3_CONFIG_SLEEPDEEP_PAUSE_Msk 883 #define MCWDT_CTR_CONFIG_DEBUG_RUN_Pos MCWDT_CTR_V3_CONFIG_DEBUG_RUN_Pos 884 #define MCWDT_CTR_CONFIG_DEBUG_RUN_Msk MCWDT_CTR_V3_CONFIG_DEBUG_RUN_Msk 885 #define MCWDT_CTR2_CONFIG_ACTION_Pos MCWDT_V3_CTR2_CONFIG_ACTION_Pos 886 #define MCWDT_CTR2_CONFIG_ACTION_Msk MCWDT_V3_CTR2_CONFIG_ACTION_Msk 887 #define MCWDT_CTR2_CONFIG_SLEEPDEEP_PAUSE_Pos MCWDT_V3_CTR2_CONFIG_SLEEPDEEP_PAUSE_Pos 888 #define MCWDT_CTR2_CONFIG_SLEEPDEEP_PAUSE_Msk MCWDT_V3_CTR2_CONFIG_SLEEPDEEP_PAUSE_Msk 889 #define MCWDT_CTR2_CONFIG_DEBUG_RUN_Pos MCWDT_V3_CTR2_CONFIG_DEBUG_RUN_Pos 890 #define MCWDT_CTR2_CONFIG_DEBUG_RUN_Msk MCWDT_V3_CTR2_CONFIG_DEBUG_RUN_Msk 891 892 #define MCWDT_CPU_SELECT_CPU_SEL_Msk MCWDT_V3_CPU_SELECT_CPU_SEL_Msk 893 #define MCWDT_CPU_SELECT_CPU_SEL_Pos MCWDT_V3_CPU_SELECT_CPU_SEL_Pos 894 #define MCWDT_CTR_LOWER_LIMIT_LOWER_LIMIT_Msk MCWDT_CTR_V3_LOWER_LIMIT_LOWER_LIMIT_Msk 895 #define MCWDT_CTR_LOWER_LIMIT_LOWER_LIMIT_Pos MCWDT_CTR_V3_LOWER_LIMIT_LOWER_LIMIT_Pos 896 #define MCWDT_CTR_UPPER_LIMIT_UPPER_LIMIT_Msk MCWDT_CTR_V3_UPPER_LIMIT_UPPER_LIMIT_Msk 897 #define MCWDT_CTR_UPPER_LIMIT_UPPER_LIMIT_Pos MCWDT_CTR_V3_UPPER_LIMIT_UPPER_LIMIT_Pos 898 #define MCWDT_CTR_WARN_LIMIT_WARN_LIMIT_Msk MCWDT_CTR_V3_WARN_LIMIT_WARN_LIMIT_Msk 899 #define MCWDT_CTR_WARN_LIMIT_WARN_LIMIT_Pos MCWDT_CTR_V3_WARN_LIMIT_WARN_LIMIT_Pos 900 901 #define MCWDT_INTR_MASKED_CTR0_INT_Msk MCWDT_V3_INTR_MASKED_CTR0_INT_Msk 902 #define MCWDT_INTR_MASKED_CTR1_INT_Msk MCWDT_V3_INTR_MASKED_CTR1_INT_Msk 903 #define MCWDT_INTR_MASKED_CTR2_INT_Msk MCWDT_V3_INTR_MASKED_CTR2_INT_Msk 904 905 /******************************************************************************* 906 * BACKUP 907 *******************************************************************************/ 908 /* BACKUP.CTL */ 909 #define BACKUP_CTL_WCO_EN_Pos BACKUP_V3_CTL_WCO_EN_Pos 910 #define BACKUP_CTL_WCO_EN_Msk BACKUP_V3_CTL_WCO_EN_Msk 911 #define BACKUP_CTL_CLK_SEL_Pos BACKUP_V3_CTL_CLK_SEL_Pos 912 #define BACKUP_CTL_CLK_SEL_Msk BACKUP_V3_CTL_CLK_SEL_Msk 913 #define BACKUP_CTL_PRESCALER_Pos BACKUP_V3_CTL_PRESCALER_Pos 914 #define BACKUP_CTL_PRESCALER_Msk BACKUP_V3_CTL_PRESCALER_Msk 915 #define BACKUP_CTL_WCO_BYPASS_Pos BACKUP_V3_CTL_WCO_BYPASS_Pos 916 #define BACKUP_CTL_WCO_BYPASS_Msk BACKUP_V3_CTL_WCO_BYPASS_Msk 917 #define BACKUP_CTL_VDDBAK_CTL_Pos BACKUP_V3_CTL_VDDBAK_CTL_Pos 918 #define BACKUP_CTL_VDDBAK_CTL_Msk BACKUP_V3_CTL_VDDBAK_CTL_Msk 919 #define BACKUP_CTL_VBACKUP_MEAS_Pos BACKUP_V3_CTL_VBACKUP_MEAS_Pos 920 #define BACKUP_CTL_VBACKUP_MEAS_Msk BACKUP_V3_CTL_VBACKUP_MEAS_Msk 921 #define BACKUP_CTL_EN_CHARGE_KEY_Pos BACKUP_V3_CTL_EN_CHARGE_KEY_Pos 922 #define BACKUP_CTL_EN_CHARGE_KEY_Msk BACKUP_V3_CTL_EN_CHARGE_KEY_Msk 923 /* BACKUP.RTC_RW */ 924 #define BACKUP_RTC_RW_READ_Pos BACKUP_V3_RTC_RW_READ_Pos 925 #define BACKUP_RTC_RW_READ_Msk BACKUP_V3_RTC_RW_READ_Msk 926 #define BACKUP_RTC_RW_WRITE_Pos BACKUP_V3_RTC_RW_WRITE_Pos 927 #define BACKUP_RTC_RW_WRITE_Msk BACKUP_V3_RTC_RW_WRITE_Msk 928 /* BACKUP.CAL_CTL */ 929 #define BACKUP_CAL_CTL_CALIB_VAL_Pos BACKUP_V3_CAL_CTL_CALIB_VAL_Pos 930 #define BACKUP_CAL_CTL_CALIB_VAL_Msk BACKUP_V3_CAL_CTL_CALIB_VAL_Msk 931 #define BACKUP_CAL_CTL_CALIB_SIGN_Pos BACKUP_V3_CAL_CTL_CALIB_SIGN_Pos 932 #define BACKUP_CAL_CTL_CALIB_SIGN_Msk BACKUP_V3_CAL_CTL_CALIB_SIGN_Msk 933 #define BACKUP_CAL_CTL_CAL_SEL_Pos BACKUP_V3_CAL_CTL_CAL_SEL_Pos 934 #define BACKUP_CAL_CTL_CAL_SEL_Msk BACKUP_V3_CAL_CTL_CAL_SEL_Msk 935 #define BACKUP_CAL_CTL_CAL_OUT_Pos BACKUP_V3_CAL_CTL_CAL_OUT_Pos 936 #define BACKUP_CAL_CTL_CAL_OUT_Msk BACKUP_V3_CAL_CTL_CAL_OUT_Msk 937 /* BACKUP.STATUS */ 938 #define BACKUP_STATUS_RTC_BUSY_Pos BACKUP_V3_STATUS_RTC_BUSY_Pos 939 #define BACKUP_STATUS_RTC_BUSY_Msk BACKUP_V3_STATUS_RTC_BUSY_Msk 940 #define BACKUP_STATUS_WCO_OK_Pos BACKUP_V3_STATUS_WCO_OK_Pos 941 #define BACKUP_STATUS_WCO_OK_Msk BACKUP_V3_STATUS_WCO_OK_Msk 942 /* BACKUP.RTC_TIME */ 943 #define BACKUP_RTC_TIME_RTC_SEC_Pos BACKUP_V3_RTC_TIME_RTC_SEC_Pos 944 #define BACKUP_RTC_TIME_RTC_SEC_Msk BACKUP_V3_RTC_TIME_RTC_SEC_Msk 945 #define BACKUP_RTC_TIME_RTC_MIN_Pos BACKUP_V3_RTC_TIME_RTC_MIN_Pos 946 #define BACKUP_RTC_TIME_RTC_MIN_Msk BACKUP_V3_RTC_TIME_RTC_MIN_Msk 947 #define BACKUP_RTC_TIME_RTC_HOUR_Pos BACKUP_V3_RTC_TIME_RTC_HOUR_Pos 948 #define BACKUP_RTC_TIME_RTC_HOUR_Msk BACKUP_V3_RTC_TIME_RTC_HOUR_Msk 949 #define BACKUP_RTC_TIME_CTRL_12HR_Pos BACKUP_V3_RTC_TIME_CTRL_12HR_Pos 950 #define BACKUP_RTC_TIME_CTRL_12HR_Msk BACKUP_V3_RTC_TIME_CTRL_12HR_Msk 951 #define BACKUP_RTC_TIME_RTC_DAY_Pos BACKUP_V3_RTC_TIME_RTC_DAY_Pos 952 #define BACKUP_RTC_TIME_RTC_DAY_Msk BACKUP_V3_RTC_TIME_RTC_DAY_Msk 953 /* BACKUP.RTC_DATE */ 954 #define BACKUP_RTC_DATE_RTC_DATE_Pos BACKUP_V3_RTC_DATE_RTC_DATE_Pos 955 #define BACKUP_RTC_DATE_RTC_DATE_Msk BACKUP_V3_RTC_DATE_RTC_DATE_Msk 956 #define BACKUP_RTC_DATE_RTC_MON_Pos BACKUP_V3_RTC_DATE_RTC_MON_Pos 957 #define BACKUP_RTC_DATE_RTC_MON_Msk BACKUP_V3_RTC_DATE_RTC_MON_Msk 958 #define BACKUP_RTC_DATE_RTC_YEAR_Pos BACKUP_V3_RTC_DATE_RTC_YEAR_Pos 959 #define BACKUP_RTC_DATE_RTC_YEAR_Msk BACKUP_V3_RTC_DATE_RTC_YEAR_Msk 960 /* BACKUP.ALM1_TIME */ 961 #define BACKUP_ALM1_TIME_ALM_SEC_Pos BACKUP_V3_ALM1_TIME_ALM_SEC_Pos 962 #define BACKUP_ALM1_TIME_ALM_SEC_Msk BACKUP_V3_ALM1_TIME_ALM_SEC_Msk 963 #define BACKUP_ALM1_TIME_ALM_SEC_EN_Pos BACKUP_V3_ALM1_TIME_ALM_SEC_EN_Pos 964 #define BACKUP_ALM1_TIME_ALM_SEC_EN_Msk BACKUP_V3_ALM1_TIME_ALM_SEC_EN_Msk 965 #define BACKUP_ALM1_TIME_ALM_MIN_Pos BACKUP_V3_ALM1_TIME_ALM_MIN_Pos 966 #define BACKUP_ALM1_TIME_ALM_MIN_Msk BACKUP_V3_ALM1_TIME_ALM_MIN_Msk 967 #define BACKUP_ALM1_TIME_ALM_MIN_EN_Pos BACKUP_V3_ALM1_TIME_ALM_MIN_EN_Pos 968 #define BACKUP_ALM1_TIME_ALM_MIN_EN_Msk BACKUP_V3_ALM1_TIME_ALM_MIN_EN_Msk 969 #define BACKUP_ALM1_TIME_ALM_HOUR_Pos BACKUP_V3_ALM1_TIME_ALM_HOUR_Pos 970 #define BACKUP_ALM1_TIME_ALM_HOUR_Msk BACKUP_V3_ALM1_TIME_ALM_HOUR_Msk 971 #define BACKUP_ALM1_TIME_ALM_HOUR_EN_Pos BACKUP_V3_ALM1_TIME_ALM_HOUR_EN_Pos 972 #define BACKUP_ALM1_TIME_ALM_HOUR_EN_Msk BACKUP_V3_ALM1_TIME_ALM_HOUR_EN_Msk 973 #define BACKUP_ALM1_TIME_ALM_DAY_Pos BACKUP_V3_ALM1_TIME_ALM_DAY_Pos 974 #define BACKUP_ALM1_TIME_ALM_DAY_Msk BACKUP_V3_ALM1_TIME_ALM_DAY_Msk 975 #define BACKUP_ALM1_TIME_ALM_DAY_EN_Pos BACKUP_V3_ALM1_TIME_ALM_DAY_EN_Pos 976 #define BACKUP_ALM1_TIME_ALM_DAY_EN_Msk BACKUP_V3_ALM1_TIME_ALM_DAY_EN_Msk 977 /* BACKUP.ALM1_DATE */ 978 #define BACKUP_ALM1_DATE_ALM_DATE_Pos BACKUP_V3_ALM1_DATE_ALM_DATE_Pos 979 #define BACKUP_ALM1_DATE_ALM_DATE_Msk BACKUP_V3_ALM1_DATE_ALM_DATE_Msk 980 #define BACKUP_ALM1_DATE_ALM_DATE_EN_Pos BACKUP_V3_ALM1_DATE_ALM_DATE_EN_Pos 981 #define BACKUP_ALM1_DATE_ALM_DATE_EN_Msk BACKUP_V3_ALM1_DATE_ALM_DATE_EN_Msk 982 #define BACKUP_ALM1_DATE_ALM_MON_Pos BACKUP_V3_ALM1_DATE_ALM_MON_Pos 983 #define BACKUP_ALM1_DATE_ALM_MON_Msk BACKUP_V3_ALM1_DATE_ALM_MON_Msk 984 #define BACKUP_ALM1_DATE_ALM_MON_EN_Pos BACKUP_V3_ALM1_DATE_ALM_MON_EN_Pos 985 #define BACKUP_ALM1_DATE_ALM_MON_EN_Msk BACKUP_V3_ALM1_DATE_ALM_MON_EN_Msk 986 #define BACKUP_ALM1_DATE_ALM_EN_Pos BACKUP_V3_ALM1_DATE_ALM_EN_Pos 987 #define BACKUP_ALM1_DATE_ALM_EN_Msk BACKUP_V3_ALM1_DATE_ALM_EN_Msk 988 /* BACKUP.ALM2_TIME */ 989 #define BACKUP_ALM2_TIME_ALM_SEC_Pos BACKUP_V3_ALM2_TIME_ALM_SEC_Pos 990 #define BACKUP_ALM2_TIME_ALM_SEC_Msk BACKUP_V3_ALM2_TIME_ALM_SEC_Msk 991 #define BACKUP_ALM2_TIME_ALM_SEC_EN_Pos BACKUP_V3_ALM2_TIME_ALM_SEC_EN_Pos 992 #define BACKUP_ALM2_TIME_ALM_SEC_EN_Msk BACKUP_V3_ALM2_TIME_ALM_SEC_EN_Msk 993 #define BACKUP_ALM2_TIME_ALM_MIN_Pos BACKUP_V3_ALM2_TIME_ALM_MIN_Pos 994 #define BACKUP_ALM2_TIME_ALM_MIN_Msk BACKUP_V3_ALM2_TIME_ALM_MIN_Msk 995 #define BACKUP_ALM2_TIME_ALM_MIN_EN_Pos BACKUP_V3_ALM2_TIME_ALM_MIN_EN_Pos 996 #define BACKUP_ALM2_TIME_ALM_MIN_EN_Msk BACKUP_V3_ALM2_TIME_ALM_MIN_EN_Msk 997 #define BACKUP_ALM2_TIME_ALM_HOUR_Pos BACKUP_V3_ALM2_TIME_ALM_HOUR_Pos 998 #define BACKUP_ALM2_TIME_ALM_HOUR_Msk BACKUP_V3_ALM2_TIME_ALM_HOUR_Msk 999 #define BACKUP_ALM2_TIME_ALM_HOUR_EN_Pos BACKUP_V3_ALM2_TIME_ALM_HOUR_EN_Pos 1000 #define BACKUP_ALM2_TIME_ALM_HOUR_EN_Msk BACKUP_V3_ALM2_TIME_ALM_HOUR_EN_Msk 1001 #define BACKUP_ALM2_TIME_ALM_DAY_Pos BACKUP_V3_ALM2_TIME_ALM_DAY_Pos 1002 #define BACKUP_ALM2_TIME_ALM_DAY_Msk BACKUP_V3_ALM2_TIME_ALM_DAY_Msk 1003 #define BACKUP_ALM2_TIME_ALM_DAY_EN_Pos BACKUP_V3_ALM2_TIME_ALM_DAY_EN_Pos 1004 #define BACKUP_ALM2_TIME_ALM_DAY_EN_Msk BACKUP_V3_ALM2_TIME_ALM_DAY_EN_Msk 1005 /* BACKUP.ALM2_DATE */ 1006 #define BACKUP_ALM2_DATE_ALM_DATE_Pos BACKUP_V3_ALM2_DATE_ALM_DATE_Pos 1007 #define BACKUP_ALM2_DATE_ALM_DATE_Msk BACKUP_V3_ALM2_DATE_ALM_DATE_Msk 1008 #define BACKUP_ALM2_DATE_ALM_DATE_EN_Pos BACKUP_V3_ALM2_DATE_ALM_DATE_EN_Pos 1009 #define BACKUP_ALM2_DATE_ALM_DATE_EN_Msk BACKUP_V3_ALM2_DATE_ALM_DATE_EN_Msk 1010 #define BACKUP_ALM2_DATE_ALM_MON_Pos BACKUP_V3_ALM2_DATE_ALM_MON_Pos 1011 #define BACKUP_ALM2_DATE_ALM_MON_Msk BACKUP_V3_ALM2_DATE_ALM_MON_Msk 1012 #define BACKUP_ALM2_DATE_ALM_MON_EN_Pos BACKUP_V3_ALM2_DATE_ALM_MON_EN_Pos 1013 #define BACKUP_ALM2_DATE_ALM_MON_EN_Msk BACKUP_V3_ALM2_DATE_ALM_MON_EN_Msk 1014 #define BACKUP_ALM2_DATE_ALM_EN_Pos BACKUP_V3_ALM2_DATE_ALM_EN_Pos 1015 #define BACKUP_ALM2_DATE_ALM_EN_Msk BACKUP_V3_ALM2_DATE_ALM_EN_Msk 1016 /* BACKUP.INTR */ 1017 #define BACKUP_INTR_ALARM1_Pos BACKUP_V3_INTR_ALARM1_Pos 1018 #define BACKUP_INTR_ALARM1_Msk BACKUP_V3_INTR_ALARM1_Msk 1019 #define BACKUP_INTR_ALARM2_Pos BACKUP_V3_INTR_ALARM2_Pos 1020 #define BACKUP_INTR_ALARM2_Msk BACKUP_V3_INTR_ALARM2_Msk 1021 #define BACKUP_INTR_CENTURY_Pos BACKUP_V3_INTR_CENTURY_Pos 1022 #define BACKUP_INTR_CENTURY_Msk BACKUP_V3_INTR_CENTURY_Msk 1023 /* BACKUP.INTR_SET */ 1024 #define BACKUP_INTR_SET_ALARM1_Pos BACKUP_V3_INTR_SET_ALARM1_Pos 1025 #define BACKUP_INTR_SET_ALARM1_Msk BACKUP_V3_INTR_SET_ALARM1_Msk 1026 #define BACKUP_INTR_SET_ALARM2_Pos BACKUP_V3_INTR_SET_ALARM2_Pos 1027 #define BACKUP_INTR_SET_ALARM2_Msk BACKUP_V3_INTR_SET_ALARM2_Msk 1028 #define BACKUP_INTR_SET_CENTURY_Pos BACKUP_V3_INTR_SET_CENTURY_Pos 1029 #define BACKUP_INTR_SET_CENTURY_Msk BACKUP_V3_INTR_SET_CENTURY_Msk 1030 /* BACKUP.INTR_MASK */ 1031 #define BACKUP_INTR_MASK_ALARM1_Pos BACKUP_V3_INTR_MASK_ALARM1_Pos 1032 #define BACKUP_INTR_MASK_ALARM1_Msk BACKUP_V3_INTR_MASK_ALARM1_Msk 1033 #define BACKUP_INTR_MASK_ALARM2_Pos BACKUP_V3_INTR_MASK_ALARM2_Pos 1034 #define BACKUP_INTR_MASK_ALARM2_Msk BACKUP_V3_INTR_MASK_ALARM2_Msk 1035 #define BACKUP_INTR_MASK_CENTURY_Pos BACKUP_V3_INTR_MASK_CENTURY_Pos 1036 #define BACKUP_INTR_MASK_CENTURY_Msk BACKUP_V3_INTR_MASK_CENTURY_Msk 1037 /* BACKUP.INTR_MASKED */ 1038 #define BACKUP_INTR_MASKED_ALARM1_Pos BACKUP_V3_INTR_MASKED_ALARM1_Pos 1039 #define BACKUP_INTR_MASKED_ALARM1_Msk BACKUP_V3_INTR_MASKED_ALARM1_Msk 1040 #define BACKUP_INTR_MASKED_ALARM2_Pos BACKUP_V3_INTR_MASKED_ALARM2_Pos 1041 #define BACKUP_INTR_MASKED_ALARM2_Msk BACKUP_V3_INTR_MASKED_ALARM2_Msk 1042 #define BACKUP_INTR_MASKED_CENTURY_Pos BACKUP_V3_INTR_MASKED_CENTURY_Pos 1043 #define BACKUP_INTR_MASKED_CENTURY_Msk BACKUP_V3_INTR_MASKED_CENTURY_Msk 1044 /* BACKUP.PMIC_CTL */ 1045 #define BACKUP_PMIC_CTL_UNLOCK_Pos BACKUP_V3_PMIC_CTL_UNLOCK_Pos 1046 #define BACKUP_PMIC_CTL_UNLOCK_Msk BACKUP_V3_PMIC_CTL_UNLOCK_Msk 1047 #define BACKUP_PMIC_CTL_POLARITY_Pos BACKUP_V3_PMIC_CTL_POLARITY_Pos 1048 #define BACKUP_PMIC_CTL_POLARITY_Msk BACKUP_V3_PMIC_CTL_POLARITY_Msk 1049 #define BACKUP_PMIC_CTL_PMIC_EN_OUTEN_Pos BACKUP_V3_PMIC_CTL_PMIC_EN_OUTEN_Pos 1050 #define BACKUP_PMIC_CTL_PMIC_EN_OUTEN_Msk BACKUP_V3_PMIC_CTL_PMIC_EN_OUTEN_Msk 1051 #define BACKUP_PMIC_CTL_PMIC_ALWAYSEN_Pos BACKUP_V3_PMIC_CTL_PMIC_ALWAYSEN_Pos 1052 #define BACKUP_PMIC_CTL_PMIC_ALWAYSEN_Msk BACKUP_V3_PMIC_CTL_PMIC_ALWAYSEN_Msk 1053 #define BACKUP_PMIC_CTL_PMIC_EN_Pos BACKUP_V3_PMIC_CTL_PMIC_EN_Pos 1054 #define BACKUP_PMIC_CTL_PMIC_EN_Msk BACKUP_V3_PMIC_CTL_PMIC_EN_Msk 1055 /* BACKUP.RESET */ 1056 #define BACKUP_RESET_RESET_Pos BACKUP_V3_RESET_RESET_Pos 1057 #define BACKUP_RESET_RESET_Msk BACKUP_V3_RESET_RESET_Msk 1058 /* BACKUP.LPECO_CTL */ 1059 #define BACKUP_LPECO_CTL_LPECO_CRANGE_Pos BACKUP_V3_LPECO_CTL_LPECO_CRANGE_Pos 1060 #define BACKUP_LPECO_CTL_LPECO_CRANGE_Msk BACKUP_V3_LPECO_CTL_LPECO_CRANGE_Msk 1061 #define BACKUP_LPECO_CTL_LPECO_FRANGE_Pos BACKUP_V3_LPECO_CTL_LPECO_FRANGE_Pos 1062 #define BACKUP_LPECO_CTL_LPECO_FRANGE_Msk BACKUP_V3_LPECO_CTL_LPECO_FRANGE_Msk 1063 #define BACKUP_LPECO_CTL_LPECO_AMP_SEL_Pos BACKUP_V3_LPECO_CTL_LPECO_AMP_SEL_Pos 1064 #define BACKUP_LPECO_CTL_LPECO_AMP_SEL_Msk BACKUP_V3_LPECO_CTL_LPECO_AMP_SEL_Msk 1065 #define BACKUP_LPECO_CTL_LPECO_DIV_ENABLE_Pos BACKUP_V3_LPECO_CTL_LPECO_DIV_ENABLE_Pos 1066 #define BACKUP_LPECO_CTL_LPECO_DIV_ENABLE_Msk BACKUP_V3_LPECO_CTL_LPECO_DIV_ENABLE_Msk 1067 #define BACKUP_LPECO_CTL_LPECO_AMPDET_EN_Pos BACKUP_V3_LPECO_CTL_LPECO_AMPDET_EN_Pos 1068 #define BACKUP_LPECO_CTL_LPECO_AMPDET_EN_Msk BACKUP_V3_LPECO_CTL_LPECO_AMPDET_EN_Msk 1069 #define BACKUP_LPECO_CTL_LPECO_EN_Pos BACKUP_V3_LPECO_CTL_LPECO_EN_Pos 1070 #define BACKUP_LPECO_CTL_LPECO_EN_Msk BACKUP_V3_LPECO_CTL_LPECO_EN_Msk 1071 /* BACKUP.LPECO_PRESCALE */ 1072 #define BACKUP_LPECO_PRESCALE_LPECO_DIV_ENABLED_Pos BACKUP_V3_LPECO_PRESCALE_LPECO_DIV_ENABLED_Pos 1073 #define BACKUP_LPECO_PRESCALE_LPECO_DIV_ENABLED_Msk BACKUP_V3_LPECO_PRESCALE_LPECO_DIV_ENABLED_Msk 1074 #define BACKUP_LPECO_PRESCALE_LPECO_FRAC_DIV_Pos BACKUP_V3_LPECO_PRESCALE_LPECO_FRAC_DIV_Pos 1075 #define BACKUP_LPECO_PRESCALE_LPECO_FRAC_DIV_Msk BACKUP_V3_LPECO_PRESCALE_LPECO_FRAC_DIV_Msk 1076 #define BACKUP_LPECO_PRESCALE_LPECO_INT_DIV_Pos BACKUP_V3_LPECO_PRESCALE_LPECO_INT_DIV_Pos 1077 #define BACKUP_LPECO_PRESCALE_LPECO_INT_DIV_Msk BACKUP_V3_LPECO_PRESCALE_LPECO_INT_DIV_Msk 1078 /* BACKUP.LPECO_STATUS */ 1079 #define BACKUP_LPECO_STATUS_LPECO_AMPDET_OK_Pos BACKUP_V3_LPECO_STATUS_LPECO_AMPDET_OK_Pos 1080 #define BACKUP_LPECO_STATUS_LPECO_AMPDET_OK_Msk BACKUP_V3_LPECO_STATUS_LPECO_AMPDET_OK_Msk 1081 #define BACKUP_LPECO_STATUS_LPECO_READY_Pos BACKUP_V3_LPECO_STATUS_LPECO_READY_Pos 1082 #define BACKUP_LPECO_STATUS_LPECO_READY_Msk BACKUP_V3_LPECO_STATUS_LPECO_READY_Msk 1083 /* BACKUP.BREG */ 1084 #define BACKUP_BREG_BREG_Pos BACKUP_V3_BREG_BREG_Pos 1085 #define BACKUP_BREG_BREG_Msk BACKUP_V3_BREG_BREG_Msk 1086 #endif /* CY_DEVICE_TVIIBE type */ 1087 1088 /******************************************************************************* 1089 * CPUSS 1090 *******************************************************************************/ 1091 typedef struct { 1092 __IOM uint32_t CM0_CTL; /*!< 0x00000000 CM0+ control */ 1093 __IM uint32_t RESERVED; 1094 __IM uint32_t CM0_STATUS; /*!< 0x00000008 CM0+ status */ 1095 __IM uint32_t RESERVED1; 1096 __IOM uint32_t CM0_CLOCK_CTL; /*!< 0x00000010 CM0+ clock control */ 1097 __IM uint32_t RESERVED2[3]; 1098 __IOM uint32_t CM0_INT_CTL0; /*!< 0x00000020 CM0+ interrupt control 0 */ 1099 __IOM uint32_t CM0_INT_CTL1; /*!< 0x00000024 CM0+ interrupt control 1 */ 1100 __IOM uint32_t CM0_INT_CTL2; /*!< 0x00000028 CM0+ interrupt control 2 */ 1101 __IOM uint32_t CM0_INT_CTL3; /*!< 0x0000002C CM0+ interrupt control 3 */ 1102 __IOM uint32_t CM0_INT_CTL4; /*!< 0x00000030 CM0+ interrupt control 4 */ 1103 __IOM uint32_t CM0_INT_CTL5; /*!< 0x00000034 CM0+ interrupt control 5 */ 1104 __IOM uint32_t CM0_INT_CTL6; /*!< 0x00000038 CM0+ interrupt control 6 */ 1105 __IOM uint32_t CM0_INT_CTL7; /*!< 0x0000003C CM0+ interrupt control 7 */ 1106 __IM uint32_t RESERVED3[16]; 1107 __IOM uint32_t CM4_PWR_CTL; /*!< 0x00000080 CM4 power control */ 1108 __IOM uint32_t CM4_PWR_DELAY_CTL; /*!< 0x00000084 CM4 power control */ 1109 __IM uint32_t CM4_STATUS; /*!< 0x00000088 CM4 status */ 1110 __IM uint32_t RESERVED4; 1111 __IOM uint32_t CM4_CLOCK_CTL; /*!< 0x00000090 CM4 clock control */ 1112 __IM uint32_t RESERVED5[3]; 1113 __IOM uint32_t CM4_NMI_CTL; /*!< 0x000000A0 CM4 NMI control */ 1114 __IM uint32_t RESERVED6[23]; 1115 __IOM uint32_t RAM0_CTL0; /*!< 0x00000100 RAM 0 control 0 */ 1116 __IM uint32_t RESERVED7[15]; 1117 __IOM uint32_t RAM0_PWR_MACRO_CTL[16]; /*!< 0x00000140 RAM 0 power control */ 1118 __IOM uint32_t RAM1_CTL0; /*!< 0x00000180 RAM 1 control 0 */ 1119 __IM uint32_t RESERVED8[3]; 1120 __IOM uint32_t RAM1_PWR_CTL; /*!< 0x00000190 RAM1 power control */ 1121 __IM uint32_t RESERVED9[3]; 1122 __IOM uint32_t RAM2_CTL0; /*!< 0x000001A0 RAM 2 control 0 */ 1123 __IM uint32_t RESERVED10[3]; 1124 __IOM uint32_t RAM2_PWR_CTL; /*!< 0x000001B0 RAM2 power control */ 1125 __IM uint32_t RESERVED11[3]; 1126 __IOM uint32_t RAM_PWR_DELAY_CTL; /*!< 0x000001C0 Power up delay used for all SRAM power domains */ 1127 __IM uint32_t RESERVED12[3]; 1128 __IOM uint32_t ROM_CTL; /*!< 0x000001D0 ROM control */ 1129 __IM uint32_t RESERVED13[7]; 1130 __IOM uint32_t UDB_PWR_CTL; /*!< 0x000001F0 UDB power control */ 1131 __IOM uint32_t UDB_PWR_DELAY_CTL; /*!< 0x000001F4 UDB power control */ 1132 __IM uint32_t RESERVED14[4]; 1133 __IM uint32_t DP_STATUS; /*!< 0x00000208 Debug port status */ 1134 __IM uint32_t RESERVED15[5]; 1135 __IOM uint32_t BUFF_CTL; /*!< 0x00000220 Buffer control */ 1136 __IM uint32_t RESERVED16[3]; 1137 __IOM uint32_t DDFT_CTL; /*!< 0x00000230 DDFT control */ 1138 __IM uint32_t RESERVED17[3]; 1139 __IOM uint32_t SYSTICK_CTL; /*!< 0x00000240 SysTick timer control */ 1140 __IM uint32_t RESERVED18[27]; 1141 __IOM uint32_t CM0_VECTOR_TABLE_BASE; /*!< 0x000002B0 CM0+ vector table base */ 1142 __IM uint32_t RESERVED19[3]; 1143 __IOM uint32_t CM4_VECTOR_TABLE_BASE; /*!< 0x000002C0 CM4 vector table base */ 1144 __IM uint32_t RESERVED20[23]; 1145 __IOM uint32_t CM0_PC0_HANDLER; /*!< 0x00000320 CM0+ protection context 0 handler */ 1146 __IM uint32_t RESERVED21[55]; 1147 __IM uint32_t IDENTITY; /*!< 0x00000400 Identity */ 1148 __IM uint32_t RESERVED22[63]; 1149 __IOM uint32_t PROTECTION; /*!< 0x00000500 Protection status */ 1150 __IM uint32_t RESERVED23[7]; 1151 __IOM uint32_t CM0_NMI_CTL; /*!< 0x00000520 CM0+ NMI control */ 1152 __IM uint32_t RESERVED24[7]; 1153 __IOM uint32_t AP_CTL; /*!< 0x00000540 Access port control */ 1154 __IM uint32_t RESERVED25[23]; 1155 __IM uint32_t MBIST_STAT; /*!< 0x000005A0 Memory BIST status */ 1156 __IM uint32_t RESERVED26[14999]; 1157 __IOM uint32_t TRIM_ROM_CTL; /*!< 0x0000F000 ROM trim control */ 1158 __IOM uint32_t TRIM_RAM_CTL; /*!< 0x0000F004 RAM trim control */ 1159 } CPUSS_V1_Type; /*!< Size = 61448 (0xF008) */ 1160 1161 /* CPUSS.IDENTITY */ 1162 #define CPUSS_IDENTITY_P_Pos CPUSS_V2_IDENTITY_P_Pos 1163 #define CPUSS_IDENTITY_P_Msk CPUSS_V2_IDENTITY_P_Msk 1164 #define CPUSS_IDENTITY_NS_Pos CPUSS_V2_IDENTITY_NS_Pos 1165 #define CPUSS_IDENTITY_NS_Msk CPUSS_V2_IDENTITY_NS_Msk 1166 #define CPUSS_IDENTITY_PC_Pos CPUSS_V2_IDENTITY_PC_Pos 1167 #define CPUSS_IDENTITY_PC_Msk CPUSS_V2_IDENTITY_PC_Msk 1168 #define CPUSS_IDENTITY_MS_Pos CPUSS_V2_IDENTITY_MS_Pos 1169 #define CPUSS_IDENTITY_MS_Msk CPUSS_V2_IDENTITY_MS_Msk 1170 /* CPUSS.CM4_STATUS */ 1171 #define CPUSS_CM4_STATUS_SLEEPING_Pos CPUSS_V2_CM4_STATUS_SLEEPING_Pos 1172 #define CPUSS_CM4_STATUS_SLEEPING_Msk CPUSS_V2_CM4_STATUS_SLEEPING_Msk 1173 #define CPUSS_CM4_STATUS_SLEEPDEEP_Pos CPUSS_V2_CM4_STATUS_SLEEPDEEP_Pos 1174 #define CPUSS_CM4_STATUS_SLEEPDEEP_Msk CPUSS_V2_CM4_STATUS_SLEEPDEEP_Msk 1175 #define CPUSS_CM4_STATUS_PWR_DONE_Pos CPUSS_V2_CM4_STATUS_PWR_DONE_Pos 1176 #define CPUSS_CM4_STATUS_PWR_DONE_Msk CPUSS_V2_CM4_STATUS_PWR_DONE_Msk 1177 /* CPUSS.CM4_CLOCK_CTL */ 1178 #define CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV_Pos CPUSS_V2_CM4_CLOCK_CTL_FAST_INT_DIV_Pos 1179 #define CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV_Msk CPUSS_V2_CM4_CLOCK_CTL_FAST_INT_DIV_Msk 1180 /* CPUSS.CM4_CTL */ 1181 #define CPUSS_CM4_CTL_IOC_MASK_Pos CPUSS_V2_CM4_CTL_IOC_MASK_Pos 1182 #define CPUSS_CM4_CTL_IOC_MASK_Msk CPUSS_V2_CM4_CTL_IOC_MASK_Msk 1183 #define CPUSS_CM4_CTL_DZC_MASK_Pos CPUSS_V2_CM4_CTL_DZC_MASK_Pos 1184 #define CPUSS_CM4_CTL_DZC_MASK_Msk CPUSS_V2_CM4_CTL_DZC_MASK_Msk 1185 #define CPUSS_CM4_CTL_OFC_MASK_Pos CPUSS_V2_CM4_CTL_OFC_MASK_Pos 1186 #define CPUSS_CM4_CTL_OFC_MASK_Msk CPUSS_V2_CM4_CTL_OFC_MASK_Msk 1187 #define CPUSS_CM4_CTL_UFC_MASK_Pos CPUSS_V2_CM4_CTL_UFC_MASK_Pos 1188 #define CPUSS_CM4_CTL_UFC_MASK_Msk CPUSS_V2_CM4_CTL_UFC_MASK_Msk 1189 #define CPUSS_CM4_CTL_IXC_MASK_Pos CPUSS_V2_CM4_CTL_IXC_MASK_Pos 1190 #define CPUSS_CM4_CTL_IXC_MASK_Msk CPUSS_V2_CM4_CTL_IXC_MASK_Msk 1191 #define CPUSS_CM4_CTL_IDC_MASK_Pos CPUSS_V2_CM4_CTL_IDC_MASK_Pos 1192 #define CPUSS_CM4_CTL_IDC_MASK_Msk CPUSS_V2_CM4_CTL_IDC_MASK_Msk 1193 /* CPUSS.CM4_INT0_STATUS */ 1194 #define CPUSS_CM4_INT0_STATUS_SYSTEM_INT_IDX_Pos CPUSS_V2_CM4_INT0_STATUS_SYSTEM_INT_IDX_Pos 1195 #define CPUSS_CM4_INT0_STATUS_SYSTEM_INT_IDX_Msk CPUSS_V2_CM4_INT0_STATUS_SYSTEM_INT_IDX_Msk 1196 #define CPUSS_CM4_INT0_STATUS_SYSTEM_INT_VALID_Pos CPUSS_V2_CM4_INT0_STATUS_SYSTEM_INT_VALID_Pos 1197 #define CPUSS_CM4_INT0_STATUS_SYSTEM_INT_VALID_Msk CPUSS_V2_CM4_INT0_STATUS_SYSTEM_INT_VALID_Msk 1198 /* CPUSS.CM4_INT1_STATUS */ 1199 #define CPUSS_CM4_INT1_STATUS_SYSTEM_INT_IDX_Pos CPUSS_V2_CM4_INT1_STATUS_SYSTEM_INT_IDX_Pos 1200 #define CPUSS_CM4_INT1_STATUS_SYSTEM_INT_IDX_Msk CPUSS_V2_CM4_INT1_STATUS_SYSTEM_INT_IDX_Msk 1201 #define CPUSS_CM4_INT1_STATUS_SYSTEM_INT_VALID_Pos CPUSS_V2_CM4_INT1_STATUS_SYSTEM_INT_VALID_Pos 1202 #define CPUSS_CM4_INT1_STATUS_SYSTEM_INT_VALID_Msk CPUSS_V2_CM4_INT1_STATUS_SYSTEM_INT_VALID_Msk 1203 /* CPUSS.CM4_INT2_STATUS */ 1204 #define CPUSS_CM4_INT2_STATUS_SYSTEM_INT_IDX_Pos CPUSS_V2_CM4_INT2_STATUS_SYSTEM_INT_IDX_Pos 1205 #define CPUSS_CM4_INT2_STATUS_SYSTEM_INT_IDX_Msk CPUSS_V2_CM4_INT2_STATUS_SYSTEM_INT_IDX_Msk 1206 #define CPUSS_CM4_INT2_STATUS_SYSTEM_INT_VALID_Pos CPUSS_V2_CM4_INT2_STATUS_SYSTEM_INT_VALID_Pos 1207 #define CPUSS_CM4_INT2_STATUS_SYSTEM_INT_VALID_Msk CPUSS_V2_CM4_INT2_STATUS_SYSTEM_INT_VALID_Msk 1208 /* CPUSS.CM4_INT3_STATUS */ 1209 #define CPUSS_CM4_INT3_STATUS_SYSTEM_INT_IDX_Pos CPUSS_V2_CM4_INT3_STATUS_SYSTEM_INT_IDX_Pos 1210 #define CPUSS_CM4_INT3_STATUS_SYSTEM_INT_IDX_Msk CPUSS_V2_CM4_INT3_STATUS_SYSTEM_INT_IDX_Msk 1211 #define CPUSS_CM4_INT3_STATUS_SYSTEM_INT_VALID_Pos CPUSS_V2_CM4_INT3_STATUS_SYSTEM_INT_VALID_Pos 1212 #define CPUSS_CM4_INT3_STATUS_SYSTEM_INT_VALID_Msk CPUSS_V2_CM4_INT3_STATUS_SYSTEM_INT_VALID_Msk 1213 /* CPUSS.CM4_INT4_STATUS */ 1214 #define CPUSS_CM4_INT4_STATUS_SYSTEM_INT_IDX_Pos CPUSS_V2_CM4_INT4_STATUS_SYSTEM_INT_IDX_Pos 1215 #define CPUSS_CM4_INT4_STATUS_SYSTEM_INT_IDX_Msk CPUSS_V2_CM4_INT4_STATUS_SYSTEM_INT_IDX_Msk 1216 #define CPUSS_CM4_INT4_STATUS_SYSTEM_INT_VALID_Pos CPUSS_V2_CM4_INT4_STATUS_SYSTEM_INT_VALID_Pos 1217 #define CPUSS_CM4_INT4_STATUS_SYSTEM_INT_VALID_Msk CPUSS_V2_CM4_INT4_STATUS_SYSTEM_INT_VALID_Msk 1218 /* CPUSS.CM4_INT5_STATUS */ 1219 #define CPUSS_CM4_INT5_STATUS_SYSTEM_INT_IDX_Pos CPUSS_V2_CM4_INT5_STATUS_SYSTEM_INT_IDX_Pos 1220 #define CPUSS_CM4_INT5_STATUS_SYSTEM_INT_IDX_Msk CPUSS_V2_CM4_INT5_STATUS_SYSTEM_INT_IDX_Msk 1221 #define CPUSS_CM4_INT5_STATUS_SYSTEM_INT_VALID_Pos CPUSS_V2_CM4_INT5_STATUS_SYSTEM_INT_VALID_Pos 1222 #define CPUSS_CM4_INT5_STATUS_SYSTEM_INT_VALID_Msk CPUSS_V2_CM4_INT5_STATUS_SYSTEM_INT_VALID_Msk 1223 /* CPUSS.CM4_INT6_STATUS */ 1224 #define CPUSS_CM4_INT6_STATUS_SYSTEM_INT_IDX_Pos CPUSS_V2_CM4_INT6_STATUS_SYSTEM_INT_IDX_Pos 1225 #define CPUSS_CM4_INT6_STATUS_SYSTEM_INT_IDX_Msk CPUSS_V2_CM4_INT6_STATUS_SYSTEM_INT_IDX_Msk 1226 #define CPUSS_CM4_INT6_STATUS_SYSTEM_INT_VALID_Pos CPUSS_V2_CM4_INT6_STATUS_SYSTEM_INT_VALID_Pos 1227 #define CPUSS_CM4_INT6_STATUS_SYSTEM_INT_VALID_Msk CPUSS_V2_CM4_INT6_STATUS_SYSTEM_INT_VALID_Msk 1228 /* CPUSS.CM4_INT7_STATUS */ 1229 #define CPUSS_CM4_INT7_STATUS_SYSTEM_INT_IDX_Pos CPUSS_V2_CM4_INT7_STATUS_SYSTEM_INT_IDX_Pos 1230 #define CPUSS_CM4_INT7_STATUS_SYSTEM_INT_IDX_Msk CPUSS_V2_CM4_INT7_STATUS_SYSTEM_INT_IDX_Msk 1231 #define CPUSS_CM4_INT7_STATUS_SYSTEM_INT_VALID_Pos CPUSS_V2_CM4_INT7_STATUS_SYSTEM_INT_VALID_Pos 1232 #define CPUSS_CM4_INT7_STATUS_SYSTEM_INT_VALID_Msk CPUSS_V2_CM4_INT7_STATUS_SYSTEM_INT_VALID_Msk 1233 /* CPUSS.CM4_VECTOR_TABLE_BASE */ 1234 #define CPUSS_CM4_VECTOR_TABLE_BASE_ADDR22_Pos CPUSS_V2_CM4_VECTOR_TABLE_BASE_ADDR22_Pos 1235 #define CPUSS_CM4_VECTOR_TABLE_BASE_ADDR22_Msk CPUSS_V2_CM4_VECTOR_TABLE_BASE_ADDR22_Msk 1236 /* CPUSS.CM4_NMI_CTL */ 1237 #define CPUSS_CM4_NMI_CTL_SYSTEM_INT_IDX_Pos CPUSS_V2_CM4_NMI_CTL_SYSTEM_INT_IDX_Pos 1238 #define CPUSS_CM4_NMI_CTL_SYSTEM_INT_IDX_Msk CPUSS_V2_CM4_NMI_CTL_SYSTEM_INT_IDX_Msk 1239 /* CPUSS.UDB_PWR_CTL */ 1240 #define CPUSS_UDB_PWR_CTL_PWR_MODE_Pos CPUSS_V2_UDB_PWR_CTL_PWR_MODE_Pos 1241 #define CPUSS_UDB_PWR_CTL_PWR_MODE_Msk CPUSS_V2_UDB_PWR_CTL_PWR_MODE_Msk 1242 #define CPUSS_UDB_PWR_CTL_VECTKEYSTAT_Pos CPUSS_V2_UDB_PWR_CTL_VECTKEYSTAT_Pos 1243 #define CPUSS_UDB_PWR_CTL_VECTKEYSTAT_Msk CPUSS_V2_UDB_PWR_CTL_VECTKEYSTAT_Msk 1244 /* CPUSS.UDB_PWR_DELAY_CTL */ 1245 #define CPUSS_UDB_PWR_DELAY_CTL_UP_Pos CPUSS_V2_UDB_PWR_DELAY_CTL_UP_Pos 1246 #define CPUSS_UDB_PWR_DELAY_CTL_UP_Msk CPUSS_V2_UDB_PWR_DELAY_CTL_UP_Msk 1247 /* CPUSS.CM0_CTL */ 1248 #define CPUSS_CM0_CTL_SLV_STALL_Pos CPUSS_V2_CM0_CTL_SLV_STALL_Pos 1249 #define CPUSS_CM0_CTL_SLV_STALL_Msk CPUSS_V2_CM0_CTL_SLV_STALL_Msk 1250 #define CPUSS_CM0_CTL_ENABLED_Pos CPUSS_V2_CM0_CTL_ENABLED_Pos 1251 #define CPUSS_CM0_CTL_ENABLED_Msk CPUSS_V2_CM0_CTL_ENABLED_Msk 1252 #define CPUSS_CM0_CTL_VECTKEYSTAT_Pos CPUSS_V2_CM0_CTL_VECTKEYSTAT_Pos 1253 #define CPUSS_CM0_CTL_VECTKEYSTAT_Msk CPUSS_V2_CM0_CTL_VECTKEYSTAT_Msk 1254 /* CPUSS.CM0_STATUS */ 1255 #define CPUSS_CM0_STATUS_SLEEPING_Pos CPUSS_V2_CM0_STATUS_SLEEPING_Pos 1256 #define CPUSS_CM0_STATUS_SLEEPING_Msk CPUSS_V2_CM0_STATUS_SLEEPING_Msk 1257 #define CPUSS_CM0_STATUS_SLEEPDEEP_Pos CPUSS_V2_CM0_STATUS_SLEEPDEEP_Pos 1258 #define CPUSS_CM0_STATUS_SLEEPDEEP_Msk CPUSS_V2_CM0_STATUS_SLEEPDEEP_Msk 1259 /* CPUSS.CM0_CLOCK_CTL */ 1260 #define CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV_Pos CPUSS_V2_CM0_CLOCK_CTL_SLOW_INT_DIV_Pos 1261 #define CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV_Msk CPUSS_V2_CM0_CLOCK_CTL_SLOW_INT_DIV_Msk 1262 #define CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV_Pos CPUSS_V2_CM0_CLOCK_CTL_PERI_INT_DIV_Pos 1263 #define CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV_Msk CPUSS_V2_CM0_CLOCK_CTL_PERI_INT_DIV_Msk 1264 /* CPUSS.CM0_INT_STATUS_BASE */ 1265 #define CPUSS_CM0_INT_STATUS_BASE ((volatile const uint32_t *) &(((CPUSS_Type *)(CPUSS))->CM0_INT0_STATUS)) 1266 /* CPUSS.CM0_INT0_STATUS */ 1267 #define CPUSS_CM0_INT0_STATUS_SYSTEM_INT_IDX_Pos CPUSS_V2_CM0_INT0_STATUS_SYSTEM_INT_IDX_Pos 1268 #define CPUSS_CM0_INT0_STATUS_SYSTEM_INT_IDX_Msk CPUSS_V2_CM0_INT0_STATUS_SYSTEM_INT_IDX_Msk 1269 #define CPUSS_CM0_INT0_STATUS_SYSTEM_INT_VALID_Pos CPUSS_V2_CM0_INT0_STATUS_SYSTEM_INT_VALID_Pos 1270 #define CPUSS_CM0_INT0_STATUS_SYSTEM_INT_VALID_Msk CPUSS_V2_CM0_INT0_STATUS_SYSTEM_INT_VALID_Msk 1271 /* CPUSS.CM0_INT1_STATUS */ 1272 #define CPUSS_CM0_INT1_STATUS_SYSTEM_INT_IDX_Pos CPUSS_V2_CM0_INT1_STATUS_SYSTEM_INT_IDX_Pos 1273 #define CPUSS_CM0_INT1_STATUS_SYSTEM_INT_IDX_Msk CPUSS_V2_CM0_INT1_STATUS_SYSTEM_INT_IDX_Msk 1274 #define CPUSS_CM0_INT1_STATUS_SYSTEM_INT_VALID_Pos CPUSS_V2_CM0_INT1_STATUS_SYSTEM_INT_VALID_Pos 1275 #define CPUSS_CM0_INT1_STATUS_SYSTEM_INT_VALID_Msk CPUSS_V2_CM0_INT1_STATUS_SYSTEM_INT_VALID_Msk 1276 /* CPUSS.CM0_INT2_STATUS */ 1277 #define CPUSS_CM0_INT2_STATUS_SYSTEM_INT_IDX_Pos CPUSS_V2_CM0_INT2_STATUS_SYSTEM_INT_IDX_Pos 1278 #define CPUSS_CM0_INT2_STATUS_SYSTEM_INT_IDX_Msk CPUSS_V2_CM0_INT2_STATUS_SYSTEM_INT_IDX_Msk 1279 #define CPUSS_CM0_INT2_STATUS_SYSTEM_INT_VALID_Pos CPUSS_V2_CM0_INT2_STATUS_SYSTEM_INT_VALID_Pos 1280 #define CPUSS_CM0_INT2_STATUS_SYSTEM_INT_VALID_Msk CPUSS_V2_CM0_INT2_STATUS_SYSTEM_INT_VALID_Msk 1281 /* CPUSS.CM0_INT3_STATUS */ 1282 #define CPUSS_CM0_INT3_STATUS_SYSTEM_INT_IDX_Pos CPUSS_V2_CM0_INT3_STATUS_SYSTEM_INT_IDX_Pos 1283 #define CPUSS_CM0_INT3_STATUS_SYSTEM_INT_IDX_Msk CPUSS_V2_CM0_INT3_STATUS_SYSTEM_INT_IDX_Msk 1284 #define CPUSS_CM0_INT3_STATUS_SYSTEM_INT_VALID_Pos CPUSS_V2_CM0_INT3_STATUS_SYSTEM_INT_VALID_Pos 1285 #define CPUSS_CM0_INT3_STATUS_SYSTEM_INT_VALID_Msk CPUSS_V2_CM0_INT3_STATUS_SYSTEM_INT_VALID_Msk 1286 /* CPUSS.CM0_INT4_STATUS */ 1287 #define CPUSS_CM0_INT4_STATUS_SYSTEM_INT_IDX_Pos CPUSS_V2_CM0_INT4_STATUS_SYSTEM_INT_IDX_Pos 1288 #define CPUSS_CM0_INT4_STATUS_SYSTEM_INT_IDX_Msk CPUSS_V2_CM0_INT4_STATUS_SYSTEM_INT_IDX_Msk 1289 #define CPUSS_CM0_INT4_STATUS_SYSTEM_INT_VALID_Pos CPUSS_V2_CM0_INT4_STATUS_SYSTEM_INT_VALID_Pos 1290 #define CPUSS_CM0_INT4_STATUS_SYSTEM_INT_VALID_Msk CPUSS_V2_CM0_INT4_STATUS_SYSTEM_INT_VALID_Msk 1291 /* CPUSS.CM0_INT5_STATUS */ 1292 #define CPUSS_CM0_INT5_STATUS_SYSTEM_INT_IDX_Pos CPUSS_V2_CM0_INT5_STATUS_SYSTEM_INT_IDX_Pos 1293 #define CPUSS_CM0_INT5_STATUS_SYSTEM_INT_IDX_Msk CPUSS_V2_CM0_INT5_STATUS_SYSTEM_INT_IDX_Msk 1294 #define CPUSS_CM0_INT5_STATUS_SYSTEM_INT_VALID_Pos CPUSS_V2_CM0_INT5_STATUS_SYSTEM_INT_VALID_Pos 1295 #define CPUSS_CM0_INT5_STATUS_SYSTEM_INT_VALID_Msk CPUSS_V2_CM0_INT5_STATUS_SYSTEM_INT_VALID_Msk 1296 /* CPUSS.CM0_INT6_STATUS */ 1297 #define CPUSS_CM0_INT6_STATUS_SYSTEM_INT_IDX_Pos CPUSS_V2_CM0_INT6_STATUS_SYSTEM_INT_IDX_Pos 1298 #define CPUSS_CM0_INT6_STATUS_SYSTEM_INT_IDX_Msk CPUSS_V2_CM0_INT6_STATUS_SYSTEM_INT_IDX_Msk 1299 #define CPUSS_CM0_INT6_STATUS_SYSTEM_INT_VALID_Pos CPUSS_V2_CM0_INT6_STATUS_SYSTEM_INT_VALID_Pos 1300 #define CPUSS_CM0_INT6_STATUS_SYSTEM_INT_VALID_Msk CPUSS_V2_CM0_INT6_STATUS_SYSTEM_INT_VALID_Msk 1301 /* CPUSS.CM0_INT7_STATUS */ 1302 #define CPUSS_CM0_INT7_STATUS_SYSTEM_INT_IDX_Pos CPUSS_V2_CM0_INT7_STATUS_SYSTEM_INT_IDX_Pos 1303 #define CPUSS_CM0_INT7_STATUS_SYSTEM_INT_IDX_Msk CPUSS_V2_CM0_INT7_STATUS_SYSTEM_INT_IDX_Msk 1304 #define CPUSS_CM0_INT7_STATUS_SYSTEM_INT_VALID_Pos CPUSS_V2_CM0_INT7_STATUS_SYSTEM_INT_VALID_Pos 1305 #define CPUSS_CM0_INT7_STATUS_SYSTEM_INT_VALID_Msk CPUSS_V2_CM0_INT7_STATUS_SYSTEM_INT_VALID_Msk 1306 /* CPUSS.CM0_VECTOR_TABLE_BASE */ 1307 #define CPUSS_CM0_VECTOR_TABLE_BASE_ADDR24_Pos CPUSS_V2_CM0_VECTOR_TABLE_BASE_ADDR24_Pos 1308 #define CPUSS_CM0_VECTOR_TABLE_BASE_ADDR24_Msk CPUSS_V2_CM0_VECTOR_TABLE_BASE_ADDR24_Msk 1309 /* CPUSS.CM0_NMI_CTL */ 1310 #define CPUSS_CM0_NMI_CTL_SYSTEM_INT_IDX_Pos CPUSS_V2_CM0_NMI_CTL_SYSTEM_INT_IDX_Pos 1311 #define CPUSS_CM0_NMI_CTL_SYSTEM_INT_IDX_Msk CPUSS_V2_CM0_NMI_CTL_SYSTEM_INT_IDX_Msk 1312 /* CPUSS.CM4_PWR_CTL */ 1313 #define CPUSS_CM4_PWR_CTL_PWR_MODE_Pos CPUSS_V2_CM4_PWR_CTL_PWR_MODE_Pos 1314 #define CPUSS_CM4_PWR_CTL_PWR_MODE_Msk CPUSS_V2_CM4_PWR_CTL_PWR_MODE_Msk 1315 #define CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Pos CPUSS_V2_CM4_PWR_CTL_VECTKEYSTAT_Pos 1316 #define CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk CPUSS_V2_CM4_PWR_CTL_VECTKEYSTAT_Msk 1317 /* CPUSS.CM4_PWR_DELAY_CTL */ 1318 #define CPUSS_CM4_PWR_DELAY_CTL_UP_Pos CPUSS_V2_CM4_PWR_DELAY_CTL_UP_Pos 1319 #define CPUSS_CM4_PWR_DELAY_CTL_UP_Msk CPUSS_V2_CM4_PWR_DELAY_CTL_UP_Msk 1320 /* CPUSS.RAM0_CTL0 */ 1321 #define CPUSS_RAM0_CTL0_SLOW_WS_Pos CPUSS_V2_RAM0_CTL0_SLOW_WS_Pos 1322 #define CPUSS_RAM0_CTL0_SLOW_WS_Msk CPUSS_V2_RAM0_CTL0_SLOW_WS_Msk 1323 #define CPUSS_RAM0_CTL0_FAST_WS_Pos CPUSS_V2_RAM0_CTL0_FAST_WS_Pos 1324 #define CPUSS_RAM0_CTL0_FAST_WS_Msk CPUSS_V2_RAM0_CTL0_FAST_WS_Msk 1325 #define CPUSS_RAM0_CTL0_ECC_EN_Pos CPUSS_V2_RAM0_CTL0_ECC_EN_Pos 1326 #define CPUSS_RAM0_CTL0_ECC_EN_Msk CPUSS_V2_RAM0_CTL0_ECC_EN_Msk 1327 #define CPUSS_RAM0_CTL0_ECC_AUTO_CORRECT_Pos CPUSS_V2_RAM0_CTL0_ECC_AUTO_CORRECT_Pos 1328 #define CPUSS_RAM0_CTL0_ECC_AUTO_CORRECT_Msk CPUSS_V2_RAM0_CTL0_ECC_AUTO_CORRECT_Msk 1329 #define CPUSS_RAM0_CTL0_ECC_INJ_EN_Pos CPUSS_V2_RAM0_CTL0_ECC_INJ_EN_Pos 1330 #define CPUSS_RAM0_CTL0_ECC_INJ_EN_Msk CPUSS_V2_RAM0_CTL0_ECC_INJ_EN_Msk 1331 /* CPUSS.RAM0_STATUS */ 1332 #define CPUSS_RAM0_STATUS_WB_EMPTY_Pos CPUSS_V2_RAM0_STATUS_WB_EMPTY_Pos 1333 #define CPUSS_RAM0_STATUS_WB_EMPTY_Msk CPUSS_V2_RAM0_STATUS_WB_EMPTY_Msk 1334 /* CPUSS.RAM0_PWR_MACRO_CTL */ 1335 #define CPUSS_RAM0_PWR_MACRO_CTL_PWR_MODE_Pos CPUSS_V2_RAM0_PWR_MACRO_CTL_PWR_MODE_Pos 1336 #define CPUSS_RAM0_PWR_MACRO_CTL_PWR_MODE_Msk CPUSS_V2_RAM0_PWR_MACRO_CTL_PWR_MODE_Msk 1337 #define CPUSS_RAM0_PWR_MACRO_CTL_VECTKEYSTAT_Pos CPUSS_V2_RAM0_PWR_MACRO_CTL_VECTKEYSTAT_Pos 1338 #define CPUSS_RAM0_PWR_MACRO_CTL_VECTKEYSTAT_Msk CPUSS_V2_RAM0_PWR_MACRO_CTL_VECTKEYSTAT_Msk 1339 /* CPUSS.RAM1_CTL0 */ 1340 #define CPUSS_RAM1_CTL0_SLOW_WS_Pos CPUSS_V2_RAM1_CTL0_SLOW_WS_Pos 1341 #define CPUSS_RAM1_CTL0_SLOW_WS_Msk CPUSS_V2_RAM1_CTL0_SLOW_WS_Msk 1342 #define CPUSS_RAM1_CTL0_FAST_WS_Pos CPUSS_V2_RAM1_CTL0_FAST_WS_Pos 1343 #define CPUSS_RAM1_CTL0_FAST_WS_Msk CPUSS_V2_RAM1_CTL0_FAST_WS_Msk 1344 #define CPUSS_RAM1_CTL0_ECC_EN_Pos CPUSS_V2_RAM1_CTL0_ECC_EN_Pos 1345 #define CPUSS_RAM1_CTL0_ECC_EN_Msk CPUSS_V2_RAM1_CTL0_ECC_EN_Msk 1346 #define CPUSS_RAM1_CTL0_ECC_AUTO_CORRECT_Pos CPUSS_V2_RAM1_CTL0_ECC_AUTO_CORRECT_Pos 1347 #define CPUSS_RAM1_CTL0_ECC_AUTO_CORRECT_Msk CPUSS_V2_RAM1_CTL0_ECC_AUTO_CORRECT_Msk 1348 #define CPUSS_RAM1_CTL0_ECC_INJ_EN_Pos CPUSS_V2_RAM1_CTL0_ECC_INJ_EN_Pos 1349 #define CPUSS_RAM1_CTL0_ECC_INJ_EN_Msk CPUSS_V2_RAM1_CTL0_ECC_INJ_EN_Msk 1350 /* CPUSS.RAM1_STATUS */ 1351 #define CPUSS_RAM1_STATUS_WB_EMPTY_Pos CPUSS_V2_RAM1_STATUS_WB_EMPTY_Pos 1352 #define CPUSS_RAM1_STATUS_WB_EMPTY_Msk CPUSS_V2_RAM1_STATUS_WB_EMPTY_Msk 1353 /* CPUSS.RAM1_PWR_CTL */ 1354 #define CPUSS_RAM1_PWR_CTL_PWR_MODE_Pos CPUSS_V2_RAM1_PWR_CTL_PWR_MODE_Pos 1355 #define CPUSS_RAM1_PWR_CTL_PWR_MODE_Msk CPUSS_V2_RAM1_PWR_CTL_PWR_MODE_Msk 1356 #define CPUSS_RAM1_PWR_CTL_VECTKEYSTAT_Pos CPUSS_V2_RAM1_PWR_CTL_VECTKEYSTAT_Pos 1357 #define CPUSS_RAM1_PWR_CTL_VECTKEYSTAT_Msk CPUSS_V2_RAM1_PWR_CTL_VECTKEYSTAT_Msk 1358 /* CPUSS.RAM2_CTL0 */ 1359 #define CPUSS_RAM2_CTL0_SLOW_WS_Pos CPUSS_V2_RAM2_CTL0_SLOW_WS_Pos 1360 #define CPUSS_RAM2_CTL0_SLOW_WS_Msk CPUSS_V2_RAM2_CTL0_SLOW_WS_Msk 1361 #define CPUSS_RAM2_CTL0_FAST_WS_Pos CPUSS_V2_RAM2_CTL0_FAST_WS_Pos 1362 #define CPUSS_RAM2_CTL0_FAST_WS_Msk CPUSS_V2_RAM2_CTL0_FAST_WS_Msk 1363 #define CPUSS_RAM2_CTL0_ECC_EN_Pos CPUSS_V2_RAM2_CTL0_ECC_EN_Pos 1364 #define CPUSS_RAM2_CTL0_ECC_EN_Msk CPUSS_V2_RAM2_CTL0_ECC_EN_Msk 1365 #define CPUSS_RAM2_CTL0_ECC_AUTO_CORRECT_Pos CPUSS_V2_RAM2_CTL0_ECC_AUTO_CORRECT_Pos 1366 #define CPUSS_RAM2_CTL0_ECC_AUTO_CORRECT_Msk CPUSS_V2_RAM2_CTL0_ECC_AUTO_CORRECT_Msk 1367 #define CPUSS_RAM2_CTL0_ECC_INJ_EN_Pos CPUSS_V2_RAM2_CTL0_ECC_INJ_EN_Pos 1368 #define CPUSS_RAM2_CTL0_ECC_INJ_EN_Msk CPUSS_V2_RAM2_CTL0_ECC_INJ_EN_Msk 1369 /* CPUSS.RAM2_STATUS */ 1370 #define CPUSS_RAM2_STATUS_WB_EMPTY_Pos CPUSS_V2_RAM2_STATUS_WB_EMPTY_Pos 1371 #define CPUSS_RAM2_STATUS_WB_EMPTY_Msk CPUSS_V2_RAM2_STATUS_WB_EMPTY_Msk 1372 /* CPUSS.RAM2_PWR_CTL */ 1373 #define CPUSS_RAM2_PWR_CTL_PWR_MODE_Pos CPUSS_V2_RAM2_PWR_CTL_PWR_MODE_Pos 1374 #define CPUSS_RAM2_PWR_CTL_PWR_MODE_Msk CPUSS_V2_RAM2_PWR_CTL_PWR_MODE_Msk 1375 #define CPUSS_RAM2_PWR_CTL_VECTKEYSTAT_Pos CPUSS_V2_RAM2_PWR_CTL_VECTKEYSTAT_Pos 1376 #define CPUSS_RAM2_PWR_CTL_VECTKEYSTAT_Msk CPUSS_V2_RAM2_PWR_CTL_VECTKEYSTAT_Msk 1377 /* CPUSS.RAM_PWR_DELAY_CTL */ 1378 #define CPUSS_RAM_PWR_DELAY_CTL_UP_Pos CPUSS_V2_RAM_PWR_DELAY_CTL_UP_Pos 1379 #define CPUSS_RAM_PWR_DELAY_CTL_UP_Msk CPUSS_V2_RAM_PWR_DELAY_CTL_UP_Msk 1380 /* CPUSS.ROM_CTL */ 1381 #define CPUSS_ROM_CTL_SLOW_WS_Pos CPUSS_V2_ROM_CTL_SLOW_WS_Pos 1382 #define CPUSS_ROM_CTL_SLOW_WS_Msk CPUSS_V2_ROM_CTL_SLOW_WS_Msk 1383 #define CPUSS_ROM_CTL_FAST_WS_Pos CPUSS_V2_ROM_CTL_FAST_WS_Pos 1384 #define CPUSS_ROM_CTL_FAST_WS_Msk CPUSS_V2_ROM_CTL_FAST_WS_Msk 1385 /* CPUSS.ECC_CTL */ 1386 #define CPUSS_ECC_CTL_WORD_ADDR_Pos CPUSS_V2_ECC_CTL_WORD_ADDR_Pos 1387 #define CPUSS_ECC_CTL_WORD_ADDR_Msk CPUSS_V2_ECC_CTL_WORD_ADDR_Msk 1388 #define CPUSS_ECC_CTL_PARITY_Pos CPUSS_V2_ECC_CTL_PARITY_Pos 1389 #define CPUSS_ECC_CTL_PARITY_Msk CPUSS_V2_ECC_CTL_PARITY_Msk 1390 /* CPUSS.PRODUCT_ID */ 1391 #define CPUSS_PRODUCT_ID_FAMILY_ID_Pos CPUSS_V2_PRODUCT_ID_FAMILY_ID_Pos 1392 #define CPUSS_PRODUCT_ID_FAMILY_ID_Msk CPUSS_V2_PRODUCT_ID_FAMILY_ID_Msk 1393 #define CPUSS_PRODUCT_ID_MAJOR_REV_Pos CPUSS_V2_PRODUCT_ID_MAJOR_REV_Pos 1394 #define CPUSS_PRODUCT_ID_MAJOR_REV_Msk CPUSS_V2_PRODUCT_ID_MAJOR_REV_Msk 1395 #define CPUSS_PRODUCT_ID_MINOR_REV_Pos CPUSS_V2_PRODUCT_ID_MINOR_REV_Pos 1396 #define CPUSS_PRODUCT_ID_MINOR_REV_Msk CPUSS_V2_PRODUCT_ID_MINOR_REV_Msk 1397 /* CPUSS.DP_STATUS */ 1398 #define CPUSS_DP_STATUS_SWJ_CONNECTED_Pos CPUSS_V2_DP_STATUS_SWJ_CONNECTED_Pos 1399 #define CPUSS_DP_STATUS_SWJ_CONNECTED_Msk CPUSS_V2_DP_STATUS_SWJ_CONNECTED_Msk 1400 #define CPUSS_DP_STATUS_SWJ_DEBUG_EN_Pos CPUSS_V2_DP_STATUS_SWJ_DEBUG_EN_Pos 1401 #define CPUSS_DP_STATUS_SWJ_DEBUG_EN_Msk CPUSS_V2_DP_STATUS_SWJ_DEBUG_EN_Msk 1402 #define CPUSS_DP_STATUS_SWJ_JTAG_SEL_Pos CPUSS_V2_DP_STATUS_SWJ_JTAG_SEL_Pos 1403 #define CPUSS_DP_STATUS_SWJ_JTAG_SEL_Msk CPUSS_V2_DP_STATUS_SWJ_JTAG_SEL_Msk 1404 /* CPUSS.AP_CTL */ 1405 #define CPUSS_AP_CTL_CM0_ENABLE_Pos CPUSS_V2_AP_CTL_CM0_ENABLE_Pos 1406 #define CPUSS_AP_CTL_CM0_ENABLE_Msk CPUSS_V2_AP_CTL_CM0_ENABLE_Msk 1407 #define CPUSS_AP_CTL_CM4_ENABLE_Pos CPUSS_V2_AP_CTL_CM4_ENABLE_Pos 1408 #define CPUSS_AP_CTL_CM4_ENABLE_Msk CPUSS_V2_AP_CTL_CM4_ENABLE_Msk 1409 #define CPUSS_AP_CTL_SYS_ENABLE_Pos CPUSS_V2_AP_CTL_SYS_ENABLE_Pos 1410 #define CPUSS_AP_CTL_SYS_ENABLE_Msk CPUSS_V2_AP_CTL_SYS_ENABLE_Msk 1411 #define CPUSS_AP_CTL_CM0_DISABLE_Pos CPUSS_V2_AP_CTL_CM0_DISABLE_Pos 1412 #define CPUSS_AP_CTL_CM0_DISABLE_Msk CPUSS_V2_AP_CTL_CM0_DISABLE_Msk 1413 #define CPUSS_AP_CTL_CM4_DISABLE_Pos CPUSS_V2_AP_CTL_CM4_DISABLE_Pos 1414 #define CPUSS_AP_CTL_CM4_DISABLE_Msk CPUSS_V2_AP_CTL_CM4_DISABLE_Msk 1415 #define CPUSS_AP_CTL_SYS_DISABLE_Pos CPUSS_V2_AP_CTL_SYS_DISABLE_Pos 1416 #define CPUSS_AP_CTL_SYS_DISABLE_Msk CPUSS_V2_AP_CTL_SYS_DISABLE_Msk 1417 /* CPUSS.BUFF_CTL */ 1418 #define CPUSS_BUFF_CTL_WRITE_BUFF_Pos CPUSS_V2_BUFF_CTL_WRITE_BUFF_Pos 1419 #define CPUSS_BUFF_CTL_WRITE_BUFF_Msk CPUSS_V2_BUFF_CTL_WRITE_BUFF_Msk 1420 /* CPUSS.SYSTICK_CTL */ 1421 #define CPUSS_SYSTICK_CTL_TENMS_Pos CPUSS_V2_SYSTICK_CTL_TENMS_Pos 1422 #define CPUSS_SYSTICK_CTL_TENMS_Msk CPUSS_V2_SYSTICK_CTL_TENMS_Msk 1423 #define CPUSS_SYSTICK_CTL_CLOCK_SOURCE_Pos CPUSS_V2_SYSTICK_CTL_CLOCK_SOURCE_Pos 1424 #define CPUSS_SYSTICK_CTL_CLOCK_SOURCE_Msk CPUSS_V2_SYSTICK_CTL_CLOCK_SOURCE_Msk 1425 #define CPUSS_SYSTICK_CTL_SKEW_Pos CPUSS_V2_SYSTICK_CTL_SKEW_Pos 1426 #define CPUSS_SYSTICK_CTL_SKEW_Msk CPUSS_V2_SYSTICK_CTL_SKEW_Msk 1427 #define CPUSS_SYSTICK_CTL_NOREF_Pos CPUSS_V2_SYSTICK_CTL_NOREF_Pos 1428 #define CPUSS_SYSTICK_CTL_NOREF_Msk CPUSS_V2_SYSTICK_CTL_NOREF_Msk 1429 /* CPUSS.MBIST_STAT */ 1430 #define CPUSS_MBIST_STAT_SFP_READY_Pos CPUSS_V2_MBIST_STAT_SFP_READY_Pos 1431 #define CPUSS_MBIST_STAT_SFP_READY_Msk CPUSS_V2_MBIST_STAT_SFP_READY_Msk 1432 #define CPUSS_MBIST_STAT_SFP_FAIL_Pos CPUSS_V2_MBIST_STAT_SFP_FAIL_Pos 1433 #define CPUSS_MBIST_STAT_SFP_FAIL_Msk CPUSS_V2_MBIST_STAT_SFP_FAIL_Msk 1434 /* CPUSS.CAL_SUP_SET */ 1435 #define CPUSS_CAL_SUP_SET_DATA_Pos CPUSS_V2_CAL_SUP_SET_DATA_Pos 1436 #define CPUSS_CAL_SUP_SET_DATA_Msk CPUSS_V2_CAL_SUP_SET_DATA_Msk 1437 /* CPUSS.CAL_SUP_CLR */ 1438 #define CPUSS_CAL_SUP_CLR_DATA_Pos CPUSS_V2_CAL_SUP_CLR_DATA_Pos 1439 #define CPUSS_CAL_SUP_CLR_DATA_Msk CPUSS_V2_CAL_SUP_CLR_DATA_Msk 1440 /* CPUSS.CM0_PC_CTL */ 1441 #define CPUSS_CM0_PC_CTL_VALID_Pos CPUSS_V2_CM0_PC_CTL_VALID_Pos 1442 #define CPUSS_CM0_PC_CTL_VALID_Msk CPUSS_V2_CM0_PC_CTL_VALID_Msk 1443 /* CPUSS.CM0_PC0_HANDLER */ 1444 #define CPUSS_CM0_PC0_HANDLER_ADDR_Pos CPUSS_V2_CM0_PC0_HANDLER_ADDR_Pos 1445 #define CPUSS_CM0_PC0_HANDLER_ADDR_Msk CPUSS_V2_CM0_PC0_HANDLER_ADDR_Msk 1446 /* CPUSS.CM0_PC1_HANDLER */ 1447 #define CPUSS_CM0_PC1_HANDLER_ADDR_Pos CPUSS_V2_CM0_PC1_HANDLER_ADDR_Pos 1448 #define CPUSS_CM0_PC1_HANDLER_ADDR_Msk CPUSS_V2_CM0_PC1_HANDLER_ADDR_Msk 1449 /* CPUSS.CM0_PC2_HANDLER */ 1450 #define CPUSS_CM0_PC2_HANDLER_ADDR_Pos CPUSS_V2_CM0_PC2_HANDLER_ADDR_Pos 1451 #define CPUSS_CM0_PC2_HANDLER_ADDR_Msk CPUSS_V2_CM0_PC2_HANDLER_ADDR_Msk 1452 /* CPUSS.CM0_PC3_HANDLER */ 1453 #define CPUSS_CM0_PC3_HANDLER_ADDR_Pos CPUSS_V2_CM0_PC3_HANDLER_ADDR_Pos 1454 #define CPUSS_CM0_PC3_HANDLER_ADDR_Msk CPUSS_V2_CM0_PC3_HANDLER_ADDR_Msk 1455 /* CPUSS.PROTECTION */ 1456 #define CPUSS_PROTECTION_STATE_Pos CPUSS_V2_PROTECTION_STATE_Pos 1457 #define CPUSS_PROTECTION_STATE_Msk CPUSS_V2_PROTECTION_STATE_Msk 1458 /* CPUSS.TRIM_ROM_CTL */ 1459 #define CPUSS_TRIM_ROM_CTL_TRIM_Pos CPUSS_V2_TRIM_ROM_CTL_TRIM_Pos 1460 #define CPUSS_TRIM_ROM_CTL_TRIM_Msk CPUSS_V2_TRIM_ROM_CTL_TRIM_Msk 1461 /* CPUSS.TRIM_RAM_CTL */ 1462 #define CPUSS_TRIM_RAM_CTL_TRIM_Pos CPUSS_V2_TRIM_RAM_CTL_TRIM_Pos 1463 #define CPUSS_TRIM_RAM_CTL_TRIM_Msk CPUSS_V2_TRIM_RAM_CTL_TRIM_Msk 1464 /* CPUSS.CM0_SYSTEM_INT_CTL */ 1465 #define CPUSS_CM0_SYSTEM_INT_CTL_CPU_INT_IDX_Pos CPUSS_V2_CM0_SYSTEM_INT_CTL_CPU_INT_IDX_Pos 1466 #define CPUSS_CM0_SYSTEM_INT_CTL_CPU_INT_IDX_Msk CPUSS_V2_CM0_SYSTEM_INT_CTL_CPU_INT_IDX_Msk 1467 #define CPUSS_CM0_SYSTEM_INT_CTL_CPU_INT_VALID_Pos CPUSS_V2_CM0_SYSTEM_INT_CTL_CPU_INT_VALID_Pos 1468 #define CPUSS_CM0_SYSTEM_INT_CTL_CPU_INT_VALID_Msk CPUSS_V2_CM0_SYSTEM_INT_CTL_CPU_INT_VALID_Msk 1469 /* CPUSS.CM4_SYSTEM_INT_CTL */ 1470 #define CPUSS_CM4_SYSTEM_INT_CTL_CPU_INT_IDX_Pos CPUSS_V2_CM4_SYSTEM_INT_CTL_CPU_INT_IDX_Pos 1471 #define CPUSS_CM4_SYSTEM_INT_CTL_CPU_INT_IDX_Msk CPUSS_V2_CM4_SYSTEM_INT_CTL_CPU_INT_IDX_Msk 1472 #define CPUSS_CM4_SYSTEM_INT_CTL_CPU_INT_VALID_Pos CPUSS_V2_CM4_SYSTEM_INT_CTL_CPU_INT_VALID_Pos 1473 #define CPUSS_CM4_SYSTEM_INT_CTL_CPU_INT_VALID_Msk CPUSS_V2_CM4_SYSTEM_INT_CTL_CPU_INT_VALID_Msk 1474 1475 /******************************************************************************* 1476 * FAULT 1477 *******************************************************************************/ 1478 /* FAULT_STRUCT.CTL */ 1479 #define FAULT_STRUCT_CTL_TR_EN_Pos FAULT_STRUCT_V2_CTL_TR_EN_Pos 1480 #define FAULT_STRUCT_CTL_TR_EN_Msk FAULT_STRUCT_V2_CTL_TR_EN_Msk 1481 #define FAULT_STRUCT_CTL_OUT_EN_Pos FAULT_STRUCT_V2_CTL_OUT_EN_Pos 1482 #define FAULT_STRUCT_CTL_OUT_EN_Msk FAULT_STRUCT_V2_CTL_OUT_EN_Msk 1483 #define FAULT_STRUCT_CTL_RESET_REQ_EN_Pos FAULT_STRUCT_V2_CTL_RESET_REQ_EN_Pos 1484 #define FAULT_STRUCT_CTL_RESET_REQ_EN_Msk FAULT_STRUCT_V2_CTL_RESET_REQ_EN_Msk 1485 /* FAULT_STRUCT.STATUS */ 1486 #define FAULT_STRUCT_STATUS_IDX_Pos FAULT_STRUCT_V2_STATUS_IDX_Pos 1487 #define FAULT_STRUCT_STATUS_IDX_Msk FAULT_STRUCT_V2_STATUS_IDX_Msk 1488 #define FAULT_STRUCT_STATUS_VALID_Pos FAULT_STRUCT_V2_STATUS_VALID_Pos 1489 #define FAULT_STRUCT_STATUS_VALID_Msk FAULT_STRUCT_V2_STATUS_VALID_Msk 1490 /* FAULT_STRUCT.DATA */ 1491 #define FAULT_STRUCT_DATA_DATA_Pos FAULT_STRUCT_V2_DATA_DATA_Pos 1492 #define FAULT_STRUCT_DATA_DATA_Msk FAULT_STRUCT_V2_DATA_DATA_Msk 1493 /* FAULT_STRUCT.PENDING0 */ 1494 #define FAULT_STRUCT_PENDING0_SOURCE_Pos FAULT_STRUCT_V2_PENDING0_SOURCE_Pos 1495 #define FAULT_STRUCT_PENDING0_SOURCE_Msk FAULT_STRUCT_V2_PENDING0_SOURCE_Msk 1496 /* FAULT_STRUCT.PENDING1 */ 1497 #define FAULT_STRUCT_PENDING1_SOURCE_Pos FAULT_STRUCT_V2_PENDING1_SOURCE_Pos 1498 #define FAULT_STRUCT_PENDING1_SOURCE_Msk FAULT_STRUCT_V2_PENDING1_SOURCE_Msk 1499 /* FAULT_STRUCT.PENDING2 */ 1500 #define FAULT_STRUCT_PENDING2_SOURCE_Pos FAULT_STRUCT_V2_PENDING2_SOURCE_Pos 1501 #define FAULT_STRUCT_PENDING2_SOURCE_Msk FAULT_STRUCT_V2_PENDING2_SOURCE_Msk 1502 /* FAULT_STRUCT.MASK0 */ 1503 #define FAULT_STRUCT_MASK0_SOURCE_Pos FAULT_STRUCT_V2_MASK0_SOURCE_Pos 1504 #define FAULT_STRUCT_MASK0_SOURCE_Msk FAULT_STRUCT_V2_MASK0_SOURCE_Msk 1505 /* FAULT_STRUCT.MASK1 */ 1506 #define FAULT_STRUCT_MASK1_SOURCE_Pos FAULT_STRUCT_V2_MASK1_SOURCE_Pos 1507 #define FAULT_STRUCT_MASK1_SOURCE_Msk FAULT_STRUCT_V2_MASK1_SOURCE_Msk 1508 /* FAULT_STRUCT.MASK2 */ 1509 #define FAULT_STRUCT_MASK2_SOURCE_Pos FAULT_STRUCT_V2_MASK2_SOURCE_Pos 1510 #define FAULT_STRUCT_MASK2_SOURCE_Msk FAULT_STRUCT_V2_MASK2_SOURCE_Msk 1511 /* FAULT_STRUCT.INTR */ 1512 #define FAULT_STRUCT_INTR_FAULT_Pos FAULT_STRUCT_V2_INTR_FAULT_Pos 1513 #define FAULT_STRUCT_INTR_FAULT_Msk FAULT_STRUCT_V2_INTR_FAULT_Msk 1514 /* FAULT_STRUCT.INTR_SET */ 1515 #define FAULT_STRUCT_INTR_SET_FAULT_Pos FAULT_STRUCT_V2_INTR_SET_FAULT_Pos 1516 #define FAULT_STRUCT_INTR_SET_FAULT_Msk FAULT_STRUCT_V2_INTR_SET_FAULT_Msk 1517 /* FAULT_STRUCT.INTR_MASK */ 1518 #define FAULT_STRUCT_INTR_MASK_FAULT_Pos FAULT_STRUCT_V2_INTR_MASK_FAULT_Pos 1519 #define FAULT_STRUCT_INTR_MASK_FAULT_Msk FAULT_STRUCT_V2_INTR_MASK_FAULT_Msk 1520 /* FAULT_STRUCT.INTR_MASKED */ 1521 #define FAULT_STRUCT_INTR_MASKED_FAULT_Pos FAULT_STRUCT_V2_INTR_MASKED_FAULT_Pos 1522 #define FAULT_STRUCT_INTR_MASKED_FAULT_Msk FAULT_STRUCT_V2_INTR_MASKED_FAULT_Msk 1523 1524 /******************************************************************************* 1525 * FLASH 1526 *******************************************************************************/ 1527 #define FLASHC_FLASH_CTL_MAIN_WS_Pos FLASHC_V2_FLASH_CTL_MAIN_WS_Pos 1528 #define FLASHC_FLASH_CTL_MAIN_WS_Msk FLASHC_V2_FLASH_CTL_MAIN_WS_Msk 1529 1530 #define FLASHC_FLASH_CTL_MAIN_MAP_Pos FLASHC_V2_FLASH_CTL_MAIN_MAP_Pos 1531 #define FLASHC_FLASH_CTL_MAIN_MAP_Msk FLASHC_V2_FLASH_CTL_MAIN_MAP_Msk 1532 #define FLASHC_FLASH_CTL_WORK_MAP_Pos FLASHC_V2_FLASH_CTL_WORK_MAP_Pos 1533 #define FLASHC_FLASH_CTL_WORK_MAP_Msk FLASHC_V2_FLASH_CTL_WORK_MAP_Msk 1534 #define FLASHC_FLASH_CTL_MAIN_BANK_MODE_Pos FLASHC_V2_FLASH_CTL_MAIN_BANK_MODE_Pos 1535 #define FLASHC_FLASH_CTL_MAIN_BANK_MODE_Msk FLASHC_V2_FLASH_CTL_MAIN_BANK_MODE_Msk 1536 #define FLASHC_FLASH_CTL_WORK_BANK_MODE_Pos FLASHC_V2_FLASH_CTL_WORK_BANK_MODE_Pos 1537 #define FLASHC_FLASH_CTL_WORK_BANK_MODE_Msk FLASHC_V2_FLASH_CTL_WORK_BANK_MODE_Msk 1538 #define FLASHC_FLASH_CMD_INV_Msk FLASHC_V2_FLASH_CMD_INV_Msk 1539 #define FLASHC_FLASH_CMD_INV_Pos FLASHC_V2_FLASH_CMD_INV_Pos 1540 #define FLASHC_FM_CTL_ECT_STATUS_PGM_WORK_Msk FLASHC_FM_CTL_ECT_V2_STATUS_PGM_WORK_Msk 1541 #define FLASHC_FM_CTL_ECT_STATUS_PGM_CODE_Msk FLASHC_FM_CTL_ECT_V2_STATUS_PGM_CODE_Msk 1542 #define FLASHC_FM_CTL_ECT_STATUS_BLANK_CHECK_WORK_Msk FLASHC_FM_CTL_ECT_V2_STATUS_BLANK_CHECK_WORK_Msk 1543 #define FLASHC_FM_CTL_ECT_STATUS_ERASE_CODE_Msk FLASHC_FM_CTL_ECT_V2_STATUS_ERASE_CODE_Msk 1544 #define FLASHC_FM_CTL_ECT_STATUS_ERASE_WORK_Msk FLASHC_FM_CTL_ECT_V2_STATUS_ERASE_WORK_Msk 1545 #define FLASHC_FM_CTL_ECT_MAIN_FLASH_SAFETY_MAINFLASHWRITEENABLE_Msk FLASHC_FM_CTL_ECT_V2_MAIN_FLASH_SAFETY_MAINFLASHWRITEENABLE_Msk 1546 #define FLASHC_FM_CTL_ECT_WORK_FLASH_SAFETY_WORKFLASHWRITEENABLE_Msk FLASHC_FM_CTL_ECT_V2_WORK_FLASH_SAFETY_WORKFLASHWRITEENABLE_Msk 1547 #define FLASHC_FLASH_CTL_MAIN_ECC_INJ_EN FLASHC_V2_FLASH_CTL_MAIN_ECC_INJ_EN 1548 #define FLASHC_FLASH_CTL_MAIN_ECC_INJ_EN_Pos FLASHC_V2_FLASH_CTL_MAIN_ECC_INJ_EN_Pos 1549 #define FLASHC_FLASH_CTL_MAIN_ECC_INJ_EN_Msk FLASHC_V2_FLASH_CTL_MAIN_ECC_INJ_EN_Msk 1550 #define FLASHC_FLASH_CTL_WORK_ECC_INJ_EN_Pos FLASHC_V2_FLASH_CTL_WORK_ECC_INJ_EN_Pos 1551 #define FLASHC_FLASH_CTL_WORK_ECC_INJ_EN_Msk FLASHC_V2_FLASH_CTL_WORK_ECC_INJ_EN_Msk 1552 #define FLASHC_CM0_CA_CTL0_RAM_ECC_INJ_EN_Pos FLASHC_V2_CM0_CA_CTL0_RAM_ECC_INJ_EN_Pos 1553 #define FLASHC_ECC_CTL_WORD_ADDR FLASHC_V2_ECC_CTL_WORD_ADDR 1554 #define FLASHC_ECC_CTL_PARITY FLASHC_V2_ECC_CTL_PARITY 1555 #define FLASHC_FLASH_CTL_WORK_ECC_EN_Msk FLASHC_V2_FLASH_CTL_WORK_ECC_EN_Msk 1556 #define FLASHC_ECC_CTL_WORD_ADDR_Pos FLASHC_V2_ECC_CTL_WORD_ADDR_Pos 1557 #define FLASHC_ECC_CTL_WORD_ADDR_Msk FLASHC_V2_ECC_CTL_WORD_ADDR_Msk 1558 #define FLASHC_ECC_CTL_PARITY_Pos FLASHC_V2_ECC_CTL_PARITY_Pos 1559 #define FLASHC_ECC_CTL_PARITY_Msk FLASHC_V2_ECC_CTL_PARITY_Msk 1560 #define FLASHC_CM0_CA_CTL0_RAM_ECC_INJ_EN_Msk FLASHC_V2_CM0_CA_CTL0_RAM_ECC_INJ_EN_Msk 1561 #define FLASHC_FLASH_CTL_MAIN_ECC_EN_Msk FLASHC_V2_FLASH_CTL_MAIN_ECC_EN_Msk 1562 1563 /******************************************************************************* 1564 * DW 1565 *******************************************************************************/ 1566 /* DW_CH_STRUCT.CH_CTL */ 1567 #define DW_CH_STRUCT_CH_CTL_P_Pos DW_CH_STRUCT_V2_CH_CTL_P_Pos 1568 #define DW_CH_STRUCT_CH_CTL_P_Msk DW_CH_STRUCT_V2_CH_CTL_P_Msk 1569 #define DW_CH_STRUCT_CH_CTL_NS_Pos DW_CH_STRUCT_V2_CH_CTL_NS_Pos 1570 #define DW_CH_STRUCT_CH_CTL_NS_Msk DW_CH_STRUCT_V2_CH_CTL_NS_Msk 1571 #define DW_CH_STRUCT_CH_CTL_B_Pos DW_CH_STRUCT_V2_CH_CTL_B_Pos 1572 #define DW_CH_STRUCT_CH_CTL_B_Msk DW_CH_STRUCT_V2_CH_CTL_B_Msk 1573 #define DW_CH_STRUCT_CH_CTL_PC_Pos DW_CH_STRUCT_V2_CH_CTL_PC_Pos 1574 #define DW_CH_STRUCT_CH_CTL_PC_Msk DW_CH_STRUCT_V2_CH_CTL_PC_Msk 1575 #define DW_CH_STRUCT_CH_CTL_PRIO_Pos DW_CH_STRUCT_V2_CH_CTL_PRIO_Pos 1576 #define DW_CH_STRUCT_CH_CTL_PRIO_Msk DW_CH_STRUCT_V2_CH_CTL_PRIO_Msk 1577 #define DW_CH_STRUCT_CH_CTL_PREEMPTABLE_Pos DW_CH_STRUCT_V2_CH_CTL_PREEMPTABLE_Pos 1578 #define DW_CH_STRUCT_CH_CTL_PREEMPTABLE_Msk DW_CH_STRUCT_V2_CH_CTL_PREEMPTABLE_Msk 1579 #define DW_CH_STRUCT_CH_CTL_ENABLED_Pos DW_CH_STRUCT_V2_CH_CTL_ENABLED_Pos 1580 #define DW_CH_STRUCT_CH_CTL_ENABLED_Msk DW_CH_STRUCT_V2_CH_CTL_ENABLED_Msk 1581 /* DW_CH_STRUCT.CH_STATUS */ 1582 #define DW_CH_STRUCT_CH_STATUS_INTR_CAUSE_Pos DW_CH_STRUCT_V2_CH_STATUS_INTR_CAUSE_Pos 1583 #define DW_CH_STRUCT_CH_STATUS_INTR_CAUSE_Msk DW_CH_STRUCT_V2_CH_STATUS_INTR_CAUSE_Msk 1584 #define DW_CH_STRUCT_CH_STATUS_PENDING_Pos DW_CH_STRUCT_V2_CH_STATUS_PENDING_Pos 1585 #define DW_CH_STRUCT_CH_STATUS_PENDING_Msk DW_CH_STRUCT_V2_CH_STATUS_PENDING_Msk 1586 /* DW_CH_STRUCT.CH_IDX */ 1587 #define DW_CH_STRUCT_CH_IDX_X_IDX_Pos DW_CH_STRUCT_V2_CH_IDX_X_IDX_Pos 1588 #define DW_CH_STRUCT_CH_IDX_X_IDX_Msk DW_CH_STRUCT_V2_CH_IDX_X_IDX_Msk 1589 #define DW_CH_STRUCT_CH_IDX_Y_IDX_Pos DW_CH_STRUCT_V2_CH_IDX_Y_IDX_Pos 1590 #define DW_CH_STRUCT_CH_IDX_Y_IDX_Msk DW_CH_STRUCT_V2_CH_IDX_Y_IDX_Msk 1591 /* DW_CH_STRUCT.CH_CURR_PTR */ 1592 #define DW_CH_STRUCT_CH_CURR_PTR_ADDR_Pos DW_CH_STRUCT_V2_CH_CURR_PTR_ADDR_Pos 1593 #define DW_CH_STRUCT_CH_CURR_PTR_ADDR_Msk DW_CH_STRUCT_V2_CH_CURR_PTR_ADDR_Msk 1594 /* DW_CH_STRUCT.INTR */ 1595 #define DW_CH_STRUCT_INTR_CH_Pos DW_CH_STRUCT_V2_INTR_CH_Pos 1596 #define DW_CH_STRUCT_INTR_CH_Msk DW_CH_STRUCT_V2_INTR_CH_Msk 1597 /* DW_CH_STRUCT.INTR_SET */ 1598 #define DW_CH_STRUCT_INTR_SET_CH_Pos DW_CH_STRUCT_V2_INTR_SET_CH_Pos 1599 #define DW_CH_STRUCT_INTR_SET_CH_Msk DW_CH_STRUCT_V2_INTR_SET_CH_Msk 1600 /* DW_CH_STRUCT.INTR_MASK */ 1601 #define DW_CH_STRUCT_INTR_MASK_CH_Pos DW_CH_STRUCT_V2_INTR_MASK_CH_Pos 1602 #define DW_CH_STRUCT_INTR_MASK_CH_Msk DW_CH_STRUCT_V2_INTR_MASK_CH_Msk 1603 /* DW_CH_STRUCT.INTR_MASKED */ 1604 #define DW_CH_STRUCT_INTR_MASKED_CH_Pos DW_CH_STRUCT_V2_INTR_MASKED_CH_Pos 1605 #define DW_CH_STRUCT_INTR_MASKED_CH_Msk DW_CH_STRUCT_V2_INTR_MASKED_CH_Msk 1606 /* DW_CH_STRUCT.SRAM_DATA0 */ 1607 #define DW_CH_STRUCT_SRAM_DATA0_DATA_Pos DW_CH_STRUCT_V2_SRAM_DATA0_DATA_Pos 1608 #define DW_CH_STRUCT_SRAM_DATA0_DATA_Msk DW_CH_STRUCT_V2_SRAM_DATA0_DATA_Msk 1609 /* DW_CH_STRUCT.SRAM_DATA1 */ 1610 #define DW_CH_STRUCT_SRAM_DATA1_DATA_Pos DW_CH_STRUCT_V2_SRAM_DATA1_DATA_Pos 1611 #define DW_CH_STRUCT_SRAM_DATA1_DATA_Msk DW_CH_STRUCT_V2_SRAM_DATA1_DATA_Msk 1612 /* DW_CH_STRUCT.TR_CMD */ 1613 #define DW_CH_STRUCT_TR_CMD_ACTIVATE_Pos DW_CH_STRUCT_V2_TR_CMD_ACTIVATE_Pos 1614 #define DW_CH_STRUCT_TR_CMD_ACTIVATE_Msk DW_CH_STRUCT_V2_TR_CMD_ACTIVATE_Msk 1615 /* DW.CTL */ 1616 #define DW_CTL_ECC_EN_Pos DW_CTL_ECC_EN_Pos 1617 #define DW_CTL_ECC_EN_Msk 0x1UL 1618 #define DW_CTL_ECC_INJ_EN_Pos DW_V2_CTL_ECC_INJ_EN_Pos 1619 #define DW_CTL_ECC_INJ_EN_Msk DW_V2_CTL_ECC_INJ_EN_Msk 1620 #define DW_CTL_ENABLED_Pos DW_V2_CTL_ENABLED_Pos 1621 #define DW_CTL_ENABLED_Msk DW_V2_CTL_ENABLED_Msk 1622 /* DW.STATUS */ 1623 #define DW_STATUS_P_Pos DW_V2_STATUS_P_Pos 1624 #define DW_STATUS_P_Msk DW_V2_STATUS_P_Msk 1625 #define DW_STATUS_NS_Pos DW_V2_STATUS_NS_Pos 1626 #define DW_STATUS_NS_Msk DW_V2_STATUS_NS_Msk 1627 #define DW_STATUS_B_Pos DW_V2_STATUS_B_Pos 1628 #define DW_STATUS_B_Msk DW_V2_STATUS_B_Msk 1629 #define DW_STATUS_PC_Pos DW_V2_STATUS_PC_Pos 1630 #define DW_STATUS_PC_Msk DW_V2_STATUS_PC_Msk 1631 #define DW_STATUS_PRIO_Pos DW_V2_STATUS_PRIO_Pos 1632 #define DW_STATUS_PRIO_Msk DW_V2_STATUS_PRIO_Msk 1633 #define DW_STATUS_PREEMPTABLE_Pos DW_V2_STATUS_PREEMPTABLE_Pos 1634 #define DW_STATUS_PREEMPTABLE_Msk DW_V2_STATUS_PREEMPTABLE_Msk 1635 #define DW_STATUS_CH_IDX_Pos DW_V2_STATUS_CH_IDX_Pos 1636 #define DW_STATUS_CH_IDX_Msk DW_V2_STATUS_CH_IDX_Msk 1637 #define DW_STATUS_STATE_Pos DW_V2_STATUS_STATE_Pos 1638 #define DW_STATUS_STATE_Msk DW_V2_STATUS_STATE_Msk 1639 #define DW_STATUS_ACTIVE_Pos DW_V2_STATUS_ACTIVE_Pos 1640 #define DW_STATUS_ACTIVE_Msk DW_V2_STATUS_ACTIVE_Msk 1641 /* DW.ACT_DESCR_CTL */ 1642 #define DW_ACT_DESCR_CTL_DATA_Pos DW_V2_ACT_DESCR_CTL_DATA_Pos 1643 #define DW_ACT_DESCR_CTL_DATA_Msk DW_V2_ACT_DESCR_CTL_DATA_Msk 1644 /* DW.ACT_DESCR_SRC */ 1645 #define DW_ACT_DESCR_SRC_DATA_Pos DW_V2_ACT_DESCR_SRC_DATA_Pos 1646 #define DW_ACT_DESCR_SRC_DATA_Msk DW_V2_ACT_DESCR_SRC_DATA_Msk 1647 /* DW.ACT_DESCR_DST */ 1648 #define DW_ACT_DESCR_DST_DATA_Pos DW_V2_ACT_DESCR_DST_DATA_Pos 1649 #define DW_ACT_DESCR_DST_DATA_Msk DW_V2_ACT_DESCR_DST_DATA_Msk 1650 /* DW.ACT_DESCR_X_CTL */ 1651 #define DW_ACT_DESCR_X_CTL_DATA_Pos DW_V2_ACT_DESCR_X_CTL_DATA_Pos 1652 #define DW_ACT_DESCR_X_CTL_DATA_Msk DW_V2_ACT_DESCR_X_CTL_DATA_Msk 1653 /* DW.ACT_DESCR_Y_CTL */ 1654 #define DW_ACT_DESCR_Y_CTL_DATA_Pos DW_V2_ACT_DESCR_Y_CTL_DATA_Pos 1655 #define DW_ACT_DESCR_Y_CTL_DATA_Msk DW_V2_ACT_DESCR_Y_CTL_DATA_Msk 1656 /* DW.ACT_DESCR_NEXT_PTR */ 1657 #define DW_ACT_DESCR_NEXT_PTR_ADDR_Pos DW_V2_ACT_DESCR_NEXT_PTR_ADDR_Pos 1658 #define DW_ACT_DESCR_NEXT_PTR_ADDR_Msk DW_V2_ACT_DESCR_NEXT_PTR_ADDR_Msk 1659 /* DW.ACT_SRC */ 1660 #define DW_ACT_SRC_SRC_ADDR_Pos DW_V2_ACT_SRC_SRC_ADDR_Pos 1661 #define DW_ACT_SRC_SRC_ADDR_Msk DW_V2_ACT_SRC_SRC_ADDR_Msk 1662 /* DW.ACT_DST */ 1663 #define DW_ACT_DST_DST_ADDR_Pos DW_V2_ACT_DST_DST_ADDR_Pos 1664 #define DW_ACT_DST_DST_ADDR_Msk DW_V2_ACT_DST_DST_ADDR_Msk 1665 /* DW.ECC_CTL */ 1666 #define DW_ECC_CTL_WORD_ADDR_Pos DW_V2_ECC_CTL_WORD_ADDR_Pos 1667 #define DW_ECC_CTL_WORD_ADDR_Msk DW_V2_ECC_CTL_WORD_ADDR_Msk 1668 #define DW_ECC_CTL_PARITY_Pos DW_V2_ECC_CTL_PARITY_Pos 1669 #define DW_ECC_CTL_PARITY_Msk DW_V2_ECC_CTL_PARITY_Msk 1670 /* DW.CRC_CTL */ 1671 #define DW_CRC_CTL_DATA_REVERSE_Pos DW_V2_CRC_CTL_DATA_REVERSE_Pos 1672 #define DW_CRC_CTL_DATA_REVERSE_Msk DW_V2_CRC_CTL_DATA_REVERSE_Msk 1673 #define DW_CRC_CTL_REM_REVERSE_Pos DW_V2_CRC_CTL_REM_REVERSE_Pos 1674 #define DW_CRC_CTL_REM_REVERSE_Msk DW_V2_CRC_CTL_REM_REVERSE_Msk 1675 /* DW.CRC_DATA_CTL */ 1676 #define DW_CRC_DATA_CTL_DATA_XOR_Pos DW_V2_CRC_DATA_CTL_DATA_XOR_Pos 1677 #define DW_CRC_DATA_CTL_DATA_XOR_Msk DW_V2_CRC_DATA_CTL_DATA_XOR_Msk 1678 /* DW.CRC_POL_CTL */ 1679 #define DW_CRC_POL_CTL_POLYNOMIAL_Pos DW_V2_CRC_POL_CTL_POLYNOMIAL_Pos 1680 #define DW_CRC_POL_CTL_POLYNOMIAL_Msk DW_V2_CRC_POL_CTL_POLYNOMIAL_Msk 1681 /* DW.CRC_LFSR_CTL */ 1682 #define DW_CRC_LFSR_CTL_LFSR32_Pos DW_V2_CRC_LFSR_CTL_LFSR32_Pos 1683 #define DW_CRC_LFSR_CTL_LFSR32_Msk DW_V2_CRC_LFSR_CTL_LFSR32_Msk 1684 /* DW.CRC_REM_CTL */ 1685 #define DW_CRC_REM_CTL_REM_XOR_Pos DW_V2_CRC_REM_CTL_REM_XOR_Pos 1686 #define DW_CRC_REM_CTL_REM_XOR_Msk DW_V2_CRC_REM_CTL_REM_XOR_Msk 1687 /* DW.CRC_REM_RESULT */ 1688 #define DW_CRC_REM_RESULT_REM_Pos DW_V2_CRC_REM_RESULT_REM_Pos 1689 #define DW_CRC_REM_RESULT_REM_Msk DW_V2_CRC_REM_RESULT_REM_Msk 1690 1691 1692 /******************************************************************************* 1693 * GPIO 1694 *******************************************************************************/ 1695 #define GPIO_PRT_SECTION_SIZE GPIO_PRT_V2_SECTION_SIZE 1696 #define GPIO_SECTION_SIZE GPIO_V2_SECTION_SIZE 1697 1698 /* GPIO_PRT.OUT */ 1699 #define GPIO_PRT_OUT_OUT0_Pos GPIO_PRT_V2_OUT_OUT0_Pos 1700 #define GPIO_PRT_OUT_OUT0_Msk GPIO_PRT_V2_OUT_OUT0_Msk 1701 #define GPIO_PRT_OUT_OUT1_Pos GPIO_PRT_V2_OUT_OUT1_Pos 1702 #define GPIO_PRT_OUT_OUT1_Msk GPIO_PRT_V2_OUT_OUT1_Msk 1703 #define GPIO_PRT_OUT_OUT2_Pos GPIO_PRT_V2_OUT_OUT2_Pos 1704 #define GPIO_PRT_OUT_OUT2_Msk GPIO_PRT_V2_OUT_OUT2_Msk 1705 #define GPIO_PRT_OUT_OUT3_Pos GPIO_PRT_V2_OUT_OUT3_Pos 1706 #define GPIO_PRT_OUT_OUT3_Msk GPIO_PRT_V2_OUT_OUT3_Msk 1707 #define GPIO_PRT_OUT_OUT4_Pos GPIO_PRT_V2_OUT_OUT4_Pos 1708 #define GPIO_PRT_OUT_OUT4_Msk GPIO_PRT_V2_OUT_OUT4_Msk 1709 #define GPIO_PRT_OUT_OUT5_Pos GPIO_PRT_V2_OUT_OUT5_Pos 1710 #define GPIO_PRT_OUT_OUT5_Msk GPIO_PRT_V2_OUT_OUT5_Msk 1711 #define GPIO_PRT_OUT_OUT6_Pos GPIO_PRT_V2_OUT_OUT6_Pos 1712 #define GPIO_PRT_OUT_OUT6_Msk GPIO_PRT_V2_OUT_OUT6_Msk 1713 #define GPIO_PRT_OUT_OUT7_Pos GPIO_PRT_V2_OUT_OUT7_Pos 1714 #define GPIO_PRT_OUT_OUT7_Msk GPIO_PRT_V2_OUT_OUT7_Msk 1715 /* GPIO_PRT.OUT_CLR */ 1716 #define GPIO_PRT_OUT_CLR_OUT0_Pos GPIO_PRT_V2_OUT_CLR_OUT0_Pos 1717 #define GPIO_PRT_OUT_CLR_OUT0_Msk GPIO_PRT_V2_OUT_CLR_OUT0_Msk 1718 #define GPIO_PRT_OUT_CLR_OUT1_Pos GPIO_PRT_V2_OUT_CLR_OUT1_Pos 1719 #define GPIO_PRT_OUT_CLR_OUT1_Msk GPIO_PRT_V2_OUT_CLR_OUT1_Msk 1720 #define GPIO_PRT_OUT_CLR_OUT2_Pos GPIO_PRT_V2_OUT_CLR_OUT2_Pos 1721 #define GPIO_PRT_OUT_CLR_OUT2_Msk GPIO_PRT_V2_OUT_CLR_OUT2_Msk 1722 #define GPIO_PRT_OUT_CLR_OUT3_Pos GPIO_PRT_V2_OUT_CLR_OUT3_Pos 1723 #define GPIO_PRT_OUT_CLR_OUT3_Msk GPIO_PRT_V2_OUT_CLR_OUT3_Msk 1724 #define GPIO_PRT_OUT_CLR_OUT4_Pos GPIO_PRT_V2_OUT_CLR_OUT4_Pos 1725 #define GPIO_PRT_OUT_CLR_OUT4_Msk GPIO_PRT_V2_OUT_CLR_OUT4_Msk 1726 #define GPIO_PRT_OUT_CLR_OUT5_Pos GPIO_PRT_V2_OUT_CLR_OUT5_Pos 1727 #define GPIO_PRT_OUT_CLR_OUT5_Msk GPIO_PRT_V2_OUT_CLR_OUT5_Msk 1728 #define GPIO_PRT_OUT_CLR_OUT6_Pos GPIO_PRT_V2_OUT_CLR_OUT6_Pos 1729 #define GPIO_PRT_OUT_CLR_OUT6_Msk GPIO_PRT_V2_OUT_CLR_OUT6_Msk 1730 #define GPIO_PRT_OUT_CLR_OUT7_Pos GPIO_PRT_V2_OUT_CLR_OUT7_Pos 1731 #define GPIO_PRT_OUT_CLR_OUT7_Msk GPIO_PRT_V2_OUT_CLR_OUT7_Msk 1732 /* GPIO_PRT.OUT_SET */ 1733 #define GPIO_PRT_OUT_SET_OUT0_Pos GPIO_PRT_V2_OUT_SET_OUT0_Pos 1734 #define GPIO_PRT_OUT_SET_OUT0_Msk GPIO_PRT_V2_OUT_SET_OUT0_Msk 1735 #define GPIO_PRT_OUT_SET_OUT1_Pos GPIO_PRT_V2_OUT_SET_OUT1_Pos 1736 #define GPIO_PRT_OUT_SET_OUT1_Msk GPIO_PRT_V2_OUT_SET_OUT1_Msk 1737 #define GPIO_PRT_OUT_SET_OUT2_Pos GPIO_PRT_V2_OUT_SET_OUT2_Pos 1738 #define GPIO_PRT_OUT_SET_OUT2_Msk GPIO_PRT_V2_OUT_SET_OUT2_Msk 1739 #define GPIO_PRT_OUT_SET_OUT3_Pos GPIO_PRT_V2_OUT_SET_OUT3_Pos 1740 #define GPIO_PRT_OUT_SET_OUT3_Msk GPIO_PRT_V2_OUT_SET_OUT3_Msk 1741 #define GPIO_PRT_OUT_SET_OUT4_Pos GPIO_PRT_V2_OUT_SET_OUT4_Pos 1742 #define GPIO_PRT_OUT_SET_OUT4_Msk GPIO_PRT_V2_OUT_SET_OUT4_Msk 1743 #define GPIO_PRT_OUT_SET_OUT5_Pos GPIO_PRT_V2_OUT_SET_OUT5_Pos 1744 #define GPIO_PRT_OUT_SET_OUT5_Msk GPIO_PRT_V2_OUT_SET_OUT5_Msk 1745 #define GPIO_PRT_OUT_SET_OUT6_Pos GPIO_PRT_V2_OUT_SET_OUT6_Pos 1746 #define GPIO_PRT_OUT_SET_OUT6_Msk GPIO_PRT_V2_OUT_SET_OUT6_Msk 1747 #define GPIO_PRT_OUT_SET_OUT7_Pos GPIO_PRT_V2_OUT_SET_OUT7_Pos 1748 #define GPIO_PRT_OUT_SET_OUT7_Msk GPIO_PRT_V2_OUT_SET_OUT7_Msk 1749 /* GPIO_PRT.OUT_INV */ 1750 #define GPIO_PRT_OUT_INV_OUT0_Pos GPIO_PRT_V2_OUT_INV_OUT0_Pos 1751 #define GPIO_PRT_OUT_INV_OUT0_Msk GPIO_PRT_V2_OUT_INV_OUT0_Msk 1752 #define GPIO_PRT_OUT_INV_OUT1_Pos GPIO_PRT_V2_OUT_INV_OUT1_Pos 1753 #define GPIO_PRT_OUT_INV_OUT1_Msk GPIO_PRT_V2_OUT_INV_OUT1_Msk 1754 #define GPIO_PRT_OUT_INV_OUT2_Pos GPIO_PRT_V2_OUT_INV_OUT2_Pos 1755 #define GPIO_PRT_OUT_INV_OUT2_Msk GPIO_PRT_V2_OUT_INV_OUT2_Msk 1756 #define GPIO_PRT_OUT_INV_OUT3_Pos GPIO_PRT_V2_OUT_INV_OUT3_Pos 1757 #define GPIO_PRT_OUT_INV_OUT3_Msk GPIO_PRT_V2_OUT_INV_OUT3_Msk 1758 #define GPIO_PRT_OUT_INV_OUT4_Pos GPIO_PRT_V2_OUT_INV_OUT4_Pos 1759 #define GPIO_PRT_OUT_INV_OUT4_Msk GPIO_PRT_V2_OUT_INV_OUT4_Msk 1760 #define GPIO_PRT_OUT_INV_OUT5_Pos GPIO_PRT_V2_OUT_INV_OUT5_Pos 1761 #define GPIO_PRT_OUT_INV_OUT5_Msk GPIO_PRT_V2_OUT_INV_OUT5_Msk 1762 #define GPIO_PRT_OUT_INV_OUT6_Pos GPIO_PRT_V2_OUT_INV_OUT6_Pos 1763 #define GPIO_PRT_OUT_INV_OUT6_Msk GPIO_PRT_V2_OUT_INV_OUT6_Msk 1764 #define GPIO_PRT_OUT_INV_OUT7_Pos GPIO_PRT_V2_OUT_INV_OUT7_Pos 1765 #define GPIO_PRT_OUT_INV_OUT7_Msk GPIO_PRT_V2_OUT_INV_OUT7_Msk 1766 /* GPIO_PRT.IN */ 1767 #define GPIO_PRT_IN_IN0_Pos GPIO_PRT_V2_IN_IN0_Pos 1768 #define GPIO_PRT_IN_IN0_Msk GPIO_PRT_V2_IN_IN0_Msk 1769 #define GPIO_PRT_IN_IN1_Pos GPIO_PRT_V2_IN_IN1_Pos 1770 #define GPIO_PRT_IN_IN1_Msk GPIO_PRT_V2_IN_IN1_Msk 1771 #define GPIO_PRT_IN_IN2_Pos GPIO_PRT_V2_IN_IN2_Pos 1772 #define GPIO_PRT_IN_IN2_Msk GPIO_PRT_V2_IN_IN2_Msk 1773 #define GPIO_PRT_IN_IN3_Pos GPIO_PRT_V2_IN_IN3_Pos 1774 #define GPIO_PRT_IN_IN3_Msk GPIO_PRT_V2_IN_IN3_Msk 1775 #define GPIO_PRT_IN_IN4_Pos GPIO_PRT_V2_IN_IN4_Pos 1776 #define GPIO_PRT_IN_IN4_Msk GPIO_PRT_V2_IN_IN4_Msk 1777 #define GPIO_PRT_IN_IN5_Pos GPIO_PRT_V2_IN_IN5_Pos 1778 #define GPIO_PRT_IN_IN5_Msk GPIO_PRT_V2_IN_IN5_Msk 1779 #define GPIO_PRT_IN_IN6_Pos GPIO_PRT_V2_IN_IN6_Pos 1780 #define GPIO_PRT_IN_IN6_Msk GPIO_PRT_V2_IN_IN6_Msk 1781 #define GPIO_PRT_IN_IN7_Pos GPIO_PRT_V2_IN_IN7_Pos 1782 #define GPIO_PRT_IN_IN7_Msk GPIO_PRT_V2_IN_IN7_Msk 1783 #define GPIO_PRT_IN_FLT_IN_Pos GPIO_PRT_V2_IN_FLT_IN_Pos 1784 #define GPIO_PRT_IN_FLT_IN_Msk GPIO_PRT_V2_IN_FLT_IN_Msk 1785 /* GPIO_PRT.INTR */ 1786 #define GPIO_PRT_INTR_EDGE0_Pos GPIO_PRT_V2_INTR_EDGE0_Pos 1787 #define GPIO_PRT_INTR_EDGE0_Msk GPIO_PRT_V2_INTR_EDGE0_Msk 1788 #define GPIO_PRT_INTR_EDGE1_Pos GPIO_PRT_V2_INTR_EDGE1_Pos 1789 #define GPIO_PRT_INTR_EDGE1_Msk GPIO_PRT_V2_INTR_EDGE1_Msk 1790 #define GPIO_PRT_INTR_EDGE2_Pos GPIO_PRT_V2_INTR_EDGE2_Pos 1791 #define GPIO_PRT_INTR_EDGE2_Msk GPIO_PRT_V2_INTR_EDGE2_Msk 1792 #define GPIO_PRT_INTR_EDGE3_Pos GPIO_PRT_V2_INTR_EDGE3_Pos 1793 #define GPIO_PRT_INTR_EDGE3_Msk GPIO_PRT_V2_INTR_EDGE3_Msk 1794 #define GPIO_PRT_INTR_EDGE4_Pos GPIO_PRT_V2_INTR_EDGE4_Pos 1795 #define GPIO_PRT_INTR_EDGE4_Msk GPIO_PRT_V2_INTR_EDGE4_Msk 1796 #define GPIO_PRT_INTR_EDGE5_Pos GPIO_PRT_V2_INTR_EDGE5_Pos 1797 #define GPIO_PRT_INTR_EDGE5_Msk GPIO_PRT_V2_INTR_EDGE5_Msk 1798 #define GPIO_PRT_INTR_EDGE6_Pos GPIO_PRT_V2_INTR_EDGE6_Pos 1799 #define GPIO_PRT_INTR_EDGE6_Msk GPIO_PRT_V2_INTR_EDGE6_Msk 1800 #define GPIO_PRT_INTR_EDGE7_Pos GPIO_PRT_V2_INTR_EDGE7_Pos 1801 #define GPIO_PRT_INTR_EDGE7_Msk GPIO_PRT_V2_INTR_EDGE7_Msk 1802 #define GPIO_PRT_INTR_FLT_EDGE_Pos GPIO_PRT_V2_INTR_FLT_EDGE_Pos 1803 #define GPIO_PRT_INTR_FLT_EDGE_Msk GPIO_PRT_V2_INTR_FLT_EDGE_Msk 1804 #define GPIO_PRT_INTR_IN_IN0_Pos GPIO_PRT_V2_INTR_IN_IN0_Pos 1805 #define GPIO_PRT_INTR_IN_IN0_Msk GPIO_PRT_V2_INTR_IN_IN0_Msk 1806 #define GPIO_PRT_INTR_IN_IN1_Pos GPIO_PRT_V2_INTR_IN_IN1_Pos 1807 #define GPIO_PRT_INTR_IN_IN1_Msk GPIO_PRT_V2_INTR_IN_IN1_Msk 1808 #define GPIO_PRT_INTR_IN_IN2_Pos GPIO_PRT_V2_INTR_IN_IN2_Pos 1809 #define GPIO_PRT_INTR_IN_IN2_Msk GPIO_PRT_V2_INTR_IN_IN2_Msk 1810 #define GPIO_PRT_INTR_IN_IN3_Pos GPIO_PRT_V2_INTR_IN_IN3_Pos 1811 #define GPIO_PRT_INTR_IN_IN3_Msk GPIO_PRT_V2_INTR_IN_IN3_Msk 1812 #define GPIO_PRT_INTR_IN_IN4_Pos GPIO_PRT_V2_INTR_IN_IN4_Pos 1813 #define GPIO_PRT_INTR_IN_IN4_Msk GPIO_PRT_V2_INTR_IN_IN4_Msk 1814 #define GPIO_PRT_INTR_IN_IN5_Pos GPIO_PRT_V2_INTR_IN_IN5_Pos 1815 #define GPIO_PRT_INTR_IN_IN5_Msk GPIO_PRT_V2_INTR_IN_IN5_Msk 1816 #define GPIO_PRT_INTR_IN_IN6_Pos GPIO_PRT_V2_INTR_IN_IN6_Pos 1817 #define GPIO_PRT_INTR_IN_IN6_Msk GPIO_PRT_V2_INTR_IN_IN6_Msk 1818 #define GPIO_PRT_INTR_IN_IN7_Pos GPIO_PRT_V2_INTR_IN_IN7_Pos 1819 #define GPIO_PRT_INTR_IN_IN7_Msk GPIO_PRT_V2_INTR_IN_IN7_Msk 1820 #define GPIO_PRT_INTR_FLT_IN_IN_Pos GPIO_PRT_V2_INTR_FLT_IN_IN_Pos 1821 #define GPIO_PRT_INTR_FLT_IN_IN_Msk GPIO_PRT_V2_INTR_FLT_IN_IN_Msk 1822 /* GPIO_PRT.INTR_MASK */ 1823 #define GPIO_PRT_INTR_MASK_EDGE0_Pos GPIO_PRT_V2_INTR_MASK_EDGE0_Pos 1824 #define GPIO_PRT_INTR_MASK_EDGE0_Msk GPIO_PRT_V2_INTR_MASK_EDGE0_Msk 1825 #define GPIO_PRT_INTR_MASK_EDGE1_Pos GPIO_PRT_V2_INTR_MASK_EDGE1_Pos 1826 #define GPIO_PRT_INTR_MASK_EDGE1_Msk GPIO_PRT_V2_INTR_MASK_EDGE1_Msk 1827 #define GPIO_PRT_INTR_MASK_EDGE2_Pos GPIO_PRT_V2_INTR_MASK_EDGE2_Pos 1828 #define GPIO_PRT_INTR_MASK_EDGE2_Msk GPIO_PRT_V2_INTR_MASK_EDGE2_Msk 1829 #define GPIO_PRT_INTR_MASK_EDGE3_Pos GPIO_PRT_V2_INTR_MASK_EDGE3_Pos 1830 #define GPIO_PRT_INTR_MASK_EDGE3_Msk GPIO_PRT_V2_INTR_MASK_EDGE3_Msk 1831 #define GPIO_PRT_INTR_MASK_EDGE4_Pos GPIO_PRT_V2_INTR_MASK_EDGE4_Pos 1832 #define GPIO_PRT_INTR_MASK_EDGE4_Msk GPIO_PRT_V2_INTR_MASK_EDGE4_Msk 1833 #define GPIO_PRT_INTR_MASK_EDGE5_Pos GPIO_PRT_V2_INTR_MASK_EDGE5_Pos 1834 #define GPIO_PRT_INTR_MASK_EDGE5_Msk GPIO_PRT_V2_INTR_MASK_EDGE5_Msk 1835 #define GPIO_PRT_INTR_MASK_EDGE6_Pos GPIO_PRT_V2_INTR_MASK_EDGE6_Pos 1836 #define GPIO_PRT_INTR_MASK_EDGE6_Msk GPIO_PRT_V2_INTR_MASK_EDGE6_Msk 1837 #define GPIO_PRT_INTR_MASK_EDGE7_Pos GPIO_PRT_V2_INTR_MASK_EDGE7_Pos 1838 #define GPIO_PRT_INTR_MASK_EDGE7_Msk GPIO_PRT_V2_INTR_MASK_EDGE7_Msk 1839 #define GPIO_PRT_INTR_MASK_FLT_EDGE_Pos GPIO_PRT_V2_INTR_MASK_FLT_EDGE_Pos 1840 #define GPIO_PRT_INTR_MASK_FLT_EDGE_Msk GPIO_PRT_V2_INTR_MASK_FLT_EDGE_Msk 1841 /* GPIO_PRT.INTR_MASKED */ 1842 #define GPIO_PRT_INTR_MASKED_EDGE0_Pos GPIO_PRT_V2_INTR_MASKED_EDGE0_Pos 1843 #define GPIO_PRT_INTR_MASKED_EDGE0_Msk GPIO_PRT_V2_INTR_MASKED_EDGE0_Msk 1844 #define GPIO_PRT_INTR_MASKED_EDGE1_Pos GPIO_PRT_V2_INTR_MASKED_EDGE1_Pos 1845 #define GPIO_PRT_INTR_MASKED_EDGE1_Msk GPIO_PRT_V2_INTR_MASKED_EDGE1_Msk 1846 #define GPIO_PRT_INTR_MASKED_EDGE2_Pos GPIO_PRT_V2_INTR_MASKED_EDGE2_Pos 1847 #define GPIO_PRT_INTR_MASKED_EDGE2_Msk GPIO_PRT_V2_INTR_MASKED_EDGE2_Msk 1848 #define GPIO_PRT_INTR_MASKED_EDGE3_Pos GPIO_PRT_V2_INTR_MASKED_EDGE3_Pos 1849 #define GPIO_PRT_INTR_MASKED_EDGE3_Msk GPIO_PRT_V2_INTR_MASKED_EDGE3_Msk 1850 #define GPIO_PRT_INTR_MASKED_EDGE4_Pos GPIO_PRT_V2_INTR_MASKED_EDGE4_Pos 1851 #define GPIO_PRT_INTR_MASKED_EDGE4_Msk GPIO_PRT_V2_INTR_MASKED_EDGE4_Msk 1852 #define GPIO_PRT_INTR_MASKED_EDGE5_Pos GPIO_PRT_V2_INTR_MASKED_EDGE5_Pos 1853 #define GPIO_PRT_INTR_MASKED_EDGE5_Msk GPIO_PRT_V2_INTR_MASKED_EDGE5_Msk 1854 #define GPIO_PRT_INTR_MASKED_EDGE6_Pos GPIO_PRT_V2_INTR_MASKED_EDGE6_Pos 1855 #define GPIO_PRT_INTR_MASKED_EDGE6_Msk GPIO_PRT_V2_INTR_MASKED_EDGE6_Msk 1856 #define GPIO_PRT_INTR_MASKED_EDGE7_Pos GPIO_PRT_V2_INTR_MASKED_EDGE7_Pos 1857 #define GPIO_PRT_INTR_MASKED_EDGE7_Msk GPIO_PRT_V2_INTR_MASKED_EDGE7_Msk 1858 #define GPIO_PRT_INTR_MASKED_FLT_EDGE_Pos GPIO_PRT_V2_INTR_MASKED_FLT_EDGE_Pos 1859 #define GPIO_PRT_INTR_MASKED_FLT_EDGE_Msk GPIO_PRT_V2_INTR_MASKED_FLT_EDGE_Msk 1860 /* GPIO_PRT.INTR_SET */ 1861 #define GPIO_PRT_INTR_SET_EDGE0_Pos GPIO_PRT_V2_INTR_SET_EDGE0_Pos 1862 #define GPIO_PRT_INTR_SET_EDGE0_Msk GPIO_PRT_V2_INTR_SET_EDGE0_Msk 1863 #define GPIO_PRT_INTR_SET_EDGE1_Pos GPIO_PRT_V2_INTR_SET_EDGE1_Pos 1864 #define GPIO_PRT_INTR_SET_EDGE1_Msk GPIO_PRT_V2_INTR_SET_EDGE1_Msk 1865 #define GPIO_PRT_INTR_SET_EDGE2_Pos GPIO_PRT_V2_INTR_SET_EDGE2_Pos 1866 #define GPIO_PRT_INTR_SET_EDGE2_Msk GPIO_PRT_V2_INTR_SET_EDGE2_Msk 1867 #define GPIO_PRT_INTR_SET_EDGE3_Pos GPIO_PRT_V2_INTR_SET_EDGE3_Pos 1868 #define GPIO_PRT_INTR_SET_EDGE3_Msk GPIO_PRT_V2_INTR_SET_EDGE3_Msk 1869 #define GPIO_PRT_INTR_SET_EDGE4_Pos GPIO_PRT_V2_INTR_SET_EDGE4_Pos 1870 #define GPIO_PRT_INTR_SET_EDGE4_Msk GPIO_PRT_V2_INTR_SET_EDGE4_Msk 1871 #define GPIO_PRT_INTR_SET_EDGE5_Pos GPIO_PRT_V2_INTR_SET_EDGE5_Pos 1872 #define GPIO_PRT_INTR_SET_EDGE5_Msk GPIO_PRT_V2_INTR_SET_EDGE5_Msk 1873 #define GPIO_PRT_INTR_SET_EDGE6_Pos GPIO_PRT_V2_INTR_SET_EDGE6_Pos 1874 #define GPIO_PRT_INTR_SET_EDGE6_Msk GPIO_PRT_V2_INTR_SET_EDGE6_Msk 1875 #define GPIO_PRT_INTR_SET_EDGE7_Pos GPIO_PRT_V2_INTR_SET_EDGE7_Pos 1876 #define GPIO_PRT_INTR_SET_EDGE7_Msk GPIO_PRT_V2_INTR_SET_EDGE7_Msk 1877 #define GPIO_PRT_INTR_SET_FLT_EDGE_Pos GPIO_PRT_V2_INTR_SET_FLT_EDGE_Pos 1878 #define GPIO_PRT_INTR_SET_FLT_EDGE_Msk GPIO_PRT_V2_INTR_SET_FLT_EDGE_Msk 1879 /* GPIO_PRT.INTR_CFG */ 1880 #define GPIO_PRT_INTR_CFG_EDGE0_SEL_Pos GPIO_PRT_V2_INTR_CFG_EDGE0_SEL_Pos 1881 #define GPIO_PRT_INTR_CFG_EDGE0_SEL_Msk GPIO_PRT_V2_INTR_CFG_EDGE0_SEL_Msk 1882 #define GPIO_PRT_INTR_CFG_EDGE1_SEL_Pos GPIO_PRT_V2_INTR_CFG_EDGE1_SEL_Pos 1883 #define GPIO_PRT_INTR_CFG_EDGE1_SEL_Msk GPIO_PRT_V2_INTR_CFG_EDGE1_SEL_Msk 1884 #define GPIO_PRT_INTR_CFG_EDGE2_SEL_Pos GPIO_PRT_V2_INTR_CFG_EDGE2_SEL_Pos 1885 #define GPIO_PRT_INTR_CFG_EDGE2_SEL_Msk GPIO_PRT_V2_INTR_CFG_EDGE2_SEL_Msk 1886 #define GPIO_PRT_INTR_CFG_EDGE3_SEL_Pos GPIO_PRT_V2_INTR_CFG_EDGE3_SEL_Pos 1887 #define GPIO_PRT_INTR_CFG_EDGE3_SEL_Msk GPIO_PRT_V2_INTR_CFG_EDGE3_SEL_Msk 1888 #define GPIO_PRT_INTR_CFG_EDGE4_SEL_Pos GPIO_PRT_V2_INTR_CFG_EDGE4_SEL_Pos 1889 #define GPIO_PRT_INTR_CFG_EDGE4_SEL_Msk GPIO_PRT_V2_INTR_CFG_EDGE4_SEL_Msk 1890 #define GPIO_PRT_INTR_CFG_EDGE5_SEL_Pos GPIO_PRT_V2_INTR_CFG_EDGE5_SEL_Pos 1891 #define GPIO_PRT_INTR_CFG_EDGE5_SEL_Msk GPIO_PRT_V2_INTR_CFG_EDGE5_SEL_Msk 1892 #define GPIO_PRT_INTR_CFG_EDGE6_SEL_Pos GPIO_PRT_V2_INTR_CFG_EDGE6_SEL_Pos 1893 #define GPIO_PRT_INTR_CFG_EDGE6_SEL_Msk GPIO_PRT_V2_INTR_CFG_EDGE6_SEL_Msk 1894 #define GPIO_PRT_INTR_CFG_EDGE7_SEL_Pos GPIO_PRT_V2_INTR_CFG_EDGE7_SEL_Pos 1895 #define GPIO_PRT_INTR_CFG_EDGE7_SEL_Msk GPIO_PRT_V2_INTR_CFG_EDGE7_SEL_Msk 1896 #define GPIO_PRT_INTR_CFG_FLT_EDGE_SEL_Pos GPIO_PRT_V2_INTR_CFG_FLT_EDGE_SEL_Pos 1897 #define GPIO_PRT_INTR_CFG_FLT_EDGE_SEL_Msk GPIO_PRT_V2_INTR_CFG_FLT_EDGE_SEL_Msk 1898 #define GPIO_PRT_INTR_CFG_FLT_SEL_Pos GPIO_PRT_V2_INTR_CFG_FLT_SEL_Pos 1899 #define GPIO_PRT_INTR_CFG_FLT_SEL_Msk GPIO_PRT_V2_INTR_CFG_FLT_SEL_Msk 1900 /* GPIO_PRT.CFG */ 1901 #define GPIO_PRT_CFG_DRIVE_MODE0_Pos GPIO_PRT_V2_CFG_DRIVE_MODE0_Pos 1902 #define GPIO_PRT_CFG_DRIVE_MODE0_Msk GPIO_PRT_V2_CFG_DRIVE_MODE0_Msk 1903 #define GPIO_PRT_CFG_IN_EN0_Pos GPIO_PRT_V2_CFG_IN_EN0_Pos 1904 #define GPIO_PRT_CFG_IN_EN0_Msk GPIO_PRT_V2_CFG_IN_EN0_Msk 1905 #define GPIO_PRT_CFG_DRIVE_MODE1_Pos GPIO_PRT_V2_CFG_DRIVE_MODE1_Pos 1906 #define GPIO_PRT_CFG_DRIVE_MODE1_Msk GPIO_PRT_V2_CFG_DRIVE_MODE1_Msk 1907 #define GPIO_PRT_CFG_IN_EN1_Pos GPIO_PRT_V2_CFG_IN_EN1_Pos 1908 #define GPIO_PRT_CFG_IN_EN1_Msk GPIO_PRT_V2_CFG_IN_EN1_Msk 1909 #define GPIO_PRT_CFG_DRIVE_MODE2_Pos GPIO_PRT_V2_CFG_DRIVE_MODE2_Pos 1910 #define GPIO_PRT_CFG_DRIVE_MODE2_Msk GPIO_PRT_V2_CFG_DRIVE_MODE2_Msk 1911 #define GPIO_PRT_CFG_IN_EN2_Pos GPIO_PRT_V2_CFG_IN_EN2_Pos 1912 #define GPIO_PRT_CFG_IN_EN2_Msk GPIO_PRT_V2_CFG_IN_EN2_Msk 1913 #define GPIO_PRT_CFG_DRIVE_MODE3_Pos GPIO_PRT_V2_CFG_DRIVE_MODE3_Pos 1914 #define GPIO_PRT_CFG_DRIVE_MODE3_Msk GPIO_PRT_V2_CFG_DRIVE_MODE3_Msk 1915 #define GPIO_PRT_CFG_IN_EN3_Pos GPIO_PRT_V2_CFG_IN_EN3_Pos 1916 #define GPIO_PRT_CFG_IN_EN3_Msk GPIO_PRT_V2_CFG_IN_EN3_Msk 1917 #define GPIO_PRT_CFG_DRIVE_MODE4_Pos GPIO_PRT_V2_CFG_DRIVE_MODE4_Pos 1918 #define GPIO_PRT_CFG_DRIVE_MODE4_Msk GPIO_PRT_V2_CFG_DRIVE_MODE4_Msk 1919 #define GPIO_PRT_CFG_IN_EN4_Pos GPIO_PRT_V2_CFG_IN_EN4_Pos 1920 #define GPIO_PRT_CFG_IN_EN4_Msk GPIO_PRT_V2_CFG_IN_EN4_Msk 1921 #define GPIO_PRT_CFG_DRIVE_MODE5_Pos GPIO_PRT_V2_CFG_DRIVE_MODE5_Pos 1922 #define GPIO_PRT_CFG_DRIVE_MODE5_Msk GPIO_PRT_V2_CFG_DRIVE_MODE5_Msk 1923 #define GPIO_PRT_CFG_IN_EN5_Pos GPIO_PRT_V2_CFG_IN_EN5_Pos 1924 #define GPIO_PRT_CFG_IN_EN5_Msk GPIO_PRT_V2_CFG_IN_EN5_Msk 1925 #define GPIO_PRT_CFG_DRIVE_MODE6_Pos GPIO_PRT_V2_CFG_DRIVE_MODE6_Pos 1926 #define GPIO_PRT_CFG_DRIVE_MODE6_Msk GPIO_PRT_V2_CFG_DRIVE_MODE6_Msk 1927 #define GPIO_PRT_CFG_IN_EN6_Pos GPIO_PRT_V2_CFG_IN_EN6_Pos 1928 #define GPIO_PRT_CFG_IN_EN6_Msk GPIO_PRT_V2_CFG_IN_EN6_Msk 1929 #define GPIO_PRT_CFG_DRIVE_MODE7_Pos GPIO_PRT_V2_CFG_DRIVE_MODE7_Pos 1930 #define GPIO_PRT_CFG_DRIVE_MODE7_Msk GPIO_PRT_V2_CFG_DRIVE_MODE7_Msk 1931 #define GPIO_PRT_CFG_IN_EN7_Pos GPIO_PRT_V2_CFG_IN_EN7_Pos 1932 #define GPIO_PRT_CFG_IN_EN7_Msk GPIO_PRT_V2_CFG_IN_EN7_Msk 1933 /* GPIO_PRT.CFG_IN */ 1934 #define GPIO_PRT_CFG_IN_VTRIP_SEL0_0_Pos GPIO_PRT_V2_CFG_IN_VTRIP_SEL0_0_Pos 1935 #define GPIO_PRT_CFG_IN_VTRIP_SEL0_0_Msk GPIO_PRT_V2_CFG_IN_VTRIP_SEL0_0_Msk 1936 #define GPIO_PRT_CFG_IN_VTRIP_SEL1_0_Pos GPIO_PRT_V2_CFG_IN_VTRIP_SEL1_0_Pos 1937 #define GPIO_PRT_CFG_IN_VTRIP_SEL1_0_Msk GPIO_PRT_V2_CFG_IN_VTRIP_SEL1_0_Msk 1938 #define GPIO_PRT_CFG_IN_VTRIP_SEL2_0_Pos GPIO_PRT_V2_CFG_IN_VTRIP_SEL2_0_Pos 1939 #define GPIO_PRT_CFG_IN_VTRIP_SEL2_0_Msk GPIO_PRT_V2_CFG_IN_VTRIP_SEL2_0_Msk 1940 #define GPIO_PRT_CFG_IN_VTRIP_SEL3_0_Pos GPIO_PRT_V2_CFG_IN_VTRIP_SEL3_0_Pos 1941 #define GPIO_PRT_CFG_IN_VTRIP_SEL3_0_Msk GPIO_PRT_V2_CFG_IN_VTRIP_SEL3_0_Msk 1942 #define GPIO_PRT_CFG_IN_VTRIP_SEL4_0_Pos GPIO_PRT_V2_CFG_IN_VTRIP_SEL4_0_Pos 1943 #define GPIO_PRT_CFG_IN_VTRIP_SEL4_0_Msk GPIO_PRT_V2_CFG_IN_VTRIP_SEL4_0_Msk 1944 #define GPIO_PRT_CFG_IN_VTRIP_SEL5_0_Pos GPIO_PRT_V2_CFG_IN_VTRIP_SEL5_0_Pos 1945 #define GPIO_PRT_CFG_IN_VTRIP_SEL5_0_Msk GPIO_PRT_V2_CFG_IN_VTRIP_SEL5_0_Msk 1946 #define GPIO_PRT_CFG_IN_VTRIP_SEL6_0_Pos GPIO_PRT_V2_CFG_IN_VTRIP_SEL6_0_Pos 1947 #define GPIO_PRT_CFG_IN_VTRIP_SEL6_0_Msk GPIO_PRT_V2_CFG_IN_VTRIP_SEL6_0_Msk 1948 #define GPIO_PRT_CFG_IN_VTRIP_SEL7_0_Pos GPIO_PRT_V2_CFG_IN_VTRIP_SEL7_0_Pos 1949 #define GPIO_PRT_CFG_IN_VTRIP_SEL7_0_Msk GPIO_PRT_V2_CFG_IN_VTRIP_SEL7_0_Msk 1950 /* GPIO_PRT.CFG_OUT */ 1951 #define GPIO_PRT_CFG_OUT_SLOW0_Pos GPIO_PRT_V2_CFG_OUT_SLOW0_Pos 1952 #define GPIO_PRT_CFG_OUT_SLOW0_Msk GPIO_PRT_V2_CFG_OUT_SLOW0_Msk 1953 #define GPIO_PRT_CFG_OUT_SLOW1_Pos GPIO_PRT_V2_CFG_OUT_SLOW1_Pos 1954 #define GPIO_PRT_CFG_OUT_SLOW1_Msk GPIO_PRT_V2_CFG_OUT_SLOW1_Msk 1955 #define GPIO_PRT_CFG_OUT_SLOW2_Pos GPIO_PRT_V2_CFG_OUT_SLOW2_Pos 1956 #define GPIO_PRT_CFG_OUT_SLOW2_Msk GPIO_PRT_V2_CFG_OUT_SLOW2_Msk 1957 #define GPIO_PRT_CFG_OUT_SLOW3_Pos GPIO_PRT_V2_CFG_OUT_SLOW3_Pos 1958 #define GPIO_PRT_CFG_OUT_SLOW3_Msk GPIO_PRT_V2_CFG_OUT_SLOW3_Msk 1959 #define GPIO_PRT_CFG_OUT_SLOW4_Pos GPIO_PRT_V2_CFG_OUT_SLOW4_Pos 1960 #define GPIO_PRT_CFG_OUT_SLOW4_Msk GPIO_PRT_V2_CFG_OUT_SLOW4_Msk 1961 #define GPIO_PRT_CFG_OUT_SLOW5_Pos GPIO_PRT_V2_CFG_OUT_SLOW5_Pos 1962 #define GPIO_PRT_CFG_OUT_SLOW5_Msk GPIO_PRT_V2_CFG_OUT_SLOW5_Msk 1963 #define GPIO_PRT_CFG_OUT_SLOW6_Pos GPIO_PRT_V2_CFG_OUT_SLOW6_Pos 1964 #define GPIO_PRT_CFG_OUT_SLOW6_Msk GPIO_PRT_V2_CFG_OUT_SLOW6_Msk 1965 #define GPIO_PRT_CFG_OUT_SLOW7_Pos GPIO_PRT_V2_CFG_OUT_SLOW7_Pos 1966 #define GPIO_PRT_CFG_OUT_SLOW7_Msk GPIO_PRT_V2_CFG_OUT_SLOW7_Msk 1967 #define GPIO_PRT_CFG_OUT_DRIVE_SEL0_Pos GPIO_PRT_V2_CFG_OUT_DRIVE_SEL0_Pos 1968 #define GPIO_PRT_CFG_OUT_DRIVE_SEL0_Msk GPIO_PRT_V2_CFG_OUT_DRIVE_SEL0_Msk 1969 #define GPIO_PRT_CFG_OUT_DRIVE_SEL1_Pos GPIO_PRT_V2_CFG_OUT_DRIVE_SEL1_Pos 1970 #define GPIO_PRT_CFG_OUT_DRIVE_SEL1_Msk GPIO_PRT_V2_CFG_OUT_DRIVE_SEL1_Msk 1971 #define GPIO_PRT_CFG_OUT_DRIVE_SEL2_Pos GPIO_PRT_V2_CFG_OUT_DRIVE_SEL2_Pos 1972 #define GPIO_PRT_CFG_OUT_DRIVE_SEL2_Msk GPIO_PRT_V2_CFG_OUT_DRIVE_SEL2_Msk 1973 #define GPIO_PRT_CFG_OUT_DRIVE_SEL3_Pos GPIO_PRT_V2_CFG_OUT_DRIVE_SEL3_Pos 1974 #define GPIO_PRT_CFG_OUT_DRIVE_SEL3_Msk GPIO_PRT_V2_CFG_OUT_DRIVE_SEL3_Msk 1975 #define GPIO_PRT_CFG_OUT_DRIVE_SEL4_Pos GPIO_PRT_V2_CFG_OUT_DRIVE_SEL4_Pos 1976 #define GPIO_PRT_CFG_OUT_DRIVE_SEL4_Msk GPIO_PRT_V2_CFG_OUT_DRIVE_SEL4_Msk 1977 #define GPIO_PRT_CFG_OUT_DRIVE_SEL5_Pos GPIO_PRT_V2_CFG_OUT_DRIVE_SEL5_Pos 1978 #define GPIO_PRT_CFG_OUT_DRIVE_SEL5_Msk GPIO_PRT_V2_CFG_OUT_DRIVE_SEL5_Msk 1979 #define GPIO_PRT_CFG_OUT_DRIVE_SEL6_Pos GPIO_PRT_V2_CFG_OUT_DRIVE_SEL6_Pos 1980 #define GPIO_PRT_CFG_OUT_DRIVE_SEL6_Msk GPIO_PRT_V2_CFG_OUT_DRIVE_SEL6_Msk 1981 #define GPIO_PRT_CFG_OUT_DRIVE_SEL7_Pos GPIO_PRT_V2_CFG_OUT_DRIVE_SEL7_Pos 1982 #define GPIO_PRT_CFG_OUT_DRIVE_SEL7_Msk GPIO_PRT_V2_CFG_OUT_DRIVE_SEL7_Msk 1983 /* GPIO_PRT.CFG_SIO */ 1984 #define GPIO_PRT_CFG_SIO_VREG_EN01_Pos GPIO_PRT_V2_CFG_SIO_VREG_EN01_Pos 1985 #define GPIO_PRT_CFG_SIO_VREG_EN01_Msk GPIO_PRT_V2_CFG_SIO_VREG_EN01_Msk 1986 #define GPIO_PRT_CFG_SIO_IBUF_SEL01_Pos GPIO_PRT_V2_CFG_SIO_IBUF_SEL01_Pos 1987 #define GPIO_PRT_CFG_SIO_IBUF_SEL01_Msk GPIO_PRT_V2_CFG_SIO_IBUF_SEL01_Msk 1988 #define GPIO_PRT_CFG_SIO_VTRIP_SEL01_Pos GPIO_PRT_V2_CFG_SIO_VTRIP_SEL01_Pos 1989 #define GPIO_PRT_CFG_SIO_VTRIP_SEL01_Msk GPIO_PRT_V2_CFG_SIO_VTRIP_SEL01_Msk 1990 #define GPIO_PRT_CFG_SIO_VREF_SEL01_Pos GPIO_PRT_V2_CFG_SIO_VREF_SEL01_Pos 1991 #define GPIO_PRT_CFG_SIO_VREF_SEL01_Msk GPIO_PRT_V2_CFG_SIO_VREF_SEL01_Msk 1992 #define GPIO_PRT_CFG_SIO_VOH_SEL01_Pos GPIO_PRT_V2_CFG_SIO_VOH_SEL01_Pos 1993 #define GPIO_PRT_CFG_SIO_VOH_SEL01_Msk GPIO_PRT_V2_CFG_SIO_VOH_SEL01_Msk 1994 #define GPIO_PRT_CFG_SIO_VREG_EN23_Pos GPIO_PRT_V2_CFG_SIO_VREG_EN23_Pos 1995 #define GPIO_PRT_CFG_SIO_VREG_EN23_Msk GPIO_PRT_V2_CFG_SIO_VREG_EN23_Msk 1996 #define GPIO_PRT_CFG_SIO_IBUF_SEL23_Pos GPIO_PRT_V2_CFG_SIO_IBUF_SEL23_Pos 1997 #define GPIO_PRT_CFG_SIO_IBUF_SEL23_Msk GPIO_PRT_V2_CFG_SIO_IBUF_SEL23_Msk 1998 #define GPIO_PRT_CFG_SIO_VTRIP_SEL23_Pos GPIO_PRT_V2_CFG_SIO_VTRIP_SEL23_Pos 1999 #define GPIO_PRT_CFG_SIO_VTRIP_SEL23_Msk GPIO_PRT_V2_CFG_SIO_VTRIP_SEL23_Msk 2000 #define GPIO_PRT_CFG_SIO_VREF_SEL23_Pos GPIO_PRT_V2_CFG_SIO_VREF_SEL23_Pos 2001 #define GPIO_PRT_CFG_SIO_VREF_SEL23_Msk GPIO_PRT_V2_CFG_SIO_VREF_SEL23_Msk 2002 #define GPIO_PRT_CFG_SIO_VOH_SEL23_Pos GPIO_PRT_V2_CFG_SIO_VOH_SEL23_Pos 2003 #define GPIO_PRT_CFG_SIO_VOH_SEL23_Msk GPIO_PRT_V2_CFG_SIO_VOH_SEL23_Msk 2004 #define GPIO_PRT_CFG_SIO_VREG_EN45_Pos GPIO_PRT_V2_CFG_SIO_VREG_EN45_Pos 2005 #define GPIO_PRT_CFG_SIO_VREG_EN45_Msk GPIO_PRT_V2_CFG_SIO_VREG_EN45_Msk 2006 #define GPIO_PRT_CFG_SIO_IBUF_SEL45_Pos GPIO_PRT_V2_CFG_SIO_IBUF_SEL45_Pos 2007 #define GPIO_PRT_CFG_SIO_IBUF_SEL45_Msk GPIO_PRT_V2_CFG_SIO_IBUF_SEL45_Msk 2008 #define GPIO_PRT_CFG_SIO_VTRIP_SEL45_Pos GPIO_PRT_V2_CFG_SIO_VTRIP_SEL45_Pos 2009 #define GPIO_PRT_CFG_SIO_VTRIP_SEL45_Msk GPIO_PRT_V2_CFG_SIO_VTRIP_SEL45_Msk 2010 #define GPIO_PRT_CFG_SIO_VREF_SEL45_Pos GPIO_PRT_V2_CFG_SIO_VREF_SEL45_Pos 2011 #define GPIO_PRT_CFG_SIO_VREF_SEL45_Msk GPIO_PRT_V2_CFG_SIO_VREF_SEL45_Msk 2012 #define GPIO_PRT_CFG_SIO_VOH_SEL45_Pos GPIO_PRT_V2_CFG_SIO_VOH_SEL45_Pos 2013 #define GPIO_PRT_CFG_SIO_VOH_SEL45_Msk GPIO_PRT_V2_CFG_SIO_VOH_SEL45_Msk 2014 #define GPIO_PRT_CFG_SIO_VREG_EN67_Pos GPIO_PRT_V2_CFG_SIO_VREG_EN67_Pos 2015 #define GPIO_PRT_CFG_SIO_VREG_EN67_Msk GPIO_PRT_V2_CFG_SIO_VREG_EN67_Msk 2016 #define GPIO_PRT_CFG_SIO_IBUF_SEL67_Pos GPIO_PRT_V2_CFG_SIO_IBUF_SEL67_Pos 2017 #define GPIO_PRT_CFG_SIO_IBUF_SEL67_Msk GPIO_PRT_V2_CFG_SIO_IBUF_SEL67_Msk 2018 #define GPIO_PRT_CFG_SIO_VTRIP_SEL67_Pos GPIO_PRT_V2_CFG_SIO_VTRIP_SEL67_Pos 2019 #define GPIO_PRT_CFG_SIO_VTRIP_SEL67_Msk GPIO_PRT_V2_CFG_SIO_VTRIP_SEL67_Msk 2020 #define GPIO_PRT_CFG_SIO_VREF_SEL67_Pos GPIO_PRT_V2_CFG_SIO_VREF_SEL67_Pos 2021 #define GPIO_PRT_CFG_SIO_VREF_SEL67_Msk GPIO_PRT_V2_CFG_SIO_VREF_SEL67_Msk 2022 #define GPIO_PRT_CFG_SIO_VOH_SEL67_Pos GPIO_PRT_V2_CFG_SIO_VOH_SEL67_Pos 2023 #define GPIO_PRT_CFG_SIO_VOH_SEL67_Msk GPIO_PRT_V2_CFG_SIO_VOH_SEL67_Msk 2024 /* GPIO_PRT.CFG_IN_AUTOLVL */ 2025 #define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL0_1_Pos GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL0_1_Pos 2026 #define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL0_1_Msk GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL0_1_Msk 2027 #define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL1_1_Pos GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL1_1_Pos 2028 #define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL1_1_Msk GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL1_1_Msk 2029 #define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL2_1_Pos GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL2_1_Pos 2030 #define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL2_1_Msk GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL2_1_Msk 2031 #define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL3_1_Pos GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL3_1_Pos 2032 #define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL3_1_Msk GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL3_1_Msk 2033 #define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL4_1_Pos GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL4_1_Pos 2034 #define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL4_1_Msk GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL4_1_Msk 2035 #define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL5_1_Pos GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL5_1_Pos 2036 #define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL5_1_Msk GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL5_1_Msk 2037 #define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL6_1_Pos GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL6_1_Pos 2038 #define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL6_1_Msk GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL6_1_Msk 2039 #define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL7_1_Pos GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL7_1_Pos 2040 #define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL7_1_Msk GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL7_1_Msk 2041 /* GPIO.INTR_CAUSE0 */ 2042 #define GPIO_INTR_CAUSE0_PORT_INT_Pos GPIO_V2_INTR_CAUSE0_PORT_INT_Pos 2043 #define GPIO_INTR_CAUSE0_PORT_INT_Msk GPIO_V2_INTR_CAUSE0_PORT_INT_Msk 2044 /* GPIO.INTR_CAUSE1 */ 2045 #define GPIO_INTR_CAUSE1_PORT_INT_Pos GPIO_V2_INTR_CAUSE1_PORT_INT_Pos 2046 #define GPIO_INTR_CAUSE1_PORT_INT_Msk GPIO_V2_INTR_CAUSE1_PORT_INT_Msk 2047 /* GPIO.INTR_CAUSE2 */ 2048 #define GPIO_INTR_CAUSE2_PORT_INT_Pos GPIO_V2_INTR_CAUSE2_PORT_INT_Pos 2049 #define GPIO_INTR_CAUSE2_PORT_INT_Msk GPIO_V2_INTR_CAUSE2_PORT_INT_Msk 2050 /* GPIO.INTR_CAUSE3 */ 2051 #define GPIO_INTR_CAUSE3_PORT_INT_Pos GPIO_V2_INTR_CAUSE3_PORT_INT_Pos 2052 #define GPIO_INTR_CAUSE3_PORT_INT_Msk GPIO_V2_INTR_CAUSE3_PORT_INT_Msk 2053 /* GPIO.VDD_ACTIVE */ 2054 #define GPIO_VDD_ACTIVE_VDDIO_ACTIVE_Pos GPIO_V2_VDD_ACTIVE_VDDIO_ACTIVE_Pos 2055 #define GPIO_VDD_ACTIVE_VDDIO_ACTIVE_Msk GPIO_V2_VDD_ACTIVE_VDDIO_ACTIVE_Msk 2056 #define GPIO_VDD_ACTIVE_VDDA_ACTIVE_Pos GPIO_V2_VDD_ACTIVE_VDDA_ACTIVE_Pos 2057 #define GPIO_VDD_ACTIVE_VDDA_ACTIVE_Msk GPIO_V2_VDD_ACTIVE_VDDA_ACTIVE_Msk 2058 #define GPIO_VDD_ACTIVE_VDDD_ACTIVE_Pos GPIO_V2_VDD_ACTIVE_VDDD_ACTIVE_Pos 2059 #define GPIO_VDD_ACTIVE_VDDD_ACTIVE_Msk GPIO_V2_VDD_ACTIVE_VDDD_ACTIVE_Msk 2060 /* GPIO.VDD_INTR */ 2061 #define GPIO_VDD_INTR_VDDIO_ACTIVE_Pos GPIO_V2_VDD_INTR_VDDIO_ACTIVE_Pos 2062 #define GPIO_VDD_INTR_VDDIO_ACTIVE_Msk GPIO_V2_VDD_INTR_VDDIO_ACTIVE_Msk 2063 #define GPIO_VDD_INTR_VDDA_ACTIVE_Pos GPIO_V2_VDD_INTR_VDDA_ACTIVE_Pos 2064 #define GPIO_VDD_INTR_VDDA_ACTIVE_Msk GPIO_V2_VDD_INTR_VDDA_ACTIVE_Msk 2065 #define GPIO_VDD_INTR_VDDD_ACTIVE_Pos GPIO_V2_VDD_INTR_VDDD_ACTIVE_Pos 2066 #define GPIO_VDD_INTR_VDDD_ACTIVE_Msk GPIO_V2_VDD_INTR_VDDD_ACTIVE_Msk 2067 /* GPIO.VDD_INTR_MASK */ 2068 #define GPIO_VDD_INTR_MASK_VDDIO_ACTIVE_Pos GPIO_V2_VDD_INTR_MASK_VDDIO_ACTIVE_Pos 2069 #define GPIO_VDD_INTR_MASK_VDDIO_ACTIVE_Msk GPIO_V2_VDD_INTR_MASK_VDDIO_ACTIVE_Msk 2070 #define GPIO_VDD_INTR_MASK_VDDA_ACTIVE_Pos GPIO_V2_VDD_INTR_MASK_VDDA_ACTIVE_Pos 2071 #define GPIO_VDD_INTR_MASK_VDDA_ACTIVE_Msk GPIO_V2_VDD_INTR_MASK_VDDA_ACTIVE_Msk 2072 #define GPIO_VDD_INTR_MASK_VDDD_ACTIVE_Pos GPIO_V2_VDD_INTR_MASK_VDDD_ACTIVE_Pos 2073 #define GPIO_VDD_INTR_MASK_VDDD_ACTIVE_Msk GPIO_V2_VDD_INTR_MASK_VDDD_ACTIVE_Msk 2074 /* GPIO.VDD_INTR_MASKED */ 2075 #define GPIO_VDD_INTR_MASKED_VDDIO_ACTIVE_Pos GPIO_V2_VDD_INTR_MASKED_VDDIO_ACTIVE_Pos 2076 #define GPIO_VDD_INTR_MASKED_VDDIO_ACTIVE_Msk GPIO_V2_VDD_INTR_MASKED_VDDIO_ACTIVE_Msk 2077 #define GPIO_VDD_INTR_MASKED_VDDA_ACTIVE_Pos GPIO_V2_VDD_INTR_MASKED_VDDA_ACTIVE_Pos 2078 #define GPIO_VDD_INTR_MASKED_VDDA_ACTIVE_Msk GPIO_V2_VDD_INTR_MASKED_VDDA_ACTIVE_Msk 2079 #define GPIO_VDD_INTR_MASKED_VDDD_ACTIVE_Pos GPIO_V2_VDD_INTR_MASKED_VDDD_ACTIVE_Pos 2080 #define GPIO_VDD_INTR_MASKED_VDDD_ACTIVE_Msk GPIO_V2_VDD_INTR_MASKED_VDDD_ACTIVE_Msk 2081 /* GPIO.VDD_INTR_SET */ 2082 #define GPIO_VDD_INTR_SET_VDDIO_ACTIVE_Pos GPIO_V2_VDD_INTR_SET_VDDIO_ACTIVE_Pos 2083 #define GPIO_VDD_INTR_SET_VDDIO_ACTIVE_Msk GPIO_V2_VDD_INTR_SET_VDDIO_ACTIVE_Msk 2084 #define GPIO_VDD_INTR_SET_VDDA_ACTIVE_Pos GPIO_V2_VDD_INTR_SET_VDDA_ACTIVE_Pos 2085 #define GPIO_VDD_INTR_SET_VDDA_ACTIVE_Msk GPIO_V2_VDD_INTR_SET_VDDA_ACTIVE_Msk 2086 #define GPIO_VDD_INTR_SET_VDDD_ACTIVE_Pos GPIO_V2_VDD_INTR_SET_VDDD_ACTIVE_Pos 2087 #define GPIO_VDD_INTR_SET_VDDD_ACTIVE_Msk GPIO_V2_VDD_INTR_SET_VDDD_ACTIVE_Msk 2088 2089 2090 /******************************************************************************* 2091 * HSIOM 2092 *******************************************************************************/ 2093 #define HSIOM_PRT_SECTION_SIZE HSIOM_PRT_V2_SECTION_SIZE 2094 #define HSIOM_SECTION_SIZE HSIOM_V2_SECTION_SIZE 2095 2096 /* HSIOM_PRT.PORT_SEL0 */ 2097 #define HSIOM_PRT_PORT_SEL0_IO0_SEL_Pos HSIOM_PRT_V2_PORT_SEL0_IO0_SEL_Pos 2098 #define HSIOM_PRT_PORT_SEL0_IO0_SEL_Msk HSIOM_PRT_V2_PORT_SEL0_IO0_SEL_Msk 2099 #define HSIOM_PRT_PORT_SEL0_IO1_SEL_Pos HSIOM_PRT_V2_PORT_SEL0_IO1_SEL_Pos 2100 #define HSIOM_PRT_PORT_SEL0_IO1_SEL_Msk HSIOM_PRT_V2_PORT_SEL0_IO1_SEL_Msk 2101 #define HSIOM_PRT_PORT_SEL0_IO2_SEL_Pos HSIOM_PRT_V2_PORT_SEL0_IO2_SEL_Pos 2102 #define HSIOM_PRT_PORT_SEL0_IO2_SEL_Msk HSIOM_PRT_V2_PORT_SEL0_IO2_SEL_Msk 2103 #define HSIOM_PRT_PORT_SEL0_IO3_SEL_Pos HSIOM_PRT_V2_PORT_SEL0_IO3_SEL_Pos 2104 #define HSIOM_PRT_PORT_SEL0_IO3_SEL_Msk HSIOM_PRT_V2_PORT_SEL0_IO3_SEL_Msk 2105 /* HSIOM_PRT.PORT_SEL1 */ 2106 #define HSIOM_PRT_PORT_SEL1_IO4_SEL_Pos HSIOM_PRT_V2_PORT_SEL1_IO4_SEL_Pos 2107 #define HSIOM_PRT_PORT_SEL1_IO4_SEL_Msk HSIOM_PRT_V2_PORT_SEL1_IO4_SEL_Msk 2108 #define HSIOM_PRT_PORT_SEL1_IO5_SEL_Pos HSIOM_PRT_V2_PORT_SEL1_IO5_SEL_Pos 2109 #define HSIOM_PRT_PORT_SEL1_IO5_SEL_Msk HSIOM_PRT_V2_PORT_SEL1_IO5_SEL_Msk 2110 #define HSIOM_PRT_PORT_SEL1_IO6_SEL_Pos HSIOM_PRT_V2_PORT_SEL1_IO6_SEL_Pos 2111 #define HSIOM_PRT_PORT_SEL1_IO6_SEL_Msk HSIOM_PRT_V2_PORT_SEL1_IO6_SEL_Msk 2112 #define HSIOM_PRT_PORT_SEL1_IO7_SEL_Pos HSIOM_PRT_V2_PORT_SEL1_IO7_SEL_Pos 2113 #define HSIOM_PRT_PORT_SEL1_IO7_SEL_Msk HSIOM_PRT_V2_PORT_SEL1_IO7_SEL_Msk 2114 /* HSIOM.AMUX_SPLIT_CTL */ 2115 #define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Pos HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Pos 2116 #define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk 2117 #define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Pos HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Pos 2118 #define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk 2119 #define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_S0_Pos HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_S0_Pos 2120 #define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_S0_Msk HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_S0_Msk 2121 #define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Pos HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SL_Pos 2122 #define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk 2123 #define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Pos HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SR_Pos 2124 #define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk 2125 #define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_S0_Pos HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_S0_Pos 2126 #define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_S0_Msk HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_S0_Msk 2127 /* HSIOM.MONITOR_CTL_0 */ 2128 #define HSIOM_MONITOR_CTL_0_MONITOR_EN_Pos HSIOM_V2_MONITOR_CTL_0_MONITOR_EN_Pos 2129 #define HSIOM_MONITOR_CTL_0_MONITOR_EN_Msk HSIOM_V2_MONITOR_CTL_0_MONITOR_EN_Msk 2130 /* HSIOM.MONITOR_CTL_1 */ 2131 #define HSIOM_MONITOR_CTL_1_MONITOR_EN_Pos HSIOM_V2_MONITOR_CTL_1_MONITOR_EN_Pos 2132 #define HSIOM_MONITOR_CTL_1_MONITOR_EN_Msk HSIOM_V2_MONITOR_CTL_1_MONITOR_EN_Msk 2133 /* HSIOM.MONITOR_CTL_2 */ 2134 #define HSIOM_MONITOR_CTL_2_MONITOR_EN_Pos HSIOM_V2_MONITOR_CTL_2_MONITOR_EN_Pos 2135 #define HSIOM_MONITOR_CTL_2_MONITOR_EN_Msk HSIOM_V2_MONITOR_CTL_2_MONITOR_EN_Msk 2136 /* HSIOM.MONITOR_CTL_3 */ 2137 #define HSIOM_MONITOR_CTL_3_MONITOR_EN_Pos HSIOM_V2_MONITOR_CTL_3_MONITOR_EN_Pos 2138 #define HSIOM_MONITOR_CTL_3_MONITOR_EN_Msk HSIOM_V2_MONITOR_CTL_3_MONITOR_EN_Msk 2139 /* HSIOM.ALT_JTAG_EN */ 2140 #define HSIOM_ALT_JTAG_EN_ENABLE_Pos HSIOM_V2_ALT_JTAG_EN_ENABLE_Pos 2141 #define HSIOM_ALT_JTAG_EN_ENABLE_Msk HSIOM_V2_ALT_JTAG_EN_ENABLE_Msk 2142 2143 2144 /******************************************************************************* 2145 * IPC 2146 *******************************************************************************/ 2147 /* IPC_STRUCT.ACQUIRE */ 2148 #define IPC_STRUCT_ACQUIRE_P_Pos IPC_STRUCT_V2_ACQUIRE_P_Pos 2149 #define IPC_STRUCT_ACQUIRE_P_Msk IPC_STRUCT_V2_ACQUIRE_P_Msk 2150 #define IPC_STRUCT_ACQUIRE_NS_Pos IPC_STRUCT_V2_ACQUIRE_NS_Pos 2151 #define IPC_STRUCT_ACQUIRE_NS_Msk IPC_STRUCT_V2_ACQUIRE_NS_Msk 2152 #define IPC_STRUCT_ACQUIRE_PC_Pos IPC_STRUCT_V2_ACQUIRE_PC_Pos 2153 #define IPC_STRUCT_ACQUIRE_PC_Msk IPC_STRUCT_V2_ACQUIRE_PC_Msk 2154 #define IPC_STRUCT_ACQUIRE_MS_Pos IPC_STRUCT_V2_ACQUIRE_MS_Pos 2155 #define IPC_STRUCT_ACQUIRE_MS_Msk IPC_STRUCT_V2_ACQUIRE_MS_Msk 2156 #define IPC_STRUCT_ACQUIRE_SUCCESS_Pos IPC_STRUCT_V2_ACQUIRE_SUCCESS_Pos 2157 #define IPC_STRUCT_ACQUIRE_SUCCESS_Msk IPC_STRUCT_V2_ACQUIRE_SUCCESS_Msk 2158 /* IPC_STRUCT.RELEASE */ 2159 #define IPC_STRUCT_RELEASE_INTR_RELEASE_Pos IPC_STRUCT_V2_RELEASE_INTR_RELEASE_Pos 2160 #define IPC_STRUCT_RELEASE_INTR_RELEASE_Msk IPC_STRUCT_V2_RELEASE_INTR_RELEASE_Msk 2161 /* IPC_STRUCT.NOTIFY */ 2162 #define IPC_STRUCT_NOTIFY_INTR_NOTIFY_Pos IPC_STRUCT_V2_NOTIFY_INTR_NOTIFY_Pos 2163 #define IPC_STRUCT_NOTIFY_INTR_NOTIFY_Msk IPC_STRUCT_V2_NOTIFY_INTR_NOTIFY_Msk 2164 /* IPC_STRUCT.DATA0 */ 2165 #define IPC_STRUCT_DATA0_DATA_Pos IPC_STRUCT_V2_DATA0_DATA_Pos 2166 #define IPC_STRUCT_DATA0_DATA_Msk IPC_STRUCT_V2_DATA0_DATA_Msk 2167 /* IPC_STRUCT.DATA1 */ 2168 #define IPC_STRUCT_DATA1_DATA_Pos IPC_STRUCT_V2_DATA1_DATA_Pos 2169 #define IPC_STRUCT_DATA1_DATA_Msk IPC_STRUCT_V2_DATA1_DATA_Msk 2170 /* IPC_STRUCT.LOCK_STATUS */ 2171 #define IPC_STRUCT_LOCK_STATUS_P_Pos IPC_STRUCT_V2_LOCK_STATUS_P_Pos 2172 #define IPC_STRUCT_LOCK_STATUS_P_Msk IPC_STRUCT_V2_LOCK_STATUS_P_Msk 2173 #define IPC_STRUCT_LOCK_STATUS_NS_Pos IPC_STRUCT_V2_LOCK_STATUS_NS_Pos 2174 #define IPC_STRUCT_LOCK_STATUS_NS_Msk IPC_STRUCT_V2_LOCK_STATUS_NS_Msk 2175 #define IPC_STRUCT_LOCK_STATUS_PC_Pos IPC_STRUCT_V2_LOCK_STATUS_PC_Pos 2176 #define IPC_STRUCT_LOCK_STATUS_PC_Msk IPC_STRUCT_V2_LOCK_STATUS_PC_Msk 2177 #define IPC_STRUCT_LOCK_STATUS_MS_Pos IPC_STRUCT_V2_LOCK_STATUS_MS_Pos 2178 #define IPC_STRUCT_LOCK_STATUS_MS_Msk IPC_STRUCT_V2_LOCK_STATUS_MS_Msk 2179 #define IPC_STRUCT_LOCK_STATUS_ACQUIRED_Pos IPC_STRUCT_V2_LOCK_STATUS_ACQUIRED_Pos 2180 #define IPC_STRUCT_LOCK_STATUS_ACQUIRED_Msk IPC_STRUCT_V2_LOCK_STATUS_ACQUIRED_Msk 2181 /* IPC_INTR_STRUCT.INTR */ 2182 #define IPC_INTR_STRUCT_INTR_RELEASE_Pos IPC_INTR_STRUCT_V2_INTR_RELEASE_Pos 2183 #define IPC_INTR_STRUCT_INTR_RELEASE_Msk IPC_INTR_STRUCT_V2_INTR_RELEASE_Msk 2184 #define IPC_INTR_STRUCT_INTR_NOTIFY_Pos IPC_INTR_STRUCT_V2_INTR_NOTIFY_Pos 2185 #define IPC_INTR_STRUCT_INTR_NOTIFY_Msk IPC_INTR_STRUCT_V2_INTR_NOTIFY_Msk 2186 /* IPC_INTR_STRUCT.INTR_SET */ 2187 #define IPC_INTR_STRUCT_INTR_SET_RELEASE_Pos IPC_INTR_STRUCT_V2_INTR_SET_RELEASE_Pos 2188 #define IPC_INTR_STRUCT_INTR_SET_RELEASE_Msk IPC_INTR_STRUCT_V2_INTR_SET_RELEASE_Msk 2189 #define IPC_INTR_STRUCT_INTR_SET_NOTIFY_Pos IPC_INTR_STRUCT_V2_INTR_SET_NOTIFY_Pos 2190 #define IPC_INTR_STRUCT_INTR_SET_NOTIFY_Msk IPC_INTR_STRUCT_V2_INTR_SET_NOTIFY_Msk 2191 /* IPC_INTR_STRUCT.INTR_MASK */ 2192 #define IPC_INTR_STRUCT_INTR_MASK_RELEASE_Pos IPC_INTR_STRUCT_V2_INTR_MASK_RELEASE_Pos 2193 #define IPC_INTR_STRUCT_INTR_MASK_RELEASE_Msk IPC_INTR_STRUCT_V2_INTR_MASK_RELEASE_Msk 2194 #define IPC_INTR_STRUCT_INTR_MASK_NOTIFY_Pos IPC_INTR_STRUCT_V2_INTR_MASK_NOTIFY_Pos 2195 #define IPC_INTR_STRUCT_INTR_MASK_NOTIFY_Msk IPC_INTR_STRUCT_V2_INTR_MASK_NOTIFY_Msk 2196 /* IPC_INTR_STRUCT.INTR_MASKED */ 2197 #define IPC_INTR_STRUCT_INTR_MASKED_RELEASE_Pos IPC_INTR_STRUCT_V2_INTR_MASKED_RELEASE_Pos 2198 #define IPC_INTR_STRUCT_INTR_MASKED_RELEASE_Msk IPC_INTR_STRUCT_V2_INTR_MASKED_RELEASE_Msk 2199 #define IPC_INTR_STRUCT_INTR_MASKED_NOTIFY_Pos IPC_INTR_STRUCT_V2_INTR_MASKED_NOTIFY_Pos 2200 #define IPC_INTR_STRUCT_INTR_MASKED_NOTIFY_Msk IPC_INTR_STRUCT_V2_INTR_MASKED_NOTIFY_Msk 2201 2202 2203 /******************************************************************************* 2204 * PERI 2205 *******************************************************************************/ 2206 /* PERI_GR.CLOCK_CTL */ 2207 #define PERI_GR_CLOCK_CTL_INT8_DIV_Pos PERI_GR_V2_CLOCK_CTL_INT8_DIV_Pos 2208 #define PERI_GR_CLOCK_CTL_INT8_DIV_Msk PERI_GR_V2_CLOCK_CTL_INT8_DIV_Msk 2209 /* PERI_GR.SL_CTL */ 2210 #define PERI_GR_SL_CTL_ENABLED_0_Pos PERI_GR_V2_SL_CTL_ENABLED_0_Pos 2211 #define PERI_GR_SL_CTL_ENABLED_0_Msk PERI_GR_V2_SL_CTL_ENABLED_0_Msk 2212 #define PERI_GR_SL_CTL_ENABLED_1_Pos PERI_GR_V2_SL_CTL_ENABLED_1_Pos 2213 #define PERI_GR_SL_CTL_ENABLED_1_Msk PERI_GR_V2_SL_CTL_ENABLED_1_Msk 2214 #define PERI_GR_SL_CTL_ENABLED_2_Pos PERI_GR_V2_SL_CTL_ENABLED_2_Pos 2215 #define PERI_GR_SL_CTL_ENABLED_2_Msk PERI_GR_V2_SL_CTL_ENABLED_2_Msk 2216 #define PERI_GR_SL_CTL_ENABLED_3_Pos PERI_GR_V2_SL_CTL_ENABLED_3_Pos 2217 #define PERI_GR_SL_CTL_ENABLED_3_Msk PERI_GR_V2_SL_CTL_ENABLED_3_Msk 2218 #define PERI_GR_SL_CTL_ENABLED_4_Pos PERI_GR_V2_SL_CTL_ENABLED_4_Pos 2219 #define PERI_GR_SL_CTL_ENABLED_4_Msk PERI_GR_V2_SL_CTL_ENABLED_4_Msk 2220 #define PERI_GR_SL_CTL_ENABLED_5_Pos PERI_GR_V2_SL_CTL_ENABLED_5_Pos 2221 #define PERI_GR_SL_CTL_ENABLED_5_Msk PERI_GR_V2_SL_CTL_ENABLED_5_Msk 2222 #define PERI_GR_SL_CTL_ENABLED_6_Pos PERI_GR_V2_SL_CTL_ENABLED_6_Pos 2223 #define PERI_GR_SL_CTL_ENABLED_6_Msk PERI_GR_V2_SL_CTL_ENABLED_6_Msk 2224 #define PERI_GR_SL_CTL_ENABLED_7_Pos PERI_GR_V2_SL_CTL_ENABLED_7_Pos 2225 #define PERI_GR_SL_CTL_ENABLED_7_Msk PERI_GR_V2_SL_CTL_ENABLED_7_Msk 2226 #define PERI_GR_SL_CTL_ENABLED_8_Pos PERI_GR_V2_SL_CTL_ENABLED_8_Pos 2227 #define PERI_GR_SL_CTL_ENABLED_8_Msk PERI_GR_V2_SL_CTL_ENABLED_8_Msk 2228 #define PERI_GR_SL_CTL_ENABLED_9_Pos PERI_GR_V2_SL_CTL_ENABLED_9_Pos 2229 #define PERI_GR_SL_CTL_ENABLED_9_Msk PERI_GR_V2_SL_CTL_ENABLED_9_Msk 2230 #define PERI_GR_SL_CTL_ENABLED_10_Pos PERI_GR_V2_SL_CTL_ENABLED_10_Pos 2231 #define PERI_GR_SL_CTL_ENABLED_10_Msk PERI_GR_V2_SL_CTL_ENABLED_10_Msk 2232 #define PERI_GR_SL_CTL_ENABLED_11_Pos PERI_GR_V2_SL_CTL_ENABLED_11_Pos 2233 #define PERI_GR_SL_CTL_ENABLED_11_Msk PERI_GR_V2_SL_CTL_ENABLED_11_Msk 2234 #define PERI_GR_SL_CTL_ENABLED_12_Pos PERI_GR_V2_SL_CTL_ENABLED_12_Pos 2235 #define PERI_GR_SL_CTL_ENABLED_12_Msk PERI_GR_V2_SL_CTL_ENABLED_12_Msk 2236 #define PERI_GR_SL_CTL_ENABLED_13_Pos PERI_GR_V2_SL_CTL_ENABLED_13_Pos 2237 #define PERI_GR_SL_CTL_ENABLED_13_Msk PERI_GR_V2_SL_CTL_ENABLED_13_Msk 2238 #define PERI_GR_SL_CTL_ENABLED_14_Pos PERI_GR_V2_SL_CTL_ENABLED_14_Pos 2239 #define PERI_GR_SL_CTL_ENABLED_14_Msk PERI_GR_V2_SL_CTL_ENABLED_14_Msk 2240 #define PERI_GR_SL_CTL_ENABLED_15_Pos PERI_GR_V2_SL_CTL_ENABLED_15_Pos 2241 #define PERI_GR_SL_CTL_ENABLED_15_Msk PERI_GR_V2_SL_CTL_ENABLED_15_Msk 2242 #define PERI_GR_SL_CTL_DISABLED_0_Pos PERI_GR_V2_SL_CTL_DISABLED_0_Pos 2243 #define PERI_GR_SL_CTL_DISABLED_0_Msk PERI_GR_V2_SL_CTL_DISABLED_0_Msk 2244 #define PERI_GR_SL_CTL_DISABLED_1_Pos PERI_GR_V2_SL_CTL_DISABLED_1_Pos 2245 #define PERI_GR_SL_CTL_DISABLED_1_Msk PERI_GR_V2_SL_CTL_DISABLED_1_Msk 2246 #define PERI_GR_SL_CTL_DISABLED_2_Pos PERI_GR_V2_SL_CTL_DISABLED_2_Pos 2247 #define PERI_GR_SL_CTL_DISABLED_2_Msk PERI_GR_V2_SL_CTL_DISABLED_2_Msk 2248 #define PERI_GR_SL_CTL_DISABLED_3_Pos PERI_GR_V2_SL_CTL_DISABLED_3_Pos 2249 #define PERI_GR_SL_CTL_DISABLED_3_Msk PERI_GR_V2_SL_CTL_DISABLED_3_Msk 2250 #define PERI_GR_SL_CTL_DISABLED_4_Pos PERI_GR_V2_SL_CTL_DISABLED_4_Pos 2251 #define PERI_GR_SL_CTL_DISABLED_4_Msk PERI_GR_V2_SL_CTL_DISABLED_4_Msk 2252 #define PERI_GR_SL_CTL_DISABLED_5_Pos PERI_GR_V2_SL_CTL_DISABLED_5_Pos 2253 #define PERI_GR_SL_CTL_DISABLED_5_Msk PERI_GR_V2_SL_CTL_DISABLED_5_Msk 2254 #define PERI_GR_SL_CTL_DISABLED_6_Pos PERI_GR_V2_SL_CTL_DISABLED_6_Pos 2255 #define PERI_GR_SL_CTL_DISABLED_6_Msk PERI_GR_V2_SL_CTL_DISABLED_6_Msk 2256 #define PERI_GR_SL_CTL_DISABLED_7_Pos PERI_GR_V2_SL_CTL_DISABLED_7_Pos 2257 #define PERI_GR_SL_CTL_DISABLED_7_Msk PERI_GR_V2_SL_CTL_DISABLED_7_Msk 2258 #define PERI_GR_SL_CTL_DISABLED_8_Pos PERI_GR_V2_SL_CTL_DISABLED_8_Pos 2259 #define PERI_GR_SL_CTL_DISABLED_8_Msk PERI_GR_V2_SL_CTL_DISABLED_8_Msk 2260 #define PERI_GR_SL_CTL_DISABLED_9_Pos PERI_GR_V2_SL_CTL_DISABLED_9_Pos 2261 #define PERI_GR_SL_CTL_DISABLED_9_Msk PERI_GR_V2_SL_CTL_DISABLED_9_Msk 2262 #define PERI_GR_SL_CTL_DISABLED_10_Pos PERI_GR_V2_SL_CTL_DISABLED_10_Pos 2263 #define PERI_GR_SL_CTL_DISABLED_10_Msk PERI_GR_V2_SL_CTL_DISABLED_10_Msk 2264 #define PERI_GR_SL_CTL_DISABLED_11_Pos PERI_GR_V2_SL_CTL_DISABLED_11_Pos 2265 #define PERI_GR_SL_CTL_DISABLED_11_Msk PERI_GR_V2_SL_CTL_DISABLED_11_Msk 2266 #define PERI_GR_SL_CTL_DISABLED_12_Pos PERI_GR_V2_SL_CTL_DISABLED_12_Pos 2267 #define PERI_GR_SL_CTL_DISABLED_12_Msk PERI_GR_V2_SL_CTL_DISABLED_12_Msk 2268 #define PERI_GR_SL_CTL_DISABLED_13_Pos PERI_GR_V2_SL_CTL_DISABLED_13_Pos 2269 #define PERI_GR_SL_CTL_DISABLED_13_Msk PERI_GR_V2_SL_CTL_DISABLED_13_Msk 2270 #define PERI_GR_SL_CTL_DISABLED_14_Pos PERI_GR_V2_SL_CTL_DISABLED_14_Pos 2271 #define PERI_GR_SL_CTL_DISABLED_14_Msk PERI_GR_V2_SL_CTL_DISABLED_14_Msk 2272 #define PERI_GR_SL_CTL_DISABLED_15_Pos PERI_GR_V2_SL_CTL_DISABLED_15_Pos 2273 #define PERI_GR_SL_CTL_DISABLED_15_Msk PERI_GR_V2_SL_CTL_DISABLED_15_Msk 2274 /* PERI_TR_GR.TR_CTL */ 2275 #define PERI_TR_GR_TR_CTL_TR_SEL_Pos PERI_TR_GR_V2_TR_CTL_TR_SEL_Pos 2276 #define PERI_TR_GR_TR_CTL_TR_SEL_Msk PERI_TR_GR_V2_TR_CTL_TR_SEL_Msk 2277 #define PERI_TR_GR_TR_CTL_TR_INV_Pos PERI_TR_GR_V2_TR_CTL_TR_INV_Pos 2278 #define PERI_TR_GR_TR_CTL_TR_INV_Msk PERI_TR_GR_V2_TR_CTL_TR_INV_Msk 2279 #define PERI_TR_GR_TR_CTL_TR_EDGE_Pos PERI_TR_GR_V2_TR_CTL_TR_EDGE_Pos 2280 #define PERI_TR_GR_TR_CTL_TR_EDGE_Msk PERI_TR_GR_V2_TR_CTL_TR_EDGE_Msk 2281 #define PERI_TR_GR_TR_CTL_DBG_FREEZE_EN_Pos PERI_TR_GR_V2_TR_CTL_DBG_FREEZE_EN_Pos 2282 #define PERI_TR_GR_TR_CTL_DBG_FREEZE_EN_Msk PERI_TR_GR_V2_TR_CTL_DBG_FREEZE_EN_Msk 2283 /* PERI_TR_1TO1_GR.TR_CTL */ 2284 #define PERI_TR_1TO1_GR_TR_CTL_TR_SEL_Pos PERI_TR_1TO1_GR_V2_TR_CTL_TR_SEL_Pos 2285 #define PERI_TR_1TO1_GR_TR_CTL_TR_SEL_Msk PERI_TR_1TO1_GR_V2_TR_CTL_TR_SEL_Msk 2286 #define PERI_TR_1TO1_GR_TR_CTL_TR_INV_Pos PERI_TR_1TO1_GR_V2_TR_CTL_TR_INV_Pos 2287 #define PERI_TR_1TO1_GR_TR_CTL_TR_INV_Msk PERI_TR_1TO1_GR_V2_TR_CTL_TR_INV_Msk 2288 #define PERI_TR_1TO1_GR_TR_CTL_TR_EDGE_Pos PERI_TR_1TO1_GR_V2_TR_CTL_TR_EDGE_Pos 2289 #define PERI_TR_1TO1_GR_TR_CTL_TR_EDGE_Msk PERI_TR_1TO1_GR_V2_TR_CTL_TR_EDGE_Msk 2290 #define PERI_TR_1TO1_GR_TR_CTL_DBG_FREEZE_EN_Pos PERI_TR_1TO1_GR_V2_TR_CTL_DBG_FREEZE_EN_Pos 2291 #define PERI_TR_1TO1_GR_TR_CTL_DBG_FREEZE_EN_Msk PERI_TR_1TO1_GR_V2_TR_CTL_DBG_FREEZE_EN_Msk 2292 /* PERI.TIMEOUT_CTL */ 2293 #define PERI_TIMEOUT_CTL_TIMEOUT_Pos PERI_V2_TIMEOUT_CTL_TIMEOUT_Pos 2294 #define PERI_TIMEOUT_CTL_TIMEOUT_Msk PERI_V2_TIMEOUT_CTL_TIMEOUT_Msk 2295 /* PERI.TR_CMD */ 2296 #define PERI_TR_CMD_TR_SEL_Pos PERI_V2_TR_CMD_TR_SEL_Pos 2297 #define PERI_TR_CMD_TR_SEL_Msk PERI_V2_TR_CMD_TR_SEL_Msk 2298 #define PERI_TR_CMD_GROUP_SEL_Pos PERI_V2_TR_CMD_GROUP_SEL_Pos 2299 /* Bits 8-12, values: 1 - 15: trigger mulitplxer groups, values: 16 - 31: trigger 1-to-1 groups. */ 2300 /* Not remapping to PERI_V2_TR_CMD_GROUP_SEL_Msk as this mask is defined as 0x1F00UL which has Bit 12 mask value */ 2301 /* The define is required for PDL code for PERI version less than 3. Version >= 3 has different check for bit 12 */ 2302 #define PERI_TR_CMD_GROUP_SEL_Msk 0x0F00UL 2303 #define PERI_TR_CMD_TR_EDGE_Pos PERI_V2_TR_CMD_TR_EDGE_Pos 2304 #define PERI_TR_CMD_TR_EDGE_Msk PERI_V2_TR_CMD_TR_EDGE_Msk 2305 #define PERI_TR_CMD_OUT_SEL_Pos PERI_V2_TR_CMD_OUT_SEL_Pos 2306 #define PERI_TR_CMD_OUT_SEL_Msk PERI_V2_TR_CMD_OUT_SEL_Msk 2307 #define PERI_TR_CMD_ACTIVATE_Pos PERI_V2_TR_CMD_ACTIVATE_Pos 2308 #define PERI_TR_CMD_ACTIVATE_Msk PERI_V2_TR_CMD_ACTIVATE_Msk 2309 /* PERI.DIV_CMD */ 2310 #define PERI_DIV_CMD_DIV_SEL_Pos PERI_V2_DIV_CMD_DIV_SEL_Pos 2311 #define PERI_DIV_CMD_DIV_SEL_Msk PERI_V2_DIV_CMD_DIV_SEL_Msk 2312 #define PERI_DIV_CMD_TYPE_SEL_Pos PERI_V2_DIV_CMD_TYPE_SEL_Pos 2313 #define PERI_DIV_CMD_TYPE_SEL_Msk PERI_V2_DIV_CMD_TYPE_SEL_Msk 2314 #define PERI_DIV_CMD_PA_DIV_SEL_Pos PERI_V2_DIV_CMD_PA_DIV_SEL_Pos 2315 #define PERI_DIV_CMD_PA_DIV_SEL_Msk PERI_V2_DIV_CMD_PA_DIV_SEL_Msk 2316 #define PERI_DIV_CMD_PA_TYPE_SEL_Pos PERI_V2_DIV_CMD_PA_TYPE_SEL_Pos 2317 #define PERI_DIV_CMD_PA_TYPE_SEL_Msk PERI_V2_DIV_CMD_PA_TYPE_SEL_Msk 2318 #define PERI_DIV_CMD_DISABLE_Pos PERI_V2_DIV_CMD_DISABLE_Pos 2319 #define PERI_DIV_CMD_DISABLE_Msk PERI_V2_DIV_CMD_DISABLE_Msk 2320 #define PERI_DIV_CMD_ENABLE_Pos PERI_V2_DIV_CMD_ENABLE_Pos 2321 #define PERI_DIV_CMD_ENABLE_Msk PERI_V2_DIV_CMD_ENABLE_Msk 2322 /* PERI.CLOCK_CTL */ 2323 #define PERI_CLOCK_CTL_DIV_SEL_Pos PERI_V2_CLOCK_CTL_DIV_SEL_Pos 2324 #define PERI_CLOCK_CTL_DIV_SEL_Msk PERI_V2_CLOCK_CTL_DIV_SEL_Msk 2325 #define PERI_CLOCK_CTL_TYPE_SEL_Pos PERI_V2_CLOCK_CTL_TYPE_SEL_Pos 2326 #define PERI_CLOCK_CTL_TYPE_SEL_Msk PERI_V2_CLOCK_CTL_TYPE_SEL_Msk 2327 /* PERI.DIV_8_CTL */ 2328 #define PERI_DIV_8_CTL_EN_Pos PERI_V2_DIV_8_CTL_EN_Pos 2329 #define PERI_DIV_8_CTL_EN_Msk PERI_V2_DIV_8_CTL_EN_Msk 2330 #define PERI_DIV_8_CTL_INT8_DIV_Pos PERI_V2_DIV_8_CTL_INT8_DIV_Pos 2331 #define PERI_DIV_8_CTL_INT8_DIV_Msk PERI_V2_DIV_8_CTL_INT8_DIV_Msk 2332 /* PERI.DIV_16_CTL */ 2333 #define PERI_DIV_16_CTL_EN_Pos PERI_V2_DIV_16_CTL_EN_Pos 2334 #define PERI_DIV_16_CTL_EN_Msk PERI_V2_DIV_16_CTL_EN_Msk 2335 #define PERI_DIV_16_CTL_INT16_DIV_Pos PERI_V2_DIV_16_CTL_INT16_DIV_Pos 2336 #define PERI_DIV_16_CTL_INT16_DIV_Msk PERI_V2_DIV_16_CTL_INT16_DIV_Msk 2337 /* PERI.DIV_16_5_CTL */ 2338 #define PERI_DIV_16_5_CTL_EN_Pos PERI_V2_DIV_16_5_CTL_EN_Pos 2339 #define PERI_DIV_16_5_CTL_EN_Msk PERI_V2_DIV_16_5_CTL_EN_Msk 2340 #define PERI_DIV_16_5_CTL_FRAC5_DIV_Pos PERI_V2_DIV_16_5_CTL_FRAC5_DIV_Pos 2341 #define PERI_DIV_16_5_CTL_FRAC5_DIV_Msk PERI_V2_DIV_16_5_CTL_FRAC5_DIV_Msk 2342 #define PERI_DIV_16_5_CTL_INT16_DIV_Pos PERI_V2_DIV_16_5_CTL_INT16_DIV_Pos 2343 #define PERI_DIV_16_5_CTL_INT16_DIV_Msk PERI_V2_DIV_16_5_CTL_INT16_DIV_Msk 2344 /* PERI.DIV_24_5_CTL */ 2345 #define PERI_DIV_24_5_CTL_EN_Pos PERI_V2_DIV_24_5_CTL_EN_Pos 2346 #define PERI_DIV_24_5_CTL_EN_Msk PERI_V2_DIV_24_5_CTL_EN_Msk 2347 #define PERI_DIV_24_5_CTL_FRAC5_DIV_Pos PERI_V2_DIV_24_5_CTL_FRAC5_DIV_Pos 2348 #define PERI_DIV_24_5_CTL_FRAC5_DIV_Msk PERI_V2_DIV_24_5_CTL_FRAC5_DIV_Msk 2349 #define PERI_DIV_24_5_CTL_INT24_DIV_Pos PERI_V2_DIV_24_5_CTL_INT24_DIV_Pos 2350 #define PERI_DIV_24_5_CTL_INT24_DIV_Msk PERI_V2_DIV_24_5_CTL_INT24_DIV_Msk 2351 /* PERI.ECC_CTL */ 2352 #define PERI_ECC_CTL_WORD_ADDR_Pos PERI_V2_ECC_CTL_WORD_ADDR_Pos 2353 #define PERI_ECC_CTL_WORD_ADDR_Msk PERI_V2_ECC_CTL_WORD_ADDR_Msk 2354 #define PERI_ECC_CTL_ECC_EN_Pos PERI_V2_ECC_CTL_ECC_EN_Pos 2355 #define PERI_ECC_CTL_ECC_EN_Msk PERI_V2_ECC_CTL_ECC_EN_Msk 2356 #define PERI_ECC_CTL_ECC_INJ_EN_Pos PERI_V2_ECC_CTL_ECC_INJ_EN_Pos 2357 #define PERI_ECC_CTL_ECC_INJ_EN_Msk PERI_V2_ECC_CTL_ECC_INJ_EN_Msk 2358 #define PERI_ECC_CTL_PARITY_Pos PERI_V2_ECC_CTL_PARITY_Pos 2359 #define PERI_ECC_CTL_PARITY_Msk PERI_V2_ECC_CTL_PARITY_Msk 2360 2361 2362 /******************************************************************************* 2363 * PROT 2364 *******************************************************************************/ 2365 #define PROT_SMPU_SMPU_STRUCT_SECTION_SIZE PROT_SMPU_SMPU_STRUCT_V2_SECTION_SIZE 2366 #define PROT_SMPU_SECTION_SIZE PROT_SMPU_V2_SECTION_SIZE 2367 #define PROT_MPU_MPU_STRUCT_SECTION_SIZE PROT_MPU_MPU_STRUCT_V2_SECTION_SIZE 2368 #define PROT_MPU_SECTION_SIZE PROT_MPU_V2_SECTION_SIZE 2369 #define PROT_SECTION_SIZE PROT_V2_SECTION_SIZE 2370 2371 /* PROT_SMPU_SMPU_STRUCT.ADDR0 */ 2372 #define PROT_SMPU_SMPU_STRUCT_ADDR0_SUBREGION_DISABLE_Pos PROT_SMPU_SMPU_STRUCT_V2_ADDR0_SUBREGION_DISABLE_Pos 2373 #define PROT_SMPU_SMPU_STRUCT_ADDR0_SUBREGION_DISABLE_Msk PROT_SMPU_SMPU_STRUCT_V2_ADDR0_SUBREGION_DISABLE_Msk 2374 #define PROT_SMPU_SMPU_STRUCT_ADDR0_ADDR24_Pos PROT_SMPU_SMPU_STRUCT_V2_ADDR0_ADDR24_Pos 2375 #define PROT_SMPU_SMPU_STRUCT_ADDR0_ADDR24_Msk PROT_SMPU_SMPU_STRUCT_V2_ADDR0_ADDR24_Msk 2376 /* PROT_SMPU_SMPU_STRUCT.ATT0 */ 2377 #define PROT_SMPU_SMPU_STRUCT_ATT0_UR_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT0_UR_Pos 2378 #define PROT_SMPU_SMPU_STRUCT_ATT0_UR_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT0_UR_Msk 2379 #define PROT_SMPU_SMPU_STRUCT_ATT0_UW_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT0_UW_Pos 2380 #define PROT_SMPU_SMPU_STRUCT_ATT0_UW_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT0_UW_Msk 2381 #define PROT_SMPU_SMPU_STRUCT_ATT0_UX_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT0_UX_Pos 2382 #define PROT_SMPU_SMPU_STRUCT_ATT0_UX_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT0_UX_Msk 2383 #define PROT_SMPU_SMPU_STRUCT_ATT0_PR_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT0_PR_Pos 2384 #define PROT_SMPU_SMPU_STRUCT_ATT0_PR_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT0_PR_Msk 2385 #define PROT_SMPU_SMPU_STRUCT_ATT0_PW_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT0_PW_Pos 2386 #define PROT_SMPU_SMPU_STRUCT_ATT0_PW_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT0_PW_Msk 2387 #define PROT_SMPU_SMPU_STRUCT_ATT0_PX_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT0_PX_Pos 2388 #define PROT_SMPU_SMPU_STRUCT_ATT0_PX_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT0_PX_Msk 2389 #define PROT_SMPU_SMPU_STRUCT_ATT0_NS_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT0_NS_Pos 2390 #define PROT_SMPU_SMPU_STRUCT_ATT0_NS_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT0_NS_Msk 2391 #define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MASK_0_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT0_PC_MASK_0_Pos 2392 #define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MASK_0_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT0_PC_MASK_0_Msk 2393 #define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MASK_15_TO_1_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT0_PC_MASK_15_TO_1_Pos 2394 #define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MASK_15_TO_1_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT0_PC_MASK_15_TO_1_Msk 2395 #define PROT_SMPU_SMPU_STRUCT_ATT0_REGION_SIZE_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT0_REGION_SIZE_Pos 2396 #define PROT_SMPU_SMPU_STRUCT_ATT0_REGION_SIZE_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT0_REGION_SIZE_Msk 2397 #define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MATCH_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT0_PC_MATCH_Pos 2398 #define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MATCH_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT0_PC_MATCH_Msk 2399 #define PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT0_ENABLED_Pos 2400 #define PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT0_ENABLED_Msk 2401 /* PROT_SMPU_SMPU_STRUCT.ADDR1 */ 2402 #define PROT_SMPU_SMPU_STRUCT_ADDR1_SUBREGION_DISABLE_Pos PROT_SMPU_SMPU_STRUCT_V2_ADDR1_SUBREGION_DISABLE_Pos 2403 #define PROT_SMPU_SMPU_STRUCT_ADDR1_SUBREGION_DISABLE_Msk PROT_SMPU_SMPU_STRUCT_V2_ADDR1_SUBREGION_DISABLE_Msk 2404 #define PROT_SMPU_SMPU_STRUCT_ADDR1_ADDR24_Pos PROT_SMPU_SMPU_STRUCT_V2_ADDR1_ADDR24_Pos 2405 #define PROT_SMPU_SMPU_STRUCT_ADDR1_ADDR24_Msk PROT_SMPU_SMPU_STRUCT_V2_ADDR1_ADDR24_Msk 2406 /* PROT_SMPU_SMPU_STRUCT.ATT1 */ 2407 #define PROT_SMPU_SMPU_STRUCT_ATT1_UR_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT1_UR_Pos 2408 #define PROT_SMPU_SMPU_STRUCT_ATT1_UR_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT1_UR_Msk 2409 #define PROT_SMPU_SMPU_STRUCT_ATT1_UW_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT1_UW_Pos 2410 #define PROT_SMPU_SMPU_STRUCT_ATT1_UW_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT1_UW_Msk 2411 #define PROT_SMPU_SMPU_STRUCT_ATT1_UX_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT1_UX_Pos 2412 #define PROT_SMPU_SMPU_STRUCT_ATT1_UX_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT1_UX_Msk 2413 #define PROT_SMPU_SMPU_STRUCT_ATT1_PR_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT1_PR_Pos 2414 #define PROT_SMPU_SMPU_STRUCT_ATT1_PR_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT1_PR_Msk 2415 #define PROT_SMPU_SMPU_STRUCT_ATT1_PW_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT1_PW_Pos 2416 #define PROT_SMPU_SMPU_STRUCT_ATT1_PW_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT1_PW_Msk 2417 #define PROT_SMPU_SMPU_STRUCT_ATT1_PX_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT1_PX_Pos 2418 #define PROT_SMPU_SMPU_STRUCT_ATT1_PX_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT1_PX_Msk 2419 #define PROT_SMPU_SMPU_STRUCT_ATT1_NS_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT1_NS_Pos 2420 #define PROT_SMPU_SMPU_STRUCT_ATT1_NS_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT1_NS_Msk 2421 #define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MASK_0_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT1_PC_MASK_0_Pos 2422 #define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MASK_0_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT1_PC_MASK_0_Msk 2423 #define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MASK_15_TO_1_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT1_PC_MASK_15_TO_1_Pos 2424 #define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MASK_15_TO_1_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT1_PC_MASK_15_TO_1_Msk 2425 #define PROT_SMPU_SMPU_STRUCT_ATT1_REGION_SIZE_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT1_REGION_SIZE_Pos 2426 #define PROT_SMPU_SMPU_STRUCT_ATT1_REGION_SIZE_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT1_REGION_SIZE_Msk 2427 #define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MATCH_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT1_PC_MATCH_Pos 2428 #define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MATCH_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT1_PC_MATCH_Msk 2429 #define PROT_SMPU_SMPU_STRUCT_ATT1_ENABLED_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT1_ENABLED_Pos 2430 #define PROT_SMPU_SMPU_STRUCT_ATT1_ENABLED_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT1_ENABLED_Msk 2431 /* PROT_SMPU.MS0_CTL */ 2432 #define PROT_SMPU_MS0_CTL_P_Pos PROT_SMPU_V2_MS0_CTL_P_Pos 2433 #define PROT_SMPU_MS0_CTL_P_Msk PROT_SMPU_V2_MS0_CTL_P_Msk 2434 #define PROT_SMPU_MS0_CTL_NS_Pos PROT_SMPU_V2_MS0_CTL_NS_Pos 2435 #define PROT_SMPU_MS0_CTL_NS_Msk PROT_SMPU_V2_MS0_CTL_NS_Msk 2436 #define PROT_SMPU_MS0_CTL_PRIO_Pos PROT_SMPU_V2_MS0_CTL_PRIO_Pos 2437 #define PROT_SMPU_MS0_CTL_PRIO_Msk PROT_SMPU_V2_MS0_CTL_PRIO_Msk 2438 #define PROT_SMPU_MS0_CTL_PC_MASK_0_Pos PROT_SMPU_V2_MS0_CTL_PC_MASK_0_Pos 2439 #define PROT_SMPU_MS0_CTL_PC_MASK_0_Msk PROT_SMPU_V2_MS0_CTL_PC_MASK_0_Msk 2440 #define PROT_SMPU_MS0_CTL_PC_MASK_15_TO_1_Pos PROT_SMPU_V2_MS0_CTL_PC_MASK_15_TO_1_Pos 2441 #define PROT_SMPU_MS0_CTL_PC_MASK_15_TO_1_Msk PROT_SMPU_V2_MS0_CTL_PC_MASK_15_TO_1_Msk 2442 /* PROT_SMPU.MS1_CTL */ 2443 #define PROT_SMPU_MS1_CTL_P_Pos PROT_SMPU_V2_MS1_CTL_P_Pos 2444 #define PROT_SMPU_MS1_CTL_P_Msk PROT_SMPU_V2_MS1_CTL_P_Msk 2445 #define PROT_SMPU_MS1_CTL_NS_Pos PROT_SMPU_V2_MS1_CTL_NS_Pos 2446 #define PROT_SMPU_MS1_CTL_NS_Msk PROT_SMPU_V2_MS1_CTL_NS_Msk 2447 #define PROT_SMPU_MS1_CTL_PRIO_Pos PROT_SMPU_V2_MS1_CTL_PRIO_Pos 2448 #define PROT_SMPU_MS1_CTL_PRIO_Msk PROT_SMPU_V2_MS1_CTL_PRIO_Msk 2449 #define PROT_SMPU_MS1_CTL_PC_MASK_0_Pos PROT_SMPU_V2_MS1_CTL_PC_MASK_0_Pos 2450 #define PROT_SMPU_MS1_CTL_PC_MASK_0_Msk PROT_SMPU_V2_MS1_CTL_PC_MASK_0_Msk 2451 #define PROT_SMPU_MS1_CTL_PC_MASK_15_TO_1_Pos PROT_SMPU_V2_MS1_CTL_PC_MASK_15_TO_1_Pos 2452 #define PROT_SMPU_MS1_CTL_PC_MASK_15_TO_1_Msk PROT_SMPU_V2_MS1_CTL_PC_MASK_15_TO_1_Msk 2453 /* PROT_SMPU.MS2_CTL */ 2454 #define PROT_SMPU_MS2_CTL_P_Pos PROT_SMPU_V2_MS2_CTL_P_Pos 2455 #define PROT_SMPU_MS2_CTL_P_Msk PROT_SMPU_V2_MS2_CTL_P_Msk 2456 #define PROT_SMPU_MS2_CTL_NS_Pos PROT_SMPU_V2_MS2_CTL_NS_Pos 2457 #define PROT_SMPU_MS2_CTL_NS_Msk PROT_SMPU_V2_MS2_CTL_NS_Msk 2458 #define PROT_SMPU_MS2_CTL_PRIO_Pos PROT_SMPU_V2_MS2_CTL_PRIO_Pos 2459 #define PROT_SMPU_MS2_CTL_PRIO_Msk PROT_SMPU_V2_MS2_CTL_PRIO_Msk 2460 #define PROT_SMPU_MS2_CTL_PC_MASK_0_Pos PROT_SMPU_V2_MS2_CTL_PC_MASK_0_Pos 2461 #define PROT_SMPU_MS2_CTL_PC_MASK_0_Msk PROT_SMPU_V2_MS2_CTL_PC_MASK_0_Msk 2462 #define PROT_SMPU_MS2_CTL_PC_MASK_15_TO_1_Pos PROT_SMPU_V2_MS2_CTL_PC_MASK_15_TO_1_Pos 2463 #define PROT_SMPU_MS2_CTL_PC_MASK_15_TO_1_Msk PROT_SMPU_V2_MS2_CTL_PC_MASK_15_TO_1_Msk 2464 /* PROT_SMPU.MS3_CTL */ 2465 #define PROT_SMPU_MS3_CTL_P_Pos PROT_SMPU_V2_MS3_CTL_P_Pos 2466 #define PROT_SMPU_MS3_CTL_P_Msk PROT_SMPU_V2_MS3_CTL_P_Msk 2467 #define PROT_SMPU_MS3_CTL_NS_Pos PROT_SMPU_V2_MS3_CTL_NS_Pos 2468 #define PROT_SMPU_MS3_CTL_NS_Msk PROT_SMPU_V2_MS3_CTL_NS_Msk 2469 #define PROT_SMPU_MS3_CTL_PRIO_Pos PROT_SMPU_V2_MS3_CTL_PRIO_Pos 2470 #define PROT_SMPU_MS3_CTL_PRIO_Msk PROT_SMPU_V2_MS3_CTL_PRIO_Msk 2471 #define PROT_SMPU_MS3_CTL_PC_MASK_0_Pos PROT_SMPU_V2_MS3_CTL_PC_MASK_0_Pos 2472 #define PROT_SMPU_MS3_CTL_PC_MASK_0_Msk PROT_SMPU_V2_MS3_CTL_PC_MASK_0_Msk 2473 #define PROT_SMPU_MS3_CTL_PC_MASK_15_TO_1_Pos PROT_SMPU_V2_MS3_CTL_PC_MASK_15_TO_1_Pos 2474 #define PROT_SMPU_MS3_CTL_PC_MASK_15_TO_1_Msk PROT_SMPU_V2_MS3_CTL_PC_MASK_15_TO_1_Msk 2475 /* PROT_SMPU.MS4_CTL */ 2476 #define PROT_SMPU_MS4_CTL_P_Pos PROT_SMPU_V2_MS4_CTL_P_Pos 2477 #define PROT_SMPU_MS4_CTL_P_Msk PROT_SMPU_V2_MS4_CTL_P_Msk 2478 #define PROT_SMPU_MS4_CTL_NS_Pos PROT_SMPU_V2_MS4_CTL_NS_Pos 2479 #define PROT_SMPU_MS4_CTL_NS_Msk PROT_SMPU_V2_MS4_CTL_NS_Msk 2480 #define PROT_SMPU_MS4_CTL_PRIO_Pos PROT_SMPU_V2_MS4_CTL_PRIO_Pos 2481 #define PROT_SMPU_MS4_CTL_PRIO_Msk PROT_SMPU_V2_MS4_CTL_PRIO_Msk 2482 #define PROT_SMPU_MS4_CTL_PC_MASK_0_Pos PROT_SMPU_V2_MS4_CTL_PC_MASK_0_Pos 2483 #define PROT_SMPU_MS4_CTL_PC_MASK_0_Msk PROT_SMPU_V2_MS4_CTL_PC_MASK_0_Msk 2484 #define PROT_SMPU_MS4_CTL_PC_MASK_15_TO_1_Pos PROT_SMPU_V2_MS4_CTL_PC_MASK_15_TO_1_Pos 2485 #define PROT_SMPU_MS4_CTL_PC_MASK_15_TO_1_Msk PROT_SMPU_V2_MS4_CTL_PC_MASK_15_TO_1_Msk 2486 /* PROT_SMPU.MS5_CTL */ 2487 #define PROT_SMPU_MS5_CTL_P_Pos PROT_SMPU_V2_MS5_CTL_P_Pos 2488 #define PROT_SMPU_MS5_CTL_P_Msk PROT_SMPU_V2_MS5_CTL_P_Msk 2489 #define PROT_SMPU_MS5_CTL_NS_Pos PROT_SMPU_V2_MS5_CTL_NS_Pos 2490 #define PROT_SMPU_MS5_CTL_NS_Msk PROT_SMPU_V2_MS5_CTL_NS_Msk 2491 #define PROT_SMPU_MS5_CTL_PRIO_Pos PROT_SMPU_V2_MS5_CTL_PRIO_Pos 2492 #define PROT_SMPU_MS5_CTL_PRIO_Msk PROT_SMPU_V2_MS5_CTL_PRIO_Msk 2493 #define PROT_SMPU_MS5_CTL_PC_MASK_0_Pos PROT_SMPU_V2_MS5_CTL_PC_MASK_0_Pos 2494 #define PROT_SMPU_MS5_CTL_PC_MASK_0_Msk PROT_SMPU_V2_MS5_CTL_PC_MASK_0_Msk 2495 #define PROT_SMPU_MS5_CTL_PC_MASK_15_TO_1_Pos PROT_SMPU_V2_MS5_CTL_PC_MASK_15_TO_1_Pos 2496 #define PROT_SMPU_MS5_CTL_PC_MASK_15_TO_1_Msk PROT_SMPU_V2_MS5_CTL_PC_MASK_15_TO_1_Msk 2497 /* PROT_SMPU.MS6_CTL */ 2498 #define PROT_SMPU_MS6_CTL_P_Pos PROT_SMPU_V2_MS6_CTL_P_Pos 2499 #define PROT_SMPU_MS6_CTL_P_Msk PROT_SMPU_V2_MS6_CTL_P_Msk 2500 #define PROT_SMPU_MS6_CTL_NS_Pos PROT_SMPU_V2_MS6_CTL_NS_Pos 2501 #define PROT_SMPU_MS6_CTL_NS_Msk PROT_SMPU_V2_MS6_CTL_NS_Msk 2502 #define PROT_SMPU_MS6_CTL_PRIO_Pos PROT_SMPU_V2_MS6_CTL_PRIO_Pos 2503 #define PROT_SMPU_MS6_CTL_PRIO_Msk PROT_SMPU_V2_MS6_CTL_PRIO_Msk 2504 #define PROT_SMPU_MS6_CTL_PC_MASK_0_Pos PROT_SMPU_V2_MS6_CTL_PC_MASK_0_Pos 2505 #define PROT_SMPU_MS6_CTL_PC_MASK_0_Msk PROT_SMPU_V2_MS6_CTL_PC_MASK_0_Msk 2506 #define PROT_SMPU_MS6_CTL_PC_MASK_15_TO_1_Pos PROT_SMPU_V2_MS6_CTL_PC_MASK_15_TO_1_Pos 2507 #define PROT_SMPU_MS6_CTL_PC_MASK_15_TO_1_Msk PROT_SMPU_V2_MS6_CTL_PC_MASK_15_TO_1_Msk 2508 /* PROT_SMPU.MS7_CTL */ 2509 #define PROT_SMPU_MS7_CTL_P_Pos PROT_SMPU_V2_MS7_CTL_P_Pos 2510 #define PROT_SMPU_MS7_CTL_P_Msk PROT_SMPU_V2_MS7_CTL_P_Msk 2511 #define PROT_SMPU_MS7_CTL_NS_Pos PROT_SMPU_V2_MS7_CTL_NS_Pos 2512 #define PROT_SMPU_MS7_CTL_NS_Msk PROT_SMPU_V2_MS7_CTL_NS_Msk 2513 #define PROT_SMPU_MS7_CTL_PRIO_Pos PROT_SMPU_V2_MS7_CTL_PRIO_Pos 2514 #define PROT_SMPU_MS7_CTL_PRIO_Msk PROT_SMPU_V2_MS7_CTL_PRIO_Msk 2515 #define PROT_SMPU_MS7_CTL_PC_MASK_0_Pos PROT_SMPU_V2_MS7_CTL_PC_MASK_0_Pos 2516 #define PROT_SMPU_MS7_CTL_PC_MASK_0_Msk PROT_SMPU_V2_MS7_CTL_PC_MASK_0_Msk 2517 #define PROT_SMPU_MS7_CTL_PC_MASK_15_TO_1_Pos PROT_SMPU_V2_MS7_CTL_PC_MASK_15_TO_1_Pos 2518 #define PROT_SMPU_MS7_CTL_PC_MASK_15_TO_1_Msk PROT_SMPU_V2_MS7_CTL_PC_MASK_15_TO_1_Msk 2519 /* PROT_SMPU.MS8_CTL */ 2520 #define PROT_SMPU_MS8_CTL_P_Pos PROT_SMPU_V2_MS8_CTL_P_Pos 2521 #define PROT_SMPU_MS8_CTL_P_Msk PROT_SMPU_V2_MS8_CTL_P_Msk 2522 #define PROT_SMPU_MS8_CTL_NS_Pos PROT_SMPU_V2_MS8_CTL_NS_Pos 2523 #define PROT_SMPU_MS8_CTL_NS_Msk PROT_SMPU_V2_MS8_CTL_NS_Msk 2524 #define PROT_SMPU_MS8_CTL_PRIO_Pos PROT_SMPU_V2_MS8_CTL_PRIO_Pos 2525 #define PROT_SMPU_MS8_CTL_PRIO_Msk PROT_SMPU_V2_MS8_CTL_PRIO_Msk 2526 #define PROT_SMPU_MS8_CTL_PC_MASK_0_Pos PROT_SMPU_V2_MS8_CTL_PC_MASK_0_Pos 2527 #define PROT_SMPU_MS8_CTL_PC_MASK_0_Msk PROT_SMPU_V2_MS8_CTL_PC_MASK_0_Msk 2528 #define PROT_SMPU_MS8_CTL_PC_MASK_15_TO_1_Pos PROT_SMPU_V2_MS8_CTL_PC_MASK_15_TO_1_Pos 2529 #define PROT_SMPU_MS8_CTL_PC_MASK_15_TO_1_Msk PROT_SMPU_V2_MS8_CTL_PC_MASK_15_TO_1_Msk 2530 /* PROT_SMPU.MS9_CTL */ 2531 #define PROT_SMPU_MS9_CTL_P_Pos PROT_SMPU_V2_MS9_CTL_P_Pos 2532 #define PROT_SMPU_MS9_CTL_P_Msk PROT_SMPU_V2_MS9_CTL_P_Msk 2533 #define PROT_SMPU_MS9_CTL_NS_Pos PROT_SMPU_V2_MS9_CTL_NS_Pos 2534 #define PROT_SMPU_MS9_CTL_NS_Msk PROT_SMPU_V2_MS9_CTL_NS_Msk 2535 #define PROT_SMPU_MS9_CTL_PRIO_Pos PROT_SMPU_V2_MS9_CTL_PRIO_Pos 2536 #define PROT_SMPU_MS9_CTL_PRIO_Msk PROT_SMPU_V2_MS9_CTL_PRIO_Msk 2537 #define PROT_SMPU_MS9_CTL_PC_MASK_0_Pos PROT_SMPU_V2_MS9_CTL_PC_MASK_0_Pos 2538 #define PROT_SMPU_MS9_CTL_PC_MASK_0_Msk PROT_SMPU_V2_MS9_CTL_PC_MASK_0_Msk 2539 #define PROT_SMPU_MS9_CTL_PC_MASK_15_TO_1_Pos PROT_SMPU_V2_MS9_CTL_PC_MASK_15_TO_1_Pos 2540 #define PROT_SMPU_MS9_CTL_PC_MASK_15_TO_1_Msk PROT_SMPU_V2_MS9_CTL_PC_MASK_15_TO_1_Msk 2541 /* PROT_SMPU.MS10_CTL */ 2542 #define PROT_SMPU_MS10_CTL_P_Pos PROT_SMPU_V2_MS10_CTL_P_Pos 2543 #define PROT_SMPU_MS10_CTL_P_Msk PROT_SMPU_V2_MS10_CTL_P_Msk 2544 #define PROT_SMPU_MS10_CTL_NS_Pos PROT_SMPU_V2_MS10_CTL_NS_Pos 2545 #define PROT_SMPU_MS10_CTL_NS_Msk PROT_SMPU_V2_MS10_CTL_NS_Msk 2546 #define PROT_SMPU_MS10_CTL_PRIO_Pos PROT_SMPU_V2_MS10_CTL_PRIO_Pos 2547 #define PROT_SMPU_MS10_CTL_PRIO_Msk PROT_SMPU_V2_MS10_CTL_PRIO_Msk 2548 #define PROT_SMPU_MS10_CTL_PC_MASK_0_Pos PROT_SMPU_V2_MS10_CTL_PC_MASK_0_Pos 2549 #define PROT_SMPU_MS10_CTL_PC_MASK_0_Msk PROT_SMPU_V2_MS10_CTL_PC_MASK_0_Msk 2550 #define PROT_SMPU_MS10_CTL_PC_MASK_15_TO_1_Pos PROT_SMPU_V2_MS10_CTL_PC_MASK_15_TO_1_Pos 2551 #define PROT_SMPU_MS10_CTL_PC_MASK_15_TO_1_Msk PROT_SMPU_V2_MS10_CTL_PC_MASK_15_TO_1_Msk 2552 /* PROT_SMPU.MS11_CTL */ 2553 #define PROT_SMPU_MS11_CTL_P_Pos PROT_SMPU_V2_MS11_CTL_P_Pos 2554 #define PROT_SMPU_MS11_CTL_P_Msk PROT_SMPU_V2_MS11_CTL_P_Msk 2555 #define PROT_SMPU_MS11_CTL_NS_Pos PROT_SMPU_V2_MS11_CTL_NS_Pos 2556 #define PROT_SMPU_MS11_CTL_NS_Msk PROT_SMPU_V2_MS11_CTL_NS_Msk 2557 #define PROT_SMPU_MS11_CTL_PRIO_Pos PROT_SMPU_V2_MS11_CTL_PRIO_Pos 2558 #define PROT_SMPU_MS11_CTL_PRIO_Msk PROT_SMPU_V2_MS11_CTL_PRIO_Msk 2559 #define PROT_SMPU_MS11_CTL_PC_MASK_0_Pos PROT_SMPU_V2_MS11_CTL_PC_MASK_0_Pos 2560 #define PROT_SMPU_MS11_CTL_PC_MASK_0_Msk PROT_SMPU_V2_MS11_CTL_PC_MASK_0_Msk 2561 #define PROT_SMPU_MS11_CTL_PC_MASK_15_TO_1_Pos PROT_SMPU_V2_MS11_CTL_PC_MASK_15_TO_1_Pos 2562 #define PROT_SMPU_MS11_CTL_PC_MASK_15_TO_1_Msk PROT_SMPU_V2_MS11_CTL_PC_MASK_15_TO_1_Msk 2563 /* PROT_SMPU.MS12_CTL */ 2564 #define PROT_SMPU_MS12_CTL_P_Pos PROT_SMPU_V2_MS12_CTL_P_Pos 2565 #define PROT_SMPU_MS12_CTL_P_Msk PROT_SMPU_V2_MS12_CTL_P_Msk 2566 #define PROT_SMPU_MS12_CTL_NS_Pos PROT_SMPU_V2_MS12_CTL_NS_Pos 2567 #define PROT_SMPU_MS12_CTL_NS_Msk PROT_SMPU_V2_MS12_CTL_NS_Msk 2568 #define PROT_SMPU_MS12_CTL_PRIO_Pos PROT_SMPU_V2_MS12_CTL_PRIO_Pos 2569 #define PROT_SMPU_MS12_CTL_PRIO_Msk PROT_SMPU_V2_MS12_CTL_PRIO_Msk 2570 #define PROT_SMPU_MS12_CTL_PC_MASK_0_Pos PROT_SMPU_V2_MS12_CTL_PC_MASK_0_Pos 2571 #define PROT_SMPU_MS12_CTL_PC_MASK_0_Msk PROT_SMPU_V2_MS12_CTL_PC_MASK_0_Msk 2572 #define PROT_SMPU_MS12_CTL_PC_MASK_15_TO_1_Pos PROT_SMPU_V2_MS12_CTL_PC_MASK_15_TO_1_Pos 2573 #define PROT_SMPU_MS12_CTL_PC_MASK_15_TO_1_Msk PROT_SMPU_V2_MS12_CTL_PC_MASK_15_TO_1_Msk 2574 /* PROT_SMPU.MS13_CTL */ 2575 #define PROT_SMPU_MS13_CTL_P_Pos PROT_SMPU_V2_MS13_CTL_P_Pos 2576 #define PROT_SMPU_MS13_CTL_P_Msk PROT_SMPU_V2_MS13_CTL_P_Msk 2577 #define PROT_SMPU_MS13_CTL_NS_Pos PROT_SMPU_V2_MS13_CTL_NS_Pos 2578 #define PROT_SMPU_MS13_CTL_NS_Msk PROT_SMPU_V2_MS13_CTL_NS_Msk 2579 #define PROT_SMPU_MS13_CTL_PRIO_Pos PROT_SMPU_V2_MS13_CTL_PRIO_Pos 2580 #define PROT_SMPU_MS13_CTL_PRIO_Msk PROT_SMPU_V2_MS13_CTL_PRIO_Msk 2581 #define PROT_SMPU_MS13_CTL_PC_MASK_0_Pos PROT_SMPU_V2_MS13_CTL_PC_MASK_0_Pos 2582 #define PROT_SMPU_MS13_CTL_PC_MASK_0_Msk PROT_SMPU_V2_MS13_CTL_PC_MASK_0_Msk 2583 #define PROT_SMPU_MS13_CTL_PC_MASK_15_TO_1_Pos PROT_SMPU_V2_MS13_CTL_PC_MASK_15_TO_1_Pos 2584 #define PROT_SMPU_MS13_CTL_PC_MASK_15_TO_1_Msk PROT_SMPU_V2_MS13_CTL_PC_MASK_15_TO_1_Msk 2585 /* PROT_SMPU.MS14_CTL */ 2586 #define PROT_SMPU_MS14_CTL_P_Pos PROT_SMPU_V2_MS14_CTL_P_Pos 2587 #define PROT_SMPU_MS14_CTL_P_Msk PROT_SMPU_V2_MS14_CTL_P_Msk 2588 #define PROT_SMPU_MS14_CTL_NS_Pos PROT_SMPU_V2_MS14_CTL_NS_Pos 2589 #define PROT_SMPU_MS14_CTL_NS_Msk PROT_SMPU_V2_MS14_CTL_NS_Msk 2590 #define PROT_SMPU_MS14_CTL_PRIO_Pos PROT_SMPU_V2_MS14_CTL_PRIO_Pos 2591 #define PROT_SMPU_MS14_CTL_PRIO_Msk PROT_SMPU_V2_MS14_CTL_PRIO_Msk 2592 #define PROT_SMPU_MS14_CTL_PC_MASK_0_Pos PROT_SMPU_V2_MS14_CTL_PC_MASK_0_Pos 2593 #define PROT_SMPU_MS14_CTL_PC_MASK_0_Msk PROT_SMPU_V2_MS14_CTL_PC_MASK_0_Msk 2594 #define PROT_SMPU_MS14_CTL_PC_MASK_15_TO_1_Pos PROT_SMPU_V2_MS14_CTL_PC_MASK_15_TO_1_Pos 2595 #define PROT_SMPU_MS14_CTL_PC_MASK_15_TO_1_Msk PROT_SMPU_V2_MS14_CTL_PC_MASK_15_TO_1_Msk 2596 /* PROT_SMPU.MS15_CTL */ 2597 #define PROT_SMPU_MS15_CTL_P_Pos PROT_SMPU_V2_MS15_CTL_P_Pos 2598 #define PROT_SMPU_MS15_CTL_P_Msk PROT_SMPU_V2_MS15_CTL_P_Msk 2599 #define PROT_SMPU_MS15_CTL_NS_Pos PROT_SMPU_V2_MS15_CTL_NS_Pos 2600 #define PROT_SMPU_MS15_CTL_NS_Msk PROT_SMPU_V2_MS15_CTL_NS_Msk 2601 #define PROT_SMPU_MS15_CTL_PRIO_Pos PROT_SMPU_V2_MS15_CTL_PRIO_Pos 2602 #define PROT_SMPU_MS15_CTL_PRIO_Msk PROT_SMPU_V2_MS15_CTL_PRIO_Msk 2603 #define PROT_SMPU_MS15_CTL_PC_MASK_0_Pos PROT_SMPU_V2_MS15_CTL_PC_MASK_0_Pos 2604 #define PROT_SMPU_MS15_CTL_PC_MASK_0_Msk PROT_SMPU_V2_MS15_CTL_PC_MASK_0_Msk 2605 #define PROT_SMPU_MS15_CTL_PC_MASK_15_TO_1_Pos PROT_SMPU_V2_MS15_CTL_PC_MASK_15_TO_1_Pos 2606 #define PROT_SMPU_MS15_CTL_PC_MASK_15_TO_1_Msk PROT_SMPU_V2_MS15_CTL_PC_MASK_15_TO_1_Msk 2607 /* PROT_MPU_MPU_STRUCT.ADDR */ 2608 #define PROT_MPU_MPU_STRUCT_ADDR_SUBREGION_DISABLE_Pos PROT_MPU_MPU_STRUCT_V2_ADDR_SUBREGION_DISABLE_Pos 2609 #define PROT_MPU_MPU_STRUCT_ADDR_SUBREGION_DISABLE_Msk PROT_MPU_MPU_STRUCT_V2_ADDR_SUBREGION_DISABLE_Msk 2610 #define PROT_MPU_MPU_STRUCT_ADDR_ADDR24_Pos PROT_MPU_MPU_STRUCT_V2_ADDR_ADDR24_Pos 2611 #define PROT_MPU_MPU_STRUCT_ADDR_ADDR24_Msk PROT_MPU_MPU_STRUCT_V2_ADDR_ADDR24_Msk 2612 /* PROT_MPU_MPU_STRUCT.ATT */ 2613 #define PROT_MPU_MPU_STRUCT_ATT_UR_Pos PROT_MPU_MPU_STRUCT_V2_ATT_UR_Pos 2614 #define PROT_MPU_MPU_STRUCT_ATT_UR_Msk PROT_MPU_MPU_STRUCT_V2_ATT_UR_Msk 2615 #define PROT_MPU_MPU_STRUCT_ATT_UW_Pos PROT_MPU_MPU_STRUCT_V2_ATT_UW_Pos 2616 #define PROT_MPU_MPU_STRUCT_ATT_UW_Msk PROT_MPU_MPU_STRUCT_V2_ATT_UW_Msk 2617 #define PROT_MPU_MPU_STRUCT_ATT_UX_Pos PROT_MPU_MPU_STRUCT_V2_ATT_UX_Pos 2618 #define PROT_MPU_MPU_STRUCT_ATT_UX_Msk PROT_MPU_MPU_STRUCT_V2_ATT_UX_Msk 2619 #define PROT_MPU_MPU_STRUCT_ATT_PR_Pos PROT_MPU_MPU_STRUCT_V2_ATT_PR_Pos 2620 #define PROT_MPU_MPU_STRUCT_ATT_PR_Msk PROT_MPU_MPU_STRUCT_V2_ATT_PR_Msk 2621 #define PROT_MPU_MPU_STRUCT_ATT_PW_Pos PROT_MPU_MPU_STRUCT_V2_ATT_PW_Pos 2622 #define PROT_MPU_MPU_STRUCT_ATT_PW_Msk PROT_MPU_MPU_STRUCT_V2_ATT_PW_Msk 2623 #define PROT_MPU_MPU_STRUCT_ATT_PX_Pos PROT_MPU_MPU_STRUCT_V2_ATT_PX_Pos 2624 #define PROT_MPU_MPU_STRUCT_ATT_PX_Msk PROT_MPU_MPU_STRUCT_V2_ATT_PX_Msk 2625 #define PROT_MPU_MPU_STRUCT_ATT_NS_Pos PROT_MPU_MPU_STRUCT_V2_ATT_NS_Pos 2626 #define PROT_MPU_MPU_STRUCT_ATT_NS_Msk PROT_MPU_MPU_STRUCT_V2_ATT_NS_Msk 2627 #define PROT_MPU_MPU_STRUCT_ATT_REGION_SIZE_Pos PROT_MPU_MPU_STRUCT_V2_ATT_REGION_SIZE_Pos 2628 #define PROT_MPU_MPU_STRUCT_ATT_REGION_SIZE_Msk PROT_MPU_MPU_STRUCT_V2_ATT_REGION_SIZE_Msk 2629 #define PROT_MPU_MPU_STRUCT_ATT_ENABLED_Pos PROT_MPU_MPU_STRUCT_V2_ATT_ENABLED_Pos 2630 #define PROT_MPU_MPU_STRUCT_ATT_ENABLED_Msk PROT_MPU_MPU_STRUCT_V2_ATT_ENABLED_Msk 2631 /* PROT_MPU.MS_CTL */ 2632 #define PROT_MPU_MS_CTL_PC_Pos PROT_MPU_V2_MS_CTL_PC_Pos 2633 #define PROT_MPU_MS_CTL_PC_Msk PROT_MPU_V2_MS_CTL_PC_Msk 2634 #define PROT_MPU_MS_CTL_PC_SAVED_Pos PROT_MPU_V2_MS_CTL_PC_SAVED_Pos 2635 #define PROT_MPU_MS_CTL_PC_SAVED_Msk PROT_MPU_V2_MS_CTL_PC_SAVED_Msk 2636 /* PROT_MPU.MS_CTL_READ_MIR */ 2637 #define PROT_MPU_MS_CTL_READ_MIR_PC_Pos PROT_MPU_V2_MS_CTL_READ_MIR_PC_Pos 2638 #define PROT_MPU_MS_CTL_READ_MIR_PC_Msk PROT_MPU_V2_MS_CTL_READ_MIR_PC_Msk 2639 #define PROT_MPU_MS_CTL_READ_MIR_PC_SAVED_Pos PROT_MPU_V2_MS_CTL_READ_MIR_PC_SAVED_Pos 2640 #define PROT_MPU_MS_CTL_READ_MIR_PC_SAVED_Msk PROT_MPU_V2_MS_CTL_READ_MIR_PC_SAVED_Msk 2641 2642 2643 /******************************************************************************* 2644 * SCB 2645 *******************************************************************************/ 2646 /* SCB.CTRL */ 2647 #define SCB_CTRL_OVS_Pos SCB_V2_CTRL_OVS_Pos 2648 #define SCB_CTRL_OVS_Msk SCB_V2_CTRL_OVS_Msk 2649 #define SCB_CTRL_EC_AM_MODE_Pos SCB_V2_CTRL_EC_AM_MODE_Pos 2650 #define SCB_CTRL_EC_AM_MODE_Msk SCB_V2_CTRL_EC_AM_MODE_Msk 2651 #define SCB_CTRL_EC_OP_MODE_Pos SCB_V2_CTRL_EC_OP_MODE_Pos 2652 #define SCB_CTRL_EC_OP_MODE_Msk SCB_V2_CTRL_EC_OP_MODE_Msk 2653 #define SCB_CTRL_EZ_MODE_Pos SCB_V2_CTRL_EZ_MODE_Pos 2654 #define SCB_CTRL_EZ_MODE_Msk SCB_V2_CTRL_EZ_MODE_Msk 2655 #define SCB_CTRL_CMD_RESP_MODE_Pos SCB_V2_CTRL_CMD_RESP_MODE_Pos 2656 #define SCB_CTRL_CMD_RESP_MODE_Msk SCB_V2_CTRL_CMD_RESP_MODE_Msk 2657 #define SCB_CTRL_MEM_WIDTH_Pos SCB_V2_CTRL_MEM_WIDTH_Pos 2658 #define SCB_CTRL_MEM_WIDTH_Msk SCB_V2_CTRL_MEM_WIDTH_Msk 2659 #define SCB_CTRL_ADDR_ACCEPT_Pos SCB_V2_CTRL_ADDR_ACCEPT_Pos 2660 #define SCB_CTRL_ADDR_ACCEPT_Msk SCB_V2_CTRL_ADDR_ACCEPT_Msk 2661 #define SCB_CTRL_BLOCK_Pos SCB_V2_CTRL_BLOCK_Pos 2662 #define SCB_CTRL_BLOCK_Msk SCB_V2_CTRL_BLOCK_Msk 2663 #define SCB_CTRL_MODE_Pos SCB_V2_CTRL_MODE_Pos 2664 #define SCB_CTRL_MODE_Msk SCB_V2_CTRL_MODE_Msk 2665 #define SCB_CTRL_EC_ACCESS_Pos SCB_V2_CTRL_EC_ACCESS_Pos 2666 #define SCB_CTRL_EC_ACCESS_Msk SCB_V2_CTRL_EC_ACCESS_Msk 2667 #define SCB_CTRL_ENABLED_Pos SCB_V2_CTRL_ENABLED_Pos 2668 #define SCB_CTRL_ENABLED_Msk SCB_V2_CTRL_ENABLED_Msk 2669 /* SCB.STATUS */ 2670 #define SCB_STATUS_EC_BUSY_Pos SCB_V2_STATUS_EC_BUSY_Pos 2671 #define SCB_STATUS_EC_BUSY_Msk SCB_V2_STATUS_EC_BUSY_Msk 2672 /* SCB.CMD_RESP_CTRL */ 2673 #define SCB_CMD_RESP_CTRL_BASE_RD_ADDR_Pos SCB_V2_CMD_RESP_CTRL_BASE_RD_ADDR_Pos 2674 #define SCB_CMD_RESP_CTRL_BASE_RD_ADDR_Msk SCB_V2_CMD_RESP_CTRL_BASE_RD_ADDR_Msk 2675 #define SCB_CMD_RESP_CTRL_BASE_WR_ADDR_Pos SCB_V2_CMD_RESP_CTRL_BASE_WR_ADDR_Pos 2676 #define SCB_CMD_RESP_CTRL_BASE_WR_ADDR_Msk SCB_V2_CMD_RESP_CTRL_BASE_WR_ADDR_Msk 2677 /* SCB.CMD_RESP_STATUS */ 2678 #define SCB_CMD_RESP_STATUS_CURR_RD_ADDR_Pos SCB_V2_CMD_RESP_STATUS_CURR_RD_ADDR_Pos 2679 #define SCB_CMD_RESP_STATUS_CURR_RD_ADDR_Msk SCB_V2_CMD_RESP_STATUS_CURR_RD_ADDR_Msk 2680 #define SCB_CMD_RESP_STATUS_CURR_WR_ADDR_Pos SCB_V2_CMD_RESP_STATUS_CURR_WR_ADDR_Pos 2681 #define SCB_CMD_RESP_STATUS_CURR_WR_ADDR_Msk SCB_V2_CMD_RESP_STATUS_CURR_WR_ADDR_Msk 2682 #define SCB_CMD_RESP_STATUS_CMD_RESP_EC_BUS_BUSY_Pos SCB_V2_CMD_RESP_STATUS_CMD_RESP_EC_BUS_BUSY_Pos 2683 #define SCB_CMD_RESP_STATUS_CMD_RESP_EC_BUS_BUSY_Msk SCB_V2_CMD_RESP_STATUS_CMD_RESP_EC_BUS_BUSY_Msk 2684 #define SCB_CMD_RESP_STATUS_CMD_RESP_EC_BUSY_Pos SCB_V2_CMD_RESP_STATUS_CMD_RESP_EC_BUSY_Pos 2685 #define SCB_CMD_RESP_STATUS_CMD_RESP_EC_BUSY_Msk SCB_V2_CMD_RESP_STATUS_CMD_RESP_EC_BUSY_Msk 2686 /* SCB.SPI_CTRL */ 2687 #define SCB_SPI_CTRL_SSEL_CONTINUOUS_Pos SCB_V2_SPI_CTRL_SSEL_CONTINUOUS_Pos 2688 #define SCB_SPI_CTRL_SSEL_CONTINUOUS_Msk SCB_V2_SPI_CTRL_SSEL_CONTINUOUS_Msk 2689 #define SCB_SPI_CTRL_SELECT_PRECEDE_Pos SCB_V2_SPI_CTRL_SELECT_PRECEDE_Pos 2690 #define SCB_SPI_CTRL_SELECT_PRECEDE_Msk SCB_V2_SPI_CTRL_SELECT_PRECEDE_Msk 2691 #define SCB_SPI_CTRL_CPHA_Pos SCB_V2_SPI_CTRL_CPHA_Pos 2692 #define SCB_SPI_CTRL_CPHA_Msk SCB_V2_SPI_CTRL_CPHA_Msk 2693 #define SCB_SPI_CTRL_CPOL_Pos SCB_V2_SPI_CTRL_CPOL_Pos 2694 #define SCB_SPI_CTRL_CPOL_Msk SCB_V2_SPI_CTRL_CPOL_Msk 2695 #define SCB_SPI_CTRL_LATE_MISO_SAMPLE_Pos SCB_V2_SPI_CTRL_LATE_MISO_SAMPLE_Pos 2696 #define SCB_SPI_CTRL_LATE_MISO_SAMPLE_Msk SCB_V2_SPI_CTRL_LATE_MISO_SAMPLE_Msk 2697 #define SCB_SPI_CTRL_SCLK_CONTINUOUS_Pos SCB_V2_SPI_CTRL_SCLK_CONTINUOUS_Pos 2698 #define SCB_SPI_CTRL_SCLK_CONTINUOUS_Msk SCB_V2_SPI_CTRL_SCLK_CONTINUOUS_Msk 2699 #define SCB_SPI_CTRL_SSEL_POLARITY0_Pos SCB_V2_SPI_CTRL_SSEL_POLARITY0_Pos 2700 #define SCB_SPI_CTRL_SSEL_POLARITY0_Msk SCB_V2_SPI_CTRL_SSEL_POLARITY0_Msk 2701 #define SCB_SPI_CTRL_SSEL_POLARITY1_Pos SCB_V2_SPI_CTRL_SSEL_POLARITY1_Pos 2702 #define SCB_SPI_CTRL_SSEL_POLARITY1_Msk SCB_V2_SPI_CTRL_SSEL_POLARITY1_Msk 2703 #define SCB_SPI_CTRL_SSEL_POLARITY2_Pos SCB_V2_SPI_CTRL_SSEL_POLARITY2_Pos 2704 #define SCB_SPI_CTRL_SSEL_POLARITY2_Msk SCB_V2_SPI_CTRL_SSEL_POLARITY2_Msk 2705 #define SCB_SPI_CTRL_SSEL_POLARITY3_Pos SCB_V2_SPI_CTRL_SSEL_POLARITY3_Pos 2706 #define SCB_SPI_CTRL_SSEL_POLARITY3_Msk SCB_V2_SPI_CTRL_SSEL_POLARITY3_Msk 2707 #define SCB_SPI_CTRL_SSEL_SETUP_DEL_Pos SCB_V2_SPI_CTRL_SSEL_SETUP_DEL_Pos 2708 #define SCB_SPI_CTRL_SSEL_SETUP_DEL_Msk SCB_V2_SPI_CTRL_SSEL_SETUP_DEL_Msk 2709 #define SCB_SPI_CTRL_SSEL_HOLD_DEL_Pos SCB_V2_SPI_CTRL_SSEL_HOLD_DEL_Pos 2710 #define SCB_SPI_CTRL_SSEL_HOLD_DEL_Msk SCB_V2_SPI_CTRL_SSEL_HOLD_DEL_Msk 2711 #define SCB_SPI_CTRL_SSEL_INTER_FRAME_DEL_Pos SCB_V2_SPI_CTRL_SSEL_INTER_FRAME_DEL_Pos 2712 #define SCB_SPI_CTRL_SSEL_INTER_FRAME_DEL_Msk SCB_V2_SPI_CTRL_SSEL_INTER_FRAME_DEL_Msk 2713 #define SCB_SPI_CTRL_LOOPBACK_Pos SCB_V2_SPI_CTRL_LOOPBACK_Pos 2714 #define SCB_SPI_CTRL_LOOPBACK_Msk SCB_V2_SPI_CTRL_LOOPBACK_Msk 2715 #define SCB_SPI_CTRL_MODE_Pos SCB_V2_SPI_CTRL_MODE_Pos 2716 #define SCB_SPI_CTRL_MODE_Msk SCB_V2_SPI_CTRL_MODE_Msk 2717 #define SCB_SPI_CTRL_SSEL_Pos SCB_V2_SPI_CTRL_SSEL_Pos 2718 #define SCB_SPI_CTRL_SSEL_Msk SCB_V2_SPI_CTRL_SSEL_Msk 2719 #define SCB_SPI_CTRL_MASTER_MODE_Pos SCB_V2_SPI_CTRL_MASTER_MODE_Pos 2720 #define SCB_SPI_CTRL_MASTER_MODE_Msk SCB_V2_SPI_CTRL_MASTER_MODE_Msk 2721 /* SCB.SPI_STATUS */ 2722 #define SCB_SPI_STATUS_BUS_BUSY_Pos SCB_V2_SPI_STATUS_BUS_BUSY_Pos 2723 #define SCB_SPI_STATUS_BUS_BUSY_Msk SCB_V2_SPI_STATUS_BUS_BUSY_Msk 2724 #define SCB_SPI_STATUS_SPI_EC_BUSY_Pos SCB_V2_SPI_STATUS_SPI_EC_BUSY_Pos 2725 #define SCB_SPI_STATUS_SPI_EC_BUSY_Msk SCB_V2_SPI_STATUS_SPI_EC_BUSY_Msk 2726 #define SCB_SPI_STATUS_CURR_EZ_ADDR_Pos SCB_V2_SPI_STATUS_CURR_EZ_ADDR_Pos 2727 #define SCB_SPI_STATUS_CURR_EZ_ADDR_Msk SCB_V2_SPI_STATUS_CURR_EZ_ADDR_Msk 2728 #define SCB_SPI_STATUS_BASE_EZ_ADDR_Pos SCB_V2_SPI_STATUS_BASE_EZ_ADDR_Pos 2729 #define SCB_SPI_STATUS_BASE_EZ_ADDR_Msk SCB_V2_SPI_STATUS_BASE_EZ_ADDR_Msk 2730 /* SCB.SPI_TX_CTRL */ 2731 #define SCB_SPI_TX_CTRL_PARITY_Pos SCB_V2_SPI_TX_CTRL_PARITY_Pos 2732 #define SCB_SPI_TX_CTRL_PARITY_Msk SCB_V2_SPI_TX_CTRL_PARITY_Msk 2733 #define SCB_SPI_TX_CTRL_PARITY_ENABLED_Pos SCB_V2_SPI_TX_CTRL_PARITY_ENABLED_Pos 2734 #define SCB_SPI_TX_CTRL_PARITY_ENABLED_Msk SCB_V2_SPI_TX_CTRL_PARITY_ENABLED_Msk 2735 /* SCB.SPI_RX_CTRL */ 2736 #define SCB_SPI_RX_CTRL_PARITY_Pos SCB_V2_SPI_RX_CTRL_PARITY_Pos 2737 #define SCB_SPI_RX_CTRL_PARITY_Msk SCB_V2_SPI_RX_CTRL_PARITY_Msk 2738 #define SCB_SPI_RX_CTRL_PARITY_ENABLED_Pos SCB_V2_SPI_RX_CTRL_PARITY_ENABLED_Pos 2739 #define SCB_SPI_RX_CTRL_PARITY_ENABLED_Msk SCB_V2_SPI_RX_CTRL_PARITY_ENABLED_Msk 2740 #define SCB_SPI_RX_CTRL_DROP_ON_PARITY_ERROR_Pos SCB_V2_SPI_RX_CTRL_DROP_ON_PARITY_ERROR_Pos 2741 #define SCB_SPI_RX_CTRL_DROP_ON_PARITY_ERROR_Msk SCB_V2_SPI_RX_CTRL_DROP_ON_PARITY_ERROR_Msk 2742 /* SCB.UART_CTRL */ 2743 #define SCB_UART_CTRL_LOOPBACK_Pos SCB_V2_UART_CTRL_LOOPBACK_Pos 2744 #define SCB_UART_CTRL_LOOPBACK_Msk SCB_V2_UART_CTRL_LOOPBACK_Msk 2745 #define SCB_UART_CTRL_MODE_Pos SCB_V2_UART_CTRL_MODE_Pos 2746 #define SCB_UART_CTRL_MODE_Msk SCB_V2_UART_CTRL_MODE_Msk 2747 /* SCB.UART_TX_CTRL */ 2748 #define SCB_UART_TX_CTRL_STOP_BITS_Pos SCB_V2_UART_TX_CTRL_STOP_BITS_Pos 2749 #define SCB_UART_TX_CTRL_STOP_BITS_Msk SCB_V2_UART_TX_CTRL_STOP_BITS_Msk 2750 #define SCB_UART_TX_CTRL_PARITY_Pos SCB_V2_UART_TX_CTRL_PARITY_Pos 2751 #define SCB_UART_TX_CTRL_PARITY_Msk SCB_V2_UART_TX_CTRL_PARITY_Msk 2752 #define SCB_UART_TX_CTRL_PARITY_ENABLED_Pos SCB_V2_UART_TX_CTRL_PARITY_ENABLED_Pos 2753 #define SCB_UART_TX_CTRL_PARITY_ENABLED_Msk SCB_V2_UART_TX_CTRL_PARITY_ENABLED_Msk 2754 #define SCB_UART_TX_CTRL_RETRY_ON_NACK_Pos SCB_V2_UART_TX_CTRL_RETRY_ON_NACK_Pos 2755 #define SCB_UART_TX_CTRL_RETRY_ON_NACK_Msk SCB_V2_UART_TX_CTRL_RETRY_ON_NACK_Msk 2756 /* SCB.UART_RX_CTRL */ 2757 #define SCB_UART_RX_CTRL_STOP_BITS_Pos SCB_V2_UART_RX_CTRL_STOP_BITS_Pos 2758 #define SCB_UART_RX_CTRL_STOP_BITS_Msk SCB_V2_UART_RX_CTRL_STOP_BITS_Msk 2759 #define SCB_UART_RX_CTRL_PARITY_Pos SCB_V2_UART_RX_CTRL_PARITY_Pos 2760 #define SCB_UART_RX_CTRL_PARITY_Msk SCB_V2_UART_RX_CTRL_PARITY_Msk 2761 #define SCB_UART_RX_CTRL_PARITY_ENABLED_Pos SCB_V2_UART_RX_CTRL_PARITY_ENABLED_Pos 2762 #define SCB_UART_RX_CTRL_PARITY_ENABLED_Msk SCB_V2_UART_RX_CTRL_PARITY_ENABLED_Msk 2763 #define SCB_UART_RX_CTRL_POLARITY_Pos SCB_V2_UART_RX_CTRL_POLARITY_Pos 2764 #define SCB_UART_RX_CTRL_POLARITY_Msk SCB_V2_UART_RX_CTRL_POLARITY_Msk 2765 #define SCB_UART_RX_CTRL_DROP_ON_PARITY_ERROR_Pos SCB_V2_UART_RX_CTRL_DROP_ON_PARITY_ERROR_Pos 2766 #define SCB_UART_RX_CTRL_DROP_ON_PARITY_ERROR_Msk SCB_V2_UART_RX_CTRL_DROP_ON_PARITY_ERROR_Msk 2767 #define SCB_UART_RX_CTRL_DROP_ON_FRAME_ERROR_Pos SCB_V2_UART_RX_CTRL_DROP_ON_FRAME_ERROR_Pos 2768 #define SCB_UART_RX_CTRL_DROP_ON_FRAME_ERROR_Msk SCB_V2_UART_RX_CTRL_DROP_ON_FRAME_ERROR_Msk 2769 #define SCB_UART_RX_CTRL_MP_MODE_Pos SCB_V2_UART_RX_CTRL_MP_MODE_Pos 2770 #define SCB_UART_RX_CTRL_MP_MODE_Msk SCB_V2_UART_RX_CTRL_MP_MODE_Msk 2771 #define SCB_UART_RX_CTRL_LIN_MODE_Pos SCB_V2_UART_RX_CTRL_LIN_MODE_Pos 2772 #define SCB_UART_RX_CTRL_LIN_MODE_Msk SCB_V2_UART_RX_CTRL_LIN_MODE_Msk 2773 #define SCB_UART_RX_CTRL_SKIP_START_Pos SCB_V2_UART_RX_CTRL_SKIP_START_Pos 2774 #define SCB_UART_RX_CTRL_SKIP_START_Msk SCB_V2_UART_RX_CTRL_SKIP_START_Msk 2775 #define SCB_UART_RX_CTRL_BREAK_WIDTH_Pos SCB_V2_UART_RX_CTRL_BREAK_WIDTH_Pos 2776 #define SCB_UART_RX_CTRL_BREAK_WIDTH_Msk SCB_V2_UART_RX_CTRL_BREAK_WIDTH_Msk 2777 #define SCB_UART_RX_CTRL_BREAK_LEVEL_Pos SCB_V2_UART_RX_CTRL_BREAK_LEVEL_Pos 2778 #define SCB_UART_RX_CTRL_BREAK_LEVEL_Msk SCB_V2_UART_RX_CTRL_BREAK_LEVEL_Msk 2779 /* SCB.UART_RX_STATUS */ 2780 #define SCB_UART_RX_STATUS_BR_COUNTER_Pos SCB_V2_UART_RX_STATUS_BR_COUNTER_Pos 2781 #define SCB_UART_RX_STATUS_BR_COUNTER_Msk SCB_V2_UART_RX_STATUS_BR_COUNTER_Msk 2782 /* SCB.UART_FLOW_CTRL */ 2783 #define SCB_UART_FLOW_CTRL_TRIGGER_LEVEL_Pos SCB_V2_UART_FLOW_CTRL_TRIGGER_LEVEL_Pos 2784 #define SCB_UART_FLOW_CTRL_TRIGGER_LEVEL_Msk SCB_V2_UART_FLOW_CTRL_TRIGGER_LEVEL_Msk 2785 #define SCB_UART_FLOW_CTRL_RTS_POLARITY_Pos SCB_V2_UART_FLOW_CTRL_RTS_POLARITY_Pos 2786 #define SCB_UART_FLOW_CTRL_RTS_POLARITY_Msk SCB_V2_UART_FLOW_CTRL_RTS_POLARITY_Msk 2787 #define SCB_UART_FLOW_CTRL_CTS_POLARITY_Pos SCB_V2_UART_FLOW_CTRL_CTS_POLARITY_Pos 2788 #define SCB_UART_FLOW_CTRL_CTS_POLARITY_Msk SCB_V2_UART_FLOW_CTRL_CTS_POLARITY_Msk 2789 #define SCB_UART_FLOW_CTRL_CTS_ENABLED_Pos SCB_V2_UART_FLOW_CTRL_CTS_ENABLED_Pos 2790 #define SCB_UART_FLOW_CTRL_CTS_ENABLED_Msk SCB_V2_UART_FLOW_CTRL_CTS_ENABLED_Msk 2791 /* SCB.I2C_CTRL */ 2792 #define SCB_I2C_CTRL_HIGH_PHASE_OVS_Pos SCB_V2_I2C_CTRL_HIGH_PHASE_OVS_Pos 2793 #define SCB_I2C_CTRL_HIGH_PHASE_OVS_Msk SCB_V2_I2C_CTRL_HIGH_PHASE_OVS_Msk 2794 #define SCB_I2C_CTRL_LOW_PHASE_OVS_Pos SCB_V2_I2C_CTRL_LOW_PHASE_OVS_Pos 2795 #define SCB_I2C_CTRL_LOW_PHASE_OVS_Msk SCB_V2_I2C_CTRL_LOW_PHASE_OVS_Msk 2796 #define SCB_I2C_CTRL_M_READY_DATA_ACK_Pos SCB_V2_I2C_CTRL_M_READY_DATA_ACK_Pos 2797 #define SCB_I2C_CTRL_M_READY_DATA_ACK_Msk SCB_V2_I2C_CTRL_M_READY_DATA_ACK_Msk 2798 #define SCB_I2C_CTRL_M_NOT_READY_DATA_NACK_Pos SCB_V2_I2C_CTRL_M_NOT_READY_DATA_NACK_Pos 2799 #define SCB_I2C_CTRL_M_NOT_READY_DATA_NACK_Msk SCB_V2_I2C_CTRL_M_NOT_READY_DATA_NACK_Msk 2800 #define SCB_I2C_CTRL_S_GENERAL_IGNORE_Pos SCB_V2_I2C_CTRL_S_GENERAL_IGNORE_Pos 2801 #define SCB_I2C_CTRL_S_GENERAL_IGNORE_Msk SCB_V2_I2C_CTRL_S_GENERAL_IGNORE_Msk 2802 #define SCB_I2C_CTRL_S_READY_ADDR_ACK_Pos SCB_V2_I2C_CTRL_S_READY_ADDR_ACK_Pos 2803 #define SCB_I2C_CTRL_S_READY_ADDR_ACK_Msk SCB_V2_I2C_CTRL_S_READY_ADDR_ACK_Msk 2804 #define SCB_I2C_CTRL_S_READY_DATA_ACK_Pos SCB_V2_I2C_CTRL_S_READY_DATA_ACK_Pos 2805 #define SCB_I2C_CTRL_S_READY_DATA_ACK_Msk SCB_V2_I2C_CTRL_S_READY_DATA_ACK_Msk 2806 #define SCB_I2C_CTRL_S_NOT_READY_ADDR_NACK_Pos SCB_V2_I2C_CTRL_S_NOT_READY_ADDR_NACK_Pos 2807 #define SCB_I2C_CTRL_S_NOT_READY_ADDR_NACK_Msk SCB_V2_I2C_CTRL_S_NOT_READY_ADDR_NACK_Msk 2808 #define SCB_I2C_CTRL_S_NOT_READY_DATA_NACK_Pos SCB_V2_I2C_CTRL_S_NOT_READY_DATA_NACK_Pos 2809 #define SCB_I2C_CTRL_S_NOT_READY_DATA_NACK_Msk SCB_V2_I2C_CTRL_S_NOT_READY_DATA_NACK_Msk 2810 #define SCB_I2C_CTRL_LOOPBACK_Pos SCB_V2_I2C_CTRL_LOOPBACK_Pos 2811 #define SCB_I2C_CTRL_LOOPBACK_Msk SCB_V2_I2C_CTRL_LOOPBACK_Msk 2812 #define SCB_I2C_CTRL_SLAVE_MODE_Pos SCB_V2_I2C_CTRL_SLAVE_MODE_Pos 2813 #define SCB_I2C_CTRL_SLAVE_MODE_Msk SCB_V2_I2C_CTRL_SLAVE_MODE_Msk 2814 #define SCB_I2C_CTRL_MASTER_MODE_Pos SCB_V2_I2C_CTRL_MASTER_MODE_Pos 2815 #define SCB_I2C_CTRL_MASTER_MODE_Msk SCB_V2_I2C_CTRL_MASTER_MODE_Msk 2816 /* SCB.I2C_STATUS */ 2817 #define SCB_I2C_STATUS_BUS_BUSY_Pos SCB_V2_I2C_STATUS_BUS_BUSY_Pos 2818 #define SCB_I2C_STATUS_BUS_BUSY_Msk SCB_V2_I2C_STATUS_BUS_BUSY_Msk 2819 #define SCB_I2C_STATUS_I2C_EC_BUSY_Pos SCB_V2_I2C_STATUS_I2C_EC_BUSY_Pos 2820 #define SCB_I2C_STATUS_I2C_EC_BUSY_Msk SCB_V2_I2C_STATUS_I2C_EC_BUSY_Msk 2821 #define SCB_I2C_STATUS_I2CS_IC_BUSY_Pos SCB_V2_I2C_STATUS_I2CS_IC_BUSY_Pos 2822 #define SCB_I2C_STATUS_I2CS_IC_BUSY_Msk SCB_V2_I2C_STATUS_I2CS_IC_BUSY_Msk 2823 #define SCB_I2C_STATUS_S_READ_Pos SCB_V2_I2C_STATUS_S_READ_Pos 2824 #define SCB_I2C_STATUS_S_READ_Msk SCB_V2_I2C_STATUS_S_READ_Msk 2825 #define SCB_I2C_STATUS_M_READ_Pos SCB_V2_I2C_STATUS_M_READ_Pos 2826 #define SCB_I2C_STATUS_M_READ_Msk SCB_V2_I2C_STATUS_M_READ_Msk 2827 #define SCB_I2C_STATUS_CURR_EZ_ADDR_Pos SCB_V2_I2C_STATUS_CURR_EZ_ADDR_Pos 2828 #define SCB_I2C_STATUS_CURR_EZ_ADDR_Msk SCB_V2_I2C_STATUS_CURR_EZ_ADDR_Msk 2829 #define SCB_I2C_STATUS_BASE_EZ_ADDR_Pos SCB_V2_I2C_STATUS_BASE_EZ_ADDR_Pos 2830 #define SCB_I2C_STATUS_BASE_EZ_ADDR_Msk SCB_V2_I2C_STATUS_BASE_EZ_ADDR_Msk 2831 /* SCB.I2C_M_CMD */ 2832 #define SCB_I2C_M_CMD_M_START_Pos SCB_V2_I2C_M_CMD_M_START_Pos 2833 #define SCB_I2C_M_CMD_M_START_Msk SCB_V2_I2C_M_CMD_M_START_Msk 2834 #define SCB_I2C_M_CMD_M_START_ON_IDLE_Pos SCB_V2_I2C_M_CMD_M_START_ON_IDLE_Pos 2835 #define SCB_I2C_M_CMD_M_START_ON_IDLE_Msk SCB_V2_I2C_M_CMD_M_START_ON_IDLE_Msk 2836 #define SCB_I2C_M_CMD_M_ACK_Pos SCB_V2_I2C_M_CMD_M_ACK_Pos 2837 #define SCB_I2C_M_CMD_M_ACK_Msk SCB_V2_I2C_M_CMD_M_ACK_Msk 2838 #define SCB_I2C_M_CMD_M_NACK_Pos SCB_V2_I2C_M_CMD_M_NACK_Pos 2839 #define SCB_I2C_M_CMD_M_NACK_Msk SCB_V2_I2C_M_CMD_M_NACK_Msk 2840 #define SCB_I2C_M_CMD_M_STOP_Pos SCB_V2_I2C_M_CMD_M_STOP_Pos 2841 #define SCB_I2C_M_CMD_M_STOP_Msk SCB_V2_I2C_M_CMD_M_STOP_Msk 2842 /* SCB.I2C_S_CMD */ 2843 #define SCB_I2C_S_CMD_S_ACK_Pos SCB_V2_I2C_S_CMD_S_ACK_Pos 2844 #define SCB_I2C_S_CMD_S_ACK_Msk SCB_V2_I2C_S_CMD_S_ACK_Msk 2845 #define SCB_I2C_S_CMD_S_NACK_Pos SCB_V2_I2C_S_CMD_S_NACK_Pos 2846 #define SCB_I2C_S_CMD_S_NACK_Msk SCB_V2_I2C_S_CMD_S_NACK_Msk 2847 /* SCB.I2C_CFG */ 2848 #define SCB_I2C_CFG_SDA_IN_FILT_TRIM_Pos SCB_V2_I2C_CFG_SDA_IN_FILT_TRIM_Pos 2849 #define SCB_I2C_CFG_SDA_IN_FILT_TRIM_Msk SCB_V2_I2C_CFG_SDA_IN_FILT_TRIM_Msk 2850 #define SCB_I2C_CFG_SDA_IN_FILT_SEL_Pos SCB_V2_I2C_CFG_SDA_IN_FILT_SEL_Pos 2851 #define SCB_I2C_CFG_SDA_IN_FILT_SEL_Msk SCB_V2_I2C_CFG_SDA_IN_FILT_SEL_Msk 2852 #define SCB_I2C_CFG_SCL_IN_FILT_TRIM_Pos SCB_V2_I2C_CFG_SCL_IN_FILT_TRIM_Pos 2853 #define SCB_I2C_CFG_SCL_IN_FILT_TRIM_Msk SCB_V2_I2C_CFG_SCL_IN_FILT_TRIM_Msk 2854 #define SCB_I2C_CFG_SCL_IN_FILT_SEL_Pos SCB_V2_I2C_CFG_SCL_IN_FILT_SEL_Pos 2855 #define SCB_I2C_CFG_SCL_IN_FILT_SEL_Msk SCB_V2_I2C_CFG_SCL_IN_FILT_SEL_Msk 2856 #define SCB_I2C_CFG_SDA_OUT_FILT0_TRIM_Pos SCB_V2_I2C_CFG_SDA_OUT_FILT0_TRIM_Pos 2857 #define SCB_I2C_CFG_SDA_OUT_FILT0_TRIM_Msk SCB_V2_I2C_CFG_SDA_OUT_FILT0_TRIM_Msk 2858 #define SCB_I2C_CFG_SDA_OUT_FILT1_TRIM_Pos SCB_V2_I2C_CFG_SDA_OUT_FILT1_TRIM_Pos 2859 #define SCB_I2C_CFG_SDA_OUT_FILT1_TRIM_Msk SCB_V2_I2C_CFG_SDA_OUT_FILT1_TRIM_Msk 2860 #define SCB_I2C_CFG_SDA_OUT_FILT2_TRIM_Pos SCB_V2_I2C_CFG_SDA_OUT_FILT2_TRIM_Pos 2861 #define SCB_I2C_CFG_SDA_OUT_FILT2_TRIM_Msk SCB_V2_I2C_CFG_SDA_OUT_FILT2_TRIM_Msk 2862 #define SCB_I2C_CFG_SDA_OUT_FILT_SEL_Pos SCB_V2_I2C_CFG_SDA_OUT_FILT_SEL_Pos 2863 #define SCB_I2C_CFG_SDA_OUT_FILT_SEL_Msk SCB_V2_I2C_CFG_SDA_OUT_FILT_SEL_Msk 2864 /* SCB.TX_CTRL */ 2865 #define SCB_TX_CTRL_DATA_WIDTH_Pos SCB_V2_TX_CTRL_DATA_WIDTH_Pos 2866 #define SCB_TX_CTRL_DATA_WIDTH_Msk SCB_V2_TX_CTRL_DATA_WIDTH_Msk 2867 #define SCB_TX_CTRL_MSB_FIRST_Pos SCB_V2_TX_CTRL_MSB_FIRST_Pos 2868 #define SCB_TX_CTRL_MSB_FIRST_Msk SCB_V2_TX_CTRL_MSB_FIRST_Msk 2869 #define SCB_TX_CTRL_OPEN_DRAIN_Pos SCB_V2_TX_CTRL_OPEN_DRAIN_Pos 2870 #define SCB_TX_CTRL_OPEN_DRAIN_Msk SCB_V2_TX_CTRL_OPEN_DRAIN_Msk 2871 /* SCB.TX_FIFO_CTRL */ 2872 #define SCB_TX_FIFO_CTRL_TRIGGER_LEVEL_Pos SCB_V2_TX_FIFO_CTRL_TRIGGER_LEVEL_Pos 2873 #define SCB_TX_FIFO_CTRL_TRIGGER_LEVEL_Msk SCB_V2_TX_FIFO_CTRL_TRIGGER_LEVEL_Msk 2874 #define SCB_TX_FIFO_CTRL_CLEAR_Pos SCB_V2_TX_FIFO_CTRL_CLEAR_Pos 2875 #define SCB_TX_FIFO_CTRL_CLEAR_Msk SCB_V2_TX_FIFO_CTRL_CLEAR_Msk 2876 #define SCB_TX_FIFO_CTRL_FREEZE_Pos SCB_V2_TX_FIFO_CTRL_FREEZE_Pos 2877 #define SCB_TX_FIFO_CTRL_FREEZE_Msk SCB_V2_TX_FIFO_CTRL_FREEZE_Msk 2878 /* SCB.TX_FIFO_STATUS */ 2879 #define SCB_TX_FIFO_STATUS_USED_Pos SCB_V2_TX_FIFO_STATUS_USED_Pos 2880 #define SCB_TX_FIFO_STATUS_USED_Msk SCB_V2_TX_FIFO_STATUS_USED_Msk 2881 #define SCB_TX_FIFO_STATUS_SR_VALID_Pos SCB_V2_TX_FIFO_STATUS_SR_VALID_Pos 2882 #define SCB_TX_FIFO_STATUS_SR_VALID_Msk SCB_V2_TX_FIFO_STATUS_SR_VALID_Msk 2883 #define SCB_TX_FIFO_STATUS_RD_PTR_Pos SCB_V2_TX_FIFO_STATUS_RD_PTR_Pos 2884 #define SCB_TX_FIFO_STATUS_RD_PTR_Msk SCB_V2_TX_FIFO_STATUS_RD_PTR_Msk 2885 #define SCB_TX_FIFO_STATUS_WR_PTR_Pos SCB_V2_TX_FIFO_STATUS_WR_PTR_Pos 2886 #define SCB_TX_FIFO_STATUS_WR_PTR_Msk SCB_V2_TX_FIFO_STATUS_WR_PTR_Msk 2887 /* SCB.TX_FIFO_WR */ 2888 #define SCB_TX_FIFO_WR_DATA_Pos SCB_V2_TX_FIFO_WR_DATA_Pos 2889 #define SCB_TX_FIFO_WR_DATA_Msk SCB_V2_TX_FIFO_WR_DATA_Msk 2890 /* SCB.RX_CTRL */ 2891 #define SCB_RX_CTRL_DATA_WIDTH_Pos SCB_V2_RX_CTRL_DATA_WIDTH_Pos 2892 #define SCB_RX_CTRL_DATA_WIDTH_Msk SCB_V2_RX_CTRL_DATA_WIDTH_Msk 2893 #define SCB_RX_CTRL_MSB_FIRST_Pos SCB_V2_RX_CTRL_MSB_FIRST_Pos 2894 #define SCB_RX_CTRL_MSB_FIRST_Msk SCB_V2_RX_CTRL_MSB_FIRST_Msk 2895 #define SCB_RX_CTRL_MEDIAN_Pos SCB_V2_RX_CTRL_MEDIAN_Pos 2896 #define SCB_RX_CTRL_MEDIAN_Msk SCB_V2_RX_CTRL_MEDIAN_Msk 2897 /* SCB.RX_FIFO_CTRL */ 2898 #define SCB_RX_FIFO_CTRL_TRIGGER_LEVEL_Pos SCB_V2_RX_FIFO_CTRL_TRIGGER_LEVEL_Pos 2899 #define SCB_RX_FIFO_CTRL_TRIGGER_LEVEL_Msk SCB_V2_RX_FIFO_CTRL_TRIGGER_LEVEL_Msk 2900 #define SCB_RX_FIFO_CTRL_CLEAR_Pos SCB_V2_RX_FIFO_CTRL_CLEAR_Pos 2901 #define SCB_RX_FIFO_CTRL_CLEAR_Msk SCB_V2_RX_FIFO_CTRL_CLEAR_Msk 2902 #define SCB_RX_FIFO_CTRL_FREEZE_Pos SCB_V2_RX_FIFO_CTRL_FREEZE_Pos 2903 #define SCB_RX_FIFO_CTRL_FREEZE_Msk SCB_V2_RX_FIFO_CTRL_FREEZE_Msk 2904 /* SCB.RX_FIFO_STATUS */ 2905 #define SCB_RX_FIFO_STATUS_USED_Pos SCB_V2_RX_FIFO_STATUS_USED_Pos 2906 #define SCB_RX_FIFO_STATUS_USED_Msk SCB_V2_RX_FIFO_STATUS_USED_Msk 2907 #define SCB_RX_FIFO_STATUS_SR_VALID_Pos SCB_V2_RX_FIFO_STATUS_SR_VALID_Pos 2908 #define SCB_RX_FIFO_STATUS_SR_VALID_Msk SCB_V2_RX_FIFO_STATUS_SR_VALID_Msk 2909 #define SCB_RX_FIFO_STATUS_RD_PTR_Pos SCB_V2_RX_FIFO_STATUS_RD_PTR_Pos 2910 #define SCB_RX_FIFO_STATUS_RD_PTR_Msk SCB_V2_RX_FIFO_STATUS_RD_PTR_Msk 2911 #define SCB_RX_FIFO_STATUS_WR_PTR_Pos SCB_V2_RX_FIFO_STATUS_WR_PTR_Pos 2912 #define SCB_RX_FIFO_STATUS_WR_PTR_Msk SCB_V2_RX_FIFO_STATUS_WR_PTR_Msk 2913 /* SCB.RX_MATCH */ 2914 #define SCB_RX_MATCH_ADDR_Pos SCB_V2_RX_MATCH_ADDR_Pos 2915 #define SCB_RX_MATCH_ADDR_Msk SCB_V2_RX_MATCH_ADDR_Msk 2916 #define SCB_RX_MATCH_MASK_Pos SCB_V2_RX_MATCH_MASK_Pos 2917 #define SCB_RX_MATCH_MASK_Msk SCB_V2_RX_MATCH_MASK_Msk 2918 /* SCB.RX_FIFO_RD */ 2919 #define SCB_RX_FIFO_RD_DATA_Pos SCB_V2_RX_FIFO_RD_DATA_Pos 2920 #define SCB_RX_FIFO_RD_DATA_Msk SCB_V2_RX_FIFO_RD_DATA_Msk 2921 /* SCB.RX_FIFO_RD_SILENT */ 2922 #define SCB_RX_FIFO_RD_SILENT_DATA_Pos SCB_V2_RX_FIFO_RD_SILENT_DATA_Pos 2923 #define SCB_RX_FIFO_RD_SILENT_DATA_Msk SCB_V2_RX_FIFO_RD_SILENT_DATA_Msk 2924 /* SCB.EZ_DATA */ 2925 #define SCB_EZ_DATA_EZ_DATA_Pos SCB_V2_EZ_DATA_EZ_DATA_Pos 2926 #define SCB_EZ_DATA_EZ_DATA_Msk SCB_V2_EZ_DATA_EZ_DATA_Msk 2927 /* SCB.INTR_CAUSE */ 2928 #define SCB_INTR_CAUSE_M_Pos SCB_V2_INTR_CAUSE_M_Pos 2929 #define SCB_INTR_CAUSE_M_Msk SCB_V2_INTR_CAUSE_M_Msk 2930 #define SCB_INTR_CAUSE_S_Pos SCB_V2_INTR_CAUSE_S_Pos 2931 #define SCB_INTR_CAUSE_S_Msk SCB_V2_INTR_CAUSE_S_Msk 2932 #define SCB_INTR_CAUSE_TX_Pos SCB_V2_INTR_CAUSE_TX_Pos 2933 #define SCB_INTR_CAUSE_TX_Msk SCB_V2_INTR_CAUSE_TX_Msk 2934 #define SCB_INTR_CAUSE_RX_Pos SCB_V2_INTR_CAUSE_RX_Pos 2935 #define SCB_INTR_CAUSE_RX_Msk SCB_V2_INTR_CAUSE_RX_Msk 2936 #define SCB_INTR_CAUSE_I2C_EC_Pos SCB_V2_INTR_CAUSE_I2C_EC_Pos 2937 #define SCB_INTR_CAUSE_I2C_EC_Msk SCB_V2_INTR_CAUSE_I2C_EC_Msk 2938 #define SCB_INTR_CAUSE_SPI_EC_Pos SCB_V2_INTR_CAUSE_SPI_EC_Pos 2939 #define SCB_INTR_CAUSE_SPI_EC_Msk SCB_V2_INTR_CAUSE_SPI_EC_Msk 2940 /* SCB.INTR_I2C_EC */ 2941 #define SCB_INTR_I2C_EC_WAKE_UP_Pos SCB_V2_INTR_I2C_EC_WAKE_UP_Pos 2942 #define SCB_INTR_I2C_EC_WAKE_UP_Msk SCB_V2_INTR_I2C_EC_WAKE_UP_Msk 2943 #define SCB_INTR_I2C_EC_EZ_STOP_Pos SCB_V2_INTR_I2C_EC_EZ_STOP_Pos 2944 #define SCB_INTR_I2C_EC_EZ_STOP_Msk SCB_V2_INTR_I2C_EC_EZ_STOP_Msk 2945 #define SCB_INTR_I2C_EC_EZ_WRITE_STOP_Pos SCB_V2_INTR_I2C_EC_EZ_WRITE_STOP_Pos 2946 #define SCB_INTR_I2C_EC_EZ_WRITE_STOP_Msk SCB_V2_INTR_I2C_EC_EZ_WRITE_STOP_Msk 2947 #define SCB_INTR_I2C_EC_EZ_READ_STOP_Pos SCB_V2_INTR_I2C_EC_EZ_READ_STOP_Pos 2948 #define SCB_INTR_I2C_EC_EZ_READ_STOP_Msk SCB_V2_INTR_I2C_EC_EZ_READ_STOP_Msk 2949 /* SCB.INTR_I2C_EC_MASK */ 2950 #define SCB_INTR_I2C_EC_MASK_WAKE_UP_Pos SCB_V2_INTR_I2C_EC_MASK_WAKE_UP_Pos 2951 #define SCB_INTR_I2C_EC_MASK_WAKE_UP_Msk SCB_V2_INTR_I2C_EC_MASK_WAKE_UP_Msk 2952 #define SCB_INTR_I2C_EC_MASK_EZ_STOP_Pos SCB_V2_INTR_I2C_EC_MASK_EZ_STOP_Pos 2953 #define SCB_INTR_I2C_EC_MASK_EZ_STOP_Msk SCB_V2_INTR_I2C_EC_MASK_EZ_STOP_Msk 2954 #define SCB_INTR_I2C_EC_MASK_EZ_WRITE_STOP_Pos SCB_V2_INTR_I2C_EC_MASK_EZ_WRITE_STOP_Pos 2955 #define SCB_INTR_I2C_EC_MASK_EZ_WRITE_STOP_Msk SCB_V2_INTR_I2C_EC_MASK_EZ_WRITE_STOP_Msk 2956 #define SCB_INTR_I2C_EC_MASK_EZ_READ_STOP_Pos SCB_V2_INTR_I2C_EC_MASK_EZ_READ_STOP_Pos 2957 #define SCB_INTR_I2C_EC_MASK_EZ_READ_STOP_Msk SCB_V2_INTR_I2C_EC_MASK_EZ_READ_STOP_Msk 2958 /* SCB.INTR_I2C_EC_MASKED */ 2959 #define SCB_INTR_I2C_EC_MASKED_WAKE_UP_Pos SCB_V2_INTR_I2C_EC_MASKED_WAKE_UP_Pos 2960 #define SCB_INTR_I2C_EC_MASKED_WAKE_UP_Msk SCB_V2_INTR_I2C_EC_MASKED_WAKE_UP_Msk 2961 #define SCB_INTR_I2C_EC_MASKED_EZ_STOP_Pos SCB_V2_INTR_I2C_EC_MASKED_EZ_STOP_Pos 2962 #define SCB_INTR_I2C_EC_MASKED_EZ_STOP_Msk SCB_V2_INTR_I2C_EC_MASKED_EZ_STOP_Msk 2963 #define SCB_INTR_I2C_EC_MASKED_EZ_WRITE_STOP_Pos SCB_V2_INTR_I2C_EC_MASKED_EZ_WRITE_STOP_Pos 2964 #define SCB_INTR_I2C_EC_MASKED_EZ_WRITE_STOP_Msk SCB_V2_INTR_I2C_EC_MASKED_EZ_WRITE_STOP_Msk 2965 #define SCB_INTR_I2C_EC_MASKED_EZ_READ_STOP_Pos SCB_V2_INTR_I2C_EC_MASKED_EZ_READ_STOP_Pos 2966 #define SCB_INTR_I2C_EC_MASKED_EZ_READ_STOP_Msk SCB_V2_INTR_I2C_EC_MASKED_EZ_READ_STOP_Msk 2967 /* SCB.INTR_SPI_EC */ 2968 #define SCB_INTR_SPI_EC_WAKE_UP_Pos SCB_V2_INTR_SPI_EC_WAKE_UP_Pos 2969 #define SCB_INTR_SPI_EC_WAKE_UP_Msk SCB_V2_INTR_SPI_EC_WAKE_UP_Msk 2970 #define SCB_INTR_SPI_EC_EZ_STOP_Pos SCB_V2_INTR_SPI_EC_EZ_STOP_Pos 2971 #define SCB_INTR_SPI_EC_EZ_STOP_Msk SCB_V2_INTR_SPI_EC_EZ_STOP_Msk 2972 #define SCB_INTR_SPI_EC_EZ_WRITE_STOP_Pos SCB_V2_INTR_SPI_EC_EZ_WRITE_STOP_Pos 2973 #define SCB_INTR_SPI_EC_EZ_WRITE_STOP_Msk SCB_V2_INTR_SPI_EC_EZ_WRITE_STOP_Msk 2974 #define SCB_INTR_SPI_EC_EZ_READ_STOP_Pos SCB_V2_INTR_SPI_EC_EZ_READ_STOP_Pos 2975 #define SCB_INTR_SPI_EC_EZ_READ_STOP_Msk SCB_V2_INTR_SPI_EC_EZ_READ_STOP_Msk 2976 /* SCB.INTR_SPI_EC_MASK */ 2977 #define SCB_INTR_SPI_EC_MASK_WAKE_UP_Pos SCB_V2_INTR_SPI_EC_MASK_WAKE_UP_Pos 2978 #define SCB_INTR_SPI_EC_MASK_WAKE_UP_Msk SCB_V2_INTR_SPI_EC_MASK_WAKE_UP_Msk 2979 #define SCB_INTR_SPI_EC_MASK_EZ_STOP_Pos SCB_V2_INTR_SPI_EC_MASK_EZ_STOP_Pos 2980 #define SCB_INTR_SPI_EC_MASK_EZ_STOP_Msk SCB_V2_INTR_SPI_EC_MASK_EZ_STOP_Msk 2981 #define SCB_INTR_SPI_EC_MASK_EZ_WRITE_STOP_Pos SCB_V2_INTR_SPI_EC_MASK_EZ_WRITE_STOP_Pos 2982 #define SCB_INTR_SPI_EC_MASK_EZ_WRITE_STOP_Msk SCB_V2_INTR_SPI_EC_MASK_EZ_WRITE_STOP_Msk 2983 #define SCB_INTR_SPI_EC_MASK_EZ_READ_STOP_Pos SCB_V2_INTR_SPI_EC_MASK_EZ_READ_STOP_Pos 2984 #define SCB_INTR_SPI_EC_MASK_EZ_READ_STOP_Msk SCB_V2_INTR_SPI_EC_MASK_EZ_READ_STOP_Msk 2985 /* SCB.INTR_SPI_EC_MASKED */ 2986 #define SCB_INTR_SPI_EC_MASKED_WAKE_UP_Pos SCB_V2_INTR_SPI_EC_MASKED_WAKE_UP_Pos 2987 #define SCB_INTR_SPI_EC_MASKED_WAKE_UP_Msk SCB_V2_INTR_SPI_EC_MASKED_WAKE_UP_Msk 2988 #define SCB_INTR_SPI_EC_MASKED_EZ_STOP_Pos SCB_V2_INTR_SPI_EC_MASKED_EZ_STOP_Pos 2989 #define SCB_INTR_SPI_EC_MASKED_EZ_STOP_Msk SCB_V2_INTR_SPI_EC_MASKED_EZ_STOP_Msk 2990 #define SCB_INTR_SPI_EC_MASKED_EZ_WRITE_STOP_Pos SCB_V2_INTR_SPI_EC_MASKED_EZ_WRITE_STOP_Pos 2991 #define SCB_INTR_SPI_EC_MASKED_EZ_WRITE_STOP_Msk SCB_V2_INTR_SPI_EC_MASKED_EZ_WRITE_STOP_Msk 2992 #define SCB_INTR_SPI_EC_MASKED_EZ_READ_STOP_Pos SCB_V2_INTR_SPI_EC_MASKED_EZ_READ_STOP_Pos 2993 #define SCB_INTR_SPI_EC_MASKED_EZ_READ_STOP_Msk SCB_V2_INTR_SPI_EC_MASKED_EZ_READ_STOP_Msk 2994 /* SCB.INTR_M */ 2995 #define SCB_INTR_M_I2C_ARB_LOST_Pos SCB_V2_INTR_M_I2C_ARB_LOST_Pos 2996 #define SCB_INTR_M_I2C_ARB_LOST_Msk SCB_V2_INTR_M_I2C_ARB_LOST_Msk 2997 #define SCB_INTR_M_I2C_NACK_Pos SCB_V2_INTR_M_I2C_NACK_Pos 2998 #define SCB_INTR_M_I2C_NACK_Msk SCB_V2_INTR_M_I2C_NACK_Msk 2999 #define SCB_INTR_M_I2C_ACK_Pos SCB_V2_INTR_M_I2C_ACK_Pos 3000 #define SCB_INTR_M_I2C_ACK_Msk SCB_V2_INTR_M_I2C_ACK_Msk 3001 #define SCB_INTR_M_I2C_STOP_Pos SCB_V2_INTR_M_I2C_STOP_Pos 3002 #define SCB_INTR_M_I2C_STOP_Msk SCB_V2_INTR_M_I2C_STOP_Msk 3003 #define SCB_INTR_M_I2C_BUS_ERROR_Pos SCB_V2_INTR_M_I2C_BUS_ERROR_Pos 3004 #define SCB_INTR_M_I2C_BUS_ERROR_Msk SCB_V2_INTR_M_I2C_BUS_ERROR_Msk 3005 #define SCB_INTR_M_SPI_DONE_Pos SCB_V2_INTR_M_SPI_DONE_Pos 3006 #define SCB_INTR_M_SPI_DONE_Msk SCB_V2_INTR_M_SPI_DONE_Msk 3007 /* SCB.INTR_M_SET */ 3008 #define SCB_INTR_M_SET_I2C_ARB_LOST_Pos SCB_V2_INTR_M_SET_I2C_ARB_LOST_Pos 3009 #define SCB_INTR_M_SET_I2C_ARB_LOST_Msk SCB_V2_INTR_M_SET_I2C_ARB_LOST_Msk 3010 #define SCB_INTR_M_SET_I2C_NACK_Pos SCB_V2_INTR_M_SET_I2C_NACK_Pos 3011 #define SCB_INTR_M_SET_I2C_NACK_Msk SCB_V2_INTR_M_SET_I2C_NACK_Msk 3012 #define SCB_INTR_M_SET_I2C_ACK_Pos SCB_V2_INTR_M_SET_I2C_ACK_Pos 3013 #define SCB_INTR_M_SET_I2C_ACK_Msk SCB_V2_INTR_M_SET_I2C_ACK_Msk 3014 #define SCB_INTR_M_SET_I2C_STOP_Pos SCB_V2_INTR_M_SET_I2C_STOP_Pos 3015 #define SCB_INTR_M_SET_I2C_STOP_Msk SCB_V2_INTR_M_SET_I2C_STOP_Msk 3016 #define SCB_INTR_M_SET_I2C_BUS_ERROR_Pos SCB_V2_INTR_M_SET_I2C_BUS_ERROR_Pos 3017 #define SCB_INTR_M_SET_I2C_BUS_ERROR_Msk SCB_V2_INTR_M_SET_I2C_BUS_ERROR_Msk 3018 #define SCB_INTR_M_SET_SPI_DONE_Pos SCB_V2_INTR_M_SET_SPI_DONE_Pos 3019 #define SCB_INTR_M_SET_SPI_DONE_Msk SCB_V2_INTR_M_SET_SPI_DONE_Msk 3020 /* SCB.INTR_M_MASK */ 3021 #define SCB_INTR_M_MASK_I2C_ARB_LOST_Pos SCB_V2_INTR_M_MASK_I2C_ARB_LOST_Pos 3022 #define SCB_INTR_M_MASK_I2C_ARB_LOST_Msk SCB_V2_INTR_M_MASK_I2C_ARB_LOST_Msk 3023 #define SCB_INTR_M_MASK_I2C_NACK_Pos SCB_V2_INTR_M_MASK_I2C_NACK_Pos 3024 #define SCB_INTR_M_MASK_I2C_NACK_Msk SCB_V2_INTR_M_MASK_I2C_NACK_Msk 3025 #define SCB_INTR_M_MASK_I2C_ACK_Pos SCB_V2_INTR_M_MASK_I2C_ACK_Pos 3026 #define SCB_INTR_M_MASK_I2C_ACK_Msk SCB_V2_INTR_M_MASK_I2C_ACK_Msk 3027 #define SCB_INTR_M_MASK_I2C_STOP_Pos SCB_V2_INTR_M_MASK_I2C_STOP_Pos 3028 #define SCB_INTR_M_MASK_I2C_STOP_Msk SCB_V2_INTR_M_MASK_I2C_STOP_Msk 3029 #define SCB_INTR_M_MASK_I2C_BUS_ERROR_Pos SCB_V2_INTR_M_MASK_I2C_BUS_ERROR_Pos 3030 #define SCB_INTR_M_MASK_I2C_BUS_ERROR_Msk SCB_V2_INTR_M_MASK_I2C_BUS_ERROR_Msk 3031 #define SCB_INTR_M_MASK_SPI_DONE_Pos SCB_V2_INTR_M_MASK_SPI_DONE_Pos 3032 #define SCB_INTR_M_MASK_SPI_DONE_Msk SCB_V2_INTR_M_MASK_SPI_DONE_Msk 3033 /* SCB.INTR_M_MASKED */ 3034 #define SCB_INTR_M_MASKED_I2C_ARB_LOST_Pos SCB_V2_INTR_M_MASKED_I2C_ARB_LOST_Pos 3035 #define SCB_INTR_M_MASKED_I2C_ARB_LOST_Msk SCB_V2_INTR_M_MASKED_I2C_ARB_LOST_Msk 3036 #define SCB_INTR_M_MASKED_I2C_NACK_Pos SCB_V2_INTR_M_MASKED_I2C_NACK_Pos 3037 #define SCB_INTR_M_MASKED_I2C_NACK_Msk SCB_V2_INTR_M_MASKED_I2C_NACK_Msk 3038 #define SCB_INTR_M_MASKED_I2C_ACK_Pos SCB_V2_INTR_M_MASKED_I2C_ACK_Pos 3039 #define SCB_INTR_M_MASKED_I2C_ACK_Msk SCB_V2_INTR_M_MASKED_I2C_ACK_Msk 3040 #define SCB_INTR_M_MASKED_I2C_STOP_Pos SCB_V2_INTR_M_MASKED_I2C_STOP_Pos 3041 #define SCB_INTR_M_MASKED_I2C_STOP_Msk SCB_V2_INTR_M_MASKED_I2C_STOP_Msk 3042 #define SCB_INTR_M_MASKED_I2C_BUS_ERROR_Pos SCB_V2_INTR_M_MASKED_I2C_BUS_ERROR_Pos 3043 #define SCB_INTR_M_MASKED_I2C_BUS_ERROR_Msk SCB_V2_INTR_M_MASKED_I2C_BUS_ERROR_Msk 3044 #define SCB_INTR_M_MASKED_SPI_DONE_Pos SCB_V2_INTR_M_MASKED_SPI_DONE_Pos 3045 #define SCB_INTR_M_MASKED_SPI_DONE_Msk SCB_V2_INTR_M_MASKED_SPI_DONE_Msk 3046 /* SCB.INTR_S */ 3047 #define SCB_INTR_S_I2C_ARB_LOST_Pos SCB_V2_INTR_S_I2C_ARB_LOST_Pos 3048 #define SCB_INTR_S_I2C_ARB_LOST_Msk SCB_V2_INTR_S_I2C_ARB_LOST_Msk 3049 #define SCB_INTR_S_I2C_NACK_Pos SCB_V2_INTR_S_I2C_NACK_Pos 3050 #define SCB_INTR_S_I2C_NACK_Msk SCB_V2_INTR_S_I2C_NACK_Msk 3051 #define SCB_INTR_S_I2C_ACK_Pos SCB_V2_INTR_S_I2C_ACK_Pos 3052 #define SCB_INTR_S_I2C_ACK_Msk SCB_V2_INTR_S_I2C_ACK_Msk 3053 #define SCB_INTR_S_I2C_WRITE_STOP_Pos SCB_V2_INTR_S_I2C_WRITE_STOP_Pos 3054 #define SCB_INTR_S_I2C_WRITE_STOP_Msk SCB_V2_INTR_S_I2C_WRITE_STOP_Msk 3055 #define SCB_INTR_S_I2C_STOP_Pos SCB_V2_INTR_S_I2C_STOP_Pos 3056 #define SCB_INTR_S_I2C_STOP_Msk SCB_V2_INTR_S_I2C_STOP_Msk 3057 #define SCB_INTR_S_I2C_START_Pos SCB_V2_INTR_S_I2C_START_Pos 3058 #define SCB_INTR_S_I2C_START_Msk SCB_V2_INTR_S_I2C_START_Msk 3059 #define SCB_INTR_S_I2C_ADDR_MATCH_Pos SCB_V2_INTR_S_I2C_ADDR_MATCH_Pos 3060 #define SCB_INTR_S_I2C_ADDR_MATCH_Msk SCB_V2_INTR_S_I2C_ADDR_MATCH_Msk 3061 #define SCB_INTR_S_I2C_GENERAL_Pos SCB_V2_INTR_S_I2C_GENERAL_Pos 3062 #define SCB_INTR_S_I2C_GENERAL_Msk SCB_V2_INTR_S_I2C_GENERAL_Msk 3063 #define SCB_INTR_S_I2C_BUS_ERROR_Pos SCB_V2_INTR_S_I2C_BUS_ERROR_Pos 3064 #define SCB_INTR_S_I2C_BUS_ERROR_Msk SCB_V2_INTR_S_I2C_BUS_ERROR_Msk 3065 #define SCB_INTR_S_SPI_EZ_WRITE_STOP_Pos SCB_V2_INTR_S_SPI_EZ_WRITE_STOP_Pos 3066 #define SCB_INTR_S_SPI_EZ_WRITE_STOP_Msk SCB_V2_INTR_S_SPI_EZ_WRITE_STOP_Msk 3067 #define SCB_INTR_S_SPI_EZ_STOP_Pos SCB_V2_INTR_S_SPI_EZ_STOP_Pos 3068 #define SCB_INTR_S_SPI_EZ_STOP_Msk SCB_V2_INTR_S_SPI_EZ_STOP_Msk 3069 #define SCB_INTR_S_SPI_BUS_ERROR_Pos SCB_V2_INTR_S_SPI_BUS_ERROR_Pos 3070 #define SCB_INTR_S_SPI_BUS_ERROR_Msk SCB_V2_INTR_S_SPI_BUS_ERROR_Msk 3071 /* SCB.INTR_S_SET */ 3072 #define SCB_INTR_S_SET_I2C_ARB_LOST_Pos SCB_V2_INTR_S_SET_I2C_ARB_LOST_Pos 3073 #define SCB_INTR_S_SET_I2C_ARB_LOST_Msk SCB_V2_INTR_S_SET_I2C_ARB_LOST_Msk 3074 #define SCB_INTR_S_SET_I2C_NACK_Pos SCB_V2_INTR_S_SET_I2C_NACK_Pos 3075 #define SCB_INTR_S_SET_I2C_NACK_Msk SCB_V2_INTR_S_SET_I2C_NACK_Msk 3076 #define SCB_INTR_S_SET_I2C_ACK_Pos SCB_V2_INTR_S_SET_I2C_ACK_Pos 3077 #define SCB_INTR_S_SET_I2C_ACK_Msk SCB_V2_INTR_S_SET_I2C_ACK_Msk 3078 #define SCB_INTR_S_SET_I2C_WRITE_STOP_Pos SCB_V2_INTR_S_SET_I2C_WRITE_STOP_Pos 3079 #define SCB_INTR_S_SET_I2C_WRITE_STOP_Msk SCB_V2_INTR_S_SET_I2C_WRITE_STOP_Msk 3080 #define SCB_INTR_S_SET_I2C_STOP_Pos SCB_V2_INTR_S_SET_I2C_STOP_Pos 3081 #define SCB_INTR_S_SET_I2C_STOP_Msk SCB_V2_INTR_S_SET_I2C_STOP_Msk 3082 #define SCB_INTR_S_SET_I2C_START_Pos SCB_V2_INTR_S_SET_I2C_START_Pos 3083 #define SCB_INTR_S_SET_I2C_START_Msk SCB_V2_INTR_S_SET_I2C_START_Msk 3084 #define SCB_INTR_S_SET_I2C_ADDR_MATCH_Pos SCB_V2_INTR_S_SET_I2C_ADDR_MATCH_Pos 3085 #define SCB_INTR_S_SET_I2C_ADDR_MATCH_Msk SCB_V2_INTR_S_SET_I2C_ADDR_MATCH_Msk 3086 #define SCB_INTR_S_SET_I2C_GENERAL_Pos SCB_V2_INTR_S_SET_I2C_GENERAL_Pos 3087 #define SCB_INTR_S_SET_I2C_GENERAL_Msk SCB_V2_INTR_S_SET_I2C_GENERAL_Msk 3088 #define SCB_INTR_S_SET_I2C_BUS_ERROR_Pos SCB_V2_INTR_S_SET_I2C_BUS_ERROR_Pos 3089 #define SCB_INTR_S_SET_I2C_BUS_ERROR_Msk SCB_V2_INTR_S_SET_I2C_BUS_ERROR_Msk 3090 #define SCB_INTR_S_SET_SPI_EZ_WRITE_STOP_Pos SCB_V2_INTR_S_SET_SPI_EZ_WRITE_STOP_Pos 3091 #define SCB_INTR_S_SET_SPI_EZ_WRITE_STOP_Msk SCB_V2_INTR_S_SET_SPI_EZ_WRITE_STOP_Msk 3092 #define SCB_INTR_S_SET_SPI_EZ_STOP_Pos SCB_V2_INTR_S_SET_SPI_EZ_STOP_Pos 3093 #define SCB_INTR_S_SET_SPI_EZ_STOP_Msk SCB_V2_INTR_S_SET_SPI_EZ_STOP_Msk 3094 #define SCB_INTR_S_SET_SPI_BUS_ERROR_Pos SCB_V2_INTR_S_SET_SPI_BUS_ERROR_Pos 3095 #define SCB_INTR_S_SET_SPI_BUS_ERROR_Msk SCB_V2_INTR_S_SET_SPI_BUS_ERROR_Msk 3096 /* SCB.INTR_S_MASK */ 3097 #define SCB_INTR_S_MASK_I2C_ARB_LOST_Pos SCB_V2_INTR_S_MASK_I2C_ARB_LOST_Pos 3098 #define SCB_INTR_S_MASK_I2C_ARB_LOST_Msk SCB_V2_INTR_S_MASK_I2C_ARB_LOST_Msk 3099 #define SCB_INTR_S_MASK_I2C_NACK_Pos SCB_V2_INTR_S_MASK_I2C_NACK_Pos 3100 #define SCB_INTR_S_MASK_I2C_NACK_Msk SCB_V2_INTR_S_MASK_I2C_NACK_Msk 3101 #define SCB_INTR_S_MASK_I2C_ACK_Pos SCB_V2_INTR_S_MASK_I2C_ACK_Pos 3102 #define SCB_INTR_S_MASK_I2C_ACK_Msk SCB_V2_INTR_S_MASK_I2C_ACK_Msk 3103 #define SCB_INTR_S_MASK_I2C_WRITE_STOP_Pos SCB_V2_INTR_S_MASK_I2C_WRITE_STOP_Pos 3104 #define SCB_INTR_S_MASK_I2C_WRITE_STOP_Msk SCB_V2_INTR_S_MASK_I2C_WRITE_STOP_Msk 3105 #define SCB_INTR_S_MASK_I2C_STOP_Pos SCB_V2_INTR_S_MASK_I2C_STOP_Pos 3106 #define SCB_INTR_S_MASK_I2C_STOP_Msk SCB_V2_INTR_S_MASK_I2C_STOP_Msk 3107 #define SCB_INTR_S_MASK_I2C_START_Pos SCB_V2_INTR_S_MASK_I2C_START_Pos 3108 #define SCB_INTR_S_MASK_I2C_START_Msk SCB_V2_INTR_S_MASK_I2C_START_Msk 3109 #define SCB_INTR_S_MASK_I2C_ADDR_MATCH_Pos SCB_V2_INTR_S_MASK_I2C_ADDR_MATCH_Pos 3110 #define SCB_INTR_S_MASK_I2C_ADDR_MATCH_Msk SCB_V2_INTR_S_MASK_I2C_ADDR_MATCH_Msk 3111 #define SCB_INTR_S_MASK_I2C_GENERAL_Pos SCB_V2_INTR_S_MASK_I2C_GENERAL_Pos 3112 #define SCB_INTR_S_MASK_I2C_GENERAL_Msk SCB_V2_INTR_S_MASK_I2C_GENERAL_Msk 3113 #define SCB_INTR_S_MASK_I2C_BUS_ERROR_Pos SCB_V2_INTR_S_MASK_I2C_BUS_ERROR_Pos 3114 #define SCB_INTR_S_MASK_I2C_BUS_ERROR_Msk SCB_V2_INTR_S_MASK_I2C_BUS_ERROR_Msk 3115 #define SCB_INTR_S_MASK_SPI_EZ_WRITE_STOP_Pos SCB_V2_INTR_S_MASK_SPI_EZ_WRITE_STOP_Pos 3116 #define SCB_INTR_S_MASK_SPI_EZ_WRITE_STOP_Msk SCB_V2_INTR_S_MASK_SPI_EZ_WRITE_STOP_Msk 3117 #define SCB_INTR_S_MASK_SPI_EZ_STOP_Pos SCB_V2_INTR_S_MASK_SPI_EZ_STOP_Pos 3118 #define SCB_INTR_S_MASK_SPI_EZ_STOP_Msk SCB_V2_INTR_S_MASK_SPI_EZ_STOP_Msk 3119 #define SCB_INTR_S_MASK_SPI_BUS_ERROR_Pos SCB_V2_INTR_S_MASK_SPI_BUS_ERROR_Pos 3120 #define SCB_INTR_S_MASK_SPI_BUS_ERROR_Msk SCB_V2_INTR_S_MASK_SPI_BUS_ERROR_Msk 3121 /* SCB.INTR_S_MASKED */ 3122 #define SCB_INTR_S_MASKED_I2C_ARB_LOST_Pos SCB_V2_INTR_S_MASKED_I2C_ARB_LOST_Pos 3123 #define SCB_INTR_S_MASKED_I2C_ARB_LOST_Msk SCB_V2_INTR_S_MASKED_I2C_ARB_LOST_Msk 3124 #define SCB_INTR_S_MASKED_I2C_NACK_Pos SCB_V2_INTR_S_MASKED_I2C_NACK_Pos 3125 #define SCB_INTR_S_MASKED_I2C_NACK_Msk SCB_V2_INTR_S_MASKED_I2C_NACK_Msk 3126 #define SCB_INTR_S_MASKED_I2C_ACK_Pos SCB_V2_INTR_S_MASKED_I2C_ACK_Pos 3127 #define SCB_INTR_S_MASKED_I2C_ACK_Msk SCB_V2_INTR_S_MASKED_I2C_ACK_Msk 3128 #define SCB_INTR_S_MASKED_I2C_WRITE_STOP_Pos SCB_V2_INTR_S_MASKED_I2C_WRITE_STOP_Pos 3129 #define SCB_INTR_S_MASKED_I2C_WRITE_STOP_Msk SCB_V2_INTR_S_MASKED_I2C_WRITE_STOP_Msk 3130 #define SCB_INTR_S_MASKED_I2C_STOP_Pos SCB_V2_INTR_S_MASKED_I2C_STOP_Pos 3131 #define SCB_INTR_S_MASKED_I2C_STOP_Msk SCB_V2_INTR_S_MASKED_I2C_STOP_Msk 3132 #define SCB_INTR_S_MASKED_I2C_START_Pos SCB_V2_INTR_S_MASKED_I2C_START_Pos 3133 #define SCB_INTR_S_MASKED_I2C_START_Msk SCB_V2_INTR_S_MASKED_I2C_START_Msk 3134 #define SCB_INTR_S_MASKED_I2C_ADDR_MATCH_Pos SCB_V2_INTR_S_MASKED_I2C_ADDR_MATCH_Pos 3135 #define SCB_INTR_S_MASKED_I2C_ADDR_MATCH_Msk SCB_V2_INTR_S_MASKED_I2C_ADDR_MATCH_Msk 3136 #define SCB_INTR_S_MASKED_I2C_GENERAL_Pos SCB_V2_INTR_S_MASKED_I2C_GENERAL_Pos 3137 #define SCB_INTR_S_MASKED_I2C_GENERAL_Msk SCB_V2_INTR_S_MASKED_I2C_GENERAL_Msk 3138 #define SCB_INTR_S_MASKED_I2C_BUS_ERROR_Pos SCB_V2_INTR_S_MASKED_I2C_BUS_ERROR_Pos 3139 #define SCB_INTR_S_MASKED_I2C_BUS_ERROR_Msk SCB_V2_INTR_S_MASKED_I2C_BUS_ERROR_Msk 3140 #define SCB_INTR_S_MASKED_SPI_EZ_WRITE_STOP_Pos SCB_V2_INTR_S_MASKED_SPI_EZ_WRITE_STOP_Pos 3141 #define SCB_INTR_S_MASKED_SPI_EZ_WRITE_STOP_Msk SCB_V2_INTR_S_MASKED_SPI_EZ_WRITE_STOP_Msk 3142 #define SCB_INTR_S_MASKED_SPI_EZ_STOP_Pos SCB_V2_INTR_S_MASKED_SPI_EZ_STOP_Pos 3143 #define SCB_INTR_S_MASKED_SPI_EZ_STOP_Msk SCB_V2_INTR_S_MASKED_SPI_EZ_STOP_Msk 3144 #define SCB_INTR_S_MASKED_SPI_BUS_ERROR_Pos SCB_V2_INTR_S_MASKED_SPI_BUS_ERROR_Pos 3145 #define SCB_INTR_S_MASKED_SPI_BUS_ERROR_Msk SCB_V2_INTR_S_MASKED_SPI_BUS_ERROR_Msk 3146 /* SCB.INTR_TX */ 3147 #define SCB_INTR_TX_TRIGGER_Pos SCB_V2_INTR_TX_TRIGGER_Pos 3148 #define SCB_INTR_TX_TRIGGER_Msk SCB_V2_INTR_TX_TRIGGER_Msk 3149 #define SCB_INTR_TX_NOT_FULL_Pos SCB_V2_INTR_TX_NOT_FULL_Pos 3150 #define SCB_INTR_TX_NOT_FULL_Msk SCB_V2_INTR_TX_NOT_FULL_Msk 3151 #define SCB_INTR_TX_EMPTY_Pos SCB_V2_INTR_TX_EMPTY_Pos 3152 #define SCB_INTR_TX_EMPTY_Msk SCB_V2_INTR_TX_EMPTY_Msk 3153 #define SCB_INTR_TX_OVERFLOW_Pos SCB_V2_INTR_TX_OVERFLOW_Pos 3154 #define SCB_INTR_TX_OVERFLOW_Msk SCB_V2_INTR_TX_OVERFLOW_Msk 3155 #define SCB_INTR_TX_UNDERFLOW_Pos SCB_V2_INTR_TX_UNDERFLOW_Pos 3156 #define SCB_INTR_TX_UNDERFLOW_Msk SCB_V2_INTR_TX_UNDERFLOW_Msk 3157 #define SCB_INTR_TX_BLOCKED_Pos SCB_V2_INTR_TX_BLOCKED_Pos 3158 #define SCB_INTR_TX_BLOCKED_Msk SCB_V2_INTR_TX_BLOCKED_Msk 3159 #define SCB_INTR_TX_UART_NACK_Pos SCB_V2_INTR_TX_UART_NACK_Pos 3160 #define SCB_INTR_TX_UART_NACK_Msk SCB_V2_INTR_TX_UART_NACK_Msk 3161 #define SCB_INTR_TX_UART_DONE_Pos SCB_V2_INTR_TX_UART_DONE_Pos 3162 #define SCB_INTR_TX_UART_DONE_Msk SCB_V2_INTR_TX_UART_DONE_Msk 3163 #define SCB_INTR_TX_UART_ARB_LOST_Pos SCB_V2_INTR_TX_UART_ARB_LOST_Pos 3164 #define SCB_INTR_TX_UART_ARB_LOST_Msk SCB_V2_INTR_TX_UART_ARB_LOST_Msk 3165 /* SCB.INTR_TX_SET */ 3166 #define SCB_INTR_TX_SET_TRIGGER_Pos SCB_V2_INTR_TX_SET_TRIGGER_Pos 3167 #define SCB_INTR_TX_SET_TRIGGER_Msk SCB_V2_INTR_TX_SET_TRIGGER_Msk 3168 #define SCB_INTR_TX_SET_NOT_FULL_Pos SCB_V2_INTR_TX_SET_NOT_FULL_Pos 3169 #define SCB_INTR_TX_SET_NOT_FULL_Msk SCB_V2_INTR_TX_SET_NOT_FULL_Msk 3170 #define SCB_INTR_TX_SET_EMPTY_Pos SCB_V2_INTR_TX_SET_EMPTY_Pos 3171 #define SCB_INTR_TX_SET_EMPTY_Msk SCB_V2_INTR_TX_SET_EMPTY_Msk 3172 #define SCB_INTR_TX_SET_OVERFLOW_Pos SCB_V2_INTR_TX_SET_OVERFLOW_Pos 3173 #define SCB_INTR_TX_SET_OVERFLOW_Msk SCB_V2_INTR_TX_SET_OVERFLOW_Msk 3174 #define SCB_INTR_TX_SET_UNDERFLOW_Pos SCB_V2_INTR_TX_SET_UNDERFLOW_Pos 3175 #define SCB_INTR_TX_SET_UNDERFLOW_Msk SCB_V2_INTR_TX_SET_UNDERFLOW_Msk 3176 #define SCB_INTR_TX_SET_BLOCKED_Pos SCB_V2_INTR_TX_SET_BLOCKED_Pos 3177 #define SCB_INTR_TX_SET_BLOCKED_Msk SCB_V2_INTR_TX_SET_BLOCKED_Msk 3178 #define SCB_INTR_TX_SET_UART_NACK_Pos SCB_V2_INTR_TX_SET_UART_NACK_Pos 3179 #define SCB_INTR_TX_SET_UART_NACK_Msk SCB_V2_INTR_TX_SET_UART_NACK_Msk 3180 #define SCB_INTR_TX_SET_UART_DONE_Pos SCB_V2_INTR_TX_SET_UART_DONE_Pos 3181 #define SCB_INTR_TX_SET_UART_DONE_Msk SCB_V2_INTR_TX_SET_UART_DONE_Msk 3182 #define SCB_INTR_TX_SET_UART_ARB_LOST_Pos SCB_V2_INTR_TX_SET_UART_ARB_LOST_Pos 3183 #define SCB_INTR_TX_SET_UART_ARB_LOST_Msk SCB_V2_INTR_TX_SET_UART_ARB_LOST_Msk 3184 /* SCB.INTR_TX_MASK */ 3185 #define SCB_INTR_TX_MASK_TRIGGER_Pos SCB_V2_INTR_TX_MASK_TRIGGER_Pos 3186 #define SCB_INTR_TX_MASK_TRIGGER_Msk SCB_V2_INTR_TX_MASK_TRIGGER_Msk 3187 #define SCB_INTR_TX_MASK_NOT_FULL_Pos SCB_V2_INTR_TX_MASK_NOT_FULL_Pos 3188 #define SCB_INTR_TX_MASK_NOT_FULL_Msk SCB_V2_INTR_TX_MASK_NOT_FULL_Msk 3189 #define SCB_INTR_TX_MASK_EMPTY_Pos SCB_V2_INTR_TX_MASK_EMPTY_Pos 3190 #define SCB_INTR_TX_MASK_EMPTY_Msk SCB_V2_INTR_TX_MASK_EMPTY_Msk 3191 #define SCB_INTR_TX_MASK_OVERFLOW_Pos SCB_V2_INTR_TX_MASK_OVERFLOW_Pos 3192 #define SCB_INTR_TX_MASK_OVERFLOW_Msk SCB_V2_INTR_TX_MASK_OVERFLOW_Msk 3193 #define SCB_INTR_TX_MASK_UNDERFLOW_Pos SCB_V2_INTR_TX_MASK_UNDERFLOW_Pos 3194 #define SCB_INTR_TX_MASK_UNDERFLOW_Msk SCB_V2_INTR_TX_MASK_UNDERFLOW_Msk 3195 #define SCB_INTR_TX_MASK_BLOCKED_Pos SCB_V2_INTR_TX_MASK_BLOCKED_Pos 3196 #define SCB_INTR_TX_MASK_BLOCKED_Msk SCB_V2_INTR_TX_MASK_BLOCKED_Msk 3197 #define SCB_INTR_TX_MASK_UART_NACK_Pos SCB_V2_INTR_TX_MASK_UART_NACK_Pos 3198 #define SCB_INTR_TX_MASK_UART_NACK_Msk SCB_V2_INTR_TX_MASK_UART_NACK_Msk 3199 #define SCB_INTR_TX_MASK_UART_DONE_Pos SCB_V2_INTR_TX_MASK_UART_DONE_Pos 3200 #define SCB_INTR_TX_MASK_UART_DONE_Msk SCB_V2_INTR_TX_MASK_UART_DONE_Msk 3201 #define SCB_INTR_TX_MASK_UART_ARB_LOST_Pos SCB_V2_INTR_TX_MASK_UART_ARB_LOST_Pos 3202 #define SCB_INTR_TX_MASK_UART_ARB_LOST_Msk SCB_V2_INTR_TX_MASK_UART_ARB_LOST_Msk 3203 /* SCB.INTR_TX_MASKED */ 3204 #define SCB_INTR_TX_MASKED_TRIGGER_Pos SCB_V2_INTR_TX_MASKED_TRIGGER_Pos 3205 #define SCB_INTR_TX_MASKED_TRIGGER_Msk SCB_V2_INTR_TX_MASKED_TRIGGER_Msk 3206 #define SCB_INTR_TX_MASKED_NOT_FULL_Pos SCB_V2_INTR_TX_MASKED_NOT_FULL_Pos 3207 #define SCB_INTR_TX_MASKED_NOT_FULL_Msk SCB_V2_INTR_TX_MASKED_NOT_FULL_Msk 3208 #define SCB_INTR_TX_MASKED_EMPTY_Pos SCB_V2_INTR_TX_MASKED_EMPTY_Pos 3209 #define SCB_INTR_TX_MASKED_EMPTY_Msk SCB_V2_INTR_TX_MASKED_EMPTY_Msk 3210 #define SCB_INTR_TX_MASKED_OVERFLOW_Pos SCB_V2_INTR_TX_MASKED_OVERFLOW_Pos 3211 #define SCB_INTR_TX_MASKED_OVERFLOW_Msk SCB_V2_INTR_TX_MASKED_OVERFLOW_Msk 3212 #define SCB_INTR_TX_MASKED_UNDERFLOW_Pos SCB_V2_INTR_TX_MASKED_UNDERFLOW_Pos 3213 #define SCB_INTR_TX_MASKED_UNDERFLOW_Msk SCB_V2_INTR_TX_MASKED_UNDERFLOW_Msk 3214 #define SCB_INTR_TX_MASKED_BLOCKED_Pos SCB_V2_INTR_TX_MASKED_BLOCKED_Pos 3215 #define SCB_INTR_TX_MASKED_BLOCKED_Msk SCB_V2_INTR_TX_MASKED_BLOCKED_Msk 3216 #define SCB_INTR_TX_MASKED_UART_NACK_Pos SCB_V2_INTR_TX_MASKED_UART_NACK_Pos 3217 #define SCB_INTR_TX_MASKED_UART_NACK_Msk SCB_V2_INTR_TX_MASKED_UART_NACK_Msk 3218 #define SCB_INTR_TX_MASKED_UART_DONE_Pos SCB_V2_INTR_TX_MASKED_UART_DONE_Pos 3219 #define SCB_INTR_TX_MASKED_UART_DONE_Msk SCB_V2_INTR_TX_MASKED_UART_DONE_Msk 3220 #define SCB_INTR_TX_MASKED_UART_ARB_LOST_Pos SCB_V2_INTR_TX_MASKED_UART_ARB_LOST_Pos 3221 #define SCB_INTR_TX_MASKED_UART_ARB_LOST_Msk SCB_V2_INTR_TX_MASKED_UART_ARB_LOST_Msk 3222 /* SCB.INTR_RX */ 3223 #define SCB_INTR_RX_TRIGGER_Pos SCB_V2_INTR_RX_TRIGGER_Pos 3224 #define SCB_INTR_RX_TRIGGER_Msk SCB_V2_INTR_RX_TRIGGER_Msk 3225 #define SCB_INTR_RX_NOT_EMPTY_Pos SCB_V2_INTR_RX_NOT_EMPTY_Pos 3226 #define SCB_INTR_RX_NOT_EMPTY_Msk SCB_V2_INTR_RX_NOT_EMPTY_Msk 3227 #define SCB_INTR_RX_FULL_Pos SCB_V2_INTR_RX_FULL_Pos 3228 #define SCB_INTR_RX_FULL_Msk SCB_V2_INTR_RX_FULL_Msk 3229 #define SCB_INTR_RX_OVERFLOW_Pos SCB_V2_INTR_RX_OVERFLOW_Pos 3230 #define SCB_INTR_RX_OVERFLOW_Msk SCB_V2_INTR_RX_OVERFLOW_Msk 3231 #define SCB_INTR_RX_UNDERFLOW_Pos SCB_V2_INTR_RX_UNDERFLOW_Pos 3232 #define SCB_INTR_RX_UNDERFLOW_Msk SCB_V2_INTR_RX_UNDERFLOW_Msk 3233 #define SCB_INTR_RX_BLOCKED_Pos SCB_V2_INTR_RX_BLOCKED_Pos 3234 #define SCB_INTR_RX_BLOCKED_Msk SCB_V2_INTR_RX_BLOCKED_Msk 3235 #define SCB_INTR_RX_FRAME_ERROR_Pos SCB_V2_INTR_RX_FRAME_ERROR_Pos 3236 #define SCB_INTR_RX_FRAME_ERROR_Msk SCB_V2_INTR_RX_FRAME_ERROR_Msk 3237 #define SCB_INTR_RX_PARITY_ERROR_Pos SCB_V2_INTR_RX_PARITY_ERROR_Pos 3238 #define SCB_INTR_RX_PARITY_ERROR_Msk SCB_V2_INTR_RX_PARITY_ERROR_Msk 3239 #define SCB_INTR_RX_BAUD_DETECT_Pos SCB_V2_INTR_RX_BAUD_DETECT_Pos 3240 #define SCB_INTR_RX_BAUD_DETECT_Msk SCB_V2_INTR_RX_BAUD_DETECT_Msk 3241 #define SCB_INTR_RX_BREAK_DETECT_Pos SCB_V2_INTR_RX_BREAK_DETECT_Pos 3242 #define SCB_INTR_RX_BREAK_DETECT_Msk SCB_V2_INTR_RX_BREAK_DETECT_Msk 3243 /* SCB.INTR_RX_SET */ 3244 #define SCB_INTR_RX_SET_TRIGGER_Pos SCB_V2_INTR_RX_SET_TRIGGER_Pos 3245 #define SCB_INTR_RX_SET_TRIGGER_Msk SCB_V2_INTR_RX_SET_TRIGGER_Msk 3246 #define SCB_INTR_RX_SET_NOT_EMPTY_Pos SCB_V2_INTR_RX_SET_NOT_EMPTY_Pos 3247 #define SCB_INTR_RX_SET_NOT_EMPTY_Msk SCB_V2_INTR_RX_SET_NOT_EMPTY_Msk 3248 #define SCB_INTR_RX_SET_FULL_Pos SCB_V2_INTR_RX_SET_FULL_Pos 3249 #define SCB_INTR_RX_SET_FULL_Msk SCB_V2_INTR_RX_SET_FULL_Msk 3250 #define SCB_INTR_RX_SET_OVERFLOW_Pos SCB_V2_INTR_RX_SET_OVERFLOW_Pos 3251 #define SCB_INTR_RX_SET_OVERFLOW_Msk SCB_V2_INTR_RX_SET_OVERFLOW_Msk 3252 #define SCB_INTR_RX_SET_UNDERFLOW_Pos SCB_V2_INTR_RX_SET_UNDERFLOW_Pos 3253 #define SCB_INTR_RX_SET_UNDERFLOW_Msk SCB_V2_INTR_RX_SET_UNDERFLOW_Msk 3254 #define SCB_INTR_RX_SET_BLOCKED_Pos SCB_V2_INTR_RX_SET_BLOCKED_Pos 3255 #define SCB_INTR_RX_SET_BLOCKED_Msk SCB_V2_INTR_RX_SET_BLOCKED_Msk 3256 #define SCB_INTR_RX_SET_FRAME_ERROR_Pos SCB_V2_INTR_RX_SET_FRAME_ERROR_Pos 3257 #define SCB_INTR_RX_SET_FRAME_ERROR_Msk SCB_V2_INTR_RX_SET_FRAME_ERROR_Msk 3258 #define SCB_INTR_RX_SET_PARITY_ERROR_Pos SCB_V2_INTR_RX_SET_PARITY_ERROR_Pos 3259 #define SCB_INTR_RX_SET_PARITY_ERROR_Msk SCB_V2_INTR_RX_SET_PARITY_ERROR_Msk 3260 #define SCB_INTR_RX_SET_BAUD_DETECT_Pos SCB_V2_INTR_RX_SET_BAUD_DETECT_Pos 3261 #define SCB_INTR_RX_SET_BAUD_DETECT_Msk SCB_V2_INTR_RX_SET_BAUD_DETECT_Msk 3262 #define SCB_INTR_RX_SET_BREAK_DETECT_Pos SCB_V2_INTR_RX_SET_BREAK_DETECT_Pos 3263 #define SCB_INTR_RX_SET_BREAK_DETECT_Msk SCB_V2_INTR_RX_SET_BREAK_DETECT_Msk 3264 /* SCB.INTR_RX_MASK */ 3265 #define SCB_INTR_RX_MASK_TRIGGER_Pos SCB_V2_INTR_RX_MASK_TRIGGER_Pos 3266 #define SCB_INTR_RX_MASK_TRIGGER_Msk SCB_V2_INTR_RX_MASK_TRIGGER_Msk 3267 #define SCB_INTR_RX_MASK_NOT_EMPTY_Pos SCB_V2_INTR_RX_MASK_NOT_EMPTY_Pos 3268 #define SCB_INTR_RX_MASK_NOT_EMPTY_Msk SCB_V2_INTR_RX_MASK_NOT_EMPTY_Msk 3269 #define SCB_INTR_RX_MASK_FULL_Pos SCB_V2_INTR_RX_MASK_FULL_Pos 3270 #define SCB_INTR_RX_MASK_FULL_Msk SCB_V2_INTR_RX_MASK_FULL_Msk 3271 #define SCB_INTR_RX_MASK_OVERFLOW_Pos SCB_V2_INTR_RX_MASK_OVERFLOW_Pos 3272 #define SCB_INTR_RX_MASK_OVERFLOW_Msk SCB_V2_INTR_RX_MASK_OVERFLOW_Msk 3273 #define SCB_INTR_RX_MASK_UNDERFLOW_Pos SCB_V2_INTR_RX_MASK_UNDERFLOW_Pos 3274 #define SCB_INTR_RX_MASK_UNDERFLOW_Msk SCB_V2_INTR_RX_MASK_UNDERFLOW_Msk 3275 #define SCB_INTR_RX_MASK_BLOCKED_Pos SCB_V2_INTR_RX_MASK_BLOCKED_Pos 3276 #define SCB_INTR_RX_MASK_BLOCKED_Msk SCB_V2_INTR_RX_MASK_BLOCKED_Msk 3277 #define SCB_INTR_RX_MASK_FRAME_ERROR_Pos SCB_V2_INTR_RX_MASK_FRAME_ERROR_Pos 3278 #define SCB_INTR_RX_MASK_FRAME_ERROR_Msk SCB_V2_INTR_RX_MASK_FRAME_ERROR_Msk 3279 #define SCB_INTR_RX_MASK_PARITY_ERROR_Pos SCB_V2_INTR_RX_MASK_PARITY_ERROR_Pos 3280 #define SCB_INTR_RX_MASK_PARITY_ERROR_Msk SCB_V2_INTR_RX_MASK_PARITY_ERROR_Msk 3281 #define SCB_INTR_RX_MASK_BAUD_DETECT_Pos SCB_V2_INTR_RX_MASK_BAUD_DETECT_Pos 3282 #define SCB_INTR_RX_MASK_BAUD_DETECT_Msk SCB_V2_INTR_RX_MASK_BAUD_DETECT_Msk 3283 #define SCB_INTR_RX_MASK_BREAK_DETECT_Pos SCB_V2_INTR_RX_MASK_BREAK_DETECT_Pos 3284 #define SCB_INTR_RX_MASK_BREAK_DETECT_Msk SCB_V2_INTR_RX_MASK_BREAK_DETECT_Msk 3285 /* SCB.INTR_RX_MASKED */ 3286 #define SCB_INTR_RX_MASKED_TRIGGER_Pos SCB_V2_INTR_RX_MASKED_TRIGGER_Pos 3287 #define SCB_INTR_RX_MASKED_TRIGGER_Msk SCB_V2_INTR_RX_MASKED_TRIGGER_Msk 3288 #define SCB_INTR_RX_MASKED_NOT_EMPTY_Pos SCB_V2_INTR_RX_MASKED_NOT_EMPTY_Pos 3289 #define SCB_INTR_RX_MASKED_NOT_EMPTY_Msk SCB_V2_INTR_RX_MASKED_NOT_EMPTY_Msk 3290 #define SCB_INTR_RX_MASKED_FULL_Pos SCB_V2_INTR_RX_MASKED_FULL_Pos 3291 #define SCB_INTR_RX_MASKED_FULL_Msk SCB_V2_INTR_RX_MASKED_FULL_Msk 3292 #define SCB_INTR_RX_MASKED_OVERFLOW_Pos SCB_V2_INTR_RX_MASKED_OVERFLOW_Pos 3293 #define SCB_INTR_RX_MASKED_OVERFLOW_Msk SCB_V2_INTR_RX_MASKED_OVERFLOW_Msk 3294 #define SCB_INTR_RX_MASKED_UNDERFLOW_Pos SCB_V2_INTR_RX_MASKED_UNDERFLOW_Pos 3295 #define SCB_INTR_RX_MASKED_UNDERFLOW_Msk SCB_V2_INTR_RX_MASKED_UNDERFLOW_Msk 3296 #define SCB_INTR_RX_MASKED_BLOCKED_Pos SCB_V2_INTR_RX_MASKED_BLOCKED_Pos 3297 #define SCB_INTR_RX_MASKED_BLOCKED_Msk SCB_V2_INTR_RX_MASKED_BLOCKED_Msk 3298 #define SCB_INTR_RX_MASKED_FRAME_ERROR_Pos SCB_V2_INTR_RX_MASKED_FRAME_ERROR_Pos 3299 #define SCB_INTR_RX_MASKED_FRAME_ERROR_Msk SCB_V2_INTR_RX_MASKED_FRAME_ERROR_Msk 3300 #define SCB_INTR_RX_MASKED_PARITY_ERROR_Pos SCB_V2_INTR_RX_MASKED_PARITY_ERROR_Pos 3301 #define SCB_INTR_RX_MASKED_PARITY_ERROR_Msk SCB_V2_INTR_RX_MASKED_PARITY_ERROR_Msk 3302 #define SCB_INTR_RX_MASKED_BAUD_DETECT_Pos SCB_V2_INTR_RX_MASKED_BAUD_DETECT_Pos 3303 #define SCB_INTR_RX_MASKED_BAUD_DETECT_Msk SCB_V2_INTR_RX_MASKED_BAUD_DETECT_Msk 3304 #define SCB_INTR_RX_MASKED_BREAK_DETECT_Pos SCB_V2_INTR_RX_MASKED_BREAK_DETECT_Pos 3305 #define SCB_INTR_RX_MASKED_BREAK_DETECT_Msk SCB_V2_INTR_RX_MASKED_BREAK_DETECT_Msk 3306 3307 3308 /******************************************************************************* 3309 * SMARTIO 3310 *******************************************************************************/ 3311 /* SMARTIO_PRT.CTL */ 3312 #define SMARTIO_PRT_CTL_BYPASS_Pos SMARTIO_PRT_V2_CTL_BYPASS_Pos 3313 #define SMARTIO_PRT_CTL_BYPASS_Msk SMARTIO_PRT_V2_CTL_BYPASS_Msk 3314 #define SMARTIO_PRT_CTL_CLOCK_SRC_Pos SMARTIO_PRT_V2_CTL_CLOCK_SRC_Pos 3315 #define SMARTIO_PRT_CTL_CLOCK_SRC_Msk SMARTIO_PRT_V2_CTL_CLOCK_SRC_Msk 3316 #define SMARTIO_PRT_CTL_HLD_OVR_Pos SMARTIO_PRT_V2_CTL_HLD_OVR_Pos 3317 #define SMARTIO_PRT_CTL_HLD_OVR_Msk SMARTIO_PRT_V2_CTL_HLD_OVR_Msk 3318 #define SMARTIO_PRT_CTL_PIPELINE_EN_Pos SMARTIO_PRT_V2_CTL_PIPELINE_EN_Pos 3319 #define SMARTIO_PRT_CTL_PIPELINE_EN_Msk SMARTIO_PRT_V2_CTL_PIPELINE_EN_Msk 3320 #define SMARTIO_PRT_CTL_ENABLED_Pos SMARTIO_PRT_V2_CTL_ENABLED_Pos 3321 #define SMARTIO_PRT_CTL_ENABLED_Msk SMARTIO_PRT_V2_CTL_ENABLED_Msk 3322 /* SMARTIO_PRT.SYNC_CTL */ 3323 #define SMARTIO_PRT_SYNC_CTL_IO_SYNC_EN_Pos SMARTIO_PRT_V2_SYNC_CTL_IO_SYNC_EN_Pos 3324 #define SMARTIO_PRT_SYNC_CTL_IO_SYNC_EN_Msk SMARTIO_PRT_V2_SYNC_CTL_IO_SYNC_EN_Msk 3325 #define SMARTIO_PRT_SYNC_CTL_CHIP_SYNC_EN_Pos SMARTIO_PRT_V2_SYNC_CTL_CHIP_SYNC_EN_Pos 3326 #define SMARTIO_PRT_SYNC_CTL_CHIP_SYNC_EN_Msk SMARTIO_PRT_V2_SYNC_CTL_CHIP_SYNC_EN_Msk 3327 /* SMARTIO_PRT.LUT_SEL */ 3328 #define SMARTIO_PRT_LUT_SEL_LUT_TR0_SEL_Pos SMARTIO_PRT_V2_LUT_SEL_LUT_TR0_SEL_Pos 3329 #define SMARTIO_PRT_LUT_SEL_LUT_TR0_SEL_Msk SMARTIO_PRT_V2_LUT_SEL_LUT_TR0_SEL_Msk 3330 #define SMARTIO_PRT_LUT_SEL_LUT_TR1_SEL_Pos SMARTIO_PRT_V2_LUT_SEL_LUT_TR1_SEL_Pos 3331 #define SMARTIO_PRT_LUT_SEL_LUT_TR1_SEL_Msk SMARTIO_PRT_V2_LUT_SEL_LUT_TR1_SEL_Msk 3332 #define SMARTIO_PRT_LUT_SEL_LUT_TR2_SEL_Pos SMARTIO_PRT_V2_LUT_SEL_LUT_TR2_SEL_Pos 3333 #define SMARTIO_PRT_LUT_SEL_LUT_TR2_SEL_Msk SMARTIO_PRT_V2_LUT_SEL_LUT_TR2_SEL_Msk 3334 /* SMARTIO_PRT.LUT_CTL */ 3335 #define SMARTIO_PRT_LUT_CTL_LUT_Pos SMARTIO_PRT_V2_LUT_CTL_LUT_Pos 3336 #define SMARTIO_PRT_LUT_CTL_LUT_Msk SMARTIO_PRT_V2_LUT_CTL_LUT_Msk 3337 #define SMARTIO_PRT_LUT_CTL_LUT_OPC_Pos SMARTIO_PRT_V2_LUT_CTL_LUT_OPC_Pos 3338 #define SMARTIO_PRT_LUT_CTL_LUT_OPC_Msk SMARTIO_PRT_V2_LUT_CTL_LUT_OPC_Msk 3339 /* SMARTIO_PRT.DU_SEL */ 3340 #define SMARTIO_PRT_DU_SEL_DU_TR0_SEL_Pos SMARTIO_PRT_V2_DU_SEL_DU_TR0_SEL_Pos 3341 #define SMARTIO_PRT_DU_SEL_DU_TR0_SEL_Msk SMARTIO_PRT_V2_DU_SEL_DU_TR0_SEL_Msk 3342 #define SMARTIO_PRT_DU_SEL_DU_TR1_SEL_Pos SMARTIO_PRT_V2_DU_SEL_DU_TR1_SEL_Pos 3343 #define SMARTIO_PRT_DU_SEL_DU_TR1_SEL_Msk SMARTIO_PRT_V2_DU_SEL_DU_TR1_SEL_Msk 3344 #define SMARTIO_PRT_DU_SEL_DU_TR2_SEL_Pos SMARTIO_PRT_V2_DU_SEL_DU_TR2_SEL_Pos 3345 #define SMARTIO_PRT_DU_SEL_DU_TR2_SEL_Msk SMARTIO_PRT_V2_DU_SEL_DU_TR2_SEL_Msk 3346 #define SMARTIO_PRT_DU_SEL_DU_DATA0_SEL_Pos SMARTIO_PRT_V2_DU_SEL_DU_DATA0_SEL_Pos 3347 #define SMARTIO_PRT_DU_SEL_DU_DATA0_SEL_Msk SMARTIO_PRT_V2_DU_SEL_DU_DATA0_SEL_Msk 3348 #define SMARTIO_PRT_DU_SEL_DU_DATA1_SEL_Pos SMARTIO_PRT_V2_DU_SEL_DU_DATA1_SEL_Pos 3349 #define SMARTIO_PRT_DU_SEL_DU_DATA1_SEL_Msk SMARTIO_PRT_V2_DU_SEL_DU_DATA1_SEL_Msk 3350 /* SMARTIO_PRT.DU_CTL */ 3351 #define SMARTIO_PRT_DU_CTL_DU_SIZE_Pos SMARTIO_PRT_V2_DU_CTL_DU_SIZE_Pos 3352 #define SMARTIO_PRT_DU_CTL_DU_SIZE_Msk SMARTIO_PRT_V2_DU_CTL_DU_SIZE_Msk 3353 #define SMARTIO_PRT_DU_CTL_DU_OPC_Pos SMARTIO_PRT_V2_DU_CTL_DU_OPC_Pos 3354 #define SMARTIO_PRT_DU_CTL_DU_OPC_Msk SMARTIO_PRT_V2_DU_CTL_DU_OPC_Msk 3355 /* SMARTIO_PRT.DATA */ 3356 #define SMARTIO_PRT_DATA_DATA_Pos SMARTIO_PRT_V2_DATA_DATA_Pos 3357 #define SMARTIO_PRT_DATA_DATA_Msk SMARTIO_PRT_V2_DATA_DATA_Msk 3358 3359 3360 /******************************************************************************* 3361 * TCPWM 3362 *******************************************************************************/ 3363 /* TCPWM_GRP_CNT.CTRL */ 3364 #define TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_CC0_Pos TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC0_Pos 3365 #define TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_CC0_Msk TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC0_Msk 3366 #define TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_CC1_Pos TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC1_Pos 3367 #define TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_CC1_Msk TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC1_Msk 3368 #define TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_PERIOD_Pos TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_PERIOD_Pos 3369 #define TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_PERIOD_Msk TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_PERIOD_Msk 3370 #define TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_LINE_SEL_Pos TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_LINE_SEL_Pos 3371 #define TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_LINE_SEL_Msk TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_LINE_SEL_Msk 3372 #define TCPWM_GRP_CNT_CTRL_CC0_MATCH_UP_EN_Pos TCPWM_GRP_CNT_V2_CTRL_CC0_MATCH_UP_EN_Pos 3373 #define TCPWM_GRP_CNT_CTRL_CC0_MATCH_UP_EN_Msk TCPWM_GRP_CNT_V2_CTRL_CC0_MATCH_UP_EN_Msk 3374 #define TCPWM_GRP_CNT_CTRL_CC0_MATCH_DOWN_EN_Pos TCPWM_GRP_CNT_V2_CTRL_CC0_MATCH_DOWN_EN_Pos 3375 #define TCPWM_GRP_CNT_CTRL_CC0_MATCH_DOWN_EN_Msk TCPWM_GRP_CNT_V2_CTRL_CC0_MATCH_DOWN_EN_Msk 3376 #define TCPWM_GRP_CNT_CTRL_CC1_MATCH_UP_EN_Pos TCPWM_GRP_CNT_V2_CTRL_CC1_MATCH_UP_EN_Pos 3377 #define TCPWM_GRP_CNT_CTRL_CC1_MATCH_UP_EN_Msk TCPWM_GRP_CNT_V2_CTRL_CC1_MATCH_UP_EN_Msk 3378 #define TCPWM_GRP_CNT_CTRL_CC1_MATCH_DOWN_EN_Pos TCPWM_GRP_CNT_V2_CTRL_CC1_MATCH_DOWN_EN_Pos 3379 #define TCPWM_GRP_CNT_CTRL_CC1_MATCH_DOWN_EN_Msk TCPWM_GRP_CNT_V2_CTRL_CC1_MATCH_DOWN_EN_Msk 3380 #define TCPWM_GRP_CNT_CTRL_PWM_IMM_KILL_Pos TCPWM_GRP_CNT_V2_CTRL_PWM_IMM_KILL_Pos 3381 #define TCPWM_GRP_CNT_CTRL_PWM_IMM_KILL_Msk TCPWM_GRP_CNT_V2_CTRL_PWM_IMM_KILL_Msk 3382 #define TCPWM_GRP_CNT_CTRL_PWM_STOP_ON_KILL_Pos TCPWM_GRP_CNT_V2_CTRL_PWM_STOP_ON_KILL_Pos 3383 #define TCPWM_GRP_CNT_CTRL_PWM_STOP_ON_KILL_Msk TCPWM_GRP_CNT_V2_CTRL_PWM_STOP_ON_KILL_Msk 3384 #define TCPWM_GRP_CNT_CTRL_PWM_SYNC_KILL_Pos TCPWM_GRP_CNT_V2_CTRL_PWM_SYNC_KILL_Pos 3385 #define TCPWM_GRP_CNT_CTRL_PWM_SYNC_KILL_Msk TCPWM_GRP_CNT_V2_CTRL_PWM_SYNC_KILL_Msk 3386 #define TCPWM_GRP_CNT_CTRL_PWM_DISABLE_MODE_Pos TCPWM_GRP_CNT_V2_CTRL_PWM_DISABLE_MODE_Pos 3387 #define TCPWM_GRP_CNT_CTRL_PWM_DISABLE_MODE_Msk TCPWM_GRP_CNT_V2_CTRL_PWM_DISABLE_MODE_Msk 3388 #define TCPWM_GRP_CNT_CTRL_UP_DOWN_MODE_Pos TCPWM_GRP_CNT_V2_CTRL_UP_DOWN_MODE_Pos 3389 #define TCPWM_GRP_CNT_CTRL_UP_DOWN_MODE_Msk TCPWM_GRP_CNT_V2_CTRL_UP_DOWN_MODE_Msk 3390 #define TCPWM_GRP_CNT_CTRL_ONE_SHOT_Pos TCPWM_GRP_CNT_V2_CTRL_ONE_SHOT_Pos 3391 #define TCPWM_GRP_CNT_CTRL_ONE_SHOT_Msk TCPWM_GRP_CNT_V2_CTRL_ONE_SHOT_Msk 3392 #define TCPWM_GRP_CNT_CTRL_QUAD_ENCODING_MODE_Pos TCPWM_GRP_CNT_V2_CTRL_QUAD_ENCODING_MODE_Pos 3393 #define TCPWM_GRP_CNT_CTRL_QUAD_ENCODING_MODE_Msk TCPWM_GRP_CNT_V2_CTRL_QUAD_ENCODING_MODE_Msk 3394 #define TCPWM_GRP_CNT_CTRL_MODE_Pos TCPWM_GRP_CNT_V2_CTRL_MODE_Pos 3395 #define TCPWM_GRP_CNT_CTRL_MODE_Msk TCPWM_GRP_CNT_V2_CTRL_MODE_Msk 3396 #define TCPWM_GRP_CNT_CTRL_DBG_FREEZE_EN_Pos TCPWM_GRP_CNT_V2_CTRL_DBG_FREEZE_EN_Pos 3397 #define TCPWM_GRP_CNT_CTRL_DBG_FREEZE_EN_Msk TCPWM_GRP_CNT_V2_CTRL_DBG_FREEZE_EN_Msk 3398 #define TCPWM_GRP_CNT_CTRL_ENABLED_Pos TCPWM_GRP_CNT_V2_CTRL_ENABLED_Pos 3399 #define TCPWM_GRP_CNT_CTRL_ENABLED_Msk TCPWM_GRP_CNT_V2_CTRL_ENABLED_Msk 3400 /* TCPWM_GRP_CNT.STATUS */ 3401 #define TCPWM_GRP_CNT_STATUS_DOWN_Pos TCPWM_GRP_CNT_V2_STATUS_DOWN_Pos 3402 #define TCPWM_GRP_CNT_STATUS_DOWN_Msk TCPWM_GRP_CNT_V2_STATUS_DOWN_Msk 3403 #define TCPWM_GRP_CNT_STATUS_TR_CAPTURE0_Pos TCPWM_GRP_CNT_V2_STATUS_TR_CAPTURE0_Pos 3404 #define TCPWM_GRP_CNT_STATUS_TR_CAPTURE0_Msk TCPWM_GRP_CNT_V2_STATUS_TR_CAPTURE0_Msk 3405 #define TCPWM_GRP_CNT_STATUS_TR_COUNT_Pos TCPWM_GRP_CNT_V2_STATUS_TR_COUNT_Pos 3406 #define TCPWM_GRP_CNT_STATUS_TR_COUNT_Msk TCPWM_GRP_CNT_V2_STATUS_TR_COUNT_Msk 3407 #define TCPWM_GRP_CNT_STATUS_TR_RELOAD_Pos TCPWM_GRP_CNT_V2_STATUS_TR_RELOAD_Pos 3408 #define TCPWM_GRP_CNT_STATUS_TR_RELOAD_Msk TCPWM_GRP_CNT_V2_STATUS_TR_RELOAD_Msk 3409 #define TCPWM_GRP_CNT_STATUS_TR_STOP_Pos TCPWM_GRP_CNT_V2_STATUS_TR_STOP_Pos 3410 #define TCPWM_GRP_CNT_STATUS_TR_STOP_Msk TCPWM_GRP_CNT_V2_STATUS_TR_STOP_Msk 3411 #define TCPWM_GRP_CNT_STATUS_TR_START_Pos TCPWM_GRP_CNT_V2_STATUS_TR_START_Pos 3412 #define TCPWM_GRP_CNT_STATUS_TR_START_Msk TCPWM_GRP_CNT_V2_STATUS_TR_START_Msk 3413 #define TCPWM_GRP_CNT_STATUS_TR_CAPTURE1_Pos TCPWM_GRP_CNT_V2_STATUS_TR_CAPTURE1_Pos 3414 #define TCPWM_GRP_CNT_STATUS_TR_CAPTURE1_Msk TCPWM_GRP_CNT_V2_STATUS_TR_CAPTURE1_Msk 3415 #define TCPWM_GRP_CNT_STATUS_LINE_OUT_Pos TCPWM_GRP_CNT_V2_STATUS_LINE_OUT_Pos 3416 #define TCPWM_GRP_CNT_STATUS_LINE_OUT_Msk TCPWM_GRP_CNT_V2_STATUS_LINE_OUT_Msk 3417 #define TCPWM_GRP_CNT_STATUS_LINE_COMPL_OUT_Pos TCPWM_GRP_CNT_V2_STATUS_LINE_COMPL_OUT_Pos 3418 #define TCPWM_GRP_CNT_STATUS_LINE_COMPL_OUT_Msk TCPWM_GRP_CNT_V2_STATUS_LINE_COMPL_OUT_Msk 3419 #define TCPWM_GRP_CNT_STATUS_RUNNING_Pos TCPWM_GRP_CNT_V2_STATUS_RUNNING_Pos 3420 #define TCPWM_GRP_CNT_STATUS_RUNNING_Msk TCPWM_GRP_CNT_V2_STATUS_RUNNING_Msk 3421 #define TCPWM_GRP_CNT_STATUS_DT_CNT_L_Pos TCPWM_GRP_CNT_V2_STATUS_DT_CNT_L_Pos 3422 #define TCPWM_GRP_CNT_STATUS_DT_CNT_L_Msk TCPWM_GRP_CNT_V2_STATUS_DT_CNT_L_Msk 3423 #define TCPWM_GRP_CNT_STATUS_DT_CNT_H_Pos TCPWM_GRP_CNT_V2_STATUS_DT_CNT_H_Pos 3424 #define TCPWM_GRP_CNT_STATUS_DT_CNT_H_Msk TCPWM_GRP_CNT_V2_STATUS_DT_CNT_H_Msk 3425 /* TCPWM_GRP_CNT.COUNTER */ 3426 #define TCPWM_GRP_CNT_COUNTER_COUNTER_Pos TCPWM_GRP_CNT_V2_COUNTER_COUNTER_Pos 3427 #define TCPWM_GRP_CNT_COUNTER_COUNTER_Msk TCPWM_GRP_CNT_V2_COUNTER_COUNTER_Msk 3428 /* TCPWM_GRP_CNT.CC0 */ 3429 #define TCPWM_GRP_CNT_CC0_CC_Pos TCPWM_GRP_CNT_V2_CC0_CC_Pos 3430 #define TCPWM_GRP_CNT_CC0_CC_Msk TCPWM_GRP_CNT_V2_CC0_CC_Msk 3431 /* TCPWM_GRP_CNT.CC0_BUFF */ 3432 #define TCPWM_GRP_CNT_CC0_BUFF_CC_Pos TCPWM_GRP_CNT_V2_CC0_BUFF_CC_Pos 3433 #define TCPWM_GRP_CNT_CC0_BUFF_CC_Msk TCPWM_GRP_CNT_V2_CC0_BUFF_CC_Msk 3434 /* TCPWM_GRP_CNT.CC1 */ 3435 #define TCPWM_GRP_CNT_CC1_CC_Pos TCPWM_GRP_CNT_V2_CC1_CC_Pos 3436 #define TCPWM_GRP_CNT_CC1_CC_Msk TCPWM_GRP_CNT_V2_CC1_CC_Msk 3437 /* TCPWM_GRP_CNT.CC1_BUFF */ 3438 #define TCPWM_GRP_CNT_CC1_BUFF_CC_Pos TCPWM_GRP_CNT_V2_CC1_BUFF_CC_Pos 3439 #define TCPWM_GRP_CNT_CC1_BUFF_CC_Msk TCPWM_GRP_CNT_V2_CC1_BUFF_CC_Msk 3440 /* TCPWM_GRP_CNT.PERIOD */ 3441 #define TCPWM_GRP_CNT_PERIOD_PERIOD_Pos TCPWM_GRP_CNT_V2_PERIOD_PERIOD_Pos 3442 #define TCPWM_GRP_CNT_PERIOD_PERIOD_Msk TCPWM_GRP_CNT_V2_PERIOD_PERIOD_Msk 3443 /* TCPWM_GRP_CNT.PERIOD_BUFF */ 3444 #define TCPWM_GRP_CNT_PERIOD_BUFF_PERIOD_Pos TCPWM_GRP_CNT_V2_PERIOD_BUFF_PERIOD_Pos 3445 #define TCPWM_GRP_CNT_PERIOD_BUFF_PERIOD_Msk TCPWM_GRP_CNT_V2_PERIOD_BUFF_PERIOD_Msk 3446 /* TCPWM_GRP_CNT.LINE_SEL */ 3447 #define TCPWM_GRP_CNT_LINE_SEL_OUT_SEL_Pos TCPWM_GRP_CNT_V2_LINE_SEL_OUT_SEL_Pos 3448 #define TCPWM_GRP_CNT_LINE_SEL_OUT_SEL_Msk TCPWM_GRP_CNT_V2_LINE_SEL_OUT_SEL_Msk 3449 #define TCPWM_GRP_CNT_LINE_SEL_COMPL_OUT_SEL_Pos TCPWM_GRP_CNT_V2_LINE_SEL_COMPL_OUT_SEL_Pos 3450 #define TCPWM_GRP_CNT_LINE_SEL_COMPL_OUT_SEL_Msk TCPWM_GRP_CNT_V2_LINE_SEL_COMPL_OUT_SEL_Msk 3451 /* TCPWM_GRP_CNT.LINE_SEL_BUFF */ 3452 #define TCPWM_GRP_CNT_LINE_SEL_BUFF_OUT_SEL_Pos TCPWM_GRP_CNT_V2_LINE_SEL_BUFF_OUT_SEL_Pos 3453 #define TCPWM_GRP_CNT_LINE_SEL_BUFF_OUT_SEL_Msk TCPWM_GRP_CNT_V2_LINE_SEL_BUFF_OUT_SEL_Msk 3454 #define TCPWM_GRP_CNT_LINE_SEL_BUFF_COMPL_OUT_SEL_Pos TCPWM_GRP_CNT_V2_LINE_SEL_BUFF_COMPL_OUT_SEL_Pos 3455 #define TCPWM_GRP_CNT_LINE_SEL_BUFF_COMPL_OUT_SEL_Msk TCPWM_GRP_CNT_V2_LINE_SEL_BUFF_COMPL_OUT_SEL_Msk 3456 /* TCPWM_GRP_CNT.DT */ 3457 #define TCPWM_GRP_CNT_DT_DT_LINE_OUT_L_Pos TCPWM_GRP_CNT_V2_DT_DT_LINE_OUT_L_Pos 3458 #define TCPWM_GRP_CNT_DT_DT_LINE_OUT_L_Msk TCPWM_GRP_CNT_V2_DT_DT_LINE_OUT_L_Msk 3459 #define TCPWM_GRP_CNT_DT_DT_LINE_OUT_H_Pos TCPWM_GRP_CNT_V2_DT_DT_LINE_OUT_H_Pos 3460 #define TCPWM_GRP_CNT_DT_DT_LINE_OUT_H_Msk TCPWM_GRP_CNT_V2_DT_DT_LINE_OUT_H_Msk 3461 #define TCPWM_GRP_CNT_DT_DT_LINE_COMPL_OUT_Pos TCPWM_GRP_CNT_V2_DT_DT_LINE_COMPL_OUT_Pos 3462 #define TCPWM_GRP_CNT_DT_DT_LINE_COMPL_OUT_Msk TCPWM_GRP_CNT_V2_DT_DT_LINE_COMPL_OUT_Msk 3463 /* TCPWM_GRP_CNT.TR_CMD */ 3464 #define TCPWM_GRP_CNT_TR_CMD_CAPTURE0_Pos TCPWM_GRP_CNT_V2_TR_CMD_CAPTURE0_Pos 3465 #define TCPWM_GRP_CNT_TR_CMD_CAPTURE0_Msk TCPWM_GRP_CNT_V2_TR_CMD_CAPTURE0_Msk 3466 #define TCPWM_GRP_CNT_TR_CMD_RELOAD_Pos TCPWM_GRP_CNT_V2_TR_CMD_RELOAD_Pos 3467 #define TCPWM_GRP_CNT_TR_CMD_RELOAD_Msk TCPWM_GRP_CNT_V2_TR_CMD_RELOAD_Msk 3468 #define TCPWM_GRP_CNT_TR_CMD_STOP_Pos TCPWM_GRP_CNT_V2_TR_CMD_STOP_Pos 3469 #define TCPWM_GRP_CNT_TR_CMD_STOP_Msk TCPWM_GRP_CNT_V2_TR_CMD_STOP_Msk 3470 #define TCPWM_GRP_CNT_TR_CMD_START_Pos TCPWM_GRP_CNT_V2_TR_CMD_START_Pos 3471 #define TCPWM_GRP_CNT_TR_CMD_START_Msk TCPWM_GRP_CNT_V2_TR_CMD_START_Msk 3472 #define TCPWM_GRP_CNT_TR_CMD_CAPTURE1_Pos TCPWM_GRP_CNT_V2_TR_CMD_CAPTURE1_Pos 3473 #define TCPWM_GRP_CNT_TR_CMD_CAPTURE1_Msk TCPWM_GRP_CNT_V2_TR_CMD_CAPTURE1_Msk 3474 /* TCPWM_GRP_CNT.TR_IN_SEL0 */ 3475 #define TCPWM_GRP_CNT_TR_IN_SEL0_CAPTURE0_SEL_Pos TCPWM_GRP_CNT_V2_TR_IN_SEL0_CAPTURE0_SEL_Pos 3476 #define TCPWM_GRP_CNT_TR_IN_SEL0_CAPTURE0_SEL_Msk TCPWM_GRP_CNT_V2_TR_IN_SEL0_CAPTURE0_SEL_Msk 3477 #define TCPWM_GRP_CNT_TR_IN_SEL0_COUNT_SEL_Pos TCPWM_GRP_CNT_V2_TR_IN_SEL0_COUNT_SEL_Pos 3478 #define TCPWM_GRP_CNT_TR_IN_SEL0_COUNT_SEL_Msk TCPWM_GRP_CNT_V2_TR_IN_SEL0_COUNT_SEL_Msk 3479 #define TCPWM_GRP_CNT_TR_IN_SEL0_RELOAD_SEL_Pos TCPWM_GRP_CNT_V2_TR_IN_SEL0_RELOAD_SEL_Pos 3480 #define TCPWM_GRP_CNT_TR_IN_SEL0_RELOAD_SEL_Msk TCPWM_GRP_CNT_V2_TR_IN_SEL0_RELOAD_SEL_Msk 3481 #define TCPWM_GRP_CNT_TR_IN_SEL0_STOP_SEL_Pos TCPWM_GRP_CNT_V2_TR_IN_SEL0_STOP_SEL_Pos 3482 #define TCPWM_GRP_CNT_TR_IN_SEL0_STOP_SEL_Msk TCPWM_GRP_CNT_V2_TR_IN_SEL0_STOP_SEL_Msk 3483 /* TCPWM_GRP_CNT.TR_IN_SEL1 */ 3484 #define TCPWM_GRP_CNT_TR_IN_SEL1_START_SEL_Pos TCPWM_GRP_CNT_V2_TR_IN_SEL1_START_SEL_Pos 3485 #define TCPWM_GRP_CNT_TR_IN_SEL1_START_SEL_Msk TCPWM_GRP_CNT_V2_TR_IN_SEL1_START_SEL_Msk 3486 #define TCPWM_GRP_CNT_TR_IN_SEL1_CAPTURE1_SEL_Pos TCPWM_GRP_CNT_V2_TR_IN_SEL1_CAPTURE1_SEL_Pos 3487 #define TCPWM_GRP_CNT_TR_IN_SEL1_CAPTURE1_SEL_Msk TCPWM_GRP_CNT_V2_TR_IN_SEL1_CAPTURE1_SEL_Msk 3488 /* TCPWM_GRP_CNT.TR_IN_EDGE_SEL */ 3489 #define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_CAPTURE0_EDGE_Pos TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_CAPTURE0_EDGE_Pos 3490 #define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_CAPTURE0_EDGE_Msk TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_CAPTURE0_EDGE_Msk 3491 #define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_COUNT_EDGE_Pos TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_COUNT_EDGE_Pos 3492 #define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_COUNT_EDGE_Msk TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_COUNT_EDGE_Msk 3493 #define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_RELOAD_EDGE_Pos TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_RELOAD_EDGE_Pos 3494 #define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_RELOAD_EDGE_Msk TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_RELOAD_EDGE_Msk 3495 #define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_STOP_EDGE_Pos TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_STOP_EDGE_Pos 3496 #define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_STOP_EDGE_Msk TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_STOP_EDGE_Msk 3497 #define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_START_EDGE_Pos TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_START_EDGE_Pos 3498 #define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_START_EDGE_Msk TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_START_EDGE_Msk 3499 #define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_CAPTURE1_EDGE_Pos TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_CAPTURE1_EDGE_Pos 3500 #define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_CAPTURE1_EDGE_Msk TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_CAPTURE1_EDGE_Msk 3501 /* TCPWM_GRP_CNT.TR_PWM_CTRL */ 3502 #define TCPWM_GRP_CNT_TR_PWM_CTRL_CC0_MATCH_MODE_Pos TCPWM_GRP_CNT_V2_TR_PWM_CTRL_CC0_MATCH_MODE_Pos 3503 #define TCPWM_GRP_CNT_TR_PWM_CTRL_CC0_MATCH_MODE_Msk TCPWM_GRP_CNT_V2_TR_PWM_CTRL_CC0_MATCH_MODE_Msk 3504 #define TCPWM_GRP_CNT_TR_PWM_CTRL_OVERFLOW_MODE_Pos TCPWM_GRP_CNT_V2_TR_PWM_CTRL_OVERFLOW_MODE_Pos 3505 #define TCPWM_GRP_CNT_TR_PWM_CTRL_OVERFLOW_MODE_Msk TCPWM_GRP_CNT_V2_TR_PWM_CTRL_OVERFLOW_MODE_Msk 3506 #define TCPWM_GRP_CNT_TR_PWM_CTRL_UNDERFLOW_MODE_Pos TCPWM_GRP_CNT_V2_TR_PWM_CTRL_UNDERFLOW_MODE_Pos 3507 #define TCPWM_GRP_CNT_TR_PWM_CTRL_UNDERFLOW_MODE_Msk TCPWM_GRP_CNT_V2_TR_PWM_CTRL_UNDERFLOW_MODE_Msk 3508 #define TCPWM_GRP_CNT_TR_PWM_CTRL_CC1_MATCH_MODE_Pos TCPWM_GRP_CNT_V2_TR_PWM_CTRL_CC1_MATCH_MODE_Pos 3509 #define TCPWM_GRP_CNT_TR_PWM_CTRL_CC1_MATCH_MODE_Msk TCPWM_GRP_CNT_V2_TR_PWM_CTRL_CC1_MATCH_MODE_Msk 3510 /* TCPWM_GRP_CNT.TR_OUT_SEL */ 3511 #define TCPWM_GRP_CNT_TR_OUT_SEL_OUT0_Pos TCPWM_GRP_CNT_V2_TR_OUT_SEL_OUT0_Pos 3512 #define TCPWM_GRP_CNT_TR_OUT_SEL_OUT0_Msk TCPWM_GRP_CNT_V2_TR_OUT_SEL_OUT0_Msk 3513 #define TCPWM_GRP_CNT_TR_OUT_SEL_OUT1_Pos TCPWM_GRP_CNT_V2_TR_OUT_SEL_OUT1_Pos 3514 #define TCPWM_GRP_CNT_TR_OUT_SEL_OUT1_Msk TCPWM_GRP_CNT_V2_TR_OUT_SEL_OUT1_Msk 3515 /* TCPWM_GRP_CNT.INTR */ 3516 #define TCPWM_GRP_CNT_INTR_TC_Pos TCPWM_GRP_CNT_V2_INTR_TC_Pos 3517 #define TCPWM_GRP_CNT_INTR_TC_Msk TCPWM_GRP_CNT_V2_INTR_TC_Msk 3518 #define TCPWM_GRP_CNT_INTR_CC0_MATCH_Pos TCPWM_GRP_CNT_V2_INTR_CC0_MATCH_Pos 3519 #define TCPWM_GRP_CNT_INTR_CC0_MATCH_Msk TCPWM_GRP_CNT_V2_INTR_CC0_MATCH_Msk 3520 #define TCPWM_GRP_CNT_INTR_CC1_MATCH_Pos TCPWM_GRP_CNT_V2_INTR_CC1_MATCH_Pos 3521 #define TCPWM_GRP_CNT_INTR_CC1_MATCH_Msk TCPWM_GRP_CNT_V2_INTR_CC1_MATCH_Msk 3522 /* TCPWM_GRP_CNT.INTR_SET */ 3523 #define TCPWM_GRP_CNT_INTR_SET_TC_Pos TCPWM_GRP_CNT_V2_INTR_SET_TC_Pos 3524 #define TCPWM_GRP_CNT_INTR_SET_TC_Msk TCPWM_GRP_CNT_V2_INTR_SET_TC_Msk 3525 #define TCPWM_GRP_CNT_INTR_SET_CC0_MATCH_Pos TCPWM_GRP_CNT_V2_INTR_SET_CC0_MATCH_Pos 3526 #define TCPWM_GRP_CNT_INTR_SET_CC0_MATCH_Msk TCPWM_GRP_CNT_V2_INTR_SET_CC0_MATCH_Msk 3527 #define TCPWM_GRP_CNT_INTR_SET_CC1_MATCH_Pos TCPWM_GRP_CNT_V2_INTR_SET_CC1_MATCH_Pos 3528 #define TCPWM_GRP_CNT_INTR_SET_CC1_MATCH_Msk TCPWM_GRP_CNT_V2_INTR_SET_CC1_MATCH_Msk 3529 /* TCPWM_GRP_CNT.INTR_MASK */ 3530 #define TCPWM_GRP_CNT_INTR_MASK_TC_Pos TCPWM_GRP_CNT_V2_INTR_MASK_TC_Pos 3531 #define TCPWM_GRP_CNT_INTR_MASK_TC_Msk TCPWM_GRP_CNT_V2_INTR_MASK_TC_Msk 3532 #define TCPWM_GRP_CNT_INTR_MASK_CC0_MATCH_Pos TCPWM_GRP_CNT_V2_INTR_MASK_CC0_MATCH_Pos 3533 #define TCPWM_GRP_CNT_INTR_MASK_CC0_MATCH_Msk TCPWM_GRP_CNT_V2_INTR_MASK_CC0_MATCH_Msk 3534 #define TCPWM_GRP_CNT_INTR_MASK_CC1_MATCH_Pos TCPWM_GRP_CNT_V2_INTR_MASK_CC1_MATCH_Pos 3535 #define TCPWM_GRP_CNT_INTR_MASK_CC1_MATCH_Msk TCPWM_GRP_CNT_V2_INTR_MASK_CC1_MATCH_Msk 3536 /* TCPWM_GRP_CNT.INTR_MASKED */ 3537 #define TCPWM_GRP_CNT_INTR_MASKED_TC_Pos TCPWM_GRP_CNT_V2_INTR_MASKED_TC_Pos 3538 #define TCPWM_GRP_CNT_INTR_MASKED_TC_Msk TCPWM_GRP_CNT_V2_INTR_MASKED_TC_Msk 3539 #define TCPWM_GRP_CNT_INTR_MASKED_CC0_MATCH_Pos TCPWM_GRP_CNT_V2_INTR_MASKED_CC0_MATCH_Pos 3540 #define TCPWM_GRP_CNT_INTR_MASKED_CC0_MATCH_Msk TCPWM_GRP_CNT_V2_INTR_MASKED_CC0_MATCH_Msk 3541 #define TCPWM_GRP_CNT_INTR_MASKED_CC1_MATCH_Pos TCPWM_GRP_CNT_V2_INTR_MASKED_CC1_MATCH_Pos 3542 #define TCPWM_GRP_CNT_INTR_MASKED_CC1_MATCH_Msk TCPWM_GRP_CNT_V2_INTR_MASKED_CC1_MATCH_Msk 3543 3544 3545 3546 3547 #endif /* _TVIIBE_REMAPS_H_ */ 3548 3549 3550 /* [] END OF FILE */ 3551
