/***************************************************************************//** * \file tviibe_remaps.h * * \brief * Remaps IP defines for Traveo II B-E device compatibility with CAT1A IP headers. * * NOTE: This file should only be included for TVIIBE device builds, and is not * designed to be used with PSoC6 or other platforms. ******************************************************************************** * \copyright * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or * an affiliate of Cypress Semiconductor Corporation. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. *******************************************************************************/ #ifndef _TVIIBE_REMAPS_H_ #define _TVIIBE_REMAPS_H_ /* The first section of remaps for TVIIBE512K, TVIIBE1M, and TVIIBE2M devices (SRSSv2) */ #if defined(CY_DEVICE_SERIES_CYT2B6) || defined(CY_DEVICE_SERIES_CYT2B7) || defined(CY_DEVICE_SERIES_CYT2B9) /******************************************************************************* * SRSS *******************************************************************************/ /* SRSSv2 remaps for what is generated in a TVII generated header file */ #define SRSS_PWR_HIBERNATE_MASK_HIBPIN_Pos SRSS_V2_PWR_HIBERNATE_MASK_HIBPIN_Pos #define SRSS_PWR_HIBERNATE_MASK_HIBPIN_Msk SRSS_V2_PWR_HIBERNATE_MASK_HIBPIN_Msk #define SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Pos SRSS_V2_PWR_HIBERNATE_POLARITY_HIBPIN_Pos #define SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Msk SRSS_V2_PWR_HIBERNATE_POLARITY_HIBPIN_Msk #define SRSS_PWR_HIBERNATE_MASK_HIBALARM_Msk SRSS_V2_PWR_HIBERNATE_MASK_HIBALARM_Msk #define SRSS_PWR_HIBERNATE_MASK_HIBALARM_Pos SRSS_V2_PWR_HIBERNATE_MASK_HIBALARM_Pos #define SRSS_PWR_HIBERNATE_MASK_HIBWDT_Msk SRSS_V2_PWR_HIBERNATE_MASK_HIBWDT_Msk #define SRSS_PWR_LVD_CTL_HVLVD1_EN_HT_Msk SRSS_V2_PWR_LVD_CTL_HVLVD1_EN_HT_Msk #define SRSS_PWR_LVD_CTL_HVLVD1_EN_HT_Pos SRSS_V2_PWR_LVD_CTL_HVLVD1_EN_HT_Pos #define SRSS_PWR_LVD_CTL_HVLVD1_EN_HT_Msk SRSS_V2_PWR_LVD_CTL_HVLVD1_EN_HT_Msk #define SRSS_PWR_LVD_CTL_HVLVD1_EN_HT_Pos SRSS_V2_PWR_LVD_CTL_HVLVD1_EN_HT_Pos #define SRSS_PWR_LVD_CTL2_HVLVD2_EN_HT_Msk SRSS_V2_PWR_LVD_CTL2_HVLVD2_EN_HT_Msk #define SRSS_PWR_LVD_CTL2_HVLVD2_EN_HT_Pos SRSS_V2_PWR_LVD_CTL2_HVLVD2_EN_HT_Pos #define SRSS_PWR_LVD_CTL_HVLVD1_TRIPSEL_HT_Msk SRSS_V2_PWR_LVD_CTL_HVLVD1_TRIPSEL_HT_Msk #define SRSS_PWR_LVD_CTL_HVLVD1_TRIPSEL_HT_Pos SRSS_V2_PWR_LVD_CTL_HVLVD1_TRIPSEL_HT_Pos #define SRSS_PWR_LVD_CTL2_HVLVD2_TRIPSEL_HT_Msk SRSS_V2_PWR_LVD_CTL2_HVLVD2_TRIPSEL_HT_Msk #define SRSS_PWR_LVD_CTL2_HVLVD2_TRIPSEL_HT_Pos SRSS_V2_PWR_LVD_CTL2_HVLVD2_TRIPSEL_HT_Pos #define SRSS_PWR_LVD_STATUS_HVLVD1_OUT_Msk SRSS_V2_PWR_LVD_STATUS_HVLVD1_OUT_Msk #define SRSS_PWR_LVD_STATUS_HVLVD1_OUT_Pos SRSS_V2_PWR_LVD_STATUS_HVLVD1_OUT_Pos #define SRSS_PWR_LVD_STATUS2_HVLVD2_OUT_Msk SRSS_V2_PWR_LVD_STATUS2_HVLVD2_OUT_Msk #define SRSS_PWR_LVD_STATUS2_HVLVD2_OUT_Pos SRSS_V2_PWR_LVD_STATUS2_HVLVD2_OUT_Pos #define SRSS_SRSS_INTR_HVLVD1_Msk SRSS_V2_SRSS_INTR_HVLVD1_Msk #define SRSS_SRSS_INTR_HVLVD1_Pos SRSS_V2_SRSS_INTR_HVLVD1_Pos #define SRSS_SRSS_INTR_HVLVD2_Msk SRSS_V2_SRSS_INTR_HVLVD2_Msk #define SRSS_SRSS_INTR_HVLVD2_Pos SRSS_V2_SRSS_INTR_HVLVD2_Pos #define SRSS_SRSS_INTR_SET_HVLVD1_Msk SRSS_V2_SRSS_INTR_SET_HVLVD1_Msk #define SRSS_SRSS_INTR_SET_HVLVD1_Pos SRSS_V2_SRSS_INTR_SET_HVLVD1_Pos #define SRSS_SRSS_INTR_SET_HVLVD2_Msk SRSS_V2_SRSS_INTR_SET_HVLVD2_Msk #define SRSS_SRSS_INTR_SET_HVLVD2_Pos SRSS_V2_SRSS_INTR_SET_HVLVD2_Pos #define SRSS_SRSS_INTR_MASK_HVLVD1_Msk SRSS_V2_SRSS_INTR_MASK_HVLVD1_Msk #define SRSS_SRSS_INTR_MASK_HVLVD1_Pos SRSS_V2_SRSS_INTR_MASK_HVLVD1_Pos #define SRSS_SRSS_INTR_MASK_HVLVD2_Msk SRSS_V2_SRSS_INTR_MASK_HVLVD2_Msk #define SRSS_SRSS_INTR_MASK_HVLVD2_Pos SRSS_V2_SRSS_INTR_MASK_HVLVD2_Pos #define SRSS_PWR_LVD_CTL_HVLVD1_EDGE_SEL_Msk SRSS_V2_PWR_LVD_CTL_HVLVD1_EDGE_SEL_Msk #define SRSS_PWR_LVD_CTL_HVLVD1_EDGE_SEL_Pos SRSS_V2_PWR_LVD_CTL_HVLVD1_EDGE_SEL_Pos #define SRSS_PWR_LVD_CTL_HVLVD2_EDGE_SEL_Msk SRSS_V2_PWR_LVD_CTL_HVLVD2_EDGE_SEL_Msk #define SRSS_PWR_LVD_CTL_HVLVD2_EDGE_SEL_Pos SRSS_V2_PWR_LVD_CTL_HVLVD2_EDGE_SEL_Pos #define SRSS_PWR_LVD_CTL2_HVLVD2_EDGE_SEL_Msk SRSS_V2_PWR_LVD_CTL2_HVLVD2_EDGE_SEL_Msk #define SRSS_PWR_LVD_CTL2_HVLVD2_EDGE_SEL_Pos SRSS_V2_PWR_LVD_CTL2_HVLVD2_EDGE_SEL_Pos #define SRSS_PWR_LVD_CTL2_HVLVD2_ACTION_Msk SRSS_V2_PWR_LVD_CTL2_HVLVD2_ACTION_Msk #define SRSS_PWR_LVD_CTL2_HVLVD2_ACTION_Pos SRSS_V2_PWR_LVD_CTL2_HVLVD2_ACTION_Pos #define SRSS_PWR_LVD_CTL_HVLVD1_ACTION_Msk SRSS_V2_PWR_LVD_CTL_HVLVD1_ACTION_Msk #define SRSS_PWR_LVD_CTL_HVLVD1_ACTION_Pos SRSS_V2_PWR_LVD_CTL_HVLVD1_ACTION_Pos #define SRSS_PWR_LVD_CTL_HVLVD1_DPSLP_EN_HT_Msk SRSS_V2_PWR_LVD_CTL_HVLVD1_DPSLP_EN_HT_Msk #define SRSS_PWR_LVD_CTL_HVLVD1_DPSLP_EN_HT_Pos SRSS_V2_PWR_LVD_CTL_HVLVD1_DPSLP_EN_HT_Pos #define SRSS_PWR_LVD_CTL2_HVLVD2_DPSLP_EN_HT_Msk SRSS_V2_PWR_LVD_CTL2_HVLVD2_DPSLP_EN_HT_Msk #define SRSS_PWR_LVD_CTL2_HVLVD2_DPSLP_EN_HT_Pos SRSS_V2_PWR_LVD_CTL2_HVLVD2_DPSLP_EN_HT_Pos #define SRSS_CLK_SELECT_PUMP_SEL_Msk SRSS_V2_CLK_SELECT_PUMP_SEL_Msk #define SRSS_CLK_SELECT_PUMP_SEL_Pos SRSS_V2_CLK_SELECT_PUMP_SEL_Pos #define SRSS_CLK_SELECT_PUMP_DIV_Msk SRSS_V2_CLK_SELECT_PUMP_DIV_Msk #define SRSS_CLK_SELECT_PUMP_DIV_Pos SRSS_V2_CLK_SELECT_PUMP_DIV_Pos #define SRSS_RES_CAUSE2_RESET_CSV_HF_Msk SRSS_V2_RES_CAUSE2_RESET_CSV_HF_Msk #define SRSS_RES_CAUSE2_RESET_CSV_HF_Pos SRSS_V2_RES_CAUSE2_RESET_CSV_HF_Pos #define SRSS_CLK_SELECT_PUMP_ENABLE_Msk SRSS_V2_CLK_SELECT_PUMP_ENABLE_Msk #define SRSS_CLK_SELECT_PUMP_ENABLE_Pos SRSS_V2_CLK_SELECT_PUMP_ENABLE_Pos #define SRSS_PWR_CTL2_BGREF_LPMODE_Msk SRSS_V2_PWR_CTL2_BGREF_LPMODE_Msk #define SRSS_PWR_CTL2_BGREF_LPMODE_Pos SRSS_V2_PWR_CTL2_BGREF_LPMODE_Pos #define SRSS_RES_CAUSE2_RESET_CSV_HF_Pos SRSS_V2_RES_CAUSE2_RESET_CSV_HF_Pos #define SRSS_RES_CAUSE2_RESET_CSV_HF_Msk SRSS_V2_RES_CAUSE2_RESET_CSV_HF_Msk #define SRSS_PWR_HIBERNATE_TOKEN_Msk SRSS_V2_PWR_HIBERNATE_TOKEN_Msk #define SRSS_PWR_HIBERNATE_TOKEN_Pos SRSS_V2_PWR_HIBERNATE_TOKEN_Pos #define SRSS_PWR_HIBERNATE_UNLOCK_Pos SRSS_V2_PWR_HIBERNATE_UNLOCK_Pos #define SRSS_PWR_HIBERNATE_UNLOCK_Msk SRSS_V2_PWR_HIBERNATE_UNLOCK_Msk #define SRSS_PWR_HIBERNATE_FREEZE_Msk SRSS_V2_PWR_HIBERNATE_FREEZE_Msk #define SRSS_PWR_HIBERNATE_FREEZE_Pos SRSS_V2_PWR_HIBERNATE_FREEZE_Pos #define SRSS_PWR_HIBERNATE_HIBERNATE_Msk SRSS_V2_PWR_HIBERNATE_HIBERNATE_Msk #define SRSS_PWR_HIBERNATE_HIBERNATE_Pos SRSS_V2_PWR_HIBERNATE_HIBERNATE_Pos #define SRSS_CLK_SELECT_LFCLK_SEL_Msk SRSS_V2_CLK_SELECT_LFCLK_SEL_Msk #define SRSS_CLK_SELECT_LFCLK_SEL_Pos SRSS_V2_CLK_SELECT_LFCLK_SEL_Pos #define SRSS_RES_CAUSE2_RESET_CSV_REF_Msk SRSS_V2_RES_CAUSE2_RESET_CSV_REF_Msk #define SRSS_RES_CAUSE2_RESET_CSV_REF_Pos SRSS_V2_RES_CAUSE2_RESET_CSV_REF_Pos #define SRSS_CLK_ROOT_SELECT_ENABLE_Msk SRSS_V2_CLK_ROOT_SELECT_ENABLE_Msk #define SRSS_CLK_ROOT_SELECT_ENABLE_Pos SRSS_V2_CLK_ROOT_SELECT_ENABLE_Pos #define SRSS_CLK_ROOT_SELECT_ROOT_MUX_Msk SRSS_V2_CLK_ROOT_SELECT_ROOT_MUX_Msk #define SRSS_CLK_ROOT_SELECT_ROOT_MUX_Pos SRSS_V2_CLK_ROOT_SELECT_ROOT_MUX_Pos #define SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk SRSS_V2_CLK_ROOT_SELECT_ROOT_DIV_Msk #define SRSS_CLK_ROOT_SELECT_ROOT_DIV_Pos SRSS_V2_CLK_ROOT_SELECT_ROOT_DIV_Pos #define SRSS_PWR_CTL2_LINREG_DIS_Msk SRSS_V2_PWR_CTL2_LINREG_DIS_Msk #define SRSS_PWR_CTL2_LINREG_DIS_Pos SRSS_V2_PWR_CTL2_LINREG_DIS_Pos #define SRSS_PWR_CTL2_DPSLP_REG_DIS_Msk SRSS_V2_PWR_CTL2_DPSLP_REG_DIS_Msk #define SRSS_PWR_CTL2_DPSLP_REG_DIS_Pos SRSS_V2_PWR_CTL2_DPSLP_REG_DIS_Pos #define SRSS_CLK_ILO0_CONFIG_ENABLE_Msk SRSS_V2_CLK_ILO0_CONFIG_ENABLE_Msk #define SRSS_CLK_ILO0_CONFIG_ENABLE_Pos SRSS_V2_CLK_ILO0_CONFIG_ENABLE_Pos #define SRSS_CLK_ILO0_CONFIG_ILO0_BACKUP_Msk SRSS_V2_CLK_ILO0_CONFIG_ILO0_BACKUP_Msk #define SRSS_CLK_ILO0_CONFIG_ILO0_BACKUP_Pos SRSS_V2_CLK_ILO0_CONFIG_ILO0_BACKUP_Pos #define SRSS_CLK_ILO1_CONFIG_ENABLE_Msk SRSS_V2_CLK_ILO1_CONFIG_ENABLE_Msk #define SRSS_CLK_ILO1_CONFIG_ENABLE_Pos SRSS_V2_CLK_ILO1_CONFIG_ENABLE_Pos #define SRSS_CLK_ECO_CONFIG_ECO_EN_Msk SRSS_V2_CLK_ECO_CONFIG_ECO_EN_Msk #define SRSS_CLK_ECO_CONFIG_ECO_EN_Pos SRSS_V2_CLK_ECO_CONFIG_ECO_EN_Pos #define SRSS_CLK_ECO_CONFIG2_WDTRIM_Pos SRSS_V2_CLK_ECO_CONFIG2_WDTRIM_Pos #define SRSS_CLK_ECO_CONFIG2_WDTRIM_Msk SRSS_V2_CLK_ECO_CONFIG2_WDTRIM_Msk #define SRSS_CLK_ECO_CONFIG2_ATRIM_Pos SRSS_V2_CLK_ECO_CONFIG2_ATRIM_Pos #define SRSS_CLK_ECO_CONFIG2_ATRIM_Msk SRSS_V2_CLK_ECO_CONFIG2_ATRIM_Msk #define SRSS_CLK_ECO_CONFIG2_FTRIM_Msk SRSS_V2_CLK_ECO_CONFIG2_FTRIM_Msk #define SRSS_CLK_ECO_CONFIG2_FTRIM_Pos SRSS_V2_CLK_ECO_CONFIG2_FTRIM_Pos #define SRSS_CLK_ECO_CONFIG2_RTRIM_Pos SRSS_V2_CLK_ECO_CONFIG2_RTRIM_Pos #define SRSS_CLK_ECO_CONFIG2_RTRIM_Msk SRSS_V2_CLK_ECO_CONFIG2_RTRIM_Msk #define SRSS_CLK_ECO_CONFIG2_GTRIM_Pos SRSS_V2_CLK_ECO_CONFIG2_GTRIM_Pos #define SRSS_CLK_ECO_CONFIG2_GTRIM_Msk SRSS_V2_CLK_ECO_CONFIG2_GTRIM_Msk #define SRSS_CLK_ECO_CONFIG_AGC_EN_Pos SRSS_V2_CLK_ECO_CONFIG_AGC_EN_Pos #define SRSS_CLK_ECO_CONFIG_AGC_EN_Msk SRSS_V2_CLK_ECO_CONFIG_AGC_EN_Msk #define SRSS_PWR_CTL_LPM_READY_Msk SRSS_V2_PWR_CTL_LPM_READY_Msk #define SRSS_PWR_CTL_LPM_READY_Pos SRSS_V2_PWR_CTL_LPM_READY_Pos #define SRSS_CLK_ECO_STATUS_ECO_OK_Msk SRSS_V2_CLK_ECO_STATUS_ECO_OK_Msk #define SRSS_CLK_ECO_STATUS_ECO_OK_Pos SRSS_V2_CLK_ECO_STATUS_ECO_OK_Pos #define SRSS_CLK_ECO_STATUS_ECO_READY_Msk SRSS_V2_CLK_ECO_STATUS_ECO_READY_Msk #define SRSS_CLK_ECO_STATUS_ECO_READY_Pos SRSS_V2_CLK_ECO_STATUS_ECO_READY_Pos #define SRSS_CLK_ECO_PRESCALE_ECO_DIV_ENABLED_Msk SRSS_V2_CLK_ECO_PRESCALE_ECO_DIV_ENABLED_Msk #define SRSS_CLK_ECO_PRESCALE_ECO_DIV_ENABLED_Pos SRSS_V2_CLK_ECO_PRESCALE_ECO_DIV_ENABLED_Pos #define SRSS_CLK_ECO_PRESCALE_ECO_INT_DIV_Pos SRSS_V2_CLK_ECO_PRESCALE_ECO_INT_DIV_Pos #define SRSS_CLK_ECO_PRESCALE_ECO_INT_DIV_Msk SRSS_V2_CLK_ECO_PRESCALE_ECO_INT_DIV_Msk #define SRSS_CLK_ECO_PRESCALE_ECO_INT_DIV_Msk SRSS_V2_CLK_ECO_PRESCALE_ECO_INT_DIV_Msk #define SRSS_CLK_ECO_PRESCALE_ECO_INT_DIV_Pos SRSS_V2_CLK_ECO_PRESCALE_ECO_INT_DIV_Pos #define SRSS_CLK_ECO_PRESCALE_ECO_FRAC_DIV_Pos SRSS_V2_CLK_ECO_PRESCALE_ECO_FRAC_DIV_Pos #define SRSS_CLK_ECO_PRESCALE_ECO_FRAC_DIV_Msk SRSS_V2_CLK_ECO_PRESCALE_ECO_FRAC_DIV_Msk #define SRSS_PWR_SSV_CTL_OVDVDDD_ENABLE_Msk SRSS_V2_PWR_SSV_CTL_OVDVDDD_ENABLE_Msk #define SRSS_PWR_SSV_CTL_OVDVDDD_ENABLE_Pos SRSS_V2_PWR_SSV_CTL_OVDVDDD_ENABLE_Pos #define SRSS_CLK_ECO_CONFIG_ECO_DIV_ENABLE_Msk SRSS_V2_CLK_ECO_CONFIG_ECO_DIV_ENABLE_Msk #define SRSS_CLK_ECO_CONFIG_ECO_DIV_ENABLE_Pos SRSS_V2_CLK_ECO_CONFIG_ECO_DIV_ENABLE_Pos #define SRSS_PWR_SSV_CTL_OVDVDDA_ENABLE_Msk SRSS_V2_PWR_SSV_CTL_OVDVDDA_ENABLE_Msk #define SRSS_PWR_SSV_CTL_OVDVDDA_ENABLE_Pos SRSS_V2_PWR_SSV_CTL_OVDVDDA_ENABLE_Pos #define SRSS_CLK_ECO_CONFIG_ECO_DIV_DISABLE_Msk SRSS_V2_CLK_ECO_CONFIG_ECO_DIV_DISABLE_Msk #define SRSS_CLK_ECO_CONFIG_ECO_DIV_DISABLE_Pos SRSS_V2_CLK_ECO_CONFIG_ECO_DIV_DISABLE_Pos #define SRSS_CLK_IMO_CONFIG_ENABLE_Msk SRSS_V2_CLK_IMO_CONFIG_ENABLE_Msk #define SRSS_CLK_IMO_CONFIG_ENABLE_Pos SRSS_V2_CLK_IMO_CONFIG_ENABLE_Pos #define SRSS_CLK_DSI_SELECT_DSI_MUX_Pos SRSS_V2_CLK_DSI_SELECT_DSI_MUX_Pos #define SRSS_CLK_DSI_SELECT_DSI_MUX_Msk SRSS_V2_CLK_DSI_SELECT_DSI_MUX_Msk #define SRSS_PWR_SSV_CTL_OVDVCCD_ENABLE_Msk SRSS_V2_PWR_SSV_CTL_OVDVCCD_ENABLE_Msk #define SRSS_PWR_SSV_CTL_OVDVCCD_ENABLE_Pos SRSS_V2_PWR_SSV_CTL_OVDVCCD_ENABLE_Pos #define SRSS_CLK_PATH_SELECT_PATH_MUX_Pos SRSS_V2_CLK_PATH_SELECT_PATH_MUX_Pos #define SRSS_CLK_PATH_SELECT_PATH_MUX_Msk SRSS_V2_CLK_PATH_SELECT_PATH_MUX_Msk #define SRSS_PWR_SSV_CTL_OVDVDDD_VSEL_Msk SRSS_V2_PWR_SSV_CTL_OVDVDDD_VSEL_Msk #define SRSS_PWR_SSV_CTL_OVDVDDD_VSEL_Pos SRSS_V2_PWR_SSV_CTL_OVDVDDD_VSEL_Pos #define SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk SRSS_V2_CLK_FLL_CONFIG_FLL_ENABLE_Msk #define SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Pos SRSS_V2_CLK_FLL_CONFIG_FLL_ENABLE_Pos #define SRSS_CLK_FLL_STATUS_LOCKED_Msk SRSS_V2_CLK_FLL_STATUS_LOCKED_Msk #define SRSS_CLK_FLL_STATUS_LOCKED_Pos SRSS_V2_CLK_FLL_STATUS_LOCKED_Pos #define SRSS_CLK_FLL_CONFIG3_BYPASS_SEL_Msk SRSS_V2_CLK_FLL_CONFIG3_BYPASS_SEL_Msk #define SRSS_CLK_FLL_CONFIG3_BYPASS_SEL_Pos SRSS_V2_CLK_FLL_CONFIG3_BYPASS_SEL_Pos #define SRSS_CLK_FLL_CONFIG4_CCO_ENABLE_Msk SRSS_V2_CLK_FLL_CONFIG4_CCO_ENABLE_Msk #define SRSS_CLK_FLL_CONFIG4_CCO_ENABLE_Pos SRSS_V2_CLK_FLL_CONFIG4_CCO_ENABLE_Pos #define SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV_Msk SRSS_V2_CLK_FLL_CONFIG_FLL_OUTPUT_DIV_Msk #define SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV_Pos SRSS_V2_CLK_FLL_CONFIG_FLL_OUTPUT_DIV_Pos #define SRSS_CLK_FLL_CONFIG_FLL_MULT_Msk SRSS_V2_CLK_FLL_CONFIG_FLL_MULT_Msk #define SRSS_CLK_FLL_CONFIG_FLL_MULT_Pos SRSS_V2_CLK_FLL_CONFIG_FLL_MULT_Pos #define SRSS_CLK_FLL_CONFIG_FLL_MULT_Pos SRSS_V2_CLK_FLL_CONFIG_FLL_MULT_Pos #define SRSS_CLK_FLL_CONFIG_FLL_MULT_Msk SRSS_V2_CLK_FLL_CONFIG_FLL_MULT_Msk #define SRSS_PWR_SSV_CTL_OVDVDDA_VSEL_Msk SRSS_V2_PWR_SSV_CTL_OVDVDDA_VSEL_Msk #define SRSS_PWR_SSV_CTL_OVDVDDA_VSEL_Pos SRSS_V2_PWR_SSV_CTL_OVDVDDA_VSEL_Pos #define SRSS_PWR_SSV_CTL_OVDVDDA_VSEL_Pos SRSS_V2_PWR_SSV_CTL_OVDVDDA_VSEL_Pos #define SRSS_PWR_SSV_CTL_OVDVDDA_VSEL_Msk SRSS_V2_PWR_SSV_CTL_OVDVDDA_VSEL_Msk #define SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV_Msk SRSS_V2_CLK_FLL_CONFIG2_FLL_REF_DIV_Msk #define SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV_Pos SRSS_V2_CLK_FLL_CONFIG2_FLL_REF_DIV_Pos #define SRSS_PWR_SSV_CTL_OVDVDDA_ACTION_Msk SRSS_V2_PWR_SSV_CTL_OVDVDDA_ACTION_Msk #define SRSS_PWR_SSV_CTL_OVDVDDA_ACTION_Pos SRSS_V2_PWR_SSV_CTL_OVDVDDA_ACTION_Pos #define SRSS_CLK_FLL_CONFIG2_LOCK_TOL_Msk SRSS_V2_CLK_FLL_CONFIG2_LOCK_TOL_Msk #define SRSS_CLK_FLL_CONFIG2_LOCK_TOL_Pos SRSS_V2_CLK_FLL_CONFIG2_LOCK_TOL_Pos #define SRSS_PWR_SSV_CTL_BODVDDD_ENABLE_Msk SRSS_V2_PWR_SSV_CTL_BODVDDD_ENABLE_Msk #define SRSS_PWR_SSV_CTL_BODVDDD_ENABLE_Pos SRSS_V2_PWR_SSV_CTL_BODVDDD_ENABLE_Pos #define SRSS_PWR_SSV_CTL_BODVDDA_ENABLE_Msk SRSS_V2_PWR_SSV_CTL_BODVDDA_ENABLE_Msk #define SRSS_PWR_SSV_CTL_BODVDDA_ENABLE_Pos SRSS_V2_PWR_SSV_CTL_BODVDDA_ENABLE_Pos #define SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Msk SRSS_V2_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Msk #define SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Pos SRSS_V2_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Pos #define SRSS_PWR_SSV_CTL_BODVCCD_ENABLE_Msk SRSS_V2_PWR_SSV_CTL_BODVCCD_ENABLE_Msk #define SRSS_PWR_SSV_CTL_BODVCCD_ENABLE_Pos SRSS_V2_PWR_SSV_CTL_BODVCCD_ENABLE_Pos #define SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Msk SRSS_V2_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Msk #define SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Pos SRSS_V2_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Pos #define SRSS_PWR_SSV_CTL_BODVDDD_VSEL_Msk SRSS_V2_PWR_SSV_CTL_BODVDDD_VSEL_Msk #define SRSS_PWR_SSV_CTL_BODVDDD_VSEL_Pos SRSS_V2_PWR_SSV_CTL_BODVDDD_VSEL_Pos #define SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT_Msk SRSS_V2_CLK_FLL_CONFIG3_SETTLING_COUNT_Msk #define SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT_Pos SRSS_V2_CLK_FLL_CONFIG3_SETTLING_COUNT_Pos #define SRSS_PWR_SSV_CTL_BODVDDA_VSEL_Msk SRSS_V2_PWR_SSV_CTL_BODVDDA_VSEL_Msk #define SRSS_PWR_SSV_CTL_BODVDDA_VSEL_Pos SRSS_V2_PWR_SSV_CTL_BODVDDA_VSEL_Pos #define SRSS_CLK_FLL_CONFIG4_CCO_FREQ_Msk SRSS_V2_CLK_FLL_CONFIG4_CCO_FREQ_Msk #define SRSS_CLK_FLL_CONFIG4_CCO_FREQ_Pos SRSS_V2_CLK_FLL_CONFIG4_CCO_FREQ_Pos #define SRSS_PWR_SSV_CTL_BODVDDA_ACTION_Msk SRSS_V2_PWR_SSV_CTL_BODVDDA_ACTION_Msk #define SRSS_PWR_SSV_CTL_BODVDDA_ACTION_Pos SRSS_V2_PWR_SSV_CTL_BODVDDA_ACTION_Pos #define SRSS_CLK_FLL_CONFIG4_CCO_RANGE_Msk SRSS_V2_CLK_FLL_CONFIG4_CCO_RANGE_Msk #define SRSS_CLK_FLL_CONFIG4_CCO_RANGE_Pos SRSS_V2_CLK_FLL_CONFIG4_CCO_RANGE_Pos #define SRSS_PWR_SSV_STATUS_BODVDDD_OK_Msk SRSS_V2_PWR_SSV_STATUS_BODVDDD_OK_Msk #define SRSS_PWR_SSV_STATUS_BODVDDD_OK_Pos SRSS_V2_PWR_SSV_STATUS_BODVDDD_OK_Pos #define SRSS_PWR_SSV_STATUS_BODVDDA_OK_Msk SRSS_V2_PWR_SSV_STATUS_BODVDDA_OK_Msk #define SRSS_PWR_SSV_STATUS_BODVDDA_OK_Pos SRSS_V2_PWR_SSV_STATUS_BODVDDA_OK_Pos #define SRSS_PWR_SSV_STATUS_BODVCCD_OK_Msk SRSS_V2_PWR_SSV_STATUS_BODVCCD_OK_Msk #define SRSS_PWR_SSV_STATUS_BODVCCD_OK_Pos SRSS_V2_PWR_SSV_STATUS_BODVCCD_OK_Pos #define SRSS_CLK_FLL_STATUS_CCO_READY_Msk SRSS_V2_CLK_FLL_STATUS_CCO_READY_Msk #define SRSS_CLK_FLL_STATUS_CCO_READY_Pos SRSS_V2_CLK_FLL_STATUS_CCO_READY_Pos #define SRSS_CLK_PLL_CONFIG_ENABLE_Msk SRSS_V2_CLK_PLL_CONFIG_ENABLE_Msk #define SRSS_CLK_PLL_CONFIG_ENABLE_Pos SRSS_V2_CLK_PLL_CONFIG_ENABLE_Pos #define SRSS_CLK_PLL_STATUS_LOCKED_Msk SRSS_V2_CLK_PLL_STATUS_LOCKED_Msk #define SRSS_CLK_PLL_STATUS_LOCKED_Pos SRSS_V2_CLK_PLL_STATUS_LOCKED_Pos #define SRSS_CLK_PLL_STATUS_UNLOCK_OCCURRED_Msk SRSS_V2_CLK_PLL_STATUS_UNLOCK_OCCURRED_Msk #define SRSS_CLK_PLL_STATUS_UNLOCK_OCCURRED_Pos SRSS_V2_CLK_PLL_STATUS_UNLOCK_OCCURRED_Pos #define SRSS_CLK_PLL_CONFIG_BYPASS_SEL_Msk SRSS_V2_CLK_PLL_CONFIG_BYPASS_SEL_Msk #define SRSS_CLK_PLL_CONFIG_BYPASS_SEL_Pos SRSS_V2_CLK_PLL_CONFIG_BYPASS_SEL_Pos #define SRSS_PWR_SSV_STATUS_OVDVDDD_OK_Msk SRSS_V2_PWR_SSV_STATUS_OVDVDDD_OK_Msk #define SRSS_PWR_SSV_STATUS_OVDVDDD_OK_Pos SRSS_V2_PWR_SSV_STATUS_OVDVDDD_OK_Pos #define SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV_Pos SRSS_V2_CLK_PLL_CONFIG_FEEDBACK_DIV_Pos #define SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV_Msk SRSS_V2_CLK_PLL_CONFIG_FEEDBACK_DIV_Msk #define SRSS_PWR_SSV_STATUS_OVDVDDA_OK_Msk SRSS_V2_PWR_SSV_STATUS_OVDVDDA_OK_Msk #define SRSS_PWR_SSV_STATUS_OVDVDDA_OK_Pos SRSS_V2_PWR_SSV_STATUS_OVDVDDA_OK_Pos #define SRSS_PWR_SSV_STATUS_OVDVDDA_OK_Pos SRSS_V2_PWR_SSV_STATUS_OVDVDDA_OK_Pos #define SRSS_PWR_SSV_STATUS_OVDVDDA_OK_Msk SRSS_V2_PWR_SSV_STATUS_OVDVDDA_OK_Msk #define SRSS_PWR_SSV_STATUS_OVDVCCD_OK_Msk SRSS_V2_PWR_SSV_STATUS_OVDVCCD_OK_Msk #define SRSS_PWR_SSV_STATUS_OVDVCCD_OK_Pos SRSS_V2_PWR_SSV_STATUS_OVDVCCD_OK_Pos #define SRSS_CLK_PLL_CONFIG_REFERENCE_DIV_Pos SRSS_V2_CLK_PLL_CONFIG_REFERENCE_DIV_Pos #define SRSS_CLK_PLL_CONFIG_REFERENCE_DIV_Msk SRSS_V2_CLK_PLL_CONFIG_REFERENCE_DIV_Msk #define SRSS_PWR_CTL2_LINREG_LPMODE_Msk SRSS_V2_PWR_CTL2_LINREG_LPMODE_Msk #define SRSS_PWR_CTL2_LINREG_LPMODE_Pos SRSS_V2_PWR_CTL2_LINREG_LPMODE_Pos #define SRSS_CLK_PLL_CONFIG_OUTPUT_DIV_Pos SRSS_V2_CLK_PLL_CONFIG_OUTPUT_DIV_Pos #define SRSS_CLK_PLL_CONFIG_OUTPUT_DIV_Msk SRSS_V2_CLK_PLL_CONFIG_OUTPUT_DIV_Msk #define SRSS_PWR_CTL2_PORBOD_LPMODE_Msk SRSS_V2_PWR_CTL2_PORBOD_LPMODE_Msk #define SRSS_PWR_CTL2_PORBOD_LPMODE_Pos SRSS_V2_PWR_CTL2_PORBOD_LPMODE_Pos #define SRSS_PWR_CTL2_REFVBUF_DIS_Msk SRSS_V2_PWR_CTL2_REFVBUF_DIS_Msk #define SRSS_PWR_CTL2_REFVBUF_DIS_Pos SRSS_V2_PWR_CTL2_REFVBUF_DIS_Pos #define SRSS_PWR_CTL2_LINREG_OK_Msk SRSS_V2_PWR_CTL2_LINREG_OK_Msk #define SRSS_PWR_CTL2_LINREG_OK_Pos SRSS_V2_PWR_CTL2_LINREG_OK_Pos #define SRSS_CLK_PLL_CONFIG_PLL_LF_MODE_Pos SRSS_V2_CLK_PLL_CONFIG_PLL_LF_MODE_Pos #define SRSS_CLK_PLL_CONFIG_PLL_LF_MODE_Msk SRSS_V2_CLK_PLL_CONFIG_PLL_LF_MODE_Msk #define SRSS_CLK_PLL_CONFIG_BYPASS_SEL_Msk SRSS_V2_CLK_PLL_CONFIG_BYPASS_SEL_Msk #define SRSS_CLK_PLL_CONFIG_BYPASS_SEL_Pos SRSS_V2_CLK_PLL_CONFIG_BYPASS_SEL_Pos #define SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE_Msk SRSS_V2_CLK_CAL_CNT1_CAL_COUNTER_DONE_Msk #define SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE_Pos SRSS_V2_CLK_CAL_CNT1_CAL_COUNTER_DONE_Pos #define SRSS_CLK_CAL_CNT1_CAL_COUNTER1_Msk SRSS_V2_CLK_CAL_CNT1_CAL_COUNTER1_Msk #define SRSS_CLK_CAL_CNT1_CAL_COUNTER1_Pos SRSS_V2_CLK_CAL_CNT1_CAL_COUNTER1_Pos #define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL0_Pos SRSS_V2_CLK_OUTPUT_SLOW_SLOW_SEL0_Pos #define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL0_Msk SRSS_V2_CLK_OUTPUT_SLOW_SLOW_SEL0_Msk #define SRSS_CLK_OUTPUT_FAST_FAST_SEL0_Pos SRSS_V2_CLK_OUTPUT_FAST_FAST_SEL0_Pos #define SRSS_CLK_OUTPUT_FAST_FAST_SEL0_Msk SRSS_V2_CLK_OUTPUT_FAST_FAST_SEL0_Msk #define SRSS_CLK_OUTPUT_FAST_PATH_SEL0_Pos SRSS_V2_CLK_OUTPUT_FAST_PATH_SEL0_Pos #define SRSS_CLK_OUTPUT_FAST_PATH_SEL0_Msk SRSS_V2_CLK_OUTPUT_FAST_PATH_SEL0_Msk #define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL0_Pos SRSS_V2_CLK_OUTPUT_FAST_HFCLK_SEL0_Pos #define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL0_Msk SRSS_V2_CLK_OUTPUT_FAST_HFCLK_SEL0_Msk #define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL1_Pos SRSS_V2_CLK_OUTPUT_SLOW_SLOW_SEL1_Pos #define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL1_Msk SRSS_V2_CLK_OUTPUT_SLOW_SLOW_SEL1_Msk #define SRSS_CLK_OUTPUT_FAST_FAST_SEL1_Pos SRSS_V2_CLK_OUTPUT_FAST_FAST_SEL1_Pos #define SRSS_CLK_OUTPUT_FAST_FAST_SEL1_Msk SRSS_V2_CLK_OUTPUT_FAST_FAST_SEL1_Msk #define SRSS_CLK_OUTPUT_FAST_PATH_SEL1_Pos SRSS_V2_CLK_OUTPUT_FAST_PATH_SEL1_Pos #define SRSS_CLK_OUTPUT_FAST_PATH_SEL1_Msk SRSS_V2_CLK_OUTPUT_FAST_PATH_SEL1_Msk #define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL1_Pos SRSS_V2_CLK_OUTPUT_FAST_HFCLK_SEL1_Pos #define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL1_Msk SRSS_V2_CLK_OUTPUT_FAST_HFCLK_SEL1_Msk #define SRSS_CLK_CAL_CNT2_CAL_COUNTER2_Msk SRSS_V2_CLK_CAL_CNT2_CAL_COUNTER2_Msk #define SRSS_CLK_CAL_CNT2_CAL_COUNTER2_Pos SRSS_V2_CLK_CAL_CNT2_CAL_COUNTER2_Pos /* SRSS.CLK_TIMER_CTL */ #define SRSS_CLK_TIMER_CTL_TIMER_SEL_Pos SRSS_V2_CLK_TIMER_CTL_TIMER_SEL_Pos #define SRSS_CLK_TIMER_CTL_TIMER_SEL_Msk SRSS_V2_CLK_TIMER_CTL_TIMER_SEL_Msk #define SRSS_CLK_TIMER_CTL_TIMER_HF0_DIV_Pos SRSS_V2_CLK_TIMER_CTL_TIMER_HF0_DIV_Pos #define SRSS_CLK_TIMER_CTL_TIMER_HF0_DIV_Msk SRSS_V2_CLK_TIMER_CTL_TIMER_HF0_DIV_Msk #define SRSS_CLK_TIMER_CTL_TIMER_DIV_Pos SRSS_V2_CLK_TIMER_CTL_TIMER_DIV_Pos #define SRSS_CLK_TIMER_CTL_TIMER_DIV_Msk SRSS_V2_CLK_TIMER_CTL_TIMER_DIV_Msk #define SRSS_CLK_TIMER_CTL_ENABLE_Pos SRSS_V2_CLK_TIMER_CTL_ENABLE_Pos #define SRSS_CLK_TIMER_CTL_ENABLE_Msk SRSS_V2_CLK_TIMER_CTL_ENABLE_Msk #define WDT_CTL_ENABLED_Pos WDT_V2_CTL_ENABLED_Pos #define WDT_CTL_ENABLED_Msk WDT_V2_CTL_ENABLED_Msk #define WDT_CTL_ENABLE_Pos WDT_V2_CTL_ENABLE_Pos #define WDT_CTL_ENABLE_Msk WDT_V2_CTL_ENABLE_Msk #define WDT_CNT_CNT_Msk WDT_V2_CNT_CNT_Msk #define WDT_CNT_CNT_Pos WDT_V2_CNT_CNT_Pos #define WDT_INTR_MASK_WDT_Msk WDT_V2_INTR_MASK_WDT_Msk #define WDT_INTR_WDT_Pos WDT_V2_INTR_WDT_Pos #define WDT_INTR_WDT_Msk WDT_V2_INTR_WDT_Msk #define WDT_LOCK_WDT_LOCK_Pos WDT_V2_LOCK_WDT_LOCK_Pos #define WDT_LOCK_WDT_LOCK_Msk WDT_V2_LOCK_WDT_LOCK_Msk #define WDT_CONFIG_LOWER_ACTION_Msk WDT_V2_CONFIG_LOWER_ACTION_Msk #define WDT_CONFIG_LOWER_ACTION_Pos WDT_V2_CONFIG_LOWER_ACTION_Pos #define WDT_CONFIG_UPPER_ACTION_Msk WDT_V2_CONFIG_UPPER_ACTION_Msk #define WDT_CONFIG_UPPER_ACTION_Pos WDT_V2_CONFIG_UPPER_ACTION_Pos #define WDT_CONFIG_WARN_ACTION_Msk WDT_V2_CONFIG_WARN_ACTION_Msk #define WDT_CONFIG_WARN_ACTION_Pos WDT_V2_CONFIG_WARN_ACTION_Pos #define WDT_CONFIG_AUTO_SERVICE_Msk WDT_V2_CONFIG_AUTO_SERVICE_Msk #define WDT_CONFIG_AUTO_SERVICE_Pos WDT_V2_CONFIG_AUTO_SERVICE_Pos #define WDT_CONFIG_DPSLP_PAUSE_Msk WDT_V2_CONFIG_DPSLP_PAUSE_Msk #define WDT_CONFIG_DPSLP_PAUSE_Pos WDT_V2_CONFIG_DPSLP_PAUSE_Pos #define WDT_CONFIG_HIB_PAUSE_Msk WDT_V2_CONFIG_HIB_PAUSE_Msk #define WDT_CONFIG_HIB_PAUSE_Pos WDT_V2_CONFIG_HIB_PAUSE_Pos #define WDT_CONFIG_DEBUG_RUN_Msk WDT_V2_CONFIG_DEBUG_RUN_Msk #define WDT_CONFIG_DEBUG_RUN_Pos WDT_V2_CONFIG_DEBUG_RUN_Pos #define WDT_SERVICE_SERVICE_Msk WDT_V2_SERVICE_SERVICE_Msk #define WDT_SERVICE_SERVICE_Pos WDT_V2_SERVICE_SERVICE_Pos #define MCWDT_CTR_CTL_ENABLE_Msk MCWDT_CTR_V2_CTL_ENABLE_Msk #define MCWDT_CTR_CTL_ENABLE_Pos MCWDT_CTR_V2_CTL_ENABLE_Pos #define MCWDT_CTR2_CTL_ENABLE_Msk MCWDT_V2_CTR2_CTL_ENABLE_Msk #define MCWDT_CTR2_CTL_ENABLE_Pos MCWDT_V2_CTR2_CTL_ENABLE_Pos #define MCWDT_LOCK_MCWDT_LOCK_Msk MCWDT_V2_LOCK_MCWDT_LOCK_Msk #define MCWDT_LOCK_MCWDT_LOCK_Pos MCWDT_V2_LOCK_MCWDT_LOCK_Pos #define MCWDT_CTR2_CONFIG_BITS_Msk MCWDT_V2_CTR2_CONFIG_BITS_Msk #define MCWDT_CTR2_CONFIG_BITS_Pos MCWDT_V2_CTR2_CONFIG_BITS_Pos #define MCWDT_CTR_CNT_CNT_Msk MCWDT_CTR_V2_CNT_CNT_Msk #define MCWDT_CTR_CNT_CNT_Pos MCWDT_CTR_V2_CNT_CNT_Pos #define MCWDT_CTR2_CNT_CNT2_Msk MCWDT_V2_CTR2_CNT_CNT2_Msk #define MCWDT_CTR2_CNT_CNT2_Pos MCWDT_V2_CTR2_CNT_CNT2_Pos #define MCWDT_SERVICE_CTR0_SERVICE_Msk MCWDT_V2_SERVICE_CTR0_SERVICE_Msk #define MCWDT_SERVICE_CTR0_SERVICE_Pos MCWDT_V2_SERVICE_CTR0_SERVICE_Pos #define MCWDT_SERVICE_CTR1_SERVICE_Msk MCWDT_V2_SERVICE_CTR1_SERVICE_Msk #define MCWDT_SERVICE_CTR1_SERVICE_Pos MCWDT_V2_SERVICE_CTR1_SERVICE_Pos #define MCWDT_CTR_CONFIG_LOWER_ACTION_Pos MCWDT_CTR_V2_CONFIG_LOWER_ACTION_Pos #define MCWDT_CTR_CONFIG_LOWER_ACTION_Msk MCWDT_CTR_V2_CONFIG_LOWER_ACTION_Msk #define MCWDT_CTR_CONFIG_UPPER_ACTION_Pos MCWDT_CTR_V2_CONFIG_UPPER_ACTION_Pos #define MCWDT_CTR_CONFIG_UPPER_ACTION_Msk MCWDT_CTR_V2_CONFIG_UPPER_ACTION_Msk #define MCWDT_CTR_CONFIG_WARN_ACTION_Pos MCWDT_CTR_V2_CONFIG_WARN_ACTION_Pos #define MCWDT_CTR_CONFIG_WARN_ACTION_Msk MCWDT_CTR_V2_CONFIG_WARN_ACTION_Msk #define MCWDT_CTR_CONFIG_AUTO_SERVICE_Pos MCWDT_CTR_V2_CONFIG_AUTO_SERVICE_Pos #define MCWDT_CTR_CONFIG_AUTO_SERVICE_Msk MCWDT_CTR_V2_CONFIG_AUTO_SERVICE_Msk #define MCWDT_CTR_CONFIG_SLEEPDEEP_PAUSE_Pos MCWDT_CTR_V2_CONFIG_SLEEPDEEP_PAUSE_Pos #define MCWDT_CTR_CONFIG_SLEEPDEEP_PAUSE_Msk MCWDT_CTR_V2_CONFIG_SLEEPDEEP_PAUSE_Msk #define MCWDT_CTR_CONFIG_DEBUG_RUN_Pos MCWDT_CTR_V2_CONFIG_DEBUG_RUN_Pos #define MCWDT_CTR_CONFIG_DEBUG_RUN_Msk MCWDT_CTR_V2_CONFIG_DEBUG_RUN_Msk #define MCWDT_CTR2_CONFIG_ACTION_Pos MCWDT_V2_CTR2_CONFIG_ACTION_Pos #define MCWDT_CTR2_CONFIG_ACTION_Msk MCWDT_V2_CTR2_CONFIG_ACTION_Msk #define MCWDT_CTR2_CONFIG_SLEEPDEEP_PAUSE_Pos MCWDT_V2_CTR2_CONFIG_SLEEPDEEP_PAUSE_Pos #define MCWDT_CTR2_CONFIG_SLEEPDEEP_PAUSE_Msk MCWDT_V2_CTR2_CONFIG_SLEEPDEEP_PAUSE_Msk #define MCWDT_CTR2_CONFIG_DEBUG_RUN_Pos MCWDT_V2_CTR2_CONFIG_DEBUG_RUN_Pos #define MCWDT_CTR2_CONFIG_DEBUG_RUN_Msk MCWDT_V2_CTR2_CONFIG_DEBUG_RUN_Msk #define MCWDT_CPU_SELECT_CPU_SEL_Msk MCWDT_V2_CPU_SELECT_CPU_SEL_Msk #define MCWDT_CPU_SELECT_CPU_SEL_Pos MCWDT_V2_CPU_SELECT_CPU_SEL_Pos #define MCWDT_CTR_LOWER_LIMIT_LOWER_LIMIT_Msk MCWDT_CTR_V2_LOWER_LIMIT_LOWER_LIMIT_Msk #define MCWDT_CTR_LOWER_LIMIT_LOWER_LIMIT_Pos MCWDT_CTR_V2_LOWER_LIMIT_LOWER_LIMIT_Pos #define MCWDT_CTR_UPPER_LIMIT_UPPER_LIMIT_Msk MCWDT_CTR_V2_UPPER_LIMIT_UPPER_LIMIT_Msk #define MCWDT_CTR_UPPER_LIMIT_UPPER_LIMIT_Pos MCWDT_CTR_V2_UPPER_LIMIT_UPPER_LIMIT_Pos #define MCWDT_CTR_WARN_LIMIT_WARN_LIMIT_Msk MCWDT_CTR_V2_WARN_LIMIT_WARN_LIMIT_Msk #define MCWDT_CTR_WARN_LIMIT_WARN_LIMIT_Pos MCWDT_CTR_V2_WARN_LIMIT_WARN_LIMIT_Pos #define MCWDT_INTR_MASKED_CTR0_INT_Msk MCWDT_V2_INTR_MASKED_CTR0_INT_Msk #define MCWDT_INTR_MASKED_CTR1_INT_Msk MCWDT_V2_INTR_MASKED_CTR1_INT_Msk #define MCWDT_INTR_MASKED_CTR2_INT_Msk MCWDT_V2_INTR_MASKED_CTR2_INT_Msk /******************************************************************************* * BACKUP *******************************************************************************/ /* BACKUP.CTL */ #define BACKUP_CTL_WCO_EN_Pos BACKUP_V2_CTL_WCO_EN_Pos #define BACKUP_CTL_WCO_EN_Msk BACKUP_V2_CTL_WCO_EN_Msk #define BACKUP_CTL_CLK_SEL_Pos BACKUP_V2_CTL_CLK_SEL_Pos #define BACKUP_CTL_CLK_SEL_Msk BACKUP_V2_CTL_CLK_SEL_Msk #define BACKUP_CTL_PRESCALER_Pos BACKUP_V2_CTL_PRESCALER_Pos #define BACKUP_CTL_PRESCALER_Msk BACKUP_V2_CTL_PRESCALER_Msk #define BACKUP_CTL_WCO_BYPASS_Pos BACKUP_V2_CTL_WCO_BYPASS_Pos #define BACKUP_CTL_WCO_BYPASS_Msk BACKUP_V2_CTL_WCO_BYPASS_Msk #define BACKUP_CTL_VDDBAK_CTL_Pos BACKUP_V2_CTL_VDDBAK_CTL_Pos #define BACKUP_CTL_VDDBAK_CTL_Msk BACKUP_V2_CTL_VDDBAK_CTL_Msk #define BACKUP_CTL_VBACKUP_MEAS_Pos BACKUP_V2_CTL_VBACKUP_MEAS_Pos #define BACKUP_CTL_VBACKUP_MEAS_Msk BACKUP_V2_CTL_VBACKUP_MEAS_Msk #define BACKUP_CTL_EN_CHARGE_KEY_Pos BACKUP_V2_CTL_EN_CHARGE_KEY_Pos #define BACKUP_CTL_EN_CHARGE_KEY_Msk BACKUP_V2_CTL_EN_CHARGE_KEY_Msk /* BACKUP.RTC_RW */ #define BACKUP_RTC_RW_READ_Pos BACKUP_V2_RTC_RW_READ_Pos #define BACKUP_RTC_RW_READ_Msk BACKUP_V2_RTC_RW_READ_Msk #define BACKUP_RTC_RW_WRITE_Pos BACKUP_V2_RTC_RW_WRITE_Pos #define BACKUP_RTC_RW_WRITE_Msk BACKUP_V2_RTC_RW_WRITE_Msk /* BACKUP.CAL_CTL */ #define BACKUP_CAL_CTL_CALIB_VAL_Pos BACKUP_V2_CAL_CTL_CALIB_VAL_Pos #define BACKUP_CAL_CTL_CALIB_VAL_Msk BACKUP_V2_CAL_CTL_CALIB_VAL_Msk #define BACKUP_CAL_CTL_CALIB_SIGN_Pos BACKUP_V2_CAL_CTL_CALIB_SIGN_Pos #define BACKUP_CAL_CTL_CALIB_SIGN_Msk BACKUP_V2_CAL_CTL_CALIB_SIGN_Msk #define BACKUP_CAL_CTL_CAL_SEL_Pos BACKUP_V2_CAL_CTL_CAL_SEL_Pos #define BACKUP_CAL_CTL_CAL_SEL_Msk BACKUP_V2_CAL_CTL_CAL_SEL_Msk #define BACKUP_CAL_CTL_CAL_OUT_Pos BACKUP_V2_CAL_CTL_CAL_OUT_Pos #define BACKUP_CAL_CTL_CAL_OUT_Msk BACKUP_V2_CAL_CTL_CAL_OUT_Msk /* BACKUP.STATUS */ #define BACKUP_STATUS_RTC_BUSY_Pos BACKUP_V2_STATUS_RTC_BUSY_Pos #define BACKUP_STATUS_RTC_BUSY_Msk BACKUP_V2_STATUS_RTC_BUSY_Msk #define BACKUP_STATUS_WCO_OK_Pos BACKUP_V2_STATUS_WCO_OK_Pos #define BACKUP_STATUS_WCO_OK_Msk BACKUP_V2_STATUS_WCO_OK_Msk /* BACKUP.RTC_TIME */ #define BACKUP_RTC_TIME_RTC_SEC_Pos BACKUP_V2_RTC_TIME_RTC_SEC_Pos #define BACKUP_RTC_TIME_RTC_SEC_Msk BACKUP_V2_RTC_TIME_RTC_SEC_Msk #define BACKUP_RTC_TIME_RTC_MIN_Pos BACKUP_V2_RTC_TIME_RTC_MIN_Pos #define BACKUP_RTC_TIME_RTC_MIN_Msk BACKUP_V2_RTC_TIME_RTC_MIN_Msk #define BACKUP_RTC_TIME_RTC_HOUR_Pos BACKUP_V2_RTC_TIME_RTC_HOUR_Pos #define BACKUP_RTC_TIME_RTC_HOUR_Msk BACKUP_V2_RTC_TIME_RTC_HOUR_Msk #define BACKUP_RTC_TIME_CTRL_12HR_Pos BACKUP_V2_RTC_TIME_CTRL_12HR_Pos #define BACKUP_RTC_TIME_CTRL_12HR_Msk BACKUP_V2_RTC_TIME_CTRL_12HR_Msk #define BACKUP_RTC_TIME_RTC_DAY_Pos BACKUP_V2_RTC_TIME_RTC_DAY_Pos #define BACKUP_RTC_TIME_RTC_DAY_Msk BACKUP_V2_RTC_TIME_RTC_DAY_Msk /* BACKUP.RTC_DATE */ #define BACKUP_RTC_DATE_RTC_DATE_Pos BACKUP_V2_RTC_DATE_RTC_DATE_Pos #define BACKUP_RTC_DATE_RTC_DATE_Msk BACKUP_V2_RTC_DATE_RTC_DATE_Msk #define BACKUP_RTC_DATE_RTC_MON_Pos BACKUP_V2_RTC_DATE_RTC_MON_Pos #define BACKUP_RTC_DATE_RTC_MON_Msk BACKUP_V2_RTC_DATE_RTC_MON_Msk #define BACKUP_RTC_DATE_RTC_YEAR_Pos BACKUP_V2_RTC_DATE_RTC_YEAR_Pos #define BACKUP_RTC_DATE_RTC_YEAR_Msk BACKUP_V2_RTC_DATE_RTC_YEAR_Msk /* BACKUP.ALM1_TIME */ #define BACKUP_ALM1_TIME_ALM_SEC_Pos BACKUP_V2_ALM1_TIME_ALM_SEC_Pos #define BACKUP_ALM1_TIME_ALM_SEC_Msk BACKUP_V2_ALM1_TIME_ALM_SEC_Msk #define BACKUP_ALM1_TIME_ALM_SEC_EN_Pos BACKUP_V2_ALM1_TIME_ALM_SEC_EN_Pos #define BACKUP_ALM1_TIME_ALM_SEC_EN_Msk BACKUP_V2_ALM1_TIME_ALM_SEC_EN_Msk #define BACKUP_ALM1_TIME_ALM_MIN_Pos BACKUP_V2_ALM1_TIME_ALM_MIN_Pos #define BACKUP_ALM1_TIME_ALM_MIN_Msk BACKUP_V2_ALM1_TIME_ALM_MIN_Msk #define BACKUP_ALM1_TIME_ALM_MIN_EN_Pos BACKUP_V2_ALM1_TIME_ALM_MIN_EN_Pos #define BACKUP_ALM1_TIME_ALM_MIN_EN_Msk BACKUP_V2_ALM1_TIME_ALM_MIN_EN_Msk #define BACKUP_ALM1_TIME_ALM_HOUR_Pos BACKUP_V2_ALM1_TIME_ALM_HOUR_Pos #define BACKUP_ALM1_TIME_ALM_HOUR_Msk BACKUP_V2_ALM1_TIME_ALM_HOUR_Msk #define BACKUP_ALM1_TIME_ALM_HOUR_EN_Pos BACKUP_V2_ALM1_TIME_ALM_HOUR_EN_Pos #define BACKUP_ALM1_TIME_ALM_HOUR_EN_Msk BACKUP_V2_ALM1_TIME_ALM_HOUR_EN_Msk #define BACKUP_ALM1_TIME_ALM_DAY_Pos BACKUP_V2_ALM1_TIME_ALM_DAY_Pos #define BACKUP_ALM1_TIME_ALM_DAY_Msk BACKUP_V2_ALM1_TIME_ALM_DAY_Msk #define BACKUP_ALM1_TIME_ALM_DAY_EN_Pos BACKUP_V2_ALM1_TIME_ALM_DAY_EN_Pos #define BACKUP_ALM1_TIME_ALM_DAY_EN_Msk BACKUP_V2_ALM1_TIME_ALM_DAY_EN_Msk /* BACKUP.ALM1_DATE */ #define BACKUP_ALM1_DATE_ALM_DATE_Pos BACKUP_V2_ALM1_DATE_ALM_DATE_Pos #define BACKUP_ALM1_DATE_ALM_DATE_Msk BACKUP_V2_ALM1_DATE_ALM_DATE_Msk #define BACKUP_ALM1_DATE_ALM_DATE_EN_Pos BACKUP_V2_ALM1_DATE_ALM_DATE_EN_Pos #define BACKUP_ALM1_DATE_ALM_DATE_EN_Msk BACKUP_V2_ALM1_DATE_ALM_DATE_EN_Msk #define BACKUP_ALM1_DATE_ALM_MON_Pos BACKUP_V2_ALM1_DATE_ALM_MON_Pos #define BACKUP_ALM1_DATE_ALM_MON_Msk BACKUP_V2_ALM1_DATE_ALM_MON_Msk #define BACKUP_ALM1_DATE_ALM_MON_EN_Pos BACKUP_V2_ALM1_DATE_ALM_MON_EN_Pos #define BACKUP_ALM1_DATE_ALM_MON_EN_Msk BACKUP_V2_ALM1_DATE_ALM_MON_EN_Msk #define BACKUP_ALM1_DATE_ALM_EN_Pos BACKUP_V2_ALM1_DATE_ALM_EN_Pos #define BACKUP_ALM1_DATE_ALM_EN_Msk BACKUP_V2_ALM1_DATE_ALM_EN_Msk /* BACKUP.ALM2_TIME */ #define BACKUP_ALM2_TIME_ALM_SEC_Pos BACKUP_V2_ALM2_TIME_ALM_SEC_Pos #define BACKUP_ALM2_TIME_ALM_SEC_Msk BACKUP_V2_ALM2_TIME_ALM_SEC_Msk #define BACKUP_ALM2_TIME_ALM_SEC_EN_Pos BACKUP_V2_ALM2_TIME_ALM_SEC_EN_Pos #define BACKUP_ALM2_TIME_ALM_SEC_EN_Msk BACKUP_V2_ALM2_TIME_ALM_SEC_EN_Msk #define BACKUP_ALM2_TIME_ALM_MIN_Pos BACKUP_V2_ALM2_TIME_ALM_MIN_Pos #define BACKUP_ALM2_TIME_ALM_MIN_Msk BACKUP_V2_ALM2_TIME_ALM_MIN_Msk #define BACKUP_ALM2_TIME_ALM_MIN_EN_Pos BACKUP_V2_ALM2_TIME_ALM_MIN_EN_Pos #define BACKUP_ALM2_TIME_ALM_MIN_EN_Msk BACKUP_V2_ALM2_TIME_ALM_MIN_EN_Msk #define BACKUP_ALM2_TIME_ALM_HOUR_Pos BACKUP_V2_ALM2_TIME_ALM_HOUR_Pos #define BACKUP_ALM2_TIME_ALM_HOUR_Msk BACKUP_V2_ALM2_TIME_ALM_HOUR_Msk #define BACKUP_ALM2_TIME_ALM_HOUR_EN_Pos BACKUP_V2_ALM2_TIME_ALM_HOUR_EN_Pos #define BACKUP_ALM2_TIME_ALM_HOUR_EN_Msk BACKUP_V2_ALM2_TIME_ALM_HOUR_EN_Msk #define BACKUP_ALM2_TIME_ALM_DAY_Pos BACKUP_V2_ALM2_TIME_ALM_DAY_Pos #define BACKUP_ALM2_TIME_ALM_DAY_Msk BACKUP_V2_ALM2_TIME_ALM_DAY_Msk #define BACKUP_ALM2_TIME_ALM_DAY_EN_Pos BACKUP_V2_ALM2_TIME_ALM_DAY_EN_Pos #define BACKUP_ALM2_TIME_ALM_DAY_EN_Msk BACKUP_V2_ALM2_TIME_ALM_DAY_EN_Msk /* BACKUP.ALM2_DATE */ #define BACKUP_ALM2_DATE_ALM_DATE_Pos BACKUP_V2_ALM2_DATE_ALM_DATE_Pos #define BACKUP_ALM2_DATE_ALM_DATE_Msk BACKUP_V2_ALM2_DATE_ALM_DATE_Msk #define BACKUP_ALM2_DATE_ALM_DATE_EN_Pos BACKUP_V2_ALM2_DATE_ALM_DATE_EN_Pos #define BACKUP_ALM2_DATE_ALM_DATE_EN_Msk BACKUP_V2_ALM2_DATE_ALM_DATE_EN_Msk #define BACKUP_ALM2_DATE_ALM_MON_Pos BACKUP_V2_ALM2_DATE_ALM_MON_Pos #define BACKUP_ALM2_DATE_ALM_MON_Msk BACKUP_V2_ALM2_DATE_ALM_MON_Msk #define BACKUP_ALM2_DATE_ALM_MON_EN_Pos BACKUP_V2_ALM2_DATE_ALM_MON_EN_Pos #define BACKUP_ALM2_DATE_ALM_MON_EN_Msk BACKUP_V2_ALM2_DATE_ALM_MON_EN_Msk #define BACKUP_ALM2_DATE_ALM_EN_Pos BACKUP_V2_ALM2_DATE_ALM_EN_Pos #define BACKUP_ALM2_DATE_ALM_EN_Msk BACKUP_V2_ALM2_DATE_ALM_EN_Msk /* BACKUP.INTR */ #define BACKUP_INTR_ALARM1_Pos BACKUP_V2_INTR_ALARM1_Pos #define BACKUP_INTR_ALARM1_Msk BACKUP_V2_INTR_ALARM1_Msk #define BACKUP_INTR_ALARM2_Pos BACKUP_V2_INTR_ALARM2_Pos #define BACKUP_INTR_ALARM2_Msk BACKUP_V2_INTR_ALARM2_Msk #define BACKUP_INTR_CENTURY_Pos BACKUP_V2_INTR_CENTURY_Pos #define BACKUP_INTR_CENTURY_Msk BACKUP_V2_INTR_CENTURY_Msk /* BACKUP.INTR_SET */ #define BACKUP_INTR_SET_ALARM1_Pos BACKUP_V2_INTR_SET_ALARM1_Pos #define BACKUP_INTR_SET_ALARM1_Msk BACKUP_V2_INTR_SET_ALARM1_Msk #define BACKUP_INTR_SET_ALARM2_Pos BACKUP_V2_INTR_SET_ALARM2_Pos #define BACKUP_INTR_SET_ALARM2_Msk BACKUP_V2_INTR_SET_ALARM2_Msk #define BACKUP_INTR_SET_CENTURY_Pos BACKUP_V2_INTR_SET_CENTURY_Pos #define BACKUP_INTR_SET_CENTURY_Msk BACKUP_V2_INTR_SET_CENTURY_Msk /* BACKUP.INTR_MASK */ #define BACKUP_INTR_MASK_ALARM1_Pos BACKUP_V2_INTR_MASK_ALARM1_Pos #define BACKUP_INTR_MASK_ALARM1_Msk BACKUP_V2_INTR_MASK_ALARM1_Msk #define BACKUP_INTR_MASK_ALARM2_Pos BACKUP_V2_INTR_MASK_ALARM2_Pos #define BACKUP_INTR_MASK_ALARM2_Msk BACKUP_V2_INTR_MASK_ALARM2_Msk #define BACKUP_INTR_MASK_CENTURY_Pos BACKUP_V2_INTR_MASK_CENTURY_Pos #define BACKUP_INTR_MASK_CENTURY_Msk BACKUP_V2_INTR_MASK_CENTURY_Msk /* BACKUP.INTR_MASKED */ #define BACKUP_INTR_MASKED_ALARM1_Pos BACKUP_V2_INTR_MASKED_ALARM1_Pos #define BACKUP_INTR_MASKED_ALARM1_Msk BACKUP_V2_INTR_MASKED_ALARM1_Msk #define BACKUP_INTR_MASKED_ALARM2_Pos BACKUP_V2_INTR_MASKED_ALARM2_Pos #define BACKUP_INTR_MASKED_ALARM2_Msk BACKUP_V2_INTR_MASKED_ALARM2_Msk #define BACKUP_INTR_MASKED_CENTURY_Pos BACKUP_V2_INTR_MASKED_CENTURY_Pos #define BACKUP_INTR_MASKED_CENTURY_Msk BACKUP_V2_INTR_MASKED_CENTURY_Msk /* BACKUP.PMIC_CTL */ #define BACKUP_PMIC_CTL_UNLOCK_Pos BACKUP_V2_PMIC_CTL_UNLOCK_Pos #define BACKUP_PMIC_CTL_UNLOCK_Msk BACKUP_V2_PMIC_CTL_UNLOCK_Msk #define BACKUP_PMIC_CTL_POLARITY_Pos BACKUP_V2_PMIC_CTL_POLARITY_Pos #define BACKUP_PMIC_CTL_POLARITY_Msk BACKUP_V2_PMIC_CTL_POLARITY_Msk #define BACKUP_PMIC_CTL_PMIC_EN_OUTEN_Pos BACKUP_V2_PMIC_CTL_PMIC_EN_OUTEN_Pos #define BACKUP_PMIC_CTL_PMIC_EN_OUTEN_Msk BACKUP_V2_PMIC_CTL_PMIC_EN_OUTEN_Msk #define BACKUP_PMIC_CTL_PMIC_ALWAYSEN_Pos BACKUP_V2_PMIC_CTL_PMIC_ALWAYSEN_Pos #define BACKUP_PMIC_CTL_PMIC_ALWAYSEN_Msk BACKUP_V2_PMIC_CTL_PMIC_ALWAYSEN_Msk #define BACKUP_PMIC_CTL_PMIC_EN_Pos BACKUP_V2_PMIC_CTL_PMIC_EN_Pos #define BACKUP_PMIC_CTL_PMIC_EN_Msk BACKUP_V2_PMIC_CTL_PMIC_EN_Msk /* BACKUP.RESET */ #define BACKUP_RESET_RESET_Pos BACKUP_V2_RESET_RESET_Pos #define BACKUP_RESET_RESET_Msk BACKUP_V2_RESET_RESET_Msk /* BACKUP.BREG */ #define BACKUP_BREG_BREG_Pos BACKUP_V2_BREG_BREG_Pos #define BACKUP_BREG_BREG_Msk BACKUP_V2_BREG_BREG_Msk #elif defined(CY_DEVICE_TVIIBE4M) /* SRSSv3 remaps for what is generated in a TVII generated header file */ /******************************************************************************* * SRSS *******************************************************************************/ /* SRSS 3 Additions for TVII Generated Header file */ #define SRSS_PWR_HIBERNATE_MASK_HIBPIN_Pos SRSS_V3_PWR_HIBERNATE_MASK_HIBPIN_Pos #define SRSS_PWR_HIBERNATE_MASK_HIBPIN_Msk SRSS_V3_PWR_HIBERNATE_MASK_HIBPIN_Msk #define SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Pos SRSS_V3_PWR_HIBERNATE_POLARITY_HIBPIN_Pos #define SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Msk SRSS_V3_PWR_HIBERNATE_POLARITY_HIBPIN_Msk #define SRSS_PWR_HIBERNATE_MASK_HIBALARM_Msk SRSS_V3_PWR_HIBERNATE_MASK_HIBALARM_Msk #define SRSS_PWR_HIBERNATE_MASK_HIBALARM_Pos SRSS_V3_PWR_HIBERNATE_MASK_HIBALARM_Pos #define SRSS_PWR_HIBERNATE_MASK_HIBWDT_Msk SRSS_V3_PWR_HIBERNATE_MASK_HIBWDT_Msk #define SRSS_PWR_LVD_CTL_HVLVD1_EN_HT_Msk SRSS_V3_PWR_LVD_CTL_HVLVD1_EN_HT_Msk #define SRSS_PWR_LVD_CTL_HVLVD1_EN_HT_Pos SRSS_V3_PWR_LVD_CTL_HVLVD1_EN_HT_Pos #define SRSS_PWR_LVD_CTL_HVLVD1_EN_HT_Msk SRSS_V3_PWR_LVD_CTL_HVLVD1_EN_HT_Msk #define SRSS_PWR_LVD_CTL_HVLVD1_EN_HT_Pos SRSS_V3_PWR_LVD_CTL_HVLVD1_EN_HT_Pos #define SRSS_PWR_LVD_CTL2_HVLVD2_EN_HT_Msk SRSS_V3_PWR_LVD_CTL2_HVLVD2_EN_HT_Msk #define SRSS_PWR_LVD_CTL2_HVLVD2_EN_HT_Pos SRSS_V3_PWR_LVD_CTL2_HVLVD2_EN_HT_Pos #define SRSS_PWR_LVD_CTL_HVLVD1_TRIPSEL_HT_Msk SRSS_V3_PWR_LVD_CTL_HVLVD1_TRIPSEL_HT_Msk #define SRSS_PWR_LVD_CTL_HVLVD1_TRIPSEL_HT_Pos SRSS_V3_PWR_LVD_CTL_HVLVD1_TRIPSEL_HT_Pos #define SRSS_PWR_LVD_CTL2_HVLVD2_TRIPSEL_HT_Msk SRSS_V3_PWR_LVD_CTL2_HVLVD2_TRIPSEL_HT_Msk #define SRSS_PWR_LVD_CTL2_HVLVD2_TRIPSEL_HT_Pos SRSS_V3_PWR_LVD_CTL2_HVLVD2_TRIPSEL_HT_Pos #define SRSS_PWR_LVD_STATUS_HVLVD1_OUT_Msk SRSS_V3_PWR_LVD_STATUS_HVLVD1_OUT_Msk #define SRSS_PWR_LVD_STATUS_HVLVD1_OUT_Pos SRSS_V3_PWR_LVD_STATUS_HVLVD1_OUT_Pos #define SRSS_PWR_LVD_STATUS2_HVLVD2_OUT_Msk SRSS_V3_PWR_LVD_STATUS2_HVLVD2_OUT_Msk #define SRSS_PWR_LVD_STATUS2_HVLVD2_OUT_Pos SRSS_V3_PWR_LVD_STATUS2_HVLVD2_OUT_Pos #define SRSS_SRSS_INTR_HVLVD1_Msk SRSS_V3_SRSS_INTR_HVLVD1_Msk #define SRSS_SRSS_INTR_HVLVD1_Pos SRSS_V3_SRSS_INTR_HVLVD1_Pos #define SRSS_SRSS_INTR_HVLVD2_Msk SRSS_V3_SRSS_INTR_HVLVD2_Msk #define SRSS_SRSS_INTR_HVLVD2_Pos SRSS_V3_SRSS_INTR_HVLVD2_Pos #define SRSS_SRSS_INTR_SET_HVLVD1_Msk SRSS_V3_SRSS_INTR_SET_HVLVD1_Msk #define SRSS_SRSS_INTR_SET_HVLVD1_Pos SRSS_V3_SRSS_INTR_SET_HVLVD1_Pos #define SRSS_SRSS_INTR_SET_HVLVD2_Msk SRSS_V3_SRSS_INTR_SET_HVLVD2_Msk #define SRSS_SRSS_INTR_SET_HVLVD2_Pos SRSS_V3_SRSS_INTR_SET_HVLVD2_Pos #define SRSS_SRSS_INTR_MASK_HVLVD1_Msk SRSS_V3_SRSS_INTR_MASK_HVLVD1_Msk #define SRSS_SRSS_INTR_MASK_HVLVD1_Pos SRSS_V3_SRSS_INTR_MASK_HVLVD1_Pos #define SRSS_SRSS_INTR_MASK_HVLVD2_Msk SRSS_V3_SRSS_INTR_MASK_HVLVD2_Msk #define SRSS_SRSS_INTR_MASK_HVLVD2_Pos SRSS_V3_SRSS_INTR_MASK_HVLVD2_Pos #define SRSS_PWR_LVD_CTL_HVLVD1_EDGE_SEL_Msk SRSS_V3_PWR_LVD_CTL_HVLVD1_EDGE_SEL_Msk #define SRSS_PWR_LVD_CTL_HVLVD1_EDGE_SEL_Pos SRSS_V3_PWR_LVD_CTL_HVLVD1_EDGE_SEL_Pos #define SRSS_PWR_LVD_CTL_HVLVD2_EDGE_SEL_Msk SRSS_V3_PWR_LVD_CTL_HVLVD2_EDGE_SEL_Msk #define SRSS_PWR_LVD_CTL_HVLVD2_EDGE_SEL_Pos SRSS_V3_PWR_LVD_CTL_HVLVD2_EDGE_SEL_Pos #define SRSS_PWR_LVD_CTL2_HVLVD2_EDGE_SEL_Msk SRSS_V3_PWR_LVD_CTL2_HVLVD2_EDGE_SEL_Msk #define SRSS_PWR_LVD_CTL2_HVLVD2_EDGE_SEL_Pos SRSS_V3_PWR_LVD_CTL2_HVLVD2_EDGE_SEL_Pos #define SRSS_PWR_LVD_CTL2_HVLVD2_ACTION_Msk SRSS_V3_PWR_LVD_CTL2_HVLVD2_ACTION_Msk #define SRSS_PWR_LVD_CTL2_HVLVD2_ACTION_Pos SRSS_V3_PWR_LVD_CTL2_HVLVD2_ACTION_Pos #define SRSS_PWR_LVD_CTL_HVLVD1_ACTION_Msk SRSS_V3_PWR_LVD_CTL_HVLVD1_ACTION_Msk #define SRSS_PWR_LVD_CTL_HVLVD1_ACTION_Pos SRSS_V3_PWR_LVD_CTL_HVLVD1_ACTION_Pos #define SRSS_PWR_LVD_CTL_HVLVD1_DPSLP_EN_HT_Msk SRSS_V3_PWR_LVD_CTL_HVLVD1_DPSLP_EN_HT_Msk #define SRSS_PWR_LVD_CTL_HVLVD1_DPSLP_EN_HT_Pos SRSS_V3_PWR_LVD_CTL_HVLVD1_DPSLP_EN_HT_Pos #define SRSS_PWR_LVD_CTL2_HVLVD2_DPSLP_EN_HT_Msk SRSS_V3_PWR_LVD_CTL2_HVLVD2_DPSLP_EN_HT_Msk #define SRSS_PWR_LVD_CTL2_HVLVD2_DPSLP_EN_HT_Pos SRSS_V3_PWR_LVD_CTL2_HVLVD2_DPSLP_EN_HT_Pos #define SRSS_CLK_SELECT_PUMP_SEL_Msk SRSS_V3_CLK_SELECT_PUMP_SEL_Msk #define SRSS_CLK_SELECT_PUMP_SEL_Pos SRSS_V3_CLK_SELECT_PUMP_SEL_Pos #define SRSS_CLK_SELECT_PUMP_DIV_Msk SRSS_V3_CLK_SELECT_PUMP_DIV_Msk #define SRSS_CLK_SELECT_PUMP_DIV_Pos SRSS_V3_CLK_SELECT_PUMP_DIV_Pos #define SRSS_RES_CAUSE2_RESET_CSV_HF_Msk SRSS_V3_RES_CAUSE2_RESET_CSV_HF_Msk #define SRSS_RES_CAUSE2_RESET_CSV_HF_Pos SRSS_V3_RES_CAUSE2_RESET_CSV_HF_Pos #define SRSS_CLK_SELECT_PUMP_ENABLE_Msk SRSS_V3_CLK_SELECT_PUMP_ENABLE_Msk #define SRSS_CLK_SELECT_PUMP_ENABLE_Pos SRSS_V3_CLK_SELECT_PUMP_ENABLE_Pos #define SRSS_PWR_CTL2_BGREF_LPMODE_Msk SRSS_V3_PWR_CTL2_BGREF_LPMODE_Msk #define SRSS_PWR_CTL2_BGREF_LPMODE_Pos SRSS_V3_PWR_CTL2_BGREF_LPMODE_Pos #define SRSS_RES_CAUSE2_RESET_CSV_HF_Pos SRSS_V3_RES_CAUSE2_RESET_CSV_HF_Pos #define SRSS_RES_CAUSE2_RESET_CSV_HF_Msk SRSS_V3_RES_CAUSE2_RESET_CSV_HF_Msk #define SRSS_PWR_HIBERNATE_TOKEN_Msk SRSS_V3_PWR_HIBERNATE_TOKEN_Msk #define SRSS_PWR_HIBERNATE_TOKEN_Pos SRSS_V3_PWR_HIBERNATE_TOKEN_Pos #define SRSS_PWR_HIBERNATE_UNLOCK_Pos SRSS_V3_PWR_HIBERNATE_UNLOCK_Pos #define SRSS_PWR_HIBERNATE_UNLOCK_Msk SRSS_V3_PWR_HIBERNATE_UNLOCK_Msk #define SRSS_PWR_HIBERNATE_FREEZE_Msk SRSS_V3_PWR_HIBERNATE_FREEZE_Msk #define SRSS_PWR_HIBERNATE_FREEZE_Pos SRSS_V3_PWR_HIBERNATE_FREEZE_Pos #define SRSS_PWR_HIBERNATE_HIBERNATE_Msk SRSS_V3_PWR_HIBERNATE_HIBERNATE_Msk #define SRSS_PWR_HIBERNATE_HIBERNATE_Pos SRSS_V3_PWR_HIBERNATE_HIBERNATE_Pos #define SRSS_CLK_SELECT_LFCLK_SEL_Msk SRSS_V3_CLK_SELECT_LFCLK_SEL_Msk #define SRSS_CLK_SELECT_LFCLK_SEL_Pos SRSS_V3_CLK_SELECT_LFCLK_SEL_Pos #define SRSS_RES_CAUSE2_RESET_CSV_REF_Msk SRSS_V3_RES_CAUSE2_RESET_CSV_REF_Msk #define SRSS_RES_CAUSE2_RESET_CSV_REF_Pos SRSS_V3_RES_CAUSE2_RESET_CSV_REF_Pos #define SRSS_CLK_ROOT_SELECT_ENABLE_Msk SRSS_V3_CLK_ROOT_SELECT_ENABLE_Msk #define SRSS_CLK_ROOT_SELECT_ENABLE_Pos SRSS_V3_CLK_ROOT_SELECT_ENABLE_Pos #define SRSS_CLK_ROOT_SELECT_ROOT_MUX_Msk SRSS_V3_CLK_ROOT_SELECT_ROOT_MUX_Msk #define SRSS_CLK_ROOT_SELECT_ROOT_MUX_Pos SRSS_V3_CLK_ROOT_SELECT_ROOT_MUX_Pos #define SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk SRSS_V3_CLK_ROOT_SELECT_ROOT_DIV_Msk #define SRSS_CLK_ROOT_SELECT_ROOT_DIV_Pos SRSS_V3_CLK_ROOT_SELECT_ROOT_DIV_Pos #define SRSS_CLK_ROOT_SELECT_DIRECT_MUX_Msk SRSS_V3_CLK_ROOT_SELECT_DIRECT_MUX_Msk #define SRSS_CLK_ROOT_SELECT_DIRECT_MUX_Pos SRSS_V3_CLK_ROOT_SELECT_DIRECT_MUX_Pos #define SRSS_PWR_CTL2_LINREG_DIS_Msk SRSS_V3_PWR_CTL2_LINREG_DIS_Msk #define SRSS_PWR_CTL2_LINREG_DIS_Pos SRSS_V3_PWR_CTL2_LINREG_DIS_Pos #define SRSS_PWR_CTL2_DPSLP_REG_DIS_Msk SRSS_V3_PWR_CTL2_DPSLP_REG_DIS_Msk #define SRSS_PWR_CTL2_DPSLP_REG_DIS_Pos SRSS_V3_PWR_CTL2_DPSLP_REG_DIS_Pos #define SRSS_CLK_ILO0_CONFIG_ENABLE_Msk SRSS_V3_CLK_ILO0_CONFIG_ENABLE_Msk #define SRSS_CLK_ILO0_CONFIG_ENABLE_Pos SRSS_V3_CLK_ILO0_CONFIG_ENABLE_Pos #define SRSS_CLK_ILO0_CONFIG_ILO0_BACKUP_Msk SRSS_V3_CLK_ILO0_CONFIG_ILO0_BACKUP_Msk #define SRSS_CLK_ILO0_CONFIG_ILO0_BACKUP_Pos SRSS_V3_CLK_ILO0_CONFIG_ILO0_BACKUP_Pos #define SRSS_CLK_ILO1_CONFIG_ENABLE_Msk SRSS_V3_CLK_ILO1_CONFIG_ENABLE_Msk #define SRSS_CLK_ILO1_CONFIG_ENABLE_Pos SRSS_V3_CLK_ILO1_CONFIG_ENABLE_Pos #define SRSS_CLK_ECO_CONFIG_ECO_EN_Msk SRSS_V3_CLK_ECO_CONFIG_ECO_EN_Msk #define SRSS_CLK_ECO_CONFIG_ECO_EN_Pos SRSS_V3_CLK_ECO_CONFIG_ECO_EN_Pos #define SRSS_CLK_ECO_CONFIG2_WDTRIM_Pos SRSS_V3_CLK_ECO_CONFIG2_WDTRIM_Pos #define SRSS_CLK_ECO_CONFIG2_WDTRIM_Msk SRSS_V3_CLK_ECO_CONFIG2_WDTRIM_Msk #define SRSS_CLK_ECO_CONFIG2_ATRIM_Pos SRSS_V3_CLK_ECO_CONFIG2_ATRIM_Pos #define SRSS_CLK_ECO_CONFIG2_ATRIM_Msk SRSS_V3_CLK_ECO_CONFIG2_ATRIM_Msk #define SRSS_CLK_ECO_CONFIG2_FTRIM_Msk SRSS_V3_CLK_ECO_CONFIG2_FTRIM_Msk #define SRSS_CLK_ECO_CONFIG2_FTRIM_Pos SRSS_V3_CLK_ECO_CONFIG2_FTRIM_Pos #define SRSS_CLK_ECO_CONFIG2_RTRIM_Pos SRSS_V3_CLK_ECO_CONFIG2_RTRIM_Pos #define SRSS_CLK_ECO_CONFIG2_RTRIM_Msk SRSS_V3_CLK_ECO_CONFIG2_RTRIM_Msk #define SRSS_CLK_ECO_CONFIG2_GTRIM_Pos SRSS_V3_CLK_ECO_CONFIG2_GTRIM_Pos #define SRSS_CLK_ECO_CONFIG2_GTRIM_Msk SRSS_V3_CLK_ECO_CONFIG2_GTRIM_Msk #define SRSS_CLK_ECO_CONFIG_AGC_EN_Pos SRSS_V3_CLK_ECO_CONFIG_AGC_EN_Pos #define SRSS_CLK_ECO_CONFIG_AGC_EN_Msk SRSS_V3_CLK_ECO_CONFIG_AGC_EN_Msk #define SRSS_PWR_CTL_LPM_READY_Msk SRSS_V3_PWR_CTL_LPM_READY_Msk #define SRSS_PWR_CTL_LPM_READY_Pos SRSS_V3_PWR_CTL_LPM_READY_Pos #define SRSS_CLK_ECO_STATUS_ECO_OK_Msk SRSS_V3_CLK_ECO_STATUS_ECO_OK_Msk #define SRSS_CLK_ECO_STATUS_ECO_OK_Pos SRSS_V3_CLK_ECO_STATUS_ECO_OK_Pos #define SRSS_CLK_ECO_STATUS_ECO_READY_Msk SRSS_V3_CLK_ECO_STATUS_ECO_READY_Msk #define SRSS_CLK_ECO_STATUS_ECO_READY_Pos SRSS_V3_CLK_ECO_STATUS_ECO_READY_Pos #define SRSS_CLK_ECO_PRESCALE_ECO_DIV_ENABLED_Msk SRSS_V3_CLK_ECO_PRESCALE_ECO_DIV_ENABLED_Msk #define SRSS_CLK_ECO_PRESCALE_ECO_DIV_ENABLED_Pos SRSS_V3_CLK_ECO_PRESCALE_ECO_DIV_ENABLED_Pos #define SRSS_CLK_ECO_PRESCALE_ECO_INT_DIV_Pos SRSS_V3_CLK_ECO_PRESCALE_ECO_INT_DIV_Pos #define SRSS_CLK_ECO_PRESCALE_ECO_INT_DIV_Msk SRSS_V3_CLK_ECO_PRESCALE_ECO_INT_DIV_Msk #define SRSS_CLK_ECO_PRESCALE_ECO_INT_DIV_Msk SRSS_V3_CLK_ECO_PRESCALE_ECO_INT_DIV_Msk #define SRSS_CLK_ECO_PRESCALE_ECO_INT_DIV_Pos SRSS_V3_CLK_ECO_PRESCALE_ECO_INT_DIV_Pos #define SRSS_CLK_ECO_PRESCALE_ECO_FRAC_DIV_Pos SRSS_V3_CLK_ECO_PRESCALE_ECO_FRAC_DIV_Pos #define SRSS_CLK_ECO_PRESCALE_ECO_FRAC_DIV_Msk SRSS_V3_CLK_ECO_PRESCALE_ECO_FRAC_DIV_Msk #define SRSS_PWR_SSV_CTL_OVDVDDD_ENABLE_Msk SRSS_V3_PWR_SSV_CTL_OVDVDDD_ENABLE_Msk #define SRSS_PWR_SSV_CTL_OVDVDDD_ENABLE_Pos SRSS_V3_PWR_SSV_CTL_OVDVDDD_ENABLE_Pos #define SRSS_CLK_ECO_CONFIG_ECO_DIV_ENABLE_Msk SRSS_V3_CLK_ECO_CONFIG_ECO_DIV_ENABLE_Msk #define SRSS_CLK_ECO_CONFIG_ECO_DIV_ENABLE_Pos SRSS_V3_CLK_ECO_CONFIG_ECO_DIV_ENABLE_Pos #define SRSS_PWR_SSV_CTL_OVDVDDA_ENABLE_Msk SRSS_V3_PWR_SSV_CTL_OVDVDDA_ENABLE_Msk #define SRSS_PWR_SSV_CTL_OVDVDDA_ENABLE_Pos SRSS_V3_PWR_SSV_CTL_OVDVDDA_ENABLE_Pos #define SRSS_CLK_ECO_CONFIG_ECO_DIV_DISABLE_Msk SRSS_V3_CLK_ECO_CONFIG_ECO_DIV_DISABLE_Msk #define SRSS_CLK_ECO_CONFIG_ECO_DIV_DISABLE_Pos SRSS_V3_CLK_ECO_CONFIG_ECO_DIV_DISABLE_Pos #define SRSS_CLK_IMO_CONFIG_ENABLE_Msk SRSS_V3_CLK_IMO_CONFIG_ENABLE_Msk #define SRSS_CLK_IMO_CONFIG_ENABLE_Pos SRSS_V3_CLK_IMO_CONFIG_ENABLE_Pos #define SRSS_CLK_DSI_SELECT_DSI_MUX_Pos SRSS_V3_CLK_DSI_SELECT_DSI_MUX_Pos #define SRSS_CLK_DSI_SELECT_DSI_MUX_Msk SRSS_V3_CLK_DSI_SELECT_DSI_MUX_Msk #define SRSS_PWR_SSV_CTL_OVDVCCD_ENABLE_Msk SRSS_V3_PWR_SSV_CTL_OVDVCCD_ENABLE_Msk #define SRSS_PWR_SSV_CTL_OVDVCCD_ENABLE_Pos SRSS_V3_PWR_SSV_CTL_OVDVCCD_ENABLE_Pos #define SRSS_CLK_PATH_SELECT_PATH_MUX_Pos SRSS_V3_CLK_PATH_SELECT_PATH_MUX_Pos #define SRSS_CLK_PATH_SELECT_PATH_MUX_Msk SRSS_V3_CLK_PATH_SELECT_PATH_MUX_Msk #define SRSS_PWR_SSV_CTL_OVDVDDD_VSEL_Msk SRSS_V3_PWR_SSV_CTL_OVDVDDD_VSEL_Msk #define SRSS_PWR_SSV_CTL_OVDVDDD_VSEL_Pos SRSS_V3_PWR_SSV_CTL_OVDVDDD_VSEL_Pos #define SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk SRSS_V3_CLK_FLL_CONFIG_FLL_ENABLE_Msk #define SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Pos SRSS_V3_CLK_FLL_CONFIG_FLL_ENABLE_Pos #define SRSS_CLK_FLL_STATUS_LOCKED_Msk SRSS_V3_CLK_FLL_STATUS_LOCKED_Msk #define SRSS_CLK_FLL_STATUS_LOCKED_Pos SRSS_V3_CLK_FLL_STATUS_LOCKED_Pos #define SRSS_CLK_FLL_CONFIG3_BYPASS_SEL_Msk SRSS_V3_CLK_FLL_CONFIG3_BYPASS_SEL_Msk #define SRSS_CLK_FLL_CONFIG3_BYPASS_SEL_Pos SRSS_V3_CLK_FLL_CONFIG3_BYPASS_SEL_Pos #define SRSS_CLK_FLL_CONFIG4_CCO_ENABLE_Msk SRSS_V3_CLK_FLL_CONFIG4_CCO_ENABLE_Msk #define SRSS_CLK_FLL_CONFIG4_CCO_ENABLE_Pos SRSS_V3_CLK_FLL_CONFIG4_CCO_ENABLE_Pos #define SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV_Msk SRSS_V3_CLK_FLL_CONFIG_FLL_OUTPUT_DIV_Msk #define SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV_Pos SRSS_V3_CLK_FLL_CONFIG_FLL_OUTPUT_DIV_Pos #define SRSS_CLK_FLL_CONFIG_FLL_MULT_Msk SRSS_V3_CLK_FLL_CONFIG_FLL_MULT_Msk #define SRSS_CLK_FLL_CONFIG_FLL_MULT_Pos SRSS_V3_CLK_FLL_CONFIG_FLL_MULT_Pos #define SRSS_CLK_FLL_CONFIG_FLL_MULT_Pos SRSS_V3_CLK_FLL_CONFIG_FLL_MULT_Pos #define SRSS_CLK_FLL_CONFIG_FLL_MULT_Msk SRSS_V3_CLK_FLL_CONFIG_FLL_MULT_Msk #define SRSS_PWR_SSV_CTL_OVDVDDA_VSEL_Msk SRSS_V3_PWR_SSV_CTL_OVDVDDA_VSEL_Msk #define SRSS_PWR_SSV_CTL_OVDVDDA_VSEL_Pos SRSS_V3_PWR_SSV_CTL_OVDVDDA_VSEL_Pos #define SRSS_PWR_SSV_CTL_OVDVDDA_VSEL_Pos SRSS_V3_PWR_SSV_CTL_OVDVDDA_VSEL_Pos #define SRSS_PWR_SSV_CTL_OVDVDDA_VSEL_Msk SRSS_V3_PWR_SSV_CTL_OVDVDDA_VSEL_Msk #define SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV_Msk SRSS_V3_CLK_FLL_CONFIG2_FLL_REF_DIV_Msk #define SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV_Pos SRSS_V3_CLK_FLL_CONFIG2_FLL_REF_DIV_Pos #define SRSS_PWR_SSV_CTL_OVDVDDA_ACTION_Msk SRSS_V3_PWR_SSV_CTL_OVDVDDA_ACTION_Msk #define SRSS_PWR_SSV_CTL_OVDVDDA_ACTION_Pos SRSS_V3_PWR_SSV_CTL_OVDVDDA_ACTION_Pos #define SRSS_CLK_FLL_CONFIG2_LOCK_TOL_Msk SRSS_V3_CLK_FLL_CONFIG2_LOCK_TOL_Msk #define SRSS_CLK_FLL_CONFIG2_LOCK_TOL_Pos SRSS_V3_CLK_FLL_CONFIG2_LOCK_TOL_Pos #define SRSS_PWR_SSV_CTL_BODVDDD_ENABLE_Msk SRSS_V3_PWR_SSV_CTL_BODVDDD_ENABLE_Msk #define SRSS_PWR_SSV_CTL_BODVDDD_ENABLE_Pos SRSS_V3_PWR_SSV_CTL_BODVDDD_ENABLE_Pos #define SRSS_PWR_SSV_CTL_BODVDDA_ENABLE_Msk SRSS_V3_PWR_SSV_CTL_BODVDDA_ENABLE_Msk #define SRSS_PWR_SSV_CTL_BODVDDA_ENABLE_Pos SRSS_V3_PWR_SSV_CTL_BODVDDA_ENABLE_Pos #define SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Msk SRSS_V3_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Msk #define SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Pos SRSS_V3_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Pos #define SRSS_PWR_SSV_CTL_BODVCCD_ENABLE_Msk SRSS_V3_PWR_SSV_CTL_BODVCCD_ENABLE_Msk #define SRSS_PWR_SSV_CTL_BODVCCD_ENABLE_Pos SRSS_V3_PWR_SSV_CTL_BODVCCD_ENABLE_Pos #define SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Msk SRSS_V3_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Msk #define SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Pos SRSS_V3_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Pos #define SRSS_PWR_SSV_CTL_BODVDDD_VSEL_Msk SRSS_V3_PWR_SSV_CTL_BODVDDD_VSEL_Msk #define SRSS_PWR_SSV_CTL_BODVDDD_VSEL_Pos SRSS_V3_PWR_SSV_CTL_BODVDDD_VSEL_Pos #define SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT_Msk SRSS_V3_CLK_FLL_CONFIG3_SETTLING_COUNT_Msk #define SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT_Pos SRSS_V3_CLK_FLL_CONFIG3_SETTLING_COUNT_Pos #define SRSS_PWR_SSV_CTL_BODVDDA_VSEL_Msk SRSS_V3_PWR_SSV_CTL_BODVDDA_VSEL_Msk #define SRSS_PWR_SSV_CTL_BODVDDA_VSEL_Pos SRSS_V3_PWR_SSV_CTL_BODVDDA_VSEL_Pos #define SRSS_CLK_FLL_CONFIG4_CCO_FREQ_Msk SRSS_V3_CLK_FLL_CONFIG4_CCO_FREQ_Msk #define SRSS_CLK_FLL_CONFIG4_CCO_FREQ_Pos SRSS_V3_CLK_FLL_CONFIG4_CCO_FREQ_Pos #define SRSS_PWR_SSV_CTL_BODVDDA_ACTION_Msk SRSS_V3_PWR_SSV_CTL_BODVDDA_ACTION_Msk #define SRSS_PWR_SSV_CTL_BODVDDA_ACTION_Pos SRSS_V3_PWR_SSV_CTL_BODVDDA_ACTION_Pos #define SRSS_CLK_FLL_CONFIG4_CCO_RANGE_Msk SRSS_V3_CLK_FLL_CONFIG4_CCO_RANGE_Msk #define SRSS_CLK_FLL_CONFIG4_CCO_RANGE_Pos SRSS_V3_CLK_FLL_CONFIG4_CCO_RANGE_Pos #define SRSS_PWR_SSV_STATUS_BODVDDD_OK_Msk SRSS_V3_PWR_SSV_STATUS_BODVDDD_OK_Msk #define SRSS_PWR_SSV_STATUS_BODVDDD_OK_Pos SRSS_V3_PWR_SSV_STATUS_BODVDDD_OK_Pos #define SRSS_PWR_SSV_STATUS_BODVDDA_OK_Msk SRSS_V3_PWR_SSV_STATUS_BODVDDA_OK_Msk #define SRSS_PWR_SSV_STATUS_BODVDDA_OK_Pos SRSS_V3_PWR_SSV_STATUS_BODVDDA_OK_Pos #define SRSS_PWR_SSV_STATUS_BODVCCD_OK_Msk SRSS_V3_PWR_SSV_STATUS_BODVCCD_OK_Msk #define SRSS_PWR_SSV_STATUS_BODVCCD_OK_Pos SRSS_V3_PWR_SSV_STATUS_BODVCCD_OK_Pos #define SRSS_CLK_FLL_STATUS_CCO_READY_Msk SRSS_V3_CLK_FLL_STATUS_CCO_READY_Msk #define SRSS_CLK_FLL_STATUS_CCO_READY_Pos SRSS_V3_CLK_FLL_STATUS_CCO_READY_Pos #define SRSS_CLK_PLL_CONFIG_ENABLE_Msk SRSS_V3_CLK_PLL_CONFIG_ENABLE_Msk #define SRSS_CLK_PLL_CONFIG_ENABLE_Pos SRSS_V3_CLK_PLL_CONFIG_ENABLE_Pos #define SRSS_CLK_PLL_STATUS_LOCKED_Msk SRSS_V3_CLK_PLL_STATUS_LOCKED_Msk #define SRSS_CLK_PLL_STATUS_LOCKED_Pos SRSS_V3_CLK_PLL_STATUS_LOCKED_Pos #define SRSS_CLK_PLL_STATUS_UNLOCK_OCCURRED_Msk SRSS_V3_CLK_PLL_STATUS_UNLOCK_OCCURRED_Msk #define SRSS_CLK_PLL_STATUS_UNLOCK_OCCURRED_Pos SRSS_V3_CLK_PLL_STATUS_UNLOCK_OCCURRED_Pos #define SRSS_CLK_PLL_CONFIG_BYPASS_SEL_Msk SRSS_V3_CLK_PLL_CONFIG_BYPASS_SEL_Msk #define SRSS_CLK_PLL_CONFIG_BYPASS_SEL_Pos SRSS_V3_CLK_PLL_CONFIG_BYPASS_SEL_Pos #define SRSS_PWR_SSV_STATUS_OVDVDDD_OK_Msk SRSS_V3_PWR_SSV_STATUS_OVDVDDD_OK_Msk #define SRSS_PWR_SSV_STATUS_OVDVDDD_OK_Pos SRSS_V3_PWR_SSV_STATUS_OVDVDDD_OK_Pos #define SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV_Pos SRSS_V3_CLK_PLL_CONFIG_FEEDBACK_DIV_Pos #define SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV_Msk SRSS_V3_CLK_PLL_CONFIG_FEEDBACK_DIV_Msk #define SRSS_PWR_SSV_STATUS_OVDVDDA_OK_Msk SRSS_V3_PWR_SSV_STATUS_OVDVDDA_OK_Msk #define SRSS_PWR_SSV_STATUS_OVDVDDA_OK_Pos SRSS_V3_PWR_SSV_STATUS_OVDVDDA_OK_Pos #define SRSS_PWR_SSV_STATUS_OVDVDDA_OK_Pos SRSS_V3_PWR_SSV_STATUS_OVDVDDA_OK_Pos #define SRSS_PWR_SSV_STATUS_OVDVDDA_OK_Msk SRSS_V3_PWR_SSV_STATUS_OVDVDDA_OK_Msk #define SRSS_PWR_SSV_STATUS_OVDVCCD_OK_Msk SRSS_V3_PWR_SSV_STATUS_OVDVCCD_OK_Msk #define SRSS_PWR_SSV_STATUS_OVDVCCD_OK_Pos SRSS_V3_PWR_SSV_STATUS_OVDVCCD_OK_Pos #define SRSS_CLK_PLL_CONFIG_REFERENCE_DIV_Pos SRSS_V3_CLK_PLL_CONFIG_REFERENCE_DIV_Pos #define SRSS_CLK_PLL_CONFIG_REFERENCE_DIV_Msk SRSS_V3_CLK_PLL_CONFIG_REFERENCE_DIV_Msk #define SRSS_PWR_CTL2_LINREG_LPMODE_Msk SRSS_V3_PWR_CTL2_LINREG_LPMODE_Msk #define SRSS_PWR_CTL2_LINREG_LPMODE_Pos SRSS_V3_PWR_CTL2_LINREG_LPMODE_Pos #define SRSS_CLK_PLL_CONFIG_OUTPUT_DIV_Pos SRSS_V3_CLK_PLL_CONFIG_OUTPUT_DIV_Pos #define SRSS_CLK_PLL_CONFIG_OUTPUT_DIV_Msk SRSS_V3_CLK_PLL_CONFIG_OUTPUT_DIV_Msk #define SRSS_PWR_CTL2_PORBOD_LPMODE_Msk SRSS_V3_PWR_CTL2_PORBOD_LPMODE_Msk #define SRSS_PWR_CTL2_PORBOD_LPMODE_Pos SRSS_V3_PWR_CTL2_PORBOD_LPMODE_Pos #define SRSS_PWR_CTL2_REFVBUF_DIS_Msk SRSS_V3_PWR_CTL2_REFVBUF_DIS_Msk #define SRSS_PWR_CTL2_REFVBUF_DIS_Pos SRSS_V3_PWR_CTL2_REFVBUF_DIS_Pos #define SRSS_PWR_CTL2_LINREG_OK_Msk SRSS_V3_PWR_CTL2_LINREG_OK_Msk #define SRSS_PWR_CTL2_LINREG_OK_Pos SRSS_V3_PWR_CTL2_LINREG_OK_Pos #define SRSS_CLK_PLL_CONFIG_PLL_LF_MODE_Pos SRSS_V3_CLK_PLL_CONFIG_PLL_LF_MODE_Pos #define SRSS_CLK_PLL_CONFIG_PLL_LF_MODE_Msk SRSS_V3_CLK_PLL_CONFIG_PLL_LF_MODE_Msk #define SRSS_PWR_REGHC_CTL_REGHC_MODE_Msk SRSS_V3_PWR_REGHC_CTL_REGHC_MODE_Msk #define SRSS_PWR_REGHC_CTL_REGHC_MODE_Pos SRSS_V3_PWR_REGHC_CTL_REGHC_MODE_Pos #define SRSS_PWR_REGHC_CTL_REGHC_MODE_Msk SRSS_V3_PWR_REGHC_CTL_REGHC_MODE_Msk #define SRSS_PWR_REGHC_CTL_REGHC_MODE_Pos SRSS_V3_PWR_REGHC_CTL_REGHC_MODE_Pos #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_DRV_VOUT_Msk SRSS_V3_PWR_REGHC_CTL_REGHC_PMIC_DRV_VOUT_Msk #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_DRV_VOUT_Pos SRSS_V3_PWR_REGHC_CTL_REGHC_PMIC_DRV_VOUT_Pos #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_DRV_VOUT_Pos SRSS_V3_PWR_REGHC_CTL_REGHC_PMIC_DRV_VOUT_Pos #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_DRV_VOUT_Msk SRSS_V3_PWR_REGHC_CTL_REGHC_PMIC_DRV_VOUT_Msk #define SRSS_PWR_REGHC_CTL_REGHC_VADJ_Msk SRSS_V3_PWR_REGHC_CTL_REGHC_VADJ_Msk #define SRSS_PWR_REGHC_CTL_REGHC_VADJ_Pos SRSS_V3_PWR_REGHC_CTL_REGHC_VADJ_Pos #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_USE_LINREG_Msk SRSS_V3_PWR_REGHC_CTL_REGHC_PMIC_USE_LINREG_Msk #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_USE_LINREG_Pos SRSS_V3_PWR_REGHC_CTL_REGHC_PMIC_USE_LINREG_Pos #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_CTL_OUTEN_Msk SRSS_V3_PWR_REGHC_CTL_REGHC_PMIC_CTL_OUTEN_Msk #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_CTL_OUTEN_Pos SRSS_V3_PWR_REGHC_CTL_REGHC_PMIC_CTL_OUTEN_Pos #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_CTL_POLARITY_Msk SRSS_V3_PWR_REGHC_CTL_REGHC_PMIC_CTL_POLARITY_Msk #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_CTL_POLARITY_Pos SRSS_V3_PWR_REGHC_CTL_REGHC_PMIC_CTL_POLARITY_Pos #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_INEN_Msk SRSS_V3_PWR_REGHC_CTL_REGHC_PMIC_STATUS_INEN_Msk #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_INEN_Pos SRSS_V3_PWR_REGHC_CTL_REGHC_PMIC_STATUS_INEN_Pos #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_POLARITY_Msk SRSS_V3_PWR_REGHC_CTL_REGHC_PMIC_STATUS_POLARITY_Msk #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_POLARITY_Pos SRSS_V3_PWR_REGHC_CTL_REGHC_PMIC_STATUS_POLARITY_Pos #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_WAIT_Msk SRSS_V3_PWR_REGHC_CTL_REGHC_PMIC_STATUS_WAIT_Msk #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_WAIT_Pos SRSS_V3_PWR_REGHC_CTL_REGHC_PMIC_STATUS_WAIT_Pos #define SRSS_PWR_REGHC_CTL_REGHC_CONFIGURED_Msk SRSS_V3_PWR_REGHC_CTL_REGHC_CONFIGURED_Msk #define SRSS_PWR_REGHC_CTL_REGHC_CONFIGURED_Pos SRSS_V3_PWR_REGHC_CTL_REGHC_CONFIGURED_Pos #define SRSS_PWR_REGHC_CTL2_REGHC_EN_Msk SRSS_V3_PWR_REGHC_CTL2_REGHC_EN_Msk #define SRSS_PWR_REGHC_CTL2_REGHC_EN_Pos SRSS_V3_PWR_REGHC_CTL2_REGHC_EN_Pos #define SRSS_PWR_REGHC_CTL2_REGHC_PMIC_STATUS_TIMEOUT_Msk SRSS_V3_PWR_REGHC_CTL2_REGHC_PMIC_STATUS_TIMEOUT_Msk #define SRSS_PWR_REGHC_CTL2_REGHC_PMIC_STATUS_TIMEOUT_Pos SRSS_V3_PWR_REGHC_CTL2_REGHC_PMIC_STATUS_TIMEOUT_Pos #define SRSS_PWR_REGHC_STATUS_REGHC_ENABLED_Msk SRSS_V3_PWR_REGHC_STATUS_REGHC_ENABLED_Msk #define SRSS_PWR_REGHC_STATUS_REGHC_ENABLED_Pos SRSS_V3_PWR_REGHC_STATUS_REGHC_ENABLED_Pos #define SRSS_PWR_REGHC_STATUS_REGHC_PMIC_STATUS_OK_Msk SRSS_V3_PWR_REGHC_STATUS_REGHC_PMIC_STATUS_OK_Msk #define SRSS_PWR_REGHC_STATUS_REGHC_PMIC_STATUS_OK_Pos SRSS_V3_PWR_REGHC_STATUS_REGHC_PMIC_STATUS_OK_Pos #define SRSS_PWR_REGHC_STATUS_REGHC_SEQ_BUSY_Msk SRSS_V3_PWR_REGHC_STATUS_REGHC_SEQ_BUSY_Msk #define SRSS_PWR_REGHC_STATUS_REGHC_SEQ_BUSY_Pos SRSS_V3_PWR_REGHC_STATUS_REGHC_SEQ_BUSY_Pos #define SRSS_PWR_REGHC_CTL4_REGHC_PMIC_VADJ_DIS_Msk SRSS_V3_PWR_REGHC_CTL4_REGHC_PMIC_VADJ_DIS_Msk #define SRSS_PWR_REGHC_CTL4_REGHC_PMIC_VADJ_DIS_Pos SRSS_V3_PWR_REGHC_CTL4_REGHC_PMIC_VADJ_DIS_Pos #define SRSS_PWR_REGHC_CTL4_REGHC_PMIC_DPSLP_Msk SRSS_V3_PWR_REGHC_CTL4_REGHC_PMIC_DPSLP_Msk #define SRSS_PWR_REGHC_CTL4_REGHC_PMIC_DPSLP_Pos SRSS_V3_PWR_REGHC_CTL4_REGHC_PMIC_DPSLP_Pos #define SRSS_PWR_REGHC_STATUS_REGHC_OCD_OK_Msk SRSS_V3_PWR_REGHC_STATUS_REGHC_OCD_OK_Msk #define SRSS_PWR_REGHC_STATUS_REGHC_OCD_OK_Pos SRSS_V3_PWR_REGHC_STATUS_REGHC_OCD_OK_Pos #define SRSS_PWR_REGHC_STATUS_REGHC_CKT_OK_Msk SRSS_V3_PWR_REGHC_STATUS_REGHC_CKT_OK_Msk #define SRSS_PWR_REGHC_STATUS_REGHC_CKT_OK_Pos SRSS_V3_PWR_REGHC_STATUS_REGHC_CKT_OK_Pos #define SRSS_CLK_PLL_CONFIG_BYPASS_SEL_Msk SRSS_V3_CLK_PLL_CONFIG_BYPASS_SEL_Msk #define SRSS_CLK_PLL_CONFIG_BYPASS_SEL_Pos SRSS_V3_CLK_PLL_CONFIG_BYPASS_SEL_Pos #define SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE_Msk SRSS_V3_CLK_CAL_CNT1_CAL_COUNTER_DONE_Msk #define SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE_Pos SRSS_V3_CLK_CAL_CNT1_CAL_COUNTER_DONE_Pos #define SRSS_CLK_CAL_CNT1_CAL_COUNTER1_Msk SRSS_V3_CLK_CAL_CNT1_CAL_COUNTER1_Msk #define SRSS_CLK_CAL_CNT1_CAL_COUNTER1_Pos SRSS_V3_CLK_CAL_CNT1_CAL_COUNTER1_Pos #define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL0_Pos SRSS_V3_CLK_OUTPUT_SLOW_SLOW_SEL0_Pos #define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL0_Msk SRSS_V3_CLK_OUTPUT_SLOW_SLOW_SEL0_Msk #define SRSS_CLK_OUTPUT_FAST_FAST_SEL0_Pos SRSS_V3_CLK_OUTPUT_FAST_FAST_SEL0_Pos #define SRSS_CLK_OUTPUT_FAST_FAST_SEL0_Msk SRSS_V3_CLK_OUTPUT_FAST_FAST_SEL0_Msk #define SRSS_CLK_OUTPUT_FAST_PATH_SEL0_Pos SRSS_V3_CLK_OUTPUT_FAST_PATH_SEL0_Pos #define SRSS_CLK_OUTPUT_FAST_PATH_SEL0_Msk SRSS_V3_CLK_OUTPUT_FAST_PATH_SEL0_Msk #define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL0_Pos SRSS_V3_CLK_OUTPUT_FAST_HFCLK_SEL0_Pos #define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL0_Msk SRSS_V3_CLK_OUTPUT_FAST_HFCLK_SEL0_Msk #define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL1_Pos SRSS_V3_CLK_OUTPUT_SLOW_SLOW_SEL1_Pos #define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL1_Msk SRSS_V3_CLK_OUTPUT_SLOW_SLOW_SEL1_Msk #define SRSS_CLK_OUTPUT_FAST_FAST_SEL1_Pos SRSS_V3_CLK_OUTPUT_FAST_FAST_SEL1_Pos #define SRSS_CLK_OUTPUT_FAST_FAST_SEL1_Msk SRSS_V3_CLK_OUTPUT_FAST_FAST_SEL1_Msk #define SRSS_CLK_OUTPUT_FAST_PATH_SEL1_Pos SRSS_V3_CLK_OUTPUT_FAST_PATH_SEL1_Pos #define SRSS_CLK_OUTPUT_FAST_PATH_SEL1_Msk SRSS_V3_CLK_OUTPUT_FAST_PATH_SEL1_Msk #define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL1_Pos SRSS_V3_CLK_OUTPUT_FAST_HFCLK_SEL1_Pos #define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL1_Msk SRSS_V3_CLK_OUTPUT_FAST_HFCLK_SEL1_Msk #define SRSS_CLK_CAL_CNT2_CAL_COUNTER2_Msk SRSS_V3_CLK_CAL_CNT2_CAL_COUNTER2_Msk #define SRSS_CLK_CAL_CNT2_CAL_COUNTER2_Pos SRSS_V3_CLK_CAL_CNT2_CAL_COUNTER2_Pos #define WDT_CTL_ENABLED_Pos WDT_V3_CTL_ENABLED_Pos #define WDT_CTL_ENABLED_Msk WDT_V3_CTL_ENABLED_Msk #define WDT_CTL_ENABLE_Pos WDT_V3_CTL_ENABLE_Pos #define WDT_CTL_ENABLE_Msk WDT_V3_CTL_ENABLE_Msk #define WDT_CNT_CNT_Msk WDT_V3_CNT_CNT_Msk #define WDT_CNT_CNT_Pos WDT_V3_CNT_CNT_Pos #define WDT_INTR_MASK_WDT_Msk WDT_V3_INTR_MASK_WDT_Msk #define WDT_INTR_WDT_Pos WDT_V3_INTR_WDT_Pos #define WDT_INTR_WDT_Msk WDT_V3_INTR_WDT_Msk #define WDT_LOCK_WDT_LOCK_Pos WDT_V3_LOCK_WDT_LOCK_Pos #define WDT_LOCK_WDT_LOCK_Msk WDT_V3_LOCK_WDT_LOCK_Msk #define WDT_CONFIG_LOWER_ACTION_Msk WDT_V3_CONFIG_LOWER_ACTION_Msk #define WDT_CONFIG_LOWER_ACTION_Pos WDT_V3_CONFIG_LOWER_ACTION_Pos #define WDT_CONFIG_UPPER_ACTION_Msk WDT_V3_CONFIG_UPPER_ACTION_Msk #define WDT_CONFIG_UPPER_ACTION_Pos WDT_V3_CONFIG_UPPER_ACTION_Pos #define WDT_CONFIG_WARN_ACTION_Msk WDT_V3_CONFIG_WARN_ACTION_Msk #define WDT_CONFIG_WARN_ACTION_Pos WDT_V3_CONFIG_WARN_ACTION_Pos #define WDT_CONFIG_AUTO_SERVICE_Msk WDT_V3_CONFIG_AUTO_SERVICE_Msk #define WDT_CONFIG_AUTO_SERVICE_Pos WDT_V3_CONFIG_AUTO_SERVICE_Pos #define WDT_CONFIG_DPSLP_PAUSE_Msk WDT_V3_CONFIG_DPSLP_PAUSE_Msk #define WDT_CONFIG_DPSLP_PAUSE_Pos WDT_V3_CONFIG_DPSLP_PAUSE_Pos #define WDT_CONFIG_HIB_PAUSE_Msk WDT_V3_CONFIG_HIB_PAUSE_Msk #define WDT_CONFIG_HIB_PAUSE_Pos WDT_V3_CONFIG_HIB_PAUSE_Pos #define WDT_CONFIG_DEBUG_RUN_Msk WDT_V3_CONFIG_DEBUG_RUN_Msk #define WDT_CONFIG_DEBUG_RUN_Pos WDT_V3_CONFIG_DEBUG_RUN_Pos #define WDT_SERVICE_SERVICE_Msk WDT_V3_SERVICE_SERVICE_Msk #define WDT_SERVICE_SERVICE_Pos WDT_V3_SERVICE_SERVICE_Pos #define MCWDT_CTR_CTL_ENABLE_Msk MCWDT_CTR_V3_CTL_ENABLE_Msk #define MCWDT_CTR_CTL_ENABLE_Pos MCWDT_CTR_V3_CTL_ENABLE_Pos #define MCWDT_CTR2_CTL_ENABLE_Msk MCWDT_V3_CTR2_CTL_ENABLE_Msk #define MCWDT_CTR2_CTL_ENABLE_Pos MCWDT_V3_CTR2_CTL_ENABLE_Pos #define MCWDT_LOCK_MCWDT_LOCK_Msk MCWDT_V3_LOCK_MCWDT_LOCK_Msk #define MCWDT_LOCK_MCWDT_LOCK_Pos MCWDT_V3_LOCK_MCWDT_LOCK_Pos #define MCWDT_CTR2_CONFIG_BITS_Msk MCWDT_V3_CTR2_CONFIG_BITS_Msk #define MCWDT_CTR2_CONFIG_BITS_Pos MCWDT_V3_CTR2_CONFIG_BITS_Pos #define MCWDT_CTR_CNT_CNT_Msk MCWDT_CTR_V3_CNT_CNT_Msk #define MCWDT_CTR_CNT_CNT_Pos MCWDT_CTR_V3_CNT_CNT_Pos #define MCWDT_CTR2_CNT_CNT2_Msk MCWDT_V3_CTR2_CNT_CNT2_Msk #define MCWDT_CTR2_CNT_CNT2_Pos MCWDT_V3_CTR2_CNT_CNT2_Pos #define MCWDT_SERVICE_CTR0_SERVICE_Msk MCWDT_V3_SERVICE_CTR0_SERVICE_Msk #define MCWDT_SERVICE_CTR0_SERVICE_Pos MCWDT_V3_SERVICE_CTR0_SERVICE_Pos #define MCWDT_SERVICE_CTR1_SERVICE_Msk MCWDT_V3_SERVICE_CTR1_SERVICE_Msk #define MCWDT_SERVICE_CTR1_SERVICE_Pos MCWDT_V3_SERVICE_CTR1_SERVICE_Pos #define MCWDT_CTR_CONFIG_LOWER_ACTION_Pos MCWDT_CTR_V3_CONFIG_LOWER_ACTION_Pos #define MCWDT_CTR_CONFIG_LOWER_ACTION_Msk MCWDT_CTR_V3_CONFIG_LOWER_ACTION_Msk #define MCWDT_CTR_CONFIG_UPPER_ACTION_Pos MCWDT_CTR_V3_CONFIG_UPPER_ACTION_Pos #define MCWDT_CTR_CONFIG_UPPER_ACTION_Msk MCWDT_CTR_V3_CONFIG_UPPER_ACTION_Msk #define MCWDT_CTR_CONFIG_WARN_ACTION_Pos MCWDT_CTR_V3_CONFIG_WARN_ACTION_Pos #define MCWDT_CTR_CONFIG_WARN_ACTION_Msk MCWDT_CTR_V3_CONFIG_WARN_ACTION_Msk #define MCWDT_CTR_CONFIG_AUTO_SERVICE_Pos MCWDT_CTR_V3_CONFIG_AUTO_SERVICE_Pos #define MCWDT_CTR_CONFIG_AUTO_SERVICE_Msk MCWDT_CTR_V3_CONFIG_AUTO_SERVICE_Msk #define MCWDT_CTR_CONFIG_SLEEPDEEP_PAUSE_Pos MCWDT_CTR_V3_CONFIG_SLEEPDEEP_PAUSE_Pos #define MCWDT_CTR_CONFIG_SLEEPDEEP_PAUSE_Msk MCWDT_CTR_V3_CONFIG_SLEEPDEEP_PAUSE_Msk #define MCWDT_CTR_CONFIG_DEBUG_RUN_Pos MCWDT_CTR_V3_CONFIG_DEBUG_RUN_Pos #define MCWDT_CTR_CONFIG_DEBUG_RUN_Msk MCWDT_CTR_V3_CONFIG_DEBUG_RUN_Msk #define MCWDT_CTR2_CONFIG_ACTION_Pos MCWDT_V3_CTR2_CONFIG_ACTION_Pos #define MCWDT_CTR2_CONFIG_ACTION_Msk MCWDT_V3_CTR2_CONFIG_ACTION_Msk #define MCWDT_CTR2_CONFIG_SLEEPDEEP_PAUSE_Pos MCWDT_V3_CTR2_CONFIG_SLEEPDEEP_PAUSE_Pos #define MCWDT_CTR2_CONFIG_SLEEPDEEP_PAUSE_Msk MCWDT_V3_CTR2_CONFIG_SLEEPDEEP_PAUSE_Msk #define MCWDT_CTR2_CONFIG_DEBUG_RUN_Pos MCWDT_V3_CTR2_CONFIG_DEBUG_RUN_Pos #define MCWDT_CTR2_CONFIG_DEBUG_RUN_Msk MCWDT_V3_CTR2_CONFIG_DEBUG_RUN_Msk #define MCWDT_CPU_SELECT_CPU_SEL_Msk MCWDT_V3_CPU_SELECT_CPU_SEL_Msk #define MCWDT_CPU_SELECT_CPU_SEL_Pos MCWDT_V3_CPU_SELECT_CPU_SEL_Pos #define MCWDT_CTR_LOWER_LIMIT_LOWER_LIMIT_Msk MCWDT_CTR_V3_LOWER_LIMIT_LOWER_LIMIT_Msk #define MCWDT_CTR_LOWER_LIMIT_LOWER_LIMIT_Pos MCWDT_CTR_V3_LOWER_LIMIT_LOWER_LIMIT_Pos #define MCWDT_CTR_UPPER_LIMIT_UPPER_LIMIT_Msk MCWDT_CTR_V3_UPPER_LIMIT_UPPER_LIMIT_Msk #define MCWDT_CTR_UPPER_LIMIT_UPPER_LIMIT_Pos MCWDT_CTR_V3_UPPER_LIMIT_UPPER_LIMIT_Pos #define MCWDT_CTR_WARN_LIMIT_WARN_LIMIT_Msk MCWDT_CTR_V3_WARN_LIMIT_WARN_LIMIT_Msk #define MCWDT_CTR_WARN_LIMIT_WARN_LIMIT_Pos MCWDT_CTR_V3_WARN_LIMIT_WARN_LIMIT_Pos #define MCWDT_INTR_MASKED_CTR0_INT_Msk MCWDT_V3_INTR_MASKED_CTR0_INT_Msk #define MCWDT_INTR_MASKED_CTR1_INT_Msk MCWDT_V3_INTR_MASKED_CTR1_INT_Msk #define MCWDT_INTR_MASKED_CTR2_INT_Msk MCWDT_V3_INTR_MASKED_CTR2_INT_Msk /******************************************************************************* * BACKUP *******************************************************************************/ /* BACKUP.CTL */ #define BACKUP_CTL_WCO_EN_Pos BACKUP_V3_CTL_WCO_EN_Pos #define BACKUP_CTL_WCO_EN_Msk BACKUP_V3_CTL_WCO_EN_Msk #define BACKUP_CTL_CLK_SEL_Pos BACKUP_V3_CTL_CLK_SEL_Pos #define BACKUP_CTL_CLK_SEL_Msk BACKUP_V3_CTL_CLK_SEL_Msk #define BACKUP_CTL_PRESCALER_Pos BACKUP_V3_CTL_PRESCALER_Pos #define BACKUP_CTL_PRESCALER_Msk BACKUP_V3_CTL_PRESCALER_Msk #define BACKUP_CTL_WCO_BYPASS_Pos BACKUP_V3_CTL_WCO_BYPASS_Pos #define BACKUP_CTL_WCO_BYPASS_Msk BACKUP_V3_CTL_WCO_BYPASS_Msk #define BACKUP_CTL_VDDBAK_CTL_Pos BACKUP_V3_CTL_VDDBAK_CTL_Pos #define BACKUP_CTL_VDDBAK_CTL_Msk BACKUP_V3_CTL_VDDBAK_CTL_Msk #define BACKUP_CTL_VBACKUP_MEAS_Pos BACKUP_V3_CTL_VBACKUP_MEAS_Pos #define BACKUP_CTL_VBACKUP_MEAS_Msk BACKUP_V3_CTL_VBACKUP_MEAS_Msk #define BACKUP_CTL_EN_CHARGE_KEY_Pos BACKUP_V3_CTL_EN_CHARGE_KEY_Pos #define BACKUP_CTL_EN_CHARGE_KEY_Msk BACKUP_V3_CTL_EN_CHARGE_KEY_Msk /* BACKUP.RTC_RW */ #define BACKUP_RTC_RW_READ_Pos BACKUP_V3_RTC_RW_READ_Pos #define BACKUP_RTC_RW_READ_Msk BACKUP_V3_RTC_RW_READ_Msk #define BACKUP_RTC_RW_WRITE_Pos BACKUP_V3_RTC_RW_WRITE_Pos #define BACKUP_RTC_RW_WRITE_Msk BACKUP_V3_RTC_RW_WRITE_Msk /* BACKUP.CAL_CTL */ #define BACKUP_CAL_CTL_CALIB_VAL_Pos BACKUP_V3_CAL_CTL_CALIB_VAL_Pos #define BACKUP_CAL_CTL_CALIB_VAL_Msk BACKUP_V3_CAL_CTL_CALIB_VAL_Msk #define BACKUP_CAL_CTL_CALIB_SIGN_Pos BACKUP_V3_CAL_CTL_CALIB_SIGN_Pos #define BACKUP_CAL_CTL_CALIB_SIGN_Msk BACKUP_V3_CAL_CTL_CALIB_SIGN_Msk #define BACKUP_CAL_CTL_CAL_SEL_Pos BACKUP_V3_CAL_CTL_CAL_SEL_Pos #define BACKUP_CAL_CTL_CAL_SEL_Msk BACKUP_V3_CAL_CTL_CAL_SEL_Msk #define BACKUP_CAL_CTL_CAL_OUT_Pos BACKUP_V3_CAL_CTL_CAL_OUT_Pos #define BACKUP_CAL_CTL_CAL_OUT_Msk BACKUP_V3_CAL_CTL_CAL_OUT_Msk /* BACKUP.STATUS */ #define BACKUP_STATUS_RTC_BUSY_Pos BACKUP_V3_STATUS_RTC_BUSY_Pos #define BACKUP_STATUS_RTC_BUSY_Msk BACKUP_V3_STATUS_RTC_BUSY_Msk #define BACKUP_STATUS_WCO_OK_Pos BACKUP_V3_STATUS_WCO_OK_Pos #define BACKUP_STATUS_WCO_OK_Msk BACKUP_V3_STATUS_WCO_OK_Msk /* BACKUP.RTC_TIME */ #define BACKUP_RTC_TIME_RTC_SEC_Pos BACKUP_V3_RTC_TIME_RTC_SEC_Pos #define BACKUP_RTC_TIME_RTC_SEC_Msk BACKUP_V3_RTC_TIME_RTC_SEC_Msk #define BACKUP_RTC_TIME_RTC_MIN_Pos BACKUP_V3_RTC_TIME_RTC_MIN_Pos #define BACKUP_RTC_TIME_RTC_MIN_Msk BACKUP_V3_RTC_TIME_RTC_MIN_Msk #define BACKUP_RTC_TIME_RTC_HOUR_Pos BACKUP_V3_RTC_TIME_RTC_HOUR_Pos #define BACKUP_RTC_TIME_RTC_HOUR_Msk BACKUP_V3_RTC_TIME_RTC_HOUR_Msk #define BACKUP_RTC_TIME_CTRL_12HR_Pos BACKUP_V3_RTC_TIME_CTRL_12HR_Pos #define BACKUP_RTC_TIME_CTRL_12HR_Msk BACKUP_V3_RTC_TIME_CTRL_12HR_Msk #define BACKUP_RTC_TIME_RTC_DAY_Pos BACKUP_V3_RTC_TIME_RTC_DAY_Pos #define BACKUP_RTC_TIME_RTC_DAY_Msk BACKUP_V3_RTC_TIME_RTC_DAY_Msk /* BACKUP.RTC_DATE */ #define BACKUP_RTC_DATE_RTC_DATE_Pos BACKUP_V3_RTC_DATE_RTC_DATE_Pos #define BACKUP_RTC_DATE_RTC_DATE_Msk BACKUP_V3_RTC_DATE_RTC_DATE_Msk #define BACKUP_RTC_DATE_RTC_MON_Pos BACKUP_V3_RTC_DATE_RTC_MON_Pos #define BACKUP_RTC_DATE_RTC_MON_Msk BACKUP_V3_RTC_DATE_RTC_MON_Msk #define BACKUP_RTC_DATE_RTC_YEAR_Pos BACKUP_V3_RTC_DATE_RTC_YEAR_Pos #define BACKUP_RTC_DATE_RTC_YEAR_Msk BACKUP_V3_RTC_DATE_RTC_YEAR_Msk /* BACKUP.ALM1_TIME */ #define BACKUP_ALM1_TIME_ALM_SEC_Pos BACKUP_V3_ALM1_TIME_ALM_SEC_Pos #define BACKUP_ALM1_TIME_ALM_SEC_Msk BACKUP_V3_ALM1_TIME_ALM_SEC_Msk #define BACKUP_ALM1_TIME_ALM_SEC_EN_Pos BACKUP_V3_ALM1_TIME_ALM_SEC_EN_Pos #define BACKUP_ALM1_TIME_ALM_SEC_EN_Msk BACKUP_V3_ALM1_TIME_ALM_SEC_EN_Msk #define BACKUP_ALM1_TIME_ALM_MIN_Pos BACKUP_V3_ALM1_TIME_ALM_MIN_Pos #define BACKUP_ALM1_TIME_ALM_MIN_Msk BACKUP_V3_ALM1_TIME_ALM_MIN_Msk #define BACKUP_ALM1_TIME_ALM_MIN_EN_Pos BACKUP_V3_ALM1_TIME_ALM_MIN_EN_Pos #define BACKUP_ALM1_TIME_ALM_MIN_EN_Msk BACKUP_V3_ALM1_TIME_ALM_MIN_EN_Msk #define BACKUP_ALM1_TIME_ALM_HOUR_Pos BACKUP_V3_ALM1_TIME_ALM_HOUR_Pos #define BACKUP_ALM1_TIME_ALM_HOUR_Msk BACKUP_V3_ALM1_TIME_ALM_HOUR_Msk #define BACKUP_ALM1_TIME_ALM_HOUR_EN_Pos BACKUP_V3_ALM1_TIME_ALM_HOUR_EN_Pos #define BACKUP_ALM1_TIME_ALM_HOUR_EN_Msk BACKUP_V3_ALM1_TIME_ALM_HOUR_EN_Msk #define BACKUP_ALM1_TIME_ALM_DAY_Pos BACKUP_V3_ALM1_TIME_ALM_DAY_Pos #define BACKUP_ALM1_TIME_ALM_DAY_Msk BACKUP_V3_ALM1_TIME_ALM_DAY_Msk #define BACKUP_ALM1_TIME_ALM_DAY_EN_Pos BACKUP_V3_ALM1_TIME_ALM_DAY_EN_Pos #define BACKUP_ALM1_TIME_ALM_DAY_EN_Msk BACKUP_V3_ALM1_TIME_ALM_DAY_EN_Msk /* BACKUP.ALM1_DATE */ #define BACKUP_ALM1_DATE_ALM_DATE_Pos BACKUP_V3_ALM1_DATE_ALM_DATE_Pos #define BACKUP_ALM1_DATE_ALM_DATE_Msk BACKUP_V3_ALM1_DATE_ALM_DATE_Msk #define BACKUP_ALM1_DATE_ALM_DATE_EN_Pos BACKUP_V3_ALM1_DATE_ALM_DATE_EN_Pos #define BACKUP_ALM1_DATE_ALM_DATE_EN_Msk BACKUP_V3_ALM1_DATE_ALM_DATE_EN_Msk #define BACKUP_ALM1_DATE_ALM_MON_Pos BACKUP_V3_ALM1_DATE_ALM_MON_Pos #define BACKUP_ALM1_DATE_ALM_MON_Msk BACKUP_V3_ALM1_DATE_ALM_MON_Msk #define BACKUP_ALM1_DATE_ALM_MON_EN_Pos BACKUP_V3_ALM1_DATE_ALM_MON_EN_Pos #define BACKUP_ALM1_DATE_ALM_MON_EN_Msk BACKUP_V3_ALM1_DATE_ALM_MON_EN_Msk #define BACKUP_ALM1_DATE_ALM_EN_Pos BACKUP_V3_ALM1_DATE_ALM_EN_Pos #define BACKUP_ALM1_DATE_ALM_EN_Msk BACKUP_V3_ALM1_DATE_ALM_EN_Msk /* BACKUP.ALM2_TIME */ #define BACKUP_ALM2_TIME_ALM_SEC_Pos BACKUP_V3_ALM2_TIME_ALM_SEC_Pos #define BACKUP_ALM2_TIME_ALM_SEC_Msk BACKUP_V3_ALM2_TIME_ALM_SEC_Msk #define BACKUP_ALM2_TIME_ALM_SEC_EN_Pos BACKUP_V3_ALM2_TIME_ALM_SEC_EN_Pos #define BACKUP_ALM2_TIME_ALM_SEC_EN_Msk BACKUP_V3_ALM2_TIME_ALM_SEC_EN_Msk #define BACKUP_ALM2_TIME_ALM_MIN_Pos BACKUP_V3_ALM2_TIME_ALM_MIN_Pos #define BACKUP_ALM2_TIME_ALM_MIN_Msk BACKUP_V3_ALM2_TIME_ALM_MIN_Msk #define BACKUP_ALM2_TIME_ALM_MIN_EN_Pos BACKUP_V3_ALM2_TIME_ALM_MIN_EN_Pos #define BACKUP_ALM2_TIME_ALM_MIN_EN_Msk BACKUP_V3_ALM2_TIME_ALM_MIN_EN_Msk #define BACKUP_ALM2_TIME_ALM_HOUR_Pos BACKUP_V3_ALM2_TIME_ALM_HOUR_Pos #define BACKUP_ALM2_TIME_ALM_HOUR_Msk BACKUP_V3_ALM2_TIME_ALM_HOUR_Msk #define BACKUP_ALM2_TIME_ALM_HOUR_EN_Pos BACKUP_V3_ALM2_TIME_ALM_HOUR_EN_Pos #define BACKUP_ALM2_TIME_ALM_HOUR_EN_Msk BACKUP_V3_ALM2_TIME_ALM_HOUR_EN_Msk #define BACKUP_ALM2_TIME_ALM_DAY_Pos BACKUP_V3_ALM2_TIME_ALM_DAY_Pos #define BACKUP_ALM2_TIME_ALM_DAY_Msk BACKUP_V3_ALM2_TIME_ALM_DAY_Msk #define BACKUP_ALM2_TIME_ALM_DAY_EN_Pos BACKUP_V3_ALM2_TIME_ALM_DAY_EN_Pos #define BACKUP_ALM2_TIME_ALM_DAY_EN_Msk BACKUP_V3_ALM2_TIME_ALM_DAY_EN_Msk /* BACKUP.ALM2_DATE */ #define BACKUP_ALM2_DATE_ALM_DATE_Pos BACKUP_V3_ALM2_DATE_ALM_DATE_Pos #define BACKUP_ALM2_DATE_ALM_DATE_Msk BACKUP_V3_ALM2_DATE_ALM_DATE_Msk #define BACKUP_ALM2_DATE_ALM_DATE_EN_Pos BACKUP_V3_ALM2_DATE_ALM_DATE_EN_Pos #define BACKUP_ALM2_DATE_ALM_DATE_EN_Msk BACKUP_V3_ALM2_DATE_ALM_DATE_EN_Msk #define BACKUP_ALM2_DATE_ALM_MON_Pos BACKUP_V3_ALM2_DATE_ALM_MON_Pos #define BACKUP_ALM2_DATE_ALM_MON_Msk BACKUP_V3_ALM2_DATE_ALM_MON_Msk #define BACKUP_ALM2_DATE_ALM_MON_EN_Pos BACKUP_V3_ALM2_DATE_ALM_MON_EN_Pos #define BACKUP_ALM2_DATE_ALM_MON_EN_Msk BACKUP_V3_ALM2_DATE_ALM_MON_EN_Msk #define BACKUP_ALM2_DATE_ALM_EN_Pos BACKUP_V3_ALM2_DATE_ALM_EN_Pos #define BACKUP_ALM2_DATE_ALM_EN_Msk BACKUP_V3_ALM2_DATE_ALM_EN_Msk /* BACKUP.INTR */ #define BACKUP_INTR_ALARM1_Pos BACKUP_V3_INTR_ALARM1_Pos #define BACKUP_INTR_ALARM1_Msk BACKUP_V3_INTR_ALARM1_Msk #define BACKUP_INTR_ALARM2_Pos BACKUP_V3_INTR_ALARM2_Pos #define BACKUP_INTR_ALARM2_Msk BACKUP_V3_INTR_ALARM2_Msk #define BACKUP_INTR_CENTURY_Pos BACKUP_V3_INTR_CENTURY_Pos #define BACKUP_INTR_CENTURY_Msk BACKUP_V3_INTR_CENTURY_Msk /* BACKUP.INTR_SET */ #define BACKUP_INTR_SET_ALARM1_Pos BACKUP_V3_INTR_SET_ALARM1_Pos #define BACKUP_INTR_SET_ALARM1_Msk BACKUP_V3_INTR_SET_ALARM1_Msk #define BACKUP_INTR_SET_ALARM2_Pos BACKUP_V3_INTR_SET_ALARM2_Pos #define BACKUP_INTR_SET_ALARM2_Msk BACKUP_V3_INTR_SET_ALARM2_Msk #define BACKUP_INTR_SET_CENTURY_Pos BACKUP_V3_INTR_SET_CENTURY_Pos #define BACKUP_INTR_SET_CENTURY_Msk BACKUP_V3_INTR_SET_CENTURY_Msk /* BACKUP.INTR_MASK */ #define BACKUP_INTR_MASK_ALARM1_Pos BACKUP_V3_INTR_MASK_ALARM1_Pos #define BACKUP_INTR_MASK_ALARM1_Msk BACKUP_V3_INTR_MASK_ALARM1_Msk #define BACKUP_INTR_MASK_ALARM2_Pos BACKUP_V3_INTR_MASK_ALARM2_Pos #define BACKUP_INTR_MASK_ALARM2_Msk BACKUP_V3_INTR_MASK_ALARM2_Msk #define BACKUP_INTR_MASK_CENTURY_Pos BACKUP_V3_INTR_MASK_CENTURY_Pos #define BACKUP_INTR_MASK_CENTURY_Msk BACKUP_V3_INTR_MASK_CENTURY_Msk /* BACKUP.INTR_MASKED */ #define BACKUP_INTR_MASKED_ALARM1_Pos BACKUP_V3_INTR_MASKED_ALARM1_Pos #define BACKUP_INTR_MASKED_ALARM1_Msk BACKUP_V3_INTR_MASKED_ALARM1_Msk #define BACKUP_INTR_MASKED_ALARM2_Pos BACKUP_V3_INTR_MASKED_ALARM2_Pos #define BACKUP_INTR_MASKED_ALARM2_Msk BACKUP_V3_INTR_MASKED_ALARM2_Msk #define BACKUP_INTR_MASKED_CENTURY_Pos BACKUP_V3_INTR_MASKED_CENTURY_Pos #define BACKUP_INTR_MASKED_CENTURY_Msk BACKUP_V3_INTR_MASKED_CENTURY_Msk /* BACKUP.PMIC_CTL */ #define BACKUP_PMIC_CTL_UNLOCK_Pos BACKUP_V3_PMIC_CTL_UNLOCK_Pos #define BACKUP_PMIC_CTL_UNLOCK_Msk BACKUP_V3_PMIC_CTL_UNLOCK_Msk #define BACKUP_PMIC_CTL_POLARITY_Pos BACKUP_V3_PMIC_CTL_POLARITY_Pos #define BACKUP_PMIC_CTL_POLARITY_Msk BACKUP_V3_PMIC_CTL_POLARITY_Msk #define BACKUP_PMIC_CTL_PMIC_EN_OUTEN_Pos BACKUP_V3_PMIC_CTL_PMIC_EN_OUTEN_Pos #define BACKUP_PMIC_CTL_PMIC_EN_OUTEN_Msk BACKUP_V3_PMIC_CTL_PMIC_EN_OUTEN_Msk #define BACKUP_PMIC_CTL_PMIC_ALWAYSEN_Pos BACKUP_V3_PMIC_CTL_PMIC_ALWAYSEN_Pos #define BACKUP_PMIC_CTL_PMIC_ALWAYSEN_Msk BACKUP_V3_PMIC_CTL_PMIC_ALWAYSEN_Msk #define BACKUP_PMIC_CTL_PMIC_EN_Pos BACKUP_V3_PMIC_CTL_PMIC_EN_Pos #define BACKUP_PMIC_CTL_PMIC_EN_Msk BACKUP_V3_PMIC_CTL_PMIC_EN_Msk /* BACKUP.RESET */ #define BACKUP_RESET_RESET_Pos BACKUP_V3_RESET_RESET_Pos #define BACKUP_RESET_RESET_Msk BACKUP_V3_RESET_RESET_Msk /* BACKUP.LPECO_CTL */ #define BACKUP_LPECO_CTL_LPECO_CRANGE_Pos BACKUP_V3_LPECO_CTL_LPECO_CRANGE_Pos #define BACKUP_LPECO_CTL_LPECO_CRANGE_Msk BACKUP_V3_LPECO_CTL_LPECO_CRANGE_Msk #define BACKUP_LPECO_CTL_LPECO_FRANGE_Pos BACKUP_V3_LPECO_CTL_LPECO_FRANGE_Pos #define BACKUP_LPECO_CTL_LPECO_FRANGE_Msk BACKUP_V3_LPECO_CTL_LPECO_FRANGE_Msk #define BACKUP_LPECO_CTL_LPECO_AMP_SEL_Pos BACKUP_V3_LPECO_CTL_LPECO_AMP_SEL_Pos #define BACKUP_LPECO_CTL_LPECO_AMP_SEL_Msk BACKUP_V3_LPECO_CTL_LPECO_AMP_SEL_Msk #define BACKUP_LPECO_CTL_LPECO_DIV_ENABLE_Pos BACKUP_V3_LPECO_CTL_LPECO_DIV_ENABLE_Pos #define BACKUP_LPECO_CTL_LPECO_DIV_ENABLE_Msk BACKUP_V3_LPECO_CTL_LPECO_DIV_ENABLE_Msk #define BACKUP_LPECO_CTL_LPECO_AMPDET_EN_Pos BACKUP_V3_LPECO_CTL_LPECO_AMPDET_EN_Pos #define BACKUP_LPECO_CTL_LPECO_AMPDET_EN_Msk BACKUP_V3_LPECO_CTL_LPECO_AMPDET_EN_Msk #define BACKUP_LPECO_CTL_LPECO_EN_Pos BACKUP_V3_LPECO_CTL_LPECO_EN_Pos #define BACKUP_LPECO_CTL_LPECO_EN_Msk BACKUP_V3_LPECO_CTL_LPECO_EN_Msk /* BACKUP.LPECO_PRESCALE */ #define BACKUP_LPECO_PRESCALE_LPECO_DIV_ENABLED_Pos BACKUP_V3_LPECO_PRESCALE_LPECO_DIV_ENABLED_Pos #define BACKUP_LPECO_PRESCALE_LPECO_DIV_ENABLED_Msk BACKUP_V3_LPECO_PRESCALE_LPECO_DIV_ENABLED_Msk #define BACKUP_LPECO_PRESCALE_LPECO_FRAC_DIV_Pos BACKUP_V3_LPECO_PRESCALE_LPECO_FRAC_DIV_Pos #define BACKUP_LPECO_PRESCALE_LPECO_FRAC_DIV_Msk BACKUP_V3_LPECO_PRESCALE_LPECO_FRAC_DIV_Msk #define BACKUP_LPECO_PRESCALE_LPECO_INT_DIV_Pos BACKUP_V3_LPECO_PRESCALE_LPECO_INT_DIV_Pos #define BACKUP_LPECO_PRESCALE_LPECO_INT_DIV_Msk BACKUP_V3_LPECO_PRESCALE_LPECO_INT_DIV_Msk /* BACKUP.LPECO_STATUS */ #define BACKUP_LPECO_STATUS_LPECO_AMPDET_OK_Pos BACKUP_V3_LPECO_STATUS_LPECO_AMPDET_OK_Pos #define BACKUP_LPECO_STATUS_LPECO_AMPDET_OK_Msk BACKUP_V3_LPECO_STATUS_LPECO_AMPDET_OK_Msk #define BACKUP_LPECO_STATUS_LPECO_READY_Pos BACKUP_V3_LPECO_STATUS_LPECO_READY_Pos #define BACKUP_LPECO_STATUS_LPECO_READY_Msk BACKUP_V3_LPECO_STATUS_LPECO_READY_Msk /* BACKUP.BREG */ #define BACKUP_BREG_BREG_Pos BACKUP_V3_BREG_BREG_Pos #define BACKUP_BREG_BREG_Msk BACKUP_V3_BREG_BREG_Msk #endif /* CY_DEVICE_TVIIBE type */ /******************************************************************************* * CPUSS *******************************************************************************/ typedef struct { __IOM uint32_t CM0_CTL; /*!< 0x00000000 CM0+ control */ __IM uint32_t RESERVED; __IM uint32_t CM0_STATUS; /*!< 0x00000008 CM0+ status */ __IM uint32_t RESERVED1; __IOM uint32_t CM0_CLOCK_CTL; /*!< 0x00000010 CM0+ clock control */ __IM uint32_t RESERVED2[3]; __IOM uint32_t CM0_INT_CTL0; /*!< 0x00000020 CM0+ interrupt control 0 */ __IOM uint32_t CM0_INT_CTL1; /*!< 0x00000024 CM0+ interrupt control 1 */ __IOM uint32_t CM0_INT_CTL2; /*!< 0x00000028 CM0+ interrupt control 2 */ __IOM uint32_t CM0_INT_CTL3; /*!< 0x0000002C CM0+ interrupt control 3 */ __IOM uint32_t CM0_INT_CTL4; /*!< 0x00000030 CM0+ interrupt control 4 */ __IOM uint32_t CM0_INT_CTL5; /*!< 0x00000034 CM0+ interrupt control 5 */ __IOM uint32_t CM0_INT_CTL6; /*!< 0x00000038 CM0+ interrupt control 6 */ __IOM uint32_t CM0_INT_CTL7; /*!< 0x0000003C CM0+ interrupt control 7 */ __IM uint32_t RESERVED3[16]; __IOM uint32_t CM4_PWR_CTL; /*!< 0x00000080 CM4 power control */ __IOM uint32_t CM4_PWR_DELAY_CTL; /*!< 0x00000084 CM4 power control */ __IM uint32_t CM4_STATUS; /*!< 0x00000088 CM4 status */ __IM uint32_t RESERVED4; __IOM uint32_t CM4_CLOCK_CTL; /*!< 0x00000090 CM4 clock control */ __IM uint32_t RESERVED5[3]; __IOM uint32_t CM4_NMI_CTL; /*!< 0x000000A0 CM4 NMI control */ __IM uint32_t RESERVED6[23]; __IOM uint32_t RAM0_CTL0; /*!< 0x00000100 RAM 0 control 0 */ __IM uint32_t RESERVED7[15]; __IOM uint32_t RAM0_PWR_MACRO_CTL[16]; /*!< 0x00000140 RAM 0 power control */ __IOM uint32_t RAM1_CTL0; /*!< 0x00000180 RAM 1 control 0 */ __IM uint32_t RESERVED8[3]; __IOM uint32_t RAM1_PWR_CTL; /*!< 0x00000190 RAM1 power control */ __IM uint32_t RESERVED9[3]; __IOM uint32_t RAM2_CTL0; /*!< 0x000001A0 RAM 2 control 0 */ __IM uint32_t RESERVED10[3]; __IOM uint32_t RAM2_PWR_CTL; /*!< 0x000001B0 RAM2 power control */ __IM uint32_t RESERVED11[3]; __IOM uint32_t RAM_PWR_DELAY_CTL; /*!< 0x000001C0 Power up delay used for all SRAM power domains */ __IM uint32_t RESERVED12[3]; __IOM uint32_t ROM_CTL; /*!< 0x000001D0 ROM control */ __IM uint32_t RESERVED13[7]; __IOM uint32_t UDB_PWR_CTL; /*!< 0x000001F0 UDB power control */ __IOM uint32_t UDB_PWR_DELAY_CTL; /*!< 0x000001F4 UDB power control */ __IM uint32_t RESERVED14[4]; __IM uint32_t DP_STATUS; /*!< 0x00000208 Debug port status */ __IM uint32_t RESERVED15[5]; __IOM uint32_t BUFF_CTL; /*!< 0x00000220 Buffer control */ __IM uint32_t RESERVED16[3]; __IOM uint32_t DDFT_CTL; /*!< 0x00000230 DDFT control */ __IM uint32_t RESERVED17[3]; __IOM uint32_t SYSTICK_CTL; /*!< 0x00000240 SysTick timer control */ __IM uint32_t RESERVED18[27]; __IOM uint32_t CM0_VECTOR_TABLE_BASE; /*!< 0x000002B0 CM0+ vector table base */ __IM uint32_t RESERVED19[3]; __IOM uint32_t CM4_VECTOR_TABLE_BASE; /*!< 0x000002C0 CM4 vector table base */ __IM uint32_t RESERVED20[23]; __IOM uint32_t CM0_PC0_HANDLER; /*!< 0x00000320 CM0+ protection context 0 handler */ __IM uint32_t RESERVED21[55]; __IM uint32_t IDENTITY; /*!< 0x00000400 Identity */ __IM uint32_t RESERVED22[63]; __IOM uint32_t PROTECTION; /*!< 0x00000500 Protection status */ __IM uint32_t RESERVED23[7]; __IOM uint32_t CM0_NMI_CTL; /*!< 0x00000520 CM0+ NMI control */ __IM uint32_t RESERVED24[7]; __IOM uint32_t AP_CTL; /*!< 0x00000540 Access port control */ __IM uint32_t RESERVED25[23]; __IM uint32_t MBIST_STAT; /*!< 0x000005A0 Memory BIST status */ __IM uint32_t RESERVED26[14999]; __IOM uint32_t TRIM_ROM_CTL; /*!< 0x0000F000 ROM trim control */ __IOM uint32_t TRIM_RAM_CTL; /*!< 0x0000F004 RAM trim control */ } CPUSS_V1_Type; /*!< Size = 61448 (0xF008) */ /* CPUSS.IDENTITY */ #define CPUSS_IDENTITY_P_Pos CPUSS_V2_IDENTITY_P_Pos #define CPUSS_IDENTITY_P_Msk CPUSS_V2_IDENTITY_P_Msk #define CPUSS_IDENTITY_NS_Pos CPUSS_V2_IDENTITY_NS_Pos #define CPUSS_IDENTITY_NS_Msk CPUSS_V2_IDENTITY_NS_Msk #define CPUSS_IDENTITY_PC_Pos CPUSS_V2_IDENTITY_PC_Pos #define CPUSS_IDENTITY_PC_Msk CPUSS_V2_IDENTITY_PC_Msk #define CPUSS_IDENTITY_MS_Pos CPUSS_V2_IDENTITY_MS_Pos #define CPUSS_IDENTITY_MS_Msk CPUSS_V2_IDENTITY_MS_Msk /* CPUSS.CM4_STATUS */ #define CPUSS_CM4_STATUS_SLEEPING_Pos CPUSS_V2_CM4_STATUS_SLEEPING_Pos #define CPUSS_CM4_STATUS_SLEEPING_Msk CPUSS_V2_CM4_STATUS_SLEEPING_Msk #define CPUSS_CM4_STATUS_SLEEPDEEP_Pos CPUSS_V2_CM4_STATUS_SLEEPDEEP_Pos #define CPUSS_CM4_STATUS_SLEEPDEEP_Msk CPUSS_V2_CM4_STATUS_SLEEPDEEP_Msk #define CPUSS_CM4_STATUS_PWR_DONE_Pos CPUSS_V2_CM4_STATUS_PWR_DONE_Pos #define CPUSS_CM4_STATUS_PWR_DONE_Msk CPUSS_V2_CM4_STATUS_PWR_DONE_Msk /* CPUSS.CM4_CLOCK_CTL */ #define CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV_Pos CPUSS_V2_CM4_CLOCK_CTL_FAST_INT_DIV_Pos #define CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV_Msk CPUSS_V2_CM4_CLOCK_CTL_FAST_INT_DIV_Msk /* CPUSS.CM4_CTL */ #define CPUSS_CM4_CTL_IOC_MASK_Pos CPUSS_V2_CM4_CTL_IOC_MASK_Pos #define CPUSS_CM4_CTL_IOC_MASK_Msk CPUSS_V2_CM4_CTL_IOC_MASK_Msk #define CPUSS_CM4_CTL_DZC_MASK_Pos CPUSS_V2_CM4_CTL_DZC_MASK_Pos #define CPUSS_CM4_CTL_DZC_MASK_Msk CPUSS_V2_CM4_CTL_DZC_MASK_Msk #define CPUSS_CM4_CTL_OFC_MASK_Pos CPUSS_V2_CM4_CTL_OFC_MASK_Pos #define CPUSS_CM4_CTL_OFC_MASK_Msk CPUSS_V2_CM4_CTL_OFC_MASK_Msk #define CPUSS_CM4_CTL_UFC_MASK_Pos CPUSS_V2_CM4_CTL_UFC_MASK_Pos #define CPUSS_CM4_CTL_UFC_MASK_Msk CPUSS_V2_CM4_CTL_UFC_MASK_Msk #define CPUSS_CM4_CTL_IXC_MASK_Pos CPUSS_V2_CM4_CTL_IXC_MASK_Pos #define CPUSS_CM4_CTL_IXC_MASK_Msk CPUSS_V2_CM4_CTL_IXC_MASK_Msk #define CPUSS_CM4_CTL_IDC_MASK_Pos CPUSS_V2_CM4_CTL_IDC_MASK_Pos #define CPUSS_CM4_CTL_IDC_MASK_Msk CPUSS_V2_CM4_CTL_IDC_MASK_Msk /* CPUSS.CM4_INT0_STATUS */ #define CPUSS_CM4_INT0_STATUS_SYSTEM_INT_IDX_Pos CPUSS_V2_CM4_INT0_STATUS_SYSTEM_INT_IDX_Pos #define CPUSS_CM4_INT0_STATUS_SYSTEM_INT_IDX_Msk CPUSS_V2_CM4_INT0_STATUS_SYSTEM_INT_IDX_Msk #define CPUSS_CM4_INT0_STATUS_SYSTEM_INT_VALID_Pos CPUSS_V2_CM4_INT0_STATUS_SYSTEM_INT_VALID_Pos #define CPUSS_CM4_INT0_STATUS_SYSTEM_INT_VALID_Msk CPUSS_V2_CM4_INT0_STATUS_SYSTEM_INT_VALID_Msk /* CPUSS.CM4_INT1_STATUS */ #define CPUSS_CM4_INT1_STATUS_SYSTEM_INT_IDX_Pos CPUSS_V2_CM4_INT1_STATUS_SYSTEM_INT_IDX_Pos #define CPUSS_CM4_INT1_STATUS_SYSTEM_INT_IDX_Msk CPUSS_V2_CM4_INT1_STATUS_SYSTEM_INT_IDX_Msk #define CPUSS_CM4_INT1_STATUS_SYSTEM_INT_VALID_Pos CPUSS_V2_CM4_INT1_STATUS_SYSTEM_INT_VALID_Pos #define CPUSS_CM4_INT1_STATUS_SYSTEM_INT_VALID_Msk CPUSS_V2_CM4_INT1_STATUS_SYSTEM_INT_VALID_Msk /* CPUSS.CM4_INT2_STATUS */ #define CPUSS_CM4_INT2_STATUS_SYSTEM_INT_IDX_Pos CPUSS_V2_CM4_INT2_STATUS_SYSTEM_INT_IDX_Pos #define CPUSS_CM4_INT2_STATUS_SYSTEM_INT_IDX_Msk CPUSS_V2_CM4_INT2_STATUS_SYSTEM_INT_IDX_Msk #define CPUSS_CM4_INT2_STATUS_SYSTEM_INT_VALID_Pos CPUSS_V2_CM4_INT2_STATUS_SYSTEM_INT_VALID_Pos #define CPUSS_CM4_INT2_STATUS_SYSTEM_INT_VALID_Msk CPUSS_V2_CM4_INT2_STATUS_SYSTEM_INT_VALID_Msk /* CPUSS.CM4_INT3_STATUS */ #define CPUSS_CM4_INT3_STATUS_SYSTEM_INT_IDX_Pos CPUSS_V2_CM4_INT3_STATUS_SYSTEM_INT_IDX_Pos #define CPUSS_CM4_INT3_STATUS_SYSTEM_INT_IDX_Msk CPUSS_V2_CM4_INT3_STATUS_SYSTEM_INT_IDX_Msk #define CPUSS_CM4_INT3_STATUS_SYSTEM_INT_VALID_Pos CPUSS_V2_CM4_INT3_STATUS_SYSTEM_INT_VALID_Pos #define CPUSS_CM4_INT3_STATUS_SYSTEM_INT_VALID_Msk CPUSS_V2_CM4_INT3_STATUS_SYSTEM_INT_VALID_Msk /* CPUSS.CM4_INT4_STATUS */ #define CPUSS_CM4_INT4_STATUS_SYSTEM_INT_IDX_Pos CPUSS_V2_CM4_INT4_STATUS_SYSTEM_INT_IDX_Pos #define CPUSS_CM4_INT4_STATUS_SYSTEM_INT_IDX_Msk CPUSS_V2_CM4_INT4_STATUS_SYSTEM_INT_IDX_Msk #define CPUSS_CM4_INT4_STATUS_SYSTEM_INT_VALID_Pos CPUSS_V2_CM4_INT4_STATUS_SYSTEM_INT_VALID_Pos #define CPUSS_CM4_INT4_STATUS_SYSTEM_INT_VALID_Msk CPUSS_V2_CM4_INT4_STATUS_SYSTEM_INT_VALID_Msk /* CPUSS.CM4_INT5_STATUS */ #define CPUSS_CM4_INT5_STATUS_SYSTEM_INT_IDX_Pos CPUSS_V2_CM4_INT5_STATUS_SYSTEM_INT_IDX_Pos #define CPUSS_CM4_INT5_STATUS_SYSTEM_INT_IDX_Msk CPUSS_V2_CM4_INT5_STATUS_SYSTEM_INT_IDX_Msk #define CPUSS_CM4_INT5_STATUS_SYSTEM_INT_VALID_Pos CPUSS_V2_CM4_INT5_STATUS_SYSTEM_INT_VALID_Pos #define CPUSS_CM4_INT5_STATUS_SYSTEM_INT_VALID_Msk CPUSS_V2_CM4_INT5_STATUS_SYSTEM_INT_VALID_Msk /* CPUSS.CM4_INT6_STATUS */ #define CPUSS_CM4_INT6_STATUS_SYSTEM_INT_IDX_Pos CPUSS_V2_CM4_INT6_STATUS_SYSTEM_INT_IDX_Pos #define CPUSS_CM4_INT6_STATUS_SYSTEM_INT_IDX_Msk CPUSS_V2_CM4_INT6_STATUS_SYSTEM_INT_IDX_Msk #define CPUSS_CM4_INT6_STATUS_SYSTEM_INT_VALID_Pos CPUSS_V2_CM4_INT6_STATUS_SYSTEM_INT_VALID_Pos #define CPUSS_CM4_INT6_STATUS_SYSTEM_INT_VALID_Msk CPUSS_V2_CM4_INT6_STATUS_SYSTEM_INT_VALID_Msk /* CPUSS.CM4_INT7_STATUS */ #define CPUSS_CM4_INT7_STATUS_SYSTEM_INT_IDX_Pos CPUSS_V2_CM4_INT7_STATUS_SYSTEM_INT_IDX_Pos #define CPUSS_CM4_INT7_STATUS_SYSTEM_INT_IDX_Msk CPUSS_V2_CM4_INT7_STATUS_SYSTEM_INT_IDX_Msk #define CPUSS_CM4_INT7_STATUS_SYSTEM_INT_VALID_Pos CPUSS_V2_CM4_INT7_STATUS_SYSTEM_INT_VALID_Pos #define CPUSS_CM4_INT7_STATUS_SYSTEM_INT_VALID_Msk CPUSS_V2_CM4_INT7_STATUS_SYSTEM_INT_VALID_Msk /* CPUSS.CM4_VECTOR_TABLE_BASE */ #define CPUSS_CM4_VECTOR_TABLE_BASE_ADDR22_Pos CPUSS_V2_CM4_VECTOR_TABLE_BASE_ADDR22_Pos #define CPUSS_CM4_VECTOR_TABLE_BASE_ADDR22_Msk CPUSS_V2_CM4_VECTOR_TABLE_BASE_ADDR22_Msk /* CPUSS.CM4_NMI_CTL */ #define CPUSS_CM4_NMI_CTL_SYSTEM_INT_IDX_Pos CPUSS_V2_CM4_NMI_CTL_SYSTEM_INT_IDX_Pos #define CPUSS_CM4_NMI_CTL_SYSTEM_INT_IDX_Msk CPUSS_V2_CM4_NMI_CTL_SYSTEM_INT_IDX_Msk /* CPUSS.UDB_PWR_CTL */ #define CPUSS_UDB_PWR_CTL_PWR_MODE_Pos CPUSS_V2_UDB_PWR_CTL_PWR_MODE_Pos #define CPUSS_UDB_PWR_CTL_PWR_MODE_Msk CPUSS_V2_UDB_PWR_CTL_PWR_MODE_Msk #define CPUSS_UDB_PWR_CTL_VECTKEYSTAT_Pos CPUSS_V2_UDB_PWR_CTL_VECTKEYSTAT_Pos #define CPUSS_UDB_PWR_CTL_VECTKEYSTAT_Msk CPUSS_V2_UDB_PWR_CTL_VECTKEYSTAT_Msk /* CPUSS.UDB_PWR_DELAY_CTL */ #define CPUSS_UDB_PWR_DELAY_CTL_UP_Pos CPUSS_V2_UDB_PWR_DELAY_CTL_UP_Pos #define CPUSS_UDB_PWR_DELAY_CTL_UP_Msk CPUSS_V2_UDB_PWR_DELAY_CTL_UP_Msk /* CPUSS.CM0_CTL */ #define CPUSS_CM0_CTL_SLV_STALL_Pos CPUSS_V2_CM0_CTL_SLV_STALL_Pos #define CPUSS_CM0_CTL_SLV_STALL_Msk CPUSS_V2_CM0_CTL_SLV_STALL_Msk #define CPUSS_CM0_CTL_ENABLED_Pos CPUSS_V2_CM0_CTL_ENABLED_Pos #define CPUSS_CM0_CTL_ENABLED_Msk CPUSS_V2_CM0_CTL_ENABLED_Msk #define CPUSS_CM0_CTL_VECTKEYSTAT_Pos CPUSS_V2_CM0_CTL_VECTKEYSTAT_Pos #define CPUSS_CM0_CTL_VECTKEYSTAT_Msk CPUSS_V2_CM0_CTL_VECTKEYSTAT_Msk /* CPUSS.CM0_STATUS */ #define CPUSS_CM0_STATUS_SLEEPING_Pos CPUSS_V2_CM0_STATUS_SLEEPING_Pos #define CPUSS_CM0_STATUS_SLEEPING_Msk CPUSS_V2_CM0_STATUS_SLEEPING_Msk #define CPUSS_CM0_STATUS_SLEEPDEEP_Pos CPUSS_V2_CM0_STATUS_SLEEPDEEP_Pos #define CPUSS_CM0_STATUS_SLEEPDEEP_Msk CPUSS_V2_CM0_STATUS_SLEEPDEEP_Msk /* CPUSS.CM0_CLOCK_CTL */ #define CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV_Pos CPUSS_V2_CM0_CLOCK_CTL_SLOW_INT_DIV_Pos #define CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV_Msk CPUSS_V2_CM0_CLOCK_CTL_SLOW_INT_DIV_Msk #define CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV_Pos CPUSS_V2_CM0_CLOCK_CTL_PERI_INT_DIV_Pos #define CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV_Msk CPUSS_V2_CM0_CLOCK_CTL_PERI_INT_DIV_Msk /* CPUSS.CM0_INT_STATUS_BASE */ #define CPUSS_CM0_INT_STATUS_BASE ((volatile const uint32_t *) &(((CPUSS_Type *)(CPUSS))->CM0_INT0_STATUS)) /* CPUSS.CM0_INT0_STATUS */ #define CPUSS_CM0_INT0_STATUS_SYSTEM_INT_IDX_Pos CPUSS_V2_CM0_INT0_STATUS_SYSTEM_INT_IDX_Pos #define CPUSS_CM0_INT0_STATUS_SYSTEM_INT_IDX_Msk CPUSS_V2_CM0_INT0_STATUS_SYSTEM_INT_IDX_Msk #define CPUSS_CM0_INT0_STATUS_SYSTEM_INT_VALID_Pos CPUSS_V2_CM0_INT0_STATUS_SYSTEM_INT_VALID_Pos #define CPUSS_CM0_INT0_STATUS_SYSTEM_INT_VALID_Msk CPUSS_V2_CM0_INT0_STATUS_SYSTEM_INT_VALID_Msk /* CPUSS.CM0_INT1_STATUS */ #define CPUSS_CM0_INT1_STATUS_SYSTEM_INT_IDX_Pos CPUSS_V2_CM0_INT1_STATUS_SYSTEM_INT_IDX_Pos #define CPUSS_CM0_INT1_STATUS_SYSTEM_INT_IDX_Msk CPUSS_V2_CM0_INT1_STATUS_SYSTEM_INT_IDX_Msk #define CPUSS_CM0_INT1_STATUS_SYSTEM_INT_VALID_Pos CPUSS_V2_CM0_INT1_STATUS_SYSTEM_INT_VALID_Pos #define CPUSS_CM0_INT1_STATUS_SYSTEM_INT_VALID_Msk CPUSS_V2_CM0_INT1_STATUS_SYSTEM_INT_VALID_Msk /* CPUSS.CM0_INT2_STATUS */ #define CPUSS_CM0_INT2_STATUS_SYSTEM_INT_IDX_Pos CPUSS_V2_CM0_INT2_STATUS_SYSTEM_INT_IDX_Pos #define CPUSS_CM0_INT2_STATUS_SYSTEM_INT_IDX_Msk CPUSS_V2_CM0_INT2_STATUS_SYSTEM_INT_IDX_Msk #define CPUSS_CM0_INT2_STATUS_SYSTEM_INT_VALID_Pos CPUSS_V2_CM0_INT2_STATUS_SYSTEM_INT_VALID_Pos #define CPUSS_CM0_INT2_STATUS_SYSTEM_INT_VALID_Msk CPUSS_V2_CM0_INT2_STATUS_SYSTEM_INT_VALID_Msk /* CPUSS.CM0_INT3_STATUS */ #define CPUSS_CM0_INT3_STATUS_SYSTEM_INT_IDX_Pos CPUSS_V2_CM0_INT3_STATUS_SYSTEM_INT_IDX_Pos #define CPUSS_CM0_INT3_STATUS_SYSTEM_INT_IDX_Msk CPUSS_V2_CM0_INT3_STATUS_SYSTEM_INT_IDX_Msk #define CPUSS_CM0_INT3_STATUS_SYSTEM_INT_VALID_Pos CPUSS_V2_CM0_INT3_STATUS_SYSTEM_INT_VALID_Pos #define CPUSS_CM0_INT3_STATUS_SYSTEM_INT_VALID_Msk CPUSS_V2_CM0_INT3_STATUS_SYSTEM_INT_VALID_Msk /* CPUSS.CM0_INT4_STATUS */ #define CPUSS_CM0_INT4_STATUS_SYSTEM_INT_IDX_Pos CPUSS_V2_CM0_INT4_STATUS_SYSTEM_INT_IDX_Pos #define CPUSS_CM0_INT4_STATUS_SYSTEM_INT_IDX_Msk CPUSS_V2_CM0_INT4_STATUS_SYSTEM_INT_IDX_Msk #define CPUSS_CM0_INT4_STATUS_SYSTEM_INT_VALID_Pos CPUSS_V2_CM0_INT4_STATUS_SYSTEM_INT_VALID_Pos #define CPUSS_CM0_INT4_STATUS_SYSTEM_INT_VALID_Msk CPUSS_V2_CM0_INT4_STATUS_SYSTEM_INT_VALID_Msk /* CPUSS.CM0_INT5_STATUS */ #define CPUSS_CM0_INT5_STATUS_SYSTEM_INT_IDX_Pos CPUSS_V2_CM0_INT5_STATUS_SYSTEM_INT_IDX_Pos #define CPUSS_CM0_INT5_STATUS_SYSTEM_INT_IDX_Msk CPUSS_V2_CM0_INT5_STATUS_SYSTEM_INT_IDX_Msk #define CPUSS_CM0_INT5_STATUS_SYSTEM_INT_VALID_Pos CPUSS_V2_CM0_INT5_STATUS_SYSTEM_INT_VALID_Pos #define CPUSS_CM0_INT5_STATUS_SYSTEM_INT_VALID_Msk CPUSS_V2_CM0_INT5_STATUS_SYSTEM_INT_VALID_Msk /* CPUSS.CM0_INT6_STATUS */ #define CPUSS_CM0_INT6_STATUS_SYSTEM_INT_IDX_Pos CPUSS_V2_CM0_INT6_STATUS_SYSTEM_INT_IDX_Pos #define CPUSS_CM0_INT6_STATUS_SYSTEM_INT_IDX_Msk CPUSS_V2_CM0_INT6_STATUS_SYSTEM_INT_IDX_Msk #define CPUSS_CM0_INT6_STATUS_SYSTEM_INT_VALID_Pos CPUSS_V2_CM0_INT6_STATUS_SYSTEM_INT_VALID_Pos #define CPUSS_CM0_INT6_STATUS_SYSTEM_INT_VALID_Msk CPUSS_V2_CM0_INT6_STATUS_SYSTEM_INT_VALID_Msk /* CPUSS.CM0_INT7_STATUS */ #define CPUSS_CM0_INT7_STATUS_SYSTEM_INT_IDX_Pos CPUSS_V2_CM0_INT7_STATUS_SYSTEM_INT_IDX_Pos #define CPUSS_CM0_INT7_STATUS_SYSTEM_INT_IDX_Msk CPUSS_V2_CM0_INT7_STATUS_SYSTEM_INT_IDX_Msk #define CPUSS_CM0_INT7_STATUS_SYSTEM_INT_VALID_Pos CPUSS_V2_CM0_INT7_STATUS_SYSTEM_INT_VALID_Pos #define CPUSS_CM0_INT7_STATUS_SYSTEM_INT_VALID_Msk CPUSS_V2_CM0_INT7_STATUS_SYSTEM_INT_VALID_Msk /* CPUSS.CM0_VECTOR_TABLE_BASE */ #define CPUSS_CM0_VECTOR_TABLE_BASE_ADDR24_Pos CPUSS_V2_CM0_VECTOR_TABLE_BASE_ADDR24_Pos #define CPUSS_CM0_VECTOR_TABLE_BASE_ADDR24_Msk CPUSS_V2_CM0_VECTOR_TABLE_BASE_ADDR24_Msk /* CPUSS.CM0_NMI_CTL */ #define CPUSS_CM0_NMI_CTL_SYSTEM_INT_IDX_Pos CPUSS_V2_CM0_NMI_CTL_SYSTEM_INT_IDX_Pos #define CPUSS_CM0_NMI_CTL_SYSTEM_INT_IDX_Msk CPUSS_V2_CM0_NMI_CTL_SYSTEM_INT_IDX_Msk /* CPUSS.CM4_PWR_CTL */ #define CPUSS_CM4_PWR_CTL_PWR_MODE_Pos CPUSS_V2_CM4_PWR_CTL_PWR_MODE_Pos #define CPUSS_CM4_PWR_CTL_PWR_MODE_Msk CPUSS_V2_CM4_PWR_CTL_PWR_MODE_Msk #define CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Pos CPUSS_V2_CM4_PWR_CTL_VECTKEYSTAT_Pos #define CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk CPUSS_V2_CM4_PWR_CTL_VECTKEYSTAT_Msk /* CPUSS.CM4_PWR_DELAY_CTL */ #define CPUSS_CM4_PWR_DELAY_CTL_UP_Pos CPUSS_V2_CM4_PWR_DELAY_CTL_UP_Pos #define CPUSS_CM4_PWR_DELAY_CTL_UP_Msk CPUSS_V2_CM4_PWR_DELAY_CTL_UP_Msk /* CPUSS.RAM0_CTL0 */ #define CPUSS_RAM0_CTL0_SLOW_WS_Pos CPUSS_V2_RAM0_CTL0_SLOW_WS_Pos #define CPUSS_RAM0_CTL0_SLOW_WS_Msk CPUSS_V2_RAM0_CTL0_SLOW_WS_Msk #define CPUSS_RAM0_CTL0_FAST_WS_Pos CPUSS_V2_RAM0_CTL0_FAST_WS_Pos #define CPUSS_RAM0_CTL0_FAST_WS_Msk CPUSS_V2_RAM0_CTL0_FAST_WS_Msk #define CPUSS_RAM0_CTL0_ECC_EN_Pos CPUSS_V2_RAM0_CTL0_ECC_EN_Pos #define CPUSS_RAM0_CTL0_ECC_EN_Msk CPUSS_V2_RAM0_CTL0_ECC_EN_Msk #define CPUSS_RAM0_CTL0_ECC_AUTO_CORRECT_Pos CPUSS_V2_RAM0_CTL0_ECC_AUTO_CORRECT_Pos #define CPUSS_RAM0_CTL0_ECC_AUTO_CORRECT_Msk CPUSS_V2_RAM0_CTL0_ECC_AUTO_CORRECT_Msk #define CPUSS_RAM0_CTL0_ECC_INJ_EN_Pos CPUSS_V2_RAM0_CTL0_ECC_INJ_EN_Pos #define CPUSS_RAM0_CTL0_ECC_INJ_EN_Msk CPUSS_V2_RAM0_CTL0_ECC_INJ_EN_Msk /* CPUSS.RAM0_STATUS */ #define CPUSS_RAM0_STATUS_WB_EMPTY_Pos CPUSS_V2_RAM0_STATUS_WB_EMPTY_Pos #define CPUSS_RAM0_STATUS_WB_EMPTY_Msk CPUSS_V2_RAM0_STATUS_WB_EMPTY_Msk /* CPUSS.RAM0_PWR_MACRO_CTL */ #define CPUSS_RAM0_PWR_MACRO_CTL_PWR_MODE_Pos CPUSS_V2_RAM0_PWR_MACRO_CTL_PWR_MODE_Pos #define CPUSS_RAM0_PWR_MACRO_CTL_PWR_MODE_Msk CPUSS_V2_RAM0_PWR_MACRO_CTL_PWR_MODE_Msk #define CPUSS_RAM0_PWR_MACRO_CTL_VECTKEYSTAT_Pos CPUSS_V2_RAM0_PWR_MACRO_CTL_VECTKEYSTAT_Pos #define CPUSS_RAM0_PWR_MACRO_CTL_VECTKEYSTAT_Msk CPUSS_V2_RAM0_PWR_MACRO_CTL_VECTKEYSTAT_Msk /* CPUSS.RAM1_CTL0 */ #define CPUSS_RAM1_CTL0_SLOW_WS_Pos CPUSS_V2_RAM1_CTL0_SLOW_WS_Pos #define CPUSS_RAM1_CTL0_SLOW_WS_Msk CPUSS_V2_RAM1_CTL0_SLOW_WS_Msk #define CPUSS_RAM1_CTL0_FAST_WS_Pos CPUSS_V2_RAM1_CTL0_FAST_WS_Pos #define CPUSS_RAM1_CTL0_FAST_WS_Msk CPUSS_V2_RAM1_CTL0_FAST_WS_Msk #define CPUSS_RAM1_CTL0_ECC_EN_Pos CPUSS_V2_RAM1_CTL0_ECC_EN_Pos #define CPUSS_RAM1_CTL0_ECC_EN_Msk CPUSS_V2_RAM1_CTL0_ECC_EN_Msk #define CPUSS_RAM1_CTL0_ECC_AUTO_CORRECT_Pos CPUSS_V2_RAM1_CTL0_ECC_AUTO_CORRECT_Pos #define CPUSS_RAM1_CTL0_ECC_AUTO_CORRECT_Msk CPUSS_V2_RAM1_CTL0_ECC_AUTO_CORRECT_Msk #define CPUSS_RAM1_CTL0_ECC_INJ_EN_Pos CPUSS_V2_RAM1_CTL0_ECC_INJ_EN_Pos #define CPUSS_RAM1_CTL0_ECC_INJ_EN_Msk CPUSS_V2_RAM1_CTL0_ECC_INJ_EN_Msk /* CPUSS.RAM1_STATUS */ #define CPUSS_RAM1_STATUS_WB_EMPTY_Pos CPUSS_V2_RAM1_STATUS_WB_EMPTY_Pos #define CPUSS_RAM1_STATUS_WB_EMPTY_Msk CPUSS_V2_RAM1_STATUS_WB_EMPTY_Msk /* CPUSS.RAM1_PWR_CTL */ #define CPUSS_RAM1_PWR_CTL_PWR_MODE_Pos CPUSS_V2_RAM1_PWR_CTL_PWR_MODE_Pos #define CPUSS_RAM1_PWR_CTL_PWR_MODE_Msk CPUSS_V2_RAM1_PWR_CTL_PWR_MODE_Msk #define CPUSS_RAM1_PWR_CTL_VECTKEYSTAT_Pos CPUSS_V2_RAM1_PWR_CTL_VECTKEYSTAT_Pos #define CPUSS_RAM1_PWR_CTL_VECTKEYSTAT_Msk CPUSS_V2_RAM1_PWR_CTL_VECTKEYSTAT_Msk /* CPUSS.RAM2_CTL0 */ #define CPUSS_RAM2_CTL0_SLOW_WS_Pos CPUSS_V2_RAM2_CTL0_SLOW_WS_Pos #define CPUSS_RAM2_CTL0_SLOW_WS_Msk CPUSS_V2_RAM2_CTL0_SLOW_WS_Msk #define CPUSS_RAM2_CTL0_FAST_WS_Pos CPUSS_V2_RAM2_CTL0_FAST_WS_Pos #define CPUSS_RAM2_CTL0_FAST_WS_Msk CPUSS_V2_RAM2_CTL0_FAST_WS_Msk #define CPUSS_RAM2_CTL0_ECC_EN_Pos CPUSS_V2_RAM2_CTL0_ECC_EN_Pos #define CPUSS_RAM2_CTL0_ECC_EN_Msk CPUSS_V2_RAM2_CTL0_ECC_EN_Msk #define CPUSS_RAM2_CTL0_ECC_AUTO_CORRECT_Pos CPUSS_V2_RAM2_CTL0_ECC_AUTO_CORRECT_Pos #define CPUSS_RAM2_CTL0_ECC_AUTO_CORRECT_Msk CPUSS_V2_RAM2_CTL0_ECC_AUTO_CORRECT_Msk #define CPUSS_RAM2_CTL0_ECC_INJ_EN_Pos CPUSS_V2_RAM2_CTL0_ECC_INJ_EN_Pos #define CPUSS_RAM2_CTL0_ECC_INJ_EN_Msk CPUSS_V2_RAM2_CTL0_ECC_INJ_EN_Msk /* CPUSS.RAM2_STATUS */ #define CPUSS_RAM2_STATUS_WB_EMPTY_Pos CPUSS_V2_RAM2_STATUS_WB_EMPTY_Pos #define CPUSS_RAM2_STATUS_WB_EMPTY_Msk CPUSS_V2_RAM2_STATUS_WB_EMPTY_Msk /* CPUSS.RAM2_PWR_CTL */ #define CPUSS_RAM2_PWR_CTL_PWR_MODE_Pos CPUSS_V2_RAM2_PWR_CTL_PWR_MODE_Pos #define CPUSS_RAM2_PWR_CTL_PWR_MODE_Msk CPUSS_V2_RAM2_PWR_CTL_PWR_MODE_Msk #define CPUSS_RAM2_PWR_CTL_VECTKEYSTAT_Pos CPUSS_V2_RAM2_PWR_CTL_VECTKEYSTAT_Pos #define CPUSS_RAM2_PWR_CTL_VECTKEYSTAT_Msk CPUSS_V2_RAM2_PWR_CTL_VECTKEYSTAT_Msk /* CPUSS.RAM_PWR_DELAY_CTL */ #define CPUSS_RAM_PWR_DELAY_CTL_UP_Pos CPUSS_V2_RAM_PWR_DELAY_CTL_UP_Pos #define CPUSS_RAM_PWR_DELAY_CTL_UP_Msk CPUSS_V2_RAM_PWR_DELAY_CTL_UP_Msk /* CPUSS.ROM_CTL */ #define CPUSS_ROM_CTL_SLOW_WS_Pos CPUSS_V2_ROM_CTL_SLOW_WS_Pos #define CPUSS_ROM_CTL_SLOW_WS_Msk CPUSS_V2_ROM_CTL_SLOW_WS_Msk #define CPUSS_ROM_CTL_FAST_WS_Pos CPUSS_V2_ROM_CTL_FAST_WS_Pos #define CPUSS_ROM_CTL_FAST_WS_Msk CPUSS_V2_ROM_CTL_FAST_WS_Msk /* CPUSS.ECC_CTL */ #define CPUSS_ECC_CTL_WORD_ADDR_Pos CPUSS_V2_ECC_CTL_WORD_ADDR_Pos #define CPUSS_ECC_CTL_WORD_ADDR_Msk CPUSS_V2_ECC_CTL_WORD_ADDR_Msk #define CPUSS_ECC_CTL_PARITY_Pos CPUSS_V2_ECC_CTL_PARITY_Pos #define CPUSS_ECC_CTL_PARITY_Msk CPUSS_V2_ECC_CTL_PARITY_Msk /* CPUSS.PRODUCT_ID */ #define CPUSS_PRODUCT_ID_FAMILY_ID_Pos CPUSS_V2_PRODUCT_ID_FAMILY_ID_Pos #define CPUSS_PRODUCT_ID_FAMILY_ID_Msk CPUSS_V2_PRODUCT_ID_FAMILY_ID_Msk #define CPUSS_PRODUCT_ID_MAJOR_REV_Pos CPUSS_V2_PRODUCT_ID_MAJOR_REV_Pos #define CPUSS_PRODUCT_ID_MAJOR_REV_Msk CPUSS_V2_PRODUCT_ID_MAJOR_REV_Msk #define CPUSS_PRODUCT_ID_MINOR_REV_Pos CPUSS_V2_PRODUCT_ID_MINOR_REV_Pos #define CPUSS_PRODUCT_ID_MINOR_REV_Msk CPUSS_V2_PRODUCT_ID_MINOR_REV_Msk /* CPUSS.DP_STATUS */ #define CPUSS_DP_STATUS_SWJ_CONNECTED_Pos CPUSS_V2_DP_STATUS_SWJ_CONNECTED_Pos #define CPUSS_DP_STATUS_SWJ_CONNECTED_Msk CPUSS_V2_DP_STATUS_SWJ_CONNECTED_Msk #define CPUSS_DP_STATUS_SWJ_DEBUG_EN_Pos CPUSS_V2_DP_STATUS_SWJ_DEBUG_EN_Pos #define CPUSS_DP_STATUS_SWJ_DEBUG_EN_Msk CPUSS_V2_DP_STATUS_SWJ_DEBUG_EN_Msk #define CPUSS_DP_STATUS_SWJ_JTAG_SEL_Pos CPUSS_V2_DP_STATUS_SWJ_JTAG_SEL_Pos #define CPUSS_DP_STATUS_SWJ_JTAG_SEL_Msk CPUSS_V2_DP_STATUS_SWJ_JTAG_SEL_Msk /* CPUSS.AP_CTL */ #define CPUSS_AP_CTL_CM0_ENABLE_Pos CPUSS_V2_AP_CTL_CM0_ENABLE_Pos #define CPUSS_AP_CTL_CM0_ENABLE_Msk CPUSS_V2_AP_CTL_CM0_ENABLE_Msk #define CPUSS_AP_CTL_CM4_ENABLE_Pos CPUSS_V2_AP_CTL_CM4_ENABLE_Pos #define CPUSS_AP_CTL_CM4_ENABLE_Msk CPUSS_V2_AP_CTL_CM4_ENABLE_Msk #define CPUSS_AP_CTL_SYS_ENABLE_Pos CPUSS_V2_AP_CTL_SYS_ENABLE_Pos #define CPUSS_AP_CTL_SYS_ENABLE_Msk CPUSS_V2_AP_CTL_SYS_ENABLE_Msk #define CPUSS_AP_CTL_CM0_DISABLE_Pos CPUSS_V2_AP_CTL_CM0_DISABLE_Pos #define CPUSS_AP_CTL_CM0_DISABLE_Msk CPUSS_V2_AP_CTL_CM0_DISABLE_Msk #define CPUSS_AP_CTL_CM4_DISABLE_Pos CPUSS_V2_AP_CTL_CM4_DISABLE_Pos #define CPUSS_AP_CTL_CM4_DISABLE_Msk CPUSS_V2_AP_CTL_CM4_DISABLE_Msk #define CPUSS_AP_CTL_SYS_DISABLE_Pos CPUSS_V2_AP_CTL_SYS_DISABLE_Pos #define CPUSS_AP_CTL_SYS_DISABLE_Msk CPUSS_V2_AP_CTL_SYS_DISABLE_Msk /* CPUSS.BUFF_CTL */ #define CPUSS_BUFF_CTL_WRITE_BUFF_Pos CPUSS_V2_BUFF_CTL_WRITE_BUFF_Pos #define CPUSS_BUFF_CTL_WRITE_BUFF_Msk CPUSS_V2_BUFF_CTL_WRITE_BUFF_Msk /* CPUSS.SYSTICK_CTL */ #define CPUSS_SYSTICK_CTL_TENMS_Pos CPUSS_V2_SYSTICK_CTL_TENMS_Pos #define CPUSS_SYSTICK_CTL_TENMS_Msk CPUSS_V2_SYSTICK_CTL_TENMS_Msk #define CPUSS_SYSTICK_CTL_CLOCK_SOURCE_Pos CPUSS_V2_SYSTICK_CTL_CLOCK_SOURCE_Pos #define CPUSS_SYSTICK_CTL_CLOCK_SOURCE_Msk CPUSS_V2_SYSTICK_CTL_CLOCK_SOURCE_Msk #define CPUSS_SYSTICK_CTL_SKEW_Pos CPUSS_V2_SYSTICK_CTL_SKEW_Pos #define CPUSS_SYSTICK_CTL_SKEW_Msk CPUSS_V2_SYSTICK_CTL_SKEW_Msk #define CPUSS_SYSTICK_CTL_NOREF_Pos CPUSS_V2_SYSTICK_CTL_NOREF_Pos #define CPUSS_SYSTICK_CTL_NOREF_Msk CPUSS_V2_SYSTICK_CTL_NOREF_Msk /* CPUSS.MBIST_STAT */ #define CPUSS_MBIST_STAT_SFP_READY_Pos CPUSS_V2_MBIST_STAT_SFP_READY_Pos #define CPUSS_MBIST_STAT_SFP_READY_Msk CPUSS_V2_MBIST_STAT_SFP_READY_Msk #define CPUSS_MBIST_STAT_SFP_FAIL_Pos CPUSS_V2_MBIST_STAT_SFP_FAIL_Pos #define CPUSS_MBIST_STAT_SFP_FAIL_Msk CPUSS_V2_MBIST_STAT_SFP_FAIL_Msk /* CPUSS.CAL_SUP_SET */ #define CPUSS_CAL_SUP_SET_DATA_Pos CPUSS_V2_CAL_SUP_SET_DATA_Pos #define CPUSS_CAL_SUP_SET_DATA_Msk CPUSS_V2_CAL_SUP_SET_DATA_Msk /* CPUSS.CAL_SUP_CLR */ #define CPUSS_CAL_SUP_CLR_DATA_Pos CPUSS_V2_CAL_SUP_CLR_DATA_Pos #define CPUSS_CAL_SUP_CLR_DATA_Msk CPUSS_V2_CAL_SUP_CLR_DATA_Msk /* CPUSS.CM0_PC_CTL */ #define CPUSS_CM0_PC_CTL_VALID_Pos CPUSS_V2_CM0_PC_CTL_VALID_Pos #define CPUSS_CM0_PC_CTL_VALID_Msk CPUSS_V2_CM0_PC_CTL_VALID_Msk /* CPUSS.CM0_PC0_HANDLER */ #define CPUSS_CM0_PC0_HANDLER_ADDR_Pos CPUSS_V2_CM0_PC0_HANDLER_ADDR_Pos #define CPUSS_CM0_PC0_HANDLER_ADDR_Msk CPUSS_V2_CM0_PC0_HANDLER_ADDR_Msk /* CPUSS.CM0_PC1_HANDLER */ #define CPUSS_CM0_PC1_HANDLER_ADDR_Pos CPUSS_V2_CM0_PC1_HANDLER_ADDR_Pos #define CPUSS_CM0_PC1_HANDLER_ADDR_Msk CPUSS_V2_CM0_PC1_HANDLER_ADDR_Msk /* CPUSS.CM0_PC2_HANDLER */ #define CPUSS_CM0_PC2_HANDLER_ADDR_Pos CPUSS_V2_CM0_PC2_HANDLER_ADDR_Pos #define CPUSS_CM0_PC2_HANDLER_ADDR_Msk CPUSS_V2_CM0_PC2_HANDLER_ADDR_Msk /* CPUSS.CM0_PC3_HANDLER */ #define CPUSS_CM0_PC3_HANDLER_ADDR_Pos CPUSS_V2_CM0_PC3_HANDLER_ADDR_Pos #define CPUSS_CM0_PC3_HANDLER_ADDR_Msk CPUSS_V2_CM0_PC3_HANDLER_ADDR_Msk /* CPUSS.PROTECTION */ #define CPUSS_PROTECTION_STATE_Pos CPUSS_V2_PROTECTION_STATE_Pos #define CPUSS_PROTECTION_STATE_Msk CPUSS_V2_PROTECTION_STATE_Msk /* CPUSS.TRIM_ROM_CTL */ #define CPUSS_TRIM_ROM_CTL_TRIM_Pos CPUSS_V2_TRIM_ROM_CTL_TRIM_Pos #define CPUSS_TRIM_ROM_CTL_TRIM_Msk CPUSS_V2_TRIM_ROM_CTL_TRIM_Msk /* CPUSS.TRIM_RAM_CTL */ #define CPUSS_TRIM_RAM_CTL_TRIM_Pos CPUSS_V2_TRIM_RAM_CTL_TRIM_Pos #define CPUSS_TRIM_RAM_CTL_TRIM_Msk CPUSS_V2_TRIM_RAM_CTL_TRIM_Msk /* CPUSS.CM0_SYSTEM_INT_CTL */ #define CPUSS_CM0_SYSTEM_INT_CTL_CPU_INT_IDX_Pos CPUSS_V2_CM0_SYSTEM_INT_CTL_CPU_INT_IDX_Pos #define CPUSS_CM0_SYSTEM_INT_CTL_CPU_INT_IDX_Msk CPUSS_V2_CM0_SYSTEM_INT_CTL_CPU_INT_IDX_Msk #define CPUSS_CM0_SYSTEM_INT_CTL_CPU_INT_VALID_Pos CPUSS_V2_CM0_SYSTEM_INT_CTL_CPU_INT_VALID_Pos #define CPUSS_CM0_SYSTEM_INT_CTL_CPU_INT_VALID_Msk CPUSS_V2_CM0_SYSTEM_INT_CTL_CPU_INT_VALID_Msk /* CPUSS.CM4_SYSTEM_INT_CTL */ #define CPUSS_CM4_SYSTEM_INT_CTL_CPU_INT_IDX_Pos CPUSS_V2_CM4_SYSTEM_INT_CTL_CPU_INT_IDX_Pos #define CPUSS_CM4_SYSTEM_INT_CTL_CPU_INT_IDX_Msk CPUSS_V2_CM4_SYSTEM_INT_CTL_CPU_INT_IDX_Msk #define CPUSS_CM4_SYSTEM_INT_CTL_CPU_INT_VALID_Pos CPUSS_V2_CM4_SYSTEM_INT_CTL_CPU_INT_VALID_Pos #define CPUSS_CM4_SYSTEM_INT_CTL_CPU_INT_VALID_Msk CPUSS_V2_CM4_SYSTEM_INT_CTL_CPU_INT_VALID_Msk /******************************************************************************* * FAULT *******************************************************************************/ /* FAULT_STRUCT.CTL */ #define FAULT_STRUCT_CTL_TR_EN_Pos FAULT_STRUCT_V2_CTL_TR_EN_Pos #define FAULT_STRUCT_CTL_TR_EN_Msk FAULT_STRUCT_V2_CTL_TR_EN_Msk #define FAULT_STRUCT_CTL_OUT_EN_Pos FAULT_STRUCT_V2_CTL_OUT_EN_Pos #define FAULT_STRUCT_CTL_OUT_EN_Msk FAULT_STRUCT_V2_CTL_OUT_EN_Msk #define FAULT_STRUCT_CTL_RESET_REQ_EN_Pos FAULT_STRUCT_V2_CTL_RESET_REQ_EN_Pos #define FAULT_STRUCT_CTL_RESET_REQ_EN_Msk FAULT_STRUCT_V2_CTL_RESET_REQ_EN_Msk /* FAULT_STRUCT.STATUS */ #define FAULT_STRUCT_STATUS_IDX_Pos FAULT_STRUCT_V2_STATUS_IDX_Pos #define FAULT_STRUCT_STATUS_IDX_Msk FAULT_STRUCT_V2_STATUS_IDX_Msk #define FAULT_STRUCT_STATUS_VALID_Pos FAULT_STRUCT_V2_STATUS_VALID_Pos #define FAULT_STRUCT_STATUS_VALID_Msk FAULT_STRUCT_V2_STATUS_VALID_Msk /* FAULT_STRUCT.DATA */ #define FAULT_STRUCT_DATA_DATA_Pos FAULT_STRUCT_V2_DATA_DATA_Pos #define FAULT_STRUCT_DATA_DATA_Msk FAULT_STRUCT_V2_DATA_DATA_Msk /* FAULT_STRUCT.PENDING0 */ #define FAULT_STRUCT_PENDING0_SOURCE_Pos FAULT_STRUCT_V2_PENDING0_SOURCE_Pos #define FAULT_STRUCT_PENDING0_SOURCE_Msk FAULT_STRUCT_V2_PENDING0_SOURCE_Msk /* FAULT_STRUCT.PENDING1 */ #define FAULT_STRUCT_PENDING1_SOURCE_Pos FAULT_STRUCT_V2_PENDING1_SOURCE_Pos #define FAULT_STRUCT_PENDING1_SOURCE_Msk FAULT_STRUCT_V2_PENDING1_SOURCE_Msk /* FAULT_STRUCT.PENDING2 */ #define FAULT_STRUCT_PENDING2_SOURCE_Pos FAULT_STRUCT_V2_PENDING2_SOURCE_Pos #define FAULT_STRUCT_PENDING2_SOURCE_Msk FAULT_STRUCT_V2_PENDING2_SOURCE_Msk /* FAULT_STRUCT.MASK0 */ #define FAULT_STRUCT_MASK0_SOURCE_Pos FAULT_STRUCT_V2_MASK0_SOURCE_Pos #define FAULT_STRUCT_MASK0_SOURCE_Msk FAULT_STRUCT_V2_MASK0_SOURCE_Msk /* FAULT_STRUCT.MASK1 */ #define FAULT_STRUCT_MASK1_SOURCE_Pos FAULT_STRUCT_V2_MASK1_SOURCE_Pos #define FAULT_STRUCT_MASK1_SOURCE_Msk FAULT_STRUCT_V2_MASK1_SOURCE_Msk /* FAULT_STRUCT.MASK2 */ #define FAULT_STRUCT_MASK2_SOURCE_Pos FAULT_STRUCT_V2_MASK2_SOURCE_Pos #define FAULT_STRUCT_MASK2_SOURCE_Msk FAULT_STRUCT_V2_MASK2_SOURCE_Msk /* FAULT_STRUCT.INTR */ #define FAULT_STRUCT_INTR_FAULT_Pos FAULT_STRUCT_V2_INTR_FAULT_Pos #define FAULT_STRUCT_INTR_FAULT_Msk FAULT_STRUCT_V2_INTR_FAULT_Msk /* FAULT_STRUCT.INTR_SET */ #define FAULT_STRUCT_INTR_SET_FAULT_Pos FAULT_STRUCT_V2_INTR_SET_FAULT_Pos #define FAULT_STRUCT_INTR_SET_FAULT_Msk FAULT_STRUCT_V2_INTR_SET_FAULT_Msk /* FAULT_STRUCT.INTR_MASK */ #define FAULT_STRUCT_INTR_MASK_FAULT_Pos FAULT_STRUCT_V2_INTR_MASK_FAULT_Pos #define FAULT_STRUCT_INTR_MASK_FAULT_Msk FAULT_STRUCT_V2_INTR_MASK_FAULT_Msk /* FAULT_STRUCT.INTR_MASKED */ #define FAULT_STRUCT_INTR_MASKED_FAULT_Pos FAULT_STRUCT_V2_INTR_MASKED_FAULT_Pos #define FAULT_STRUCT_INTR_MASKED_FAULT_Msk FAULT_STRUCT_V2_INTR_MASKED_FAULT_Msk /******************************************************************************* * FLASH *******************************************************************************/ #define FLASHC_FLASH_CTL_MAIN_WS_Pos FLASHC_V2_FLASH_CTL_MAIN_WS_Pos #define FLASHC_FLASH_CTL_MAIN_WS_Msk FLASHC_V2_FLASH_CTL_MAIN_WS_Msk #define FLASHC_FLASH_CTL_MAIN_MAP_Pos FLASHC_V2_FLASH_CTL_MAIN_MAP_Pos #define FLASHC_FLASH_CTL_MAIN_MAP_Msk FLASHC_V2_FLASH_CTL_MAIN_MAP_Msk #define FLASHC_FLASH_CTL_WORK_MAP_Pos FLASHC_V2_FLASH_CTL_WORK_MAP_Pos #define FLASHC_FLASH_CTL_WORK_MAP_Msk FLASHC_V2_FLASH_CTL_WORK_MAP_Msk #define FLASHC_FLASH_CTL_MAIN_BANK_MODE_Pos FLASHC_V2_FLASH_CTL_MAIN_BANK_MODE_Pos #define FLASHC_FLASH_CTL_MAIN_BANK_MODE_Msk FLASHC_V2_FLASH_CTL_MAIN_BANK_MODE_Msk #define FLASHC_FLASH_CTL_WORK_BANK_MODE_Pos FLASHC_V2_FLASH_CTL_WORK_BANK_MODE_Pos #define FLASHC_FLASH_CTL_WORK_BANK_MODE_Msk FLASHC_V2_FLASH_CTL_WORK_BANK_MODE_Msk #define FLASHC_FLASH_CMD_INV_Msk FLASHC_V2_FLASH_CMD_INV_Msk #define FLASHC_FLASH_CMD_INV_Pos FLASHC_V2_FLASH_CMD_INV_Pos #define FLASHC_FM_CTL_ECT_STATUS_PGM_WORK_Msk FLASHC_FM_CTL_ECT_V2_STATUS_PGM_WORK_Msk #define FLASHC_FM_CTL_ECT_STATUS_PGM_CODE_Msk FLASHC_FM_CTL_ECT_V2_STATUS_PGM_CODE_Msk #define FLASHC_FM_CTL_ECT_STATUS_BLANK_CHECK_WORK_Msk FLASHC_FM_CTL_ECT_V2_STATUS_BLANK_CHECK_WORK_Msk #define FLASHC_FM_CTL_ECT_STATUS_ERASE_CODE_Msk FLASHC_FM_CTL_ECT_V2_STATUS_ERASE_CODE_Msk #define FLASHC_FM_CTL_ECT_STATUS_ERASE_WORK_Msk FLASHC_FM_CTL_ECT_V2_STATUS_ERASE_WORK_Msk #define FLASHC_FM_CTL_ECT_MAIN_FLASH_SAFETY_MAINFLASHWRITEENABLE_Msk FLASHC_FM_CTL_ECT_V2_MAIN_FLASH_SAFETY_MAINFLASHWRITEENABLE_Msk #define FLASHC_FM_CTL_ECT_WORK_FLASH_SAFETY_WORKFLASHWRITEENABLE_Msk FLASHC_FM_CTL_ECT_V2_WORK_FLASH_SAFETY_WORKFLASHWRITEENABLE_Msk #define FLASHC_FLASH_CTL_MAIN_ECC_INJ_EN FLASHC_V2_FLASH_CTL_MAIN_ECC_INJ_EN #define FLASHC_FLASH_CTL_MAIN_ECC_INJ_EN_Pos FLASHC_V2_FLASH_CTL_MAIN_ECC_INJ_EN_Pos #define FLASHC_FLASH_CTL_MAIN_ECC_INJ_EN_Msk FLASHC_V2_FLASH_CTL_MAIN_ECC_INJ_EN_Msk #define FLASHC_FLASH_CTL_WORK_ECC_INJ_EN_Pos FLASHC_V2_FLASH_CTL_WORK_ECC_INJ_EN_Pos #define FLASHC_FLASH_CTL_WORK_ECC_INJ_EN_Msk FLASHC_V2_FLASH_CTL_WORK_ECC_INJ_EN_Msk #define FLASHC_CM0_CA_CTL0_RAM_ECC_INJ_EN_Pos FLASHC_V2_CM0_CA_CTL0_RAM_ECC_INJ_EN_Pos #define FLASHC_ECC_CTL_WORD_ADDR FLASHC_V2_ECC_CTL_WORD_ADDR #define FLASHC_ECC_CTL_PARITY FLASHC_V2_ECC_CTL_PARITY #define FLASHC_FLASH_CTL_WORK_ECC_EN_Msk FLASHC_V2_FLASH_CTL_WORK_ECC_EN_Msk #define FLASHC_ECC_CTL_WORD_ADDR_Pos FLASHC_V2_ECC_CTL_WORD_ADDR_Pos #define FLASHC_ECC_CTL_WORD_ADDR_Msk FLASHC_V2_ECC_CTL_WORD_ADDR_Msk #define FLASHC_ECC_CTL_PARITY_Pos FLASHC_V2_ECC_CTL_PARITY_Pos #define FLASHC_ECC_CTL_PARITY_Msk FLASHC_V2_ECC_CTL_PARITY_Msk #define FLASHC_CM0_CA_CTL0_RAM_ECC_INJ_EN_Msk FLASHC_V2_CM0_CA_CTL0_RAM_ECC_INJ_EN_Msk #define FLASHC_FLASH_CTL_MAIN_ECC_EN_Msk FLASHC_V2_FLASH_CTL_MAIN_ECC_EN_Msk /******************************************************************************* * DW *******************************************************************************/ /* DW_CH_STRUCT.CH_CTL */ #define DW_CH_STRUCT_CH_CTL_P_Pos DW_CH_STRUCT_V2_CH_CTL_P_Pos #define DW_CH_STRUCT_CH_CTL_P_Msk DW_CH_STRUCT_V2_CH_CTL_P_Msk #define DW_CH_STRUCT_CH_CTL_NS_Pos DW_CH_STRUCT_V2_CH_CTL_NS_Pos #define DW_CH_STRUCT_CH_CTL_NS_Msk DW_CH_STRUCT_V2_CH_CTL_NS_Msk #define DW_CH_STRUCT_CH_CTL_B_Pos DW_CH_STRUCT_V2_CH_CTL_B_Pos #define DW_CH_STRUCT_CH_CTL_B_Msk DW_CH_STRUCT_V2_CH_CTL_B_Msk #define DW_CH_STRUCT_CH_CTL_PC_Pos DW_CH_STRUCT_V2_CH_CTL_PC_Pos #define DW_CH_STRUCT_CH_CTL_PC_Msk DW_CH_STRUCT_V2_CH_CTL_PC_Msk #define DW_CH_STRUCT_CH_CTL_PRIO_Pos DW_CH_STRUCT_V2_CH_CTL_PRIO_Pos #define DW_CH_STRUCT_CH_CTL_PRIO_Msk DW_CH_STRUCT_V2_CH_CTL_PRIO_Msk #define DW_CH_STRUCT_CH_CTL_PREEMPTABLE_Pos DW_CH_STRUCT_V2_CH_CTL_PREEMPTABLE_Pos #define DW_CH_STRUCT_CH_CTL_PREEMPTABLE_Msk DW_CH_STRUCT_V2_CH_CTL_PREEMPTABLE_Msk #define DW_CH_STRUCT_CH_CTL_ENABLED_Pos DW_CH_STRUCT_V2_CH_CTL_ENABLED_Pos #define DW_CH_STRUCT_CH_CTL_ENABLED_Msk DW_CH_STRUCT_V2_CH_CTL_ENABLED_Msk /* DW_CH_STRUCT.CH_STATUS */ #define DW_CH_STRUCT_CH_STATUS_INTR_CAUSE_Pos DW_CH_STRUCT_V2_CH_STATUS_INTR_CAUSE_Pos #define DW_CH_STRUCT_CH_STATUS_INTR_CAUSE_Msk DW_CH_STRUCT_V2_CH_STATUS_INTR_CAUSE_Msk #define DW_CH_STRUCT_CH_STATUS_PENDING_Pos DW_CH_STRUCT_V2_CH_STATUS_PENDING_Pos #define DW_CH_STRUCT_CH_STATUS_PENDING_Msk DW_CH_STRUCT_V2_CH_STATUS_PENDING_Msk /* DW_CH_STRUCT.CH_IDX */ #define DW_CH_STRUCT_CH_IDX_X_IDX_Pos DW_CH_STRUCT_V2_CH_IDX_X_IDX_Pos #define DW_CH_STRUCT_CH_IDX_X_IDX_Msk DW_CH_STRUCT_V2_CH_IDX_X_IDX_Msk #define DW_CH_STRUCT_CH_IDX_Y_IDX_Pos DW_CH_STRUCT_V2_CH_IDX_Y_IDX_Pos #define DW_CH_STRUCT_CH_IDX_Y_IDX_Msk DW_CH_STRUCT_V2_CH_IDX_Y_IDX_Msk /* DW_CH_STRUCT.CH_CURR_PTR */ #define DW_CH_STRUCT_CH_CURR_PTR_ADDR_Pos DW_CH_STRUCT_V2_CH_CURR_PTR_ADDR_Pos #define DW_CH_STRUCT_CH_CURR_PTR_ADDR_Msk DW_CH_STRUCT_V2_CH_CURR_PTR_ADDR_Msk /* DW_CH_STRUCT.INTR */ #define DW_CH_STRUCT_INTR_CH_Pos DW_CH_STRUCT_V2_INTR_CH_Pos #define DW_CH_STRUCT_INTR_CH_Msk DW_CH_STRUCT_V2_INTR_CH_Msk /* DW_CH_STRUCT.INTR_SET */ #define DW_CH_STRUCT_INTR_SET_CH_Pos DW_CH_STRUCT_V2_INTR_SET_CH_Pos #define DW_CH_STRUCT_INTR_SET_CH_Msk DW_CH_STRUCT_V2_INTR_SET_CH_Msk /* DW_CH_STRUCT.INTR_MASK */ #define DW_CH_STRUCT_INTR_MASK_CH_Pos DW_CH_STRUCT_V2_INTR_MASK_CH_Pos #define DW_CH_STRUCT_INTR_MASK_CH_Msk DW_CH_STRUCT_V2_INTR_MASK_CH_Msk /* DW_CH_STRUCT.INTR_MASKED */ #define DW_CH_STRUCT_INTR_MASKED_CH_Pos DW_CH_STRUCT_V2_INTR_MASKED_CH_Pos #define DW_CH_STRUCT_INTR_MASKED_CH_Msk DW_CH_STRUCT_V2_INTR_MASKED_CH_Msk /* DW_CH_STRUCT.SRAM_DATA0 */ #define DW_CH_STRUCT_SRAM_DATA0_DATA_Pos DW_CH_STRUCT_V2_SRAM_DATA0_DATA_Pos #define DW_CH_STRUCT_SRAM_DATA0_DATA_Msk DW_CH_STRUCT_V2_SRAM_DATA0_DATA_Msk /* DW_CH_STRUCT.SRAM_DATA1 */ #define DW_CH_STRUCT_SRAM_DATA1_DATA_Pos DW_CH_STRUCT_V2_SRAM_DATA1_DATA_Pos #define DW_CH_STRUCT_SRAM_DATA1_DATA_Msk DW_CH_STRUCT_V2_SRAM_DATA1_DATA_Msk /* DW_CH_STRUCT.TR_CMD */ #define DW_CH_STRUCT_TR_CMD_ACTIVATE_Pos DW_CH_STRUCT_V2_TR_CMD_ACTIVATE_Pos #define DW_CH_STRUCT_TR_CMD_ACTIVATE_Msk DW_CH_STRUCT_V2_TR_CMD_ACTIVATE_Msk /* DW.CTL */ #define DW_CTL_ECC_EN_Pos DW_CTL_ECC_EN_Pos #define DW_CTL_ECC_EN_Msk 0x1UL #define DW_CTL_ECC_INJ_EN_Pos DW_V2_CTL_ECC_INJ_EN_Pos #define DW_CTL_ECC_INJ_EN_Msk DW_V2_CTL_ECC_INJ_EN_Msk #define DW_CTL_ENABLED_Pos DW_V2_CTL_ENABLED_Pos #define DW_CTL_ENABLED_Msk DW_V2_CTL_ENABLED_Msk /* DW.STATUS */ #define DW_STATUS_P_Pos DW_V2_STATUS_P_Pos #define DW_STATUS_P_Msk DW_V2_STATUS_P_Msk #define DW_STATUS_NS_Pos DW_V2_STATUS_NS_Pos #define DW_STATUS_NS_Msk DW_V2_STATUS_NS_Msk #define DW_STATUS_B_Pos DW_V2_STATUS_B_Pos #define DW_STATUS_B_Msk DW_V2_STATUS_B_Msk #define DW_STATUS_PC_Pos DW_V2_STATUS_PC_Pos #define DW_STATUS_PC_Msk DW_V2_STATUS_PC_Msk #define DW_STATUS_PRIO_Pos DW_V2_STATUS_PRIO_Pos #define DW_STATUS_PRIO_Msk DW_V2_STATUS_PRIO_Msk #define DW_STATUS_PREEMPTABLE_Pos DW_V2_STATUS_PREEMPTABLE_Pos #define DW_STATUS_PREEMPTABLE_Msk DW_V2_STATUS_PREEMPTABLE_Msk #define DW_STATUS_CH_IDX_Pos DW_V2_STATUS_CH_IDX_Pos #define DW_STATUS_CH_IDX_Msk DW_V2_STATUS_CH_IDX_Msk #define DW_STATUS_STATE_Pos DW_V2_STATUS_STATE_Pos #define DW_STATUS_STATE_Msk DW_V2_STATUS_STATE_Msk #define DW_STATUS_ACTIVE_Pos DW_V2_STATUS_ACTIVE_Pos #define DW_STATUS_ACTIVE_Msk DW_V2_STATUS_ACTIVE_Msk /* DW.ACT_DESCR_CTL */ #define DW_ACT_DESCR_CTL_DATA_Pos DW_V2_ACT_DESCR_CTL_DATA_Pos #define DW_ACT_DESCR_CTL_DATA_Msk DW_V2_ACT_DESCR_CTL_DATA_Msk /* DW.ACT_DESCR_SRC */ #define DW_ACT_DESCR_SRC_DATA_Pos DW_V2_ACT_DESCR_SRC_DATA_Pos #define DW_ACT_DESCR_SRC_DATA_Msk DW_V2_ACT_DESCR_SRC_DATA_Msk /* DW.ACT_DESCR_DST */ #define DW_ACT_DESCR_DST_DATA_Pos DW_V2_ACT_DESCR_DST_DATA_Pos #define DW_ACT_DESCR_DST_DATA_Msk DW_V2_ACT_DESCR_DST_DATA_Msk /* DW.ACT_DESCR_X_CTL */ #define DW_ACT_DESCR_X_CTL_DATA_Pos DW_V2_ACT_DESCR_X_CTL_DATA_Pos #define DW_ACT_DESCR_X_CTL_DATA_Msk DW_V2_ACT_DESCR_X_CTL_DATA_Msk /* DW.ACT_DESCR_Y_CTL */ #define DW_ACT_DESCR_Y_CTL_DATA_Pos DW_V2_ACT_DESCR_Y_CTL_DATA_Pos #define DW_ACT_DESCR_Y_CTL_DATA_Msk DW_V2_ACT_DESCR_Y_CTL_DATA_Msk /* DW.ACT_DESCR_NEXT_PTR */ #define DW_ACT_DESCR_NEXT_PTR_ADDR_Pos DW_V2_ACT_DESCR_NEXT_PTR_ADDR_Pos #define DW_ACT_DESCR_NEXT_PTR_ADDR_Msk DW_V2_ACT_DESCR_NEXT_PTR_ADDR_Msk /* DW.ACT_SRC */ #define DW_ACT_SRC_SRC_ADDR_Pos DW_V2_ACT_SRC_SRC_ADDR_Pos #define DW_ACT_SRC_SRC_ADDR_Msk DW_V2_ACT_SRC_SRC_ADDR_Msk /* DW.ACT_DST */ #define DW_ACT_DST_DST_ADDR_Pos DW_V2_ACT_DST_DST_ADDR_Pos #define DW_ACT_DST_DST_ADDR_Msk DW_V2_ACT_DST_DST_ADDR_Msk /* DW.ECC_CTL */ #define DW_ECC_CTL_WORD_ADDR_Pos DW_V2_ECC_CTL_WORD_ADDR_Pos #define DW_ECC_CTL_WORD_ADDR_Msk DW_V2_ECC_CTL_WORD_ADDR_Msk #define DW_ECC_CTL_PARITY_Pos DW_V2_ECC_CTL_PARITY_Pos #define DW_ECC_CTL_PARITY_Msk DW_V2_ECC_CTL_PARITY_Msk /* DW.CRC_CTL */ #define DW_CRC_CTL_DATA_REVERSE_Pos DW_V2_CRC_CTL_DATA_REVERSE_Pos #define DW_CRC_CTL_DATA_REVERSE_Msk DW_V2_CRC_CTL_DATA_REVERSE_Msk #define DW_CRC_CTL_REM_REVERSE_Pos DW_V2_CRC_CTL_REM_REVERSE_Pos #define DW_CRC_CTL_REM_REVERSE_Msk DW_V2_CRC_CTL_REM_REVERSE_Msk /* DW.CRC_DATA_CTL */ #define DW_CRC_DATA_CTL_DATA_XOR_Pos DW_V2_CRC_DATA_CTL_DATA_XOR_Pos #define DW_CRC_DATA_CTL_DATA_XOR_Msk DW_V2_CRC_DATA_CTL_DATA_XOR_Msk /* DW.CRC_POL_CTL */ #define DW_CRC_POL_CTL_POLYNOMIAL_Pos DW_V2_CRC_POL_CTL_POLYNOMIAL_Pos #define DW_CRC_POL_CTL_POLYNOMIAL_Msk DW_V2_CRC_POL_CTL_POLYNOMIAL_Msk /* DW.CRC_LFSR_CTL */ #define DW_CRC_LFSR_CTL_LFSR32_Pos DW_V2_CRC_LFSR_CTL_LFSR32_Pos #define DW_CRC_LFSR_CTL_LFSR32_Msk DW_V2_CRC_LFSR_CTL_LFSR32_Msk /* DW.CRC_REM_CTL */ #define DW_CRC_REM_CTL_REM_XOR_Pos DW_V2_CRC_REM_CTL_REM_XOR_Pos #define DW_CRC_REM_CTL_REM_XOR_Msk DW_V2_CRC_REM_CTL_REM_XOR_Msk /* DW.CRC_REM_RESULT */ #define DW_CRC_REM_RESULT_REM_Pos DW_V2_CRC_REM_RESULT_REM_Pos #define DW_CRC_REM_RESULT_REM_Msk DW_V2_CRC_REM_RESULT_REM_Msk /******************************************************************************* * GPIO *******************************************************************************/ #define GPIO_PRT_SECTION_SIZE GPIO_PRT_V2_SECTION_SIZE #define GPIO_SECTION_SIZE GPIO_V2_SECTION_SIZE /* GPIO_PRT.OUT */ #define GPIO_PRT_OUT_OUT0_Pos GPIO_PRT_V2_OUT_OUT0_Pos #define GPIO_PRT_OUT_OUT0_Msk GPIO_PRT_V2_OUT_OUT0_Msk #define GPIO_PRT_OUT_OUT1_Pos GPIO_PRT_V2_OUT_OUT1_Pos #define GPIO_PRT_OUT_OUT1_Msk GPIO_PRT_V2_OUT_OUT1_Msk #define GPIO_PRT_OUT_OUT2_Pos GPIO_PRT_V2_OUT_OUT2_Pos #define GPIO_PRT_OUT_OUT2_Msk GPIO_PRT_V2_OUT_OUT2_Msk #define GPIO_PRT_OUT_OUT3_Pos GPIO_PRT_V2_OUT_OUT3_Pos #define GPIO_PRT_OUT_OUT3_Msk GPIO_PRT_V2_OUT_OUT3_Msk #define GPIO_PRT_OUT_OUT4_Pos GPIO_PRT_V2_OUT_OUT4_Pos #define GPIO_PRT_OUT_OUT4_Msk GPIO_PRT_V2_OUT_OUT4_Msk #define GPIO_PRT_OUT_OUT5_Pos GPIO_PRT_V2_OUT_OUT5_Pos #define GPIO_PRT_OUT_OUT5_Msk GPIO_PRT_V2_OUT_OUT5_Msk #define GPIO_PRT_OUT_OUT6_Pos GPIO_PRT_V2_OUT_OUT6_Pos #define GPIO_PRT_OUT_OUT6_Msk GPIO_PRT_V2_OUT_OUT6_Msk #define GPIO_PRT_OUT_OUT7_Pos GPIO_PRT_V2_OUT_OUT7_Pos #define GPIO_PRT_OUT_OUT7_Msk GPIO_PRT_V2_OUT_OUT7_Msk /* GPIO_PRT.OUT_CLR */ #define GPIO_PRT_OUT_CLR_OUT0_Pos GPIO_PRT_V2_OUT_CLR_OUT0_Pos #define GPIO_PRT_OUT_CLR_OUT0_Msk GPIO_PRT_V2_OUT_CLR_OUT0_Msk #define GPIO_PRT_OUT_CLR_OUT1_Pos GPIO_PRT_V2_OUT_CLR_OUT1_Pos #define GPIO_PRT_OUT_CLR_OUT1_Msk GPIO_PRT_V2_OUT_CLR_OUT1_Msk #define GPIO_PRT_OUT_CLR_OUT2_Pos GPIO_PRT_V2_OUT_CLR_OUT2_Pos #define GPIO_PRT_OUT_CLR_OUT2_Msk GPIO_PRT_V2_OUT_CLR_OUT2_Msk #define GPIO_PRT_OUT_CLR_OUT3_Pos GPIO_PRT_V2_OUT_CLR_OUT3_Pos #define GPIO_PRT_OUT_CLR_OUT3_Msk GPIO_PRT_V2_OUT_CLR_OUT3_Msk #define GPIO_PRT_OUT_CLR_OUT4_Pos GPIO_PRT_V2_OUT_CLR_OUT4_Pos #define GPIO_PRT_OUT_CLR_OUT4_Msk GPIO_PRT_V2_OUT_CLR_OUT4_Msk #define GPIO_PRT_OUT_CLR_OUT5_Pos GPIO_PRT_V2_OUT_CLR_OUT5_Pos #define GPIO_PRT_OUT_CLR_OUT5_Msk GPIO_PRT_V2_OUT_CLR_OUT5_Msk #define GPIO_PRT_OUT_CLR_OUT6_Pos GPIO_PRT_V2_OUT_CLR_OUT6_Pos #define GPIO_PRT_OUT_CLR_OUT6_Msk GPIO_PRT_V2_OUT_CLR_OUT6_Msk #define GPIO_PRT_OUT_CLR_OUT7_Pos GPIO_PRT_V2_OUT_CLR_OUT7_Pos #define GPIO_PRT_OUT_CLR_OUT7_Msk GPIO_PRT_V2_OUT_CLR_OUT7_Msk /* GPIO_PRT.OUT_SET */ #define GPIO_PRT_OUT_SET_OUT0_Pos GPIO_PRT_V2_OUT_SET_OUT0_Pos #define GPIO_PRT_OUT_SET_OUT0_Msk GPIO_PRT_V2_OUT_SET_OUT0_Msk #define GPIO_PRT_OUT_SET_OUT1_Pos GPIO_PRT_V2_OUT_SET_OUT1_Pos #define GPIO_PRT_OUT_SET_OUT1_Msk GPIO_PRT_V2_OUT_SET_OUT1_Msk #define GPIO_PRT_OUT_SET_OUT2_Pos GPIO_PRT_V2_OUT_SET_OUT2_Pos #define GPIO_PRT_OUT_SET_OUT2_Msk GPIO_PRT_V2_OUT_SET_OUT2_Msk #define GPIO_PRT_OUT_SET_OUT3_Pos GPIO_PRT_V2_OUT_SET_OUT3_Pos #define GPIO_PRT_OUT_SET_OUT3_Msk GPIO_PRT_V2_OUT_SET_OUT3_Msk #define GPIO_PRT_OUT_SET_OUT4_Pos GPIO_PRT_V2_OUT_SET_OUT4_Pos #define GPIO_PRT_OUT_SET_OUT4_Msk GPIO_PRT_V2_OUT_SET_OUT4_Msk #define GPIO_PRT_OUT_SET_OUT5_Pos GPIO_PRT_V2_OUT_SET_OUT5_Pos #define GPIO_PRT_OUT_SET_OUT5_Msk GPIO_PRT_V2_OUT_SET_OUT5_Msk #define GPIO_PRT_OUT_SET_OUT6_Pos GPIO_PRT_V2_OUT_SET_OUT6_Pos #define GPIO_PRT_OUT_SET_OUT6_Msk GPIO_PRT_V2_OUT_SET_OUT6_Msk #define GPIO_PRT_OUT_SET_OUT7_Pos GPIO_PRT_V2_OUT_SET_OUT7_Pos #define GPIO_PRT_OUT_SET_OUT7_Msk GPIO_PRT_V2_OUT_SET_OUT7_Msk /* GPIO_PRT.OUT_INV */ #define GPIO_PRT_OUT_INV_OUT0_Pos GPIO_PRT_V2_OUT_INV_OUT0_Pos #define GPIO_PRT_OUT_INV_OUT0_Msk GPIO_PRT_V2_OUT_INV_OUT0_Msk #define GPIO_PRT_OUT_INV_OUT1_Pos GPIO_PRT_V2_OUT_INV_OUT1_Pos #define GPIO_PRT_OUT_INV_OUT1_Msk GPIO_PRT_V2_OUT_INV_OUT1_Msk #define GPIO_PRT_OUT_INV_OUT2_Pos GPIO_PRT_V2_OUT_INV_OUT2_Pos #define GPIO_PRT_OUT_INV_OUT2_Msk GPIO_PRT_V2_OUT_INV_OUT2_Msk #define GPIO_PRT_OUT_INV_OUT3_Pos GPIO_PRT_V2_OUT_INV_OUT3_Pos #define GPIO_PRT_OUT_INV_OUT3_Msk GPIO_PRT_V2_OUT_INV_OUT3_Msk #define GPIO_PRT_OUT_INV_OUT4_Pos GPIO_PRT_V2_OUT_INV_OUT4_Pos #define GPIO_PRT_OUT_INV_OUT4_Msk GPIO_PRT_V2_OUT_INV_OUT4_Msk #define GPIO_PRT_OUT_INV_OUT5_Pos GPIO_PRT_V2_OUT_INV_OUT5_Pos #define GPIO_PRT_OUT_INV_OUT5_Msk GPIO_PRT_V2_OUT_INV_OUT5_Msk #define GPIO_PRT_OUT_INV_OUT6_Pos GPIO_PRT_V2_OUT_INV_OUT6_Pos #define GPIO_PRT_OUT_INV_OUT6_Msk GPIO_PRT_V2_OUT_INV_OUT6_Msk #define GPIO_PRT_OUT_INV_OUT7_Pos GPIO_PRT_V2_OUT_INV_OUT7_Pos #define GPIO_PRT_OUT_INV_OUT7_Msk GPIO_PRT_V2_OUT_INV_OUT7_Msk /* GPIO_PRT.IN */ #define GPIO_PRT_IN_IN0_Pos GPIO_PRT_V2_IN_IN0_Pos #define GPIO_PRT_IN_IN0_Msk GPIO_PRT_V2_IN_IN0_Msk #define GPIO_PRT_IN_IN1_Pos GPIO_PRT_V2_IN_IN1_Pos #define GPIO_PRT_IN_IN1_Msk GPIO_PRT_V2_IN_IN1_Msk #define GPIO_PRT_IN_IN2_Pos GPIO_PRT_V2_IN_IN2_Pos #define GPIO_PRT_IN_IN2_Msk GPIO_PRT_V2_IN_IN2_Msk #define GPIO_PRT_IN_IN3_Pos GPIO_PRT_V2_IN_IN3_Pos #define GPIO_PRT_IN_IN3_Msk GPIO_PRT_V2_IN_IN3_Msk #define GPIO_PRT_IN_IN4_Pos GPIO_PRT_V2_IN_IN4_Pos #define GPIO_PRT_IN_IN4_Msk GPIO_PRT_V2_IN_IN4_Msk #define GPIO_PRT_IN_IN5_Pos GPIO_PRT_V2_IN_IN5_Pos #define GPIO_PRT_IN_IN5_Msk GPIO_PRT_V2_IN_IN5_Msk #define GPIO_PRT_IN_IN6_Pos GPIO_PRT_V2_IN_IN6_Pos #define GPIO_PRT_IN_IN6_Msk GPIO_PRT_V2_IN_IN6_Msk #define GPIO_PRT_IN_IN7_Pos GPIO_PRT_V2_IN_IN7_Pos #define GPIO_PRT_IN_IN7_Msk GPIO_PRT_V2_IN_IN7_Msk #define GPIO_PRT_IN_FLT_IN_Pos GPIO_PRT_V2_IN_FLT_IN_Pos #define GPIO_PRT_IN_FLT_IN_Msk GPIO_PRT_V2_IN_FLT_IN_Msk /* GPIO_PRT.INTR */ #define GPIO_PRT_INTR_EDGE0_Pos GPIO_PRT_V2_INTR_EDGE0_Pos #define GPIO_PRT_INTR_EDGE0_Msk GPIO_PRT_V2_INTR_EDGE0_Msk #define GPIO_PRT_INTR_EDGE1_Pos GPIO_PRT_V2_INTR_EDGE1_Pos #define GPIO_PRT_INTR_EDGE1_Msk GPIO_PRT_V2_INTR_EDGE1_Msk #define GPIO_PRT_INTR_EDGE2_Pos GPIO_PRT_V2_INTR_EDGE2_Pos #define GPIO_PRT_INTR_EDGE2_Msk GPIO_PRT_V2_INTR_EDGE2_Msk #define GPIO_PRT_INTR_EDGE3_Pos GPIO_PRT_V2_INTR_EDGE3_Pos #define GPIO_PRT_INTR_EDGE3_Msk GPIO_PRT_V2_INTR_EDGE3_Msk #define GPIO_PRT_INTR_EDGE4_Pos GPIO_PRT_V2_INTR_EDGE4_Pos #define GPIO_PRT_INTR_EDGE4_Msk GPIO_PRT_V2_INTR_EDGE4_Msk #define GPIO_PRT_INTR_EDGE5_Pos GPIO_PRT_V2_INTR_EDGE5_Pos #define GPIO_PRT_INTR_EDGE5_Msk GPIO_PRT_V2_INTR_EDGE5_Msk #define GPIO_PRT_INTR_EDGE6_Pos GPIO_PRT_V2_INTR_EDGE6_Pos #define GPIO_PRT_INTR_EDGE6_Msk GPIO_PRT_V2_INTR_EDGE6_Msk #define GPIO_PRT_INTR_EDGE7_Pos GPIO_PRT_V2_INTR_EDGE7_Pos #define GPIO_PRT_INTR_EDGE7_Msk GPIO_PRT_V2_INTR_EDGE7_Msk #define GPIO_PRT_INTR_FLT_EDGE_Pos GPIO_PRT_V2_INTR_FLT_EDGE_Pos #define GPIO_PRT_INTR_FLT_EDGE_Msk GPIO_PRT_V2_INTR_FLT_EDGE_Msk #define GPIO_PRT_INTR_IN_IN0_Pos GPIO_PRT_V2_INTR_IN_IN0_Pos #define GPIO_PRT_INTR_IN_IN0_Msk GPIO_PRT_V2_INTR_IN_IN0_Msk #define GPIO_PRT_INTR_IN_IN1_Pos GPIO_PRT_V2_INTR_IN_IN1_Pos #define GPIO_PRT_INTR_IN_IN1_Msk GPIO_PRT_V2_INTR_IN_IN1_Msk #define GPIO_PRT_INTR_IN_IN2_Pos GPIO_PRT_V2_INTR_IN_IN2_Pos #define GPIO_PRT_INTR_IN_IN2_Msk GPIO_PRT_V2_INTR_IN_IN2_Msk #define GPIO_PRT_INTR_IN_IN3_Pos GPIO_PRT_V2_INTR_IN_IN3_Pos #define GPIO_PRT_INTR_IN_IN3_Msk GPIO_PRT_V2_INTR_IN_IN3_Msk #define GPIO_PRT_INTR_IN_IN4_Pos GPIO_PRT_V2_INTR_IN_IN4_Pos #define GPIO_PRT_INTR_IN_IN4_Msk GPIO_PRT_V2_INTR_IN_IN4_Msk #define GPIO_PRT_INTR_IN_IN5_Pos GPIO_PRT_V2_INTR_IN_IN5_Pos #define GPIO_PRT_INTR_IN_IN5_Msk GPIO_PRT_V2_INTR_IN_IN5_Msk #define GPIO_PRT_INTR_IN_IN6_Pos GPIO_PRT_V2_INTR_IN_IN6_Pos #define GPIO_PRT_INTR_IN_IN6_Msk GPIO_PRT_V2_INTR_IN_IN6_Msk #define GPIO_PRT_INTR_IN_IN7_Pos GPIO_PRT_V2_INTR_IN_IN7_Pos #define GPIO_PRT_INTR_IN_IN7_Msk GPIO_PRT_V2_INTR_IN_IN7_Msk #define GPIO_PRT_INTR_FLT_IN_IN_Pos GPIO_PRT_V2_INTR_FLT_IN_IN_Pos #define GPIO_PRT_INTR_FLT_IN_IN_Msk GPIO_PRT_V2_INTR_FLT_IN_IN_Msk /* GPIO_PRT.INTR_MASK */ #define GPIO_PRT_INTR_MASK_EDGE0_Pos GPIO_PRT_V2_INTR_MASK_EDGE0_Pos #define GPIO_PRT_INTR_MASK_EDGE0_Msk GPIO_PRT_V2_INTR_MASK_EDGE0_Msk #define GPIO_PRT_INTR_MASK_EDGE1_Pos GPIO_PRT_V2_INTR_MASK_EDGE1_Pos #define GPIO_PRT_INTR_MASK_EDGE1_Msk GPIO_PRT_V2_INTR_MASK_EDGE1_Msk #define GPIO_PRT_INTR_MASK_EDGE2_Pos GPIO_PRT_V2_INTR_MASK_EDGE2_Pos #define GPIO_PRT_INTR_MASK_EDGE2_Msk GPIO_PRT_V2_INTR_MASK_EDGE2_Msk #define GPIO_PRT_INTR_MASK_EDGE3_Pos GPIO_PRT_V2_INTR_MASK_EDGE3_Pos #define GPIO_PRT_INTR_MASK_EDGE3_Msk GPIO_PRT_V2_INTR_MASK_EDGE3_Msk #define GPIO_PRT_INTR_MASK_EDGE4_Pos GPIO_PRT_V2_INTR_MASK_EDGE4_Pos #define GPIO_PRT_INTR_MASK_EDGE4_Msk GPIO_PRT_V2_INTR_MASK_EDGE4_Msk #define GPIO_PRT_INTR_MASK_EDGE5_Pos GPIO_PRT_V2_INTR_MASK_EDGE5_Pos #define GPIO_PRT_INTR_MASK_EDGE5_Msk GPIO_PRT_V2_INTR_MASK_EDGE5_Msk #define GPIO_PRT_INTR_MASK_EDGE6_Pos GPIO_PRT_V2_INTR_MASK_EDGE6_Pos #define GPIO_PRT_INTR_MASK_EDGE6_Msk GPIO_PRT_V2_INTR_MASK_EDGE6_Msk #define GPIO_PRT_INTR_MASK_EDGE7_Pos GPIO_PRT_V2_INTR_MASK_EDGE7_Pos #define GPIO_PRT_INTR_MASK_EDGE7_Msk GPIO_PRT_V2_INTR_MASK_EDGE7_Msk #define GPIO_PRT_INTR_MASK_FLT_EDGE_Pos GPIO_PRT_V2_INTR_MASK_FLT_EDGE_Pos #define GPIO_PRT_INTR_MASK_FLT_EDGE_Msk GPIO_PRT_V2_INTR_MASK_FLT_EDGE_Msk /* GPIO_PRT.INTR_MASKED */ #define GPIO_PRT_INTR_MASKED_EDGE0_Pos GPIO_PRT_V2_INTR_MASKED_EDGE0_Pos #define GPIO_PRT_INTR_MASKED_EDGE0_Msk GPIO_PRT_V2_INTR_MASKED_EDGE0_Msk #define GPIO_PRT_INTR_MASKED_EDGE1_Pos GPIO_PRT_V2_INTR_MASKED_EDGE1_Pos #define GPIO_PRT_INTR_MASKED_EDGE1_Msk GPIO_PRT_V2_INTR_MASKED_EDGE1_Msk #define GPIO_PRT_INTR_MASKED_EDGE2_Pos GPIO_PRT_V2_INTR_MASKED_EDGE2_Pos #define GPIO_PRT_INTR_MASKED_EDGE2_Msk GPIO_PRT_V2_INTR_MASKED_EDGE2_Msk #define GPIO_PRT_INTR_MASKED_EDGE3_Pos GPIO_PRT_V2_INTR_MASKED_EDGE3_Pos #define GPIO_PRT_INTR_MASKED_EDGE3_Msk GPIO_PRT_V2_INTR_MASKED_EDGE3_Msk #define GPIO_PRT_INTR_MASKED_EDGE4_Pos GPIO_PRT_V2_INTR_MASKED_EDGE4_Pos #define GPIO_PRT_INTR_MASKED_EDGE4_Msk GPIO_PRT_V2_INTR_MASKED_EDGE4_Msk #define GPIO_PRT_INTR_MASKED_EDGE5_Pos GPIO_PRT_V2_INTR_MASKED_EDGE5_Pos #define GPIO_PRT_INTR_MASKED_EDGE5_Msk GPIO_PRT_V2_INTR_MASKED_EDGE5_Msk #define GPIO_PRT_INTR_MASKED_EDGE6_Pos GPIO_PRT_V2_INTR_MASKED_EDGE6_Pos #define GPIO_PRT_INTR_MASKED_EDGE6_Msk GPIO_PRT_V2_INTR_MASKED_EDGE6_Msk #define GPIO_PRT_INTR_MASKED_EDGE7_Pos GPIO_PRT_V2_INTR_MASKED_EDGE7_Pos #define GPIO_PRT_INTR_MASKED_EDGE7_Msk GPIO_PRT_V2_INTR_MASKED_EDGE7_Msk #define GPIO_PRT_INTR_MASKED_FLT_EDGE_Pos GPIO_PRT_V2_INTR_MASKED_FLT_EDGE_Pos #define GPIO_PRT_INTR_MASKED_FLT_EDGE_Msk GPIO_PRT_V2_INTR_MASKED_FLT_EDGE_Msk /* GPIO_PRT.INTR_SET */ #define GPIO_PRT_INTR_SET_EDGE0_Pos GPIO_PRT_V2_INTR_SET_EDGE0_Pos #define GPIO_PRT_INTR_SET_EDGE0_Msk GPIO_PRT_V2_INTR_SET_EDGE0_Msk #define GPIO_PRT_INTR_SET_EDGE1_Pos GPIO_PRT_V2_INTR_SET_EDGE1_Pos #define GPIO_PRT_INTR_SET_EDGE1_Msk GPIO_PRT_V2_INTR_SET_EDGE1_Msk #define GPIO_PRT_INTR_SET_EDGE2_Pos GPIO_PRT_V2_INTR_SET_EDGE2_Pos #define GPIO_PRT_INTR_SET_EDGE2_Msk GPIO_PRT_V2_INTR_SET_EDGE2_Msk #define GPIO_PRT_INTR_SET_EDGE3_Pos GPIO_PRT_V2_INTR_SET_EDGE3_Pos #define GPIO_PRT_INTR_SET_EDGE3_Msk GPIO_PRT_V2_INTR_SET_EDGE3_Msk #define GPIO_PRT_INTR_SET_EDGE4_Pos GPIO_PRT_V2_INTR_SET_EDGE4_Pos #define GPIO_PRT_INTR_SET_EDGE4_Msk GPIO_PRT_V2_INTR_SET_EDGE4_Msk #define GPIO_PRT_INTR_SET_EDGE5_Pos GPIO_PRT_V2_INTR_SET_EDGE5_Pos #define GPIO_PRT_INTR_SET_EDGE5_Msk GPIO_PRT_V2_INTR_SET_EDGE5_Msk #define GPIO_PRT_INTR_SET_EDGE6_Pos GPIO_PRT_V2_INTR_SET_EDGE6_Pos #define GPIO_PRT_INTR_SET_EDGE6_Msk GPIO_PRT_V2_INTR_SET_EDGE6_Msk #define GPIO_PRT_INTR_SET_EDGE7_Pos GPIO_PRT_V2_INTR_SET_EDGE7_Pos #define GPIO_PRT_INTR_SET_EDGE7_Msk GPIO_PRT_V2_INTR_SET_EDGE7_Msk #define GPIO_PRT_INTR_SET_FLT_EDGE_Pos GPIO_PRT_V2_INTR_SET_FLT_EDGE_Pos #define GPIO_PRT_INTR_SET_FLT_EDGE_Msk GPIO_PRT_V2_INTR_SET_FLT_EDGE_Msk /* GPIO_PRT.INTR_CFG */ #define GPIO_PRT_INTR_CFG_EDGE0_SEL_Pos GPIO_PRT_V2_INTR_CFG_EDGE0_SEL_Pos #define GPIO_PRT_INTR_CFG_EDGE0_SEL_Msk GPIO_PRT_V2_INTR_CFG_EDGE0_SEL_Msk #define GPIO_PRT_INTR_CFG_EDGE1_SEL_Pos GPIO_PRT_V2_INTR_CFG_EDGE1_SEL_Pos #define GPIO_PRT_INTR_CFG_EDGE1_SEL_Msk GPIO_PRT_V2_INTR_CFG_EDGE1_SEL_Msk #define GPIO_PRT_INTR_CFG_EDGE2_SEL_Pos GPIO_PRT_V2_INTR_CFG_EDGE2_SEL_Pos #define GPIO_PRT_INTR_CFG_EDGE2_SEL_Msk GPIO_PRT_V2_INTR_CFG_EDGE2_SEL_Msk #define GPIO_PRT_INTR_CFG_EDGE3_SEL_Pos GPIO_PRT_V2_INTR_CFG_EDGE3_SEL_Pos #define GPIO_PRT_INTR_CFG_EDGE3_SEL_Msk GPIO_PRT_V2_INTR_CFG_EDGE3_SEL_Msk #define GPIO_PRT_INTR_CFG_EDGE4_SEL_Pos GPIO_PRT_V2_INTR_CFG_EDGE4_SEL_Pos #define GPIO_PRT_INTR_CFG_EDGE4_SEL_Msk GPIO_PRT_V2_INTR_CFG_EDGE4_SEL_Msk #define GPIO_PRT_INTR_CFG_EDGE5_SEL_Pos GPIO_PRT_V2_INTR_CFG_EDGE5_SEL_Pos #define GPIO_PRT_INTR_CFG_EDGE5_SEL_Msk GPIO_PRT_V2_INTR_CFG_EDGE5_SEL_Msk #define GPIO_PRT_INTR_CFG_EDGE6_SEL_Pos GPIO_PRT_V2_INTR_CFG_EDGE6_SEL_Pos #define GPIO_PRT_INTR_CFG_EDGE6_SEL_Msk GPIO_PRT_V2_INTR_CFG_EDGE6_SEL_Msk #define GPIO_PRT_INTR_CFG_EDGE7_SEL_Pos GPIO_PRT_V2_INTR_CFG_EDGE7_SEL_Pos #define GPIO_PRT_INTR_CFG_EDGE7_SEL_Msk GPIO_PRT_V2_INTR_CFG_EDGE7_SEL_Msk #define GPIO_PRT_INTR_CFG_FLT_EDGE_SEL_Pos GPIO_PRT_V2_INTR_CFG_FLT_EDGE_SEL_Pos #define GPIO_PRT_INTR_CFG_FLT_EDGE_SEL_Msk GPIO_PRT_V2_INTR_CFG_FLT_EDGE_SEL_Msk #define GPIO_PRT_INTR_CFG_FLT_SEL_Pos GPIO_PRT_V2_INTR_CFG_FLT_SEL_Pos #define GPIO_PRT_INTR_CFG_FLT_SEL_Msk GPIO_PRT_V2_INTR_CFG_FLT_SEL_Msk /* GPIO_PRT.CFG */ #define GPIO_PRT_CFG_DRIVE_MODE0_Pos GPIO_PRT_V2_CFG_DRIVE_MODE0_Pos #define GPIO_PRT_CFG_DRIVE_MODE0_Msk GPIO_PRT_V2_CFG_DRIVE_MODE0_Msk #define GPIO_PRT_CFG_IN_EN0_Pos GPIO_PRT_V2_CFG_IN_EN0_Pos #define GPIO_PRT_CFG_IN_EN0_Msk GPIO_PRT_V2_CFG_IN_EN0_Msk #define GPIO_PRT_CFG_DRIVE_MODE1_Pos GPIO_PRT_V2_CFG_DRIVE_MODE1_Pos #define GPIO_PRT_CFG_DRIVE_MODE1_Msk GPIO_PRT_V2_CFG_DRIVE_MODE1_Msk #define GPIO_PRT_CFG_IN_EN1_Pos GPIO_PRT_V2_CFG_IN_EN1_Pos #define GPIO_PRT_CFG_IN_EN1_Msk GPIO_PRT_V2_CFG_IN_EN1_Msk #define GPIO_PRT_CFG_DRIVE_MODE2_Pos GPIO_PRT_V2_CFG_DRIVE_MODE2_Pos #define GPIO_PRT_CFG_DRIVE_MODE2_Msk GPIO_PRT_V2_CFG_DRIVE_MODE2_Msk #define GPIO_PRT_CFG_IN_EN2_Pos GPIO_PRT_V2_CFG_IN_EN2_Pos #define GPIO_PRT_CFG_IN_EN2_Msk GPIO_PRT_V2_CFG_IN_EN2_Msk #define GPIO_PRT_CFG_DRIVE_MODE3_Pos GPIO_PRT_V2_CFG_DRIVE_MODE3_Pos #define GPIO_PRT_CFG_DRIVE_MODE3_Msk GPIO_PRT_V2_CFG_DRIVE_MODE3_Msk #define GPIO_PRT_CFG_IN_EN3_Pos GPIO_PRT_V2_CFG_IN_EN3_Pos #define GPIO_PRT_CFG_IN_EN3_Msk GPIO_PRT_V2_CFG_IN_EN3_Msk #define GPIO_PRT_CFG_DRIVE_MODE4_Pos GPIO_PRT_V2_CFG_DRIVE_MODE4_Pos #define GPIO_PRT_CFG_DRIVE_MODE4_Msk GPIO_PRT_V2_CFG_DRIVE_MODE4_Msk #define GPIO_PRT_CFG_IN_EN4_Pos GPIO_PRT_V2_CFG_IN_EN4_Pos #define GPIO_PRT_CFG_IN_EN4_Msk GPIO_PRT_V2_CFG_IN_EN4_Msk #define GPIO_PRT_CFG_DRIVE_MODE5_Pos GPIO_PRT_V2_CFG_DRIVE_MODE5_Pos #define GPIO_PRT_CFG_DRIVE_MODE5_Msk GPIO_PRT_V2_CFG_DRIVE_MODE5_Msk #define GPIO_PRT_CFG_IN_EN5_Pos GPIO_PRT_V2_CFG_IN_EN5_Pos #define GPIO_PRT_CFG_IN_EN5_Msk GPIO_PRT_V2_CFG_IN_EN5_Msk #define GPIO_PRT_CFG_DRIVE_MODE6_Pos GPIO_PRT_V2_CFG_DRIVE_MODE6_Pos #define GPIO_PRT_CFG_DRIVE_MODE6_Msk GPIO_PRT_V2_CFG_DRIVE_MODE6_Msk #define GPIO_PRT_CFG_IN_EN6_Pos GPIO_PRT_V2_CFG_IN_EN6_Pos #define GPIO_PRT_CFG_IN_EN6_Msk GPIO_PRT_V2_CFG_IN_EN6_Msk #define GPIO_PRT_CFG_DRIVE_MODE7_Pos GPIO_PRT_V2_CFG_DRIVE_MODE7_Pos #define GPIO_PRT_CFG_DRIVE_MODE7_Msk GPIO_PRT_V2_CFG_DRIVE_MODE7_Msk #define GPIO_PRT_CFG_IN_EN7_Pos GPIO_PRT_V2_CFG_IN_EN7_Pos #define GPIO_PRT_CFG_IN_EN7_Msk GPIO_PRT_V2_CFG_IN_EN7_Msk /* GPIO_PRT.CFG_IN */ #define GPIO_PRT_CFG_IN_VTRIP_SEL0_0_Pos GPIO_PRT_V2_CFG_IN_VTRIP_SEL0_0_Pos #define GPIO_PRT_CFG_IN_VTRIP_SEL0_0_Msk GPIO_PRT_V2_CFG_IN_VTRIP_SEL0_0_Msk #define GPIO_PRT_CFG_IN_VTRIP_SEL1_0_Pos GPIO_PRT_V2_CFG_IN_VTRIP_SEL1_0_Pos #define GPIO_PRT_CFG_IN_VTRIP_SEL1_0_Msk GPIO_PRT_V2_CFG_IN_VTRIP_SEL1_0_Msk #define GPIO_PRT_CFG_IN_VTRIP_SEL2_0_Pos GPIO_PRT_V2_CFG_IN_VTRIP_SEL2_0_Pos #define GPIO_PRT_CFG_IN_VTRIP_SEL2_0_Msk GPIO_PRT_V2_CFG_IN_VTRIP_SEL2_0_Msk #define GPIO_PRT_CFG_IN_VTRIP_SEL3_0_Pos GPIO_PRT_V2_CFG_IN_VTRIP_SEL3_0_Pos #define GPIO_PRT_CFG_IN_VTRIP_SEL3_0_Msk GPIO_PRT_V2_CFG_IN_VTRIP_SEL3_0_Msk #define GPIO_PRT_CFG_IN_VTRIP_SEL4_0_Pos GPIO_PRT_V2_CFG_IN_VTRIP_SEL4_0_Pos #define GPIO_PRT_CFG_IN_VTRIP_SEL4_0_Msk GPIO_PRT_V2_CFG_IN_VTRIP_SEL4_0_Msk #define GPIO_PRT_CFG_IN_VTRIP_SEL5_0_Pos GPIO_PRT_V2_CFG_IN_VTRIP_SEL5_0_Pos #define GPIO_PRT_CFG_IN_VTRIP_SEL5_0_Msk GPIO_PRT_V2_CFG_IN_VTRIP_SEL5_0_Msk #define GPIO_PRT_CFG_IN_VTRIP_SEL6_0_Pos GPIO_PRT_V2_CFG_IN_VTRIP_SEL6_0_Pos #define GPIO_PRT_CFG_IN_VTRIP_SEL6_0_Msk GPIO_PRT_V2_CFG_IN_VTRIP_SEL6_0_Msk #define GPIO_PRT_CFG_IN_VTRIP_SEL7_0_Pos GPIO_PRT_V2_CFG_IN_VTRIP_SEL7_0_Pos #define GPIO_PRT_CFG_IN_VTRIP_SEL7_0_Msk GPIO_PRT_V2_CFG_IN_VTRIP_SEL7_0_Msk /* GPIO_PRT.CFG_OUT */ #define GPIO_PRT_CFG_OUT_SLOW0_Pos GPIO_PRT_V2_CFG_OUT_SLOW0_Pos #define GPIO_PRT_CFG_OUT_SLOW0_Msk GPIO_PRT_V2_CFG_OUT_SLOW0_Msk #define GPIO_PRT_CFG_OUT_SLOW1_Pos GPIO_PRT_V2_CFG_OUT_SLOW1_Pos #define GPIO_PRT_CFG_OUT_SLOW1_Msk GPIO_PRT_V2_CFG_OUT_SLOW1_Msk #define GPIO_PRT_CFG_OUT_SLOW2_Pos GPIO_PRT_V2_CFG_OUT_SLOW2_Pos #define GPIO_PRT_CFG_OUT_SLOW2_Msk GPIO_PRT_V2_CFG_OUT_SLOW2_Msk #define GPIO_PRT_CFG_OUT_SLOW3_Pos GPIO_PRT_V2_CFG_OUT_SLOW3_Pos #define GPIO_PRT_CFG_OUT_SLOW3_Msk GPIO_PRT_V2_CFG_OUT_SLOW3_Msk #define GPIO_PRT_CFG_OUT_SLOW4_Pos GPIO_PRT_V2_CFG_OUT_SLOW4_Pos #define GPIO_PRT_CFG_OUT_SLOW4_Msk GPIO_PRT_V2_CFG_OUT_SLOW4_Msk #define GPIO_PRT_CFG_OUT_SLOW5_Pos GPIO_PRT_V2_CFG_OUT_SLOW5_Pos #define GPIO_PRT_CFG_OUT_SLOW5_Msk GPIO_PRT_V2_CFG_OUT_SLOW5_Msk #define GPIO_PRT_CFG_OUT_SLOW6_Pos GPIO_PRT_V2_CFG_OUT_SLOW6_Pos #define GPIO_PRT_CFG_OUT_SLOW6_Msk GPIO_PRT_V2_CFG_OUT_SLOW6_Msk #define GPIO_PRT_CFG_OUT_SLOW7_Pos GPIO_PRT_V2_CFG_OUT_SLOW7_Pos #define GPIO_PRT_CFG_OUT_SLOW7_Msk GPIO_PRT_V2_CFG_OUT_SLOW7_Msk #define GPIO_PRT_CFG_OUT_DRIVE_SEL0_Pos GPIO_PRT_V2_CFG_OUT_DRIVE_SEL0_Pos #define GPIO_PRT_CFG_OUT_DRIVE_SEL0_Msk GPIO_PRT_V2_CFG_OUT_DRIVE_SEL0_Msk #define GPIO_PRT_CFG_OUT_DRIVE_SEL1_Pos GPIO_PRT_V2_CFG_OUT_DRIVE_SEL1_Pos #define GPIO_PRT_CFG_OUT_DRIVE_SEL1_Msk GPIO_PRT_V2_CFG_OUT_DRIVE_SEL1_Msk #define GPIO_PRT_CFG_OUT_DRIVE_SEL2_Pos GPIO_PRT_V2_CFG_OUT_DRIVE_SEL2_Pos #define GPIO_PRT_CFG_OUT_DRIVE_SEL2_Msk GPIO_PRT_V2_CFG_OUT_DRIVE_SEL2_Msk #define GPIO_PRT_CFG_OUT_DRIVE_SEL3_Pos GPIO_PRT_V2_CFG_OUT_DRIVE_SEL3_Pos #define GPIO_PRT_CFG_OUT_DRIVE_SEL3_Msk GPIO_PRT_V2_CFG_OUT_DRIVE_SEL3_Msk #define GPIO_PRT_CFG_OUT_DRIVE_SEL4_Pos GPIO_PRT_V2_CFG_OUT_DRIVE_SEL4_Pos #define GPIO_PRT_CFG_OUT_DRIVE_SEL4_Msk GPIO_PRT_V2_CFG_OUT_DRIVE_SEL4_Msk #define GPIO_PRT_CFG_OUT_DRIVE_SEL5_Pos GPIO_PRT_V2_CFG_OUT_DRIVE_SEL5_Pos #define GPIO_PRT_CFG_OUT_DRIVE_SEL5_Msk GPIO_PRT_V2_CFG_OUT_DRIVE_SEL5_Msk #define GPIO_PRT_CFG_OUT_DRIVE_SEL6_Pos GPIO_PRT_V2_CFG_OUT_DRIVE_SEL6_Pos #define GPIO_PRT_CFG_OUT_DRIVE_SEL6_Msk GPIO_PRT_V2_CFG_OUT_DRIVE_SEL6_Msk #define GPIO_PRT_CFG_OUT_DRIVE_SEL7_Pos GPIO_PRT_V2_CFG_OUT_DRIVE_SEL7_Pos #define GPIO_PRT_CFG_OUT_DRIVE_SEL7_Msk GPIO_PRT_V2_CFG_OUT_DRIVE_SEL7_Msk /* GPIO_PRT.CFG_SIO */ #define GPIO_PRT_CFG_SIO_VREG_EN01_Pos GPIO_PRT_V2_CFG_SIO_VREG_EN01_Pos #define GPIO_PRT_CFG_SIO_VREG_EN01_Msk GPIO_PRT_V2_CFG_SIO_VREG_EN01_Msk #define GPIO_PRT_CFG_SIO_IBUF_SEL01_Pos GPIO_PRT_V2_CFG_SIO_IBUF_SEL01_Pos #define GPIO_PRT_CFG_SIO_IBUF_SEL01_Msk GPIO_PRT_V2_CFG_SIO_IBUF_SEL01_Msk #define GPIO_PRT_CFG_SIO_VTRIP_SEL01_Pos GPIO_PRT_V2_CFG_SIO_VTRIP_SEL01_Pos #define GPIO_PRT_CFG_SIO_VTRIP_SEL01_Msk GPIO_PRT_V2_CFG_SIO_VTRIP_SEL01_Msk #define GPIO_PRT_CFG_SIO_VREF_SEL01_Pos GPIO_PRT_V2_CFG_SIO_VREF_SEL01_Pos #define GPIO_PRT_CFG_SIO_VREF_SEL01_Msk GPIO_PRT_V2_CFG_SIO_VREF_SEL01_Msk #define GPIO_PRT_CFG_SIO_VOH_SEL01_Pos GPIO_PRT_V2_CFG_SIO_VOH_SEL01_Pos #define GPIO_PRT_CFG_SIO_VOH_SEL01_Msk GPIO_PRT_V2_CFG_SIO_VOH_SEL01_Msk #define GPIO_PRT_CFG_SIO_VREG_EN23_Pos GPIO_PRT_V2_CFG_SIO_VREG_EN23_Pos #define GPIO_PRT_CFG_SIO_VREG_EN23_Msk GPIO_PRT_V2_CFG_SIO_VREG_EN23_Msk #define GPIO_PRT_CFG_SIO_IBUF_SEL23_Pos GPIO_PRT_V2_CFG_SIO_IBUF_SEL23_Pos #define GPIO_PRT_CFG_SIO_IBUF_SEL23_Msk GPIO_PRT_V2_CFG_SIO_IBUF_SEL23_Msk #define GPIO_PRT_CFG_SIO_VTRIP_SEL23_Pos GPIO_PRT_V2_CFG_SIO_VTRIP_SEL23_Pos #define GPIO_PRT_CFG_SIO_VTRIP_SEL23_Msk GPIO_PRT_V2_CFG_SIO_VTRIP_SEL23_Msk #define GPIO_PRT_CFG_SIO_VREF_SEL23_Pos GPIO_PRT_V2_CFG_SIO_VREF_SEL23_Pos #define GPIO_PRT_CFG_SIO_VREF_SEL23_Msk GPIO_PRT_V2_CFG_SIO_VREF_SEL23_Msk #define GPIO_PRT_CFG_SIO_VOH_SEL23_Pos GPIO_PRT_V2_CFG_SIO_VOH_SEL23_Pos #define GPIO_PRT_CFG_SIO_VOH_SEL23_Msk GPIO_PRT_V2_CFG_SIO_VOH_SEL23_Msk #define GPIO_PRT_CFG_SIO_VREG_EN45_Pos GPIO_PRT_V2_CFG_SIO_VREG_EN45_Pos #define GPIO_PRT_CFG_SIO_VREG_EN45_Msk GPIO_PRT_V2_CFG_SIO_VREG_EN45_Msk #define GPIO_PRT_CFG_SIO_IBUF_SEL45_Pos GPIO_PRT_V2_CFG_SIO_IBUF_SEL45_Pos #define GPIO_PRT_CFG_SIO_IBUF_SEL45_Msk GPIO_PRT_V2_CFG_SIO_IBUF_SEL45_Msk #define GPIO_PRT_CFG_SIO_VTRIP_SEL45_Pos GPIO_PRT_V2_CFG_SIO_VTRIP_SEL45_Pos #define GPIO_PRT_CFG_SIO_VTRIP_SEL45_Msk GPIO_PRT_V2_CFG_SIO_VTRIP_SEL45_Msk #define GPIO_PRT_CFG_SIO_VREF_SEL45_Pos GPIO_PRT_V2_CFG_SIO_VREF_SEL45_Pos #define GPIO_PRT_CFG_SIO_VREF_SEL45_Msk GPIO_PRT_V2_CFG_SIO_VREF_SEL45_Msk #define GPIO_PRT_CFG_SIO_VOH_SEL45_Pos GPIO_PRT_V2_CFG_SIO_VOH_SEL45_Pos #define GPIO_PRT_CFG_SIO_VOH_SEL45_Msk GPIO_PRT_V2_CFG_SIO_VOH_SEL45_Msk #define GPIO_PRT_CFG_SIO_VREG_EN67_Pos GPIO_PRT_V2_CFG_SIO_VREG_EN67_Pos #define GPIO_PRT_CFG_SIO_VREG_EN67_Msk GPIO_PRT_V2_CFG_SIO_VREG_EN67_Msk #define GPIO_PRT_CFG_SIO_IBUF_SEL67_Pos GPIO_PRT_V2_CFG_SIO_IBUF_SEL67_Pos #define GPIO_PRT_CFG_SIO_IBUF_SEL67_Msk GPIO_PRT_V2_CFG_SIO_IBUF_SEL67_Msk #define GPIO_PRT_CFG_SIO_VTRIP_SEL67_Pos GPIO_PRT_V2_CFG_SIO_VTRIP_SEL67_Pos #define GPIO_PRT_CFG_SIO_VTRIP_SEL67_Msk GPIO_PRT_V2_CFG_SIO_VTRIP_SEL67_Msk #define GPIO_PRT_CFG_SIO_VREF_SEL67_Pos GPIO_PRT_V2_CFG_SIO_VREF_SEL67_Pos #define GPIO_PRT_CFG_SIO_VREF_SEL67_Msk GPIO_PRT_V2_CFG_SIO_VREF_SEL67_Msk #define GPIO_PRT_CFG_SIO_VOH_SEL67_Pos GPIO_PRT_V2_CFG_SIO_VOH_SEL67_Pos #define GPIO_PRT_CFG_SIO_VOH_SEL67_Msk GPIO_PRT_V2_CFG_SIO_VOH_SEL67_Msk /* GPIO_PRT.CFG_IN_AUTOLVL */ #define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL0_1_Pos GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL0_1_Pos #define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL0_1_Msk GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL0_1_Msk #define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL1_1_Pos GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL1_1_Pos #define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL1_1_Msk GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL1_1_Msk #define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL2_1_Pos GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL2_1_Pos #define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL2_1_Msk GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL2_1_Msk #define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL3_1_Pos GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL3_1_Pos #define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL3_1_Msk GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL3_1_Msk #define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL4_1_Pos GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL4_1_Pos #define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL4_1_Msk GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL4_1_Msk #define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL5_1_Pos GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL5_1_Pos #define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL5_1_Msk GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL5_1_Msk #define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL6_1_Pos GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL6_1_Pos #define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL6_1_Msk GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL6_1_Msk #define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL7_1_Pos GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL7_1_Pos #define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL7_1_Msk GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL7_1_Msk /* GPIO.INTR_CAUSE0 */ #define GPIO_INTR_CAUSE0_PORT_INT_Pos GPIO_V2_INTR_CAUSE0_PORT_INT_Pos #define GPIO_INTR_CAUSE0_PORT_INT_Msk GPIO_V2_INTR_CAUSE0_PORT_INT_Msk /* GPIO.INTR_CAUSE1 */ #define GPIO_INTR_CAUSE1_PORT_INT_Pos GPIO_V2_INTR_CAUSE1_PORT_INT_Pos #define GPIO_INTR_CAUSE1_PORT_INT_Msk GPIO_V2_INTR_CAUSE1_PORT_INT_Msk /* GPIO.INTR_CAUSE2 */ #define GPIO_INTR_CAUSE2_PORT_INT_Pos GPIO_V2_INTR_CAUSE2_PORT_INT_Pos #define GPIO_INTR_CAUSE2_PORT_INT_Msk GPIO_V2_INTR_CAUSE2_PORT_INT_Msk /* GPIO.INTR_CAUSE3 */ #define GPIO_INTR_CAUSE3_PORT_INT_Pos GPIO_V2_INTR_CAUSE3_PORT_INT_Pos #define GPIO_INTR_CAUSE3_PORT_INT_Msk GPIO_V2_INTR_CAUSE3_PORT_INT_Msk /* GPIO.VDD_ACTIVE */ #define GPIO_VDD_ACTIVE_VDDIO_ACTIVE_Pos GPIO_V2_VDD_ACTIVE_VDDIO_ACTIVE_Pos #define GPIO_VDD_ACTIVE_VDDIO_ACTIVE_Msk GPIO_V2_VDD_ACTIVE_VDDIO_ACTIVE_Msk #define GPIO_VDD_ACTIVE_VDDA_ACTIVE_Pos GPIO_V2_VDD_ACTIVE_VDDA_ACTIVE_Pos #define GPIO_VDD_ACTIVE_VDDA_ACTIVE_Msk GPIO_V2_VDD_ACTIVE_VDDA_ACTIVE_Msk #define GPIO_VDD_ACTIVE_VDDD_ACTIVE_Pos GPIO_V2_VDD_ACTIVE_VDDD_ACTIVE_Pos #define GPIO_VDD_ACTIVE_VDDD_ACTIVE_Msk GPIO_V2_VDD_ACTIVE_VDDD_ACTIVE_Msk /* GPIO.VDD_INTR */ #define GPIO_VDD_INTR_VDDIO_ACTIVE_Pos GPIO_V2_VDD_INTR_VDDIO_ACTIVE_Pos #define GPIO_VDD_INTR_VDDIO_ACTIVE_Msk GPIO_V2_VDD_INTR_VDDIO_ACTIVE_Msk #define GPIO_VDD_INTR_VDDA_ACTIVE_Pos GPIO_V2_VDD_INTR_VDDA_ACTIVE_Pos #define GPIO_VDD_INTR_VDDA_ACTIVE_Msk GPIO_V2_VDD_INTR_VDDA_ACTIVE_Msk #define GPIO_VDD_INTR_VDDD_ACTIVE_Pos GPIO_V2_VDD_INTR_VDDD_ACTIVE_Pos #define GPIO_VDD_INTR_VDDD_ACTIVE_Msk GPIO_V2_VDD_INTR_VDDD_ACTIVE_Msk /* GPIO.VDD_INTR_MASK */ #define GPIO_VDD_INTR_MASK_VDDIO_ACTIVE_Pos GPIO_V2_VDD_INTR_MASK_VDDIO_ACTIVE_Pos #define GPIO_VDD_INTR_MASK_VDDIO_ACTIVE_Msk GPIO_V2_VDD_INTR_MASK_VDDIO_ACTIVE_Msk #define GPIO_VDD_INTR_MASK_VDDA_ACTIVE_Pos GPIO_V2_VDD_INTR_MASK_VDDA_ACTIVE_Pos #define GPIO_VDD_INTR_MASK_VDDA_ACTIVE_Msk GPIO_V2_VDD_INTR_MASK_VDDA_ACTIVE_Msk #define GPIO_VDD_INTR_MASK_VDDD_ACTIVE_Pos GPIO_V2_VDD_INTR_MASK_VDDD_ACTIVE_Pos #define GPIO_VDD_INTR_MASK_VDDD_ACTIVE_Msk GPIO_V2_VDD_INTR_MASK_VDDD_ACTIVE_Msk /* GPIO.VDD_INTR_MASKED */ #define GPIO_VDD_INTR_MASKED_VDDIO_ACTIVE_Pos GPIO_V2_VDD_INTR_MASKED_VDDIO_ACTIVE_Pos #define GPIO_VDD_INTR_MASKED_VDDIO_ACTIVE_Msk GPIO_V2_VDD_INTR_MASKED_VDDIO_ACTIVE_Msk #define GPIO_VDD_INTR_MASKED_VDDA_ACTIVE_Pos GPIO_V2_VDD_INTR_MASKED_VDDA_ACTIVE_Pos #define GPIO_VDD_INTR_MASKED_VDDA_ACTIVE_Msk GPIO_V2_VDD_INTR_MASKED_VDDA_ACTIVE_Msk #define GPIO_VDD_INTR_MASKED_VDDD_ACTIVE_Pos GPIO_V2_VDD_INTR_MASKED_VDDD_ACTIVE_Pos #define GPIO_VDD_INTR_MASKED_VDDD_ACTIVE_Msk GPIO_V2_VDD_INTR_MASKED_VDDD_ACTIVE_Msk /* GPIO.VDD_INTR_SET */ #define GPIO_VDD_INTR_SET_VDDIO_ACTIVE_Pos GPIO_V2_VDD_INTR_SET_VDDIO_ACTIVE_Pos #define GPIO_VDD_INTR_SET_VDDIO_ACTIVE_Msk GPIO_V2_VDD_INTR_SET_VDDIO_ACTIVE_Msk #define GPIO_VDD_INTR_SET_VDDA_ACTIVE_Pos GPIO_V2_VDD_INTR_SET_VDDA_ACTIVE_Pos #define GPIO_VDD_INTR_SET_VDDA_ACTIVE_Msk GPIO_V2_VDD_INTR_SET_VDDA_ACTIVE_Msk #define GPIO_VDD_INTR_SET_VDDD_ACTIVE_Pos GPIO_V2_VDD_INTR_SET_VDDD_ACTIVE_Pos #define GPIO_VDD_INTR_SET_VDDD_ACTIVE_Msk GPIO_V2_VDD_INTR_SET_VDDD_ACTIVE_Msk /******************************************************************************* * HSIOM *******************************************************************************/ #define HSIOM_PRT_SECTION_SIZE HSIOM_PRT_V2_SECTION_SIZE #define HSIOM_SECTION_SIZE HSIOM_V2_SECTION_SIZE /* HSIOM_PRT.PORT_SEL0 */ #define HSIOM_PRT_PORT_SEL0_IO0_SEL_Pos HSIOM_PRT_V2_PORT_SEL0_IO0_SEL_Pos #define HSIOM_PRT_PORT_SEL0_IO0_SEL_Msk HSIOM_PRT_V2_PORT_SEL0_IO0_SEL_Msk #define HSIOM_PRT_PORT_SEL0_IO1_SEL_Pos HSIOM_PRT_V2_PORT_SEL0_IO1_SEL_Pos #define HSIOM_PRT_PORT_SEL0_IO1_SEL_Msk HSIOM_PRT_V2_PORT_SEL0_IO1_SEL_Msk #define HSIOM_PRT_PORT_SEL0_IO2_SEL_Pos HSIOM_PRT_V2_PORT_SEL0_IO2_SEL_Pos #define HSIOM_PRT_PORT_SEL0_IO2_SEL_Msk HSIOM_PRT_V2_PORT_SEL0_IO2_SEL_Msk #define HSIOM_PRT_PORT_SEL0_IO3_SEL_Pos HSIOM_PRT_V2_PORT_SEL0_IO3_SEL_Pos #define HSIOM_PRT_PORT_SEL0_IO3_SEL_Msk HSIOM_PRT_V2_PORT_SEL0_IO3_SEL_Msk /* HSIOM_PRT.PORT_SEL1 */ #define HSIOM_PRT_PORT_SEL1_IO4_SEL_Pos HSIOM_PRT_V2_PORT_SEL1_IO4_SEL_Pos #define HSIOM_PRT_PORT_SEL1_IO4_SEL_Msk HSIOM_PRT_V2_PORT_SEL1_IO4_SEL_Msk #define HSIOM_PRT_PORT_SEL1_IO5_SEL_Pos HSIOM_PRT_V2_PORT_SEL1_IO5_SEL_Pos #define HSIOM_PRT_PORT_SEL1_IO5_SEL_Msk HSIOM_PRT_V2_PORT_SEL1_IO5_SEL_Msk #define HSIOM_PRT_PORT_SEL1_IO6_SEL_Pos HSIOM_PRT_V2_PORT_SEL1_IO6_SEL_Pos #define HSIOM_PRT_PORT_SEL1_IO6_SEL_Msk HSIOM_PRT_V2_PORT_SEL1_IO6_SEL_Msk #define HSIOM_PRT_PORT_SEL1_IO7_SEL_Pos HSIOM_PRT_V2_PORT_SEL1_IO7_SEL_Pos #define HSIOM_PRT_PORT_SEL1_IO7_SEL_Msk HSIOM_PRT_V2_PORT_SEL1_IO7_SEL_Msk /* HSIOM.AMUX_SPLIT_CTL */ #define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Pos HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Pos #define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk #define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Pos HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Pos #define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk #define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_S0_Pos HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_S0_Pos #define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_S0_Msk HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_S0_Msk #define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Pos HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SL_Pos #define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk #define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Pos HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SR_Pos #define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk #define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_S0_Pos HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_S0_Pos #define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_S0_Msk HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_S0_Msk /* HSIOM.MONITOR_CTL_0 */ #define HSIOM_MONITOR_CTL_0_MONITOR_EN_Pos HSIOM_V2_MONITOR_CTL_0_MONITOR_EN_Pos #define HSIOM_MONITOR_CTL_0_MONITOR_EN_Msk HSIOM_V2_MONITOR_CTL_0_MONITOR_EN_Msk /* HSIOM.MONITOR_CTL_1 */ #define HSIOM_MONITOR_CTL_1_MONITOR_EN_Pos HSIOM_V2_MONITOR_CTL_1_MONITOR_EN_Pos #define HSIOM_MONITOR_CTL_1_MONITOR_EN_Msk HSIOM_V2_MONITOR_CTL_1_MONITOR_EN_Msk /* HSIOM.MONITOR_CTL_2 */ #define HSIOM_MONITOR_CTL_2_MONITOR_EN_Pos HSIOM_V2_MONITOR_CTL_2_MONITOR_EN_Pos #define HSIOM_MONITOR_CTL_2_MONITOR_EN_Msk HSIOM_V2_MONITOR_CTL_2_MONITOR_EN_Msk /* HSIOM.MONITOR_CTL_3 */ #define HSIOM_MONITOR_CTL_3_MONITOR_EN_Pos HSIOM_V2_MONITOR_CTL_3_MONITOR_EN_Pos #define HSIOM_MONITOR_CTL_3_MONITOR_EN_Msk HSIOM_V2_MONITOR_CTL_3_MONITOR_EN_Msk /* HSIOM.ALT_JTAG_EN */ #define HSIOM_ALT_JTAG_EN_ENABLE_Pos HSIOM_V2_ALT_JTAG_EN_ENABLE_Pos #define HSIOM_ALT_JTAG_EN_ENABLE_Msk HSIOM_V2_ALT_JTAG_EN_ENABLE_Msk /******************************************************************************* * IPC *******************************************************************************/ /* IPC_STRUCT.ACQUIRE */ #define IPC_STRUCT_ACQUIRE_P_Pos IPC_STRUCT_V2_ACQUIRE_P_Pos #define IPC_STRUCT_ACQUIRE_P_Msk IPC_STRUCT_V2_ACQUIRE_P_Msk #define IPC_STRUCT_ACQUIRE_NS_Pos IPC_STRUCT_V2_ACQUIRE_NS_Pos #define IPC_STRUCT_ACQUIRE_NS_Msk IPC_STRUCT_V2_ACQUIRE_NS_Msk #define IPC_STRUCT_ACQUIRE_PC_Pos IPC_STRUCT_V2_ACQUIRE_PC_Pos #define IPC_STRUCT_ACQUIRE_PC_Msk IPC_STRUCT_V2_ACQUIRE_PC_Msk #define IPC_STRUCT_ACQUIRE_MS_Pos IPC_STRUCT_V2_ACQUIRE_MS_Pos #define IPC_STRUCT_ACQUIRE_MS_Msk IPC_STRUCT_V2_ACQUIRE_MS_Msk #define IPC_STRUCT_ACQUIRE_SUCCESS_Pos IPC_STRUCT_V2_ACQUIRE_SUCCESS_Pos #define IPC_STRUCT_ACQUIRE_SUCCESS_Msk IPC_STRUCT_V2_ACQUIRE_SUCCESS_Msk /* IPC_STRUCT.RELEASE */ #define IPC_STRUCT_RELEASE_INTR_RELEASE_Pos IPC_STRUCT_V2_RELEASE_INTR_RELEASE_Pos #define IPC_STRUCT_RELEASE_INTR_RELEASE_Msk IPC_STRUCT_V2_RELEASE_INTR_RELEASE_Msk /* IPC_STRUCT.NOTIFY */ #define IPC_STRUCT_NOTIFY_INTR_NOTIFY_Pos IPC_STRUCT_V2_NOTIFY_INTR_NOTIFY_Pos #define IPC_STRUCT_NOTIFY_INTR_NOTIFY_Msk IPC_STRUCT_V2_NOTIFY_INTR_NOTIFY_Msk /* IPC_STRUCT.DATA0 */ #define IPC_STRUCT_DATA0_DATA_Pos IPC_STRUCT_V2_DATA0_DATA_Pos #define IPC_STRUCT_DATA0_DATA_Msk IPC_STRUCT_V2_DATA0_DATA_Msk /* IPC_STRUCT.DATA1 */ #define IPC_STRUCT_DATA1_DATA_Pos IPC_STRUCT_V2_DATA1_DATA_Pos #define IPC_STRUCT_DATA1_DATA_Msk IPC_STRUCT_V2_DATA1_DATA_Msk /* IPC_STRUCT.LOCK_STATUS */ #define IPC_STRUCT_LOCK_STATUS_P_Pos IPC_STRUCT_V2_LOCK_STATUS_P_Pos #define IPC_STRUCT_LOCK_STATUS_P_Msk IPC_STRUCT_V2_LOCK_STATUS_P_Msk #define IPC_STRUCT_LOCK_STATUS_NS_Pos IPC_STRUCT_V2_LOCK_STATUS_NS_Pos #define IPC_STRUCT_LOCK_STATUS_NS_Msk IPC_STRUCT_V2_LOCK_STATUS_NS_Msk #define IPC_STRUCT_LOCK_STATUS_PC_Pos IPC_STRUCT_V2_LOCK_STATUS_PC_Pos #define IPC_STRUCT_LOCK_STATUS_PC_Msk IPC_STRUCT_V2_LOCK_STATUS_PC_Msk #define IPC_STRUCT_LOCK_STATUS_MS_Pos IPC_STRUCT_V2_LOCK_STATUS_MS_Pos #define IPC_STRUCT_LOCK_STATUS_MS_Msk IPC_STRUCT_V2_LOCK_STATUS_MS_Msk #define IPC_STRUCT_LOCK_STATUS_ACQUIRED_Pos IPC_STRUCT_V2_LOCK_STATUS_ACQUIRED_Pos #define IPC_STRUCT_LOCK_STATUS_ACQUIRED_Msk IPC_STRUCT_V2_LOCK_STATUS_ACQUIRED_Msk /* IPC_INTR_STRUCT.INTR */ #define IPC_INTR_STRUCT_INTR_RELEASE_Pos IPC_INTR_STRUCT_V2_INTR_RELEASE_Pos #define IPC_INTR_STRUCT_INTR_RELEASE_Msk IPC_INTR_STRUCT_V2_INTR_RELEASE_Msk #define IPC_INTR_STRUCT_INTR_NOTIFY_Pos IPC_INTR_STRUCT_V2_INTR_NOTIFY_Pos #define IPC_INTR_STRUCT_INTR_NOTIFY_Msk IPC_INTR_STRUCT_V2_INTR_NOTIFY_Msk /* IPC_INTR_STRUCT.INTR_SET */ #define IPC_INTR_STRUCT_INTR_SET_RELEASE_Pos IPC_INTR_STRUCT_V2_INTR_SET_RELEASE_Pos #define IPC_INTR_STRUCT_INTR_SET_RELEASE_Msk IPC_INTR_STRUCT_V2_INTR_SET_RELEASE_Msk #define IPC_INTR_STRUCT_INTR_SET_NOTIFY_Pos IPC_INTR_STRUCT_V2_INTR_SET_NOTIFY_Pos #define IPC_INTR_STRUCT_INTR_SET_NOTIFY_Msk IPC_INTR_STRUCT_V2_INTR_SET_NOTIFY_Msk /* IPC_INTR_STRUCT.INTR_MASK */ #define IPC_INTR_STRUCT_INTR_MASK_RELEASE_Pos IPC_INTR_STRUCT_V2_INTR_MASK_RELEASE_Pos #define IPC_INTR_STRUCT_INTR_MASK_RELEASE_Msk IPC_INTR_STRUCT_V2_INTR_MASK_RELEASE_Msk #define IPC_INTR_STRUCT_INTR_MASK_NOTIFY_Pos IPC_INTR_STRUCT_V2_INTR_MASK_NOTIFY_Pos #define IPC_INTR_STRUCT_INTR_MASK_NOTIFY_Msk IPC_INTR_STRUCT_V2_INTR_MASK_NOTIFY_Msk /* IPC_INTR_STRUCT.INTR_MASKED */ #define IPC_INTR_STRUCT_INTR_MASKED_RELEASE_Pos IPC_INTR_STRUCT_V2_INTR_MASKED_RELEASE_Pos #define IPC_INTR_STRUCT_INTR_MASKED_RELEASE_Msk IPC_INTR_STRUCT_V2_INTR_MASKED_RELEASE_Msk #define IPC_INTR_STRUCT_INTR_MASKED_NOTIFY_Pos IPC_INTR_STRUCT_V2_INTR_MASKED_NOTIFY_Pos #define IPC_INTR_STRUCT_INTR_MASKED_NOTIFY_Msk IPC_INTR_STRUCT_V2_INTR_MASKED_NOTIFY_Msk /******************************************************************************* * PERI *******************************************************************************/ /* PERI_GR.CLOCK_CTL */ #define PERI_GR_CLOCK_CTL_INT8_DIV_Pos PERI_GR_V2_CLOCK_CTL_INT8_DIV_Pos #define PERI_GR_CLOCK_CTL_INT8_DIV_Msk PERI_GR_V2_CLOCK_CTL_INT8_DIV_Msk /* PERI_GR.SL_CTL */ #define PERI_GR_SL_CTL_ENABLED_0_Pos PERI_GR_V2_SL_CTL_ENABLED_0_Pos #define PERI_GR_SL_CTL_ENABLED_0_Msk PERI_GR_V2_SL_CTL_ENABLED_0_Msk #define PERI_GR_SL_CTL_ENABLED_1_Pos PERI_GR_V2_SL_CTL_ENABLED_1_Pos #define PERI_GR_SL_CTL_ENABLED_1_Msk PERI_GR_V2_SL_CTL_ENABLED_1_Msk #define PERI_GR_SL_CTL_ENABLED_2_Pos PERI_GR_V2_SL_CTL_ENABLED_2_Pos #define PERI_GR_SL_CTL_ENABLED_2_Msk PERI_GR_V2_SL_CTL_ENABLED_2_Msk #define PERI_GR_SL_CTL_ENABLED_3_Pos PERI_GR_V2_SL_CTL_ENABLED_3_Pos #define PERI_GR_SL_CTL_ENABLED_3_Msk PERI_GR_V2_SL_CTL_ENABLED_3_Msk #define PERI_GR_SL_CTL_ENABLED_4_Pos PERI_GR_V2_SL_CTL_ENABLED_4_Pos #define PERI_GR_SL_CTL_ENABLED_4_Msk PERI_GR_V2_SL_CTL_ENABLED_4_Msk #define PERI_GR_SL_CTL_ENABLED_5_Pos PERI_GR_V2_SL_CTL_ENABLED_5_Pos #define PERI_GR_SL_CTL_ENABLED_5_Msk PERI_GR_V2_SL_CTL_ENABLED_5_Msk #define PERI_GR_SL_CTL_ENABLED_6_Pos PERI_GR_V2_SL_CTL_ENABLED_6_Pos #define PERI_GR_SL_CTL_ENABLED_6_Msk PERI_GR_V2_SL_CTL_ENABLED_6_Msk #define PERI_GR_SL_CTL_ENABLED_7_Pos PERI_GR_V2_SL_CTL_ENABLED_7_Pos #define PERI_GR_SL_CTL_ENABLED_7_Msk PERI_GR_V2_SL_CTL_ENABLED_7_Msk #define PERI_GR_SL_CTL_ENABLED_8_Pos PERI_GR_V2_SL_CTL_ENABLED_8_Pos #define PERI_GR_SL_CTL_ENABLED_8_Msk PERI_GR_V2_SL_CTL_ENABLED_8_Msk #define PERI_GR_SL_CTL_ENABLED_9_Pos PERI_GR_V2_SL_CTL_ENABLED_9_Pos #define PERI_GR_SL_CTL_ENABLED_9_Msk PERI_GR_V2_SL_CTL_ENABLED_9_Msk #define PERI_GR_SL_CTL_ENABLED_10_Pos PERI_GR_V2_SL_CTL_ENABLED_10_Pos #define PERI_GR_SL_CTL_ENABLED_10_Msk PERI_GR_V2_SL_CTL_ENABLED_10_Msk #define PERI_GR_SL_CTL_ENABLED_11_Pos PERI_GR_V2_SL_CTL_ENABLED_11_Pos #define PERI_GR_SL_CTL_ENABLED_11_Msk PERI_GR_V2_SL_CTL_ENABLED_11_Msk #define PERI_GR_SL_CTL_ENABLED_12_Pos PERI_GR_V2_SL_CTL_ENABLED_12_Pos #define PERI_GR_SL_CTL_ENABLED_12_Msk PERI_GR_V2_SL_CTL_ENABLED_12_Msk #define PERI_GR_SL_CTL_ENABLED_13_Pos PERI_GR_V2_SL_CTL_ENABLED_13_Pos #define PERI_GR_SL_CTL_ENABLED_13_Msk PERI_GR_V2_SL_CTL_ENABLED_13_Msk #define PERI_GR_SL_CTL_ENABLED_14_Pos PERI_GR_V2_SL_CTL_ENABLED_14_Pos #define PERI_GR_SL_CTL_ENABLED_14_Msk PERI_GR_V2_SL_CTL_ENABLED_14_Msk #define PERI_GR_SL_CTL_ENABLED_15_Pos PERI_GR_V2_SL_CTL_ENABLED_15_Pos #define PERI_GR_SL_CTL_ENABLED_15_Msk PERI_GR_V2_SL_CTL_ENABLED_15_Msk #define PERI_GR_SL_CTL_DISABLED_0_Pos PERI_GR_V2_SL_CTL_DISABLED_0_Pos #define PERI_GR_SL_CTL_DISABLED_0_Msk PERI_GR_V2_SL_CTL_DISABLED_0_Msk #define PERI_GR_SL_CTL_DISABLED_1_Pos PERI_GR_V2_SL_CTL_DISABLED_1_Pos #define PERI_GR_SL_CTL_DISABLED_1_Msk PERI_GR_V2_SL_CTL_DISABLED_1_Msk #define PERI_GR_SL_CTL_DISABLED_2_Pos PERI_GR_V2_SL_CTL_DISABLED_2_Pos #define PERI_GR_SL_CTL_DISABLED_2_Msk PERI_GR_V2_SL_CTL_DISABLED_2_Msk #define PERI_GR_SL_CTL_DISABLED_3_Pos PERI_GR_V2_SL_CTL_DISABLED_3_Pos #define PERI_GR_SL_CTL_DISABLED_3_Msk PERI_GR_V2_SL_CTL_DISABLED_3_Msk #define PERI_GR_SL_CTL_DISABLED_4_Pos PERI_GR_V2_SL_CTL_DISABLED_4_Pos #define PERI_GR_SL_CTL_DISABLED_4_Msk PERI_GR_V2_SL_CTL_DISABLED_4_Msk #define PERI_GR_SL_CTL_DISABLED_5_Pos PERI_GR_V2_SL_CTL_DISABLED_5_Pos #define PERI_GR_SL_CTL_DISABLED_5_Msk PERI_GR_V2_SL_CTL_DISABLED_5_Msk #define PERI_GR_SL_CTL_DISABLED_6_Pos PERI_GR_V2_SL_CTL_DISABLED_6_Pos #define PERI_GR_SL_CTL_DISABLED_6_Msk PERI_GR_V2_SL_CTL_DISABLED_6_Msk #define PERI_GR_SL_CTL_DISABLED_7_Pos PERI_GR_V2_SL_CTL_DISABLED_7_Pos #define PERI_GR_SL_CTL_DISABLED_7_Msk PERI_GR_V2_SL_CTL_DISABLED_7_Msk #define PERI_GR_SL_CTL_DISABLED_8_Pos PERI_GR_V2_SL_CTL_DISABLED_8_Pos #define PERI_GR_SL_CTL_DISABLED_8_Msk PERI_GR_V2_SL_CTL_DISABLED_8_Msk #define PERI_GR_SL_CTL_DISABLED_9_Pos PERI_GR_V2_SL_CTL_DISABLED_9_Pos #define PERI_GR_SL_CTL_DISABLED_9_Msk PERI_GR_V2_SL_CTL_DISABLED_9_Msk #define PERI_GR_SL_CTL_DISABLED_10_Pos PERI_GR_V2_SL_CTL_DISABLED_10_Pos #define PERI_GR_SL_CTL_DISABLED_10_Msk PERI_GR_V2_SL_CTL_DISABLED_10_Msk #define PERI_GR_SL_CTL_DISABLED_11_Pos PERI_GR_V2_SL_CTL_DISABLED_11_Pos #define PERI_GR_SL_CTL_DISABLED_11_Msk PERI_GR_V2_SL_CTL_DISABLED_11_Msk #define PERI_GR_SL_CTL_DISABLED_12_Pos PERI_GR_V2_SL_CTL_DISABLED_12_Pos #define PERI_GR_SL_CTL_DISABLED_12_Msk PERI_GR_V2_SL_CTL_DISABLED_12_Msk #define PERI_GR_SL_CTL_DISABLED_13_Pos PERI_GR_V2_SL_CTL_DISABLED_13_Pos #define PERI_GR_SL_CTL_DISABLED_13_Msk PERI_GR_V2_SL_CTL_DISABLED_13_Msk #define PERI_GR_SL_CTL_DISABLED_14_Pos PERI_GR_V2_SL_CTL_DISABLED_14_Pos #define PERI_GR_SL_CTL_DISABLED_14_Msk PERI_GR_V2_SL_CTL_DISABLED_14_Msk #define PERI_GR_SL_CTL_DISABLED_15_Pos PERI_GR_V2_SL_CTL_DISABLED_15_Pos #define PERI_GR_SL_CTL_DISABLED_15_Msk PERI_GR_V2_SL_CTL_DISABLED_15_Msk /* PERI_TR_GR.TR_CTL */ #define PERI_TR_GR_TR_CTL_TR_SEL_Pos PERI_TR_GR_V2_TR_CTL_TR_SEL_Pos #define PERI_TR_GR_TR_CTL_TR_SEL_Msk PERI_TR_GR_V2_TR_CTL_TR_SEL_Msk #define PERI_TR_GR_TR_CTL_TR_INV_Pos PERI_TR_GR_V2_TR_CTL_TR_INV_Pos #define PERI_TR_GR_TR_CTL_TR_INV_Msk PERI_TR_GR_V2_TR_CTL_TR_INV_Msk #define PERI_TR_GR_TR_CTL_TR_EDGE_Pos PERI_TR_GR_V2_TR_CTL_TR_EDGE_Pos #define PERI_TR_GR_TR_CTL_TR_EDGE_Msk PERI_TR_GR_V2_TR_CTL_TR_EDGE_Msk #define PERI_TR_GR_TR_CTL_DBG_FREEZE_EN_Pos PERI_TR_GR_V2_TR_CTL_DBG_FREEZE_EN_Pos #define PERI_TR_GR_TR_CTL_DBG_FREEZE_EN_Msk PERI_TR_GR_V2_TR_CTL_DBG_FREEZE_EN_Msk /* PERI_TR_1TO1_GR.TR_CTL */ #define PERI_TR_1TO1_GR_TR_CTL_TR_SEL_Pos PERI_TR_1TO1_GR_V2_TR_CTL_TR_SEL_Pos #define PERI_TR_1TO1_GR_TR_CTL_TR_SEL_Msk PERI_TR_1TO1_GR_V2_TR_CTL_TR_SEL_Msk #define PERI_TR_1TO1_GR_TR_CTL_TR_INV_Pos PERI_TR_1TO1_GR_V2_TR_CTL_TR_INV_Pos #define PERI_TR_1TO1_GR_TR_CTL_TR_INV_Msk PERI_TR_1TO1_GR_V2_TR_CTL_TR_INV_Msk #define PERI_TR_1TO1_GR_TR_CTL_TR_EDGE_Pos PERI_TR_1TO1_GR_V2_TR_CTL_TR_EDGE_Pos #define PERI_TR_1TO1_GR_TR_CTL_TR_EDGE_Msk PERI_TR_1TO1_GR_V2_TR_CTL_TR_EDGE_Msk #define PERI_TR_1TO1_GR_TR_CTL_DBG_FREEZE_EN_Pos PERI_TR_1TO1_GR_V2_TR_CTL_DBG_FREEZE_EN_Pos #define PERI_TR_1TO1_GR_TR_CTL_DBG_FREEZE_EN_Msk PERI_TR_1TO1_GR_V2_TR_CTL_DBG_FREEZE_EN_Msk /* PERI.TIMEOUT_CTL */ #define PERI_TIMEOUT_CTL_TIMEOUT_Pos PERI_V2_TIMEOUT_CTL_TIMEOUT_Pos #define PERI_TIMEOUT_CTL_TIMEOUT_Msk PERI_V2_TIMEOUT_CTL_TIMEOUT_Msk /* PERI.TR_CMD */ #define PERI_TR_CMD_TR_SEL_Pos PERI_V2_TR_CMD_TR_SEL_Pos #define PERI_TR_CMD_TR_SEL_Msk PERI_V2_TR_CMD_TR_SEL_Msk #define PERI_TR_CMD_GROUP_SEL_Pos PERI_V2_TR_CMD_GROUP_SEL_Pos /* Bits 8-12, values: 1 - 15: trigger mulitplxer groups, values: 16 - 31: trigger 1-to-1 groups. */ /* Not remapping to PERI_V2_TR_CMD_GROUP_SEL_Msk as this mask is defined as 0x1F00UL which has Bit 12 mask value */ /* The define is required for PDL code for PERI version less than 3. Version >= 3 has different check for bit 12 */ #define PERI_TR_CMD_GROUP_SEL_Msk 0x0F00UL #define PERI_TR_CMD_TR_EDGE_Pos PERI_V2_TR_CMD_TR_EDGE_Pos #define PERI_TR_CMD_TR_EDGE_Msk PERI_V2_TR_CMD_TR_EDGE_Msk #define PERI_TR_CMD_OUT_SEL_Pos PERI_V2_TR_CMD_OUT_SEL_Pos #define PERI_TR_CMD_OUT_SEL_Msk PERI_V2_TR_CMD_OUT_SEL_Msk #define PERI_TR_CMD_ACTIVATE_Pos PERI_V2_TR_CMD_ACTIVATE_Pos #define PERI_TR_CMD_ACTIVATE_Msk PERI_V2_TR_CMD_ACTIVATE_Msk /* PERI.DIV_CMD */ #define PERI_DIV_CMD_DIV_SEL_Pos PERI_V2_DIV_CMD_DIV_SEL_Pos #define PERI_DIV_CMD_DIV_SEL_Msk PERI_V2_DIV_CMD_DIV_SEL_Msk #define PERI_DIV_CMD_TYPE_SEL_Pos PERI_V2_DIV_CMD_TYPE_SEL_Pos #define PERI_DIV_CMD_TYPE_SEL_Msk PERI_V2_DIV_CMD_TYPE_SEL_Msk #define PERI_DIV_CMD_PA_DIV_SEL_Pos PERI_V2_DIV_CMD_PA_DIV_SEL_Pos #define PERI_DIV_CMD_PA_DIV_SEL_Msk PERI_V2_DIV_CMD_PA_DIV_SEL_Msk #define PERI_DIV_CMD_PA_TYPE_SEL_Pos PERI_V2_DIV_CMD_PA_TYPE_SEL_Pos #define PERI_DIV_CMD_PA_TYPE_SEL_Msk PERI_V2_DIV_CMD_PA_TYPE_SEL_Msk #define PERI_DIV_CMD_DISABLE_Pos PERI_V2_DIV_CMD_DISABLE_Pos #define PERI_DIV_CMD_DISABLE_Msk PERI_V2_DIV_CMD_DISABLE_Msk #define PERI_DIV_CMD_ENABLE_Pos PERI_V2_DIV_CMD_ENABLE_Pos #define PERI_DIV_CMD_ENABLE_Msk PERI_V2_DIV_CMD_ENABLE_Msk /* PERI.CLOCK_CTL */ #define PERI_CLOCK_CTL_DIV_SEL_Pos PERI_V2_CLOCK_CTL_DIV_SEL_Pos #define PERI_CLOCK_CTL_DIV_SEL_Msk PERI_V2_CLOCK_CTL_DIV_SEL_Msk #define PERI_CLOCK_CTL_TYPE_SEL_Pos PERI_V2_CLOCK_CTL_TYPE_SEL_Pos #define PERI_CLOCK_CTL_TYPE_SEL_Msk PERI_V2_CLOCK_CTL_TYPE_SEL_Msk /* PERI.DIV_8_CTL */ #define PERI_DIV_8_CTL_EN_Pos PERI_V2_DIV_8_CTL_EN_Pos #define PERI_DIV_8_CTL_EN_Msk PERI_V2_DIV_8_CTL_EN_Msk #define PERI_DIV_8_CTL_INT8_DIV_Pos PERI_V2_DIV_8_CTL_INT8_DIV_Pos #define PERI_DIV_8_CTL_INT8_DIV_Msk PERI_V2_DIV_8_CTL_INT8_DIV_Msk /* PERI.DIV_16_CTL */ #define PERI_DIV_16_CTL_EN_Pos PERI_V2_DIV_16_CTL_EN_Pos #define PERI_DIV_16_CTL_EN_Msk PERI_V2_DIV_16_CTL_EN_Msk #define PERI_DIV_16_CTL_INT16_DIV_Pos PERI_V2_DIV_16_CTL_INT16_DIV_Pos #define PERI_DIV_16_CTL_INT16_DIV_Msk PERI_V2_DIV_16_CTL_INT16_DIV_Msk /* PERI.DIV_16_5_CTL */ #define PERI_DIV_16_5_CTL_EN_Pos PERI_V2_DIV_16_5_CTL_EN_Pos #define PERI_DIV_16_5_CTL_EN_Msk PERI_V2_DIV_16_5_CTL_EN_Msk #define PERI_DIV_16_5_CTL_FRAC5_DIV_Pos PERI_V2_DIV_16_5_CTL_FRAC5_DIV_Pos #define PERI_DIV_16_5_CTL_FRAC5_DIV_Msk PERI_V2_DIV_16_5_CTL_FRAC5_DIV_Msk #define PERI_DIV_16_5_CTL_INT16_DIV_Pos PERI_V2_DIV_16_5_CTL_INT16_DIV_Pos #define PERI_DIV_16_5_CTL_INT16_DIV_Msk PERI_V2_DIV_16_5_CTL_INT16_DIV_Msk /* PERI.DIV_24_5_CTL */ #define PERI_DIV_24_5_CTL_EN_Pos PERI_V2_DIV_24_5_CTL_EN_Pos #define PERI_DIV_24_5_CTL_EN_Msk PERI_V2_DIV_24_5_CTL_EN_Msk #define PERI_DIV_24_5_CTL_FRAC5_DIV_Pos PERI_V2_DIV_24_5_CTL_FRAC5_DIV_Pos #define PERI_DIV_24_5_CTL_FRAC5_DIV_Msk PERI_V2_DIV_24_5_CTL_FRAC5_DIV_Msk #define PERI_DIV_24_5_CTL_INT24_DIV_Pos PERI_V2_DIV_24_5_CTL_INT24_DIV_Pos #define PERI_DIV_24_5_CTL_INT24_DIV_Msk PERI_V2_DIV_24_5_CTL_INT24_DIV_Msk /* PERI.ECC_CTL */ #define PERI_ECC_CTL_WORD_ADDR_Pos PERI_V2_ECC_CTL_WORD_ADDR_Pos #define PERI_ECC_CTL_WORD_ADDR_Msk PERI_V2_ECC_CTL_WORD_ADDR_Msk #define PERI_ECC_CTL_ECC_EN_Pos PERI_V2_ECC_CTL_ECC_EN_Pos #define PERI_ECC_CTL_ECC_EN_Msk PERI_V2_ECC_CTL_ECC_EN_Msk #define PERI_ECC_CTL_ECC_INJ_EN_Pos PERI_V2_ECC_CTL_ECC_INJ_EN_Pos #define PERI_ECC_CTL_ECC_INJ_EN_Msk PERI_V2_ECC_CTL_ECC_INJ_EN_Msk #define PERI_ECC_CTL_PARITY_Pos PERI_V2_ECC_CTL_PARITY_Pos #define PERI_ECC_CTL_PARITY_Msk PERI_V2_ECC_CTL_PARITY_Msk /******************************************************************************* * PROT *******************************************************************************/ #define PROT_SMPU_SMPU_STRUCT_SECTION_SIZE PROT_SMPU_SMPU_STRUCT_V2_SECTION_SIZE #define PROT_SMPU_SECTION_SIZE PROT_SMPU_V2_SECTION_SIZE #define PROT_MPU_MPU_STRUCT_SECTION_SIZE PROT_MPU_MPU_STRUCT_V2_SECTION_SIZE #define PROT_MPU_SECTION_SIZE PROT_MPU_V2_SECTION_SIZE #define PROT_SECTION_SIZE PROT_V2_SECTION_SIZE /* PROT_SMPU_SMPU_STRUCT.ADDR0 */ #define PROT_SMPU_SMPU_STRUCT_ADDR0_SUBREGION_DISABLE_Pos PROT_SMPU_SMPU_STRUCT_V2_ADDR0_SUBREGION_DISABLE_Pos #define PROT_SMPU_SMPU_STRUCT_ADDR0_SUBREGION_DISABLE_Msk PROT_SMPU_SMPU_STRUCT_V2_ADDR0_SUBREGION_DISABLE_Msk #define PROT_SMPU_SMPU_STRUCT_ADDR0_ADDR24_Pos PROT_SMPU_SMPU_STRUCT_V2_ADDR0_ADDR24_Pos #define PROT_SMPU_SMPU_STRUCT_ADDR0_ADDR24_Msk PROT_SMPU_SMPU_STRUCT_V2_ADDR0_ADDR24_Msk /* PROT_SMPU_SMPU_STRUCT.ATT0 */ #define PROT_SMPU_SMPU_STRUCT_ATT0_UR_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT0_UR_Pos #define PROT_SMPU_SMPU_STRUCT_ATT0_UR_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT0_UR_Msk #define PROT_SMPU_SMPU_STRUCT_ATT0_UW_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT0_UW_Pos #define PROT_SMPU_SMPU_STRUCT_ATT0_UW_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT0_UW_Msk #define PROT_SMPU_SMPU_STRUCT_ATT0_UX_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT0_UX_Pos #define PROT_SMPU_SMPU_STRUCT_ATT0_UX_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT0_UX_Msk #define PROT_SMPU_SMPU_STRUCT_ATT0_PR_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT0_PR_Pos #define PROT_SMPU_SMPU_STRUCT_ATT0_PR_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT0_PR_Msk #define PROT_SMPU_SMPU_STRUCT_ATT0_PW_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT0_PW_Pos #define PROT_SMPU_SMPU_STRUCT_ATT0_PW_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT0_PW_Msk #define PROT_SMPU_SMPU_STRUCT_ATT0_PX_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT0_PX_Pos #define PROT_SMPU_SMPU_STRUCT_ATT0_PX_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT0_PX_Msk #define PROT_SMPU_SMPU_STRUCT_ATT0_NS_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT0_NS_Pos #define PROT_SMPU_SMPU_STRUCT_ATT0_NS_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT0_NS_Msk #define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MASK_0_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT0_PC_MASK_0_Pos #define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MASK_0_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT0_PC_MASK_0_Msk #define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MASK_15_TO_1_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT0_PC_MASK_15_TO_1_Pos #define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MASK_15_TO_1_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT0_PC_MASK_15_TO_1_Msk #define PROT_SMPU_SMPU_STRUCT_ATT0_REGION_SIZE_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT0_REGION_SIZE_Pos #define PROT_SMPU_SMPU_STRUCT_ATT0_REGION_SIZE_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT0_REGION_SIZE_Msk #define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MATCH_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT0_PC_MATCH_Pos #define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MATCH_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT0_PC_MATCH_Msk #define PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT0_ENABLED_Pos #define PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT0_ENABLED_Msk /* PROT_SMPU_SMPU_STRUCT.ADDR1 */ #define PROT_SMPU_SMPU_STRUCT_ADDR1_SUBREGION_DISABLE_Pos PROT_SMPU_SMPU_STRUCT_V2_ADDR1_SUBREGION_DISABLE_Pos #define PROT_SMPU_SMPU_STRUCT_ADDR1_SUBREGION_DISABLE_Msk PROT_SMPU_SMPU_STRUCT_V2_ADDR1_SUBREGION_DISABLE_Msk #define PROT_SMPU_SMPU_STRUCT_ADDR1_ADDR24_Pos PROT_SMPU_SMPU_STRUCT_V2_ADDR1_ADDR24_Pos #define PROT_SMPU_SMPU_STRUCT_ADDR1_ADDR24_Msk PROT_SMPU_SMPU_STRUCT_V2_ADDR1_ADDR24_Msk /* PROT_SMPU_SMPU_STRUCT.ATT1 */ #define PROT_SMPU_SMPU_STRUCT_ATT1_UR_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT1_UR_Pos #define PROT_SMPU_SMPU_STRUCT_ATT1_UR_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT1_UR_Msk #define PROT_SMPU_SMPU_STRUCT_ATT1_UW_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT1_UW_Pos #define PROT_SMPU_SMPU_STRUCT_ATT1_UW_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT1_UW_Msk #define PROT_SMPU_SMPU_STRUCT_ATT1_UX_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT1_UX_Pos #define PROT_SMPU_SMPU_STRUCT_ATT1_UX_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT1_UX_Msk #define PROT_SMPU_SMPU_STRUCT_ATT1_PR_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT1_PR_Pos #define PROT_SMPU_SMPU_STRUCT_ATT1_PR_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT1_PR_Msk #define PROT_SMPU_SMPU_STRUCT_ATT1_PW_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT1_PW_Pos #define PROT_SMPU_SMPU_STRUCT_ATT1_PW_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT1_PW_Msk #define PROT_SMPU_SMPU_STRUCT_ATT1_PX_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT1_PX_Pos #define PROT_SMPU_SMPU_STRUCT_ATT1_PX_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT1_PX_Msk #define PROT_SMPU_SMPU_STRUCT_ATT1_NS_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT1_NS_Pos #define PROT_SMPU_SMPU_STRUCT_ATT1_NS_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT1_NS_Msk #define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MASK_0_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT1_PC_MASK_0_Pos #define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MASK_0_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT1_PC_MASK_0_Msk #define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MASK_15_TO_1_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT1_PC_MASK_15_TO_1_Pos #define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MASK_15_TO_1_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT1_PC_MASK_15_TO_1_Msk #define PROT_SMPU_SMPU_STRUCT_ATT1_REGION_SIZE_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT1_REGION_SIZE_Pos #define PROT_SMPU_SMPU_STRUCT_ATT1_REGION_SIZE_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT1_REGION_SIZE_Msk #define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MATCH_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT1_PC_MATCH_Pos #define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MATCH_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT1_PC_MATCH_Msk #define PROT_SMPU_SMPU_STRUCT_ATT1_ENABLED_Pos PROT_SMPU_SMPU_STRUCT_V2_ATT1_ENABLED_Pos #define PROT_SMPU_SMPU_STRUCT_ATT1_ENABLED_Msk PROT_SMPU_SMPU_STRUCT_V2_ATT1_ENABLED_Msk /* PROT_SMPU.MS0_CTL */ #define PROT_SMPU_MS0_CTL_P_Pos PROT_SMPU_V2_MS0_CTL_P_Pos #define PROT_SMPU_MS0_CTL_P_Msk PROT_SMPU_V2_MS0_CTL_P_Msk #define PROT_SMPU_MS0_CTL_NS_Pos PROT_SMPU_V2_MS0_CTL_NS_Pos #define PROT_SMPU_MS0_CTL_NS_Msk PROT_SMPU_V2_MS0_CTL_NS_Msk #define PROT_SMPU_MS0_CTL_PRIO_Pos PROT_SMPU_V2_MS0_CTL_PRIO_Pos #define PROT_SMPU_MS0_CTL_PRIO_Msk PROT_SMPU_V2_MS0_CTL_PRIO_Msk #define PROT_SMPU_MS0_CTL_PC_MASK_0_Pos PROT_SMPU_V2_MS0_CTL_PC_MASK_0_Pos #define PROT_SMPU_MS0_CTL_PC_MASK_0_Msk PROT_SMPU_V2_MS0_CTL_PC_MASK_0_Msk #define PROT_SMPU_MS0_CTL_PC_MASK_15_TO_1_Pos PROT_SMPU_V2_MS0_CTL_PC_MASK_15_TO_1_Pos #define PROT_SMPU_MS0_CTL_PC_MASK_15_TO_1_Msk PROT_SMPU_V2_MS0_CTL_PC_MASK_15_TO_1_Msk /* PROT_SMPU.MS1_CTL */ #define PROT_SMPU_MS1_CTL_P_Pos PROT_SMPU_V2_MS1_CTL_P_Pos #define PROT_SMPU_MS1_CTL_P_Msk PROT_SMPU_V2_MS1_CTL_P_Msk #define PROT_SMPU_MS1_CTL_NS_Pos PROT_SMPU_V2_MS1_CTL_NS_Pos #define PROT_SMPU_MS1_CTL_NS_Msk PROT_SMPU_V2_MS1_CTL_NS_Msk #define PROT_SMPU_MS1_CTL_PRIO_Pos PROT_SMPU_V2_MS1_CTL_PRIO_Pos #define PROT_SMPU_MS1_CTL_PRIO_Msk PROT_SMPU_V2_MS1_CTL_PRIO_Msk #define PROT_SMPU_MS1_CTL_PC_MASK_0_Pos PROT_SMPU_V2_MS1_CTL_PC_MASK_0_Pos #define PROT_SMPU_MS1_CTL_PC_MASK_0_Msk PROT_SMPU_V2_MS1_CTL_PC_MASK_0_Msk #define PROT_SMPU_MS1_CTL_PC_MASK_15_TO_1_Pos PROT_SMPU_V2_MS1_CTL_PC_MASK_15_TO_1_Pos #define PROT_SMPU_MS1_CTL_PC_MASK_15_TO_1_Msk PROT_SMPU_V2_MS1_CTL_PC_MASK_15_TO_1_Msk /* PROT_SMPU.MS2_CTL */ #define PROT_SMPU_MS2_CTL_P_Pos PROT_SMPU_V2_MS2_CTL_P_Pos #define PROT_SMPU_MS2_CTL_P_Msk PROT_SMPU_V2_MS2_CTL_P_Msk #define PROT_SMPU_MS2_CTL_NS_Pos PROT_SMPU_V2_MS2_CTL_NS_Pos #define PROT_SMPU_MS2_CTL_NS_Msk PROT_SMPU_V2_MS2_CTL_NS_Msk #define PROT_SMPU_MS2_CTL_PRIO_Pos PROT_SMPU_V2_MS2_CTL_PRIO_Pos #define PROT_SMPU_MS2_CTL_PRIO_Msk PROT_SMPU_V2_MS2_CTL_PRIO_Msk #define PROT_SMPU_MS2_CTL_PC_MASK_0_Pos PROT_SMPU_V2_MS2_CTL_PC_MASK_0_Pos #define PROT_SMPU_MS2_CTL_PC_MASK_0_Msk PROT_SMPU_V2_MS2_CTL_PC_MASK_0_Msk #define PROT_SMPU_MS2_CTL_PC_MASK_15_TO_1_Pos PROT_SMPU_V2_MS2_CTL_PC_MASK_15_TO_1_Pos #define PROT_SMPU_MS2_CTL_PC_MASK_15_TO_1_Msk PROT_SMPU_V2_MS2_CTL_PC_MASK_15_TO_1_Msk /* PROT_SMPU.MS3_CTL */ #define PROT_SMPU_MS3_CTL_P_Pos PROT_SMPU_V2_MS3_CTL_P_Pos #define PROT_SMPU_MS3_CTL_P_Msk PROT_SMPU_V2_MS3_CTL_P_Msk #define PROT_SMPU_MS3_CTL_NS_Pos PROT_SMPU_V2_MS3_CTL_NS_Pos #define PROT_SMPU_MS3_CTL_NS_Msk PROT_SMPU_V2_MS3_CTL_NS_Msk #define PROT_SMPU_MS3_CTL_PRIO_Pos PROT_SMPU_V2_MS3_CTL_PRIO_Pos #define PROT_SMPU_MS3_CTL_PRIO_Msk PROT_SMPU_V2_MS3_CTL_PRIO_Msk #define PROT_SMPU_MS3_CTL_PC_MASK_0_Pos PROT_SMPU_V2_MS3_CTL_PC_MASK_0_Pos #define PROT_SMPU_MS3_CTL_PC_MASK_0_Msk PROT_SMPU_V2_MS3_CTL_PC_MASK_0_Msk #define PROT_SMPU_MS3_CTL_PC_MASK_15_TO_1_Pos PROT_SMPU_V2_MS3_CTL_PC_MASK_15_TO_1_Pos #define PROT_SMPU_MS3_CTL_PC_MASK_15_TO_1_Msk PROT_SMPU_V2_MS3_CTL_PC_MASK_15_TO_1_Msk /* PROT_SMPU.MS4_CTL */ #define PROT_SMPU_MS4_CTL_P_Pos PROT_SMPU_V2_MS4_CTL_P_Pos #define PROT_SMPU_MS4_CTL_P_Msk PROT_SMPU_V2_MS4_CTL_P_Msk #define PROT_SMPU_MS4_CTL_NS_Pos PROT_SMPU_V2_MS4_CTL_NS_Pos #define PROT_SMPU_MS4_CTL_NS_Msk PROT_SMPU_V2_MS4_CTL_NS_Msk #define PROT_SMPU_MS4_CTL_PRIO_Pos PROT_SMPU_V2_MS4_CTL_PRIO_Pos #define PROT_SMPU_MS4_CTL_PRIO_Msk PROT_SMPU_V2_MS4_CTL_PRIO_Msk #define PROT_SMPU_MS4_CTL_PC_MASK_0_Pos PROT_SMPU_V2_MS4_CTL_PC_MASK_0_Pos #define PROT_SMPU_MS4_CTL_PC_MASK_0_Msk PROT_SMPU_V2_MS4_CTL_PC_MASK_0_Msk #define PROT_SMPU_MS4_CTL_PC_MASK_15_TO_1_Pos PROT_SMPU_V2_MS4_CTL_PC_MASK_15_TO_1_Pos #define PROT_SMPU_MS4_CTL_PC_MASK_15_TO_1_Msk PROT_SMPU_V2_MS4_CTL_PC_MASK_15_TO_1_Msk /* PROT_SMPU.MS5_CTL */ #define PROT_SMPU_MS5_CTL_P_Pos PROT_SMPU_V2_MS5_CTL_P_Pos #define PROT_SMPU_MS5_CTL_P_Msk PROT_SMPU_V2_MS5_CTL_P_Msk #define PROT_SMPU_MS5_CTL_NS_Pos PROT_SMPU_V2_MS5_CTL_NS_Pos #define PROT_SMPU_MS5_CTL_NS_Msk PROT_SMPU_V2_MS5_CTL_NS_Msk #define PROT_SMPU_MS5_CTL_PRIO_Pos PROT_SMPU_V2_MS5_CTL_PRIO_Pos #define PROT_SMPU_MS5_CTL_PRIO_Msk PROT_SMPU_V2_MS5_CTL_PRIO_Msk #define PROT_SMPU_MS5_CTL_PC_MASK_0_Pos PROT_SMPU_V2_MS5_CTL_PC_MASK_0_Pos #define PROT_SMPU_MS5_CTL_PC_MASK_0_Msk PROT_SMPU_V2_MS5_CTL_PC_MASK_0_Msk #define PROT_SMPU_MS5_CTL_PC_MASK_15_TO_1_Pos PROT_SMPU_V2_MS5_CTL_PC_MASK_15_TO_1_Pos #define PROT_SMPU_MS5_CTL_PC_MASK_15_TO_1_Msk PROT_SMPU_V2_MS5_CTL_PC_MASK_15_TO_1_Msk /* PROT_SMPU.MS6_CTL */ #define PROT_SMPU_MS6_CTL_P_Pos PROT_SMPU_V2_MS6_CTL_P_Pos #define PROT_SMPU_MS6_CTL_P_Msk PROT_SMPU_V2_MS6_CTL_P_Msk #define PROT_SMPU_MS6_CTL_NS_Pos PROT_SMPU_V2_MS6_CTL_NS_Pos #define PROT_SMPU_MS6_CTL_NS_Msk PROT_SMPU_V2_MS6_CTL_NS_Msk #define PROT_SMPU_MS6_CTL_PRIO_Pos PROT_SMPU_V2_MS6_CTL_PRIO_Pos #define PROT_SMPU_MS6_CTL_PRIO_Msk PROT_SMPU_V2_MS6_CTL_PRIO_Msk #define PROT_SMPU_MS6_CTL_PC_MASK_0_Pos PROT_SMPU_V2_MS6_CTL_PC_MASK_0_Pos #define PROT_SMPU_MS6_CTL_PC_MASK_0_Msk PROT_SMPU_V2_MS6_CTL_PC_MASK_0_Msk #define PROT_SMPU_MS6_CTL_PC_MASK_15_TO_1_Pos PROT_SMPU_V2_MS6_CTL_PC_MASK_15_TO_1_Pos #define PROT_SMPU_MS6_CTL_PC_MASK_15_TO_1_Msk PROT_SMPU_V2_MS6_CTL_PC_MASK_15_TO_1_Msk /* PROT_SMPU.MS7_CTL */ #define PROT_SMPU_MS7_CTL_P_Pos PROT_SMPU_V2_MS7_CTL_P_Pos #define PROT_SMPU_MS7_CTL_P_Msk PROT_SMPU_V2_MS7_CTL_P_Msk #define PROT_SMPU_MS7_CTL_NS_Pos PROT_SMPU_V2_MS7_CTL_NS_Pos #define PROT_SMPU_MS7_CTL_NS_Msk PROT_SMPU_V2_MS7_CTL_NS_Msk #define PROT_SMPU_MS7_CTL_PRIO_Pos PROT_SMPU_V2_MS7_CTL_PRIO_Pos #define PROT_SMPU_MS7_CTL_PRIO_Msk PROT_SMPU_V2_MS7_CTL_PRIO_Msk #define PROT_SMPU_MS7_CTL_PC_MASK_0_Pos PROT_SMPU_V2_MS7_CTL_PC_MASK_0_Pos #define PROT_SMPU_MS7_CTL_PC_MASK_0_Msk PROT_SMPU_V2_MS7_CTL_PC_MASK_0_Msk #define PROT_SMPU_MS7_CTL_PC_MASK_15_TO_1_Pos PROT_SMPU_V2_MS7_CTL_PC_MASK_15_TO_1_Pos #define PROT_SMPU_MS7_CTL_PC_MASK_15_TO_1_Msk PROT_SMPU_V2_MS7_CTL_PC_MASK_15_TO_1_Msk /* PROT_SMPU.MS8_CTL */ #define PROT_SMPU_MS8_CTL_P_Pos PROT_SMPU_V2_MS8_CTL_P_Pos #define PROT_SMPU_MS8_CTL_P_Msk PROT_SMPU_V2_MS8_CTL_P_Msk #define PROT_SMPU_MS8_CTL_NS_Pos PROT_SMPU_V2_MS8_CTL_NS_Pos #define PROT_SMPU_MS8_CTL_NS_Msk PROT_SMPU_V2_MS8_CTL_NS_Msk #define PROT_SMPU_MS8_CTL_PRIO_Pos PROT_SMPU_V2_MS8_CTL_PRIO_Pos #define PROT_SMPU_MS8_CTL_PRIO_Msk PROT_SMPU_V2_MS8_CTL_PRIO_Msk #define PROT_SMPU_MS8_CTL_PC_MASK_0_Pos PROT_SMPU_V2_MS8_CTL_PC_MASK_0_Pos #define PROT_SMPU_MS8_CTL_PC_MASK_0_Msk PROT_SMPU_V2_MS8_CTL_PC_MASK_0_Msk #define PROT_SMPU_MS8_CTL_PC_MASK_15_TO_1_Pos PROT_SMPU_V2_MS8_CTL_PC_MASK_15_TO_1_Pos #define PROT_SMPU_MS8_CTL_PC_MASK_15_TO_1_Msk PROT_SMPU_V2_MS8_CTL_PC_MASK_15_TO_1_Msk /* PROT_SMPU.MS9_CTL */ #define PROT_SMPU_MS9_CTL_P_Pos PROT_SMPU_V2_MS9_CTL_P_Pos #define PROT_SMPU_MS9_CTL_P_Msk PROT_SMPU_V2_MS9_CTL_P_Msk #define PROT_SMPU_MS9_CTL_NS_Pos PROT_SMPU_V2_MS9_CTL_NS_Pos #define PROT_SMPU_MS9_CTL_NS_Msk PROT_SMPU_V2_MS9_CTL_NS_Msk #define PROT_SMPU_MS9_CTL_PRIO_Pos PROT_SMPU_V2_MS9_CTL_PRIO_Pos #define PROT_SMPU_MS9_CTL_PRIO_Msk PROT_SMPU_V2_MS9_CTL_PRIO_Msk #define PROT_SMPU_MS9_CTL_PC_MASK_0_Pos PROT_SMPU_V2_MS9_CTL_PC_MASK_0_Pos #define PROT_SMPU_MS9_CTL_PC_MASK_0_Msk PROT_SMPU_V2_MS9_CTL_PC_MASK_0_Msk #define PROT_SMPU_MS9_CTL_PC_MASK_15_TO_1_Pos PROT_SMPU_V2_MS9_CTL_PC_MASK_15_TO_1_Pos #define PROT_SMPU_MS9_CTL_PC_MASK_15_TO_1_Msk PROT_SMPU_V2_MS9_CTL_PC_MASK_15_TO_1_Msk /* PROT_SMPU.MS10_CTL */ #define PROT_SMPU_MS10_CTL_P_Pos PROT_SMPU_V2_MS10_CTL_P_Pos #define PROT_SMPU_MS10_CTL_P_Msk PROT_SMPU_V2_MS10_CTL_P_Msk #define PROT_SMPU_MS10_CTL_NS_Pos PROT_SMPU_V2_MS10_CTL_NS_Pos #define PROT_SMPU_MS10_CTL_NS_Msk PROT_SMPU_V2_MS10_CTL_NS_Msk #define PROT_SMPU_MS10_CTL_PRIO_Pos PROT_SMPU_V2_MS10_CTL_PRIO_Pos #define PROT_SMPU_MS10_CTL_PRIO_Msk PROT_SMPU_V2_MS10_CTL_PRIO_Msk #define PROT_SMPU_MS10_CTL_PC_MASK_0_Pos PROT_SMPU_V2_MS10_CTL_PC_MASK_0_Pos #define PROT_SMPU_MS10_CTL_PC_MASK_0_Msk PROT_SMPU_V2_MS10_CTL_PC_MASK_0_Msk #define PROT_SMPU_MS10_CTL_PC_MASK_15_TO_1_Pos PROT_SMPU_V2_MS10_CTL_PC_MASK_15_TO_1_Pos #define PROT_SMPU_MS10_CTL_PC_MASK_15_TO_1_Msk PROT_SMPU_V2_MS10_CTL_PC_MASK_15_TO_1_Msk /* PROT_SMPU.MS11_CTL */ #define PROT_SMPU_MS11_CTL_P_Pos PROT_SMPU_V2_MS11_CTL_P_Pos #define PROT_SMPU_MS11_CTL_P_Msk PROT_SMPU_V2_MS11_CTL_P_Msk #define PROT_SMPU_MS11_CTL_NS_Pos PROT_SMPU_V2_MS11_CTL_NS_Pos #define PROT_SMPU_MS11_CTL_NS_Msk PROT_SMPU_V2_MS11_CTL_NS_Msk #define PROT_SMPU_MS11_CTL_PRIO_Pos PROT_SMPU_V2_MS11_CTL_PRIO_Pos #define PROT_SMPU_MS11_CTL_PRIO_Msk PROT_SMPU_V2_MS11_CTL_PRIO_Msk #define PROT_SMPU_MS11_CTL_PC_MASK_0_Pos PROT_SMPU_V2_MS11_CTL_PC_MASK_0_Pos #define PROT_SMPU_MS11_CTL_PC_MASK_0_Msk PROT_SMPU_V2_MS11_CTL_PC_MASK_0_Msk #define PROT_SMPU_MS11_CTL_PC_MASK_15_TO_1_Pos PROT_SMPU_V2_MS11_CTL_PC_MASK_15_TO_1_Pos #define PROT_SMPU_MS11_CTL_PC_MASK_15_TO_1_Msk PROT_SMPU_V2_MS11_CTL_PC_MASK_15_TO_1_Msk /* PROT_SMPU.MS12_CTL */ #define PROT_SMPU_MS12_CTL_P_Pos PROT_SMPU_V2_MS12_CTL_P_Pos #define PROT_SMPU_MS12_CTL_P_Msk PROT_SMPU_V2_MS12_CTL_P_Msk #define PROT_SMPU_MS12_CTL_NS_Pos PROT_SMPU_V2_MS12_CTL_NS_Pos #define PROT_SMPU_MS12_CTL_NS_Msk PROT_SMPU_V2_MS12_CTL_NS_Msk #define PROT_SMPU_MS12_CTL_PRIO_Pos PROT_SMPU_V2_MS12_CTL_PRIO_Pos #define PROT_SMPU_MS12_CTL_PRIO_Msk PROT_SMPU_V2_MS12_CTL_PRIO_Msk #define PROT_SMPU_MS12_CTL_PC_MASK_0_Pos PROT_SMPU_V2_MS12_CTL_PC_MASK_0_Pos #define PROT_SMPU_MS12_CTL_PC_MASK_0_Msk PROT_SMPU_V2_MS12_CTL_PC_MASK_0_Msk #define PROT_SMPU_MS12_CTL_PC_MASK_15_TO_1_Pos PROT_SMPU_V2_MS12_CTL_PC_MASK_15_TO_1_Pos #define PROT_SMPU_MS12_CTL_PC_MASK_15_TO_1_Msk PROT_SMPU_V2_MS12_CTL_PC_MASK_15_TO_1_Msk /* PROT_SMPU.MS13_CTL */ #define PROT_SMPU_MS13_CTL_P_Pos PROT_SMPU_V2_MS13_CTL_P_Pos #define PROT_SMPU_MS13_CTL_P_Msk PROT_SMPU_V2_MS13_CTL_P_Msk #define PROT_SMPU_MS13_CTL_NS_Pos PROT_SMPU_V2_MS13_CTL_NS_Pos #define PROT_SMPU_MS13_CTL_NS_Msk PROT_SMPU_V2_MS13_CTL_NS_Msk #define PROT_SMPU_MS13_CTL_PRIO_Pos PROT_SMPU_V2_MS13_CTL_PRIO_Pos #define PROT_SMPU_MS13_CTL_PRIO_Msk PROT_SMPU_V2_MS13_CTL_PRIO_Msk #define PROT_SMPU_MS13_CTL_PC_MASK_0_Pos PROT_SMPU_V2_MS13_CTL_PC_MASK_0_Pos #define PROT_SMPU_MS13_CTL_PC_MASK_0_Msk PROT_SMPU_V2_MS13_CTL_PC_MASK_0_Msk #define PROT_SMPU_MS13_CTL_PC_MASK_15_TO_1_Pos PROT_SMPU_V2_MS13_CTL_PC_MASK_15_TO_1_Pos #define PROT_SMPU_MS13_CTL_PC_MASK_15_TO_1_Msk PROT_SMPU_V2_MS13_CTL_PC_MASK_15_TO_1_Msk /* PROT_SMPU.MS14_CTL */ #define PROT_SMPU_MS14_CTL_P_Pos PROT_SMPU_V2_MS14_CTL_P_Pos #define PROT_SMPU_MS14_CTL_P_Msk PROT_SMPU_V2_MS14_CTL_P_Msk #define PROT_SMPU_MS14_CTL_NS_Pos PROT_SMPU_V2_MS14_CTL_NS_Pos #define PROT_SMPU_MS14_CTL_NS_Msk PROT_SMPU_V2_MS14_CTL_NS_Msk #define PROT_SMPU_MS14_CTL_PRIO_Pos PROT_SMPU_V2_MS14_CTL_PRIO_Pos #define PROT_SMPU_MS14_CTL_PRIO_Msk PROT_SMPU_V2_MS14_CTL_PRIO_Msk #define PROT_SMPU_MS14_CTL_PC_MASK_0_Pos PROT_SMPU_V2_MS14_CTL_PC_MASK_0_Pos #define PROT_SMPU_MS14_CTL_PC_MASK_0_Msk PROT_SMPU_V2_MS14_CTL_PC_MASK_0_Msk #define PROT_SMPU_MS14_CTL_PC_MASK_15_TO_1_Pos PROT_SMPU_V2_MS14_CTL_PC_MASK_15_TO_1_Pos #define PROT_SMPU_MS14_CTL_PC_MASK_15_TO_1_Msk PROT_SMPU_V2_MS14_CTL_PC_MASK_15_TO_1_Msk /* PROT_SMPU.MS15_CTL */ #define PROT_SMPU_MS15_CTL_P_Pos PROT_SMPU_V2_MS15_CTL_P_Pos #define PROT_SMPU_MS15_CTL_P_Msk PROT_SMPU_V2_MS15_CTL_P_Msk #define PROT_SMPU_MS15_CTL_NS_Pos PROT_SMPU_V2_MS15_CTL_NS_Pos #define PROT_SMPU_MS15_CTL_NS_Msk PROT_SMPU_V2_MS15_CTL_NS_Msk #define PROT_SMPU_MS15_CTL_PRIO_Pos PROT_SMPU_V2_MS15_CTL_PRIO_Pos #define PROT_SMPU_MS15_CTL_PRIO_Msk PROT_SMPU_V2_MS15_CTL_PRIO_Msk #define PROT_SMPU_MS15_CTL_PC_MASK_0_Pos PROT_SMPU_V2_MS15_CTL_PC_MASK_0_Pos #define PROT_SMPU_MS15_CTL_PC_MASK_0_Msk PROT_SMPU_V2_MS15_CTL_PC_MASK_0_Msk #define PROT_SMPU_MS15_CTL_PC_MASK_15_TO_1_Pos PROT_SMPU_V2_MS15_CTL_PC_MASK_15_TO_1_Pos #define PROT_SMPU_MS15_CTL_PC_MASK_15_TO_1_Msk PROT_SMPU_V2_MS15_CTL_PC_MASK_15_TO_1_Msk /* PROT_MPU_MPU_STRUCT.ADDR */ #define PROT_MPU_MPU_STRUCT_ADDR_SUBREGION_DISABLE_Pos PROT_MPU_MPU_STRUCT_V2_ADDR_SUBREGION_DISABLE_Pos #define PROT_MPU_MPU_STRUCT_ADDR_SUBREGION_DISABLE_Msk PROT_MPU_MPU_STRUCT_V2_ADDR_SUBREGION_DISABLE_Msk #define PROT_MPU_MPU_STRUCT_ADDR_ADDR24_Pos PROT_MPU_MPU_STRUCT_V2_ADDR_ADDR24_Pos #define PROT_MPU_MPU_STRUCT_ADDR_ADDR24_Msk PROT_MPU_MPU_STRUCT_V2_ADDR_ADDR24_Msk /* PROT_MPU_MPU_STRUCT.ATT */ #define PROT_MPU_MPU_STRUCT_ATT_UR_Pos PROT_MPU_MPU_STRUCT_V2_ATT_UR_Pos #define PROT_MPU_MPU_STRUCT_ATT_UR_Msk PROT_MPU_MPU_STRUCT_V2_ATT_UR_Msk #define PROT_MPU_MPU_STRUCT_ATT_UW_Pos PROT_MPU_MPU_STRUCT_V2_ATT_UW_Pos #define PROT_MPU_MPU_STRUCT_ATT_UW_Msk PROT_MPU_MPU_STRUCT_V2_ATT_UW_Msk #define PROT_MPU_MPU_STRUCT_ATT_UX_Pos PROT_MPU_MPU_STRUCT_V2_ATT_UX_Pos #define PROT_MPU_MPU_STRUCT_ATT_UX_Msk PROT_MPU_MPU_STRUCT_V2_ATT_UX_Msk #define PROT_MPU_MPU_STRUCT_ATT_PR_Pos PROT_MPU_MPU_STRUCT_V2_ATT_PR_Pos #define PROT_MPU_MPU_STRUCT_ATT_PR_Msk PROT_MPU_MPU_STRUCT_V2_ATT_PR_Msk #define PROT_MPU_MPU_STRUCT_ATT_PW_Pos PROT_MPU_MPU_STRUCT_V2_ATT_PW_Pos #define PROT_MPU_MPU_STRUCT_ATT_PW_Msk PROT_MPU_MPU_STRUCT_V2_ATT_PW_Msk #define PROT_MPU_MPU_STRUCT_ATT_PX_Pos PROT_MPU_MPU_STRUCT_V2_ATT_PX_Pos #define PROT_MPU_MPU_STRUCT_ATT_PX_Msk PROT_MPU_MPU_STRUCT_V2_ATT_PX_Msk #define PROT_MPU_MPU_STRUCT_ATT_NS_Pos PROT_MPU_MPU_STRUCT_V2_ATT_NS_Pos #define PROT_MPU_MPU_STRUCT_ATT_NS_Msk PROT_MPU_MPU_STRUCT_V2_ATT_NS_Msk #define PROT_MPU_MPU_STRUCT_ATT_REGION_SIZE_Pos PROT_MPU_MPU_STRUCT_V2_ATT_REGION_SIZE_Pos #define PROT_MPU_MPU_STRUCT_ATT_REGION_SIZE_Msk PROT_MPU_MPU_STRUCT_V2_ATT_REGION_SIZE_Msk #define PROT_MPU_MPU_STRUCT_ATT_ENABLED_Pos PROT_MPU_MPU_STRUCT_V2_ATT_ENABLED_Pos #define PROT_MPU_MPU_STRUCT_ATT_ENABLED_Msk PROT_MPU_MPU_STRUCT_V2_ATT_ENABLED_Msk /* PROT_MPU.MS_CTL */ #define PROT_MPU_MS_CTL_PC_Pos PROT_MPU_V2_MS_CTL_PC_Pos #define PROT_MPU_MS_CTL_PC_Msk PROT_MPU_V2_MS_CTL_PC_Msk #define PROT_MPU_MS_CTL_PC_SAVED_Pos PROT_MPU_V2_MS_CTL_PC_SAVED_Pos #define PROT_MPU_MS_CTL_PC_SAVED_Msk PROT_MPU_V2_MS_CTL_PC_SAVED_Msk /* PROT_MPU.MS_CTL_READ_MIR */ #define PROT_MPU_MS_CTL_READ_MIR_PC_Pos PROT_MPU_V2_MS_CTL_READ_MIR_PC_Pos #define PROT_MPU_MS_CTL_READ_MIR_PC_Msk PROT_MPU_V2_MS_CTL_READ_MIR_PC_Msk #define PROT_MPU_MS_CTL_READ_MIR_PC_SAVED_Pos PROT_MPU_V2_MS_CTL_READ_MIR_PC_SAVED_Pos #define PROT_MPU_MS_CTL_READ_MIR_PC_SAVED_Msk PROT_MPU_V2_MS_CTL_READ_MIR_PC_SAVED_Msk /******************************************************************************* * SCB *******************************************************************************/ /* SCB.CTRL */ #define SCB_CTRL_OVS_Pos SCB_V2_CTRL_OVS_Pos #define SCB_CTRL_OVS_Msk SCB_V2_CTRL_OVS_Msk #define SCB_CTRL_EC_AM_MODE_Pos SCB_V2_CTRL_EC_AM_MODE_Pos #define SCB_CTRL_EC_AM_MODE_Msk SCB_V2_CTRL_EC_AM_MODE_Msk #define SCB_CTRL_EC_OP_MODE_Pos SCB_V2_CTRL_EC_OP_MODE_Pos #define SCB_CTRL_EC_OP_MODE_Msk SCB_V2_CTRL_EC_OP_MODE_Msk #define SCB_CTRL_EZ_MODE_Pos SCB_V2_CTRL_EZ_MODE_Pos #define SCB_CTRL_EZ_MODE_Msk SCB_V2_CTRL_EZ_MODE_Msk #define SCB_CTRL_CMD_RESP_MODE_Pos SCB_V2_CTRL_CMD_RESP_MODE_Pos #define SCB_CTRL_CMD_RESP_MODE_Msk SCB_V2_CTRL_CMD_RESP_MODE_Msk #define SCB_CTRL_MEM_WIDTH_Pos SCB_V2_CTRL_MEM_WIDTH_Pos #define SCB_CTRL_MEM_WIDTH_Msk SCB_V2_CTRL_MEM_WIDTH_Msk #define SCB_CTRL_ADDR_ACCEPT_Pos SCB_V2_CTRL_ADDR_ACCEPT_Pos #define SCB_CTRL_ADDR_ACCEPT_Msk SCB_V2_CTRL_ADDR_ACCEPT_Msk #define SCB_CTRL_BLOCK_Pos SCB_V2_CTRL_BLOCK_Pos #define SCB_CTRL_BLOCK_Msk SCB_V2_CTRL_BLOCK_Msk #define SCB_CTRL_MODE_Pos SCB_V2_CTRL_MODE_Pos #define SCB_CTRL_MODE_Msk SCB_V2_CTRL_MODE_Msk #define SCB_CTRL_EC_ACCESS_Pos SCB_V2_CTRL_EC_ACCESS_Pos #define SCB_CTRL_EC_ACCESS_Msk SCB_V2_CTRL_EC_ACCESS_Msk #define SCB_CTRL_ENABLED_Pos SCB_V2_CTRL_ENABLED_Pos #define SCB_CTRL_ENABLED_Msk SCB_V2_CTRL_ENABLED_Msk /* SCB.STATUS */ #define SCB_STATUS_EC_BUSY_Pos SCB_V2_STATUS_EC_BUSY_Pos #define SCB_STATUS_EC_BUSY_Msk SCB_V2_STATUS_EC_BUSY_Msk /* SCB.CMD_RESP_CTRL */ #define SCB_CMD_RESP_CTRL_BASE_RD_ADDR_Pos SCB_V2_CMD_RESP_CTRL_BASE_RD_ADDR_Pos #define SCB_CMD_RESP_CTRL_BASE_RD_ADDR_Msk SCB_V2_CMD_RESP_CTRL_BASE_RD_ADDR_Msk #define SCB_CMD_RESP_CTRL_BASE_WR_ADDR_Pos SCB_V2_CMD_RESP_CTRL_BASE_WR_ADDR_Pos #define SCB_CMD_RESP_CTRL_BASE_WR_ADDR_Msk SCB_V2_CMD_RESP_CTRL_BASE_WR_ADDR_Msk /* SCB.CMD_RESP_STATUS */ #define SCB_CMD_RESP_STATUS_CURR_RD_ADDR_Pos SCB_V2_CMD_RESP_STATUS_CURR_RD_ADDR_Pos #define SCB_CMD_RESP_STATUS_CURR_RD_ADDR_Msk SCB_V2_CMD_RESP_STATUS_CURR_RD_ADDR_Msk #define SCB_CMD_RESP_STATUS_CURR_WR_ADDR_Pos SCB_V2_CMD_RESP_STATUS_CURR_WR_ADDR_Pos #define SCB_CMD_RESP_STATUS_CURR_WR_ADDR_Msk SCB_V2_CMD_RESP_STATUS_CURR_WR_ADDR_Msk #define SCB_CMD_RESP_STATUS_CMD_RESP_EC_BUS_BUSY_Pos SCB_V2_CMD_RESP_STATUS_CMD_RESP_EC_BUS_BUSY_Pos #define SCB_CMD_RESP_STATUS_CMD_RESP_EC_BUS_BUSY_Msk SCB_V2_CMD_RESP_STATUS_CMD_RESP_EC_BUS_BUSY_Msk #define SCB_CMD_RESP_STATUS_CMD_RESP_EC_BUSY_Pos SCB_V2_CMD_RESP_STATUS_CMD_RESP_EC_BUSY_Pos #define SCB_CMD_RESP_STATUS_CMD_RESP_EC_BUSY_Msk SCB_V2_CMD_RESP_STATUS_CMD_RESP_EC_BUSY_Msk /* SCB.SPI_CTRL */ #define SCB_SPI_CTRL_SSEL_CONTINUOUS_Pos SCB_V2_SPI_CTRL_SSEL_CONTINUOUS_Pos #define SCB_SPI_CTRL_SSEL_CONTINUOUS_Msk SCB_V2_SPI_CTRL_SSEL_CONTINUOUS_Msk #define SCB_SPI_CTRL_SELECT_PRECEDE_Pos SCB_V2_SPI_CTRL_SELECT_PRECEDE_Pos #define SCB_SPI_CTRL_SELECT_PRECEDE_Msk SCB_V2_SPI_CTRL_SELECT_PRECEDE_Msk #define SCB_SPI_CTRL_CPHA_Pos SCB_V2_SPI_CTRL_CPHA_Pos #define SCB_SPI_CTRL_CPHA_Msk SCB_V2_SPI_CTRL_CPHA_Msk #define SCB_SPI_CTRL_CPOL_Pos SCB_V2_SPI_CTRL_CPOL_Pos #define SCB_SPI_CTRL_CPOL_Msk SCB_V2_SPI_CTRL_CPOL_Msk #define SCB_SPI_CTRL_LATE_MISO_SAMPLE_Pos SCB_V2_SPI_CTRL_LATE_MISO_SAMPLE_Pos #define SCB_SPI_CTRL_LATE_MISO_SAMPLE_Msk SCB_V2_SPI_CTRL_LATE_MISO_SAMPLE_Msk #define SCB_SPI_CTRL_SCLK_CONTINUOUS_Pos SCB_V2_SPI_CTRL_SCLK_CONTINUOUS_Pos #define SCB_SPI_CTRL_SCLK_CONTINUOUS_Msk SCB_V2_SPI_CTRL_SCLK_CONTINUOUS_Msk #define SCB_SPI_CTRL_SSEL_POLARITY0_Pos SCB_V2_SPI_CTRL_SSEL_POLARITY0_Pos #define SCB_SPI_CTRL_SSEL_POLARITY0_Msk SCB_V2_SPI_CTRL_SSEL_POLARITY0_Msk #define SCB_SPI_CTRL_SSEL_POLARITY1_Pos SCB_V2_SPI_CTRL_SSEL_POLARITY1_Pos #define SCB_SPI_CTRL_SSEL_POLARITY1_Msk SCB_V2_SPI_CTRL_SSEL_POLARITY1_Msk #define SCB_SPI_CTRL_SSEL_POLARITY2_Pos SCB_V2_SPI_CTRL_SSEL_POLARITY2_Pos #define SCB_SPI_CTRL_SSEL_POLARITY2_Msk SCB_V2_SPI_CTRL_SSEL_POLARITY2_Msk #define SCB_SPI_CTRL_SSEL_POLARITY3_Pos SCB_V2_SPI_CTRL_SSEL_POLARITY3_Pos #define SCB_SPI_CTRL_SSEL_POLARITY3_Msk SCB_V2_SPI_CTRL_SSEL_POLARITY3_Msk #define SCB_SPI_CTRL_SSEL_SETUP_DEL_Pos SCB_V2_SPI_CTRL_SSEL_SETUP_DEL_Pos #define SCB_SPI_CTRL_SSEL_SETUP_DEL_Msk SCB_V2_SPI_CTRL_SSEL_SETUP_DEL_Msk #define SCB_SPI_CTRL_SSEL_HOLD_DEL_Pos SCB_V2_SPI_CTRL_SSEL_HOLD_DEL_Pos #define SCB_SPI_CTRL_SSEL_HOLD_DEL_Msk SCB_V2_SPI_CTRL_SSEL_HOLD_DEL_Msk #define SCB_SPI_CTRL_SSEL_INTER_FRAME_DEL_Pos SCB_V2_SPI_CTRL_SSEL_INTER_FRAME_DEL_Pos #define SCB_SPI_CTRL_SSEL_INTER_FRAME_DEL_Msk SCB_V2_SPI_CTRL_SSEL_INTER_FRAME_DEL_Msk #define SCB_SPI_CTRL_LOOPBACK_Pos SCB_V2_SPI_CTRL_LOOPBACK_Pos #define SCB_SPI_CTRL_LOOPBACK_Msk SCB_V2_SPI_CTRL_LOOPBACK_Msk #define SCB_SPI_CTRL_MODE_Pos SCB_V2_SPI_CTRL_MODE_Pos #define SCB_SPI_CTRL_MODE_Msk SCB_V2_SPI_CTRL_MODE_Msk #define SCB_SPI_CTRL_SSEL_Pos SCB_V2_SPI_CTRL_SSEL_Pos #define SCB_SPI_CTRL_SSEL_Msk SCB_V2_SPI_CTRL_SSEL_Msk #define SCB_SPI_CTRL_MASTER_MODE_Pos SCB_V2_SPI_CTRL_MASTER_MODE_Pos #define SCB_SPI_CTRL_MASTER_MODE_Msk SCB_V2_SPI_CTRL_MASTER_MODE_Msk /* SCB.SPI_STATUS */ #define SCB_SPI_STATUS_BUS_BUSY_Pos SCB_V2_SPI_STATUS_BUS_BUSY_Pos #define SCB_SPI_STATUS_BUS_BUSY_Msk SCB_V2_SPI_STATUS_BUS_BUSY_Msk #define SCB_SPI_STATUS_SPI_EC_BUSY_Pos SCB_V2_SPI_STATUS_SPI_EC_BUSY_Pos #define SCB_SPI_STATUS_SPI_EC_BUSY_Msk SCB_V2_SPI_STATUS_SPI_EC_BUSY_Msk #define SCB_SPI_STATUS_CURR_EZ_ADDR_Pos SCB_V2_SPI_STATUS_CURR_EZ_ADDR_Pos #define SCB_SPI_STATUS_CURR_EZ_ADDR_Msk SCB_V2_SPI_STATUS_CURR_EZ_ADDR_Msk #define SCB_SPI_STATUS_BASE_EZ_ADDR_Pos SCB_V2_SPI_STATUS_BASE_EZ_ADDR_Pos #define SCB_SPI_STATUS_BASE_EZ_ADDR_Msk SCB_V2_SPI_STATUS_BASE_EZ_ADDR_Msk /* SCB.SPI_TX_CTRL */ #define SCB_SPI_TX_CTRL_PARITY_Pos SCB_V2_SPI_TX_CTRL_PARITY_Pos #define SCB_SPI_TX_CTRL_PARITY_Msk SCB_V2_SPI_TX_CTRL_PARITY_Msk #define SCB_SPI_TX_CTRL_PARITY_ENABLED_Pos SCB_V2_SPI_TX_CTRL_PARITY_ENABLED_Pos #define SCB_SPI_TX_CTRL_PARITY_ENABLED_Msk SCB_V2_SPI_TX_CTRL_PARITY_ENABLED_Msk /* SCB.SPI_RX_CTRL */ #define SCB_SPI_RX_CTRL_PARITY_Pos SCB_V2_SPI_RX_CTRL_PARITY_Pos #define SCB_SPI_RX_CTRL_PARITY_Msk SCB_V2_SPI_RX_CTRL_PARITY_Msk #define SCB_SPI_RX_CTRL_PARITY_ENABLED_Pos SCB_V2_SPI_RX_CTRL_PARITY_ENABLED_Pos #define SCB_SPI_RX_CTRL_PARITY_ENABLED_Msk SCB_V2_SPI_RX_CTRL_PARITY_ENABLED_Msk #define SCB_SPI_RX_CTRL_DROP_ON_PARITY_ERROR_Pos SCB_V2_SPI_RX_CTRL_DROP_ON_PARITY_ERROR_Pos #define SCB_SPI_RX_CTRL_DROP_ON_PARITY_ERROR_Msk SCB_V2_SPI_RX_CTRL_DROP_ON_PARITY_ERROR_Msk /* SCB.UART_CTRL */ #define SCB_UART_CTRL_LOOPBACK_Pos SCB_V2_UART_CTRL_LOOPBACK_Pos #define SCB_UART_CTRL_LOOPBACK_Msk SCB_V2_UART_CTRL_LOOPBACK_Msk #define SCB_UART_CTRL_MODE_Pos SCB_V2_UART_CTRL_MODE_Pos #define SCB_UART_CTRL_MODE_Msk SCB_V2_UART_CTRL_MODE_Msk /* SCB.UART_TX_CTRL */ #define SCB_UART_TX_CTRL_STOP_BITS_Pos SCB_V2_UART_TX_CTRL_STOP_BITS_Pos #define SCB_UART_TX_CTRL_STOP_BITS_Msk SCB_V2_UART_TX_CTRL_STOP_BITS_Msk #define SCB_UART_TX_CTRL_PARITY_Pos SCB_V2_UART_TX_CTRL_PARITY_Pos #define SCB_UART_TX_CTRL_PARITY_Msk SCB_V2_UART_TX_CTRL_PARITY_Msk #define SCB_UART_TX_CTRL_PARITY_ENABLED_Pos SCB_V2_UART_TX_CTRL_PARITY_ENABLED_Pos #define SCB_UART_TX_CTRL_PARITY_ENABLED_Msk SCB_V2_UART_TX_CTRL_PARITY_ENABLED_Msk #define SCB_UART_TX_CTRL_RETRY_ON_NACK_Pos SCB_V2_UART_TX_CTRL_RETRY_ON_NACK_Pos #define SCB_UART_TX_CTRL_RETRY_ON_NACK_Msk SCB_V2_UART_TX_CTRL_RETRY_ON_NACK_Msk /* SCB.UART_RX_CTRL */ #define SCB_UART_RX_CTRL_STOP_BITS_Pos SCB_V2_UART_RX_CTRL_STOP_BITS_Pos #define SCB_UART_RX_CTRL_STOP_BITS_Msk SCB_V2_UART_RX_CTRL_STOP_BITS_Msk #define SCB_UART_RX_CTRL_PARITY_Pos SCB_V2_UART_RX_CTRL_PARITY_Pos #define SCB_UART_RX_CTRL_PARITY_Msk SCB_V2_UART_RX_CTRL_PARITY_Msk #define SCB_UART_RX_CTRL_PARITY_ENABLED_Pos SCB_V2_UART_RX_CTRL_PARITY_ENABLED_Pos #define SCB_UART_RX_CTRL_PARITY_ENABLED_Msk SCB_V2_UART_RX_CTRL_PARITY_ENABLED_Msk #define SCB_UART_RX_CTRL_POLARITY_Pos SCB_V2_UART_RX_CTRL_POLARITY_Pos #define SCB_UART_RX_CTRL_POLARITY_Msk SCB_V2_UART_RX_CTRL_POLARITY_Msk #define SCB_UART_RX_CTRL_DROP_ON_PARITY_ERROR_Pos SCB_V2_UART_RX_CTRL_DROP_ON_PARITY_ERROR_Pos #define SCB_UART_RX_CTRL_DROP_ON_PARITY_ERROR_Msk SCB_V2_UART_RX_CTRL_DROP_ON_PARITY_ERROR_Msk #define SCB_UART_RX_CTRL_DROP_ON_FRAME_ERROR_Pos SCB_V2_UART_RX_CTRL_DROP_ON_FRAME_ERROR_Pos #define SCB_UART_RX_CTRL_DROP_ON_FRAME_ERROR_Msk SCB_V2_UART_RX_CTRL_DROP_ON_FRAME_ERROR_Msk #define SCB_UART_RX_CTRL_MP_MODE_Pos SCB_V2_UART_RX_CTRL_MP_MODE_Pos #define SCB_UART_RX_CTRL_MP_MODE_Msk SCB_V2_UART_RX_CTRL_MP_MODE_Msk #define SCB_UART_RX_CTRL_LIN_MODE_Pos SCB_V2_UART_RX_CTRL_LIN_MODE_Pos #define SCB_UART_RX_CTRL_LIN_MODE_Msk SCB_V2_UART_RX_CTRL_LIN_MODE_Msk #define SCB_UART_RX_CTRL_SKIP_START_Pos SCB_V2_UART_RX_CTRL_SKIP_START_Pos #define SCB_UART_RX_CTRL_SKIP_START_Msk SCB_V2_UART_RX_CTRL_SKIP_START_Msk #define SCB_UART_RX_CTRL_BREAK_WIDTH_Pos SCB_V2_UART_RX_CTRL_BREAK_WIDTH_Pos #define SCB_UART_RX_CTRL_BREAK_WIDTH_Msk SCB_V2_UART_RX_CTRL_BREAK_WIDTH_Msk #define SCB_UART_RX_CTRL_BREAK_LEVEL_Pos SCB_V2_UART_RX_CTRL_BREAK_LEVEL_Pos #define SCB_UART_RX_CTRL_BREAK_LEVEL_Msk SCB_V2_UART_RX_CTRL_BREAK_LEVEL_Msk /* SCB.UART_RX_STATUS */ #define SCB_UART_RX_STATUS_BR_COUNTER_Pos SCB_V2_UART_RX_STATUS_BR_COUNTER_Pos #define SCB_UART_RX_STATUS_BR_COUNTER_Msk SCB_V2_UART_RX_STATUS_BR_COUNTER_Msk /* SCB.UART_FLOW_CTRL */ #define SCB_UART_FLOW_CTRL_TRIGGER_LEVEL_Pos SCB_V2_UART_FLOW_CTRL_TRIGGER_LEVEL_Pos #define SCB_UART_FLOW_CTRL_TRIGGER_LEVEL_Msk SCB_V2_UART_FLOW_CTRL_TRIGGER_LEVEL_Msk #define SCB_UART_FLOW_CTRL_RTS_POLARITY_Pos SCB_V2_UART_FLOW_CTRL_RTS_POLARITY_Pos #define SCB_UART_FLOW_CTRL_RTS_POLARITY_Msk SCB_V2_UART_FLOW_CTRL_RTS_POLARITY_Msk #define SCB_UART_FLOW_CTRL_CTS_POLARITY_Pos SCB_V2_UART_FLOW_CTRL_CTS_POLARITY_Pos #define SCB_UART_FLOW_CTRL_CTS_POLARITY_Msk SCB_V2_UART_FLOW_CTRL_CTS_POLARITY_Msk #define SCB_UART_FLOW_CTRL_CTS_ENABLED_Pos SCB_V2_UART_FLOW_CTRL_CTS_ENABLED_Pos #define SCB_UART_FLOW_CTRL_CTS_ENABLED_Msk SCB_V2_UART_FLOW_CTRL_CTS_ENABLED_Msk /* SCB.I2C_CTRL */ #define SCB_I2C_CTRL_HIGH_PHASE_OVS_Pos SCB_V2_I2C_CTRL_HIGH_PHASE_OVS_Pos #define SCB_I2C_CTRL_HIGH_PHASE_OVS_Msk SCB_V2_I2C_CTRL_HIGH_PHASE_OVS_Msk #define SCB_I2C_CTRL_LOW_PHASE_OVS_Pos SCB_V2_I2C_CTRL_LOW_PHASE_OVS_Pos #define SCB_I2C_CTRL_LOW_PHASE_OVS_Msk SCB_V2_I2C_CTRL_LOW_PHASE_OVS_Msk #define SCB_I2C_CTRL_M_READY_DATA_ACK_Pos SCB_V2_I2C_CTRL_M_READY_DATA_ACK_Pos #define SCB_I2C_CTRL_M_READY_DATA_ACK_Msk SCB_V2_I2C_CTRL_M_READY_DATA_ACK_Msk #define SCB_I2C_CTRL_M_NOT_READY_DATA_NACK_Pos SCB_V2_I2C_CTRL_M_NOT_READY_DATA_NACK_Pos #define SCB_I2C_CTRL_M_NOT_READY_DATA_NACK_Msk SCB_V2_I2C_CTRL_M_NOT_READY_DATA_NACK_Msk #define SCB_I2C_CTRL_S_GENERAL_IGNORE_Pos SCB_V2_I2C_CTRL_S_GENERAL_IGNORE_Pos #define SCB_I2C_CTRL_S_GENERAL_IGNORE_Msk SCB_V2_I2C_CTRL_S_GENERAL_IGNORE_Msk #define SCB_I2C_CTRL_S_READY_ADDR_ACK_Pos SCB_V2_I2C_CTRL_S_READY_ADDR_ACK_Pos #define SCB_I2C_CTRL_S_READY_ADDR_ACK_Msk SCB_V2_I2C_CTRL_S_READY_ADDR_ACK_Msk #define SCB_I2C_CTRL_S_READY_DATA_ACK_Pos SCB_V2_I2C_CTRL_S_READY_DATA_ACK_Pos #define SCB_I2C_CTRL_S_READY_DATA_ACK_Msk SCB_V2_I2C_CTRL_S_READY_DATA_ACK_Msk #define SCB_I2C_CTRL_S_NOT_READY_ADDR_NACK_Pos SCB_V2_I2C_CTRL_S_NOT_READY_ADDR_NACK_Pos #define SCB_I2C_CTRL_S_NOT_READY_ADDR_NACK_Msk SCB_V2_I2C_CTRL_S_NOT_READY_ADDR_NACK_Msk #define SCB_I2C_CTRL_S_NOT_READY_DATA_NACK_Pos SCB_V2_I2C_CTRL_S_NOT_READY_DATA_NACK_Pos #define SCB_I2C_CTRL_S_NOT_READY_DATA_NACK_Msk SCB_V2_I2C_CTRL_S_NOT_READY_DATA_NACK_Msk #define SCB_I2C_CTRL_LOOPBACK_Pos SCB_V2_I2C_CTRL_LOOPBACK_Pos #define SCB_I2C_CTRL_LOOPBACK_Msk SCB_V2_I2C_CTRL_LOOPBACK_Msk #define SCB_I2C_CTRL_SLAVE_MODE_Pos SCB_V2_I2C_CTRL_SLAVE_MODE_Pos #define SCB_I2C_CTRL_SLAVE_MODE_Msk SCB_V2_I2C_CTRL_SLAVE_MODE_Msk #define SCB_I2C_CTRL_MASTER_MODE_Pos SCB_V2_I2C_CTRL_MASTER_MODE_Pos #define SCB_I2C_CTRL_MASTER_MODE_Msk SCB_V2_I2C_CTRL_MASTER_MODE_Msk /* SCB.I2C_STATUS */ #define SCB_I2C_STATUS_BUS_BUSY_Pos SCB_V2_I2C_STATUS_BUS_BUSY_Pos #define SCB_I2C_STATUS_BUS_BUSY_Msk SCB_V2_I2C_STATUS_BUS_BUSY_Msk #define SCB_I2C_STATUS_I2C_EC_BUSY_Pos SCB_V2_I2C_STATUS_I2C_EC_BUSY_Pos #define SCB_I2C_STATUS_I2C_EC_BUSY_Msk SCB_V2_I2C_STATUS_I2C_EC_BUSY_Msk #define SCB_I2C_STATUS_I2CS_IC_BUSY_Pos SCB_V2_I2C_STATUS_I2CS_IC_BUSY_Pos #define SCB_I2C_STATUS_I2CS_IC_BUSY_Msk SCB_V2_I2C_STATUS_I2CS_IC_BUSY_Msk #define SCB_I2C_STATUS_S_READ_Pos SCB_V2_I2C_STATUS_S_READ_Pos #define SCB_I2C_STATUS_S_READ_Msk SCB_V2_I2C_STATUS_S_READ_Msk #define SCB_I2C_STATUS_M_READ_Pos SCB_V2_I2C_STATUS_M_READ_Pos #define SCB_I2C_STATUS_M_READ_Msk SCB_V2_I2C_STATUS_M_READ_Msk #define SCB_I2C_STATUS_CURR_EZ_ADDR_Pos SCB_V2_I2C_STATUS_CURR_EZ_ADDR_Pos #define SCB_I2C_STATUS_CURR_EZ_ADDR_Msk SCB_V2_I2C_STATUS_CURR_EZ_ADDR_Msk #define SCB_I2C_STATUS_BASE_EZ_ADDR_Pos SCB_V2_I2C_STATUS_BASE_EZ_ADDR_Pos #define SCB_I2C_STATUS_BASE_EZ_ADDR_Msk SCB_V2_I2C_STATUS_BASE_EZ_ADDR_Msk /* SCB.I2C_M_CMD */ #define SCB_I2C_M_CMD_M_START_Pos SCB_V2_I2C_M_CMD_M_START_Pos #define SCB_I2C_M_CMD_M_START_Msk SCB_V2_I2C_M_CMD_M_START_Msk #define SCB_I2C_M_CMD_M_START_ON_IDLE_Pos SCB_V2_I2C_M_CMD_M_START_ON_IDLE_Pos #define SCB_I2C_M_CMD_M_START_ON_IDLE_Msk SCB_V2_I2C_M_CMD_M_START_ON_IDLE_Msk #define SCB_I2C_M_CMD_M_ACK_Pos SCB_V2_I2C_M_CMD_M_ACK_Pos #define SCB_I2C_M_CMD_M_ACK_Msk SCB_V2_I2C_M_CMD_M_ACK_Msk #define SCB_I2C_M_CMD_M_NACK_Pos SCB_V2_I2C_M_CMD_M_NACK_Pos #define SCB_I2C_M_CMD_M_NACK_Msk SCB_V2_I2C_M_CMD_M_NACK_Msk #define SCB_I2C_M_CMD_M_STOP_Pos SCB_V2_I2C_M_CMD_M_STOP_Pos #define SCB_I2C_M_CMD_M_STOP_Msk SCB_V2_I2C_M_CMD_M_STOP_Msk /* SCB.I2C_S_CMD */ #define SCB_I2C_S_CMD_S_ACK_Pos SCB_V2_I2C_S_CMD_S_ACK_Pos #define SCB_I2C_S_CMD_S_ACK_Msk SCB_V2_I2C_S_CMD_S_ACK_Msk #define SCB_I2C_S_CMD_S_NACK_Pos SCB_V2_I2C_S_CMD_S_NACK_Pos #define SCB_I2C_S_CMD_S_NACK_Msk SCB_V2_I2C_S_CMD_S_NACK_Msk /* SCB.I2C_CFG */ #define SCB_I2C_CFG_SDA_IN_FILT_TRIM_Pos SCB_V2_I2C_CFG_SDA_IN_FILT_TRIM_Pos #define SCB_I2C_CFG_SDA_IN_FILT_TRIM_Msk SCB_V2_I2C_CFG_SDA_IN_FILT_TRIM_Msk #define SCB_I2C_CFG_SDA_IN_FILT_SEL_Pos SCB_V2_I2C_CFG_SDA_IN_FILT_SEL_Pos #define SCB_I2C_CFG_SDA_IN_FILT_SEL_Msk SCB_V2_I2C_CFG_SDA_IN_FILT_SEL_Msk #define SCB_I2C_CFG_SCL_IN_FILT_TRIM_Pos SCB_V2_I2C_CFG_SCL_IN_FILT_TRIM_Pos #define SCB_I2C_CFG_SCL_IN_FILT_TRIM_Msk SCB_V2_I2C_CFG_SCL_IN_FILT_TRIM_Msk #define SCB_I2C_CFG_SCL_IN_FILT_SEL_Pos SCB_V2_I2C_CFG_SCL_IN_FILT_SEL_Pos #define SCB_I2C_CFG_SCL_IN_FILT_SEL_Msk SCB_V2_I2C_CFG_SCL_IN_FILT_SEL_Msk #define SCB_I2C_CFG_SDA_OUT_FILT0_TRIM_Pos SCB_V2_I2C_CFG_SDA_OUT_FILT0_TRIM_Pos #define SCB_I2C_CFG_SDA_OUT_FILT0_TRIM_Msk SCB_V2_I2C_CFG_SDA_OUT_FILT0_TRIM_Msk #define SCB_I2C_CFG_SDA_OUT_FILT1_TRIM_Pos SCB_V2_I2C_CFG_SDA_OUT_FILT1_TRIM_Pos #define SCB_I2C_CFG_SDA_OUT_FILT1_TRIM_Msk SCB_V2_I2C_CFG_SDA_OUT_FILT1_TRIM_Msk #define SCB_I2C_CFG_SDA_OUT_FILT2_TRIM_Pos SCB_V2_I2C_CFG_SDA_OUT_FILT2_TRIM_Pos #define SCB_I2C_CFG_SDA_OUT_FILT2_TRIM_Msk SCB_V2_I2C_CFG_SDA_OUT_FILT2_TRIM_Msk #define SCB_I2C_CFG_SDA_OUT_FILT_SEL_Pos SCB_V2_I2C_CFG_SDA_OUT_FILT_SEL_Pos #define SCB_I2C_CFG_SDA_OUT_FILT_SEL_Msk SCB_V2_I2C_CFG_SDA_OUT_FILT_SEL_Msk /* SCB.TX_CTRL */ #define SCB_TX_CTRL_DATA_WIDTH_Pos SCB_V2_TX_CTRL_DATA_WIDTH_Pos #define SCB_TX_CTRL_DATA_WIDTH_Msk SCB_V2_TX_CTRL_DATA_WIDTH_Msk #define SCB_TX_CTRL_MSB_FIRST_Pos SCB_V2_TX_CTRL_MSB_FIRST_Pos #define SCB_TX_CTRL_MSB_FIRST_Msk SCB_V2_TX_CTRL_MSB_FIRST_Msk #define SCB_TX_CTRL_OPEN_DRAIN_Pos SCB_V2_TX_CTRL_OPEN_DRAIN_Pos #define SCB_TX_CTRL_OPEN_DRAIN_Msk SCB_V2_TX_CTRL_OPEN_DRAIN_Msk /* SCB.TX_FIFO_CTRL */ #define SCB_TX_FIFO_CTRL_TRIGGER_LEVEL_Pos SCB_V2_TX_FIFO_CTRL_TRIGGER_LEVEL_Pos #define SCB_TX_FIFO_CTRL_TRIGGER_LEVEL_Msk SCB_V2_TX_FIFO_CTRL_TRIGGER_LEVEL_Msk #define SCB_TX_FIFO_CTRL_CLEAR_Pos SCB_V2_TX_FIFO_CTRL_CLEAR_Pos #define SCB_TX_FIFO_CTRL_CLEAR_Msk SCB_V2_TX_FIFO_CTRL_CLEAR_Msk #define SCB_TX_FIFO_CTRL_FREEZE_Pos SCB_V2_TX_FIFO_CTRL_FREEZE_Pos #define SCB_TX_FIFO_CTRL_FREEZE_Msk SCB_V2_TX_FIFO_CTRL_FREEZE_Msk /* SCB.TX_FIFO_STATUS */ #define SCB_TX_FIFO_STATUS_USED_Pos SCB_V2_TX_FIFO_STATUS_USED_Pos #define SCB_TX_FIFO_STATUS_USED_Msk SCB_V2_TX_FIFO_STATUS_USED_Msk #define SCB_TX_FIFO_STATUS_SR_VALID_Pos SCB_V2_TX_FIFO_STATUS_SR_VALID_Pos #define SCB_TX_FIFO_STATUS_SR_VALID_Msk SCB_V2_TX_FIFO_STATUS_SR_VALID_Msk #define SCB_TX_FIFO_STATUS_RD_PTR_Pos SCB_V2_TX_FIFO_STATUS_RD_PTR_Pos #define SCB_TX_FIFO_STATUS_RD_PTR_Msk SCB_V2_TX_FIFO_STATUS_RD_PTR_Msk #define SCB_TX_FIFO_STATUS_WR_PTR_Pos SCB_V2_TX_FIFO_STATUS_WR_PTR_Pos #define SCB_TX_FIFO_STATUS_WR_PTR_Msk SCB_V2_TX_FIFO_STATUS_WR_PTR_Msk /* SCB.TX_FIFO_WR */ #define SCB_TX_FIFO_WR_DATA_Pos SCB_V2_TX_FIFO_WR_DATA_Pos #define SCB_TX_FIFO_WR_DATA_Msk SCB_V2_TX_FIFO_WR_DATA_Msk /* SCB.RX_CTRL */ #define SCB_RX_CTRL_DATA_WIDTH_Pos SCB_V2_RX_CTRL_DATA_WIDTH_Pos #define SCB_RX_CTRL_DATA_WIDTH_Msk SCB_V2_RX_CTRL_DATA_WIDTH_Msk #define SCB_RX_CTRL_MSB_FIRST_Pos SCB_V2_RX_CTRL_MSB_FIRST_Pos #define SCB_RX_CTRL_MSB_FIRST_Msk SCB_V2_RX_CTRL_MSB_FIRST_Msk #define SCB_RX_CTRL_MEDIAN_Pos SCB_V2_RX_CTRL_MEDIAN_Pos #define SCB_RX_CTRL_MEDIAN_Msk SCB_V2_RX_CTRL_MEDIAN_Msk /* SCB.RX_FIFO_CTRL */ #define SCB_RX_FIFO_CTRL_TRIGGER_LEVEL_Pos SCB_V2_RX_FIFO_CTRL_TRIGGER_LEVEL_Pos #define SCB_RX_FIFO_CTRL_TRIGGER_LEVEL_Msk SCB_V2_RX_FIFO_CTRL_TRIGGER_LEVEL_Msk #define SCB_RX_FIFO_CTRL_CLEAR_Pos SCB_V2_RX_FIFO_CTRL_CLEAR_Pos #define SCB_RX_FIFO_CTRL_CLEAR_Msk SCB_V2_RX_FIFO_CTRL_CLEAR_Msk #define SCB_RX_FIFO_CTRL_FREEZE_Pos SCB_V2_RX_FIFO_CTRL_FREEZE_Pos #define SCB_RX_FIFO_CTRL_FREEZE_Msk SCB_V2_RX_FIFO_CTRL_FREEZE_Msk /* SCB.RX_FIFO_STATUS */ #define SCB_RX_FIFO_STATUS_USED_Pos SCB_V2_RX_FIFO_STATUS_USED_Pos #define SCB_RX_FIFO_STATUS_USED_Msk SCB_V2_RX_FIFO_STATUS_USED_Msk #define SCB_RX_FIFO_STATUS_SR_VALID_Pos SCB_V2_RX_FIFO_STATUS_SR_VALID_Pos #define SCB_RX_FIFO_STATUS_SR_VALID_Msk SCB_V2_RX_FIFO_STATUS_SR_VALID_Msk #define SCB_RX_FIFO_STATUS_RD_PTR_Pos SCB_V2_RX_FIFO_STATUS_RD_PTR_Pos #define SCB_RX_FIFO_STATUS_RD_PTR_Msk SCB_V2_RX_FIFO_STATUS_RD_PTR_Msk #define SCB_RX_FIFO_STATUS_WR_PTR_Pos SCB_V2_RX_FIFO_STATUS_WR_PTR_Pos #define SCB_RX_FIFO_STATUS_WR_PTR_Msk SCB_V2_RX_FIFO_STATUS_WR_PTR_Msk /* SCB.RX_MATCH */ #define SCB_RX_MATCH_ADDR_Pos SCB_V2_RX_MATCH_ADDR_Pos #define SCB_RX_MATCH_ADDR_Msk SCB_V2_RX_MATCH_ADDR_Msk #define SCB_RX_MATCH_MASK_Pos SCB_V2_RX_MATCH_MASK_Pos #define SCB_RX_MATCH_MASK_Msk SCB_V2_RX_MATCH_MASK_Msk /* SCB.RX_FIFO_RD */ #define SCB_RX_FIFO_RD_DATA_Pos SCB_V2_RX_FIFO_RD_DATA_Pos #define SCB_RX_FIFO_RD_DATA_Msk SCB_V2_RX_FIFO_RD_DATA_Msk /* SCB.RX_FIFO_RD_SILENT */ #define SCB_RX_FIFO_RD_SILENT_DATA_Pos SCB_V2_RX_FIFO_RD_SILENT_DATA_Pos #define SCB_RX_FIFO_RD_SILENT_DATA_Msk SCB_V2_RX_FIFO_RD_SILENT_DATA_Msk /* SCB.EZ_DATA */ #define SCB_EZ_DATA_EZ_DATA_Pos SCB_V2_EZ_DATA_EZ_DATA_Pos #define SCB_EZ_DATA_EZ_DATA_Msk SCB_V2_EZ_DATA_EZ_DATA_Msk /* SCB.INTR_CAUSE */ #define SCB_INTR_CAUSE_M_Pos SCB_V2_INTR_CAUSE_M_Pos #define SCB_INTR_CAUSE_M_Msk SCB_V2_INTR_CAUSE_M_Msk #define SCB_INTR_CAUSE_S_Pos SCB_V2_INTR_CAUSE_S_Pos #define SCB_INTR_CAUSE_S_Msk SCB_V2_INTR_CAUSE_S_Msk #define SCB_INTR_CAUSE_TX_Pos SCB_V2_INTR_CAUSE_TX_Pos #define SCB_INTR_CAUSE_TX_Msk SCB_V2_INTR_CAUSE_TX_Msk #define SCB_INTR_CAUSE_RX_Pos SCB_V2_INTR_CAUSE_RX_Pos #define SCB_INTR_CAUSE_RX_Msk SCB_V2_INTR_CAUSE_RX_Msk #define SCB_INTR_CAUSE_I2C_EC_Pos SCB_V2_INTR_CAUSE_I2C_EC_Pos #define SCB_INTR_CAUSE_I2C_EC_Msk SCB_V2_INTR_CAUSE_I2C_EC_Msk #define SCB_INTR_CAUSE_SPI_EC_Pos SCB_V2_INTR_CAUSE_SPI_EC_Pos #define SCB_INTR_CAUSE_SPI_EC_Msk SCB_V2_INTR_CAUSE_SPI_EC_Msk /* SCB.INTR_I2C_EC */ #define SCB_INTR_I2C_EC_WAKE_UP_Pos SCB_V2_INTR_I2C_EC_WAKE_UP_Pos #define SCB_INTR_I2C_EC_WAKE_UP_Msk SCB_V2_INTR_I2C_EC_WAKE_UP_Msk #define SCB_INTR_I2C_EC_EZ_STOP_Pos SCB_V2_INTR_I2C_EC_EZ_STOP_Pos #define SCB_INTR_I2C_EC_EZ_STOP_Msk SCB_V2_INTR_I2C_EC_EZ_STOP_Msk #define SCB_INTR_I2C_EC_EZ_WRITE_STOP_Pos SCB_V2_INTR_I2C_EC_EZ_WRITE_STOP_Pos #define SCB_INTR_I2C_EC_EZ_WRITE_STOP_Msk SCB_V2_INTR_I2C_EC_EZ_WRITE_STOP_Msk #define SCB_INTR_I2C_EC_EZ_READ_STOP_Pos SCB_V2_INTR_I2C_EC_EZ_READ_STOP_Pos #define SCB_INTR_I2C_EC_EZ_READ_STOP_Msk SCB_V2_INTR_I2C_EC_EZ_READ_STOP_Msk /* SCB.INTR_I2C_EC_MASK */ #define SCB_INTR_I2C_EC_MASK_WAKE_UP_Pos SCB_V2_INTR_I2C_EC_MASK_WAKE_UP_Pos #define SCB_INTR_I2C_EC_MASK_WAKE_UP_Msk SCB_V2_INTR_I2C_EC_MASK_WAKE_UP_Msk #define SCB_INTR_I2C_EC_MASK_EZ_STOP_Pos SCB_V2_INTR_I2C_EC_MASK_EZ_STOP_Pos #define SCB_INTR_I2C_EC_MASK_EZ_STOP_Msk SCB_V2_INTR_I2C_EC_MASK_EZ_STOP_Msk #define SCB_INTR_I2C_EC_MASK_EZ_WRITE_STOP_Pos SCB_V2_INTR_I2C_EC_MASK_EZ_WRITE_STOP_Pos #define SCB_INTR_I2C_EC_MASK_EZ_WRITE_STOP_Msk SCB_V2_INTR_I2C_EC_MASK_EZ_WRITE_STOP_Msk #define SCB_INTR_I2C_EC_MASK_EZ_READ_STOP_Pos SCB_V2_INTR_I2C_EC_MASK_EZ_READ_STOP_Pos #define SCB_INTR_I2C_EC_MASK_EZ_READ_STOP_Msk SCB_V2_INTR_I2C_EC_MASK_EZ_READ_STOP_Msk /* SCB.INTR_I2C_EC_MASKED */ #define SCB_INTR_I2C_EC_MASKED_WAKE_UP_Pos SCB_V2_INTR_I2C_EC_MASKED_WAKE_UP_Pos #define SCB_INTR_I2C_EC_MASKED_WAKE_UP_Msk SCB_V2_INTR_I2C_EC_MASKED_WAKE_UP_Msk #define SCB_INTR_I2C_EC_MASKED_EZ_STOP_Pos SCB_V2_INTR_I2C_EC_MASKED_EZ_STOP_Pos #define SCB_INTR_I2C_EC_MASKED_EZ_STOP_Msk SCB_V2_INTR_I2C_EC_MASKED_EZ_STOP_Msk #define SCB_INTR_I2C_EC_MASKED_EZ_WRITE_STOP_Pos SCB_V2_INTR_I2C_EC_MASKED_EZ_WRITE_STOP_Pos #define SCB_INTR_I2C_EC_MASKED_EZ_WRITE_STOP_Msk SCB_V2_INTR_I2C_EC_MASKED_EZ_WRITE_STOP_Msk #define SCB_INTR_I2C_EC_MASKED_EZ_READ_STOP_Pos SCB_V2_INTR_I2C_EC_MASKED_EZ_READ_STOP_Pos #define SCB_INTR_I2C_EC_MASKED_EZ_READ_STOP_Msk SCB_V2_INTR_I2C_EC_MASKED_EZ_READ_STOP_Msk /* SCB.INTR_SPI_EC */ #define SCB_INTR_SPI_EC_WAKE_UP_Pos SCB_V2_INTR_SPI_EC_WAKE_UP_Pos #define SCB_INTR_SPI_EC_WAKE_UP_Msk SCB_V2_INTR_SPI_EC_WAKE_UP_Msk #define SCB_INTR_SPI_EC_EZ_STOP_Pos SCB_V2_INTR_SPI_EC_EZ_STOP_Pos #define SCB_INTR_SPI_EC_EZ_STOP_Msk SCB_V2_INTR_SPI_EC_EZ_STOP_Msk #define SCB_INTR_SPI_EC_EZ_WRITE_STOP_Pos SCB_V2_INTR_SPI_EC_EZ_WRITE_STOP_Pos #define SCB_INTR_SPI_EC_EZ_WRITE_STOP_Msk SCB_V2_INTR_SPI_EC_EZ_WRITE_STOP_Msk #define SCB_INTR_SPI_EC_EZ_READ_STOP_Pos SCB_V2_INTR_SPI_EC_EZ_READ_STOP_Pos #define SCB_INTR_SPI_EC_EZ_READ_STOP_Msk SCB_V2_INTR_SPI_EC_EZ_READ_STOP_Msk /* SCB.INTR_SPI_EC_MASK */ #define SCB_INTR_SPI_EC_MASK_WAKE_UP_Pos SCB_V2_INTR_SPI_EC_MASK_WAKE_UP_Pos #define SCB_INTR_SPI_EC_MASK_WAKE_UP_Msk SCB_V2_INTR_SPI_EC_MASK_WAKE_UP_Msk #define SCB_INTR_SPI_EC_MASK_EZ_STOP_Pos SCB_V2_INTR_SPI_EC_MASK_EZ_STOP_Pos #define SCB_INTR_SPI_EC_MASK_EZ_STOP_Msk SCB_V2_INTR_SPI_EC_MASK_EZ_STOP_Msk #define SCB_INTR_SPI_EC_MASK_EZ_WRITE_STOP_Pos SCB_V2_INTR_SPI_EC_MASK_EZ_WRITE_STOP_Pos #define SCB_INTR_SPI_EC_MASK_EZ_WRITE_STOP_Msk SCB_V2_INTR_SPI_EC_MASK_EZ_WRITE_STOP_Msk #define SCB_INTR_SPI_EC_MASK_EZ_READ_STOP_Pos SCB_V2_INTR_SPI_EC_MASK_EZ_READ_STOP_Pos #define SCB_INTR_SPI_EC_MASK_EZ_READ_STOP_Msk SCB_V2_INTR_SPI_EC_MASK_EZ_READ_STOP_Msk /* SCB.INTR_SPI_EC_MASKED */ #define SCB_INTR_SPI_EC_MASKED_WAKE_UP_Pos SCB_V2_INTR_SPI_EC_MASKED_WAKE_UP_Pos #define SCB_INTR_SPI_EC_MASKED_WAKE_UP_Msk SCB_V2_INTR_SPI_EC_MASKED_WAKE_UP_Msk #define SCB_INTR_SPI_EC_MASKED_EZ_STOP_Pos SCB_V2_INTR_SPI_EC_MASKED_EZ_STOP_Pos #define SCB_INTR_SPI_EC_MASKED_EZ_STOP_Msk SCB_V2_INTR_SPI_EC_MASKED_EZ_STOP_Msk #define SCB_INTR_SPI_EC_MASKED_EZ_WRITE_STOP_Pos SCB_V2_INTR_SPI_EC_MASKED_EZ_WRITE_STOP_Pos #define SCB_INTR_SPI_EC_MASKED_EZ_WRITE_STOP_Msk SCB_V2_INTR_SPI_EC_MASKED_EZ_WRITE_STOP_Msk #define SCB_INTR_SPI_EC_MASKED_EZ_READ_STOP_Pos SCB_V2_INTR_SPI_EC_MASKED_EZ_READ_STOP_Pos #define SCB_INTR_SPI_EC_MASKED_EZ_READ_STOP_Msk SCB_V2_INTR_SPI_EC_MASKED_EZ_READ_STOP_Msk /* SCB.INTR_M */ #define SCB_INTR_M_I2C_ARB_LOST_Pos SCB_V2_INTR_M_I2C_ARB_LOST_Pos #define SCB_INTR_M_I2C_ARB_LOST_Msk SCB_V2_INTR_M_I2C_ARB_LOST_Msk #define SCB_INTR_M_I2C_NACK_Pos SCB_V2_INTR_M_I2C_NACK_Pos #define SCB_INTR_M_I2C_NACK_Msk SCB_V2_INTR_M_I2C_NACK_Msk #define SCB_INTR_M_I2C_ACK_Pos SCB_V2_INTR_M_I2C_ACK_Pos #define SCB_INTR_M_I2C_ACK_Msk SCB_V2_INTR_M_I2C_ACK_Msk #define SCB_INTR_M_I2C_STOP_Pos SCB_V2_INTR_M_I2C_STOP_Pos #define SCB_INTR_M_I2C_STOP_Msk SCB_V2_INTR_M_I2C_STOP_Msk #define SCB_INTR_M_I2C_BUS_ERROR_Pos SCB_V2_INTR_M_I2C_BUS_ERROR_Pos #define SCB_INTR_M_I2C_BUS_ERROR_Msk SCB_V2_INTR_M_I2C_BUS_ERROR_Msk #define SCB_INTR_M_SPI_DONE_Pos SCB_V2_INTR_M_SPI_DONE_Pos #define SCB_INTR_M_SPI_DONE_Msk SCB_V2_INTR_M_SPI_DONE_Msk /* SCB.INTR_M_SET */ #define SCB_INTR_M_SET_I2C_ARB_LOST_Pos SCB_V2_INTR_M_SET_I2C_ARB_LOST_Pos #define SCB_INTR_M_SET_I2C_ARB_LOST_Msk SCB_V2_INTR_M_SET_I2C_ARB_LOST_Msk #define SCB_INTR_M_SET_I2C_NACK_Pos SCB_V2_INTR_M_SET_I2C_NACK_Pos #define SCB_INTR_M_SET_I2C_NACK_Msk SCB_V2_INTR_M_SET_I2C_NACK_Msk #define SCB_INTR_M_SET_I2C_ACK_Pos SCB_V2_INTR_M_SET_I2C_ACK_Pos #define SCB_INTR_M_SET_I2C_ACK_Msk SCB_V2_INTR_M_SET_I2C_ACK_Msk #define SCB_INTR_M_SET_I2C_STOP_Pos SCB_V2_INTR_M_SET_I2C_STOP_Pos #define SCB_INTR_M_SET_I2C_STOP_Msk SCB_V2_INTR_M_SET_I2C_STOP_Msk #define SCB_INTR_M_SET_I2C_BUS_ERROR_Pos SCB_V2_INTR_M_SET_I2C_BUS_ERROR_Pos #define SCB_INTR_M_SET_I2C_BUS_ERROR_Msk SCB_V2_INTR_M_SET_I2C_BUS_ERROR_Msk #define SCB_INTR_M_SET_SPI_DONE_Pos SCB_V2_INTR_M_SET_SPI_DONE_Pos #define SCB_INTR_M_SET_SPI_DONE_Msk SCB_V2_INTR_M_SET_SPI_DONE_Msk /* SCB.INTR_M_MASK */ #define SCB_INTR_M_MASK_I2C_ARB_LOST_Pos SCB_V2_INTR_M_MASK_I2C_ARB_LOST_Pos #define SCB_INTR_M_MASK_I2C_ARB_LOST_Msk SCB_V2_INTR_M_MASK_I2C_ARB_LOST_Msk #define SCB_INTR_M_MASK_I2C_NACK_Pos SCB_V2_INTR_M_MASK_I2C_NACK_Pos #define SCB_INTR_M_MASK_I2C_NACK_Msk SCB_V2_INTR_M_MASK_I2C_NACK_Msk #define SCB_INTR_M_MASK_I2C_ACK_Pos SCB_V2_INTR_M_MASK_I2C_ACK_Pos #define SCB_INTR_M_MASK_I2C_ACK_Msk SCB_V2_INTR_M_MASK_I2C_ACK_Msk #define SCB_INTR_M_MASK_I2C_STOP_Pos SCB_V2_INTR_M_MASK_I2C_STOP_Pos #define SCB_INTR_M_MASK_I2C_STOP_Msk SCB_V2_INTR_M_MASK_I2C_STOP_Msk #define SCB_INTR_M_MASK_I2C_BUS_ERROR_Pos SCB_V2_INTR_M_MASK_I2C_BUS_ERROR_Pos #define SCB_INTR_M_MASK_I2C_BUS_ERROR_Msk SCB_V2_INTR_M_MASK_I2C_BUS_ERROR_Msk #define SCB_INTR_M_MASK_SPI_DONE_Pos SCB_V2_INTR_M_MASK_SPI_DONE_Pos #define SCB_INTR_M_MASK_SPI_DONE_Msk SCB_V2_INTR_M_MASK_SPI_DONE_Msk /* SCB.INTR_M_MASKED */ #define SCB_INTR_M_MASKED_I2C_ARB_LOST_Pos SCB_V2_INTR_M_MASKED_I2C_ARB_LOST_Pos #define SCB_INTR_M_MASKED_I2C_ARB_LOST_Msk SCB_V2_INTR_M_MASKED_I2C_ARB_LOST_Msk #define SCB_INTR_M_MASKED_I2C_NACK_Pos SCB_V2_INTR_M_MASKED_I2C_NACK_Pos #define SCB_INTR_M_MASKED_I2C_NACK_Msk SCB_V2_INTR_M_MASKED_I2C_NACK_Msk #define SCB_INTR_M_MASKED_I2C_ACK_Pos SCB_V2_INTR_M_MASKED_I2C_ACK_Pos #define SCB_INTR_M_MASKED_I2C_ACK_Msk SCB_V2_INTR_M_MASKED_I2C_ACK_Msk #define SCB_INTR_M_MASKED_I2C_STOP_Pos SCB_V2_INTR_M_MASKED_I2C_STOP_Pos #define SCB_INTR_M_MASKED_I2C_STOP_Msk SCB_V2_INTR_M_MASKED_I2C_STOP_Msk #define SCB_INTR_M_MASKED_I2C_BUS_ERROR_Pos SCB_V2_INTR_M_MASKED_I2C_BUS_ERROR_Pos #define SCB_INTR_M_MASKED_I2C_BUS_ERROR_Msk SCB_V2_INTR_M_MASKED_I2C_BUS_ERROR_Msk #define SCB_INTR_M_MASKED_SPI_DONE_Pos SCB_V2_INTR_M_MASKED_SPI_DONE_Pos #define SCB_INTR_M_MASKED_SPI_DONE_Msk SCB_V2_INTR_M_MASKED_SPI_DONE_Msk /* SCB.INTR_S */ #define SCB_INTR_S_I2C_ARB_LOST_Pos SCB_V2_INTR_S_I2C_ARB_LOST_Pos #define SCB_INTR_S_I2C_ARB_LOST_Msk SCB_V2_INTR_S_I2C_ARB_LOST_Msk #define SCB_INTR_S_I2C_NACK_Pos SCB_V2_INTR_S_I2C_NACK_Pos #define SCB_INTR_S_I2C_NACK_Msk SCB_V2_INTR_S_I2C_NACK_Msk #define SCB_INTR_S_I2C_ACK_Pos SCB_V2_INTR_S_I2C_ACK_Pos #define SCB_INTR_S_I2C_ACK_Msk SCB_V2_INTR_S_I2C_ACK_Msk #define SCB_INTR_S_I2C_WRITE_STOP_Pos SCB_V2_INTR_S_I2C_WRITE_STOP_Pos #define SCB_INTR_S_I2C_WRITE_STOP_Msk SCB_V2_INTR_S_I2C_WRITE_STOP_Msk #define SCB_INTR_S_I2C_STOP_Pos SCB_V2_INTR_S_I2C_STOP_Pos #define SCB_INTR_S_I2C_STOP_Msk SCB_V2_INTR_S_I2C_STOP_Msk #define SCB_INTR_S_I2C_START_Pos SCB_V2_INTR_S_I2C_START_Pos #define SCB_INTR_S_I2C_START_Msk SCB_V2_INTR_S_I2C_START_Msk #define SCB_INTR_S_I2C_ADDR_MATCH_Pos SCB_V2_INTR_S_I2C_ADDR_MATCH_Pos #define SCB_INTR_S_I2C_ADDR_MATCH_Msk SCB_V2_INTR_S_I2C_ADDR_MATCH_Msk #define SCB_INTR_S_I2C_GENERAL_Pos SCB_V2_INTR_S_I2C_GENERAL_Pos #define SCB_INTR_S_I2C_GENERAL_Msk SCB_V2_INTR_S_I2C_GENERAL_Msk #define SCB_INTR_S_I2C_BUS_ERROR_Pos SCB_V2_INTR_S_I2C_BUS_ERROR_Pos #define SCB_INTR_S_I2C_BUS_ERROR_Msk SCB_V2_INTR_S_I2C_BUS_ERROR_Msk #define SCB_INTR_S_SPI_EZ_WRITE_STOP_Pos SCB_V2_INTR_S_SPI_EZ_WRITE_STOP_Pos #define SCB_INTR_S_SPI_EZ_WRITE_STOP_Msk SCB_V2_INTR_S_SPI_EZ_WRITE_STOP_Msk #define SCB_INTR_S_SPI_EZ_STOP_Pos SCB_V2_INTR_S_SPI_EZ_STOP_Pos #define SCB_INTR_S_SPI_EZ_STOP_Msk SCB_V2_INTR_S_SPI_EZ_STOP_Msk #define SCB_INTR_S_SPI_BUS_ERROR_Pos SCB_V2_INTR_S_SPI_BUS_ERROR_Pos #define SCB_INTR_S_SPI_BUS_ERROR_Msk SCB_V2_INTR_S_SPI_BUS_ERROR_Msk /* SCB.INTR_S_SET */ #define SCB_INTR_S_SET_I2C_ARB_LOST_Pos SCB_V2_INTR_S_SET_I2C_ARB_LOST_Pos #define SCB_INTR_S_SET_I2C_ARB_LOST_Msk SCB_V2_INTR_S_SET_I2C_ARB_LOST_Msk #define SCB_INTR_S_SET_I2C_NACK_Pos SCB_V2_INTR_S_SET_I2C_NACK_Pos #define SCB_INTR_S_SET_I2C_NACK_Msk SCB_V2_INTR_S_SET_I2C_NACK_Msk #define SCB_INTR_S_SET_I2C_ACK_Pos SCB_V2_INTR_S_SET_I2C_ACK_Pos #define SCB_INTR_S_SET_I2C_ACK_Msk SCB_V2_INTR_S_SET_I2C_ACK_Msk #define SCB_INTR_S_SET_I2C_WRITE_STOP_Pos SCB_V2_INTR_S_SET_I2C_WRITE_STOP_Pos #define SCB_INTR_S_SET_I2C_WRITE_STOP_Msk SCB_V2_INTR_S_SET_I2C_WRITE_STOP_Msk #define SCB_INTR_S_SET_I2C_STOP_Pos SCB_V2_INTR_S_SET_I2C_STOP_Pos #define SCB_INTR_S_SET_I2C_STOP_Msk SCB_V2_INTR_S_SET_I2C_STOP_Msk #define SCB_INTR_S_SET_I2C_START_Pos SCB_V2_INTR_S_SET_I2C_START_Pos #define SCB_INTR_S_SET_I2C_START_Msk SCB_V2_INTR_S_SET_I2C_START_Msk #define SCB_INTR_S_SET_I2C_ADDR_MATCH_Pos SCB_V2_INTR_S_SET_I2C_ADDR_MATCH_Pos #define SCB_INTR_S_SET_I2C_ADDR_MATCH_Msk SCB_V2_INTR_S_SET_I2C_ADDR_MATCH_Msk #define SCB_INTR_S_SET_I2C_GENERAL_Pos SCB_V2_INTR_S_SET_I2C_GENERAL_Pos #define SCB_INTR_S_SET_I2C_GENERAL_Msk SCB_V2_INTR_S_SET_I2C_GENERAL_Msk #define SCB_INTR_S_SET_I2C_BUS_ERROR_Pos SCB_V2_INTR_S_SET_I2C_BUS_ERROR_Pos #define SCB_INTR_S_SET_I2C_BUS_ERROR_Msk SCB_V2_INTR_S_SET_I2C_BUS_ERROR_Msk #define SCB_INTR_S_SET_SPI_EZ_WRITE_STOP_Pos SCB_V2_INTR_S_SET_SPI_EZ_WRITE_STOP_Pos #define SCB_INTR_S_SET_SPI_EZ_WRITE_STOP_Msk SCB_V2_INTR_S_SET_SPI_EZ_WRITE_STOP_Msk #define SCB_INTR_S_SET_SPI_EZ_STOP_Pos SCB_V2_INTR_S_SET_SPI_EZ_STOP_Pos #define SCB_INTR_S_SET_SPI_EZ_STOP_Msk SCB_V2_INTR_S_SET_SPI_EZ_STOP_Msk #define SCB_INTR_S_SET_SPI_BUS_ERROR_Pos SCB_V2_INTR_S_SET_SPI_BUS_ERROR_Pos #define SCB_INTR_S_SET_SPI_BUS_ERROR_Msk SCB_V2_INTR_S_SET_SPI_BUS_ERROR_Msk /* SCB.INTR_S_MASK */ #define SCB_INTR_S_MASK_I2C_ARB_LOST_Pos SCB_V2_INTR_S_MASK_I2C_ARB_LOST_Pos #define SCB_INTR_S_MASK_I2C_ARB_LOST_Msk SCB_V2_INTR_S_MASK_I2C_ARB_LOST_Msk #define SCB_INTR_S_MASK_I2C_NACK_Pos SCB_V2_INTR_S_MASK_I2C_NACK_Pos #define SCB_INTR_S_MASK_I2C_NACK_Msk SCB_V2_INTR_S_MASK_I2C_NACK_Msk #define SCB_INTR_S_MASK_I2C_ACK_Pos SCB_V2_INTR_S_MASK_I2C_ACK_Pos #define SCB_INTR_S_MASK_I2C_ACK_Msk SCB_V2_INTR_S_MASK_I2C_ACK_Msk #define SCB_INTR_S_MASK_I2C_WRITE_STOP_Pos SCB_V2_INTR_S_MASK_I2C_WRITE_STOP_Pos #define SCB_INTR_S_MASK_I2C_WRITE_STOP_Msk SCB_V2_INTR_S_MASK_I2C_WRITE_STOP_Msk #define SCB_INTR_S_MASK_I2C_STOP_Pos SCB_V2_INTR_S_MASK_I2C_STOP_Pos #define SCB_INTR_S_MASK_I2C_STOP_Msk SCB_V2_INTR_S_MASK_I2C_STOP_Msk #define SCB_INTR_S_MASK_I2C_START_Pos SCB_V2_INTR_S_MASK_I2C_START_Pos #define SCB_INTR_S_MASK_I2C_START_Msk SCB_V2_INTR_S_MASK_I2C_START_Msk #define SCB_INTR_S_MASK_I2C_ADDR_MATCH_Pos SCB_V2_INTR_S_MASK_I2C_ADDR_MATCH_Pos #define SCB_INTR_S_MASK_I2C_ADDR_MATCH_Msk SCB_V2_INTR_S_MASK_I2C_ADDR_MATCH_Msk #define SCB_INTR_S_MASK_I2C_GENERAL_Pos SCB_V2_INTR_S_MASK_I2C_GENERAL_Pos #define SCB_INTR_S_MASK_I2C_GENERAL_Msk SCB_V2_INTR_S_MASK_I2C_GENERAL_Msk #define SCB_INTR_S_MASK_I2C_BUS_ERROR_Pos SCB_V2_INTR_S_MASK_I2C_BUS_ERROR_Pos #define SCB_INTR_S_MASK_I2C_BUS_ERROR_Msk SCB_V2_INTR_S_MASK_I2C_BUS_ERROR_Msk #define SCB_INTR_S_MASK_SPI_EZ_WRITE_STOP_Pos SCB_V2_INTR_S_MASK_SPI_EZ_WRITE_STOP_Pos #define SCB_INTR_S_MASK_SPI_EZ_WRITE_STOP_Msk SCB_V2_INTR_S_MASK_SPI_EZ_WRITE_STOP_Msk #define SCB_INTR_S_MASK_SPI_EZ_STOP_Pos SCB_V2_INTR_S_MASK_SPI_EZ_STOP_Pos #define SCB_INTR_S_MASK_SPI_EZ_STOP_Msk SCB_V2_INTR_S_MASK_SPI_EZ_STOP_Msk #define SCB_INTR_S_MASK_SPI_BUS_ERROR_Pos SCB_V2_INTR_S_MASK_SPI_BUS_ERROR_Pos #define SCB_INTR_S_MASK_SPI_BUS_ERROR_Msk SCB_V2_INTR_S_MASK_SPI_BUS_ERROR_Msk /* SCB.INTR_S_MASKED */ #define SCB_INTR_S_MASKED_I2C_ARB_LOST_Pos SCB_V2_INTR_S_MASKED_I2C_ARB_LOST_Pos #define SCB_INTR_S_MASKED_I2C_ARB_LOST_Msk SCB_V2_INTR_S_MASKED_I2C_ARB_LOST_Msk #define SCB_INTR_S_MASKED_I2C_NACK_Pos SCB_V2_INTR_S_MASKED_I2C_NACK_Pos #define SCB_INTR_S_MASKED_I2C_NACK_Msk SCB_V2_INTR_S_MASKED_I2C_NACK_Msk #define SCB_INTR_S_MASKED_I2C_ACK_Pos SCB_V2_INTR_S_MASKED_I2C_ACK_Pos #define SCB_INTR_S_MASKED_I2C_ACK_Msk SCB_V2_INTR_S_MASKED_I2C_ACK_Msk #define SCB_INTR_S_MASKED_I2C_WRITE_STOP_Pos SCB_V2_INTR_S_MASKED_I2C_WRITE_STOP_Pos #define SCB_INTR_S_MASKED_I2C_WRITE_STOP_Msk SCB_V2_INTR_S_MASKED_I2C_WRITE_STOP_Msk #define SCB_INTR_S_MASKED_I2C_STOP_Pos SCB_V2_INTR_S_MASKED_I2C_STOP_Pos #define SCB_INTR_S_MASKED_I2C_STOP_Msk SCB_V2_INTR_S_MASKED_I2C_STOP_Msk #define SCB_INTR_S_MASKED_I2C_START_Pos SCB_V2_INTR_S_MASKED_I2C_START_Pos #define SCB_INTR_S_MASKED_I2C_START_Msk SCB_V2_INTR_S_MASKED_I2C_START_Msk #define SCB_INTR_S_MASKED_I2C_ADDR_MATCH_Pos SCB_V2_INTR_S_MASKED_I2C_ADDR_MATCH_Pos #define SCB_INTR_S_MASKED_I2C_ADDR_MATCH_Msk SCB_V2_INTR_S_MASKED_I2C_ADDR_MATCH_Msk #define SCB_INTR_S_MASKED_I2C_GENERAL_Pos SCB_V2_INTR_S_MASKED_I2C_GENERAL_Pos #define SCB_INTR_S_MASKED_I2C_GENERAL_Msk SCB_V2_INTR_S_MASKED_I2C_GENERAL_Msk #define SCB_INTR_S_MASKED_I2C_BUS_ERROR_Pos SCB_V2_INTR_S_MASKED_I2C_BUS_ERROR_Pos #define SCB_INTR_S_MASKED_I2C_BUS_ERROR_Msk SCB_V2_INTR_S_MASKED_I2C_BUS_ERROR_Msk #define SCB_INTR_S_MASKED_SPI_EZ_WRITE_STOP_Pos SCB_V2_INTR_S_MASKED_SPI_EZ_WRITE_STOP_Pos #define SCB_INTR_S_MASKED_SPI_EZ_WRITE_STOP_Msk SCB_V2_INTR_S_MASKED_SPI_EZ_WRITE_STOP_Msk #define SCB_INTR_S_MASKED_SPI_EZ_STOP_Pos SCB_V2_INTR_S_MASKED_SPI_EZ_STOP_Pos #define SCB_INTR_S_MASKED_SPI_EZ_STOP_Msk SCB_V2_INTR_S_MASKED_SPI_EZ_STOP_Msk #define SCB_INTR_S_MASKED_SPI_BUS_ERROR_Pos SCB_V2_INTR_S_MASKED_SPI_BUS_ERROR_Pos #define SCB_INTR_S_MASKED_SPI_BUS_ERROR_Msk SCB_V2_INTR_S_MASKED_SPI_BUS_ERROR_Msk /* SCB.INTR_TX */ #define SCB_INTR_TX_TRIGGER_Pos SCB_V2_INTR_TX_TRIGGER_Pos #define SCB_INTR_TX_TRIGGER_Msk SCB_V2_INTR_TX_TRIGGER_Msk #define SCB_INTR_TX_NOT_FULL_Pos SCB_V2_INTR_TX_NOT_FULL_Pos #define SCB_INTR_TX_NOT_FULL_Msk SCB_V2_INTR_TX_NOT_FULL_Msk #define SCB_INTR_TX_EMPTY_Pos SCB_V2_INTR_TX_EMPTY_Pos #define SCB_INTR_TX_EMPTY_Msk SCB_V2_INTR_TX_EMPTY_Msk #define SCB_INTR_TX_OVERFLOW_Pos SCB_V2_INTR_TX_OVERFLOW_Pos #define SCB_INTR_TX_OVERFLOW_Msk SCB_V2_INTR_TX_OVERFLOW_Msk #define SCB_INTR_TX_UNDERFLOW_Pos SCB_V2_INTR_TX_UNDERFLOW_Pos #define SCB_INTR_TX_UNDERFLOW_Msk SCB_V2_INTR_TX_UNDERFLOW_Msk #define SCB_INTR_TX_BLOCKED_Pos SCB_V2_INTR_TX_BLOCKED_Pos #define SCB_INTR_TX_BLOCKED_Msk SCB_V2_INTR_TX_BLOCKED_Msk #define SCB_INTR_TX_UART_NACK_Pos SCB_V2_INTR_TX_UART_NACK_Pos #define SCB_INTR_TX_UART_NACK_Msk SCB_V2_INTR_TX_UART_NACK_Msk #define SCB_INTR_TX_UART_DONE_Pos SCB_V2_INTR_TX_UART_DONE_Pos #define SCB_INTR_TX_UART_DONE_Msk SCB_V2_INTR_TX_UART_DONE_Msk #define SCB_INTR_TX_UART_ARB_LOST_Pos SCB_V2_INTR_TX_UART_ARB_LOST_Pos #define SCB_INTR_TX_UART_ARB_LOST_Msk SCB_V2_INTR_TX_UART_ARB_LOST_Msk /* SCB.INTR_TX_SET */ #define SCB_INTR_TX_SET_TRIGGER_Pos SCB_V2_INTR_TX_SET_TRIGGER_Pos #define SCB_INTR_TX_SET_TRIGGER_Msk SCB_V2_INTR_TX_SET_TRIGGER_Msk #define SCB_INTR_TX_SET_NOT_FULL_Pos SCB_V2_INTR_TX_SET_NOT_FULL_Pos #define SCB_INTR_TX_SET_NOT_FULL_Msk SCB_V2_INTR_TX_SET_NOT_FULL_Msk #define SCB_INTR_TX_SET_EMPTY_Pos SCB_V2_INTR_TX_SET_EMPTY_Pos #define SCB_INTR_TX_SET_EMPTY_Msk SCB_V2_INTR_TX_SET_EMPTY_Msk #define SCB_INTR_TX_SET_OVERFLOW_Pos SCB_V2_INTR_TX_SET_OVERFLOW_Pos #define SCB_INTR_TX_SET_OVERFLOW_Msk SCB_V2_INTR_TX_SET_OVERFLOW_Msk #define SCB_INTR_TX_SET_UNDERFLOW_Pos SCB_V2_INTR_TX_SET_UNDERFLOW_Pos #define SCB_INTR_TX_SET_UNDERFLOW_Msk SCB_V2_INTR_TX_SET_UNDERFLOW_Msk #define SCB_INTR_TX_SET_BLOCKED_Pos SCB_V2_INTR_TX_SET_BLOCKED_Pos #define SCB_INTR_TX_SET_BLOCKED_Msk SCB_V2_INTR_TX_SET_BLOCKED_Msk #define SCB_INTR_TX_SET_UART_NACK_Pos SCB_V2_INTR_TX_SET_UART_NACK_Pos #define SCB_INTR_TX_SET_UART_NACK_Msk SCB_V2_INTR_TX_SET_UART_NACK_Msk #define SCB_INTR_TX_SET_UART_DONE_Pos SCB_V2_INTR_TX_SET_UART_DONE_Pos #define SCB_INTR_TX_SET_UART_DONE_Msk SCB_V2_INTR_TX_SET_UART_DONE_Msk #define SCB_INTR_TX_SET_UART_ARB_LOST_Pos SCB_V2_INTR_TX_SET_UART_ARB_LOST_Pos #define SCB_INTR_TX_SET_UART_ARB_LOST_Msk SCB_V2_INTR_TX_SET_UART_ARB_LOST_Msk /* SCB.INTR_TX_MASK */ #define SCB_INTR_TX_MASK_TRIGGER_Pos SCB_V2_INTR_TX_MASK_TRIGGER_Pos #define SCB_INTR_TX_MASK_TRIGGER_Msk SCB_V2_INTR_TX_MASK_TRIGGER_Msk #define SCB_INTR_TX_MASK_NOT_FULL_Pos SCB_V2_INTR_TX_MASK_NOT_FULL_Pos #define SCB_INTR_TX_MASK_NOT_FULL_Msk SCB_V2_INTR_TX_MASK_NOT_FULL_Msk #define SCB_INTR_TX_MASK_EMPTY_Pos SCB_V2_INTR_TX_MASK_EMPTY_Pos #define SCB_INTR_TX_MASK_EMPTY_Msk SCB_V2_INTR_TX_MASK_EMPTY_Msk #define SCB_INTR_TX_MASK_OVERFLOW_Pos SCB_V2_INTR_TX_MASK_OVERFLOW_Pos #define SCB_INTR_TX_MASK_OVERFLOW_Msk SCB_V2_INTR_TX_MASK_OVERFLOW_Msk #define SCB_INTR_TX_MASK_UNDERFLOW_Pos SCB_V2_INTR_TX_MASK_UNDERFLOW_Pos #define SCB_INTR_TX_MASK_UNDERFLOW_Msk SCB_V2_INTR_TX_MASK_UNDERFLOW_Msk #define SCB_INTR_TX_MASK_BLOCKED_Pos SCB_V2_INTR_TX_MASK_BLOCKED_Pos #define SCB_INTR_TX_MASK_BLOCKED_Msk SCB_V2_INTR_TX_MASK_BLOCKED_Msk #define SCB_INTR_TX_MASK_UART_NACK_Pos SCB_V2_INTR_TX_MASK_UART_NACK_Pos #define SCB_INTR_TX_MASK_UART_NACK_Msk SCB_V2_INTR_TX_MASK_UART_NACK_Msk #define SCB_INTR_TX_MASK_UART_DONE_Pos SCB_V2_INTR_TX_MASK_UART_DONE_Pos #define SCB_INTR_TX_MASK_UART_DONE_Msk SCB_V2_INTR_TX_MASK_UART_DONE_Msk #define SCB_INTR_TX_MASK_UART_ARB_LOST_Pos SCB_V2_INTR_TX_MASK_UART_ARB_LOST_Pos #define SCB_INTR_TX_MASK_UART_ARB_LOST_Msk SCB_V2_INTR_TX_MASK_UART_ARB_LOST_Msk /* SCB.INTR_TX_MASKED */ #define SCB_INTR_TX_MASKED_TRIGGER_Pos SCB_V2_INTR_TX_MASKED_TRIGGER_Pos #define SCB_INTR_TX_MASKED_TRIGGER_Msk SCB_V2_INTR_TX_MASKED_TRIGGER_Msk #define SCB_INTR_TX_MASKED_NOT_FULL_Pos SCB_V2_INTR_TX_MASKED_NOT_FULL_Pos #define SCB_INTR_TX_MASKED_NOT_FULL_Msk SCB_V2_INTR_TX_MASKED_NOT_FULL_Msk #define SCB_INTR_TX_MASKED_EMPTY_Pos SCB_V2_INTR_TX_MASKED_EMPTY_Pos #define SCB_INTR_TX_MASKED_EMPTY_Msk SCB_V2_INTR_TX_MASKED_EMPTY_Msk #define SCB_INTR_TX_MASKED_OVERFLOW_Pos SCB_V2_INTR_TX_MASKED_OVERFLOW_Pos #define SCB_INTR_TX_MASKED_OVERFLOW_Msk SCB_V2_INTR_TX_MASKED_OVERFLOW_Msk #define SCB_INTR_TX_MASKED_UNDERFLOW_Pos SCB_V2_INTR_TX_MASKED_UNDERFLOW_Pos #define SCB_INTR_TX_MASKED_UNDERFLOW_Msk SCB_V2_INTR_TX_MASKED_UNDERFLOW_Msk #define SCB_INTR_TX_MASKED_BLOCKED_Pos SCB_V2_INTR_TX_MASKED_BLOCKED_Pos #define SCB_INTR_TX_MASKED_BLOCKED_Msk SCB_V2_INTR_TX_MASKED_BLOCKED_Msk #define SCB_INTR_TX_MASKED_UART_NACK_Pos SCB_V2_INTR_TX_MASKED_UART_NACK_Pos #define SCB_INTR_TX_MASKED_UART_NACK_Msk SCB_V2_INTR_TX_MASKED_UART_NACK_Msk #define SCB_INTR_TX_MASKED_UART_DONE_Pos SCB_V2_INTR_TX_MASKED_UART_DONE_Pos #define SCB_INTR_TX_MASKED_UART_DONE_Msk SCB_V2_INTR_TX_MASKED_UART_DONE_Msk #define SCB_INTR_TX_MASKED_UART_ARB_LOST_Pos SCB_V2_INTR_TX_MASKED_UART_ARB_LOST_Pos #define SCB_INTR_TX_MASKED_UART_ARB_LOST_Msk SCB_V2_INTR_TX_MASKED_UART_ARB_LOST_Msk /* SCB.INTR_RX */ #define SCB_INTR_RX_TRIGGER_Pos SCB_V2_INTR_RX_TRIGGER_Pos #define SCB_INTR_RX_TRIGGER_Msk SCB_V2_INTR_RX_TRIGGER_Msk #define SCB_INTR_RX_NOT_EMPTY_Pos SCB_V2_INTR_RX_NOT_EMPTY_Pos #define SCB_INTR_RX_NOT_EMPTY_Msk SCB_V2_INTR_RX_NOT_EMPTY_Msk #define SCB_INTR_RX_FULL_Pos SCB_V2_INTR_RX_FULL_Pos #define SCB_INTR_RX_FULL_Msk SCB_V2_INTR_RX_FULL_Msk #define SCB_INTR_RX_OVERFLOW_Pos SCB_V2_INTR_RX_OVERFLOW_Pos #define SCB_INTR_RX_OVERFLOW_Msk SCB_V2_INTR_RX_OVERFLOW_Msk #define SCB_INTR_RX_UNDERFLOW_Pos SCB_V2_INTR_RX_UNDERFLOW_Pos #define SCB_INTR_RX_UNDERFLOW_Msk SCB_V2_INTR_RX_UNDERFLOW_Msk #define SCB_INTR_RX_BLOCKED_Pos SCB_V2_INTR_RX_BLOCKED_Pos #define SCB_INTR_RX_BLOCKED_Msk SCB_V2_INTR_RX_BLOCKED_Msk #define SCB_INTR_RX_FRAME_ERROR_Pos SCB_V2_INTR_RX_FRAME_ERROR_Pos #define SCB_INTR_RX_FRAME_ERROR_Msk SCB_V2_INTR_RX_FRAME_ERROR_Msk #define SCB_INTR_RX_PARITY_ERROR_Pos SCB_V2_INTR_RX_PARITY_ERROR_Pos #define SCB_INTR_RX_PARITY_ERROR_Msk SCB_V2_INTR_RX_PARITY_ERROR_Msk #define SCB_INTR_RX_BAUD_DETECT_Pos SCB_V2_INTR_RX_BAUD_DETECT_Pos #define SCB_INTR_RX_BAUD_DETECT_Msk SCB_V2_INTR_RX_BAUD_DETECT_Msk #define SCB_INTR_RX_BREAK_DETECT_Pos SCB_V2_INTR_RX_BREAK_DETECT_Pos #define SCB_INTR_RX_BREAK_DETECT_Msk SCB_V2_INTR_RX_BREAK_DETECT_Msk /* SCB.INTR_RX_SET */ #define SCB_INTR_RX_SET_TRIGGER_Pos SCB_V2_INTR_RX_SET_TRIGGER_Pos #define SCB_INTR_RX_SET_TRIGGER_Msk SCB_V2_INTR_RX_SET_TRIGGER_Msk #define SCB_INTR_RX_SET_NOT_EMPTY_Pos SCB_V2_INTR_RX_SET_NOT_EMPTY_Pos #define SCB_INTR_RX_SET_NOT_EMPTY_Msk SCB_V2_INTR_RX_SET_NOT_EMPTY_Msk #define SCB_INTR_RX_SET_FULL_Pos SCB_V2_INTR_RX_SET_FULL_Pos #define SCB_INTR_RX_SET_FULL_Msk SCB_V2_INTR_RX_SET_FULL_Msk #define SCB_INTR_RX_SET_OVERFLOW_Pos SCB_V2_INTR_RX_SET_OVERFLOW_Pos #define SCB_INTR_RX_SET_OVERFLOW_Msk SCB_V2_INTR_RX_SET_OVERFLOW_Msk #define SCB_INTR_RX_SET_UNDERFLOW_Pos SCB_V2_INTR_RX_SET_UNDERFLOW_Pos #define SCB_INTR_RX_SET_UNDERFLOW_Msk SCB_V2_INTR_RX_SET_UNDERFLOW_Msk #define SCB_INTR_RX_SET_BLOCKED_Pos SCB_V2_INTR_RX_SET_BLOCKED_Pos #define SCB_INTR_RX_SET_BLOCKED_Msk SCB_V2_INTR_RX_SET_BLOCKED_Msk #define SCB_INTR_RX_SET_FRAME_ERROR_Pos SCB_V2_INTR_RX_SET_FRAME_ERROR_Pos #define SCB_INTR_RX_SET_FRAME_ERROR_Msk SCB_V2_INTR_RX_SET_FRAME_ERROR_Msk #define SCB_INTR_RX_SET_PARITY_ERROR_Pos SCB_V2_INTR_RX_SET_PARITY_ERROR_Pos #define SCB_INTR_RX_SET_PARITY_ERROR_Msk SCB_V2_INTR_RX_SET_PARITY_ERROR_Msk #define SCB_INTR_RX_SET_BAUD_DETECT_Pos SCB_V2_INTR_RX_SET_BAUD_DETECT_Pos #define SCB_INTR_RX_SET_BAUD_DETECT_Msk SCB_V2_INTR_RX_SET_BAUD_DETECT_Msk #define SCB_INTR_RX_SET_BREAK_DETECT_Pos SCB_V2_INTR_RX_SET_BREAK_DETECT_Pos #define SCB_INTR_RX_SET_BREAK_DETECT_Msk SCB_V2_INTR_RX_SET_BREAK_DETECT_Msk /* SCB.INTR_RX_MASK */ #define SCB_INTR_RX_MASK_TRIGGER_Pos SCB_V2_INTR_RX_MASK_TRIGGER_Pos #define SCB_INTR_RX_MASK_TRIGGER_Msk SCB_V2_INTR_RX_MASK_TRIGGER_Msk #define SCB_INTR_RX_MASK_NOT_EMPTY_Pos SCB_V2_INTR_RX_MASK_NOT_EMPTY_Pos #define SCB_INTR_RX_MASK_NOT_EMPTY_Msk SCB_V2_INTR_RX_MASK_NOT_EMPTY_Msk #define SCB_INTR_RX_MASK_FULL_Pos SCB_V2_INTR_RX_MASK_FULL_Pos #define SCB_INTR_RX_MASK_FULL_Msk SCB_V2_INTR_RX_MASK_FULL_Msk #define SCB_INTR_RX_MASK_OVERFLOW_Pos SCB_V2_INTR_RX_MASK_OVERFLOW_Pos #define SCB_INTR_RX_MASK_OVERFLOW_Msk SCB_V2_INTR_RX_MASK_OVERFLOW_Msk #define SCB_INTR_RX_MASK_UNDERFLOW_Pos SCB_V2_INTR_RX_MASK_UNDERFLOW_Pos #define SCB_INTR_RX_MASK_UNDERFLOW_Msk SCB_V2_INTR_RX_MASK_UNDERFLOW_Msk #define SCB_INTR_RX_MASK_BLOCKED_Pos SCB_V2_INTR_RX_MASK_BLOCKED_Pos #define SCB_INTR_RX_MASK_BLOCKED_Msk SCB_V2_INTR_RX_MASK_BLOCKED_Msk #define SCB_INTR_RX_MASK_FRAME_ERROR_Pos SCB_V2_INTR_RX_MASK_FRAME_ERROR_Pos #define SCB_INTR_RX_MASK_FRAME_ERROR_Msk SCB_V2_INTR_RX_MASK_FRAME_ERROR_Msk #define SCB_INTR_RX_MASK_PARITY_ERROR_Pos SCB_V2_INTR_RX_MASK_PARITY_ERROR_Pos #define SCB_INTR_RX_MASK_PARITY_ERROR_Msk SCB_V2_INTR_RX_MASK_PARITY_ERROR_Msk #define SCB_INTR_RX_MASK_BAUD_DETECT_Pos SCB_V2_INTR_RX_MASK_BAUD_DETECT_Pos #define SCB_INTR_RX_MASK_BAUD_DETECT_Msk SCB_V2_INTR_RX_MASK_BAUD_DETECT_Msk #define SCB_INTR_RX_MASK_BREAK_DETECT_Pos SCB_V2_INTR_RX_MASK_BREAK_DETECT_Pos #define SCB_INTR_RX_MASK_BREAK_DETECT_Msk SCB_V2_INTR_RX_MASK_BREAK_DETECT_Msk /* SCB.INTR_RX_MASKED */ #define SCB_INTR_RX_MASKED_TRIGGER_Pos SCB_V2_INTR_RX_MASKED_TRIGGER_Pos #define SCB_INTR_RX_MASKED_TRIGGER_Msk SCB_V2_INTR_RX_MASKED_TRIGGER_Msk #define SCB_INTR_RX_MASKED_NOT_EMPTY_Pos SCB_V2_INTR_RX_MASKED_NOT_EMPTY_Pos #define SCB_INTR_RX_MASKED_NOT_EMPTY_Msk SCB_V2_INTR_RX_MASKED_NOT_EMPTY_Msk #define SCB_INTR_RX_MASKED_FULL_Pos SCB_V2_INTR_RX_MASKED_FULL_Pos #define SCB_INTR_RX_MASKED_FULL_Msk SCB_V2_INTR_RX_MASKED_FULL_Msk #define SCB_INTR_RX_MASKED_OVERFLOW_Pos SCB_V2_INTR_RX_MASKED_OVERFLOW_Pos #define SCB_INTR_RX_MASKED_OVERFLOW_Msk SCB_V2_INTR_RX_MASKED_OVERFLOW_Msk #define SCB_INTR_RX_MASKED_UNDERFLOW_Pos SCB_V2_INTR_RX_MASKED_UNDERFLOW_Pos #define SCB_INTR_RX_MASKED_UNDERFLOW_Msk SCB_V2_INTR_RX_MASKED_UNDERFLOW_Msk #define SCB_INTR_RX_MASKED_BLOCKED_Pos SCB_V2_INTR_RX_MASKED_BLOCKED_Pos #define SCB_INTR_RX_MASKED_BLOCKED_Msk SCB_V2_INTR_RX_MASKED_BLOCKED_Msk #define SCB_INTR_RX_MASKED_FRAME_ERROR_Pos SCB_V2_INTR_RX_MASKED_FRAME_ERROR_Pos #define SCB_INTR_RX_MASKED_FRAME_ERROR_Msk SCB_V2_INTR_RX_MASKED_FRAME_ERROR_Msk #define SCB_INTR_RX_MASKED_PARITY_ERROR_Pos SCB_V2_INTR_RX_MASKED_PARITY_ERROR_Pos #define SCB_INTR_RX_MASKED_PARITY_ERROR_Msk SCB_V2_INTR_RX_MASKED_PARITY_ERROR_Msk #define SCB_INTR_RX_MASKED_BAUD_DETECT_Pos SCB_V2_INTR_RX_MASKED_BAUD_DETECT_Pos #define SCB_INTR_RX_MASKED_BAUD_DETECT_Msk SCB_V2_INTR_RX_MASKED_BAUD_DETECT_Msk #define SCB_INTR_RX_MASKED_BREAK_DETECT_Pos SCB_V2_INTR_RX_MASKED_BREAK_DETECT_Pos #define SCB_INTR_RX_MASKED_BREAK_DETECT_Msk SCB_V2_INTR_RX_MASKED_BREAK_DETECT_Msk /******************************************************************************* * SMARTIO *******************************************************************************/ /* SMARTIO_PRT.CTL */ #define SMARTIO_PRT_CTL_BYPASS_Pos SMARTIO_PRT_V2_CTL_BYPASS_Pos #define SMARTIO_PRT_CTL_BYPASS_Msk SMARTIO_PRT_V2_CTL_BYPASS_Msk #define SMARTIO_PRT_CTL_CLOCK_SRC_Pos SMARTIO_PRT_V2_CTL_CLOCK_SRC_Pos #define SMARTIO_PRT_CTL_CLOCK_SRC_Msk SMARTIO_PRT_V2_CTL_CLOCK_SRC_Msk #define SMARTIO_PRT_CTL_HLD_OVR_Pos SMARTIO_PRT_V2_CTL_HLD_OVR_Pos #define SMARTIO_PRT_CTL_HLD_OVR_Msk SMARTIO_PRT_V2_CTL_HLD_OVR_Msk #define SMARTIO_PRT_CTL_PIPELINE_EN_Pos SMARTIO_PRT_V2_CTL_PIPELINE_EN_Pos #define SMARTIO_PRT_CTL_PIPELINE_EN_Msk SMARTIO_PRT_V2_CTL_PIPELINE_EN_Msk #define SMARTIO_PRT_CTL_ENABLED_Pos SMARTIO_PRT_V2_CTL_ENABLED_Pos #define SMARTIO_PRT_CTL_ENABLED_Msk SMARTIO_PRT_V2_CTL_ENABLED_Msk /* SMARTIO_PRT.SYNC_CTL */ #define SMARTIO_PRT_SYNC_CTL_IO_SYNC_EN_Pos SMARTIO_PRT_V2_SYNC_CTL_IO_SYNC_EN_Pos #define SMARTIO_PRT_SYNC_CTL_IO_SYNC_EN_Msk SMARTIO_PRT_V2_SYNC_CTL_IO_SYNC_EN_Msk #define SMARTIO_PRT_SYNC_CTL_CHIP_SYNC_EN_Pos SMARTIO_PRT_V2_SYNC_CTL_CHIP_SYNC_EN_Pos #define SMARTIO_PRT_SYNC_CTL_CHIP_SYNC_EN_Msk SMARTIO_PRT_V2_SYNC_CTL_CHIP_SYNC_EN_Msk /* SMARTIO_PRT.LUT_SEL */ #define SMARTIO_PRT_LUT_SEL_LUT_TR0_SEL_Pos SMARTIO_PRT_V2_LUT_SEL_LUT_TR0_SEL_Pos #define SMARTIO_PRT_LUT_SEL_LUT_TR0_SEL_Msk SMARTIO_PRT_V2_LUT_SEL_LUT_TR0_SEL_Msk #define SMARTIO_PRT_LUT_SEL_LUT_TR1_SEL_Pos SMARTIO_PRT_V2_LUT_SEL_LUT_TR1_SEL_Pos #define SMARTIO_PRT_LUT_SEL_LUT_TR1_SEL_Msk SMARTIO_PRT_V2_LUT_SEL_LUT_TR1_SEL_Msk #define SMARTIO_PRT_LUT_SEL_LUT_TR2_SEL_Pos SMARTIO_PRT_V2_LUT_SEL_LUT_TR2_SEL_Pos #define SMARTIO_PRT_LUT_SEL_LUT_TR2_SEL_Msk SMARTIO_PRT_V2_LUT_SEL_LUT_TR2_SEL_Msk /* SMARTIO_PRT.LUT_CTL */ #define SMARTIO_PRT_LUT_CTL_LUT_Pos SMARTIO_PRT_V2_LUT_CTL_LUT_Pos #define SMARTIO_PRT_LUT_CTL_LUT_Msk SMARTIO_PRT_V2_LUT_CTL_LUT_Msk #define SMARTIO_PRT_LUT_CTL_LUT_OPC_Pos SMARTIO_PRT_V2_LUT_CTL_LUT_OPC_Pos #define SMARTIO_PRT_LUT_CTL_LUT_OPC_Msk SMARTIO_PRT_V2_LUT_CTL_LUT_OPC_Msk /* SMARTIO_PRT.DU_SEL */ #define SMARTIO_PRT_DU_SEL_DU_TR0_SEL_Pos SMARTIO_PRT_V2_DU_SEL_DU_TR0_SEL_Pos #define SMARTIO_PRT_DU_SEL_DU_TR0_SEL_Msk SMARTIO_PRT_V2_DU_SEL_DU_TR0_SEL_Msk #define SMARTIO_PRT_DU_SEL_DU_TR1_SEL_Pos SMARTIO_PRT_V2_DU_SEL_DU_TR1_SEL_Pos #define SMARTIO_PRT_DU_SEL_DU_TR1_SEL_Msk SMARTIO_PRT_V2_DU_SEL_DU_TR1_SEL_Msk #define SMARTIO_PRT_DU_SEL_DU_TR2_SEL_Pos SMARTIO_PRT_V2_DU_SEL_DU_TR2_SEL_Pos #define SMARTIO_PRT_DU_SEL_DU_TR2_SEL_Msk SMARTIO_PRT_V2_DU_SEL_DU_TR2_SEL_Msk #define SMARTIO_PRT_DU_SEL_DU_DATA0_SEL_Pos SMARTIO_PRT_V2_DU_SEL_DU_DATA0_SEL_Pos #define SMARTIO_PRT_DU_SEL_DU_DATA0_SEL_Msk SMARTIO_PRT_V2_DU_SEL_DU_DATA0_SEL_Msk #define SMARTIO_PRT_DU_SEL_DU_DATA1_SEL_Pos SMARTIO_PRT_V2_DU_SEL_DU_DATA1_SEL_Pos #define SMARTIO_PRT_DU_SEL_DU_DATA1_SEL_Msk SMARTIO_PRT_V2_DU_SEL_DU_DATA1_SEL_Msk /* SMARTIO_PRT.DU_CTL */ #define SMARTIO_PRT_DU_CTL_DU_SIZE_Pos SMARTIO_PRT_V2_DU_CTL_DU_SIZE_Pos #define SMARTIO_PRT_DU_CTL_DU_SIZE_Msk SMARTIO_PRT_V2_DU_CTL_DU_SIZE_Msk #define SMARTIO_PRT_DU_CTL_DU_OPC_Pos SMARTIO_PRT_V2_DU_CTL_DU_OPC_Pos #define SMARTIO_PRT_DU_CTL_DU_OPC_Msk SMARTIO_PRT_V2_DU_CTL_DU_OPC_Msk /* SMARTIO_PRT.DATA */ #define SMARTIO_PRT_DATA_DATA_Pos SMARTIO_PRT_V2_DATA_DATA_Pos #define SMARTIO_PRT_DATA_DATA_Msk SMARTIO_PRT_V2_DATA_DATA_Msk /******************************************************************************* * TCPWM *******************************************************************************/ /* TCPWM_GRP_CNT.CTRL */ #define TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_CC0_Pos TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC0_Pos #define TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_CC0_Msk TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC0_Msk #define TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_CC1_Pos TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC1_Pos #define TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_CC1_Msk TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC1_Msk #define TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_PERIOD_Pos TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_PERIOD_Pos #define TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_PERIOD_Msk TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_PERIOD_Msk #define TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_LINE_SEL_Pos TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_LINE_SEL_Pos #define TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_LINE_SEL_Msk TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_LINE_SEL_Msk #define TCPWM_GRP_CNT_CTRL_CC0_MATCH_UP_EN_Pos TCPWM_GRP_CNT_V2_CTRL_CC0_MATCH_UP_EN_Pos #define TCPWM_GRP_CNT_CTRL_CC0_MATCH_UP_EN_Msk TCPWM_GRP_CNT_V2_CTRL_CC0_MATCH_UP_EN_Msk #define TCPWM_GRP_CNT_CTRL_CC0_MATCH_DOWN_EN_Pos TCPWM_GRP_CNT_V2_CTRL_CC0_MATCH_DOWN_EN_Pos #define TCPWM_GRP_CNT_CTRL_CC0_MATCH_DOWN_EN_Msk TCPWM_GRP_CNT_V2_CTRL_CC0_MATCH_DOWN_EN_Msk #define TCPWM_GRP_CNT_CTRL_CC1_MATCH_UP_EN_Pos TCPWM_GRP_CNT_V2_CTRL_CC1_MATCH_UP_EN_Pos #define TCPWM_GRP_CNT_CTRL_CC1_MATCH_UP_EN_Msk TCPWM_GRP_CNT_V2_CTRL_CC1_MATCH_UP_EN_Msk #define TCPWM_GRP_CNT_CTRL_CC1_MATCH_DOWN_EN_Pos TCPWM_GRP_CNT_V2_CTRL_CC1_MATCH_DOWN_EN_Pos #define TCPWM_GRP_CNT_CTRL_CC1_MATCH_DOWN_EN_Msk TCPWM_GRP_CNT_V2_CTRL_CC1_MATCH_DOWN_EN_Msk #define TCPWM_GRP_CNT_CTRL_PWM_IMM_KILL_Pos TCPWM_GRP_CNT_V2_CTRL_PWM_IMM_KILL_Pos #define TCPWM_GRP_CNT_CTRL_PWM_IMM_KILL_Msk TCPWM_GRP_CNT_V2_CTRL_PWM_IMM_KILL_Msk #define TCPWM_GRP_CNT_CTRL_PWM_STOP_ON_KILL_Pos TCPWM_GRP_CNT_V2_CTRL_PWM_STOP_ON_KILL_Pos #define TCPWM_GRP_CNT_CTRL_PWM_STOP_ON_KILL_Msk TCPWM_GRP_CNT_V2_CTRL_PWM_STOP_ON_KILL_Msk #define TCPWM_GRP_CNT_CTRL_PWM_SYNC_KILL_Pos TCPWM_GRP_CNT_V2_CTRL_PWM_SYNC_KILL_Pos #define TCPWM_GRP_CNT_CTRL_PWM_SYNC_KILL_Msk TCPWM_GRP_CNT_V2_CTRL_PWM_SYNC_KILL_Msk #define TCPWM_GRP_CNT_CTRL_PWM_DISABLE_MODE_Pos TCPWM_GRP_CNT_V2_CTRL_PWM_DISABLE_MODE_Pos #define TCPWM_GRP_CNT_CTRL_PWM_DISABLE_MODE_Msk TCPWM_GRP_CNT_V2_CTRL_PWM_DISABLE_MODE_Msk #define TCPWM_GRP_CNT_CTRL_UP_DOWN_MODE_Pos TCPWM_GRP_CNT_V2_CTRL_UP_DOWN_MODE_Pos #define TCPWM_GRP_CNT_CTRL_UP_DOWN_MODE_Msk TCPWM_GRP_CNT_V2_CTRL_UP_DOWN_MODE_Msk #define TCPWM_GRP_CNT_CTRL_ONE_SHOT_Pos TCPWM_GRP_CNT_V2_CTRL_ONE_SHOT_Pos #define TCPWM_GRP_CNT_CTRL_ONE_SHOT_Msk TCPWM_GRP_CNT_V2_CTRL_ONE_SHOT_Msk #define TCPWM_GRP_CNT_CTRL_QUAD_ENCODING_MODE_Pos TCPWM_GRP_CNT_V2_CTRL_QUAD_ENCODING_MODE_Pos #define TCPWM_GRP_CNT_CTRL_QUAD_ENCODING_MODE_Msk TCPWM_GRP_CNT_V2_CTRL_QUAD_ENCODING_MODE_Msk #define TCPWM_GRP_CNT_CTRL_MODE_Pos TCPWM_GRP_CNT_V2_CTRL_MODE_Pos #define TCPWM_GRP_CNT_CTRL_MODE_Msk TCPWM_GRP_CNT_V2_CTRL_MODE_Msk #define TCPWM_GRP_CNT_CTRL_DBG_FREEZE_EN_Pos TCPWM_GRP_CNT_V2_CTRL_DBG_FREEZE_EN_Pos #define TCPWM_GRP_CNT_CTRL_DBG_FREEZE_EN_Msk TCPWM_GRP_CNT_V2_CTRL_DBG_FREEZE_EN_Msk #define TCPWM_GRP_CNT_CTRL_ENABLED_Pos TCPWM_GRP_CNT_V2_CTRL_ENABLED_Pos #define TCPWM_GRP_CNT_CTRL_ENABLED_Msk TCPWM_GRP_CNT_V2_CTRL_ENABLED_Msk /* TCPWM_GRP_CNT.STATUS */ #define TCPWM_GRP_CNT_STATUS_DOWN_Pos TCPWM_GRP_CNT_V2_STATUS_DOWN_Pos #define TCPWM_GRP_CNT_STATUS_DOWN_Msk TCPWM_GRP_CNT_V2_STATUS_DOWN_Msk #define TCPWM_GRP_CNT_STATUS_TR_CAPTURE0_Pos TCPWM_GRP_CNT_V2_STATUS_TR_CAPTURE0_Pos #define TCPWM_GRP_CNT_STATUS_TR_CAPTURE0_Msk TCPWM_GRP_CNT_V2_STATUS_TR_CAPTURE0_Msk #define TCPWM_GRP_CNT_STATUS_TR_COUNT_Pos TCPWM_GRP_CNT_V2_STATUS_TR_COUNT_Pos #define TCPWM_GRP_CNT_STATUS_TR_COUNT_Msk TCPWM_GRP_CNT_V2_STATUS_TR_COUNT_Msk #define TCPWM_GRP_CNT_STATUS_TR_RELOAD_Pos TCPWM_GRP_CNT_V2_STATUS_TR_RELOAD_Pos #define TCPWM_GRP_CNT_STATUS_TR_RELOAD_Msk TCPWM_GRP_CNT_V2_STATUS_TR_RELOAD_Msk #define TCPWM_GRP_CNT_STATUS_TR_STOP_Pos TCPWM_GRP_CNT_V2_STATUS_TR_STOP_Pos #define TCPWM_GRP_CNT_STATUS_TR_STOP_Msk TCPWM_GRP_CNT_V2_STATUS_TR_STOP_Msk #define TCPWM_GRP_CNT_STATUS_TR_START_Pos TCPWM_GRP_CNT_V2_STATUS_TR_START_Pos #define TCPWM_GRP_CNT_STATUS_TR_START_Msk TCPWM_GRP_CNT_V2_STATUS_TR_START_Msk #define TCPWM_GRP_CNT_STATUS_TR_CAPTURE1_Pos TCPWM_GRP_CNT_V2_STATUS_TR_CAPTURE1_Pos #define TCPWM_GRP_CNT_STATUS_TR_CAPTURE1_Msk TCPWM_GRP_CNT_V2_STATUS_TR_CAPTURE1_Msk #define TCPWM_GRP_CNT_STATUS_LINE_OUT_Pos TCPWM_GRP_CNT_V2_STATUS_LINE_OUT_Pos #define TCPWM_GRP_CNT_STATUS_LINE_OUT_Msk TCPWM_GRP_CNT_V2_STATUS_LINE_OUT_Msk #define TCPWM_GRP_CNT_STATUS_LINE_COMPL_OUT_Pos TCPWM_GRP_CNT_V2_STATUS_LINE_COMPL_OUT_Pos #define TCPWM_GRP_CNT_STATUS_LINE_COMPL_OUT_Msk TCPWM_GRP_CNT_V2_STATUS_LINE_COMPL_OUT_Msk #define TCPWM_GRP_CNT_STATUS_RUNNING_Pos TCPWM_GRP_CNT_V2_STATUS_RUNNING_Pos #define TCPWM_GRP_CNT_STATUS_RUNNING_Msk TCPWM_GRP_CNT_V2_STATUS_RUNNING_Msk #define TCPWM_GRP_CNT_STATUS_DT_CNT_L_Pos TCPWM_GRP_CNT_V2_STATUS_DT_CNT_L_Pos #define TCPWM_GRP_CNT_STATUS_DT_CNT_L_Msk TCPWM_GRP_CNT_V2_STATUS_DT_CNT_L_Msk #define TCPWM_GRP_CNT_STATUS_DT_CNT_H_Pos TCPWM_GRP_CNT_V2_STATUS_DT_CNT_H_Pos #define TCPWM_GRP_CNT_STATUS_DT_CNT_H_Msk TCPWM_GRP_CNT_V2_STATUS_DT_CNT_H_Msk /* TCPWM_GRP_CNT.COUNTER */ #define TCPWM_GRP_CNT_COUNTER_COUNTER_Pos TCPWM_GRP_CNT_V2_COUNTER_COUNTER_Pos #define TCPWM_GRP_CNT_COUNTER_COUNTER_Msk TCPWM_GRP_CNT_V2_COUNTER_COUNTER_Msk /* TCPWM_GRP_CNT.CC0 */ #define TCPWM_GRP_CNT_CC0_CC_Pos TCPWM_GRP_CNT_V2_CC0_CC_Pos #define TCPWM_GRP_CNT_CC0_CC_Msk TCPWM_GRP_CNT_V2_CC0_CC_Msk /* TCPWM_GRP_CNT.CC0_BUFF */ #define TCPWM_GRP_CNT_CC0_BUFF_CC_Pos TCPWM_GRP_CNT_V2_CC0_BUFF_CC_Pos #define TCPWM_GRP_CNT_CC0_BUFF_CC_Msk TCPWM_GRP_CNT_V2_CC0_BUFF_CC_Msk /* TCPWM_GRP_CNT.CC1 */ #define TCPWM_GRP_CNT_CC1_CC_Pos TCPWM_GRP_CNT_V2_CC1_CC_Pos #define TCPWM_GRP_CNT_CC1_CC_Msk TCPWM_GRP_CNT_V2_CC1_CC_Msk /* TCPWM_GRP_CNT.CC1_BUFF */ #define TCPWM_GRP_CNT_CC1_BUFF_CC_Pos TCPWM_GRP_CNT_V2_CC1_BUFF_CC_Pos #define TCPWM_GRP_CNT_CC1_BUFF_CC_Msk TCPWM_GRP_CNT_V2_CC1_BUFF_CC_Msk /* TCPWM_GRP_CNT.PERIOD */ #define TCPWM_GRP_CNT_PERIOD_PERIOD_Pos TCPWM_GRP_CNT_V2_PERIOD_PERIOD_Pos #define TCPWM_GRP_CNT_PERIOD_PERIOD_Msk TCPWM_GRP_CNT_V2_PERIOD_PERIOD_Msk /* TCPWM_GRP_CNT.PERIOD_BUFF */ #define TCPWM_GRP_CNT_PERIOD_BUFF_PERIOD_Pos TCPWM_GRP_CNT_V2_PERIOD_BUFF_PERIOD_Pos #define TCPWM_GRP_CNT_PERIOD_BUFF_PERIOD_Msk TCPWM_GRP_CNT_V2_PERIOD_BUFF_PERIOD_Msk /* TCPWM_GRP_CNT.LINE_SEL */ #define TCPWM_GRP_CNT_LINE_SEL_OUT_SEL_Pos TCPWM_GRP_CNT_V2_LINE_SEL_OUT_SEL_Pos #define TCPWM_GRP_CNT_LINE_SEL_OUT_SEL_Msk TCPWM_GRP_CNT_V2_LINE_SEL_OUT_SEL_Msk #define TCPWM_GRP_CNT_LINE_SEL_COMPL_OUT_SEL_Pos TCPWM_GRP_CNT_V2_LINE_SEL_COMPL_OUT_SEL_Pos #define TCPWM_GRP_CNT_LINE_SEL_COMPL_OUT_SEL_Msk TCPWM_GRP_CNT_V2_LINE_SEL_COMPL_OUT_SEL_Msk /* TCPWM_GRP_CNT.LINE_SEL_BUFF */ #define TCPWM_GRP_CNT_LINE_SEL_BUFF_OUT_SEL_Pos TCPWM_GRP_CNT_V2_LINE_SEL_BUFF_OUT_SEL_Pos #define TCPWM_GRP_CNT_LINE_SEL_BUFF_OUT_SEL_Msk TCPWM_GRP_CNT_V2_LINE_SEL_BUFF_OUT_SEL_Msk #define TCPWM_GRP_CNT_LINE_SEL_BUFF_COMPL_OUT_SEL_Pos TCPWM_GRP_CNT_V2_LINE_SEL_BUFF_COMPL_OUT_SEL_Pos #define TCPWM_GRP_CNT_LINE_SEL_BUFF_COMPL_OUT_SEL_Msk TCPWM_GRP_CNT_V2_LINE_SEL_BUFF_COMPL_OUT_SEL_Msk /* TCPWM_GRP_CNT.DT */ #define TCPWM_GRP_CNT_DT_DT_LINE_OUT_L_Pos TCPWM_GRP_CNT_V2_DT_DT_LINE_OUT_L_Pos #define TCPWM_GRP_CNT_DT_DT_LINE_OUT_L_Msk TCPWM_GRP_CNT_V2_DT_DT_LINE_OUT_L_Msk #define TCPWM_GRP_CNT_DT_DT_LINE_OUT_H_Pos TCPWM_GRP_CNT_V2_DT_DT_LINE_OUT_H_Pos #define TCPWM_GRP_CNT_DT_DT_LINE_OUT_H_Msk TCPWM_GRP_CNT_V2_DT_DT_LINE_OUT_H_Msk #define TCPWM_GRP_CNT_DT_DT_LINE_COMPL_OUT_Pos TCPWM_GRP_CNT_V2_DT_DT_LINE_COMPL_OUT_Pos #define TCPWM_GRP_CNT_DT_DT_LINE_COMPL_OUT_Msk TCPWM_GRP_CNT_V2_DT_DT_LINE_COMPL_OUT_Msk /* TCPWM_GRP_CNT.TR_CMD */ #define TCPWM_GRP_CNT_TR_CMD_CAPTURE0_Pos TCPWM_GRP_CNT_V2_TR_CMD_CAPTURE0_Pos #define TCPWM_GRP_CNT_TR_CMD_CAPTURE0_Msk TCPWM_GRP_CNT_V2_TR_CMD_CAPTURE0_Msk #define TCPWM_GRP_CNT_TR_CMD_RELOAD_Pos TCPWM_GRP_CNT_V2_TR_CMD_RELOAD_Pos #define TCPWM_GRP_CNT_TR_CMD_RELOAD_Msk TCPWM_GRP_CNT_V2_TR_CMD_RELOAD_Msk #define TCPWM_GRP_CNT_TR_CMD_STOP_Pos TCPWM_GRP_CNT_V2_TR_CMD_STOP_Pos #define TCPWM_GRP_CNT_TR_CMD_STOP_Msk TCPWM_GRP_CNT_V2_TR_CMD_STOP_Msk #define TCPWM_GRP_CNT_TR_CMD_START_Pos TCPWM_GRP_CNT_V2_TR_CMD_START_Pos #define TCPWM_GRP_CNT_TR_CMD_START_Msk TCPWM_GRP_CNT_V2_TR_CMD_START_Msk #define TCPWM_GRP_CNT_TR_CMD_CAPTURE1_Pos TCPWM_GRP_CNT_V2_TR_CMD_CAPTURE1_Pos #define TCPWM_GRP_CNT_TR_CMD_CAPTURE1_Msk TCPWM_GRP_CNT_V2_TR_CMD_CAPTURE1_Msk /* TCPWM_GRP_CNT.TR_IN_SEL0 */ #define TCPWM_GRP_CNT_TR_IN_SEL0_CAPTURE0_SEL_Pos TCPWM_GRP_CNT_V2_TR_IN_SEL0_CAPTURE0_SEL_Pos #define TCPWM_GRP_CNT_TR_IN_SEL0_CAPTURE0_SEL_Msk TCPWM_GRP_CNT_V2_TR_IN_SEL0_CAPTURE0_SEL_Msk #define TCPWM_GRP_CNT_TR_IN_SEL0_COUNT_SEL_Pos TCPWM_GRP_CNT_V2_TR_IN_SEL0_COUNT_SEL_Pos #define TCPWM_GRP_CNT_TR_IN_SEL0_COUNT_SEL_Msk TCPWM_GRP_CNT_V2_TR_IN_SEL0_COUNT_SEL_Msk #define TCPWM_GRP_CNT_TR_IN_SEL0_RELOAD_SEL_Pos TCPWM_GRP_CNT_V2_TR_IN_SEL0_RELOAD_SEL_Pos #define TCPWM_GRP_CNT_TR_IN_SEL0_RELOAD_SEL_Msk TCPWM_GRP_CNT_V2_TR_IN_SEL0_RELOAD_SEL_Msk #define TCPWM_GRP_CNT_TR_IN_SEL0_STOP_SEL_Pos TCPWM_GRP_CNT_V2_TR_IN_SEL0_STOP_SEL_Pos #define TCPWM_GRP_CNT_TR_IN_SEL0_STOP_SEL_Msk TCPWM_GRP_CNT_V2_TR_IN_SEL0_STOP_SEL_Msk /* TCPWM_GRP_CNT.TR_IN_SEL1 */ #define TCPWM_GRP_CNT_TR_IN_SEL1_START_SEL_Pos TCPWM_GRP_CNT_V2_TR_IN_SEL1_START_SEL_Pos #define TCPWM_GRP_CNT_TR_IN_SEL1_START_SEL_Msk TCPWM_GRP_CNT_V2_TR_IN_SEL1_START_SEL_Msk #define TCPWM_GRP_CNT_TR_IN_SEL1_CAPTURE1_SEL_Pos TCPWM_GRP_CNT_V2_TR_IN_SEL1_CAPTURE1_SEL_Pos #define TCPWM_GRP_CNT_TR_IN_SEL1_CAPTURE1_SEL_Msk TCPWM_GRP_CNT_V2_TR_IN_SEL1_CAPTURE1_SEL_Msk /* TCPWM_GRP_CNT.TR_IN_EDGE_SEL */ #define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_CAPTURE0_EDGE_Pos TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_CAPTURE0_EDGE_Pos #define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_CAPTURE0_EDGE_Msk TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_CAPTURE0_EDGE_Msk #define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_COUNT_EDGE_Pos TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_COUNT_EDGE_Pos #define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_COUNT_EDGE_Msk TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_COUNT_EDGE_Msk #define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_RELOAD_EDGE_Pos TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_RELOAD_EDGE_Pos #define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_RELOAD_EDGE_Msk TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_RELOAD_EDGE_Msk #define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_STOP_EDGE_Pos TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_STOP_EDGE_Pos #define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_STOP_EDGE_Msk TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_STOP_EDGE_Msk #define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_START_EDGE_Pos TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_START_EDGE_Pos #define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_START_EDGE_Msk TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_START_EDGE_Msk #define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_CAPTURE1_EDGE_Pos TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_CAPTURE1_EDGE_Pos #define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_CAPTURE1_EDGE_Msk TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_CAPTURE1_EDGE_Msk /* TCPWM_GRP_CNT.TR_PWM_CTRL */ #define TCPWM_GRP_CNT_TR_PWM_CTRL_CC0_MATCH_MODE_Pos TCPWM_GRP_CNT_V2_TR_PWM_CTRL_CC0_MATCH_MODE_Pos #define TCPWM_GRP_CNT_TR_PWM_CTRL_CC0_MATCH_MODE_Msk TCPWM_GRP_CNT_V2_TR_PWM_CTRL_CC0_MATCH_MODE_Msk #define TCPWM_GRP_CNT_TR_PWM_CTRL_OVERFLOW_MODE_Pos TCPWM_GRP_CNT_V2_TR_PWM_CTRL_OVERFLOW_MODE_Pos #define TCPWM_GRP_CNT_TR_PWM_CTRL_OVERFLOW_MODE_Msk TCPWM_GRP_CNT_V2_TR_PWM_CTRL_OVERFLOW_MODE_Msk #define TCPWM_GRP_CNT_TR_PWM_CTRL_UNDERFLOW_MODE_Pos TCPWM_GRP_CNT_V2_TR_PWM_CTRL_UNDERFLOW_MODE_Pos #define TCPWM_GRP_CNT_TR_PWM_CTRL_UNDERFLOW_MODE_Msk TCPWM_GRP_CNT_V2_TR_PWM_CTRL_UNDERFLOW_MODE_Msk #define TCPWM_GRP_CNT_TR_PWM_CTRL_CC1_MATCH_MODE_Pos TCPWM_GRP_CNT_V2_TR_PWM_CTRL_CC1_MATCH_MODE_Pos #define TCPWM_GRP_CNT_TR_PWM_CTRL_CC1_MATCH_MODE_Msk TCPWM_GRP_CNT_V2_TR_PWM_CTRL_CC1_MATCH_MODE_Msk /* TCPWM_GRP_CNT.TR_OUT_SEL */ #define TCPWM_GRP_CNT_TR_OUT_SEL_OUT0_Pos TCPWM_GRP_CNT_V2_TR_OUT_SEL_OUT0_Pos #define TCPWM_GRP_CNT_TR_OUT_SEL_OUT0_Msk TCPWM_GRP_CNT_V2_TR_OUT_SEL_OUT0_Msk #define TCPWM_GRP_CNT_TR_OUT_SEL_OUT1_Pos TCPWM_GRP_CNT_V2_TR_OUT_SEL_OUT1_Pos #define TCPWM_GRP_CNT_TR_OUT_SEL_OUT1_Msk TCPWM_GRP_CNT_V2_TR_OUT_SEL_OUT1_Msk /* TCPWM_GRP_CNT.INTR */ #define TCPWM_GRP_CNT_INTR_TC_Pos TCPWM_GRP_CNT_V2_INTR_TC_Pos #define TCPWM_GRP_CNT_INTR_TC_Msk TCPWM_GRP_CNT_V2_INTR_TC_Msk #define TCPWM_GRP_CNT_INTR_CC0_MATCH_Pos TCPWM_GRP_CNT_V2_INTR_CC0_MATCH_Pos #define TCPWM_GRP_CNT_INTR_CC0_MATCH_Msk TCPWM_GRP_CNT_V2_INTR_CC0_MATCH_Msk #define TCPWM_GRP_CNT_INTR_CC1_MATCH_Pos TCPWM_GRP_CNT_V2_INTR_CC1_MATCH_Pos #define TCPWM_GRP_CNT_INTR_CC1_MATCH_Msk TCPWM_GRP_CNT_V2_INTR_CC1_MATCH_Msk /* TCPWM_GRP_CNT.INTR_SET */ #define TCPWM_GRP_CNT_INTR_SET_TC_Pos TCPWM_GRP_CNT_V2_INTR_SET_TC_Pos #define TCPWM_GRP_CNT_INTR_SET_TC_Msk TCPWM_GRP_CNT_V2_INTR_SET_TC_Msk #define TCPWM_GRP_CNT_INTR_SET_CC0_MATCH_Pos TCPWM_GRP_CNT_V2_INTR_SET_CC0_MATCH_Pos #define TCPWM_GRP_CNT_INTR_SET_CC0_MATCH_Msk TCPWM_GRP_CNT_V2_INTR_SET_CC0_MATCH_Msk #define TCPWM_GRP_CNT_INTR_SET_CC1_MATCH_Pos TCPWM_GRP_CNT_V2_INTR_SET_CC1_MATCH_Pos #define TCPWM_GRP_CNT_INTR_SET_CC1_MATCH_Msk TCPWM_GRP_CNT_V2_INTR_SET_CC1_MATCH_Msk /* TCPWM_GRP_CNT.INTR_MASK */ #define TCPWM_GRP_CNT_INTR_MASK_TC_Pos TCPWM_GRP_CNT_V2_INTR_MASK_TC_Pos #define TCPWM_GRP_CNT_INTR_MASK_TC_Msk TCPWM_GRP_CNT_V2_INTR_MASK_TC_Msk #define TCPWM_GRP_CNT_INTR_MASK_CC0_MATCH_Pos TCPWM_GRP_CNT_V2_INTR_MASK_CC0_MATCH_Pos #define TCPWM_GRP_CNT_INTR_MASK_CC0_MATCH_Msk TCPWM_GRP_CNT_V2_INTR_MASK_CC0_MATCH_Msk #define TCPWM_GRP_CNT_INTR_MASK_CC1_MATCH_Pos TCPWM_GRP_CNT_V2_INTR_MASK_CC1_MATCH_Pos #define TCPWM_GRP_CNT_INTR_MASK_CC1_MATCH_Msk TCPWM_GRP_CNT_V2_INTR_MASK_CC1_MATCH_Msk /* TCPWM_GRP_CNT.INTR_MASKED */ #define TCPWM_GRP_CNT_INTR_MASKED_TC_Pos TCPWM_GRP_CNT_V2_INTR_MASKED_TC_Pos #define TCPWM_GRP_CNT_INTR_MASKED_TC_Msk TCPWM_GRP_CNT_V2_INTR_MASKED_TC_Msk #define TCPWM_GRP_CNT_INTR_MASKED_CC0_MATCH_Pos TCPWM_GRP_CNT_V2_INTR_MASKED_CC0_MATCH_Pos #define TCPWM_GRP_CNT_INTR_MASKED_CC0_MATCH_Msk TCPWM_GRP_CNT_V2_INTR_MASKED_CC0_MATCH_Msk #define TCPWM_GRP_CNT_INTR_MASKED_CC1_MATCH_Pos TCPWM_GRP_CNT_V2_INTR_MASKED_CC1_MATCH_Pos #define TCPWM_GRP_CNT_INTR_MASKED_CC1_MATCH_Msk TCPWM_GRP_CNT_V2_INTR_MASKED_CC1_MATCH_Msk #endif /* _TVIIBE_REMAPS_H_ */ /* [] END OF FILE */