1 /*
2 ** ###################################################################
3 ** Processor: MCXC142VFM
4 ** Compilers: Freescale C/C++ for Embedded ARM
5 ** GNU C Compiler
6 ** IAR ANSI C/C++ Compiler for ARM
7 ** Keil ARM C/C++ Compiler
8 ** MCUXpresso Compiler
9 **
10 ** Reference manual: MCXC242RM, Rev.1, Mar 2024
11 ** Version: rev. 1.6, 2016-06-24
12 ** Build: b240516
13 **
14 ** Abstract:
15 ** Provides a system configuration function and a global variable that
16 ** contains the system frequency. It configures the device and initializes
17 ** the oscillator (PLL) that is part of the microcontroller device.
18 **
19 ** Copyright 2016 Freescale Semiconductor, Inc.
20 ** Copyright 2016-2024 NXP
21 ** SPDX-License-Identifier: BSD-3-Clause
22 **
23 ** http: www.nxp.com
24 ** mail: support@nxp.com
25 **
26 ** Revisions:
27 ** - rev. 1.0 (2014-05-12)
28 ** Initial version.
29 ** - rev. 1.1 (2014-07-10)
30 ** UART0 - UART0 module renamed to UART2.
31 ** - rev. 1.2 (2014-08-12)
32 ** CRC - CRC register renamed to DATA.
33 ** - rev. 1.3 (2014-09-02)
34 ** USB - USB0_CTL0 was renamed to USB0_OTGCTL register.
35 ** USB - USB0_CTL1 was renamed to USB0_CTL register.
36 ** USB - Two new bitfields (STOP_ACK_DLY_EN, AHB_DLY_EN) was added to the USB0_KEEP_ALIVE_CTRL register.
37 ** - rev. 1.4 (2014-09-22)
38 ** FLEXIO - Offsets of the SHIFTBUFBIS registers were interchanged with offsets of the SHIFTBUFBBS registers.
39 ** SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register.
40 ** SIM - Removed bitfield DIEID in SDID register.
41 ** UART2 - Removed ED register.
42 ** UART2 - Removed MODEM register.
43 ** UART2 - Removed IR register.
44 ** UART2 - Removed PFIFO register.
45 ** UART2 - Removed CFIFO register.
46 ** UART2 - Removed SFIFO register.
47 ** UART2 - Removed TWFIFO register.
48 ** UART2 - Removed TCFIFO register.
49 ** UART2 - Removed RWFIFO register.
50 ** UART2 - Removed RCFIFO register.
51 ** USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register.
52 ** USB - Renamed USBEN bitfield of USB0_CTL was renamed to USBENSOFEN.
53 ** - rev. 1.5 (2016-02-02)
54 ** FGPIO - Add FGPIO registers.
55 ** - rev. 1.6 (2016-06-24)
56 ** USB - OTGCTL register was removed.
57 ** USB - Bit RESUME was added in CTL register.
58 **
59 ** ###################################################################
60 */
61
62 /*!
63 * @file MCXC142
64 * @version 1.6
65 * @date 2016-06-24
66 * @brief Device specific configuration file for MCXC142 (implementation file)
67 *
68 * Provides a system configuration function and a global variable that contains
69 * the system frequency. It configures the device and initializes the oscillator
70 * (PLL) that is part of the microcontroller device.
71 */
72
73 #include <stdint.h>
74 #include "fsl_device_registers.h"
75
76
77
78 /* ----------------------------------------------------------------------------
79 -- Core clock
80 ---------------------------------------------------------------------------- */
81
82 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
83
84 /* ----------------------------------------------------------------------------
85 -- SystemInit()
86 ---------------------------------------------------------------------------- */
87
SystemInit(void)88 void SystemInit (void) {
89
90 #if (ACK_ISOLATION)
91 if((PMC->REGSC & PMC_REGSC_ACKISO_MASK) != 0U) {
92 PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* VLLSx recovery */
93 }
94 #endif
95
96 #if (DISABLE_WDOG)
97 /* SIM->COPC: ?=0,COPCLKSEL=0,COPDBGEN=0,COPSTPEN=0,COPT=0,COPCLKS=0,COPW=0 */
98 SIM->COPC = (uint32_t)0x00U;
99 #endif /* (DISABLE_WDOG) */
100
101 SystemInitHook();
102 }
103
104 /* ----------------------------------------------------------------------------
105 -- SystemCoreClockUpdate()
106 ---------------------------------------------------------------------------- */
107
SystemCoreClockUpdate(void)108 void SystemCoreClockUpdate (void) {
109
110 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
111 uint16_t Divider;
112
113 if ((MCG->S & MCG_S_CLKST_MASK) == 0x00U) {
114 /* High internal reference clock is selected */
115 MCGOUTClock = CPU_INT_FAST_CLK_HZ; /* Fast internal reference clock selected */
116 } else if ((MCG->S & MCG_S_CLKST_MASK) == 0x04U) {
117 /* Internal reference clock is selected */
118 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
119 MCGOUTClock = (uint32_t) (CPU_INT_SLOW_CLK_HZ / Divider); /* Slow internal reference clock 8MHz selected */
120 } else if ((MCG->S & MCG_S_CLKST_MASK) == 0x08U) {
121 /* External reference clock is selected */
122 MCGOUTClock = CPU_XTAL_CLK_HZ;
123 } else {
124 /* Reserved value */
125 return;
126 } /* (!((MCG->S & MCG_S_CLKST_MASK) == 0x08U)) */
127 SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
128 }
129
130 /* ----------------------------------------------------------------------------
131 -- SystemInitHook()
132 ---------------------------------------------------------------------------- */
133
SystemInitHook(void)134 __attribute__ ((weak)) void SystemInitHook (void) {
135 /* Void implementation of the weak function. */
136 }
137
