1 /**
2   ******************************************************************************
3   * @file    stm32n657xx.h
4   * @author  MCD Application Team
5   * @brief   CMSIS STM32N657xx Device Peripheral Access Layer Header File.
6   *
7   *          This file contains:
8   *           - Data structures and the address mapping for all peripherals
9   *           - Peripheral's registers declarations and bits definition
10   *           - Macros to access peripheral's registers hardware
11   *
12   ******************************************************************************
13   * @attention
14   *
15   * Copyright (c) 2023 STMicroelectronics.
16   * All rights reserved.
17   *
18   * This software is licensed under terms that can be found in the LICENSE file
19   * in the root directory of this software component.
20   * If no LICENSE file comes with this software, it is provided AS-IS.
21   *
22   ******************************************************************************
23   */
24 
25 #ifndef STM32N657xx_H
26 #define STM32N657xx_H
27 
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31 
32 /** @addtogroup ST
33   * @{
34   */
35 
36 /** @addtogroup STM32N657xx
37   * @{
38   */
39 
40 /** @addtogroup Configuration_of_CMSIS
41   * @{
42   */
43 
44 /* =========================================================================================================================== */
45 /* ================                                Interrupt Number Definition                                ================ */
46 /* =========================================================================================================================== */
47 typedef enum
48 {
49 /* ======================================  ARM Cortex-M55 Specific Interrupt Numbers  ======================================== */
50   NonMaskableInt_IRQn        = -14,    /*!< -14 Non maskable Interrupt, cannot be stopped or preempted                         */
51   HardFault_IRQn             = -13,    /*!< -13 Hard Fault, all classes of Fault                                               */
52   MemoryManagement_IRQn      = -12,    /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match       */
53   BusFault_IRQn              = -11,    /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
54   UsageFault_IRQn            = -10,    /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition                  */
55 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
56   SecureFault_IRQn           = -9,     /*!< -9  Secure Fault                                                                   */
57 #endif
58   SVCall_IRQn                = -5,     /*!< -5  System Service Call via SVC instruction                                        */
59   DebugMonitor_IRQn          = -4,     /*!< -4  Debug Monitor                                                                  */
60   PendSV_IRQn                = -2,     /*!< -2  Pendable request for system service                                            */
61   SysTick_IRQn               = -1,     /*!< -1  System Tick Timer                                                              */
62 
63 /* ======================================  STM32N6xx Specific Interrupt Numbers  ============================================= */
64   PVD_PVM_IRQn               = 0,      /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection                                */
65   DTS_IRQn                   = 2,      /*!< Thermal Sensor interruption                                                        */
66   RCC_IRQn                   = 3,      /*!< RCC non-secure global interrupts through EXTI Line detection                       */
67   LOCKUP_IRQn                = 4,      /*!< LOCKUP / (no Overstack in CM55)                                                    */
68   CACHE_ECC_IRQn             = 5,      /*!< Error ECC cache interrupt                                                          */
69   TCM_ECC_IRQn               = 6,      /*!< TCM ECC interrupts                                                                 */
70   BKP_ECC_IRQn               = 7,      /*!< Backup RAM Interrupts                                                              */
71   FPU_IRQn                   = 8,      /*!< FPU interrupt                                                                      */
72   RTC_S_IRQn                 = 10,     /*!< RTC secure interrupts through EXTI Line detection                                  */
73   TAMP_IRQn                  = 11,     /*!< Tamper secure and non-secure interrupts through EXTI Line detection                */
74   RIFSC_TAMPER_IRQn          = 12,     /*!< RIF Tamper interrupts                                                              */
75   IAC_IRQn                   = 13,     /*!< IAC interrupt                                                                      */
76   RCC_S_IRQn                 = 14,     /*!< RCC secure global interrupts through EXTI Line detection                           */
77   RTC_IRQn                   = 16,     /*!< RTC non-secure interrupts through EXTI Line detection                              */
78   IWDG_IRQn                  = 18,     /*!< Internal Watchdog interrupt                                                        */
79   WWDG_IRQn                  = 19,     /*!< Window Watchdog interrupt                                                          */
80   EXTI0_IRQn                 = 20,     /*!< EXTI Line0 interrupt                                                               */
81   EXTI1_IRQn                 = 21,     /*!< EXTI Line1 interrupt                                                               */
82   EXTI2_IRQn                 = 22,     /*!< EXTI Line2 interrupt                                                               */
83   EXTI3_IRQn                 = 23,     /*!< EXTI Line3 interrupt                                                               */
84   EXTI4_IRQn                 = 24,     /*!< EXTI Line4 interrupt                                                               */
85   EXTI5_IRQn                 = 25,     /*!< EXTI Line5 interrupt                                                               */
86   EXTI6_IRQn                 = 26,     /*!< EXTI Line6 interrupt                                                               */
87   EXTI7_IRQn                 = 27,     /*!< EXTI Line7 interrupt                                                               */
88   EXTI8_IRQn                 = 28,     /*!< EXTI Line8 interrupt                                                               */
89   EXTI9_IRQn                 = 29,     /*!< EXTI Line9 interrupt                                                               */
90   EXTI10_IRQn                = 30,     /*!< EXTI Line10 interrupt                                                              */
91   EXTI11_IRQn                = 31,     /*!< EXTI Line11 interrupt                                                              */
92   EXTI12_IRQn                = 32,     /*!< EXTI Line12 interrupt                                                              */
93   EXTI13_IRQn                = 33,     /*!< EXTI Line13 interrupt                                                              */
94   EXTI14_IRQn                = 34,     /*!< EXTI Line14 interrupt                                                              */
95   EXTI15_IRQn                = 35,     /*!< EXTI Line15 interrupt                                                              */
96   SAES_IRQn                  = 36,     /*!< SAES interrupt                                                                     */
97   CRYP_IRQn                  = 37,     /*!< CRYP interrupt                                                                     */
98   PKA_IRQn                   = 38,     /*!< PKA interrupt                                                                      */
99   HASH_IRQn                  = 39,     /*!< HASH interrupt                                                                     */
100   RNG_IRQn                   = 40,     /*!< RNG global interrupt                                                               */
101   MCE1_IRQn                  = 42,     /*!< MCE1 global interrupt                                                              */
102   MCE2_IRQn                  = 43,     /*!< MCE2 global interrupt                                                              */
103   MCE3_IRQn                  = 44,     /*!< MCE3 global interrupt                                                              */
104   MCE4_IRQn                  = 45,     /*!< MCE4 global interrupt                                                              */
105   ADC1_2_IRQn                = 46,     /*!< ADC1 & ADC2 interrupt                                                              */
106   CSI_IRQn                   = 47,     /*!< CSI global interrupt                                                               */
107   DCMIPP_IRQn                = 48,     /*!< DCMIPP global interrupt                                                            */
108   PAHB_ERR_IRQn              = 52,     /*!< PAHB error interrupt                                                               */
109   NPU0_IRQn                  = 53,     /*!< NPU mst_ints[0] line interrupt                                                     */
110   NPU1_IRQn                  = 54,     /*!< NPU mst_ints[1] line interrupt                                                     */
111   NPU2_IRQn                  = 55,     /*!< NPU mst_ints[2] line interrupt                                                     */
112   NPU3_IRQn                  = 56,     /*!< NPU mst_ints[3] line interrupt                                                     */
113   CACHEAXI_IRQn              = 57,     /*!< NPU cache interrupt                                                                */
114   LTDC_LO_IRQn               = 58,     /*!< LTDC low-layer global interrupt                                                    */
115   LTDC_LO_ERR_IRQn           = 59,     /*!< LTDC low-layer error interrupt                                                     */
116   DMA2D_IRQn                 = 60,     /*!< DMA2D global interrupt                                                             */
117   JPEG_IRQn                  = 61,     /*!< JPEG global interrupt                                                              */
118   VENC_IRQn                  = 62,     /*!< VENC global interrupt                                                              */
119   GFXMMU_IRQn                = 63,     /*!< GFXMMU global interrupt                                                            */
120   GFXTIM_IRQn                = 64,     /*!< GFXTIM global interrupt                                                            */
121   GPU2D_IRQn                 = 65,     /*!< GPU2D interrupt                                                                    */
122   GPU2D_ER_IRQn              = 66,     /*!< GPU2D error interrupt                                                              */
123   ICACHE_IRQn                = 67,     /*!< GPU2D cache interrupt                                                              */
124   HPDMA1_Channel0_IRQn       = 68,     /*!< HPDMA1 Channel 0 global interrupt                                                  */
125   HPDMA1_Channel1_IRQn       = 69,     /*!< HPDMA1 Channel 1 global interrupt                                                  */
126   HPDMA1_Channel2_IRQn       = 70,     /*!< HPDMA1 Channel 2 global interrupt                                                  */
127   HPDMA1_Channel3_IRQn       = 71,     /*!< HPDMA1 Channel 3 global interrupt                                                  */
128   HPDMA1_Channel4_IRQn       = 72,     /*!< HPDMA1 Channel 4 global interrupt                                                  */
129   HPDMA1_Channel5_IRQn       = 73,     /*!< HPDMA1 Channel 5 global interrupt                                                  */
130   HPDMA1_Channel6_IRQn       = 74,     /*!< HPDMA1 Channel 6 global interrupt                                                  */
131   HPDMA1_Channel7_IRQn       = 75,     /*!< HPDMA1 Channel 7 global interrupt                                                  */
132   HPDMA1_Channel8_IRQn       = 76,     /*!< HPDMA1 Channel 8 global interrupt                                                  */
133   HPDMA1_Channel9_IRQn       = 77,     /*!< HPDMA1 Channel 9 global interrupt                                                  */
134   HPDMA1_Channel10_IRQn      = 78,     /*!< HPDMA1 Channel 10 global interrupt                                                 */
135   HPDMA1_Channel11_IRQn      = 79,     /*!< HPDMA1 Channel 11 global interrupt                                                 */
136   HPDMA1_Channel12_IRQn      = 80,     /*!< HPDMA1 Channel 12 global interrupt                                                 */
137   HPDMA1_Channel13_IRQn      = 81,     /*!< HPDMA1 Channel 13 global interrupt                                                 */
138   HPDMA1_Channel14_IRQn      = 82,     /*!< HPDMA1 Channel 14 global interrupt                                                 */
139   HPDMA1_Channel15_IRQn      = 83,     /*!< HPDMA1 Channel 15 global interrupt                                                 */
140   GPDMA1_Channel0_IRQn       = 84,     /*!< GPDMA1 Channel 0 interrupt                                                         */
141   GPDMA1_Channel1_IRQn       = 85,     /*!< GPDMA1 Channel 1 interrupt                                                         */
142   GPDMA1_Channel2_IRQn       = 86,     /*!< GPDMA1 Channel 2 interrupt                                                         */
143   GPDMA1_Channel3_IRQn       = 87,     /*!< GPDMA1 Channel 3 interrupt                                                         */
144   GPDMA1_Channel4_IRQn       = 88,     /*!< GPDMA1 Channel 4 interrupt                                                         */
145   GPDMA1_Channel5_IRQn       = 89,     /*!< GPDMA1 Channel 5 interrupt                                                         */
146   GPDMA1_Channel6_IRQn       = 90,     /*!< GPDMA1 Channel 6 interrupt                                                         */
147   GPDMA1_Channel7_IRQn       = 91,     /*!< GPDMA1 Channel 7 interrupt                                                         */
148   GPDMA1_Channel8_IRQn       = 92,     /*!< GPDMA1 Channel 8 interrupt                                                         */
149   GPDMA1_Channel9_IRQn       = 93,     /*!< GPDMA1 Channel 9 interrupt                                                         */
150   GPDMA1_Channel10_IRQn      = 94,     /*!< GPDMA1 Channel 10 interrupt                                                        */
151   GPDMA1_Channel11_IRQn      = 95,     /*!< GPDMA1 Channel 11 interrupt                                                        */
152   GPDMA1_Channel12_IRQn      = 96,     /*!< GPDMA1 Channel 12 interrupt                                                        */
153   GPDMA1_Channel13_IRQn      = 97,     /*!< GPDMA1 Channel 13 interrupt                                                        */
154   GPDMA1_Channel14_IRQn      = 98,     /*!< GPDMA1 Channel 14 interrupt                                                        */
155   GPDMA1_Channel15_IRQn      = 99,     /*!< GPDMA1 Channel 15 interrupt                                                        */
156   I2C1_EV_IRQn               = 100,    /*!< I2C1 event interrupt                                                               */
157   I2C1_ER_IRQn               = 101,    /*!< I2C1 error interrupt                                                               */
158   I2C2_EV_IRQn               = 102,    /*!< I2C2 event interrupt                                                               */
159   I2C2_ER_IRQn               = 103,    /*!< I2C2 error interrupt                                                               */
160   I2C3_EV_IRQn               = 104,    /*!< I2C3 event interrupt                                                               */
161   I2C3_ER_IRQn               = 105,    /*!< I2C3 error interrupt                                                               */
162   I2C4_EV_IRQn               = 106,    /*!< I2C4 event interrupt                                                               */
163   I2C4_ER_IRQn               = 107,    /*!< I2C4 error interrupt                                                               */
164   I3C1_EV_IRQn               = 108,    /*!< I3C1 event interrupt                                                               */
165   I3C1_ER_IRQn               = 109,    /*!< I3C1 error interrupt                                                               */
166   I3C2_EV_IRQn               = 110,    /*!< I3C2 event interrupt                                                               */
167   I3C2_ER_IRQn               = 111,    /*!< I3C2 error interrupt                                                               */
168   TIM1_BRK_IRQn              = 112,    /*!< TIM1 Break interrupt                                                               */
169   TIM1_UP_IRQn               = 113,    /*!< TIM1 Update interrupt                                                              */
170   TIM1_TRG_COM_IRQn          = 114,    /*!< TIM1 Trigger and Commutation interrupt                                             */
171   TIM1_CC_IRQn               = 115,    /*!< TIM1 Capture Compare interrupt                                                     */
172   TIM2_IRQn                  = 116,    /*!< TIM2 global interrupt                                                              */
173   TIM3_IRQn                  = 117,    /*!< TIM3 global interrupt                                                              */
174   TIM4_IRQn                  = 118,    /*!< TIM4 global interrupt                                                              */
175   TIM5_IRQn                  = 119,    /*!< TIM5 global interrupt                                                              */
176   TIM6_IRQn                  = 120,    /*!< TIM6 global interrupt                                                              */
177   TIM7_IRQn                  = 121,    /*!< TIM7 global interrupt                                                              */
178   TIM8_BRK_IRQn              = 122,    /*!< TIM8 Break interrupt                                                               */
179   TIM8_UP_IRQn               = 123,    /*!< TIM8 Update interrupt                                                              */
180   TIM8_TRG_COM_IRQn          = 124,    /*!< TIM8 Trigger and Commutation interrupt                                             */
181   TIM8_CC_IRQn               = 125,    /*!< TIM8 Capture Compare interrupt                                                     */
182   TIM9_IRQn                  = 126,    /*!< TIM9 global interrupt                                                              */
183   TIM10_IRQn                 = 127,    /*!< TIM10 global interrupt                                                             */
184   TIM11_IRQn                 = 128,    /*!< TIM11 global interrupt                                                             */
185   TIM12_IRQn                 = 129,    /*!< TIM12 global interrupt                                                             */
186   TIM13_IRQn                 = 130,    /*!< TIM13 global interrupt                                                             */
187   TIM14_IRQn                 = 131,    /*!< TIM14 global interrupt                                                             */
188   TIM15_IRQn                 = 132,    /*!< TIM15 global interrupt                                                             */
189   TIM16_IRQn                 = 133,    /*!< TIM16 global interrupt                                                             */
190   TIM17_IRQn                 = 134,    /*!< TIM17 global interrupt                                                             */
191   TIM18_IRQn                 = 135,    /*!< TIM18 global interrupt                                                             */
192   LPTIM1_IRQn                = 136,    /*!< LPTIM1 global interrupt                                                            */
193   LPTIM2_IRQn                = 137,    /*!< LPTIM2 global interrupt                                                            */
194   LPTIM3_IRQn                = 138,    /*!< LPTIM3 global interrupt                                                            */
195   LPTIM4_IRQn                = 139,    /*!< LPTIM4 global interrupt                                                            */
196   LPTIM5_IRQn                = 140,    /*!< LPTIM5 global interrupt                                                            */
197   ADF1_FLT0_IRQn             = 141,    /*!< ADF1 Filter 0 global interrupt                                                     */
198   MDF1_FLT0_IRQn             = 142,    /*!< MDF1 Filter 0 global interrupt                                                     */
199   MDF1_FLT1_IRQn             = 143,    /*!< MDF1 Filter 1 global interrupt                                                     */
200   MDF1_FLT2_IRQn             = 144,    /*!< MDF1 Filter 2 global interrupt                                                     */
201   MDF1_FLT3_IRQn             = 145,    /*!< MDF1 Filter 3 global interrupt                                                     */
202   MDF1_FLT4_IRQn             = 146,    /*!< MDF1 Filter 4 global interrupt                                                     */
203   MDF1_FLT5_IRQn             = 147,    /*!< MDF1 Filter 5 global interrupt                                                     */
204   SAI1_A_IRQn                = 148,    /*!< Serial Audio Interface 1 block A interrupt                                         */
205   SAI1_B_IRQn                = 149,    /*!< Serial Audio Interface 1 block B interrupt                                         */
206   SAI2_A_IRQn                = 150,    /*!< Serial Audio Interface 2 block A interrupt                                         */
207   SAI2_B_IRQn                = 151,    /*!< Serial Audio Interface 2 block B interrupt                                         */
208   SPDIFRX1_IRQn              = 152,    /*!< SPDIFRX1 interrupt                                                                 */
209   SPI1_IRQn                  = 153,    /*!< SPI1 global interrupt                                                              */
210   SPI2_IRQn                  = 154,    /*!< SPI2 global interrupt                                                              */
211   SPI3_IRQn                  = 155,    /*!< SPI3 global interrupt                                                              */
212   SPI4_IRQn                  = 156,    /*!< SPI4 global interrupt                                                              */
213   SPI5_IRQn                  = 157,    /*!< SPI5 global interrupt                                                              */
214   SPI6_IRQn                  = 158,    /*!< SPI6 global interrupt                                                              */
215   USART1_IRQn                = 159,    /*!< USART1 global interrupt                                                            */
216   USART2_IRQn                = 160,    /*!< USART2 global interrupt                                                            */
217   USART3_IRQn                = 161,    /*!< USART3 global interrupt                                                            */
218   UART4_IRQn                 = 162,    /*!< UART4 global interrupt                                                             */
219   UART5_IRQn                 = 163,    /*!< UART5 global interrupt                                                             */
220   USART6_IRQn                = 164,    /*!< USART3 global interrupt                                                            */
221   UART7_IRQn                 = 165,    /*!< UART7 global interrupt                                                             */
222   UART8_IRQn                 = 166,    /*!< UART8 global interrupt                                                             */
223   UART9_IRQn                 = 167,    /*!< UART9 global interrupt                                                             */
224   USART10_IRQn               = 168,    /*!< USART10 global interrupt                                                           */
225   LPUART1_IRQn               = 169,    /*!< LPUART1 global interrupt                                                           */
226   XSPI1_IRQn                 = 170,    /*!< XSPI1 global interrupt                                                             */
227   XSPI2_IRQn                 = 171,    /*!< XSPI2 global interrupt                                                             */
228   XSPI3_IRQn                 = 172,    /*!< XSPI3 global interrupt                                                             */
229   FMC_IRQn                   = 173,    /*!< FMC global interrupt                                                               */
230   SDMMC1_IRQn                = 174,    /*!< SDMMC1 global interrupt                                                            */
231   SDMMC2_IRQn                = 175,    /*!< SDMMC2 global interrupt                                                            */
232   UCPD1_IRQn                 = 176,    /*!< UCPD1 global interrupt                                                             */
233   USB1_OTG_HS_IRQn           = 177,    /*!< USB1 OTG HS interrupt                                                              */
234   USB2_OTG_HS_IRQn           = 178,    /*!< USB2 OTG HS interrupt                                                              */
235   ETH1_IRQn                  = 179,    /*!< ETH1 global interrupt                                                              */
236   FDCAN1_IT0_IRQn            = 180,    /*!< FDCAN1 interrupt 0                                                                 */
237   FDCAN1_IT1_IRQn            = 181,    /*!< FDCAN1 interrupt 1                                                                 */
238   FDCAN2_IT0_IRQn            = 182,    /*!< FDCAN2 interrupt 0                                                                 */
239   FDCAN2_IT1_IRQn            = 183,    /*!< FDCAN2 interrupt 1                                                                 */
240   FDCAN3_IT0_IRQn            = 184,    /*!< FDCAN3 interrupt 0                                                                 */
241   FDCAN3_IT1_IRQn            = 185,    /*!< FDCAN3 interrupt 1                                                                 */
242   FDCAN_CU_IRQn              = 186,    /*!< FDCAN Clock Unit interrupt                                                         */
243   MDIOS_IRQn                 = 187,    /*!< MDIOS global interrupt                                                             */
244   DCMI_PSSI_IRQn             = 188,    /*!< DCMI/PSSI global interrupt                                                         */
245   WAKEUP_PIN_IRQn            = 189,    /*!< Wake-up pins interrupt                                                             */
246   CTI_INT0_IRQn              = 190,    /*!< CTI INT0 interrupt                                                                 */
247   CTI_INT1_IRQn              = 191,    /*!< CTI INT1 interrupt                                                                 */
248   LTDC_UP_IRQn               = 193,    /*!< LTDC up-layer global interrupt                                                     */
249   LTDC_UP_ERR_IRQn           = 194,    /*!< LTDC up-layer error interrupt                                                      */
250 } IRQn_Type;
251 
252 
253 /* =========================================================================================================================== */
254 /* ================                           Processor and Core Peripheral Section                           ================ */
255 /* =========================================================================================================================== */
256 
257 /**
258   * @brief Configuration of the Cortex-M55 Processor and Core Peripherals
259    */
260 #define __CM55_REV                0x0101U /*!< Cortex-M55 revision r1p1                      */
261 #define __FPU_PRESENT             1U      /*!< CM55 Floating Point Unit present              */
262 #define __DSP_PRESENT             1U      /*!< CM55 Digital Signal Processing Unit present   */
263 #define __MPU_PRESENT             1U      /*!< CM55 Memory Programming Unit present          */
264 #define __ICACHE_PRESENT          1U      /*!< CM55 Instruction cache present                */
265 #define __DCACHE_PRESENT          1U      /*!< CM55 Data cache present                       */
266 #define __VTOR_PRESENT            1U      /*!< CM55 Vector table offset register present     */
267 #define __PMU_PRESENT             1U      /*!< CM55 Performance Monitoring Unit present      */
268 #define __PMU_NUM_EVENTCNT        8U      /*!< CM55 can monitor up to 8 PMU events           */
269 #define __NVIC_PRIO_BITS          4U      /*!< CM55 uses 4 bits for the Priority Levels      */
270 #define __Vendor_SysTickConfig    0U      /*!< Set to 1 if different SysTick Config is used  */
271 #define __SAUREGION_PRESENT       1U      /*!< SAU regions present                           */
272 
273 /** @} */ /* End of group Configuration_of_CMSIS */
274 
275 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
276 #define CPU_IN_SECURE_STATE
277 #endif
278 
279 #define CPU_AS_TRUSTED_DOMAIN
280 
281 #include "core_cm55.h"                    /*!< ARM Cortex-M55 processor and core peripherals */
282 #include "system_stm32n6xx.h"             /*!< STM32N6xx System */
283 
284 /* =========================================================================================================================== */
285 /* ================                            Device Specific Peripheral Section                             ================ */
286 /* =========================================================================================================================== */
287 
288 /** @addtogroup STM32N6xx_peripherals
289   * @{
290   */
291 
292 /**
293   * @brief Analog to Digital Converter (ADC)
294   */
295 typedef struct
296 {
297   __IO uint32_t ISR;           /*!< ADC interrupt and status register,                     Address offset: 0x00 */
298   __IO uint32_t IER;           /*!< ADC interrupt enable register,                         Address offset: 0x04 */
299   __IO uint32_t CR;            /*!< ADC control register,                                  Address offset: 0x08 */
300   __IO uint32_t CFGR1;         /*!< ADC configuration register 1,                          Address offset: 0x0C */
301   __IO uint32_t CFGR2;         /*!< ADC configuration register 2,                          Address offset: 0x10 */
302   __IO uint32_t SMPR1;         /*!< ADC sample time register 1,                            Address offset: 0x14 */
303   __IO uint32_t SMPR2;         /*!< ADC sample time register 2,                            Address offset: 0x18 */
304   __IO uint32_t PCSEL;         /*!< ADC channel preselection register,                     Address offset: 0x1C */
305   uint32_t      RESERVED1[4];  /*!< Reserved,                                              Address offset: 0x020-0x02C */
306   __IO uint32_t SQR1;          /*!< ADC regular sequence register 1,                       Address offset: 0x30 */
307   __IO uint32_t SQR2;          /*!< ADC regular sequence register 2,                       Address offset: 0x34 */
308   __IO uint32_t SQR3;          /*!< ADC regular sequence register 3,                       Address offset: 0x38 */
309   __IO uint32_t SQR4;          /*!< ADC regular sequence register 4,                       Address offset: 0x3C */
310   __IO uint32_t DR;            /*!< ADC regular data register,                             Address offset: 0x40 */
311   uint32_t      RESERVED2[2];  /*!< Reserved,                                              Address offset: 0x044-0x048 */
312   __IO uint32_t JSQR;          /*!< ADC injected sequence register,                        Address offset: 0x4C */
313   __IO uint32_t OFCFGR1;       /*!< ADC offset configuration register 1,                   Address offset: 0x50 */
314   __IO uint32_t OFCFGR2;       /*!< ADC offset configuration register 2,                   Address offset: 0x54 */
315   __IO uint32_t OFCFGR3;       /*!< ADC offset configuration register 3,                   Address offset: 0x58 */
316   __IO uint32_t OFCFGR4;       /*!< ADC offset configuration register 4,                   Address offset: 0x5C */
317   __IO uint32_t OFR1;          /*!< ADC offset register 1,                                 Address offset: 0x60 */
318   __IO uint32_t OFR2;          /*!< ADC offset register 2,                                 Address offset: 0x64 */
319   __IO uint32_t OFR3;          /*!< ADC offset register 3,                                 Address offset: 0x68 */
320   __IO uint32_t OFR4;          /*!< ADC offset register 4,                                 Address offset: 0x6C */
321   __IO uint32_t GCOMP;         /*!< ADC gain compensation register,                        Address offset: 0x70 */
322   uint32_t      RESERVED3[3];  /*!< Reserved,                                              Address offset: 0x074-0x07C */
323   __IO uint32_t JDR1;          /*!< ADC injected data register 1,                          Address offset: 0x80 */
324   __IO uint32_t JDR2;          /*!< ADC injected data register 2,                          Address offset: 0x84 */
325   __IO uint32_t JDR3;          /*!< ADC injected data register 3,                          Address offset: 0x88 */
326   __IO uint32_t JDR4;          /*!< ADC injected data register 4,                          Address offset: 0x8C */
327   uint32_t      RESERVED4[4];  /*!< Reserved,                                              Address offset: 0x090-0x09C */
328   __IO uint32_t AWD2CR;        /*!< ADC analog watchdog 2 configuration register,          Address offset: 0xA0 */
329   __IO uint32_t AWD3CR;        /*!< ADC analog watchdog 3 configuration register,          Address offset: 0xA4 */
330   __IO uint32_t AWD1LTR;       /*!< ADC analog watchdog 1 low threshold register,          Address offset: 0xA8 */
331   __IO uint32_t AWD1HTR;       /*!< ADC analog watchdog 1 high threshold register,         Address offset: 0xAC */
332   __IO uint32_t AWD2LTR;       /*!< ADC analog watchdog 2 low threshold register,          Address offset: 0xB0 */
333   __IO uint32_t AWD2HTR;       /*!< ADC analog watchdog 2 high threshold register,         Address offset: 0xB4 */
334   __IO uint32_t AWD3LTR;       /*!< ADC analog watchdog 3 low threshold register,          Address offset: 0xB8 */
335   __IO uint32_t AWD3HTR;       /*!< ADC analog watchdog 3 high threshold register,         Address offset: 0xBC */
336   __IO uint32_t DIFSEL;        /*!< ADC differential mode selection register,              Address offset: 0xC0 */
337   __IO uint32_t CALFACT;       /*!< ADC calibration factors,                               Address offset: 0xC4 */
338   uint32_t      RESERVED5[2];  /*!< Reserved,                                              Address offset: 0x0C8-0x0CC */
339   __IO uint32_t OR;            /*!< ADC option register,                                   Address offset: 0xD0 */
340 } ADC_TypeDef;
341 
342 typedef struct
343 {
344   __IO uint32_t CSR;           /*!< ADC common status register,                            Address offset: 0x300 */
345   uint32_t RESERVED;           /*!< Reserved,                                              Address offset: 0x304 */
346   __IO uint32_t CCR;           /*!< ADC common control register,                           Address offset: 0x308 */
347   __IO uint32_t CDR;           /*!< ADC common regular data register for dual mode,        Address offset: 0x30C */
348   __IO uint32_t CDR2;          /*!< ADC common regular data register for dual mode 32-bit, Address offset: 0x310 */
349 } ADC_Common_TypeDef;
350 
351 /**
352   * @brief Boot and Security
353   */
354 
355 typedef struct
356 {
357   __IO uint32_t FVRw[384];       /*!< BSEC fuse word (0-383) value register,       Address offset: 0x000-0x5FC */
358        uint32_t RESERVED0[128];  /*!< Reserved,                                    Address offset: 0x600-0x7FC */
359   __IO uint32_t SPLOCKx[12];     /*!< BSEC sticky program lock register (0-11),    Address offset: 0x800-0x82C */
360        uint32_t RESERVED1[4];    /*!< Reserved,                                    Address offset: 0x830-0x83C */
361   __IO uint32_t SWLOCKx[12];     /*!< BSEC sticky write lock register (0-11),      Address offset: 0x840-0x86C */
362        uint32_t RESERVED2[4];    /*!< Reserved,                                    Address offset: 0x870-0x87C */
363   __IO uint32_t SRLOCKx[12];     /*!< BSEC sticky reload lock register (0-11),     Address offset: 0x880-0x8AC */
364        uint32_t RESERVED3[4];    /*!< Reserved,                                    Address offset: 0x8B0-0x8BC */
365   __IO uint32_t OTPVLDRx[12];    /*!< BSEC OTP valid register (0-11),              Address offset: 0x8C0-0x8EC */
366        uint32_t RESERVED4[20];   /*!< Reserved,                                    Address offset: 0x8F0-0x93C */
367   __IO uint32_t SFSRx[12];       /*!< BSEC shadowed fuses status register (0-11),  Address offset: 0x940-0x96C */
368        uint32_t RESERVED5[165];  /*!< Reserved,                                    Address offset: 0x970-0xC00 */
369   __IO uint32_t OTPCR;           /*!< BSEC OTP control register,                   Address offset: 0xC04 */
370   __IO uint32_t WDR;             /*!< BSEC write data register,                    Address offset: 0xC08 */
371        uint32_t RESERVED6[125];  /*!< Reserved,                                    Address offset: 0xC0C-0xDFC */
372   __IO uint32_t SCRATCHRx[4];    /*!< BSEC scratch register (0-3),                 Address offset: 0xE00-0xE0C */
373   __IO uint32_t LOCKR;           /*!< BSEC lock register,                          Address offset: 0xE10 */
374   __IO uint32_t JTAGINR;         /*!< BSEC JTAG input register,                    Address offset: 0xE14 */
375   __IO uint32_t JTAGOUTR;        /*!< BSEC JTAG output register,                   Address offset: 0xE18 */
376        uint32_t RESERVED7[2];    /*!< Reserved,                                    Address offset: 0xE1C-0xE20 */
377   __IO uint32_t UNMAPR;          /*!< BSEC unmap register,                         Address offset: 0xE24 */
378        uint32_t RESERVED8[6];    /*!< Reserved,                                    Address offset: 0xE28-0xE3C */
379   __IO uint32_t SR;              /*!< BSEC status register,                        Address offset: 0xE40 */
380   __IO uint32_t OTPSR;           /*!< BSEC OTP status register,                    Address offset: 0xE44 */
381        uint32_t RESERVED9[14];   /*!< Reserved,                                    Address offset: 0xE48-0xE7C */
382   __IO uint32_t EPOCHRx[2];      /*!< BSEC epoch register (0-1),                   Address offset: 0xE80-0xE84 */
383   __IO uint32_t EPOCHSELR;       /*!< BSEC epoch select register,                  Address offset: 0xE88 */
384   __IO uint32_t DBGCR;           /*!< BSEC debug control register,                 Address offset: 0xE8C */
385   __IO uint32_t AP_UNLOCK;       /*!< BSEC AP unlock,                              Address offset: 0xE90 */
386   __IO uint32_t HDPLSR;          /*!< BSEC hide protection level status register,  Address offset: 0xE94 */
387   __IO uint32_t HDPLCR;          /*!< BSEC hide protection level control register, Address offset: 0xE98 */
388   __IO uint32_t NEXTLR;          /*!< BSEC next hide protection level register,    Address offset: 0xE9C */
389        uint32_t RESERVED10[40];  /*!< Reserved,                                    Address offset: 0xEA0-0xF3C */
390   __IO uint32_t WOSCRx[8];       /*!< BSEC write once scratch register (0-7),      Address offset: 0xF40-0xF5C */
391        uint32_t RESERVED11[34];  /*!< Reserved,                                    Address offset: 0xF60-0xFE4 */
392   __IO uint32_t HRCR;            /*!< BSEC hot reset count register,               Address offset: 0xFE8 */
393   __IO uint32_t WRCR;            /*!< BSEC warm reset count register,              Address offset: 0xFEC */
394 } BSEC_TypeDef;
395 
396 /**
397   * @brief Axi Cache
398   */
399 typedef struct
400 {
401   __IO uint32_t CR1;            /*!< CACHEAXI control register 1,                   Address offset: 0x00 */
402   __IO uint32_t SR;             /*!< CACHEAXI status register,                      Address offset: 0x04 */
403   __IO uint32_t IER;            /*!< CACHEAXI interrupt enable register,            Address offset: 0x08 */
404   __IO uint32_t FCR;            /*!< CACHEAXI flag clear register,                  Address offset: 0x0C */
405   __IO uint32_t RHMONR;         /*!< CACHEAXI read hit monitor register,            Address offset: 0x10 */
406   __IO uint32_t RMMONR;         /*!< CACHEAXI read miss monitor register,           Address offset: 0x14 */
407   __IO uint32_t RAMMONR;        /*!< CACHEAXI read-allocate miss monitor register,  Address offset: 0x18 */
408   __IO uint32_t EVIMONR;        /*!< CACHEAXI eviction monitor register,            Address offset: 0x1C */
409   __IO uint32_t WHMONR;         /*!< CACHEAXI write-hit monitor register,           Address offset: 0x20 */
410   __IO uint32_t WMMONR;         /*!< CACHEAXI write-miss monitor register,          Address offset: 0x24 */
411   __IO uint32_t WAMMONR;        /*!< CACHEAXI write-allocate miss monitor register, Address offset: 0x28 */
412   __IO uint32_t WTMONR;         /*!< CACHEAXI write-through monitor register,       Address offset: 0x2C */
413        uint32_t RESERVED1[52];  /*!< Reserved,                                      Address offset: 0x30-0xFC */
414   __IO uint32_t CR2;            /*!< CACHEAXI control register 2,                   Address offset: 0x100 */
415   __IO uint32_t CMDRSADDRR;     /*!< CACHEAXI command start address register,       Address offset: 0x104 */
416   __IO uint32_t CMDREADDRR;     /*!< CACHEAXI command end address register,         Address offset: 0x108 */
417 } CACHEAXI_TypeDef;
418 
419 /**
420   * @brief CRC calculation unit
421   */
422 typedef struct
423 {
424   __IO uint32_t DR;            /*!< CRC Data register,                              Address offset: 0x00 */
425   __IO uint32_t IDR;           /*!< CRC Independent data register,                  Address offset: 0x04 */
426   __IO uint32_t CR;            /*!< CRC Control register,                           Address offset: 0x08 */
427        uint32_t RESERVED1;     /*!< Reserved,                                                       0x0C */
428   __IO uint32_t INIT;          /*!< Initial CRC value register,                     Address offset: 0x10 */
429   __IO uint32_t POL;           /*!< CRC polynomial register,                        Address offset: 0x14 */
430 } CRC_TypeDef;
431 
432 
433 /**
434   * @brief Cryp Processor
435   */
436 typedef struct
437 {
438   __IO uint32_t CR;         /*!< CRYP control register,                                    Address offset: 0x00 */
439   __IO uint32_t SR;         /*!< CRYP status register,                                     Address offset: 0x04 */
440   __IO uint32_t DIN;        /*!< CRYP data input register,                                 Address offset: 0x08 */
441   __IO uint32_t DOUT;       /*!< CRYP data output register,                                Address offset: 0x0C */
442   __IO uint32_t DMACR;      /*!< CRYP DMA control register,                                Address offset: 0x10 */
443   __IO uint32_t IMSCR;      /*!< CRYP interrupt mask set/clear register,                   Address offset: 0x14 */
444   __IO uint32_t RISR;       /*!< CRYP raw interrupt status register,                       Address offset: 0x18 */
445   __IO uint32_t MISR;       /*!< CRYP masked interrupt status register,                    Address offset: 0x1C */
446   __IO uint32_t K0LR;       /*!< CRYP key left  register 0,                                Address offset: 0x20 */
447   __IO uint32_t K0RR;       /*!< CRYP key right register 0,                                Address offset: 0x24 */
448   __IO uint32_t K1LR;       /*!< CRYP key left  register 1,                                Address offset: 0x28 */
449   __IO uint32_t K1RR;       /*!< CRYP key right register 1,                                Address offset: 0x2C */
450   __IO uint32_t K2LR;       /*!< CRYP key left  register 2,                                Address offset: 0x30 */
451   __IO uint32_t K2RR;       /*!< CRYP key right register 2,                                Address offset: 0x34 */
452   __IO uint32_t K3LR;       /*!< CRYP key left  register 3,                                Address offset: 0x38 */
453   __IO uint32_t K3RR;       /*!< CRYP key right register 3,                                Address offset: 0x3C */
454   __IO uint32_t IV0LR;      /*!< CRYP initialization vector left-word  register 0,         Address offset: 0x40 */
455   __IO uint32_t IV0RR;      /*!< CRYP initialization vector right-word register 0,         Address offset: 0x44 */
456   __IO uint32_t IV1LR;      /*!< CRYP initialization vector left-word  register 1,         Address offset: 0x48 */
457   __IO uint32_t IV1RR;      /*!< CRYP initialization vector right-word register 1,         Address offset: 0x4C */
458   __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0,        Address offset: 0x50 */
459   __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1,        Address offset: 0x54 */
460   __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2,        Address offset: 0x58 */
461   __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3,        Address offset: 0x5C */
462   __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4,        Address offset: 0x60 */
463   __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5,        Address offset: 0x64 */
464   __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6,        Address offset: 0x68 */
465   __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7,        Address offset: 0x6C */
466   __IO uint32_t CSGCM0R;    /*!< CRYP GCM/GMAC context swap register 0,                    Address offset: 0x70 */
467   __IO uint32_t CSGCM1R;    /*!< CRYP GCM/GMAC context swap register 1,                    Address offset: 0x74 */
468   __IO uint32_t CSGCM2R;    /*!< CRYP GCM/GMAC context swap register 2,                    Address offset: 0x78 */
469   __IO uint32_t CSGCM3R;    /*!< CRYP GCM/GMAC context swap register 3,                    Address offset: 0x7C */
470   __IO uint32_t CSGCM4R;    /*!< CRYP GCM/GMAC context swap register 4,                    Address offset: 0x80 */
471   __IO uint32_t CSGCM5R;    /*!< CRYP GCM/GMAC context swap register 5,                    Address offset: 0x84 */
472   __IO uint32_t CSGCM6R;    /*!< CRYP GCM/GMAC context swap register 6,                    Address offset: 0x88 */
473   __IO uint32_t CSGCM7R;    /*!< CRYP GCM/GMAC context swap register 7,                    Address offset: 0x8C */
474 } CRYP_TypeDef;
475 
476 /*
477  * @brief  (CSI)
478  */
479 typedef struct
480 {
481   __IO uint32_t CR;               /*!< CSI-2 Host control register                           Address offset: 0x0000 */
482   __IO uint32_t PCR;              /*!< CSI-2 Host DPHY_RX control register                   Address offset: 0x0004 */
483        uint32_t RESERVED0[2];     /*!< Reserved                                              Address offset: 0x0008-0x000C */
484   __IO uint32_t VC0CFGR1;         /*!< CSI-2 Host virtual channel 0 configuration register 1 Address offset: 0x0010 */
485   __IO uint32_t VC0CFGR2;         /*!< CSI-2 Host virtual channel 0 configuration register 2 Address offset: 0x0014 */
486   __IO uint32_t VC0CFGR3;         /*!< CSI-2 Host virtual channel 0 configuration register 3 Address offset: 0x0018 */
487   __IO uint32_t VC0CFGR4;         /*!< CSI-2 Host virtual channel 0 configuration register 4 Address offset: 0x001C */
488   __IO uint32_t VC1CFGR1;         /*!< CSI-2 Host virtual channel 1 configuration register 1 Address offset: 0x0020 */
489   __IO uint32_t VC1CFGR2;         /*!< CSI-2 Host virtual channel 1 configuration register 2 Address offset: 0x0024 */
490   __IO uint32_t VC1CFGR3;         /*!< CSI-2 Host virtual channel 1 configuration register 3 Address offset: 0x0028 */
491   __IO uint32_t VC1CFGR4;         /*!< CSI-2 Host virtual channel 1 configuration register 4 Address offset: 0x002C */
492   __IO uint32_t VC2CFGR1;         /*!< CSI-2 Host virtual channel 2 configuration register 1 Address offset: 0x0030 */
493   __IO uint32_t VC2CFGR2;         /*!< CSI-2 Host virtual channel 2 configuration register 2 Address offset: 0x0034 */
494   __IO uint32_t VC2CFGR3;         /*!< CSI-2 Host virtual channel 2 configuration register 3 Address offset: 0x0038 */
495   __IO uint32_t VC2CFGR4;         /*!< CSI-2 Host virtual channel 2 configuration register 4 Address offset: 0x003C */
496   __IO uint32_t VC3CFGR1;         /*!< CSI-2 Host virtual channel 3 configuration register 1 Address offset: 0x0040 */
497   __IO uint32_t VC3CFGR2;         /*!< CSI-2 Host virtual channel 3 configuration register 2 Address offset: 0x0044 */
498   __IO uint32_t VC3CFGR3;         /*!< CSI-2 Host virtual channel 3 configuration register 3 Address offset: 0x0048 */
499   __IO uint32_t VC3CFGR4;         /*!< CSI-2 Host virtual channel 3 configuration register 4 Address offset: 0x004C */
500   __IO uint32_t LB0CFGR;          /*!< CSI-2 Host line byte 0 configuration register         Address offset: 0x0050 */
501   __IO uint32_t LB1CFGR;          /*!< CSI-2 Host line byte 1 configuration register         Address offset: 0x0054 */
502   __IO uint32_t LB2CFGR;          /*!< CSI-2 Host line byte 2 configuration register         Address offset: 0x0058 */
503   __IO uint32_t LB3CFGR;          /*!< CSI-2 Host line byte 3 configuration register         Address offset: 0x005C */
504   __IO uint32_t TIM0CFGR;         /*!< CSI-2 Host timer 0 configuration register             Address offset: 0x0060 */
505   __IO uint32_t TIM1CFGR;         /*!< CSI-2 Host timer 1 configuration register             Address offset: 0x0064 */
506   __IO uint32_t TIM2CFGR;         /*!< CSI-2 Host timer 2 configuration register             Address offset: 0x0068 */
507   __IO uint32_t TIM3CFGR;         /*!< CSI-2 Host timer 3 configuration register             Address offset: 0x006C */
508   __IO uint32_t LMCFGR;           /*!< CSI-2 Host lane merger configuration register         Address offset: 0x0070 */
509   __IO uint32_t PRGITR;           /*!< CSI-2 Host program interrupt register                 Address offset: 0x0074 */
510   __IO uint32_t WDR;              /*!< CSI-2 Host watchdog register                          Address offset: 0x0078 */
511        uint32_t RESERVED1;        /*!< Reserved                                              Address offset: 0x007C */
512   __IO uint32_t IER0;             /*!< CSI-2 Host Interrupt enable register 0                Address offset: 0x0080 */
513   __IO uint32_t IER1;             /*!< CSI-2 Host Interrupt enable register 1                Address offset: 0x0084 */
514        uint32_t RESERVED2[2];     /*!< Reserved                                              Address offset: 0x0088-0x008C */
515   __IO uint32_t SR0;              /*!< CSI-2 Host status register 0                          Address offset: 0x0090 */
516   __IO uint32_t SR1;              /*!< CSI-2 Host status register 1                          Address offset: 0x0094 */
517        uint32_t RESERVED3[26];    /*!< Reserved                                              Address offset: 0x0098-0x00FC */
518   __IO uint32_t FCR0;             /*!< CSI-2 Host Flag clear register 0                      Address offset: 0x0100 */
519   __IO uint32_t FCR1;             /*!< CSI-2 Host Flag clear register 1                      Address offset: 0x0104 */
520        uint32_t RESERVED4[2];     /*!< Reserved                                              Address offset: 0x0108-0x010C */
521   __IO uint32_t SPDFR;            /*!< CSI-2 Host short packet data field register           Address offset: 0x0110 */
522   __IO uint32_t ERR1;             /*!< CSI-2 Host error register 1                           Address offset: 0x0114 */
523   __IO uint32_t ERR2;             /*!< CSI-2 Host error register 2                           Address offset: 0x0118 */
524        uint32_t RESERVED5[953];   /*!< Reserved                                              Address offset: 0x011C-0x0FFC */
525   __IO uint32_t PRCR;             /*!< CSI PHY reset control register                        Address offset: 0x1000 */
526   __IO uint32_t PMCR;             /*!< CSI PHY mode control register                         Address offset: 0x1004 */
527   __IO uint32_t PFCR;             /*!< CSI PHY frequency control register                    Address offset: 0x1008 */
528        uint32_t RESERVED6;        /*!< Reserved                                              Address offset: 0x100C */
529   __IO uint32_t PTCR0;            /*!< CSI PHY test control register 0                       Address offset: 0x1010 */
530   __IO uint32_t PTCR1;            /*!< CSI PHY test control register 1                       Address offset: 0x1014 */
531   __IO uint32_t PTSR;             /*!< CSI PHY test status register                          Address offset: 0x1018 */
532        uint32_t RESERVED7[1017];  /*!< Reserved                                              Address offset: 0x101C-0x1FFC */
533 } CSI_TypeDef;
534 
535 /**
536   * @brief Debug MCU
537   */
538 typedef struct
539 {
540   __IO uint32_t IDCODE;        /*!< MCU device ID code,                            Address offset: 0x00  */
541   __IO uint32_t CR;            /*!< Debug MCU configuration register,              Address offset: 0x04  */
542   uint32_t RESERVED1[2];       /*!< Reserved,                                  Address offset: 0x08-0x0C */
543   __IO uint32_t APB1LFZ1;      /*!< Debug MCU APB1LFZ1 freeze register,            Address offset: 0x10  */
544   __IO uint32_t APB1HFZ1;      /*!< Debug MCU APB1HFZ1 freeze register,            Address offset: 0x14  */
545   __IO uint32_t APB2FZ1;       /*!< Debug MCU APB2FZ1 freeze register,             Address offset: 0x18  */
546   __IO uint32_t APB4FZ1;       /*!< Debug MCU APB4FZ1 freeze register,             Address offset: 0x1C  */
547   __IO uint32_t APB5FZ1;       /*!< Debug MCU APB5FZ1 freeze register,             Address offset: 0x20  */
548   __IO uint32_t AHB1FZ1;       /*!< Debug MCU AHB1FZ1 freeze register,             Address offset: 0x24  */
549   __IO uint32_t AHB5FZ1;       /*!< Debug MCU AHB5FZ1 freeze register,             Address offset: 0x28  */
550   uint32_t RESERVED2[52];      /*!< Reserved,                                  Address offset: 0x2C-0xF8 */
551   __IO uint32_t SR;            /*!< Debug MCU status register,                     Address offset: 0xFC  */
552   __IO uint32_t DBG_AUTH_HOST; /*!< Debug MCU authentication host register,        Address offset: 0x100 */
553   __IO uint32_t DBG_AUTH_DEV;  /*!< Debug MCU authentication device register,      Address offset: 0x104 */
554   __IO uint32_t DBG_AUTH_ACK;  /*!< Debug MCU acknowledge authentication register, Address offset: 0x104 */
555 } DBGMCU_TypeDef;
556 
557 /**
558   * @brief DCMI
559   */
560 typedef struct
561 {
562   __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
563   __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
564   __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
565   __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
566   __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
567   __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
568   __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
569   __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
570   __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
571   __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
572   __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
573 } DCMI_TypeDef;
574 
575 #define DCMIPP_NUM_OF_PIPES 0x03U
576 
577 typedef struct
578 {
579   uint32_t PxRIxCR1;      /*! DCMIPP Pipex ROIx configuration register 1  Address offset: 0x924 + (x - 1) * 0x400, (x = 1 to 2)  */
580   uint32_t PxRIxCR2;      /*! DCMIPP Pipex ROIx configuration register 2  Address offset: 0x928 + (x - 1) * 0x400, (x = 1 to 2)  */
581 } DCMIPP_Region_TypeDef;
582 
583 /*
584  * @brief Digital camera interface pixel pipeline DCMIPP
585  */
586 typedef struct
587 {
588   __IO uint32_t IPGR1;           /*!< DCMIPP IPPLUG global register 1                                    Address offset: 0x000 */
589   __IO uint32_t IPGR2;           /*!< DCMIPP IPPLUG global register 2                                    Address offset: 0x004 */
590   __IO uint32_t IPGR3;           /*!< DCMIPP IPPLUG global register 3                                    Address offset: 0x008 */
591        uint32_t RESERVED0[4];    /*!< Reserved                                                           Address offset: 0x00C-0x018 */
592   __IO uint32_t IPGR8;           /*!< DCMIPP IPPLUG identification register                              Address offset: 0x01C */
593   __IO uint32_t IPC1R1;          /*!< DCMIPP IPPLUG Clientx register 1                                   Address offset: 0x020 + 0x10 * (x - 1), (x = 1 to 5) */
594   __IO uint32_t IPC1R2;          /*!< DCMIPP IPPLUG Clientx register 2                                   Address offset: 0x024 + 0x10 * (x - 1), (x = 1 to 5) */
595   __IO uint32_t IPC1R3;          /*!< DCMIPP IPPLUG Clientx register 3                                   Address offset: 0x028 + 0x10 * (x - 1), (x = 1 to 5) */
596        uint32_t RESERVED1;       /*!< Reserved                                                           Address offset: 0x02C */
597   __IO uint32_t IPC2R1;          /*!< DCMIPP IPPLUG Clientx register 1                                   Address offset: 0x030 */
598   __IO uint32_t IPC2R2;          /*!< DCMIPP IPPLUG Clientx register 2                                   Address offset: 0x034 */
599   __IO uint32_t IPC2R3;          /*!< DCMIPP IPPLUG Clientx register 3                                   Address offset: 0x038 */
600        uint32_t RESERVED2;       /*!< Reserved                                                           Address offset: 0x03C */
601   __IO uint32_t IPC3R1;          /*!< DCMIPP IPPLUG Clientx register 1                                   Address offset: 0x040 */
602   __IO uint32_t IPC3R2;          /*!< DCMIPP IPPLUG Clientx register 2                                   Address offset: 0x044 */
603   __IO uint32_t IPC3R3;          /*!< DCMIPP IPPLUG Clientx register 3                                   Address offset: 0x048 */
604        uint32_t RESERVED3;       /*!< Reserved                                                           Address offset: 0x04C */
605   __IO uint32_t IPC4R1;          /*!< DCMIPP IPPLUG Clientx register 1                                   Address offset: 0x050 */
606   __IO uint32_t IPC4R2;          /*!< DCMIPP IPPLUG Clientx register 2                                   Address offset: 0x054 */
607   __IO uint32_t IPC4R3;          /*!< DCMIPP IPPLUG Clientx register 3                                   Address offset: 0x058 */
608        uint32_t RESERVED4;       /*!< Reserved                                                           Address offset: 0x05C */
609   __IO uint32_t IPC5R1;          /*!< DCMIPP IPPLUG Clientx register 1                                   Address offset: 0x060 */
610   __IO uint32_t IPC5R2;          /*!< DCMIPP IPPLUG Clientx register 2                                   Address offset: 0x064 */
611   __IO uint32_t IPC5R3;          /*!< DCMIPP IPPLUG Clientx register 3                                   Address offset: 0x068 */
612        uint32_t RESERVED5[38];   /*!< Reserved                                                           Address offset: 0x06C-0x100 */
613   __IO uint32_t PRCR;            /*!< DCMIPP parallel interface control register                         Address offset: 0x104 */
614   __IO uint32_t PRESCR;          /*!< DCMIPP parallel interface embedded synchronization code register   Address offset: 0x108 */
615   __IO uint32_t PRESUR;          /*!< DCMIPP parallel interface embedded synchronization unmask register Address offset: 0x10C */
616        uint32_t RESERVED6[57];   /*!< Reserved                                                           Address offset: 0x110-0x1F0 */
617   __IO uint32_t PRIER;           /*!< DCMIPP parallel interface interrupt enable register                Address offset: 0x1F4 */
618   __IO uint32_t PRSR;            /*!< DCMIPP parallel interface status register                          Address offset: 0x1F8 */
619   __IO uint32_t PRFCR;           /*!< DCMIPP parallel interface interrupt clear register                 Address offset: 0x1FC */
620        uint32_t RESERVED7;       /*!< Reserved                                                           Address offset: 0x200 */
621   __IO uint32_t CMCR;            /*!< DCMIPP common configuration register                               Address offset: 0x204 */
622   __IO uint32_t CMFRCR;          /*!< DCMIPP common frame counter register                               Address offset: 0x208 */
623        uint32_t RESERVED8[121];  /*!< Reserved                                                           Address offset: 0x20C-0x3EC */
624   __IO uint32_t CMIER;           /*!< DCMIPP common interrupt enable register                            Address offset: 0x3F0 */
625   __IO uint32_t CMSR1;           /*!< DCMIPP common status register 1                                    Address offset: 0x3F4 */
626   __IO uint32_t CMSR2;           /*!< DCMIPP common status register 2                                    Address offset: 0x3F8 */
627   __IO uint32_t CMFCR;           /*!< DCMIPP common interrupt clear register                             Address offset: 0x3FC */
628        uint32_t RESERVED9;            /*!< Reserved                                                      Address offset: 0x400 */
629   __IO uint32_t P0FSCR;          /*!< DCMIPP Pipe0 flow selection configuration register                 Address offset: 0x404 */
630        uint32_t RESERVED10[62];  /*!< Reserved                                                           Address offset: 0x408-0x4FC */
631   __IO uint32_t P0FCTCR;         /*!< DCMIPP Pipe0 flow control configuration register                   Address offset: 0x500 */
632   __IO uint32_t P0SCSTR;         /*!< DCMIPP Pipe0 stat/crop start register                              Address offset: 0x504 */
633   __IO uint32_t P0SCSZR;         /*!< DCMIPP Pipe0 stat/crop size register                               Address offset: 0x508 */
634        uint32_t RESERVED11[41];  /*!< Reserved                                                           Address offset: 0x50C-0x5AC */
635   __IO uint32_t P0DCCNTR;        /*!< DCMIPP Pipe0 dump counter register                                 Address offset: 0x5B0 */
636   __IO uint32_t P0DCLMTR;        /*!< DCMIPP Pipe0 dump limit register                                   Address offset: 0x5B4 */
637        uint32_t RESERVED12[2];   /*!< Reserved                                                           Address offset: 0x5B8-0x5BC */
638   __IO uint32_t P0PPCR;          /*!< DCMIPP Pipe0 pixel packer configuration register                   Address offset: 0x5C0 */
639   __IO uint32_t P0PPM0AR1;       /*!< DCMIPP Pipe0 pixel packer Memory0 address register 1               Address offset: 0x5C4 */
640   __IO uint32_t P0PPM0AR2;       /*!< DCMIPP Pipe0 pixel packer Memory0 address register 2               Address offset: 0x5C8 */
641        uint32_t RESERVED13;      /*!< Reserved                                                           Address offset: 0x5C8-0x5CC */
642   __IO uint32_t P0STM0AR;        /*!< DCMIPP Pipe0 status Memory0 address register                       Address offset: 0x5D0 */
643        uint32_t RESERVED14[8];   /*!< Reserved                                                           Address offset: 0x5D4-0x5F0 */
644   __IO uint32_t P0IER;           /*!< DCMIPP Pipe0 interrupt enable register                             Address offset: 0x5F4 */
645   __IO uint32_t P0SR;            /*!< DCMIPP Pipe0 status register                                       Address offset: 0x5F8 */
646   __IO uint32_t P0FCR;           /*!< DCMIPP Pipe0 interrupt clear register                              Address offset: 0x5FC */
647        uint32_t RESERVED15;      /*!< Reserved                                                           Address offset: 0x600 */
648   __IO uint32_t P0CFSCR;         /*!< DCMIPP Pipe0 current flow selection configuration register         Address offset: 0x604 */
649        uint32_t RESERVED17[62];  /*!< Reserved                                                           Address offset: 0x608-0x6FC */
650   __IO uint32_t P0CFCTCR;        /*!< DCMIPP Pipe0 current flow control configuration register           Address offset: 0x700 */
651   __IO uint32_t P0CSCSTR;        /*!< DCMIPP Pipe0 current stat/crop start register                      Address offset: 0x704 */
652   __IO uint32_t P0CSCSZR;        /*!< DCMIPP Pipe0 current stat/crop size register                       Address offset: 0x708 */
653        uint32_t RESERVED18[45];  /*!< Reserved                                                           Address offset: 0x70C-0x7BC */
654   __IO uint32_t P0CPPCR;         /*!< DCMIPP Pipe0 current pixel packer configuration register           Address offset: 0x7C0 */
655   __IO uint32_t P0CPPM0AR1;      /*!< DCMIPP Pipe0 current pixel packer Memory0 address register 1       Address offset: 0x7C4 */
656   __IO uint32_t P0CPPM0AR2;      /*!< DCMIPP Pipe0 current pixel packer Memory0 address register 2       Address offset: */
657        uint32_t RESERVED19[14];  /*!< Reserved                                                           Address offset: 0x7C8-0x7FC */
658   __IO uint32_t P1FSCR;          /*!< DCMIPP Pipe1 flow selection configuration register                 Address offset: 0x804 */
659        uint32_t RESERVED20[6];   /*!< Reserved                                                           Address offset: 0x808-0x81C */
660   __IO uint32_t P1SRCR;          /*!< DCMIPP Pipe1 stat removal configuration register                   Address offset: 0x820 */
661   __IO uint32_t P1BPRCR;         /*!< DCMIPP Pipe1 bad pixel removal control register                    Address offset: 0x824 */
662   __IO uint32_t P1BPRSR;         /*!< DCMIPP Pipe1 bad pixel removal status register                     Address offset: 0x828 */
663        uint32_t RESERVED21;      /*!< Reserved                                                           Address offset: 0x82C */
664   __IO uint32_t P1DECR;          /*!< DCMIPP Pipe1 decimation register                                   Address offset: 0x830 */
665        uint32_t RESERVED22[3];   /*!< Reserved                                                           Address offset: 0x834-0x83C */
666   __IO uint32_t P1BLCCR;         /*!< DCMIPP Pipe1 black level calibration control register              Address offset: 0x840 */
667   __IO uint32_t P1EXCR1;         /*!< DCMIPP Pipe1 exposure control register 1                           Address offset: 0x844 */
668   __IO uint32_t P1EXCR2;         /*!< DCMIPP Pipe1 exposure control register 2                           Address offset: 0x848 */
669        uint32_t RESERVED23;      /*!< Reserved                                                           Address offset: 0x84C */
670   __IO uint32_t P1ST1CR;         /*!< DCMIPP Pipe1 statistics 1 control register                         Address offset: 0x850 */
671   __IO uint32_t P1ST2CR;         /*!< DCMIPP Pipe1 statistics 2 control register                         Address offset: 0x854 */
672   __IO uint32_t P1ST3CR;         /*!< DCMIPP Pipe1 statistics 3 control register                         Address offset: 0x858 */
673   __IO uint32_t P1STSTR;         /*!< DCMIPP Pipe1 statistics window start register                      Address offset: 0x85C */
674   __IO uint32_t P1STSZR;         /*!< DCMIPP Pipe1 statistics window size register                       Address offset: 0x860 */
675   __IO uint32_t P1ST1SR;         /*!< DCMIPP Pipe1 statistics 1 status register                          Address offset: 0x864 */
676   __IO uint32_t P1ST2SR;         /*!< DCMIPP Pipe1 statistics 2 status register                          Address offset: 0x868 */
677   __IO uint32_t P1ST3SR;         /*!< DCMIPP Pipe1 statistics 3 status register                          Address offset: 0x86C */
678   __IO uint32_t P1DMCR;          /*!< DCMIPP Pipe1 demosaicing configuration register                    Address offset: 0x870 */
679        uint32_t RESERVED24[3];   /*!< Reserved                                                           Address offset: 0x874-0x87C */
680   __IO uint32_t P1CCCR;          /*!< DCMIPP Pipe1 ColorConv configuration register                      Address offset: 0x880 */
681   __IO uint32_t P1CCRR1;         /*!< DCMIPP Pipe1 ColorConv red coefficient register 1                  Address offset: 0x884 */
682   __IO uint32_t P1CCRR2;         /*!< DCMIPP Pipe1 ColorConv red coefficient register 2                  Address offset: 0x888 */
683   __IO uint32_t P1CCGR1;         /*!< DCMIPP Pipe1 ColorConv green coefficient register 1                Address offset: 0x88C */
684   __IO uint32_t P1CCGR2;         /*!< DCMIPP Pipe1 ColorConv green coefficient register 2                Address offset: 0x890 */
685   __IO uint32_t P1CCBR1;         /*!< DCMIPP Pipe1 ColorConv blue coefficient register 1                 Address offset: 0x894 */
686   __IO uint32_t P1CCBR2;         /*!< DCMIPP Pipe1 ColorConv blue coefficient register 2                 Address offset: 0x898 */
687        uint32_t RESERVED25;      /*!< Reserved                                                           Address offset: 0x89C */
688   __IO uint32_t P1CTCR1;         /*!< DCMIPP Pipe1 contrast control register 1                           Address offset: 0x8A0 */
689   __IO uint32_t P1CTCR2;         /*!< DCMIPP Pipe1 contrast control register 2                           Address offset: 0x8A4 */
690   __IO uint32_t P1CTCR3;         /*!< DCMIPP Pipe1 contrast control register 3                           Address offset: 0x8A8 */
691        uint32_t RESERVED26[21];  /*!< Reserved                                                           Address offset: 0x8AC-0x8FC */
692   __IO uint32_t P1FCTCR;         /*!< DCMIPP Pipe1 flow control configuration register                   Address offset: 0x900 */
693   __IO uint32_t P1CRSTR;         /*!< DCMIPP Pipe1 crop window start register                            Address offset: 0x904 */
694   __IO uint32_t P1CRSZR;         /*!< DCMIPP Pipe1 crop window size register                             Address offset: 0x908 */
695   __IO uint32_t P1DCCR;          /*!< DCMIPP Pipe1 decimation register                                   Address offset: 0x90C */
696   __IO uint32_t P1DSCR;          /*!< DCMIPP Pipe1 downsize configuration register                       Address offset: 0x910 */
697   __IO uint32_t P1DSRTIOR;       /*!< DCMIPP Pipe1 downsize ratio register                               Address offset: 0x914 */
698   __IO uint32_t P1DSSZR;         /*!< DCMIPP Pipe1 downsize destination size register                    Address offset: 0x918 */
699        uint32_t RESERVED28;      /*!< Reserved                                                           Address offset:  */
700   __IO uint32_t P1CMRICR;        /*!< DCMIPP Pipe1 common ROI configuration register                     Address offset: 0x920 */
701   __IO uint32_t P1RIxCR1;        /*!< DCMIPP Pipe1 ROIx configuration register 1                         Address offset: 0x924 + (x - 1) * 0x8, (x = 1 to 8) */
702   __IO uint32_t P1RIxCR2;        /*!< DCMIPP Pipe1 ROIx configuration register 2                         Address offset: 0x928 + (x - 1) * 0x8, (x = 1 to 8) */
703        uint32_t RESERVED29[17];      /*!< Reserved                                                       Address offset:  */
704   __IO uint32_t P1GMCR;          /*!< DCMIPP Pipe1 gamma configuration register                          Address offset: 0x970 */
705        uint32_t RESERVED30[3];   /*!< Reserved                                                           Address offset: 0x974-0x97C */
706   __IO uint32_t P1YUVCR;         /*!< DCMIPP Pipe1 YUVConv configuration register                        Address offset: 0x980 */
707   __IO uint32_t P1YUVRR1;        /*!< DCMIPP Pipe1 YUVConv red coefficient register 1                    Address offset: 0x984 */
708   __IO uint32_t P1YUVRR2;        /*!< DCMIPP Pipe1 YUVConv red coefficient register 2                    Address offset: 0x988 */
709   __IO uint32_t P1YUVGR1;        /*!< DCMIPP Pipe1 YUVConv green coefficient register 1                  Address offset: 0x98C */
710   __IO uint32_t P1YUVGR2;        /*!< DCMIPP Pipe1 YUVConv green coefficient register 2                  Address offset: 0x990 */
711   __IO uint32_t P1YUVBR1;        /*!< DCMIPP Pipe1 YUVConv blue coefficient register 1                   Address offset: 0x994 */
712   __IO uint32_t P1YUVBR2;        /*!< DCMIPP Pipe1 YUV blue coefficient register 2                       Address offset: 0x998 */
713        uint32_t RESERVED31[9];   /*!< Reserved                                                           Address offset: 0x99C-0x9BC */
714   __IO uint32_t P1PPCR;          /*!< DCMIPP Pipe1 pixel packer configuration register                   Address offset: 0x9C0 */
715   __IO uint32_t P1PPM0AR1;       /*!< DCMIPP Pipe1 pixel packer Memory0 address register 1               Address offset: 0x9C4 */
716   __IO uint32_t P1PPM0AR2;       /*!< DCMIPP Pipe1 pixel packer Memory0 address register 2               Address offset: 0x9C8 */
717   __IO uint32_t P1PPM0PR;        /*!< DCMIPP Pipe1 pixel packer Memory0 pitch register                   Address offset: 0x9CC */
718   __IO uint32_t P1STM0AR;        /*!< DCMIPP Pipe1 status Memory0 address register                       Address offset: 0x9D0 */
719   __IO uint32_t P1PPM1AR1;       /*!< DCMIPP Pipe1 pixel packer Memory1 address register 1               Address offset: 0x9D4 */
720   __IO uint32_t P1PPM1AR2;       /*!< DCMIPP Pipe1 pixel packer Memory1 address register 2               Address offset: 0x9D8 */
721   __IO uint32_t P1PPM1PR;        /*!< DCMIPP Pipe1 pixel packer Memory1 pitch register                   Address offset: 0x9DC */
722   __IO uint32_t P1STM1AR;        /*!< DCMIPP Pipe1 status Memory1 address register                       Address offset: 0x9E0 */
723   __IO uint32_t P1PPM2AR1;       /*!< DCMIPP Pipe1 pixel packer memory2 address register 1               Address offset: 0x9E4 */
724   __IO uint32_t P1PPM2AR2;       /*!< DCMIPP Pipe1 pixel packer memory2 address register 2               Address offset: 0x9E8 */
725   __IO uint32_t RESERVED34;      /*!< Reserved                                                           Address offset: 0x9EC */
726   __IO uint32_t P1STM2AR;        /*!< DCMIPP Pipe1 status Memory2 address register                       Address offset: 0x9F0 */
727   __IO uint32_t P1IER;           /*!< DCMIPP Pipe1 interrupt enable register                             Address offset: 0x9F4 */
728   __IO uint32_t P1SR;            /*!< DCMIPP Pipe1 status register                                       Address offset: 0x9F8 */
729   __IO uint32_t P1FCR;           /*!< DCMIPP Pipe1 interrupt clear register                              Address offset: 0x9FC */
730        uint32_t RESERVED35;      /*!< Reserved                                                           Address offset: 0xA00 */
731   __IO uint32_t P1CFSCR;         /*!< DCMIPP Pipe1 current flow selection configuration register         Address offset: 0xA04 */
732        uint32_t RESERVED36[7];   /*!< Reserved                                                           Address offset: 0xA08-0xA20 */
733   __IO uint32_t P1CBPRCR;        /*!< DCMIPP Pipe1 current bad pixel removal register                    Address offset: 0xA24 */
734        uint32_t RESERVED37[6];   /*!< Reserved                                                           Address offset: 0xA28-0xA3C */
735   __IO uint32_t P1CBLCCR;        /*!< DCMIPP Pipe1 current black level calibration control register      Address offset: 0xA40 */
736   __IO uint32_t P1CEXCR1;        /*!< DCMIPP Pipe1 current exposure control register 1                   Address offset: 0xA44 */
737   __IO uint32_t P1CEXCR2;        /*!< DCMIPP Pipe1 current exposure control register 2                   Address offset: 0xA48 */
738        uint32_t RESERVED38;      /*!< Reserved                                                           Address offset: 0xA4C */
739   __IO uint32_t P1CST1CR;        /*!< DCMIPP Pipe1 current statistics 1 control register                 Address offset: 0xA50 */
740   __IO uint32_t P1CST2CR;        /*!< DCMIPP Pipe1 current statistics 2 control register                 Address offset: 0xA54 */
741   __IO uint32_t P1CST3CR;        /*!< DCMIPP Pipe1 current statistics 3 control register                 Address offset: 0xA58 */
742   __IO uint32_t P1CSTSTR;        /*!< DCMIPP Pipe1 current statistics window start register              Address offset: 0xA5C */
743   __IO uint32_t P1CSTSZR;        /*!< DCMIPP Pipe1 current statistics window size register               Address offset: 0xA60 */
744        uint32_t RESERVED39[7];   /*!< Reserved                                                           Address offset: 0xA64-0xA7C */
745   __IO uint32_t P1CCCCR;         /*!< DCMIPP Pipe1 current ColorConv configuration register              Address offset: 0xA80 */
746   __IO uint32_t P1CCCRR1;        /*!< DCMIPP Pipe1 current ColorConv red coefficient register 1          Address offset: 0xA84 */
747   __IO uint32_t P1CCCRR2;        /*!< DCMIPP Pipe1 current ColorConv red coefficient register 2          Address offset: 0xA88 */
748   __IO uint32_t P1CCCGR1;        /*!< DCMIPP Pipe1 current ColorConv green coefficient register 1        Address offset: 0xA8C */
749   __IO uint32_t P1CCCGR2;        /*!< DCMIPP Pipe1 current ColorConv green coefficient register 2        Address offset: 0xA90 */
750   __IO uint32_t P1CCCBR1;        /*!< DCMIPP Pipe1 current ColorConv blue coefficient register 1         Address offset: 0xA94 */
751   __IO uint32_t P1CCCBR2;        /*!< DCMIPP Pipe1 current ColorConv blue coefficient register 2         Address offset: 0xA98 */
752        uint32_t RESERVED40;      /*!< Reserved                                                           Address offset: 0xA9C */
753   __IO uint32_t P1CCTCR1;        /*!< DCMIPP Pipe1 current contrast control register 1                   Address offset: 0xAA0 */
754   __IO uint32_t P1CCTCR2;        /*!< DCMIPP Pipe1 current contrast control register 2                   Address offset: 0xAA4 */
755   __IO uint32_t P1CCTCR3;        /*!< DCMIPP Pipe1 current contrast control register 3                   Address offset: 0xAA8 */
756        uint32_t RESERVED41[21];  /*!< Reserved                                                           Address offset: 0xAAC-0xAFC */
757   __IO uint32_t P1CFCTCR;        /*!< DCMIPP Pipe1 current flow control configuration register           Address offset: 0xB00 */
758   __IO uint32_t P1CCRSTR;        /*!< DCMIPP Pipe1 current crop window start register                    Address offset: 0xB04 */
759   __IO uint32_t P1CCRSZR;        /*!< DCMIPP Pipe1 current crop window size register                     Address offset: 0xB08 */
760   __IO uint32_t P1CDCCR;         /*!< DCMIPP Pipe1 current decimation register                           Address offset: 0xB0C */
761   __IO uint32_t P1CDSCR;         /*!< DCMIPP Pipe1 current downsize configuration register               Address offset: 0xB10 */
762   __IO uint32_t P1CDSRTIOR;      /*!< DCMIPP Pipe1 current downsize ratio register                       Address offset: 0xB14 */
763   __IO uint32_t P1CDSSZR;        /*!< DCMIPP Pipe1 current downsize destination size register            Address offset: 0xB18 */
764        uint32_t RESERVED43;      /*!< Reserved                                                           Address offset: 0xB1C */
765        uint32_t P1CCMRICR;       /*!< DCMIPP Pipe1 current common ROI configuration register             Address offset: 0xB20 */
766   __IO uint32_t P1CRIxCR1;       /*!< DCMIPP Pipe1 current ROIx configuration register 1                 Address offset: 0xB24 + 0x8 * (x - 1), (x = 1 to 8) */
767   __IO uint32_t P1CRIxCR2;       /*!< DCMIPP Pipe1 current ROIx configuration register 2                 Address offset: 0xB28 + 0x8 * (x - 1), (x = 1 to 8) */
768   uint32_t RESERVED44[37];       /*!< Reserved                                                           Address offset: 0xB64-0xBBC */
769   __IO uint32_t P1CPPCR;         /*!< DCMIPP Pipe1 current pixel packer configuration register           Address offset: 0xBC0 */
770   __IO uint32_t P1CPPM0AR1;      /*!< DCMIPP Pipe1 current pixel packer Memory0 address register 1       Address offset: 0xBC4 */
771   __IO uint32_t P1CPPM0AR2;      /*!< DCMIPP Pipe1 current pixel packer Memory0 address register 1       Address offset: 0xBC8 */
772   __IO uint32_t P1CPPM0PR;       /*!< DCMIPP Pipe1 current pixel packer Memory0 pitch register           Address offset: 0xBCC */
773        uint32_t RESERVED45;      /*!< Reserved                                                           Address offset: 0xBD0 */
774   __IO uint32_t P1CPPM1AR1;      /*!< DCMIPP Pipe1 current pixel packer Memory1 address register 1       Address offset: 0xBD4 */
775   __IO uint32_t P1CPPM1AR2;      /*!< DCMIPP Pipe1 current pixel packer Memory1 address register 2       Address offset: 0xBD8 */
776   __IO uint32_t P1CPPM1PR;       /*!< DCMIPP Pipe1 current pixel packer Memory1 pitch register           Address offset: 0xBDC */
777        uint32_t RESERVED47;      /*!< Reserved                                                           Address offset: 0xBE0 */
778   __IO uint32_t P1CPPM2AR1;      /*!< DCMIPP Pipe1 current pixel packer memory2 address register 1       Address offset: 0xBE4 */
779   __IO uint32_t P1CPPM2AR2;      /*!< DCMIPP Pipe1 current pixel packer Memory2 address register 2       Address offset: 0xBE8 */
780        uint32_t RESERVED48[6];   /*!< Reserved                                                           Address offset: 0xBE8-0xBFC */
781   __IO uint32_t P2FSCR;          /*!< DCMIPP Pipe2 flow selection configuration register                 Address offset: 0xC04 */
782        uint32_t RESERVED49[62];  /*!< Reserved                                                           Address offset: 0xC08-0xCFC */
783   __IO uint32_t P2FCTCR;         /*!< DCMIPP Pipe2 flow control configuration register                   Address offset: 0xD00 */
784   __IO uint32_t P2CRSTR;         /*!< DCMIPP Pipe2 crop window start register                            Address offset: 0xD04 */
785   __IO uint32_t P2CRSZR;         /*!< DCMIPP Pipe2 crop window size register                             Address offset: 0xD08 */
786   __IO uint32_t P2DCCR;          /*!< DCMIPP Pipe2 decimation register                                   Address offset: 0xD0C */
787   __IO uint32_t P2DSCR;          /*!< DCMIPP Pipe2 downsize configuration register                       Address offset: 0xD10 */
788   __IO uint32_t P2DSRTIOR;       /*!< DCMIPP Pipe2 downsize ratio register                               Address offset: 0xD14 */
789   __IO uint32_t P2DSSZR;         /*!< DCMIPP Pipe2 downsize destination size register                    Address offset: 0xD18 */
790        uint32_t RESERVED51;      /*!< Reserved                                                           Address offset:  0xD1C */
791   __IO uint32_t P2CMRICR;        /*!< DCMIPP Pipe2 common ROI configuration register                     Address offset:  0xD20 */
792   __IO uint32_t P2RIxCR1;        /*!< DCMIPP Pipe2 ROIx configuration register 1                         Address offset: 0xD24 + (x - 1) * 0x8, (x = 1 to 8) */
793   __IO uint32_t P2RIxCR2;        /*!< DCMIPP Pipe2 ROIx configuration register 2                         Address offset: 0xD28 + (x - 1) * 0x8, (x = 1 to 8) */
794        uint32_t RESERVED53[17];  /*!< Reserved                                                           Address offset: */
795   __IO uint32_t P2GMCR;          /*!< DCMIPP Pipe2 gamma configuration register                          Address offset: 0xD70 */
796        uint32_t RESERVED54[19];  /*!< Reserved                                                           Address offset: 0xD74-0xDBC */
797   __IO uint32_t P2PPCR;          /*!< DCMIPP Pipe2 pixel packer configuration register                   Address offset: 0xDC0 */
798   __IO uint32_t P2PPM0AR1;       /*!< DCMIPP Pipe2 pixel packer Memory0 address register 1               Address offset: 0xDC4 */
799   __IO uint32_t P2PPM0AR2;       /*!< DCMIPP Pipe2 pixel packer Memory0 address register 2               Address offset: 0xDC8 */
800   __IO uint32_t P2PPM0PR;        /*!< DCMIPP Pipe2 pixel packer Memory0 pitch register                   Address offset: 0xDCC */
801   __IO uint32_t P2STM0AR;        /*!< DCMIPP Pipe2 status Memory0 address register                       Address offset: 0xDD0 */
802        uint32_t RESERVED55[8];   /*!< Reserved                                                           Address offset: 0xDD4-0xDF0 */
803   __IO uint32_t P2IER;           /*!< DCMIPP Pipe2 interrupt enable register                             Address offset: 0xDF4 */
804   __IO uint32_t P2SR;            /*!< DCMIPP Pipe2 status register                                       Address offset: 0xDF8 */
805   __IO uint32_t P2FCR;           /*!< DCMIPP Pipe2 interrupt clear register                              Address offset: 0xDFC */
806        uint32_t RESERVED56;      /*!< Reserved                                                           Address offset: 0xE00 */
807   __IO uint32_t P2CFSCR;         /*!< DCMIPP Pipe2 current flow selection configuration register         Address offset: 0xE04 */
808        uint32_t RESERVED57[62];  /*!< Reserved                                                           Address offset: 0xE08-0xEFC */
809   __IO uint32_t P2CFCTCR;        /*!< DCMIPP Pipe2 current flow control configuration register           Address offset: 0xF00 */
810   __IO uint32_t P2CCRSTR;        /*!< DCMIPP Pipe2 current crop window start register                    Address offset: 0xF04 */
811   __IO uint32_t P2CCRSZR;        /*!< DCMIPP Pipe2 current crop window size register                     Address offset: 0xF08 */
812   __IO uint32_t P2CDCCR;         /*!< DCMIPP Pipe2 current decimation register                           Address offset: 0xF0C */
813   __IO uint32_t P2CDSCR;         /*!< DCMIPP Pipe2 current downsize configuration register               Address offset: 0xF10 */
814   __IO uint32_t P2CDSRTIOR;      /*!< DCMIPP Pipe2 current downsize ratio register                       Address offset: 0xF14 */
815   __IO uint32_t P2CDSSZR;        /*!< DCMIPP Pipe2 current downsize destination size register            Address offset: 0xF18 */
816   __IO uint32_t RESERVED59[2];   /*!< Reserved                                                           Address offset: 0xF1C-0xF20 */
817   __IO uint32_t P2CRIxCR1;       /*!< Pipe2 current ROIx configuration register 1                        Address offset: 0xF24 + (x - 1) * 0x8, (x = 1 to 8)*/
818   __IO uint32_t P2CRIxCR2;       /*!< Pipe2 current ROIx configuration register 2                        Address offset: 0xF28 + (x - 1) * 0x8, (x = 1 to 8)*/
819        uint32_t RESERVED60[37];  /*!< Reserved                                                           Address offset: 0xF64-0xFBC */
820   __IO uint32_t P2CPPCR;         /*!< DCMIPP Pipe2 current pixel packer configuration register           Address offset: 0xFC0 */
821   __IO uint32_t P2CPPM0AR1;      /*!< DCMIPP Pipe2 current pixel packer Memory0 address register 1       Address offset: 0xFC4 */
822   __IO uint32_t P2CPPM0AR2;      /*!< DCMIPP Pipe2 current pixel packer Memory0 address register 2       Address offset: 0xFC8 */
823   __IO uint32_t P2CPPM0PR;       /*!< DCMIPP Pipe2 current pixel packer Memory0 pitch register           Address offset: 0xFCC */
824        uint32_t RESERVED61[7];   /*!< Reserved                                                           Address offset: 0xFD0-0xFE8 */
825   __IO uint32_t HWCFGR2;         /*!< DCMIPP hardware configuration register 2                           Address offset: 0xFEC */
826   __IO uint32_t HWCFGR1;         /*!< DCMIPP hardware configuration register 1                           Address offset: 0xFF0 */
827   __IO uint32_t VERR;            /*!< DCMIPP version register                                            Address offset: 0xFF4 */
828   __IO uint32_t IPIDR;           /*!< DCMIPP identification register                                     Address offset: 0xFF8 */
829   __IO uint32_t SIDR;            /*!< DCMIPP size identification register                                Address offset: 0xFFC */
830 } DCMIPP_TypeDef;
831 
832 /**
833   * @ brief Delay Block
834   */
835 typedef struct
836 {
837   __IO uint32_t CR;   /*!< Delay Block Control Register,       Address offset: 0x00 */
838   __IO uint32_t CFGR; /*!< Delay Block Configuration Register, Address offset: 0x04 */
839 } DLYB_TypeDef;
840 
841 /**
842   * @brief DMA Controller
843   */
844 
845 typedef struct
846 {
847   __IO uint32_t SECCFGR;      /*!< DMA secure configuration register,               Address offset: 0x00  */
848   __IO uint32_t PRIVCFGR;     /*!< DMA privileged configuration register,           Address offset: 0x04 */
849   __IO uint32_t RCFGLOCKR;    /*!< DMA configuration lock register,                 Address offset: 0x08 */
850   __IO uint32_t MISR;         /*!< DMA non secure masked interrupt status register, Address offset: 0x0C  */
851   __IO uint32_t SMISR;        /*!< DMA secure masked interrupt status register,     Address offset: 0x10  */
852 } DMA_TypeDef;
853 
854 typedef struct
855 {
856   __IO uint32_t CLBAR;         /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */
857   __IO uint32_t CCIDCFGR;      /*!< DMA channel x CID register,                      Address offset: 0x54 + (x * 0x80) */
858        uint32_t RESERVED1[1];  /*!< Reserved 1,                                      Address offset: 0x58 + (x * 0x80) */
859   __IO uint32_t CFCR;          /*!< DMA channel x flag clear register,               Address offset: 0x5C + (x * 0x80) */
860   __IO uint32_t CSR;           /*!< DMA channel x flag status register,              Address offset: 0x60 + (x * 0x80) */
861   __IO uint32_t CCR;           /*!< DMA channel x control register,                  Address offset: 0x64 + (x * 0x80) */
862        uint32_t RESERVED2[10]; /*!< Reserved 2,                                      Address offset: 0x68 -- 0x8C + (x * 0x80) */
863   __IO uint32_t CTR1;          /*!< DMA channel x transfer register 1,               Address offset: 0x90 + (x * 0x80) */
864   __IO uint32_t CTR2;          /*!< DMA channel x transfer register 2,               Address offset: 0x94 + (x * 0x80) */
865   __IO uint32_t CBR1;          /*!< DMA channel x block register 1,                  Address offset: 0x98 + (x * 0x80) */
866   __IO uint32_t CSAR;          /*!< DMA channel x source address register,           Address offset: 0x9C + (x * 0x80) */
867   __IO uint32_t CDAR;          /*!< DMA channel x destination address register,      Address offset: 0xA0 + (x * 0x80) */
868   __IO uint32_t CTR3;          /*!< DMA channel x transfer register 3,               Address offset: 0xA4 + (x * 0x80) */
869   __IO uint32_t CBR2;          /*!< DMA channel x block register 2,                  Address offset: 0xA8 + (x * 0x80) */
870        uint32_t RESERVED3[8];  /*!< Reserved 3,                                      Address offset: 0xAC -- 0xC8 + (x * 0x80) */
871   __IO uint32_t CLLR;          /*!< DMA channel x linked-list address register,      Address offset: 0xCC + (x * 0x80) */
872 } DMA_Channel_TypeDef;
873 
874 /**
875   * @brief DMA2D Controller
876   */
877 typedef struct
878 {
879   __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */
880   __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */
881   __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */
882   __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */
883   __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */
884   __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */
885   __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */
886   __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */
887   __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */
888   __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */
889   __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */
890   __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */
891   __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */
892   __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */
893   __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */
894   __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */
895   __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */
896   __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */
897   __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */
898   __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */
899   uint32_t      RESERVED[236]; /*!< Reserved,                                 Address offset: 0x50-0x3FF */
900   __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                    Address offset:0x400-0x7FF */
901   __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                    Address offset:0x800-0xBFF */
902 } DMA2D_TypeDef;
903 
904 /**
905   * @brief DTS Controller
906   */
907 typedef struct
908 {
909   uint32_t      RESERVED1[4];    /*!< Reserved,                                 Address offset: 0x00-0x0F */
910   __IO uint32_t PVTREG_LOCKR;    /*!< DTS PVT Register Lock Register,           Address offset: 0x10 */
911   __IO uint32_t PVTLOCK_SR;      /*!< DTS PVT Lock Status Register,             Address offset: 0x14 */
912   uint32_t      RESERVED2[2];    /*!< Reserved,                                 Address offset: 0x18-0x1F */
913   __IO uint32_t PVTTMR_CR;       /*!< DTS PVT Timer Control Register,           Address offset: 0x20 */
914   __IO uint32_t PVTTMR_SR;       /*!< DTS PVT Timer Status Register,            Address offset: 0x24 */
915   uint32_t      RESERVED3[6];    /*!< Reserved,                                 Address offset: 0x28-0x3F */
916   __IO uint32_t PVT_IER;         /*!< DTS PVT IRQ Enable Register,              Address offset: 0x40 */
917   uint32_t      RESERVED4[3];    /*!< Reserved,                                 Address offset: 0x44-0x4F */
918   __IO uint32_t PVTIRQTRMASKR;   /*!< DTS PVT IRQ Timer Mask Register,          Address offset: 0x50 */
919   __IO uint32_t TS_MR;           /*!< DTS PVT IRQ TS Mask Register,             Address offset: 0x54 */
920   uint32_t      RESERVED5[2];    /*!< Reserved,                                 Address offset: 0x58-0x5F */
921   __IO uint32_t PVTTR_SR;        /*!< DTS PVT IRQ Timer Status Register,        Address offset: 0x60 */
922   __IO uint32_t TS_ISR;          /*!< DTS PVT IRQ TS Status Register,           Address offset: 0x64 */
923   uint32_t      RESERVED6[2];    /*!< Reserved,                                 Address offset: 0x68-0x6F */
924   __IO uint32_t PVTTMRRAW_ISR;   /*!< DTS PVT IRQ Timer Raw Status Register,    Address offset: 0x70 */
925   __IO uint32_t TSRAW_ISR;       /*!< DTS PVT IRQ TS Raw Status Register,       Address offset: 0x74 */
926   uint32_t      RESERVED7[2];    /*!< Reserved,                                 Address offset: 0x78-0x7F */
927   __IO uint32_t TSCCLKSYNTHR;    /*!< DTS TSC Clock Synthesizer Register,       Address offset: 0x80 */
928   __IO uint32_t TSCSDIFDISABLER; /*!< DTS TSC SDIF Interface Disable Register,  Address offset: 0x84 */
929   __IO uint32_t TSCSDIF_SR;      /*!< DTS TSC SDIF Status Register,             Address offset: 0x88 */
930   __IO uint32_t TSCSDIF_CR;      /*!< DTS TSC SDIF Register,                    Address offset: 0x8C */
931   __IO uint32_t TSCSDIFHALTR;    /*!< DTS TSC SDIF Halt Register,               Address offset: 0x90 */
932   __IO uint32_t TSCSDIF_CFGR;    /*!< DTS TSC SDIF Control Register,            Address offset: 0x94 */
933   uint32_t      RESERVED8[2];    /*!< Reserved,                                 Address offset: 0x98-0x9F */
934   __IO uint32_t TSCSMPL_CR;      /*!< DTS TSC Sample Control Register,          Address offset: 0xA0 */
935   __IO uint32_t TSCSDIFSMPLCLRR; /*!< DTS TSC Sample Clear Register,            Address offset: 0xA4 */
936   __IO uint32_t TSCSMPLCNTR;     /*!< DTS TSC Sample Count Register,            Address offset: 0xA8 */
937 } DTS_TypeDef;
938 
939 /**
940   * @brief DTS Sensor Controller
941   */
942 typedef struct
943 {
944   __IO uint32_t TS_IER;          /*!< DTS TSx IRQ Enable Register,              Address offset: 0xC0 + 0x40 * x, (x = 0 to 1) */
945   __IO uint32_t TS_ISR;          /*!< DTS TSx IRQ Status Register,              Address offset: 0xC4 + 0x40 * x, (x = 0 to 1) */
946   __IO uint32_t TS_ICR;          /*!< DTS TSx IRQ Clear Register,               Address offset: 0xC8 + 0x40 * x, (x = 0 to 1) */
947   __IO uint32_t TSIRQTESTR;      /*!< DTS TSx IRQ Test Register,                Address offset: 0xCC + 0x40 * x, (x = 0 to 1) */
948   __IO uint32_t TSSDIFRDATAR;    /*!< DTS TSx SDIF RDATA Register,              Address offset: 0xD0 + 0x40 * x, (x = 0 to 1) */
949   __IO uint32_t TSSDIFDONER;     /*!< DTS TSx SDIF Done Register,               Address offset: 0xD4 + 0x40 * x, (x = 0 to 1) */
950   __IO uint32_t TSSDIFDATAR;     /*!< DTS TSx SDIF Data Register,               Address offset: 0xD8 + 0x40 * x, (x = 0 to 1) */
951   uint32_t      RESERVED1[1];    /*!< Reserved,                                 Address offset: 0xDC + 0x40 * x, (x = 0 to 1) */
952   __IO uint32_t TSALARMA_CFGR;   /*!< DTS TSx Alarm A Configuration Register,   Address offset: 0xE0 + 0x40 * x, (x = 0 to 1) */
953   __IO uint32_t TSALARMB_CFGR;   /*!< DTS TSx Alarm B Configuration Register,   Address offset: 0xE4 + 0x40 * x, (x = 0 to 1) */
954   __IO uint32_t TSHLSAMPLER;     /*!< DTS TSx High/Low Sample Register,         Address offset: 0xE8 + 0x40 * x, (x = 0 to 1) */
955   __IO uint32_t TSHILORESETR;    /*!< DTS TSx High/Low Reset Register,          Address offset: 0xEC + 0x40 * x, (x = 0 to 1) */
956 } DTS_SensorTypeDef;
957 
958 /**
959   * @brief Ethernet MAC
960   */
961 typedef struct
962 {
963   __IO uint32_t MACCR;               /*!< Operating mode configuration register,                        Address offset: 0x00 */
964   __IO uint32_t MACECR;              /*!< Extended operating mode configuration register,               Address offset: 0x04 */
965   __IO uint32_t MACPFR;              /*!< Packet filtering control register             ,               Address offset: 0x08 */
966   __IO uint32_t MACWTR;              /*!< Watchdog timeout register,                                    Address offset: 0x0C */
967   __IO uint32_t MACHT0R;             /*!< Hash Table 0 register,                                        Address offset: 0x10 */
968   __IO uint32_t MACHT1R;             /*!< Hash Table 1 register,                                        Address offset: 0x14 */
969   uint32_t      RESERVED1[14];
970   __IO uint32_t MACVTCR;             /*!< VLAN tag Control register,                                    Address offset: 0x50 */
971   __IO uint32_t MACVTDR;             /*!< VLAN tag data register,                                       Address offset: 0x54 */
972   __IO uint32_t MACVHTR;             /*!< VLAN Hash table register,                                     Address offset: 0x58 */
973   uint32_t      RESERVED2;
974   __IO uint32_t MACVIR;              /*!< VLAN inclusion register,                                      Address offset: 0x60 */
975   __IO uint32_t MACIVIR;             /*!< Inner VLAN inclusion register,                                Address offset: 0x64 */
976   uint32_t      RESERVED3[2];
977   __IO uint32_t MACQ0TXFCR;          /*!< Tx Queue 0 flow control register,                             Address offset: 0x70 */
978   uint32_t      RESERVED4[7];
979   __IO uint32_t MACRXFCR;            /*!< Rx flow control register,                                     Address offset: 0x90 */
980   __IO uint32_t MACRXQCR;            /*!< Rx Queue control register,                                    Address offset: 0x94 */
981   uint32_t      RESERVED5[2];
982   __IO uint32_t MACRXQC0R;           /*!< Rx queue control 0 register,                                  Address offset: 0xA0 */
983   __IO uint32_t MACRXQC1R;           /*!< Rx queue control 1 register,                                  Address offset: 0xA4 */
984   __IO uint32_t MACRXQC2R;           /*!< Rx queue control 2 register,                                  Address offset: 0xA8 */
985   uint32_t      RESERVED6;
986   __IO uint32_t MACISR;              /*!< Interrupt status register,                                    Address offset: 0xB0 */
987   __IO uint32_t MACIER;              /*!< Interrupt enable register,                                    Address offset: 0xB4 */
988   __IO uint32_t MACRXTXSR;           /*!< Rx Tx status register,                                        Address offset: 0xB8 */
989   uint32_t      RESERVED7;
990   __IO uint32_t MACPCSR;             /*!< PMT control status register,                                  Address offset: 0xC0 */
991   __IO uint32_t MACRWKPFR;           /*!< Remote wakeup packet filter register,                         Address offset: 0xC4 */
992   uint32_t      RESERVED8[2];
993   __IO uint32_t MACLCSR;             /*!< LPI control and status register,                              Address offset: 0xD0 */
994   __IO uint32_t MACLTCR;             /*!< LPI timers control register,                                  Address offset: 0xD4 */
995   __IO uint32_t MACLETR;             /*!< LPI entry timer register,                                     Address offset: 0xD8 */
996   __IO uint32_t MAC1USTCR;           /*!< One-microsecond-tick counter register,                        Address offset: 0xDC */
997   uint32_t      RESERVED9[6];
998   __IO uint32_t MACPHYCSR;           /*!< PHYIF control status register,                                Address offset: 0xF8 */
999   uint32_t      RESERVED10[5];
1000   __IO uint32_t MACVR;               /*!< Version register,                                             Address offset: 0x110 */
1001   __IO uint32_t MACDR;               /*!< Debug register,                                               Address offset: 0x114 */
1002   uint32_t      RESERVED11;
1003   __IO uint32_t MACHWF0R;            /*!< HW feature 0 register,                                        Address offset: 0x11C */
1004   __IO uint32_t MACHWF1R;            /*!< HW feature 1 register,                                        Address offset: 0x120 */
1005   __IO uint32_t MACHWF2R;            /*!< HW feature 2 register,                                        Address offset: 0x124 */
1006   __IO uint32_t MACHWF3R;            /*!< HW feature 3 register,                                        Address offset: 0x128 */
1007   uint32_t      RESERVED12[53];
1008   __IO uint32_t MACMDIOAR;           /*!< MDIO address register,                                        Address offset: 0x200 */
1009   __IO uint32_t MACMDIODR;           /*!< MDIO data register,                                           Address offset: 0x204 */
1010   uint32_t      RESERVED13[2];
1011   __IO uint32_t MACARPAR;            /*!< ARP address register,                                         Address offset: 0x210 */
1012   uint32_t      RESERVED14[7];
1013   __IO uint32_t MACCSRSWCR;          /*!< CSR software control register,                                Address offset: 0x230 */
1014   __IO uint32_t MACFPECSR;           /*!< FPE control and status register,                              Address offset: 0x234 */
1015    uint32_t     RESERVED15[2];
1016   __IO uint32_t MACPRSTIMR;          /*!< MAC presentation time register,                               Address offset: 0x0240 */
1017   __IO uint32_t MACPRSTIMUR;         /*!< MAC presentation time update register,                        Address offset: 0x0244 */
1018    uint32_t     RESERVED16[46];
1019   __IO uint32_t MACA0HR;             /*!< MAC Address 0 high register,                                  Address offset: 0x0300 */
1020   __IO uint32_t MACA0LR;             /*!< MAC Address 0 low register,                                   Address offset: 0x0304 */
1021   __IO uint32_t MACA1HR;             /*!< MAC Address 1 high register,                                  Address offset: 0x0308 */
1022   __IO uint32_t MACA1LR;             /*!< MAC Address 1 low register,                                   Address offset: 0x030C */
1023   __IO uint32_t MACA2HR;             /*!< MAC Address 2 high register,                                  Address offset: 0x0310 */
1024   __IO uint32_t MACA2LR;             /*!< MAC Address 2 low register,                                   Address offset: 0x0314 */
1025   __IO uint32_t MACA3HR;             /*!< MAC Address 3 high register,                                  Address offset: 0x0318 */
1026   __IO uint32_t MACA3LR;             /*!< MAC Address 3 low register,                                   Address offset: 0x031C */
1027   uint32_t      RESERVED17[248];
1028   __IO uint32_t MMCCR;               /*!< MMC control register,                                         Address offset: 0x0700 */
1029   __IO uint32_t MMCRIR;              /*!< MMC Rx interrupt register,                                    Address offset: 0x0704 */
1030   __IO uint32_t MMCTIR;              /*!< MMC Tx interrupt register,                                    Address offset: 0x0708 */
1031   __IO uint32_t MMCRIMR;             /*!< MMC Rx interrupt mask register,                               Address offset: 0x070C */
1032   __IO uint32_t MMCTIMR;             /*!< MMC Tx interrupt mask register,                               Address offset: 0x0710 */
1033   uint32_t      RESERVED18[14];
1034   __IO uint32_t MMCTSCGPR;           /*!< Tx single collision good packets register,                    Address offset: 0x074C */
1035   __IO uint32_t MMCTMCGPR;           /*!< Tx multiple collision good packets register,                  Address offset: 0x0750 */
1036   uint32_t      RESERVED19[5];
1037   __IO uint32_t MMCTPCGR;            /*!< Tx packet count good register,                                Address offset: 0x0768 */
1038   uint32_t      RESERVED20[10];
1039   __IO uint32_t MMCRCRCEPR;          /*!< Rx CRC error packets register,                                Address offset: 0x0794 */
1040   __IO uint32_t MMCRAEPR;            /*!< Rx alignment error packets register,                          Address offset: 0x0798 */
1041   uint32_t      RESERVED21[10];
1042   __IO uint32_t MMCRUPGR;            /*!< Rx unicast packets good register,                             Address offset: 0x07C4 */
1043   uint32_t      RESERVED22[9];
1044   __IO uint32_t MMCTLPIMSTR;         /*!< Tx LPI microsecond timer register,                            Address offset: 0x07EC */
1045   __IO uint32_t MMCTLPITCR;          /*!< Tx LPI transition counter register,                           Address offset: 0x07F0 */
1046   __IO uint32_t MMCRLPIMSTR;         /*!< Rx LPI microsecond counter register,                          Address offset: 0x07F4 */
1047   __IO uint32_t MMCRLPITCR;          /*!< Rx LPI transition counter register,                           Address offset: 0x07F8 */
1048   uint32_t      RESERVED23[41];
1049   __IO uint32_t MMCFPETISR;          /*!< MMC FPE Tx interrupt status register,                         Address offset: 0x08A0 */
1050   __IO uint32_t MMCFPETIMR;          /*!< MMC FPE Tx interrupt mask register,                           Address offset: 0x08A4 */
1051   __IO uint32_t MMCFPETFCR;          /*!< MMC FPE Tx fragment counter register,       -                 Address offset: 0x08A8 */
1052   __IO uint32_t MMCTHRCR;            /*!< MMC Tx hold request counter register,                         Address offset: 0x08AC */
1053   uint32_t      RESERVED24[4];
1054   __IO uint32_t MMCFPERISR;          /*!< MMC FPE Rx interrupt status register,                         Address offset: 0x08C0 */
1055   __IO uint32_t MMCFPERIMR;          /*!< MMC FPE Rx interrupt mask register,                           Address offset: 0x08C4 */
1056   __IO uint32_t MMCRPAER;            /*!< MMC Rx packet assembly error register,                        Address offset: 0x08C8 */
1057   __IO uint32_t MMCRPSMDER;          /*!< MMC Rx packet SMD error register,                             Address offset: 0x08CC */
1058   __IO uint32_t MMCRPAOKR;           /*!< MMC Rx packet assembly OK register,                           Address offset: 0x08D0 */
1059   __IO uint32_t MMCFPERFCR;          /*!< MMC Rx FPE fragments counter register,                        Address offset: 0x08D4 */
1060   uint32_t      RESERVED25[10];
1061   __IO uint32_t MACL3L4C0R;          /*!< L3 and L4 control 0 register,                                 Address offset: 0x0900 */
1062   __IO uint32_t MACL4A0R;            /*!< Layer4 Address filter 0 register,                             Address offset: 0x0904 */
1063   uint32_t      RESERVED26[2];
1064   __IO uint32_t MACL3A0R0R;           /*!< Layer3 Address 0 filter 0 register,                           Address offset: 0x0910 */
1065   __IO uint32_t MACL3A1R0R;           /*!< Layer3 Address 1 filter 0 register,                           Address offset: 0x0914 */
1066   __IO uint32_t MACL3A2R0R;           /*!< Layer3 Address 2 filter 0 register,                           Address offset: 0x0918 */
1067   __IO uint32_t MACL3A3R0R;           /*!< Layer3 Address 3 filter 0 register,                           Address offset: 0x091C */
1068   uint32_t      RESERVED27[4];
1069   __IO uint32_t MACL3L4C1R;          /*!< L3 and L4 control 1 register,                                 Address offset: 0x0930 */
1070   __IO uint32_t MACL4A1R;            /*!< Layer 4 address filter 1 register,                            Address offset: 0x0934 */
1071   uint32_t      RESERVED28[2];
1072   __IO uint32_t MACL3A01R;           /*!< Layer3 address 0 filter 1 Register,                           Address offset: 0x0940 */
1073   __IO uint32_t MACL3A11R;           /*!< Layer3 address 1 filter 1 register,                           Address offset: 0x0944 */
1074   __IO uint32_t MACL3A21R;           /*!< Layer3 address 2 filter 1 Register,                           Address offset: 0x0948 */
1075   __IO uint32_t MACL3A31R;           /*!< Layer3 address 3 filter 1 register,                           Address offset: 0x094C */
1076   uint32_t      RESERVED29[72];
1077   __IO uint32_t MACIACR;             /*!< MAC Indirect Access Control register,                         Address offset: 0x0A70 */
1078   __IO uint32_t MACTMRQR;            /*!< MAC type-based Rx Queue mapping register,                     Address offset: 0x0A74 */
1079   uint32_t      RESERVED30[34];
1080   __IO uint32_t MACTSCR;             /*!< Timestamp control Register,                                   Address offset: 0x0B00 */
1081   __IO uint32_t MACSSIR;             /*!< Subsecond increment register,                                 Address offset: 0x0B04 */
1082   __IO uint32_t MACSTSR;             /*!< System time seconds register,                                 Address offset: 0x0B08 */
1083   __IO uint32_t MACSTNR;             /*!< System time nanoseconds register,                             Address offset: 0x0B0C */
1084   __IO uint32_t MACSTSUR;            /*!< System time seconds update register,                          Address offset: 0x0B10 */
1085   __IO uint32_t MACSTNUR;            /*!< System time nanoseconds update register,                      Address offset: 0x0B14 */
1086   __IO uint32_t MACTSAR;             /*!< Timestamp addend register,                                    Address offset: 0x0B18 */
1087   uint32_t      RESERVED31;
1088   __IO uint32_t MACTSSR;             /*!< Timestamp status register,                                    Address offset: 0x0B20 */
1089   uint32_t      RESERVED32[3];
1090   __IO uint32_t MACTXTSSNR;          /*!< Tx timestamp status nanoseconds register,                     Address offset: 0x0B30 */
1091   __IO uint32_t MACTXTSSSR;          /*!< Tx timestamp status seconds register,                         Address offset: 0x0B34 */
1092   uint32_t      RESERVED33[2];
1093   __IO uint32_t MACACR;              /*!< Auxiliary control register,                                   Address offset: 0x0B40 */
1094   uint32_t      RESERVED34;
1095   __IO uint32_t MACATSNR;            /*!< Auxiliary timestamp nanoseconds register,                     Address offset: 0x0B48 */
1096   __IO uint32_t MACATSSR;            /*!< Auxiliary timestamp seconds register,                         Address offset: 0x0B4C */
1097   __IO uint32_t MACTSIACR;           /*!< Timestamp Ingress asymmetric correction register,             Address offset: 0x0B50 */
1098   __IO uint32_t MACTSEACR;           /*!< Timestamp Egress asymmetric correction register,              Address offset: 0x0B54 */
1099   __IO uint32_t MACTSICNR;           /*!< Timestamp Ingress correction nanosecond register,             Address offset: 0x0B58 */
1100   __IO uint32_t MACTSECNR;           /*!< Timestamp Egress correction nanosecond register,              Address offset: 0x0B5C */
1101   uint32_t      RESERVED35[2];
1102   __IO uint32_t MACTSILR;            /*!< Timestamp Ingress Latency register,                           Address offset: 0x0B68 */
1103   __IO uint32_t MACTSELR;            /*!< Timestamp Egress Latency register,                            Address offset: 0x0B6C */
1104   __IO uint32_t MACPPSCR;            /*!< PPS control register,                                         Address offset: 0x0B70 */
1105   uint32_t      RESERVED36[3];
1106   __IO uint32_t MACPPSTTS0R;         /*!< PPS 0 target time seconds register,                           Address offset: 0x0B80 */
1107   __IO uint32_t MACPPSTTN0R;         /*!< PPS 0 target time nanoseconds register,                       Address offset: 0x0B84 */
1108   __IO uint32_t MACPPSI0R;           /*!< PPS 0 interval register,                                      Address offset: 0x0B88 */
1109   __IO uint32_t MACPPSW0R;           /*!< PPS 0 width register,                                         Address offset: 0x0B8C */
1110   __IO uint32_t MACPPSTTS1R;         /*!< PPS 1 target time seconds register,                           Address offset: 0x0B90 */
1111   __IO uint32_t MACPPSTTN1R;         /*!< PPS 1 target time nanoseconds register,                       Address offset: 0x0B94 */
1112   __IO uint32_t MACPPSI1R;           /*!< PPS 1 interval register,                                      Address offset: 0x0B98 */
1113   __IO uint32_t MACPPSW1R;           /*!< PPS 1 width register,                                         Address offset: 0x0B9C */
1114   uint32_t      RESERVED37[8];
1115   __IO uint32_t MACPOCR;             /*!< PTP Offload control register,                                 Address offset: 0x0BC0 */
1116   __IO uint32_t MACSPI0R;            /*!< PTP Source Port Identity 0 Register,                          Address offset: 0x0BC4 */
1117   __IO uint32_t MACSPI1R;            /*!< PTP Source port identity 1 register,                          Address offset: 0x0BC8 */
1118   __IO uint32_t MACSPI2R;            /*!< PTP Source port identity 2 register,                          Address offset: 0x0BCC */
1119   __IO uint32_t MACLMIR;             /*!< Log message interval register,                                Address offset: 0x0BD0 */
1120   uint32_t      RESERVED38[11];
1121   __IO uint32_t MTLOMR;              /*!< Operating mode Register,                                      Address offset: 0x0C00 */
1122   uint32_t      RESERVED39[7];
1123   __IO uint32_t MTLISR;              /*!< Interrupt status Register,                                    Address offset: 0x0C20 */
1124   uint32_t      RESERVED40[3];
1125   __IO uint32_t MTLRXQDMAMR;         /*!< Rx Queue and DMA Channel Mapping Register,                    Address offset: 0x0C30 */
1126   uint32_t      RESERVED41[3];
1127   __IO uint32_t MTLTBSCR;            /*!< TBS control register,                                         Address offset: 0x0C40 */
1128   uint32_t      RESERVED42[3];
1129   __IO uint32_t MTLESTCR;            /*!< EST Control Register,                                         Address offset: 0x0C50 */
1130   __IO uint32_t MTLESTECR;           /*!< EST Extended Control Register,                                Address offset: 0x0C54 */
1131   __IO uint32_t MTLESTSR;            /*!< EST Status Register,                                          Address offset: 0x0C58 */
1132   uint32_t      RESERVED43;
1133   __IO uint32_t MTLESTSCHER;         /*!< EST Schedule Error Register,                                  Address offset: 0x0C60 */
1134   __IO uint32_t MTLESTFSER;          /*!< EST Frame size Error Register,                                Address offset: 0x0C64 */
1135   __IO uint32_t MTLESTFSCR;          /*!< EST Frame size Capture Register,                              Address offset: 0x0C68 */
1136   uint32_t      RESERVED44;
1137   __IO uint32_t MTLESTIER;           /*!< EST Interrupt Enable Register,                                Address offset: 0x0C70 */
1138   uint32_t      RESERVED45[3];
1139   __IO uint32_t MTLESTGCLCR;         /*!< EST Gate Control List Register,                               Address offset: 0x0C80 */
1140   __IO uint32_t MTLESTGCLDR;         /*!< EST Gate Control List Data Register,                          Address offset: 0x0C84 */
1141   uint32_t      RESERVED46[2];
1142   __IO uint32_t MTLFPECSR;           /*!< FPE Frame Preemption Control Status Register,                 Address offset: 0x0C90 */
1143   __IO uint32_t MTLFPEAR;            /*!< FPE Frame Preemption Advance Register,                        Address offset: 0x0C94 */
1144   uint32_t      RESERVED47[26];
1145   struct {
1146   __IO uint32_t MTLTXQOMR;           /*!< Tx queue x operating mode Register,                           Address offset: 0x0D00 */
1147   __IO uint32_t MTLTXQUR;            /*!< Tx queue x underflow register,                                Address offset: 0x0D04 */
1148   __IO uint32_t MTLTXQDR;            /*!< Tx queue x debug register,                                    Address offset: 0x0D08 */
1149   uint32_t      RESERVED48[1];
1150   __IO uint32_t MTLTXQ1ECR;           /*!< Tx queue 1 ETS control Register,                              Address offset: 0x0D50 */
1151   __IO uint32_t MTLTXQESR;           /*!< Tx queue x ETS status Register,                               Address offset: 0x0D14 */
1152   __IO uint32_t MTLTXQQWR;           /*!< Tx queue x quantum weight register,                           Address offset: 0x0D18 */
1153   __IO uint32_t MTLTXQ1SSCR;          /*!< Tx queue 1 send slope credit Register,                        Address offset: 0x0D5C */
1154   __IO uint32_t MTLTXQ1HCR;           /*!< Tx Queue 1 hiCredit register,                                 Address offset: 0x0D60 */
1155   __IO uint32_t MTLTXQ1LCR;           /*!< Tx queue 1 loCredit register,                                 Address offset: 0x0D64 */
1156   uint32_t      RESERVED49[1];
1157   __IO uint32_t MTLQICSR;           /*!< Queue 0 interrupt control status Register,                    Address offset: 0x0D2C */
1158   __IO uint32_t MTLRXQOMR;          /*!< Rx queue x operating mode register,                           Address offset: 0x0D30 */
1159   __IO uint32_t MTLRXQMPOCR;        /*!< Rx queue x missed packet and overflow counter register,       Address offset: 0x0D34 */
1160   __IO uint32_t MTLRXQDR;           /*!< Rx queue x debug register,                                    Address offset: 0x0D38 */
1161   __IO uint32_t MTLRXQCR;           /*!< Rx queue x control register,                                  Address offset: 0x0D3C */
1162   } MTL_QUEUE[2];
1163   uint32_t      RESERVED52[160];
1164   __IO uint32_t DMAMR;               /*!< DMA mode register,                                            Address offset: 0x1000 */
1165   __IO uint32_t DMASBMR;             /*!< System bus mode register,                                     Address offset: 0x1004 */
1166   __IO uint32_t DMAISR;              /*!< Interrupt status register,                                    Address offset: 0x1008 */
1167   __IO uint32_t DMADSR;              /*!< Debug status register,                                        Address offset: 0x100C */
1168   uint32_t      RESERVED53[4];
1169   __IO uint32_t DMAA4TXACR;          /*!< AXI4 transmit channel ACE control register,                   Address offset: 0x1020 */
1170   __IO uint32_t DMAA4RXACR;          /*!< AXI4 receive channel ACE control register,                    Address offset: 0x1024 */
1171   __IO uint32_t DMAA4DACR;           /*!< AXI4 descriptor ACE control register,                         Address offset: 0x1028 */
1172   uint32_t      RESERVED54[5];
1173   __IO uint32_t DMALPIEI;            /*!< AXI4 LPI Entry Interval register,                             Address offset: 0x1040 */
1174   uint32_t      RESERVED55[3];
1175   __IO uint32_t DMATBSCTRL0R;        /*!< DMA TBS control register 0,                                   Address offset: 0x1050 */
1176   uint32_t      RESERVED56[37];
1177   struct {
1178   uint32_t      RESERVED57[6];
1179   __IO uint32_t DMACCR;             /*!< Channel x control register,                                   Address offset: 0x1100 */
1180   __IO uint32_t DMACTXCR;           /*!< Channel x transmit control register,                          Address offset: 0x1104 */
1181   __IO uint32_t DMACRXCR;           /*!< Channel x receive control register,                           Address offset: 0x1108 */
1182   uint32_t      RESERVED58[2];
1183   __IO uint32_t DMACTXDLAR;         /*!< Channel x Tx descriptor list address register,                Address offset: 0x1114 */
1184   uint32_t      RESERVED59;
1185   __IO uint32_t DMACRXDLAR;         /*!< Channel x Rx descriptor list address register,                Address offset: 0x111C */
1186   __IO uint32_t DMACTXDTPR;         /*!< Channel x Tx descriptor tail pointer register,                Address offset: 0x1120 */
1187   uint32_t      RESERVED60;
1188   __IO uint32_t DMACRXDTPR;         /*!< Channel x Rx descriptor tail pointer register,                Address offset: 0x1128 */
1189   __IO uint32_t DMACTXRLR;          /*!< Channel x Tx descriptor ring length register,                 Address offset: 0x112C */
1190   __IO uint32_t DMACRXRLR;          /*!< Channel x Rx descriptor ring length register,                 Address offset: 0x1130 */
1191   __IO uint32_t DMACIER;            /*!< Channel x interrupt enable register,                          Address offset: 0x1134 */
1192   __IO uint32_t DMACRXIWTR;         /*!< Channel x Rx interrupt watchdog timer register,               Address offset: 0x1138 */
1193   __IO uint32_t DMACSFCSR;          /*!< Channel x slot function control status register,              Address offset: 0x113C */
1194   uint32_t      RESERVED61;
1195   __IO uint32_t DMACCATXDR;         /*!< Channel x current application transmit descriptor register,   Address offset: 0x1144 */
1196   uint32_t      RESERVED62;
1197   __IO uint32_t DMACCARXDR;         /*!< Channel x current application receive descriptor register,    Address offset: 0x114C */
1198   uint32_t      RESERVED63;
1199   __IO uint32_t DMACCATXBR;         /*!< Channel x current application transmit buffer register,       Address offset: 0x1154 */
1200   uint32_t      RESERVED64;
1201   __IO uint32_t DMACCARXBR;         /*!< Channel x current application receive buffer register,        Address offset: 0x115C */
1202   __IO uint32_t DMACSR;             /*!< Channel x status register,                                    Address offset: 0x1160 */
1203   __IO uint32_t DMACMFCR;            /*!< Channel x missed frame count register,                        Address offset: 0x1164 */
1204   } DMA_CH[2];
1205 }ETH_TypeDef;
1206 
1207 /**
1208   * @brief External Interrupt/Event Controller
1209   */
1210 typedef struct
1211 {
1212   __IO uint32_t RTSR1;          /*!< EXTI Rising Trigger Selection Register 1,        Address offset:   0x00 */
1213   __IO uint32_t FTSR1;          /*!< EXTI Falling Trigger Selection Register 1,       Address offset:   0x04 */
1214   __IO uint32_t SWIER1;         /*!< EXTI Software Interrupt event Register 1,        Address offset:   0x08 */
1215   __IO uint32_t RPR1;           /*!< EXTI Rising Pending Register 1,                  Address offset:   0x0C */
1216   __IO uint32_t FPR1;           /*!< EXTI Falling Pending Register 1,                 Address offset:   0x10 */
1217   __IO uint32_t SECCFGR1;       /*!< EXTI Security Configuration Register 1,          Address offset:   0x14 */
1218   __IO uint32_t PRIVCFGR1;      /*!< EXTI Privilege Configuration Register 1,         Address offset:   0x18 */
1219        uint32_t RESERVED1;      /*!< Reserved 1,                                      Address offset:   0x1C */
1220   __IO uint32_t RTSR2;          /*!< EXTI Rising Trigger Selection Register 2,        Address offset:   0x20 */
1221   __IO uint32_t FTSR2;          /*!< EXTI Falling Trigger Selection Register 2,       Address offset:   0x24 */
1222   __IO uint32_t SWIER2;         /*!< EXTI Software Interrupt event Register 2,        Address offset:   0x28 */
1223   __IO uint32_t RPR2;           /*!< EXTI Rising Pending Register 2,                  Address offset:   0x2C */
1224   __IO uint32_t FPR2;           /*!< EXTI Falling Pending Register 2,                 Address offset:   0x30 */
1225   __IO uint32_t SECCFGR2;       /*!< EXTI Security Configuration Register 2,          Address offset:   0x34 */
1226   __IO uint32_t PRIVCFGR2;      /*!< EXTI Privilege Configuration Register 2,         Address offset:   0x38 */
1227        uint32_t RESERVED2;      /*!< Reserved 2,                                      Address offset:   0x3C */
1228   __IO uint32_t RTSR3;          /*!< EXTI Rising Trigger Selection Register 3,        Address offset:   0x40 */
1229   __IO uint32_t FTSR3;          /*!< EXTI Falling Trigger Selection Register 3,       Address offset:   0x44 */
1230   __IO uint32_t SWIER3;         /*!< EXTI Software Interrupt event Register 3,        Address offset:   0x48 */
1231   __IO uint32_t RPR3;           /*!< EXTI Rising Pending Register 3,                  Address offset:   0x4C */
1232   __IO uint32_t FPR3;           /*!< EXTI Falling Pending Register 3,                 Address offset:   0x50 */
1233   __IO uint32_t SECCFGR3;       /*!< EXTI Security Configuration Register 3,          Address offset:   0x54 */
1234   __IO uint32_t PRIVCFGR3;      /*!< EXTI Privilege Configuration Register 3,         Address offset:   0x58 */
1235        uint32_t RESERVED3;      /*!< Reserved 3,                                      Address offset:   0x5C */
1236   __IO uint32_t EXTICR[4];      /*!< EXIT External Interrupt Configuration Register,            0x60 -- 0x6C */
1237   __IO uint32_t LOCKR;          /*!< EXTI Lock Register,                              Address offset:   0x70 */
1238        uint32_t RESERVED4[3];   /*!< Reserved 4,                                                0x74 -- 0x7C */
1239   __IO uint32_t IMR1;           /*!< EXTI Interrupt Mask Register 1,                  Address offset:   0x80 */
1240   __IO uint32_t EMR1;           /*!< EXTI Event Mask Register 1,                      Address offset:   0x84 */
1241        uint32_t RESERVED5[2];   /*!< Reserved 5,                                                0x88 -- 0x8C */
1242   __IO uint32_t IMR2;           /*!< EXTI Interrupt Mask Register 2,                  Address offset:   0x90 */
1243   __IO uint32_t EMR2;           /*!< EXTI Event Mask Register 2,                      Address offset:   0x94 */
1244        uint32_t RESERVED6[2];   /*!< Reserved 6,                                                0x98 -- 0x9C */
1245   __IO uint32_t IMR3;           /*!< EXTI Interrupt Mask Register 3,                  Address offset:   0xA0 */
1246   __IO uint32_t EMR3;           /*!< EXTI Event Mask Register 3,                      Address offset:   0xA4 */
1247 } EXTI_TypeDef;
1248 
1249 /**
1250  * @brief FD Controller Area Network
1251  */
1252 
1253 typedef struct
1254 {
1255  __IO uint32_t CREL;           /*!< FDCAN Core Release register,                                     Address offset: 0x000 */
1256  __IO uint32_t ENDN;           /*!< FDCAN Endian register,                                           Address offset: 0x004 */
1257  __IO uint32_t RESERVED1;      /*!< Reserved,                                                                        0x008 */
1258  __IO uint32_t DBTP;           /*!< FDCAN Data Bit Timing & Prescaler register,                      Address offset: 0x00C */
1259  __IO uint32_t TEST;           /*!< FDCAN Test register,                                             Address offset: 0x010 */
1260  __IO uint32_t RWD;            /*!< FDCAN RAM Watchdog register,                                     Address offset: 0x014 */
1261  __IO uint32_t CCCR;           /*!< FDCAN CC Control register,                                       Address offset: 0x018 */
1262  __IO uint32_t NBTP;           /*!< FDCAN Nominal Bit Timing & Prescaler register,                   Address offset: 0x01C */
1263  __IO uint32_t TSCC;           /*!< FDCAN Timestamp Counter Configuration register,                  Address offset: 0x020 */
1264  __IO uint32_t TSCV;           /*!< FDCAN Timestamp Counter Value register,                          Address offset: 0x024 */
1265  __IO uint32_t TOCC;           /*!< FDCAN Timeout Counter Configuration register,                    Address offset: 0x028 */
1266  __IO uint32_t TOCV;           /*!< FDCAN Timeout Counter Value register,                            Address offset: 0x02C */
1267  __IO uint32_t RESERVED2[4];   /*!< Reserved,                                                                0x030 - 0x03C */
1268  __IO uint32_t ECR;            /*!< FDCAN Error Counter register,                                    Address offset: 0x040 */
1269  __IO uint32_t PSR;            /*!< FDCAN Protocol Status register,                                  Address offset: 0x044 */
1270  __IO uint32_t TDCR;           /*!< FDCAN Transmitter Delay Compensation register,                   Address offset: 0x048 */
1271  __IO uint32_t RESERVED3;      /*!< Reserved,                                                                        0x04C */
1272  __IO uint32_t IR;             /*!< FDCAN Interrupt register,                                        Address offset: 0x050 */
1273  __IO uint32_t IE;             /*!< FDCAN Interrupt Enable register,                                 Address offset: 0x054 */
1274  __IO uint32_t ILS;            /*!< FDCAN Interrupt Line Select register,                            Address offset: 0x058 */
1275  __IO uint32_t ILE;            /*!< FDCAN Interrupt Line Enable register,                            Address offset: 0x05C */
1276  __IO uint32_t RESERVED4[8];   /*!< Reserved,                                                                0x060 - 0x07C */
1277  __IO uint32_t GFC;            /*!< FDCAN Global Filter Configuration register,                      Address offset: 0x080 */
1278  __IO uint32_t SIDFC;          /*!< FDCAN Standard ID Filter Configuration register,                 Address offset: 0x084 */
1279  __IO uint32_t XIDFC;          /*!< FDCAN Extended ID Filter Configuration register,                 Address offset: 0x088 */
1280  __IO uint32_t RESERVED5;      /*!< Reserved,                                                                        0x08C */
1281  __IO uint32_t XIDAM;          /*!< FDCAN Extended ID AND Mask register,                             Address offset: 0x090 */
1282  __IO uint32_t HPMS;           /*!< FDCAN High Priority Message Status register,                     Address offset: 0x094 */
1283  __IO uint32_t NDAT1;          /*!< FDCAN New Data 1 register,                                       Address offset: 0x098 */
1284  __IO uint32_t NDAT2;          /*!< FDCAN New Data 2 register,                                       Address offset: 0x09C */
1285  __IO uint32_t RXF0C;          /*!< FDCAN Rx FIFO 0 Configuration register,                          Address offset: 0x0A0 */
1286  __IO uint32_t RXF0S;          /*!< FDCAN Rx FIFO 0 Status register,                                 Address offset: 0x0A4 */
1287  __IO uint32_t RXF0A;          /*!< FDCAN Rx FIFO 0 Acknowledge register,                            Address offset: 0x0A8 */
1288  __IO uint32_t RXBC;           /*!< FDCAN Rx Buffer Configuration register,                          Address offset: 0x0AC */
1289  __IO uint32_t RXF1C;          /*!< FDCAN Rx FIFO 1 Configuration register,                          Address offset: 0x0B0 */
1290  __IO uint32_t RXF1S;          /*!< FDCAN Rx FIFO 1 Status register,                                 Address offset: 0x0B4 */
1291  __IO uint32_t RXF1A;          /*!< FDCAN Rx FIFO 1 Acknowledge register,                            Address offset: 0x0B8 */
1292  __IO uint32_t RXESC;          /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register,        Address offset: 0x0BC */
1293  __IO uint32_t TXBC;           /*!< FDCAN Tx Buffer Configuration register,                          Address offset: 0x0C0 */
1294  __IO uint32_t TXFQS;          /*!< FDCAN Tx FIFO/Queue Status register,                             Address offset: 0x0C4 */
1295  __IO uint32_t TXESC;          /*!< FDCAN Tx Buffer Element Size Configuration register,             Address offset: 0x0C8 */
1296  __IO uint32_t TXBRP;          /*!< FDCAN Tx Buffer Request Pending register,                        Address offset: 0x0CC */
1297  __IO uint32_t TXBAR;          /*!< FDCAN Tx Buffer Add Request register,                            Address offset: 0x0D0 */
1298  __IO uint32_t TXBCR;          /*!< FDCAN Tx Buffer Cancellation Request register,                   Address offset: 0x0D4 */
1299  __IO uint32_t TXBTO;          /*!< FDCAN Tx Buffer Transmission Occurred register,                  Address offset: 0x0D8 */
1300  __IO uint32_t TXBCF;          /*!< FDCAN Tx Buffer Cancellation Finished register,                  Address offset: 0x0DC */
1301  __IO uint32_t TXBTIE;         /*!< FDCAN Tx Buffer Transmission Interrupt Enable register,          Address offset: 0x0E0 */
1302  __IO uint32_t TXBCIE;         /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */
1303  __IO uint32_t RESERVED6[2];   /*!< Reserved,                                                                0x0E8 - 0x0EC */
1304  __IO uint32_t TXEFC;          /*!< FDCAN Tx Event FIFO Configuration register,                      Address offset: 0x0F0 */
1305  __IO uint32_t TXEFS;          /*!< FDCAN Tx Event FIFO Status register,                             Address offset: 0x0F4 */
1306  __IO uint32_t TXEFA;          /*!< FDCAN Tx Event FIFO Acknowledge register,                        Address offset: 0x0F8 */
1307  __IO uint32_t RESERVED7;      /*!< Reserved,                                                                        0x0FC */
1308 } FDCAN_GlobalTypeDef;
1309 
1310 /**
1311   * @brief TTFD Controller Area Network
1312   */
1313 
1314 typedef struct
1315 {
1316   __IO uint32_t TTTMC;         /*!< TT Trigger Memory Configuration register,        Address offset: 0x100 */
1317   __IO uint32_t TTRMC;         /*!< TT Reference Message Configuration register,     Address offset: 0x104 */
1318   __IO uint32_t TTOCF;         /*!< TT Operation Configuration register,             Address offset: 0x108 */
1319   __IO uint32_t TTMLM;         /*!< TT Matrix Limits register,                       Address offset: 0x10C */
1320   __IO uint32_t TURCF;         /*!< TUR Configuration register,                      Address offset: 0x110 */
1321   __IO uint32_t TTOCN;         /*!< TT Operation Control register,                   Address offset: 0x114 */
1322   __IO uint32_t TTGTP;         /*!< TT Global Time Preset register,                  Address offset: 0x118 */
1323   __IO uint32_t TTTMK;         /*!< TT Time Mark register,                          Address offset: 0x11C */
1324   __IO uint32_t TTIR;          /*!< TT Interrupt register,                           Address offset: 0x120 */
1325   __IO uint32_t TTIE;          /*!< TT Interrupt Enable register,                    Address offset: 0x124 */
1326   __IO uint32_t TTILS;         /*!< TT Interrupt Line Select register,               Address offset: 0x128 */
1327   __IO uint32_t TTOST;         /*!< TT Operation Status register,                    Address offset: 0x12C */
1328   __IO uint32_t TURNA;         /*!< TT TUR Numerator Actual register,                Address offset: 0x130 */
1329   __IO uint32_t TTLGT;         /*!< TT Local and Global Time register,               Address offset: 0x134 */
1330   __IO uint32_t TTCTC;         /*!< TT Cycle Time and Count register,                Address offset: 0x138 */
1331   __IO uint32_t TTCPT;         /*!< TT Capture Time register,                        Address offset: 0x13C */
1332   __IO uint32_t TTCSM;         /*!< TT Cycle Sync Mark register,                     Address offset: 0x140 */
1333   __IO uint32_t RESERVED1[111];/*!< Reserved,                                                0x144 - 0x2FC */
1334   __IO uint32_t TTTS;          /*!< TT Trigger Select register,                      Address offset: 0x300 */
1335 } TTCAN_TypeDef;
1336 
1337 /**
1338   * @brief FD Controller Area Network
1339   */
1340 
1341 typedef struct
1342 {
1343   __IO uint32_t CREL;          /*!< Clock Calibration Unit Core Release register,    Address offset: 0x00 */
1344   __IO uint32_t CCFG;          /*!< Calibration Configuration register,              Address offset: 0x04 */
1345   __IO uint32_t CSTAT;         /*!< Calibration Status register,                     Address offset: 0x08 */
1346   __IO uint32_t CWD;           /*!< Calibration Watchdog register,                   Address offset: 0x0C */
1347   __IO uint32_t IR;            /*!< CCU Interrupt register,                          Address offset: 0x10 */
1348   __IO uint32_t IE;            /*!< CCU Interrupt Enable register,                   Address offset: 0x14 */
1349 } FDCAN_ClockCalibrationUnit_TypeDef;
1350 
1351 /**
1352  * @brief FD Controller Area Network Configuration
1353  */
1354 typedef struct
1355 {
1356  __IO uint32_t CKDIV;          /*!< FDCAN clock divider register,            Address offset: 0x100 + 0x000 */
1357       uint32_t RESERVED1[128]; /*!< Reserved,                                0x100 + 0x004 - 0x100 + 0x200 */
1358  __IO uint32_t OPTR;           /*!< FDCAN option register,                   Address offset: 0x100 + 0x204 */
1359       uint32_t RESERVED2[58];  /*!< Reserved,                                0x100 + 0x208 - 0x100 + 0x2EC */
1360  __IO uint32_t HWCFG;          /*!< FDCAN hardware configuration register,   Address offset: 0x100 + 0x2F0 */
1361  __IO uint32_t VERR;           /*!< FDCAN IP version register,               Address offset: 0x100 + 0x2F4 */
1362  __IO uint32_t IPIDR;          /*!< FDCAN IP ID register,                    Address offset: 0x100 + 0x2F8 */
1363  __IO uint32_t SIDR;           /*!< FDCAN size ID register,                  Address offset: 0x100 + 0x2FC */
1364 } FDCAN_Config_TypeDef;
1365 
1366 /**
1367   * @brief Flexible Memory Controller Bank1
1368   */
1369 typedef struct
1370 {
1371   __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
1372 } FMC_Bank1_TypeDef;
1373 
1374 /**
1375   * @brief Flexible Memory Controller Bank1E
1376   */
1377 typedef struct
1378 {
1379   __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
1380 } FMC_Bank1E_TypeDef;
1381 
1382 /**
1383   * @brief Flexible Memory Controller Bank2
1384   */
1385 typedef struct
1386 {
1387   __IO uint32_t SDCR[2];         /*!< SDRAM device 1/2 control register                      Address offset: 0x140-0x144 */
1388   __IO uint32_t SDTR;            /*!< SDRAM timing register                                  Address offset: 0x148 */
1389        uint32_t RESERVED0;       /*!< Reserved                                               Address offset: 0x14C */
1390   __IO uint32_t SDCMR;           /*!< SDRAM command mode register                            Address offset: 0x150 */
1391   __IO uint32_t SDRTR;           /*!< SDRAM refresh timer register                           Address offset: 0x154 */
1392   __IO uint32_t SDSR;            /*!< SDRAM status register                                  Address offset: 0x158 */
1393 } FMC_Bank5_6_TypeDef;
1394 
1395 /**
1396   * @brief Flexible Memory Controller Bank3
1397   */
1398 typedef struct
1399 {
1400   __IO uint32_t PCR;             /*!< NAND Flash Programmable control register               Address offset: 0x080 */
1401   __IO uint32_t SR;              /*!< FMC status register                                    Address offset: 0x084 */
1402   __IO uint32_t PMEM;            /*!< Common memory space timing register                    Address offset: 0x088 */
1403   __IO uint32_t PATT;            /*!< Attribute memory space timing registers                Address offset: 0x08C */
1404   __IO uint32_t HPR;             /*!< FMC Hamming parity result registers                    Address offset: 0x090 */
1405   __IO uint32_t HECCR;           /*!< FMC Hamming code ECC result register                   Address offset: 0x094 */
1406        uint32_t RESERVED0[58];   /*!< Reserved                                               Address offset: 0x098-0x17C */
1407   __IO uint32_t IER;             /*!< FMC NAND Interrupt Enable Register                     Address offset: 0x180 */
1408   __IO uint32_t ISR;             /*!< FMC Controller Interrupt Status Register               Address offset: 0x184 */
1409   __IO uint32_t ICR;             /*!< FMC NAND Controller Interrupt Clear Register           Address offset: 0x188 */
1410        uint32_t RESERVED1[29];   /*!< Reserved                                               Address offset: 0x18C-0x1FC */
1411   __IO uint32_t CSQCR;           /*!< FMC NAND Command Sequencer Control Register            Address offset: 0x200 */
1412   __IO uint32_t CSQCFGR1;        /*!< FMC NAND Command Sequencer Configuration Register 1    Address offset: 0x204 */
1413   __IO uint32_t CSQCFGR2;        /*!< FMC NAND Command Sequencer Configuration Register 2    Address offset: 0x208 */
1414   __IO uint32_t CSQCFGR3;        /*!< FMC NAND sequencer configuration register 3            Address offset: 0x20C */
1415   __IO uint32_t CSQAR1;          /*!< FMC NAND Command Sequencer Address Register 1          Address offset: 0x210 */
1416   __IO uint32_t CSQAR2;          /*!< FMC NAND Command Sequencer Address Register 2          Address offset: 0x214 */
1417        uint32_t RESERVED2[2];    /*!< Reserved                                               Address offset: 0x218-0x21C */
1418   __IO uint32_t CSQIER;          /*!< FMC NAND Command Sequencer Interrupt Enable Register   Address offset: 0x220 */
1419   __IO uint32_t CSQISR;          /*!< FMC NAND Command Sequencer Interrupt Status Register   Address offset: 0x224 */
1420   __IO uint32_t CSQICR;          /*!< FMC NAND Command Sequencer Interrupt Clear Register    Address offset: 0x228 */
1421        uint32_t RESERVED3;       /*!< Reserved                                               Address offset: 0x22C */
1422   __IO uint32_t CSQEMSR;         /*!< FMC Command Sequencer Error Mapping Status register    Address offset: 0x230 */
1423        uint32_t RESERVED4[7];    /*!< Reserved                                               Address offset: 0x234-0x24C */
1424   __IO uint32_t BCHIER;          /*!< FMC BCH Interrupt enable register                      Address offset: 0x250 */
1425   __IO uint32_t BCHISR;          /*!< FMC BCH Interrupt and Status Register                  Address offset: 0x254 */
1426   __IO uint32_t BCHICR;          /*!< FMC BCH Interrupt Clear Register                       Address offset: 0x258 */
1427        uint32_t RESERVED5;       /*!< Reserved                                               Address offset: 0x25C */
1428   __IO uint32_t BCHPBR1;         /*!< FMC BCH Parity Bits Register 1                         Address offset: 0x260 */
1429   __IO uint32_t BCHPBR2;         /*!< FMC BCH Parity Bits Register 2                         Address offset: 0x264 */
1430   __IO uint32_t BCHPBR3;         /*!< FMC BCH Parity Bits Register 3                         Address offset: 0x268 */
1431   __IO uint32_t BCHPBR4;         /*!< FMC BCH Parity Bits Register 4                         Address offset: 0x26C */
1432        uint32_t RESERVED6[3];    /*!< Reserved                                               Address offset: 0x270-0x278 */
1433   __IO uint32_t BCHDSR0;         /*!< FMC BCH Decoder Status register 0                      Address offset: 0x27C */
1434   __IO uint32_t BCHDSR1;         /*!< FMC BCH Decoder Status register for bank 1             Address offset: 0x280 */
1435   __IO uint32_t BCHDSR2;         /*!< FMC BCH Decoder Status register for bank 2             Address offset: 0x284 */
1436   __IO uint32_t BCHDSR3;         /*!< FMC BCH Decoder Status register for bank 3             Address offset: 0x288 */
1437   __IO uint32_t BCHDSR4;         /*!< FMC BCH Decoder Status register for bank 4             Address offset: 0x28C */
1438 } FMC_Bank3_TypeDef;
1439 
1440 /**
1441   * @brief Flexible Memory Controller Common
1442   */
1443 typedef struct{
1444   __IO uint32_t CFGR;            /*!< FMC common configuration register                      Address offset: 0x020 */
1445 } FMC_Common_TypeDef;
1446 
1447 /**
1448   * @brief General Purpose I/O
1449   */
1450 typedef struct
1451 {
1452   __IO uint32_t MODER;         /*!< GPIO port mode register,                     Address offset: 0x00      */
1453   __IO uint32_t OTYPER;        /*!< GPIO port output type register,              Address offset: 0x04      */
1454   __IO uint32_t OSPEEDR;       /*!< GPIO port output speed register,             Address offset: 0x08      */
1455   __IO uint32_t PUPDR;         /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C      */
1456   __IO uint32_t IDR;           /*!< GPIO port input data register,               Address offset: 0x10      */
1457   __IO uint32_t ODR;           /*!< GPIO port output data register,              Address offset: 0x14      */
1458   __IO uint32_t BSRR;          /*!< GPIO port bit set/reset  register,           Address offset: 0x18      */
1459   __IO uint32_t LCKR;          /*!< GPIO port configuration lock register,       Address offset: 0x1C      */
1460   __IO uint32_t AFR[2];        /*!< GPIO alternate function registers,           Address offset: 0x20-0x24 */
1461   __IO uint32_t BRR;           /*!< GPIO bit reset register,                     Address offset: 0x28      */
1462        uint32_t RESERVED0;     /*!< Reserved,                                    Address offset: 0x2C      */
1463   __IO uint32_t SECCFGR;       /*!< GPIO port secure configuration register,     Address offset: 0x30      */
1464   __IO uint32_t PRIVCFGR;      /*!< GPIO port privileged configuration register, Address offset: 0x34      */
1465   __IO uint32_t RCFGLOCKR;     /*!< GPIO port resource configuration register,   Address offset: 0x38      */
1466        uint32_t RESERVED1;     /*!< Reserved,                                    Address offset: 0x3C      */
1467   __IO uint32_t DELAYR[2];     /*!< GPIO port delay register,                    Address offset: 0x40-0x44 */
1468   __IO uint32_t ADVCFGR[2];    /*!< GPIO port advanced configuration register,   Address offset: 0x48-0x4C */
1469 } GPIO_TypeDef;
1470 
1471 /**
1472   * @brief GFXMMU
1473   */
1474 typedef struct
1475 {
1476   __IO uint32_t CR;              /*!< GFXMMU configuration register,                     Address offset: 0x00 */
1477   __IO uint32_t SR;              /*!< GFXMMU status register,                            Address offset: 0x04 */
1478   __IO uint32_t FCR;             /*!< GFXMMU flag clear register,                        Address offset: 0x08 */
1479        uint32_t RESERVED0;       /*!< Reserved0,                                         Address offset: 0x0C */
1480   __IO uint32_t DVR;             /*!< GFXMMU default value register,                     Address offset: 0x10 */
1481   __IO uint32_t DAR;             /*!< GFXMMU default alpha register,                     Address offset: 0x14 */
1482        uint32_t RESERVED1[2];    /*!< Reserved1,                                 Address offset: 0x18 to 0x1C */
1483   __IO uint32_t B0CR;            /*!< GFXMMU buffer 0 configuration register,            Address offset: 0x20 */
1484   __IO uint32_t B1CR;            /*!< GFXMMU buffer 1 configuration register,            Address offset: 0x24 */
1485   __IO uint32_t B2CR;            /*!< GFXMMU buffer 2 configuration register,            Address offset: 0x28 */
1486   __IO uint32_t B3CR;            /*!< GFXMMU buffer 3 configuration register,            Address offset: 0x2C */
1487        uint32_t RESERVED2[1012]; /*!< Reserved2,                                 Address offset: 0x30 to 0xFFC */
1488   __IO uint32_t LUT[2048];       /*!< GFXMMU LUT registers,                      Address offset: 0x1000 to 0x2FFC
1489                                       For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */
1490 } GFXMMU_TypeDef;
1491 
1492 /**
1493   * @brief GFXTIM
1494   */
1495 typedef struct
1496 {
1497   __IO uint32_t CR;            /*!< GFXTIM configuration register,                    Address offset: 0x00 */
1498   __IO uint32_t CGCR;          /*!< GFXTIM clock generator configuration register,    Address offset: 0x04 */
1499   __IO uint32_t TCR;           /*!< GFXTIM timers configuration register,             Address offset: 0x08 */
1500   __IO uint32_t TDR;           /*!< GFXTIM timers disable register,                   Address offset: 0x0C */
1501   __IO uint32_t EVCR;          /*!< GFXTIM events control register,                   Address offset: 0x10 */
1502   __IO uint32_t EVSR;          /*!< GFXTIM events selection register,                 Address offset: 0x14 */
1503   uint32_t RESERVED1[2];       /*!< Reserved,                                         Address offset: 0x18-0x1C */
1504   __IO uint32_t WDGTCR;        /*!< GFXTIM watchdog timer configuration register,     Address offset: 0x20 */
1505   uint32_t RESERVED2[3];       /*!< Reserved,                                         Address offset: 0x24-0x2C */
1506   __IO uint32_t ISR;           /*!< GFXTIM interrupt status register,                 Address offset: 0x30 */
1507   __IO uint32_t ICR;           /*!< GFXTIM interrupt clear register,                  Address offset: 0x34 */
1508   __IO uint32_t IER;           /*!< GFXTIM interrupt enable register,                 Address offset: 0x38 */
1509   __IO uint32_t TSR;           /*!< GFXTIM timers status register,                    Address offset: 0x3C */
1510   __IO uint32_t LCCRR;         /*!< GFXTIM line clock counter reload register,        Address offset: 0x40 */
1511   __IO uint32_t FCCRR;         /*!< GFXTIM frame clock counter reload register,       Address offset: 0x44 */
1512   uint32_t RESERVED3[2];       /*!< Reserved,                                         Address offset: 0x48-0x4C */
1513   __IO uint32_t ATR;           /*!< GFXTIM absolute time register,                    Address offset: 0x50 */
1514   __IO uint32_t AFCR;          /*!< GFXTIM absolute frame counter register,           Address offset: 0x54 */
1515   __IO uint32_t ALCR;          /*!< GFXTIM absolute line counter register,            Address offset: 0x58 */
1516   uint32_t RESERVED4[1];       /*!< Reserved,                                         Address offset: 0x5C */
1517   __IO uint32_t AFCC1R;        /*!< GFXTIM absolute frame counter compare 1 register, Address offset: 0x60 */
1518   uint32_t RESERVED5[3];       /*!< Reserved,                                         Address offset: 0x64-0X6C */
1519   __IO uint32_t ALCC1R;        /*!< GFXTIM absolute line counter compare 1 register,  Address offset: 0x70 */
1520   __IO uint32_t ALCC2R;        /*!< GFXTIM absolute line counter compare 2 register,  Address offset: 0x74 */
1521   uint32_t RESERVED6[2];       /*!< Reserved,                                         Address offset: 0x78-0X7C */
1522   __IO uint32_t RFC1R;         /*!< GFXTIM relative frame counter 1 register,         Address offset: 0x80 */
1523   __IO uint32_t RFC1RR;        /*!< GFXTIM relative frame counter 1 reload register,  Address offset: 0x84 */
1524   __IO uint32_t RFC2R;         /*!< GFXTIM relative frame counter 2 register,         Address offset: 0x88 */
1525   __IO uint32_t RFC2RR;        /*!< GFXTIM relative frame counter 2 reload register,  Address offset: 0x8C */
1526   uint32_t RESERVED7[4];       /*!< Reserved,                                         Address offset: 0x90-0X9C */
1527   __IO uint32_t WDGCR;         /*!< GFXTIM watchdog counter register,                 Address offset: 0xA0 */
1528   __IO uint32_t WDGRR;         /*!< GFXTIM watchdog reload register,                  Address offset: 0xA4 */
1529   __IO uint32_t WDGPAR;        /*!< GFXTIM watchdog pre-alarm register,               Address offset: 0xA8 */
1530   uint32_t RESERVED8[209];     /*!< Reserved,                                         Address offset: 0xAC-0X3EC */
1531   __IO uint32_t HWCFGR;        /*!< GFXTIM HW configuration register,                 Address offset: 0x3F0 */
1532   __IO uint32_t VERR;          /*!< GFXTIM version register,                          Address offset: 0x3F4 */
1533   __IO uint32_t IPIDR;         /*!< GFXTIM identification register,                   Address offset: 0x3F8 */
1534   __IO uint32_t SIDR;          /*!< GFXTIM size identification register,              Address offset: 0x3FC */
1535 } GFXTIM_TypeDef;
1536 
1537 /**
1538   * @brief HASH
1539   */
1540 typedef struct
1541 {
1542   __IO uint32_t CR;               /*!< HASH control register,          Address offset: 0x00        */
1543   __IO uint32_t DIN;              /*!< HASH data input register,       Address offset: 0x04        */
1544   __IO uint32_t STR;              /*!< HASH start register,            Address offset: 0x08        */
1545   __IO uint32_t HR[5];            /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */
1546   __IO uint32_t IMR;              /*!< HASH interrupt enable register, Address offset: 0x20        */
1547   __IO uint32_t SR;               /*!< HASH status register,           Address offset: 0x24        */
1548        uint32_t RESERVED[52];     /*!< Reserved, 0x28-0xF4                                         */
1549   __IO uint32_t CSR[103];         /*!< HASH context swap registers,    Address offset: 0x0F8-0x290 */
1550 } HASH_TypeDef;
1551 
1552 /**
1553   * @brief HASH_DIGEST
1554   */
1555 typedef struct
1556 {
1557   __IO uint32_t HR[16];           /*!< HASH digest registers,          Address offset: 0x310-0x34C */
1558 } HASH_DIGEST_TypeDef;
1559 
1560 /**
1561   * @brief Inter-integrated Circuit Interface
1562   */
1563 typedef struct
1564 {
1565   __IO uint32_t CR1;         /*!< I2C Control register 1,            Address offset: 0x00 */
1566   __IO uint32_t CR2;         /*!< I2C Control register 2,            Address offset: 0x04 */
1567   __IO uint32_t OAR1;        /*!< I2C Own address 1 register,        Address offset: 0x08 */
1568   __IO uint32_t OAR2;        /*!< I2C Own address 2 register,        Address offset: 0x0C */
1569   __IO uint32_t TIMINGR;     /*!< I2C Timing register,               Address offset: 0x10 */
1570   __IO uint32_t TIMEOUTR;    /*!< I2C Timeout register,              Address offset: 0x14 */
1571   __IO uint32_t ISR;         /*!< I2C Interrupt and status register, Address offset: 0x18 */
1572   __IO uint32_t ICR;         /*!< I2C Interrupt clear register,      Address offset: 0x1C */
1573   __IO uint32_t PECR;        /*!< I2C PEC register,                  Address offset: 0x20 */
1574   __IO uint32_t RXDR;        /*!< I2C Receive data register,         Address offset: 0x24 */
1575   __IO uint32_t TXDR;        /*!< I2C Transmit data register,        Address offset: 0x28 */
1576 } I2C_TypeDef;
1577 
1578 /**
1579   * @brief Improved Inter-integrated Circuit Interface
1580   */
1581 typedef struct
1582 {
1583   __IO uint32_t CR;             /*!< I3C Control register,                      Address offset: 0x00      */
1584   __IO uint32_t CFGR;           /*!< I3C Controller Configuration register,     Address offset: 0x04      */
1585   uint32_t      RESERVED1[2];   /*!< Reserved,                                  Address offset: 0x08-0x0C */
1586   __IO uint32_t RDR;            /*!< I3C Received Data register,                Address offset: 0x10      */
1587   __IO uint32_t RDWR;           /*!< I3C Received Data Word register,           Address offset: 0x14      */
1588   __IO uint32_t TDR;            /*!< I3C Transmit Data register,                Address offset: 0x18      */
1589   __IO uint32_t TDWR;           /*!< I3C Transmit Data Word register,           Address offset: 0x1C      */
1590   __IO uint32_t IBIDR;          /*!< I3C IBI payload Data register,             Address offset: 0x20      */
1591   __IO uint32_t TGTTDR;         /*!< I3C Target Transmit register,              Address offset: 0x24      */
1592   uint32_t      RESERVED2[2];   /*!< Reserved,                                  Address offset: 0x28-0x2C */
1593   __IO uint32_t SR;             /*!< I3C Status register,                       Address offset: 0x30      */
1594   __IO uint32_t SER;            /*!< I3C Status Error register,                 Address offset: 0x34      */
1595   uint32_t      RESERVED3[2];   /*!< Reserved,                                  Address offset: 0x38-0x3C */
1596   __IO uint32_t RMR;            /*!< I3C Received Message register,             Address offset: 0x40      */
1597   uint32_t      RESERVED4[3];   /*!< Reserved,                                  Address offset: 0x44-0x4C */
1598   __IO uint32_t EVR;            /*!< I3C Event register,                        Address offset: 0x50      */
1599   __IO uint32_t IER;            /*!< I3C Interrupt Enable register,             Address offset: 0x54      */
1600   __IO uint32_t CEVR;           /*!< I3C Clear Event register,                  Address offset: 0x58      */
1601   uint32_t RESERVED5;           /*!< Reserved,                                  Address offset: 0x5C      */
1602   __IO uint32_t DEVR0;          /*!< I3C own Target characteristics register,   Address offset: 0x60      */
1603   __IO uint32_t DEVRX[4];       /*!< I3C Target x (1<=x<=4) register,           Address offset: 0x64-0x70 */
1604   uint32_t      RESERVED6[7];   /*!< Reserved,                                  Address offset: 0x74-0x8C */
1605   __IO uint32_t MAXRLR;         /*!< I3C Maximum Read Length register,          Address offset: 0x90      */
1606   __IO uint32_t MAXWLR;         /*!< I3C Maximum Write Length register,         Address offset: 0x94      */
1607   uint32_t      RESERVED7[2];   /*!< Reserved,                                  Address offset: 0x98-0x9C */
1608   __IO uint32_t TIMINGR0;       /*!< I3C Timing 0 register,                     Address offset: 0xA0      */
1609   __IO uint32_t TIMINGR1;       /*!< I3C Timing 1 register,                     Address offset: 0xA4      */
1610   __IO uint32_t TIMINGR2;       /*!< I3C Timing 2 register,                     Address offset: 0xA8      */
1611   uint32_t      RESERVED9[5];   /*!< Reserved,                                  Address offset: 0xAC-0xBC */
1612   __IO uint32_t BCR;            /*!< I3C Bus Characteristics register,          Address offset: 0xC0      */
1613   __IO uint32_t DCR;            /*!< I3C Device Characteristics register,       Address offset: 0xC4      */
1614   __IO uint32_t GETCAPR;        /*!< I3C GET CAPabilities register,             Address offset: 0xC8      */
1615   __IO uint32_t CRCAPR;         /*!< I3C Controller CAPabilities register,      Address offset: 0xCC      */
1616   __IO uint32_t GETMXDSR;       /*!< I3C GET Max Data Speed register,           Address offset: 0xD0      */
1617   __IO uint32_t EPIDR;          /*!< I3C Extended Provisioned ID register,      Address offset: 0xD4      */
1618 } I3C_TypeDef;
1619 
1620 /**
1621   * @brief Illegal Access Controller
1622   */
1623 typedef struct
1624 {
1625   __IO uint32_t IER[5];         /*!< Interrupt Enable register,                 Address offset: 0x000       */
1626   uint32_t      RESERVED1[27];  /*!< Reserved,                                  Address offset: 0x014-0x07C */
1627   __IO uint32_t ISR[5];         /*!< Interrupt Status register,                 Address offset: 0x080       */
1628   uint32_t      RESERVED2[27];  /*!< Reserved,                                  Address offset: 0x094-0x0FC */
1629   __IO uint32_t ICR[5];         /*!< Interrupt Clear register,                  Address offset: 0x100       */
1630 } IAC_TypeDef;
1631 
1632 /**
1633   * @brief Instruction Cache
1634   */
1635 typedef struct
1636 {
1637   __IO uint32_t CR;             /*!< ICACHE control register,                Address offset: 0x00 */
1638   __IO uint32_t SR;             /*!< ICACHE status register,                 Address offset: 0x04 */
1639   __IO uint32_t IER;            /*!< ICACHE interrupt enable register,       Address offset: 0x08 */
1640   __IO uint32_t FCR;            /*!< ICACHE flag clear register,             Address offset: 0x0C */
1641   __IO uint32_t HMONR;          /*!< ICACHE hit monitor register,            Address offset: 0x10 */
1642   __IO uint32_t MMONR;          /*!< ICACHE miss monitor register,           Address offset: 0x14 */
1643 } ICACHE_TypeDef;
1644 
1645 typedef struct
1646 {
1647   __IO uint32_t KR;              /*!< IWDG key register                    Address offset: 0x000 */
1648   __IO uint32_t PR;              /*!< IWDG prescaler register              Address offset: 0x004 */
1649   __IO uint32_t RLR;             /*!< IWDG reload register                 Address offset: 0x008 */
1650   __IO uint32_t SR;              /*!< IWDG status register                 Address offset: 0x00C */
1651   __IO uint32_t WINR;            /*!< IWDG window register                 Address offset: 0x010 */
1652   __IO uint32_t EWCR;            /*!< IWDG early wakeup interrupt register Address offset: 0x014 */
1653   __IO uint32_t ICR;             /*!< IWDG interrupt clear register        Address offset: 0x018 */
1654 } IWDG_TypeDef;
1655 
1656 /**
1657   * @brief JPEG Codec
1658   */
1659 typedef struct
1660 {
1661   __IO uint32_t CONFR0;          /*!< JPEG Codec Control Register (JPEG_CONFR0),        Address offset: 00h       */
1662   __IO uint32_t CONFR1;          /*!< JPEG Codec Control Register (JPEG_CONFR1),        Address offset: 04h       */
1663   __IO uint32_t CONFR2;          /*!< JPEG Codec Control Register (JPEG_CONFR2),        Address offset: 08h       */
1664   __IO uint32_t CONFR3;          /*!< JPEG Codec Control Register (JPEG_CONFR3),        Address offset: 0Ch       */
1665   __IO uint32_t CONFR4;          /*!< JPEG Codec Control Register (JPEG_CONFR4),        Address offset: 10h       */
1666   __IO uint32_t CONFR5;          /*!< JPEG Codec Control Register (JPEG_CONFR5),        Address offset: 14h       */
1667   __IO uint32_t CONFR6;          /*!< JPEG Codec Control Register (JPEG_CONFR6),        Address offset: 18h       */
1668   __IO uint32_t CONFR7;          /*!< JPEG Codec Control Register (JPEG_CONFR7),        Address offset: 1Ch       */
1669   uint32_t  Reserved20[4];       /* Reserved                                            Address offset: 20h-2Ch   */
1670   __IO uint32_t CR;              /*!< JPEG Control Register (JPEG_CR),                  Address offset: 30h       */
1671   __IO uint32_t SR;              /*!< JPEG Status Register (JPEG_SR),                   Address offset: 34h       */
1672   __IO uint32_t CFR;             /*!< JPEG Clear Flag Register (JPEG_CFR),              Address offset: 38h       */
1673   uint32_t  Reserved3c;          /* Reserved                                            Address offset: 3Ch       */
1674   __IO uint32_t DIR;             /*!< JPEG Data Input Register (JPEG_DIR),              Address offset: 40h       */
1675   __IO uint32_t DOR;             /*!< JPEG Data Output Register (JPEG_DOR),             Address offset: 44h       */
1676   uint32_t  Reserved48[2];       /* Reserved                                            Address offset: 48h-4Ch   */
1677   __IO uint32_t QMEM0[16];       /*!< JPEG quantization tables 0,                       Address offset: 50h-8Ch   */
1678   __IO uint32_t QMEM1[16];       /*!< JPEG quantization tables 1,                       Address offset: 90h-CCh   */
1679   __IO uint32_t QMEM2[16];       /*!< JPEG quantization tables 2,                       Address offset: D0h-10Ch  */
1680   __IO uint32_t QMEM3[16];       /*!< JPEG quantization tables 3,                       Address offset: 110h-14Ch */
1681   __IO uint32_t HUFFMIN[16];     /*!< JPEG HuffMin tables,                              Address offset: 150h-18Ch */
1682   __IO uint32_t HUFFBASE[32];    /*!< JPEG HuffSymb tables,                             Address offset: 190h-20Ch */
1683   __IO uint32_t HUFFSYMB[84];    /*!< JPEG HUFFSYMB tables,                             Address offset: 210h-35Ch */
1684   __IO uint32_t DHTMEM[103];     /*!< JPEG DHTMem tables,                               Address offset: 360h-4F8h */
1685   uint32_t  Reserved4FC;         /* Reserved                                            Address offset: 4FCh      */
1686   __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0,                 Address offset: 500h-65Ch */
1687   __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1,                 Address offset: 660h-7BCh */
1688   __IO uint32_t HUFFENC_DC0[8];  /*!< JPEG encodor, DC Huffman table 0,                 Address offset: 7C0h-7DCh */
1689   __IO uint32_t HUFFENC_DC1[8];  /*!< JPEG encodor, DC Huffman table 1,                 Address offset: 7E0h-7FCh */
1690 
1691 } JPEG_TypeDef;
1692 
1693 
1694 /**
1695   * @brief LCD-TFT Display Controller (LTDC)
1696   */
1697 typedef struct
1698 {
1699        uint32_t RESERVED0[2];   /*!< Reserved Address offset: 0x00-0x04 */
1700   __IO uint32_t SSCR;           /*!< LTDC synchronization size configuration register Address offset: 0x8 */
1701   __IO uint32_t BPCR;           /*!< LTDC back porch configuration register Address offset: 0xc */
1702   __IO uint32_t AWCR;           /*!< LTDC active width configuration register Address offset: 0x10 */
1703   __IO uint32_t TWCR;           /*!< LTDC total width configuration register Address offset: 0x14 */
1704   __IO uint32_t GCR;            /*!< LTDC global control register Address offset: 0x18 */
1705        uint32_t RESERVED1[2];   /*!< Reserved Address offset: */
1706   __IO uint32_t SRCR;           /*!< LTDC shadow reload configuration register Address offset: 0x24 */
1707   __IO uint32_t GCCR;           /*!< LTDC gamma correction configuration register Address offset: 0x28 */
1708   __IO uint32_t BCCR;           /*!< LTDC background color configuration register Address offset: 0x2c */
1709        uint32_t RESERVED2;      /*!< Reserved Address offset: 0x30 */
1710   __IO uint32_t IER;            /*!< LTDC interrupt enable register Address offset: 0x34 */
1711   __IO uint32_t ISR;            /*!< LTDC interrupt status register Address offset: 0x38 */
1712   __IO uint32_t ICR;            /*!< LTDC Interrupt Clear Register Address offset: 0x3c */
1713   __IO uint32_t LIPCR;          /*!< LTDC line interrupt position configuration register Address offset: 0x40 */
1714   __IO uint32_t CPSR;           /*!< LTDC current position status register Address offset: 0x44 */
1715   __IO uint32_t CDSR;           /*!< LTDC current display status register Address offset: 0x48 */
1716        uint32_t RESERVED3[5];   /*!< Reserved Address offset: 0x4c */
1717   __IO uint32_t EDCR;           /*!< LTDC external display control register Address offset: 0x60 */
1718   __IO uint32_t IER2;           /*!< LTDC interrupt enable register 2 Address offset: 0x64 */
1719   __IO uint32_t ISR2;           /*!< LTDC interrupt status register 2 Address offset: 0x68 */
1720   __IO uint32_t ICR2;           /*!< LTDC Interrupt Clear Register 2 Address offset: 0x6c */
1721   __IO uint32_t LIPCR2;         /*!< LTDC line interrupt position configuration register 2 Address offset: 0x70 */
1722        uint32_t RESERVED4;      /*!< Reserved Address offset: 0x74 */
1723   __IO uint32_t ECRCR;          /*!< LTDC expected CRC register Address offset: 0x78 */
1724   __IO uint32_t CCRCR;          /*!< LTDC computed CRC register Address offset: 0x7c */
1725   __IO uint32_t RB0AR;          /*!< LTDC rotation buffer 0 address register Address offset: 0x80 */
1726   __IO uint32_t RB1AR;          /*!< LTDC rotation buffer 1 address register Address offset: 0x84 */
1727   __IO uint32_t RBPR;           /*!< LTDC rotation buffer pitch register Address offset: 0x88 */
1728   __IO uint32_t RIFCR;          /*!< LTDC rotation intermediate frame color register Address offset: 0x8c */
1729   __IO uint32_t FUTR;           /*!< LTDC FIFO underrun threshold register Address offset: 0x90 */
1730 } LTDC_TypeDef;
1731 
1732 /**
1733   * @brief LCD-TFT Display layer x Controller (LTDC)
1734   */
1735 typedef struct
1736 {
1737   __IO uint32_t C0R;          /*!< LTDC layer x configuration 0 register Address offset: 0x100 */
1738   __IO uint32_t C1R;          /*!< LTDC layer x configuration 1 register Address offset: 0x104 */
1739   __IO uint32_t RCR;          /*!< LTDC layer x reload control register Address offset: 0x108 */
1740   __IO uint32_t CR;           /*!< LTDC layer x control register Address offset: 0x10c */
1741   __IO uint32_t WHPCR;        /*!< LTDC layer x window horizontal position configuration register Address offset: 0x110 */
1742   __IO uint32_t WVPCR;        /*!< LTDC layer x window vertical position configuration register Address offset: 0x114 */
1743   __IO uint32_t CKCR;         /*!< LTDC layer x color keying configuration register Address offset: 0x118 */
1744   __IO uint32_t PFCR;         /*!< LTDC layer x pixel format configuration register Address offset: 0x11c */
1745   __IO uint32_t CACR;         /*!< LTDC layer x constant alpha configuration register Address offset: 0x120 */
1746   __IO uint32_t DCCR;         /*!< LTDC layer x default color configuration register Address offset: 0x124 */
1747   __IO uint32_t BFCR;         /*!< LTDC layer x blending factors configuration register Address offset: 0x128 */
1748   __IO uint32_t BLCR;         /*!< LTDC layer x burst length configuration register Address offset: 0x12c */
1749   __IO uint32_t PCR;          /*!< LTDC layer x planar configuration register Address offset: 0x130 */
1750   __IO uint32_t CFBAR;        /*!< LTDC layer x color frame buffer address register Address offset: 0x134 */
1751   __IO uint32_t CFBLR;        /*!< LTDC layer x color frame buffer length register Address offset: 0x138 */
1752   __IO uint32_t CFBLNR;       /*!< LTDC layer x color frame buffer line number register Address offset: 0x13c */
1753   __IO uint32_t AFBA0R;       /*!< LTDC layer x auxiliary frame buffer address 0 register Address offset: 0x140 */
1754   __IO uint32_t AFBA1R;       /*!< LTDC layer x auxiliary frame buffer address 1 register Address offset: 0x144 */
1755   __IO uint32_t AFBLR;        /*!< LTDC layer x auxiliary frame buffer length register Address offset: 0x148 */
1756   __IO uint32_t AFBLNR;       /*!< LTDC layer x auxiliary frame buffer line number register Address offset: 0x14c */
1757   __IO uint32_t CLUTWR;       /*!< LTDC layer x CLUT write register Address offset: 0x150 */
1758   __IO uint32_t SISR;         /*!< LTDC layer x Scaler Input Size register Address offset: 0x154 */
1759   __IO uint32_t SOSR;         /*!< LTDC layer x Scaler Output Size register Address offset: 0x158 */
1760   __IO uint32_t SVSFR;        /*!< LTDC layer x Scaler Vertical Scaling Factor register Address offset: 0x15c */
1761   __IO uint32_t SVSPR;        /*!< LTDC layer x Scaler Vertical Scaling Phase register Address offset: 0x160 */
1762   __IO uint32_t SHSFR;        /*!< LTDC layer x Scaler Horizontal Scaling Factor register Address offset: 0x164 */
1763   __IO uint32_t SHSPR;        /*!< LTDC layer x Scaler Horizontal Scaling Phase register Address offset: 0x168 */
1764   __IO uint32_t CYR0R;        /*!< LTDC layer x Conversion YCbCr RGB 0 register Address offset: 0x16c */
1765   __IO uint32_t CYR1R;        /*!< LTDC layer x Conversion YCbCr RGB 1 register Address offset: 0x170 */
1766   __IO uint32_t FPF0R;        /*!< LTDC layer x Flexible Pixel Format 0 register Address offset: 0x174 */
1767   __IO uint32_t FPF1R;        /*!< LTDC layer x Flexible Pixel Format 1 register Address offset: 0x178 */
1768 } LTDC_Layer_TypeDef;
1769 
1770 
1771 /**
1772   * @brief LPTIMER
1773   */
1774 typedef struct
1775 {
1776   __IO uint32_t ISR;            /*!< LPTIM Interrupt and Status register,    Address offset: 0x00 */
1777   __IO uint32_t ICR;            /*!< LPTIM Interrupt Clear register,         Address offset: 0x04 */
1778   __IO uint32_t DIER;           /*!< LPTIM Interrupt Enable register,        Address offset: 0x08 */
1779   __IO uint32_t CFGR;           /*!< LPTIM Configuration register,           Address offset: 0x0C */
1780   __IO uint32_t CR;             /*!< LPTIM Control register,                 Address offset: 0x10 */
1781   __IO uint32_t CCR1;           /*!< LPTIM Capture/Compare register 1,       Address offset: 0x14 */
1782   __IO uint32_t ARR;            /*!< LPTIM Autoreload register,              Address offset: 0x18 */
1783   __IO uint32_t CNT;            /*!< LPTIM Counter register,                 Address offset: 0x1C */
1784   __IO uint32_t RESERVED1;      /*!< Reserved,                               Address offset: 0x20 */
1785   __IO uint32_t CFGR2;          /*!< LPTIM Configuration register 2,         Address offset: 0x24 */
1786   __IO uint32_t RCR;            /*!< LPTIM Repetition register,              Address offset: 0x28 */
1787   __IO uint32_t CCMR1;          /*!< LPTIM Capture/Compare mode register,    Address offset: 0x2C */
1788   __IO uint32_t RESERVED2;      /*!< Reserved,                               Address offset: 0x30 */
1789   __IO uint32_t CCR2;           /*!< LPTIM Capture/Compare register 2,       Address offset: 0x34 */
1790 } LPTIM_TypeDef;
1791 
1792 /**
1793   * @brief Memory Cipher Engine (MCE)
1794   */
1795 typedef struct
1796 {
1797   __IO uint32_t REGCR;            /*!< MCE region configuration register,             Address offset: 0x040 + 0x10 * (x-1) (x = 1 to 4) */
1798   __IO uint32_t SADDR;            /*!< MCE region start address register,             Address offset: 0x044 + 0x10 * (x-1) (x = 1 to 4) */
1799   __IO uint32_t EADDR;            /*!< MCE region end address register,               Address offset: 0x048 + 0x10 * (x-1) (x = 1 to 4) */
1800 } MCE_Region_TypeDef;
1801 
1802 typedef struct
1803 {
1804   __IO uint32_t CCCFGR;           /*!< MCE cipher context configuration register,     Address offset: 0x240 + 0x30 * (x-1) (x = 1 to 2) */
1805   __IO uint32_t CCNR0;            /*!< MCE cipher context nonce register 0,           Address offset: 0x244 + 0x30 * (x-1) (x = 1 to 2) */
1806   __IO uint32_t CCNR1;            /*!< MCE cipher context nonce register 1,           Address offset: 0x248 + 0x30 * (x-1) (x = 1 to 2) */
1807   __IO uint32_t CCKEYR0;          /*!< MCE cipher context key register 0,             Address offset: 0x24C + 0x30 * (x-1) (x = 1 to 2) */
1808   __IO uint32_t CCKEYR1;          /*!< MCE cipher context key register 1,             Address offset: 0x250 + 0x30 * (x-1) (x = 1 to 2) */
1809   __IO uint32_t CCKEYR2;          /*!< MCE cipher context key register 2,             Address offset: 0x254 + 0x30 * (x-1) (x = 1 to 2) */
1810   __IO uint32_t CCKEYR3;          /*!< MCE cipher context key register 3,             Address offset: 0x258 + 0x30 * (x-1) (x = 1 to 2) */
1811 } MCE_Context_TypeDef;
1812 
1813 typedef struct
1814 {
1815   __IO uint32_t CR;               /*!< MCE configuration register,                           Address offset: 0x000       */
1816   __IO uint32_t SR;               /*!< MCE status register,                                  Address offset: 0x004       */
1817   __IO uint32_t IASR;             /*!< MCE illegal access status register,                   Address offset: 0x008       */
1818   __IO uint32_t IACR;             /*!< MCE illegal access clear register,                    Address offset: 0x00C       */
1819   __IO uint32_t IAIER;            /*!< MCE illegal access interrupt enable register,         Address offset: 0x010       */
1820   uint32_t RESERVED0[4];          /*!< Reserved,                                             Address offset: 0x014-0x20  */
1821   __IO uint32_t IADDR;            /*!< MCE illegal address register,                         Address offset: 0x024       */
1822   uint32_t RESERVED1[118];        /*!< Reserved,                                             Address offset: 0x028-0x1FC */
1823   __IO uint32_t MKEYR0;           /*!< MCE master key register 0,                            Address offset: 0x200       */
1824   __IO uint32_t MKEYR1;           /*!< MCE master key register 1,                            Address offset: 0x204       */
1825   __IO uint32_t MKEYR2;           /*!< MCE master key register 2,                            Address offset: 0x208       */
1826   __IO uint32_t MKEYR3;           /*!< MCE master key register 3,                            Address offset: 0x20C       */
1827   __IO uint32_t MKEYR4;           /*!< MCE master key register 4,                            Address offset: 0x210       */
1828   __IO uint32_t MKEYR5;           /*!< MCE master key register 5,                            Address offset: 0x214       */
1829   __IO uint32_t MKEYR6;           /*!< MCE master key register 6,                            Address offset: 0x218       */
1830   __IO uint32_t MKEYR7;           /*!< MCE master key register 7,                            Address offset: 0x21C       */
1831   __IO uint32_t FMKEYR0;          /*!< MCE fast master key register 0,                       Address offset: 0x220       */
1832   __IO uint32_t FMKEYR1;          /*!< MCE fast master key register 1,                       Address offset: 0x224       */
1833   __IO uint32_t FMKEYR2;          /*!< MCE fast master key register 2,                       Address offset: 0x228       */
1834   __IO uint32_t FMKEYR3;          /*!< MCE fast master key register 3,                       Address offset: 0x22C       */
1835   __IO uint32_t FMKEYR4;          /*!< MCE fast master key register 4,                       Address offset: 0x230       */
1836   __IO uint32_t FMKEYR5;          /*!< MCE fast master key register 5,                       Address offset: 0x234       */
1837   __IO uint32_t FMKEYR6;          /*!< MCE fast master key register 6,                       Address offset: 0x238       */
1838   __IO uint32_t FMKEYR7;          /*!< MCE fast master key register 7,                       Address offset: 0x23C       */
1839 } MCE_TypeDef;
1840 
1841 
1842 
1843 /**
1844   * @brief ADF
1845   */
1846 typedef struct
1847 {
1848   __IO uint32_t GCR;            /*!< MDF Global Control register,             Address offset: 0x00  */
1849   __IO uint32_t CKGCR;          /*!< MDF Clock Generator Control Register,    Address offset: 0x04  */
1850   uint32_t      RESERVED1[6];   /*!< Reserved, 0x08-0x1C                                            */
1851   __IO uint32_t OR;             /*!< MDF  Option Register,                    Address offset: 0x20  */
1852 } MDF_TypeDef;
1853 
1854 /**
1855   * @brief ADF filter
1856   */
1857 typedef struct
1858 {
1859  __IO uint32_t SITFCR;         /*!< MDF Serial Interface Control Register,          Address offset: 0x80 */
1860  __IO uint32_t BSMXCR;         /*!< MDF Bitstream Matrix Control Register,          Address offset: 0x84 */
1861  __IO uint32_t DFLTCR;         /*!< MDF Digital Filter Control Register,            Address offset: 0x88 */
1862  __IO uint32_t DFLTCICR;       /*!< MDF MCIC Configuration Register,                Address offset: 0x8C */
1863  __IO uint32_t DFLTRSFR;       /*!< MDF Reshape Filter Configuration Register,      Address offset: 0x90 */
1864  __IO uint32_t DFLTINTR;       /*!< MDF Integrator Configuration Register,          Address offset: 0x94 */
1865  __IO uint32_t OLDCR;          /*!< MDF Out-Of Limit Detector Control Register,     Address offset: 0x98 */
1866  __IO uint32_t OLDTHLR;        /*!< MDF OLD Threshold Low Register,                 Address offset: 0x9C */
1867  __IO uint32_t OLDTHHR;        /*!< MDF OLD Threshold High Register,                Address offset: 0xA0 */
1868  __IO uint32_t DLYCR;          /*!< MDF Delay control Register,                     Address offset: 0xA4 */
1869  __IO uint32_t SCDCR;          /*!< MDF short circuit detector control Register,    Address offset: 0xA8 */
1870  __IO uint32_t DFLTIER;        /*!< MDF DFLT Interrupt enable Register,             Address offset: 0xAC */
1871  __IO uint32_t DFLTISR;        /*!< MDF DFLT Interrupt status Register,             Address offset: 0xB0 */
1872  __IO uint32_t OECCR;          /*!< MDF Offset Error Compensation Control Register, Address offset: 0xB4 */
1873  __IO uint32_t SADCR;          /*!< MDF SAD Control Register,                       Address offset: 0xB8 */
1874  __IO uint32_t SADCFGR;        /*!< MDF SAD configuration register,                 Address offset: 0xBC */
1875  __IO uint32_t SADSDLVR;       /*!< MDF SAD Sound level Register,                   Address offset: 0xC0 */
1876  __IO uint32_t SADANLVR;       /*!< MDF SAD Ambient Noise level Register,           Address offset: 0xC4 */
1877  uint32_t     RESERVED1[9];    /*!< Reserved, 0xC8-0xE8                                                  */
1878  __IO uint32_t SNPSDR;         /*!< MDF Snapshot Data Register,                     Address offset: 0xEC */
1879  __IO uint32_t DFLTDR;         /*!< MDF Digital Filter Data Register,               Address offset: 0xF0 */
1880 } MDF_Filter_TypeDef;
1881 
1882 
1883 /**
1884   * @brief MDIOS
1885   */
1886 
1887 typedef struct
1888 {
1889   __IO uint32_t CR;
1890   __IO uint32_t WRFR;
1891   __IO uint32_t CWRFR;
1892   __IO uint32_t RDFR;
1893   __IO uint32_t CRDFR;
1894   __IO uint32_t SR;
1895   __IO uint32_t CLRFR;
1896   uint32_t RESERVED[57];
1897   __IO uint32_t DINR0;
1898   __IO uint32_t DINR1;
1899   __IO uint32_t DINR2;
1900   __IO uint32_t DINR3;
1901   __IO uint32_t DINR4;
1902   __IO uint32_t DINR5;
1903   __IO uint32_t DINR6;
1904   __IO uint32_t DINR7;
1905   __IO uint32_t DINR8;
1906   __IO uint32_t DINR9;
1907   __IO uint32_t DINR10;
1908   __IO uint32_t DINR11;
1909   __IO uint32_t DINR12;
1910   __IO uint32_t DINR13;
1911   __IO uint32_t DINR14;
1912   __IO uint32_t DINR15;
1913   __IO uint32_t DINR16;
1914   __IO uint32_t DINR17;
1915   __IO uint32_t DINR18;
1916   __IO uint32_t DINR19;
1917   __IO uint32_t DINR20;
1918   __IO uint32_t DINR21;
1919   __IO uint32_t DINR22;
1920   __IO uint32_t DINR23;
1921   __IO uint32_t DINR24;
1922   __IO uint32_t DINR25;
1923   __IO uint32_t DINR26;
1924   __IO uint32_t DINR27;
1925   __IO uint32_t DINR28;
1926   __IO uint32_t DINR29;
1927   __IO uint32_t DINR30;
1928   __IO uint32_t DINR31;
1929   __IO uint32_t DOUTR0;
1930   __IO uint32_t DOUTR1;
1931   __IO uint32_t DOUTR2;
1932   __IO uint32_t DOUTR3;
1933   __IO uint32_t DOUTR4;
1934   __IO uint32_t DOUTR5;
1935   __IO uint32_t DOUTR6;
1936   __IO uint32_t DOUTR7;
1937   __IO uint32_t DOUTR8;
1938   __IO uint32_t DOUTR9;
1939   __IO uint32_t DOUTR10;
1940   __IO uint32_t DOUTR11;
1941   __IO uint32_t DOUTR12;
1942   __IO uint32_t DOUTR13;
1943   __IO uint32_t DOUTR14;
1944   __IO uint32_t DOUTR15;
1945   __IO uint32_t DOUTR16;
1946   __IO uint32_t DOUTR17;
1947   __IO uint32_t DOUTR18;
1948   __IO uint32_t DOUTR19;
1949   __IO uint32_t DOUTR20;
1950   __IO uint32_t DOUTR21;
1951   __IO uint32_t DOUTR22;
1952   __IO uint32_t DOUTR23;
1953   __IO uint32_t DOUTR24;
1954   __IO uint32_t DOUTR25;
1955   __IO uint32_t DOUTR26;
1956   __IO uint32_t DOUTR27;
1957   __IO uint32_t DOUTR28;
1958   __IO uint32_t DOUTR29;
1959   __IO uint32_t DOUTR30;
1960   __IO uint32_t DOUTR31;
1961 } MDIOS_TypeDef;
1962 
1963 /**
1964   * @brief PSSI
1965   */
1966 typedef struct
1967 {
1968   __IO uint32_t CR;             /*!< PSSI control register,                 Address offset: 0x000 */
1969   __IO uint32_t SR;             /*!< PSSI status register,                  Address offset: 0x004 */
1970   __IO uint32_t RIS;            /*!< PSSI raw interrupt status register,    Address offset: 0x008 */
1971   __IO uint32_t IER;            /*!< PSSI interrupt enable register,        Address offset: 0x00C */
1972   __IO uint32_t MIS;            /*!< PSSI masked interrupt status register, Address offset: 0x010 */
1973   __IO uint32_t ICR;            /*!< PSSI interrupt clear register,         Address offset: 0x014 */
1974   __IO uint32_t RESERVED1[4];   /*!< Reserved,                                      0x018 - 0x024 */
1975   __IO uint32_t DR;             /*!< PSSI data register,                    Address offset: 0x028 */
1976 } PSSI_TypeDef;
1977 
1978 /**
1979   * @brief Power Control
1980   */
1981 typedef struct
1982 {
1983   __IO uint32_t CR1;             /*!< PWR Control register 1                           Address offset: 0x000 */
1984   __IO uint32_t CR2;             /*!< PWR Control Register 2                           Address offset: 0x004 */
1985   __IO uint32_t CR3;             /*!< PWR Control Register 3                           Address offset: 0x008 */
1986   __IO uint32_t CR4;             /*!< PWR Control Register 4                           Address offset: 0x00C */
1987        uint32_t RESERVED0[4];    /*!< Reserved                                         Address offset: 0x010-0x01C */
1988   __IO uint32_t VOSCR;           /*!< PWR Voltage scaling control register             Address offset: 0x020 */
1989   __IO uint32_t BDCR1;           /*!< PWR Backup domain control register 1             Address offset: 0x024 */
1990   __IO uint32_t BDCR2;           /*!< PWR Backup domain control register 2             Address offset: 0x028 */
1991   __IO uint32_t DBPCR;           /*!< PWR Disable backup protection control register   Address offset: 0x02C */
1992   __IO uint32_t CPUCR;           /*!< PWR CPU control register                         Address offset: 0x030 */
1993   __IO uint32_t SVMCR1;          /*!< PWR Supply voltage monitoring control register 1 Address offset: 0x034 */
1994   __IO uint32_t SVMCR2;          /*!< PWR Supply voltage monitoring control register 2 Address offset: 0x038 */
1995   __IO uint32_t SVMCR3;          /*!< PWR Supply voltage monitoring control register 3 Address offset: 0x03C */
1996        uint32_t RESERVED1[4];    /*!< Reserved                                         Address offset: 0x040-0x04C */
1997   __IO uint32_t WKUPCR;          /*!< PWR Wakeup control register 1                    Address offset: 0x050 */
1998   __IO uint32_t WKUPSR;          /*!< PWR Wakeup control register 2                    Address offset: 0x054 */
1999   __IO uint32_t WKUPEPR;         /*!< PWR Wakeup control register 3                    Address offset: 0x058 */
2000        uint32_t RESERVED2[5];    /*!< Reserved                                         Address offset: 0x05C-0x06C */
2001   __IO uint32_t SECCFGR;         /*!< PWR Security configuration register              Address offset: 0x070 */
2002   __IO uint32_t PRIVCFGR;        /*!< PWR Privilege configuration register             Address offset: 0x074 */
2003 } PWR_TypeDef;
2004 
2005 /**
2006   * @brief PKA
2007   */
2008 typedef struct
2009 {
2010   __IO uint32_t CR;            /*!< PKA control register,             Address offset: 0x00 */
2011   __IO uint32_t SR;            /*!< PKA status register,              Address offset: 0x04 */
2012   __IO uint32_t CLRFR;         /*!< PKA clear flag register,          Address offset: 0x08 */
2013   uint32_t Reserved[253];      /*!< Reserved memory area              Address offset: 0x0C  -> 0x03FC */
2014   __IO uint32_t RAM[1334];     /*!< PKA RAM                           Address offset: 0x400 -> 0x18D4 */
2015 } PKA_TypeDef;
2016 
2017 /**
2018   * @brief RAMs configuration controller
2019   */
2020 typedef struct
2021 {
2022   __IO uint32_t CR;          /*!< Control Register,                    Address offset: 0x00 */
2023   __IO uint32_t IER;         /*!< Interrupt Enable Register,           Address offset: 0x04 */
2024   __IO uint32_t ISR;         /*!< Interrupt Status Register,           Address offset: 0x08 */
2025   __IO uint32_t ESEAR;       /*!< ECC Single Error Address Register,   Address offset: 0x0C */
2026   __IO uint32_t EDEAR;       /*!< ECC Double Error Address Register,   Address offset: 0x10 */
2027   __IO uint32_t ICR;         /*!< Interrupt Clear Register,            Address offset: 0x14 */
2028   uint32_t      RESERVED[3]; /*!< Reserved,                       Address offset: 0x18-0x20 */
2029   __IO uint32_t ECCKEYR;     /*!< RAM ECC Key Register,                Address offset: 0x24 */
2030   __IO uint32_t ERKEYR;      /*!< RAM Erase Key Register,              Address offset: 0x28 */
2031 }RAMCFG_TypeDef;
2032 
2033 /**
2034   * @brief Reset and Clock Control
2035   */
2036 
2037 typedef struct
2038 {
2039   __IO uint32_t CR;               /*!< RCC control register                                           Address offset: 0x0000 */
2040   __IO uint32_t SR;               /*!< RCC status register                                            Address offset: 0x0004 */
2041   __IO uint32_t STOPCR;           /*!< RCC Stop mode control register                                 Address offset: 0x0008 */
2042        uint32_t RESERVED0[5];     /*!< Reserved                                                       Address offset: 0x000C-0x001C */
2043   __IO uint32_t CFGR1;            /*!< RCC configuration register 1                                   Address offset: 0x0020 */
2044   __IO uint32_t CFGR2;            /*!< RCC configuration register 2                                   Address offset: 0x0024 */
2045        uint32_t RESERVED1;        /*!< Reserved                                                       Address offset: 0x0028 */
2046   __IO uint32_t BDCR;             /*!< RCC backup domain protection register                          Address offset: 0x002C */
2047   __IO uint32_t HWRSR;            /*!< RCC reset status register for hardware                         Address offset: 0x0030 */
2048   __IO uint32_t RSR;              /*!< RCC reset register                                             Address offset: 0x0034 */
2049        uint32_t RESERVED2[2];     /*!< Reserved                                                       Address offset: 0x0038-0x003C */
2050   __IO uint32_t LSECFGR;          /*!< RCC LSE configuration register                                 Address offset: 0x0040 */
2051   __IO uint32_t MSICFGR;          /*!< RCC MSI configuration register                                 Address offset: 0x0044 */
2052   __IO uint32_t HSICFGR;          /*!< RCC HSI configuration register                                 Address offset: 0x0048 */
2053   __IO uint32_t HSIMCR;           /*!< RCC HSI Monitor control register                               Address offset: 0x004C */
2054   __IO uint32_t HSIMSR;           /*!< RCC HSI Monitor status register                                Address offset: 0x0050 */
2055   __IO uint32_t HSECFGR;          /*!< RCC HSE configuration register                                 Address offset: 0x0054 */
2056        uint32_t RESERVED3[10];    /*!< Reserved                                                       Address offset: 0x0058-0x007C */
2057   __IO uint32_t PLL1CFGR1;        /*!< RCC PLL1 configuration register 1                              Address offset: 0x0080 */
2058   __IO uint32_t PLL1CFGR2;        /*!< RCC PLL1 configuration register 2                              Address offset: 0x0084 */
2059   __IO uint32_t PLL1CFGR3;        /*!< RCC PLL1 configuration register 3                              Address offset: 0x0088 */
2060        uint32_t RESERVED4;        /*!< Reserved                                                       Address offset: 0x008C */
2061   __IO uint32_t PLL2CFGR1;        /*!< RCC PLL2 configuration register 1                              Address offset: 0x0090 */
2062   __IO uint32_t PLL2CFGR2;        /*!< RCC PLL2 configuration register 2                              Address offset: 0x0094 */
2063   __IO uint32_t PLL2CFGR3;        /*!< RCC PLL2 configuration register 3                              Address offset: 0x0098 */
2064        uint32_t RESERVED5;        /*!< Reserved                                                       Address offset: 0x009C */
2065   __IO uint32_t PLL3CFGR1;        /*!< RCC PLL3 configuration register 1                              Address offset: 0x00A0 */
2066   __IO uint32_t PLL3CFGR2;        /*!< RCC PLL3 configuration register 2                              Address offset: 0x00A4 */
2067   __IO uint32_t PLL3CFGR3;        /*!< RCC PLL3 configuration register 3                              Address offset: 0x00A8 */
2068        uint32_t RESERVED6;        /*!< Reserved                                                       Address offset: 0x00AC */
2069   __IO uint32_t PLL4CFGR1;        /*!< RCC PLL4 configuration register 1                              Address offset: 0x00B0 */
2070   __IO uint32_t PLL4CFGR2;        /*!< RCC PLL4 configuration register 2                              Address offset: 0x00B4 */
2071   __IO uint32_t PLL4CFGR3;        /*!< RCC PLL4 configuration register 3                              Address offset: 0x00B8 */
2072        uint32_t RESERVED7[2];     /*!< Reserved                                                       Address offset: 0x00BC-0x00C0 */
2073   __IO uint32_t IC1CFGR;          /*!< RCC IC1 configuration register                                 Address offset: 0x00C4 */
2074   __IO uint32_t IC2CFGR;          /*!< RCC IC2 configuration register                                 Address offset: 0x00C8 */
2075   __IO uint32_t IC3CFGR;          /*!< RCC IC3 configuration register                                 Address offset: 0x00CC */
2076   __IO uint32_t IC4CFGR;          /*!< RCC IC4 configuration register                                 Address offset: 0x00D0 */
2077   __IO uint32_t IC5CFGR;          /*!< RCC IC5 configuration register                                 Address offset: 0x00D4 */
2078   __IO uint32_t IC6CFGR;          /*!< RCC IC6 configuration register                                 Address offset: 0x00D8 */
2079   __IO uint32_t IC7CFGR;          /*!< RCC IC7 configuration register                                 Address offset: 0x00DC */
2080   __IO uint32_t IC8CFGR;          /*!< RCC IC8 configuration register                                 Address offset: 0x00E0 */
2081   __IO uint32_t IC9CFGR;          /*!< RCC IC9 configuration register                                 Address offset: 0x00E4 */
2082   __IO uint32_t IC10CFGR;         /*!< RCC IC10 configuration register                                Address offset: 0x00E8 */
2083   __IO uint32_t IC11CFGR;         /*!< RCC IC11 configuration register                                Address offset: 0x00EC */
2084   __IO uint32_t IC12CFGR;         /*!< RCC IC12 configuration register                                Address offset: 0x00F0 */
2085   __IO uint32_t IC13CFGR;         /*!< RCC IC13 configuration register                                Address offset: 0x00F4 */
2086   __IO uint32_t IC14CFGR;         /*!< RCC IC14 configuration register                                Address offset: 0x00F8 */
2087   __IO uint32_t IC15CFGR;         /*!< RCC IC15 configuration register                                Address offset: 0x00FC */
2088   __IO uint32_t IC16CFGR;         /*!< RCC IC16 configuration register                                Address offset: 0x0100 */
2089   __IO uint32_t IC17CFGR;         /*!< RCC IC17 configuration register                                Address offset: 0x0104 */
2090   __IO uint32_t IC18CFGR;         /*!< RCC IC18 configuration register                                Address offset: 0x0108 */
2091   __IO uint32_t IC19CFGR;         /*!< RCC IC19 configuration register                                Address offset: 0x010C */
2092   __IO uint32_t IC20CFGR;         /*!< RCC IC20 configuration register                                Address offset: 0x0110 */
2093        uint32_t RESERVED8[4];     /*!< Reserved                                                       Address offset: 0x0114-0x0120 */
2094   __IO uint32_t CIER;             /*!< RCC clock-source interrupt enable register                     Address offset: 0x0124 */
2095   __IO uint32_t CIFR;             /*!< RCC clock-source interrupt flag register                       Address offset: 0x0128 */
2096   __IO uint32_t CICR;             /*!< RCC clock-source interrupt clear register                      Address offset: 0x012C */
2097        uint32_t RESERVED9[5];     /*!< Reserved                                                       Address offset: 0x0130-0x0140 */
2098   __IO uint32_t CCIPR1;           /*!< RCC clock configuration for independent peripheral register 1  Address offset: 0x0144 */
2099   __IO uint32_t CCIPR2;           /*!< RCC clock configuration for independent peripheral register 2  Address offset: 0x0148 */
2100   __IO uint32_t CCIPR3;           /*!< RCC clock configuration for independent peripheral register 3  Address offset: 0x014C */
2101   __IO uint32_t CCIPR4;           /*!< RCC clock configuration for independent peripheral register 4  Address offset: 0x0150 */
2102   __IO uint32_t CCIPR5;           /*!< RCC clock configuration for independent peripheral register 5  Address offset: 0x0154 */
2103   __IO uint32_t CCIPR6;           /*!< RCC clock configuration for independent peripheral register 6  Address offset: 0x0158 */
2104   __IO uint32_t CCIPR7;           /*!< RCC clock configuration for independent peripheral register 7  Address offset: 0x015C */
2105   __IO uint32_t CCIPR8;           /*!< RCC clock configuration for independent peripheral register 8  Address offset: 0x0160 */
2106   __IO uint32_t CCIPR9;           /*!< RCC clock configuration for independent peripheral register 9  Address offset: 0x0164 */
2107        uint32_t RESERVED10[2];    /*!< Reserved                                                       Address offset: 0x0168-0x016C */
2108   __IO uint32_t CCIPR12;          /*!< RCC clock configuration for independent peripheral register 12 Address offset: 0x0170 */
2109   __IO uint32_t CCIPR13;          /*!< RCC clock configuration for independent peripheral register 13 Address offset: 0x0174 */
2110   __IO uint32_t CCIPR14;          /*!< RCC clock configuration for independent peripheral register 14 Address offset: 0x0178 */
2111        uint32_t RESERVED11[35];   /*!< Reserved                                                       Address offset: 0x017C-0x0204 */
2112   __IO uint32_t MISCRSTR;         /*!< RCC miscellaneous configurations reset register                Address offset: 0x0208 */
2113   __IO uint32_t MEMRSTR;          /*!< RCC embedded memories reset register                           Address offset: 0x020C */
2114   __IO uint32_t AHB1RSTR;         /*!< RCC AHB1 reset register                                        Address offset: 0x0210 */
2115   __IO uint32_t AHB2RSTR;         /*!< RCC AHB2 reset register                                        Address offset: 0x0214 */
2116   __IO uint32_t AHB3RSTR;         /*!< RCC AHB3 reset register                                        Address offset: 0x0218 */
2117   __IO uint32_t AHB4RSTR;         /*!< RCC AHB4 reset register                                        Address offset: 0x021C */
2118   __IO uint32_t AHB5RSTR;         /*!< RCC AHB5 reset register                                        Address offset: 0x0220 */
2119   __IO uint32_t APB1RSTR1;        /*!< RCC APB1 reset register 1                                      Address offset: 0x0224 */
2120   __IO uint32_t APB1RSTR2;        /*!< RCC APB1 reset register 2                                      Address offset: 0x0228 */
2121   __IO uint32_t APB2RSTR;         /*!< RCC APB2 reset register                                        Address offset: 0x022C */
2122        uint32_t RESERVED12;       /*!< Reserved                                                       Address offset: 0x0230 */
2123   __IO uint32_t APB4RSTR1;        /*!< RCC APB4 reset register 1                                      Address offset: 0x0234 */
2124   __IO uint32_t APB4RSTR2;        /*!< RCC APB4 reset register 2                                      Address offset: 0x0238 */
2125   __IO uint32_t APB5RSTR;         /*!< RCC APB5 reset register                                        Address offset: 0x023C */
2126   __IO uint32_t DIVENR;           /*!< RCC IC dividers enable register                                Address offset: 0x0240 */
2127   __IO uint32_t BUSENR;           /*!< RCC embedded buses enable register                             Address offset: 0x0244 */
2128   __IO uint32_t MISCENR;          /*!< RCC miscellaneous configurations enable register               Address offset: 0x0248 */
2129   __IO uint32_t MEMENR;           /*!< RCC embedded memories enable register                          Address offset: 0x024C */
2130   __IO uint32_t AHB1ENR;          /*!< RCC AHB1 enable register                                       Address offset: 0x0250 */
2131   __IO uint32_t AHB2ENR;          /*!< RCC AHB2 enable register                                       Address offset: 0x0254 */
2132   __IO uint32_t AHB3ENR;          /*!< RCC AHB3 enable register                                       Address offset: 0x0258 */
2133   __IO uint32_t AHB4ENR;          /*!< RCC AHB4 enable register                                       Address offset: 0x025C */
2134   __IO uint32_t AHB5ENR;          /*!< RCC AHB5 enable register                                       Address offset: 0x0260 */
2135   __IO uint32_t APB1ENR1;         /*!< RCC APB1 enable register 1                                     Address offset: 0x0264 */
2136   __IO uint32_t APB1ENR2;         /*!< RCC APB1 enable register 2                                     Address offset: 0x0268 */
2137   __IO uint32_t APB2ENR;          /*!< RCC APB2 enable register                                       Address offset: 0x026C */
2138   __IO uint32_t APB3ENR;          /*!< RCC APB3 enable register                                       Address offset: 0x0270 */
2139   __IO uint32_t APB4ENR1;         /*!< RCC APB4 enable register 1                                     Address offset: 0x0274 */
2140   __IO uint32_t APB4ENR2;         /*!< RCC APB4 enable register 2                                     Address offset: 0x0278 */
2141   __IO uint32_t APB5ENR;          /*!< RCC APB5 enable register                                       Address offset: 0x027C */
2142        uint32_t RESERVED13;       /*!< Reserved                                                       Address offset: 0x0280 */
2143   __IO uint32_t BUSLPENR;         /*!< RCC embedded buses sleep enable register                       Address offset: 0x0284 */
2144   __IO uint32_t MISCLPENR;        /*!< RCC miscellaneous configurations sleep enable register         Address offset: 0x0288 */
2145   __IO uint32_t MEMLPENR;         /*!< RCC embedded memories sleep enable register                    Address offset: 0x028C */
2146   __IO uint32_t AHB1LPENR;        /*!< RCC AHB1 sleep enable register                                 Address offset: 0x0290 */
2147   __IO uint32_t AHB2LPENR;        /*!< RCC AHB2 sleep enable register                                 Address offset: 0x0294 */
2148   __IO uint32_t AHB3LPENR;        /*!< RCC AHB3 sleep enable register                                 Address offset: 0x0298 */
2149   __IO uint32_t AHB4LPENR;        /*!< RCC AHB4 sleep enable register                                 Address offset: 0x029C */
2150   __IO uint32_t AHB5LPENR;        /*!< RCC AHB5 sleep enable register                                 Address offset: 0x02A0 */
2151   __IO uint32_t APB1LPENR1;       /*!< RCC APB1 sleep enable register 1                               Address offset: 0x02A4 */
2152   __IO uint32_t APB1LPENR2;       /*!< RCC APB1 sleep enable register 2                               Address offset: 0x02A8 */
2153   __IO uint32_t APB2LPENR;        /*!< RCC APB2 sleep enable register                                 Address offset: 0x02AC */
2154   __IO uint32_t APB3LPENR;        /*!< RCC APB3 sleep enable register                                 Address offset: 0x02B0 */
2155   __IO uint32_t APB4LPENR1;       /*!< RCC APB4 sleep enable register 1                               Address offset: 0x02B4 */
2156   __IO uint32_t APB4LPENR2;       /*!< RCC APB4 sleep enable register 2                               Address offset: 0x02B8 */
2157   __IO uint32_t APB5LPENR;        /*!< RCC APB5 sleep enable register                                 Address offset: 0x02BC */
2158        uint32_t RESERVED14[99];   /*!< Reserved                                                       Address offset: 0x02C0-0x0448 */
2159   __IO uint32_t RDCR;             /*!< RCC reset duration control register                            Address offset: 0x044C */
2160        uint32_t RESERVED15[204];  /*!< Reserved                                                       Address offset: 0x0450-0x077C */
2161   __IO uint32_t SECCFGR0;         /*!< RCC oscillator secure configuration register 0                 Address offset: 0x0780 */
2162   __IO uint32_t PRIVCFGR0;        /*!< RCC oscillator privilege configuration register 0              Address offset: 0x0784 */
2163   __IO uint32_t LOCKCFGR0;        /*!< RCC oscillator lock configuration register 0                   Address offset: 0x0788 */
2164   __IO uint32_t PUBCFGR0;         /*!< RCC oscillator public configuration register 0                 Address offset: 0x078C */
2165   __IO uint32_t SECCFGR1;         /*!< RCC PLL secure configuration register 1                        Address offset: 0x0790 */
2166   __IO uint32_t PRIVCFGR1;        /*!< RCC PLL privilege configuration register 1                     Address offset: 0x0794 */
2167   __IO uint32_t LOCKCFGR1;        /*!< RCC PLL lock configuration register 1                          Address offset: 0x0798 */
2168   __IO uint32_t PUBCFGR1;         /*!< RCC PLL public configuration register 1                        Address offset: 0x079C */
2169   __IO uint32_t SECCFGR2;         /*!< RCC divider secure configuration register 2                    Address offset: 0x07A0 */
2170   __IO uint32_t PRIVCFGR2;        /*!< RCC divider privilege configuration register 2                 Address offset: 0x07A4 */
2171   __IO uint32_t LOCKCFGR2;        /*!< RCC divider lock configuration register 2                      Address offset: 0x07A8 */
2172   __IO uint32_t PUBCFGR2;         /*!< RCC divider public configuration register 2                    Address offset: 0x07AC */
2173   __IO uint32_t SECCFGR3;         /*!< RCC system secure configuration register 3                     Address offset: 0x07B0 */
2174   __IO uint32_t PRIVCFGR3;        /*!< RCC system privilege configuration register 3                  Address offset: 0x07B4 */
2175   __IO uint32_t LOCKCFGR3;        /*!< RCC system lock configuration register 3                       Address offset: 0x07B8 */
2176   __IO uint32_t PUBCFGR3;         /*!< RCC system public configuration register 3                     Address offset: 0x07BC */
2177   __IO uint32_t SECCFGR4;         /*!< RCC bus secure configuration register 4                        Address offset: 0x07C0 */
2178   __IO uint32_t PRIVCFGR4;        /*!< RCC bus privilege configuration register 4                     Address offset: 0x07C4 */
2179   __IO uint32_t LOCKCFGR4;        /*!< RCC bus lock configuration register 4                          Address offset: 0x07C8 */
2180   __IO uint32_t PUBCFGR4;         /*!< RCC bus public configuration register 4                        Address offset: 0x07CC */
2181   __IO uint32_t PUBCFGR5;         /*!< RCC bus public configuration register 4                        Address offset: 0x07D0 */
2182        uint32_t RESERVED16[11];   /*!< Reserved                                                       Address offset: 0x07D4-0x07FC */
2183   __IO uint32_t CSR;              /*!< RCC control Set register                                       Address offset: 0x0800 */
2184        uint32_t RESERVED17;       /*!< Reserved                                                       Address offset: 0x0804 */
2185   __IO uint32_t STOPCSR;          /*!< RCC STOPCSR configuration register                             Address offset: 0x0808 */
2186        uint32_t RESERVED18[127];  /*!< Reserved                                                       Address offset: 0x080C-0x0A00 */
2187   __IO uint32_t MISCRSTSR;        /*!< RCC miscellaneous reset register                               Address offset: 0x0A08 */
2188   __IO uint32_t MEMRSTSR;         /*!< RCC memory reset register                                      Address offset: 0x0A0C */
2189   __IO uint32_t AHB1RSTSR;        /*!< RCC AHB1 reset register                                        Address offset: 0x0A10 */
2190   __IO uint32_t AHB2RSTSR;        /*!< RCC AHB2 reset register                                        Address offset: 0x0A14 */
2191   __IO uint32_t AHB3RSTSR;        /*!< RCC AHB3 reset register                                        Address offset: 0x0A18 */
2192   __IO uint32_t AHB4RSTSR;        /*!< RCC AHB4 reset register                                        Address offset: 0x0A1C */
2193   __IO uint32_t AHB5RSTSR;        /*!< RCC AHB5 reset register                                        Address offset: 0x0A20 */
2194   __IO uint32_t APB1RSTSR1;       /*!< RCC APB1 reset register 1                                      Address offset: 0x0A24 */
2195   __IO uint32_t APB1RSTSR2;       /*!< RCC APB1 reset register 2                                      Address offset: 0x0A28 */
2196   __IO uint32_t APB2RSTSR;        /*!< RCC APB2 reset register                                        Address offset: 0x0A2C */
2197        uint32_t RESERVED19;       /*!< Reserved                                                       Address offset: 0x0A30 */
2198   __IO uint32_t APB4RSTSR1;       /*!< RCC APB4 reset register 1                                      Address offset: 0x0A34 */
2199   __IO uint32_t APB4RSTSR2;       /*!< RCC APB4 reset register 2                                      Address offset: 0x0A38 */
2200   __IO uint32_t APB5RSTSR;        /*!< RCC APB5 reset register                                        Address offset: 0x0A3C */
2201   __IO uint32_t DIVENSR;          /*!< RCC divider enable register                                    Address offset: 0x0A40 */
2202   __IO uint32_t BUSENSR;          /*!< RCC bus enable register                                        Address offset: 0x0A44 */
2203   __IO uint32_t MISCENSR;         /*!< RCC miscellaneous enable register                              Address offset: 0x0A48 */
2204   __IO uint32_t MEMENSR;          /*!< RCC memory enable register                                     Address offset: 0x0A4C */
2205   __IO uint32_t AHB1ENSR;         /*!< RCC AHB1 enable register                                       Address offset: 0x0A50 */
2206   __IO uint32_t AHB2ENSR;         /*!< RCC AHB2 enable register                                       Address offset: 0x0A54 */
2207   __IO uint32_t AHB3ENSR;         /*!< RCC AHB3 enable register                                       Address offset: 0x0A58 */
2208   __IO uint32_t AHB4ENSR;         /*!< RCC AHB4 enable register                                       Address offset: 0x0A5C */
2209   __IO uint32_t AHB5ENSR;         /*!< RCC AHB5 enable register                                       Address offset: 0x0A60 */
2210   __IO uint32_t APB1ENSR1;        /*!< RCC APB1 enable register 1                                     Address offset: 0x0A64 */
2211   __IO uint32_t APB1ENSR2;        /*!< RCC APB1 enable register 2                                     Address offset: 0x0A68 */
2212   __IO uint32_t APB2ENSR;         /*!< RCC APB2 enable register                                       Address offset: 0x0A6C */
2213   __IO uint32_t APB3ENSR;         /*!< RCC APB3 enable register                                       Address offset: 0x0A70 */
2214   __IO uint32_t APB4ENSR1;        /*!< RCC APB4 enable register 1                                     Address offset: 0x0A74 */
2215   __IO uint32_t APB4ENSR2;        /*!< RCC APB4 enable register 2                                     Address offset: 0x0A78 */
2216   __IO uint32_t APB5ENSR;         /*!< RCC APB5 enable register                                       Address offset: 0x0A7C */
2217        uint32_t RESERVED20;       /*!< Reserved                                                       Address offset: 0x0A80 */
2218   __IO uint32_t BUSLPENSR;        /*!< RCC bus sleep enable register                                  Address offset: 0x0A84 */
2219   __IO uint32_t MISCLPENSR;       /*!< RCC miscellaneous sleep enable register                        Address offset: 0x0A88 */
2220   __IO uint32_t MEMLPENSR;        /*!< RCC memory sleep enable register                               Address offset: 0x0A8C */
2221   __IO uint32_t AHB1LPENSR;       /*!< RCC AHB1 sleep enable register                                 Address offset: 0x0A90 */
2222   __IO uint32_t AHB2LPENSR;       /*!< RCC AHB2 sleep enable register                                 Address offset: 0x0A94 */
2223   __IO uint32_t AHB3LPENSR;       /*!< RCC AHB3 sleep enable register                                 Address offset: 0x0A98 */
2224   __IO uint32_t AHB4LPENSR;       /*!< RCC AHB4 sleep enable register                                 Address offset: 0x0A9C */
2225   __IO uint32_t AHB5LPENSR;       /*!< RCC AHB5 sleep enable register                                 Address offset: 0x0AA0 */
2226   __IO uint32_t APB1LPENSR1;      /*!< RCC APB1 sleep enable register 1                               Address offset: 0x0AA4 */
2227   __IO uint32_t APB1LPENSR2;      /*!< RCC APB1 sleep enable register 2                               Address offset: 0x0AA8 */
2228   __IO uint32_t APB2LPENSR;       /*!< RCC APB2 sleep enable register                                 Address offset: 0x0AAC */
2229   __IO uint32_t APB3LPENSR;       /*!< RCC APB3 sleep enable register                                 Address offset: 0x0AB0 */
2230   __IO uint32_t APB4LPENSR1;      /*!< RCC APB4 sleep enable register 1                               Address offset: 0x0AB4 */
2231   __IO uint32_t APB4LPENSR2;      /*!< RCC APB4 sleep enable register 2                               Address offset: 0x0AB8 */
2232   __IO uint32_t APB5LPENSR;       /*!< RCC APB5 sleep enable register                                 Address offset: 0x0ABC */
2233        uint32_t RESERVED21[305];  /*!< Reserved                                                       Address offset: 0x0AC0-0x0F80 */
2234   __IO uint32_t PRIVCFGSR0;       /*!< RCC oscillator privilege configuration set register 0          Address offset: 0x0F84 */
2235        uint32_t RESERVED22;       /*!< Reserved                                                       Address offset: 0x0F88 */
2236   __IO uint32_t PUBCFGSR0;        /*!< RCC oscillator public configuration set register 0             Address offset: 0x0F8C */
2237        uint32_t RESERVED23;       /*!< Reserved                                                       Address offset: 0x0F90 */
2238   __IO uint32_t PRIVCFGSR1;       /*!< RCC PLL privilege configuration set register 1                 Address offset: 0x0F94 */
2239        uint32_t RESERVED24;       /*!< Reserved                                                       Address offset: 0x0F98 */
2240   __IO uint32_t PUBCFGSR1;        /*!< RCC PLL public configuration set register 1                    Address offset: 0x0F9C */
2241        uint32_t RESERVED25;       /*!< Reserved                                                       Address offset: 0x0FA0 */
2242   __IO uint32_t PRIVCFGSR2;       /*!< RCC divider privilege configuration set register 2             Address offset: 0x0FA4 */
2243        uint32_t RESERVED26;       /*!< Reserved                                                       Address offset: 0x0FA8 */
2244   __IO uint32_t PUBCFGSR2;        /*!< RCC divider public configuration set register 2                Address offset: 0x0FAC */
2245        uint32_t RESERVED27;       /*!< Reserved                                                       Address offset: 0x0FB0 */
2246   __IO uint32_t PRIVCFGSR3;       /*!< RCC system privilege configuration set register 3              Address offset: 0x0FB4 */
2247        uint32_t RESERVED28;       /*!< Reserved                                                       Address offset: 0x0FB8 */
2248   __IO uint32_t PUBCFGSR3;        /*!< RCC system public configuration set register 3                 Address offset: 0x0FBC */
2249        uint32_t RESERVED29;       /*!< Reserved                                                       Address offset: 0x0FC0 */
2250   __IO uint32_t PRIVCFGSR4;       /*!< RCC privilege configuration set register 4                     Address offset: 0x0FC4 */
2251        uint32_t RESERVED30;       /*!< Reserved                                                       Address offset: 0x0FC8 */
2252   __IO uint32_t PUBCFGSR4;        /*!< RCC public configuration set register 4                            Address offset: 0x0FCC */
2253   __IO uint32_t PUBCFGSR5;        /*!< RCC public configuration set register 5                            Address offset: 0x0FD0 */
2254        uint32_t RESERVED31[11];   /*!< Reserved                                                       Address offset: 0x0FD4-0x0FFC */
2255   __IO uint32_t CCR;              /*!< RCC control clear register                                     Address offset: 0x1000 */
2256        uint32_t RESERVED32;       /*!< Reserved                                                       Address offset: 0x1004 */
2257   __IO uint32_t STOPCCR;          /*!< RCC Stop mode configuration clear register                     Address offset: 0x1008 */
2258        uint32_t RESERVED33[127];  /*!< Reserved                                                       Address offset: 0x100C-0x1200 */
2259   __IO uint32_t MISCRSTCR;        /*!< RCC miscellaneous reset clear register                         Address offset: 0x1208 */
2260   __IO uint32_t MEMRSTCR;         /*!< RCC memory reset clear register                                Address offset: 0x120C */
2261   __IO uint32_t AHB1RSTCR;        /*!< RCC AHB1 reset clear register                                  Address offset: 0x1210 */
2262   __IO uint32_t AHB2RSTCR;        /*!< RCC AHB2 reset clear register                                  Address offset: 0x1214 */
2263   __IO uint32_t AHB3RSTCR;        /*!< RCC AHB3 reset r clear register                                Address offset: 0x1218 */
2264   __IO uint32_t AHB4RSTCR;        /*!< RCC AHB4 reset clear register                                  Address offset: 0x121C */
2265   __IO uint32_t AHB5RSTCR;        /*!< RCC AHB5 reset clear register                                  Address offset: 0x1220 */
2266   __IO uint32_t APB1RSTCR1;       /*!< RCC APB1 reset clear register 1                                Address offset: 0x1224 */
2267   __IO uint32_t APB1RSTCR2;       /*!< RCC APB1 reset clear register 2                                Address offset: 0x1228 */
2268   __IO uint32_t APB2RSTCR;        /*!< RCC APB2 reset clear register                                  Address offset: 0x122C */
2269        uint32_t RESERVED34;       /*!< Reserved                                                       Address offset: 0x1230 */
2270   __IO uint32_t APB4RSTCR1;       /*!< RCC APB4 reset clear register 1                                Address offset: 0x1234 */
2271   __IO uint32_t APB4RSTCR2;       /*!< RCC APB4 reset clear register 2                                Address offset: 0x1238 */
2272   __IO uint32_t APB5RSTCR;        /*!< RCC APB5 reset clear register                                  Address offset: 0x123C */
2273   __IO uint32_t DIVENCR;          /*!< RCC divider enable clear register                              Address offset: 0x1240 */
2274   __IO uint32_t BUSENCR;          /*!< RCC bus enable clear register                                  Address offset: 0x1244 */
2275   __IO uint32_t MISCENCR;         /*!< RCC miscellaneous enable clear register                        Address offset: 0x1248 */
2276   __IO uint32_t MEMENCR;          /*!< RCC memory enable clear register                               Address offset: 0x124C */
2277   __IO uint32_t AHB1ENCR;         /*!< RCC AHB1 enable clear register                                 Address offset: 0x1250 */
2278   __IO uint32_t AHB2ENCR;         /*!< RCC AHB2 enable clear register                                 Address offset: 0x1254 */
2279   __IO uint32_t AHB3ENCR;         /*!< RCC AHB3 enable clear register                                 Address offset: 0x1258 */
2280   __IO uint32_t AHB4ENCR;         /*!< RCC AHB4 enable clear register                                 Address offset: 0x125C */
2281   __IO uint32_t AHB5ENCR;         /*!< RCC AHB5 enable clear register                                 Address offset: 0x1260 */
2282   __IO uint32_t APB1ENCR1;        /*!< RCC APB1 enable clear register 1                               Address offset: 0x1264 */
2283   __IO uint32_t APB1ENCR2;        /*!< RCC APB1 enable clear register 2                               Address offset: 0x1268 */
2284   __IO uint32_t APB2ENCR;         /*!< RCC APB2 enable clear register                                 Address offset: 0x126C */
2285   __IO uint32_t APB3ENCR;         /*!< RCC APB3 enable clear register                                 Address offset: 0x1270 */
2286   __IO uint32_t APB4ENCR1;        /*!< RCC APB4 enable clear register 1                               Address offset: 0x1274 */
2287   __IO uint32_t APB4ENCR2;        /*!< RCC APB4 enable clear register 2                               Address offset: 0x1278 */
2288   __IO uint32_t APB5ENCR;         /*!< RCC APB5 enable clear register                                 Address offset: 0x127C */
2289        uint32_t RESERVED35;       /*!< Reserved                                                       Address offset: 0x1280 */
2290   __IO uint32_t BUSLPENCR;        /*!< RCC bus sleep enable clear register                            Address offset: 0x1284 */
2291   __IO uint32_t MISCLPENCR;       /*!< RCC miscellaneous sleep enable clear register                  Address offset: 0x1288 */
2292   __IO uint32_t MEMLPENCR;        /*!< RCC memory sleep enable clear register                         Address offset: 0x128C */
2293   __IO uint32_t AHB1LPENCR;       /*!< RCC AHB1 sleep enable clear register                           Address offset: 0x1290 */
2294   __IO uint32_t AHB2LPENCR;       /*!< RCC AHB2 sleep enable clear register                           Address offset: 0x1294 */
2295   __IO uint32_t AHB3LPENCR;       /*!< RCC AHB3 sleep enable clear register                           Address offset: 0x1298 */
2296   __IO uint32_t AHB4LPENCR;       /*!< RCC AHB4 sleep enable clear register                           Address offset: 0x129C */
2297   __IO uint32_t AHB5LPENCR;       /*!< RCC AHB5 sleep enable clear register                           Address offset: 0x12A0 */
2298   __IO uint32_t APB1LPENCR1;      /*!< RCC APB1 sleep enable clear register 1                         Address offset: 0x12A4 */
2299   __IO uint32_t APB1LPENCR2;      /*!< RCC APB1 sleep enable clear register 2                         Address offset: 0x12A8 */
2300   __IO uint32_t APB2LPENCR;       /*!< RCC APB2 sleep enable clear register                           Address offset: 0x12AC */
2301   __IO uint32_t APB3LPENCR;       /*!< RCC APB3 sleep enable clear register                           Address offset: 0x12B0 */
2302   __IO uint32_t APB4LPENCR1;      /*!< RCC APB4 sleep enable clear register 1                         Address offset: 0x12B4 */
2303   __IO uint32_t APB4LPENCR2;      /*!< RCC APB4 sleep enable clear register 2                         Address offset: 0x12B8 */
2304   __IO uint32_t APB5LPENCR;       /*!< RCC APB5 sleep enable clear register                           Address offset: 0x12BC */
2305        uint32_t RESERVED36[305];  /*!< Reserved                                                       Address offset: 0x12C0-0x1780 */
2306   __IO uint32_t PRIVCFGCR0;       /*!< RCC oscillator privilege configuration clear register 0        Address offset: 0x1784 */
2307        uint32_t RESERVED37;       /*!< Reserved                                                       Address offset: 0x1788 */
2308   __IO uint32_t PUBCFGCR0;        /*!< RCC oscillator public configuration clear register 0           Address offset: 0x178C */
2309        uint32_t RESERVED38;       /*!< Reserved                                                       Address offset: 0x1790 */
2310   __IO uint32_t PRIVCFGCR1;       /*!< RCC PLL privilege configuration clear register 1               Address offset: 0x1794 */
2311        uint32_t RESERVED39;       /*!< Reserved                                                       Address offset: 0x1798 */
2312   __IO uint32_t PUBCFGCR1;        /*!< RCC PLL public configuration clear register 1                  Address offset: 0x179C */
2313        uint32_t RESERVED40;       /*!< Reserved                                                       Address offset: 0x17A0 */
2314   __IO uint32_t PRIVCFGCR2;       /*!< RCC divider privilege configuration clear register 2           Address offset: 0x17A4 */
2315        uint32_t RESERVED41;       /*!< Reserved                                                       Address offset: 0x17A8 */
2316   __IO uint32_t PUBCFGCR2;        /*!< RCC divider public configuration clear register 2              Address offset: 0x17AC */
2317        uint32_t RESERVED42;       /*!< Reserved                                                       Address offset: 0x17B0 */
2318   __IO uint32_t PRIVCFGCR3;       /*!< RCC system privilege configuration clear register 3            Address offset: 0x17B4 */
2319        uint32_t RESERVED43;       /*!< Reserved                                                       Address offset: 0x17B8 */
2320   __IO uint32_t PUBCFGCR3;        /*!< RCC system public configuration clear register 3               Address offset: 0x17BC */
2321        uint32_t RESERVED44;       /*!< Reserved                                                       Address offset: 0x17C0 */
2322   __IO uint32_t PRIVCFGCR4;       /*!< RCC privilege configuration clear register 4                   Address offset: 0x17C4 */
2323        uint32_t RESERVED45;       /*!< Reserved                                                       Address offset: 0x17C8 */
2324   __IO uint32_t PUBCFGCR4;        /*!< RCC public configuration clear register 4                      Address offset: 0x17CC */
2325   __IO uint32_t PUBCFGCR5;        /*!< RCC public configuration clear register 5                      Address offset: 0x17D0 */
2326 } RCC_TypeDef;
2327 
2328 /*
2329  * @brief  RIFSC Resource Isolation Framework Security Controller (full version) (RIFSC User Spec Rev 1.1)
2330  */
2331 typedef struct
2332 {
2333   __IO uint32_t RISC_CR;            /*!< RIFSC RISC slave configuration register x               Address offset: 0x000 */
2334        uint32_t RESERVED0[3];       /*!< Reserved                                                Address offset: 0x004-0x00C */
2335   __IO uint32_t RISC_SECCFGRx[6];   /*!< RIFSC RISC slave security configuration register x      Address offset: 0x010-0x24 */
2336        uint32_t RESERVED1[2];       /*!< Reserved                                                Address offset: 0x028-0x02C */
2337   __IO uint32_t RISC_PRIVCFGRx[6];  /*!< RIFSC RISFC slave privileged register x                 Address offset: 0x030-0x44 */
2338        uint32_t RESERVED2[2];       /*!< Reserved                                                Address offset: 0x048-0x04C */
2339   __IO uint32_t RISC_RCFGLOCKRx[6]; /*!< RIFSC RISC slave resource configuration lock register x Address offset: 0x050 - 0x64 */
2340        uint32_t RESERVED3[742];     /*!< Reserved                                                Address offset: 0x068-0xBFC */
2341   __IO uint32_t RIMC_CR;            /*!< RIFSC RIMC master configuration register                Address offset: 0xC00 */
2342        uint32_t RESERVED4[3];       /*!< Reserved                                                Address offset: 0xC04-0xC0C */
2343   __IO uint32_t RIMC_ATTRx[13];     /*!< RIFSC RIMC master attribute register x                  Address offset: 0xC10-0xC40 */
2344        uint32_t RESERVED5[219];     /*!< Reserved                                                Address offset: 0xC40-0xFAC */
2345   __IO uint32_t PPSRx[6];           /*!< RIFSC peripheral protection status register x           Address offset: 0xFB0-0xFC4 */
2346        uint32_t RESERVED6[8];       /*!< Reserved                                                Address offset: 0xFC8-0xFE4 */
2347 } RIFSC_TypeDef;
2348 
2349 /**
2350   * @brief RISAF Resource Isolation Slave Unit for Address Space Protection (full version)
2351   */
2352 typedef struct
2353 {
2354   __IO uint32_t CFGR;          /*!< RISAF Region X configuration register             */
2355   __IO uint32_t STARTR;        /*!< RISAF Region X start address register             */
2356   __IO uint32_t ENDR;          /*!< RISAF Region X end address register               */
2357   __IO uint32_t CIDCFGR;       /*!< RISAF Region X CID configuration register         */
2358   __IO uint32_t ACFGR;         /*!< RISAF Region X subregion A configuration register */
2359   __IO uint32_t ASTARTR;       /*!< RISAF Region X subregion A start address register */
2360   __IO uint32_t AENDR;         /*!< RISAF Region X subregion A end address register   */
2361   __IO uint32_t ANESTR;        /*!< RISAF Region X subregion A nested mode register   */
2362   __IO uint32_t BCFGR;         /*!< RISAF Region X subregion B configuration register */
2363   __IO uint32_t BSTARTR;       /*!< RISAF Region X subregion B start address register */
2364   __IO uint32_t BENDR;         /*!< RISAF Region X subregion B end address register   */
2365   __IO uint32_t BNESTR;        /*!< RISAF Region X subregion B nested mode register   */
2366        uint32_t RESERVED0[4];  /*!< Reserved                                          */
2367 } RISAF_Region_TypeDef;
2368 
2369 /**
2370   * @brief RISAF Resource Isolation Slave Unit for Address Space Protection (full version) Illegal Access Register (RIF User Spec Rev 1.0.14)
2371   */
2372 typedef struct
2373 {
2374   __IO uint32_t IAESR;         /*!< RISAF Illegal access error status register */
2375   __IO uint32_t IADDR;         /*!< RISAF Illegal address register,            */
2376 } RISAF_Illegal_TypeDef;
2377 
2378 /**
2379   * @brief RISAF Resource Isolation Slave Unit for Address Space Protection (full version) (RIF User Spec Rev 1.0.14)
2380   */
2381 typedef struct
2382 {
2383   __IO uint32_t              CR;            /*!< RISAF Configuration register,                            Address offset: 0x000 */
2384   __IO uint32_t              RESERVED0;     /*!< Reserved,                                                Address offset: 0x004 */
2385   __IO uint32_t              IASR;          /*!< RISAF Illegal access status register,                    Address offset: 0x008 */
2386   __IO uint32_t              IACR;          /*!< RISAF Illegal access clear register,                     Address offset: 0x00C */
2387        uint32_t              RESERVED1[4];  /*!< Reserved,                                                          0x010-0x01C */
2388        RISAF_Illegal_TypeDef IAR[1];        /*!< RISAF Illegal access error status and address register,            0x020-0x024 */
2389        uint32_t              RESERVED2[6];  /*!< Reserved,                                                          0x028-0x03C */
2390        RISAF_Region_TypeDef  REG[15];       /*!< RISAF Region X configuration register,                             0x040-0x3FC */
2391 } RISAF_TypeDef;
2392 
2393 /**
2394   * @brief RNG
2395   */
2396 typedef struct
2397 {
2398   __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
2399   __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
2400   __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
2401   uint32_t RESERVED;
2402   __IO uint32_t HTCR;  /*!< RNG health test configuration register, Address offset: 0x10 */
2403 } RNG_TypeDef;
2404 
2405 /*
2406 * @brief RTC Specific device feature definitions
2407 */
2408 #define RTC_BKP_NB         32U
2409 #define RTC_TAMP_NB        7U
2410 
2411 /**
2412  * @brief Real-Time Clock
2413  */
2414 typedef struct
2415 {
2416  __IO uint32_t TR;          /*!< RTC time register,                              Address offset: 0x00 */
2417  __IO uint32_t DR;          /*!< RTC date register,                              Address offset: 0x04 */
2418  __IO uint32_t SSR;         /*!< RTC sub second register,                        Address offset: 0x08 */
2419  __IO uint32_t ICSR;        /*!< RTC initialization control and status register, Address offset: 0x0C */
2420  __IO uint32_t PRER;        /*!< RTC prescaler register,                         Address offset: 0x10 */
2421  __IO uint32_t WUTR;        /*!< RTC wakeup timer register,                      Address offset: 0x14 */
2422  __IO uint32_t CR;          /*!< RTC control register,                           Address offset: 0x18 */
2423  __IO uint32_t PRIVCFGR;    /*!< RTC privilege mode control register,            Address offset: 0x1C */
2424 __IO uint32_t SECCFGR;      /*!< RTC secure mode control register,               Address offset: 0x20 */
2425  __IO uint32_t WPR;         /*!< RTC write protection register,                  Address offset: 0x24 */
2426  __IO uint32_t CALR;        /*!< RTC calibration register,                       Address offset: 0x28 */
2427  __IO uint32_t SHIFTR;      /*!< RTC shift control register,                     Address offset: 0x2C */
2428  __IO uint32_t TSTR;        /*!< RTC time stamp time register,                   Address offset: 0x30 */
2429  __IO uint32_t TSDR;        /*!< RTC time stamp date register,                   Address offset: 0x34 */
2430  __IO uint32_t TSSSR;       /*!< RTC time-stamp sub second register,             Address offset: 0x38 */
2431       uint32_t RESERVED1;   /*!< Reserved,                                       Address offset: 0x3C */
2432  __IO uint32_t ALRMAR;      /*!< RTC alarm A register,                           Address offset: 0x40 */
2433  __IO uint32_t ALRMASSR;    /*!< RTC alarm A sub second register,                Address offset: 0x44 */
2434  __IO uint32_t ALRMBR;      /*!< RTC alarm B register,                           Address offset: 0x48 */
2435  __IO uint32_t ALRMBSSR;    /*!< RTC alarm B sub second register,                Address offset: 0x4C */
2436  __IO uint32_t SR;          /*!< RTC Status register,                            Address offset: 0x50 */
2437  __IO uint32_t MISR;        /*!< RTC masked interrupt status register,           Address offset: 0x54 */
2438  __IO uint32_t SMISR;       /*!< RTC secure masked interrupt status register,    Address offset: 0x58 */
2439  __IO uint32_t SCR;         /*!< RTC status Clear register,                      Address offset: 0x5C */
2440       uint32_t RESERVED3[4];/*!< Reserved,                                       Address offset: 0x58 */
2441  __IO uint32_t ALRABINR;    /*!< RTC alarm A binary mode register,               Address offset: 0x70 */
2442  __IO uint32_t ALRBBINR;    /*!< RTC alarm B binary mode register,               Address offset: 0x74 */
2443 } RTC_TypeDef;
2444 
2445 /**
2446   * @brief SAES Processor
2447   */
2448 typedef struct
2449 {
2450   __IO uint32_t CR;             /*!< SAES control register,                      Address offset: 0x000 */
2451   __IO uint32_t SR;             /*!< SAES status register,                       Address offset: 0x004 */
2452   __IO uint32_t DINR;           /*!< SAES data input register,                   Address offset: 0x008 */
2453   __IO uint32_t DOUTR;          /*!< SAES data output register,                  Address offset: 0x00C */
2454   __IO uint32_t KEYR0;          /*!< SAES key register 0,                        Address offset: 0x010 */
2455   __IO uint32_t KEYR1;          /*!< SAES key register 1,                        Address offset: 0x014 */
2456   __IO uint32_t KEYR2;          /*!< SAES key register 2,                        Address offset: 0x018 */
2457   __IO uint32_t KEYR3;          /*!< SAES key register 3,                        Address offset: 0x01C */
2458   __IO uint32_t IVR0;           /*!< SAES initialization vector register 0,      Address offset: 0x020 */
2459   __IO uint32_t IVR1;           /*!< SAES initialization vector register 1,      Address offset: 0x024 */
2460   __IO uint32_t IVR2;           /*!< SAES initialization vector register 2,      Address offset: 0x028 */
2461   __IO uint32_t IVR3;           /*!< SAES initialization vector register 3,      Address offset: 0x02C */
2462   __IO uint32_t KEYR4;          /*!< SAES key register 4,                        Address offset: 0x030 */
2463   __IO uint32_t KEYR5;          /*!< SAES key register 5,                        Address offset: 0x034 */
2464   __IO uint32_t KEYR6;          /*!< SAES key register 6,                        Address offset: 0x038 */
2465   __IO uint32_t KEYR7;          /*!< SAES key register 7,                        Address offset: 0x03C */
2466        uint32_t RESERVED1[48];  /*!< Reserved,                                   Address offset: 0x040 -- 0x0FC */
2467   __IO uint32_t DPACFGR;        /*!< SAES DPA configuration register,            Address offset: 0x100 */
2468        uint32_t RESERVED2[127]; /*!< Reserved,                                   Address offset: 0x104 -- 0x2FC */
2469   __IO uint32_t IER;            /*!< SAES Interrupt Enable Register,             Address offset: 0x300 */
2470   __IO uint32_t ISR;            /*!< SAES Interrupt Status Register,             Address offset: 0x304 */
2471   __IO uint32_t ICR;            /*!< SAES Interrupt Clear Register,              Address offset: 0x308 */
2472 } SAES_TypeDef;
2473 
2474 /**
2475   * @brief Serial Audio Interface
2476   */
2477 typedef struct
2478 {
2479   __IO uint32_t GCR;          /*!< SAI global configuration register,        Address offset: 0x00 */
2480   uint32_t      RESERVED[16]; /*!< Reserved,                         Address offset: 0x04 to 0x40 */
2481   __IO uint32_t PDMCR;        /*!< SAI PDM control register,                 Address offset: 0x44 */
2482   __IO uint32_t PDMDLY;       /*!< SAI PDM delay register,                   Address offset: 0x48 */
2483 } SAI_TypeDef;
2484 
2485 typedef struct
2486 {
2487   __IO uint32_t CR1;         /*!< SAI block x configuration register 1,     Address offset: 0x04 */
2488   __IO uint32_t CR2;         /*!< SAI block x configuration register 2,     Address offset: 0x08 */
2489   __IO uint32_t FRCR;        /*!< SAI block x frame configuration register, Address offset: 0x0C */
2490   __IO uint32_t SLOTR;       /*!< SAI block x slot register,                Address offset: 0x10 */
2491   __IO uint32_t IMR;         /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
2492   __IO uint32_t SR;          /*!< SAI block x status register,              Address offset: 0x18 */
2493   __IO uint32_t CLRFR;       /*!< SAI block x clear flag register,          Address offset: 0x1C */
2494   __IO uint32_t DR;          /*!< SAI block x data register,                Address offset: 0x20 */
2495 } SAI_Block_TypeDef;
2496 
2497 /**
2498   * @brief Secure digital input/output Interface
2499   */
2500 typedef struct
2501 {
2502   __IO uint32_t POWER;          /*!< SDMMC power control register,              Address offset: 0x00 */
2503   __IO uint32_t CLKCR;          /*!< SDMMC clock control register,              Address offset: 0x04 */
2504   __IO uint32_t ARG;            /*!< SDMMC argument register,                   Address offset: 0x08 */
2505   __IO uint32_t CMD;            /*!< SDMMC command register,                    Address offset: 0x0C */
2506   __I uint32_t  RESPCMD;        /*!< SDMMC command response register,           Address offset: 0x10 */
2507   __I uint32_t  RESP1;          /*!< SDMMC response 1 register,                 Address offset: 0x14 */
2508   __I uint32_t  RESP2;          /*!< SDMMC response 2 register,                 Address offset: 0x18 */
2509   __I uint32_t  RESP3;          /*!< SDMMC response 3 register,                 Address offset: 0x1C */
2510   __I uint32_t  RESP4;          /*!< SDMMC response 4 register,                 Address offset: 0x20 */
2511   __IO uint32_t DTIMER;         /*!< SDMMC data timer register,                 Address offset: 0x24 */
2512   __IO uint32_t DLEN;           /*!< SDMMC data length register,                Address offset: 0x28 */
2513   __IO uint32_t DCTRL;          /*!< SDMMC data control register,               Address offset: 0x2C */
2514   __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,               Address offset: 0x30 */
2515   __I uint32_t  STA;            /*!< SDMMC status register,                     Address offset: 0x34 */
2516   __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,            Address offset: 0x38 */
2517   __IO uint32_t MASK;           /*!< SDMMC mask register,                       Address offset: 0x3C */
2518   __IO uint32_t ACKTIME;        /*!< SDMMC Acknowledgement timer register,      Address offset: 0x40 */
2519   __IO uint32_t FIFOTHR;        /*!< SDMMC data FIFO threshold register,        Address offset: 0x44 */
2520   uint32_t      RESERVED0[2];   /*!< Reserved, 0x48 - 0x4C                                           */
2521   __IO uint32_t IDMACTRL;       /*!< SDMMC DMA control register,                Address offset: 0x50 */
2522   __IO uint32_t IDMABSIZE;      /*!< SDMMC DMA buffer size register,            Address offset: 0x54 */
2523   __IO uint32_t IDMABASER;      /*!< SDMMC DMA buffer base address register,    Address offset: 0x58 */
2524   uint32_t      RESERVED1[2];   /*!< Reserved, 0x5C - 0x60                                           */
2525   __IO uint32_t IDMALAR;        /*!< SDMMC DMA linked list address register,    Address offset: 0x64 */
2526   __IO uint32_t IDMABAR;        /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */
2527   uint32_t      RESERVED2[5];   /*!< Reserved, 0x6C-0x7C                                             */
2528   __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,                  Address offset: 0x80 */
2529 } SDMMC_TypeDef;
2530 
2531 /**
2532   * @brief SPI
2533   */
2534 typedef struct
2535 {
2536   __IO uint32_t CR1;           /*!< SPI/I2S Control register 1,                      Address offset: 0x00 */
2537   __IO uint32_t CR2;           /*!< SPI Control register 2,                          Address offset: 0x04 */
2538   __IO uint32_t CFG1;          /*!< SPI Configuration register 1,                    Address offset: 0x08 */
2539   __IO uint32_t CFG2;          /*!< SPI Configuration register 2,                    Address offset: 0x0C */
2540   __IO uint32_t IER;           /*!< SPI/I2S Interrupt Enable register,               Address offset: 0x10 */
2541   __IO uint32_t SR;            /*!< SPI/I2S Status register,                         Address offset: 0x14 */
2542   __IO uint32_t IFCR;          /*!< SPI/I2S Interrupt/Status flags clear register,   Address offset: 0x18 */
2543   uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                        */
2544   __IO uint32_t TXDR;          /*!< SPI/I2S Transmit data register,                  Address offset: 0x20 */
2545   uint32_t      RESERVED1[3];  /*!< Reserved, 0x24-0x2C                                                   */
2546   __IO uint32_t RXDR;          /*!< SPI/I2S Receive data register,                   Address offset: 0x30 */
2547   uint32_t      RESERVED2[3];  /*!< Reserved, 0x34-0x3C                                                   */
2548   __IO uint32_t CRCPOLY;       /*!< SPI CRC Polynomial register,                     Address offset: 0x40 */
2549   __IO uint32_t TXCRC;         /*!< SPI Transmitter CRC register,                    Address offset: 0x44 */
2550   __IO uint32_t RXCRC;         /*!< SPI Receiver CRC register,                       Address offset: 0x48 */
2551   __IO uint32_t UDRDR;         /*!< SPI Underrun data register,                      Address offset: 0x4C */
2552   __IO uint32_t I2SCFGR;       /*!< I2S Configuration register,                      Address offset: 0x50 */
2553 } SPI_TypeDef;
2554 
2555 
2556 /**
2557   * @brief UCPD
2558   */
2559 typedef struct
2560 {
2561   __IO uint32_t CFG1;        /*!< UCPD configuration register 1,            Address offset: 0x00 */
2562   __IO uint32_t CFG2;        /*!< UCPD configuration register 2,            Address offset: 0x04 */
2563   __IO uint32_t RESERVED0;   /*!< UCPD reserved register,                   Address offset: 0x08 */
2564   __IO uint32_t CR;          /*!< UCPD control register,                    Address offset: 0x0C */
2565   __IO uint32_t IMR;         /*!< UCPD interrupt mask register,             Address offset: 0x10 */
2566   __IO uint32_t SR;          /*!< UCPD status register,                     Address offset: 0x14 */
2567   __IO uint32_t ICR;         /*!< UCPD interrupt flag clear register        Address offset: 0x18 */
2568   __IO uint32_t TX_ORDSET;   /*!< UCPD Tx ordered set type register,        Address offset: 0x1C */
2569   __IO uint32_t TX_PAYSZ;    /*!< UCPD Tx payload size register,            Address offset: 0x20 */
2570   __IO uint32_t TXDR;        /*!< UCPD Tx data register,                    Address offset: 0x24 */
2571   __IO uint32_t RX_ORDSET;   /*!< UCPD Rx ordered set type register,        Address offset: 0x28 */
2572   __IO uint32_t RX_PAYSZ;    /*!< UCPD Rx payload size register,            Address offset: 0x2C */
2573   __IO uint32_t RXDR;        /*!< UCPD Rx data register,                    Address offset: 0x30 */
2574   __IO uint32_t RX_ORDEXT1;  /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */
2575   __IO uint32_t RX_ORDEXT2;  /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */
2576 } UCPD_TypeDef;
2577 
2578 /**
2579   * @brief USB_OTG_Core_register
2580   */
2581 typedef struct
2582 {
2583   __IO uint32_t GOTGCTL;             /*!< USB_OTG Control and Status Register,       Address offset: 000h */
2584   __IO uint32_t GOTGINT;             /*!< USB_OTG Interrupt Register,                Address offset: 004h */
2585   __IO uint32_t GAHBCFG;             /*!< Core AHB Configuration Register,           Address offset: 008h */
2586   __IO uint32_t GUSBCFG;             /*!< Core USB Configuration Register,           Address offset: 00Ch */
2587   __IO uint32_t GRSTCTL;             /*!< Core Reset Register,                       Address offset: 010h */
2588   __IO uint32_t GINTSTS;             /*!< Core Interrupt Register,                   Address offset: 014h */
2589   __IO uint32_t GINTMSK;             /*!< Core Interrupt Mask Register,              Address offset: 018h */
2590   __IO uint32_t GRXSTSR;             /*!< Receive Sts Q Read Register,               Address offset: 01Ch */
2591   __IO uint32_t GRXSTSP;             /*!< Receive Sts Q Read & POP Register,         Address offset: 020h */
2592   __IO uint32_t GRXFSIZ;             /*!< Receive FIFO Size Register,                Address offset: 024h */
2593   __IO uint32_t DIEPTXF0_HNPTXFSIZ;  /*!< EP0 / Non Periodic Tx FIFO Size Register,  Address offset: 028h */
2594   __IO uint32_t HNPTXSTS;            /*!< Non Periodic Tx FIFO/Queue Sts reg,        Address offset: 02Ch */
2595   __IO uint32_t Reserved30[2];       /*!< Reserved,                                  Address offset: 030h */
2596   __IO uint32_t GCCFG;               /*!< General Purpose IO Register,               Address offset: 038h */
2597   __IO uint32_t CID;                 /*!< User ID Register,                          Address offset: 03Ch */
2598   __IO uint32_t GSNPSID;             /*!< USB_OTG core ID,                           Address offset: 040h */
2599   __IO uint32_t GHWCFG1;             /*!< User HW config1,                           Address offset: 044h */
2600   __IO uint32_t GHWCFG2;             /*!< User HW config2,                           Address offset: 048h */
2601   __IO uint32_t GHWCFG3;             /*!< User HW config3,                           Address offset: 04Ch */
2602   __IO uint32_t Reserved6;           /*!< Reserved,                                  Address offset: 050h */
2603   __IO uint32_t GLPMCFG;             /*!< LPM Register,                              Address offset: 054h */
2604   __IO uint32_t GPWRDN;              /*!< Power Down Register,                       Address offset: 058h */
2605   __IO uint32_t GDFIFOCFG;           /*!< DFIFO Software Config Register,            Address offset: 05Ch */
2606   __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register,    Address offset: 60Ch */
2607   __IO uint32_t Reserved43[39];      /*!< Reserved,                                  Address offset: 058h */
2608   __IO uint32_t HPTXFSIZ;            /*!< Host Periodic Tx FIFO Size Reg,            Address offset: 100h */
2609   __IO uint32_t DIEPTXF[0x0F];       /*!< dev Periodic Transmit FIFO                 Address offset: 104h */
2610 } USB_OTG_GlobalTypeDef;
2611 
2612 typedef struct
2613 {
2614   __IO uint32_t USBPHYC_CR;          /*!< USB_OTG Control and Status Register,       Address offset: 000h */
2615   __IO uint32_t USBPHYC_TRIM1CR;     /*!< USB_OTG Interrupt Register,                Address offset: 004h */
2616   __IO uint32_t USBPHYC_TRIM2CR;     /*!< Core AHB Configuration Register,           Address offset: 008h */
2617 } USB_PHY_GlobalTypeDef;
2618 
2619 /**
2620   * @brief USB_OTG_device_Registers
2621   */
2622 typedef struct
2623 {
2624   __IO uint32_t DCFG;                /*!< dev Configuration Register,   Address offset: 800h */
2625   __IO uint32_t DCTL;                /*!< dev Control Register,         Address offset: 804h */
2626   __IO uint32_t DSTS;                /*!< dev Status Register (RO),     Address offset: 808h */
2627   __IO uint32_t Reserved0C;          /*!< Reserved,                     Address offset: 80Ch */
2628   __IO uint32_t DIEPMSK;             /*!< dev IN Endpoint Mask,         Address offset: 810h */
2629   __IO uint32_t DOEPMSK;             /*!< dev OUT Endpoint Mask,        Address offset: 814h */
2630   __IO uint32_t DAINT;               /*!< dev All Endpoints Itr Reg,    Address offset: 818h */
2631   __IO uint32_t DAINTMSK;            /*!< dev All Endpoints Itr Mask,   Address offset: 81Ch */
2632   __IO uint32_t Reserved20;          /*!< Reserved,                     Address offset: 820h */
2633   __IO uint32_t Reserved9;           /*!< Reserved,                     Address offset: 824h */
2634   __IO uint32_t DVBUSDIS;            /*!< dev VBUS discharge Register,  Address offset: 828h */
2635   __IO uint32_t DVBUSPULSE;          /*!< dev VBUS Pulse Register,      Address offset: 82Ch */
2636   __IO uint32_t DTHRCTL;             /*!< dev threshold,                Address offset: 830h */
2637   __IO uint32_t DIEPEMPMSK;          /*!< dev empty msk,                Address offset: 834h */
2638   __IO uint32_t DEACHINT;            /*!< dedicated EP interrupt,       Address offset: 838h */
2639   __IO uint32_t DEACHMSK;            /*!< dedicated EP msk,             Address offset: 83Ch */
2640   __IO uint32_t Reserved40;          /*!< dedicated EP mask,            Address offset: 840h */
2641   __IO uint32_t DINEP1MSK;           /*!< dedicated EP mask,            Address offset: 844h */
2642   __IO uint32_t Reserved44[15];      /*!< Reserved,                     Address offset: 844-87Ch */
2643   __IO uint32_t DOUTEP1MSK;          /*!< dedicated EP msk,             Address offset: 884h */
2644 } USB_OTG_DeviceTypeDef;
2645 
2646 /**
2647   * @brief USB_OTG_IN_Endpoint-Specific_Register
2648   */
2649 typedef struct
2650 {
2651   __IO uint32_t DIEPCTL;             /*!< dev IN Endpoint Control Register,          Address offset: 900h + (ep_num * 20h) + 00h */
2652   __IO uint32_t Reserved04;          /*!< Reserved,                                  Address offset: 900h + (ep_num * 20h) + 04h */
2653   __IO uint32_t DIEPINT;             /*!< dev IN Endpoint Itr Register,              Address offset: 900h + (ep_num * 20h) + 08h */
2654   __IO uint32_t Reserved0C;          /*!< Reserved,                                  Address offset: 900h + (ep_num * 20h) + 0Ch */
2655   __IO uint32_t DIEPTSIZ;            /*!< IN Endpoint Txfer Size Register,           Address offset: 900h + (ep_num * 20h) + 10h */
2656   __IO uint32_t DIEPDMA;             /*!< IN Endpoint DMA Address Register,          Address offset: 900h + (ep_num * 20h) + 14h */
2657   __IO uint32_t DTXFSTS;             /*!< IN Endpoint Tx FIFO Status Register,       Address offset: 900h + (ep_num * 20h) + 18h */
2658   __IO uint32_t Reserved18;          /*!< Reserved,                                  Address offset: 900h + (ep_num * 20h) + 1Ch */
2659 } USB_OTG_INEndpointTypeDef;
2660 
2661 /**
2662   * @brief USB_OTG_OUT_Endpoint-Specific_Registers
2663   */
2664 typedef struct
2665 {
2666   __IO uint32_t DOEPCTL;             /*!< dev OUT Endpoint Control Register,         Address offset: B00h + (ep_num * 20h) + 00h */
2667   __IO uint32_t Reserved04;          /*!< Reserved,                                  Address offset: B00h + (ep_num * 20h) + 04h */
2668   __IO uint32_t DOEPINT;             /*!< dev OUT Endpoint Itr Register,             Address offset: B00h + (ep_num * 20h) + 08h */
2669   __IO uint32_t Reserved0C;          /*!< Reserved,                                  Address offset: B00h + (ep_num * 20h) + 0Ch */
2670   __IO uint32_t DOEPTSIZ;            /*!< dev OUT Endpoint Txfer Size Register,      Address offset: B00h + (ep_num * 20h) + 10h */
2671   __IO uint32_t DOEPDMA;             /*!< dev OUT Endpoint DMA Address Register,     Address offset: B00h + (ep_num * 20h) + 14h */
2672   __IO uint32_t Reserved18[2];       /*!< Reserved,                                  Address offset: B00h + (ep_num * 20h) + 18h */
2673 } USB_OTG_OUTEndpointTypeDef;
2674 
2675 /**
2676   * @brief USB_OTG_Host_Mode_Register_Structures
2677   */
2678 typedef struct
2679 {
2680   __IO uint32_t HCFG;                 /*!< Host Configuration Register,              Address offset: 400h */
2681   __IO uint32_t HFIR;                 /*!< Host Frame Interval Register,             Address offset: 404h */
2682   __IO uint32_t HFNUM;                /*!< Host Frame Nbr/Frame Remaining,           Address offset: 408h */
2683   __IO uint32_t Reserved40C;          /*!< Reserved,                                 Address offset: 40Ch */
2684   __IO uint32_t HPTXSTS;              /*!< Host Periodic Tx FIFO/ Queue Status,      Address offset: 410h */
2685   __IO uint32_t HAINT;                /*!< Host All Channels Interrupt Register,     Address offset: 414h */
2686   __IO uint32_t HAINTMSK;             /*!< Host All Channels Interrupt Mask,         Address offset: 418h */
2687 } USB_OTG_HostTypeDef;
2688 
2689 /**
2690   * @brief USB_OTG_Host_Channel_Specific_Registers
2691   */
2692 typedef struct
2693 {
2694   __IO uint32_t HCCHAR;               /*!< Host Channel Characteristics Register,    Address offset: 500h */
2695   __IO uint32_t HCSPLT;               /*!< Host Channel Split Control Register,      Address offset: 504h */
2696   __IO uint32_t HCINT;                /*!< Host Channel Interrupt Register,          Address offset: 508h */
2697   __IO uint32_t HCINTMSK;             /*!< Host Channel Interrupt Mask Register,     Address offset: 50Ch */
2698   __IO uint32_t HCTSIZ;               /*!< Host Channel Transfer Size Register,      Address offset: 510h */
2699   __IO uint32_t HCDMA;                /*!< Host Channel DMA Address Register,        Address offset: 514h */
2700   uint32_t Reserved[2];               /*!< Reserved,                                 Address offset: 518h */
2701 } USB_OTG_HostChannelTypeDef;
2702 
2703 typedef struct
2704 {
2705   __IO uint32_t USBPHYC_CR;           /*!< USB HS PHY Control Register,              Address offset: 000h */
2706   __IO uint32_t USBPHYC_TRIM1CR;      /*!< USB HS PHY Trimming_1 Register,           Address offset: 004h */
2707   __IO uint32_t USBPHYC_TRIM2CR;      /*!< USB HS PHY Trimming_2 Register,           Address offset: 008h */
2708 } USB_HS_PHYC_GlobalTypeDef;
2709 
2710 /**
2711   * @brief SPDIF-RX Interface
2712   */
2713 typedef struct
2714 {
2715   __IO uint32_t CR;          /*!< Control register,                   Address offset: 0x00 */
2716   __IO uint32_t IMR;         /*!< Interrupt mask register,            Address offset: 0x04 */
2717   __IO uint32_t SR;          /*!< Status register,                    Address offset: 0x08 */
2718   __IO uint32_t IFCR;        /*!< Interrupt Flag Clear register,      Address offset: 0x0C */
2719   __IO uint32_t DR;          /*!< Data input register,                Address offset: 0x10 */
2720   __IO uint32_t CSR;         /*!< Channel Status register,            Address offset: 0x14 */
2721   __IO uint32_t DIR;         /*!< Debug Information register,         Address offset: 0x18 */
2722 } SPDIFRX_TypeDef;
2723 
2724 
2725 /**
2726   * @brief System configuration controller
2727   */
2728 typedef struct
2729 {
2730   __IO uint32_t BOOTCR;         /*!< SYSCFG boot pin control register,                                            Address offset: 0x00 */
2731   __IO uint32_t CM55CR;         /*!< SYSCFG Cortex-M55 control register,                                          Address offset: 0x04 */
2732   __IO uint32_t CM55TCMCR;      /*!< SYSCFG Cortex-M55 TCM control register,                                      Address offset: 0x08 */
2733   __IO uint32_t CM55RWMCR;      /*!< SYSCFG Cortex-M55 memory RW margin register,                                 Address offset: 0x0C */
2734   __IO uint32_t INITSVTORCR;    /*!< SYSCFG Cortex-M55 SVTOR control register,                                    Address offset: 0x10 */
2735   __IO uint32_t INITNSVTORCR;   /*!< Cortex-M55 NSVTOR control register,                                          Address offset: 0x14 */
2736   __IO uint32_t CM55RSTCR;      /*!< SYSCFG Cortex-M55 reset type control register,                               Address offset: 0x18 */
2737   __IO uint32_t CM55PAHBWPR;    /*!< SYSCFG Cortex-M55 P-AHB write posting control register,                      Address offset: 0x1C */
2738   __IO uint32_t VENCRAMCR;      /*!< SYSCFG VENCRAM control register,                                             Address offset: 0x20 */
2739   __IO uint32_t POTTAMPRSTCR;   /*!< SYSCFG potential tamper reset register,                                      Address offset: 0x24 */
2740   __IO uint32_t NPUNICQOSCR;    /*!< SYSCFG NPUNIC QoS control register,                                          Address offset: 0x28 */
2741   uint32_t      RESERVED1[2];   /*!< Reserved,                                                                    Address offset: 0x2C-0x30 */
2742   __IO uint32_t ICNEWRCR;       /*!< SYSCFG AHB-AXI bridge early write response,                                  Address offset: 0x34 */
2743   __IO uint32_t ICNCGCR;        /*!< SYSCFG ICN clock gating control register,                                    Address offset: 0x38 */
2744   uint32_t      RESERVED2[2];   /*!< Reserved,                                                                    Address offset: 0x3C-0x40 */
2745   __IO uint32_t VDDIO2CCCR;     /*!< SYSCFG VDDIO2 compensation cell control register,                            Address offset: 0x44 */
2746   __IO uint32_t VDDIO2CCSR;     /*!< SYSCFG VDDIO2 compensation cell status register,                             Address offset: 0x48 */
2747   __IO uint32_t VDDIO3CCCR;     /*!< SYSCFG VDDIO3 compensation cell control register,                            Address offset: 0x4C */
2748   __IO uint32_t VDDIO3CCSR;     /*!< SYSCFG VDDIO3 compensation cell status register,                             Address offset: 0x50 */
2749   __IO uint32_t VDDIO4CCCR;     /*!< SYSCFG VDDIO4 compensation cell control register,                            Address offset: 0x54 */
2750   __IO uint32_t VDDIO4CCSR;     /*!< SYSCFG VDDIO4 compensation cell status register,                             Address offset: 0x58 */
2751   __IO uint32_t VDDIO5CCCR;     /*!< SYSCFG VDDIO5 compensation cell control register,                            Address offset: 0x5C */
2752   __IO uint32_t VDDIO5CCSR;     /*!< SYSCFG VDDIO5 compensation cell status register,                             Address offset: 0x60 */
2753   __IO uint32_t VDDCCCR;        /*!< SYSCFG VDD compensation cell control register,                               Address offset: 0x64 */
2754   __IO uint32_t VDDCCSR;        /*!< SYSCFG VDD compensation cell status register,                                Address offset: 0x68 */
2755   __IO uint32_t CBR;            /*!< SYSCFG control timer break register,                                         Address offset: 0x6C */
2756   __IO uint32_t SEC_AIDCR;      /*!< SYSCFG DMA CID secure control register,                                      Address offset: 0x70 */
2757   __IO uint32_t FMC_RETIMECR;   /*!< SYSCFG FMC retiming logic control register,                                  Address offset: 0x74 */
2758   __IO uint32_t NPU_ICNCR;      /*!< SYSCFG NPU RAM interleaving control register,                                Address offset: 0x78 */
2759   uint32_t      RESERVED3[33];  /*!< Reserved,                                                                    Address offset: 0x7C-0xFC */
2760   __IO uint32_t BOOTSR;         /*!< SYSCFG boot pin status register,                                             Address offset: 0x100 */
2761   __IO uint32_t AHBWP_ERROR_SR; /*!< SYSCFG AHB write posting address error register,                             Address offset: 0x104 */
2762   uint32_t      RESERVED4[446]; /*!< Reserved,                                                                    Address offset: 0x108-0x3FC */
2763   __IO uint32_t SECPRIV_AIDCR;  /*!< SYSCFG DMA CID non-secure control register,                                  Address offset: 0x800 */
2764   uint32_t      RESERVED5[507]; /*!< Reserved,                                                                    Address offset: 0x804-0xFEC */
2765   __IO uint32_t DEVICEID;       /*!< SYSCFG Device ID,                                                            Address offset: 0xFF0 */
2766 } SYSCFG_TypeDef;
2767 
2768 /**
2769  * @brief Tamper and backup registers
2770  */
2771 typedef struct
2772 {
2773  __IO uint32_t CR1;           /*!< TAMP configuration register 1,                    Address offset: 0x00 */
2774  __IO uint32_t CR2;           /*!< TAMP configuration register 2,                    Address offset: 0x04 */
2775  __IO uint32_t CR3;           /*!< TAMP configuration register 3,                    Address offset: 0x08 */
2776  __IO uint32_t FLTCR;         /*!< TAMP filter control register,                     Address offset: 0x0C */
2777  __IO uint32_t ATCR1;         /*!< TAMP filter control register 1                    Address offset: 0x10 */
2778  __IO uint32_t ATSEEDR;       /*!< TAMP active tamper seed register,                 Address offset: 0x14 */
2779  __IO uint32_t ATOR;          /*!< TAMP active tamper output register,               Address offset: 0x18 */
2780  __IO uint32_t ATCR2;         /*!< TAMP filter control register 2,                   Address offset: 0x1C */
2781  __IO uint32_t SECCFGR;       /*!< TAMP secure mode control register,                Address offset: 0x20 */
2782  __IO uint32_t PRIVCFGR;      /*!< TAMP privilege mode control register,             Address offset: 0x24 */
2783       uint32_t RESERVED2;     /*!< Reserved,                                         Address offset: 0x28 */
2784  __IO uint32_t IER;           /*!< TAMP interrupt enable register,                   Address offset: 0x2C */
2785  __IO uint32_t SR;            /*!< TAMP status register,                             Address offset: 0x30 */
2786  __IO uint32_t MISR;          /*!< TAMP masked interrupt status register,            Address offset: 0x34 */
2787  __IO uint32_t SMISR;         /*!< TAMP secure masked interrupt status register,     Address offset: 0x38 */
2788  __IO uint32_t SCR;           /*!< TAMP status clear register,                       Address offset: 0x3C */
2789  __IO uint32_t COUNT1R;       /*!< TAMP monotonic counter register,                  Address offset: 0x40 */
2790       uint32_t RESERVED4[3];  /*!< Reserved,                                         Address offset: 0x43 -- 0x4C */
2791  __IO uint32_t OR;            /*!< TAMP option register,                             Address offset: 0x50 */
2792  __IO uint32_t RPCFGR;        /*!< TAMP resources protection configuration register, Address offset: 0x54 */
2793       uint32_t RESERVED5[42]; /*!< Reserved,                                         Address offset: 0x58 -- 0xFC */
2794  __IO uint32_t BKP0R;         /*!< TAMP backup register 0,                           Address offset: 0x100 */
2795  __IO uint32_t BKP1R;         /*!< TAMP backup register 1,                           Address offset: 0x104 */
2796  __IO uint32_t BKP2R;         /*!< TAMP backup register 2,                           Address offset: 0x108 */
2797  __IO uint32_t BKP3R;         /*!< TAMP backup register 3,                           Address offset: 0x10C */
2798  __IO uint32_t BKP4R;         /*!< TAMP backup register 4,                           Address offset: 0x110 */
2799  __IO uint32_t BKP5R;         /*!< TAMP backup register 5,                           Address offset: 0x114 */
2800  __IO uint32_t BKP6R;         /*!< TAMP backup register 6,                           Address offset: 0x118 */
2801  __IO uint32_t BKP7R;         /*!< TAMP backup register 7,                           Address offset: 0x11C */
2802  __IO uint32_t BKP8R;         /*!< TAMP backup register 8,                           Address offset: 0x120 */
2803  __IO uint32_t BKP9R;         /*!< TAMP backup register 9,                           Address offset: 0x124 */
2804  __IO uint32_t BKP10R;        /*!< TAMP backup register 10,                          Address offset: 0x128 */
2805  __IO uint32_t BKP11R;        /*!< TAMP backup register 11,                          Address offset: 0x12C */
2806  __IO uint32_t BKP12R;        /*!< TAMP backup register 12,                          Address offset: 0x130 */
2807  __IO uint32_t BKP13R;        /*!< TAMP backup register 13,                          Address offset: 0x134 */
2808  __IO uint32_t BKP14R;        /*!< TAMP backup register 14,                          Address offset: 0x138 */
2809  __IO uint32_t BKP15R;        /*!< TAMP backup register 15,                          Address offset: 0x13C */
2810  __IO uint32_t BKP16R;        /*!< TAMP backup register 16,                          Address offset: 0x140 */
2811  __IO uint32_t BKP17R;        /*!< TAMP backup register 17,                          Address offset: 0x144 */
2812  __IO uint32_t BKP18R;        /*!< TAMP backup register 18,                          Address offset: 0x148 */
2813  __IO uint32_t BKP19R;        /*!< TAMP backup register 19,                          Address offset: 0x14C */
2814  __IO uint32_t BKP20R;        /*!< TAMP backup register 20,                          Address offset: 0x150 */
2815  __IO uint32_t BKP21R;        /*!< TAMP backup register 21,                          Address offset: 0x154 */
2816  __IO uint32_t BKP22R;        /*!< TAMP backup register 22,                          Address offset: 0x158 */
2817  __IO uint32_t BKP23R;        /*!< TAMP backup register 23,                          Address offset: 0x15C */
2818  __IO uint32_t BKP24R;        /*!< TAMP backup register 24,                          Address offset: 0x160 */
2819  __IO uint32_t BKP25R;        /*!< TAMP backup register 25,                          Address offset: 0x164 */
2820  __IO uint32_t BKP26R;        /*!< TAMP backup register 26,                          Address offset: 0x168 */
2821  __IO uint32_t BKP27R;        /*!< TAMP backup register 27,                          Address offset: 0x16C */
2822  __IO uint32_t BKP28R;        /*!< TAMP backup register 28,                          Address offset: 0x170 */
2823  __IO uint32_t BKP29R;        /*!< TAMP backup register 29,                          Address offset: 0x174 */
2824  __IO uint32_t BKP30R;        /*!< TAMP backup register 30,                          Address offset: 0x178 */
2825  __IO uint32_t BKP31R;        /*!< TAMP backup register 31,                          Address offset: 0x17C */
2826 } TAMP_TypeDef;
2827 
2828 /**
2829   * @brief TIM
2830   */
2831 typedef struct
2832 {
2833   __IO uint32_t CR1;            /*!< TIM control register 1,                   Address offset:  0x00 */
2834   __IO uint32_t CR2;            /*!< TIM control register 2,                   Address offset:  0x04 */
2835   __IO uint32_t SMCR;           /*!< TIM slave mode control register,          Address offset:  0x08 */
2836   __IO uint32_t DIER;           /*!< TIM DMA/interrupt enable register,        Address offset:  0x0C */
2837   __IO uint32_t SR;             /*!< TIM status register,                      Address offset:  0x10 */
2838   __IO uint32_t EGR;            /*!< TIM event generation register,            Address offset:  0x14 */
2839   __IO uint32_t CCMR1;          /*!< TIM capture/compare mode register 1,      Address offset:  0x18 */
2840   __IO uint32_t CCMR2;          /*!< TIM capture/compare mode register 2,      Address offset:  0x1C */
2841   __IO uint32_t CCER;           /*!< TIM capture/compare enable register,      Address offset:  0x20 */
2842   __IO uint32_t CNT;            /*!< TIM counter register,                     Address offset:  0x24 */
2843   __IO uint32_t PSC;            /*!< TIM prescaler,                            Address offset:  0x28 */
2844   __IO uint32_t ARR;            /*!< TIM auto-reload register,                 Address offset:  0x2C */
2845   __IO uint32_t RCR;            /*!< TIM repetition counter register,          Address offset:  0x30 */
2846   __IO uint32_t CCR1;           /*!< TIM capture/compare register 1,           Address offset:  0x34 */
2847   __IO uint32_t CCR2;           /*!< TIM capture/compare register 2,           Address offset:  0x38 */
2848   __IO uint32_t CCR3;           /*!< TIM capture/compare register 3,           Address offset:  0x3C */
2849   __IO uint32_t CCR4;           /*!< TIM capture/compare register 4,           Address offset:  0x40 */
2850   __IO uint32_t BDTR;           /*!< TIM break and dead-time register,         Address offset:  0x44 */
2851   __IO uint32_t CCR5;           /*!< TIM capture/compare register 5,           Address offset:  0x48 */
2852   __IO uint32_t CCR6;           /*!< TIM capture/compare register 6,           Address offset:  0x4C */
2853   __IO uint32_t CCMR3;          /*!< TIM capture/compare mode register 3,      Address offset:  0x50 */
2854   __IO uint32_t DTR2;           /*!< TIM deadtime register 2,                  Address offset:  0x54 */
2855   __IO uint32_t ECR;            /*!< TIM encoder control register,             Address offset:  0x58 */
2856   __IO uint32_t TISEL;          /*!< TIM Input Selection register,             Address offset:  0x5C */
2857   __IO uint32_t AF1;            /*!< TIM alternate function option register 1, Address offset:  0x60 */
2858   __IO uint32_t AF2;            /*!< TIM alternate function option register 2, Address offset:  0x64 */
2859        uint32_t RESERVED1[221]; /*!< Reserved,                                            0x6C-0x3D8 */
2860   __IO uint32_t DCR;            /*!< TIM DMA control register,                 Address offset: 0x3DC */
2861   __IO uint32_t DMAR;           /*!< TIM DMA address for full transfer,        Address offset: 0x3E0 */
2862 } TIM_TypeDef;
2863 
2864 
2865 /**
2866   * @brief Universal Synchronous Asynchronous Receiver Transmitter
2867   */
2868 typedef struct
2869 {
2870   __IO uint32_t CR1;         /*!< USART Control register 1,                 Address offset: 0x00 */
2871   __IO uint32_t CR2;         /*!< USART Control register 2,                 Address offset: 0x04 */
2872   __IO uint32_t CR3;         /*!< USART Control register 3,                 Address offset: 0x08 */
2873   __IO uint32_t BRR;         /*!< USART Baud rate register,                 Address offset: 0x0C */
2874   __IO uint32_t GTPR;        /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
2875   __IO uint32_t RTOR;        /*!< USART Receiver Time Out register,         Address offset: 0x14 */
2876   __IO uint32_t RQR;         /*!< USART Request register,                   Address offset: 0x18 */
2877   __IO uint32_t ISR;         /*!< USART Interrupt and status register,      Address offset: 0x1C */
2878   __IO uint32_t ICR;         /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
2879   __IO uint32_t RDR;         /*!< USART Receive Data register,              Address offset: 0x24 */
2880   __IO uint32_t TDR;         /*!< USART Transmit Data register,             Address offset: 0x28 */
2881   __IO uint32_t PRESC;       /*!< USART Prescaler register,                 Address offset: 0x2C */
2882 } USART_TypeDef;
2883 
2884 
2885 /**
2886   * @brief VREFBUF
2887   */
2888 typedef struct
2889 {
2890   __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */
2891   __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */
2892 } VREFBUF_TypeDef;
2893 
2894 
2895 /**
2896   * @brief Window Watchdog
2897   */
2898 typedef struct
2899 {
2900   __IO uint32_t CR;          /*!< WWDG Control register,              Address offset: 0x00 */
2901   __IO uint32_t CFR;         /*!< WWDG Configuration register,        Address offset: 0x04 */
2902   __IO uint32_t SR;          /*!< WWDG Status register,               Address offset: 0x08 */
2903 } WWDG_TypeDef;
2904 
2905 /**
2906   * @brief Extended-SPI Interface
2907   */
2908 typedef struct
2909 {
2910   __IO uint32_t CR;             /*!< XSPI Control Register,                                Address offset: 0x000         */
2911        uint32_t RESERVED1;      /*!< Reserved,                                             Address offset: 0x004         */
2912   __IO uint32_t DCR1;           /*!< XSPI Device Configuration Register 1,                 Address offset: 0x008         */
2913   __IO uint32_t DCR2;           /*!< XSPI Device Configuration Register 2,                 Address offset: 0x00C         */
2914   __IO uint32_t DCR3;           /*!< XSPI Device Configuration Register 3,                 Address offset: 0x010         */
2915   __IO uint32_t DCR4;           /*!< XSPI Device Configuration Register 4,                 Address offset: 0x014         */
2916        uint32_t RESERVED2[2];   /*!< Reserved,                                             Address offset: 0x018 - 0x01C */
2917   __IO uint32_t SR;             /*!< XSPI Status Register,                                 Address offset: 0x020         */
2918   __IO uint32_t FCR;            /*!< XSPI Flag Clear Register,                             Address offset: 0x024         */
2919        uint32_t RESERVED3[6];   /*!< Reserved,                                             Address offset: 0x028 - 0x03C */
2920   __IO uint32_t DLR;            /*!< XSPI Data Length Register,                            Address offset: 0x040         */
2921        uint32_t RESERVED4;      /*!< Reserved,                                             Address offset: 0x044         */
2922   __IO uint32_t AR;             /*!< XSPI Address Register,                                Address offset: 0x048         */
2923        uint32_t RESERVED5;      /*!< Reserved,                                             Address offset: 0x04C         */
2924   __IO uint32_t DR;             /*!< XSPI Data Register,                                   Address offset: 0x050         */
2925        uint32_t RESERVED6[11];  /*!< Reserved,                                             Address offset: 0x054 - 0x07C */
2926   __IO uint32_t PSMKR;          /*!< XSPI Polling Status Mask Register,                    Address offset: 0x080         */
2927        uint32_t RESERVED7;      /*!< Reserved,                                             Address offset: 0x084         */
2928   __IO uint32_t PSMAR;          /*!< XSPI Polling Status Match Register,                   Address offset: 0x088         */
2929        uint32_t RESERVED8;      /*!< Reserved,                                             Address offset: 0x08C         */
2930   __IO uint32_t PIR;            /*!< XSPI Polling Interval Register,                       Address offset: 0x090         */
2931        uint32_t RESERVED9[27];  /*!< Reserved,                                             Address offset: 0x094 - 0x0FC */
2932   __IO uint32_t CCR;            /*!< XSPI Communication Configuration Register,            Address offset: 0x100         */
2933        uint32_t RESERVED10;     /*!< Reserved,                                             Address offset: 0x104         */
2934   __IO uint32_t TCR;            /*!< XSPI Timing Configuration Register,                   Address offset: 0x108         */
2935        uint32_t RESERVED11;     /*!< Reserved,                                             Address offset: 0x10C         */
2936   __IO uint32_t IR;             /*!< XSPI Instruction Register,                            Address offset: 0x110         */
2937        uint32_t RESERVED12[3];  /*!< Reserved,                                             Address offset: 0x114 - 0x11C */
2938   __IO uint32_t ABR;            /*!< XSPI Alternate Bytes Register,                        Address offset: 0x120         */
2939        uint32_t RESERVED13[3];  /*!< Reserved,                                             Address offset: 0x124 - 0x12C */
2940   __IO uint32_t LPTR;           /*!< XSPI Low-Power Timeout Register,                      Address offset: 0x130         */
2941        uint32_t RESERVED14[3];  /*!< Reserved,                                             Address offset: 0x134 - 0x13C */
2942   __IO uint32_t WPCCR;          /*!< XSPI Wrap Communication Configuration Register,       Address offset: 0x140         */
2943        uint32_t RESERVED15;     /*!< Reserved,                                             Address offset: 0x144         */
2944   __IO uint32_t WPTCR;          /*!< XSPI Wrap Timing Configuration Register,              Address offset: 0x148         */
2945        uint32_t RESERVED16;     /*!< Reserved,                                             Address offset: 0x14C         */
2946   __IO uint32_t WPIR;           /*!< XSPI Wrap Instruction Register,                       Address offset: 0x150         */
2947        uint32_t RESERVED17[3];  /*!< Reserved,                                             Address offset: 0x154 - 0x15C */
2948   __IO uint32_t WPABR;          /*!< XSPI Wrap Alternate Bytes Register,                   Address offset: 0x160         */
2949        uint32_t RESERVED18[7];  /*!< Reserved,                                             Address offset: 0x164 - 0x17C */
2950   __IO uint32_t WCCR;           /*!< XSPI Write Communication Configuration Register,      Address offset: 0x180         */
2951        uint32_t RESERVED19;     /*!< Reserved,                                             Address offset: 0x184         */
2952   __IO uint32_t WTCR;           /*!< XSPI Write Timing Configuration Register,             Address offset: 0x188         */
2953        uint32_t RESERVED20;     /*!< Reserved,                                             Address offset: 0x18C         */
2954   __IO uint32_t WIR;            /*!< XSPI Write Instruction Register,                      Address offset: 0x190         */
2955        uint32_t RESERVED21[3];  /*!< Reserved,                                             Address offset: 0x194 - 0x19C */
2956   __IO uint32_t WABR;           /*!< XSPI Write Alternate Bytes Register,                  Address offset: 0x1A0         */
2957        uint32_t RESERVED22[23]; /*!< Reserved,                                             Address offset: 0x1A4 - 0x1FC */
2958   __IO uint32_t HLCR;           /*!< XSPI HyperBus Latency Configuration Register,         Address offset: 0x200         */
2959        uint32_t RESERVED23[3];  /*!< Reserved,                                             Address offset: 0x204 - 0x20C */
2960   __IO uint32_t CALFCR;         /*!< XSPI Full-Cycle Calibration Configuration Register,   Address offset: 0x210         */
2961        uint32_t RESERVED24;     /*!< Reserved,                                             Address offset: 0x214         */
2962   __IO uint32_t CALMR;          /*!< XSPI DLL Master Calibration Configuration Register,   Address offset: 0x218         */
2963        uint32_t RESERVED25;     /*!< Reserved,                                             Address offset: 0x21C         */
2964   __IO uint32_t CALSOR;         /*!< XSPI Slave Output Calibration Configuration Register, Address offset: 0x220         */
2965        uint32_t RESERVED26;     /*!< Reserved,                                             Address offset: 0x224         */
2966   __IO uint32_t CALSIR;         /*!< XSPI Slave Input Calibration Configuration Register,  Address offset: 0x228         */
2967 } XSPI_TypeDef;
2968 
2969 /**
2970   * @brief XSPI IO Manager
2971   */
2972 typedef struct
2973 {
2974   __IO uint32_t CR;             /*!< XSPI IO Manager Control Register,                     Address offset: 0x00        */
2975 } XSPIM_TypeDef;
2976 
2977 /** @} */ /* End of group STM32N6xx_peripherals */
2978 
2979 /* =========================================================================================================================== */
2980 /* ================                          Device Specific Peripheral Address Map                           ================ */
2981 /* =========================================================================================================================== */
2982 /** @addtogroup STM32N6xx_Peripheral_peripheralAddr
2983   * @{
2984   */
2985 
2986 /* Internal RAMs sizes */
2987 #define SRAM1_AXI_SIZE                  0x100000UL   /*!< SRAM1_AXI = 1024 Kbytes */
2988 #define SRAM2_AXI_SIZE                  0x100000UL   /*!< SRAM2_AXI = 1024 Kbytes */
2989 #define FLEXRAM_SIZE                     0x64000UL   /*!< FLEXRAM <= 400 Kbytes   */
2990 #define SRAM3_AXI_SIZE                   0x70000UL   /*!< SRAM3_AXI = 448 Kbytes  */
2991 #define SRAM4_AXI_SIZE                   0x70000UL   /*!< SRAM4_AXI = 448 Kbytes  */
2992 #define SRAM5_AXI_SIZE                   0x70000UL   /*!< SRAM5_AXI = 448 Kbytes  */
2993 #define SRAM6_AXI_SIZE                   0x70000UL   /*!< SRAM6_AXI = 448 Kbytes  */
2994 #define SRAM1_AHB_SIZE                    0x4000UL   /*!< SRAM1_AHB = 16 Kbytes   */
2995 #define SRAM2_AHB_SIZE                    0x4000UL   /*!< SRAM2_AHB = 16 Kbytes   */
2996 #define VENC_RAM_SIZE                    0x20000UL   /*!< VENC RAM  = 128 Kbytes  */
2997 #define CACHEAXI_RAM_SIZE                0x40000UL   /*!< CACHEAXI RAM = 256 Kbytes */
2998 #define BKPSRAM_SIZE                      0x2000UL   /*!< BKPSRAM  = 8 Kbytes     */
2999 
3000 
3001 #define FMC_BASE                        0x60000000UL /*!< Base address of : FMC NOR/RAM memories accessible over AXI */
3002 #define FMC_BANK1                       FMC_BASE
3003 #define FMC_BANK1_1                     FMC_BANK1
3004 #define FMC_BANK1_2                     (FMC_BANK1 + 0x04000000UL)
3005 #define FMC_BANK1_3                     (FMC_BANK1 + 0x08000000UL)
3006 #define FMC_BANK1_4                     (FMC_BANK1 + 0x0C000000UL)
3007 #define FMC_BANK5                       0xC0000000UL  /*!< Base address of : FMC SDRAM memories accessible over AXI */
3008 #define FMC_BANK5_1                     FMC_BANK5
3009 #define FMC_BANK5_2                     (FMC_BANK5 + 0x04000000UL)
3010 #define FMC_BANK5_3                     (FMC_BANK5 + 0x08000000UL)
3011 #define FMC_BANK5_4                     (FMC_BANK5 + 0x0C000000UL)
3012 #define FMC_BANK6                       0xD0000000UL  /*!< Base address of : FMC SDRAM memories accessible over AXI */
3013 #define FMC_BANK6_1                     FMC_BANK6
3014 #define FMC_BANK6_2                     (FMC_BANK6 + 0x04000000UL)
3015 #define FMC_BANK6_3                     (FMC_BANK6 + 0x08000000UL)
3016 #define FMC_BANK6_4                     (FMC_BANK6 + 0x0C000000UL)
3017 #define XSPI1_BASE                      0x90000000UL /*!< Base address of : XSPI1 memories accessible over AXI    */
3018 #define XSPI2_BASE                      0x70000000UL /*!< Base address of : XSPI2 memories accessible over AXI    */
3019 #define XSPI3_BASE                      0x80000000UL /*!< Base address of : XSPI3 memories accessible over AXI    */
3020 
3021 /**************************************************************************/
3022 /*                                                                        */
3023 /* Peripheral and internal SRAMs base addresses - Non secure (aliased_NS) */
3024 /*                                                                        */
3025 /**************************************************************************/
3026 
3027 #define ITCM_BASE_NS                    0x00000000UL /*!< Base address of ITCM from 64 KB up to 256 KB               */
3028 #define BOOTROM_BASE_NS                 0x08000000UL /*!< Base address of 128 KB boot ROM accessible over AXI        */
3029 #define DTCM_BASE_NS                    0x20000000UL /*!< Base address of DTCM from 128 KB up to 256 KB              */
3030 #define SRAM1_AXI_BASE_NS               0x24000000UL /*!< Base address of up to 1 MB system RAM 1 accessible over AXI */
3031 #define SRAM2_AXI_BASE_NS               0x24100000UL /*!< Base address of 1 MB system RAM 2 accessible over AXI      */
3032 #define SRAM3_AXI_BASE_NS               0x24200000UL /*!< Base address of 448 KB system RAM 3 accessible over AXI      */
3033 #define SRAM4_AXI_BASE_NS               0x24270000UL /*!< Base address of 448 KB system RAM 4 accessible over AXI */
3034 #define SRAM5_AXI_BASE_NS               0x242E0000UL /*!< Base address of 448 KB system RAM 5 accessible over AXI */
3035 #define SRAM6_AXI_BASE_NS               0x24350000UL /*!< Base address of 448 KB system RAM 6 accessible over AXI */
3036 #define SRAM_AXI_BASE_NS                SRAM1_AXI_BASE_NS /*!< Base address of 3.792 MB system RAM accessible over AXI */
3037 #define CACHEAXI_RAM_BASE_NS            0x243C0000UL /*!< Base address of 256 KB NPU Cache RAM accessible over AXI   */
3038 #define VENC_RAM_BASE_NS                0x24400000UL /*!< Base address of 128 KB of Video Encoder RAM accessible over AXI */
3039 #define GFXMMU_VIRTUAL_BUFFER0_BASE_NS  0x25000000UL /*!< Base address of 4 MB GFXMMU virtual buffer 0               */
3040 #define GFXMMU_VIRTUAL_BUFFER1_BASE_NS  0x25400000UL /*!< Base address of 4 MB GFXMMU virtual buffer 1               */
3041 #define GFXMMU_VIRTUAL_BUFFER2_BASE_NS  0x25800000UL /*!< Base address of 4 MB GFXMMU virtual buffer 2               */
3042 #define GFXMMU_VIRTUAL_BUFFER3_BASE_NS  0x25C00000UL /*!< Base address of 4 MB GFXMMU virtual buffer 3               */
3043 #define STM500_CHANNELS_BASE_NS         0x27F00000UL /*!< Base address of 1 MB of STM500 Channels (System Trace)     */
3044 #define SRAM1_AHB_BASE_NS               0x28000000UL /*!< Base address of 16 KB system RAM 1 over AXI->AHB Bridge    */
3045 #define SRAM2_AHB_BASE_NS               0x28004000UL /*!< Base address of 16 KB system RAM 2 over AXI->AHB Bridge    */
3046 #define SRAM_AHB_BASE_NS                SRAM1_AHB_BASE_NS /*!< Base address of 32 KB system RAM over AXI->AHB Bridge */
3047 #define BKPSRAM_BASE_NS                 0x2C000000UL /*!< Base address of 8 KB Backup SRAM over AXI->AHB Bridge      */
3048 #define PERIPH_BASE_NS                  0x40000000UL /*!< Base address of : AHB/APB Peripherals                      */
3049 
3050 /*!< Peripheral memory map */
3051 #define APB1PERIPH_BASE_NS              PERIPH_BASE_NS
3052 #define AHB1PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x00020000UL)
3053 #define APB2PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x02000000UL)
3054 #define AHB2PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x02020000UL)
3055 #define APB3PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x04000000UL)
3056 #define AHB3PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x04020000UL)
3057 #define APB4PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x06000000UL)
3058 #define AHB4PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x06020000UL)
3059 #define APB5PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x08000000UL)
3060 #define AHB5PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x08020000UL)
3061 
3062 /*!< APB1 peripherals */
3063 #define TIM2_BASE_NS                    (APB1PERIPH_BASE_NS + 0x0000UL)
3064 #define TIM3_BASE_NS                    (APB1PERIPH_BASE_NS + 0x0400UL)
3065 #define TIM4_BASE_NS                    (APB1PERIPH_BASE_NS + 0x0800UL)
3066 #define TIM5_BASE_NS                    (APB1PERIPH_BASE_NS + 0x0C00UL)
3067 #define TIM6_BASE_NS                    (APB1PERIPH_BASE_NS + 0x1000UL)
3068 #define TIM7_BASE_NS                    (APB1PERIPH_BASE_NS + 0x1400UL)
3069 #define TIM12_BASE_NS                   (APB1PERIPH_BASE_NS + 0x1800UL)
3070 #define TIM13_BASE_NS                   (APB1PERIPH_BASE_NS + 0x1C00UL)
3071 #define TIM14_BASE_NS                   (APB1PERIPH_BASE_NS + 0x2000UL)
3072 #define LPTIM1_BASE_NS                  (APB1PERIPH_BASE_NS + 0x2400UL)
3073 #define WWDG_BASE_NS                    (APB1PERIPH_BASE_NS + 0x2C00UL)
3074 #define TIM10_BASE_NS                   (APB1PERIPH_BASE_NS + 0x3000UL)
3075 #define TIM11_BASE_NS                   (APB1PERIPH_BASE_NS + 0x3400UL)
3076 #define SPI2_BASE_NS                    (APB1PERIPH_BASE_NS + 0x3800UL)
3077 #define SPI3_BASE_NS                    (APB1PERIPH_BASE_NS + 0x3C00UL)
3078 #define SPDIFRX_BASE_NS                 (APB1PERIPH_BASE_NS + 0x4000UL)
3079 #define USART2_BASE_NS                  (APB1PERIPH_BASE_NS + 0x4400UL)
3080 #define USART3_BASE_NS                  (APB1PERIPH_BASE_NS + 0x4800UL)
3081 #define UART4_BASE_NS                   (APB1PERIPH_BASE_NS + 0x4C00UL)
3082 #define UART5_BASE_NS                   (APB1PERIPH_BASE_NS + 0x5000UL)
3083 #define I2C1_BASE_NS                    (APB1PERIPH_BASE_NS + 0x5400UL)
3084 #define I2C2_BASE_NS                    (APB1PERIPH_BASE_NS + 0x5800UL)
3085 #define I2C3_BASE_NS                    (APB1PERIPH_BASE_NS + 0x5C00UL)
3086 #define I3C1_BASE_NS                    (APB1PERIPH_BASE_NS + 0x6000UL)
3087 #define I3C2_BASE_NS                    (APB1PERIPH_BASE_NS + 0x6400UL)
3088 #define UART7_BASE_NS                   (APB1PERIPH_BASE_NS + 0x7800UL)
3089 #define UART8_BASE_NS                   (APB1PERIPH_BASE_NS + 0x7C00UL)
3090 #define MDIOS_BASE_NS                   (APB1PERIPH_BASE_NS + 0x9400UL)
3091 #define FDCAN1_BASE_NS                  (APB1PERIPH_BASE_NS + 0xA000UL)
3092 #define FDCAN_CONFIG_BASE_NS            (APB1PERIPH_BASE_NS + 0xA100UL)
3093 #define FDCAN2_BASE_NS                  (APB1PERIPH_BASE_NS + 0xA400UL)
3094 #define FDCAN_CCU_BASE_NS               (APB1PERIPH_BASE_NS + 0xA800UL)
3095 #define SRAMCAN_BASE_NS                 (APB1PERIPH_BASE_NS + 0xC000UL)
3096 #define FDCAN3_BASE_NS                  (APB1PERIPH_BASE_NS + 0xE800UL)
3097 #define UCPD1_BASE_NS                   (APB1PERIPH_BASE_NS + 0xFC00UL)
3098 
3099 /*!< AHB1 peripherals */
3100 #define GPDMA1_BASE_NS                  (AHB1PERIPH_BASE_NS + 0x1000UL)
3101 #define GPDMA1_Channel0_BASE_NS         (GPDMA1_BASE_NS + 0x0050UL)
3102 #define GPDMA1_Channel1_BASE_NS         (GPDMA1_BASE_NS + 0x00D0UL)
3103 #define GPDMA1_Channel2_BASE_NS         (GPDMA1_BASE_NS + 0x0150UL)
3104 #define GPDMA1_Channel3_BASE_NS         (GPDMA1_BASE_NS + 0x01D0UL)
3105 #define GPDMA1_Channel4_BASE_NS         (GPDMA1_BASE_NS + 0x0250UL)
3106 #define GPDMA1_Channel5_BASE_NS         (GPDMA1_BASE_NS + 0x02D0UL)
3107 #define GPDMA1_Channel6_BASE_NS         (GPDMA1_BASE_NS + 0x0350UL)
3108 #define GPDMA1_Channel7_BASE_NS         (GPDMA1_BASE_NS + 0x03D0UL)
3109 #define GPDMA1_Channel8_BASE_NS         (GPDMA1_BASE_NS + 0x0450UL)
3110 #define GPDMA1_Channel9_BASE_NS         (GPDMA1_BASE_NS + 0x04D0UL)
3111 #define GPDMA1_Channel10_BASE_NS        (GPDMA1_BASE_NS + 0x0550UL)
3112 #define GPDMA1_Channel11_BASE_NS        (GPDMA1_BASE_NS + 0x05D0UL)
3113 #define GPDMA1_Channel12_BASE_NS        (GPDMA1_BASE_NS + 0x0650UL)
3114 #define GPDMA1_Channel13_BASE_NS        (GPDMA1_BASE_NS + 0x06D0UL)
3115 #define GPDMA1_Channel14_BASE_NS        (GPDMA1_BASE_NS + 0x0750UL)
3116 #define GPDMA1_Channel15_BASE_NS        (GPDMA1_BASE_NS + 0x07D0UL)
3117 #define ADC1_BASE_NS                    (AHB1PERIPH_BASE_NS + 0x2000UL)
3118 #define ADC2_BASE_NS                    (AHB1PERIPH_BASE_NS + 0x2100UL)
3119 #define ADC12_COMMON_BASE_NS            (AHB1PERIPH_BASE_NS + 0x2300UL)
3120 
3121 /*!< APB2 peripherals */
3122 #define TIM1_BASE_NS                    (APB2PERIPH_BASE_NS + 0x0000UL)
3123 #define TIM8_BASE_NS                    (APB2PERIPH_BASE_NS + 0x0400UL)
3124 #define USART1_BASE_NS                  (APB2PERIPH_BASE_NS + 0x1000UL)
3125 #define USART6_BASE_NS                  (APB2PERIPH_BASE_NS + 0x1400UL)
3126 #define UART9_BASE_NS                   (APB2PERIPH_BASE_NS + 0x1800UL)
3127 #define USART10_BASE_NS                 (APB2PERIPH_BASE_NS + 0x1C00UL)
3128 #define SPI1_BASE_NS                    (APB2PERIPH_BASE_NS + 0x3000UL)
3129 #define SPI4_BASE_NS                    (APB2PERIPH_BASE_NS + 0x3400UL)
3130 #define TIM18_BASE_NS                   (APB2PERIPH_BASE_NS + 0x3C00UL)
3131 #define TIM15_BASE_NS                   (APB2PERIPH_BASE_NS + 0x4000UL)
3132 #define TIM16_BASE_NS                   (APB2PERIPH_BASE_NS + 0x4400UL)
3133 #define TIM17_BASE_NS                   (APB2PERIPH_BASE_NS + 0x4800UL)
3134 #define TIM9_BASE_NS                    (APB2PERIPH_BASE_NS + 0x4C00UL)
3135 #define SPI5_BASE_NS                    (APB2PERIPH_BASE_NS + 0x5000UL)
3136 #define SAI1_BASE_NS                    (APB2PERIPH_BASE_NS + 0x5800UL)
3137 #define SAI1_Block_A_BASE_NS            (SAI1_BASE_NS + 0x0004UL)
3138 #define SAI1_Block_B_BASE_NS            (SAI1_BASE_NS + 0x0024UL)
3139 #define SAI2_BASE_NS                    (APB2PERIPH_BASE_NS + 0x5C00UL)
3140 #define SAI2_Block_A_BASE_NS            (SAI2_BASE_NS + 0x0004UL)
3141 #define SAI2_Block_B_BASE_NS            (SAI2_BASE_NS + 0x0024UL)
3142 
3143 /*!< AHB2 peripherals */
3144 #define RAMCFG_BASE_NS                  (AHB2PERIPH_BASE_NS + 0x3000UL)
3145 #define RAMCFG_SRAM1_AXI_BASE_NS        (RAMCFG_BASE_NS)
3146 #define RAMCFG_SRAM2_AXI_BASE_NS        (RAMCFG_BASE_NS + 0x0080UL)
3147 #define RAMCFG_SRAM3_AXI_BASE_NS        (RAMCFG_BASE_NS + 0x0100UL)
3148 #define RAMCFG_SRAM4_AXI_BASE_NS        (RAMCFG_BASE_NS + 0x0180UL)
3149 #define RAMCFG_SRAM5_AXI_BASE_NS        (RAMCFG_BASE_NS + 0x0200UL)
3150 #define RAMCFG_SRAM6_AXI_BASE_NS        (RAMCFG_BASE_NS + 0x0280UL)
3151 #define RAMCFG_SRAM1_AHB_BASE_NS        (RAMCFG_BASE_NS + 0x0300UL)
3152 #define RAMCFG_SRAM2_AHB_BASE_NS        (RAMCFG_BASE_NS + 0x0380UL)
3153 #define RAMCFG_VENC_RAM_BASE_NS         (RAMCFG_BASE_NS + 0x0400UL)
3154 #define RAMCFG_BKPSRAM_BASE_NS          (RAMCFG_BASE_NS + 0x0480UL)
3155 #define RAMCFG_FLEXRAM_BASE_NS          (RAMCFG_BASE_NS + 0x0500UL)
3156 #define MDF1_BASE_NS                    (AHB2PERIPH_BASE_NS + 0x5000UL)
3157 #define MDF1_Filter0_BASE_NS            (MDF1_BASE_NS + 0x0080UL)
3158 #define MDF1_Filter1_BASE_NS            (MDF1_BASE_NS + 0x0100UL)
3159 #define MDF1_Filter2_BASE_NS            (MDF1_BASE_NS + 0x0180UL)
3160 #define MDF1_Filter3_BASE_NS            (MDF1_BASE_NS + 0x0200UL)
3161 #define MDF1_Filter4_BASE_NS            (MDF1_BASE_NS + 0x0280UL)
3162 #define MDF1_Filter5_BASE_NS            (MDF1_BASE_NS + 0x0300UL)
3163 #define ADF1_BASE_NS                    (AHB2PERIPH_BASE_NS + 0x6000UL)
3164 #define ADF1_Filter0_BASE_NS            (ADF1_BASE_NS + 0x0080UL)
3165 
3166 /*!< APB3 peripherals */
3167 #define DAP_ROM_BASE_NS                 (APB3PERIPH_BASE_NS + 0x0000UL)
3168 #define DBGMCU_BASE_NS                  (APB3PERIPH_BASE_NS + 0x1000UL)
3169 #define DFT_APB_BASE_NS                 (APB3PERIPH_BASE_NS + 0x2000UL)
3170 
3171 /*!< AHB3 peripherals */
3172 #define RNG_BASE_NS                     (AHB3PERIPH_BASE_NS + 0x0000UL)
3173 #define HASH_BASE_NS                    (AHB3PERIPH_BASE_NS + 0x0400UL)
3174 #define HASH_DIGEST_BASE_NS             (AHB3PERIPH_BASE_NS + 0x0710UL)
3175 #define CRYP_BASE_NS                    (AHB3PERIPH_BASE_NS + 0x0800UL)
3176 #define SAES_BASE_NS                    (AHB3PERIPH_BASE_NS + 0x1000UL)
3177 #define PKA_BASE_NS                     (AHB3PERIPH_BASE_NS + 0x2000UL)
3178 #define RIFSC_BASE_NS                   (AHB3PERIPH_BASE_NS + 0x4000UL)
3179 #define RISAF1_BASE_NS                  (AHB3PERIPH_BASE_NS + 0x6000UL)
3180 #define RISAF2_BASE_NS                  (AHB3PERIPH_BASE_NS + 0x7000UL)
3181 #define RISAF3_BASE_NS                  (AHB3PERIPH_BASE_NS + 0x8000UL)
3182 #define RISAF4_BASE_NS                  (AHB3PERIPH_BASE_NS + 0x9000UL)
3183 #define RISAF5_BASE_NS                  (AHB3PERIPH_BASE_NS + 0xA000UL)
3184 #define RISAF6_BASE_NS                  (AHB3PERIPH_BASE_NS + 0xB000UL)
3185 #define RISAF7_BASE_NS                  (AHB3PERIPH_BASE_NS + 0xC000UL)
3186 #define RISAF8_BASE_NS                  (AHB3PERIPH_BASE_NS + 0xD000UL)
3187 #define RISAF9_BASE_NS                  (AHB3PERIPH_BASE_NS + 0xE000UL)
3188 #define RISAF11_BASE_NS                 (AHB3PERIPH_BASE_NS + 0x010000UL)
3189 #define RISAF12_BASE_NS                 (AHB3PERIPH_BASE_NS + 0x011000UL)
3190 #define RISAF13_BASE_NS                 (AHB3PERIPH_BASE_NS + 0x012000UL)
3191 #define RISAF14_BASE_NS                 (AHB3PERIPH_BASE_NS + 0x013000UL)
3192 #define RISAF15_BASE_NS                 (AHB3PERIPH_BASE_NS + 0x014000UL)
3193 #define RISAF21_BASE_NS                 (AHB3PERIPH_BASE_NS + 0x015000UL)
3194 #define RISAF22_BASE_NS                 (AHB3PERIPH_BASE_NS + 0x016000UL)
3195 #define RISAF23_BASE_NS                 (AHB3PERIPH_BASE_NS + 0x017000UL)
3196 
3197 /*!< APB4 peripherals */
3198 #define HDP_BASE_NS                     (APB4PERIPH_BASE_NS + 0x0800UL)
3199 #define LPUART1_BASE_NS                 (APB4PERIPH_BASE_NS + 0x0C00UL)
3200 #define SPI6_BASE_NS                    (APB4PERIPH_BASE_NS + 0x1400UL)
3201 #define I2C4_BASE_NS                    (APB4PERIPH_BASE_NS + 0x1C00UL)
3202 #define LPTIM2_BASE_NS                  (APB4PERIPH_BASE_NS + 0x2400UL)
3203 #define LPTIM3_BASE_NS                  (APB4PERIPH_BASE_NS + 0x2800UL)
3204 #define LPTIM4_BASE_NS                  (APB4PERIPH_BASE_NS + 0x2C00UL)
3205 #define LPTIM5_BASE_NS                  (APB4PERIPH_BASE_NS + 0x3000UL)
3206 #define VREFBUF_BASE_NS                 (APB4PERIPH_BASE_NS + 0x3C00UL)
3207 #define RTC_BASE_NS                     (APB4PERIPH_BASE_NS + 0x4000UL)
3208 #define TAMP_BASE_NS                    (APB4PERIPH_BASE_NS + 0x4400UL)
3209 #define IWDG_BASE_NS                    (APB4PERIPH_BASE_NS + 0x4800UL)
3210 #define SERC_BASE_NS                    (APB4PERIPH_BASE_NS + 0x7C00UL)
3211 #define SYSCFG_BASE_NS                  (APB4PERIPH_BASE_NS + 0x8000UL)
3212 #define BSEC_BASE_NS                    (APB4PERIPH_BASE_NS + 0x9000UL)
3213 #define DTS_BASE_NS                     (APB4PERIPH_BASE_NS + 0xA000UL)
3214 #define DTS_Sensor0_BASE_NS             (DTS_BASE_NS + 0x0C0UL)
3215 #define DTS_Sensor1_BASE_NS             (DTS_BASE_NS + 0x100UL)
3216 
3217 /*!< AHB4 peripherals */
3218 #define GPIOA_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x0000UL)
3219 #define GPIOB_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x0400UL)
3220 #define GPIOC_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x0800UL)
3221 #define GPIOD_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x0C00UL)
3222 #define GPIOE_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x1000UL)
3223 #define GPIOF_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x1400UL)
3224 #define GPIOG_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x1800UL)
3225 #define GPIOH_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x1C00UL)
3226 #define GPION_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x3400UL)
3227 #define GPIOO_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x3800UL)
3228 #define GPIOP_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x3C00UL)
3229 #define GPIOQ_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x4000UL)
3230 #define PWR_BASE_NS                     (AHB4PERIPH_BASE_NS + 0x4800UL)
3231 #define CRC_BASE_NS                     (AHB4PERIPH_BASE_NS + 0x4C00UL)
3232 #define EXTI_BASE_NS                    (AHB4PERIPH_BASE_NS + 0x5000UL)
3233 #define RCC_BASE_NS                     (AHB4PERIPH_BASE_NS + 0x8000UL)
3234 
3235 /*!< APB5 peripherals */
3236 #define LTDC_BASE_NS                    (APB5PERIPH_BASE_NS + 0x1000UL)
3237 #define LTDC_Layer1_BASE_NS             (LTDC_BASE_NS + 0x0100UL)
3238 #define LTDC_Layer2_BASE_NS             (LTDC_BASE_NS + 0x0200UL)
3239 #define DCMIPP_BASE_NS                  (APB5PERIPH_BASE_NS + 0x2000UL)
3240 #define GFXTIM_BASE_NS                  (APB5PERIPH_BASE_NS + 0x4000UL)
3241 #define VENC_BASE_NS                    (APB5PERIPH_BASE_NS + 0x5000UL)
3242 #define CSI_BASE_NS                     (APB5PERIPH_BASE_NS + 0x6000UL)
3243 
3244 /*!< AHB5 peripherals */
3245 #define HPDMA1_BASE_NS                  (AHB5PERIPH_BASE_NS + 0x0000UL)
3246 #define HPDMA1_Channel0_BASE_NS         (HPDMA1_BASE_NS + 0x0050UL)
3247 #define HPDMA1_Channel1_BASE_NS         (HPDMA1_BASE_NS + 0x00D0UL)
3248 #define HPDMA1_Channel2_BASE_NS         (HPDMA1_BASE_NS + 0x0150UL)
3249 #define HPDMA1_Channel3_BASE_NS         (HPDMA1_BASE_NS + 0x01D0UL)
3250 #define HPDMA1_Channel4_BASE_NS         (HPDMA1_BASE_NS + 0x0250UL)
3251 #define HPDMA1_Channel5_BASE_NS         (HPDMA1_BASE_NS + 0x02D0UL)
3252 #define HPDMA1_Channel6_BASE_NS         (HPDMA1_BASE_NS + 0x0350UL)
3253 #define HPDMA1_Channel7_BASE_NS         (HPDMA1_BASE_NS + 0x03D0UL)
3254 #define HPDMA1_Channel8_BASE_NS         (HPDMA1_BASE_NS + 0x0450UL)
3255 #define HPDMA1_Channel9_BASE_NS         (HPDMA1_BASE_NS + 0x04D0UL)
3256 #define HPDMA1_Channel10_BASE_NS        (HPDMA1_BASE_NS + 0x0550UL)
3257 #define HPDMA1_Channel11_BASE_NS        (HPDMA1_BASE_NS + 0x05D0UL)
3258 #define HPDMA1_Channel12_BASE_NS        (HPDMA1_BASE_NS + 0x0650UL)
3259 #define HPDMA1_Channel13_BASE_NS        (HPDMA1_BASE_NS + 0x06D0UL)
3260 #define HPDMA1_Channel14_BASE_NS        (HPDMA1_BASE_NS + 0x0750UL)
3261 #define HPDMA1_Channel15_BASE_NS        (HPDMA1_BASE_NS + 0x07D0UL)
3262 #define DMA2D_BASE_NS                   (AHB5PERIPH_BASE_NS + 0x1000UL)
3263 #define JPEG_BASE_NS                    (AHB5PERIPH_BASE_NS + 0x3000UL)
3264 #define FMC_R_BASE_NS                   (AHB5PERIPH_BASE_NS + 0x4000UL)
3265 #define FMC_Bank1_R_BASE_NS             (FMC_R_BASE_NS + 0x0000UL)
3266 #define FMC_Bank1E_R_BASE_NS            (FMC_R_BASE_NS + 0x0104UL)
3267 #define FMC_Bank3_R_BASE_NS             (FMC_R_BASE_NS + 0x0080UL)
3268 #define FMC_Bank5_6_R_BASE_NS           (FMC_R_BASE_NS + 0x0140UL)
3269 #define FMC_Common_R_BASE_NS            (FMC_R_BASE_NS + 0x0020UL)
3270 #define XSPI1_BASE_NS                   (AHB5PERIPH_BASE_NS + 0x5000UL)
3271 #define PSSI_BASE_NS                    (AHB5PERIPH_BASE_NS + 0x6400UL)
3272 #define SDMMC2_BASE_NS                  (AHB5PERIPH_BASE_NS + 0x6800UL)
3273 #define DLYB_SDMMC2_BASE_NS             (AHB5PERIPH_BASE_NS + 0x6C00UL)
3274 #define SDMMC1_BASE_NS                  (AHB5PERIPH_BASE_NS + 0x7000UL)
3275 #define DLYB_SDMMC1_BASE_NS             (AHB5PERIPH_BASE_NS + 0x8000UL)
3276 #define DCMI_BASE_NS                    (AHB5PERIPH_BASE_NS + 0x8400UL)
3277 #define XSPI2_BASE_NS                   (AHB5PERIPH_BASE_NS + 0xA000UL)
3278 #define XSPIM_BASE_NS                   (AHB5PERIPH_BASE_NS + 0xB400UL)
3279 #define MCE1_BASE_NS                    (AHB5PERIPH_BASE_NS + 0xB800UL)
3280 #define MCE1_REGION1_BASE_NS            (MCE1_BASE_NS + 0x040UL)
3281 #define MCE1_REGION2_BASE_NS            (MCE1_BASE_NS + 0x050UL)
3282 #define MCE1_REGION3_BASE_NS            (MCE1_BASE_NS + 0x060UL)
3283 #define MCE1_REGION4_BASE_NS            (MCE1_BASE_NS + 0x070UL)
3284 #define MCE1_CONTEXT1_BASE_NS           (MCE1_BASE_NS + 0x240UL)
3285 #define MCE1_CONTEXT2_BASE_NS           (MCE1_BASE_NS + 0x270UL)
3286 #define MCE2_BASE_NS                    (AHB5PERIPH_BASE_NS + 0xBC00UL)
3287 #define MCE2_REGION1_BASE_NS            (MCE2_BASE_NS + 0x040UL)
3288 #define MCE2_REGION2_BASE_NS            (MCE2_BASE_NS + 0x050UL)
3289 #define MCE2_REGION3_BASE_NS            (MCE2_BASE_NS + 0x060UL)
3290 #define MCE2_REGION4_BASE_NS            (MCE2_BASE_NS + 0x070UL)
3291 #define MCE2_CONTEXT1_BASE_NS           (MCE2_BASE_NS + 0x240UL)
3292 #define MCE2_CONTEXT2_BASE_NS           (MCE2_BASE_NS + 0x270UL)
3293 #define MCE3_BASE_NS                    (AHB5PERIPH_BASE_NS + 0xC000UL)
3294 #define MCE3_REGION1_BASE_NS            (MCE3_BASE_NS + 0x040UL)
3295 #define MCE3_REGION2_BASE_NS            (MCE3_BASE_NS + 0x050UL)
3296 #define MCE3_REGION3_BASE_NS            (MCE3_BASE_NS + 0x060UL)
3297 #define MCE3_REGION4_BASE_NS            (MCE3_BASE_NS + 0x070UL)
3298 #define MCE3_CONTEXT1_BASE_NS           (MCE3_BASE_NS + 0x240UL)
3299 #define MCE3_CONTEXT2_BASE_NS           (MCE3_BASE_NS + 0x270UL)
3300 #define MCE4_BASE_NS                    (AHB5PERIPH_BASE_NS + 0xE000UL)
3301 #define MCE4_REGION1_BASE_NS            (MCE4_BASE_NS + 0x040UL)
3302 #define MCE4_REGION2_BASE_NS            (MCE4_BASE_NS + 0x050UL)
3303 #define MCE4_REGION3_BASE_NS            (MCE4_BASE_NS + 0x060UL)
3304 #define MCE4_REGION4_BASE_NS            (MCE4_BASE_NS + 0x070UL)
3305 #define MCE4_CONTEXT1_BASE_NS           (MCE4_BASE_NS + 0x240UL)
3306 #define MCE4_CONTEXT2_BASE_NS           (MCE4_BASE_NS + 0x270UL)
3307 #define XSPI3_BASE_NS                   (AHB5PERIPH_BASE_NS + 0xD000UL)
3308 #define GFXMMU_BASE_NS                  (AHB5PERIPH_BASE_NS + 0x010000UL)
3309 #define GPU2D_BASE_NS                   (AHB5PERIPH_BASE_NS + 0x014000UL)
3310 #define GPUCACHE_BASE_NS                (AHB5PERIPH_BASE_NS + 0x015000UL)
3311 #define ICACHE_BASE_NS                  (AHB5PERIPH_BASE_NS + 0x015000UL)
3312 #define ETH1_BASE_NS                    (AHB5PERIPH_BASE_NS + 0x016000UL)
3313 #define ETH1_MAC_BASE_NS                (ETH1_BASE_NS)
3314 #define USB1_HS_PHYC_BASE_NS            (AHB5PERIPH_BASE_NS + 0x01FC00UL)
3315 #define USB2_HS_PHYC_BASE_NS            (AHB5PERIPH_BASE_NS + 0x0A0000UL)
3316 #define USB1_OTG_HS_BASE_NS             (AHB5PERIPH_BASE_NS + 0x020000UL)
3317 #define USB2_OTG_HS_BASE_NS             (AHB5PERIPH_BASE_NS + 0x060000UL)
3318 #define CACHEAXI_BASE_NS                (AHB5PERIPH_BASE_NS + 0x0BFC00UL)
3319 #define NPU_BASE_NS                     (AHB5PERIPH_BASE_NS + 0x0C0000UL)
3320 
3321 
3322 /*!< Unique device ID register base address */
3323 #define UID_BASE_NS                     (0x46009014UL)
3324 
3325 /*!< Revision ID base address */
3326 #define REVID_BASE_NS                   (BOOTROM_BASE_NS + 0x0047ECUL)
3327 
3328 
3329 #if defined (CPU_IN_SECURE_STATE)
3330 /*********************************************************************/
3331 /*                                                                   */
3332 /* Peripheral and internal SRAMs base addresses - Secure (aliased_S) */
3333 /*                                                                   */
3334 /*********************************************************************/
3335 #define ITCM_BASE_S                     0x10000000UL /*!< Base address of ITCM from 64 KB up to 256 KB               */
3336 #define BOOTROM_BASE_S                  0x18000000UL /*!< Base address of 128 KB boot ROM accessible over AXI        */
3337 #define DTCM_BASE_S                     0x30000000UL /*!< Base address of DTCM from 128 KB up to 256 KB              */
3338 #define SRAM1_AXI_BASE_S                0x34000000UL /*!< Base address of up to 1 MB system RAM 1 accessible over AXI */
3339 #define SRAM2_AXI_BASE_S                0x34100000UL /*!< Base address of 1 MB system RAM 2 accessible over AXI      */
3340 #define SRAM3_AXI_BASE_S                0x34200000UL /*!< Base address of 448 KB system RAM 3 accessible over AXI      */
3341 #define SRAM4_AXI_BASE_S                0x34270000UL /*!< Base address of 448 KB system RAM 4 accessible over AXI */
3342 #define SRAM5_AXI_BASE_S                0x342E0000UL /*!< Base address of 448 KB system RAM 5 accessible over AXI */
3343 #define SRAM6_AXI_BASE_S                0x34350000UL /*!< Base address of 448 KB system RAM 6 accessible over AXI */
3344 #define SRAM_AXI_BASE_S                 SRAM1_AXI_BASE_NS /*!< Base address of 3.792 MB system RAM accessible over AXI */
3345 #define CACHEAXI_RAM_BASE_S             0x343C0000UL /*!< Base address of 256 KB NPU Cache RAM accessible over AXI   */
3346 #define VENC_RAM_BASE_S                 0x34400000UL /*!< Base address of 128 KB of Video Encoder RAM accessible over AXI */
3347 #define GFXMMU_VIRTUAL_BUFFER0_BASE_S   0x35000000UL /*!< Base address of 4 MB GFXMMU virtual buffer 0               */
3348 #define GFXMMU_VIRTUAL_BUFFER1_BASE_S   0x35400000UL /*!< Base address of 4 MB GFXMMU virtual buffer 1               */
3349 #define GFXMMU_VIRTUAL_BUFFER2_BASE_S   0x35800000UL /*!< Base address of 4 MB GFXMMU virtual buffer 2               */
3350 #define GFXMMU_VIRTUAL_BUFFER3_BASE_S   0x35C00000UL /*!< Base address of 4 MB GFXMMU virtual buffer 3               */
3351 #define STM500_CHANNELS_BASE_S          0x37F00000UL /*!< Base address of 1 MB of STM500 Channels (System Trace)     */
3352 #define SRAM1_AHB_BASE_S                0x38000000UL /*!< Base address of 16 KB system RAM 1 over AXI->AHB Bridge    */
3353 #define SRAM2_AHB_BASE_S                0x38004000UL /*!< Base address of 16 KB system RAM 2 over AXI->AHB Bridge    */
3354 #define SRAM_AHB_BASE_S                 SRAM1_AHB_BASE_S /*!< Base address of 32 KB system RAM over AXI->AHB Bridge  */
3355 #define BKPSRAM_BASE_S                  0x3C000000UL   /*!< Base address of 8 KB Backup SRAM over AXI->AHB Bridge    */
3356 #define PERIPH_BASE_S                   0x50000000UL   /*!< Base address of : AHB/APB Peripherals                    */
3357 
3358 /*!< Peripheral memory map */
3359 #define APB1PERIPH_BASE_S               PERIPH_BASE_S
3360 #define AHB1PERIPH_BASE_S               (PERIPH_BASE_S + 0x00020000UL)
3361 #define APB2PERIPH_BASE_S               (PERIPH_BASE_S + 0x02000000UL)
3362 #define AHB2PERIPH_BASE_S               (PERIPH_BASE_S + 0x02020000UL)
3363 #define APB3PERIPH_BASE_S               (PERIPH_BASE_S + 0x04000000UL)
3364 #define AHB3PERIPH_BASE_S               (PERIPH_BASE_S + 0x04020000UL)
3365 #define APB4PERIPH_BASE_S               (PERIPH_BASE_S + 0x06000000UL)
3366 #define AHB4PERIPH_BASE_S               (PERIPH_BASE_S + 0x06020000UL)
3367 #define APB5PERIPH_BASE_S               (PERIPH_BASE_S + 0x08000000UL)
3368 #define AHB5PERIPH_BASE_S               (PERIPH_BASE_S + 0x08020000UL)
3369 
3370 /*!< APB1 peripherals */
3371 #define TIM2_BASE_S                     (APB1PERIPH_BASE_S + 0x0000UL)
3372 #define TIM3_BASE_S                     (APB1PERIPH_BASE_S + 0x0400UL)
3373 #define TIM4_BASE_S                     (APB1PERIPH_BASE_S + 0x0800UL)
3374 #define TIM5_BASE_S                     (APB1PERIPH_BASE_S + 0x0C00UL)
3375 #define TIM6_BASE_S                     (APB1PERIPH_BASE_S + 0x1000UL)
3376 #define TIM7_BASE_S                     (APB1PERIPH_BASE_S + 0x1400UL)
3377 #define TIM12_BASE_S                    (APB1PERIPH_BASE_S + 0x1800UL)
3378 #define TIM13_BASE_S                    (APB1PERIPH_BASE_S + 0x1C00UL)
3379 #define TIM14_BASE_S                    (APB1PERIPH_BASE_S + 0x2000UL)
3380 #define LPTIM1_BASE_S                   (APB1PERIPH_BASE_S + 0x2400UL)
3381 #define WWDG_BASE_S                     (APB1PERIPH_BASE_S + 0x2C00UL)
3382 #define TIM10_BASE_S                    (APB1PERIPH_BASE_S + 0x3000UL)
3383 #define TIM11_BASE_S                    (APB1PERIPH_BASE_S + 0x3400UL)
3384 #define SPI2_BASE_S                     (APB1PERIPH_BASE_S + 0x3800UL)
3385 #define SPI3_BASE_S                     (APB1PERIPH_BASE_S + 0x3C00UL)
3386 #define SPDIFRX_BASE_S                  (APB1PERIPH_BASE_S + 0x4000UL)
3387 #define USART2_BASE_S                   (APB1PERIPH_BASE_S + 0x4400UL)
3388 #define USART3_BASE_S                   (APB1PERIPH_BASE_S + 0x4800UL)
3389 #define UART4_BASE_S                    (APB1PERIPH_BASE_S + 0x4C00UL)
3390 #define UART5_BASE_S                    (APB1PERIPH_BASE_S + 0x5000UL)
3391 #define I2C1_BASE_S                     (APB1PERIPH_BASE_S + 0x5400UL)
3392 #define I2C2_BASE_S                     (APB1PERIPH_BASE_S + 0x5800UL)
3393 #define I2C3_BASE_S                     (APB1PERIPH_BASE_S + 0x5C00UL)
3394 #define I3C1_BASE_S                     (APB1PERIPH_BASE_S + 0x6000UL)
3395 #define I3C2_BASE_S                     (APB1PERIPH_BASE_S + 0x6400UL)
3396 #define UART7_BASE_S                    (APB1PERIPH_BASE_S + 0x7800UL)
3397 #define UART8_BASE_S                    (APB1PERIPH_BASE_S + 0x7C00UL)
3398 #define MDIOS_BASE_S                    (APB1PERIPH_BASE_S + 0x9400UL)
3399 #define FDCAN1_BASE_S                   (APB1PERIPH_BASE_S + 0xA000UL)
3400 #define FDCAN_CONFIG_BASE_S             (APB1PERIPH_BASE_S + 0xA100UL)
3401 #define FDCAN2_BASE_S                   (APB1PERIPH_BASE_S + 0xA400UL)
3402 #define FDCAN_CCU_BASE_S                (APB1PERIPH_BASE_S + 0xA800UL)
3403 #define SRAMCAN_BASE_S                  (APB1PERIPH_BASE_S + 0xC000UL)
3404 #define FDCAN3_BASE_S                   (APB1PERIPH_BASE_S + 0xE800UL)
3405 #define UCPD1_BASE_S                    (APB1PERIPH_BASE_S + 0xFC00UL)
3406 
3407 /*!< AHB1 peripherals */
3408 #define GPDMA1_BASE_S                   (AHB1PERIPH_BASE_S + 0x1000UL)
3409 #define GPDMA1_Channel0_BASE_S          (GPDMA1_BASE_S + 0x0050UL)
3410 #define GPDMA1_Channel1_BASE_S          (GPDMA1_BASE_S + 0x00D0UL)
3411 #define GPDMA1_Channel2_BASE_S          (GPDMA1_BASE_S + 0x0150UL)
3412 #define GPDMA1_Channel3_BASE_S          (GPDMA1_BASE_S + 0x01D0UL)
3413 #define GPDMA1_Channel4_BASE_S          (GPDMA1_BASE_S + 0x0250UL)
3414 #define GPDMA1_Channel5_BASE_S          (GPDMA1_BASE_S + 0x02D0UL)
3415 #define GPDMA1_Channel6_BASE_S          (GPDMA1_BASE_S + 0x0350UL)
3416 #define GPDMA1_Channel7_BASE_S          (GPDMA1_BASE_S + 0x03D0UL)
3417 #define GPDMA1_Channel8_BASE_S          (GPDMA1_BASE_S + 0x0450UL)
3418 #define GPDMA1_Channel9_BASE_S          (GPDMA1_BASE_S + 0x04D0UL)
3419 #define GPDMA1_Channel10_BASE_S         (GPDMA1_BASE_S + 0x0550UL)
3420 #define GPDMA1_Channel11_BASE_S         (GPDMA1_BASE_S + 0x05D0UL)
3421 #define GPDMA1_Channel12_BASE_S         (GPDMA1_BASE_S + 0x0650UL)
3422 #define GPDMA1_Channel13_BASE_S         (GPDMA1_BASE_S + 0x06D0UL)
3423 #define GPDMA1_Channel14_BASE_S         (GPDMA1_BASE_S + 0x0750UL)
3424 #define GPDMA1_Channel15_BASE_S         (GPDMA1_BASE_S + 0x07D0UL)
3425 #define ADC1_BASE_S                     (AHB1PERIPH_BASE_S + 0x2000UL)
3426 #define ADC2_BASE_S                     (AHB1PERIPH_BASE_S + 0x2100UL)
3427 #define ADC12_COMMON_BASE_S             (AHB1PERIPH_BASE_S + 0x2300UL)
3428 
3429 /*!< APB2 peripherals */
3430 #define TIM1_BASE_S                     (APB2PERIPH_BASE_S + 0x0000UL)
3431 #define TIM8_BASE_S                     (APB2PERIPH_BASE_S + 0x0400UL)
3432 #define USART1_BASE_S                   (APB2PERIPH_BASE_S + 0x1000UL)
3433 #define USART6_BASE_S                   (APB2PERIPH_BASE_S + 0x1400UL)
3434 #define UART9_BASE_S                    (APB2PERIPH_BASE_S + 0x1800UL)
3435 #define USART10_BASE_S                  (APB2PERIPH_BASE_S + 0x1C00UL)
3436 #define SPI1_BASE_S                     (APB2PERIPH_BASE_S + 0x3000UL)
3437 #define SPI4_BASE_S                     (APB2PERIPH_BASE_S + 0x3400UL)
3438 #define TIM18_BASE_S                    (APB2PERIPH_BASE_S + 0x3C00UL)
3439 #define TIM15_BASE_S                    (APB2PERIPH_BASE_S + 0x4000UL)
3440 #define TIM16_BASE_S                    (APB2PERIPH_BASE_S + 0x4400UL)
3441 #define TIM17_BASE_S                    (APB2PERIPH_BASE_S + 0x4800UL)
3442 #define TIM9_BASE_S                     (APB2PERIPH_BASE_S + 0x4C00UL)
3443 #define SPI5_BASE_S                     (APB2PERIPH_BASE_S + 0x5000UL)
3444 #define SAI1_BASE_S                     (APB2PERIPH_BASE_S + 0x5800UL)
3445 #define SAI1_Block_A_BASE_S             (SAI1_BASE_S + 0x0004UL)
3446 #define SAI1_Block_B_BASE_S             (SAI1_BASE_S + 0x0024UL)
3447 #define SAI2_BASE_S                     (APB2PERIPH_BASE_S + 0x5C00UL)
3448 #define SAI2_Block_A_BASE_S             (SAI2_BASE_S + 0x0004UL)
3449 #define SAI2_Block_B_BASE_S             (SAI2_BASE_S + 0x0024UL)
3450 
3451 /*!< AHB2 peripherals */
3452 #define RAMCFG_BASE_S                   (AHB2PERIPH_BASE_S + 0x3000UL)
3453 #define RAMCFG_SRAM1_AXI_BASE_S         (RAMCFG_BASE_S)
3454 #define RAMCFG_SRAM2_AXI_BASE_S         (RAMCFG_BASE_S + 0x0080UL)
3455 #define RAMCFG_SRAM3_AXI_BASE_S         (RAMCFG_BASE_S + 0x0100UL)
3456 #define RAMCFG_SRAM4_AXI_BASE_S         (RAMCFG_BASE_S + 0x0180UL)
3457 #define RAMCFG_SRAM5_AXI_BASE_S         (RAMCFG_BASE_S + 0x0200UL)
3458 #define RAMCFG_SRAM6_AXI_BASE_S         (RAMCFG_BASE_S + 0x0280UL)
3459 #define RAMCFG_SRAM1_AHB_BASE_S         (RAMCFG_BASE_S + 0x0300UL)
3460 #define RAMCFG_SRAM2_AHB_BASE_S         (RAMCFG_BASE_S + 0x0380UL)
3461 #define RAMCFG_VENC_RAM_BASE_S          (RAMCFG_BASE_S + 0x0400UL)
3462 #define RAMCFG_BKPSRAM_BASE_S           (RAMCFG_BASE_S + 0x0480UL)
3463 #define RAMCFG_FLEXRAM_BASE_S           (RAMCFG_BASE_S + 0x0500UL)
3464 #define MDF1_BASE_S                     (AHB2PERIPH_BASE_S + 0x5000UL)
3465 #define MDF1_Filter0_BASE_S             (MDF1_BASE_S + 0x0080UL)
3466 #define MDF1_Filter1_BASE_S             (MDF1_BASE_S + 0x0100UL)
3467 #define MDF1_Filter2_BASE_S             (MDF1_BASE_S + 0x0180UL)
3468 #define MDF1_Filter3_BASE_S             (MDF1_BASE_S + 0x0200UL)
3469 #define MDF1_Filter4_BASE_S             (MDF1_BASE_S + 0x0280UL)
3470 #define MDF1_Filter5_BASE_S             (MDF1_BASE_S + 0x0300UL)
3471 #define ADF1_BASE_S                     (AHB2PERIPH_BASE_S + 0x6000UL)
3472 #define ADF1_Filter0_BASE_S             (ADF1_BASE_S + 0x0080UL)
3473 
3474 /*!< APB3 peripherals */
3475 #define DAP_ROM_BASE_S                  (APB3PERIPH_BASE_S + 0x0000UL)
3476 #define DBGMCU_BASE_S                   (APB3PERIPH_BASE_S + 0x1000UL)
3477 #define DFT_APB_BASE_S                  (APB3PERIPH_BASE_S + 0x2000UL)
3478 
3479 /*!< AHB3 peripherals */
3480 #define RNG_BASE_S                      (AHB3PERIPH_BASE_S + 0x0000UL)
3481 #define HASH_BASE_S                     (AHB3PERIPH_BASE_S + 0x0400UL)
3482 #define HASH_DIGEST_BASE_S              (AHB3PERIPH_BASE_S + 0x0710UL)
3483 #define CRYP_BASE_S                     (AHB3PERIPH_BASE_S + 0x0800UL)
3484 #define SAES_BASE_S                     (AHB3PERIPH_BASE_S + 0x1000UL)
3485 #define PKA_BASE_S                      (AHB3PERIPH_BASE_S + 0x2000UL)
3486 #define RIFSC_BASE_S                    (AHB3PERIPH_BASE_S + 0x4000UL)
3487 #define IAC_BASE_S                      (AHB3PERIPH_BASE_S + 0x5000UL)
3488 #define RISAF1_BASE_S                   (AHB3PERIPH_BASE_S + 0x6000UL)
3489 #define RISAF2_BASE_S                   (AHB3PERIPH_BASE_S + 0x7000UL)
3490 #define RISAF3_BASE_S                   (AHB3PERIPH_BASE_S + 0x8000UL)
3491 #define RISAF4_BASE_S                   (AHB3PERIPH_BASE_S + 0x9000UL)
3492 #define RISAF5_BASE_S                   (AHB3PERIPH_BASE_S + 0xA000UL)
3493 #define RISAF6_BASE_S                   (AHB3PERIPH_BASE_S + 0xB000UL)
3494 #define RISAF7_BASE_S                   (AHB3PERIPH_BASE_S + 0xC000UL)
3495 #define RISAF8_BASE_S                   (AHB3PERIPH_BASE_S + 0xD000UL)
3496 #define RISAF9_BASE_S                   (AHB3PERIPH_BASE_S + 0xE000UL)
3497 #define RISAF11_BASE_S                  (AHB3PERIPH_BASE_S + 0x010000UL)
3498 #define RISAF12_BASE_S                  (AHB3PERIPH_BASE_S + 0x011000UL)
3499 #define RISAF13_BASE_S                  (AHB3PERIPH_BASE_S + 0x012000UL)
3500 #define RISAF14_BASE_S                  (AHB3PERIPH_BASE_S + 0x013000UL)
3501 #define RISAF15_BASE_S                  (AHB3PERIPH_BASE_S + 0x014000UL)
3502 #define RISAF21_BASE_S                  (AHB3PERIPH_BASE_S + 0x015000UL)
3503 #define RISAF22_BASE_S                  (AHB3PERIPH_BASE_S + 0x016000UL)
3504 #define RISAF23_BASE_S                  (AHB3PERIPH_BASE_S + 0x017000UL)
3505 
3506 /*!< APB4 peripherals */
3507 #define HDP_BASE_S                      (APB4PERIPH_BASE_S + 0x0800UL)
3508 #define LPUART1_BASE_S                  (APB4PERIPH_BASE_S + 0x0C00UL)
3509 #define SPI6_BASE_S                     (APB4PERIPH_BASE_S + 0x1400UL)
3510 #define I2C4_BASE_S                     (APB4PERIPH_BASE_S + 0x1C00UL)
3511 #define LPTIM2_BASE_S                   (APB4PERIPH_BASE_S + 0x2400UL)
3512 #define LPTIM3_BASE_S                   (APB4PERIPH_BASE_S + 0x2800UL)
3513 #define LPTIM4_BASE_S                   (APB4PERIPH_BASE_S + 0x2C00UL)
3514 #define LPTIM5_BASE_S                   (APB4PERIPH_BASE_S + 0x3000UL)
3515 #define VREFBUF_BASE_S                  (APB4PERIPH_BASE_S + 0x3C00UL)
3516 #define RTC_BASE_S                      (APB4PERIPH_BASE_S + 0x4000UL)
3517 #define TAMP_BASE_S                     (APB4PERIPH_BASE_S + 0x4400UL)
3518 #define IWDG_BASE_S                     (APB4PERIPH_BASE_S + 0x4800UL)
3519 
3520 #define SERC_BASE_S                     (APB4PERIPH_BASE_S + 0x7C00UL)
3521 #define SYSCFG_BASE_S                   (APB4PERIPH_BASE_S + 0x8000UL)
3522 #define BSEC_BASE_S                     (APB4PERIPH_BASE_S + 0x9000UL)
3523 #define DTS_BASE_S                      (APB4PERIPH_BASE_S + 0xA000UL)
3524 #define DTS_Sensor0_BASE_S              (DTS_BASE_S + 0x0C0UL)
3525 #define DTS_Sensor1_BASE_S              (DTS_BASE_S + 0x100UL)
3526 
3527 /*!< AHB4 peripherals */
3528 #define GPIOA_BASE_S                    (AHB4PERIPH_BASE_S + 0x0000UL)
3529 #define GPIOB_BASE_S                    (AHB4PERIPH_BASE_S + 0x0400UL)
3530 #define GPIOC_BASE_S                    (AHB4PERIPH_BASE_S + 0x0800UL)
3531 #define GPIOD_BASE_S                    (AHB4PERIPH_BASE_S + 0x0C00UL)
3532 #define GPIOE_BASE_S                    (AHB4PERIPH_BASE_S + 0x1000UL)
3533 #define GPIOF_BASE_S                    (AHB4PERIPH_BASE_S + 0x1400UL)
3534 #define GPIOG_BASE_S                    (AHB4PERIPH_BASE_S + 0x1800UL)
3535 #define GPIOH_BASE_S                    (AHB4PERIPH_BASE_S + 0x1C00UL)
3536 #define GPION_BASE_S                    (AHB4PERIPH_BASE_S + 0x3400UL)
3537 #define GPIOO_BASE_S                    (AHB4PERIPH_BASE_S + 0x3800UL)
3538 #define GPIOP_BASE_S                    (AHB4PERIPH_BASE_S + 0x3C00UL)
3539 #define GPIOQ_BASE_S                    (AHB4PERIPH_BASE_S + 0x4000UL)
3540 #define PWR_BASE_S                      (AHB4PERIPH_BASE_S + 0x4800UL)
3541 #define CRC_BASE_S                      (AHB4PERIPH_BASE_S + 0x4C00UL)
3542 #define EXTI_BASE_S                     (AHB4PERIPH_BASE_S + 0x5000UL)
3543 #define RCC_BASE_S                      (AHB4PERIPH_BASE_S + 0x8000UL)
3544 
3545 /*!< APB5 peripherals */
3546 #define LTDC_BASE_S                     (APB5PERIPH_BASE_S + 0x1000UL)
3547 #define LTDC_Layer1_BASE_S              (LTDC_BASE_S + 0x0100UL)
3548 #define LTDC_Layer2_BASE_S              (LTDC_BASE_S + 0x0200UL)
3549 #define DCMIPP_BASE_S                   (APB5PERIPH_BASE_S + 0x2000UL)
3550 #define GFXTIM_BASE_S                   (APB5PERIPH_BASE_S + 0x4000UL)
3551 #define VENC_BASE_S                     (APB5PERIPH_BASE_S + 0x5000UL)
3552 #define CSI_BASE_S                      (APB5PERIPH_BASE_S + 0x6000UL)
3553 
3554 /*!< AHB5 peripherals */
3555 #define HPDMA1_BASE_S                   (AHB5PERIPH_BASE_S + 0x0000UL)
3556 #define HPDMA1_Channel0_BASE_S          (HPDMA1_BASE_S + 0x0050UL)
3557 #define HPDMA1_Channel1_BASE_S          (HPDMA1_BASE_S + 0x00D0UL)
3558 #define HPDMA1_Channel2_BASE_S          (HPDMA1_BASE_S + 0x0150UL)
3559 #define HPDMA1_Channel3_BASE_S          (HPDMA1_BASE_S + 0x01D0UL)
3560 #define HPDMA1_Channel4_BASE_S          (HPDMA1_BASE_S + 0x0250UL)
3561 #define HPDMA1_Channel5_BASE_S          (HPDMA1_BASE_S + 0x02D0UL)
3562 #define HPDMA1_Channel6_BASE_S          (HPDMA1_BASE_S + 0x0350UL)
3563 #define HPDMA1_Channel7_BASE_S          (HPDMA1_BASE_S + 0x03D0UL)
3564 #define HPDMA1_Channel8_BASE_S          (HPDMA1_BASE_S + 0x0450UL)
3565 #define HPDMA1_Channel9_BASE_S          (HPDMA1_BASE_S + 0x04D0UL)
3566 #define HPDMA1_Channel10_BASE_S         (HPDMA1_BASE_S + 0x0550UL)
3567 #define HPDMA1_Channel11_BASE_S         (HPDMA1_BASE_S + 0x05D0UL)
3568 #define HPDMA1_Channel12_BASE_S         (HPDMA1_BASE_S + 0x0650UL)
3569 #define HPDMA1_Channel13_BASE_S         (HPDMA1_BASE_S + 0x06D0UL)
3570 #define HPDMA1_Channel14_BASE_S         (HPDMA1_BASE_S + 0x0750UL)
3571 #define HPDMA1_Channel15_BASE_S         (HPDMA1_BASE_S + 0x07D0UL)
3572 #define DMA2D_BASE_S                    (AHB5PERIPH_BASE_S + 0x1000UL)
3573 #define JPEG_BASE_S                     (AHB5PERIPH_BASE_S + 0x3000UL)
3574 #define FMC_R_BASE_S                    (AHB5PERIPH_BASE_S + 0x4000UL)
3575 #define FMC_Bank1_R_BASE_S              (FMC_R_BASE_S + 0x0000UL)
3576 #define FMC_Bank1E_R_BASE_S             (FMC_R_BASE_S + 0x0104UL)
3577 #define FMC_Bank3_R_BASE_S              (FMC_R_BASE_S + 0x0080UL)
3578 #define FMC_Bank5_6_R_BASE_S            (FMC_R_BASE_S + 0x0140UL)
3579 #define FMC_Common_R_BASE_S             (FMC_R_BASE_S + 0x0020UL)
3580 #define XSPI1_BASE_S                    (AHB5PERIPH_BASE_S + 0x5000UL)
3581 #define PSSI_BASE_S                     (AHB5PERIPH_BASE_S + 0x6400UL)
3582 #define SDMMC2_BASE_S                   (AHB5PERIPH_BASE_S + 0x6800UL)
3583 #define DLYB_SDMMC2_BASE_S              (AHB5PERIPH_BASE_S + 0x6C00UL)
3584 #define SDMMC1_BASE_S                   (AHB5PERIPH_BASE_S + 0x7000UL)
3585 #define DLYB_SDMMC1_BASE_S              (AHB5PERIPH_BASE_S + 0x8000UL)
3586 #define DCMI_BASE_S                     (AHB5PERIPH_BASE_S + 0x8400UL)
3587 #define XSPI2_BASE_S                    (AHB5PERIPH_BASE_S + 0xA000UL)
3588 #define XSPIM_BASE_S                    (AHB5PERIPH_BASE_S + 0xB400UL)
3589 #define MCE1_BASE_S                     (AHB5PERIPH_BASE_S + 0xB800UL)
3590 #define MCE1_REGION1_BASE_S             (MCE1_BASE_S + 0x040UL)
3591 #define MCE1_REGION2_BASE_S             (MCE1_BASE_S + 0x050UL)
3592 #define MCE1_REGION3_BASE_S             (MCE1_BASE_S + 0x060UL)
3593 #define MCE1_REGION4_BASE_S             (MCE1_BASE_S + 0x070UL)
3594 #define MCE1_CONTEXT1_BASE_S            (MCE1_BASE_S + 0x240UL)
3595 #define MCE1_CONTEXT2_BASE_S            (MCE1_BASE_S + 0x270UL)
3596 #define MCE2_BASE_S                     (AHB5PERIPH_BASE_S + 0xBC00UL)
3597 #define MCE2_REGION1_BASE_S             (MCE2_BASE_S + 0x040UL)
3598 #define MCE2_REGION2_BASE_S             (MCE2_BASE_S + 0x050UL)
3599 #define MCE2_REGION3_BASE_S             (MCE2_BASE_S + 0x060UL)
3600 #define MCE2_REGION4_BASE_S             (MCE2_BASE_S + 0x070UL)
3601 #define MCE2_CONTEXT1_BASE_S            (MCE2_BASE_S + 0x240UL)
3602 #define MCE2_CONTEXT2_BASE_S            (MCE2_BASE_S + 0x270UL)
3603 #define MCE3_BASE_S                     (AHB5PERIPH_BASE_S + 0xC000UL)
3604 #define MCE3_REGION1_BASE_S             (MCE3_BASE_S + 0x040UL)
3605 #define MCE3_REGION2_BASE_S             (MCE3_BASE_S + 0x050UL)
3606 #define MCE3_REGION3_BASE_S             (MCE3_BASE_S + 0x060UL)
3607 #define MCE3_REGION4_BASE_S             (MCE3_BASE_S + 0x070UL)
3608 #define MCE3_CONTEXT1_BASE_S            (MCE3_BASE_S + 0x240UL)
3609 #define MCE3_CONTEXT2_BASE_S            (MCE3_BASE_S + 0x270UL)
3610 #define MCE4_BASE_S                     (AHB5PERIPH_BASE_S + 0xE000UL)
3611 #define MCE4_REGION1_BASE_S             (MCE4_BASE_S + 0x040UL)
3612 #define MCE4_REGION2_BASE_S             (MCE4_BASE_S + 0x050UL)
3613 #define MCE4_REGION3_BASE_S             (MCE4_BASE_S + 0x060UL)
3614 #define MCE4_REGION4_BASE_S             (MCE4_BASE_S + 0x070UL)
3615 #define MCE4_CONTEXT1_BASE_S            (MCE4_BASE_S + 0x240UL)
3616 #define MCE4_CONTEXT2_BASE_S            (MCE4_BASE_S + 0x270UL)
3617 #define XSPI3_BASE_S                    (AHB5PERIPH_BASE_S + 0xD000UL)
3618 #define GFXMMU_BASE_S                   (AHB5PERIPH_BASE_S + 0x010000UL)
3619 #define GPU2D_BASE_S                    (AHB5PERIPH_BASE_S + 0x014000UL)
3620 #define GPUCACHE_BASE_S                 (AHB5PERIPH_BASE_S + 0x015000UL)
3621 #define ICACHE_BASE_S                   (AHB5PERIPH_BASE_S + 0x015000UL)
3622 #define ETH1_BASE_S                     (AHB5PERIPH_BASE_S + 0x016000UL)
3623 #define ETH1_MAC_BASE_S                 (ETH1_BASE_S)
3624 #define USB1_HS_PHYC_BASE_S             (AHB5PERIPH_BASE_S + 0x01FC00UL)
3625 #define USB2_HS_PHYC_BASE_S             (AHB5PERIPH_BASE_S + 0x0A0000UL)
3626 #define USB1_OTG_HS_BASE_S              (AHB5PERIPH_BASE_S + 0x020000UL)
3627 #define USB2_OTG_HS_BASE_S              (AHB5PERIPH_BASE_S + 0x060000UL)
3628 #define CACHEAXI_BASE_S                 (AHB5PERIPH_BASE_S + 0x0BFC00UL)
3629 #define NPU_BASE_S                      (AHB5PERIPH_BASE_S + 0x0C0000UL)
3630 
3631 
3632 /*!< Unique device ID register base address */
3633 #define UID_BASE_S                      (0x56009014UL)
3634 
3635 /*!< Revision ID base address */
3636 #define REVID_BASE_S                    (BOOTROM_BASE_S + 0x0047ECUL)
3637 
3638 #endif
3639 
3640 /** @} */ /* End of group STM32N6xx_Peripheral_peripheralAddr */
3641 
3642 /* =========================================================================================================================== */
3643 /* ================                                  Peripheral declaration                                   ================ */
3644 /* =========================================================================================================================== */
3645 /** @addtogroup STM32N6xx_Peripheral_declaration
3646   * @{
3647   */
3648 #define ADC12_COMMON_NS           ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS)
3649 #define ADC1_NS                   ((ADC_TypeDef *) ADC1_BASE_NS)
3650 #define ADC2_NS                   ((ADC_TypeDef *) ADC2_BASE_NS)
3651 #define ADF1_NS                   ((MDF_TypeDef *) ADF1_BASE_NS)
3652 #define ADF1_Filter0_NS           ((MDF_Filter_TypeDef *) ADF1_Filter0_BASE_NS)
3653 #define BSEC_NS                   ((BSEC_TypeDef *) BSEC_BASE_NS)
3654 #define CACHEAXI_NS               ((CACHEAXI_TypeDef *) CACHEAXI_BASE_NS)
3655 #define CRC_NS                    ((CRC_TypeDef *) CRC_BASE_NS)
3656 #define CRYP_NS                   ((CRYP_TypeDef *) CRYP_BASE_NS)
3657 #define CSI_NS                    ((CSI_TypeDef *) CSI_BASE_NS)
3658 #define DBGMCU_NS                 ((DBGMCU_TypeDef *) DBGMCU_BASE_NS)
3659 #define DCMI_NS                   ((DCMI_TypeDef *) DCMI_BASE_NS)
3660 #define DCMIPP_NS                 ((DCMIPP_TypeDef *) DCMIPP_BASE_NS)
3661 #define DLYB_SDMMC1_NS            ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS)
3662 #define DLYB_SDMMC2_NS            ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_NS)
3663 #define DMA2D_NS                  ((DMA2D_TypeDef *) DMA2D_BASE_NS)
3664 #define DTS_NS                    ((DTS_TypeDef *) DTS_BASE_NS)
3665 #define DTS_Sensor0_NS            ((DTS_SensorTypeDef *) DTS_Sensor0_BASE_NS)
3666 #define DTS_Sensor1_NS            ((DTS_SensorTypeDef *) DTS_Sensor1_BASE_NS)
3667 #define ETH1_NS                   ((ETH_TypeDef *) ETH1_BASE_NS)
3668 #define EXTI_NS                   ((EXTI_TypeDef *) EXTI_BASE_NS)
3669 #define FDCAN1_NS                 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS)
3670 #define FDCAN2_NS                 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE_NS)
3671 #define FDCAN3_NS                 ((FDCAN_GlobalTypeDef *) FDCAN3_BASE_NS)
3672 #define FDCAN_CCU_NS              ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE_NS)
3673 #define FDCAN_CONFIG_NS           ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_NS)
3674 #define FMC_Bank1E_R_NS           ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS)
3675 #define FMC_Bank1_R_NS            ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS)
3676 #define FMC_Bank3_R_NS            ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS)
3677 #define FMC_Bank5_6_R_NS          ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE_NS)
3678 #define FMC_Common_R_NS           ((FMC_Common_TypeDef *) FMC_Common_R_BASE_NS)
3679 #define GFXMMU_NS                 ((GFXMMU_TypeDef *) GFXMMU_BASE_NS)
3680 #define GFXTIM_NS                 ((GFXTIM_TypeDef *) GFXTIM_BASE_NS)
3681 #define GPDMA1_NS                 ((DMA_TypeDef *) GPDMA1_BASE_NS)
3682 #define GPDMA1_Channel0_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS)
3683 #define GPDMA1_Channel1_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS)
3684 #define GPDMA1_Channel2_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS)
3685 #define GPDMA1_Channel3_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS)
3686 #define GPDMA1_Channel4_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS)
3687 #define GPDMA1_Channel5_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS)
3688 #define GPDMA1_Channel6_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS)
3689 #define GPDMA1_Channel7_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS)
3690 #define GPDMA1_Channel8_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_NS)
3691 #define GPDMA1_Channel9_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_NS)
3692 #define GPDMA1_Channel10_NS       ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_NS)
3693 #define GPDMA1_Channel11_NS       ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_NS)
3694 #define GPDMA1_Channel12_NS       ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_NS)
3695 #define GPDMA1_Channel13_NS       ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_NS)
3696 #define GPDMA1_Channel14_NS       ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_NS)
3697 #define GPDMA1_Channel15_NS       ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_NS)
3698 #define GPIOA_NS                  ((GPIO_TypeDef *) GPIOA_BASE_NS)
3699 #define GPIOB_NS                  ((GPIO_TypeDef *) GPIOB_BASE_NS)
3700 #define GPIOC_NS                  ((GPIO_TypeDef *) GPIOC_BASE_NS)
3701 #define GPIOD_NS                  ((GPIO_TypeDef *) GPIOD_BASE_NS)
3702 #define GPIOE_NS                  ((GPIO_TypeDef *) GPIOE_BASE_NS)
3703 #define GPIOF_NS                  ((GPIO_TypeDef *) GPIOF_BASE_NS)
3704 #define GPIOG_NS                  ((GPIO_TypeDef *) GPIOG_BASE_NS)
3705 #define GPIOH_NS                  ((GPIO_TypeDef *) GPIOH_BASE_NS)
3706 #define GPION_NS                  ((GPIO_TypeDef *) GPION_BASE_NS)
3707 #define GPIOO_NS                  ((GPIO_TypeDef *) GPIOO_BASE_NS)
3708 #define GPIOP_NS                  ((GPIO_TypeDef *) GPIOP_BASE_NS)
3709 #define GPIOQ_NS                  ((GPIO_TypeDef *) GPIOQ_BASE_NS)
3710 #define HASH_NS                   ((HASH_TypeDef *) HASH_BASE_NS)
3711 #define HASH_DIGEST_NS            ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS)
3712 #define HPDMA1_NS                 ((DMA_TypeDef *) HPDMA1_BASE_NS)
3713 #define HPDMA1_Channel0_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel0_BASE_NS)
3714 #define HPDMA1_Channel1_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel1_BASE_NS)
3715 #define HPDMA1_Channel2_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel2_BASE_NS)
3716 #define HPDMA1_Channel3_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel3_BASE_NS)
3717 #define HPDMA1_Channel4_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel4_BASE_NS)
3718 #define HPDMA1_Channel5_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel5_BASE_NS)
3719 #define HPDMA1_Channel6_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel6_BASE_NS)
3720 #define HPDMA1_Channel7_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel7_BASE_NS)
3721 #define HPDMA1_Channel8_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel8_BASE_NS)
3722 #define HPDMA1_Channel9_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel9_BASE_NS)
3723 #define HPDMA1_Channel10_NS       ((DMA_Channel_TypeDef *) HPDMA1_Channel10_BASE_NS)
3724 #define HPDMA1_Channel11_NS       ((DMA_Channel_TypeDef *) HPDMA1_Channel11_BASE_NS)
3725 #define HPDMA1_Channel12_NS       ((DMA_Channel_TypeDef *) HPDMA1_Channel12_BASE_NS)
3726 #define HPDMA1_Channel13_NS       ((DMA_Channel_TypeDef *) HPDMA1_Channel13_BASE_NS)
3727 #define HPDMA1_Channel14_NS       ((DMA_Channel_TypeDef *) HPDMA1_Channel14_BASE_NS)
3728 #define HPDMA1_Channel15_NS       ((DMA_Channel_TypeDef *) HPDMA1_Channel15_BASE_NS)
3729 #define I2C1_NS                   ((I2C_TypeDef *) I2C1_BASE_NS)
3730 #define I2C2_NS                   ((I2C_TypeDef *) I2C2_BASE_NS)
3731 #define I2C3_NS                   ((I2C_TypeDef *) I2C3_BASE_NS)
3732 #define I2C4_NS                   ((I2C_TypeDef *) I2C4_BASE_NS)
3733 #define I3C1_NS                   ((I3C_TypeDef *) I3C1_BASE_NS)
3734 #define I3C2_NS                   ((I3C_TypeDef *) I3C2_BASE_NS)
3735 #define ICACHE_NS                 ((ICACHE_TypeDef *) ICACHE_BASE_NS)
3736 #define IWDG_NS                   ((IWDG_TypeDef *) IWDG_BASE_NS)
3737 #define JPEG_NS                   ((JPEG_TypeDef *) JPEG_BASE_NS)
3738 #define LPTIM1_NS                 ((LPTIM_TypeDef *) LPTIM1_BASE_NS)
3739 #define LPTIM2_NS                 ((LPTIM_TypeDef *) LPTIM2_BASE_NS)
3740 #define LPTIM3_NS                 ((LPTIM_TypeDef *) LPTIM3_BASE_NS)
3741 #define LPTIM4_NS                 ((LPTIM_TypeDef *) LPTIM4_BASE_NS)
3742 #define LPTIM5_NS                 ((LPTIM_TypeDef *) LPTIM5_BASE_NS)
3743 #define LPUART1_NS                ((USART_TypeDef *) LPUART1_BASE_NS)
3744 #define LTDC_NS                   ((LTDC_TypeDef *)LTDC_BASE_NS)
3745 #define LTDC_Layer1_NS            ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE_NS)
3746 #define LTDC_Layer2_NS            ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE_NS)
3747 #define MCE1_NS                   ((MCE_TypeDef *) MCE1_BASE_NS)
3748 #define MCE1_REGION1_NS           ((MCE_Region_TypeDef *) MCE1_REGION1_BASE_NS)
3749 #define MCE1_REGION2_NS           ((MCE_Region_TypeDef *) MCE1_REGION2_BASE_NS)
3750 #define MCE1_REGION3_NS           ((MCE_Region_TypeDef *) MCE1_REGION3_BASE_NS)
3751 #define MCE1_REGION4_NS           ((MCE_Region_TypeDef *) MCE1_REGION4_BASE_NS)
3752 #define MCE1_CONTEXT1_NS          ((MCE_Context_TypeDef *) MCE1_CONTEXT1_BASE_NS)
3753 #define MCE1_CONTEXT2_NS          ((MCE_Context_TypeDef *) MCE1_CONTEXT2_BASE_NS)
3754 #define MCE2_NS                   ((MCE_TypeDef *) MCE2_BASE_NS)
3755 #define MCE2_REGION1_NS           ((MCE_Region_TypeDef *) MCE2_REGION1_BASE_NS)
3756 #define MCE2_REGION2_NS           ((MCE_Region_TypeDef *) MCE2_REGION2_BASE_NS)
3757 #define MCE2_REGION3_NS           ((MCE_Region_TypeDef *) MCE2_REGION3_BASE_NS)
3758 #define MCE2_REGION4_NS           ((MCE_Region_TypeDef *) MCE2_REGION4_BASE_NS)
3759 #define MCE2_CONTEXT1_NS          ((MCE_Context_TypeDef *) MCE2_CONTEXT1_BASE_NS)
3760 #define MCE2_CONTEXT2_NS          ((MCE_Context_TypeDef *) MCE2_CONTEXT2_BASE_NS)
3761 #define MCE3_NS                   ((MCE_TypeDef *) MCE3_BASE_NS)
3762 #define MCE3_REGION1_NS           ((MCE_Region_TypeDef *) MCE3_REGION1_BASE_NS)
3763 #define MCE3_REGION2_NS           ((MCE_Region_TypeDef *) MCE3_REGION2_BASE_NS)
3764 #define MCE3_REGION3_NS           ((MCE_Region_TypeDef *) MCE3_REGION3_BASE_NS)
3765 #define MCE3_REGION4_NS           ((MCE_Region_TypeDef *) MCE3_REGION4_BASE_NS)
3766 #define MCE3_CONTEXT1_NS          ((MCE_Context_TypeDef *) MCE3_CONTEXT1_BASE_NS)
3767 #define MCE3_CONTEXT2_NS          ((MCE_Context_TypeDef *) MCE3_CONTEXT2_BASE_NS)
3768 #define MCE4_NS                   ((MCE_TypeDef *) MCE4_BASE_NS)
3769 #define MCE4_REGION1_NS           ((MCE_Region_TypeDef *) MCE4_REGION1_BASE_NS)
3770 #define MCE4_REGION2_NS           ((MCE_Region_TypeDef *) MCE4_REGION2_BASE_NS)
3771 #define MCE4_REGION3_NS           ((MCE_Region_TypeDef *) MCE4_REGION3_BASE_NS)
3772 #define MCE4_REGION4_NS           ((MCE_Region_TypeDef *) MCE4_REGION4_BASE_NS)
3773 #define MCE4_CONTEXT1_NS          ((MCE_Context_TypeDef *) MCE4_CONTEXT1_BASE_NS)
3774 #define MCE4_CONTEXT2_NS          ((MCE_Context_TypeDef *) MCE4_CONTEXT2_BASE_NS)
3775 #define MDF1_NS                   ((MDF_TypeDef *) MDF1_BASE_NS)
3776 #define MDF1_Filter0_NS           ((MDF_Filter_TypeDef *) MDF1_Filter0_BASE_NS)
3777 #define MDF1_Filter1_NS           ((MDF_Filter_TypeDef *) MDF1_Filter1_BASE_NS)
3778 #define MDF1_Filter2_NS           ((MDF_Filter_TypeDef *) MDF1_Filter2_BASE_NS)
3779 #define MDF1_Filter3_NS           ((MDF_Filter_TypeDef *) MDF1_Filter3_BASE_NS)
3780 #define MDF1_Filter4_NS           ((MDF_Filter_TypeDef *) MDF1_Filter4_BASE_NS)
3781 #define MDF1_Filter5_NS           ((MDF_Filter_TypeDef *) MDF1_Filter5_BASE_NS)
3782 #define MDIOS_NS                  ((MDIOS_TypeDef *) MDIOS_BASE_NS)
3783 #define PKA_NS                    ((PKA_TypeDef *) PKA_BASE_NS)
3784 #define PSSI_NS                   ((PSSI_TypeDef *) PSSI_BASE_NS)
3785 #define PWR_NS                    ((PWR_TypeDef *) PWR_BASE_NS)
3786 #define RAMCFG_NS                 ((RAMCFG_TypeDef *) RAMCFG_BASE_NS)
3787 #define RAMCFG_SRAM1_AXI_NS       ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AXI_BASE_NS)
3788 #define RAMCFG_SRAM2_AXI_NS       ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AXI_BASE_NS)
3789 #define RAMCFG_SRAM3_AXI_NS       ((RAMCFG_TypeDef *) RAMCFG_SRAM3_AXI_BASE_NS)
3790 #define RAMCFG_SRAM4_AXI_NS       ((RAMCFG_TypeDef *) RAMCFG_SRAM4_AXI_BASE_NS)
3791 #define RAMCFG_SRAM5_AXI_NS       ((RAMCFG_TypeDef *) RAMCFG_SRAM5_AXI_BASE_NS)
3792 #define RAMCFG_SRAM6_AXI_NS       ((RAMCFG_TypeDef *) RAMCFG_SRAM6_AXI_BASE_NS)
3793 #define RAMCFG_SRAM1_AHB_NS       ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AHB_BASE_NS)
3794 #define RAMCFG_SRAM2_AHB_NS       ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AHB_BASE_NS)
3795 #define RAMCFG_VENC_RAM_NS        ((RAMCFG_TypeDef *) RAMCFG_VENC_RAM_BASE_NS)
3796 #define RAMCFG_BKPSRAM_NS         ((RAMCFG_TypeDef *) RAMCFG_BKPSRAM_BASE_NS)
3797 #define RAMCFG_FLEXRAM_NS         ((RAMCFG_TypeDef *) RAMCFG_FLEXRAM_BASE_NS)
3798 #define RCC_NS                    ((RCC_TypeDef *) RCC_BASE_NS)
3799 #define RIFSC_NS                  ((RIFSC_TypeDef *) RIFSC_BASE_NS)
3800 #define RISAF1_NS                 ((RISAF_TypeDef *) RISAF1_BASE_NS)
3801 #define RISAF2_NS                 ((RISAF_TypeDef *) RISAF2_BASE_NS)
3802 #define RISAF3_NS                 ((RISAF_TypeDef *) RISAF3_BASE_NS)
3803 #define RISAF4_NS                 ((RISAF_TypeDef *) RISAF4_BASE_NS)
3804 #define RISAF5_NS                 ((RISAF_TypeDef *) RISAF5_BASE_NS)
3805 #define RISAF6_NS                 ((RISAF_TypeDef *) RISAF6_BASE_NS)
3806 #define RISAF7_NS                 ((RISAF_TypeDef *) RISAF7_BASE_NS)
3807 #define RISAF8_NS                 ((RISAF_TypeDef *) RISAF8_BASE_NS)
3808 #define RISAF9_NS                 ((RISAF_TypeDef *) RISAF9_BASE_NS)
3809 #define RISAF11_NS                ((RISAF_TypeDef *) RISAF11_BASE_NS)
3810 #define RISAF12_NS                ((RISAF_TypeDef *) RISAF12_BASE_NS)
3811 #define RISAF13_NS                ((RISAF_TypeDef *) RISAF13_BASE_NS)
3812 #define RISAF14_NS                ((RISAF_TypeDef *) RISAF14_BASE_NS)
3813 #define RISAF15_NS                ((RISAF_TypeDef *) RISAF15_BASE_NS)
3814 #define RISAF21_NS                ((RISAF_TypeDef *) RISAF21_BASE_NS)
3815 #define RISAF22_NS                ((RISAF_TypeDef *) RISAF22_BASE_NS)
3816 #define RISAF23_NS                ((RISAF_TypeDef *) RISAF23_BASE_NS)
3817 #define RNG_NS                    ((RNG_TypeDef *) RNG_BASE_NS)
3818 #define RTC_NS                    ((RTC_TypeDef *) RTC_BASE_NS)
3819 #define SAES_NS                   ((SAES_TypeDef *) SAES_BASE_NS)
3820 #define SAI1_NS                   ((SAI_TypeDef *) SAI1_BASE_NS)
3821 #define SAI1_Block_A_NS           ((SAI_Block_TypeDef *) SAI1_Block_A_BASE_NS)
3822 #define SAI1_Block_B_NS           ((SAI_Block_TypeDef *) SAI1_Block_B_BASE_NS)
3823 #define SAI2_NS                   ((SAI_TypeDef *) SAI2_BASE_NS)
3824 #define SAI2_Block_A_NS           ((SAI_Block_TypeDef *) SAI2_Block_A_BASE_NS)
3825 #define SAI2_Block_B_NS           ((SAI_Block_TypeDef *) SAI2_Block_B_BASE_NS)
3826 #define SDMMC1_NS                 ((SDMMC_TypeDef *) SDMMC1_BASE_NS)
3827 #define SDMMC2_NS                 ((SDMMC_TypeDef *) SDMMC2_BASE_NS)
3828 #define SPDIFRX_NS                ((SPDIFRX_TypeDef *) SPDIFRX_BASE_NS)
3829 #define SPI1_NS                   ((SPI_TypeDef *) SPI1_BASE_NS)
3830 #define SPI2_NS                   ((SPI_TypeDef *) SPI2_BASE_NS)
3831 #define SPI3_NS                   ((SPI_TypeDef *) SPI3_BASE_NS)
3832 #define SPI4_NS                   ((SPI_TypeDef *) SPI4_BASE_NS)
3833 #define SPI5_NS                   ((SPI_TypeDef *) SPI5_BASE_NS)
3834 #define SPI6_NS                   ((SPI_TypeDef *) SPI6_BASE_NS)
3835 #define SYSCFG_NS                 ((SYSCFG_TypeDef *) SYSCFG_BASE_NS)
3836 #define TAMP_NS                   ((TAMP_TypeDef *) TAMP_BASE_NS)
3837 #define TIM1_NS                   ((TIM_TypeDef *) TIM1_BASE_NS)
3838 #define TIM2_NS                   ((TIM_TypeDef *) TIM2_BASE_NS)
3839 #define TIM3_NS                   ((TIM_TypeDef *) TIM3_BASE_NS)
3840 #define TIM4_NS                   ((TIM_TypeDef *) TIM4_BASE_NS)
3841 #define TIM5_NS                   ((TIM_TypeDef *) TIM5_BASE_NS)
3842 #define TIM6_NS                   ((TIM_TypeDef *) TIM6_BASE_NS)
3843 #define TIM7_NS                   ((TIM_TypeDef *) TIM7_BASE_NS)
3844 #define TIM8_NS                   ((TIM_TypeDef *) TIM8_BASE_NS)
3845 #define TIM9_NS                   ((TIM_TypeDef *) TIM9_BASE_NS)
3846 #define TIM10_NS                  ((TIM_TypeDef *) TIM10_BASE_NS)
3847 #define TIM11_NS                  ((TIM_TypeDef *) TIM11_BASE_NS)
3848 #define TIM12_NS                  ((TIM_TypeDef *) TIM12_BASE_NS)
3849 #define TIM13_NS                  ((TIM_TypeDef *) TIM13_BASE_NS)
3850 #define TIM14_NS                  ((TIM_TypeDef *) TIM14_BASE_NS)
3851 #define TIM15_NS                  ((TIM_TypeDef *) TIM15_BASE_NS)
3852 #define TIM16_NS                  ((TIM_TypeDef *) TIM16_BASE_NS)
3853 #define TIM17_NS                  ((TIM_TypeDef *) TIM17_BASE_NS)
3854 #define TIM18_NS                  ((TIM_TypeDef *) TIM18_BASE_NS)
3855 #define UART4_NS                  ((USART_TypeDef *) UART4_BASE_NS)
3856 #define UART5_NS                  ((USART_TypeDef *) UART5_BASE_NS)
3857 #define UART7_NS                  ((USART_TypeDef *) UART7_BASE_NS)
3858 #define UART8_NS                  ((USART_TypeDef *) UART8_BASE_NS)
3859 #define UART9_NS                  ((USART_TypeDef *) UART9_BASE_NS)
3860 #define UCPD1_NS                  ((UCPD_TypeDef *) UCPD1_BASE_NS)
3861 #define USART1_NS                 ((USART_TypeDef *) USART1_BASE_NS)
3862 #define USART2_NS                 ((USART_TypeDef *) USART2_BASE_NS)
3863 #define USART3_NS                 ((USART_TypeDef *) USART3_BASE_NS)
3864 #define USART6_NS                 ((USART_TypeDef *) USART6_BASE_NS)
3865 #define USART10_NS                ((USART_TypeDef *) USART10_BASE_NS)
3866 #define USB1_OTG_HS_NS            ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_BASE_NS)
3867 #define USB2_OTG_HS_NS            ((USB_OTG_GlobalTypeDef *) USB2_OTG_HS_BASE_NS)
3868 #define USB1_HS_PHYC_NS           ((USB_HS_PHYC_GlobalTypeDef *) USB1_HS_PHYC_BASE_NS)
3869 #define USB2_HS_PHYC_NS           ((USB_HS_PHYC_GlobalTypeDef *) USB2_HS_PHYC_BASE_NS)
3870 #define VENC_NS                   ((VENC_TypeDef *) VENC_BASE_NS)
3871 #define VREFBUF_NS                ((VREFBUF_TypeDef *) VREFBUF_BASE_NS)
3872 #define WWDG_NS                   ((WWDG_TypeDef *) WWDG_BASE_NS)
3873 #define XSPI1_NS                  ((XSPI_TypeDef *) XSPI1_BASE_NS)
3874 #define XSPI2_NS                  ((XSPI_TypeDef *) XSPI2_BASE_NS)
3875 #define XSPI3_NS                  ((XSPI_TypeDef *) XSPI3_BASE_NS)
3876 #define XSPIM_NS                  ((XSPIM_TypeDef *) XSPIM_BASE_NS)
3877 
3878 #if defined (CPU_IN_SECURE_STATE)
3879 #define ADC12_COMMON_S            ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S)
3880 #define ADC1_S                    ((ADC_TypeDef *) ADC1_BASE_S)
3881 #define ADC2_S                    ((ADC_TypeDef *) ADC2_BASE_S)
3882 #define ADF1_S                    ((MDF_TypeDef *) ADF1_BASE_S)
3883 #define ADF1_Filter0_S            ((MDF_Filter_TypeDef *) ADF1_Filter0_BASE_S)
3884 #define BSEC_S                    ((BSEC_TypeDef *) BSEC_BASE_S)
3885 #define CACHEAXI_S                ((CACHEAXI_TypeDef *) CACHEAXI_BASE_S)
3886 #define CRC_S                     ((CRC_TypeDef *) CRC_BASE_S)
3887 #define CRYP_S                    ((CRYP_TypeDef *) CRYP_BASE_S)
3888 #define CSI_S                     ((CSI_TypeDef *) CSI_BASE_S)
3889 #define DBGMCU_S                  ((DBGMCU_TypeDef *) DBGMCU_BASE_S)
3890 #define DCMI_S                    ((DCMI_TypeDef *) DCMI_BASE_S)
3891 #define DCMIPP_S                  ((DCMIPP_TypeDef *) DCMIPP_BASE_S)
3892 #define DLYB_SDMMC1_S             ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S)
3893 #define DLYB_SDMMC2_S             ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_S)
3894 #define DMA2D_S                   ((DMA2D_TypeDef *) DMA2D_BASE_S)
3895 #define DTS_S                     ((DTS_TypeDef *) DTS_BASE_S)
3896 #define DTS_Sensor0_S             ((DTS_SensorTypeDef *) DTS_Sensor0_BASE_S)
3897 #define DTS_Sensor1_S             ((DTS_SensorTypeDef *) DTS_Sensor1_BASE_S)
3898 #define ETH1_S                    ((ETH_TypeDef *) ETH1_BASE_S)
3899 #define EXTI_S                    ((EXTI_TypeDef *) EXTI_BASE_S)
3900 #define FDCAN1_S                  ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S)
3901 #define FDCAN2_S                  ((FDCAN_GlobalTypeDef *) FDCAN2_BASE_S)
3902 #define FDCAN3_S                  ((FDCAN_GlobalTypeDef *) FDCAN3_BASE_S)
3903 #define FDCAN_CCU_S               ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE_S)
3904 #define FDCAN_CONFIG_S            ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_S)
3905 #define FMC_Bank1E_R_S            ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S)
3906 #define FMC_Bank1_R_S             ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S)
3907 #define FMC_Bank3_R_S             ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S)
3908 #define FMC_Bank5_6_R_S           ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE_S)
3909 #define FMC_Common_R_S            ((FMC_Common_TypeDef *) FMC_Common_R_BASE_S)
3910 #define GFXMMU_S                  ((GFXMMU_TypeDef *) GFXMMU_BASE_S)
3911 #define GFXTIM_S                  ((GFXTIM_TypeDef *) GFXTIM_BASE_S)
3912 #define GPDMA1_S                  ((DMA_TypeDef *) GPDMA1_BASE_S)
3913 #define GPDMA1_Channel0_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S)
3914 #define GPDMA1_Channel1_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S)
3915 #define GPDMA1_Channel2_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S)
3916 #define GPDMA1_Channel3_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S)
3917 #define GPDMA1_Channel4_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S)
3918 #define GPDMA1_Channel5_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S)
3919 #define GPDMA1_Channel6_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S)
3920 #define GPDMA1_Channel7_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S)
3921 #define GPDMA1_Channel8_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_S)
3922 #define GPDMA1_Channel9_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_S)
3923 #define GPDMA1_Channel10_S        ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_S)
3924 #define GPDMA1_Channel11_S        ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_S)
3925 #define GPDMA1_Channel12_S        ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_S)
3926 #define GPDMA1_Channel13_S        ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_S)
3927 #define GPDMA1_Channel14_S        ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_S)
3928 #define GPDMA1_Channel15_S        ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_S)
3929 #define GPIOA_S                   ((GPIO_TypeDef *) GPIOA_BASE_S)
3930 #define GPIOB_S                   ((GPIO_TypeDef *) GPIOB_BASE_S)
3931 #define GPIOC_S                   ((GPIO_TypeDef *) GPIOC_BASE_S)
3932 #define GPIOD_S                   ((GPIO_TypeDef *) GPIOD_BASE_S)
3933 #define GPIOE_S                   ((GPIO_TypeDef *) GPIOE_BASE_S)
3934 #define GPIOF_S                   ((GPIO_TypeDef *) GPIOF_BASE_S)
3935 #define GPIOG_S                   ((GPIO_TypeDef *) GPIOG_BASE_S)
3936 #define GPIOH_S                   ((GPIO_TypeDef *) GPIOH_BASE_S)
3937 #define GPION_S                   ((GPIO_TypeDef *) GPION_BASE_S)
3938 #define GPIOO_S                   ((GPIO_TypeDef *) GPIOO_BASE_S)
3939 #define GPIOP_S                   ((GPIO_TypeDef *) GPIOP_BASE_S)
3940 #define GPIOQ_S                   ((GPIO_TypeDef *) GPIOQ_BASE_S)
3941 #define HASH_S                    ((HASH_TypeDef *) HASH_BASE_S)
3942 #define HASH_DIGEST_S             ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S)
3943 #define HPDMA1_S                  ((DMA_TypeDef *) HPDMA1_BASE_S)
3944 #define HPDMA1_Channel0_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel0_BASE_S)
3945 #define HPDMA1_Channel1_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel1_BASE_S)
3946 #define HPDMA1_Channel2_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel2_BASE_S)
3947 #define HPDMA1_Channel3_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel3_BASE_S)
3948 #define HPDMA1_Channel4_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel4_BASE_S)
3949 #define HPDMA1_Channel5_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel5_BASE_S)
3950 #define HPDMA1_Channel6_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel6_BASE_S)
3951 #define HPDMA1_Channel7_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel7_BASE_S)
3952 #define HPDMA1_Channel8_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel8_BASE_S)
3953 #define HPDMA1_Channel9_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel9_BASE_S)
3954 #define HPDMA1_Channel10_S        ((DMA_Channel_TypeDef *) HPDMA1_Channel10_BASE_S)
3955 #define HPDMA1_Channel11_S        ((DMA_Channel_TypeDef *) HPDMA1_Channel11_BASE_S)
3956 #define HPDMA1_Channel12_S        ((DMA_Channel_TypeDef *) HPDMA1_Channel12_BASE_S)
3957 #define HPDMA1_Channel13_S        ((DMA_Channel_TypeDef *) HPDMA1_Channel13_BASE_S)
3958 #define HPDMA1_Channel14_S        ((DMA_Channel_TypeDef *) HPDMA1_Channel14_BASE_S)
3959 #define HPDMA1_Channel15_S        ((DMA_Channel_TypeDef *) HPDMA1_Channel15_BASE_S)
3960 #define I2C1_S                    ((I2C_TypeDef *) I2C1_BASE_S)
3961 #define I2C2_S                    ((I2C_TypeDef *) I2C2_BASE_S)
3962 #define I2C3_S                    ((I2C_TypeDef *) I2C3_BASE_S)
3963 #define I2C4_S                    ((I2C_TypeDef *) I2C4_BASE_S)
3964 #define I3C1_S                    ((I3C_TypeDef *) I3C1_BASE_S)
3965 #define I3C2_S                    ((I3C_TypeDef *) I3C2_BASE_S)
3966 #define IAC_S                     ((IAC_TypeDef *) IAC_BASE_S)
3967 #define ICACHE_S                  ((ICACHE_TypeDef *) ICACHE_BASE_S)
3968 #define IWDG_S                    ((IWDG_TypeDef *) IWDG_BASE_S)
3969 #define JPEG_S                    ((JPEG_TypeDef *) JPEG_BASE_S)
3970 #define LPTIM1_S                  ((LPTIM_TypeDef *) LPTIM1_BASE_S)
3971 #define LPTIM2_S                  ((LPTIM_TypeDef *) LPTIM2_BASE_S)
3972 #define LPTIM3_S                  ((LPTIM_TypeDef *) LPTIM3_BASE_S)
3973 #define LPTIM4_S                  ((LPTIM_TypeDef *) LPTIM4_BASE_S)
3974 #define LPTIM5_S                  ((LPTIM_TypeDef *) LPTIM5_BASE_S)
3975 #define LPUART1_S                 ((USART_TypeDef *) LPUART1_BASE_S)
3976 #define LTDC_S                    ((LTDC_TypeDef *)LTDC_BASE_S)
3977 #define LTDC_Layer1_S             ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE_S)
3978 #define LTDC_Layer2_S             ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE_S)
3979 #define MCE1_S                    ((MCE_TypeDef *) MCE1_BASE_S)
3980 #define MCE1_REGION1_S            ((MCE_Region_TypeDef *) MCE1_REGION1_BASE_S)
3981 #define MCE1_REGION2_S            ((MCE_Region_TypeDef *) MCE1_REGION2_BASE_S)
3982 #define MCE1_REGION3_S            ((MCE_Region_TypeDef *) MCE1_REGION3_BASE_S)
3983 #define MCE1_REGION4_S            ((MCE_Region_TypeDef *) MCE1_REGION4_BASE_S)
3984 #define MCE1_CONTEXT1_S           ((MCE_Context_TypeDef *) MCE1_CONTEXT1_BASE_S)
3985 #define MCE1_CONTEXT2_S           ((MCE_Context_TypeDef *) MCE1_CONTEXT2_BASE_S)
3986 #define MCE2_S                    ((MCE_TypeDef *) MCE2_BASE_S)
3987 #define MCE2_REGION1_S            ((MCE_Region_TypeDef *) MCE2_REGION1_BASE_S)
3988 #define MCE2_REGION2_S            ((MCE_Region_TypeDef *) MCE2_REGION2_BASE_S)
3989 #define MCE2_REGION3_S            ((MCE_Region_TypeDef *) MCE2_REGION3_BASE_S)
3990 #define MCE2_REGION4_S            ((MCE_Region_TypeDef *) MCE2_REGION4_BASE_S)
3991 #define MCE2_CONTEXT1_S           ((MCE_Context_TypeDef *) MCE2_CONTEXT1_BASE_S)
3992 #define MCE2_CONTEXT2_S           ((MCE_Context_TypeDef *) MCE2_CONTEXT2_BASE_S)
3993 #define MCE3_S                    ((MCE_TypeDef *) MCE3_BASE_S)
3994 #define MCE3_REGION1_S            ((MCE_Region_TypeDef *) MCE3_REGION1_BASE_S)
3995 #define MCE3_REGION2_S            ((MCE_Region_TypeDef *) MCE3_REGION2_BASE_S)
3996 #define MCE3_REGION3_S            ((MCE_Region_TypeDef *) MCE3_REGION3_BASE_S)
3997 #define MCE3_REGION4_S            ((MCE_Region_TypeDef *) MCE3_REGION4_BASE_S)
3998 #define MCE3_CONTEXT1_S           ((MCE_Context_TypeDef *) MCE3_CONTEXT1_BASE_S)
3999 #define MCE3_CONTEXT2_S           ((MCE_Context_TypeDef *) MCE3_CONTEXT2_BASE_S)
4000 #define MCE4_S                    ((MCE_TypeDef *) MCE4_BASE_S)
4001 #define MCE4_REGION1_S            ((MCE_Region_TypeDef *) MCE4_REGION1_BASE_S)
4002 #define MCE4_REGION2_S            ((MCE_Region_TypeDef *) MCE4_REGION2_BASE_S)
4003 #define MCE4_REGION3_S            ((MCE_Region_TypeDef *) MCE4_REGION3_BASE_S)
4004 #define MCE4_REGION4_S            ((MCE_Region_TypeDef *) MCE4_REGION4_BASE_S)
4005 #define MCE4_CONTEXT1_S           ((MCE_Context_TypeDef *) MCE4_CONTEXT1_BASE_S)
4006 #define MCE4_CONTEXT2_S           ((MCE_Context_TypeDef *) MCE4_CONTEXT2_BASE_S)
4007 #define MDF1_S                    ((MDF_TypeDef *) MDF1_BASE_S)
4008 #define MDF1_Filter0_S            ((MDF_Filter_TypeDef *) MDF1_Filter0_BASE_S)
4009 #define MDF1_Filter1_S            ((MDF_Filter_TypeDef *) MDF1_Filter1_BASE_S)
4010 #define MDF1_Filter2_S            ((MDF_Filter_TypeDef *) MDF1_Filter2_BASE_S)
4011 #define MDF1_Filter3_S            ((MDF_Filter_TypeDef *) MDF1_Filter3_BASE_S)
4012 #define MDF1_Filter4_S            ((MDF_Filter_TypeDef *) MDF1_Filter4_BASE_S)
4013 #define MDF1_Filter5_S            ((MDF_Filter_TypeDef *) MDF1_Filter5_BASE_S)
4014 #define MDIOS_S                   ((MDIOS_TypeDef *) MDIOS_BASE_S)
4015 #define PKA_S                     ((PKA_TypeDef *) PKA_BASE_S)
4016 #define PSSI_S                    ((PSSI_TypeDef *) PSSI_BASE_S)
4017 #define PWR_S                     ((PWR_TypeDef *) PWR_BASE_S)
4018 #define RAMCFG_S                  ((RAMCFG_TypeDef *) RAMCFG_BASE_S)
4019 #define RAMCFG_SRAM1_AXI_S        ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AXI_BASE_S)
4020 #define RAMCFG_SRAM2_AXI_S        ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AXI_BASE_S)
4021 #define RAMCFG_SRAM3_AXI_S        ((RAMCFG_TypeDef *) RAMCFG_SRAM3_AXI_BASE_S)
4022 #define RAMCFG_SRAM4_AXI_S        ((RAMCFG_TypeDef *) RAMCFG_SRAM4_AXI_BASE_S)
4023 #define RAMCFG_SRAM5_AXI_S        ((RAMCFG_TypeDef *) RAMCFG_SRAM5_AXI_BASE_S)
4024 #define RAMCFG_SRAM6_AXI_S        ((RAMCFG_TypeDef *) RAMCFG_SRAM6_AXI_BASE_S)
4025 #define RAMCFG_SRAM1_AHB_S        ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AHB_BASE_S)
4026 #define RAMCFG_SRAM2_AHB_S        ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AHB_BASE_S)
4027 #define RAMCFG_VENC_RAM_S         ((RAMCFG_TypeDef *) RAMCFG_VENC_RAM_BASE_NS)
4028 #define RAMCFG_BKPSRAM_S          ((RAMCFG_TypeDef *) RAMCFG_BKPSRAM_BASE_S)
4029 #define RAMCFG_FLEXRAM_S          ((RAMCFG_TypeDef *) RAMCFG_FLEXRAM_BASE_S)
4030 #define RCC_S                     ((RCC_TypeDef *) RCC_BASE_S)
4031 #define RIFSC_S                   ((RIFSC_TypeDef *) RIFSC_BASE_S)
4032 #define RISAF1_S                  ((RISAF_TypeDef *) RISAF1_BASE_S)
4033 #define RISAF2_S                  ((RISAF_TypeDef *) RISAF2_BASE_S)
4034 #define RISAF3_S                  ((RISAF_TypeDef *) RISAF3_BASE_S)
4035 #define RISAF4_S                  ((RISAF_TypeDef *) RISAF4_BASE_S)
4036 #define RISAF5_S                  ((RISAF_TypeDef *) RISAF5_BASE_S)
4037 #define RISAF6_S                  ((RISAF_TypeDef *) RISAF6_BASE_S)
4038 #define RISAF7_S                  ((RISAF_TypeDef *) RISAF7_BASE_S)
4039 #define RISAF8_S                  ((RISAF_TypeDef *) RISAF8_BASE_S)
4040 #define RISAF9_S                  ((RISAF_TypeDef *) RISAF9_BASE_S)
4041 #define RISAF11_S                 ((RISAF_TypeDef *) RISAF11_BASE_S)
4042 #define RISAF12_S                 ((RISAF_TypeDef *) RISAF12_BASE_S)
4043 #define RISAF13_S                 ((RISAF_TypeDef *) RISAF13_BASE_S)
4044 #define RISAF14_S                 ((RISAF_TypeDef *) RISAF14_BASE_S)
4045 #define RISAF15_S                 ((RISAF_TypeDef *) RISAF15_BASE_S)
4046 #define RISAF21_S                 ((RISAF_TypeDef *) RISAF21_BASE_S)
4047 #define RISAF22_S                 ((RISAF_TypeDef *) RISAF22_BASE_S)
4048 #define RISAF23_S                 ((RISAF_TypeDef *) RISAF23_BASE_S)
4049 #define RNG_S                     ((RNG_TypeDef *) RNG_BASE_S)
4050 #define RTC_S                     ((RTC_TypeDef *) RTC_BASE_S)
4051 #define SAES_S                    ((SAES_TypeDef *) SAES_BASE_S)
4052 #define SAI1_S                    ((SAI_TypeDef *) SAI1_BASE_S)
4053 #define SAI1_Block_A_S            ((SAI_Block_TypeDef *) SAI1_Block_A_BASE_S)
4054 #define SAI1_Block_B_S            ((SAI_Block_TypeDef *) SAI1_Block_B_BASE_S)
4055 #define SAI2_S                    ((SAI_TypeDef *) SAI2_BASE_S)
4056 #define SAI2_Block_A_S            ((SAI_Block_TypeDef *) SAI2_Block_A_BASE_S)
4057 #define SAI2_Block_B_S            ((SAI_Block_TypeDef *) SAI2_Block_B_BASE_S)
4058 #define SDMMC1_S                  ((SDMMC_TypeDef *) SDMMC1_BASE_S)
4059 #define SDMMC2_S                  ((SDMMC_TypeDef *) SDMMC2_BASE_S)
4060 #define SPDIFRX_S                 ((SPDIFRX_TypeDef *) SPDIFRX_BASE_S)
4061 #define SPI1_S                    ((SPI_TypeDef *) SPI1_BASE_S)
4062 #define SPI2_S                    ((SPI_TypeDef *) SPI2_BASE_S)
4063 #define SPI3_S                    ((SPI_TypeDef *) SPI3_BASE_S)
4064 #define SPI4_S                    ((SPI_TypeDef *) SPI4_BASE_S)
4065 #define SPI5_S                    ((SPI_TypeDef *) SPI5_BASE_S)
4066 #define SPI6_S                    ((SPI_TypeDef *) SPI6_BASE_S)
4067 #define SYSCFG_S                  ((SYSCFG_TypeDef *) SYSCFG_BASE_S)
4068 #define TAMP_S                    ((TAMP_TypeDef *) TAMP_BASE_S)
4069 #define TIM1_S                    ((TIM_TypeDef *) TIM1_BASE_S)
4070 #define TIM2_S                    ((TIM_TypeDef *) TIM2_BASE_S)
4071 #define TIM3_S                    ((TIM_TypeDef *) TIM3_BASE_S)
4072 #define TIM4_S                    ((TIM_TypeDef *) TIM4_BASE_S)
4073 #define TIM5_S                    ((TIM_TypeDef *) TIM5_BASE_S)
4074 #define TIM6_S                    ((TIM_TypeDef *) TIM6_BASE_S)
4075 #define TIM7_S                    ((TIM_TypeDef *) TIM7_BASE_S)
4076 #define TIM8_S                    ((TIM_TypeDef *) TIM8_BASE_S)
4077 #define TIM9_S                    ((TIM_TypeDef *) TIM9_BASE_S)
4078 #define TIM10_S                   ((TIM_TypeDef *) TIM10_BASE_S)
4079 #define TIM11_S                   ((TIM_TypeDef *) TIM11_BASE_S)
4080 #define TIM12_S                   ((TIM_TypeDef *) TIM12_BASE_S)
4081 #define TIM13_S                   ((TIM_TypeDef *) TIM13_BASE_S)
4082 #define TIM14_S                   ((TIM_TypeDef *) TIM14_BASE_S)
4083 #define TIM15_S                   ((TIM_TypeDef *) TIM15_BASE_S)
4084 #define TIM16_S                   ((TIM_TypeDef *) TIM16_BASE_S)
4085 #define TIM17_S                   ((TIM_TypeDef *) TIM17_BASE_S)
4086 #define TIM18_S                   ((TIM_TypeDef *) TIM18_BASE_S)
4087 #define UART4_S                   ((USART_TypeDef *) UART4_BASE_S)
4088 #define UART5_S                   ((USART_TypeDef *) UART5_BASE_S)
4089 #define UART7_S                   ((USART_TypeDef *) UART7_BASE_S)
4090 #define UART8_S                   ((USART_TypeDef *) UART8_BASE_S)
4091 #define UART9_S                   ((USART_TypeDef *) UART9_BASE_S)
4092 #define UCPD1_S                   ((UCPD_TypeDef *) UCPD1_BASE_S)
4093 #define USART1_S                  ((USART_TypeDef *) USART1_BASE_S)
4094 #define USART2_S                  ((USART_TypeDef *) USART2_BASE_S)
4095 #define USART3_S                  ((USART_TypeDef *) USART3_BASE_S)
4096 #define USART6_S                  ((USART_TypeDef *) USART6_BASE_S)
4097 #define USART10_S                 ((USART_TypeDef *) USART10_BASE_S)
4098 #define USB1_OTG_HS_S             ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_BASE_S)
4099 #define USB2_OTG_HS_S             ((USB_OTG_GlobalTypeDef *) USB2_OTG_HS_BASE_S)
4100 #define USB1_HS_PHYC_S            ((USB_HS_PHYC_GlobalTypeDef *) USB1_HS_PHYC_BASE_S)
4101 #define USB2_HS_PHYC_S            ((USB_HS_PHYC_GlobalTypeDef *) USB2_HS_PHYC_BASE_S)
4102 #define VENC_S                    ((VENC_TypeDef *) VENC_BASE_S)
4103 #define VREFBUF_S                 ((VREFBUF_TypeDef *) VREFBUF_BASE_S)
4104 #define WWDG_S                    ((WWDG_TypeDef *) WWDG_BASE_S)
4105 #define XSPI1_S                   ((XSPI_TypeDef *) XSPI1_BASE_S)
4106 #define XSPI2_S                   ((XSPI_TypeDef *) XSPI2_BASE_S)
4107 #define XSPI3_S                   ((XSPI_TypeDef *) XSPI3_BASE_S)
4108 #define XSPIM_S                   ((XSPIM_TypeDef *) XSPIM_BASE_S)
4109 #endif
4110 
4111 /*!< Peripheral Instance aliases for Non-Secure/Secure execution  */
4112 #if defined (CPU_IN_SECURE_STATE)
4113 #define ADC12_COMMON              ADC12_COMMON_S
4114 #define ADC12_COMMON_BASE         ADC12_COMMON_BASE_S
4115 
4116 #define ADC1                      ADC1_S
4117 #define ADC1_BASE                 ADC1_BASE_S
4118 
4119 #define ADC2                      ADC2_S
4120 #define ADC2_BASE                 ADC2_BASE_S
4121 
4122 #define ADF1                      ADF1_S
4123 #define ADF1_BASE                 ADF1_BASE_S
4124 
4125 #define ADF1_Filter0              ADF1_Filter0_S
4126 #define ADF1_Filter0_BASE         ADF1_Filter0_BASE_S
4127 
4128 #define BSEC                      BSEC_S
4129 #define BSEC_BASE                 BSEC_BASE_S
4130 
4131 #define CACHEAXI                  CACHEAXI_S
4132 #define CACHEAXI_BASE             CACHEAXI_BASE_S
4133 
4134 #define CRC                       CRC_S
4135 #define CRC_BASE                  CRC_BASE_S
4136 
4137 #define CRYP                      CRYP_S
4138 #define CRYP_BASE                 CRYP_BASE_S
4139 
4140 #define CSI                       CSI_S
4141 #define CSI_BASE                  CSI_BASE_S
4142 
4143 #define DBGMCU                    DBGMCU_S
4144 #define DBGMCU_BASE               DBGMCU_BASE_S
4145 
4146 #define DCMI                      DCMI_S
4147 #define DCMI_BASE                 DCMI_BASE_S
4148 
4149 #define DCMIPP                    DCMIPP_S
4150 #define DCMIPP_BASE               DCMIPP_BASE_S
4151 
4152 #define DLYB_SDMMC1               DLYB_SDMMC1_S
4153 #define DLYB_SDMMC1_BASE          DLYB_SDMMC1_BASE_S
4154 
4155 #define DLYB_SDMMC2               DLYB_SDMMC2_S
4156 #define DLYB_SDMMC2_BASE          DLYB_SDMMC2_BASE_S
4157 
4158 #define DMA2D                     DMA2D_S
4159 #define DMA2D_BASE                DMA2D_BASE_S
4160 
4161 #define DTS                       DTS_S
4162 #define DTS_BASE                  DTS_BASE_S
4163 
4164 #define DTS_Sensor0               DTS_Sensor0_S
4165 #define DTS_Sensor0_BASE          DTS_Sensor0_BASE_S
4166 
4167 #define DTS_Sensor1               DTS_Sensor1_S
4168 #define DTS_Sensor1_BASE          DTS_Sensor1_BASE_S
4169 
4170 #define ETH1                      ETH1_S
4171 #define ETH1_BASE                 ETH1_BASE_S
4172 
4173 #define EXTI                      EXTI_S
4174 #define EXTI_BASE                 EXTI_BASE_S
4175 
4176 #define FDCAN1                    FDCAN1_S
4177 #define FDCAN1_BASE               FDCAN1_BASE_S
4178 
4179 #define FDCAN2                    FDCAN2_S
4180 #define FDCAN2_BASE               FDCAN2_BASE_S
4181 
4182 #define FDCAN3                    FDCAN3_S
4183 #define FDCAN3_BASE               FDCAN3_BASE_S
4184 
4185 #define FDCAN_CCU                 FDCAN_CCU_S
4186 #define FDCAN_CCU_BASE            FDCAN_CCU_BASE_S
4187 
4188 #define FDCAN_CONFIG              FDCAN_CONFIG_S
4189 #define FDCAN_CONFIG_BASE         FDCAN_CONFIG_BASE_S
4190 
4191 #define FMC_R_BASE                FMC_R_BASE_S
4192 
4193 #define FMC_Bank1E_R              FMC_Bank1E_R_S
4194 #define FMC_Bank1E_R_BASE         FMC_Bank1E_R_BASE_S
4195 
4196 #define FMC_Bank1_R               FMC_Bank1_R_S
4197 #define FMC_Bank1_R_BASE          FMC_Bank1_R_BASE_S
4198 
4199 #define FMC_Bank3_R               FMC_Bank3_R_S
4200 #define FMC_Bank3_R_BASE          FMC_Bank3_R_BASE_S
4201 
4202 #define FMC_Bank5_6_R             FMC_Bank5_6_R_S
4203 #define FMC_Bank5_6_R_BASE        FMC_Bank5_6_R_BASE_S
4204 
4205 #define FMC_Common_R              FMC_Common_R_S
4206 #define FMC_Common_R_BASE         FMC_Common_R_BASE_S
4207 
4208 #define GFXMMU                       GFXMMU_S
4209 #define GFXMMU_BASE                  GFXMMU_BASE_S
4210 #define GFXMMU_VIRTUAL_BUFFER0_BASE  GFXMMU_VIRTUAL_BUFFER0_BASE_S
4211 #define GFXMMU_VIRTUAL_BUFFER1_BASE  GFXMMU_VIRTUAL_BUFFER1_BASE_S
4212 #define GFXMMU_VIRTUAL_BUFFER2_BASE  GFXMMU_VIRTUAL_BUFFER2_BASE_S
4213 #define GFXMMU_VIRTUAL_BUFFER3_BASE  GFXMMU_VIRTUAL_BUFFER3_BASE_S
4214 
4215 #define GFXTIM                    GFXTIM_S
4216 #define GFXTIM_BASE               GFXTIM_BASE_S
4217 
4218 #define GPDMA1                    GPDMA1_S
4219 #define GPDMA1_BASE               GPDMA1_BASE_S
4220 
4221 #define GPDMA1_Channel0           GPDMA1_Channel0_S
4222 #define GPDMA1_Channel0_BASE      GPDMA1_Channel0_BASE_S
4223 
4224 #define GPDMA1_Channel1           GPDMA1_Channel1_S
4225 #define GPDMA1_Channel1_BASE      GPDMA1_Channel1_BASE_S
4226 
4227 #define GPDMA1_Channel2           GPDMA1_Channel2_S
4228 #define GPDMA1_Channel2_BASE      GPDMA1_Channel2_BASE_S
4229 
4230 #define GPDMA1_Channel3           GPDMA1_Channel3_S
4231 #define GPDMA1_Channel3_BASE      GPDMA1_Channel3_BASE_S
4232 
4233 #define GPDMA1_Channel4           GPDMA1_Channel4_S
4234 #define GPDMA1_Channel4_BASE      GPDMA1_Channel4_BASE_S
4235 
4236 #define GPDMA1_Channel5           GPDMA1_Channel5_S
4237 #define GPDMA1_Channel5_BASE      GPDMA1_Channel5_BASE_S
4238 
4239 #define GPDMA1_Channel6           GPDMA1_Channel6_S
4240 #define GPDMA1_Channel6_BASE      GPDMA1_Channel6_BASE_S
4241 
4242 #define GPDMA1_Channel7           GPDMA1_Channel7_S
4243 #define GPDMA1_Channel7_BASE      GPDMA1_Channel7_BASE_S
4244 
4245 #define GPDMA1_Channel8           GPDMA1_Channel8_S
4246 #define GPDMA1_Channel8_BASE      GPDMA1_Channel8_BASE_S
4247 
4248 #define GPDMA1_Channel9           GPDMA1_Channel9_S
4249 #define GPDMA1_Channel9_BASE      GPDMA1_Channel9_BASE_S
4250 
4251 #define GPDMA1_Channel10          GPDMA1_Channel10_S
4252 #define GPDMA1_Channel10_BASE     GPDMA1_Channel10_BASE_S
4253 
4254 #define GPDMA1_Channel11          GPDMA1_Channel11_S
4255 #define GPDMA1_Channel11_BASE     GPDMA1_Channel11_BASE_S
4256 
4257 #define GPDMA1_Channel12          GPDMA1_Channel12_S
4258 #define GPDMA1_Channel12_BASE     GPDMA1_Channel12_BASE_S
4259 
4260 #define GPDMA1_Channel13          GPDMA1_Channel13_S
4261 #define GPDMA1_Channel13_BASE     GPDMA1_Channel13_BASE_S
4262 
4263 #define GPDMA1_Channel14          GPDMA1_Channel14_S
4264 #define GPDMA1_Channel14_BASE     GPDMA1_Channel14_BASE_S
4265 
4266 #define GPDMA1_Channel15          GPDMA1_Channel15_S
4267 #define GPDMA1_Channel15_BASE     GPDMA1_Channel15_BASE_S
4268 
4269 #define GPIOA                     GPIOA_S
4270 #define GPIOA_BASE                GPIOA_BASE_S
4271 
4272 #define GPIOB                     GPIOB_S
4273 #define GPIOB_BASE                GPIOB_BASE_S
4274 
4275 #define GPIOC                     GPIOC_S
4276 #define GPIOC_BASE                GPIOC_BASE_S
4277 
4278 #define GPIOD                     GPIOD_S
4279 #define GPIOD_BASE                GPIOD_BASE_S
4280 
4281 #define GPIOE                     GPIOE_S
4282 #define GPIOE_BASE                GPIOE_BASE_S
4283 
4284 #define GPIOF                     GPIOF_S
4285 #define GPIOF_BASE                GPIOF_BASE_S
4286 
4287 #define GPIOG                     GPIOG_S
4288 #define GPIOG_BASE                GPIOG_BASE_S
4289 
4290 #define GPIOH                     GPIOH_S
4291 #define GPIOH_BASE                GPIOH_BASE_S
4292 
4293 #define GPION                     GPION_S
4294 #define GPION_BASE                GPION_BASE_S
4295 
4296 #define GPIOO                     GPIOO_S
4297 #define GPIOO_BASE                GPIOO_BASE_S
4298 
4299 #define GPIOP                     GPIOP_S
4300 #define GPIOP_BASE                GPIOP_BASE_S
4301 
4302 #define GPIOQ                     GPIOQ_S
4303 #define GPIOQ_BASE                GPIOQ_BASE_S
4304 
4305 #define GPU2D                     GPU2D_BASE_S
4306 #define GPU2D_BASE                GPU2D_BASE_S
4307 
4308 #define HASH                      HASH_S
4309 #define HASH_BASE                 HASH_BASE_S
4310 
4311 #define HASH_DIGEST               HASH_DIGEST_S
4312 #define HASH_DIGEST_BASE          HASH_DIGEST_BASE_S
4313 
4314 #define HPDMA1                    HPDMA1_S
4315 #define HPDMA1_BASE               HPDMA1_BASE_S
4316 
4317 #define HPDMA1_Channel0           HPDMA1_Channel0_S
4318 #define HPDMA1_Channel0_BASE      HPDMA1_Channel0_BASE_S
4319 
4320 #define HPDMA1_Channel1           HPDMA1_Channel1_S
4321 #define HPDMA1_Channel1_BASE      HPDMA1_Channel1_BASE_S
4322 
4323 #define HPDMA1_Channel2           HPDMA1_Channel2_S
4324 #define HPDMA1_Channel2_BASE      HPDMA1_Channel2_BASE_S
4325 
4326 #define HPDMA1_Channel3           HPDMA1_Channel3_S
4327 #define HPDMA1_Channel3_BASE      HPDMA1_Channel3_BASE_S
4328 
4329 #define HPDMA1_Channel4           HPDMA1_Channel4_S
4330 #define HPDMA1_Channel4_BASE      HPDMA1_Channel4_BASE_S
4331 
4332 #define HPDMA1_Channel5           HPDMA1_Channel5_S
4333 #define HPDMA1_Channel5_BASE      HPDMA1_Channel5_BASE_S
4334 
4335 #define HPDMA1_Channel6           HPDMA1_Channel6_S
4336 #define HPDMA1_Channel6_BASE      HPDMA1_Channel6_BASE_S
4337 
4338 #define HPDMA1_Channel7           HPDMA1_Channel7_S
4339 #define HPDMA1_Channel7_BASE      HPDMA1_Channel7_BASE_S
4340 
4341 #define HPDMA1_Channel8           HPDMA1_Channel8_S
4342 #define HPDMA1_Channel8_BASE      HPDMA1_Channel8_BASE_S
4343 
4344 #define HPDMA1_Channel9           HPDMA1_Channel9_S
4345 #define HPDMA1_Channel9_BASE      HPDMA1_Channel9_BASE_S
4346 
4347 #define HPDMA1_Channel10          HPDMA1_Channel10_S
4348 #define HPDMA1_Channel10_BASE     HPDMA1_Channel10_BASE_S
4349 
4350 #define HPDMA1_Channel11          HPDMA1_Channel11_S
4351 #define HPDMA1_Channel11_BASE     HPDMA1_Channel11_BASE_S
4352 
4353 #define HPDMA1_Channel12          HPDMA1_Channel12_S
4354 #define HPDMA1_Channel12_BASE     HPDMA1_Channel12_BASE_S
4355 
4356 #define HPDMA1_Channel13          HPDMA1_Channel13_S
4357 #define HPDMA1_Channel13_BASE     HPDMA1_Channel13_BASE_S
4358 
4359 #define HPDMA1_Channel14          HPDMA1_Channel14_S
4360 #define HPDMA1_Channel14_BASE     HPDMA1_Channel14_BASE_S
4361 
4362 #define HPDMA1_Channel15          HPDMA1_Channel15_S
4363 #define HPDMA1_Channel15_BASE     HPDMA1_Channel15_BASE_S
4364 
4365 #define I2C1                      I2C1_S
4366 #define I2C1_BASE                 I2C1_BASE_S
4367 
4368 #define I2C2                      I2C2_S
4369 #define I2C2_BASE                 I2C2_BASE_S
4370 
4371 #define I2C3                      I2C3_S
4372 #define I2C3_BASE                 I2C3_BASE_S
4373 
4374 #define I2C4                      I2C4_S
4375 #define I2C4_BASE                 I2C4_BASE_S
4376 
4377 #define I3C1                      I3C1_S
4378 #define I3C1_BASE                 I3C1_BASE_S
4379 
4380 #define I3C2                      I3C2_S
4381 #define I3C2_BASE                 I3C2_BASE_S
4382 
4383 #define IAC                       IAC_S
4384 #define IAC_BASE                  IAC_BASE_S
4385 
4386 #define ICACHE                    ICACHE_S
4387 #define ICACHE_BASE               ICACHE_BASE_S
4388 
4389 #define IWDG                      IWDG_S
4390 #define IWDG_BASE                 IWDG_BASE_S
4391 
4392 #define JPEG                      JPEG_S
4393 #define JPEG_BASE                 JPEG_BASE_S
4394 
4395 #define LPTIM1                    LPTIM1_S
4396 #define LPTIM1_BASE               LPTIM1_BASE_S
4397 
4398 #define LPTIM2                    LPTIM2_S
4399 #define LPTIM2_BASE               LPTIM2_BASE_S
4400 
4401 #define LPTIM3                    LPTIM3_S
4402 #define LPTIM3_BASE               LPTIM3_BASE_S
4403 
4404 #define LPTIM4                    LPTIM4_S
4405 #define LPTIM4_BASE               LPTIM4_BASE_S
4406 
4407 #define LPTIM5                    LPTIM5_S
4408 #define LPTIM5_BASE               LPTIM5_BASE_S
4409 
4410 #define LPUART1                   LPUART1_S
4411 #define LPUART1_BASE              LPUART1_BASE_S
4412 
4413 #define LTDC                      LTDC_S
4414 #define LTDC_BASE                 LTDC_BASE_S
4415 
4416 #define LTDC_Layer1               LTDC_Layer1_S
4417 #define LTDC_Layer1_BASE          LTDC_Layer1_BASE_S
4418 
4419 #define LTDC_Layer2               LTDC_Layer2_S
4420 #define LTDC_Layer2_BASE          LTDC_Layer2_BASE_S
4421 
4422 #define MCE1                      MCE1_S
4423 #define MCE1_BASE                 MCE1_BASE_S
4424 
4425 #define MCE1_REGION1              MCE1_REGION1_S
4426 #define MCE1_REGION1_BASE         MCE1_REGION1_BASE_S
4427 
4428 #define MCE1_REGION2              MCE1_REGION2_S
4429 #define MCE1_REGION2_BASE         MCE1_REGION2_BASE_S
4430 
4431 #define MCE1_REGION3              MCE1_REGION3_S
4432 #define MCE1_REGION3_BASE         MCE1_REGION3_BASE_S
4433 
4434 #define MCE1_REGION4              MCE1_REGION4_S
4435 #define MCE1_REGION4_BASE         MCE1_REGION4_BASE_S
4436 
4437 #define MCE1_CONTEXT1             MCE1_CONTEXT1_S
4438 #define MCE1_CONTEXT1_BASE        MCE1_CONTEXT1_BASE_S
4439 
4440 #define MCE1_CONTEXT2             MCE1_CONTEXT2_S
4441 #define MCE1_CONTEXT2_BASE        MCE1_CONTEXT2_BASE_S
4442 
4443 #define MCE2                      MCE2_S
4444 #define MCE2_BASE                 MCE2_BASE_S
4445 
4446 #define MCE2_REGION1              MCE2_REGION1_S
4447 #define MCE2_REGION1_BASE         MCE2_REGION1_BASE_S
4448 
4449 #define MCE2_REGION2              MCE2_REGION2_S
4450 #define MCE2_REGION2_BASE         MCE2_REGION2_BASE_S
4451 
4452 #define MCE2_REGION3              MCE2_REGION3_S
4453 #define MCE2_REGION3_BASE         MCE2_REGION3_BASE_S
4454 
4455 #define MCE2_REGION4              MCE2_REGION4_S
4456 #define MCE2_REGION4_BASE         MCE2_REGION4_BASE_S
4457 
4458 #define MCE2_CONTEXT1             MCE2_CONTEXT1_S
4459 #define MCE2_CONTEXT1_BASE        MCE2_CONTEXT1_BASE_S
4460 
4461 #define MCE2_CONTEXT2             MCE2_CONTEXT2_S
4462 #define MCE2_CONTEXT2_BASE        MCE2_CONTEXT2_BASE_S
4463 
4464 #define MCE3                      MCE3_S
4465 #define MCE3_BASE                 MCE3_BASE_S
4466 
4467 #define MCE3_REGION1              MCE3_REGION1_S
4468 #define MCE3_REGION1_BASE         MCE3_REGION1_BASE_S
4469 
4470 #define MCE3_REGION2              MCE3_REGION2_S
4471 #define MCE3_REGION2_BASE         MCE3_REGION2_BASE_S
4472 
4473 #define MCE3_REGION3              MCE3_REGION3_S
4474 #define MCE3_REGION3_BASE         MCE3_REGION3_BASE_S
4475 
4476 #define MCE3_REGION4              MCE3_REGION4_S
4477 #define MCE3_REGION4_BASE         MCE3_REGION4_BASE_S
4478 
4479 #define MCE3_CONTEXT1             MCE3_CONTEXT1_S
4480 #define MCE3_CONTEXT1_BASE        MCE3_CONTEXT1_BASE_S
4481 
4482 #define MCE3_CONTEXT2             MCE3_CONTEXT2_S
4483 #define MCE3_CONTEXT2_BASE        MCE3_CONTEXT2_BASE_S
4484 
4485 #define MCE4                      MCE4_S
4486 #define MCE4_BASE                 MCE4_BASE_S
4487 
4488 #define MCE4_REGION1              MCE4_REGION1_S
4489 #define MCE4_REGION1_BASE         MCE4_REGION1_BASE_S
4490 
4491 #define MCE4_REGION2              MCE4_REGION2_S
4492 #define MCE4_REGION2_BASE         MCE4_REGION2_BASE_S
4493 
4494 #define MCE4_REGION3              MCE4_REGION3_S
4495 #define MCE4_REGION3_BASE         MCE4_REGION3_BASE_S
4496 
4497 #define MCE4_REGION4              MCE4_REGION4_S
4498 #define MCE4_REGION4_BASE         MCE4_REGION4_BASE_S
4499 
4500 #define MCE4_CONTEXT1             MCE4_CONTEXT1_S
4501 #define MCE4_CONTEXT1_BASE        MCE4_CONTEXT1_BASE_S
4502 
4503 #define MCE4_CONTEXT2             MCE4_CONTEXT2_S
4504 #define MCE4_CONTEXT2_BASE        MCE4_CONTEXT2_BASE_S
4505 
4506 #define MDF1                      MDF1_S
4507 #define MDF1_BASE                 MDF1_BASE_S
4508 
4509 #define MDF1_Filter0              MDF1_Filter0_S
4510 #define MDF1_Filter0_BASE         MDF1_Filter0_BASE_S
4511 
4512 #define MDF1_Filter1              MDF1_Filter1_S
4513 #define MDF1_Filter1_BASE         MDF1_Filter1_BASE_S
4514 
4515 #define MDF1_Filter2              MDF1_Filter2_S
4516 #define MDF1_Filter2_BASE         MDF1_Filter2_BASE_S
4517 
4518 #define MDF1_Filter3              MDF1_Filter3_S
4519 #define MDF1_Filter3_BASE         MDF1_Filter3_BASE_S
4520 
4521 #define MDF1_Filter4              MDF1_Filter4_S
4522 #define MDF1_Filter4_BASE         MDF1_Filter4_BASE_S
4523 
4524 #define MDF1_Filter5              MDF1_Filter5_S
4525 #define MDF1_Filter5_BASE         MDF1_Filter5_BASE_S
4526 
4527 #define MDIOS                     MDIOS_S
4528 #define MDIOS_BASE                MDIOS_BASE_S
4529 
4530 #define NPU_PRESENT
4531 #define NPU_BASE                  NPU_BASE_S
4532 
4533 #define PKA                       PKA_S
4534 #define PKA_BASE                  PKA_BASE_S
4535 
4536 #define PSSI                      PSSI_S
4537 #define PSSI_BASE                 PSSI_BASE_S
4538 
4539 #define PWR                       PWR_S
4540 #define PWR_BASE                  PWR_BASE_S
4541 
4542 #define RAMCFG                    RAMCFG_S
4543 #define RAMCFG_BASE               RAMCFG_BASE_S
4544 
4545 #define RAMCFG_SRAM1_AXI          RAMCFG_SRAM1_AXI_S
4546 #define RAMCFG_SRAM1_AXI_BASE     RAMCFG_SRAM1_AXI_BASE_S
4547 
4548 #define RAMCFG_SRAM2_AXI          RAMCFG_SRAM2_AXI_S
4549 #define RAMCFG_SRAM2_AXI_BASE     RAMCFG_SRAM2_AXI_BASE_S
4550 
4551 #define RAMCFG_SRAM3_AXI          RAMCFG_SRAM3_AXI_S
4552 #define RAMCFG_SRAM3_AXI_BASE     RAMCFG_SRAM3_AXI_BASE_S
4553 
4554 #define RAMCFG_SRAM4_AXI          RAMCFG_SRAM4_AXI_S
4555 #define RAMCFG_SRAM4_AXI_BASE     RAMCFG_SRAM4_AXI_BASE_S
4556 
4557 #define RAMCFG_SRAM5_AXI          RAMCFG_SRAM5_AXI_S
4558 #define RAMCFG_SRAM5_AXI_BASE     RAMCFG_SRAM5_AXI_BASE_S
4559 
4560 #define RAMCFG_SRAM6_AXI          RAMCFG_SRAM6_AXI_S
4561 #define RAMCFG_SRAM6_AXI_BASE     RAMCFG_SRAM6_AXI_BASE_S
4562 
4563 #define RAMCFG_SRAM1_AHB          RAMCFG_SRAM1_AHB_S
4564 #define RAMCFG_SRAM1_AHB_BASE     RAMCFG_SRAM1_AHB_BASE_S
4565 
4566 #define RAMCFG_SRAM2_AHB          RAMCFG_SRAM2_AHB_S
4567 #define RAMCFG_SRAM2_AHB_BASE     RAMCFG_SRAM2_AHB_BASE_S
4568 
4569 #define RAMCFG_VENC_RAM           RAMCFG_VENC_RAM_S
4570 #define RAMCFG_VENC_RAM_BASE      RAMCFG_VENC_RAM_BASE_S
4571 
4572 #define RAMCFG_BKPSRAM            RAMCFG_BKPSRAM_S
4573 #define RAMCFG_BKPSRAM_BASE       RAMCFG_BKPSRAM_BASE_S
4574 
4575 #define RAMCFG_FLEXRAM            RAMCFG_FLEXRAM_S
4576 #define RAMCFG_FLEXRAM_BASE       RAMCFG_FLEXRAM_BASE_S
4577 
4578 #define RCC                       RCC_S
4579 #define RCC_BASE                  RCC_BASE_S
4580 
4581 #define RIFSC                     RIFSC_S
4582 #define RIFSC_BASE                RIFSC_BASE_S
4583 
4584 #define RISAF1                    RISAF1_S
4585 #define RISAF1_BASE               RISAF1_BASE_S
4586 
4587 #define RISAF2                    RISAF2_S
4588 #define RISAF2_BASE               RISAF2_BASE_S
4589 
4590 #define RISAF3                    RISAF3_S
4591 #define RISAF3_BASE               RISAF3_BASE_S
4592 
4593 #define RISAF4                    RISAF4_S
4594 #define RISAF4_BASE               RISAF4_BASE_S
4595 
4596 #define RISAF5                    RISAF5_S
4597 #define RISAF5_BASE               RISAF5_BASE_S
4598 
4599 #define RISAF6                    RISAF6_S
4600 #define RISAF6_BASE               RISAF6_BASE_S
4601 
4602 #define RISAF7                    RISAF7_S
4603 #define RISAF7_BASE               RISAF7_BASE_S
4604 
4605 #define RISAF8                    RISAF8_S
4606 #define RISAF8_BASE               RISAF8_BASE_S
4607 
4608 #define RISAF9                    RISAF9_S
4609 #define RISAF9_BASE               RISAF9_BASE_S
4610 
4611 #define RISAF11                   RISAF11_S
4612 #define RISAF11_BASE              RISAF11_BASE_S
4613 
4614 #define RISAF12                   RISAF12_S
4615 #define RISAF12_BASE              RISAF12_BASE_S
4616 
4617 #define RISAF13                   RISAF13_S
4618 #define RISAF13_BASE              RISAF13_BASE_S
4619 
4620 #define RISAF14                   RISAF14_S
4621 #define RISAF14_BASE              RISAF14_BASE_S
4622 
4623 #define RISAF15                   RISAF15_S
4624 #define RISAF15_BASE              RISAF15_BASE_S
4625 
4626 #define RISAF21                   RISAF21_S
4627 #define RISAF21_BASE              RISAF21_BASE_S
4628 
4629 #define RISAF22                   RISAF22_S
4630 #define RISAF22_BASE              RISAF22_BASE_S
4631 
4632 #define RISAF23                   RISAF23_S
4633 #define RISAF23_BASE              RISAF23_BASE_S
4634 
4635 #define RNG                       RNG_S
4636 #define RNG_BASE                  RNG_BASE_S
4637 
4638 #define RTC                       RTC_S
4639 #define RTC_BASE                  RTC_BASE_S
4640 
4641 #define SAES                      SAES_S
4642 #define SAES_BASE                 SAES_BASE_S
4643 
4644 #define SAI1                      SAI1_S
4645 #define SAI1_BASE                 SAI1_BASE_S
4646 
4647 #define SAI1_Block_A              SAI1_Block_A_S
4648 #define SAI1_Block_A_BASE         SAI1_Block_A_BASE_S
4649 
4650 #define SAI1_Block_B              SAI1_Block_B_S
4651 #define SAI1_Block_B_BASE         SAI1_Block_B_BASE_S
4652 
4653 #define SAI2                      SAI2_S
4654 #define SAI2_BASE                 SAI2_BASE_S
4655 
4656 #define SAI2_Block_A              SAI2_Block_A_S
4657 #define SAI2_Block_A_BASE         SAI2_Block_A_BASE_S
4658 
4659 #define SAI2_Block_B              SAI2_Block_B_S
4660 #define SAI2_Block_B_BASE         SAI2_Block_B_BASE_S
4661 
4662 #define SDMMC1                    SDMMC1_S
4663 #define SDMMC1_BASE               SDMMC1_BASE_S
4664 
4665 #define SDMMC2                    SDMMC2_S
4666 #define SDMMC2_BASE               SDMMC2_BASE_S
4667 
4668 #define SPDIFRX                   SPDIFRX_S
4669 #define SPDIFRX_BASE              SPDIFRX_BASE_S
4670 
4671 #define SPI1                      SPI1_S
4672 #define SPI1_BASE                 SPI1_BASE_S
4673 
4674 #define SPI2                      SPI2_S
4675 #define SPI2_BASE                 SPI2_BASE_S
4676 
4677 #define SPI3                      SPI3_S
4678 #define SPI3_BASE                 SPI3_BASE_S
4679 
4680 #define SPI4                      SPI4_S
4681 #define SPI4_BASE                 SPI4_BASE_S
4682 
4683 #define SPI5                      SPI5_S
4684 #define SPI5_BASE                 SPI5_BASE_S
4685 
4686 #define SPI6                      SPI6_S
4687 #define SPI6_BASE                 SPI6_BASE_S
4688 
4689 #define SRAMCAN_BASE              SRAMCAN_BASE_S
4690 
4691 #define SYSCFG                    SYSCFG_S
4692 #define SYSCFG_BASE               SYSCFG_BASE_S
4693 
4694 #define TAMP                      TAMP_S
4695 #define TAMP_BASE                 TAMP_BASE_S
4696 
4697 #define TIM1                      TIM1_S
4698 #define TIM1_BASE                 TIM1_BASE_S
4699 
4700 #define TIM2                      TIM2_S
4701 #define TIM2_BASE                 TIM2_BASE_S
4702 
4703 #define TIM3                      TIM3_S
4704 #define TIM3_BASE                 TIM3_BASE_S
4705 
4706 #define TIM4                      TIM4_S
4707 #define TIM4_BASE                 TIM4_BASE_S
4708 
4709 #define TIM5                      TIM5_S
4710 #define TIM5_BASE                 TIM5_BASE_S
4711 
4712 #define TIM6                      TIM6_S
4713 #define TIM6_BASE                 TIM6_BASE_S
4714 
4715 #define TIM7                      TIM7_S
4716 #define TIM7_BASE                 TIM7_BASE_S
4717 
4718 #define TIM8                      TIM8_S
4719 #define TIM8_BASE                 TIM8_BASE_S
4720 
4721 #define TIM9                      TIM9_S
4722 #define TIM9_BASE                 TIM9_BASE_S
4723 
4724 #define TIM10                     TIM10_S
4725 #define TIM10_BASE                TIM10_BASE_S
4726 
4727 #define TIM11                     TIM11_S
4728 #define TIM11_BASE                TIM11_BASE_S
4729 
4730 #define TIM12                     TIM12_S
4731 #define TIM12_BASE                TIM12_BASE_S
4732 
4733 #define TIM13                     TIM13_S
4734 #define TIM13_BASE                TIM13_BASE_S
4735 
4736 #define TIM14                     TIM14_S
4737 #define TIM14_BASE                TIM14_BASE_S
4738 
4739 #define TIM15                     TIM15_S
4740 #define TIM15_BASE                TIM15_BASE_S
4741 
4742 #define TIM16                     TIM16_S
4743 #define TIM16_BASE                TIM16_BASE_S
4744 
4745 #define TIM17                     TIM17_S
4746 #define TIM17_BASE                TIM17_BASE_S
4747 
4748 #define TIM18                     TIM18_S
4749 #define TIM18_BASE                TIM18_BASE_S
4750 
4751 #define UART4                     UART4_S
4752 #define UART4_BASE                UART4_BASE_S
4753 
4754 #define UART5                     UART5_S
4755 #define UART5_BASE                UART5_BASE_S
4756 
4757 #define UART7                     UART7_S
4758 #define UART7_BASE                UART7_BASE_S
4759 
4760 #define UART8                     UART8_S
4761 #define UART8_BASE                UART8_BASE_S
4762 
4763 #define UART9                     UART9_S
4764 #define UART9_BASE                UART9_BASE_S
4765 
4766 #define UCPD1                     UCPD1_S
4767 #define UCPD1_BASE                UCPD1_BASE_S
4768 
4769 #define USART1                    USART1_S
4770 #define USART1_BASE               USART1_BASE_S
4771 
4772 #define USART2                    USART2_S
4773 #define USART2_BASE               USART2_BASE_S
4774 
4775 #define USART3                    USART3_S
4776 #define USART3_BASE               USART3_BASE_S
4777 
4778 #define USART6                    USART6_S
4779 #define USART6_BASE               USART6_BASE_S
4780 
4781 #define USART10                   USART10_S
4782 #define USART10_BASE              USART10_BASE_S
4783 
4784 #define USB1_OTG_HS               USB1_OTG_HS_S
4785 #define USB1_OTG_HS_BASE          USB1_OTG_HS_BASE_S
4786 
4787 #define USB2_OTG_HS               USB2_OTG_HS_S
4788 #define USB2_OTG_HS_BASE          USB2_OTG_HS_BASE_S
4789 
4790 #define USB1_HS_PHYC              USB1_HS_PHYC_S
4791 #define USB1_HS_PHYC_BASE         USB1_HS_PHYC_BASE_S
4792 
4793 #define USB2_HS_PHYC              USB2_HS_PHYC_S
4794 #define USB2_HS_PHYC_BASE         USB2_HS_PHYC_BASE_S
4795 
4796 #define VENC                      VENC_S
4797 #define VENC_BASE                 VENC_BASE_S
4798 
4799 #define VREFBUF                   VREFBUF_S
4800 #define VREFBUF_BASE              VREFBUF_BASE_S
4801 
4802 #define WWDG                      WWDG_S
4803 #define WWDG_BASE                 WWDG_BASE_S
4804 
4805 #define XSPI1                     XSPI1_S
4806 
4807 #define XSPI2                     XSPI2_S
4808 
4809 #define XSPI3                     XSPI3_S
4810 
4811 #define XSPIM                     XSPIM_S
4812 #define XSPIM_BASE                XSPIM_BASE_S
4813 
4814 /*!< Unique device ID register base address */
4815 #define UID_BASE                  UID_BASE_S
4816 
4817 /*!< Revision ID base address */
4818 #define REVID_BASE                REVID_BASE_S
4819 
4820 #else
4821 
4822 #define ADC12_COMMON              ADC12_COMMON_NS
4823 #define ADC12_COMMON_BASE         ADC12_COMMON_BASE_NS
4824 
4825 #define ADC1                      ADC1_NS
4826 #define ADC1_BASE                 ADC1_BASE_NS
4827 
4828 #define ADC2                      ADC2_NS
4829 #define ADC2_BASE                 ADC2_BASE_NS
4830 
4831 #define ADF1                      ADF1_NS
4832 #define ADF1_BASE                 ADF1_BASE_NS
4833 
4834 #define ADF1_Filter0              ADF1_Filter0_NS
4835 #define ADF1_Filter0_BASE         ADF1_Filter0_BASE_NS
4836 
4837 #define BSEC                      BSEC_NS
4838 #define BSEC_BASE                 BSEC_BASE_NS
4839 
4840 #define CACHEAXI                  CACHEAXI_NS
4841 #define CACHEAXI_BASE             CACHEAXI_BASE_NS
4842 
4843 #define CRC                       CRC_NS
4844 #define CRC_BASE                  CRC_BASE_NS
4845 
4846 #define CRYP                      CRYP_NS
4847 #define CRYP_BASE                 CRYP_BASE_NS
4848 
4849 #define CSI                       CSI_NS
4850 #define CSI_BASE                  CSI_BASE_NS
4851 
4852 #define DBGMCU                    DBGMCU_NS
4853 #define DBGMCU_BASE               DBGMCU_BASE_NS
4854 
4855 #define DCMI                      DCMI_NS
4856 #define DCMI_BASE                 DCMI_BASE_NS
4857 
4858 #define DCMIPP                    DCMIPP_NS
4859 #define DCMIPP_BASE               DCMIPP_BASE_NS
4860 
4861 #define DLYB_SDMMC1               DLYB_SDMMC1_NS
4862 #define DLYB_SDMMC1_BASE          DLYB_SDMMC1_BASE_NS
4863 
4864 #define DLYB_SDMMC2               DLYB_SDMMC2_NS
4865 #define DLYB_SDMMC2_BASE          DLYB_SDMMC2_BASE_NS
4866 
4867 #define DMA2D                     DMA2D_NS
4868 #define DMA2D_BASE                DMA2D_BASE_NS
4869 
4870 #define DTS                       DTS_NS
4871 #define DTS_BASE                  DTS_BASE_NS
4872 
4873 #define DTS_Sensor0               DTS_Sensor0_NS
4874 #define DTS_Sensor0_BASE          DTS_Sensor0_BASE_NS
4875 
4876 #define DTS_Sensor1               DTS_Sensor1_NS
4877 #define DTS_Sensor1_BASE          DTS_Sensor1_BASE_NS
4878 
4879 #define ETH1                      ETH1_NS
4880 #define ETH1_BASE                 ETH1_BASE_NS
4881 
4882 #define EXTI                      EXTI_NS
4883 #define EXTI_BASE                 EXTI_BASE_NS
4884 
4885 #define FDCAN1                    FDCAN1_NS
4886 #define FDCAN1_BASE               FDCAN1_BASE_NS
4887 
4888 #define FDCAN2                    FDCAN2_NS
4889 #define FDCAN2_BASE               FDCAN2_BASE_NS
4890 
4891 #define FDCAN3                    FDCAN3_NS
4892 #define FDCAN3_BASE               FDCAN3_BASE_NS
4893 
4894 #define FDCAN_CCU                 FDCAN_CCU_NS
4895 #define FDCAN_CCU_BASE            FDCAN_CCU_BASE_NS
4896 
4897 #define FDCAN_CONFIG              FDCAN_CONFIG_NS
4898 #define FDCAN_CONFIG_BASE         FDCAN_CONFIG_BASE_NS
4899 
4900 #define FMC_R_BASE                FMC_R_BASE_NS
4901 #define FMC_R_BASE_BASE           FMC_R_BASE_BASE_NS
4902 
4903 #define FMC_Bank1E_R              FMC_Bank1E_R_NS
4904 #define FMC_Bank1E_R_BASE         FMC_Bank1E_R_BASE_NS
4905 
4906 #define FMC_Bank1_R               FMC_Bank1_R_NS
4907 #define FMC_Bank1_Rv              FMC_Bank1_R_BASE_NS
4908 
4909 #define FMC_Bank3_R               FMC_Bank3_R_NS
4910 #define FMC_Bank3_R_BASE          FMC_Bank3_R_BASE_NS
4911 
4912 #define FMC_Bank5_6_R             FMC_Bank5_6_R_NS
4913 #define FMC_Bank5_6_R_BASE        FMC_Bank5_6_R_BASE_NS
4914 
4915 #define FMC_Common_R              FMC_Common_R_NS
4916 #define FMC_Common_R_BASE         FMC_Common_R_BASE_NS
4917 
4918 #define GFXMMU                       GFXMMU_NS
4919 #define GFXMMU_BASE                  GFXMMU_BASE_NS
4920 #define GFXMMU_VIRTUAL_BUFFER0_BASE  GFXMMU_VIRTUAL_BUFFER0_BASE_NS
4921 #define GFXMMU_VIRTUAL_BUFFER1_BASE  GFXMMU_VIRTUAL_BUFFER1_BASE_NS
4922 #define GFXMMU_VIRTUAL_BUFFER2_BASE  GFXMMU_VIRTUAL_BUFFER2_BASE_NS
4923 #define GFXMMU_VIRTUAL_BUFFER3_BASE  GFXMMU_VIRTUAL_BUFFER3_BASE_NS
4924 
4925 #define GFXTIM                    GFXTIM_NS
4926 #define GFXTIM_BASE               GFXTIM_BASE_NS
4927 
4928 #define GPDMA1                    GPDMA1_NS
4929 #define GPDMA1_BASE               GPDMA1_BASE_NS
4930 
4931 #define GPDMA1_Channel0           GPDMA1_Channel0_NS
4932 #define GPDMA1_Channel0_BASE      GPDMA1_Channel0_BASE_NS
4933 
4934 #define GPDMA1_Channel1           GPDMA1_Channel1_NS
4935 #define GPDMA1_Channel1_BASE      GPDMA1_Channel1_BASE_NS
4936 
4937 #define GPDMA1_Channel2           GPDMA1_Channel2_NS
4938 #define GPDMA1_Channel2_BASE      GPDMA1_Channel2_BASE_NS
4939 
4940 #define GPDMA1_Channel3           GPDMA1_Channel3_NS
4941 #define GPDMA1_Channel3_BASE      GPDMA1_Channel3_BASE_NS
4942 
4943 #define GPDMA1_Channel4           GPDMA1_Channel4_NS
4944 #define GPDMA1_Channel4_BASE      GPDMA1_Channel4_BASE_NS
4945 
4946 #define GPDMA1_Channel5           GPDMA1_Channel5_NS
4947 #define GPDMA1_Channel5_BASE      GPDMA1_Channel5_BASE_NS
4948 
4949 #define GPDMA1_Channel6           GPDMA1_Channel6_NS
4950 #define GPDMA1_Channel6_BASE      GPDMA1_Channel6_BASE_NS
4951 
4952 #define GPDMA1_Channel7           GPDMA1_Channel7_NS
4953 #define GPDMA1_Channel7_BASE      GPDMA1_Channel7_BASE_NS
4954 
4955 #define GPDMA1_Channel8           GPDMA1_Channel8_NS
4956 #define GPDMA1_Channel8_BASE      GPDMA1_Channel8_BASE_NS
4957 
4958 #define GPDMA1_Channel9           GPDMA1_Channel9_NS
4959 #define GPDMA1_Channel9_BASE      GPDMA1_Channel9_BASE_NS
4960 
4961 #define GPDMA1_Channel10          GPDMA1_Channel10_NS
4962 #define GPDMA1_Channel10_BASE     GPDMA1_Channel10_BASE_NS
4963 
4964 #define GPDMA1_Channel11          GPDMA1_Channel11_NS
4965 #define GPDMA1_Channel11_BASE     GPDMA1_Channel11_BASE_NS
4966 
4967 #define GPDMA1_Channel12          GPDMA1_Channel12_NS
4968 #define GPDMA1_Channel12_BASE     GPDMA1_Channel12_BASE_NS
4969 
4970 #define GPDMA1_Channel13          GPDMA1_Channel13_NS
4971 #define GPDMA1_Channel13_BASE     GPDMA1_Channel13_BASE_NS
4972 
4973 #define GPDMA1_Channel14          GPDMA1_Channel14_NS
4974 #define GPDMA1_Channel14_BASE     GPDMA1_Channel14_BASE_NS
4975 
4976 #define GPDMA1_Channel15          GPDMA1_Channel15_NS
4977 #define GPDMA1_Channel15_BASE     GPDMA1_Channel15_BASE_NS
4978 
4979 #define GPIOA                     GPIOA_NS
4980 #define GPIOA_BASE                GPIOA_BASE_NS
4981 
4982 #define GPIOB                     GPIOB_NS
4983 #define GPIOB_BASE                GPIOB_BASE_NS
4984 
4985 #define GPIOC                     GPIOC_NS
4986 #define GPIOC_BASE                GPIOC_BASE_NS
4987 
4988 #define GPIOD                     GPIOD_NS
4989 #define GPIOD_BASE                GPIOD_BASE_NS
4990 
4991 #define GPIOE                     GPIOE_NS
4992 #define GPIOE_BASE                GPIOE_BASE_NS
4993 
4994 #define GPIOF                     GPIOF_NS
4995 #define GPIOF_BASE                GPIOF_BASE_NS
4996 
4997 #define GPIOG                     GPIOG_NS
4998 #define GPIOG_BASE                GPIOG_BASE_NS
4999 
5000 #define GPIOH                     GPIOH_NS
5001 #define GPIOH_BASE                GPIOH_BASE_NS
5002 
5003 #define GPION                     GPION_NS
5004 #define GPION_BASE                GPION_BASE_NS
5005 
5006 #define GPIOO                     GPIOO_NS
5007 #define GPIOO_BASE                GPIOO_BASE_NS
5008 
5009 #define GPIOP                     GPIOP_NS
5010 #define GPIOP_BASE                GPIOP_BASE_NS
5011 
5012 #define GPIOQ                     GPIOQ_NS
5013 #define GPIOQ_BASE                GPIOQ_BASE_NS
5014 
5015 #define GPU2D                     GPU2D_BASE_NS
5016 #define GPU2D_BASE                GPU2D_BASE_NS
5017 
5018 #define HASH                      HASH_NS
5019 #define HASH_BASE                 HASH_BASE_NS
5020 
5021 #define HASH_DIGEST               HASH_DIGEST_NS
5022 #define HASH_DIGEST_BASE          HASH_DIGEST_BASE_NS
5023 
5024 #define HPDMA1                    HPDMA1_NS
5025 #define HPDMA1_BASE               HPDMA1_BASE_NS
5026 
5027 #define HPDMA1_Channel0           HPDMA1_Channel0_NS
5028 #define HPDMA1_Channel0_BASE      HPDMA1_Channel0_BASE_NS
5029 
5030 #define HPDMA1_Channel1           HPDMA1_Channel1_NS
5031 #define HPDMA1_Channel1_BASE      HPDMA1_Channel1_BASE_NS
5032 
5033 #define HPDMA1_Channel2           HPDMA1_Channel2_NS
5034 #define HPDMA1_Channel2_BASE      HPDMA1_Channel2_BASE_NS
5035 
5036 #define HPDMA1_Channel3           HPDMA1_Channel3_NS
5037 #define HPDMA1_Channel3_BASE      HPDMA1_Channel3_BASE_NS
5038 
5039 #define HPDMA1_Channel4           HPDMA1_Channel4_NS
5040 #define HPDMA1_Channel4_BASE      HPDMA1_Channel4_BASE_NS
5041 
5042 #define HPDMA1_Channel5           HPDMA1_Channel5_NS
5043 #define HPDMA1_Channel5_BASE      HPDMA1_Channel5_BASE_NS
5044 
5045 #define HPDMA1_Channel6           HPDMA1_Channel6_NS
5046 #define HPDMA1_Channel6_BASE      HPDMA1_Channel6_BASE_NS
5047 
5048 #define HPDMA1_Channel7           HPDMA1_Channel7_NS
5049 #define HPDMA1_Channel7_BASE      HPDMA1_Channel7_BASE_NS
5050 
5051 #define HPDMA1_Channel8           HPDMA1_Channel8_NS
5052 #define HPDMA1_Channel8_BASE      HPDMA1_Channel8_BASE_NS
5053 
5054 #define HPDMA1_Channel9           HPDMA1_Channel9_NS
5055 #define HPDMA1_Channel9_BASE      HPDMA1_Channel9_BASE_NS
5056 
5057 #define HPDMA1_Channel10          HPDMA1_Channel10_NS
5058 #define HPDMA1_Channel10_BASE     HPDMA1_Channel10_BASE_NS
5059 
5060 #define HPDMA1_Channel11          HPDMA1_Channel11_NS
5061 #define HPDMA1_Channel11_BASE     HPDMA1_Channel11_BASE_NS
5062 
5063 #define HPDMA1_Channel12          HPDMA1_Channel12_NS
5064 #define HPDMA1_Channel12_BASE     HPDMA1_Channel12_BASE_NS
5065 
5066 #define HPDMA1_Channel13          HPDMA1_Channel13_NS
5067 #define HPDMA1_Channel13_BASE     HPDMA1_Channel13_BASE_NS
5068 
5069 #define HPDMA1_Channel14          HPDMA1_Channel14_NS
5070 #define HPDMA1_Channel14_BASE     HPDMA1_Channel14_BASE_NS
5071 
5072 #define HPDMA1_Channel15          HPDMA1_Channel15_NS
5073 #define HPDMA1_Channel15_BASE     HPDMA1_Channel15_BASE_NS
5074 
5075 #define I2C1                      I2C1_NS
5076 #define I2C1_BASE                 I2C1_BASE_NS
5077 
5078 #define I2C2                      I2C2_NS
5079 #define I2C2_BASE                 I2C2_BASE_NS
5080 
5081 #define I2C3                      I2C3_NS
5082 #define I2C3_BASE                 I2C3_BASE_NS
5083 
5084 #define I2C4                      I2C4_NS
5085 #define I2C4_BASE                 I2C4_BASE_NS
5086 
5087 #define I3C1                      I3C1_NS
5088 #define I3C1_BASE                 I3C1_BASE_NS
5089 
5090 #define I3C2                      I3C2_NS
5091 #define I3C2_BASE                 I3C2_BASE_NS
5092 
5093 #define ICACHE                    ICACHE_NS
5094 #define ICACHE_BASE               ICACHE_BASE_NS
5095 
5096 #define IWDG                      IWDG_NS
5097 #define IWDG_BASE                 IWDG_BASE_NS
5098 
5099 #define JPEG                      JPEG_NS
5100 #define JPEG_BASE                 JPEG_BASE_NS
5101 
5102 #define LPTIM1                    LPTIM1_NS
5103 #define LPTIM1_BASE               LPTIM1_BASE_NS
5104 
5105 #define LPTIM2                    LPTIM2_NS
5106 #define LPTIM2_BASE               LPTIM2_BASE_NS
5107 
5108 #define LPTIM3                    LPTIM3_NS
5109 #define LPTIM3_BASE               LPTIM3_BASE_NS
5110 
5111 #define LPTIM4                    LPTIM4_NS
5112 #define LPTIM4_BASE               LPTIM4_BASE_NS
5113 
5114 #define LPTIM5                    LPTIM5_NS
5115 #define LPTIM5_BASE               LPTIM5_BASE_NS
5116 
5117 #define LPUART1                   LPUART1_NS
5118 #define LPUART1_BASE              LPUART1_BASE_NS
5119 
5120 #define LTDC                      LTDC_NS
5121 #define LTDC_BASE                 LTDC_BASE_NS
5122 
5123 #define LTDC_Layer1               LTDC_Layer1_NS
5124 #define LTDC_Layer1_BASE          LTDC_Layer1_BASE_NS
5125 
5126 #define LTDC_Layer2               LTDC_Layer2_NS
5127 #define LTDC_Layer2_BASE          LTDC_Layer2_BASE_NS
5128 
5129 #define MCE1                      MCE1_NS
5130 #define MCE1_BASE                 MCE1_BASE_NS
5131 
5132 #define MCE1_REGION1              MCE1_REGION1_NS
5133 #define MCE1_REGION1_BASE         MCE1_REGION1_BASE_NS
5134 
5135 #define MCE1_REGION2              MCE1_REGION2_NS
5136 #define MCE1_REGION2_BASE         MCE1_REGION2_BASE_NS
5137 
5138 #define MCE1_REGION3              MCE1_REGION3_NS
5139 #define MCE1_REGION3_BASE         MCE1_REGION3_BASE_NS
5140 
5141 #define MCE1_REGION4              MCE1_REGION4_NS
5142 #define MCE1_REGION4_BASE         MCE1_REGION4_BASE_NS
5143 
5144 #define MCE1_CONTEXT1             MCE1_CONTEXT1_NS
5145 #define MCE1_CONTEXT1_BASE        MCE1_CONTEXT1_BASE_NS
5146 
5147 #define MCE1_CONTEXT2             MCE1_CONTEXT2_NS
5148 #define MCE1_CONTEXT2_BASE        MCE1_CONTEXT2_BASE_NS
5149 
5150 #define MCE2                      MCE2_NS
5151 #define MCE2_BASE                 MCE2_BASE_NS
5152 
5153 #define MCE2_REGION1              MCE2_REGION1_NS
5154 #define MCE2_REGION1_BASE         MCE2_REGION1_BASE_NS
5155 
5156 #define MCE2_REGION2              MCE2_REGION2_NS
5157 #define MCE2_REGION2_BASE         MCE2_REGION2_BASE_NS
5158 
5159 #define MCE2_REGION3              MCE2_REGION3_NS
5160 #define MCE2_REGION3_BASE         MCE2_REGION3_BASE_NS
5161 
5162 #define MCE2_REGION4              MCE2_REGION4_NS
5163 #define MCE2_REGION4_BASE         MCE2_REGION4_BASE_NS
5164 
5165 #define MCE2_CONTEXT1             MCE2_CONTEXT1_NS
5166 #define MCE2_CONTEXT1_BASE        MCE2_CONTEXT1_BASE_NS
5167 
5168 #define MCE2_CONTEXT2             MCE2_CONTEXT2_NS
5169 #define MCE2_CONTEXT2_BASE        MCE2_CONTEXT2_BASE_NS
5170 
5171 #define MCE3                      MCE3_NS
5172 #define MCE3_BASE                 MCE3_BASE_NS
5173 
5174 #define MCE3_REGION1              MCE3_REGION1_NS
5175 #define MCE3_REGION1_BASE         MCE3_REGION1_BASE_NS
5176 
5177 #define MCE3_REGION2              MCE3_REGION2_NS
5178 #define MCE3_REGION2_BASE         MCE3_REGION2_BASE_NS
5179 
5180 #define MCE3_REGION3              MCE3_REGION3_NS
5181 #define MCE3_REGION3_BASE         MCE3_REGION3_BASE_NS
5182 
5183 #define MCE3_REGION4              MCE3_REGION4_NS
5184 #define MCE3_REGION4_BASE         MCE3_REGION4_BASE_NS
5185 
5186 #define MCE3_CONTEXT1             MCE3_CONTEXT1_NS
5187 #define MCE3_CONTEXT1_BASE        MCE3_CONTEXT1_BASE_NS
5188 
5189 #define MCE3_CONTEXT2             MCE3_CONTEXT2_NS
5190 #define MCE3_CONTEXT2_BASE        MCE3_CONTEXT2_BASE_NS
5191 
5192 #define MCE4                      MCE4_NS
5193 #define MCE4_BASE                 MCE4_BASE_NS
5194 
5195 #define MCE4_REGION1              MCE4_REGION1_NS
5196 #define MCE4_REGION1_BASE         MCE4_REGION1_BASE_NS
5197 
5198 #define MCE4_REGION2              MCE4_REGION2_NS
5199 #define MCE4_REGION2_BASE         MCE4_REGION2_BASE_NS
5200 
5201 #define MCE4_REGION3              MCE4_REGION3_NS
5202 #define MCE4_REGION3_BASE         MCE4_REGION3_BASE_NS
5203 
5204 #define MCE4_REGION4              MCE4_REGION4_NS
5205 #define MCE4_REGION4_BASE         MCE4_REGION4_BASE_NS
5206 
5207 #define MCE4_CONTEXT1             MCE4_CONTEXT1_NS
5208 #define MCE4_CONTEXT1_BASE        MCE4_CONTEXT1_BASE_NS
5209 
5210 #define MCE4_CONTEXT2             MCE4_CONTEXT2_NS
5211 #define MCE4_CONTEXT2_BASE        MCE4_CONTEXT2_BASE_NS
5212 
5213 #define MDF1                      MDF1_NS
5214 #define MDF1_BASE                 MDF1_BASE_NS
5215 
5216 #define MDF1_Filter0              MDF1_Filter0_NS
5217 #define MDF1_Filter0_BASE         MDF1_Filter0_BASE_NS
5218 
5219 #define MDF1_Filter1              MDF1_Filter1_NS
5220 #define MDF1_Filter1_BASE         MDF1_Filter1_BASE_NS
5221 
5222 #define MDF1_Filter2              MDF1_Filter2_NS
5223 #define MDF1_Filter2_BASE         MDF1_Filter2_BASE_NS
5224 
5225 #define MDF1_Filter3              MDF1_Filter3_NS
5226 #define MDF1_Filter3_BASE         MDF1_Filter3_BASE_NS
5227 
5228 #define MDF1_Filter4              MDF1_Filter4_NS
5229 #define MDF1_Filter4_BASE         MDF1_Filter4_BASE_NS
5230 
5231 #define MDF1_Filter5              MDF1_Filter5_NS
5232 #define MDF1_Filter5_BASE         MDF1_Filter5_BASE_NS
5233 
5234 #define MDIOS                     MDIOS_NS
5235 #define MDIOS_BASE                MDIOS_BASE_NS
5236 
5237 #define NPU_PRESENT
5238 #define NPU_BASE                  NPU_BASE_NS
5239 
5240 #define PKA                       PKA_NS
5241 #define PKA_BASE                  PKA_BASE_NS
5242 
5243 #define PSSI                      PSSI_NS
5244 #define PSSI_BASE                 PSSI_BASE_NS
5245 
5246 #define PWR                       PWR_NS
5247 #define PWR_BASE                  PWR_BASE_NS
5248 
5249 #define RAMCFG                    RAMCFG_NS
5250 #define RAMCFG_BASE               RAMCFG_BASE_NS
5251 
5252 #define RAMCFG_SRAM1_AXI          RAMCFG_SRAM1_AXI_NS
5253 #define RAMCFG_SRAM1_AXI_BASE     RAMCFG_SRAM1_AXI_BASE_NS
5254 
5255 #define RAMCFG_SRAM2_AXI          RAMCFG_SRAM2_AXI_NS
5256 #define RAMCFG_SRAM2_AXI_BASE     RAMCFG_SRAM2_AXI_BASE_NS
5257 
5258 #define RAMCFG_SRAM3_AXI          RAMCFG_SRAM3_AXI_NS
5259 #define RAMCFG_SRAM3_AXI_BASE     RAMCFG_SRAM3_AXI_BASE_NS
5260 
5261 #define RAMCFG_SRAM4_AXI          RAMCFG_SRAM4_AXI_NS
5262 #define RAMCFG_SRAM4_AXI_BASE     RAMCFG_SRAM4_AXI_BASE_NS
5263 
5264 #define RAMCFG_SRAM5_AXI          RAMCFG_SRAM5_AXI_NS
5265 #define RAMCFG_SRAM5_AXI_BASE     RAMCFG_SRAM5_AXI_BASE_NS
5266 
5267 #define RAMCFG_SRAM6_AXI          RAMCFG_SRAM6_AXI_NS
5268 #define RAMCFG_SRAM6_AXI_BASE     RAMCFG_SRAM6_AXI_BASE_NS
5269 
5270 #define RAMCFG_SRAM1_AHB          RAMCFG_SRAM1_AHB_NS
5271 #define RAMCFG_SRAM1_AHB_BASE     RAMCFG_SRAM1_AHB_BASE_NS
5272 
5273 #define RAMCFG_SRAM2_AHB          RAMCFG_SRAM2_AHB_NS
5274 #define RAMCFG_SRAM2_AHB_BASE     RAMCFG_SRAM2_AHB_BASE_NS
5275 
5276 #define RAMCFG_VENC_RAM           RAMCFG_VENC_RAM_NS
5277 #define RAMCFG_VENC_RAM_BASE      RAMCFG_VENC_RAM_BASE_NS
5278 
5279 #define RAMCFG_BKPSRAM            RAMCFG_BKPSRAM_NS
5280 #define RAMCFG_BKPSRAM_BASE       RAMCFG_BKPSRAM_BASE_NS
5281 
5282 #define RAMCFG_FLEXRAM            RAMCFG_FLEXRAM_NS
5283 #define RAMCFG_FLEXRAM_BASE       RAMCFG_FLEXRAM_BASE_NS
5284 
5285 #define RCC                       RCC_NS
5286 #define RCC_BASE                  RCC_BASE_NS
5287 
5288 #define RIFSC                     RIFSC_NS
5289 #define RIFSC_BASE                RIFSC_BASE_NS
5290 
5291 #define RISAF1                    RISAF1_NS
5292 #define RISAF1_BASE               RISAF1_BASE_NS
5293 
5294 #define RISAF2                    RISAF2_NS
5295 #define RISAF2_BASE               RISAF2_BASE_NS
5296 
5297 #define RISAF3                    RISAF3_NS
5298 #define RISAF3_BASE               RISAF3_BASE_NS
5299 
5300 #define RISAF4                    RISAF4_NS
5301 #define RISAF4_BASE               RISAF4_BASE_NS
5302 
5303 #define RISAF5                    RISAF5_NS
5304 #define RISAF5_BASE               RISAF5_BASE_NS
5305 
5306 #define RISAF6                    RISAF6_NS
5307 #define RISAF6_BASE               RISAF6_BASE_NS
5308 
5309 #define RISAF7                    RISAF7_NS
5310 #define RISAF7_BASE               RISAF7_BASE_NS
5311 
5312 #define RISAF8                    RISAF8_NS
5313 #define RISAF8_BASE               RISAF8_BASE_NS
5314 
5315 #define RISAF9                    RISAF9_NS
5316 #define RISAF9_BASE               RISAF9_BASE_NS
5317 
5318 #define RISAF11                   RISAF11_NS
5319 #define RISAF11_BASE              RISAF11_BASE_NS
5320 
5321 #define RISAF12                   RISAF12_NS
5322 #define RISAF12_BASE              RISAF12_BASE_NS
5323 
5324 #define RISAF13                   RISAF13_NS
5325 #define RISAF13_BASE              RISAF13_BASE_NS
5326 
5327 #define RISAF14                   RISAF14_NS
5328 #define RISAF14_BASE              RISAF14_BASE_NS
5329 
5330 #define RISAF15                   RISAF15_NS
5331 #define RISAF15_BASE              RISAF15_BASE_NS
5332 
5333 #define RISAF21                   RISAF21_NS
5334 #define RISAF21_BASE              RISAF21_BASE_NS
5335 
5336 #define RISAF22                   RISAF22_NS
5337 #define RISAF22_BASE              RISAF22_BASE_NS
5338 
5339 #define RISAF23                   RISAF23_NS
5340 #define RISAF23_BASE              RISAF23_BASE_NS
5341 
5342 #define RNG                       RNG_NS
5343 #define RNG_BASE                  RNG_BASE_NS
5344 
5345 #define RTC                       RTC_NS
5346 #define RTC_BASE                  RTC_BASE_NS
5347 
5348 #define SAES                      SAES_NS
5349 #define SAES_BASE                 SAES_BASE_NS
5350 
5351 #define SAI1                      SAI1_NS
5352 #define SAI1_BASE                 SAI1_BASE_NS
5353 
5354 #define SAI1_Block_A              SAI1_Block_A_NS
5355 #define SAI1_Block_A_BASE         SAI1_Block_A_BASE_NS
5356 
5357 #define SAI1_Block_B              SAI1_Block_B_NS
5358 #define SAI1_Block_B_BASE         SAI1_Block_B_BASE_NS
5359 
5360 #define SAI2                      SAI2_NS
5361 #define SAI2_BASE                 SAI2_BASE_NS
5362 
5363 #define SAI2_Block_A              SAI2_Block_A_NS
5364 #define SAI2_Block_A_BASE         SAI2_Block_A_BASE_NS
5365 
5366 #define SAI2_Block_B              SAI2_Block_B_NS
5367 #define SAI2_Block_B_BASE         SAI2_Block_B_BASE_NS
5368 
5369 #define SDMMC1                    SDMMC1_NS
5370 #define SDMMC1_BASE               SDMMC1_BASE_NS
5371 
5372 #define SDMMC2                    SDMMC2_NS
5373 #define SDMMC2_BASE               SDMMC2_BASE_NS
5374 
5375 #define SPDIFRX                   SPDIFRX_NS
5376 #define SPDIFRX_BASE              SPDIFRX_BASE_NS
5377 
5378 #define SPI1                      SPI1_NS
5379 #define SPI1_BASE                 SPI1_BASE_NS
5380 
5381 #define SPI2                      SPI2_NS
5382 #define SPI2_BASE                 SPI2_BASE_NS
5383 
5384 #define SPI3                      SPI3_NS
5385 #define SPI3_BASE                 SPI3_BASE_NS
5386 
5387 #define SPI4                      SPI4_NS
5388 #define SPI4_BASE                 SPI4_BASE_NS
5389 
5390 #define SPI5                      SPI5_NS
5391 #define SPI5_BASE                 SPI5_BASE_NS
5392 
5393 #define SPI6                      SPI6_NS
5394 #define SPI6_BASE                 SPI6_BASE_NS
5395 
5396 #define SRAMCAN_BASE              SRAMCAN_BASE_NS
5397 
5398 #define SYSCFG                    SYSCFG_NS
5399 #define SYSCFG_BASE               SYSCFG_BASE_NS
5400 
5401 #define TAMP                      TAMP_NS
5402 #define TAMP_BASE                 TAMP_BASE_NS
5403 
5404 #define TIM1                      TIM1_NS
5405 #define TIM1_BASE                 TIM1_BASE_NS
5406 
5407 #define TIM2                      TIM2_NS
5408 #define TIM2_BASE                 TIM2_BASE_NS
5409 
5410 #define TIM3                      TIM3_NS
5411 #define TIM3_BASE                 TIM3_BASE_NS
5412 
5413 #define TIM4                      TIM4_NS
5414 #define TIM4_BASE                 TIM4_BASE_NS
5415 
5416 #define TIM5                      TIM5_NS
5417 #define TIM5_BASE                 TIM5_BASE_NS
5418 
5419 #define TIM6                      TIM6_NS
5420 #define TIM6_BASE                 TIM6_BASE_NS
5421 
5422 #define TIM7                      TIM7_NS
5423 #define TIM7_BASE                 TIM7_BASE_NS
5424 
5425 #define TIM8                      TIM8_NS
5426 #define TIM8_BASE                 TIM8_BASE_NS
5427 
5428 #define TIM9                      TIM9_NS
5429 #define TIM9_BASE                 TIM9_BASE_NS
5430 
5431 #define TIM10                     TIM10_NS
5432 #define TIM10_BASE                TIM10_BASE_NS
5433 
5434 #define TIM11                     TIM11_NS
5435 #define TIM11_BASE                TIM11_BASE_NS
5436 
5437 #define TIM12                     TIM12_NS
5438 #define TIM12_BASE                TIM12_BASE_NS
5439 
5440 #define TIM13                     TIM13_NS
5441 #define TIM13_BASE                TIM13_BASE_NS
5442 
5443 #define TIM14                     TIM14_NS
5444 #define TIM14_BASE                TIM14_BASE_NS
5445 
5446 #define TIM15                     TIM15_NS
5447 #define TIM15_BASE                TIM15_BASE_NS
5448 
5449 #define TIM16                     TIM16_NS
5450 #define TIM16_BASE                TIM16_BASE_NS
5451 
5452 #define TIM17                     TIM17_NS
5453 #define TIM17_BASE                TIM17_BASE_NS
5454 
5455 #define TIM18                     TIM18_NS
5456 #define TIM18_BASE                TIM18_BASE_NS
5457 
5458 #define UART4                     UART4_NS
5459 #define UART4_BASE                UART4_BASE_NS
5460 
5461 #define UART5                     UART5_NS
5462 #define UART5_BASE                UART5_BASE_NS
5463 
5464 #define UART7                     UART7_NS
5465 #define UART7_BASE                UART7_BASE_NS
5466 
5467 #define UART8                     UART8_NS
5468 #define UART8_BASE                UART8_BASE_NS
5469 
5470 #define UART9                     UART9_NS
5471 #define UART9_BASE                UART9_BASE_NS
5472 
5473 #define UCPD1                     UCPD1_NS
5474 #define UCPD1_BASE                UCPD1_BASE_NS
5475 
5476 #define USART1                    USART1_NS
5477 #define USART1_BASE               USART1_BASE_NS
5478 
5479 #define USART2                    USART2_NS
5480 #define USART2_BASE               USART2_BASE_NS
5481 
5482 #define USART3                    USART3_NS
5483 #define USART3_BASE               USART3_BASE_NS
5484 
5485 #define USART6                    USART6_NS
5486 #define USART6_BASE               USART6_BASE_NS
5487 
5488 #define USART10                   USART10_NS
5489 #define USART10_BASE              USART10_BASE_NS
5490 
5491 #define USB1_OTG_HS               USB1_OTG_HS_NS
5492 #define USB1_OTG_HS_BASE          USB1_OTG_HS_BASE_NS
5493 
5494 #define USB2_OTG_HS               USB2_OTG_HS_NS
5495 #define USB2_OTG_HS_BASE          USB2_OTG_HS_BASE_NS
5496 
5497 #define USB1_HS_PHYC              USB1_HS_PHYC_NS
5498 #define USB1_HS_PHYC_BASE         USB1_HS_PHYC_BASE_NS
5499 
5500 #define USB2_HS_PHYC              USB2_HS_PHYC_NS
5501 #define USB2_HS_PHYC_BASE         USB2_HS_PHYC_BASE_NS
5502 
5503 #define VENC                      VENC_NS
5504 #define VENC_BASE                 VENC_BASE_NS
5505 
5506 #define VREFBUF                   VREFBUF_NS
5507 #define VREFBUF_BASE              VREFBUF_BASE_NS
5508 
5509 #define WWDG                      WWDG_NS
5510 #define WWDG_BASE                 WWDG_BASE_NS
5511 
5512 #define XSPI1                     XSPI1_NS
5513 
5514 #define XSPI2                     XSPI2_NS
5515 
5516 #define XSPI3                     XSPI3_NS
5517 
5518 #define XSPIM                     XSPIM_NS
5519 #define XSPIM_BASE                XSPIM_BASE_NS
5520 
5521 /*!< Unique device ID register base address */
5522 #define UID_BASE                  UID_BASE_NS
5523 
5524 /*!< Revision ID base address */
5525 #define REVID_BASE                REVID_BASE_NS
5526 
5527 #endif
5528 
5529 /** @} */ /* End of group STM32N6xx_Peripheral_declaration */
5530 
5531 /** @addtogroup STM32N6xx_Peripheral_Timing_Definition
5532   * @{
5533   */
5534 
5535 #define LSI_STARTUP_TIME                16000U /*!< LSI Maximum startup time in us : 4 cycles @ 250 Hz = 16 ms */
5536 
5537 /** @} */ /* End of group STM32N6xx_Peripheral_Timing_Definition */
5538 
5539 /** @addtogroup Peripheral_Registers_Bits_Definition
5540   * @{
5541   */
5542 
5543 /******************************************************************************/
5544 /*                                                                            */
5545 /*                        Analog to Digital Converter (ADC)                   */
5546 /*                                                                            */
5547 /******************************************************************************/
5548 
5549 /* Specific device feature definitions */
5550 #define ADC_MULTIMODE_SUPPORT         /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
5551 
5552 /********************  Bit definition for ADC_ISR register  *******************/
5553 #define ADC_ISR_ADRDY_Pos              (0U)
5554 #define ADC_ISR_ADRDY_Msk              (0x1UL << ADC_ISR_ADRDY_Pos)            /*!< 0x00000001 */
5555 #define ADC_ISR_ADRDY                  ADC_ISR_ADRDY_Msk                       /*!< ADC ready flag */
5556 #define ADC_ISR_EOSMP_Pos              (1U)
5557 #define ADC_ISR_EOSMP_Msk              (0x1UL << ADC_ISR_EOSMP_Pos)            /*!< 0x00000002 */
5558 #define ADC_ISR_EOSMP                  ADC_ISR_EOSMP_Msk                       /*!< ADC group regular end of sampling flag */
5559 #define ADC_ISR_EOC_Pos                (2U)
5560 #define ADC_ISR_EOC_Msk                (0x1UL << ADC_ISR_EOC_Pos)              /*!< 0x00000004 */
5561 #define ADC_ISR_EOC                    ADC_ISR_EOC_Msk                         /*!< ADC group regular end of unitary conversion flag */
5562 #define ADC_ISR_EOS_Pos                (3U)
5563 #define ADC_ISR_EOS_Msk                (0x1UL << ADC_ISR_EOS_Pos)              /*!< 0x00000008 */
5564 #define ADC_ISR_EOS                    ADC_ISR_EOS_Msk                         /*!< ADC group regular end of sequence conversions flag */
5565 #define ADC_ISR_OVR_Pos                (4U)
5566 #define ADC_ISR_OVR_Msk                (0x1UL << ADC_ISR_OVR_Pos)              /*!< 0x00000010 */
5567 #define ADC_ISR_OVR                    ADC_ISR_OVR_Msk                         /*!< ADC group regular overrun flag */
5568 #define ADC_ISR_JEOC_Pos               (5U)
5569 #define ADC_ISR_JEOC_Msk               (0x1UL << ADC_ISR_JEOC_Pos)             /*!< 0x00000020 */
5570 #define ADC_ISR_JEOC                   ADC_ISR_JEOC_Msk                        /*!< ADC group injected end of unitary conversion flag */
5571 #define ADC_ISR_JEOS_Pos               (6U)
5572 #define ADC_ISR_JEOS_Msk               (0x1UL << ADC_ISR_JEOS_Pos)             /*!< 0x00000040 */
5573 #define ADC_ISR_JEOS                   ADC_ISR_JEOS_Msk                        /*!< ADC group injected end of sequence conversions flag */
5574 #define ADC_ISR_AWD1_Pos               (7U)
5575 #define ADC_ISR_AWD1_Msk               (0x1UL << ADC_ISR_AWD1_Pos)             /*!< 0x00000080 */
5576 #define ADC_ISR_AWD1                   ADC_ISR_AWD1_Msk                        /*!< ADC analog watchdog 1 flag */
5577 #define ADC_ISR_AWD2_Pos               (8U)
5578 #define ADC_ISR_AWD2_Msk               (0x1UL << ADC_ISR_AWD2_Pos)             /*!< 0x00000100 */
5579 #define ADC_ISR_AWD2                   ADC_ISR_AWD2_Msk                        /*!< ADC analog watchdog 2 flag */
5580 #define ADC_ISR_AWD3_Pos               (9U)
5581 #define ADC_ISR_AWD3_Msk               (0x1UL << ADC_ISR_AWD3_Pos)             /*!< 0x00000200 */
5582 #define ADC_ISR_AWD3                   ADC_ISR_AWD3_Msk                        /*!< ADC analog watchdog 3 flag */
5583 
5584 /********************  Bit definition for ADC_IER register  *******************/
5585 #define ADC_IER_ADRDYIE_Pos            (0U)
5586 #define ADC_IER_ADRDYIE_Msk            (0x1UL << ADC_IER_ADRDYIE_Pos)          /*!< 0x00000001 */
5587 #define ADC_IER_ADRDYIE                ADC_IER_ADRDYIE_Msk                     /*!< ADC ready interrupt */
5588 #define ADC_IER_EOSMPIE_Pos            (1U)
5589 #define ADC_IER_EOSMPIE_Msk            (0x1UL << ADC_IER_EOSMPIE_Pos)          /*!< 0x00000002 */
5590 #define ADC_IER_EOSMPIE                ADC_IER_EOSMPIE_Msk                     /*!< ADC group regular end of sampling interrupt */
5591 #define ADC_IER_EOCIE_Pos              (2U)
5592 #define ADC_IER_EOCIE_Msk              (0x1UL << ADC_IER_EOCIE_Pos)            /*!< 0x00000004 */
5593 #define ADC_IER_EOCIE                  ADC_IER_EOCIE_Msk                       /*!< ADC group regular end of unitary conversion interrupt */
5594 #define ADC_IER_EOSIE_Pos              (3U)
5595 #define ADC_IER_EOSIE_Msk              (0x1UL << ADC_IER_EOSIE_Pos)            /*!< 0x00000008 */
5596 #define ADC_IER_EOSIE                  ADC_IER_EOSIE_Msk                       /*!< ADC group regular end of sequence conversions interrupt */
5597 #define ADC_IER_OVRIE_Pos              (4U)
5598 #define ADC_IER_OVRIE_Msk              (0x1UL << ADC_IER_OVRIE_Pos)            /*!< 0x00000010 */
5599 #define ADC_IER_OVRIE                  ADC_IER_OVRIE_Msk                       /*!< ADC group regular overrun interrupt */
5600 #define ADC_IER_JEOCIE_Pos             (5U)
5601 #define ADC_IER_JEOCIE_Msk             (0x1UL << ADC_IER_JEOCIE_Pos)           /*!< 0x00000020 */
5602 #define ADC_IER_JEOCIE                 ADC_IER_JEOCIE_Msk                      /*!< ADC group injected end of unitary conversion interrupt */
5603 #define ADC_IER_JEOSIE_Pos             (6U)
5604 #define ADC_IER_JEOSIE_Msk             (0x1UL << ADC_IER_JEOSIE_Pos)           /*!< 0x00000040 */
5605 #define ADC_IER_JEOSIE                 ADC_IER_JEOSIE_Msk                      /*!< ADC group injected end of sequence conversions interrupt */
5606 #define ADC_IER_AWD1IE_Pos             (7U)
5607 #define ADC_IER_AWD1IE_Msk             (0x1UL << ADC_IER_AWD1IE_Pos)           /*!< 0x00000080 */
5608 #define ADC_IER_AWD1IE                 ADC_IER_AWD1IE_Msk                      /*!< ADC analog watchdog 1 interrupt */
5609 #define ADC_IER_AWD2IE_Pos             (8U)
5610 #define ADC_IER_AWD2IE_Msk             (0x1UL << ADC_IER_AWD2IE_Pos)           /*!< 0x00000100 */
5611 #define ADC_IER_AWD2IE                 ADC_IER_AWD2IE_Msk                      /*!< ADC analog watchdog 2 interrupt */
5612 #define ADC_IER_AWD3IE_Pos             (9U)
5613 #define ADC_IER_AWD3IE_Msk             (0x1UL << ADC_IER_AWD3IE_Pos)           /*!< 0x00000200 */
5614 #define ADC_IER_AWD3IE                 ADC_IER_AWD3IE_Msk                      /*!< ADC analog watchdog 3 interrupt */
5615 
5616 /********************  Bit definition for ADC_CR register  ********************/
5617 #define ADC_CR_ADEN_Pos                (0U)
5618 #define ADC_CR_ADEN_Msk                (0x1UL << ADC_CR_ADEN_Pos)              /*!< 0x00000001 */
5619 #define ADC_CR_ADEN                    ADC_CR_ADEN_Msk                         /*!< ADC enable */
5620 #define ADC_CR_ADDIS_Pos               (1U)
5621 #define ADC_CR_ADDIS_Msk               (0x1UL << ADC_CR_ADDIS_Pos)             /*!< 0x00000002 */
5622 #define ADC_CR_ADDIS                   ADC_CR_ADDIS_Msk                        /*!< ADC disable */
5623 #define ADC_CR_ADSTART_Pos             (2U)
5624 #define ADC_CR_ADSTART_Msk             (0x1UL << ADC_CR_ADSTART_Pos)           /*!< 0x00000004 */
5625 #define ADC_CR_ADSTART                 ADC_CR_ADSTART_Msk                      /*!< ADC group regular conversion start */
5626 #define ADC_CR_JADSTART_Pos            (3U)
5627 #define ADC_CR_JADSTART_Msk            (0x1UL << ADC_CR_JADSTART_Pos)          /*!< 0x00000008 */
5628 #define ADC_CR_JADSTART                ADC_CR_JADSTART_Msk                     /*!< ADC group injected conversion start */
5629 #define ADC_CR_ADSTP_Pos               (4U)
5630 #define ADC_CR_ADSTP_Msk               (0x1UL << ADC_CR_ADSTP_Pos)             /*!< 0x00000010 */
5631 #define ADC_CR_ADSTP                   ADC_CR_ADSTP_Msk                        /*!< ADC group regular conversion stop */
5632 #define ADC_CR_JADSTP_Pos              (5U)
5633 #define ADC_CR_JADSTP_Msk              (0x1UL << ADC_CR_JADSTP_Pos)            /*!< 0x00000020 */
5634 #define ADC_CR_JADSTP                  ADC_CR_JADSTP_Msk                       /*!< ADC group injected conversion stop */
5635 #define ADC_CR_DEEPPWD_Pos             (29U)
5636 #define ADC_CR_DEEPPWD_Msk             (0x1UL << ADC_CR_DEEPPWD_Pos)           /*!< 0x20000000 */
5637 #define ADC_CR_DEEPPWD                 ADC_CR_DEEPPWD_Msk                      /*!< ADC deep power down enable */
5638 #define ADC_CR_ADCALDIF_Pos            (30U)
5639 #define ADC_CR_ADCALDIF_Msk            (0x1UL << ADC_CR_ADCALDIF_Pos)          /*!< 0x40000000 */
5640 #define ADC_CR_ADCALDIF                ADC_CR_ADCALDIF_Msk                     /*!< ADC differential mode for calibration */
5641 #define ADC_CR_ADCAL_Pos               (31U)
5642 #define ADC_CR_ADCAL_Msk               (0x1UL << ADC_CR_ADCAL_Pos)             /*!< 0x80000000 */
5643 #define ADC_CR_ADCAL                   ADC_CR_ADCAL_Msk                        /*!< ADC calibration */
5644 
5645 /********************  Bit definition for ADC_CFGR1 register  ******************/
5646 #define ADC_CFGR1_DMNGT_Pos            (0U)
5647 #define ADC_CFGR1_DMNGT_Msk            (0x3UL << ADC_CFGR1_DMNGT_Pos)          /*!< 0x00000003 */
5648 #define ADC_CFGR1_DMNGT                ADC_CFGR1_DMNGT_Msk                     /*!< ADC data management configuration */
5649 #define ADC_CFGR1_DMNGT_0              (0x1UL << ADC_CFGR1_DMNGT_Pos)          /*!< 0x00000001 */
5650 #define ADC_CFGR1_DMNGT_1              (0x2UL << ADC_CFGR1_DMNGT_Pos)          /*!< 0x00000002 */
5651 
5652 #define ADC_CFGR1_RES_Pos              (2U)
5653 #define ADC_CFGR1_RES_Msk              (0x3UL << ADC_CFGR1_RES_Pos)            /*!< 0x0000000C */
5654 #define ADC_CFGR1_RES                  ADC_CFGR1_RES_Msk                       /*!< ADC data resolution */
5655 #define ADC_CFGR1_RES_0                (0x1UL << ADC_CFGR1_RES_Pos)            /*!< 0x00000004 */
5656 #define ADC_CFGR1_RES_1                (0x2UL << ADC_CFGR1_RES_Pos)            /*!< 0x00000008 */
5657 
5658 #define ADC_CFGR1_EXTSEL_Pos           (5U)
5659 #define ADC_CFGR1_EXTSEL_Msk           (0x1FUL << ADC_CFGR1_EXTSEL_Pos)        /*!< 0x000003E0 */
5660 #define ADC_CFGR1_EXTSEL               ADC_CFGR1_EXTSEL_Msk                    /*!< ADC group regular external trigger source */
5661 #define ADC_CFGR1_EXTSEL_0             (0x01UL << ADC_CFGR1_EXTSEL_Pos)        /*!< 0x00000020 */
5662 #define ADC_CFGR1_EXTSEL_1             (0x02UL << ADC_CFGR1_EXTSEL_Pos)        /*!< 0x00000040 */
5663 #define ADC_CFGR1_EXTSEL_2             (0x04UL << ADC_CFGR1_EXTSEL_Pos)        /*!< 0x00000080 */
5664 #define ADC_CFGR1_EXTSEL_3             (0x08UL << ADC_CFGR1_EXTSEL_Pos)        /*!< 0x00000100 */
5665 #define ADC_CFGR1_EXTSEL_4             (0x10UL << ADC_CFGR1_EXTSEL_Pos)        /*!< 0x00000200 */
5666 
5667 #define ADC_CFGR1_EXTEN_Pos            (10U)
5668 #define ADC_CFGR1_EXTEN_Msk            (0x3UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000C00 */
5669 #define ADC_CFGR1_EXTEN                ADC_CFGR1_EXTEN_Msk                     /*!< ADC group regular external trigger polarity */
5670 #define ADC_CFGR1_EXTEN_0              (0x1UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000400 */
5671 #define ADC_CFGR1_EXTEN_1              (0x2UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000800 */
5672 
5673 #define ADC_CFGR1_OVRMOD_Pos           (12U)
5674 #define ADC_CFGR1_OVRMOD_Msk           (0x1UL << ADC_CFGR1_OVRMOD_Pos)         /*!< 0x00001000 */
5675 #define ADC_CFGR1_OVRMOD               ADC_CFGR1_OVRMOD_Msk                    /*!< ADC group regular overrun configuration */
5676 #define ADC_CFGR1_CONT_Pos             (13U)
5677 #define ADC_CFGR1_CONT_Msk             (0x1UL << ADC_CFGR1_CONT_Pos)           /*!< 0x00002000 */
5678 #define ADC_CFGR1_CONT                 ADC_CFGR1_CONT_Msk                      /*!< ADC group regular continuous conversion mode */
5679 #define ADC_CFGR1_AUTDLY_Pos           (14U)
5680 #define ADC_CFGR1_AUTDLY_Msk           (0x1UL << ADC_CFGR1_AUTDLY_Pos)         /*!< 0x00004000 */
5681 #define ADC_CFGR1_AUTDLY               ADC_CFGR1_AUTDLY_Msk                    /*!< ADC low power auto wait */
5682 
5683 #define ADC_CFGR1_DISCEN_Pos           (16U)
5684 #define ADC_CFGR1_DISCEN_Msk           (0x1UL << ADC_CFGR1_DISCEN_Pos)         /*!< 0x00010000 */
5685 #define ADC_CFGR1_DISCEN               ADC_CFGR1_DISCEN_Msk                    /*!< ADC group regular sequencer discontinuous mode */
5686 
5687 #define ADC_CFGR1_DISCNUM_Pos          (17U)
5688 #define ADC_CFGR1_DISCNUM_Msk          (0x7UL << ADC_CFGR1_DISCNUM_Pos)        /*!< 0x000E0000 */
5689 #define ADC_CFGR1_DISCNUM              ADC_CFGR1_DISCNUM_Msk                   /*!< ADC group regular sequencer discontinuous number of ranks */
5690 #define ADC_CFGR1_DISCNUM_0            (0x1UL << ADC_CFGR1_DISCNUM_Pos)        /*!< 0x00020000 */
5691 #define ADC_CFGR1_DISCNUM_1            (0x2UL << ADC_CFGR1_DISCNUM_Pos)        /*!< 0x00040000 */
5692 #define ADC_CFGR1_DISCNUM_2            (0x4UL << ADC_CFGR1_DISCNUM_Pos)        /*!< 0x00080000 */
5693 
5694 #define ADC_CFGR1_JDISCEN_Pos          (20U)
5695 #define ADC_CFGR1_JDISCEN_Msk          (0x1UL << ADC_CFGR1_JDISCEN_Pos)        /*!< 0x00100000 */
5696 #define ADC_CFGR1_JDISCEN              ADC_CFGR1_JDISCEN_Msk                   /*!< ADC group injected sequencer discontinuous mode */
5697 
5698 #define ADC_CFGR1_AWD1SGL_Pos          (22U)
5699 #define ADC_CFGR1_AWD1SGL_Msk          (0x1UL << ADC_CFGR1_AWD1SGL_Pos)        /*!< 0x00400000 */
5700 #define ADC_CFGR1_AWD1SGL              ADC_CFGR1_AWD1SGL_Msk                   /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
5701 #define ADC_CFGR1_AWD1EN_Pos           (23U)
5702 #define ADC_CFGR1_AWD1EN_Msk           (0x1UL << ADC_CFGR1_AWD1EN_Pos)         /*!< 0x00800000 */
5703 #define ADC_CFGR1_AWD1EN               ADC_CFGR1_AWD1EN_Msk                    /*!< ADC analog watchdog 1 enable on scope ADC group regular */
5704 #define ADC_CFGR1_JAWD1EN_Pos          (24U)
5705 #define ADC_CFGR1_JAWD1EN_Msk          (0x1UL << ADC_CFGR1_JAWD1EN_Pos)        /*!< 0x01000000 */
5706 #define ADC_CFGR1_JAWD1EN              ADC_CFGR1_JAWD1EN_Msk                   /*!< ADC analog watchdog 1 enable on scope ADC group injected */
5707 #define ADC_CFGR1_JAUTO_Pos            (25U)
5708 #define ADC_CFGR1_JAUTO_Msk            (0x1UL << ADC_CFGR1_JAUTO_Pos)          /*!< 0x02000000 */
5709 #define ADC_CFGR1_JAUTO                ADC_CFGR1_JAUTO_Msk                     /*!< ADC group injected automatic trigger mode */
5710 
5711 #define ADC_CFGR1_AWD1CH_Pos           (26U)
5712 #define ADC_CFGR1_AWD1CH_Msk           (0x1FUL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x7C000000 */
5713 #define ADC_CFGR1_AWD1CH               ADC_CFGR1_AWD1CH_Msk                    /*!< ADC analog watchdog 1 monitored channel selection */
5714 #define ADC_CFGR1_AWD1CH_0             (0x01UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x04000000 */
5715 #define ADC_CFGR1_AWD1CH_1             (0x02UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x08000000 */
5716 #define ADC_CFGR1_AWD1CH_2             (0x04UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x10000000 */
5717 #define ADC_CFGR1_AWD1CH_3             (0x08UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x20000000 */
5718 #define ADC_CFGR1_AWD1CH_4             (0x10UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x40000000 */
5719 
5720 /********************  Bit definition for ADC_CFGR2 register  *****************/
5721 #define ADC_CFGR2_ROVSE_Pos            (0U)
5722 #define ADC_CFGR2_ROVSE_Msk            (0x1UL << ADC_CFGR2_ROVSE_Pos)          /*!< 0x00000001 */
5723 #define ADC_CFGR2_ROVSE                ADC_CFGR2_ROVSE_Msk                     /*!< ADC oversampler enable on scope ADC group regular */
5724 #define ADC_CFGR2_JOVSE_Pos            (1U)
5725 #define ADC_CFGR2_JOVSE_Msk            (0x1UL << ADC_CFGR2_JOVSE_Pos)          /*!< 0x00000002 */
5726 #define ADC_CFGR2_JOVSE                ADC_CFGR2_JOVSE_Msk                     /*!< ADC oversampler enable on scope ADC group injected */
5727 
5728 #define ADC_CFGR2_OVSS_Pos             (5U)
5729 #define ADC_CFGR2_OVSS_Msk             (0xFUL << ADC_CFGR2_OVSS_Pos)           /*!< 0x000001E0 */
5730 #define ADC_CFGR2_OVSS                 ADC_CFGR2_OVSS_Msk                      /*!< ADC oversampling shift */
5731 #define ADC_CFGR2_OVSS_0               (0x1UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000020 */
5732 #define ADC_CFGR2_OVSS_1               (0x2UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000040 */
5733 #define ADC_CFGR2_OVSS_2               (0x4UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000080 */
5734 #define ADC_CFGR2_OVSS_3               (0x8UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000100 */
5735 
5736 #define ADC_CFGR2_TROVS_Pos            (9U)
5737 #define ADC_CFGR2_TROVS_Msk            (0x1UL << ADC_CFGR2_TROVS_Pos)          /*!< 0x00000200 */
5738 #define ADC_CFGR2_TROVS                ADC_CFGR2_TROVS_Msk                     /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
5739 #define ADC_CFGR2_ROVSM_Pos            (10U)
5740 #define ADC_CFGR2_ROVSM_Msk            (0x1UL << ADC_CFGR2_ROVSM_Pos)          /*!< 0x00000400 */
5741 #define ADC_CFGR2_ROVSM                ADC_CFGR2_ROVSM_Msk                     /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
5742 
5743 #define ADC_CFGR2_BULB_Pos             (13U)
5744 #define ADC_CFGR2_BULB_Msk             (0x1UL << ADC_CFGR2_BULB_Pos)            /*!< 0x00002000 */
5745 #define ADC_CFGR2_BULB                 ADC_CFGR2_BULB_Msk                       /*!< ADC bulb sampling mode */
5746 
5747 #define ADC_CFGR2_SWTRIG_Pos           (14U)
5748 #define ADC_CFGR2_SWTRIG_Msk           (0x1UL << ADC_CFGR2_SWTRIG_Pos)          /*!< 0x00004000 */
5749 #define ADC_CFGR2_SWTRIG               ADC_CFGR2_SWTRIG_Msk                     /*!< ADC software trigger bit for sampling time control trigger mode */
5750 
5751 #define ADC_CFGR2_SMPTRIG_Pos          (15U)
5752 #define ADC_CFGR2_SMPTRIG_Msk          (0x1UL << ADC_CFGR2_SMPTRIG_Pos)         /*!< 0x00008000 */
5753 #define ADC_CFGR2_SMPTRIG              ADC_CFGR2_SMPTRIG_Msk                    /*!< ADC sampling time control trigger mode */
5754 
5755 #define ADC_CFGR2_OVSR_Pos             (16U)
5756 #define ADC_CFGR2_OVSR_Msk             (0x3FFUL << ADC_CFGR2_OVSR_Pos)          /*!< 0x03FF0000 */
5757 #define ADC_CFGR2_OVSR                 ADC_CFGR2_OVSR_Msk                       /*!< ADC oversampling ratio */
5758 #define ADC_CFGR2_OVSR_0               (0x001UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00010000 */
5759 #define ADC_CFGR2_OVSR_1               (0x002UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00020000 */
5760 #define ADC_CFGR2_OVSR_2               (0x004UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00040000 */
5761 #define ADC_CFGR2_OVSR_3               (0x008UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00080000 */
5762 #define ADC_CFGR2_OVSR_4               (0x010UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00100000 */
5763 #define ADC_CFGR2_OVSR_5               (0x020UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00200000 */
5764 #define ADC_CFGR2_OVSR_6               (0x040UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00400000 */
5765 #define ADC_CFGR2_OVSR_7               (0x080UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00800000 */
5766 #define ADC_CFGR2_OVSR_8               (0x100UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x01000000 */
5767 #define ADC_CFGR2_OVSR_9               (0x200UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x02000000 */
5768 
5769 #define ADC_CFGR2_LSHIFT_Pos           (28U)
5770 #define ADC_CFGR2_LSHIFT_Msk           (0xFUL << ADC_CFGR2_LSHIFT_Pos)          /*!< 0xF0000000 */
5771 #define ADC_CFGR2_LSHIFT               ADC_CFGR2_LSHIFT_Msk                     /*!< ADC left shift factor */
5772 #define ADC_CFGR2_LSHIFT_0             (0x1UL << ADC_CFGR2_LSHIFT_Pos)          /*!< 0x10000000 */
5773 #define ADC_CFGR2_LSHIFT_1             (0x2UL << ADC_CFGR2_LSHIFT_Pos)          /*!< 0x20000000 */
5774 #define ADC_CFGR2_LSHIFT_2             (0x4UL << ADC_CFGR2_LSHIFT_Pos)          /*!< 0x40000000 */
5775 #define ADC_CFGR2_LSHIFT_3             (0x8UL << ADC_CFGR2_LSHIFT_Pos)          /*!< 0x80000000 */
5776 
5777 /********************  Bit definition for ADC_SMPR1 register  *****************/
5778 #define ADC_SMPR1_SMP0_Pos             (0U)
5779 #define ADC_SMPR1_SMP0_Msk             (0x7UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000007 */
5780 #define ADC_SMPR1_SMP0                 ADC_SMPR1_SMP0_Msk                      /*!< ADC channel 0 sampling time selection  */
5781 #define ADC_SMPR1_SMP0_0               (0x1UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000001 */
5782 #define ADC_SMPR1_SMP0_1               (0x2UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000002 */
5783 #define ADC_SMPR1_SMP0_2               (0x4UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000004 */
5784 
5785 #define ADC_SMPR1_SMP1_Pos             (3U)
5786 #define ADC_SMPR1_SMP1_Msk             (0x7UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000038 */
5787 #define ADC_SMPR1_SMP1                 ADC_SMPR1_SMP1_Msk                      /*!< ADC channel 1 sampling time selection  */
5788 #define ADC_SMPR1_SMP1_0               (0x1UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000008 */
5789 #define ADC_SMPR1_SMP1_1               (0x2UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000010 */
5790 #define ADC_SMPR1_SMP1_2               (0x4UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000020 */
5791 
5792 #define ADC_SMPR1_SMP2_Pos             (6U)
5793 #define ADC_SMPR1_SMP2_Msk             (0x7UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x000001C0 */
5794 #define ADC_SMPR1_SMP2                 ADC_SMPR1_SMP2_Msk                      /*!< ADC channel 2 sampling time selection  */
5795 #define ADC_SMPR1_SMP2_0               (0x1UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000040 */
5796 #define ADC_SMPR1_SMP2_1               (0x2UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000080 */
5797 #define ADC_SMPR1_SMP2_2               (0x4UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000100 */
5798 
5799 #define ADC_SMPR1_SMP3_Pos             (9U)
5800 #define ADC_SMPR1_SMP3_Msk             (0x7UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000E00 */
5801 #define ADC_SMPR1_SMP3                 ADC_SMPR1_SMP3_Msk                      /*!< ADC channel 3 sampling time selection  */
5802 #define ADC_SMPR1_SMP3_0               (0x1UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000200 */
5803 #define ADC_SMPR1_SMP3_1               (0x2UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000400 */
5804 #define ADC_SMPR1_SMP3_2               (0x4UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000800 */
5805 
5806 #define ADC_SMPR1_SMP4_Pos             (12U)
5807 #define ADC_SMPR1_SMP4_Msk             (0x7UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00007000 */
5808 #define ADC_SMPR1_SMP4                 ADC_SMPR1_SMP4_Msk                      /*!< ADC channel 4 sampling time selection  */
5809 #define ADC_SMPR1_SMP4_0               (0x1UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00001000 */
5810 #define ADC_SMPR1_SMP4_1               (0x2UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00002000 */
5811 #define ADC_SMPR1_SMP4_2               (0x4UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00004000 */
5812 
5813 #define ADC_SMPR1_SMP5_Pos             (15U)
5814 #define ADC_SMPR1_SMP5_Msk             (0x7UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00038000 */
5815 #define ADC_SMPR1_SMP5                 ADC_SMPR1_SMP5_Msk                      /*!< ADC channel 5 sampling time selection  */
5816 #define ADC_SMPR1_SMP5_0               (0x1UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00008000 */
5817 #define ADC_SMPR1_SMP5_1               (0x2UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00010000 */
5818 #define ADC_SMPR1_SMP5_2               (0x4UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00020000 */
5819 
5820 #define ADC_SMPR1_SMP6_Pos             (18U)
5821 #define ADC_SMPR1_SMP6_Msk             (0x7UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x001C0000 */
5822 #define ADC_SMPR1_SMP6                 ADC_SMPR1_SMP6_Msk                      /*!< ADC channel 6 sampling time selection  */
5823 #define ADC_SMPR1_SMP6_0               (0x1UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00040000 */
5824 #define ADC_SMPR1_SMP6_1               (0x2UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00080000 */
5825 #define ADC_SMPR1_SMP6_2               (0x4UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00100000 */
5826 
5827 #define ADC_SMPR1_SMP7_Pos             (21U)
5828 #define ADC_SMPR1_SMP7_Msk             (0x7UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00E00000 */
5829 #define ADC_SMPR1_SMP7                 ADC_SMPR1_SMP7_Msk                      /*!< ADC channel 7 sampling time selection  */
5830 #define ADC_SMPR1_SMP7_0               (0x1UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00200000 */
5831 #define ADC_SMPR1_SMP7_1               (0x2UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00400000 */
5832 #define ADC_SMPR1_SMP7_2               (0x4UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00800000 */
5833 
5834 #define ADC_SMPR1_SMP8_Pos             (24U)
5835 #define ADC_SMPR1_SMP8_Msk             (0x7UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x07000000 */
5836 #define ADC_SMPR1_SMP8                 ADC_SMPR1_SMP8_Msk                      /*!< ADC channel 8 sampling time selection  */
5837 #define ADC_SMPR1_SMP8_0               (0x1UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x01000000 */
5838 #define ADC_SMPR1_SMP8_1               (0x2UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x02000000 */
5839 #define ADC_SMPR1_SMP8_2               (0x4UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x04000000 */
5840 
5841 #define ADC_SMPR1_SMP9_Pos             (27U)
5842 #define ADC_SMPR1_SMP9_Msk             (0x7UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x38000000 */
5843 #define ADC_SMPR1_SMP9                 ADC_SMPR1_SMP9_Msk                      /*!< ADC channel 9 sampling time selection  */
5844 #define ADC_SMPR1_SMP9_0               (0x1UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x08000000 */
5845 #define ADC_SMPR1_SMP9_1               (0x2UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x10000000 */
5846 #define ADC_SMPR1_SMP9_2               (0x4UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x20000000 */
5847 
5848 /********************  Bit definition for ADC_SMPR2 register  *****************/
5849 #define ADC_SMPR2_SMP10_Pos            (0U)
5850 #define ADC_SMPR2_SMP10_Msk            (0x7UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000007 */
5851 #define ADC_SMPR2_SMP10                ADC_SMPR2_SMP10_Msk                     /*!< ADC channel 10 sampling time selection  */
5852 #define ADC_SMPR2_SMP10_0              (0x1UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000001 */
5853 #define ADC_SMPR2_SMP10_1              (0x2UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000002 */
5854 #define ADC_SMPR2_SMP10_2              (0x4UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000004 */
5855 
5856 #define ADC_SMPR2_SMP11_Pos            (3U)
5857 #define ADC_SMPR2_SMP11_Msk            (0x7UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000038 */
5858 #define ADC_SMPR2_SMP11                ADC_SMPR2_SMP11_Msk                     /*!< ADC channel 11 sampling time selection  */
5859 #define ADC_SMPR2_SMP11_0              (0x1UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000008 */
5860 #define ADC_SMPR2_SMP11_1              (0x2UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000010 */
5861 #define ADC_SMPR2_SMP11_2              (0x4UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000020 */
5862 
5863 #define ADC_SMPR2_SMP12_Pos            (6U)
5864 #define ADC_SMPR2_SMP12_Msk            (0x7UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x000001C0 */
5865 #define ADC_SMPR2_SMP12                ADC_SMPR2_SMP12_Msk                     /*!< ADC channel 12 sampling time selection  */
5866 #define ADC_SMPR2_SMP12_0              (0x1UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000040 */
5867 #define ADC_SMPR2_SMP12_1              (0x2UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000080 */
5868 #define ADC_SMPR2_SMP12_2              (0x4UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000100 */
5869 
5870 #define ADC_SMPR2_SMP13_Pos            (9U)
5871 #define ADC_SMPR2_SMP13_Msk            (0x7UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000E00 */
5872 #define ADC_SMPR2_SMP13                ADC_SMPR2_SMP13_Msk                     /*!< ADC channel 13 sampling time selection  */
5873 #define ADC_SMPR2_SMP13_0              (0x1UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000200 */
5874 #define ADC_SMPR2_SMP13_1              (0x2UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000400 */
5875 #define ADC_SMPR2_SMP13_2              (0x4UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000800 */
5876 
5877 #define ADC_SMPR2_SMP14_Pos            (12U)
5878 #define ADC_SMPR2_SMP14_Msk            (0x7UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00007000 */
5879 #define ADC_SMPR2_SMP14                ADC_SMPR2_SMP14_Msk                     /*!< ADC channel 14 sampling time selection  */
5880 #define ADC_SMPR2_SMP14_0              (0x1UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00001000 */
5881 #define ADC_SMPR2_SMP14_1              (0x2UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00002000 */
5882 #define ADC_SMPR2_SMP14_2              (0x4UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00004000 */
5883 
5884 #define ADC_SMPR2_SMP15_Pos            (15U)
5885 #define ADC_SMPR2_SMP15_Msk            (0x7UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00038000 */
5886 #define ADC_SMPR2_SMP15                ADC_SMPR2_SMP15_Msk                     /*!< ADC channel 15 sampling time selection  */
5887 #define ADC_SMPR2_SMP15_0              (0x1UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00008000 */
5888 #define ADC_SMPR2_SMP15_1              (0x2UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00010000 */
5889 #define ADC_SMPR2_SMP15_2              (0x4UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00020000 */
5890 
5891 #define ADC_SMPR2_SMP16_Pos            (18U)
5892 #define ADC_SMPR2_SMP16_Msk            (0x7UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x001C0000 */
5893 #define ADC_SMPR2_SMP16                ADC_SMPR2_SMP16_Msk                     /*!< ADC channel 16 sampling time selection  */
5894 #define ADC_SMPR2_SMP16_0              (0x1UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00040000 */
5895 #define ADC_SMPR2_SMP16_1              (0x2UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00080000 */
5896 #define ADC_SMPR2_SMP16_2              (0x4UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00100000 */
5897 
5898 #define ADC_SMPR2_SMP17_Pos            (21U)
5899 #define ADC_SMPR2_SMP17_Msk            (0x7UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00E00000 */
5900 #define ADC_SMPR2_SMP17                ADC_SMPR2_SMP17_Msk                     /*!< ADC channel 17 sampling time selection  */
5901 #define ADC_SMPR2_SMP17_0              (0x1UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00200000 */
5902 #define ADC_SMPR2_SMP17_1              (0x2UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00400000 */
5903 #define ADC_SMPR2_SMP17_2              (0x4UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00800000 */
5904 
5905 #define ADC_SMPR2_SMP18_Pos            (24U)
5906 #define ADC_SMPR2_SMP18_Msk            (0x7UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x07000000 */
5907 #define ADC_SMPR2_SMP18                ADC_SMPR2_SMP18_Msk                     /*!< ADC channel 18 sampling time selection  */
5908 #define ADC_SMPR2_SMP18_0              (0x1UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x01000000 */
5909 #define ADC_SMPR2_SMP18_1              (0x2UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x02000000 */
5910 #define ADC_SMPR2_SMP18_2              (0x4UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x04000000 */
5911 
5912 #define ADC_SMPR2_SMP19_Pos            (27U)
5913 #define ADC_SMPR2_SMP19_Msk            (0x7UL << ADC_SMPR2_SMP19_Pos)          /*!< 0x38000000 */
5914 #define ADC_SMPR2_SMP19                ADC_SMPR2_SMP19_Msk                     /*!< ADC Channel 19 Sampling time selection  */
5915 #define ADC_SMPR2_SMP19_0              (0x1UL << ADC_SMPR2_SMP19_Pos)          /*!< 0x08000000 */
5916 #define ADC_SMPR2_SMP19_1              (0x2UL << ADC_SMPR2_SMP19_Pos)          /*!< 0x10000000 */
5917 #define ADC_SMPR2_SMP19_2              (0x4UL << ADC_SMPR2_SMP19_Pos)          /*!< 0x20000000 */
5918 
5919 /********************  Bit definition for ADC_PCSEL register  *****************/
5920 #define ADC_PCSEL_PCSEL_Pos            (0U)
5921 #define ADC_PCSEL_PCSEL_Msk            (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x000FFFFF */
5922 #define ADC_PCSEL_PCSEL                ADC_PCSEL_PCSEL_Msk                   /*!< ADC channel preselection */
5923 #define ADC_PCSEL_PCSEL_0              (0x00001UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000001 */
5924 #define ADC_PCSEL_PCSEL_1              (0x00002UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000002 */
5925 #define ADC_PCSEL_PCSEL_2              (0x00004UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000004 */
5926 #define ADC_PCSEL_PCSEL_3              (0x00008UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000008 */
5927 #define ADC_PCSEL_PCSEL_4              (0x00010UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000010 */
5928 #define ADC_PCSEL_PCSEL_5              (0x00020UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000020 */
5929 #define ADC_PCSEL_PCSEL_6              (0x00040UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000040 */
5930 #define ADC_PCSEL_PCSEL_7              (0x00080UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000080 */
5931 #define ADC_PCSEL_PCSEL_8              (0x00100UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000100 */
5932 #define ADC_PCSEL_PCSEL_9              (0x00200UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000200 */
5933 #define ADC_PCSEL_PCSEL_10             (0x00400UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000400 */
5934 #define ADC_PCSEL_PCSEL_11             (0x00800UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000800 */
5935 #define ADC_PCSEL_PCSEL_12             (0x01000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00001000 */
5936 #define ADC_PCSEL_PCSEL_13             (0x02000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00002000 */
5937 #define ADC_PCSEL_PCSEL_14             (0x04000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00004000 */
5938 #define ADC_PCSEL_PCSEL_15             (0x08000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00008000 */
5939 #define ADC_PCSEL_PCSEL_16             (0x10000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00010000 */
5940 #define ADC_PCSEL_PCSEL_17             (0x20000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00020000 */
5941 #define ADC_PCSEL_PCSEL_18             (0x40000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00040000 */
5942 #define ADC_PCSEL_PCSEL_19             (0x80000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00080000 */
5943 
5944 /********************  Bit definition for ADC_SQR1 register  ******************/
5945 #define ADC_SQR1_L_Pos                 (0U)
5946 #define ADC_SQR1_L_Msk                 (0xFUL << ADC_SQR1_L_Pos)               /*!< 0x0000000F */
5947 #define ADC_SQR1_L                     ADC_SQR1_L_Msk                          /*!< ADC group regular sequencer scan length */
5948 #define ADC_SQR1_L_0                   (0x1UL << ADC_SQR1_L_Pos)               /*!< 0x00000001 */
5949 #define ADC_SQR1_L_1                   (0x2UL << ADC_SQR1_L_Pos)               /*!< 0x00000002 */
5950 #define ADC_SQR1_L_2                   (0x4UL << ADC_SQR1_L_Pos)               /*!< 0x00000004 */
5951 #define ADC_SQR1_L_3                   (0x8UL << ADC_SQR1_L_Pos)               /*!< 0x00000008 */
5952 
5953 #define ADC_SQR1_SQ1_Pos               (6U)
5954 #define ADC_SQR1_SQ1_Msk               (0x1FUL << ADC_SQR1_SQ1_Pos)            /*!< 0x000007C0 */
5955 #define ADC_SQR1_SQ1                   ADC_SQR1_SQ1_Msk                        /*!< ADC group regular sequencer rank 1 */
5956 #define ADC_SQR1_SQ1_0                 (0x01UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000040 */
5957 #define ADC_SQR1_SQ1_1                 (0x02UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000080 */
5958 #define ADC_SQR1_SQ1_2                 (0x04UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000100 */
5959 #define ADC_SQR1_SQ1_3                 (0x08UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000200 */
5960 #define ADC_SQR1_SQ1_4                 (0x10UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000400 */
5961 
5962 #define ADC_SQR1_SQ2_Pos               (12U)
5963 #define ADC_SQR1_SQ2_Msk               (0x1FUL << ADC_SQR1_SQ2_Pos)            /*!< 0x0001F000 */
5964 #define ADC_SQR1_SQ2                   ADC_SQR1_SQ2_Msk                        /*!< ADC group regular sequencer rank 2 */
5965 #define ADC_SQR1_SQ2_0                 (0x01UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00001000 */
5966 #define ADC_SQR1_SQ2_1                 (0x02UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00002000 */
5967 #define ADC_SQR1_SQ2_2                 (0x04UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00004000 */
5968 #define ADC_SQR1_SQ2_3                 (0x08UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00008000 */
5969 #define ADC_SQR1_SQ2_4                 (0x10UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00010000 */
5970 
5971 #define ADC_SQR1_SQ3_Pos               (18U)
5972 #define ADC_SQR1_SQ3_Msk               (0x1FUL << ADC_SQR1_SQ3_Pos)            /*!< 0x007C0000 */
5973 #define ADC_SQR1_SQ3                   ADC_SQR1_SQ3_Msk                        /*!< ADC group regular sequencer rank 3 */
5974 #define ADC_SQR1_SQ3_0                 (0x01UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00040000 */
5975 #define ADC_SQR1_SQ3_1                 (0x02UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00080000 */
5976 #define ADC_SQR1_SQ3_2                 (0x04UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00100000 */
5977 #define ADC_SQR1_SQ3_3                 (0x08UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00200000 */
5978 #define ADC_SQR1_SQ3_4                 (0x10UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00400000 */
5979 
5980 #define ADC_SQR1_SQ4_Pos               (24U)
5981 #define ADC_SQR1_SQ4_Msk               (0x1FUL << ADC_SQR1_SQ4_Pos)            /*!< 0x1F000000 */
5982 #define ADC_SQR1_SQ4                   ADC_SQR1_SQ4_Msk                        /*!< ADC group regular sequencer rank 4 */
5983 #define ADC_SQR1_SQ4_0                 (0x01UL << ADC_SQR1_SQ4_Pos)            /*!< 0x01000000 */
5984 #define ADC_SQR1_SQ4_1                 (0x02UL << ADC_SQR1_SQ4_Pos)            /*!< 0x02000000 */
5985 #define ADC_SQR1_SQ4_2                 (0x04UL << ADC_SQR1_SQ4_Pos)            /*!< 0x04000000 */
5986 #define ADC_SQR1_SQ4_3                 (0x08UL << ADC_SQR1_SQ4_Pos)            /*!< 0x08000000 */
5987 #define ADC_SQR1_SQ4_4                 (0x10UL << ADC_SQR1_SQ4_Pos)            /*!< 0x10000000 */
5988 
5989 /********************  Bit definition for ADC_SQR2 register  ******************/
5990 #define ADC_SQR2_SQ5_Pos               (0U)
5991 #define ADC_SQR2_SQ5_Msk               (0x1FUL << ADC_SQR2_SQ5_Pos)            /*!< 0x0000001F */
5992 #define ADC_SQR2_SQ5                   ADC_SQR2_SQ5_Msk                        /*!< ADC group regular sequencer rank 5 */
5993 #define ADC_SQR2_SQ5_0                 (0x01UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000001 */
5994 #define ADC_SQR2_SQ5_1                 (0x02UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000002 */
5995 #define ADC_SQR2_SQ5_2                 (0x04UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000004 */
5996 #define ADC_SQR2_SQ5_3                 (0x08UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000008 */
5997 #define ADC_SQR2_SQ5_4                 (0x10UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000010 */
5998 
5999 #define ADC_SQR2_SQ6_Pos               (6U)
6000 #define ADC_SQR2_SQ6_Msk               (0x1FUL << ADC_SQR2_SQ6_Pos)            /*!< 0x000007C0 */
6001 #define ADC_SQR2_SQ6                   ADC_SQR2_SQ6_Msk                        /*!< ADC group regular sequencer rank 6 */
6002 #define ADC_SQR2_SQ6_0                 (0x01UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000040 */
6003 #define ADC_SQR2_SQ6_1                 (0x02UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000080 */
6004 #define ADC_SQR2_SQ6_2                 (0x04UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000100 */
6005 #define ADC_SQR2_SQ6_3                 (0x08UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000200 */
6006 #define ADC_SQR2_SQ6_4                 (0x10UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000400 */
6007 
6008 #define ADC_SQR2_SQ7_Pos               (12U)
6009 #define ADC_SQR2_SQ7_Msk               (0x1FUL << ADC_SQR2_SQ7_Pos)            /*!< 0x0001F000 */
6010 #define ADC_SQR2_SQ7                   ADC_SQR2_SQ7_Msk                        /*!< ADC group regular sequencer rank 7 */
6011 #define ADC_SQR2_SQ7_0                 (0x01UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00001000 */
6012 #define ADC_SQR2_SQ7_1                 (0x02UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00002000 */
6013 #define ADC_SQR2_SQ7_2                 (0x04UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00004000 */
6014 #define ADC_SQR2_SQ7_3                 (0x08UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00008000 */
6015 #define ADC_SQR2_SQ7_4                 (0x10UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00010000 */
6016 
6017 #define ADC_SQR2_SQ8_Pos               (18U)
6018 #define ADC_SQR2_SQ8_Msk               (0x1FUL << ADC_SQR2_SQ8_Pos)            /*!< 0x007C0000 */
6019 #define ADC_SQR2_SQ8                   ADC_SQR2_SQ8_Msk                        /*!< ADC group regular sequencer rank 8 */
6020 #define ADC_SQR2_SQ8_0                 (0x01UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00040000 */
6021 #define ADC_SQR2_SQ8_1                 (0x02UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00080000 */
6022 #define ADC_SQR2_SQ8_2                 (0x04UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00100000 */
6023 #define ADC_SQR2_SQ8_3                 (0x08UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00200000 */
6024 #define ADC_SQR2_SQ8_4                 (0x10UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00400000 */
6025 
6026 #define ADC_SQR2_SQ9_Pos               (24U)
6027 #define ADC_SQR2_SQ9_Msk               (0x1FUL << ADC_SQR2_SQ9_Pos)            /*!< 0x1F000000 */
6028 #define ADC_SQR2_SQ9                   ADC_SQR2_SQ9_Msk                        /*!< ADC group regular sequencer rank 9 */
6029 #define ADC_SQR2_SQ9_0                 (0x01UL << ADC_SQR2_SQ9_Pos)            /*!< 0x01000000 */
6030 #define ADC_SQR2_SQ9_1                 (0x02UL << ADC_SQR2_SQ9_Pos)            /*!< 0x02000000 */
6031 #define ADC_SQR2_SQ9_2                 (0x04UL << ADC_SQR2_SQ9_Pos)            /*!< 0x04000000 */
6032 #define ADC_SQR2_SQ9_3                 (0x08UL << ADC_SQR2_SQ9_Pos)            /*!< 0x08000000 */
6033 #define ADC_SQR2_SQ9_4                 (0x10UL << ADC_SQR2_SQ9_Pos)            /*!< 0x10000000 */
6034 
6035 /********************  Bit definition for ADC_SQR3 register  ******************/
6036 #define ADC_SQR3_SQ10_Pos              (0U)
6037 #define ADC_SQR3_SQ10_Msk              (0x1FUL << ADC_SQR3_SQ10_Pos)           /*!< 0x0000001F */
6038 #define ADC_SQR3_SQ10                  ADC_SQR3_SQ10_Msk                       /*!< ADC group regular sequencer rank 10 */
6039 #define ADC_SQR3_SQ10_0                (0x01UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000001 */
6040 #define ADC_SQR3_SQ10_1                (0x02UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000002 */
6041 #define ADC_SQR3_SQ10_2                (0x04UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000004 */
6042 #define ADC_SQR3_SQ10_3                (0x08UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000008 */
6043 #define ADC_SQR3_SQ10_4                (0x10UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000010 */
6044 
6045 #define ADC_SQR3_SQ11_Pos              (6U)
6046 #define ADC_SQR3_SQ11_Msk              (0x1FUL << ADC_SQR3_SQ11_Pos)           /*!< 0x000007C0 */
6047 #define ADC_SQR3_SQ11                  ADC_SQR3_SQ11_Msk                       /*!< ADC group regular sequencer rank 11 */
6048 #define ADC_SQR3_SQ11_0                (0x01UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000040 */
6049 #define ADC_SQR3_SQ11_1                (0x02UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000080 */
6050 #define ADC_SQR3_SQ11_2                (0x04UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000100 */
6051 #define ADC_SQR3_SQ11_3                (0x08UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000200 */
6052 #define ADC_SQR3_SQ11_4                (0x10UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000400 */
6053 
6054 #define ADC_SQR3_SQ12_Pos              (12U)
6055 #define ADC_SQR3_SQ12_Msk              (0x1FUL << ADC_SQR3_SQ12_Pos)           /*!< 0x0001F000 */
6056 #define ADC_SQR3_SQ12                  ADC_SQR3_SQ12_Msk                       /*!< ADC group regular sequencer rank 12 */
6057 #define ADC_SQR3_SQ12_0                (0x01UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00001000 */
6058 #define ADC_SQR3_SQ12_1                (0x02UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00002000 */
6059 #define ADC_SQR3_SQ12_2                (0x04UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00004000 */
6060 #define ADC_SQR3_SQ12_3                (0x08UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00008000 */
6061 #define ADC_SQR3_SQ12_4                (0x10UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00010000 */
6062 
6063 #define ADC_SQR3_SQ13_Pos              (18U)
6064 #define ADC_SQR3_SQ13_Msk              (0x1FUL << ADC_SQR3_SQ13_Pos)           /*!< 0x007C0000 */
6065 #define ADC_SQR3_SQ13                  ADC_SQR3_SQ13_Msk                       /*!< ADC group regular sequencer rank 13 */
6066 #define ADC_SQR3_SQ13_0                (0x01UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00040000 */
6067 #define ADC_SQR3_SQ13_1                (0x02UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00080000 */
6068 #define ADC_SQR3_SQ13_2                (0x04UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00100000 */
6069 #define ADC_SQR3_SQ13_3                (0x08UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00200000 */
6070 #define ADC_SQR3_SQ13_4                (0x10UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00400000 */
6071 
6072 #define ADC_SQR3_SQ14_Pos              (24U)
6073 #define ADC_SQR3_SQ14_Msk              (0x1FUL << ADC_SQR3_SQ14_Pos)           /*!< 0x1F000000 */
6074 #define ADC_SQR3_SQ14                  ADC_SQR3_SQ14_Msk                       /*!< ADC group regular sequencer rank 14 */
6075 #define ADC_SQR3_SQ14_0                (0x01UL << ADC_SQR3_SQ14_Pos)           /*!< 0x01000000 */
6076 #define ADC_SQR3_SQ14_1                (0x02UL << ADC_SQR3_SQ14_Pos)           /*!< 0x02000000 */
6077 #define ADC_SQR3_SQ14_2                (0x04UL << ADC_SQR3_SQ14_Pos)           /*!< 0x04000000 */
6078 #define ADC_SQR3_SQ14_3                (0x08UL << ADC_SQR3_SQ14_Pos)           /*!< 0x08000000 */
6079 #define ADC_SQR3_SQ14_4                (0x10UL << ADC_SQR3_SQ14_Pos)           /*!< 0x10000000 */
6080 
6081 /********************  Bit definition for ADC_SQR4 register  ******************/
6082 #define ADC_SQR4_SQ15_Pos              (0U)
6083 #define ADC_SQR4_SQ15_Msk              (0x1FUL << ADC_SQR4_SQ15_Pos)           /*!< 0x0000001F */
6084 #define ADC_SQR4_SQ15                  ADC_SQR4_SQ15_Msk                       /*!< ADC group regular sequencer rank 15 */
6085 #define ADC_SQR4_SQ15_0                (0x01UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000001 */
6086 #define ADC_SQR4_SQ15_1                (0x02UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000002 */
6087 #define ADC_SQR4_SQ15_2                (0x04UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000004 */
6088 #define ADC_SQR4_SQ15_3                (0x08UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000008 */
6089 #define ADC_SQR4_SQ15_4                (0x10UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000010 */
6090 
6091 #define ADC_SQR4_SQ16_Pos              (6U)
6092 #define ADC_SQR4_SQ16_Msk              (0x1FUL << ADC_SQR4_SQ16_Pos)           /*!< 0x000007C0 */
6093 #define ADC_SQR4_SQ16                  ADC_SQR4_SQ16_Msk                       /*!< ADC group regular sequencer rank 16 */
6094 #define ADC_SQR4_SQ16_0                (0x01UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000040 */
6095 #define ADC_SQR4_SQ16_1                (0x02UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000080 */
6096 #define ADC_SQR4_SQ16_2                (0x04UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000100 */
6097 #define ADC_SQR4_SQ16_3                (0x08UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000200 */
6098 #define ADC_SQR4_SQ16_4                (0x10UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000400 */
6099 
6100 /********************  Bit definition for ADC_DR register  ********************/
6101 #define ADC_DR_RDATA_Pos               (0U)
6102 #define ADC_DR_RDATA_Msk               (0xFFFFFFFFUL << ADC_DR_RDATA_Pos)      /*!< 0xFFFFFFFF */
6103 #define ADC_DR_RDATA                   ADC_DR_RDATA_Msk                        /*!< ADC group regular conversion data */
6104 #define ADC_DR_RDATA_0                 (0x00000001UL << ADC_DR_RDATA_Pos)      /*!< 0x00000001 */
6105 #define ADC_DR_RDATA_1                 (0x00000002UL << ADC_DR_RDATA_Pos)      /*!< 0x00000002 */
6106 #define ADC_DR_RDATA_2                 (0x00000004UL << ADC_DR_RDATA_Pos)      /*!< 0x00000004 */
6107 #define ADC_DR_RDATA_3                 (0x00000008UL << ADC_DR_RDATA_Pos)      /*!< 0x00000008 */
6108 #define ADC_DR_RDATA_4                 (0x00000010UL << ADC_DR_RDATA_Pos)      /*!< 0x00000010 */
6109 #define ADC_DR_RDATA_5                 (0x00000020UL << ADC_DR_RDATA_Pos)      /*!< 0x00000020 */
6110 #define ADC_DR_RDATA_6                 (0x00000040UL << ADC_DR_RDATA_Pos)      /*!< 0x00000040 */
6111 #define ADC_DR_RDATA_7                 (0x00000080UL << ADC_DR_RDATA_Pos)      /*!< 0x00000080 */
6112 #define ADC_DR_RDATA_8                 (0x00000100UL << ADC_DR_RDATA_Pos)      /*!< 0x00000100 */
6113 #define ADC_DR_RDATA_9                 (0x00000200UL << ADC_DR_RDATA_Pos)      /*!< 0x00000200 */
6114 #define ADC_DR_RDATA_10                (0x00000400UL << ADC_DR_RDATA_Pos)      /*!< 0x00000400 */
6115 #define ADC_DR_RDATA_11                (0x00000800UL << ADC_DR_RDATA_Pos)      /*!< 0x00000800 */
6116 #define ADC_DR_RDATA_12                (0x00001000UL << ADC_DR_RDATA_Pos)      /*!< 0x00001000 */
6117 #define ADC_DR_RDATA_13                (0x00002000UL << ADC_DR_RDATA_Pos)      /*!< 0x00002000 */
6118 #define ADC_DR_RDATA_14                (0x00004000UL << ADC_DR_RDATA_Pos)      /*!< 0x00004000 */
6119 #define ADC_DR_RDATA_15                (0x00008000UL << ADC_DR_RDATA_Pos)      /*!< 0x00008000 */
6120 #define ADC_DR_RDATA_16                (0x00010000UL << ADC_DR_RDATA_Pos)      /*!< 0x00010000 */
6121 #define ADC_DR_RDATA_17                (0x00020000UL << ADC_DR_RDATA_Pos)      /*!< 0x00020000 */
6122 #define ADC_DR_RDATA_18                (0x00040000UL << ADC_DR_RDATA_Pos)      /*!< 0x00040000 */
6123 #define ADC_DR_RDATA_19                (0x00080000UL << ADC_DR_RDATA_Pos)      /*!< 0x00080000 */
6124 #define ADC_DR_RDATA_20                (0x00100000UL << ADC_DR_RDATA_Pos)      /*!< 0x00100000 */
6125 #define ADC_DR_RDATA_21                (0x00200000UL << ADC_DR_RDATA_Pos)      /*!< 0x00200000 */
6126 #define ADC_DR_RDATA_22                (0x00400000UL << ADC_DR_RDATA_Pos)      /*!< 0x00400000 */
6127 #define ADC_DR_RDATA_23                (0x00800000UL << ADC_DR_RDATA_Pos)      /*!< 0x00800000 */
6128 #define ADC_DR_RDATA_24                (0x01000000UL << ADC_DR_RDATA_Pos)      /*!< 0x01000000 */
6129 #define ADC_DR_RDATA_25                (0x02000000UL << ADC_DR_RDATA_Pos)      /*!< 0x02000000 */
6130 #define ADC_DR_RDATA_26                (0x04000000UL << ADC_DR_RDATA_Pos)      /*!< 0x04000000 */
6131 #define ADC_DR_RDATA_27                (0x08000000UL << ADC_DR_RDATA_Pos)      /*!< 0x08000000 */
6132 #define ADC_DR_RDATA_28                (0x10000000UL << ADC_DR_RDATA_Pos)      /*!< 0x10000000 */
6133 #define ADC_DR_RDATA_29                (0x20000000UL << ADC_DR_RDATA_Pos)      /*!< 0x20000000 */
6134 #define ADC_DR_RDATA_30                (0x40000000UL << ADC_DR_RDATA_Pos)      /*!< 0x40000000 */
6135 #define ADC_DR_RDATA_31                (0x80000000UL << ADC_DR_RDATA_Pos)      /*!< 0x80000000 */
6136 
6137 /********************  Bit definition for ADC_JSQR register  ******************/
6138 #define ADC_JSQR_JL_Pos                (0U)
6139 #define ADC_JSQR_JL_Msk                (0x3UL << ADC_JSQR_JL_Pos)              /*!< 0x00000003 */
6140 #define ADC_JSQR_JL                    ADC_JSQR_JL_Msk                         /*!< ADC group injected sequencer scan length */
6141 #define ADC_JSQR_JL_0                  (0x1UL << ADC_JSQR_JL_Pos)              /*!< 0x00000001 */
6142 #define ADC_JSQR_JL_1                  (0x2UL << ADC_JSQR_JL_Pos)              /*!< 0x00000002 */
6143 
6144 #define ADC_JSQR_JEXTSEL_Pos           (2U)
6145 #define ADC_JSQR_JEXTSEL_Msk           (0x1FUL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x0000007C */
6146 #define ADC_JSQR_JEXTSEL               ADC_JSQR_JEXTSEL_Msk                    /*!< ADC group injected external trigger source */
6147 #define ADC_JSQR_JEXTSEL_0             (0x01UL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x00000004 */
6148 #define ADC_JSQR_JEXTSEL_1             (0x02UL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x00000008 */
6149 #define ADC_JSQR_JEXTSEL_2             (0x04UL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x00000010 */
6150 #define ADC_JSQR_JEXTSEL_3             (0x08UL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x00000020 */
6151 #define ADC_JSQR_JEXTSEL_4             (0x10UL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x00000040 */
6152 
6153 #define ADC_JSQR_JEXTEN_Pos            (7U)
6154 #define ADC_JSQR_JEXTEN_Msk            (0x3UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000180 */
6155 #define ADC_JSQR_JEXTEN                ADC_JSQR_JEXTEN_Msk                     /*!< ADC group injected external trigger polarity */
6156 #define ADC_JSQR_JEXTEN_0              (0x1UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000080 */
6157 #define ADC_JSQR_JEXTEN_1              (0x2UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000100 */
6158 
6159 #define ADC_JSQR_JSQ1_Pos              (9U)
6160 #define ADC_JSQR_JSQ1_Msk              (0x1FUL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00003E00 */
6161 #define ADC_JSQR_JSQ1                  ADC_JSQR_JSQ1_Msk                       /*!< ADC group injected sequencer rank 1 */
6162 #define ADC_JSQR_JSQ1_0                (0x01UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000200 */
6163 #define ADC_JSQR_JSQ1_1                (0x02UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000400 */
6164 #define ADC_JSQR_JSQ1_2                (0x04UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000800 */
6165 #define ADC_JSQR_JSQ1_3                (0x08UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00001000 */
6166 #define ADC_JSQR_JSQ1_4                (0x10UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00002000 */
6167 
6168 #define ADC_JSQR_JSQ2_Pos              (15U)
6169 #define ADC_JSQR_JSQ2_Msk              (0x1FUL << ADC_JSQR_JSQ2_Pos)           /*!< 0x000F8000 */
6170 #define ADC_JSQR_JSQ2                  ADC_JSQR_JSQ2_Msk                       /*!< ADC group injected sequencer rank 2 */
6171 #define ADC_JSQR_JSQ2_0                (0x01UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00008000 */
6172 #define ADC_JSQR_JSQ2_1                (0x02UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00010000 */
6173 #define ADC_JSQR_JSQ2_2                (0x04UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00020000 */
6174 #define ADC_JSQR_JSQ2_3                (0x08UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00040000 */
6175 #define ADC_JSQR_JSQ2_4                (0x10UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00080000 */
6176 
6177 #define ADC_JSQR_JSQ3_Pos              (21U)
6178 #define ADC_JSQR_JSQ3_Msk              (0x1FUL << ADC_JSQR_JSQ3_Pos)           /*!< 0x03E00000 */
6179 #define ADC_JSQR_JSQ3                  ADC_JSQR_JSQ3_Msk                       /*!< ADC group injected sequencer rank 3 */
6180 #define ADC_JSQR_JSQ3_0                (0x01UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00200000 */
6181 #define ADC_JSQR_JSQ3_1                (0x02UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00400000 */
6182 #define ADC_JSQR_JSQ3_2                (0x04UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00800000 */
6183 #define ADC_JSQR_JSQ3_3                (0x08UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x01000000 */
6184 #define ADC_JSQR_JSQ3_4                (0x10UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x02000000 */
6185 
6186 #define ADC_JSQR_JSQ4_Pos              (27U)
6187 #define ADC_JSQR_JSQ4_Msk              (0x1FUL << ADC_JSQR_JSQ4_Pos)           /*!< 0xF8000000 */
6188 #define ADC_JSQR_JSQ4                  ADC_JSQR_JSQ4_Msk                       /*!< ADC group injected sequencer rank 4 */
6189 #define ADC_JSQR_JSQ4_0                (0x01UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x08000000 */
6190 #define ADC_JSQR_JSQ4_1                (0x02UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x10000000 */
6191 #define ADC_JSQR_JSQ4_2                (0x04UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x20000000 */
6192 #define ADC_JSQR_JSQ4_3                (0x08UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x40000000 */
6193 #define ADC_JSQR_JSQ4_4                (0x10UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x80000000 */
6194 
6195 /********************  Bit definition for ADC_OFCFGR1 register  ***************/
6196 #define ADC_OFCFGR1_POSOFF_Pos         (24U)
6197 #define ADC_OFCFGR1_POSOFF_Msk         (0x01UL << ADC_OFCFGR1_POSOFF_Pos)      /*!< 0x01000000 */
6198 #define ADC_OFCFGR1_POSOFF             ADC_OFCFGR1_POSOFF_Msk                  /*!< ADC offset instance 1 positive offset enable */
6199 
6200 #define ADC_OFCFGR1_USAT_Pos           (25U)
6201 #define ADC_OFCFGR1_USAT_Msk           (0x01UL << ADC_OFCFGR1_USAT_Pos)        /*!< 0x02000000 */
6202 #define ADC_OFCFGR1_USAT               ADC_OFCFGR1_USAT_Msk                    /*!< ADC offset instance 1  unsigned saturation value */
6203 
6204 #define ADC_OFCFGR1_SSAT_Pos           (26U)
6205 #define ADC_OFCFGR1_SSAT_Msk           (0x01UL << ADC_OFCFGR1_SSAT_Pos)        /*!< 0x04000000 */
6206 #define ADC_OFCFGR1_SSAT               ADC_OFCFGR1_SSAT_Msk                    /*!< ADC offset instance 1 signed satuaration enable */
6207 
6208 #define ADC_OFCFGR1_OFFSET_CH_Pos      (27U)
6209 #define ADC_OFCFGR1_OFFSET_CH_Msk      (0x1FUL << ADC_OFCFGR1_OFFSET_CH_Pos)   /*!< 0xF8000000 */
6210 #define ADC_OFCFGR1_OFFSET_CH          ADC_OFCFGR1_OFFSET_CH_Msk               /*!< ADC offset instance 1 channel selection */
6211 #define ADC_OFCFGR1_OFFSET_CH_0        (0x01UL << ADC_OFCFGR1_OFFSET1_CH_Pos)  /*!< 0x08000000 */
6212 #define ADC_OFCFGR1_OFFSET_CH_1        (0x02UL << ADC_OFCFGR1_OFFSET1_CH_Pos)  /*!< 0x10000000 */
6213 #define ADC_OFCFGR1_OFFSET_CH_2        (0x03UL << ADC_OFCFGR1_OFFSET1_CH_Pos)  /*!< 0x20000000 */
6214 #define ADC_OFCFGR1_OFFSET_CH_3        (0x04UL << ADC_OFCFGR1_OFFSET1_CH_Pos)  /*!< 0x40000000 */
6215 #define ADC_OFCFGR1_OFFSET_CH_4        (0x05UL << ADC_OFCFGR1_OFFSET1_CH_Pos)  /*!< 0x80000000 */
6216 
6217 /********************  Bit definition for ADC_OFCFGR2 register  ***************/
6218 #define ADC_OFCFGR2_POSOFF_Pos         (24U)
6219 #define ADC_OFCFGR2_POSOFF_Msk         (0x01UL << ADC_OFCFGR2_POSOFF_Pos)      /*!< 0x01000000 */
6220 #define ADC_OFCFGR2_POSOFF             ADC_OFCFGR2_POSOFF_Msk                  /*!< ADC offset instance 2 positive offset enable */
6221 
6222 #define ADC_OFCFGR2_USAT_Pos           (25U)
6223 #define ADC_OFCFGR2_USAT_Msk           (0x01UL << ADC_OFCFGR2_USAT_Pos)        /*!< 0x02000000 */
6224 #define ADC_OFCFGR2_USAT               ADC_OFCFGR2_USAT_Msk                    /*!< ADC offset instance 2 unsigned saturation value */
6225 
6226 #define ADC_OFCFGR2_SSAT_Pos           (26U)
6227 #define ADC_OFCFGR2_SSAT_Msk           (0x01UL << ADC_OFCFGR2_SSAT_Pos)        /*!< 0x04000000 */
6228 #define ADC_OFCFGR2_SSAT               ADC_OFCFGR2_SSAT_Msk                    /*!< ADC offset instance 2 signed satuaration enable */
6229 
6230 #define ADC_OFCFGR2_OFFSET_CH_Pos      (27U)
6231 #define ADC_OFCFGR2_OFFSET_CH_Msk      (0x1FUL << ADC_OFCFGR2_OFFSET_CH_Pos)   /*!< 0xF8000000 */
6232 #define ADC_OFCFGR2_OFFSET_CH          ADC_OFCFGR2_OFFSET_CH_Msk               /*!< ADC offset instance 2 channel selection */
6233 #define ADC_OFCFGR2_OFFSET_CH_0        (0x01UL << ADC_OFCFGR2_OFFSET2_CH_Pos)  /*!< 0x08000000 */
6234 #define ADC_OFCFGR2_OFFSET_CH_1        (0x02UL << ADC_OFCFGR2_OFFSET2_CH_Pos)  /*!< 0x10000000 */
6235 #define ADC_OFCFGR2_OFFSET_CH_2        (0x03UL << ADC_OFCFGR2_OFFSET2_CH_Pos)  /*!< 0x20000000 */
6236 #define ADC_OFCFGR2_OFFSET_CH_3        (0x04UL << ADC_OFCFGR2_OFFSET2_CH_Pos)  /*!< 0x40000000 */
6237 #define ADC_OFCFGR2_OFFSET_CH_4        (0x05UL << ADC_OFCFGR2_OFFSET1_CH_Pos)  /*!< 0x80000000 */
6238 
6239 /********************  Bit definition for ADC_OFCFGR3 register  ***************/
6240 #define ADC_OFCFGR3_POSOFF_Pos         (24U)
6241 #define ADC_OFCFGR3_POSOFF_Msk         (0x01UL << ADC_OFCFGR3_POSOFF_Pos)      /*!< 0x01000000 */
6242 #define ADC_OFCFGR3_POSOFF             ADC_OFCFGR3_POSOFF_Msk                  /*!< ADC offset instance 3 positive offset enable */
6243 
6244 #define ADC_OFCFGR3_USAT_Pos           (25U)
6245 #define ADC_OFCFGR3_USAT_Msk           (0x01UL << ADC_OFCFGR3_USAT_Pos)        /*!< 0x02000000 */
6246 #define ADC_OFCFGR3_USAT               ADC_OFCFGR3_USAT_Msk                    /*!< ADC offset instance 3 unsigned saturation value */
6247 
6248 #define ADC_OFCFGR3_SSAT_Pos           (26U)
6249 #define ADC_OFCFGR3_SSAT_Msk           (0x01UL << ADC_OFCFGR3_SSAT_Pos)        /*!< 0x04000000 */
6250 #define ADC_OFCFGR3_SSAT               ADC_OFCFGR3_SSAT_Msk                    /*!< ADC offset instance 3 signed satuaration enable */
6251 
6252 #define ADC_OFCFGR3_OFFSET_CH_Pos      (27U)
6253 #define ADC_OFCFGR3_OFFSET_CH_Msk      (0x1FUL << ADC_OFCFGR3_OFFSET_CH_Pos)   /*!< 0xF8000000 */
6254 #define ADC_OFCFGR3_OFFSET_CH          ADC_OFCFGR3_OFFSET_CH_Msk               /*!< ADC offset instance 3 channel selection for the data offset */
6255 #define ADC_OFCFGR3_OFFSET_CH_0        (0x01UL << ADC_OFCFGR3_OFFSET3_CH_Pos)  /*!< 0x08000000 */
6256 #define ADC_OFCFGR3_OFFSET_CH_1        (0x02UL << ADC_OFCFGR3_OFFSET3_CH_Pos)  /*!< 0x10000000 */
6257 #define ADC_OFCFGR3_OFFSET_CH_2        (0x03UL << ADC_OFCFGR3_OFFSET3_CH_Pos)  /*!< 0x20000000 */
6258 #define ADC_OFCFGR3_OFFSET_CH_3        (0x04UL << ADC_OFCFGR3_OFFSET3_CH_Pos)  /*!< 0x40000000 */
6259 #define ADC_OFCFGR3_OFFSET_CH_4        (0x05UL << ADC_OFCFGR3_OFFSET3_CH_Pos)  /*!< 0x80000000 */
6260 
6261 /********************  Bit definition for ADC_OFCFGR4 register  ***************/
6262 #define ADC_OFCFGR4_POSOFF_Pos         (24U)
6263 #define ADC_OFCFGR4_POSOFF_Msk         (0x01UL << ADC_OFCFGR4_POSOFF_Pos)      /*!< 0x01000000 */
6264 #define ADC_OFCFGR4_POSOFF             ADC_OFCFGR4_POSOFF_Msk                  /*!< ADC offset instance 4 positive offset enable */
6265 
6266 #define ADC_OFCFGR4_USAT_Pos           (25U)
6267 #define ADC_OFCFGR4_USAT_Msk           (0x01UL << ADC_OFCFGR4_USAT_Pos)        /*!< 0x02000000 */
6268 #define ADC_OFCFGR4_USAT               ADC_OFCFGR4_USAT_Msk                    /*!< ADC offset instance 4 unsigned saturation value */
6269 
6270 #define ADC_OFCFGR4_SSAT_Pos           (26U)
6271 #define ADC_OFCFGR4_SSAT_Msk           (0x01UL << ADC_OFCFGR4_SSAT_Pos)        /*!< 0x04000000 */
6272 #define ADC_OFCFGR4_SSAT               ADC_OFCFGR4_SSAT_Msk                    /*!< ADC offset instance 4 signed satuaration enable */
6273 
6274 #define ADC_OFCFGR4_OFFSET_CH_Pos      (27U)
6275 #define ADC_OFCFGR4_OFFSET_CH_Msk      (0x1FUL << ADC_OFCFGR4_OFFSET_CH_Pos)   /*!< 0xF8000000 */
6276 #define ADC_OFCFGR4_OFFSET_CH          ADC_OFCFGR4_OFFSET_CH_Msk               /*!< ADC offset instance 4 channel selection for the data offset */
6277 #define ADC_OFCFGR4_OFFSET_CH_0        (0x01UL << ADC_OFCFGR4_OFFSET4_CH_Pos)  /*!< 0x08000000 */
6278 #define ADC_OFCFGR4_OFFSET_CH_1        (0x02UL << ADC_OFCFGR4_OFFSET4_CH_Pos)  /*!< 0x10000000 */
6279 #define ADC_OFCFGR4_OFFSET_CH_2        (0x03UL << ADC_OFCFGR4_OFFSET4_CH_Pos)  /*!< 0x20000000 */
6280 #define ADC_OFCFGR4_OFFSET_CH_3        (0x04UL << ADC_OFCFGR4_OFFSET4_CH_Pos)  /*!< 0x40000000 */
6281 #define ADC_OFCFGR4_OFFSET_CH_4        (0x05UL << ADC_OFCFGR4_OFFSET4_CH_Pos)  /*!< 0x80000000 */
6282 
6283 /********************  Bit definition for ADC_OFR1 register  ******************/
6284 #define ADC_OFR1_OFFSET_Pos            (0U)
6285 #define ADC_OFR1_OFFSET_Msk            (0x03FFFFFUL << ADC_OFR1_OFFSET_Pos)    /*!< 0x003FFFFF */
6286 #define ADC_OFR1_OFFSET                ADC_OFR1_OFFSET_Msk                     /*!< ADC offset instance 1 offset level */
6287 #define ADC_OFR1_OFFSET_0              (0x0000001UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000001 */
6288 #define ADC_OFR1_OFFSET_1              (0x0000002UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000002 */
6289 #define ADC_OFR1_OFFSET_2              (0x0000004UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000004 */
6290 #define ADC_OFR1_OFFSET_3              (0x0000008UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000008 */
6291 #define ADC_OFR1_OFFSET_4              (0x0000010UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000010 */
6292 #define ADC_OFR1_OFFSET_5              (0x0000020UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000020 */
6293 #define ADC_OFR1_OFFSET_6              (0x0000040UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000040 */
6294 #define ADC_OFR1_OFFSET_7              (0x0000080UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000080 */
6295 #define ADC_OFR1_OFFSET_8              (0x0000100UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000100 */
6296 #define ADC_OFR1_OFFSET_9              (0x0000200UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000200 */
6297 #define ADC_OFR1_OFFSET_10             (0x0000400UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000400 */
6298 #define ADC_OFR1_OFFSET_11             (0x0000800UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000800 */
6299 #define ADC_OFR1_OFFSET_12             (0x0001000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00001000 */
6300 #define ADC_OFR1_OFFSET_13             (0x0002000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00002000 */
6301 #define ADC_OFR1_OFFSET_14             (0x0004000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00004000 */
6302 #define ADC_OFR1_OFFSET_15             (0x0008000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00008000 */
6303 #define ADC_OFR1_OFFSET_16             (0x0010000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00010000 */
6304 #define ADC_OFR1_OFFSET_17             (0x0020000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00020000 */
6305 #define ADC_OFR1_OFFSET_18             (0x0040000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00040000 */
6306 #define ADC_OFR1_OFFSET_19             (0x0080000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00080000 */
6307 #define ADC_OFR1_OFFSET_20             (0x0100000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00100000 */
6308 #define ADC_OFR1_OFFSET_21             (0x0200000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00200000 */
6309 
6310 /********************  Bit definition for ADC_OFR2 register  ******************/
6311 #define ADC_OFR2_OFFSET_Pos            (0U)
6312 #define ADC_OFR2_OFFSET_Msk            (0x03FFFFFUL << ADC_OFR2_OFFSET_Pos)    /*!< 0x003FFFFF */
6313 #define ADC_OFR2_OFFSET                ADC_OFR2_OFFSET_Msk                     /*!< ADC offset instance 2 offset level */
6314 #define ADC_OFR2_OFFSET_0              (0x0000001UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000001 */
6315 #define ADC_OFR2_OFFSET_1              (0x0000002UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000002 */
6316 #define ADC_OFR2_OFFSET_2              (0x0000004UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000004 */
6317 #define ADC_OFR2_OFFSET_3              (0x0000008UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000008 */
6318 #define ADC_OFR2_OFFSET_4              (0x0000010UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000010 */
6319 #define ADC_OFR2_OFFSET_5              (0x0000020UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000020 */
6320 #define ADC_OFR2_OFFSET_6              (0x0000040UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000040 */
6321 #define ADC_OFR2_OFFSET_7              (0x0000080UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000080 */
6322 #define ADC_OFR2_OFFSET_8              (0x0000100UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000100 */
6323 #define ADC_OFR2_OFFSET_9              (0x0000200UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000200 */
6324 #define ADC_OFR2_OFFSET_10             (0x0000400UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000400 */
6325 #define ADC_OFR2_OFFSET_11             (0x0000800UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000800 */
6326 #define ADC_OFR2_OFFSET_12             (0x0001000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00001000 */
6327 #define ADC_OFR2_OFFSET_13             (0x0002000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00002000 */
6328 #define ADC_OFR2_OFFSET_14             (0x0004000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00004000 */
6329 #define ADC_OFR2_OFFSET_15             (0x0008000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00008000 */
6330 #define ADC_OFR2_OFFSET_16             (0x0010000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00010000 */
6331 #define ADC_OFR2_OFFSET_17             (0x0020000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00020000 */
6332 #define ADC_OFR2_OFFSET_18             (0x0040000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00040000 */
6333 #define ADC_OFR2_OFFSET_19             (0x0080000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00080000 */
6334 #define ADC_OFR2_OFFSET_20             (0x0100000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00100000 */
6335 #define ADC_OFR2_OFFSET_21             (0x0200000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00200000 */
6336 
6337 /********************  Bit definition for ADC_OFR3 register  ******************/
6338 #define ADC_OFR3_OFFSET_Pos            (0U)
6339 #define ADC_OFR3_OFFSET_Msk            (0x03FFFFFUL << ADC_OFR3_OFFSET_Pos)    /*!< 0x003FFFFF */
6340 #define ADC_OFR3_OFFSET                ADC_OFR3_OFFSET_Msk                     /*!< ADC offset instance 3 offset level */
6341 #define ADC_OFR3_OFFSET_0              (0x0000001UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000001 */
6342 #define ADC_OFR3_OFFSET_1              (0x0000002UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000002 */
6343 #define ADC_OFR3_OFFSET_2              (0x0000004UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000004 */
6344 #define ADC_OFR3_OFFSET_3              (0x0000008UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000008 */
6345 #define ADC_OFR3_OFFSET_4              (0x0000010UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000010 */
6346 #define ADC_OFR3_OFFSET_5              (0x0000020UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000020 */
6347 #define ADC_OFR3_OFFSET_6              (0x0000040UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000040 */
6348 #define ADC_OFR3_OFFSET_7              (0x0000080UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000080 */
6349 #define ADC_OFR3_OFFSET_8              (0x0000100UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000100 */
6350 #define ADC_OFR3_OFFSET_9              (0x0000200UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000200 */
6351 #define ADC_OFR3_OFFSET_10             (0x0000400UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000400 */
6352 #define ADC_OFR3_OFFSET_11             (0x0000800UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000800 */
6353 #define ADC_OFR3_OFFSET_12             (0x0001000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00001000 */
6354 #define ADC_OFR3_OFFSET_13             (0x0002000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00002000 */
6355 #define ADC_OFR3_OFFSET_14             (0x0004000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00004000 */
6356 #define ADC_OFR3_OFFSET_15             (0x0008000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00008000 */
6357 #define ADC_OFR3_OFFSET_16             (0x0010000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00010000 */
6358 #define ADC_OFR3_OFFSET_17             (0x0020000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00020000 */
6359 #define ADC_OFR3_OFFSET_18             (0x0040000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00040000 */
6360 #define ADC_OFR3_OFFSET_19             (0x0080000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00080000 */
6361 #define ADC_OFR3_OFFSET_20             (0x0100000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00100000 */
6362 #define ADC_OFR3_OFFSET_21             (0x0200000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00200000 */
6363 
6364 /********************  Bit definition for ADC_OFR4 register  ******************/
6365 #define ADC_OFR4_OFFSET_Pos            (0U)
6366 #define ADC_OFR4_OFFSET_Msk            (0x03FFFFFUL << ADC_OFR4_OFFSET_Pos)    /*!< 0x003FFFFF */
6367 #define ADC_OFR4_OFFSET                ADC_OFR4_OFFSET_Msk                     /*!< ADC offset instance 4 offset level */
6368 #define ADC_OFR4_OFFSET_0              (0x0000001UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000001 */
6369 #define ADC_OFR4_OFFSET_1              (0x0000002UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000002 */
6370 #define ADC_OFR4_OFFSET_2              (0x0000004UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000004 */
6371 #define ADC_OFR4_OFFSET_3              (0x0000008UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000008 */
6372 #define ADC_OFR4_OFFSET_4              (0x0000010UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000010 */
6373 #define ADC_OFR4_OFFSET_5              (0x0000020UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000020 */
6374 #define ADC_OFR4_OFFSET_6              (0x0000040UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000040 */
6375 #define ADC_OFR4_OFFSET_7              (0x0000080UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000080 */
6376 #define ADC_OFR4_OFFSET_8              (0x0000100UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000100 */
6377 #define ADC_OFR4_OFFSET_9              (0x0000200UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000200 */
6378 #define ADC_OFR4_OFFSET_10             (0x0000400UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000400 */
6379 #define ADC_OFR4_OFFSET_11             (0x0000800UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000800 */
6380 #define ADC_OFR4_OFFSET_12             (0x0001000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00001000 */
6381 #define ADC_OFR4_OFFSET_13             (0x0002000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00002000 */
6382 #define ADC_OFR4_OFFSET_14             (0x0004000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00004000 */
6383 #define ADC_OFR4_OFFSET_15             (0x0008000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00008000 */
6384 #define ADC_OFR4_OFFSET_16             (0x0010000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00010000 */
6385 #define ADC_OFR4_OFFSET_17             (0x0020000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00020000 */
6386 #define ADC_OFR4_OFFSET_18             (0x0040000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00040000 */
6387 #define ADC_OFR4_OFFSET_19             (0x0080000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00080000 */
6388 #define ADC_OFR4_OFFSET_20             (0x0100000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00100000 */
6389 #define ADC_OFR4_OFFSET_21             (0x0200000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00200000 */
6390 
6391 /********************  Bit definition for ADC_GCOMP register  *****************/
6392 #define ADC_GCOMP_GCOMPCOEFF_Pos       (0U)
6393 #define ADC_GCOMP_GCOMPCOEFF_Msk       (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)  /*!< 0x00003FFF */
6394 #define ADC_GCOMP_GCOMPCOEFF           ADC_GCOMP_GCOMPCOEFF_Msk                /*!< Gain compensation coefficient */
6395 #define ADC_GCOMP_GCOMP_Pos            (31U)
6396 #define ADC_GCOMP_GCOMP_Msk            (0x1UL << ADC_GCOMP_GCOMP_Pos)          /*!< 0x80000000 */
6397 #define ADC_GCOMP_GCOMP                ADC_GCOMP_GCOMP_Msk                     /*!< Gain compensation mode */
6398 
6399 /********************  Bit definition for ADC_JDR1 register  ******************/
6400 #define ADC_JDR1_JDATA_Pos             (0U)
6401 #define ADC_JDR1_JDATA_Msk             (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos)    /*!< 0xFFFFFFFF */
6402 #define ADC_JDR1_JDATA                 ADC_JDR1_JDATA_Msk                      /*!< ADC group injected sequencer rank 1 conversion data */
6403 #define ADC_JDR1_JDATA_0               (0x00000001UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000001 */
6404 #define ADC_JDR1_JDATA_1               (0x00000002UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000002 */
6405 #define ADC_JDR1_JDATA_2               (0x00000004UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000004 */
6406 #define ADC_JDR1_JDATA_3               (0x00000008UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000008 */
6407 #define ADC_JDR1_JDATA_4               (0x00000010UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000010 */
6408 #define ADC_JDR1_JDATA_5               (0x00000020UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000020 */
6409 #define ADC_JDR1_JDATA_6               (0x00000040UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000040 */
6410 #define ADC_JDR1_JDATA_7               (0x00000080UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000080 */
6411 #define ADC_JDR1_JDATA_8               (0x00000100UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000100 */
6412 #define ADC_JDR1_JDATA_9               (0x00000200UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000200 */
6413 #define ADC_JDR1_JDATA_10              (0x00000400UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000400 */
6414 #define ADC_JDR1_JDATA_11              (0x00000800UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000800 */
6415 #define ADC_JDR1_JDATA_12              (0x00001000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00001000 */
6416 #define ADC_JDR1_JDATA_13              (0x00002000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00002000 */
6417 #define ADC_JDR1_JDATA_14              (0x00004000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00004000 */
6418 #define ADC_JDR1_JDATA_15              (0x00008000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00008000 */
6419 #define ADC_JDR1_JDATA_16              (0x00010000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00010000 */
6420 #define ADC_JDR1_JDATA_17              (0x00020000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00020000 */
6421 #define ADC_JDR1_JDATA_18              (0x00040000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00040000 */
6422 #define ADC_JDR1_JDATA_19              (0x00080000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00080000 */
6423 #define ADC_JDR1_JDATA_20              (0x00100000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00100000 */
6424 #define ADC_JDR1_JDATA_21              (0x00200000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00200000 */
6425 #define ADC_JDR1_JDATA_22              (0x00400000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00400000 */
6426 #define ADC_JDR1_JDATA_23              (0x00800000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00800000 */
6427 #define ADC_JDR1_JDATA_24              (0x01000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x01000000 */
6428 #define ADC_JDR1_JDATA_25              (0x02000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x02000000 */
6429 #define ADC_JDR1_JDATA_26              (0x04000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x04000000 */
6430 #define ADC_JDR1_JDATA_27              (0x08000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x08000000 */
6431 #define ADC_JDR1_JDATA_28              (0x10000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x10000000 */
6432 #define ADC_JDR1_JDATA_29              (0x20000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x20000000 */
6433 #define ADC_JDR1_JDATA_30              (0x40000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x40000000 */
6434 #define ADC_JDR1_JDATA_31              (0x80000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x80000000 */
6435 
6436 /********************  Bit definition for ADC_JDR2 register  ********************/
6437 #define ADC_JDR2_JDATA_Pos             (0U)
6438 #define ADC_JDR2_JDATA_Msk             (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos)    /*!< 0xFFFFFFFF */
6439 #define ADC_JDR2_JDATA                 ADC_JDR2_JDATA_Msk                      /*!< ADC group injected sequencer rank 2 conversion data */
6440 #define ADC_JDR2_JDATA_0               (0x00000001UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000001 */
6441 #define ADC_JDR2_JDATA_1               (0x00000002UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000002 */
6442 #define ADC_JDR2_JDATA_2               (0x00000004UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000004 */
6443 #define ADC_JDR2_JDATA_3               (0x00000008UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000008 */
6444 #define ADC_JDR2_JDATA_4               (0x00000010UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000010 */
6445 #define ADC_JDR2_JDATA_5               (0x00000020UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000020 */
6446 #define ADC_JDR2_JDATA_6               (0x00000040UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000040 */
6447 #define ADC_JDR2_JDATA_7               (0x00000080UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000080 */
6448 #define ADC_JDR2_JDATA_8               (0x00000100UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000100 */
6449 #define ADC_JDR2_JDATA_9               (0x00000200UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000200 */
6450 #define ADC_JDR2_JDATA_10              (0x00000400UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000400 */
6451 #define ADC_JDR2_JDATA_11              (0x00000800UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000800 */
6452 #define ADC_JDR2_JDATA_12              (0x00001000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00001000 */
6453 #define ADC_JDR2_JDATA_13              (0x00002000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00002000 */
6454 #define ADC_JDR2_JDATA_14              (0x00004000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00004000 */
6455 #define ADC_JDR2_JDATA_15              (0x00008000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00008000 */
6456 #define ADC_JDR2_JDATA_16              (0x00010000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00010000 */
6457 #define ADC_JDR2_JDATA_17              (0x00020000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00020000 */
6458 #define ADC_JDR2_JDATA_18              (0x00040000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00040000 */
6459 #define ADC_JDR2_JDATA_19              (0x00080000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00080000 */
6460 #define ADC_JDR2_JDATA_20              (0x00100000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00100000 */
6461 #define ADC_JDR2_JDATA_21              (0x00200000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00200000 */
6462 #define ADC_JDR2_JDATA_22              (0x00400000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00400000 */
6463 #define ADC_JDR2_JDATA_23              (0x00800000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00800000 */
6464 #define ADC_JDR2_JDATA_24              (0x01000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x01000000 */
6465 #define ADC_JDR2_JDATA_25              (0x02000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x02000000 */
6466 #define ADC_JDR2_JDATA_26              (0x04000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x04000000 */
6467 #define ADC_JDR2_JDATA_27              (0x08000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x08000000 */
6468 #define ADC_JDR2_JDATA_28              (0x10000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x10000000 */
6469 #define ADC_JDR2_JDATA_29              (0x20000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x20000000 */
6470 #define ADC_JDR2_JDATA_30              (0x40000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x40000000 */
6471 #define ADC_JDR2_JDATA_31              (0x80000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x80000000 */
6472 
6473 /********************  Bit definition for ADC_JDR3 register  ********************/
6474 #define ADC_JDR3_JDATA_Pos             (0U)
6475 #define ADC_JDR3_JDATA_Msk             (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos)    /*!< 0xFFFFFFFF */
6476 #define ADC_JDR3_JDATA                 ADC_JDR3_JDATA_Msk                      /*!< ADC group injected sequencer rank 3 conversion data */
6477 #define ADC_JDR3_JDATA_0               (0x00000001UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000001 */
6478 #define ADC_JDR3_JDATA_1               (0x00000002UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000002 */
6479 #define ADC_JDR3_JDATA_2               (0x00000004UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000004 */
6480 #define ADC_JDR3_JDATA_3               (0x00000008UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000008 */
6481 #define ADC_JDR3_JDATA_4               (0x00000010UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000010 */
6482 #define ADC_JDR3_JDATA_5               (0x00000020UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000020 */
6483 #define ADC_JDR3_JDATA_6               (0x00000040UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000040 */
6484 #define ADC_JDR3_JDATA_7               (0x00000080UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000080 */
6485 #define ADC_JDR3_JDATA_8               (0x00000100UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000100 */
6486 #define ADC_JDR3_JDATA_9               (0x00000200UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000200 */
6487 #define ADC_JDR3_JDATA_10              (0x00000400UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000400 */
6488 #define ADC_JDR3_JDATA_11              (0x00000800UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000800 */
6489 #define ADC_JDR3_JDATA_12              (0x00001000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00001000 */
6490 #define ADC_JDR3_JDATA_13              (0x00002000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00002000 */
6491 #define ADC_JDR3_JDATA_14              (0x00004000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00004000 */
6492 #define ADC_JDR3_JDATA_15              (0x00008000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00008000 */
6493 #define ADC_JDR3_JDATA_16              (0x00010000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00010000 */
6494 #define ADC_JDR3_JDATA_17              (0x00020000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00020000 */
6495 #define ADC_JDR3_JDATA_18              (0x00040000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00040000 */
6496 #define ADC_JDR3_JDATA_19              (0x00080000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00080000 */
6497 #define ADC_JDR3_JDATA_20              (0x00100000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00100000 */
6498 #define ADC_JDR3_JDATA_21              (0x00200000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00200000 */
6499 #define ADC_JDR3_JDATA_22              (0x00400000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00400000 */
6500 #define ADC_JDR3_JDATA_23              (0x00800000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00800000 */
6501 #define ADC_JDR3_JDATA_24              (0x01000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x01000000 */
6502 #define ADC_JDR3_JDATA_25              (0x02000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x02000000 */
6503 #define ADC_JDR3_JDATA_26              (0x04000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x04000000 */
6504 #define ADC_JDR3_JDATA_27              (0x08000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x08000000 */
6505 #define ADC_JDR3_JDATA_28              (0x10000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x10000000 */
6506 #define ADC_JDR3_JDATA_29              (0x20000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x20000000 */
6507 #define ADC_JDR3_JDATA_30              (0x40000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x40000000 */
6508 #define ADC_JDR3_JDATA_31              (0x80000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x80000000 */
6509 
6510 /********************  Bit definition for ADC_JDR4 register  ********************/
6511 #define ADC_JDR4_JDATA_Pos             (0U)
6512 #define ADC_JDR4_JDATA_Msk             (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos)    /*!< 0xFFFFFFFF */
6513 #define ADC_JDR4_JDATA                 ADC_JDR4_JDATA_Msk                      /*!< ADC group injected sequencer rank 4 conversion data */
6514 #define ADC_JDR4_JDATA_0               (0x00000001UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000001 */
6515 #define ADC_JDR4_JDATA_1               (0x00000002UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000002 */
6516 #define ADC_JDR4_JDATA_2               (0x00000004UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000004 */
6517 #define ADC_JDR4_JDATA_3               (0x00000008UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000008 */
6518 #define ADC_JDR4_JDATA_4               (0x00000010UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000010 */
6519 #define ADC_JDR4_JDATA_5               (0x00000020UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000020 */
6520 #define ADC_JDR4_JDATA_6               (0x00000040UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000040 */
6521 #define ADC_JDR4_JDATA_7               (0x00000080UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000080 */
6522 #define ADC_JDR4_JDATA_8               (0x00000100UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000100 */
6523 #define ADC_JDR4_JDATA_9               (0x00000200UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000200 */
6524 #define ADC_JDR4_JDATA_10              (0x00000400UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000400 */
6525 #define ADC_JDR4_JDATA_11              (0x00000800UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000800 */
6526 #define ADC_JDR4_JDATA_12              (0x00001000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00001000 */
6527 #define ADC_JDR4_JDATA_13              (0x00002000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00002000 */
6528 #define ADC_JDR4_JDATA_14              (0x00004000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00004000 */
6529 #define ADC_JDR4_JDATA_15              (0x00008000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00008000 */
6530 #define ADC_JDR4_JDATA_16              (0x00010000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00010000 */
6531 #define ADC_JDR4_JDATA_17              (0x00020000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00020000 */
6532 #define ADC_JDR4_JDATA_18              (0x00040000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00040000 */
6533 #define ADC_JDR4_JDATA_19              (0x00080000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00080000 */
6534 #define ADC_JDR4_JDATA_20              (0x00100000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00100000 */
6535 #define ADC_JDR4_JDATA_21              (0x00200000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00200000 */
6536 #define ADC_JDR4_JDATA_22              (0x00400000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00400000 */
6537 #define ADC_JDR4_JDATA_23              (0x00800000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00800000 */
6538 #define ADC_JDR4_JDATA_24              (0x01000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x01000000 */
6539 #define ADC_JDR4_JDATA_25              (0x02000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x02000000 */
6540 #define ADC_JDR4_JDATA_26              (0x04000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x04000000 */
6541 #define ADC_JDR4_JDATA_27              (0x08000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x08000000 */
6542 #define ADC_JDR4_JDATA_28              (0x10000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x10000000 */
6543 #define ADC_JDR4_JDATA_29              (0x20000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x20000000 */
6544 #define ADC_JDR4_JDATA_30              (0x40000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x40000000 */
6545 #define ADC_JDR4_JDATA_31              (0x80000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x80000000 */
6546 
6547 /********************  Bit definition for ADC_AWD2CR register  ****************/
6548 #define ADC_AWD2CR_AWD2CH_Pos          (0U)
6549 #define ADC_AWD2CR_AWD2CH_Msk          (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x000FFFFF */
6550 #define ADC_AWD2CR_AWD2CH              ADC_AWD2CR_AWD2CH_Msk                   /*!< ADC analog watchdog 2 monitored channel selection */
6551 #define ADC_AWD2CR_AWD2CH_0            (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000001 */
6552 #define ADC_AWD2CR_AWD2CH_1            (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000002 */
6553 #define ADC_AWD2CR_AWD2CH_2            (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000004 */
6554 #define ADC_AWD2CR_AWD2CH_3            (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000008 */
6555 #define ADC_AWD2CR_AWD2CH_4            (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000010 */
6556 #define ADC_AWD2CR_AWD2CH_5            (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000020 */
6557 #define ADC_AWD2CR_AWD2CH_6            (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000040 */
6558 #define ADC_AWD2CR_AWD2CH_7            (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000080 */
6559 #define ADC_AWD2CR_AWD2CH_8            (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000100 */
6560 #define ADC_AWD2CR_AWD2CH_9            (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000200 */
6561 #define ADC_AWD2CR_AWD2CH_10           (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000400 */
6562 #define ADC_AWD2CR_AWD2CH_11           (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000800 */
6563 #define ADC_AWD2CR_AWD2CH_12           (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00001000 */
6564 #define ADC_AWD2CR_AWD2CH_13           (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00002000 */
6565 #define ADC_AWD2CR_AWD2CH_14           (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00004000 */
6566 #define ADC_AWD2CR_AWD2CH_15           (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00008000 */
6567 #define ADC_AWD2CR_AWD2CH_16           (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00010000 */
6568 #define ADC_AWD2CR_AWD2CH_17           (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00020000 */
6569 #define ADC_AWD2CR_AWD2CH_18           (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00040000 */
6570 #define ADC_AWD2CR_AWD2CH_19           (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00080000 */
6571 
6572 /********************  Bit definition for ADC_AWD3CR register  ****************/
6573 #define ADC_AWD3CR_AWD3CH_Pos          (0U)
6574 #define ADC_AWD3CR_AWD3CH_Msk          (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x000FFFFF */
6575 #define ADC_AWD3CR_AWD3CH              ADC_AWD3CR_AWD3CH_Msk                   /*!< ADC analog watchdog 3 monitored channel selection */
6576 #define ADC_AWD3CR_AWD3CH_0            (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000001 */
6577 #define ADC_AWD3CR_AWD3CH_1            (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000002 */
6578 #define ADC_AWD3CR_AWD3CH_2            (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000004 */
6579 #define ADC_AWD3CR_AWD3CH_3            (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000008 */
6580 #define ADC_AWD3CR_AWD3CH_4            (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000010 */
6581 #define ADC_AWD3CR_AWD3CH_5            (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000020 */
6582 #define ADC_AWD3CR_AWD3CH_6            (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000040 */
6583 #define ADC_AWD3CR_AWD3CH_7            (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000080 */
6584 #define ADC_AWD3CR_AWD3CH_8            (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000100 */
6585 #define ADC_AWD3CR_AWD3CH_9            (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000200 */
6586 #define ADC_AWD3CR_AWD3CH_10           (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000400 */
6587 #define ADC_AWD3CR_AWD3CH_11           (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000800 */
6588 #define ADC_AWD3CR_AWD3CH_12           (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00001000 */
6589 #define ADC_AWD3CR_AWD3CH_13           (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00002000 */
6590 #define ADC_AWD3CR_AWD3CH_14           (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00004000 */
6591 #define ADC_AWD3CR_AWD3CH_15           (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00008000 */
6592 #define ADC_AWD3CR_AWD3CH_16           (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00010000 */
6593 #define ADC_AWD3CR_AWD3CH_17           (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00020000 */
6594 #define ADC_AWD3CR_AWD3CH_18           (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00040000 */
6595 #define ADC_AWD3CR_AWD3CH_19           (0x80000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00080000 */
6596 
6597 /********************  Bit definition for ADC_AWD1TR_LT register  *************/
6598 #define ADC_AWD1LTR_LTR_Pos            (0U)
6599 #define ADC_AWD1LTR_LTR_Msk            (0x007FFFFFUL << ADC_AWD1LTR_LTR_Pos)  /*!< 0x007FFFFF */
6600 #define ADC_AWD1LTR_LTR                ADC_AWD1LTR_LTR_Msk                    /*!< ADC analog watchdog 1 threshold low */
6601 #define ADC_AWD1LTR_LTR_0              (0x000001UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000001 */
6602 #define ADC_AWD1LTR_LTR_1              (0x000002UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000002 */
6603 #define ADC_AWD1LTR_LTR_2              (0x000004UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000004 */
6604 #define ADC_AWD1LTR_LTR_3              (0x000008UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000008 */
6605 #define ADC_AWD1LTR_LTR_4              (0x000010UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000010 */
6606 #define ADC_AWD1LTR_LTR_5              (0x000020UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000020 */
6607 #define ADC_AWD1LTR_LTR_6              (0x000040UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000040 */
6608 #define ADC_AWD1LTR_LTR_7              (0x000080UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000080 */
6609 #define ADC_AWD1LTR_LTR_8              (0x000100UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000100 */
6610 #define ADC_AWD1LTR_LTR_9              (0x000200UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000200 */
6611 #define ADC_AWD1LTR_LTR_10             (0x000400UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000400 */
6612 #define ADC_AWD1LTR_LTR_11             (0x000800UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000800 */
6613 #define ADC_AWD1LTR_LTR_12             (0x001000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00001000 */
6614 #define ADC_AWD1LTR_LTR_13             (0x002000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00002000 */
6615 #define ADC_AWD1LTR_LTR_14             (0x004000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00004000 */
6616 #define ADC_AWD1LTR_LTR_15             (0x008000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00008000 */
6617 #define ADC_AWD1LTR_LTR_16             (0x010000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00010000 */
6618 #define ADC_AWD1LTR_LTR_17             (0x020000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00020000 */
6619 #define ADC_AWD1LTR_LTR_18             (0x040000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00040000 */
6620 #define ADC_AWD1LTR_LTR_19             (0x080000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00080000 */
6621 #define ADC_AWD1LTR_LTR_20             (0x100000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00100000 */
6622 #define ADC_AWD1LTR_LTR_21             (0x200000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00200000 */
6623 #define ADC_AWD1LTR_LTR_22             (0x400000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00400000 */
6624 
6625 /********************  Bit definition for ADC_AWD1TR_HT register  *******************/
6626 #define ADC_AWD1HTR_HTR_Pos            (0U)
6627 #define ADC_AWD1HTR_HTR_Msk            (0x007FFFFFUL << ADC_AWD1HTR_HTR_Pos)  /*!< 0x007FFFFF */
6628 #define ADC_AWD1HTR_HTR                ADC_AWD1HTR_HTR_Msk                    /*!< ADC analog watchdog 1 threshold high */
6629 #define ADC_AWD1HTR_HTR_0              (0x000001UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000001 */
6630 #define ADC_AWD1HTR_HTR_1              (0x000002UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000002 */
6631 #define ADC_AWD1HTR_HTR_2              (0x000004UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000004 */
6632 #define ADC_AWD1HTR_HTR_3              (0x000008UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000008 */
6633 #define ADC_AWD1HTR_HTR_4              (0x000010UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000010 */
6634 #define ADC_AWD1HTR_HTR_5              (0x000020UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000020 */
6635 #define ADC_AWD1HTR_HTR_6              (0x000040UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000040 */
6636 #define ADC_AWD1HTR_HTR_7              (0x000080UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000080 */
6637 #define ADC_AWD1HTR_HTR_8              (0x000100UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000100 */
6638 #define ADC_AWD1HTR_HTR_9              (0x000200UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000200 */
6639 #define ADC_AWD1HTR_HTR_10             (0x000400UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000400 */
6640 #define ADC_AWD1HTR_HTR_11             (0x000800UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000800 */
6641 #define ADC_AWD1HTR_HTR_12             (0x001000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00001000 */
6642 #define ADC_AWD1HTR_HTR_13             (0x002000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00002000 */
6643 #define ADC_AWD1HTR_HTR_14             (0x004000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00004000 */
6644 #define ADC_AWD1HTR_HTR_15             (0x008000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00008000 */
6645 #define ADC_AWD1HTR_HTR_16             (0x010000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00010000 */
6646 #define ADC_AWD1HTR_HTR_17             (0x020000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00020000 */
6647 #define ADC_AWD1HTR_HTR_18             (0x040000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00040000 */
6648 #define ADC_AWD1HTR_HTR_19             (0x080000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00080000 */
6649 #define ADC_AWD1HTR_HTR_20             (0x100000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00100000 */
6650 #define ADC_AWD1HTR_HTR_21             (0x200000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00200000 */
6651 #define ADC_AWD1HTR_HTR_22             (0x400000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00400000 */
6652 
6653 #define ADC_AWD1HTR_AWDFILT_Pos         (29U)
6654 #define ADC_AWD1HTR_AWDFILT_Msk         (0x7UL << ADC_AWD1HTR_AWDFILT_Pos)      /*!< 0x00000007 */
6655 #define ADC_AWD1HTR_AWDFILT             ADC_AWD1HTR_AWDFILT_Msk                 /*!< ADC analog watchdog 1 filtering */
6656 #define ADC_AWD1HTR_AWDFILT_0           (0x000001UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000001 */
6657 #define ADC_AWD1HTR_AWDFILT_1           (0x000002UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000002 */
6658 #define ADC_AWD1HTR_AWDFILT_2           (0x000004UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000004 */
6659 
6660 /********************  Bit definition for ADC_AWD2TR_LT register  *******************/
6661 #define ADC_AWD2LTR_LTR_Pos            (0U)
6662 #define ADC_AWD2LTR_LTR_Msk            (0x007FFFFFUL << ADC_AWD2LTR_LTR_Pos)  /*!< 0x007FFFFF */
6663 #define ADC_AWD2LTR_LTR                ADC_AWD2LTR_LTR_Msk                    /*!< ADC analog watchdog 2 threshold low */
6664 #define ADC_AWD2LTR_LTR_0              (0x000001UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000001 */
6665 #define ADC_AWD2LTR_LTR_1              (0x000002UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000002 */
6666 #define ADC_AWD2LTR_LTR_2              (0x000004UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000004 */
6667 #define ADC_AWD2LTR_LTR_3              (0x000008UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000008 */
6668 #define ADC_AWD2LTR_LTR_4              (0x000010UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000010 */
6669 #define ADC_AWD2LTR_LTR_5              (0x000020UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000020 */
6670 #define ADC_AWD2LTR_LTR_6              (0x000040UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000040 */
6671 #define ADC_AWD2LTR_LTR_7              (0x000080UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000080 */
6672 #define ADC_AWD2LTR_LTR_8              (0x000100UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000100 */
6673 #define ADC_AWD2LTR_LTR_9              (0x000200UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000200 */
6674 #define ADC_AWD2LTR_LTR_10             (0x000400UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000400 */
6675 #define ADC_AWD2LTR_LTR_11             (0x000800UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000800 */
6676 #define ADC_AWD2LTR_LTR_12             (0x001000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00001000 */
6677 #define ADC_AWD2LTR_LTR_13             (0x002000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00002000 */
6678 #define ADC_AWD2LTR_LTR_14             (0x004000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00004000 */
6679 #define ADC_AWD2LTR_LTR_15             (0x008000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00008000 */
6680 #define ADC_AWD2LTR_LTR_16             (0x010000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00010000 */
6681 #define ADC_AWD2LTR_LTR_17             (0x020000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00020000 */
6682 #define ADC_AWD2LTR_LTR_18             (0x040000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00040000 */
6683 #define ADC_AWD2LTR_LTR_19             (0x080000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00080000 */
6684 #define ADC_AWD2LTR_LTR_20             (0x100000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00100000 */
6685 #define ADC_AWD2LTR_LTR_21             (0x200000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00200000 */
6686 #define ADC_AWD2LTR_LTR_22             (0x400000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00400000 */
6687 
6688 /********************  Bit definition for ADC_AWD2TR_HT register  *******************/
6689 #define ADC_AWD2HTR_HTR_Pos            (0U)
6690 #define ADC_AWD2HTR_HTR_Msk            (0x007FFFFFUL << ADC_AWD2HTR_HTR_Pos)  /*!< 0x007FFFFF */
6691 #define ADC_AWD2HTR_HTR                ADC_AWD2HTR_HTR_Msk                    /*!< ADC analog watchdog 2 threshold high */
6692 #define ADC_AWD2HTR_HTR_0              (0x000001UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000001 */
6693 #define ADC_AWD2HTR_HTR_1              (0x000002UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000002 */
6694 #define ADC_AWD2HTR_HTR_2              (0x000004UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000004 */
6695 #define ADC_AWD2HTR_HTR_3              (0x000008UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000008 */
6696 #define ADC_AWD2HTR_HTR_4              (0x000010UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000010 */
6697 #define ADC_AWD2HTR_HTR_5              (0x000020UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000020 */
6698 #define ADC_AWD2HTR_HTR_6              (0x000040UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000040 */
6699 #define ADC_AWD2HTR_HTR_7              (0x000080UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000080 */
6700 #define ADC_AWD2HTR_HTR_8              (0x000100UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000100 */
6701 #define ADC_AWD2HTR_HTR_9              (0x000200UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000200 */
6702 #define ADC_AWD2HTR_HTR_10             (0x000400UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000400 */
6703 #define ADC_AWD2HTR_HTR_11             (0x000800UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000800 */
6704 #define ADC_AWD2HTR_HTR_12             (0x001000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00001000 */
6705 #define ADC_AWD2HTR_HTR_13             (0x002000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00002000 */
6706 #define ADC_AWD2HTR_HTR_14             (0x004000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00004000 */
6707 #define ADC_AWD2HTR_HTR_15             (0x008000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00008000 */
6708 #define ADC_AWD2HTR_HTR_16             (0x010000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00010000 */
6709 #define ADC_AWD2HTR_HTR_17             (0x020000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00020000 */
6710 #define ADC_AWD2HTR_HTR_18             (0x040000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00040000 */
6711 #define ADC_AWD2HTR_HTR_19             (0x080000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00080000 */
6712 #define ADC_AWD2HTR_HTR_20             (0x100000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00100000 */
6713 #define ADC_AWD2HTR_HTR_21             (0x200000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00200000 */
6714 #define ADC_AWD2HTR_HTR_22             (0x400000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00400000 */
6715 
6716 /********************  Bit definition for ADC_AWD3TR_LT register  *******************/
6717 #define ADC_AWD3LTR_LTR_Pos            (0U)
6718 #define ADC_AWD3LTR_LTR_Msk            (0x007FFFFFUL << ADC_AWD3LTR_LTR_Pos)  /*!< 0x007FFFFF */
6719 #define ADC_AWD3LTR_LTR                ADC_AWD3LTR_LTR_Msk                    /*!< ADC analog watchdog 3 threshold low */
6720 #define ADC_AWD3LTR_LTR_0              (0x000001UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000001 */
6721 #define ADC_AWD3LTR_LTR_1              (0x000002UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000002 */
6722 #define ADC_AWD3LTR_LTR_2              (0x000004UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000004 */
6723 #define ADC_AWD3LTR_LTR_3              (0x000008UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000008 */
6724 #define ADC_AWD3LTR_LTR_4              (0x000010UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000010 */
6725 #define ADC_AWD3LTR_LTR_5              (0x000020UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000020 */
6726 #define ADC_AWD3LTR_LTR_6              (0x000040UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000040 */
6727 #define ADC_AWD3LTR_LTR_7              (0x000080UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000080 */
6728 #define ADC_AWD3LTR_LTR_8              (0x000100UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000100 */
6729 #define ADC_AWD3LTR_LTR_9              (0x000200UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000200 */
6730 #define ADC_AWD3LTR_LTR_10             (0x000400UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000400 */
6731 #define ADC_AWD3LTR_LTR_11             (0x000800UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000800 */
6732 #define ADC_AWD3LTR_LTR_12             (0x001000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00001000 */
6733 #define ADC_AWD3LTR_LTR_13             (0x002000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00002000 */
6734 #define ADC_AWD3LTR_LTR_14             (0x004000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00004000 */
6735 #define ADC_AWD3LTR_LTR_15             (0x008000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00008000 */
6736 #define ADC_AWD3LTR_LTR_16             (0x010000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00010000 */
6737 #define ADC_AWD3LTR_LTR_17             (0x020000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00020000 */
6738 #define ADC_AWD3LTR_LTR_18             (0x040000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00040000 */
6739 #define ADC_AWD3LTR_LTR_19             (0x080000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00080000 */
6740 #define ADC_AWD3LTR_LTR_20             (0x100000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00100000 */
6741 #define ADC_AWD3LTR_LTR_21             (0x200000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00200000 */
6742 #define ADC_AWD3LTR_LTR_22             (0x400000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00400000 */
6743 
6744 /********************  Bit definition for ADC_AWD3TR_HT register  *******************/
6745 #define ADC_AWD3HTR_HTR_Pos            (0U)
6746 #define ADC_AWD3HTR_HTR_Msk            (0x007FFFFFUL << ADC_AWD3HTR_HTR_Pos)  /*!< 0x007FFFFF */
6747 #define ADC_AWD3HTR_HTR                ADC_AWD3HTR_HTR_Msk                    /*!< ADC analog watchdog 3 threshold high */
6748 #define ADC_AWD3HTR_HTR_0              (0x000001UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000001 */
6749 #define ADC_AWD3HTR_HTR_1              (0x000002UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000002 */
6750 #define ADC_AWD3HTR_HTR_2              (0x000004UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000004 */
6751 #define ADC_AWD3HTR_HTR_3              (0x000008UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000008 */
6752 #define ADC_AWD3HTR_HTR_4              (0x000010UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000010 */
6753 #define ADC_AWD3HTR_HTR_5              (0x000020UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000020 */
6754 #define ADC_AWD3HTR_HTR_6              (0x000040UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000040 */
6755 #define ADC_AWD3HTR_HTR_7              (0x000080UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000080 */
6756 #define ADC_AWD3HTR_HTR_8              (0x000100UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000100 */
6757 #define ADC_AWD3HTR_HTR_9              (0x000200UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000200 */
6758 #define ADC_AWD3HTR_HTR_10             (0x000400UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000400 */
6759 #define ADC_AWD3HTR_HTR_11             (0x000800UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000800 */
6760 #define ADC_AWD3HTR_HTR_12             (0x001000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00001000 */
6761 #define ADC_AWD3HTR_HTR_13             (0x002000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00002000 */
6762 #define ADC_AWD3HTR_HTR_14             (0x004000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00004000 */
6763 #define ADC_AWD3HTR_HTR_15             (0x008000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00008000 */
6764 #define ADC_AWD3HTR_HTR_16             (0x010000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00010000 */
6765 #define ADC_AWD3HTR_HTR_17             (0x020000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00020000 */
6766 #define ADC_AWD3HTR_HTR_18             (0x040000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00040000 */
6767 #define ADC_AWD3HTR_HTR_19             (0x080000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00080000 */
6768 #define ADC_AWD3HTR_HTR_20             (0x100000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00100000 */
6769 #define ADC_AWD3HTR_HTR_21             (0x200000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00200000 */
6770 #define ADC_AWD3HTR_HTR_22             (0x400000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00400000 */
6771 
6772 /********************  Bit definition for ADC_DIFSEL register  ****************/
6773 #define ADC_DIFSEL_DIFSEL_Pos          (0U)
6774 #define ADC_DIFSEL_DIFSEL_Msk          (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x000FFFFF */
6775 #define ADC_DIFSEL_DIFSEL              ADC_DIFSEL_DIFSEL_Msk                   /*!< ADC channel differential or single-ended mode selection */
6776 #define ADC_DIFSEL_DIFSEL_0            (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000001 */
6777 #define ADC_DIFSEL_DIFSEL_1            (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000002 */
6778 #define ADC_DIFSEL_DIFSEL_2            (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000004 */
6779 #define ADC_DIFSEL_DIFSEL_3            (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000008 */
6780 #define ADC_DIFSEL_DIFSEL_4            (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000010 */
6781 #define ADC_DIFSEL_DIFSEL_5            (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000020 */
6782 #define ADC_DIFSEL_DIFSEL_6            (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000040 */
6783 #define ADC_DIFSEL_DIFSEL_7            (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000080 */
6784 #define ADC_DIFSEL_DIFSEL_8            (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000100 */
6785 #define ADC_DIFSEL_DIFSEL_9            (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000200 */
6786 #define ADC_DIFSEL_DIFSEL_10           (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000400 */
6787 #define ADC_DIFSEL_DIFSEL_11           (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000800 */
6788 #define ADC_DIFSEL_DIFSEL_12           (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00001000 */
6789 #define ADC_DIFSEL_DIFSEL_13           (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00002000 */
6790 #define ADC_DIFSEL_DIFSEL_14           (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00004000 */
6791 #define ADC_DIFSEL_DIFSEL_15           (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00008000 */
6792 #define ADC_DIFSEL_DIFSEL_16           (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00010000 */
6793 #define ADC_DIFSEL_DIFSEL_17           (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00020000 */
6794 #define ADC_DIFSEL_DIFSEL_18           (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00040000 */
6795 #define ADC_DIFSEL_DIFSEL_19           (0x80000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00080000 */
6796 
6797 /********************  Bit definition for ADC_CALFACT register  ***************/
6798 #define ADC_CALFACT_CALFACT_S_Pos      (0U)
6799 #define ADC_CALFACT_CALFACT_S_Msk      (0x3FFUL << ADC_CALFACT_CALFACT_S_Pos)  /*!< 0x000003FF */
6800 #define ADC_CALFACT_CALFACT_S          ADC_CALFACT_CALFACT_S_Msk               /*!< ADC calibration factor in single-ended mode */
6801 #define ADC_CALFACT_CALFACT_S_0        (0x01UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000001 */
6802 #define ADC_CALFACT_CALFACT_S_1        (0x02UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000002 */
6803 #define ADC_CALFACT_CALFACT_S_2        (0x04UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000004 */
6804 #define ADC_CALFACT_CALFACT_S_3        (0x08UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000008 */
6805 #define ADC_CALFACT_CALFACT_S_4        (0x10UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000010 */
6806 #define ADC_CALFACT_CALFACT_S_5        (0x20UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000020 */
6807 #define ADC_CALFACT_CALFACT_S_6        (0x40UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000040 */
6808 #define ADC_CALFACT_CALFACT_S_7        (0x80UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000080 */
6809 #define ADC_CALFACT_CALFACT_S_8        (0x100UL<< ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000100 */
6810 #define ADC_CALFACT_CALFACT_S_9        (0x200UL<< ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000200 */
6811 
6812 #define ADC_CALFACT_CALFACT_D_Pos      (16U)
6813 #define ADC_CALFACT_CALFACT_D_Msk      (0x3FFUL << ADC_CALFACT_CALFACT_D_Pos)  /*!< 0x03FF0000 */
6814 #define ADC_CALFACT_CALFACT_D          ADC_CALFACT_CALFACT_D_Msk               /*!< ADC calibration factor in differential mode */
6815 #define ADC_CALFACT_CALFACT_D_0        (0x01UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00010000 */
6816 #define ADC_CALFACT_CALFACT_D_1        (0x02UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00020000 */
6817 #define ADC_CALFACT_CALFACT_D_2        (0x04UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00040000 */
6818 #define ADC_CALFACT_CALFACT_D_3        (0x08UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00080000 */
6819 #define ADC_CALFACT_CALFACT_D_4        (0x10UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00100000 */
6820 #define ADC_CALFACT_CALFACT_D_5        (0x20UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00200000 */
6821 #define ADC_CALFACT_CALFACT_D_6        (0x40UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00400000 */
6822 #define ADC_CALFACT_CALFACT_D_7        (0x80UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00800000 */
6823 #define ADC_CALFACT_CALFACT_D_8        (0x100UL<< ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x01000000 */
6824 #define ADC_CALFACT_CALFACT_D_9        (0x200UL<< ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x02000000 */
6825 
6826 #define ADC_CALFACT_CALADDOS_Pos       (31U)
6827 #define ADC_CALFACT_CALADDOS_Msk       (0x01UL << ADC_CALFACT_CALADDOS_Pos)    /*!< 0x80000000 */
6828 #define ADC_CALFACT_CALADDOS           ADC_CALFACT_CALADDOS_Msk                /*!< ADC calibration additional offset mode */
6829 
6830 /********************  Bit definition for ADC_OR option register  ***************/
6831 #define ADC_OR_OP0_Pos                 (0U)
6832 #define ADC_OR_OP0_Msk                 (0x1UL << ADC_OR_OP0_Pos)               /*!< 0x00000001 */
6833 #define ADC_OR_OP0                     ADC_OR_OP0_Msk                          /*!< ADC internal reference voltage buffer */
6834 
6835 #define ADC_OR_OP1_Pos                 (1U)
6836 #define ADC_OR_OP1_Msk                 (0x1UL << ADC_OR_OP1_Pos)               /*!< 0x00000002 */
6837 #define ADC_OR_OP1                     ADC_OR_OP1_Msk                          /*!< ADC internal bandgap */
6838 
6839 #define ADC_OR_OP2_Pos                 (2U)
6840 #define ADC_OR_OP2_Msk                 (0x1UL << ADC_OR_OP2_Pos)               /*!< 0x00000004 */
6841 #define ADC_OR_OP2                     ADC_OR_OP2_Msk                          /*!< ADC internal path to VDDCORE */
6842 
6843 
6844 /*************************  ADC Common registers  *****************************/
6845 /********************  Bit definition for ADC_CSR register  *******************/
6846 #define ADC_CSR_ADRDY_MST_Pos          (0U)
6847 #define ADC_CSR_ADRDY_MST_Msk          (0x1UL << ADC_CSR_ADRDY_MST_Pos)        /*!< 0x00000001 */
6848 #define ADC_CSR_ADRDY_MST              ADC_CSR_ADRDY_MST_Msk                   /*!< ADC multimode master ready flag */
6849 #define ADC_CSR_EOSMP_MST_Pos          (1U)
6850 #define ADC_CSR_EOSMP_MST_Msk          (0x1UL << ADC_CSR_EOSMP_MST_Pos)        /*!< 0x00000002 */
6851 #define ADC_CSR_EOSMP_MST              ADC_CSR_EOSMP_MST_Msk                   /*!< ADC multimode master group regular end of sampling flag */
6852 #define ADC_CSR_EOC_MST_Pos            (2U)
6853 #define ADC_CSR_EOC_MST_Msk            (0x1UL << ADC_CSR_EOC_MST_Pos)          /*!< 0x00000004 */
6854 #define ADC_CSR_EOC_MST                ADC_CSR_EOC_MST_Msk                     /*!< ADC multimode master group regular end of unitary conversion flag */
6855 #define ADC_CSR_EOS_MST_Pos            (3U)
6856 #define ADC_CSR_EOS_MST_Msk            (0x1UL << ADC_CSR_EOS_MST_Pos)          /*!< 0x00000008 */
6857 #define ADC_CSR_EOS_MST                ADC_CSR_EOS_MST_Msk                     /*!< ADC multimode master group regular end of sequence conversions flag */
6858 #define ADC_CSR_OVR_MST_Pos            (4U)
6859 #define ADC_CSR_OVR_MST_Msk            (0x1UL << ADC_CSR_OVR_MST_Pos)          /*!< 0x00000010 */
6860 #define ADC_CSR_OVR_MST                ADC_CSR_OVR_MST_Msk                     /*!< ADC multimode master group regular overrun flag */
6861 #define ADC_CSR_JEOC_MST_Pos           (5U)
6862 #define ADC_CSR_JEOC_MST_Msk           (0x1UL << ADC_CSR_JEOC_MST_Pos)         /*!< 0x00000020 */
6863 #define ADC_CSR_JEOC_MST               ADC_CSR_JEOC_MST_Msk                    /*!< ADC multimode master group injected end of unitary conversion flag */
6864 #define ADC_CSR_JEOS_MST_Pos           (6U)
6865 #define ADC_CSR_JEOS_MST_Msk           (0x1UL << ADC_CSR_JEOS_MST_Pos)         /*!< 0x00000040 */
6866 #define ADC_CSR_JEOS_MST               ADC_CSR_JEOS_MST_Msk                    /*!< ADC multimode master group injected end of sequence conversions flag */
6867 #define ADC_CSR_AWD1_MST_Pos           (7U)
6868 #define ADC_CSR_AWD1_MST_Msk           (0x1UL << ADC_CSR_AWD1_MST_Pos)         /*!< 0x00000080 */
6869 #define ADC_CSR_AWD1_MST               ADC_CSR_AWD1_MST_Msk                    /*!< ADC multimode master analog watchdog 1 flag */
6870 #define ADC_CSR_AWD2_MST_Pos           (8U)
6871 #define ADC_CSR_AWD2_MST_Msk           (0x1UL << ADC_CSR_AWD2_MST_Pos)         /*!< 0x00000100 */
6872 #define ADC_CSR_AWD2_MST               ADC_CSR_AWD2_MST_Msk                    /*!< ADC multimode master analog watchdog 2 flag */
6873 #define ADC_CSR_AWD3_MST_Pos           (9U)
6874 #define ADC_CSR_AWD3_MST_Msk           (0x1UL << ADC_CSR_AWD3_MST_Pos)         /*!< 0x00000200 */
6875 #define ADC_CSR_AWD3_MST               ADC_CSR_AWD3_MST_Msk                    /*!< ADC multimode master analog watchdog 3 flag */
6876 
6877 #define ADC_CSR_ADRDY_SLV_Pos          (16U)
6878 #define ADC_CSR_ADRDY_SLV_Msk          (0x1UL << ADC_CSR_ADRDY_SLV_Pos)        /*!< 0x00010000 */
6879 #define ADC_CSR_ADRDY_SLV              ADC_CSR_ADRDY_SLV_Msk                   /*!< ADC multimode slave ready flag */
6880 #define ADC_CSR_EOSMP_SLV_Pos          (17U)
6881 #define ADC_CSR_EOSMP_SLV_Msk          (0x1UL << ADC_CSR_EOSMP_SLV_Pos)        /*!< 0x00020000 */
6882 #define ADC_CSR_EOSMP_SLV              ADC_CSR_EOSMP_SLV_Msk                   /*!< ADC multimode slave group regular end of sampling flag */
6883 #define ADC_CSR_EOC_SLV_Pos            (18U)
6884 #define ADC_CSR_EOC_SLV_Msk            (0x1UL << ADC_CSR_EOC_SLV_Pos)          /*!< 0x00040000 */
6885 #define ADC_CSR_EOC_SLV                ADC_CSR_EOC_SLV_Msk                     /*!< ADC multimode slave group regular end of unitary conversion flag */
6886 #define ADC_CSR_EOS_SLV_Pos            (19U)
6887 #define ADC_CSR_EOS_SLV_Msk            (0x1UL << ADC_CSR_EOS_SLV_Pos)          /*!< 0x00080000 */
6888 #define ADC_CSR_EOS_SLV                ADC_CSR_EOS_SLV_Msk                     /*!< ADC multimode slave group regular end of sequence conversions flag */
6889 #define ADC_CSR_OVR_SLV_Pos            (20U)
6890 #define ADC_CSR_OVR_SLV_Msk            (0x1UL << ADC_CSR_OVR_SLV_Pos)          /*!< 0x00100000 */
6891 #define ADC_CSR_OVR_SLV                ADC_CSR_OVR_SLV_Msk                     /*!< ADC multimode slave group regular overrun flag */
6892 #define ADC_CSR_JEOC_SLV_Pos           (21U)
6893 #define ADC_CSR_JEOC_SLV_Msk           (0x1UL << ADC_CSR_JEOC_SLV_Pos)         /*!< 0x00200000 */
6894 #define ADC_CSR_JEOC_SLV               ADC_CSR_JEOC_SLV_Msk                    /*!< ADC multimode slave group injected end of unitary conversion flag */
6895 #define ADC_CSR_JEOS_SLV_Pos           (22U)
6896 #define ADC_CSR_JEOS_SLV_Msk           (0x1UL << ADC_CSR_JEOS_SLV_Pos)         /*!< 0x00400000 */
6897 #define ADC_CSR_JEOS_SLV               ADC_CSR_JEOS_SLV_Msk                    /*!< ADC multimode slave group injected end of sequence conversions flag */
6898 #define ADC_CSR_AWD1_SLV_Pos           (23U)
6899 #define ADC_CSR_AWD1_SLV_Msk           (0x1UL << ADC_CSR_AWD1_SLV_Pos)         /*!< 0x00800000 */
6900 #define ADC_CSR_AWD1_SLV               ADC_CSR_AWD1_SLV_Msk                    /*!< ADC multimode slave analog watchdog 1 flag */
6901 #define ADC_CSR_AWD2_SLV_Pos           (24U)
6902 #define ADC_CSR_AWD2_SLV_Msk           (0x1UL << ADC_CSR_AWD2_SLV_Pos)         /*!< 0x01000000 */
6903 #define ADC_CSR_AWD2_SLV               ADC_CSR_AWD2_SLV_Msk                    /*!< ADC multimode slave analog watchdog 2 flag */
6904 #define ADC_CSR_AWD3_SLV_Pos           (25U)
6905 #define ADC_CSR_AWD3_SLV_Msk           (0x1UL << ADC_CSR_AWD3_SLV_Pos)         /*!< 0x02000000 */
6906 #define ADC_CSR_AWD3_SLV               ADC_CSR_AWD3_SLV_Msk                    /*!< ADC multimode slave analog watchdog 3 flag */
6907 
6908 /********************  Bit definition for ADC_CCR register  *******************/
6909 #define ADC_CCR_DUAL_Pos               (0U)
6910 #define ADC_CCR_DUAL_Msk               (0x1FUL << ADC_CCR_DUAL_Pos)            /*!< 0x0000001F */
6911 #define ADC_CCR_DUAL                   ADC_CCR_DUAL_Msk                        /*!< ADC multimode mode selection */
6912 #define ADC_CCR_DUAL_0                 (0x01UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000001 */
6913 #define ADC_CCR_DUAL_1                 (0x02UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000002 */
6914 #define ADC_CCR_DUAL_2                 (0x04UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000004 */
6915 #define ADC_CCR_DUAL_3                 (0x08UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000008 */
6916 #define ADC_CCR_DUAL_4                 (0x10UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000010 */
6917 
6918 #define ADC_CCR_DELAY_Pos              (8U)
6919 #define ADC_CCR_DELAY_Msk              (0xFUL << ADC_CCR_DELAY_Pos)            /*!< 0x00000F00 */
6920 #define ADC_CCR_DELAY                  ADC_CCR_DELAY_Msk                       /*!< ADC multimode delay between 2 sampling phases */
6921 #define ADC_CCR_DELAY_0                (0x1UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000100 */
6922 #define ADC_CCR_DELAY_1                (0x2UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000200 */
6923 #define ADC_CCR_DELAY_2                (0x4UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000400 */
6924 #define ADC_CCR_DELAY_3                (0x8UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000800 */
6925 
6926 #define ADC_CCR_DAMDF_Pos              (14U)
6927 #define ADC_CCR_DAMDF_Msk              (0x3UL << ADC_CCR_DAMDF_Pos)            /*!< 0x0000C000 */
6928 #define ADC_CCR_DAMDF                  ADC_CCR_DAMDF_Msk                       /*!< ADC multimode data format */
6929 #define ADC_CCR_DAMDF_0                (0x1UL << ADC_CCR_DAMDF_Pos)            /*!< 0x00004000 */
6930 #define ADC_CCR_DAMDF_1                (0x2UL << ADC_CCR_DAMDF_Pos)            /*!< 0x00008000 */
6931 
6932 #define ADC_CCR_VREFEN_Pos             (22U)
6933 #define ADC_CCR_VREFEN_Msk             (0x1UL << ADC_CCR_VREFEN_Pos)           /*!< 0x00400000 */
6934 #define ADC_CCR_VREFEN                 ADC_CCR_VREFEN_Msk                      /*!< ADC internal path to VrefInt enable */
6935 
6936 #define ADC_CCR_VBATEN_Pos             (24U)
6937 #define ADC_CCR_VBATEN_Msk             (0x1UL << ADC_CCR_VBATEN_Pos)           /*!< 0x01000000 */
6938 #define ADC_CCR_VBATEN                 ADC_CCR_VBATEN_Msk                      /*!< ADC internal path to battery voltage enable */
6939 
6940 /********************  Bit definition for ADC_CDR register  *******************/
6941 #define ADC_CDR_RDATA_MST_Pos          (0U)
6942 #define ADC_CDR_RDATA_MST_Msk          (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x0000FFFF */
6943 #define ADC_CDR_RDATA_MST              ADC_CDR_RDATA_MST_Msk                   /*!< ADC multimode master group regular conversion data */
6944 
6945 #define ADC_CDR_RDATA_SLV_Pos          (16U)
6946 #define ADC_CDR_RDATA_SLV_Msk          (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0xFFFF0000 */
6947 #define ADC_CDR_RDATA_SLV              ADC_CDR_RDATA_SLV_Msk                   /*!< ADC multimode slave group regular conversion data */
6948 
6949 /********************  Bit definition for ADC_CDR2 register  ******************/
6950 #define ADC_CDR2_RDATA_ALT_Pos         (0U)
6951 #define ADC_CDR2_RDATA_ALT_Msk         (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */
6952 #define ADC_CDR2_RDATA_ALT             ADC_CDR2_RDATA_ALT_Msk                   /*!< ADC multimode master or slave (alternated) group regular conversion data */
6953 
6954 
6955 /******************************************************************************/
6956 /*                                                                            */
6957 /*                       BSEC unit (Boot and Security)                        */
6958 /*                                                                            */
6959 /******************************************************************************/
6960 /******************  Bit definition for BSEC_FVRw register  *******************/
6961 #define BSEC_FVRw_FV_Pos               (0U)
6962 #define BSEC_FVRw_FV_Msk               (0xFFFFFFFFUL << BSEC_FVRw_FV_Pos)           /*!< 0xFFFFFFFF */
6963 #define BSEC_FVRw_FV                   BSEC_FVRw_FV_Msk                            /*!< Fuse value */
6964 
6965 /*****************  Bit definition for BSEC_SPLOCKx register  *****************/
6966 #define BSEC_SPLOCKx_SPLOCK0_Pos       (0U)
6967 #define BSEC_SPLOCKx_SPLOCK0_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK0_Pos)          /*!< 0x00000001 */
6968 #define BSEC_SPLOCKx_SPLOCK0           BSEC_SPLOCKx_SPLOCK0_Msk                    /*!< Sticky programming lock for word (32*x) */
6969 #define BSEC_SPLOCKx_SPLOCK1_Pos       (1U)
6970 #define BSEC_SPLOCKx_SPLOCK1_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK1_Pos)          /*!< 0x00000002 */
6971 #define BSEC_SPLOCKx_SPLOCK1           BSEC_SPLOCKx_SPLOCK1_Msk                    /*!< Sticky programming lock for word (1+32*x) */
6972 #define BSEC_SPLOCKx_SPLOCK2_Pos       (2U)
6973 #define BSEC_SPLOCKx_SPLOCK2_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK2_Pos)          /*!< 0x00000004 */
6974 #define BSEC_SPLOCKx_SPLOCK2           BSEC_SPLOCKx_SPLOCK2_Msk                    /*!< Sticky programming lock for word (2+32*x) */
6975 #define BSEC_SPLOCKx_SPLOCK3_Pos       (3U)
6976 #define BSEC_SPLOCKx_SPLOCK3_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK3_Pos)          /*!< 0x00000008 */
6977 #define BSEC_SPLOCKx_SPLOCK3           BSEC_SPLOCKx_SPLOCK3_Msk                    /*!< Sticky programming lock for word (3+32*x) */
6978 #define BSEC_SPLOCKx_SPLOCK4_Pos       (4U)
6979 #define BSEC_SPLOCKx_SPLOCK4_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK4_Pos)          /*!< 0x00000010 */
6980 #define BSEC_SPLOCKx_SPLOCK4           BSEC_SPLOCKx_SPLOCK4_Msk                    /*!< Sticky programming lock for word (4+32*x) */
6981 #define BSEC_SPLOCKx_SPLOCK5_Pos       (5U)
6982 #define BSEC_SPLOCKx_SPLOCK5_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK5_Pos)          /*!< 0x00000020 */
6983 #define BSEC_SPLOCKx_SPLOCK5           BSEC_SPLOCKx_SPLOCK5_Msk                    /*!< Sticky programming lock for word (5+32*x) */
6984 #define BSEC_SPLOCKx_SPLOCK6_Pos       (6U)
6985 #define BSEC_SPLOCKx_SPLOCK6_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK6_Pos)          /*!< 0x00000040 */
6986 #define BSEC_SPLOCKx_SPLOCK6           BSEC_SPLOCKx_SPLOCK6_Msk                    /*!< Sticky programming lock for word (6+32*x) */
6987 #define BSEC_SPLOCKx_SPLOCK7_Pos       (7U)
6988 #define BSEC_SPLOCKx_SPLOCK7_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK7_Pos)          /*!< 0x00000080 */
6989 #define BSEC_SPLOCKx_SPLOCK7           BSEC_SPLOCKx_SPLOCK7_Msk                    /*!< Sticky programming lock for word (7+32*x) */
6990 #define BSEC_SPLOCKx_SPLOCK8_Pos       (8U)
6991 #define BSEC_SPLOCKx_SPLOCK8_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK8_Pos)          /*!< 0x00000100 */
6992 #define BSEC_SPLOCKx_SPLOCK8           BSEC_SPLOCKx_SPLOCK8_Msk                    /*!< Sticky programming lock for word (8+32*x) */
6993 #define BSEC_SPLOCKx_SPLOCK9_Pos       (9U)
6994 #define BSEC_SPLOCKx_SPLOCK9_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK9_Pos)          /*!< 0x00000200 */
6995 #define BSEC_SPLOCKx_SPLOCK9           BSEC_SPLOCKx_SPLOCK9_Msk                    /*!< Sticky programming lock for word (9+32*x) */
6996 #define BSEC_SPLOCKx_SPLOCK10_Pos      (10U)
6997 #define BSEC_SPLOCKx_SPLOCK10_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK10_Pos)         /*!< 0x00000400 */
6998 #define BSEC_SPLOCKx_SPLOCK10          BSEC_SPLOCKx_SPLOCK10_Msk                   /*!< Sticky programming lock for word (10+32*x) */
6999 #define BSEC_SPLOCKx_SPLOCK11_Pos      (11U)
7000 #define BSEC_SPLOCKx_SPLOCK11_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK11_Pos)         /*!< 0x00000800 */
7001 #define BSEC_SPLOCKx_SPLOCK11          BSEC_SPLOCKx_SPLOCK11_Msk                   /*!< Sticky programming lock for word (11+32*x) */
7002 #define BSEC_SPLOCKx_SPLOCK12_Pos      (12U)
7003 #define BSEC_SPLOCKx_SPLOCK12_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK12_Pos)         /*!< 0x00001000 */
7004 #define BSEC_SPLOCKx_SPLOCK12          BSEC_SPLOCKx_SPLOCK12_Msk                   /*!< Sticky programming lock for word (12+32*x) */
7005 #define BSEC_SPLOCKx_SPLOCK13_Pos      (13U)
7006 #define BSEC_SPLOCKx_SPLOCK13_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK13_Pos)         /*!< 0x00002000 */
7007 #define BSEC_SPLOCKx_SPLOCK13          BSEC_SPLOCKx_SPLOCK13_Msk                   /*!< Sticky programming lock for word (13+32*x) */
7008 #define BSEC_SPLOCKx_SPLOCK14_Pos      (14U)
7009 #define BSEC_SPLOCKx_SPLOCK14_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK14_Pos)         /*!< 0x00004000 */
7010 #define BSEC_SPLOCKx_SPLOCK14          BSEC_SPLOCKx_SPLOCK14_Msk                   /*!< Sticky programming lock for word (14+32*x) */
7011 #define BSEC_SPLOCKx_SPLOCK15_Pos      (15U)
7012 #define BSEC_SPLOCKx_SPLOCK15_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK15_Pos)         /*!< 0x00008000 */
7013 #define BSEC_SPLOCKx_SPLOCK15          BSEC_SPLOCKx_SPLOCK15_Msk                   /*!< Sticky programming lock for word (15+32*x) */
7014 #define BSEC_SPLOCKx_SPLOCK16_Pos      (16U)
7015 #define BSEC_SPLOCKx_SPLOCK16_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK16_Pos)         /*!< 0x00010000 */
7016 #define BSEC_SPLOCKx_SPLOCK16          BSEC_SPLOCKx_SPLOCK16_Msk                   /*!< Sticky programming lock for word (16+32*x) */
7017 #define BSEC_SPLOCKx_SPLOCK17_Pos      (17U)
7018 #define BSEC_SPLOCKx_SPLOCK17_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK17_Pos)         /*!< 0x00020000 */
7019 #define BSEC_SPLOCKx_SPLOCK17          BSEC_SPLOCKx_SPLOCK17_Msk                   /*!< Sticky programming lock for word (17+32*x) */
7020 #define BSEC_SPLOCKx_SPLOCK18_Pos      (18U)
7021 #define BSEC_SPLOCKx_SPLOCK18_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK18_Pos)         /*!< 0x00040000 */
7022 #define BSEC_SPLOCKx_SPLOCK18          BSEC_SPLOCKx_SPLOCK18_Msk                   /*!< Sticky programming lock for word (18+32*x) */
7023 #define BSEC_SPLOCKx_SPLOCK19_Pos      (19U)
7024 #define BSEC_SPLOCKx_SPLOCK19_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK19_Pos)         /*!< 0x00080000 */
7025 #define BSEC_SPLOCKx_SPLOCK19          BSEC_SPLOCKx_SPLOCK19_Msk                   /*!< Sticky programming lock for word (19+32*x) */
7026 #define BSEC_SPLOCKx_SPLOCK20_Pos      (20U)
7027 #define BSEC_SPLOCKx_SPLOCK20_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK20_Pos)         /*!< 0x00100000 */
7028 #define BSEC_SPLOCKx_SPLOCK20          BSEC_SPLOCKx_SPLOCK20_Msk                   /*!< Sticky programming lock for word (20+32*x) */
7029 #define BSEC_SPLOCKx_SPLOCK21_Pos      (21U)
7030 #define BSEC_SPLOCKx_SPLOCK21_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK21_Pos)         /*!< 0x00200000 */
7031 #define BSEC_SPLOCKx_SPLOCK21          BSEC_SPLOCKx_SPLOCK21_Msk                   /*!< Sticky programming lock for word (21+32*x) */
7032 #define BSEC_SPLOCKx_SPLOCK22_Pos      (22U)
7033 #define BSEC_SPLOCKx_SPLOCK22_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK22_Pos)         /*!< 0x00400000 */
7034 #define BSEC_SPLOCKx_SPLOCK22          BSEC_SPLOCKx_SPLOCK22_Msk                   /*!< Sticky programming lock for word (22+32*x) */
7035 #define BSEC_SPLOCKx_SPLOCK23_Pos      (23U)
7036 #define BSEC_SPLOCKx_SPLOCK23_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK23_Pos)         /*!< 0x00800000 */
7037 #define BSEC_SPLOCKx_SPLOCK23          BSEC_SPLOCKx_SPLOCK23_Msk                   /*!< Sticky programming lock for word (23+32*x) */
7038 #define BSEC_SPLOCKx_SPLOCK24_Pos      (24U)
7039 #define BSEC_SPLOCKx_SPLOCK24_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK24_Pos)         /*!< 0x01000000 */
7040 #define BSEC_SPLOCKx_SPLOCK24          BSEC_SPLOCKx_SPLOCK24_Msk                   /*!< Sticky programming lock for word (24+32*x) */
7041 #define BSEC_SPLOCKx_SPLOCK25_Pos      (25U)
7042 #define BSEC_SPLOCKx_SPLOCK25_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK25_Pos)         /*!< 0x02000000 */
7043 #define BSEC_SPLOCKx_SPLOCK25          BSEC_SPLOCKx_SPLOCK25_Msk                   /*!< Sticky programming lock for word (25+32*x) */
7044 #define BSEC_SPLOCKx_SPLOCK26_Pos      (26U)
7045 #define BSEC_SPLOCKx_SPLOCK26_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK26_Pos)         /*!< 0x04000000 */
7046 #define BSEC_SPLOCKx_SPLOCK26          BSEC_SPLOCKx_SPLOCK26_Msk                   /*!< Sticky programming lock for word (26+32*x) */
7047 #define BSEC_SPLOCKx_SPLOCK27_Pos      (27U)
7048 #define BSEC_SPLOCKx_SPLOCK27_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK27_Pos)         /*!< 0x08000000 */
7049 #define BSEC_SPLOCKx_SPLOCK27          BSEC_SPLOCKx_SPLOCK27_Msk                   /*!< Sticky programming lock for word (27+32*x) */
7050 #define BSEC_SPLOCKx_SPLOCK28_Pos      (28U)
7051 #define BSEC_SPLOCKx_SPLOCK28_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK28_Pos)         /*!< 0x10000000 */
7052 #define BSEC_SPLOCKx_SPLOCK28          BSEC_SPLOCKx_SPLOCK28_Msk                   /*!< Sticky programming lock for word (28+32*x) */
7053 #define BSEC_SPLOCKx_SPLOCK29_Pos      (29U)
7054 #define BSEC_SPLOCKx_SPLOCK29_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK29_Pos)         /*!< 0x20000000 */
7055 #define BSEC_SPLOCKx_SPLOCK29          BSEC_SPLOCKx_SPLOCK29_Msk                   /*!< Sticky programming lock for word (29+32*x) */
7056 #define BSEC_SPLOCKx_SPLOCK30_Pos      (30U)
7057 #define BSEC_SPLOCKx_SPLOCK30_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK30_Pos)         /*!< 0x40000000 */
7058 #define BSEC_SPLOCKx_SPLOCK30          BSEC_SPLOCKx_SPLOCK30_Msk                   /*!< Sticky programming lock for word (30+32*x) */
7059 #define BSEC_SPLOCKx_SPLOCK31_Pos      (31U)
7060 #define BSEC_SPLOCKx_SPLOCK31_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK31_Pos)         /*!< 0x80000000 */
7061 #define BSEC_SPLOCKx_SPLOCK31          BSEC_SPLOCKx_SPLOCK31_Msk                   /*!< Sticky programming lock for word (31+32*x) */
7062 
7063 /*****************  Bit definition for BSEC_SWLOCKx register  *****************/
7064 #define BSEC_SWLOCKx_SWLOCK0_Pos       (0U)
7065 #define BSEC_SWLOCKx_SWLOCK0_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK0_Pos)          /*!< 0x00000001 */
7066 #define BSEC_SWLOCKx_SWLOCK0           BSEC_SWLOCKx_SWLOCK0_Msk                    /*!< Sticky write lock for shadow register (32*x) */
7067 #define BSEC_SWLOCKx_SWLOCK1_Pos       (1U)
7068 #define BSEC_SWLOCKx_SWLOCK1_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK1_Pos)          /*!< 0x00000002 */
7069 #define BSEC_SWLOCKx_SWLOCK1           BSEC_SWLOCKx_SWLOCK1_Msk                    /*!< Sticky write lock for shadow register (1+32*x) */
7070 #define BSEC_SWLOCKx_SWLOCK2_Pos       (2U)
7071 #define BSEC_SWLOCKx_SWLOCK2_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK2_Pos)          /*!< 0x00000004 */
7072 #define BSEC_SWLOCKx_SWLOCK2           BSEC_SWLOCKx_SWLOCK2_Msk                    /*!< Sticky write lock for shadow register (2+32*x) */
7073 #define BSEC_SWLOCKx_SWLOCK3_Pos       (3U)
7074 #define BSEC_SWLOCKx_SWLOCK3_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK3_Pos)          /*!< 0x00000008 */
7075 #define BSEC_SWLOCKx_SWLOCK3           BSEC_SWLOCKx_SWLOCK3_Msk                    /*!< Sticky write lock for shadow register (3+32*x) */
7076 #define BSEC_SWLOCKx_SWLOCK4_Pos       (4U)
7077 #define BSEC_SWLOCKx_SWLOCK4_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK4_Pos)          /*!< 0x00000010 */
7078 #define BSEC_SWLOCKx_SWLOCK4           BSEC_SWLOCKx_SWLOCK4_Msk                    /*!< Sticky write lock for shadow register (4+32*x) */
7079 #define BSEC_SWLOCKx_SWLOCK5_Pos       (5U)
7080 #define BSEC_SWLOCKx_SWLOCK5_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK5_Pos)          /*!< 0x00000020 */
7081 #define BSEC_SWLOCKx_SWLOCK5           BSEC_SWLOCKx_SWLOCK5_Msk                    /*!< Sticky write lock for shadow register (5+32*x) */
7082 #define BSEC_SWLOCKx_SWLOCK6_Pos       (6U)
7083 #define BSEC_SWLOCKx_SWLOCK6_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK6_Pos)          /*!< 0x00000040 */
7084 #define BSEC_SWLOCKx_SWLOCK6           BSEC_SWLOCKx_SWLOCK6_Msk                    /*!< Sticky write lock for shadow register (6+32*x) */
7085 #define BSEC_SWLOCKx_SWLOCK7_Pos       (7U)
7086 #define BSEC_SWLOCKx_SWLOCK7_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK7_Pos)          /*!< 0x00000080 */
7087 #define BSEC_SWLOCKx_SWLOCK7           BSEC_SWLOCKx_SWLOCK7_Msk                    /*!< Sticky write lock for shadow register (7+32*x) */
7088 #define BSEC_SWLOCKx_SWLOCK8_Pos       (8U)
7089 #define BSEC_SWLOCKx_SWLOCK8_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK8_Pos)          /*!< 0x00000100 */
7090 #define BSEC_SWLOCKx_SWLOCK8           BSEC_SWLOCKx_SWLOCK8_Msk                    /*!< Sticky write lock for shadow register (8+32*x) */
7091 #define BSEC_SWLOCKx_SWLOCK9_Pos       (9U)
7092 #define BSEC_SWLOCKx_SWLOCK9_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK9_Pos)          /*!< 0x00000200 */
7093 #define BSEC_SWLOCKx_SWLOCK9           BSEC_SWLOCKx_SWLOCK9_Msk                    /*!< Sticky write lock for shadow register (9+32*x) */
7094 #define BSEC_SWLOCKx_SWLOCK10_Pos      (10U)
7095 #define BSEC_SWLOCKx_SWLOCK10_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK10_Pos)         /*!< 0x00000400 */
7096 #define BSEC_SWLOCKx_SWLOCK10          BSEC_SWLOCKx_SWLOCK10_Msk                   /*!< Sticky write lock for shadow register (10+32*x) */
7097 #define BSEC_SWLOCKx_SWLOCK11_Pos      (11U)
7098 #define BSEC_SWLOCKx_SWLOCK11_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK11_Pos)         /*!< 0x00000800 */
7099 #define BSEC_SWLOCKx_SWLOCK11          BSEC_SWLOCKx_SWLOCK11_Msk                   /*!< Sticky write lock for shadow register (11+32*x) */
7100 #define BSEC_SWLOCKx_SWLOCK12_Pos      (12U)
7101 #define BSEC_SWLOCKx_SWLOCK12_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK12_Pos)         /*!< 0x00001000 */
7102 #define BSEC_SWLOCKx_SWLOCK12          BSEC_SWLOCKx_SWLOCK12_Msk                   /*!< Sticky write lock for shadow register (12+32*x) */
7103 #define BSEC_SWLOCKx_SWLOCK13_Pos      (13U)
7104 #define BSEC_SWLOCKx_SWLOCK13_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK13_Pos)         /*!< 0x00002000 */
7105 #define BSEC_SWLOCKx_SWLOCK13          BSEC_SWLOCKx_SWLOCK13_Msk                   /*!< Sticky write lock for shadow register (13+32*x) */
7106 #define BSEC_SWLOCKx_SWLOCK14_Pos      (14U)
7107 #define BSEC_SWLOCKx_SWLOCK14_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK14_Pos)         /*!< 0x00004000 */
7108 #define BSEC_SWLOCKx_SWLOCK14          BSEC_SWLOCKx_SWLOCK14_Msk                   /*!< Sticky write lock for shadow register (14+32*x) */
7109 #define BSEC_SWLOCKx_SWLOCK15_Pos      (15U)
7110 #define BSEC_SWLOCKx_SWLOCK15_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK15_Pos)         /*!< 0x00008000 */
7111 #define BSEC_SWLOCKx_SWLOCK15          BSEC_SWLOCKx_SWLOCK15_Msk                   /*!< Sticky write lock for shadow register (15+32*x) */
7112 #define BSEC_SWLOCKx_SWLOCK16_Pos      (16U)
7113 #define BSEC_SWLOCKx_SWLOCK16_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK16_Pos)         /*!< 0x00010000 */
7114 #define BSEC_SWLOCKx_SWLOCK16          BSEC_SWLOCKx_SWLOCK16_Msk                   /*!< Sticky write lock for shadow register (16+32*x) */
7115 #define BSEC_SWLOCKx_SWLOCK17_Pos      (17U)
7116 #define BSEC_SWLOCKx_SWLOCK17_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK17_Pos)         /*!< 0x00020000 */
7117 #define BSEC_SWLOCKx_SWLOCK17          BSEC_SWLOCKx_SWLOCK17_Msk                   /*!< Sticky write lock for shadow register (17+32*x) */
7118 #define BSEC_SWLOCKx_SWLOCK18_Pos      (18U)
7119 #define BSEC_SWLOCKx_SWLOCK18_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK18_Pos)         /*!< 0x00040000 */
7120 #define BSEC_SWLOCKx_SWLOCK18          BSEC_SWLOCKx_SWLOCK18_Msk                   /*!< Sticky write lock for shadow register (18+32*x) */
7121 #define BSEC_SWLOCKx_SWLOCK19_Pos      (19U)
7122 #define BSEC_SWLOCKx_SWLOCK19_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK19_Pos)         /*!< 0x00080000 */
7123 #define BSEC_SWLOCKx_SWLOCK19          BSEC_SWLOCKx_SWLOCK19_Msk                   /*!< Sticky write lock for shadow register (19+32*x) */
7124 #define BSEC_SWLOCKx_SWLOCK20_Pos      (20U)
7125 #define BSEC_SWLOCKx_SWLOCK20_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK20_Pos)         /*!< 0x00100000 */
7126 #define BSEC_SWLOCKx_SWLOCK20          BSEC_SWLOCKx_SWLOCK20_Msk                   /*!< Sticky write lock for shadow register (20+32*x) */
7127 #define BSEC_SWLOCKx_SWLOCK21_Pos      (21U)
7128 #define BSEC_SWLOCKx_SWLOCK21_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK21_Pos)         /*!< 0x00200000 */
7129 #define BSEC_SWLOCKx_SWLOCK21          BSEC_SWLOCKx_SWLOCK21_Msk                   /*!< Sticky write lock for shadow register (21+32*x) */
7130 #define BSEC_SWLOCKx_SWLOCK22_Pos      (22U)
7131 #define BSEC_SWLOCKx_SWLOCK22_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK22_Pos)         /*!< 0x00400000 */
7132 #define BSEC_SWLOCKx_SWLOCK22          BSEC_SWLOCKx_SWLOCK22_Msk                   /*!< Sticky write lock for shadow register (22+32*x) */
7133 #define BSEC_SWLOCKx_SWLOCK23_Pos      (23U)
7134 #define BSEC_SWLOCKx_SWLOCK23_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK23_Pos)         /*!< 0x00800000 */
7135 #define BSEC_SWLOCKx_SWLOCK23          BSEC_SWLOCKx_SWLOCK23_Msk                   /*!< Sticky write lock for shadow register (23+32*x) */
7136 #define BSEC_SWLOCKx_SWLOCK24_Pos      (24U)
7137 #define BSEC_SWLOCKx_SWLOCK24_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK24_Pos)         /*!< 0x01000000 */
7138 #define BSEC_SWLOCKx_SWLOCK24          BSEC_SWLOCKx_SWLOCK24_Msk                   /*!< Sticky write lock for shadow register (24+32*x) */
7139 #define BSEC_SWLOCKx_SWLOCK25_Pos      (25U)
7140 #define BSEC_SWLOCKx_SWLOCK25_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK25_Pos)         /*!< 0x02000000 */
7141 #define BSEC_SWLOCKx_SWLOCK25          BSEC_SWLOCKx_SWLOCK25_Msk                   /*!< Sticky write lock for shadow register (25+32*x) */
7142 #define BSEC_SWLOCKx_SWLOCK26_Pos      (26U)
7143 #define BSEC_SWLOCKx_SWLOCK26_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK26_Pos)         /*!< 0x04000000 */
7144 #define BSEC_SWLOCKx_SWLOCK26          BSEC_SWLOCKx_SWLOCK26_Msk                   /*!< Sticky write lock for shadow register (26+32*x) */
7145 #define BSEC_SWLOCKx_SWLOCK27_Pos      (27U)
7146 #define BSEC_SWLOCKx_SWLOCK27_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK27_Pos)         /*!< 0x08000000 */
7147 #define BSEC_SWLOCKx_SWLOCK27          BSEC_SWLOCKx_SWLOCK27_Msk                   /*!< Sticky write lock for shadow register (27+32*x) */
7148 #define BSEC_SWLOCKx_SWLOCK28_Pos      (28U)
7149 #define BSEC_SWLOCKx_SWLOCK28_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK28_Pos)         /*!< 0x10000000 */
7150 #define BSEC_SWLOCKx_SWLOCK28          BSEC_SWLOCKx_SWLOCK28_Msk                   /*!< Sticky write lock for shadow register (28+32*x) */
7151 #define BSEC_SWLOCKx_SWLOCK29_Pos      (29U)
7152 #define BSEC_SWLOCKx_SWLOCK29_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK29_Pos)         /*!< 0x20000000 */
7153 #define BSEC_SWLOCKx_SWLOCK29          BSEC_SWLOCKx_SWLOCK29_Msk                   /*!< Sticky write lock for shadow register (29+32*x) */
7154 #define BSEC_SWLOCKx_SWLOCK30_Pos      (30U)
7155 #define BSEC_SWLOCKx_SWLOCK30_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK30_Pos)         /*!< 0x40000000 */
7156 #define BSEC_SWLOCKx_SWLOCK30          BSEC_SWLOCKx_SWLOCK30_Msk                   /*!< Sticky write lock for shadow register (30+32*x) */
7157 #define BSEC_SWLOCKx_SWLOCK31_Pos      (31U)
7158 #define BSEC_SWLOCKx_SWLOCK31_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK31_Pos)         /*!< 0x80000000 */
7159 #define BSEC_SWLOCKx_SWLOCK31          BSEC_SWLOCKx_SWLOCK31_Msk                   /*!< Sticky write lock for shadow register (31+32*x) */
7160 
7161 /*****************  Bit definition for BSEC_SRLOCKx register  *****************/
7162 #define BSEC_SRLOCKx_SRLOCK0_Pos       (0U)
7163 #define BSEC_SRLOCKx_SRLOCK0_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK0_Pos)          /*!< 0x00000001 */
7164 #define BSEC_SRLOCKx_SRLOCK0           BSEC_SRLOCKx_SRLOCK0_Msk                    /*!< Sticky reload lock for fuse word (32*x) */
7165 #define BSEC_SRLOCKx_SRLOCK1_Pos       (1U)
7166 #define BSEC_SRLOCKx_SRLOCK1_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK1_Pos)          /*!< 0x00000002 */
7167 #define BSEC_SRLOCKx_SRLOCK1           BSEC_SRLOCKx_SRLOCK1_Msk                    /*!< Sticky reload lock for fuse word (1+32*x) */
7168 #define BSEC_SRLOCKx_SRLOCK2_Pos       (2U)
7169 #define BSEC_SRLOCKx_SRLOCK2_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK2_Pos)          /*!< 0x00000004 */
7170 #define BSEC_SRLOCKx_SRLOCK2           BSEC_SRLOCKx_SRLOCK2_Msk                    /*!< Sticky reload lock for fuse word (2+32*x) */
7171 #define BSEC_SRLOCKx_SRLOCK3_Pos       (3U)
7172 #define BSEC_SRLOCKx_SRLOCK3_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK3_Pos)          /*!< 0x00000008 */
7173 #define BSEC_SRLOCKx_SRLOCK3           BSEC_SRLOCKx_SRLOCK3_Msk                    /*!< Sticky reload lock for fuse word (3+32*x) */
7174 #define BSEC_SRLOCKx_SRLOCK4_Pos       (4U)
7175 #define BSEC_SRLOCKx_SRLOCK4_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK4_Pos)          /*!< 0x00000010 */
7176 #define BSEC_SRLOCKx_SRLOCK4           BSEC_SRLOCKx_SRLOCK4_Msk                    /*!< Sticky reload lock for fuse word (4+32*x) */
7177 #define BSEC_SRLOCKx_SRLOCK5_Pos       (5U)
7178 #define BSEC_SRLOCKx_SRLOCK5_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK5_Pos)          /*!< 0x00000020 */
7179 #define BSEC_SRLOCKx_SRLOCK5           BSEC_SRLOCKx_SRLOCK5_Msk                    /*!< Sticky reload lock for fuse word (5+32*x) */
7180 #define BSEC_SRLOCKx_SRLOCK6_Pos       (6U)
7181 #define BSEC_SRLOCKx_SRLOCK6_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK6_Pos)          /*!< 0x00000040 */
7182 #define BSEC_SRLOCKx_SRLOCK6           BSEC_SRLOCKx_SRLOCK6_Msk                    /*!< Sticky reload lock for fuse word (6+32*x) */
7183 #define BSEC_SRLOCKx_SRLOCK7_Pos       (7U)
7184 #define BSEC_SRLOCKx_SRLOCK7_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK7_Pos)          /*!< 0x00000080 */
7185 #define BSEC_SRLOCKx_SRLOCK7           BSEC_SRLOCKx_SRLOCK7_Msk                    /*!< Sticky reload lock for fuse word (7+32*x) */
7186 #define BSEC_SRLOCKx_SRLOCK8_Pos       (8U)
7187 #define BSEC_SRLOCKx_SRLOCK8_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK8_Pos)          /*!< 0x00000100 */
7188 #define BSEC_SRLOCKx_SRLOCK8           BSEC_SRLOCKx_SRLOCK8_Msk                    /*!< Sticky reload lock for fuse word (8+32*x) */
7189 #define BSEC_SRLOCKx_SRLOCK9_Pos       (9U)
7190 #define BSEC_SRLOCKx_SRLOCK9_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK9_Pos)          /*!< 0x00000200 */
7191 #define BSEC_SRLOCKx_SRLOCK9           BSEC_SRLOCKx_SRLOCK9_Msk                    /*!< Sticky reload lock for fuse word (9+32*x) */
7192 #define BSEC_SRLOCKx_SRLOCK10_Pos      (10U)
7193 #define BSEC_SRLOCKx_SRLOCK10_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK10_Pos)         /*!< 0x00000400 */
7194 #define BSEC_SRLOCKx_SRLOCK10          BSEC_SRLOCKx_SRLOCK10_Msk                   /*!< Sticky reload lock for fuse word (10+2*x) */
7195 #define BSEC_SRLOCKx_SRLOCK11_Pos      (11U)
7196 #define BSEC_SRLOCKx_SRLOCK11_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK11_Pos)         /*!< 0x00000800 */
7197 #define BSEC_SRLOCKx_SRLOCK11          BSEC_SRLOCKx_SRLOCK11_Msk                   /*!< Sticky reload lock for fuse word (11+32*x) */
7198 #define BSEC_SRLOCKx_SRLOCK12_Pos      (12U)
7199 #define BSEC_SRLOCKx_SRLOCK12_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK12_Pos)         /*!< 0x00001000 */
7200 #define BSEC_SRLOCKx_SRLOCK12          BSEC_SRLOCKx_SRLOCK12_Msk                   /*!< Sticky reload lock for fuse word (12+32*x) */
7201 #define BSEC_SRLOCKx_SRLOCK13_Pos      (13U)
7202 #define BSEC_SRLOCKx_SRLOCK13_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK13_Pos)         /*!< 0x00002000 */
7203 #define BSEC_SRLOCKx_SRLOCK13          BSEC_SRLOCKx_SRLOCK13_Msk                   /*!< Sticky reload lock for fuse word (13+32*x) */
7204 #define BSEC_SRLOCKx_SRLOCK14_Pos      (14U)
7205 #define BSEC_SRLOCKx_SRLOCK14_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK14_Pos)         /*!< 0x00004000 */
7206 #define BSEC_SRLOCKx_SRLOCK14          BSEC_SRLOCKx_SRLOCK14_Msk                   /*!< Sticky reload lock for fuse word (14+32*x) */
7207 #define BSEC_SRLOCKx_SRLOCK15_Pos      (15U)
7208 #define BSEC_SRLOCKx_SRLOCK15_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK15_Pos)         /*!< 0x00008000 */
7209 #define BSEC_SRLOCKx_SRLOCK15          BSEC_SRLOCKx_SRLOCK15_Msk                   /*!< Sticky reload lock for fuse word (15+32*x) */
7210 #define BSEC_SRLOCKx_SRLOCK16_Pos      (16U)
7211 #define BSEC_SRLOCKx_SRLOCK16_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK16_Pos)         /*!< 0x00010000 */
7212 #define BSEC_SRLOCKx_SRLOCK16          BSEC_SRLOCKx_SRLOCK16_Msk                   /*!< Sticky reload lock for fuse word (16+32*x) */
7213 #define BSEC_SRLOCKx_SRLOCK17_Pos      (17U)
7214 #define BSEC_SRLOCKx_SRLOCK17_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK17_Pos)         /*!< 0x00020000 */
7215 #define BSEC_SRLOCKx_SRLOCK17          BSEC_SRLOCKx_SRLOCK17_Msk                   /*!< Sticky reload lock for fuse word (17+32*x) */
7216 #define BSEC_SRLOCKx_SRLOCK18_Pos      (18U)
7217 #define BSEC_SRLOCKx_SRLOCK18_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK18_Pos)         /*!< 0x00040000 */
7218 #define BSEC_SRLOCKx_SRLOCK18          BSEC_SRLOCKx_SRLOCK18_Msk                   /*!< Sticky reload lock for fuse word (18+32*x) */
7219 #define BSEC_SRLOCKx_SRLOCK19_Pos      (19U)
7220 #define BSEC_SRLOCKx_SRLOCK19_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK19_Pos)         /*!< 0x00080000 */
7221 #define BSEC_SRLOCKx_SRLOCK19          BSEC_SRLOCKx_SRLOCK19_Msk                   /*!< Sticky reload lock for fuse word (19+32*x) */
7222 #define BSEC_SRLOCKx_SRLOCK20_Pos      (20U)
7223 #define BSEC_SRLOCKx_SRLOCK20_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK20_Pos)         /*!< 0x00100000 */
7224 #define BSEC_SRLOCKx_SRLOCK20          BSEC_SRLOCKx_SRLOCK20_Msk                   /*!< Sticky reload lock for fuse word (20+32*x) */
7225 #define BSEC_SRLOCKx_SRLOCK21_Pos      (21U)
7226 #define BSEC_SRLOCKx_SRLOCK21_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK21_Pos)         /*!< 0x00200000 */
7227 #define BSEC_SRLOCKx_SRLOCK21          BSEC_SRLOCKx_SRLOCK21_Msk                   /*!< Sticky reload lock for fuse word (21+32*x) */
7228 #define BSEC_SRLOCKx_SRLOCK22_Pos      (22U)
7229 #define BSEC_SRLOCKx_SRLOCK22_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK22_Pos)         /*!< 0x00400000 */
7230 #define BSEC_SRLOCKx_SRLOCK22          BSEC_SRLOCKx_SRLOCK22_Msk                   /*!< Sticky reload lock for fuse word (22+32*x) */
7231 #define BSEC_SRLOCKx_SRLOCK23_Pos      (23U)
7232 #define BSEC_SRLOCKx_SRLOCK23_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK23_Pos)         /*!< 0x00800000 */
7233 #define BSEC_SRLOCKx_SRLOCK23          BSEC_SRLOCKx_SRLOCK23_Msk                   /*!< Sticky reload lock for fuse word (23+32*x) */
7234 #define BSEC_SRLOCKx_SRLOCK24_Pos      (24U)
7235 #define BSEC_SRLOCKx_SRLOCK24_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK24_Pos)         /*!< 0x01000000 */
7236 #define BSEC_SRLOCKx_SRLOCK24          BSEC_SRLOCKx_SRLOCK24_Msk                   /*!< Sticky reload lock for fuse word (24+32*x) */
7237 #define BSEC_SRLOCKx_SRLOCK25_Pos      (25U)
7238 #define BSEC_SRLOCKx_SRLOCK25_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK25_Pos)         /*!< 0x02000000 */
7239 #define BSEC_SRLOCKx_SRLOCK25          BSEC_SRLOCKx_SRLOCK25_Msk                   /*!< Sticky reload lock for fuse word (25+32*x) */
7240 #define BSEC_SRLOCKx_SRLOCK26_Pos      (26U)
7241 #define BSEC_SRLOCKx_SRLOCK26_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK26_Pos)         /*!< 0x04000000 */
7242 #define BSEC_SRLOCKx_SRLOCK26          BSEC_SRLOCKx_SRLOCK26_Msk                   /*!< Sticky reload lock for fuse word (26+32*x) */
7243 #define BSEC_SRLOCKx_SRLOCK27_Pos      (27U)
7244 #define BSEC_SRLOCKx_SRLOCK27_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK27_Pos)         /*!< 0x08000000 */
7245 #define BSEC_SRLOCKx_SRLOCK27          BSEC_SRLOCKx_SRLOCK27_Msk                   /*!< Sticky reload lock for fuse word (27+32*x) */
7246 #define BSEC_SRLOCKx_SRLOCK28_Pos      (28U)
7247 #define BSEC_SRLOCKx_SRLOCK28_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK28_Pos)         /*!< 0x10000000 */
7248 #define BSEC_SRLOCKx_SRLOCK28          BSEC_SRLOCKx_SRLOCK28_Msk                   /*!< Sticky reload lock for fuse word (28+32*x) */
7249 #define BSEC_SRLOCKx_SRLOCK29_Pos      (29U)
7250 #define BSEC_SRLOCKx_SRLOCK29_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK29_Pos)         /*!< 0x20000000 */
7251 #define BSEC_SRLOCKx_SRLOCK29          BSEC_SRLOCKx_SRLOCK29_Msk                   /*!< Sticky reload lock for fuse word (29+32*x) */
7252 #define BSEC_SRLOCKx_SRLOCK30_Pos      (30U)
7253 #define BSEC_SRLOCKx_SRLOCK30_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK30_Pos)         /*!< 0x40000000 */
7254 #define BSEC_SRLOCKx_SRLOCK30          BSEC_SRLOCKx_SRLOCK30_Msk                   /*!< Sticky reload lock for fuse word (30+32*x) */
7255 #define BSEC_SRLOCKx_SRLOCK31_Pos      (31U)
7256 #define BSEC_SRLOCKx_SRLOCK31_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK31_Pos)         /*!< 0x80000000 */
7257 #define BSEC_SRLOCKx_SRLOCK31          BSEC_SRLOCKx_SRLOCK31_Msk                   /*!< Sticky reload lock for fuse word (31+32*x) */
7258 
7259 /****************  Bit definition for BSEC_OTPVLDRx register  *****************/
7260 #define BSEC_OTPVLDRx_VLDF0_Pos        (0U)
7261 #define BSEC_OTPVLDRx_VLDF0_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF0_Pos)           /*!< 0x00000001 */
7262 #define BSEC_OTPVLDRx_VLDF0            BSEC_OTPVLDRx_VLDF0_Msk                     /*!< Valid flag for shadow register (32*x) */
7263 #define BSEC_OTPVLDRx_VLDF1_Pos        (1U)
7264 #define BSEC_OTPVLDRx_VLDF1_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF1_Pos)           /*!< 0x00000002 */
7265 #define BSEC_OTPVLDRx_VLDF1            BSEC_OTPVLDRx_VLDF1_Msk                     /*!< Valid flag for shadow register (1+32*x) */
7266 #define BSEC_OTPVLDRx_VLDF2_Pos        (2U)
7267 #define BSEC_OTPVLDRx_VLDF2_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF2_Pos)           /*!< 0x00000004 */
7268 #define BSEC_OTPVLDRx_VLDF2            BSEC_OTPVLDRx_VLDF2_Msk                     /*!< Valid flag for shadow register (2+32*x) */
7269 #define BSEC_OTPVLDRx_VLDF3_Pos        (3U)
7270 #define BSEC_OTPVLDRx_VLDF3_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF3_Pos)           /*!< 0x00000008 */
7271 #define BSEC_OTPVLDRx_VLDF3            BSEC_OTPVLDRx_VLDF3_Msk                     /*!< Valid flag for shadow register (3+32*x) */
7272 #define BSEC_OTPVLDRx_VLDF4_Pos        (4U)
7273 #define BSEC_OTPVLDRx_VLDF4_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF4_Pos)           /*!< 0x00000010 */
7274 #define BSEC_OTPVLDRx_VLDF4            BSEC_OTPVLDRx_VLDF4_Msk                     /*!< Valid flag for shadow register (4+32*x) */
7275 #define BSEC_OTPVLDRx_VLDF5_Pos        (5U)
7276 #define BSEC_OTPVLDRx_VLDF5_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF5_Pos)           /*!< 0x00000020 */
7277 #define BSEC_OTPVLDRx_VLDF5            BSEC_OTPVLDRx_VLDF5_Msk                     /*!< Valid flag for shadow register (5+32*x) */
7278 #define BSEC_OTPVLDRx_VLDF6_Pos        (6U)
7279 #define BSEC_OTPVLDRx_VLDF6_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF6_Pos)           /*!< 0x00000040 */
7280 #define BSEC_OTPVLDRx_VLDF6            BSEC_OTPVLDRx_VLDF6_Msk                     /*!< Valid flag for shadow register (6+32*x) */
7281 #define BSEC_OTPVLDRx_VLDF7_Pos        (7U)
7282 #define BSEC_OTPVLDRx_VLDF7_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF7_Pos)           /*!< 0x00000080 */
7283 #define BSEC_OTPVLDRx_VLDF7            BSEC_OTPVLDRx_VLDF7_Msk                     /*!< Valid flag for shadow register (7+32*x) */
7284 #define BSEC_OTPVLDRx_VLDF8_Pos        (8U)
7285 #define BSEC_OTPVLDRx_VLDF8_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF8_Pos)           /*!< 0x00000100 */
7286 #define BSEC_OTPVLDRx_VLDF8            BSEC_OTPVLDRx_VLDF8_Msk                     /*!< Valid flag for shadow register (8+32*x) */
7287 #define BSEC_OTPVLDRx_VLDF9_Pos        (9U)
7288 #define BSEC_OTPVLDRx_VLDF9_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF9_Pos)           /*!< 0x00000200 */
7289 #define BSEC_OTPVLDRx_VLDF9            BSEC_OTPVLDRx_VLDF9_Msk                     /*!< Valid flag for shadow register (9+32*x) */
7290 #define BSEC_OTPVLDRx_VLDF10_Pos       (10U)
7291 #define BSEC_OTPVLDRx_VLDF10_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF10_Pos)          /*!< 0x00000400 */
7292 #define BSEC_OTPVLDRx_VLDF10           BSEC_OTPVLDRx_VLDF10_Msk                    /*!< Valid flag for shadow register (10+32*x) */
7293 #define BSEC_OTPVLDRx_VLDF11_Pos       (11U)
7294 #define BSEC_OTPVLDRx_VLDF11_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF11_Pos)          /*!< 0x00000800 */
7295 #define BSEC_OTPVLDRx_VLDF11           BSEC_OTPVLDRx_VLDF11_Msk                    /*!< Valid flag for shadow register (11+32*x) */
7296 #define BSEC_OTPVLDRx_VLDF12_Pos       (12U)
7297 #define BSEC_OTPVLDRx_VLDF12_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF12_Pos)          /*!< 0x00001000 */
7298 #define BSEC_OTPVLDRx_VLDF12           BSEC_OTPVLDRx_VLDF12_Msk                    /*!< Valid flag for shadow register (12+32*x) */
7299 #define BSEC_OTPVLDRx_VLDF13_Pos       (13U)
7300 #define BSEC_OTPVLDRx_VLDF13_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF13_Pos)          /*!< 0x00002000 */
7301 #define BSEC_OTPVLDRx_VLDF13           BSEC_OTPVLDRx_VLDF13_Msk                    /*!< Valid flag for shadow register (13+32*x) */
7302 #define BSEC_OTPVLDRx_VLDF14_Pos       (14U)
7303 #define BSEC_OTPVLDRx_VLDF14_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF14_Pos)          /*!< 0x00004000 */
7304 #define BSEC_OTPVLDRx_VLDF14           BSEC_OTPVLDRx_VLDF14_Msk                    /*!< Valid flag for shadow register (14+32*x) */
7305 #define BSEC_OTPVLDRx_VLDF15_Pos       (15U)
7306 #define BSEC_OTPVLDRx_VLDF15_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF15_Pos)          /*!< 0x00008000 */
7307 #define BSEC_OTPVLDRx_VLDF15           BSEC_OTPVLDRx_VLDF15_Msk                    /*!< Valid flag for shadow register (15+32*x) */
7308 #define BSEC_OTPVLDRx_VLDF16_Pos       (16U)
7309 #define BSEC_OTPVLDRx_VLDF16_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF16_Pos)          /*!< 0x00010000 */
7310 #define BSEC_OTPVLDRx_VLDF16           BSEC_OTPVLDRx_VLDF16_Msk                    /*!< Valid flag for shadow register (16+32*x) */
7311 #define BSEC_OTPVLDRx_VLDF17_Pos       (17U)
7312 #define BSEC_OTPVLDRx_VLDF17_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF17_Pos)          /*!< 0x00020000 */
7313 #define BSEC_OTPVLDRx_VLDF17           BSEC_OTPVLDRx_VLDF17_Msk                    /*!< Valid flag for shadow register (17+32*x) */
7314 #define BSEC_OTPVLDRx_VLDF18_Pos       (18U)
7315 #define BSEC_OTPVLDRx_VLDF18_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF18_Pos)          /*!< 0x00040000 */
7316 #define BSEC_OTPVLDRx_VLDF18           BSEC_OTPVLDRx_VLDF18_Msk                    /*!< Valid flag for shadow register (18+32*x) */
7317 #define BSEC_OTPVLDRx_VLDF19_Pos       (19U)
7318 #define BSEC_OTPVLDRx_VLDF19_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF19_Pos)          /*!< 0x00080000 */
7319 #define BSEC_OTPVLDRx_VLDF19           BSEC_OTPVLDRx_VLDF19_Msk                    /*!< Valid flag for shadow register (19+32*x) */
7320 #define BSEC_OTPVLDRx_VLDF20_Pos       (20U)
7321 #define BSEC_OTPVLDRx_VLDF20_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF20_Pos)          /*!< 0x00100000 */
7322 #define BSEC_OTPVLDRx_VLDF20           BSEC_OTPVLDRx_VLDF20_Msk                    /*!< Valid flag for shadow register (20+32*x) */
7323 #define BSEC_OTPVLDRx_VLDF21_Pos       (21U)
7324 #define BSEC_OTPVLDRx_VLDF21_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF21_Pos)          /*!< 0x00200000 */
7325 #define BSEC_OTPVLDRx_VLDF21           BSEC_OTPVLDRx_VLDF21_Msk                    /*!< Valid flag for shadow register (21+32*x) */
7326 #define BSEC_OTPVLDRx_VLDF22_Pos       (22U)
7327 #define BSEC_OTPVLDRx_VLDF22_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF22_Pos)          /*!< 0x00400000 */
7328 #define BSEC_OTPVLDRx_VLDF22           BSEC_OTPVLDRx_VLDF22_Msk                    /*!< Valid flag for shadow register (22+32*x) */
7329 #define BSEC_OTPVLDRx_VLDF23_Pos       (23U)
7330 #define BSEC_OTPVLDRx_VLDF23_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF23_Pos)          /*!< 0x00800000 */
7331 #define BSEC_OTPVLDRx_VLDF23           BSEC_OTPVLDRx_VLDF23_Msk                    /*!< Valid flag for shadow register (23+32*x) */
7332 #define BSEC_OTPVLDRx_VLDF24_Pos       (24U)
7333 #define BSEC_OTPVLDRx_VLDF24_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF24_Pos)          /*!< 0x01000000 */
7334 #define BSEC_OTPVLDRx_VLDF24           BSEC_OTPVLDRx_VLDF24_Msk                    /*!< Valid flag for shadow register (24+32*x) */
7335 #define BSEC_OTPVLDRx_VLDF25_Pos       (25U)
7336 #define BSEC_OTPVLDRx_VLDF25_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF25_Pos)          /*!< 0x02000000 */
7337 #define BSEC_OTPVLDRx_VLDF25           BSEC_OTPVLDRx_VLDF25_Msk                    /*!< Valid flag for shadow register (25+32*x) */
7338 #define BSEC_OTPVLDRx_VLDF26_Pos       (26U)
7339 #define BSEC_OTPVLDRx_VLDF26_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF26_Pos)          /*!< 0x04000000 */
7340 #define BSEC_OTPVLDRx_VLDF26           BSEC_OTPVLDRx_VLDF26_Msk                    /*!< Valid flag for shadow register (26+32*x) */
7341 #define BSEC_OTPVLDRx_VLDF27_Pos       (27U)
7342 #define BSEC_OTPVLDRx_VLDF27_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF27_Pos)          /*!< 0x08000000 */
7343 #define BSEC_OTPVLDRx_VLDF27           BSEC_OTPVLDRx_VLDF27_Msk                    /*!< Valid flag for shadow register (27+32*x) */
7344 #define BSEC_OTPVLDRx_VLDF28_Pos       (28U)
7345 #define BSEC_OTPVLDRx_VLDF28_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF28_Pos)          /*!< 0x10000000 */
7346 #define BSEC_OTPVLDRx_VLDF28           BSEC_OTPVLDRx_VLDF28_Msk                    /*!< Valid flag for shadow register (28+32*x) */
7347 #define BSEC_OTPVLDRx_VLDF29_Pos       (29U)
7348 #define BSEC_OTPVLDRx_VLDF29_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF29_Pos)          /*!< 0x20000000 */
7349 #define BSEC_OTPVLDRx_VLDF29           BSEC_OTPVLDRx_VLDF29_Msk                    /*!< Valid flag for shadow register (29+32*x) */
7350 #define BSEC_OTPVLDRx_VLDF30_Pos       (30U)
7351 #define BSEC_OTPVLDRx_VLDF30_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF30_Pos)          /*!< 0x40000000 */
7352 #define BSEC_OTPVLDRx_VLDF30           BSEC_OTPVLDRx_VLDF30_Msk                    /*!< Valid flag for shadow register (30+32*x) */
7353 #define BSEC_OTPVLDRx_VLDF31_Pos       (31U)
7354 #define BSEC_OTPVLDRx_VLDF31_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF31_Pos)          /*!< 0x80000000 */
7355 #define BSEC_OTPVLDRx_VLDF31           BSEC_OTPVLDRx_VLDF31_Msk                    /*!< Valid flag for shadow register (31+32*x) */
7356 
7357 /******************  Bit definition for BSEC_SFSRx register  ******************/
7358 #define BSEC_SFSRx_SFW0_Pos            (0U)
7359 #define BSEC_SFSRx_SFW0_Msk            (0x1UL << BSEC_SFSRx_SFW0_Pos)               /*!< 0x00000001 */
7360 #define BSEC_SFSRx_SFW0                BSEC_SFSRx_SFW0_Msk                         /*!< Shadowed fuse word (32*x) */
7361 #define BSEC_SFSRx_SFW1_Pos            (1U)
7362 #define BSEC_SFSRx_SFW1_Msk            (0x1UL << BSEC_SFSRx_SFW1_Pos)               /*!< 0x00000002 */
7363 #define BSEC_SFSRx_SFW1                BSEC_SFSRx_SFW1_Msk                         /*!< Shadowed fuse word (1+32*x) */
7364 #define BSEC_SFSRx_SFW2_Pos            (2U)
7365 #define BSEC_SFSRx_SFW2_Msk            (0x1UL << BSEC_SFSRx_SFW2_Pos)               /*!< 0x00000004 */
7366 #define BSEC_SFSRx_SFW2                BSEC_SFSRx_SFW2_Msk                         /*!< Shadowed fuse word (2+32*x) */
7367 #define BSEC_SFSRx_SFW3_Pos            (3U)
7368 #define BSEC_SFSRx_SFW3_Msk            (0x1UL << BSEC_SFSRx_SFW3_Pos)               /*!< 0x00000008 */
7369 #define BSEC_SFSRx_SFW3                BSEC_SFSRx_SFW3_Msk                         /*!< Shadowed fuse word (3+32*x) */
7370 #define BSEC_SFSRx_SFW4_Pos            (4U)
7371 #define BSEC_SFSRx_SFW4_Msk            (0x1UL << BSEC_SFSRx_SFW4_Pos)               /*!< 0x00000010 */
7372 #define BSEC_SFSRx_SFW4                BSEC_SFSRx_SFW4_Msk                         /*!< Shadowed fuse word (4+32*x) */
7373 #define BSEC_SFSRx_SFW5_Pos            (5U)
7374 #define BSEC_SFSRx_SFW5_Msk            (0x1UL << BSEC_SFSRx_SFW5_Pos)               /*!< 0x00000020 */
7375 #define BSEC_SFSRx_SFW5                BSEC_SFSRx_SFW5_Msk                         /*!< Shadowed fuse word (5+32*x) */
7376 #define BSEC_SFSRx_SFW6_Pos            (6U)
7377 #define BSEC_SFSRx_SFW6_Msk            (0x1UL << BSEC_SFSRx_SFW6_Pos)               /*!< 0x00000040 */
7378 #define BSEC_SFSRx_SFW6                BSEC_SFSRx_SFW6_Msk                         /*!< Shadowed fuse word (6+32*x) */
7379 #define BSEC_SFSRx_SFW7_Pos            (7U)
7380 #define BSEC_SFSRx_SFW7_Msk            (0x1UL << BSEC_SFSRx_SFW7_Pos)               /*!< 0x00000080 */
7381 #define BSEC_SFSRx_SFW7                BSEC_SFSRx_SFW7_Msk                         /*!< Shadowed fuse word (7+32*x) */
7382 #define BSEC_SFSRx_SFW8_Pos            (8U)
7383 #define BSEC_SFSRx_SFW8_Msk            (0x1UL << BSEC_SFSRx_SFW8_Pos)               /*!< 0x00000100 */
7384 #define BSEC_SFSRx_SFW8                BSEC_SFSRx_SFW8_Msk                         /*!< Shadowed fuse word (8+32*x) */
7385 #define BSEC_SFSRx_SFW9_Pos            (9U)
7386 #define BSEC_SFSRx_SFW9_Msk            (0x1UL << BSEC_SFSRx_SFW9_Pos)               /*!< 0x00000200 */
7387 #define BSEC_SFSRx_SFW9                BSEC_SFSRx_SFW9_Msk                         /*!< Shadowed fuse word (9+32*x) */
7388 #define BSEC_SFSRx_SFW10_Pos           (10U)
7389 #define BSEC_SFSRx_SFW10_Msk           (0x1UL << BSEC_SFSRx_SFW10_Pos)              /*!< 0x00000400 */
7390 #define BSEC_SFSRx_SFW10               BSEC_SFSRx_SFW10_Msk                        /*!< Shadowed fuse word (10+32*x) */
7391 #define BSEC_SFSRx_SFW11_Pos           (11U)
7392 #define BSEC_SFSRx_SFW11_Msk           (0x1UL << BSEC_SFSRx_SFW11_Pos)              /*!< 0x00000800 */
7393 #define BSEC_SFSRx_SFW11               BSEC_SFSRx_SFW11_Msk                        /*!< Shadowed fuse word (11+32*x) */
7394 #define BSEC_SFSRx_SFW12_Pos           (12U)
7395 #define BSEC_SFSRx_SFW12_Msk           (0x1UL << BSEC_SFSRx_SFW12_Pos)              /*!< 0x00001000 */
7396 #define BSEC_SFSRx_SFW12               BSEC_SFSRx_SFW12_Msk                        /*!< Shadowed fuse word (12+32*x) */
7397 #define BSEC_SFSRx_SFW13_Pos           (13U)
7398 #define BSEC_SFSRx_SFW13_Msk           (0x1UL << BSEC_SFSRx_SFW13_Pos)              /*!< 0x00002000 */
7399 #define BSEC_SFSRx_SFW13               BSEC_SFSRx_SFW13_Msk                        /*!< Shadowed fuse word (13+32*x) */
7400 #define BSEC_SFSRx_SFW14_Pos           (14U)
7401 #define BSEC_SFSRx_SFW14_Msk           (0x1UL << BSEC_SFSRx_SFW14_Pos)              /*!< 0x00004000 */
7402 #define BSEC_SFSRx_SFW14               BSEC_SFSRx_SFW14_Msk                        /*!< Shadowed fuse word (14+32*x) */
7403 #define BSEC_SFSRx_SFW15_Pos           (15U)
7404 #define BSEC_SFSRx_SFW15_Msk           (0x1UL << BSEC_SFSRx_SFW15_Pos)              /*!< 0x00008000 */
7405 #define BSEC_SFSRx_SFW15               BSEC_SFSRx_SFW15_Msk                        /*!< Shadowed fuse word (15+32*x) */
7406 #define BSEC_SFSRx_SFW16_Pos           (16U)
7407 #define BSEC_SFSRx_SFW16_Msk           (0x1UL << BSEC_SFSRx_SFW16_Pos)              /*!< 0x00010000 */
7408 #define BSEC_SFSRx_SFW16               BSEC_SFSRx_SFW16_Msk                        /*!< Shadowed fuse word (16+32*x) */
7409 #define BSEC_SFSRx_SFW17_Pos           (17U)
7410 #define BSEC_SFSRx_SFW17_Msk           (0x1UL << BSEC_SFSRx_SFW17_Pos)              /*!< 0x00020000 */
7411 #define BSEC_SFSRx_SFW17               BSEC_SFSRx_SFW17_Msk                        /*!< Shadowed fuse word (17+32*x) */
7412 #define BSEC_SFSRx_SFW18_Pos           (18U)
7413 #define BSEC_SFSRx_SFW18_Msk           (0x1UL << BSEC_SFSRx_SFW18_Pos)              /*!< 0x00040000 */
7414 #define BSEC_SFSRx_SFW18               BSEC_SFSRx_SFW18_Msk                        /*!< Shadowed fuse word (18+32*x) */
7415 #define BSEC_SFSRx_SFW19_Pos           (19U)
7416 #define BSEC_SFSRx_SFW19_Msk           (0x1UL << BSEC_SFSRx_SFW19_Pos)              /*!< 0x00080000 */
7417 #define BSEC_SFSRx_SFW19               BSEC_SFSRx_SFW19_Msk                        /*!< Shadowed fuse word (19+32*x) */
7418 #define BSEC_SFSRx_SFW20_Pos           (20U)
7419 #define BSEC_SFSRx_SFW20_Msk           (0x1UL << BSEC_SFSRx_SFW20_Pos)              /*!< 0x00100000 */
7420 #define BSEC_SFSRx_SFW20               BSEC_SFSRx_SFW20_Msk                        /*!< Shadowed fuse word (20+32*x) */
7421 #define BSEC_SFSRx_SFW21_Pos           (21U)
7422 #define BSEC_SFSRx_SFW21_Msk           (0x1UL << BSEC_SFSRx_SFW21_Pos)              /*!< 0x00200000 */
7423 #define BSEC_SFSRx_SFW21               BSEC_SFSRx_SFW21_Msk                        /*!< Shadowed fuse word (21+32*x) */
7424 #define BSEC_SFSRx_SFW22_Pos           (22U)
7425 #define BSEC_SFSRx_SFW22_Msk           (0x1UL << BSEC_SFSRx_SFW22_Pos)              /*!< 0x00400000 */
7426 #define BSEC_SFSRx_SFW22               BSEC_SFSRx_SFW22_Msk                        /*!< Shadowed fuse word (22+32*x) */
7427 #define BSEC_SFSRx_SFW23_Pos           (23U)
7428 #define BSEC_SFSRx_SFW23_Msk           (0x1UL << BSEC_SFSRx_SFW23_Pos)              /*!< 0x00800000 */
7429 #define BSEC_SFSRx_SFW23               BSEC_SFSRx_SFW23_Msk                        /*!< Shadowed fuse word (23+32*x) */
7430 #define BSEC_SFSRx_SFW24_Pos           (24U)
7431 #define BSEC_SFSRx_SFW24_Msk           (0x1UL << BSEC_SFSRx_SFW24_Pos)              /*!< 0x01000000 */
7432 #define BSEC_SFSRx_SFW24               BSEC_SFSRx_SFW24_Msk                        /*!< Shadowed fuse word (24+32*x) */
7433 #define BSEC_SFSRx_SFW25_Pos           (25U)
7434 #define BSEC_SFSRx_SFW25_Msk           (0x1UL << BSEC_SFSRx_SFW25_Pos)              /*!< 0x02000000 */
7435 #define BSEC_SFSRx_SFW25               BSEC_SFSRx_SFW25_Msk                        /*!< Shadowed fuse word (25+32*x) */
7436 #define BSEC_SFSRx_SFW26_Pos           (26U)
7437 #define BSEC_SFSRx_SFW26_Msk           (0x1UL << BSEC_SFSRx_SFW26_Pos)              /*!< 0x04000000 */
7438 #define BSEC_SFSRx_SFW26               BSEC_SFSRx_SFW26_Msk                        /*!< Shadowed fuse word (26+32*x) */
7439 #define BSEC_SFSRx_SFW27_Pos           (27U)
7440 #define BSEC_SFSRx_SFW27_Msk           (0x1UL << BSEC_SFSRx_SFW27_Pos)              /*!< 0x08000000 */
7441 #define BSEC_SFSRx_SFW27               BSEC_SFSRx_SFW27_Msk                        /*!< Shadowed fuse word (27+32*x) */
7442 #define BSEC_SFSRx_SFW28_Pos           (28U)
7443 #define BSEC_SFSRx_SFW28_Msk           (0x1UL << BSEC_SFSRx_SFW28_Pos)              /*!< 0x10000000 */
7444 #define BSEC_SFSRx_SFW28               BSEC_SFSRx_SFW28_Msk                        /*!< Shadowed fuse word (28+32*x) */
7445 #define BSEC_SFSRx_SFW29_Pos           (29U)
7446 #define BSEC_SFSRx_SFW29_Msk           (0x1UL << BSEC_SFSRx_SFW29_Pos)              /*!< 0x20000000 */
7447 #define BSEC_SFSRx_SFW29               BSEC_SFSRx_SFW29_Msk                        /*!< Shadowed fuse word (29+32*x) */
7448 #define BSEC_SFSRx_SFW30_Pos           (30U)
7449 #define BSEC_SFSRx_SFW30_Msk           (0x1UL << BSEC_SFSRx_SFW30_Pos)              /*!< 0x40000000 */
7450 #define BSEC_SFSRx_SFW30               BSEC_SFSRx_SFW30_Msk                        /*!< Shadowed fuse word (30+32*x) */
7451 #define BSEC_SFSRx_SFW31_Pos           (31U)
7452 #define BSEC_SFSRx_SFW31_Msk           (0x1UL << BSEC_SFSRx_SFW31_Pos)              /*!< 0x80000000 */
7453 #define BSEC_SFSRx_SFW31               BSEC_SFSRx_SFW31_Msk                        /*!< Shadowed fuse word (31+32*x) */
7454 
7455 /******************  Bit definition for BSEC_OTPCR register  ******************/
7456 #define BSEC_OTPCR_ADDR_Pos            (0U)
7457 #define BSEC_OTPCR_ADDR_Msk            (0x1FFUL << BSEC_OTPCR_ADDR_Pos)             /*!< 0x000001FF */
7458 #define BSEC_OTPCR_ADDR                BSEC_OTPCR_ADDR_Msk                         /*!< Fuse word address */
7459 #define BSEC_OTPCR_PROG_Pos            (13U)
7460 #define BSEC_OTPCR_PROG_Msk            (0x1UL << BSEC_OTPCR_PROG_Pos)               /*!< 0x00002000 */
7461 #define BSEC_OTPCR_PROG                BSEC_OTPCR_PROG_Msk                         /*!< Fuse word programming */
7462 #define BSEC_OTPCR_PPLOCK_Pos          (14U)
7463 #define BSEC_OTPCR_PPLOCK_Msk          (0x1UL << BSEC_OTPCR_PPLOCK_Pos)             /*!< 0x00004000 */
7464 #define BSEC_OTPCR_PPLOCK              BSEC_OTPCR_PPLOCK_Msk                       /*!< Permanent programming lock */
7465 #define BSEC_OTPCR_LASTCID_Pos         (19U)
7466 #define BSEC_OTPCR_LASTCID_Msk         (0x7UL << BSEC_OTPCR_LASTCID_Pos)            /*!< 0x00380000 */
7467 #define BSEC_OTPCR_LASTCID             BSEC_OTPCR_LASTCID_Msk                      /*!< Last CID */
7468 
7469 /*******************  Bit definition for BSEC_WDR register  *******************/
7470 #define BSEC_WDR_WRDATA_Pos            (0U)
7471 #define BSEC_WDR_WRDATA_Msk            (0xFFFFFFFFUL << BSEC_WDR_WRDATA_Pos)        /*!< 0xFFFFFFFF */
7472 #define BSEC_WDR_WRDATA                BSEC_WDR_WRDATA_Msk                         /*!< OTP write data */
7473 
7474 /****************  Bit definition for BSEC_SCRATCHRx register  ****************/
7475 #define BSEC_SCRATCHRx_SDATA_Pos       (0U)
7476 #define BSEC_SCRATCHRx_SDATA_Msk       (0xFFFFFFFFUL << BSEC_SCRATCHRx_SDATA_Pos)   /*!< 0xFFFFFFFF */
7477 #define BSEC_SCRATCHRx_SDATA           BSEC_SCRATCHRx_SDATA_Msk                    /*!< Scratch data */
7478 
7479 /******************  Bit definition for BSEC_LOCKR register  ******************/
7480 #define BSEC_LOCKR_GWLOCK_Pos          (0U)
7481 #define BSEC_LOCKR_GWLOCK_Msk          (0x1UL << BSEC_LOCKR_GWLOCK_Pos)             /*!< 0x00000001 */
7482 #define BSEC_LOCKR_GWLOCK              BSEC_LOCKR_GWLOCK_Msk                       /*!< Global write lock */
7483 #define BSEC_LOCKR_HKLOCK_Pos          (2U)
7484 #define BSEC_LOCKR_HKLOCK_Msk          (0x1UL << BSEC_LOCKR_HKLOCK_Pos)             /*!< 0x00000004 */
7485 #define BSEC_LOCKR_HKLOCK              BSEC_LOCKR_HKLOCK_Msk                       /*!< Hardware key lock */
7486 
7487 /*****************  Bit definition for BSEC_JTAGINR register  *****************/
7488 #define BSEC_JTAGINR_JDATAIN_Pos       (0U)
7489 #define BSEC_JTAGINR_JDATAIN_Msk       (0xFFFFFFFFUL << BSEC_JTAGINR_JDATAIN_Pos)   /*!< 0xFFFFFFFF */
7490 #define BSEC_JTAGINR_JDATAIN           BSEC_JTAGINR_JDATAIN_Msk                    /*!< JTAG input data */
7491 
7492 /****************  Bit definition for BSEC_JTAGOUTR register  *****************/
7493 #define BSEC_JTAGOUTR_JDATAOUT_Pos     (0U)
7494 #define BSEC_JTAGOUTR_JDATAOUT_Msk     (0xFFFFFFFFUL << BSEC_JTAGOUTR_JDATAOUT_Pos) /*!< 0xFFFFFFFF */
7495 #define BSEC_JTAGOUTR_JDATAOUT         BSEC_JTAGOUTR_JDATAOUT_Msk                  /*!< JTAG output data */
7496 
7497 /*****************  Bit definition for BSEC_UNMAPR register  ******************/
7498 #define BSEC_UNMAPR_UNMAP_Pos          (0U)
7499 #define BSEC_UNMAPR_UNMAP_Msk          (0xFFFFFFFFUL << BSEC_UNMAPR_UNMAP_Pos)      /*!< 0xFFFFFFFF */
7500 #define BSEC_UNMAPR_UNMAP              BSEC_UNMAPR_UNMAP_Msk                       /*!< Unmap key */
7501 
7502 /*******************  Bit definition for BSEC_SR register  ********************/
7503 #define BSEC_SR_HVALID_Pos             (1U)
7504 #define BSEC_SR_HVALID_Msk             (0x1UL << BSEC_SR_HVALID_Pos)                /*!< 0x00000002 */
7505 #define BSEC_SR_HVALID                 BSEC_SR_HVALID_Msk                          /*!< Hardware key valid */
7506 #define BSEC_SR_DBGREQ_Pos             (16U)
7507 #define BSEC_SR_DBGREQ_Msk             (0x1UL << BSEC_SR_DBGREQ_Pos)                /*!< 0x00010000 */
7508 #define BSEC_SR_DBGREQ                 BSEC_SR_DBGREQ_Msk                          /*!< Debug request */
7509 #define BSEC_SR_NVSTATE_Pos            (26U)
7510 #define BSEC_SR_NVSTATE_Msk            (0x3FUL << BSEC_SR_NVSTATE_Pos)              /*!< 0xFC000000 */
7511 #define BSEC_SR_NVSTATE                BSEC_SR_NVSTATE_Msk                         /*!< Non-volatile state */
7512 
7513 /******************  Bit definition for BSEC_OTPSR register  ******************/
7514 #define BSEC_OTPSR_BUSY_Pos            (0U)
7515 #define BSEC_OTPSR_BUSY_Msk            (0x1UL << BSEC_OTPSR_BUSY_Pos)               /*!< 0x00000001 */
7516 #define BSEC_OTPSR_BUSY                BSEC_OTPSR_BUSY_Msk                         /*!< Busy flag */
7517 #define BSEC_OTPSR_INIT_DONE_Pos       (1U)
7518 #define BSEC_OTPSR_INIT_DONE_Msk       (0x1UL << BSEC_OTPSR_INIT_DONE_Pos)          /*!< 0x00000002 */
7519 #define BSEC_OTPSR_INIT_DONE           BSEC_OTPSR_INIT_DONE_Msk                    /*!< Initialization done */
7520 #define BSEC_OTPSR_HIDEUP_Pos          (2U)
7521 #define BSEC_OTPSR_HIDEUP_Msk          (0x1UL << BSEC_OTPSR_HIDEUP_Pos)             /*!< 0x00000004 */
7522 #define BSEC_OTPSR_HIDEUP              BSEC_OTPSR_HIDEUP_Msk                       /*!< Hide upper fuse words */
7523 #define BSEC_OTPSR_OTPNVIR_Pos         (4U)
7524 #define BSEC_OTPSR_OTPNVIR_Msk         (0x1UL << BSEC_OTPSR_OTPNVIR_Pos)            /*!< 0x00000010 */
7525 #define BSEC_OTPSR_OTPNVIR             BSEC_OTPSR_OTPNVIR_Msk                      /*!< OTP not virgin */
7526 #define BSEC_OTPSR_OTPERR_Pos          (5U)
7527 #define BSEC_OTPSR_OTPERR_Msk          (0x1UL << BSEC_OTPSR_OTPERR_Pos)             /*!< 0x00000020 */
7528 #define BSEC_OTPSR_OTPERR              BSEC_OTPSR_OTPERR_Msk                       /*!< OTP with error */
7529 #define BSEC_OTPSR_OTPSEC_Pos          (6U)
7530 #define BSEC_OTPSR_OTPSEC_Msk          (0x1UL << BSEC_OTPSR_OTPSEC_Pos)             /*!< 0x00000040 */
7531 #define BSEC_OTPSR_OTPSEC              BSEC_OTPSR_OTPSEC_Msk                       /*!< OTP with single error correction */
7532 #define BSEC_OTPSR_PROGFAIL_Pos        (16U)
7533 #define BSEC_OTPSR_PROGFAIL_Msk        (0x1UL << BSEC_OTPSR_PROGFAIL_Pos)           /*!< 0x00010000 */
7534 #define BSEC_OTPSR_PROGFAIL            BSEC_OTPSR_PROGFAIL_Msk                     /*!< Programming failed */
7535 #define BSEC_OTPSR_DISTURBF_Pos        (17U)
7536 #define BSEC_OTPSR_DISTURBF_Msk        (0x1UL << BSEC_OTPSR_DISTURBF_Pos)           /*!< 0x00020000 */
7537 #define BSEC_OTPSR_DISTURBF            BSEC_OTPSR_DISTURBF_Msk                     /*!< Disturb flag */
7538 #define BSEC_OTPSR_DEDF_Pos            (18U)
7539 #define BSEC_OTPSR_DEDF_Msk            (0x1UL << BSEC_OTPSR_DEDF_Pos)               /*!< 0x00040000 */
7540 #define BSEC_OTPSR_DEDF                BSEC_OTPSR_DEDF_Msk                         /*!< Double error detection flag */
7541 #define BSEC_OTPSR_SECF_Pos            (19U)
7542 #define BSEC_OTPSR_SECF_Msk            (0x1UL << BSEC_OTPSR_SECF_Pos)               /*!< 0x00080000 */
7543 #define BSEC_OTPSR_SECF                BSEC_OTPSR_SECF_Msk                         /*!< Single error correction flag */
7544 #define BSEC_OTPSR_PPLF_Pos            (20U)
7545 #define BSEC_OTPSR_PPLF_Msk            (0x1UL << BSEC_OTPSR_PPLF_Pos)               /*!< 0x00100000 */
7546 #define BSEC_OTPSR_PPLF                BSEC_OTPSR_PPLF_Msk                         /*!< Permanent programming lock flag */
7547 #define BSEC_OTPSR_PPLMF_Pos           (21U)
7548 #define BSEC_OTPSR_PPLMF_Msk           (0x1UL << BSEC_OTPSR_PPLMF_Pos)              /*!< 0x00200000 */
7549 #define BSEC_OTPSR_PPLMF               BSEC_OTPSR_PPLMF_Msk                        /*!< Permanent programming lock mismatch flag */
7550 #define BSEC_OTPSR_AMEF_Pos            (22U)
7551 #define BSEC_OTPSR_AMEF_Msk            (0x1UL << BSEC_OTPSR_AMEF_Pos)               /*!< 0x00400000 */
7552 #define BSEC_OTPSR_AMEF                BSEC_OTPSR_AMEF_Msk                         /*!< Addresses mismatch error flag */
7553 
7554 /*****************  Bit definition for BSEC_EPOCHRx register  *****************/
7555 #define BSEC_EPOCHRx_EPOCH_Pos         (0U)
7556 #define BSEC_EPOCHRx_EPOCH_Msk         (0xFFFFFFFFUL << BSEC_EPOCHRx_EPOCH_Pos)     /*!< 0xFFFFFFFF */
7557 #define BSEC_EPOCHRx_EPOCH             BSEC_EPOCHRx_EPOCH_Msk                      /*!< Epoch */
7558 
7559 /****************  Bit definition for BSEC_EPOCHSELR register  ****************/
7560 #define BSEC_EPOCHSELR_EPSEL_Pos       (0U)
7561 #define BSEC_EPOCHSELR_EPSEL_Msk       (0x1UL << BSEC_EPOCHSELR_EPSEL_Pos)          /*!< 0x00000001 */
7562 #define BSEC_EPOCHSELR_EPSEL           BSEC_EPOCHSELR_EPSEL_Msk                    /*!< Epoch selection */
7563 
7564 /******************  Bit definition for BSEC_DBGCR register  ******************/
7565 #define BSEC_DBGCR_UNLOCK_Pos          (8U)
7566 #define BSEC_DBGCR_UNLOCK_Msk          (0xFFUL << BSEC_DBGCR_UNLOCK_Pos)            /*!< 0x0000FF00 */
7567 #define BSEC_DBGCR_UNLOCK              BSEC_DBGCR_UNLOCK_Msk                       /*!< Non-secure debug authorization */
7568 #define BSEC_DBGCR_AUTH_HDPL_Pos       (16U)
7569 #define BSEC_DBGCR_AUTH_HDPL_Msk       (0xFFUL << BSEC_DBGCR_AUTH_HDPL_Pos)         /*!< 0x00FF0000 */
7570 #define BSEC_DBGCR_AUTH_HDPL           BSEC_DBGCR_AUTH_HDPL_Msk                    /*!< Level at which debug may be opened */
7571 #define BSEC_DBGCR_AUTH_SEC_Pos        (24U)
7572 #define BSEC_DBGCR_AUTH_SEC_Msk        (0xFFUL << BSEC_DBGCR_AUTH_SEC_Pos)          /*!< 0xFF000000 */
7573 #define BSEC_DBGCR_AUTH_SEC            BSEC_DBGCR_AUTH_SEC_Msk                     /*!< Secure debug authorization */
7574 
7575 /***************  Bit definition for BSEC_AP_UNLOCK register  *****************/
7576 #define BSEC_AP_UNLOCK_UNLOCK_Pos      (0U)
7577 #define BSEC_AP_UNLOCK_UNLOCK_Msk      (0xFFUL << BSEC_AP_UNLOCK_UNLOCK_Pos)        /*!< 0x000000FF */
7578 #define BSEC_AP_UNLOCK_UNLOCK          BSEC_AP_UNLOCK_UNLOCK_Msk                   /*!< Unlock DBG_MCU AP interface */
7579 
7580 /*****************  Bit definition for BSEC_HDPLSR register  ******************/
7581 #define BSEC_HDPLSR_HDPL_Pos           (0U)
7582 #define BSEC_HDPLSR_HDPL_Msk           (0xFFUL << BSEC_HDPLSR_HDPL_Pos)             /*!< 0x000000FF */
7583 #define BSEC_HDPLSR_HDPL               BSEC_HDPLSR_HDPL_Msk                        /*!< Current HDPL */
7584 
7585 /*****************  Bit definition for BSEC_HDPLCR register  ******************/
7586 #define BSEC_HDPLCR_INCR_HDPL_Pos      (0U)
7587 #define BSEC_HDPLCR_INCR_HDPL_Msk      (0xFFFFFFFFUL << BSEC_HDPLCR_INCR_HDPL_Pos)  /*!< 0xFFFFFFFF */
7588 #define BSEC_HDPLCR_INCR_HDPL          BSEC_HDPLCR_INCR_HDPL_Msk                   /*!< Increment HDPL */
7589 
7590 /*****************  Bit definition for BSEC_NEXTLR register  ******************/
7591 #define BSEC_NEXTLR_INCR_Pos           (0U)
7592 #define BSEC_NEXTLR_INCR_Msk           (0x3UL << BSEC_NEXTLR_INCR_Pos)              /*!< 0x00000003 */
7593 #define BSEC_NEXTLR_INCR               BSEC_NEXTLR_INCR_Msk                        /*!< Increment */
7594 
7595 /*****************  Bit definition for BSEC_WOSCRx register  ******************/
7596 #define BSEC_WOSCRx_WOSDATA_Pos        (0U)
7597 #define BSEC_WOSCRx_WOSDATA_Msk        (0xFFFFFFFFUL << BSEC_WOSCRx_WOSDATA_Pos)    /*!< 0xFFFFFFFF */
7598 #define BSEC_WOSCRx_WOSDATA            BSEC_WOSCRx_WOSDATA_Msk                     /*!< Write once scratch data */
7599 
7600 /******************  Bit definition for BSEC_HRCR register  *******************/
7601 #define BSEC_HRCR_HRC_Pos              (0U)
7602 #define BSEC_HRCR_HRC_Msk              (0xFFFFFFFFUL << BSEC_HRCR_HRC_Pos)          /*!< 0xFFFFFFFF */
7603 #define BSEC_HRCR_HRC                  BSEC_HRCR_HRC_Msk                           /*!< Hot reset counter */
7604 
7605 /******************  Bit definition for BSEC_WRCR register  *******************/
7606 #define BSEC_WRCR_WRC_Pos              (0U)
7607 #define BSEC_WRCR_WRC_Msk              (0xFFFFFFFFUL << BSEC_WRCR_WRC_Pos)          /*!< 0xFFFFFFFF */
7608 #define BSEC_WRCR_WRC                  BSEC_WRCR_WRC_Msk                           /*!< Warm reset counter */
7609 
7610 
7611 /******************************************************************************/
7612 /*                                                                            */
7613 /*                                 CACHEAXI                                   */
7614 /*                                                                            */
7615 /******************************************************************************/
7616 /****************  Bit definition for CACHEAXI_CR1 register  ******************/
7617 #define CACHEAXI_CR1_EN_Pos                   (0U)
7618 #define CACHEAXI_CR1_EN_Msk                   (0x1UL << CACHEAXI_CR1_EN_Pos)             /*!< 0x00000001 */
7619 #define CACHEAXI_CR1_EN                       CACHEAXI_CR1_EN_Msk                        /*!< Enable */
7620 #define CACHEAXI_CR1_CACHEINV_Pos             (1U)
7621 #define CACHEAXI_CR1_CACHEINV_Msk             (0x1UL << CACHEAXI_CR1_CACHEINV_Pos)       /*!< 0x00000002 */
7622 #define CACHEAXI_CR1_CACHEINV                 CACHEAXI_CR1_CACHEINV_Msk                  /*!< Cache invalidation */
7623 #define CACHEAXI_CR1_RHITMEN_Pos              (16U)
7624 #define CACHEAXI_CR1_RHITMEN_Msk              (0x1UL << CACHEAXI_CR1_RHITMEN_Pos)        /*!< 0x00010000 */
7625 #define CACHEAXI_CR1_RHITMEN                  CACHEAXI_CR1_RHITMEN_Msk                   /*!< Read Hit monitor enable */
7626 #define CACHEAXI_CR1_RMISSMEN_Pos             (17U)
7627 #define CACHEAXI_CR1_RMISSMEN_Msk             (0x1UL << CACHEAXI_CR1_RMISSMEN_Pos)       /*!< 0x00020000 */
7628 #define CACHEAXI_CR1_RMISSMEN                 CACHEAXI_CR1_RMISSMEN_Msk                  /*!< Read Miss monitor enable */
7629 #define CACHEAXI_CR1_RHITMRST_Pos             (18U)
7630 #define CACHEAXI_CR1_RHITMRST_Msk             (0x1UL << CACHEAXI_CR1_RHITMRST_Pos)       /*!< 0x00040000 */
7631 #define CACHEAXI_CR1_RHITMRST                 CACHEAXI_CR1_RHITMRST_Msk                  /*!< Read Hit monitor reset */
7632 #define CACHEAXI_CR1_RMISSMRST_Pos            (19U)
7633 #define CACHEAXI_CR1_RMISSMRST_Msk            (0x1UL << CACHEAXI_CR1_RMISSMRST_Pos)      /*!< 0x00080000 */
7634 #define CACHEAXI_CR1_RMISSMRST                CACHEAXI_CR1_RMISSMRST_Msk                 /*!< Read Miss monitor reset */
7635 #define CACHEAXI_CR1_WHITMEN_Pos              (20U)
7636 #define CACHEAXI_CR1_WHITMEN_Msk              (0x1UL << CACHEAXI_CR1_WHITMEN_Pos)        /*!< 0x00100000 */
7637 #define CACHEAXI_CR1_WHITMEN                  CACHEAXI_CR1_WHITMEN_Msk                   /*!< Write Hit monitor enable */
7638 #define CACHEAXI_CR1_WMISSMEN_Pos             (21U)
7639 #define CACHEAXI_CR1_WMISSMEN_Msk             (0x1UL << CACHEAXI_CR1_WMISSMEN_Pos)       /*!< 0x00200000 */
7640 #define CACHEAXI_CR1_WMISSMEN                 CACHEAXI_CR1_WMISSMEN_Msk                  /*!< Write Miss monitor enable */
7641 #define CACHEAXI_CR1_WHITMRST_Pos             (22U)
7642 #define CACHEAXI_CR1_WHITMRST_Msk             (0x1UL << CACHEAXI_CR1_WHITMRST_Pos)       /*!< 0x00400000 */
7643 #define CACHEAXI_CR1_WHITMRST                 CACHEAXI_CR1_WHITMRST_Msk                  /*!< Write Hit monitor reset */
7644 #define CACHEAXI_CR1_WMISSMRST_Pos            (23U)
7645 #define CACHEAXI_CR1_WMISSMRST_Msk            (0x1UL << CACHEAXI_CR1_WMISSMRST_Pos)      /*!< 0x00800000 */
7646 #define CACHEAXI_CR1_WMISSMRST                CACHEAXI_CR1_WMISSMRST_Msk                 /*!< Write Miss monitor reset */
7647 #define CACHEAXI_CR1_RAMMEN_Pos               (24U)
7648 #define CACHEAXI_CR1_RAMMEN_Msk               (0x1UL << CACHEAXI_CR1_RAMMEN_Pos)         /*!< 0x01000000 */
7649 #define CACHEAXI_CR1_RAMMEN                   CACHEAXI_CR1_RAMMEN_Msk                    /*!< Read-allocate miss monitor enable */
7650 #define CACHEAXI_CR1_WAMMEN_Pos               (25U)
7651 #define CACHEAXI_CR1_WAMMEN_Msk               (0x1UL << CACHEAXI_CR1_WAMMEN_Pos)         /*!< 0x02000000 */
7652 #define CACHEAXI_CR1_WAMMEN                   CACHEAXI_CR1_WAMMEN_Msk                    /*!< Write-allocate miss monitor enable */
7653 #define CACHEAXI_CR1_RAMMRST_Pos              (26U)
7654 #define CACHEAXI_CR1_RAMMRST_Msk              (0x1UL << CACHEAXI_CR1_RAMMRST_Pos)        /*!< 0x04000000 */
7655 #define CACHEAXI_CR1_RAMMRST                  CACHEAXI_CR1_RAMMRST_Msk                   /*!< Read-allocate miss monitor reset */
7656 #define CACHEAXI_CR1_WAMMRST_Pos              (27U)
7657 #define CACHEAXI_CR1_WAMMRST_Msk              (0x1UL << CACHEAXI_CR1_WAMMRST_Pos)        /*!< 0x08000000 */
7658 #define CACHEAXI_CR1_WAMMRST                  CACHEAXI_CR1_WAMMRST_Msk                   /*!< Write-allocate miss monitor reset */
7659 #define CACHEAXI_CR1_WTMEN_Pos                (28U)
7660 #define CACHEAXI_CR1_WTMEN_Msk                (0x1UL << CACHEAXI_CR1_WTMEN_Pos)          /*!< 0x10000000 */
7661 #define CACHEAXI_CR1_WTMEN                    CACHEAXI_CR1_WTMEN_Msk                     /*!< Write-through monitor enable */
7662 #define CACHEAXI_CR1_EVIMEN_Pos               (29U)
7663 #define CACHEAXI_CR1_EVIMEN_Msk               (0x1UL << CACHEAXI_CR1_EVIMEN_Pos)         /*!< 0x20000000 */
7664 #define CACHEAXI_CR1_EVIMEN                   CACHEAXI_CR1_EVIMEN_Msk                    /*!< Eviction monitor enable */
7665 #define CACHEAXI_CR1_WTMRST_Pos               (30U)
7666 #define CACHEAXI_CR1_WTMRST_Msk               (0x1UL << CACHEAXI_CR1_WTMRST_Pos)         /*!< 0x40000000 */
7667 #define CACHEAXI_CR1_WTMRST                   CACHEAXI_CR1_WTMRST_Msk                    /*!< Write-through monitor reset */
7668 #define CACHEAXI_CR1_EVIMRST_Pos              (31U)
7669 #define CACHEAXI_CR1_EVIMRST_Msk              (0x1UL << CACHEAXI_CR1_EVIMRST_Pos)        /*!< 0x80000000 */
7670 #define CACHEAXI_CR1_EVIMRST                  CACHEAXI_CR1_EVIMRST_Msk                   /*!< Eviction monitor reset */
7671 
7672 /******************  Bit definition for CACHEAXI_SR register  *******************/
7673 #define CACHEAXI_SR_BUSYF_Pos                 (0U)
7674 #define CACHEAXI_SR_BUSYF_Msk                 (0x1UL << CACHEAXI_SR_BUSYF_Pos)           /*!< 0x00000001 */
7675 #define CACHEAXI_SR_BUSYF                     CACHEAXI_SR_BUSYF_Msk                      /*!< Busy flag */
7676 #define CACHEAXI_SR_BSYENDF_Pos               (1U)
7677 #define CACHEAXI_SR_BSYENDF_Msk               (0x1UL << CACHEAXI_SR_BSYENDF_Pos)         /*!< 0x00000002 */
7678 #define CACHEAXI_SR_BSYENDF                   CACHEAXI_SR_BSYENDF_Msk                    /*!< Busy end flag */
7679 #define CACHEAXI_SR_ERRF_Pos                  (2U)
7680 #define CACHEAXI_SR_ERRF_Msk                  (0x1UL << CACHEAXI_SR_ERRF_Pos)            /*!< 0x00000004 */
7681 #define CACHEAXI_SR_ERRF                      CACHEAXI_SR_ERRF_Msk                       /*!< Cache error flag */
7682 #define CACHEAXI_SR_BUSYCMDF_Pos              (3U)
7683 #define CACHEAXI_SR_BUSYCMDF_Msk              (0x1UL << CACHEAXI_SR_BUSYCMDF_Pos)        /*!< 0x00000008 */
7684 #define CACHEAXI_SR_BUSYCMDF                  CACHEAXI_SR_BUSYCMDF_Msk                   /*!< Busy command flag */
7685 #define CACHEAXI_SR_CMDENDF_Pos               (4U)
7686 #define CACHEAXI_SR_CMDENDF_Msk               (0x1UL << CACHEAXI_SR_CMDENDF_Pos)         /*!< 0x00000010 */
7687 #define CACHEAXI_SR_CMDENDF                   CACHEAXI_SR_CMDENDF_Msk                    /*!< Command end flag */
7688 
7689 /******************  Bit definition for CACHEAXI_IER register  ******************/
7690 #define CACHEAXI_IER_BSYENDIE_Pos             (1U)
7691 #define CACHEAXI_IER_BSYENDIE_Msk             (0x1UL << CACHEAXI_IER_BSYENDIE_Pos)       /*!< 0x00000002 */
7692 #define CACHEAXI_IER_BSYENDIE                 CACHEAXI_IER_BSYENDIE_Msk                  /*!< Busy end interrupt enable */
7693 #define CACHEAXI_IER_ERRIE_Pos                (2U)
7694 #define CACHEAXI_IER_ERRIE_Msk                (0x1UL << CACHEAXI_IER_ERRIE_Pos)          /*!< 0x00000004 */
7695 #define CACHEAXI_IER_ERRIE                    CACHEAXI_IER_ERRIE_Msk                     /*!< Cache error interrupt enable */
7696 #define CACHEAXI_IER_CMDENDIE_Pos             (4U)
7697 #define CACHEAXI_IER_CMDENDIE_Msk             (0x1UL << CACHEAXI_IER_CMDENDIE_Pos)       /*!< 0x00000010 */
7698 #define CACHEAXI_IER_CMDENDIE                 CACHEAXI_IER_CMDENDIE_Msk                  /*!< Command end interrupt enable */
7699 
7700 /******************  Bit definition for CACHEAXI_FCR register  ******************/
7701 #define CACHEAXI_FCR_CBSYENDF_Pos             (1U)
7702 #define CACHEAXI_FCR_CBSYENDF_Msk             (0x1UL << CACHEAXI_FCR_CBSYENDF_Pos)       /*!< 0x00000002 */
7703 #define CACHEAXI_FCR_CBSYENDF                 CACHEAXI_FCR_CBSYENDF_Msk                  /*!< Busy end flag clear */
7704 #define CACHEAXI_FCR_CERRF_Pos                (2U)
7705 #define CACHEAXI_FCR_CERRF_Msk                (0x1UL << CACHEAXI_FCR_CERRF_Pos)          /*!< 0x00000004 */
7706 #define CACHEAXI_FCR_CERRF                    CACHEAXI_FCR_CERRF_Msk                     /*!< Cache error flag clear */
7707 #define CACHEAXI_FCR_CCMDENDF_Pos             (4U)
7708 #define CACHEAXI_FCR_CCMDENDF_Msk             (0x1UL << CACHEAXI_FCR_CCMDENDF_Pos)       /*!< 0x00000010 */
7709 #define CACHEAXI_FCR_CCMDENDF                 CACHEAXI_FCR_CCMDENDF_Msk                  /*!< Command end flag clear */
7710 
7711 /******************  Bit definition for CACHEAXI_RHMONR register  ****************/
7712 #define CACHEAXI_RHMONR_RHITMON_Pos           (0U)
7713 #define CACHEAXI_RHMONR_RHITMON_Msk           (0xFFFFFFFFUL << CACHEAXI_RHMONR_RHITMON_Pos)  /*!< 0xFFFFFFFF */
7714 #define CACHEAXI_RHMONR_RHITMON               CACHEAXI_RHMONR_RHITMON_Msk                    /*!< Cache read hit monitor register */
7715 
7716 /******************  Bit definition for CACHEAXI_RMMONR register  ****************/
7717 #define CACHEAXI_RMMONR_RMISSMON_Pos          (0U)
7718 #define CACHEAXI_RMMONR_RMISSMON_Msk          (0xFFFFFFFFUL << CACHEAXI_RMMONR_RMISSMON_Pos) /*!< 0xFFFFFFFF */
7719 #define CACHEAXI_RMMONR_RMISSMON              CACHEAXI_RMMONR_RMISSMON_Msk                   /*!< Cache read miss monitor register */
7720 
7721 /******************  Bit definition for CACHEAXI_RAMMONR register  ****************/
7722 #define CACHEAXI_RAMMONR_RAMMON_Pos           (0U)
7723 #define CACHEAXI_RAMMONR_RAMMON_Msk           (0xFFFFFFFFUL << CACHEAXI_RAMMONR_RAMMON_Pos)  /*!< 0xFFFFFFFF */
7724 #define CACHEAXI_RAMMONR_RAMMON               CACHEAXI_RAMMONR_RAMMON_Msk                    /*!< Cache read-allocate miss monitor counter */
7725 
7726 /******************  Bit definition for CACHEAXI_EVIMONR register  ****************/
7727 #define CACHEAXI_EVIMONR_EVIMON_Pos           (0U)
7728 #define CACHEAXI_EVIMONR_EVIMON_Msk           (0xFFFFFFFFUL << CACHEAXI_EVIMONR_EVIMON_Pos)  /*!< 0xFFFFFFFF */
7729 #define CACHEAXI_EVIMONR_EVIMON               CACHEAXI_EVIMONR_EVIMON_Msk                    /*!< Cache eviction monitor counter */
7730 
7731 /******************  Bit definition for CACHEAXI_WHMONR register  ****************/
7732 #define CACHEAXI_WHMONR_WHITMON_Pos           (0U)
7733 #define CACHEAXI_WHMONR_WHITMON_Msk           (0xFFFFFFFFUL << CACHEAXI_WHMONR_WHITMON_Pos)  /*!< 0xFFFFFFFF */
7734 #define CACHEAXI_WHMONR_WHITMON               CACHEAXI_WHMONR_WHITMON_Msk                    /*!< Cache write hit monitor register */
7735 
7736 /******************  Bit definition for CACHEAXI_WMMONR register  ****************/
7737 #define CACHEAXI_WMMONR_WMISSMON_Pos          (0U)
7738 #define CACHEAXI_WMMONR_WMISSMON_Msk          (0xFFFFFFFFUL << CACHEAXI_WMMONR_WMISSMON_Pos) /*!< 0xFFFFFFFF */
7739 #define CACHEAXI_WMMONR_WMISSMON              CACHEAXI_WMMONR_WMISSMON_Msk                   /*!< Cache write miss monitor register */
7740 
7741 /******************  Bit definition for CACHEAXI_WAMMONR register  ****************/
7742 #define CACHEAXI_WAMMONR_WAMMON_Pos           (0U)
7743 #define CACHEAXI_WAMMONR_WAMMON_Msk           (0xFFFFFFFFUL << CACHEAXI_WAMMONR_WAMMON_Pos)  /*!< 0xFFFFFFFF */
7744 #define CACHEAXI_WAMMONR_WAMMON               CACHEAXI_WAMMONR_WAMMON_Msk                    /*!< Cache write-allocate miss monitor register */
7745 
7746 /******************  Bit definition for CACHEAXI_WTMONR register  ****************/
7747 #define CACHEAXI_WTMONR_WTMON_Pos             (0U)
7748 #define CACHEAXI_WTMONR_WTMON_Msk             (0xFFFFFFFFUL << CACHEAXI_WTMONR_WTMON_Pos)    /*!< 0xFFFFFFFF */
7749 #define CACHEAXI_WTMONR_WTMON                 CACHEAXI_WTMONR_WTMON_Msk                      /*!< Cache write-through monitor register */
7750 
7751 /****************  Bit definition for CACHEAXI_CR2 register  ******************/
7752 #define CACHEAXI_CR2_STARTCMD_Pos             (0U)
7753 #define CACHEAXI_CR2_STARTCMD_Msk             (0x1UL << CACHEAXI_CR2_STARTCMD_Pos)           /*!< 0x00000001 */
7754 #define CACHEAXI_CR2_STARTCMD                 CACHEAXI_CR2_STARTCMD_Msk                      /*!< Starts maintenance range command */
7755 #define CACHEAXI_CR2_CACHECMD_Pos             (1U)
7756 #define CACHEAXI_CR2_CACHECMD_Msk             (0x3UL << CACHEAXI_CR2_CACHECMD_Pos)           /*!< 0x00000006 */
7757 #define CACHEAXI_CR2_CACHECMD                 CACHEAXI_CR2_CACHECMD_Msk                      /*!< Cache command maintenance operation */
7758 #define CACHEAXI_CR2_CACHECMD_0               (0x1UL << CACHEAXI_CR2_CACHECMD_Pos)           /*!< 0x00000002 */
7759 #define CACHEAXI_CR2_CACHECMD_1               (0x2UL << CACHEAXI_CR2_CACHECMD_Pos)           /*!< 0x00000004 */
7760 
7761 /******************  Bit definition for CACHEAXI_CMDRSADDRR register  ****************/
7762 #define CACHEAXI_CMDRSADDRR_CMDSTARTADDR_Pos  (0U)
7763 #define CACHEAXI_CMDRSADDRR_CMDSTARTADDR_Msk  (0xFFFFFFC0UL << CACHEAXI_CMDRSADDRR_CMDSTARTADDR_Pos) /*!< 0xFFFFFFC0 */
7764 #define CACHEAXI_CMDRSADDRR_CMDSTARTADDR      CACHEAXI_CMDRSADDRR_CMDSTARTADDR_Msk           /*!< Command start address */
7765 
7766 /******************  Bit definition for CACHEAXI_CMDREADDRR register  ****************/
7767 #define CACHEAXI_CMDREADDRR_CMDENDADDR_Pos    (0U)
7768 #define CACHEAXI_CMDREADDRR_CMDENDADDR_Msk    (0xFFFFFFC0UL << CACHEAXI_CMDREADDRR_CMDENDADDR_Pos)   /*!< 0xFFFFFFC0 */
7769 #define CACHEAXI_CMDREADDRR_CMDENDADDR        CACHEAXI_CMDREADDRR_CMDENDADDR_Msk             /*!< Command end address */
7770 
7771 
7772 /******************************************************************************/
7773 /*                                                                            */
7774 /*                          CRC calculation unit                              */
7775 /*                                                                            */
7776 /******************************************************************************/
7777 /*******************  Bit definition for CRC_DR register  *********************/
7778 #define CRC_DR_DR_Pos              (0U)
7779 #define CRC_DR_DR_Msk              (0xFFFFFFFFUL << CRC_DR_DR_Pos)             /*!< 0xFFFFFFFF */
7780 #define CRC_DR_DR                  CRC_DR_DR_Msk                               /*!< Data register bits */
7781 
7782 /*******************  Bit definition for CRC_IDR register  ********************/
7783 #define CRC_IDR_IDR_Pos            (0U)
7784 #define CRC_IDR_IDR_Msk            (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)           /*!< 0xFFFFFFFF */
7785 #define CRC_IDR_IDR                CRC_IDR_IDR_Msk                             /*!< General-purpose 32-bits data register bits */
7786 
7787 /********************  Bit definition for CRC_CR register  ********************/
7788 #define CRC_CR_RESET_Pos           (0U)
7789 #define CRC_CR_RESET_Msk           (0x1UL << CRC_CR_RESET_Pos)                 /*!< 0x00000001 */
7790 #define CRC_CR_RESET               CRC_CR_RESET_Msk                            /*!< RESET the CRC computation unit bit */
7791 #define CRC_CR_POLYSIZE_Pos        (3U)
7792 #define CRC_CR_POLYSIZE_Msk        (0x3UL << CRC_CR_POLYSIZE_Pos)              /*!< 0x00000018 */
7793 #define CRC_CR_POLYSIZE            CRC_CR_POLYSIZE_Msk                         /*!< Polynomial size bits */
7794 #define CRC_CR_POLYSIZE_0          (0x1UL << CRC_CR_POLYSIZE_Pos)              /*!< 0x00000008 */
7795 #define CRC_CR_POLYSIZE_1          (0x2UL << CRC_CR_POLYSIZE_Pos)              /*!< 0x00000010 */
7796 #define CRC_CR_REV_IN_Pos          (5U)
7797 #define CRC_CR_REV_IN_Msk          (0x3UL << CRC_CR_REV_IN_Pos)                /*!< 0x00000060 */
7798 #define CRC_CR_REV_IN              CRC_CR_REV_IN_Msk                           /*!< REV_IN Reverse Input Data bits */
7799 #define CRC_CR_REV_IN_0            (0x1UL << CRC_CR_REV_IN_Pos)                /*!< 0x00000020 */
7800 #define CRC_CR_REV_IN_1            (0x2UL << CRC_CR_REV_IN_Pos)                /*!< 0x00000040 */
7801 #define CRC_CR_REV_OUT_Pos         (7U)
7802 #define CRC_CR_REV_OUT_Msk         (0x3UL << CRC_CR_REV_OUT_Pos)               /*!< 0x00000180 */
7803 #define CRC_CR_REV_OUT             CRC_CR_REV_OUT_Msk                          /*!< REV_OUT Reverse Output Data bits */
7804 #define CRC_CR_REV_OUT_0           (0x1UL << CRC_CR_REV_OUT_Pos)               /*!< 0x00000080 */
7805 #define CRC_CR_REV_OUT_1           (0x2UL << CRC_CR_REV_OUT_Pos)               /*!< 0x00000100 */
7806 #define CRC_CR_RTYPE_IN_Pos        (9U)
7807 #define CRC_CR_RTYPE_IN_Msk        (0x1UL << CRC_CR_RTYPE_IN_Pos)              /*!< 0x00000200 */
7808 #define CRC_CR_RTYPE_IN            CRC_CR_RTYPE_IN_Msk                         /*!< Reverse type input */
7809 #define CRC_CR_RTYPE_OUT_Pos       (10U)
7810 #define CRC_CR_RTYPE_OUT_Msk       (0x1UL << CRC_CR_RTYPE_OUT_Pos)             /*!< 0x00000400 */
7811 #define CRC_CR_RTYPE_OUT           CRC_CR_RTYPE_OUT_Msk                        /*!< Reverse type output*/
7812 
7813 /*******************  Bit definition for CRC_INIT register  *******************/
7814 #define CRC_INIT_INIT_Pos          (0U)
7815 #define CRC_INIT_INIT_Msk          (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)         /*!< 0xFFFFFFFF */
7816 #define CRC_INIT_INIT              CRC_INIT_INIT_Msk                           /*!< Initial CRC value bits */
7817 
7818 /*******************  Bit definition for CRC_POL register  ********************/
7819 #define CRC_POL_POL_Pos            (0U)
7820 #define CRC_POL_POL_Msk            (0xFFFFFFFFUL << CRC_POL_POL_Pos)           /*!< 0xFFFFFFFF */
7821 #define CRC_POL_POL                CRC_POL_POL_Msk                             /*!< Coefficients of the polynomial */
7822 
7823 
7824 /******************************************************************************/
7825 /*                                                                            */
7826 /*                             Cryp Processor                                 */
7827 /*                                                                            */
7828 /******************************************************************************/
7829 /******************* Bits definition for CRYP_CR register  ********************/
7830 #define CRYP_CR_ALGODIR_Pos              (2U)
7831 #define CRYP_CR_ALGODIR_Msk              (0x1UL << CRYP_CR_ALGODIR_Pos)           /*!< 0x00000004 */
7832 #define CRYP_CR_ALGODIR                  CRYP_CR_ALGODIR_Msk                      /*!< Algorithm direction (Encrypt/Decrypt) */
7833 
7834 #define CRYP_CR_ALGOMODE_Pos             (3U)
7835 #define CRYP_CR_ALGOMODE_Msk             (0x10007UL << CRYP_CR_ALGOMODE_Pos)      /*!< 0x00080038 */
7836 #define CRYP_CR_ALGOMODE                 CRYP_CR_ALGOMODE_Msk                     /*!< Algorithm mode */
7837 #define CRYP_CR_ALGOMODE_0               (0x00001UL << CRYP_CR_ALGOMODE_Pos)      /*!< 0x00000008 */
7838 #define CRYP_CR_ALGOMODE_1               (0x00002UL << CRYP_CR_ALGOMODE_Pos)      /*!< 0x00000010 */
7839 #define CRYP_CR_ALGOMODE_2               (0x00004UL << CRYP_CR_ALGOMODE_Pos)      /*!< 0x00000020 */
7840 #define CRYP_CR_ALGOMODE_3               (0x10000UL << CRYP_CR_ALGOMODE_Pos)      /*!< 0x00080000 */
7841 #define CRYP_CR_ALGOMODE_AES_ECB_Pos     (5U)
7842 #define CRYP_CR_ALGOMODE_AES_ECB_Msk     (0x1UL << CRYP_CR_ALGOMODE_AES_ECB_Pos)  /*!< 0x00000020 */
7843 #define CRYP_CR_ALGOMODE_AES_ECB         CRYP_CR_ALGOMODE_AES_ECB_Msk
7844 #define CRYP_CR_ALGOMODE_AES_CBC_Pos     (3U)
7845 #define CRYP_CR_ALGOMODE_AES_CBC_Msk     (0x5UL << CRYP_CR_ALGOMODE_AES_CBC_Pos)  /*!< 0x00000028 */
7846 #define CRYP_CR_ALGOMODE_AES_CBC         CRYP_CR_ALGOMODE_AES_CBC_Msk
7847 #define CRYP_CR_ALGOMODE_AES_CTR_Pos     (4U)
7848 #define CRYP_CR_ALGOMODE_AES_CTR_Msk     (0x3UL << CRYP_CR_ALGOMODE_AES_CTR_Pos)  /*!< 0x00000030 */
7849 #define CRYP_CR_ALGOMODE_AES_CTR         CRYP_CR_ALGOMODE_AES_CTR_Msk
7850 #define CRYP_CR_ALGOMODE_AES_KEY_Pos     (3U)
7851 #define CRYP_CR_ALGOMODE_AES_KEY_Msk     (0x7UL << CRYP_CR_ALGOMODE_AES_KEY_Pos)  /*!< 0x00000038 */
7852 #define CRYP_CR_ALGOMODE_AES_KEY         CRYP_CR_ALGOMODE_AES_KEY_Msk
7853 #define CRYP_CR_ALGOMODE_AES_GCM_Pos     (19U)
7854 #define CRYP_CR_ALGOMODE_AES_GCM_Msk     (0x1UL << CRYP_CR_ALGOMODE_AES_GCM_Pos)  /*!< 0x00080000 */
7855 #define CRYP_CR_ALGOMODE_AES_GCM         CRYP_CR_ALGOMODE_AES_GCM_Msk
7856 #define CRYP_CR_ALGOMODE_AES_CCM_Pos     (3U)
7857 #define CRYP_CR_ALGOMODE_AES_CCM_Msk     (0x10001UL << CRYP_CR_ALGOMODE_AES_CCM_Pos) /*!< 0x00080008 */
7858 #define CRYP_CR_ALGOMODE_AES_CCM         CRYP_CR_ALGOMODE_AES_CCM_Msk
7859 
7860 #define CRYP_CR_DATATYPE_Pos             (6U)
7861 #define CRYP_CR_DATATYPE_Msk             (0x3UL << CRYP_CR_DATATYPE_Pos)          /*!< 0x000000C0 */
7862 #define CRYP_CR_DATATYPE                 CRYP_CR_DATATYPE_Msk                     /*!< Data Type selection */
7863 #define CRYP_CR_DATATYPE_0               (0x1UL << CRYP_CR_DATATYPE_Pos)          /*!< 0x00000040 */
7864 #define CRYP_CR_DATATYPE_1               (0x2UL << CRYP_CR_DATATYPE_Pos)          /*!< 0x00000080 */
7865 #define CRYP_CR_KEYSIZE_Pos              (8U)
7866 #define CRYP_CR_KEYSIZE_Msk              (0x3UL << CRYP_CR_KEYSIZE_Pos)           /*!< 0x00000300 */
7867 #define CRYP_CR_KEYSIZE                  CRYP_CR_KEYSIZE_Msk                      /*!< Key Size selection */
7868 #define CRYP_CR_KEYSIZE_0                (0x1UL << CRYP_CR_KEYSIZE_Pos)           /*!< 0x00000100 */
7869 #define CRYP_CR_KEYSIZE_1                (0x2UL << CRYP_CR_KEYSIZE_Pos)           /*!< 0x00000200 */
7870 #define CRYP_CR_FFLUSH_Pos               (14U)
7871 #define CRYP_CR_FFLUSH_Msk               (0x1UL << CRYP_CR_FFLUSH_Pos)            /*!< 0x00004000 */
7872 #define CRYP_CR_FFLUSH                   CRYP_CR_FFLUSH_Msk                       /*!< CRYP FIFO Flush */
7873 #define CRYP_CR_CRYPEN_Pos               (15U)
7874 #define CRYP_CR_CRYPEN_Msk               (0x1UL << CRYP_CR_CRYPEN_Pos)            /*!< 0x00008000 */
7875 #define CRYP_CR_CRYPEN                   CRYP_CR_CRYPEN_Msk                       /*!< CRYP processor enable */
7876 
7877 #define CRYP_CR_GCM_CCMPH_Pos            (16U)
7878 #define CRYP_CR_GCM_CCMPH_Msk            (0x3UL << CRYP_CR_GCM_CCMPH_Pos)         /*!< 0x00030000 */
7879 #define CRYP_CR_GCM_CCMPH                CRYP_CR_GCM_CCMPH_Msk                    /*!< GCM or CCM Phase selection */
7880 #define CRYP_CR_GCM_CCMPH_0              (0x1UL << CRYP_CR_GCM_CCMPH_Pos)         /*!< 0x00010000 */
7881 #define CRYP_CR_GCM_CCMPH_1              (0x2UL << CRYP_CR_GCM_CCMPH_Pos)         /*!< 0x00020000 */
7882 
7883 #define CRYP_CR_NPBLB_Pos                (20U)
7884 #define CRYP_CR_NPBLB_Msk                (0xFUL << CRYP_CR_NPBLB_Pos)             /*!< 0x00F00000 */
7885 #define CRYP_CR_NPBLB                    CRYP_CR_NPBLB_Msk                        /*!< Number of Padding Bytes in Last Block of payload */
7886 
7887 #define CRYP_CR_KMOD_Pos                (24U)
7888 #define CRYP_CR_KMOD_Msk                (0x3UL << CRYP_CR_KMOD_Pos)               /*!< 0x03000000 */
7889 #define CRYP_CR_KMOD                    CRYP_CR_KMOD_Msk                          /*!< Key mode selection */
7890 #define CRYP_CR_KMOD_0                  (0x1UL << CRYP_CR_KMOD_Pos)               /*!< 0x01000000 */
7891 #define CRYP_CR_KMOD_1                  (0x2UL << CRYP_CR_KMOD_Pos)               /*!< 0x02000000 */
7892 
7893 #define CRYP_CR_IPRST_Pos               (31U)
7894 #define CRYP_CR_IPRST_Msk               (0x1UL << CRYP_CR_IPRST_Pos)              /*!< 0x80000000 */
7895 #define CRYP_CR_IPRST                   CRYP_CR_IPRST_Msk                         /*!< CRYP peripheral software reset */
7896 
7897 /****************** Bits definition for CRYP_SR register  *********************/
7898 #define CRYP_SR_IFEM_Pos                 (0U)
7899 #define CRYP_SR_IFEM_Msk                 (0x1UL << CRYP_SR_IFEM_Pos)              /*!< 0x00000001 */
7900 #define CRYP_SR_IFEM                     CRYP_SR_IFEM_Msk                         /*!< Input FIFO empty flag */
7901 #define CRYP_SR_IFNF_Pos                 (1U)
7902 #define CRYP_SR_IFNF_Msk                 (0x1UL << CRYP_SR_IFNF_Pos)              /*!< 0x00000002 */
7903 #define CRYP_SR_IFNF                     CRYP_SR_IFNF_Msk                         /*!< Input FIFO not full flag */
7904 #define CRYP_SR_OFNE_Pos                 (2U)
7905 #define CRYP_SR_OFNE_Msk                 (0x1UL << CRYP_SR_OFNE_Pos)              /*!< 0x00000004 */
7906 #define CRYP_SR_OFNE                     CRYP_SR_OFNE_Msk                         /*!< Output FIFO not empty flag */
7907 #define CRYP_SR_OFFU_Pos                 (3U)
7908 #define CRYP_SR_OFFU_Msk                 (0x1UL << CRYP_SR_OFFU_Pos)              /*!< 0x00000008 */
7909 #define CRYP_SR_OFFU                     CRYP_SR_OFFU_Msk                         /*!< Output FIFO full flag */
7910 #define CRYP_SR_BUSY_Pos                 (4U)
7911 #define CRYP_SR_BUSY_Msk                 (0x1UL << CRYP_SR_BUSY_Pos)              /*!< 0x00000010 */
7912 #define CRYP_SR_BUSY                     CRYP_SR_BUSY_Msk                         /*!< Busy bit */
7913 #define CRYP_SR_KERF_Pos                 (6U)
7914 #define CRYP_SR_KERF_Msk                 (0x1UL << CRYP_SR_KERF_Pos)              /*!< 0x00000040 */
7915 #define CRYP_SR_KERF                     CRYP_SR_KERF_Msk                         /*!< Key error flag */
7916 #define CRYP_SR_KEYVALID_Pos             (7U)
7917 #define CRYP_SR_KEYVALID_Msk             (0x1UL << CRYP_SR_KEYVALID_Pos)          /*!< 0x00000080 */
7918 #define CRYP_SR_KEYVALID                 CRYP_SR_KEYVALID_Msk                     /*!< Key valid flag */
7919 
7920 /*******************  Bit definition for CRYP_DIN register  *******************/
7921 #define CRYP_DIN_DATAIN_Pos              (0U)
7922 #define CRYP_DIN_DATAIN_Msk              (0xFFFFFFFFUL << CRYP_DIN_DATAIN_Pos)    /*!< 0xFFFFFFFF */
7923 #define CRYP_DIN_DATAIN                  CRYP_DIN_DATAIN_Msk                      /*!< CRYP Data Input */
7924 
7925 /*******************  Bit definition for CRYP_DIN register  *******************/
7926 #define CRYP_DOUT_DATAOUT_Pos            (0U)
7927 #define CRYP_DOUT_DATAOUT_Msk            (0xFFFFFFFFUL << CRYP_DOUT_DATAOUT_Pos)  /*!< 0xFFFFFFFF */
7928 #define CRYP_DOUT_DATAOUT                CRYP_DOUT_DATAOUT_Msk                    /*!< CRYP Data Output */
7929 
7930 /****************** Bits definition for CRYP_DMACR register  ******************/
7931 #define CRYP_DMACR_DIEN_Pos              (0U)
7932 #define CRYP_DMACR_DIEN_Msk              (0x1UL << CRYP_DMACR_DIEN_Pos)           /*!< 0x00000001 */
7933 #define CRYP_DMACR_DIEN                  CRYP_DMACR_DIEN_Msk                      /*!< DMA Input Enable */
7934 #define CRYP_DMACR_DOEN_Pos              (1U)
7935 #define CRYP_DMACR_DOEN_Msk              (0x1UL << CRYP_DMACR_DOEN_Pos)           /*!< 0x00000002 */
7936 #define CRYP_DMACR_DOEN                  CRYP_DMACR_DOEN_Msk                      /*!< DMA Output Enable */
7937 
7938 /*****************  Bits definition for CRYP_IMSCR register  ******************/
7939 #define CRYP_IMSCR_INIM_Pos              (0U)
7940 #define CRYP_IMSCR_INIM_Msk              (0x1UL << CRYP_IMSCR_INIM_Pos)           /*!< 0x00000001 */
7941 #define CRYP_IMSCR_INIM                  CRYP_IMSCR_INIM_Msk                      /*!< Input FIFO service interrupt mask */
7942 #define CRYP_IMSCR_OUTIM_Pos             (1U)
7943 #define CRYP_IMSCR_OUTIM_Msk             (0x1UL << CRYP_IMSCR_OUTIM_Pos)          /*!< 0x00000002 */
7944 #define CRYP_IMSCR_OUTIM                 CRYP_IMSCR_OUTIM_Msk                     /*!< Output FIFO service interrupt mask */
7945 
7946 /****************** Bits definition for CRYP_RISR register  *******************/
7947 #define CRYP_RISR_INRIS_Pos              (0U)
7948 #define CRYP_RISR_INRIS_Msk              (0x1UL << CRYP_RISR_INRIS_Pos)           /*!< 0x00000001 */
7949 #define CRYP_RISR_INRIS                  CRYP_RISR_INRIS_Msk                      /*!< Input FIFO service raw interrupt status */
7950 #define CRYP_RISR_OUTRIS_Pos             (1U)
7951 #define CRYP_RISR_OUTRIS_Msk             (0x1UL << CRYP_RISR_OUTRIS_Pos)          /*!< 0x00000002 */
7952 #define CRYP_RISR_OUTRIS                 CRYP_RISR_OUTRIS_Msk                     /*!< Output FIFO service raw interrupt mask */
7953 
7954 /****************** Bits definition for CRYP_MISR register  *******************/
7955 #define CRYP_MISR_INMIS_Pos              (0U)
7956 #define CRYP_MISR_INMIS_Msk              (0x1UL << CRYP_MISR_INMIS_Pos)           /*!< 0x00000001 */
7957 #define CRYP_MISR_INMIS                  CRYP_MISR_INMIS_Msk                      /*!< Input FIFO service masked interrupt status */
7958 #define CRYP_MISR_OUTMIS_Pos             (1U)
7959 #define CRYP_MISR_OUTMIS_Msk             (0x1UL << CRYP_MISR_OUTMIS_Pos)          /*!< 0x00000002 */
7960 #define CRYP_MISR_OUTMIS                 CRYP_MISR_OUTMIS_Msk                     /*!< Output FIFO service masked interrupt status */
7961 
7962 /*******************  Bit definition for CRYP_K0LR register  ******************/
7963 #define CRYP_K0LR_K_Pos                  (0U)
7964 #define CRYP_K0LR_K_Msk                  (0xFFFFFFFFUL << CRYP_K0LR_K_Pos)        /*!< 0xFFFFFFFF */
7965 #define CRYP_K0LR_K                      CRYP_K0LR_K_Msk                          /*!< AES key bit x (x= 224 to 255) */
7966 
7967 /*******************  Bit definition for CRYP_K0RR register  ******************/
7968 #define CRYP_K0RR_K_Pos                  (0U)
7969 #define CRYP_K0RR_K_Msk                  (0xFFFFFFFFUL << CRYP_K0RR_K_Pos)        /*!< 0xFFFFFFFF */
7970 #define CRYP_K0RR_K                      CRYP_K0RR_K_Msk                          /*!< AES key bit x (x= 192 to 223) */
7971 
7972 /*******************  Bit definition for CRYP_IV1LR register  ******************/
7973 #define CRYP_IV1LR_K_Pos                  (0U)
7974 #define CRYP_IV1LR_K_Msk                  (0xFFFFFFFFUL << CRYP_IV1LR_K_Pos)        /*!< 0xFFFFFFFF */
7975 #define CRYP_IV1LR_K                      CRYP_IV1LR_K_Msk                          /*!< AES key bit x (x= 160 to 291) */
7976 
7977 /*******************  Bit definition for CRYP_IV1RR register  ******************/
7978 #define CRYP_IV1RR_K_Pos                  (0U)
7979 #define CRYP_IV1RR_K_Msk                  (0xFFFFFFFFUL << CRYP_IV1RR_K_Pos)        /*!< 0xFFFFFFFF */
7980 #define CRYP_IV1RR_K                      CRYP_IV1RR_K_Msk                          /*!< AES key bit x (x= 128 to 159) */
7981 
7982 /*******************  Bit definition for CRYP_K2LR register  ******************/
7983 #define CRYP_K2LR_K_Pos                  (0U)
7984 #define CRYP_K2LR_K_Msk                  (0xFFFFFFFFUL << CRYP_K2LR_K_Pos)        /*!< 0xFFFFFFFF */
7985 #define CRYP_K2LR_K                      CRYP_K2LR_K_Msk                          /*!< AES key bit x (x= 96 to 127) */
7986 
7987 /*******************  Bit definition for CRYP_K2RR register  ******************/
7988 #define CRYP_K2RR_K_Pos                  (0U)
7989 #define CRYP_K2RR_K_Msk                  (0xFFFFFFFFUL << CRYP_K2RR_K_Pos)        /*!< 0xFFFFFFFF */
7990 #define CRYP_K2RR_K                      CRYP_K2RR_K_Msk                          /*!< AES key bit x (x= 64 to 95) */
7991 
7992 /*******************  Bit definition for CRYP_K3LR register  ******************/
7993 #define CRYP_K3LR_K_Pos                  (0U)
7994 #define CRYP_K3LR_K_Msk                  (0xFFFFFFFFUL << CRYP_K3LR_K_Pos)        /*!< 0xFFFFFFFF */
7995 #define CRYP_K3LR_K                      CRYP_K3LR_K_Msk                          /*!< AES key bit x (x= 32 to 63) */
7996 
7997 /*******************  Bit definition for CRYP_K3RR register  ******************/
7998 #define CRYP_K3RR_K_Pos                  (0U)
7999 #define CRYP_K3RR_K_Msk                  (0xFFFFFFFFUL << CRYP_K3RR_K_Pos)        /*!< 0xFFFFFFFF */
8000 #define CRYP_K3RR_K                      CRYP_K3RR_K_Msk                          /*!< AES key bit x (x= 0 to 31) */
8001 
8002 /*******************  Bit definition for CRYP_IV0LR register  ******************/
8003 #define CRYP_IV0LR_IV_Pos                (0U)
8004 #define CRYP_IV0LR_IV_Msk                (0xFFFFFFFFUL << CRYP_IV0LR_IV_Pos)      /*!< 0xFFFFFFFF */
8005 #define CRYP_IV0LR_IV                    CRYP_IV0LR_IV_Msk                        /*!< Initialization vector bit x (x= 0 to 31) */
8006 
8007 /*******************  Bit definition for CRYP_IV0RR register  ******************/
8008 #define CRYP_IV0RR_IV_Pos                (0U)
8009 #define CRYP_IV0RR_IV_Msk                (0xFFFFFFFFUL << CRYP_IV0RR_IV_Pos)      /*!< 0xFFFFFFFF */
8010 #define CRYP_IV0RR_IV                    CRYP_IV0RR_IV_Msk                        /*!< Initialization vector bit x (x= 32 to 63) */
8011 
8012 /*******************  Bit definition for CRYP_IV1LR register  ******************/
8013 #define CRYP_IV1LR_IV_Pos                (0U)
8014 #define CRYP_IV1LR_IV_Msk                (0xFFFFFFFFUL << CRYP_IV1LR_IV_Pos)      /*!< 0xFFFFFFFF */
8015 #define CRYP_IV1LR_IV                    CRYP_IV1LR_IV_Msk                        /*!< Initialization vector bit x (x= 64 to 95) */
8016 
8017 /*******************  Bit definition for CRYP_IV1RR register  ******************/
8018 #define CRYP_IV1RR_IV_Pos                (0U)
8019 #define CRYP_IV1RR_IV_Msk                (0xFFFFFFFFUL << CRYP_IV1RR_IV_Pos)      /*!< 0xFFFFFFFF */
8020 #define CRYP_IV1RR_IV                    CRYP_IV1RR_IV_Msk                        /*!< Initialization vector bit x (x= 96 to 127) */
8021 
8022 /*******************  Bit definition for CRYP_CSGCMCCM0R register  ******************/
8023 #define CRYP_CSGCMCCM0R_CSGCMCCM0_Pos          (0U)
8024 #define CRYP_CSGCMCCM0R_CSGCMCCM0_Msk          (0xFFFFFFFFUL << CRYP_CSGCMCCM0R_CSGCMCCM0_Pos) /*!< 0xFFFFFFFF */
8025 #define CRYP_CSGCMCCM0R_CSGCMCCM0              CRYP_CSGCMCCM0R_CSGCMCCM0_Msk                   /*!< CRYP internal state registers for GCM, GMAC and CCM modes */
8026 
8027 /*******************  Bit definition for CRYP_CSGCMCCM1R register  ******************/
8028 #define CRYP_CSGCMCCM1R_CSGCMCCM1_Pos          (0U)
8029 #define CRYP_CSGCMCCM1R_CSGCMCCM1_Msk          (0xFFFFFFFFUL << CRYP_CSGCMCCM1R_CSGCMCCM1_Pos) /*!< 0xFFFFFFFF */
8030 #define CRYP_CSGCMCCM1R_CSGCMCCM1              CRYP_CSGCMCCM1R_CSGCMCCM1_Msk                   /*!< CRYP internal state registers for GCM, GMAC and CCM modes */
8031 
8032 /*******************  Bit definition for CRYP_CSGCMCCM2R register  ******************/
8033 #define CRYP_CSGCMCCM2R_CSGCMCCM2_Pos          (0U)
8034 #define CRYP_CSGCMCCM2R_CSGCMCCM2_Msk          (0xFFFFFFFFUL << CRYP_CSGCMCCM2R_CSGCMCCM2_Pos) /*!< 0xFFFFFFFF */
8035 #define CRYP_CSGCMCCM2R_CSGCMCCM2              CRYP_CSGCMCCM2R_CSGCMCCM2_Msk                   /*!< CRYP internal state registers for GCM, GMAC and CCM modes */
8036 
8037 /*******************  Bit definition for CRYP_CSGCMCCM3R register  ******************/
8038 #define CRYP_CSGCMCCM3R_CSGCMCCM3_Pos          (0U)
8039 #define CRYP_CSGCMCCM3R_CSGCMCCM3_Msk          (0xFFFFFFFFUL << CRYP_CSGCMCCM3R_CSGCMCCM3_Pos) /*!< 0xFFFFFFFF */
8040 #define CRYP_CSGCMCCM3R_CSGCMCCM3              CRYP_CSGCMCCM3R_CSGCMCCM3_Msk                   /*!< CRYP internal state registers for GCM, GMAC and CCM modes */
8041 
8042 /*******************  Bit definition for CRYP_CSGCMCCM4R register  ******************/
8043 #define CRYP_CSGCMCCM4R_CSGCMCCM4_Pos          (0U)
8044 #define CRYP_CSGCMCCM4R_CSGCMCCM4_Msk          (0xFFFFFFFFUL << CRYP_CSGCMCCM4R_CSGCMCCM4_Pos) /*!< 0xFFFFFFFF */
8045 #define CRYP_CSGCMCCM4R_CSGCMCCM4              CRYP_CSGCMCCM4R_CSGCMCCM4_Msk                   /*!< CRYP internal state registers for GCM, GMAC and CCM modes */
8046 
8047 /*******************  Bit definition for CRYP_CSGCMCCM5R register  ******************/
8048 #define CRYP_CSGCMCCM5R_CSGCMCCM5_Pos          (0U)
8049 #define CRYP_CSGCMCCM5R_CSGCMCCM5_Msk          (0xFFFFFFFFUL << CRYP_CSGCMCCM5R_CSGCMCCM5_Pos) /*!< 0xFFFFFFFF */
8050 #define CRYP_CSGCMCCM5R_CSGCMCCM5              CRYP_CSGCMCCM5R_CSGCMCCM5_Msk                   /*!< CRYP internal state registers for GCM, GMAC and CCM modes */
8051 
8052 /*******************  Bit definition for CRYP_CSGCMCCM6R register  ******************/
8053 #define CRYP_CSGCMCCM6R_CSGCMCCM6_Pos          (0U)
8054 #define CRYP_CSGCMCCM6R_CSGCMCCM6_Msk          (0xFFFFFFFFUL << CRYP_CSGCMCCM6R_CSGCMCCM6_Pos) /*!< 0xFFFFFFFF */
8055 #define CRYP_CSGCMCCM6R_CSGCMCCM6              CRYP_CSGCMCCM6R_CSGCMCCM6_Msk                   /*!< CRYP internal state registers for GCM, GMAC and CCM modes */
8056 
8057 /*******************  Bit definition for CRYP_CSGCMCCM7R register  ******************/
8058 #define CRYP_CSGCMCCM7R_CSGCMCCM7_Pos          (0U)
8059 #define CRYP_CSGCMCCM7R_CSGCMCCM7_Msk          (0xFFFFFFFFUL << CRYP_CSGCMCCM7R_CSGCMCCM7_Pos) /*!< 0xFFFFFFFF */
8060 #define CRYP_CSGCMCCM7R_CSGCMCCM7              CRYP_CSGCMCCM7R_CSGCMCCM7_Msk                   /*!< CRYP internal state registers for GCM, GMAC and CCM modes */
8061 
8062 /*******************  Bit definition for CRYP_CSGCM0R register  ******************/
8063 #define CRYP_CSGCM0R_CSGCM0_Pos          (0U)
8064 #define CRYP_CSGCM0R_CSGCM0_Msk          (0xFFFFFFFFUL << CRYP_CSGCM0R_CSGCM0_Pos) /*!< 0xFFFFFFFF */
8065 #define CRYP_CSGCM0R_CSGCM0              CRYP_CSGCM0R_CSGCM0_Msk                   /*!< CRYP internal state registers for GCM and GMAC modes */
8066 
8067 /*******************  Bit definition for CRYP_CSGCM1R register  ******************/
8068 #define CRYP_CSGCM1R_CSGCM1_Pos          (0U)
8069 #define CRYP_CSGCM1R_CSGCM1_Msk          (0xFFFFFFFFUL << CRYP_CSGCM1R_CSGCM1_Pos) /*!< 0xFFFFFFFF */
8070 #define CRYP_CSGCM1R_CSGCM1              CRYP_CSGCM1R_CSGCM1_Msk                   /*!< CRYP internal state registers for GCM and GMAC modes */
8071 
8072 /*******************  Bit definition for CRYP_CSGCM2R register  ******************/
8073 #define CRYP_CSGCM2R_CSGCM2_Pos          (0U)
8074 #define CRYP_CSGCM2R_CSGCM2_Msk          (0xFFFFFFFFUL << CRYP_CSGCM2R_CSGCM2_Pos) /*!< 0xFFFFFFFF */
8075 #define CRYP_CSGCM2R_CSGCM2              CRYP_CSGCM2R_CSGCM2_Msk                   /*!< CRYP internal state registers for GCM and GMAC modes */
8076 
8077 /*******************  Bit definition for CRYP_CSGCM3R register  ******************/
8078 #define CRYP_CSGCM3R_CSGCM3_Pos          (0U)
8079 #define CRYP_CSGCM3R_CSGCM3_Msk          (0xFFFFFFFFUL << CRYP_CSGCM3R_CSGCM3_Pos) /*!< 0xFFFFFFFF */
8080 #define CRYP_CSGCM3R_CSGCM3              CRYP_CSGCM3R_CSGCM3_Msk                   /*!< CRYP internal state registers for GCM and GMAC modes */
8081 
8082 /*******************  Bit definition for CRYP_CSGCM4R register  ******************/
8083 #define CRYP_CSGCM4R_CSGCM4_Pos          (0U)
8084 #define CRYP_CSGCM4R_CSGCM4_Msk          (0xFFFFFFFFUL << CRYP_CSGCM4R_CSGCM4_Pos) /*!< 0xFFFFFFFF */
8085 #define CRYP_CSGCM4R_CSGCM4              CRYP_CSGCM4R_CSGCM4_Msk                   /*!< CRYP internal state registers for GCM and GMAC modes */
8086 
8087 /*******************  Bit definition for CRYP_CSGCM5R register  ******************/
8088 #define CRYP_CSGCM5R_CSGCM5_Pos          (0U)
8089 #define CRYP_CSGCM5R_CSGCM5_Msk          (0xFFFFFFFFUL << CRYP_CSGCM5R_CSGCM5_Pos) /*!< 0xFFFFFFFF */
8090 #define CRYP_CSGCM5R_CSGCM5              CRYP_CSGCM5R_CSGCM5_Msk                   /*!< CRYP internal state registers for GCM and GMAC modes */
8091 
8092 /*******************  Bit definition for CRYP_CSGCM6R register  ******************/
8093 #define CRYP_CSGCM6R_CSGCM6_Pos          (0U)
8094 #define CRYP_CSGCM6R_CSGCM6_Msk          (0xFFFFFFFFUL << CRYP_CSGCM6R_CSGCM6_Pos) /*!< 0xFFFFFFFF */
8095 #define CRYP_CSGCM6R_CSGCM6              CRYP_CSGCM6R_CSGCM6_Msk                   /*!< CRYP internal state registers for GCM and GMAC modes */
8096 
8097 /*******************  Bit definition for CRYP_CSGCM7R register  ******************/
8098 #define CRYP_CSGCM7R_CSGCM7_Pos          (0U)
8099 #define CRYP_CSGCM7R_CSGCM7_Msk          (0xFFFFFFFFUL << CRYP_CSGCM7R_CSGCM7_Pos) /*!< 0xFFFFFFFF */
8100 #define CRYP_CSGCM7R_CSGCM7              CRYP_CSGCM7R_CSGCM7_Msk                   /*!< CRYP internal state registers for GCM and GMAC modes */
8101 
8102 
8103 /******************************************************************************/
8104 /*                                                                            */
8105 /*                                    (CSI)                                   */
8106 /*                                                                            */
8107 /******************************************************************************/
8108 /********************  Bit definition for CSI_CR register  ********************/
8109 #define CSI_CR_CSIEN_Pos                (0U)
8110 #define CSI_CR_CSIEN_Msk                (0x1UL << CSI_CR_CSIEN_Pos)               /*!< 0x00000001 */
8111 #define CSI_CR_CSIEN                    CSI_CR_CSIEN_Msk                         /*!< CSI-2 enable */
8112 #define CSI_CR_VC0START_Pos             (2U)
8113 #define CSI_CR_VC0START_Msk             (0x1UL << CSI_CR_VC0START_Pos)            /*!< 0x00000004 */
8114 #define CSI_CR_VC0START                 CSI_CR_VC0START_Msk                      /*!< Virtual channel 0 start */
8115 #define CSI_CR_VC0STOP_Pos              (3U)
8116 #define CSI_CR_VC0STOP_Msk              (0x1UL << CSI_CR_VC0STOP_Pos)             /*!< 0x00000008 */
8117 #define CSI_CR_VC0STOP                  CSI_CR_VC0STOP_Msk                       /*!< Virtual channel 0 stop */
8118 #define CSI_CR_VC1START_Pos             (6U)
8119 #define CSI_CR_VC1START_Msk             (0x1UL << CSI_CR_VC1START_Pos)            /*!< 0x00000040 */
8120 #define CSI_CR_VC1START                 CSI_CR_VC1START_Msk                      /*!< Virtual channel 1 start */
8121 #define CSI_CR_VC1STOP_Pos              (7U)
8122 #define CSI_CR_VC1STOP_Msk              (0x1UL << CSI_CR_VC1STOP_Pos)             /*!< 0x00000080 */
8123 #define CSI_CR_VC1STOP                  CSI_CR_VC1STOP_Msk                       /*!< Virtual channel 1 stop */
8124 #define CSI_CR_VC2START_Pos             (10U)
8125 #define CSI_CR_VC2START_Msk             (0x1UL << CSI_CR_VC2START_Pos)            /*!< 0x00000400 */
8126 #define CSI_CR_VC2START                 CSI_CR_VC2START_Msk                      /*!< Virtual channel 2 start */
8127 #define CSI_CR_VC2STOP_Pos              (11U)
8128 #define CSI_CR_VC2STOP_Msk              (0x1UL << CSI_CR_VC2STOP_Pos)             /*!< 0x00000800 */
8129 #define CSI_CR_VC2STOP                  CSI_CR_VC2STOP_Msk                       /*!< Virtual channel 2 stop */
8130 #define CSI_CR_VC3START_Pos             (14U)
8131 #define CSI_CR_VC3START_Msk             (0x1UL << CSI_CR_VC3START_Pos)            /*!< 0x00004000 */
8132 #define CSI_CR_VC3START                 CSI_CR_VC3START_Msk                      /*!< Virtual channel 3 start */
8133 #define CSI_CR_VC3STOP_Pos              (15U)
8134 #define CSI_CR_VC3STOP_Msk              (0x1UL << CSI_CR_VC3STOP_Pos)             /*!< 0x00008000 */
8135 #define CSI_CR_VC3STOP                  CSI_CR_VC3STOP_Msk                       /*!< Virtual channel 3 stop */
8136 
8137 /*******************  Bit definition for CSI_PCR register  ********************/
8138 #define CSI_PCR_PWRDOWN_Pos             (0U)
8139 #define CSI_PCR_PWRDOWN_Msk             (0x1UL << CSI_PCR_PWRDOWN_Pos)            /*!< 0x00000001 */
8140 #define CSI_PCR_PWRDOWN                 CSI_PCR_PWRDOWN_Msk                      /*!< Virtual channel 3 start */
8141 #define CSI_PCR_CLEN_Pos                (1U)
8142 #define CSI_PCR_CLEN_Msk                (0x1UL << CSI_PCR_CLEN_Pos)               /*!< 0x00000002 */
8143 #define CSI_PCR_CLEN                    CSI_PCR_CLEN_Msk                         /*!< Clock lane enable */
8144 #define CSI_PCR_DL0EN_Pos               (2U)
8145 #define CSI_PCR_DL0EN_Msk               (0x1UL << CSI_PCR_DL0EN_Pos)              /*!< 0x00000004 */
8146 #define CSI_PCR_DL0EN                   CSI_PCR_DL0EN_Msk                        /*!< D-PHY_RX data lane 0 enable */
8147 #define CSI_PCR_DL1EN_Pos               (3U)
8148 #define CSI_PCR_DL1EN_Msk               (0x1UL << CSI_PCR_DL1EN_Pos)              /*!< 0x00000008 */
8149 #define CSI_PCR_DL1EN                   CSI_PCR_DL1EN_Msk                        /*!< D-PHY_RX data lane 1 enable */
8150 
8151 /*****************  Bit definition for CSI_VC0CFGR1 register  *****************/
8152 #define CSI_VC0CFGR1_ALLDT_Pos          (0U)
8153 #define CSI_VC0CFGR1_ALLDT_Msk          (0x1UL << CSI_VC0CFGR1_ALLDT_Pos)         /*!< 0x00000001 */
8154 #define CSI_VC0CFGR1_ALLDT              CSI_VC0CFGR1_ALLDT_Msk                   /*!< All data types enable for the virtual channel x */
8155 #define CSI_VC0CFGR1_DT0EN_Pos          (1U)
8156 #define CSI_VC0CFGR1_DT0EN_Msk          (0x1UL << CSI_VC0CFGR1_DT0EN_Pos)         /*!< 0x00000002 */
8157 #define CSI_VC0CFGR1_DT0EN              CSI_VC0CFGR1_DT0EN_Msk                   /*!< Data type 0 enable */
8158 #define CSI_VC0CFGR1_DT1EN_Pos          (2U)
8159 #define CSI_VC0CFGR1_DT1EN_Msk          (0x1UL << CSI_VC0CFGR1_DT1EN_Pos)         /*!< 0x00000004 */
8160 #define CSI_VC0CFGR1_DT1EN              CSI_VC0CFGR1_DT1EN_Msk                   /*!< Data type 1 enable */
8161 #define CSI_VC0CFGR1_DT2EN_Pos          (3U)
8162 #define CSI_VC0CFGR1_DT2EN_Msk          (0x1UL << CSI_VC0CFGR1_DT2EN_Pos)         /*!< 0x00000008 */
8163 #define CSI_VC0CFGR1_DT2EN              CSI_VC0CFGR1_DT2EN_Msk                   /*!< Data type 2 enable */
8164 #define CSI_VC0CFGR1_DT3EN_Pos          (4U)
8165 #define CSI_VC0CFGR1_DT3EN_Msk          (0x1UL << CSI_VC0CFGR1_DT3EN_Pos)         /*!< 0x00000010 */
8166 #define CSI_VC0CFGR1_DT3EN              CSI_VC0CFGR1_DT3EN_Msk                   /*!< Data type 3 enable */
8167 #define CSI_VC0CFGR1_DT4EN_Pos          (5U)
8168 #define CSI_VC0CFGR1_DT4EN_Msk          (0x1UL << CSI_VC0CFGR1_DT4EN_Pos)         /*!< 0x00000020 */
8169 #define CSI_VC0CFGR1_DT4EN              CSI_VC0CFGR1_DT4EN_Msk                   /*!< Data type 4 enable */
8170 #define CSI_VC0CFGR1_DT5EN_Pos          (6U)
8171 #define CSI_VC0CFGR1_DT5EN_Msk          (0x1UL << CSI_VC0CFGR1_DT5EN_Pos)         /*!< 0x00000040 */
8172 #define CSI_VC0CFGR1_DT5EN              CSI_VC0CFGR1_DT5EN_Msk                   /*!< Data type 5 enable */
8173 #define CSI_VC0CFGR1_DT6EN_Pos          (7U)
8174 #define CSI_VC0CFGR1_DT6EN_Msk          (0x1UL << CSI_VC0CFGR1_DT6EN_Pos)         /*!< 0x00000080 */
8175 #define CSI_VC0CFGR1_DT6EN              CSI_VC0CFGR1_DT6EN_Msk                   /*!< Data type 6 enable */
8176 #define CSI_VC0CFGR1_CDTFT_Pos          (8U)
8177 #define CSI_VC0CFGR1_CDTFT_Msk          (0x1FUL << CSI_VC0CFGR1_CDTFT_Pos)        /*!< 0x00001F00 */
8178 #define CSI_VC0CFGR1_CDTFT              CSI_VC0CFGR1_CDTFT_Msk                   /*!< Common format for all data types */
8179 #define CSI_VC0CFGR1_DT0_Pos            (16U)
8180 #define CSI_VC0CFGR1_DT0_Msk            (0x3FUL << CSI_VC0CFGR1_DT0_Pos)          /*!< 0x003F0000 */
8181 #define CSI_VC0CFGR1_DT0                CSI_VC0CFGR1_DT0_Msk                     /*!< Data type 0 class selection for virtual channel x */
8182 #define CSI_VC0CFGR1_DT0FT_Pos          (24U)
8183 #define CSI_VC0CFGR1_DT0FT_Msk          (0x1FUL << CSI_VC0CFGR1_DT0FT_Pos)        /*!< 0x1F000000 */
8184 #define CSI_VC0CFGR1_DT0FT              CSI_VC0CFGR1_DT0FT_Msk                   /*!< Data type 0 format */
8185 
8186 /*****************  Bit definition for CSI_VC0CFGR2 register  *****************/
8187 #define CSI_VC0CFGR2_DT1_Pos            (0U)
8188 #define CSI_VC0CFGR2_DT1_Msk            (0x3FUL << CSI_VC0CFGR2_DT1_Pos)          /*!< 0x0000003F */
8189 #define CSI_VC0CFGR2_DT1                CSI_VC0CFGR2_DT1_Msk                     /*!< Data type 1 class selection for virtual channel x */
8190 #define CSI_VC0CFGR2_DT1FT_Pos          (8U)
8191 #define CSI_VC0CFGR2_DT1FT_Msk          (0x1FUL << CSI_VC0CFGR2_DT1FT_Pos)        /*!< 0x00001F00 */
8192 #define CSI_VC0CFGR2_DT1FT              CSI_VC0CFGR2_DT1FT_Msk                   /*!< Data type 1 format */
8193 #define CSI_VC0CFGR2_DT2_Pos            (16U)
8194 #define CSI_VC0CFGR2_DT2_Msk            (0x3FUL << CSI_VC0CFGR2_DT2_Pos)          /*!< 0x003F0000 */
8195 #define CSI_VC0CFGR2_DT2                CSI_VC0CFGR2_DT2_Msk                     /*!< Data type 2 class selection for virtual channel x */
8196 #define CSI_VC0CFGR2_DT2FT_Pos          (24U)
8197 #define CSI_VC0CFGR2_DT2FT_Msk          (0x1FUL << CSI_VC0CFGR2_DT2FT_Pos)        /*!< 0x1F000000 */
8198 #define CSI_VC0CFGR2_DT2FT              CSI_VC0CFGR2_DT2FT_Msk                   /*!< Data type 2 format */
8199 
8200 /*****************  Bit definition for CSI_VC0CFGR3 register  *****************/
8201 #define CSI_VC0CFGR3_DT3_Pos            (0U)
8202 #define CSI_VC0CFGR3_DT3_Msk            (0x3FUL << CSI_VC0CFGR3_DT3_Pos)          /*!< 0x0000003F */
8203 #define CSI_VC0CFGR3_DT3                CSI_VC0CFGR3_DT3_Msk                     /*!< Data type 3 class selection for virtual channel x */
8204 #define CSI_VC0CFGR3_DT3FT_Pos          (8U)
8205 #define CSI_VC0CFGR3_DT3FT_Msk          (0x1FUL << CSI_VC0CFGR3_DT3FT_Pos)        /*!< 0x00001F00 */
8206 #define CSI_VC0CFGR3_DT3FT              CSI_VC0CFGR3_DT3FT_Msk                   /*!< Data type 3 format */
8207 #define CSI_VC0CFGR3_DT4_Pos            (16U)
8208 #define CSI_VC0CFGR3_DT4_Msk            (0x3FUL << CSI_VC0CFGR3_DT4_Pos)          /*!< 0x003F0000 */
8209 #define CSI_VC0CFGR3_DT4                CSI_VC0CFGR3_DT4_Msk                     /*!< Data type 4 class selection for virtual channel x */
8210 #define CSI_VC0CFGR3_DT4FT_Pos          (24U)
8211 #define CSI_VC0CFGR3_DT4FT_Msk          (0x1FUL << CSI_VC0CFGR3_DT4FT_Pos)        /*!< 0x1F000000 */
8212 #define CSI_VC0CFGR3_DT4FT              CSI_VC0CFGR3_DT4FT_Msk                   /*!< Data type 4 format */
8213 
8214 /*****************  Bit definition for CSI_VC0CFGR4 register  *****************/
8215 #define CSI_VC0CFGR4_DT5_Pos            (0U)
8216 #define CSI_VC0CFGR4_DT5_Msk            (0x3FUL << CSI_VC0CFGR4_DT5_Pos)          /*!< 0x0000003F */
8217 #define CSI_VC0CFGR4_DT5                CSI_VC0CFGR4_DT5_Msk                     /*!< Data type 5 class selection for virtual channel x */
8218 #define CSI_VC0CFGR4_DT5FT_Pos          (8U)
8219 #define CSI_VC0CFGR4_DT5FT_Msk          (0x1FUL << CSI_VC0CFGR4_DT5FT_Pos)        /*!< 0x00001F00 */
8220 #define CSI_VC0CFGR4_DT5FT              CSI_VC0CFGR4_DT5FT_Msk                   /*!< Data type 5 format */
8221 #define CSI_VC0CFGR4_DT6_Pos            (16U)
8222 #define CSI_VC0CFGR4_DT6_Msk            (0x3FUL << CSI_VC0CFGR4_DT6_Pos)          /*!< 0x003F0000 */
8223 #define CSI_VC0CFGR4_DT6                CSI_VC0CFGR4_DT6_Msk                     /*!< Data type 6 class selection for virtual channel x */
8224 #define CSI_VC0CFGR4_DT6FT_Pos          (24U)
8225 #define CSI_VC0CFGR4_DT6FT_Msk          (0x1FUL << CSI_VC0CFGR4_DT6FT_Pos)        /*!< 0x1F000000 */
8226 #define CSI_VC0CFGR4_DT6FT              CSI_VC0CFGR4_DT6FT_Msk                   /*!< Data type 6 format */
8227 
8228 /*****************  Bit definition for CSI_VC1CFGR1 register  *****************/
8229 #define CSI_VC1CFGR1_ALLDT_Pos          (0U)
8230 #define CSI_VC1CFGR1_ALLDT_Msk          (0x1UL << CSI_VC1CFGR1_ALLDT_Pos)         /*!< 0x00000001 */
8231 #define CSI_VC1CFGR1_ALLDT              CSI_VC1CFGR1_ALLDT_Msk                   /*!< All data types enable for the virtual channel x */
8232 #define CSI_VC1CFGR1_DT0EN_Pos          (1U)
8233 #define CSI_VC1CFGR1_DT0EN_Msk          (0x1UL << CSI_VC1CFGR1_DT0EN_Pos)         /*!< 0x00000002 */
8234 #define CSI_VC1CFGR1_DT0EN              CSI_VC1CFGR1_DT0EN_Msk                   /*!< Data type 0 enable */
8235 #define CSI_VC1CFGR1_DT1EN_Pos          (2U)
8236 #define CSI_VC1CFGR1_DT1EN_Msk          (0x1UL << CSI_VC1CFGR1_DT1EN_Pos)         /*!< 0x00000004 */
8237 #define CSI_VC1CFGR1_DT1EN              CSI_VC1CFGR1_DT1EN_Msk                   /*!< Data type 1 enable */
8238 #define CSI_VC1CFGR1_DT2EN_Pos          (3U)
8239 #define CSI_VC1CFGR1_DT2EN_Msk          (0x1UL << CSI_VC1CFGR1_DT2EN_Pos)         /*!< 0x00000008 */
8240 #define CSI_VC1CFGR1_DT2EN              CSI_VC1CFGR1_DT2EN_Msk                   /*!< Data type 2 enable */
8241 #define CSI_VC1CFGR1_DT3EN_Pos          (4U)
8242 #define CSI_VC1CFGR1_DT3EN_Msk          (0x1UL << CSI_VC1CFGR1_DT3EN_Pos)         /*!< 0x00000010 */
8243 #define CSI_VC1CFGR1_DT3EN              CSI_VC1CFGR1_DT3EN_Msk                   /*!< Data type 3 enable */
8244 #define CSI_VC1CFGR1_DT4EN_Pos          (5U)
8245 #define CSI_VC1CFGR1_DT4EN_Msk          (0x1UL << CSI_VC1CFGR1_DT4EN_Pos)         /*!< 0x00000020 */
8246 #define CSI_VC1CFGR1_DT4EN              CSI_VC1CFGR1_DT4EN_Msk                   /*!< Data type 4 enable */
8247 #define CSI_VC1CFGR1_DT5EN_Pos          (6U)
8248 #define CSI_VC1CFGR1_DT5EN_Msk          (0x1UL << CSI_VC1CFGR1_DT5EN_Pos)         /*!< 0x00000040 */
8249 #define CSI_VC1CFGR1_DT5EN              CSI_VC1CFGR1_DT5EN_Msk                   /*!< Data type 5 enable */
8250 #define CSI_VC1CFGR1_DT6EN_Pos          (7U)
8251 #define CSI_VC1CFGR1_DT6EN_Msk          (0x1UL << CSI_VC1CFGR1_DT6EN_Pos)         /*!< 0x00000080 */
8252 #define CSI_VC1CFGR1_DT6EN              CSI_VC1CFGR1_DT6EN_Msk                   /*!< Data type 6 enable */
8253 #define CSI_VC1CFGR1_CDTFT_Pos          (8U)
8254 #define CSI_VC1CFGR1_CDTFT_Msk          (0x1FUL << CSI_VC1CFGR1_CDTFT_Pos)        /*!< 0x00001F00 */
8255 #define CSI_VC1CFGR1_CDTFT              CSI_VC1CFGR1_CDTFT_Msk                   /*!< Common format for all data types */
8256 #define CSI_VC1CFGR1_DT0_Pos            (16U)
8257 #define CSI_VC1CFGR1_DT0_Msk            (0x3FUL << CSI_VC1CFGR1_DT0_Pos)          /*!< 0x003F0000 */
8258 #define CSI_VC1CFGR1_DT0                CSI_VC1CFGR1_DT0_Msk                     /*!< Data type 0 class selection for virtual channel x */
8259 #define CSI_VC1CFGR1_DT0FT_Pos          (24U)
8260 #define CSI_VC1CFGR1_DT0FT_Msk          (0x1FUL << CSI_VC1CFGR1_DT0FT_Pos)        /*!< 0x1F000000 */
8261 #define CSI_VC1CFGR1_DT0FT              CSI_VC1CFGR1_DT0FT_Msk                   /*!< Data type 0 format */
8262 
8263 /*****************  Bit definition for CSI_VC1CFGR2 register  *****************/
8264 #define CSI_VC1CFGR2_DT1_Pos            (0U)
8265 #define CSI_VC1CFGR2_DT1_Msk            (0x3FUL << CSI_VC1CFGR2_DT1_Pos)          /*!< 0x0000003F */
8266 #define CSI_VC1CFGR2_DT1                CSI_VC1CFGR2_DT1_Msk                     /*!< Data type 1 class selection for virtual channel x */
8267 #define CSI_VC1CFGR2_DT1FT_Pos          (8U)
8268 #define CSI_VC1CFGR2_DT1FT_Msk          (0x1FUL << CSI_VC1CFGR2_DT1FT_Pos)        /*!< 0x00001F00 */
8269 #define CSI_VC1CFGR2_DT1FT              CSI_VC1CFGR2_DT1FT_Msk                   /*!< Data type 1 format */
8270 #define CSI_VC1CFGR2_DT2_Pos            (16U)
8271 #define CSI_VC1CFGR2_DT2_Msk            (0x3FUL << CSI_VC1CFGR2_DT2_Pos)          /*!< 0x003F0000 */
8272 #define CSI_VC1CFGR2_DT2                CSI_VC1CFGR2_DT2_Msk                     /*!< Data type 2 class selection for virtual channel x */
8273 #define CSI_VC1CFGR2_DT2FT_Pos          (24U)
8274 #define CSI_VC1CFGR2_DT2FT_Msk          (0x1FUL << CSI_VC1CFGR2_DT2FT_Pos)        /*!< 0x1F000000 */
8275 #define CSI_VC1CFGR2_DT2FT              CSI_VC1CFGR2_DT2FT_Msk                   /*!< Data type 2 format */
8276 
8277 /*****************  Bit definition for CSI_VC1CFGR3 register  *****************/
8278 #define CSI_VC1CFGR3_DT3_Pos            (0U)
8279 #define CSI_VC1CFGR3_DT3_Msk            (0x3FUL << CSI_VC1CFGR3_DT3_Pos)          /*!< 0x0000003F */
8280 #define CSI_VC1CFGR3_DT3                CSI_VC1CFGR3_DT3_Msk                     /*!< Data type 3 class selection for virtual channel x */
8281 #define CSI_VC1CFGR3_DT3FT_Pos          (8U)
8282 #define CSI_VC1CFGR3_DT3FT_Msk          (0x1FUL << CSI_VC1CFGR3_DT3FT_Pos)        /*!< 0x00001F00 */
8283 #define CSI_VC1CFGR3_DT3FT              CSI_VC1CFGR3_DT3FT_Msk                   /*!< Data type 3 format */
8284 #define CSI_VC1CFGR3_DT4_Pos            (16U)
8285 #define CSI_VC1CFGR3_DT4_Msk            (0x3FUL << CSI_VC1CFGR3_DT4_Pos)          /*!< 0x003F0000 */
8286 #define CSI_VC1CFGR3_DT4                CSI_VC1CFGR3_DT4_Msk                     /*!< Data type 4 class selection for virtual channel x */
8287 #define CSI_VC1CFGR3_DT4FT_Pos          (24U)
8288 #define CSI_VC1CFGR3_DT4FT_Msk          (0x1FUL << CSI_VC1CFGR3_DT4FT_Pos)        /*!< 0x1F000000 */
8289 #define CSI_VC1CFGR3_DT4FT              CSI_VC1CFGR3_DT4FT_Msk                   /*!< Data type 4 format */
8290 
8291 /*****************  Bit definition for CSI_VC1CFGR4 register  *****************/
8292 #define CSI_VC1CFGR4_DT5_Pos            (0U)
8293 #define CSI_VC1CFGR4_DT5_Msk            (0x3FUL << CSI_VC1CFGR4_DT5_Pos)          /*!< 0x0000003F */
8294 #define CSI_VC1CFGR4_DT5                CSI_VC1CFGR4_DT5_Msk                     /*!< Data type 5 class selection for virtual channel x */
8295 #define CSI_VC1CFGR4_DT5FT_Pos          (8U)
8296 #define CSI_VC1CFGR4_DT5FT_Msk          (0x1FUL << CSI_VC1CFGR4_DT5FT_Pos)        /*!< 0x00001F00 */
8297 #define CSI_VC1CFGR4_DT5FT              CSI_VC1CFGR4_DT5FT_Msk                   /*!< Data type 5 format */
8298 #define CSI_VC1CFGR4_DT6_Pos            (16U)
8299 #define CSI_VC1CFGR4_DT6_Msk            (0x3FUL << CSI_VC1CFGR4_DT6_Pos)          /*!< 0x003F0000 */
8300 #define CSI_VC1CFGR4_DT6                CSI_VC1CFGR4_DT6_Msk                     /*!< Data type 6 class selection for virtual channel x */
8301 #define CSI_VC1CFGR4_DT6FT_Pos          (24U)
8302 #define CSI_VC1CFGR4_DT6FT_Msk          (0x1FUL << CSI_VC1CFGR4_DT6FT_Pos)        /*!< 0x1F000000 */
8303 #define CSI_VC1CFGR4_DT6FT              CSI_VC1CFGR4_DT6FT_Msk                   /*!< Data type 6 format */
8304 
8305 /*****************  Bit definition for CSI_VC2CFGR1 register  *****************/
8306 #define CSI_VC2CFGR1_ALLDT_Pos          (0U)
8307 #define CSI_VC2CFGR1_ALLDT_Msk          (0x1UL << CSI_VC2CFGR1_ALLDT_Pos)         /*!< 0x00000001 */
8308 #define CSI_VC2CFGR1_ALLDT              CSI_VC2CFGR1_ALLDT_Msk                   /*!< All data types enable for the virtual channel x */
8309 #define CSI_VC2CFGR1_DT0EN_Pos          (1U)
8310 #define CSI_VC2CFGR1_DT0EN_Msk          (0x1UL << CSI_VC2CFGR1_DT0EN_Pos)         /*!< 0x00000002 */
8311 #define CSI_VC2CFGR1_DT0EN              CSI_VC2CFGR1_DT0EN_Msk                   /*!< Data type 0 enable */
8312 #define CSI_VC2CFGR1_DT1EN_Pos          (2U)
8313 #define CSI_VC2CFGR1_DT1EN_Msk          (0x1UL << CSI_VC2CFGR1_DT1EN_Pos)         /*!< 0x00000004 */
8314 #define CSI_VC2CFGR1_DT1EN              CSI_VC2CFGR1_DT1EN_Msk                   /*!< Data type 1 enable */
8315 #define CSI_VC2CFGR1_DT2EN_Pos          (3U)
8316 #define CSI_VC2CFGR1_DT2EN_Msk          (0x1UL << CSI_VC2CFGR1_DT2EN_Pos)         /*!< 0x00000008 */
8317 #define CSI_VC2CFGR1_DT2EN              CSI_VC2CFGR1_DT2EN_Msk                   /*!< Data type 2 enable */
8318 #define CSI_VC2CFGR1_DT3EN_Pos          (4U)
8319 #define CSI_VC2CFGR1_DT3EN_Msk          (0x1UL << CSI_VC2CFGR1_DT3EN_Pos)         /*!< 0x00000010 */
8320 #define CSI_VC2CFGR1_DT3EN              CSI_VC2CFGR1_DT3EN_Msk                   /*!< Data type 3 enable */
8321 #define CSI_VC2CFGR1_DT4EN_Pos          (5U)
8322 #define CSI_VC2CFGR1_DT4EN_Msk          (0x1UL << CSI_VC2CFGR1_DT4EN_Pos)         /*!< 0x00000020 */
8323 #define CSI_VC2CFGR1_DT4EN              CSI_VC2CFGR1_DT4EN_Msk                   /*!< Data type 4 enable */
8324 #define CSI_VC2CFGR1_DT5EN_Pos          (6U)
8325 #define CSI_VC2CFGR1_DT5EN_Msk          (0x1UL << CSI_VC2CFGR1_DT5EN_Pos)         /*!< 0x00000040 */
8326 #define CSI_VC2CFGR1_DT5EN              CSI_VC2CFGR1_DT5EN_Msk                   /*!< Data type 5 enable */
8327 #define CSI_VC2CFGR1_DT6EN_Pos          (7U)
8328 #define CSI_VC2CFGR1_DT6EN_Msk          (0x1UL << CSI_VC2CFGR1_DT6EN_Pos)         /*!< 0x00000080 */
8329 #define CSI_VC2CFGR1_DT6EN              CSI_VC2CFGR1_DT6EN_Msk                   /*!< Data type 6 enable */
8330 #define CSI_VC2CFGR1_CDTFT_Pos          (8U)
8331 #define CSI_VC2CFGR1_CDTFT_Msk          (0x1FUL << CSI_VC2CFGR1_CDTFT_Pos)        /*!< 0x00001F00 */
8332 #define CSI_VC2CFGR1_CDTFT              CSI_VC2CFGR1_CDTFT_Msk                   /*!< Common format for all data types */
8333 #define CSI_VC2CFGR1_DT0_Pos            (16U)
8334 #define CSI_VC2CFGR1_DT0_Msk            (0x3FUL << CSI_VC2CFGR1_DT0_Pos)          /*!< 0x003F0000 */
8335 #define CSI_VC2CFGR1_DT0                CSI_VC2CFGR1_DT0_Msk                     /*!< Data type 0 class selection for virtual channel x */
8336 #define CSI_VC2CFGR1_DT0FT_Pos          (24U)
8337 #define CSI_VC2CFGR1_DT0FT_Msk          (0x1FUL << CSI_VC2CFGR1_DT0FT_Pos)        /*!< 0x1F000000 */
8338 #define CSI_VC2CFGR1_DT0FT              CSI_VC2CFGR1_DT0FT_Msk                   /*!< Data type 0 format */
8339 
8340 /*****************  Bit definition for CSI_VC2CFGR2 register  *****************/
8341 #define CSI_VC2CFGR2_DT1_Pos            (0U)
8342 #define CSI_VC2CFGR2_DT1_Msk            (0x3FUL << CSI_VC2CFGR2_DT1_Pos)          /*!< 0x0000003F */
8343 #define CSI_VC2CFGR2_DT1                CSI_VC2CFGR2_DT1_Msk                     /*!< Data type 1 class selection for virtual channel x */
8344 #define CSI_VC2CFGR2_DT1FT_Pos          (8U)
8345 #define CSI_VC2CFGR2_DT1FT_Msk          (0x1FUL << CSI_VC2CFGR2_DT1FT_Pos)        /*!< 0x00001F00 */
8346 #define CSI_VC2CFGR2_DT1FT              CSI_VC2CFGR2_DT1FT_Msk                   /*!< Data type 1 format */
8347 #define CSI_VC2CFGR2_DT2_Pos            (16U)
8348 #define CSI_VC2CFGR2_DT2_Msk            (0x3FUL << CSI_VC2CFGR2_DT2_Pos)          /*!< 0x003F0000 */
8349 #define CSI_VC2CFGR2_DT2                CSI_VC2CFGR2_DT2_Msk                     /*!< Data type 2 class selection for virtual channel x */
8350 #define CSI_VC2CFGR2_DT2FT_Pos          (24U)
8351 #define CSI_VC2CFGR2_DT2FT_Msk          (0x1FUL << CSI_VC2CFGR2_DT2FT_Pos)        /*!< 0x1F000000 */
8352 #define CSI_VC2CFGR2_DT2FT              CSI_VC2CFGR2_DT2FT_Msk                   /*!< Data type 2 format */
8353 
8354 /*****************  Bit definition for CSI_VC2CFGR3 register  *****************/
8355 #define CSI_VC2CFGR3_DT3_Pos            (0U)
8356 #define CSI_VC2CFGR3_DT3_Msk            (0x3FUL << CSI_VC2CFGR3_DT3_Pos)          /*!< 0x0000003F */
8357 #define CSI_VC2CFGR3_DT3                CSI_VC2CFGR3_DT3_Msk                     /*!< Data type 3 class selection for virtual channel x */
8358 #define CSI_VC2CFGR3_DT3FT_Pos          (8U)
8359 #define CSI_VC2CFGR3_DT3FT_Msk          (0x1FUL << CSI_VC2CFGR3_DT3FT_Pos)        /*!< 0x00001F00 */
8360 #define CSI_VC2CFGR3_DT3FT              CSI_VC2CFGR3_DT3FT_Msk                   /*!< Data type 3 format */
8361 #define CSI_VC2CFGR3_DT4_Pos            (16U)
8362 #define CSI_VC2CFGR3_DT4_Msk            (0x3FUL << CSI_VC2CFGR3_DT4_Pos)          /*!< 0x003F0000 */
8363 #define CSI_VC2CFGR3_DT4                CSI_VC2CFGR3_DT4_Msk                     /*!< Data type 4 class selection for virtual channel x */
8364 #define CSI_VC2CFGR3_DT4FT_Pos          (24U)
8365 #define CSI_VC2CFGR3_DT4FT_Msk          (0x1FUL << CSI_VC2CFGR3_DT4FT_Pos)        /*!< 0x1F000000 */
8366 #define CSI_VC2CFGR3_DT4FT              CSI_VC2CFGR3_DT4FT_Msk                   /*!< Data type 4 format */
8367 
8368 /*****************  Bit definition for CSI_VC2CFGR4 register  *****************/
8369 #define CSI_VC2CFGR4_DT5_Pos            (0U)
8370 #define CSI_VC2CFGR4_DT5_Msk            (0x3FUL << CSI_VC2CFGR4_DT5_Pos)          /*!< 0x0000003F */
8371 #define CSI_VC2CFGR4_DT5                CSI_VC2CFGR4_DT5_Msk                     /*!< Data type 5 class selection for virtual channel x */
8372 #define CSI_VC2CFGR4_DT5FT_Pos          (8U)
8373 #define CSI_VC2CFGR4_DT5FT_Msk          (0x1FUL << CSI_VC2CFGR4_DT5FT_Pos)        /*!< 0x00001F00 */
8374 #define CSI_VC2CFGR4_DT5FT              CSI_VC2CFGR4_DT5FT_Msk                   /*!< Data type 5 format */
8375 #define CSI_VC2CFGR4_DT6_Pos            (16U)
8376 #define CSI_VC2CFGR4_DT6_Msk            (0x3FUL << CSI_VC2CFGR4_DT6_Pos)          /*!< 0x003F0000 */
8377 #define CSI_VC2CFGR4_DT6                CSI_VC2CFGR4_DT6_Msk                     /*!< Data type 6 class selection for virtual channel x */
8378 #define CSI_VC2CFGR4_DT6FT_Pos          (24U)
8379 #define CSI_VC2CFGR4_DT6FT_Msk          (0x1FUL << CSI_VC2CFGR4_DT6FT_Pos)        /*!< 0x1F000000 */
8380 #define CSI_VC2CFGR4_DT6FT              CSI_VC2CFGR4_DT6FT_Msk                   /*!< Data type 6 format */
8381 
8382 /*****************  Bit definition for CSI_VC3CFGR1 register  *****************/
8383 #define CSI_VC3CFGR1_ALLDT_Pos          (0U)
8384 #define CSI_VC3CFGR1_ALLDT_Msk          (0x1UL << CSI_VC3CFGR1_ALLDT_Pos)         /*!< 0x00000001 */
8385 #define CSI_VC3CFGR1_ALLDT              CSI_VC3CFGR1_ALLDT_Msk                   /*!< All data types enable for the virtual channel x */
8386 #define CSI_VC3CFGR1_DT0EN_Pos          (1U)
8387 #define CSI_VC3CFGR1_DT0EN_Msk          (0x1UL << CSI_VC3CFGR1_DT0EN_Pos)         /*!< 0x00000002 */
8388 #define CSI_VC3CFGR1_DT0EN              CSI_VC3CFGR1_DT0EN_Msk                   /*!< Data type 0 enable */
8389 #define CSI_VC3CFGR1_DT1EN_Pos          (2U)
8390 #define CSI_VC3CFGR1_DT1EN_Msk          (0x1UL << CSI_VC3CFGR1_DT1EN_Pos)         /*!< 0x00000004 */
8391 #define CSI_VC3CFGR1_DT1EN              CSI_VC3CFGR1_DT1EN_Msk                   /*!< Data type 1 enable */
8392 #define CSI_VC3CFGR1_DT2EN_Pos          (3U)
8393 #define CSI_VC3CFGR1_DT2EN_Msk          (0x1UL << CSI_VC3CFGR1_DT2EN_Pos)         /*!< 0x00000008 */
8394 #define CSI_VC3CFGR1_DT2EN              CSI_VC3CFGR1_DT2EN_Msk                   /*!< Data type 2 enable */
8395 #define CSI_VC3CFGR1_DT3EN_Pos          (4U)
8396 #define CSI_VC3CFGR1_DT3EN_Msk          (0x1UL << CSI_VC3CFGR1_DT3EN_Pos)         /*!< 0x00000010 */
8397 #define CSI_VC3CFGR1_DT3EN              CSI_VC3CFGR1_DT3EN_Msk                   /*!< Data type 3 enable */
8398 #define CSI_VC3CFGR1_DT4EN_Pos          (5U)
8399 #define CSI_VC3CFGR1_DT4EN_Msk          (0x1UL << CSI_VC3CFGR1_DT4EN_Pos)         /*!< 0x00000020 */
8400 #define CSI_VC3CFGR1_DT4EN              CSI_VC3CFGR1_DT4EN_Msk                   /*!< Data type 4 enable */
8401 #define CSI_VC3CFGR1_DT5EN_Pos          (6U)
8402 #define CSI_VC3CFGR1_DT5EN_Msk          (0x1UL << CSI_VC3CFGR1_DT5EN_Pos)         /*!< 0x00000040 */
8403 #define CSI_VC3CFGR1_DT5EN              CSI_VC3CFGR1_DT5EN_Msk                   /*!< Data type 5 enable */
8404 #define CSI_VC3CFGR1_DT6EN_Pos          (7U)
8405 #define CSI_VC3CFGR1_DT6EN_Msk          (0x1UL << CSI_VC3CFGR1_DT6EN_Pos)         /*!< 0x00000080 */
8406 #define CSI_VC3CFGR1_DT6EN              CSI_VC3CFGR1_DT6EN_Msk                   /*!< Data type 6 enable */
8407 #define CSI_VC3CFGR1_CDTFT_Pos          (8U)
8408 #define CSI_VC3CFGR1_CDTFT_Msk          (0x1FUL << CSI_VC3CFGR1_CDTFT_Pos)        /*!< 0x00001F00 */
8409 #define CSI_VC3CFGR1_CDTFT              CSI_VC3CFGR1_CDTFT_Msk                   /*!< Common format for all data types */
8410 #define CSI_VC3CFGR1_DT0_Pos            (16U)
8411 #define CSI_VC3CFGR1_DT0_Msk            (0x3FUL << CSI_VC3CFGR1_DT0_Pos)          /*!< 0x003F0000 */
8412 #define CSI_VC3CFGR1_DT0                CSI_VC3CFGR1_DT0_Msk                     /*!< Data type 0 class selection for virtual channel x */
8413 #define CSI_VC3CFGR1_DT0FT_Pos          (24U)
8414 #define CSI_VC3CFGR1_DT0FT_Msk          (0x1FUL << CSI_VC3CFGR1_DT0FT_Pos)        /*!< 0x1F000000 */
8415 #define CSI_VC3CFGR1_DT0FT              CSI_VC3CFGR1_DT0FT_Msk                   /*!< Data type 0 format */
8416 
8417 /*****************  Bit definition for CSI_VC3CFGR2 register  *****************/
8418 #define CSI_VC3CFGR2_DT1_Pos            (0U)
8419 #define CSI_VC3CFGR2_DT1_Msk            (0x3FUL << CSI_VC3CFGR2_DT1_Pos)          /*!< 0x0000003F */
8420 #define CSI_VC3CFGR2_DT1                CSI_VC3CFGR2_DT1_Msk                     /*!< Data type 1 class selection for virtual channel x */
8421 #define CSI_VC3CFGR2_DT1FT_Pos          (8U)
8422 #define CSI_VC3CFGR2_DT1FT_Msk          (0x1FUL << CSI_VC3CFGR2_DT1FT_Pos)        /*!< 0x00001F00 */
8423 #define CSI_VC3CFGR2_DT1FT              CSI_VC3CFGR2_DT1FT_Msk                   /*!< Data type 1 format */
8424 #define CSI_VC3CFGR2_DT2_Pos            (16U)
8425 #define CSI_VC3CFGR2_DT2_Msk            (0x3FUL << CSI_VC3CFGR2_DT2_Pos)          /*!< 0x003F0000 */
8426 #define CSI_VC3CFGR2_DT2                CSI_VC3CFGR2_DT2_Msk                     /*!< Data type 2 class selection for virtual channel x */
8427 #define CSI_VC3CFGR2_DT2FT_Pos          (24U)
8428 #define CSI_VC3CFGR2_DT2FT_Msk          (0x1FUL << CSI_VC3CFGR2_DT2FT_Pos)        /*!< 0x1F000000 */
8429 #define CSI_VC3CFGR2_DT2FT              CSI_VC3CFGR2_DT2FT_Msk                   /*!< Data type 2 format */
8430 
8431 /*****************  Bit definition for CSI_VC3CFGR3 register  *****************/
8432 #define CSI_VC3CFGR3_DT3_Pos            (0U)
8433 #define CSI_VC3CFGR3_DT3_Msk            (0x3FUL << CSI_VC3CFGR3_DT3_Pos)          /*!< 0x0000003F */
8434 #define CSI_VC3CFGR3_DT3                CSI_VC3CFGR3_DT3_Msk                     /*!< Data type 3 class selection for virtual channel x */
8435 #define CSI_VC3CFGR3_DT3FT_Pos          (8U)
8436 #define CSI_VC3CFGR3_DT3FT_Msk          (0x1FUL << CSI_VC3CFGR3_DT3FT_Pos)        /*!< 0x00001F00 */
8437 #define CSI_VC3CFGR3_DT3FT              CSI_VC3CFGR3_DT3FT_Msk                   /*!< Data type 3 format */
8438 #define CSI_VC3CFGR3_DT4_Pos            (16U)
8439 #define CSI_VC3CFGR3_DT4_Msk            (0x3FUL << CSI_VC3CFGR3_DT4_Pos)          /*!< 0x003F0000 */
8440 #define CSI_VC3CFGR3_DT4                CSI_VC3CFGR3_DT4_Msk                     /*!< Data type 4 class selection for virtual channel x */
8441 #define CSI_VC3CFGR3_DT4FT_Pos          (24U)
8442 #define CSI_VC3CFGR3_DT4FT_Msk          (0x1FUL << CSI_VC3CFGR3_DT4FT_Pos)        /*!< 0x1F000000 */
8443 #define CSI_VC3CFGR3_DT4FT              CSI_VC3CFGR3_DT4FT_Msk                   /*!< Data type 4 format */
8444 
8445 /*****************  Bit definition for CSI_VC3CFGR4 register  *****************/
8446 #define CSI_VC3CFGR4_DT5_Pos            (0U)
8447 #define CSI_VC3CFGR4_DT5_Msk            (0x3FUL << CSI_VC3CFGR4_DT5_Pos)          /*!< 0x0000003F */
8448 #define CSI_VC3CFGR4_DT5                CSI_VC3CFGR4_DT5_Msk                     /*!< Data type 5 class selection for virtual channel x */
8449 #define CSI_VC3CFGR4_DT5FT_Pos          (8U)
8450 #define CSI_VC3CFGR4_DT5FT_Msk          (0x1FUL << CSI_VC3CFGR4_DT5FT_Pos)        /*!< 0x00001F00 */
8451 #define CSI_VC3CFGR4_DT5FT              CSI_VC3CFGR4_DT5FT_Msk                   /*!< Data type 5 format */
8452 #define CSI_VC3CFGR4_DT6_Pos            (16U)
8453 #define CSI_VC3CFGR4_DT6_Msk            (0x3FUL << CSI_VC3CFGR4_DT6_Pos)          /*!< 0x003F0000 */
8454 #define CSI_VC3CFGR4_DT6                CSI_VC3CFGR4_DT6_Msk                     /*!< Data type 6 class selection for virtual channel x */
8455 #define CSI_VC3CFGR4_DT6FT_Pos          (24U)
8456 #define CSI_VC3CFGR4_DT6FT_Msk          (0x1FUL << CSI_VC3CFGR4_DT6FT_Pos)        /*!< 0x1F000000 */
8457 #define CSI_VC3CFGR4_DT6FT              CSI_VC3CFGR4_DT6FT_Msk                   /*!< Data type 6 format */
8458 
8459 /*****************  Bit definition for CSI_LB0CFGR register  ******************/
8460 #define CSI_LB0CFGR_BYTECNT_Pos         (0U)
8461 #define CSI_LB0CFGR_BYTECNT_Msk         (0xFFFFUL << CSI_LB0CFGR_BYTECNT_Pos)     /*!< 0x0000FFFF */
8462 #define CSI_LB0CFGR_BYTECNT             CSI_LB0CFGR_BYTECNT_Msk                  /*!< Byte counter */
8463 #define CSI_LB0CFGR_LINECNT_Pos         (16U)
8464 #define CSI_LB0CFGR_LINECNT_Msk         (0xFFFFUL << CSI_LB0CFGR_LINECNT_Pos)     /*!< 0xFFFF0000 */
8465 #define CSI_LB0CFGR_LINECNT             CSI_LB0CFGR_LINECNT_Msk                  /*!< Line counter */
8466 
8467 /*****************  Bit definition for CSI_LB1CFGR register  ******************/
8468 #define CSI_LB1CFGR_BYTECNT_Pos         (0U)
8469 #define CSI_LB1CFGR_BYTECNT_Msk         (0xFFFFUL << CSI_LB1CFGR_BYTECNT_Pos)     /*!< 0x0000FFFF */
8470 #define CSI_LB1CFGR_BYTECNT             CSI_LB1CFGR_BYTECNT_Msk                  /*!< Byte counter */
8471 #define CSI_LB1CFGR_LINECNT_Pos         (16U)
8472 #define CSI_LB1CFGR_LINECNT_Msk         (0xFFFFUL << CSI_LB1CFGR_LINECNT_Pos)     /*!< 0xFFFF0000 */
8473 #define CSI_LB1CFGR_LINECNT             CSI_LB1CFGR_LINECNT_Msk                  /*!< Line counter */
8474 
8475 /*****************  Bit definition for CSI_LB2CFGR register  ******************/
8476 #define CSI_LB2CFGR_BYTECNT_Pos         (0U)
8477 #define CSI_LB2CFGR_BYTECNT_Msk         (0xFFFFUL << CSI_LB2CFGR_BYTECNT_Pos)     /*!< 0x0000FFFF */
8478 #define CSI_LB2CFGR_BYTECNT             CSI_LB2CFGR_BYTECNT_Msk                  /*!< Byte counter */
8479 #define CSI_LB2CFGR_LINECNT_Pos         (16U)
8480 #define CSI_LB2CFGR_LINECNT_Msk         (0xFFFFUL << CSI_LB2CFGR_LINECNT_Pos)     /*!< 0xFFFF0000 */
8481 #define CSI_LB2CFGR_LINECNT             CSI_LB2CFGR_LINECNT_Msk                  /*!< Line counter */
8482 
8483 /*****************  Bit definition for CSI_LB3CFGR register  ******************/
8484 #define CSI_LB3CFGR_BYTECNT_Pos         (0U)
8485 #define CSI_LB3CFGR_BYTECNT_Msk         (0xFFFFUL << CSI_LB3CFGR_BYTECNT_Pos)     /*!< 0x0000FFFF */
8486 #define CSI_LB3CFGR_BYTECNT             CSI_LB3CFGR_BYTECNT_Msk                  /*!< Byte counter */
8487 #define CSI_LB3CFGR_LINECNT_Pos         (16U)
8488 #define CSI_LB3CFGR_LINECNT_Msk         (0xFFFFUL << CSI_LB3CFGR_LINECNT_Pos)     /*!< 0xFFFF0000 */
8489 #define CSI_LB3CFGR_LINECNT             CSI_LB3CFGR_LINECNT_Msk                  /*!< Line counter */
8490 
8491 /*****************  Bit definition for CSI_TIM0CFGR register  *****************/
8492 #define CSI_TIM0CFGR_COUNT_Pos          (0U)
8493 #define CSI_TIM0CFGR_COUNT_Msk          (0x1FFFFFFUL << CSI_TIM0CFGR_COUNT_Pos)   /*!< 0x01FFFFFF */
8494 #define CSI_TIM0CFGR_COUNT              CSI_TIM0CFGR_COUNT_Msk                   /*!< Clock cycle counter */
8495 
8496 /*****************  Bit definition for CSI_TIM1CFGR register  *****************/
8497 #define CSI_TIM1CFGR_COUNT_Pos          (0U)
8498 #define CSI_TIM1CFGR_COUNT_Msk          (0x1FFFFFFUL << CSI_TIM1CFGR_COUNT_Pos)   /*!< 0x01FFFFFF */
8499 #define CSI_TIM1CFGR_COUNT              CSI_TIM1CFGR_COUNT_Msk                   /*!< Clock cycle counter */
8500 
8501 /*****************  Bit definition for CSI_TIM2CFGR register  *****************/
8502 #define CSI_TIM2CFGR_COUNT_Pos          (0U)
8503 #define CSI_TIM2CFGR_COUNT_Msk          (0x1FFFFFFUL << CSI_TIM2CFGR_COUNT_Pos)   /*!< 0x01FFFFFF */
8504 #define CSI_TIM2CFGR_COUNT              CSI_TIM2CFGR_COUNT_Msk                   /*!< Clock cycle counter */
8505 
8506 /*****************  Bit definition for CSI_TIM3CFGR register  *****************/
8507 #define CSI_TIM3CFGR_COUNT_Pos          (0U)
8508 #define CSI_TIM3CFGR_COUNT_Msk          (0x1FFFFFFUL << CSI_TIM3CFGR_COUNT_Pos)   /*!< 0x01FFFFFF */
8509 #define CSI_TIM3CFGR_COUNT              CSI_TIM3CFGR_COUNT_Msk                   /*!< Clock cycle counter */
8510 
8511 /******************  Bit definition for CSI_LMCFGR register  ******************/
8512 #define CSI_LMCFGR_LANENB_Pos           (8U)
8513 #define CSI_LMCFGR_LANENB_Msk           (0x7UL << CSI_LMCFGR_LANENB_Pos)          /*!< 0x00000700 */
8514 #define CSI_LMCFGR_LANENB               CSI_LMCFGR_LANENB_Msk                    /*!< Number of lanes */
8515 #define CSI_LMCFGR_DL0MAP_Pos           (16U)
8516 #define CSI_LMCFGR_DL0MAP_Msk           (0x7UL << CSI_LMCFGR_DL0MAP_Pos)          /*!< 0x00070000 */
8517 #define CSI_LMCFGR_DL0MAP               CSI_LMCFGR_DL0MAP_Msk                    /*!< Physical mapping of logical data lane 0 */
8518 #define CSI_LMCFGR_DL1MAP_Pos           (20U)
8519 #define CSI_LMCFGR_DL1MAP_Msk           (0x7UL << CSI_LMCFGR_DL1MAP_Pos)          /*!< 0x00700000 */
8520 #define CSI_LMCFGR_DL1MAP               CSI_LMCFGR_DL1MAP_Msk                    /*!< Physical mapping of logical data lane 1 */
8521 
8522 /******************  Bit definition for CSI_PRGITR register  ******************/
8523 #define CSI_PRGITR_LB0VC_Pos            (0U)
8524 #define CSI_PRGITR_LB0VC_Msk            (0x3UL << CSI_PRGITR_LB0VC_Pos)           /*!< 0x00000003 */
8525 #define CSI_PRGITR_LB0VC                CSI_PRGITR_LB0VC_Msk                     /*!< Line/Byte counter 0 linked to a virtual channel */
8526 #define CSI_PRGITR_LB0EN_Pos            (3U)
8527 #define CSI_PRGITR_LB0EN_Msk            (0x1UL << CSI_PRGITR_LB0EN_Pos)           /*!< 0x00000008 */
8528 #define CSI_PRGITR_LB0EN                CSI_PRGITR_LB0EN_Msk                     /*!< Line/Byte 0counter enable */
8529 #define CSI_PRGITR_LB1VC_Pos            (4U)
8530 #define CSI_PRGITR_LB1VC_Msk            (0x3UL << CSI_PRGITR_LB1VC_Pos)           /*!< 0x00000030 */
8531 #define CSI_PRGITR_LB1VC                CSI_PRGITR_LB1VC_Msk                     /*!< Line/Byte counter 1 linked to a virtual channel */
8532 #define CSI_PRGITR_LB1EN_Pos            (7U)
8533 #define CSI_PRGITR_LB1EN_Msk            (0x1UL << CSI_PRGITR_LB1EN_Pos)           /*!< 0x00000080 */
8534 #define CSI_PRGITR_LB1EN                CSI_PRGITR_LB1EN_Msk                     /*!< Line/Byte 1 counter enable */
8535 #define CSI_PRGITR_LB2VC_Pos            (8U)
8536 #define CSI_PRGITR_LB2VC_Msk            (0x3UL << CSI_PRGITR_LB2VC_Pos)           /*!< 0x00000300 */
8537 #define CSI_PRGITR_LB2VC                CSI_PRGITR_LB2VC_Msk                     /*!< Line/Byte counter 2 linked to a virtual channel */
8538 #define CSI_PRGITR_LB2EN_Pos            (11U)
8539 #define CSI_PRGITR_LB2EN_Msk            (0x1UL << CSI_PRGITR_LB2EN_Pos)           /*!< 0x00000800 */
8540 #define CSI_PRGITR_LB2EN                CSI_PRGITR_LB2EN_Msk                     /*!< Line/Byte 2 counter enable */
8541 #define CSI_PRGITR_LB3VC_Pos            (12U)
8542 #define CSI_PRGITR_LB3VC_Msk            (0x3UL << CSI_PRGITR_LB3VC_Pos)           /*!< 0x00003000 */
8543 #define CSI_PRGITR_LB3VC                CSI_PRGITR_LB3VC_Msk                     /*!< Line/Byte counter 3 linked to a virtual channel */
8544 #define CSI_PRGITR_LB3EN_Pos            (15U)
8545 #define CSI_PRGITR_LB3EN_Msk            (0x1UL << CSI_PRGITR_LB3EN_Pos)           /*!< 0x00008000 */
8546 #define CSI_PRGITR_LB3EN                CSI_PRGITR_LB3EN_Msk                     /*!< Line/Byte 3 counter enable */
8547 #define CSI_PRGITR_TIM0VC_Pos           (16U)
8548 #define CSI_PRGITR_TIM0VC_Msk           (0x3UL << CSI_PRGITR_TIM0VC_Pos)          /*!< 0x00030000 */
8549 #define CSI_PRGITR_TIM0VC               CSI_PRGITR_TIM0VC_Msk                    /*!< TIM0 base time linked to a virtual channel */
8550 #define CSI_PRGITR_TIM0EOF_Pos          (18U)
8551 #define CSI_PRGITR_TIM0EOF_Msk          (0x1UL << CSI_PRGITR_TIM0EOF_Pos)         /*!< 0x00040000 */
8552 #define CSI_PRGITR_TIM0EOF              CSI_PRGITR_TIM0EOF_Msk                   /*!< TIM0 base time starting from the end of frame */
8553 #define CSI_PRGITR_TIM0EN_Pos           (19U)
8554 #define CSI_PRGITR_TIM0EN_Msk           (0x1UL << CSI_PRGITR_TIM0EN_Pos)          /*!< 0x00080000 */
8555 #define CSI_PRGITR_TIM0EN               CSI_PRGITR_TIM0EN_Msk                    /*!< TIM0 base time enable */
8556 #define CSI_PRGITR_TIM1VC_Pos           (20U)
8557 #define CSI_PRGITR_TIM1VC_Msk           (0x3UL << CSI_PRGITR_TIM1VC_Pos)          /*!< 0x00300000 */
8558 #define CSI_PRGITR_TIM1VC               CSI_PRGITR_TIM1VC_Msk                    /*!< TIM1 base time linked to a virtual channel */
8559 #define CSI_PRGITR_TIM1EOF_Pos          (22U)
8560 #define CSI_PRGITR_TIM1EOF_Msk          (0x1UL << CSI_PRGITR_TIM1EOF_Pos)         /*!< 0x00400000 */
8561 #define CSI_PRGITR_TIM1EOF              CSI_PRGITR_TIM1EOF_Msk                   /*!< TIM1 base time starting from the end of frame */
8562 #define CSI_PRGITR_TIM1EN_Pos           (23U)
8563 #define CSI_PRGITR_TIM1EN_Msk           (0x1UL << CSI_PRGITR_TIM1EN_Pos)          /*!< 0x00800000 */
8564 #define CSI_PRGITR_TIM1EN               CSI_PRGITR_TIM1EN_Msk                    /*!< TIM1 base time enable */
8565 #define CSI_PRGITR_TIM2VC_Pos           (24U)
8566 #define CSI_PRGITR_TIM2VC_Msk           (0x3UL << CSI_PRGITR_TIM2VC_Pos)          /*!< 0x03000000 */
8567 #define CSI_PRGITR_TIM2VC               CSI_PRGITR_TIM2VC_Msk                    /*!< TIM2 base time linked to a virtual channel */
8568 #define CSI_PRGITR_TIM2EOF_Pos          (26U)
8569 #define CSI_PRGITR_TIM2EOF_Msk          (0x1UL << CSI_PRGITR_TIM2EOF_Pos)         /*!< 0x04000000 */
8570 #define CSI_PRGITR_TIM2EOF              CSI_PRGITR_TIM2EOF_Msk                   /*!< TIM2 base time starting from the end of frame */
8571 #define CSI_PRGITR_TIM2EN_Pos           (27U)
8572 #define CSI_PRGITR_TIM2EN_Msk           (0x1UL << CSI_PRGITR_TIM2EN_Pos)          /*!< 0x08000000 */
8573 #define CSI_PRGITR_TIM2EN               CSI_PRGITR_TIM2EN_Msk                    /*!< TIM2 base time enable */
8574 #define CSI_PRGITR_TIM3VC_Pos           (28U)
8575 #define CSI_PRGITR_TIM3VC_Msk           (0x3UL << CSI_PRGITR_TIM3VC_Pos)          /*!< 0x30000000 */
8576 #define CSI_PRGITR_TIM3VC               CSI_PRGITR_TIM3VC_Msk                    /*!< TIM3 base time linked to a virtual channel */
8577 #define CSI_PRGITR_TIM3EOF_Pos          (30U)
8578 #define CSI_PRGITR_TIM3EOF_Msk          (0x1UL << CSI_PRGITR_TIM3EOF_Pos)         /*!< 0x40000000 */
8579 #define CSI_PRGITR_TIM3EOF              CSI_PRGITR_TIM3EOF_Msk                   /*!< TIM3 base time starting from the end of frame */
8580 #define CSI_PRGITR_TIM3EN_Pos           (31U)
8581 #define CSI_PRGITR_TIM3EN_Msk           (0x1UL << CSI_PRGITR_TIM3EN_Pos)          /*!< 0x80000000 */
8582 #define CSI_PRGITR_TIM3EN               CSI_PRGITR_TIM3EN_Msk                    /*!< TIM3 base time enable */
8583 
8584 /*******************  Bit definition for CSI_WDR register  ********************/
8585 #define CSI_WDR_CNT_Pos                 (0U)
8586 #define CSI_WDR_CNT_Msk                 (0xFFFFFFFFUL << CSI_WDR_CNT_Pos)         /*!< 0xFFFFFFFF */
8587 #define CSI_WDR_CNT                     CSI_WDR_CNT_Msk                          /*!< Watchdog counter */
8588 
8589 /*******************  Bit definition for CSI_IER0 register  *******************/
8590 #define CSI_IER0_LB0IE_Pos              (0U)
8591 #define CSI_IER0_LB0IE_Msk              (0x1UL << CSI_IER0_LB0IE_Pos)             /*!< 0x00000001 */
8592 #define CSI_IER0_LB0IE                  CSI_IER0_LB0IE_Msk                       /*!< Line byte counter 0 interrupt enable */
8593 #define CSI_IER0_LB1IE_Pos              (1U)
8594 #define CSI_IER0_LB1IE_Msk              (0x1UL << CSI_IER0_LB1IE_Pos)             /*!< 0x00000002 */
8595 #define CSI_IER0_LB1IE                  CSI_IER0_LB1IE_Msk                       /*!< Line byte counter 1 interrupt enable */
8596 #define CSI_IER0_LB2IE_Pos              (2U)
8597 #define CSI_IER0_LB2IE_Msk              (0x1UL << CSI_IER0_LB2IE_Pos)             /*!< 0x00000004 */
8598 #define CSI_IER0_LB2IE                  CSI_IER0_LB2IE_Msk                       /*!< Line byte counter 2 interrupt enable */
8599 #define CSI_IER0_LB3IE_Pos              (3U)
8600 #define CSI_IER0_LB3IE_Msk              (0x1UL << CSI_IER0_LB3IE_Pos)             /*!< 0x00000008 */
8601 #define CSI_IER0_LB3IE                  CSI_IER0_LB3IE_Msk                       /*!< Line byte counter 3 interrupt enable */
8602 #define CSI_IER0_TIM0IE_Pos             (4U)
8603 #define CSI_IER0_TIM0IE_Msk             (0x1UL << CSI_IER0_TIM0IE_Pos)            /*!< 0x00000010 */
8604 #define CSI_IER0_TIM0IE                 CSI_IER0_TIM0IE_Msk                      /*!< Timer 0 interrupt enable */
8605 #define CSI_IER0_TIM1IE_Pos             (5U)
8606 #define CSI_IER0_TIM1IE_Msk             (0x1UL << CSI_IER0_TIM1IE_Pos)            /*!< 0x00000020 */
8607 #define CSI_IER0_TIM1IE                 CSI_IER0_TIM1IE_Msk                      /*!< Timer 1 interrupt enable */
8608 #define CSI_IER0_TIM2IE_Pos             (6U)
8609 #define CSI_IER0_TIM2IE_Msk             (0x1UL << CSI_IER0_TIM2IE_Pos)            /*!< 0x00000040 */
8610 #define CSI_IER0_TIM2IE                 CSI_IER0_TIM2IE_Msk                      /*!< Timer 2 interrupt enable */
8611 #define CSI_IER0_TIM3IE_Pos             (7U)
8612 #define CSI_IER0_TIM3IE_Msk             (0x1UL << CSI_IER0_TIM3IE_Pos)            /*!< 0x00000080 */
8613 #define CSI_IER0_TIM3IE                 CSI_IER0_TIM3IE_Msk                      /*!< Timer 3 interrupt enable */
8614 #define CSI_IER0_SOF0IE_Pos             (8U)
8615 #define CSI_IER0_SOF0IE_Msk             (0x1UL << CSI_IER0_SOF0IE_Pos)            /*!< 0x00000100 */
8616 #define CSI_IER0_SOF0IE                 CSI_IER0_SOF0IE_Msk                      /*!< Start of frame for virtual channel 0 interrupt enable */
8617 #define CSI_IER0_SOF1IE_Pos             (9U)
8618 #define CSI_IER0_SOF1IE_Msk             (0x1UL << CSI_IER0_SOF1IE_Pos)            /*!< 0x00000200 */
8619 #define CSI_IER0_SOF1IE                 CSI_IER0_SOF1IE_Msk                      /*!< Start of frame for virtual channel 1 interrupt enable */
8620 #define CSI_IER0_SOF2IE_Pos             (10U)
8621 #define CSI_IER0_SOF2IE_Msk             (0x1UL << CSI_IER0_SOF2IE_Pos)            /*!< 0x00000400 */
8622 #define CSI_IER0_SOF2IE                 CSI_IER0_SOF2IE_Msk                      /*!< Start of frame for virtual channel 2 interrupt enable */
8623 #define CSI_IER0_SOF3IE_Pos             (11U)
8624 #define CSI_IER0_SOF3IE_Msk             (0x1UL << CSI_IER0_SOF3IE_Pos)            /*!< 0x00000800 */
8625 #define CSI_IER0_SOF3IE                 CSI_IER0_SOF3IE_Msk                      /*!< Start of frame for virtual channel 3 interrupt enable */
8626 #define CSI_IER0_EOF0IE_Pos             (12U)
8627 #define CSI_IER0_EOF0IE_Msk             (0x1UL << CSI_IER0_EOF0IE_Pos)            /*!< 0x00001000 */
8628 #define CSI_IER0_EOF0IE                 CSI_IER0_EOF0IE_Msk                      /*!< End of frame for virtual channel 0 interrupt enable */
8629 #define CSI_IER0_EOF1IE_Pos             (13U)
8630 #define CSI_IER0_EOF1IE_Msk             (0x1UL << CSI_IER0_EOF1IE_Pos)            /*!< 0x00002000 */
8631 #define CSI_IER0_EOF1IE                 CSI_IER0_EOF1IE_Msk                      /*!< End of frame for virtual channel 1 interrupt enable */
8632 #define CSI_IER0_EOF2IE_Pos             (14U)
8633 #define CSI_IER0_EOF2IE_Msk             (0x1UL << CSI_IER0_EOF2IE_Pos)            /*!< 0x00004000 */
8634 #define CSI_IER0_EOF2IE                 CSI_IER0_EOF2IE_Msk                      /*!< End of frame for virtual channel 2 interrupt enable */
8635 #define CSI_IER0_EOF3IE_Pos             (15U)
8636 #define CSI_IER0_EOF3IE_Msk             (0x1UL << CSI_IER0_EOF3IE_Pos)            /*!< 0x00008000 */
8637 #define CSI_IER0_EOF3IE                 CSI_IER0_EOF3IE_Msk                      /*!< End of frame for virtual channel 3 interrupt enable */
8638 #define CSI_IER0_SPKTIE_Pos             (16U)
8639 #define CSI_IER0_SPKTIE_Msk             (0x1UL << CSI_IER0_SPKTIE_Pos)            /*!< 0x00010000 */
8640 #define CSI_IER0_SPKTIE                 CSI_IER0_SPKTIE_Msk                      /*!< Short packet interrupt enable */
8641 #define CSI_IER0_CCFIFOFIE_Pos          (21U)
8642 #define CSI_IER0_CCFIFOFIE_Msk          (0x1UL << CSI_IER0_CCFIFOFIE_Pos)         /*!< 0x00200000 */
8643 #define CSI_IER0_CCFIFOFIE              CSI_IER0_CCFIFOFIE_Msk                   /*!< Clock changer FIFO full interrupt enable */
8644 #define CSI_IER0_CRCERRIE_Pos           (24U)
8645 #define CSI_IER0_CRCERRIE_Msk           (0x1UL << CSI_IER0_CRCERRIE_Pos)          /*!< 0x01000000 */
8646 #define CSI_IER0_CRCERRIE               CSI_IER0_CRCERRIE_Msk                    /*!< CRC error interrupt enable */
8647 #define CSI_IER0_ECCERRIE_Pos           (25U)
8648 #define CSI_IER0_ECCERRIE_Msk           (0x1UL << CSI_IER0_ECCERRIE_Pos)          /*!< 0x02000000 */
8649 #define CSI_IER0_ECCERRIE               CSI_IER0_ECCERRIE_Msk                    /*!< ECC error interrupt enable */
8650 #define CSI_IER0_CECCERRIE_Pos          (26U)
8651 #define CSI_IER0_CECCERRIE_Msk          (0x1UL << CSI_IER0_CECCERRIE_Pos)         /*!< 0x04000000 */
8652 #define CSI_IER0_CECCERRIE              CSI_IER0_CECCERRIE_Msk                   /*!< Corrected ECC error interrupt enable */
8653 #define CSI_IER0_IDERRIE_Pos            (27U)
8654 #define CSI_IER0_IDERRIE_Msk            (0x1UL << CSI_IER0_IDERRIE_Pos)           /*!< 0x08000000 */
8655 #define CSI_IER0_IDERRIE                CSI_IER0_IDERRIE_Msk                     /*!< Data type ID error interrupt enable */
8656 #define CSI_IER0_SPKTERRIE_Pos          (28U)
8657 #define CSI_IER0_SPKTERRIE_Msk          (0x1UL << CSI_IER0_SPKTERRIE_Pos)         /*!< 0x10000000 */
8658 #define CSI_IER0_SPKTERRIE              CSI_IER0_SPKTERRIE_Msk                   /*!< Short packet error interrupt enable */
8659 #define CSI_IER0_WDERRIE_Pos            (29U)
8660 #define CSI_IER0_WDERRIE_Msk            (0x1UL << CSI_IER0_WDERRIE_Pos)           /*!< 0x20000000 */
8661 #define CSI_IER0_WDERRIE                CSI_IER0_WDERRIE_Msk                     /*!< Watchdog error interrupt enable */
8662 #define CSI_IER0_SYNCERRIE_Pos          (30U)
8663 #define CSI_IER0_SYNCERRIE_Msk          (0x1UL << CSI_IER0_SYNCERRIE_Pos)         /*!< 0x40000000 */
8664 #define CSI_IER0_SYNCERRIE              CSI_IER0_SYNCERRIE_Msk                   /*!< Invalid synchronization error interrupt enable */
8665 
8666 /*******************  Bit definition for CSI_IER1 register  *******************/
8667 #define CSI_IER1_ESOTDL0IE_Pos          (0U)
8668 #define CSI_IER1_ESOTDL0IE_Msk          (0x1UL << CSI_IER1_ESOTDL0IE_Pos)         /*!< 0x00000001 */
8669 #define CSI_IER1_ESOTDL0IE              CSI_IER1_ESOTDL0IE_Msk                   /*!< Start of transmission error interrupt enable on lane 0 */
8670 #define CSI_IER1_ESOTSYNCDL0IE_Pos      (1U)
8671 #define CSI_IER1_ESOTSYNCDL0IE_Msk      (0x1UL << CSI_IER1_ESOTSYNCDL0IE_Pos)     /*!< 0x00000002 */
8672 #define CSI_IER1_ESOTSYNCDL0IE          CSI_IER1_ESOTSYNCDL0IE_Msk               /*!< Start of transmission synchronization interrupt error enable on lane 0 */
8673 #define CSI_IER1_EESCDL0IE_Pos          (2U)
8674 #define CSI_IER1_EESCDL0IE_Msk          (0x1UL << CSI_IER1_EESCDL0IE_Pos)         /*!< 0x00000004 */
8675 #define CSI_IER1_EESCDL0IE              CSI_IER1_EESCDL0IE_Msk                   /*!< D-PHY_RX lane 0 escape entry error interrupt enable */
8676 #define CSI_IER1_ESYNCESCDL0IE_Pos      (3U)
8677 #define CSI_IER1_ESYNCESCDL0IE_Msk      (0x1UL << CSI_IER1_ESYNCESCDL0IE_Pos)     /*!< 0x00000008 */
8678 #define CSI_IER1_ESYNCESCDL0IE          CSI_IER1_ESYNCESCDL0IE_Msk               /*!< D-PHY_RX lane 0 low power data transmission synchronization error interrupt enable */
8679 #define CSI_IER1_ECTRLDL0IE_Pos         (4U)
8680 #define CSI_IER1_ECTRLDL0IE_Msk         (0x1UL << CSI_IER1_ECTRLDL0IE_Pos)        /*!< 0x00000010 */
8681 #define CSI_IER1_ECTRLDL0IE             CSI_IER1_ECTRLDL0IE_Msk                  /*!< D-PHY_RX lane 0 control error interrupt enable */
8682 #define CSI_IER1_ESOTDL1IE_Pos          (8U)
8683 #define CSI_IER1_ESOTDL1IE_Msk          (0x1UL << CSI_IER1_ESOTDL1IE_Pos)         /*!< 0x00000100 */
8684 #define CSI_IER1_ESOTDL1IE              CSI_IER1_ESOTDL1IE_Msk                   /*!< Start of transmission error interrupt enable on lane 1 */
8685 #define CSI_IER1_ESOTSYNCDL1IE_Pos      (9U)
8686 #define CSI_IER1_ESOTSYNCDL1IE_Msk      (0x1UL << CSI_IER1_ESOTSYNCDL1IE_Pos)     /*!< 0x00000200 */
8687 #define CSI_IER1_ESOTSYNCDL1IE          CSI_IER1_ESOTSYNCDL1IE_Msk               /*!< Start of transmission synchronization interrupt error enable on lane 1 */
8688 #define CSI_IER1_EESCDL1IE_Pos          (10U)
8689 #define CSI_IER1_EESCDL1IE_Msk          (0x1UL << CSI_IER1_EESCDL1IE_Pos)         /*!< 0x00000400 */
8690 #define CSI_IER1_EESCDL1IE              CSI_IER1_EESCDL1IE_Msk                   /*!< D-PHY_RX lane 1 escape entry error interrupt enable */
8691 #define CSI_IER1_ESYNCESCDL1IE_Pos      (11U)
8692 #define CSI_IER1_ESYNCESCDL1IE_Msk      (0x1UL << CSI_IER1_ESYNCESCDL1IE_Pos)     /*!< 0x00000800 */
8693 #define CSI_IER1_ESYNCESCDL1IE          CSI_IER1_ESYNCESCDL1IE_Msk               /*!< D-PHY_RX lane 1 low power data transmission synchronization error interrupt enable */
8694 #define CSI_IER1_ECTRLDL1IE_Pos         (12U)
8695 #define CSI_IER1_ECTRLDL1IE_Msk         (0x1UL << CSI_IER1_ECTRLDL1IE_Pos)        /*!< 0x00001000 */
8696 #define CSI_IER1_ECTRLDL1IE             CSI_IER1_ECTRLDL1IE_Msk                  /*!< D-PHY_RX lane 1 control error interrupt enable */
8697 
8698 /*******************  Bit definition for CSI_SR0 register  ********************/
8699 #define CSI_SR0_LB0F_Pos                (0U)
8700 #define CSI_SR0_LB0F_Msk                (0x1UL << CSI_SR0_LB0F_Pos)               /*!< 0x00000001 */
8701 #define CSI_SR0_LB0F                    CSI_SR0_LB0F_Msk                         /*!< Line byte counter 0 flag */
8702 #define CSI_SR0_LB1F_Pos                (1U)
8703 #define CSI_SR0_LB1F_Msk                (0x1UL << CSI_SR0_LB1F_Pos)               /*!< 0x00000002 */
8704 #define CSI_SR0_LB1F                    CSI_SR0_LB1F_Msk                         /*!< Line byte counter 1 flag */
8705 #define CSI_SR0_LB2F_Pos                (2U)
8706 #define CSI_SR0_LB2F_Msk                (0x1UL << CSI_SR0_LB2F_Pos)               /*!< 0x00000004 */
8707 #define CSI_SR0_LB2F                    CSI_SR0_LB2F_Msk                         /*!< Line byte counter 2 flag */
8708 #define CSI_SR0_LB3F_Pos                (3U)
8709 #define CSI_SR0_LB3F_Msk                (0x1UL << CSI_SR0_LB3F_Pos)               /*!< 0x00000008 */
8710 #define CSI_SR0_LB3F                    CSI_SR0_LB3F_Msk                         /*!< Line byte counter 3 flag */
8711 #define CSI_SR0_TIM0F_Pos               (4U)
8712 #define CSI_SR0_TIM0F_Msk               (0x1UL << CSI_SR0_TIM0F_Pos)              /*!< 0x00000010 */
8713 #define CSI_SR0_TIM0F                   CSI_SR0_TIM0F_Msk                        /*!< Timer 0 flag */
8714 #define CSI_SR0_TIM1F_Pos               (5U)
8715 #define CSI_SR0_TIM1F_Msk               (0x1UL << CSI_SR0_TIM1F_Pos)              /*!< 0x00000020 */
8716 #define CSI_SR0_TIM1F                   CSI_SR0_TIM1F_Msk                        /*!< Timer 1 flag */
8717 #define CSI_SR0_TIM2F_Pos               (6U)
8718 #define CSI_SR0_TIM2F_Msk               (0x1UL << CSI_SR0_TIM2F_Pos)              /*!< 0x00000040 */
8719 #define CSI_SR0_TIM2F                   CSI_SR0_TIM2F_Msk                        /*!< Timer 2 flag */
8720 #define CSI_SR0_TIM3F_Pos               (7U)
8721 #define CSI_SR0_TIM3F_Msk               (0x1UL << CSI_SR0_TIM3F_Pos)              /*!< 0x00000080 */
8722 #define CSI_SR0_TIM3F                   CSI_SR0_TIM3F_Msk                        /*!< Timer 3 flag */
8723 #define CSI_SR0_SOF0F_Pos               (8U)
8724 #define CSI_SR0_SOF0F_Msk               (0x1UL << CSI_SR0_SOF0F_Pos)              /*!< 0x00000100 */
8725 #define CSI_SR0_SOF0F                   CSI_SR0_SOF0F_Msk                        /*!< Start of frame flag for virtual channel 0 */
8726 #define CSI_SR0_SOF1F_Pos               (9U)
8727 #define CSI_SR0_SOF1F_Msk               (0x1UL << CSI_SR0_SOF1F_Pos)              /*!< 0x00000200 */
8728 #define CSI_SR0_SOF1F                   CSI_SR0_SOF1F_Msk                        /*!< Start of frame flag for virtual channel 1 */
8729 #define CSI_SR0_SOF2F_Pos               (10U)
8730 #define CSI_SR0_SOF2F_Msk               (0x1UL << CSI_SR0_SOF2F_Pos)              /*!< 0x00000400 */
8731 #define CSI_SR0_SOF2F                   CSI_SR0_SOF2F_Msk                        /*!< Start of frame flag for virtual channel 2 */
8732 #define CSI_SR0_SOF3F_Pos               (11U)
8733 #define CSI_SR0_SOF3F_Msk               (0x1UL << CSI_SR0_SOF3F_Pos)              /*!< 0x00000800 */
8734 #define CSI_SR0_SOF3F                   CSI_SR0_SOF3F_Msk                        /*!< Start of frame flag for virtual channel 3 */
8735 #define CSI_SR0_EOF0F_Pos               (12U)
8736 #define CSI_SR0_EOF0F_Msk               (0x1UL << CSI_SR0_EOF0F_Pos)              /*!< 0x00001000 */
8737 #define CSI_SR0_EOF0F                   CSI_SR0_EOF0F_Msk                        /*!< End of frame flag for virtual channel 0 */
8738 #define CSI_SR0_EOF1F_Pos               (13U)
8739 #define CSI_SR0_EOF1F_Msk               (0x1UL << CSI_SR0_EOF1F_Pos)              /*!< 0x00002000 */
8740 #define CSI_SR0_EOF1F                   CSI_SR0_EOF1F_Msk                        /*!< End of frame flag for virtual channel 1 */
8741 #define CSI_SR0_EOF2F_Pos               (14U)
8742 #define CSI_SR0_EOF2F_Msk               (0x1UL << CSI_SR0_EOF2F_Pos)              /*!< 0x00004000 */
8743 #define CSI_SR0_EOF2F                   CSI_SR0_EOF2F_Msk                        /*!< End of frame flag for virtual channel 2 */
8744 #define CSI_SR0_EOF3F_Pos               (15U)
8745 #define CSI_SR0_EOF3F_Msk               (0x1UL << CSI_SR0_EOF3F_Pos)              /*!< 0x00008000 */
8746 #define CSI_SR0_EOF3F                   CSI_SR0_EOF3F_Msk                        /*!< End of frame flag for virtual channel 3 */
8747 #define CSI_SR0_SPKTF_Pos               (16U)
8748 #define CSI_SR0_SPKTF_Msk               (0x1UL << CSI_SR0_SPKTF_Pos)              /*!< 0x00010000 */
8749 #define CSI_SR0_SPKTF                   CSI_SR0_SPKTF_Msk                        /*!< Short packet flag */
8750 #define CSI_SR0_VC0STATEF_Pos           (17U)
8751 #define CSI_SR0_VC0STATEF_Msk           (0x1UL << CSI_SR0_VC0STATEF_Pos)          /*!< 0x00020000 */
8752 #define CSI_SR0_VC0STATEF               CSI_SR0_VC0STATEF_Msk                    /*!< Virtual channel 0 state flag */
8753 #define CSI_SR0_VC1STATEF_Pos           (18U)
8754 #define CSI_SR0_VC1STATEF_Msk           (0x1UL << CSI_SR0_VC1STATEF_Pos)          /*!< 0x00040000 */
8755 #define CSI_SR0_VC1STATEF               CSI_SR0_VC1STATEF_Msk                    /*!< Virtual channel 1 state flag */
8756 #define CSI_SR0_VC2STATEF_Pos           (19U)
8757 #define CSI_SR0_VC2STATEF_Msk           (0x1UL << CSI_SR0_VC2STATEF_Pos)          /*!< 0x00080000 */
8758 #define CSI_SR0_VC2STATEF               CSI_SR0_VC2STATEF_Msk                    /*!< Virtual channel 2 state flag */
8759 #define CSI_SR0_VC3STATEF_Pos           (20U)
8760 #define CSI_SR0_VC3STATEF_Msk           (0x1UL << CSI_SR0_VC3STATEF_Pos)          /*!< 0x00100000 */
8761 #define CSI_SR0_VC3STATEF               CSI_SR0_VC3STATEF_Msk                    /*!< Virtual channel 3 state flag */
8762 #define CSI_SR0_CCFIFOFF_Pos            (21U)
8763 #define CSI_SR0_CCFIFOFF_Msk            (0x1UL << CSI_SR0_CCFIFOFF_Pos)           /*!< 0x00200000 */
8764 #define CSI_SR0_CCFIFOFF                CSI_SR0_CCFIFOFF_Msk                     /*!< Clock changer FIFO full flag */
8765 #define CSI_SR0_CRCERRF_Pos             (24U)
8766 #define CSI_SR0_CRCERRF_Msk             (0x1UL << CSI_SR0_CRCERRF_Pos)            /*!< 0x01000000 */
8767 #define CSI_SR0_CRCERRF                 CSI_SR0_CRCERRF_Msk                      /*!< CRC error flag */
8768 #define CSI_SR0_ECCERRF_Pos             (25U)
8769 #define CSI_SR0_ECCERRF_Msk             (0x1UL << CSI_SR0_ECCERRF_Pos)            /*!< 0x02000000 */
8770 #define CSI_SR0_ECCERRF                 CSI_SR0_ECCERRF_Msk                      /*!< ECC error flag */
8771 #define CSI_SR0_CECCERRF_Pos            (26U)
8772 #define CSI_SR0_CECCERRF_Msk            (0x1UL << CSI_SR0_CECCERRF_Pos)           /*!< 0x04000000 */
8773 #define CSI_SR0_CECCERRF                CSI_SR0_CECCERRF_Msk                     /*!< Corrected ECC error flag */
8774 #define CSI_SR0_IDERRF_Pos              (27U)
8775 #define CSI_SR0_IDERRF_Msk              (0x1UL << CSI_SR0_IDERRF_Pos)             /*!< 0x08000000 */
8776 #define CSI_SR0_IDERRF                  CSI_SR0_IDERRF_Msk                       /*!< Data type ID error flag */
8777 #define CSI_SR0_SPKTERRF_Pos            (28U)
8778 #define CSI_SR0_SPKTERRF_Msk            (0x1UL << CSI_SR0_SPKTERRF_Pos)           /*!< 0x10000000 */
8779 #define CSI_SR0_SPKTERRF                CSI_SR0_SPKTERRF_Msk                     /*!< Short packet error flag */
8780 #define CSI_SR0_WDERRF_Pos              (29U)
8781 #define CSI_SR0_WDERRF_Msk              (0x1UL << CSI_SR0_WDERRF_Pos)             /*!< 0x20000000 */
8782 #define CSI_SR0_WDERRF                  CSI_SR0_WDERRF_Msk                       /*!< Watchdog error flag */
8783 #define CSI_SR0_SYNCERRF_Pos            (30U)
8784 #define CSI_SR0_SYNCERRF_Msk            (0x1UL << CSI_SR0_SYNCERRF_Pos)           /*!< 0x40000000 */
8785 #define CSI_SR0_SYNCERRF                CSI_SR0_SYNCERRF_Msk                     /*!< Invalid synchronization error flag */
8786 
8787 /*******************  Bit definition for CSI_SR1 register  ********************/
8788 #define CSI_SR1_ESOTDL0F_Pos            (0U)
8789 #define CSI_SR1_ESOTDL0F_Msk            (0x1UL << CSI_SR1_ESOTDL0F_Pos)           /*!< 0x00000001 */
8790 #define CSI_SR1_ESOTDL0F                CSI_SR1_ESOTDL0F_Msk                     /*!< Start of transmission error flag on lane 0 */
8791 #define CSI_SR1_ESOTSYNCDL0F_Pos        (1U)
8792 #define CSI_SR1_ESOTSYNCDL0F_Msk        (0x1UL << CSI_SR1_ESOTSYNCDL0F_Pos)       /*!< 0x00000002 */
8793 #define CSI_SR1_ESOTSYNCDL0F            CSI_SR1_ESOTSYNCDL0F_Msk                 /*!< Start of transmission synchronization error flag on lane 0 */
8794 #define CSI_SR1_EESCDL0F_Pos            (2U)
8795 #define CSI_SR1_EESCDL0F_Msk            (0x1UL << CSI_SR1_EESCDL0F_Pos)           /*!< 0x00000004 */
8796 #define CSI_SR1_EESCDL0F                CSI_SR1_EESCDL0F_Msk                     /*!< D-PHY_RX lane 0 escape entry error flag */
8797 #define CSI_SR1_ESYNCESCDL0F_Pos        (3U)
8798 #define CSI_SR1_ESYNCESCDL0F_Msk        (0x1UL << CSI_SR1_ESYNCESCDL0F_Pos)       /*!< 0x00000008 */
8799 #define CSI_SR1_ESYNCESCDL0F            CSI_SR1_ESYNCESCDL0F_Msk                 /*!< D-PHY_RX lane 0 low power data transmission synchronization error flag */
8800 #define CSI_SR1_ECTRLDL0F_Pos           (4U)
8801 #define CSI_SR1_ECTRLDL0F_Msk           (0x1UL << CSI_SR1_ECTRLDL0F_Pos)          /*!< 0x00000010 */
8802 #define CSI_SR1_ECTRLDL0F               CSI_SR1_ECTRLDL0F_Msk                    /*!< D-PHY_RX lane 0 control error flag */
8803 #define CSI_SR1_ESOTDL1F_Pos            (8U)
8804 #define CSI_SR1_ESOTDL1F_Msk            (0x1UL << CSI_SR1_ESOTDL1F_Pos)           /*!< 0x00000100 */
8805 #define CSI_SR1_ESOTDL1F                CSI_SR1_ESOTDL1F_Msk                     /*!< Start of transmission error flag on lane 1 */
8806 #define CSI_SR1_ESOTSYNCDL1F_Pos        (9U)
8807 #define CSI_SR1_ESOTSYNCDL1F_Msk        (0x1UL << CSI_SR1_ESOTSYNCDL1F_Pos)       /*!< 0x00000200 */
8808 #define CSI_SR1_ESOTSYNCDL1F            CSI_SR1_ESOTSYNCDL1F_Msk                 /*!< Start of transmission synchronization error flag on lane 1 */
8809 #define CSI_SR1_EESCDL1F_Pos            (10U)
8810 #define CSI_SR1_EESCDL1F_Msk            (0x1UL << CSI_SR1_EESCDL1F_Pos)           /*!< 0x00000400 */
8811 #define CSI_SR1_EESCDL1F                CSI_SR1_EESCDL1F_Msk                     /*!< D-PHY_RX lane 1 escape entry error flag */
8812 #define CSI_SR1_ESYNCESCDL1F_Pos        (11U)
8813 #define CSI_SR1_ESYNCESCDL1F_Msk        (0x1UL << CSI_SR1_ESYNCESCDL1F_Pos)       /*!< 0x00000800 */
8814 #define CSI_SR1_ESYNCESCDL1F            CSI_SR1_ESYNCESCDL1F_Msk                 /*!< D-PHY_RX lane 1 low power data transmission synchronization error flag */
8815 #define CSI_SR1_ECTRLDL1F_Pos           (12U)
8816 #define CSI_SR1_ECTRLDL1F_Msk           (0x1UL << CSI_SR1_ECTRLDL1F_Pos)          /*!< 0x00001000 */
8817 #define CSI_SR1_ECTRLDL1F               CSI_SR1_ECTRLDL1F_Msk                    /*!< D-PHY_RX lane 1 control error flag */
8818 #define CSI_SR1_ACTDL0F_Pos             (16U)
8819 #define CSI_SR1_ACTDL0F_Msk             (0x1UL << CSI_SR1_ACTDL0F_Pos)            /*!< 0x00010000 */
8820 #define CSI_SR1_ACTDL0F                 CSI_SR1_ACTDL0F_Msk                      /*!< D-PHY_RX lane 0 High speed reception active */
8821 #define CSI_SR1_SYNCDL0F_Pos            (17U)
8822 #define CSI_SR1_SYNCDL0F_Msk            (0x1UL << CSI_SR1_SYNCDL0F_Pos)           /*!< 0x00020000 */
8823 #define CSI_SR1_SYNCDL0F                CSI_SR1_SYNCDL0F_Msk                     /*!< D-PHY_RX lane 0 receiver synchronization observed */
8824 #define CSI_SR1_SKCALDL0F_Pos           (18U)
8825 #define CSI_SR1_SKCALDL0F_Msk           (0x1UL << CSI_SR1_SKCALDL0F_Pos)          /*!< 0x00040000 */
8826 #define CSI_SR1_SKCALDL0F               CSI_SR1_SKCALDL0F_Msk                    /*!< D-PHY_RX lane 0 High speed skew calibration */
8827 #define CSI_SR1_STOPDL0F_Pos            (19U)
8828 #define CSI_SR1_STOPDL0F_Msk            (0x1UL << CSI_SR1_STOPDL0F_Pos)           /*!< 0x00080000 */
8829 #define CSI_SR1_STOPDL0F                CSI_SR1_STOPDL0F_Msk                     /*!< D-PHY_RX receiver data lane 0 in stop state */
8830 #define CSI_SR1_ULPNDL0F_Pos            (20U)
8831 #define CSI_SR1_ULPNDL0F_Msk            (0x1UL << CSI_SR1_ULPNDL0F_Pos)           /*!< 0x00100000 */
8832 #define CSI_SR1_ULPNDL0F                CSI_SR1_ULPNDL0F_Msk                     /*!< D-PHY_RX receiver Ultra low power state (not) Active on data lane 00 */
8833 #define CSI_SR1_ACTDL1F_Pos             (22U)
8834 #define CSI_SR1_ACTDL1F_Msk             (0x1UL << CSI_SR1_ACTDL1F_Pos)            /*!< 0x00400000 */
8835 #define CSI_SR1_ACTDL1F                 CSI_SR1_ACTDL1F_Msk                      /*!< D-PHY_RX lane 1 High speed reception active */
8836 #define CSI_SR1_SYNCDL1F_Pos            (23U)
8837 #define CSI_SR1_SYNCDL1F_Msk            (0x1UL << CSI_SR1_SYNCDL1F_Pos)           /*!< 0x00800000 */
8838 #define CSI_SR1_SYNCDL1F                CSI_SR1_SYNCDL1F_Msk                     /*!< D-PHY_RX lane 1 receiver synchronization observed */
8839 #define CSI_SR1_SKCALDL1F_Pos           (24U)
8840 #define CSI_SR1_SKCALDL1F_Msk           (0x1UL << CSI_SR1_SKCALDL1F_Pos)          /*!< 0x01000000 */
8841 #define CSI_SR1_SKCALDL1F               CSI_SR1_SKCALDL1F_Msk                    /*!< D-PHY_RX lane 1 High speed skew calibration */
8842 #define CSI_SR1_STOPDL1F_Pos            (25U)
8843 #define CSI_SR1_STOPDL1F_Msk            (0x1UL << CSI_SR1_STOPDL1F_Pos)           /*!< 0x02000000 */
8844 #define CSI_SR1_STOPDL1F                CSI_SR1_STOPDL1F_Msk                     /*!< D-PHY_RX receiver data lane 1 in stop state */
8845 #define CSI_SR1_ULPNDL1F_Pos            (26U)
8846 #define CSI_SR1_ULPNDL1F_Msk            (0x1UL << CSI_SR1_ULPNDL1F_Pos)           /*!< 0x04000000 */
8847 #define CSI_SR1_ULPNDL1F                CSI_SR1_ULPNDL1F_Msk                     /*!< D-PHY_RX receiver Ultra low power state (not) Active on data lane 1 */
8848 #define CSI_SR1_STOPCLF_Pos             (28U)
8849 #define CSI_SR1_STOPCLF_Msk             (0x1UL << CSI_SR1_STOPCLF_Pos)            /*!< 0x10000000 */
8850 #define CSI_SR1_STOPCLF                 CSI_SR1_STOPCLF_Msk                      /*!< D-PHY_RX receiver in stop state for the clock lane */
8851 #define CSI_SR1_ULPNACTF_Pos            (29U)
8852 #define CSI_SR1_ULPNACTF_Msk            (0x1UL << CSI_SR1_ULPNACTF_Pos)           /*!< 0x20000000 */
8853 #define CSI_SR1_ULPNACTF                CSI_SR1_ULPNACTF_Msk                     /*!< D-PHY_RX receiver ULP state (not) active */
8854 #define CSI_SR1_ULPNCLF_Pos             (30U)
8855 #define CSI_SR1_ULPNCLF_Msk             (0x1UL << CSI_SR1_ULPNCLF_Pos)            /*!< 0x40000000 */
8856 #define CSI_SR1_ULPNCLF                 CSI_SR1_ULPNCLF_Msk                      /*!< D-PHY_RX receiver Ultra-Low power state (not) on clock lane */
8857 #define CSI_SR1_ACTCLF_Pos              (31U)
8858 #define CSI_SR1_ACTCLF_Msk              (0x1UL << CSI_SR1_ACTCLF_Pos)             /*!< 0x80000000 */
8859 #define CSI_SR1_ACTCLF                  CSI_SR1_ACTCLF_Msk                       /*!< D-PHY_RX receiver clock active flag */
8860 
8861 /*******************  Bit definition for CSI_FCR0 register  *******************/
8862 #define CSI_FCR0_CLB0F_Pos              (0U)
8863 #define CSI_FCR0_CLB0F_Msk              (0x1UL << CSI_FCR0_CLB0F_Pos)             /*!< 0x00000001 */
8864 #define CSI_FCR0_CLB0F                  CSI_FCR0_CLB0F_Msk                       /*!< Clear Line byte counter 0 flag */
8865 #define CSI_FCR0_CLB1F_Pos              (1U)
8866 #define CSI_FCR0_CLB1F_Msk              (0x1UL << CSI_FCR0_CLB1F_Pos)             /*!< 0x00000002 */
8867 #define CSI_FCR0_CLB1F                  CSI_FCR0_CLB1F_Msk                       /*!< Clear Line byte counter 1 flag */
8868 #define CSI_FCR0_CLB2F_Pos              (2U)
8869 #define CSI_FCR0_CLB2F_Msk              (0x1UL << CSI_FCR0_CLB2F_Pos)             /*!< 0x00000004 */
8870 #define CSI_FCR0_CLB2F                  CSI_FCR0_CLB2F_Msk                       /*!< Clear Line byte counter 2 flag */
8871 #define CSI_FCR0_CLB3F_Pos              (3U)
8872 #define CSI_FCR0_CLB3F_Msk              (0x1UL << CSI_FCR0_CLB3F_Pos)             /*!< 0x00000008 */
8873 #define CSI_FCR0_CLB3F                  CSI_FCR0_CLB3F_Msk                       /*!< Clear Line byte counter 3 flag */
8874 #define CSI_FCR0_CTIM0F_Pos             (4U)
8875 #define CSI_FCR0_CTIM0F_Msk             (0x1UL << CSI_FCR0_CTIM0F_Pos)            /*!< 0x00000010 */
8876 #define CSI_FCR0_CTIM0F                 CSI_FCR0_CTIM0F_Msk                      /*!< Clear Timer 0 flag */
8877 #define CSI_FCR0_CTIM1F_Pos             (5U)
8878 #define CSI_FCR0_CTIM1F_Msk             (0x1UL << CSI_FCR0_CTIM1F_Pos)            /*!< 0x00000020 */
8879 #define CSI_FCR0_CTIM1F                 CSI_FCR0_CTIM1F_Msk                      /*!< Clear Timer 1 flag */
8880 #define CSI_FCR0_CTIM2F_Pos             (6U)
8881 #define CSI_FCR0_CTIM2F_Msk             (0x1UL << CSI_FCR0_CTIM2F_Pos)            /*!< 0x00000040 */
8882 #define CSI_FCR0_CTIM2F                 CSI_FCR0_CTIM2F_Msk                      /*!< Clear Timer 2 flag */
8883 #define CSI_FCR0_CTIM3F_Pos             (7U)
8884 #define CSI_FCR0_CTIM3F_Msk             (0x1UL << CSI_FCR0_CTIM3F_Pos)            /*!< 0x00000080 */
8885 #define CSI_FCR0_CTIM3F                 CSI_FCR0_CTIM3F_Msk                      /*!< Clear Timer 3 flag */
8886 #define CSI_FCR0_CSOF0F_Pos             (8U)
8887 #define CSI_FCR0_CSOF0F_Msk             (0x1UL << CSI_FCR0_CSOF0F_Pos)            /*!< 0x00000100 */
8888 #define CSI_FCR0_CSOF0F                 CSI_FCR0_CSOF0F_Msk                      /*!< Clear Start of frame flag for virtual channel 0 */
8889 #define CSI_FCR0_CSOF1F_Pos             (9U)
8890 #define CSI_FCR0_CSOF1F_Msk             (0x1UL << CSI_FCR0_CSOF1F_Pos)            /*!< 0x00000200 */
8891 #define CSI_FCR0_CSOF1F                 CSI_FCR0_CSOF1F_Msk                      /*!< Clear Start of frame flag for virtual channel 1 */
8892 #define CSI_FCR0_CSOF2F_Pos             (10U)
8893 #define CSI_FCR0_CSOF2F_Msk             (0x1UL << CSI_FCR0_CSOF2F_Pos)            /*!< 0x00000400 */
8894 #define CSI_FCR0_CSOF2F                 CSI_FCR0_CSOF2F_Msk                      /*!< Clear Start of frame flag for virtual channel 2 */
8895 #define CSI_FCR0_CSOF3F_Pos             (11U)
8896 #define CSI_FCR0_CSOF3F_Msk             (0x1UL << CSI_FCR0_CSOF3F_Pos)            /*!< 0x00000800 */
8897 #define CSI_FCR0_CSOF3F                 CSI_FCR0_CSOF3F_Msk                      /*!< Clear Start of frame flag for virtual channel 3 */
8898 #define CSI_FCR0_CEOF0F_Pos             (12U)
8899 #define CSI_FCR0_CEOF0F_Msk             (0x1UL << CSI_FCR0_CEOF0F_Pos)            /*!< 0x00001000 */
8900 #define CSI_FCR0_CEOF0F                 CSI_FCR0_CEOF0F_Msk                      /*!< Clear End of frame flag for virtual channel 0 */
8901 #define CSI_FCR0_CEOF1F_Pos             (13U)
8902 #define CSI_FCR0_CEOF1F_Msk             (0x1UL << CSI_FCR0_CEOF1F_Pos)            /*!< 0x00002000 */
8903 #define CSI_FCR0_CEOF1F                 CSI_FCR0_CEOF1F_Msk                      /*!< Clear End of frame flag for virtual channel 1 */
8904 #define CSI_FCR0_CEOF2F_Pos             (14U)
8905 #define CSI_FCR0_CEOF2F_Msk             (0x1UL << CSI_FCR0_CEOF2F_Pos)            /*!< 0x00004000 */
8906 #define CSI_FCR0_CEOF2F                 CSI_FCR0_CEOF2F_Msk                      /*!< Clear End of frame flag for virtual channel 2 */
8907 #define CSI_FCR0_CEOF3F_Pos             (15U)
8908 #define CSI_FCR0_CEOF3F_Msk             (0x1UL << CSI_FCR0_CEOF3F_Pos)            /*!< 0x00008000 */
8909 #define CSI_FCR0_CEOF3F                 CSI_FCR0_CEOF3F_Msk                      /*!< Clear End of frame flag for virtual channel 3 */
8910 #define CSI_FCR0_CSPKTF_Pos             (16U)
8911 #define CSI_FCR0_CSPKTF_Msk             (0x1UL << CSI_FCR0_CSPKTF_Pos)            /*!< 0x00010000 */
8912 #define CSI_FCR0_CSPKTF                 CSI_FCR0_CSPKTF_Msk                      /*!< Clear Short packet flag */
8913 #define CSI_FCR0_CCCFIFOFF_Pos          (21U)
8914 #define CSI_FCR0_CCCFIFOFF_Msk          (0x1UL << CSI_FCR0_CCCFIFOFF_Pos)         /*!< 0x00200000 */
8915 #define CSI_FCR0_CCCFIFOFF              CSI_FCR0_CCCFIFOFF_Msk                   /*!< Clear Clock changer FIFO full flag */
8916 #define CSI_FCR0_CCRCERRF_Pos           (24U)
8917 #define CSI_FCR0_CCRCERRF_Msk           (0x1UL << CSI_FCR0_CCRCERRF_Pos)          /*!< 0x01000000 */
8918 #define CSI_FCR0_CCRCERRF               CSI_FCR0_CCRCERRF_Msk                    /*!< Clear CRC error flag */
8919 #define CSI_FCR0_CECCERRF_Pos           (25U)
8920 #define CSI_FCR0_CECCERRF_Msk           (0x1UL << CSI_FCR0_CECCERRF_Pos)          /*!< 0x02000000 */
8921 #define CSI_FCR0_CECCERRF               CSI_FCR0_CECCERRF_Msk                    /*!< Clear ECC error flag */
8922 #define CSI_FCR0_CCECCERRF_Pos          (26U)
8923 #define CSI_FCR0_CCECCERRF_Msk          (0x1UL << CSI_FCR0_CCECCERRF_Pos)         /*!< 0x04000000 */
8924 #define CSI_FCR0_CCECCERRF              CSI_FCR0_CCECCERRF_Msk                   /*!< Clear Corrected ECC error flag */
8925 #define CSI_FCR0_CIDERRF_Pos            (27U)
8926 #define CSI_FCR0_CIDERRF_Msk            (0x1UL << CSI_FCR0_CIDERRF_Pos)           /*!< 0x08000000 */
8927 #define CSI_FCR0_CIDERRF                CSI_FCR0_CIDERRF_Msk                     /*!< Clear Data type ID error flag */
8928 #define CSI_FCR0_CSPKTERRF_Pos          (28U)
8929 #define CSI_FCR0_CSPKTERRF_Msk          (0x1UL << CSI_FCR0_CSPKTERRF_Pos)         /*!< 0x10000000 */
8930 #define CSI_FCR0_CSPKTERRF              CSI_FCR0_CSPKTERRF_Msk                   /*!< Clear Short packet error flag */
8931 #define CSI_FCR0_CWDERRF_Pos            (29U)
8932 #define CSI_FCR0_CWDERRF_Msk            (0x1UL << CSI_FCR0_CWDERRF_Pos)           /*!< 0x20000000 */
8933 #define CSI_FCR0_CWDERRF                CSI_FCR0_CWDERRF_Msk                     /*!< Clear Watchdog error flag */
8934 #define CSI_FCR0_CSYNCERRF_Pos          (30U)
8935 #define CSI_FCR0_CSYNCERRF_Msk          (0x1UL << CSI_FCR0_CSYNCERRF_Pos)         /*!< 0x40000000 */
8936 #define CSI_FCR0_CSYNCERRF              CSI_FCR0_CSYNCERRF_Msk                   /*!< Clear Invalid synchronization error flag */
8937 
8938 /*******************  Bit definition for CSI_FCR1 register  *******************/
8939 #define CSI_FCR1_CESOTDL0F_Pos          (0U)
8940 #define CSI_FCR1_CESOTDL0F_Msk          (0x1UL << CSI_FCR1_CESOTDL0F_Pos)         /*!< 0x00000001 */
8941 #define CSI_FCR1_CESOTDL0F              CSI_FCR1_CESOTDL0F_Msk                   /*!< Clear Start of transmission error flag on lane 0 */
8942 #define CSI_FCR1_CESOTSYNCDL0F_Pos      (1U)
8943 #define CSI_FCR1_CESOTSYNCDL0F_Msk      (0x1UL << CSI_FCR1_CESOTSYNCDL0F_Pos)     /*!< 0x00000002 */
8944 #define CSI_FCR1_CESOTSYNCDL0F          CSI_FCR1_CESOTSYNCDL0F_Msk               /*!< Clear Start of transmission synchronization error flag on lane 0 */
8945 #define CSI_FCR1_CEESCDL0F_Pos          (2U)
8946 #define CSI_FCR1_CEESCDL0F_Msk          (0x1UL << CSI_FCR1_CEESCDL0F_Pos)         /*!< 0x00000004 */
8947 #define CSI_FCR1_CEESCDL0F              CSI_FCR1_CEESCDL0F_Msk                   /*!< Clear D-PHY_RX lane 0 escape entry error flag */
8948 #define CSI_FCR1_CESYNCESCDL0F_Pos      (3U)
8949 #define CSI_FCR1_CESYNCESCDL0F_Msk      (0x1UL << CSI_FCR1_CESYNCESCDL0F_Pos)     /*!< 0x00000008 */
8950 #define CSI_FCR1_CESYNCESCDL0F          CSI_FCR1_CESYNCESCDL0F_Msk               /*!< Clear D-PHY_RX lane 0 low power data transmission synchronization error flag */
8951 #define CSI_FCR1_CECTRLDL0F_Pos         (4U)
8952 #define CSI_FCR1_CECTRLDL0F_Msk         (0x1UL << CSI_FCR1_CECTRLDL0F_Pos)        /*!< 0x00000010 */
8953 #define CSI_FCR1_CECTRLDL0F             CSI_FCR1_CECTRLDL0F_Msk                  /*!< Clear D-PHY_RX lane 0 control error flag */
8954 #define CSI_FCR1_CESOTDL1F_Pos          (8U)
8955 #define CSI_FCR1_CESOTDL1F_Msk          (0x1UL << CSI_FCR1_CESOTDL1F_Pos)         /*!< 0x00000100 */
8956 #define CSI_FCR1_CESOTDL1F              CSI_FCR1_CESOTDL1F_Msk                   /*!< Clear Start of transmission error flag on lane 1 */
8957 #define CSI_FCR1_CESOTSYNCDL1F_Pos      (9U)
8958 #define CSI_FCR1_CESOTSYNCDL1F_Msk      (0x1UL << CSI_FCR1_CESOTSYNCDL1F_Pos)     /*!< 0x00000200 */
8959 #define CSI_FCR1_CESOTSYNCDL1F          CSI_FCR1_CESOTSYNCDL1F_Msk               /*!< Clear Start of transmission synchronization error flag on lane 1 */
8960 #define CSI_FCR1_CEESCDL1F_Pos          (10U)
8961 #define CSI_FCR1_CEESCDL1F_Msk          (0x1UL << CSI_FCR1_CEESCDL1F_Pos)         /*!< 0x00000400 */
8962 #define CSI_FCR1_CEESCDL1F              CSI_FCR1_CEESCDL1F_Msk                   /*!< Clear D-PHY_RX lane 1 escape entry error flag */
8963 #define CSI_FCR1_CESYNCESCDL1F_Pos      (11U)
8964 #define CSI_FCR1_CESYNCESCDL1F_Msk      (0x1UL << CSI_FCR1_CESYNCESCDL1F_Pos)     /*!< 0x00000800 */
8965 #define CSI_FCR1_CESYNCESCDL1F          CSI_FCR1_CESYNCESCDL1F_Msk               /*!< Clear D-PHY_RX lane 1 low power data transmission synchronization error flag */
8966 #define CSI_FCR1_CECTRLDL1F_Pos         (12U)
8967 #define CSI_FCR1_CECTRLDL1F_Msk         (0x1UL << CSI_FCR1_CECTRLDL1F_Pos)        /*!< 0x00001000 */
8968 #define CSI_FCR1_CECTRLDL1F             CSI_FCR1_CECTRLDL1F_Msk                  /*!< Clear D-PHY_RX lane 1 control error flag */
8969 
8970 /******************  Bit definition for CSI_SPDFR register  *******************/
8971 #define CSI_SPDFR_DATAFIELD_Pos         (0U)
8972 #define CSI_SPDFR_DATAFIELD_Msk         (0xFFFFUL << CSI_SPDFR_DATAFIELD_Pos)     /*!< 0x0000FFFF */
8973 #define CSI_SPDFR_DATAFIELD             CSI_SPDFR_DATAFIELD_Msk                  /*!< Data field */
8974 #define CSI_SPDFR_DATATYPE_Pos          (16U)
8975 #define CSI_SPDFR_DATATYPE_Msk          (0x3FUL << CSI_SPDFR_DATATYPE_Pos)        /*!< 0x003F0000 */
8976 #define CSI_SPDFR_DATATYPE              CSI_SPDFR_DATATYPE_Msk                   /*!< Data type class */
8977 #define CSI_SPDFR_VCHANNEL_Pos          (22U)
8978 #define CSI_SPDFR_VCHANNEL_Msk          (0x3UL << CSI_SPDFR_VCHANNEL_Pos)         /*!< 0x00C00000 */
8979 #define CSI_SPDFR_VCHANNEL              CSI_SPDFR_VCHANNEL_Msk                   /*!< Virtual channel */
8980 
8981 /*******************  Bit definition for CSI_ERR1 register  *******************/
8982 #define CSI_ERR1_CRCDTERR_Pos           (0U)
8983 #define CSI_ERR1_CRCDTERR_Msk           (0x3FUL << CSI_ERR1_CRCDTERR_Pos)         /*!< 0x0000003F */
8984 #define CSI_ERR1_CRCDTERR               CSI_ERR1_CRCDTERR_Msk                    /*!< Data type having a CRC error */
8985 #define CSI_ERR1_CRCVCERR_Pos           (6U)
8986 #define CSI_ERR1_CRCVCERR_Msk           (0x3UL << CSI_ERR1_CRCVCERR_Pos)          /*!< 0x000000C0 */
8987 #define CSI_ERR1_CRCVCERR               CSI_ERR1_CRCVCERR_Msk                    /*!< Virtual channel having a CRC error */
8988 #define CSI_ERR1_CECCDTERR_Pos          (8U)
8989 #define CSI_ERR1_CECCDTERR_Msk          (0x3FUL << CSI_ERR1_CECCDTERR_Pos)        /*!< 0x00003F00 */
8990 #define CSI_ERR1_CECCDTERR              CSI_ERR1_CECCDTERR_Msk                   /*!< Data type having a corrected ECC error */
8991 #define CSI_ERR1_CECCVCERR_Pos          (14U)
8992 #define CSI_ERR1_CECCVCERR_Msk          (0x3UL << CSI_ERR1_CECCVCERR_Pos)         /*!< 0x0000C000 */
8993 #define CSI_ERR1_CECCVCERR              CSI_ERR1_CECCVCERR_Msk                   /*!< Virtual channel having a corrected ECC error */
8994 #define CSI_ERR1_IDDTERR_Pos            (16U)
8995 #define CSI_ERR1_IDDTERR_Msk            (0x3FUL << CSI_ERR1_IDDTERR_Pos)          /*!< 0x003F0000 */
8996 #define CSI_ERR1_IDDTERR                CSI_ERR1_IDDTERR_Msk                     /*!< Data type in error */
8997 #define CSI_ERR1_IDVCERR_Pos            (22U)
8998 #define CSI_ERR1_IDVCERR_Msk            (0x3UL << CSI_ERR1_IDVCERR_Pos)           /*!< 0x00C00000 */
8999 #define CSI_ERR1_IDVCERR                CSI_ERR1_IDVCERR_Msk                     /*!< Virtual channel having ID error */
9000 
9001 /*******************  Bit definition for CSI_ERR2 register  *******************/
9002 #define CSI_ERR2_SPKTDTERR_Pos          (0U)
9003 #define CSI_ERR2_SPKTDTERR_Msk          (0x3FUL << CSI_ERR2_SPKTDTERR_Pos)        /*!< 0x0000003F */
9004 #define CSI_ERR2_SPKTDTERR              CSI_ERR2_SPKTDTERR_Msk                   /*!< Data type having a short packet error */
9005 #define CSI_ERR2_SPKTVCERR_Pos          (6U)
9006 #define CSI_ERR2_SPKTVCERR_Msk          (0x3UL << CSI_ERR2_SPKTVCERR_Pos)         /*!< 0x000000C0 */
9007 #define CSI_ERR2_SPKTVCERR              CSI_ERR2_SPKTVCERR_Msk                   /*!< Virtual channel having a short packet error */
9008 #define CSI_ERR2_WDVCERR_Pos            (16U)
9009 #define CSI_ERR2_WDVCERR_Msk            (0x3UL << CSI_ERR2_WDVCERR_Pos)           /*!< 0x00030000 */
9010 #define CSI_ERR2_WDVCERR                CSI_ERR2_WDVCERR_Msk                     /*!< Virtual channel having a watchdog error */
9011 #define CSI_ERR2_SYNCVCERR_Pos          (18U)
9012 #define CSI_ERR2_SYNCVCERR_Msk          (0x3UL << CSI_ERR2_SYNCVCERR_Pos)         /*!< 0x000C0000 */
9013 #define CSI_ERR2_SYNCVCERR              CSI_ERR2_SYNCVCERR_Msk                   /*!< Virtual channel having synchronization error */
9014 
9015 /*******************  Bit definition for CSI_PRCR register  *******************/
9016 #define CSI_PRCR_PEN_Pos                (1U)
9017 #define CSI_PRCR_PEN_Msk                (0x1UL << CSI_PRCR_PEN_Pos)               /*!< 0x00000002 */
9018 #define CSI_PRCR_PEN                    CSI_PRCR_PEN_Msk                         /*!< When set to 0, this bit places the digital section of the D-PHY in the reset state */
9019 
9020 /*******************  Bit definition for CSI_PMCR register  *******************/
9021 #define CSI_PMCR_FRXMDL0_Pos            (0U)
9022 #define CSI_PMCR_FRXMDL0_Msk            (0x1UL << CSI_PMCR_FRXMDL0_Pos)           /*!< 0x00000001 */
9023 #define CSI_PMCR_FRXMDL0                CSI_PMCR_FRXMDL0_Msk                     /*!< Force to Rx Mode the Data Lane 0 */
9024 #define CSI_PMCR_FRXMDL1_Pos            (1U)
9025 #define CSI_PMCR_FRXMDL1_Msk            (0x1UL << CSI_PMCR_FRXMDL1_Pos)           /*!< 0x00000002 */
9026 #define CSI_PMCR_FRXMDL1                CSI_PMCR_FRXMDL1_Msk                     /*!< Force to Rx Mode the Data Lane 1 */
9027 #define CSI_PMCR_FTXSMDL0_Pos           (2U)
9028 #define CSI_PMCR_FTXSMDL0_Msk           (0x1UL << CSI_PMCR_FTXSMDL0_Pos)          /*!< 0x00000004 */
9029 #define CSI_PMCR_FTXSMDL0               CSI_PMCR_FTXSMDL0_Msk                    /*!< Force to Tx Stop Mode the Data Lane 0 */
9030 #define CSI_PMCR_DTDL_Pos               (4U)
9031 #define CSI_PMCR_DTDL_Msk               (0x1UL << CSI_PMCR_DTDL_Pos)              /*!< 0x00000010 */
9032 #define CSI_PMCR_DTDL                   CSI_PMCR_DTDL_Msk                        /*!< Disable Turn-around Data Lane 0 */
9033 #define CSI_PMCR_RTDL0_Pos              (8U)
9034 #define CSI_PMCR_RTDL0_Msk              (0x1UL << CSI_PMCR_RTDL0_Pos)             /*!< 0x00000100 */
9035 #define CSI_PMCR_RTDL0                  CSI_PMCR_RTDL0_Msk                       /*!< Turn-around Request Data Lane 0 */
9036 #define CSI_PMCR_TUESDL0_Pos            (12U)
9037 #define CSI_PMCR_TUESDL0_Msk            (0x1UL << CSI_PMCR_TUESDL0_Pos)           /*!< 0x00001000 */
9038 #define CSI_PMCR_TUESDL0                CSI_PMCR_TUESDL0_Msk                     /*!< Tx ULP Escape-mode Data Lane 0 */
9039 #define CSI_PMCR_TUEXDL0_Pos            (16U)
9040 #define CSI_PMCR_TUEXDL0_Msk            (0x1UL << CSI_PMCR_TUEXDL0_Pos)           /*!< 0x00010000 */
9041 #define CSI_PMCR_TUEXDL0                CSI_PMCR_TUEXDL0_Msk                     /*!< Tx ULP Exit-sequence Data Lane 0 */
9042 
9043 /*******************  Bit definition for CSI_PFCR register  *******************/
9044 #define CSI_PFCR_CCFR_Pos               (0U)
9045 #define CSI_PFCR_CCFR_Msk               (0x3FUL << CSI_PFCR_CCFR_Pos)             /*!< 0x0000003F */
9046 #define CSI_PFCR_CCFR                   CSI_PFCR_CCFR_Msk                        /*!< Configuration Clock Frequency Range selection */
9047 #define CSI_PFCR_HSFR_Pos               (8U)
9048 #define CSI_PFCR_HSFR_Msk               (0x7FUL << CSI_PFCR_HSFR_Pos)             /*!< 0x00007F00 */
9049 #define CSI_PFCR_HSFR                   CSI_PFCR_HSFR_Msk                        /*!< PHY-high-speed Frequency Range selection */
9050 #define CSI_PFCR_DLD_Pos                (16U)
9051 #define CSI_PFCR_DLD_Msk                (0x1UL << CSI_PFCR_DLD_Pos)               /*!< 0x00010000 */
9052 #define CSI_PFCR_DLD                    CSI_PFCR_DLD_Msk                         /*!< Data Lane Direction of lane0 */
9053 
9054 /******************  Bit definition for CSI_PTCR0 register  *******************/
9055 #define CSI_PTCR0_TCKEN_Pos             (0U)
9056 #define CSI_PTCR0_TCKEN_Msk             (0x1UL << CSI_PTCR0_TCKEN_Pos)            /*!< 0x00000001 */
9057 #define CSI_PTCR0_TCKEN                 CSI_PTCR0_TCKEN_Msk                      /*!< Test-interface Clock Enable for the TDI bus into the PHY */
9058 #define CSI_PTCR0_TRSEN_Pos             (1U)
9059 #define CSI_PTCR0_TRSEN_Msk             (0x1UL << CSI_PTCR0_TRSEN_Pos)            /*!< 0x00000002 */
9060 #define CSI_PTCR0_TRSEN                 CSI_PTCR0_TRSEN_Msk                      /*!< Test-interface Reset Enable for the TDI bus into the PHY */
9061 
9062 /******************  Bit definition for CSI_PTCR1 register  *******************/
9063 #define CSI_PTCR1_TDI_Pos               (0U)
9064 #define CSI_PTCR1_TDI_Msk               (0xFFUL << CSI_PTCR1_TDI_Pos)             /*!< 0x000000FF */
9065 #define CSI_PTCR1_TDI                   CSI_PTCR1_TDI_Msk                        /*!< Test-interface Data In */
9066 #define CSI_PTCR1_TWM_Pos               (16U)
9067 #define CSI_PTCR1_TWM_Msk               (0x1UL << CSI_PTCR1_TWM_Pos)              /*!< 0x00010000 */
9068 #define CSI_PTCR1_TWM                   CSI_PTCR1_TWM_Msk                        /*!< Test-interface Write Mode selector */
9069 
9070 /*******************  Bit definition for CSI_PTSR register  *******************/
9071 #define CSI_PTSR_TDO_Pos                (0U)
9072 #define CSI_PTSR_TDO_Msk                (0xFFUL << CSI_PTSR_TDO_Pos)              /*!< 0x000000FF */
9073 #define CSI_PTSR_TDO                    CSI_PTSR_TDO_Msk                         /*!< CSI PHY test interface data output bus for read-back and internal probing functionalities */
9074 
9075 
9076 /*********************************************************************************/
9077 /*                                                                               */
9078 /*                                DBGMCU                                         */
9079 /*                                                                               */
9080 /*********************************************************************************/
9081 /********************  Bit definition for DBGMCU_IDCODE register  ****************/
9082 #define DBGMCU_IDCODE_DEV_ID_Pos             (0U)
9083 #define DBGMCU_IDCODE_DEV_ID_Msk             (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)          /*!< 0x00000FFF */
9084 #define DBGMCU_IDCODE_DEV_ID                 DBGMCU_IDCODE_DEV_ID_Msk                       /*!< Device ID */
9085 #define DBGMCU_IDCODE_REV_ID_Pos             (16U)
9086 #define DBGMCU_IDCODE_REV_ID_Msk             (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)         /*!< 0xFFFF0000 */
9087 #define DBGMCU_IDCODE_REV_ID                 DBGMCU_IDCODE_REV_ID_Msk                       /*!< Revision ID */
9088 
9089 /********************  Bit definition for DBGMCU_CR register  ********************/
9090 #define DBGMCU_CR_DBG_SLEEP_Pos              (0U)
9091 #define DBGMCU_CR_DBG_SLEEP_Msk              (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)             /*!< 0x00000001 */
9092 #define DBGMCU_CR_DBG_SLEEP                  DBGMCU_CR_DBG_SLEEP_Msk                        /*!< Allow debug in Sleep mode */
9093 #define DBGMCU_CR_DBG_STOP_Pos               (1U)
9094 #define DBGMCU_CR_DBG_STOP_Msk               (0x1UL << DBGMCU_CR_DBG_STOP_Pos)              /*!< 0x00000002 */
9095 #define DBGMCU_CR_DBG_STOP                   DBGMCU_CR_DBG_STOP_Msk                         /*!< Allow debug in Stop mode */
9096 #define DBGMCU_CR_DBG_STANDBY_Pos            (2U)
9097 #define DBGMCU_CR_DBG_STANDBY_Msk            (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)           /*!< 0x00000004 */
9098 #define DBGMCU_CR_DBG_STANDBY                DBGMCU_CR_DBG_STANDBY_Msk                      /*!< Allow debug in Standby mode */
9099 #define DBGMCU_CR_DBGCLKEN_Pos               (20U)
9100 #define DBGMCU_CR_DBGCLKEN_Msk               (0x1UL << DBGMCU_CR_DBGCLKEN_Pos)              /*!< 0x00100000 */
9101 #define DBGMCU_CR_DBGCLKEN                   DBGMCU_CR_DBGCLKEN_Msk                         /*!< Debug clock enable through software */
9102 #define DBGMCU_CR_TRACECLKEN_Pos             (21U)
9103 #define DBGMCU_CR_TRACECLKEN_Msk             (0x1UL << DBGMCU_CR_TRACECLKEN_Pos)            /*!< 0x00200000 */
9104 #define DBGMCU_CR_TRACECLKEN                 DBGMCU_CR_TRACECLKEN_Msk                       /*!< TPIU export clock enable through software */
9105 #define DBGMCU_CR_DBTRGOEN_Pos               (28U)
9106 #define DBGMCU_CR_DBTRGOEN_Msk               (0x1UL << DBGMCU_CR_DBTRGOEN_Pos)              /*!< 0x10000000 */
9107 #define DBGMCU_CR_DBTRGOEN                   DBGMCU_CR_DBTRGOEN_Msk                         /*!< DBTRGIO connection control */
9108 #define DBGMCU_CR_HLT_TSGEN_EN_Pos           (31U)
9109 #define DBGMCU_CR_HLT_TSGEN_EN_Msk           (0x1UL << DBGMCU_CR_HLT_TSGEN_EN_Pos)          /*!< 0x80000000 */
9110 #define DBGMCU_CR_HLT_TSGEN_EN               DBGMCU_CR_HLT_TSGEN_EN_Msk                     /*!< TSGEN halt enable */
9111 
9112 /********************  Bit definition for DBGMCU_APB1LFZ1 register  ***************/
9113 #define DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Pos    (0U)
9114 #define DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Pos)   /*!< 0x00000001 */
9115 #define DBGMCU_APB1LFZ1_DBG_TIM2_STOP        DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Msk              /*!< TIM2 stop in debug */
9116 #define DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Pos    (1U)
9117 #define DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Pos)   /*!< 0x00000002 */
9118 #define DBGMCU_APB1LFZ1_DBG_TIM3_STOP        DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Msk              /*!< TIM3 stop in debug */
9119 #define DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Pos    (2U)
9120 #define DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Pos)   /*!< 0x00000004 */
9121 #define DBGMCU_APB1LFZ1_DBG_TIM4_STOP        DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Msk              /*!< TIM4 stop in debug */
9122 #define DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Pos    (3U)
9123 #define DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Pos)   /*!< 0x00000008 */
9124 #define DBGMCU_APB1LFZ1_DBG_TIM5_STOP        DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Msk              /*!< TIM5 stop in debug */
9125 #define DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Pos    (4U)
9126 #define DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Pos)   /*!< 0x00000010 */
9127 #define DBGMCU_APB1LFZ1_DBG_TIM6_STOP        DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Msk              /*!< TIM6 stop in debug */
9128 #define DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Pos    (5U)
9129 #define DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Pos)  /*!< 0x00000020 */
9130 #define DBGMCU_APB1LFZ1_DBG_TIM7_STOP        DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Msk             /*!< TIM7 stop in debug */
9131 #define DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Pos   (6U)
9132 #define DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Msk   (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Pos)  /*!< 0x00000040 */
9133 #define DBGMCU_APB1LFZ1_DBG_TIM12_STOP       DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Msk             /*!< TIM12 stop in debug */
9134 #define DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Pos   (7U)
9135 #define DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Msk   (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Pos)  /*!< 0x00000080 */
9136 #define DBGMCU_APB1LFZ1_DBG_TIM13_STOP       DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Msk             /*!< TIM13 stop in debug */
9137 #define DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Pos   (8U)
9138 #define DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Msk   (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Pos)  /*!< 0x00000100 */
9139 #define DBGMCU_APB1LFZ1_DBG_TIM14_STOP       DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Msk             /*!< TIM14 stop in debug */
9140 #define DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Pos  (9U)
9141 #define DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Msk  (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Pos) /*!< 0x00000200 */
9142 #define DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP      DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Msk            /*!< LPTIM1 stop in debug */
9143 #define DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Pos   (11U)
9144 #define DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Msk   (0x1UL << DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Pos)  /*!< 0x00000800 */
9145 #define DBGMCU_APB1LFZ1_DBG_WWDG1_STOP       DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Msk             /*!< WWDG1 stop in debug */
9146 #define DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Pos   (12U)
9147 #define DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Msk   (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Pos)  /*!< 0x00001000 */
9148 #define DBGMCU_APB1LFZ1_DBG_TIM10_STOP       DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Msk             /*!< TIM10 stop in debug */
9149 #define DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Pos   (13U)
9150 #define DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Msk   (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Pos)  /*!< 0x00002000 */
9151 #define DBGMCU_APB1LFZ1_DBG_TIM11_STOP       DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Msk             /*!< TIM11 stop in debug */
9152 #define DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Pos    (21U)
9153 #define DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Pos)   /*!< 0x00200000 */
9154 #define DBGMCU_APB1LFZ1_DBG_I2C1_STOP        DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Msk              /*!< I2C1 SMBUS timeout stop in debug */
9155 #define DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Pos    (22U)
9156 #define DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Pos)   /*!< 0x00400000 */
9157 #define DBGMCU_APB1LFZ1_DBG_I2C2_STOP        DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Msk              /*!< I2C2 SMBUS timeout stop in debug */
9158 #define DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Pos    (23U)
9159 #define DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Pos)   /*!< 0x00800000 */
9160 #define DBGMCU_APB1LFZ1_DBG_I2C3_STOP        DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Msk              /*!< I2C3 SMBUS timeout stop in debug */
9161 #define DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Pos    (24U)
9162 #define DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Pos)   /*!< 0x01000000 */
9163 #define DBGMCU_APB1LFZ1_DBG_I3C1_STOP        DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Msk              /*!< I3C1 SMBUS timeout stop in debug */
9164 #define DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Pos    (25U)
9165 #define DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Pos)   /*!< 0x00008000 */
9166 #define DBGMCU_APB1LFZ1_DBG_I3C2_STOP        DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Msk              /*!< I3C2 SMBUS timeout stop in debug */
9167 
9168 /********************  Bit definition for DBGMCU_APB1HFZ1 register  ***************/
9169 #define DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Pos   (8U)
9170 #define DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Msk   (0x1UL << DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Pos)  /*!< 0x00000100 */
9171 #define DBGMCU_APB1HFZ1_DBG_FDCAN_STOP       DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Msk             /*!< FDCAN stop in debug */
9172 
9173 /********************  Bit definition for DBGMCU_APB2FZ1 register  ***************/
9174 #define DBGMCU_APB2FZ1_DBG_TIM1_STOP_Pos     (0U)
9175 #define DBGMCU_APB2FZ1_DBG_TIM1_STOP_Msk     (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_STOP_Pos)    /*!< 0x00000001 */
9176 #define DBGMCU_APB2FZ1_DBG_TIM1_STOP         DBGMCU_APB2FZ1_DBG_TIM1_STOP_Msk               /*!< TIM1 stop in debug */
9177 #define DBGMCU_APB2FZ1_DBG_TIM8_STOP_Pos     (1U)
9178 #define DBGMCU_APB2FZ1_DBG_TIM8_STOP_Msk     (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_STOP_Pos)    /*!< 0x00000002 */
9179 #define DBGMCU_APB2FZ1_DBG_TIM8_STOP         DBGMCU_APB2FZ1_DBG_TIM8_STOP_Msk               /*!< TIM8 stop in debug */
9180 #define DBGMCU_APB2FZ1_DBG_TIM18_STOP_Pos    (15U)
9181 #define DBGMCU_APB2FZ1_DBG_TIM18_STOP_Msk    (0x1UL << DBGMCU_APB2FZ1_DBG_TIM18_STOP_Pos)   /*!< 0x00008000 */
9182 #define DBGMCU_APB2FZ1_DBG_TIM18_STOP        DBGMCU_APB2FZ1_DBG_TIM18_STOP_Msk              /*!< TIM18 stop in debug */
9183 #define DBGMCU_APB2FZ1_DBG_TIM15_STOP_Pos    (16U)
9184 #define DBGMCU_APB2FZ1_DBG_TIM15_STOP_Msk    (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_STOP_Pos)   /*!< 0x00010000 */
9185 #define DBGMCU_APB2FZ1_DBG_TIM15_STOP        DBGMCU_APB2FZ1_DBG_TIM15_STOP_Msk              /*!< TIM15 stop in debug */
9186 #define DBGMCU_APB2FZ1_DBG_TIM16_STOP_Pos    (17U)
9187 #define DBGMCU_APB2FZ1_DBG_TIM16_STOP_Msk    (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_STOP_Pos)   /*!< 0x00020000 */
9188 #define DBGMCU_APB2FZ1_DBG_TIM16_STOP        DBGMCU_APB2FZ1_DBG_TIM16_STOP_Msk              /*!< TIM16 stop in debug */
9189 #define DBGMCU_APB2FZ1_DBG_TIM17_STOP_Pos    (18U)
9190 #define DBGMCU_APB2FZ1_DBG_TIM17_STOP_Msk    (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_STOP_Pos)   /*!< 0x00040000 */
9191 #define DBGMCU_APB2FZ1_DBG_TIM17_STOP        DBGMCU_APB2FZ1_DBG_TIM17_STOP_Msk              /*!< TIM17 stop in debug */
9192 #define DBGMCU_APB2FZ1_DBG_TIM9_STOP_Pos     (19U)
9193 #define DBGMCU_APB2FZ1_DBG_TIM9_STOP_Msk     (0x1UL << DBGMCU_APB2FZ1_DBG_TIM9_STOP_Pos)    /*!< 0x00080000 */
9194 #define DBGMCU_APB2FZ1_DBG_TIM9_STOP         DBGMCU_APB2FZ1_DBG_TIM9_STOP_Msk               /*!< TIM9 stop in debug */
9195 
9196 /********************  Bit definition for DBGMCU_APB4FZ1 register  ***************/
9197 #define DBGMCU_APB4FZ1_DBG_I2C4_STOP_Pos     (8U)
9198 #define DBGMCU_APB4FZ1_DBG_I2C4_STOP_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_STOP_Pos)    /*!< 0x00000100 */
9199 #define DBGMCU_APB4FZ1_DBG_I2C4_STOP         DBGMCU_APB4FZ1_DBG_I2C4_STOP_Msk               /*!< I2C4 stop in debug */
9200 #define DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Pos   (9U)
9201 #define DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Msk   (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Pos)  /*!< 0x00000200 */
9202 #define DBGMCU_APB4FZ1_DBG_LPTIM2_STOP       DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Msk             /*!< LPTIM2 stop in debug */
9203 #define DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Pos   (10U)
9204 #define DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Msk   (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Pos)  /*!< 0x00000400 */
9205 #define DBGMCU_APB4FZ1_DBG_LPTIM3_STOP       DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Msk             /*!< LPTIM3 stop in debug */
9206 #define DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Pos   (11U)
9207 #define DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Msk   (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Pos)  /*!< 0x00000800 */
9208 #define DBGMCU_APB4FZ1_DBG_LPTIM4_STOP       DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Msk             /*!< LPTIM4 stop in debug */
9209 #define DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Pos   (12U)
9210 #define DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Msk   (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Pos)  /*!< 0x00001000 */
9211 #define DBGMCU_APB4FZ1_DBG_LPTIM5_STOP       DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Msk             /*!< LPTIM5 stop in debug */
9212 #define DBGMCU_APB4FZ1_DBG_RTC_STOP_Pos      (16U)
9213 #define DBGMCU_APB4FZ1_DBG_RTC_STOP_Msk      (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_STOP_Pos)     /*!< 0x00010000 */
9214 #define DBGMCU_APB4FZ1_DBG_RTC_STOP          DBGMCU_APB4FZ1_DBG_RTC_STOP_Msk                /*!< RTC stop in debug */
9215 #define DBGMCU_APB4FZ1_DBG_IWDG_STOP_Pos     (18U)
9216 #define DBGMCU_APB4FZ1_DBG_IWDG_STOP_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG_STOP_Pos)    /*!< 0x00040000 */
9217 #define DBGMCU_APB4FZ1_DBG_IWDG_STOP         DBGMCU_APB4FZ1_DBG_IWDG_STOP_Msk               /*!< IWDG stop in debug */
9218 
9219 /********************  Bit definition for DBGMCU_APB5FZ1 register  ***************/
9220 #define DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Pos   (4U)
9221 #define DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Msk   (0x1UL << DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Pos)  /*!< 0x00000010 */
9222 #define DBGMCU_APB5FZ1_DBG_GFXTIM_STOP       DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Msk             /*!< GFXTIM stop in debug */
9223 
9224 /********************  Bit definition for DBGMCU_AHB1FZ1 register  ***************/
9225 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Pos    (0U)
9226 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Pos)   /*!< 0x00000001 */
9227 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Msk              /*!< GPDMA1_CH0 suspend in debug */
9228 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Pos    (1U)
9229 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Pos)   /*!< 0x00000002 */
9230 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Msk              /*!< GPDMA1_CH1 suspend in debug */
9231 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Pos    (2U)
9232 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Pos)   /*!< 0x00000004 */
9233 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Msk              /*!< GPDMA1_CH2 suspend in debug */
9234 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Pos    (3U)
9235 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Pos)   /*!< 0x00000008 */
9236 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Msk              /*!< GPDMA1_CH3 suspend in debug */
9237 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Pos    (4U)
9238 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Pos)   /*!< 0x00000010 */
9239 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Msk              /*!< GPDMA1_CH4 suspend in debug */
9240 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Pos    (5U)
9241 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Pos)   /*!< 0x00000020 */
9242 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Msk              /*!< GPDMA1_CH5 suspend in debug */
9243 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Pos    (6U)
9244 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Pos)   /*!< 0x00000040 */
9245 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Msk              /*!< GPDMA1_CH6 suspend in debug */
9246 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Pos    (7U)
9247 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Pos)   /*!< 0x00000080 */
9248 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Msk              /*!< GPDMA1_CH7 suspend in debug */
9249 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Pos    (8U)
9250 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Pos)   /*!< 0x00000100 */
9251 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Msk              /*!< GPDMA1_CH8 suspend in debug */
9252 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Pos    (9U)
9253 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Pos)   /*!< 0x00000200 */
9254 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Msk              /*!< GPDMA1_CH9 suspend in debug */
9255 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Pos   (10U)
9256 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Msk   (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Pos)  /*!< 0x00000400 */
9257 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP       DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Msk             /*!< GPDMA1_CH10 suspend in debug */
9258 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Pos   (11U)
9259 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Msk   (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Pos)  /*!< 0x00000800 */
9260 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP       DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Msk             /*!< GPDMA1_CH11 suspend in debug */
9261 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Pos   (12U)
9262 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Msk   (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Pos)  /*!< 0x00001000 */
9263 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP       DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Msk             /*!< GPDMA1_CH12 suspend in debug */
9264 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Pos   (13U)
9265 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Msk   (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Pos)  /*!< 0x00002000 */
9266 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP       DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Msk             /*!< GPDMA1_CH13 suspend in debug */
9267 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Pos   (14U)
9268 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Msk   (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Pos)  /*!< 0x00004000 */
9269 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP       DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Msk             /*!< GPDMA1_CH14 suspend in debug */
9270 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Pos   (15U)
9271 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Msk   (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Pos)  /*!< 0x00008000 */
9272 #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP       DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Msk             /*!< GPDMA1_CH15 suspend in debug */
9273 
9274 /********************  Bit definition for DBGMCU_AHB5FZ1 register  ***************/
9275 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Pos    (0U)
9276 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Pos)   /*!< 0x00000001 */
9277 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Msk              /*!< HPDMA1_CH0 suspend in debug */
9278 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Pos    (1U)
9279 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Pos)   /*!< 0x00000002 */
9280 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Msk              /*!< HPDMA1_CH1 suspend in debug */
9281 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Pos    (2U)
9282 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Pos)   /*!< 0x00000004 */
9283 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Msk              /*!< HPDMA1_CH2 suspend in debug */
9284 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Pos    (3U)
9285 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Pos)   /*!< 0x00000008 */
9286 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Msk              /*!< HPDMA1_CH3 suspend in debug */
9287 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Pos    (4U)
9288 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Pos)   /*!< 0x00000010 */
9289 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Msk              /*!< HPDMA1_CH4 suspend in debug */
9290 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Pos    (5U)
9291 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Pos)   /*!< 0x00000020 */
9292 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Msk              /*!< HPDMA1_CH5 suspend in debug */
9293 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Pos    (6U)
9294 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Pos)   /*!< 0x00000040 */
9295 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Msk              /*!< HPDMA1_CH6 suspend in debug */
9296 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Pos    (7U)
9297 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Pos)   /*!< 0x00000080 */
9298 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Msk              /*!< HPDMA1_CH7 suspend in debug */
9299 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Pos    (8U)
9300 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Pos)   /*!< 0x00000100 */
9301 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Msk              /*!< HPDMA1_CH8 suspend in debug */
9302 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Pos    (9U)
9303 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Pos)   /*!< 0x00000200 */
9304 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Msk              /*!< HPDMA1_CH9 suspend in debug */
9305 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Pos   (10U)
9306 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Msk   (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Pos)  /*!< 0x00000400 */
9307 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP       DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Msk             /*!< HPDMA1_CH10 suspend in debug */
9308 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Pos   (11U)
9309 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Msk   (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Pos)  /*!< 0x00000800 */
9310 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP       DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Msk             /*!< HPDMA1_CH11 suspend in debug */
9311 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Pos   (12U)
9312 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Msk   (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Pos)  /*!< 0x00001000 */
9313 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP       DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Msk             /*!< HPDMA1_CH12 suspend in debug */
9314 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Pos   (13U)
9315 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Msk   (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Pos)  /*!< 0x00002000 */
9316 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP       DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Msk             /*!< HPDMA1_CH13 suspend in debug */
9317 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Pos   (14U)
9318 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Msk   (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Pos)  /*!< 0x00004000 */
9319 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP       DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Msk             /*!< HPDMA1_CH14 suspend in debug */
9320 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Pos   (15U)
9321 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Msk   (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Pos)  /*!< 0x00008000 */
9322 #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP       DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Msk             /*!< HPDMA1_CH15 suspend in debug */
9323 #define DBGMCU_AHB5FZ1_NPU_DBG_FREEZE_Pos         (16U)
9324 #define DBGMCU_AHB5FZ1_NPU_DBG_FREEZE_Msk         (0x1UL << DBGMCU_AHB5FZ1_NPU_DBG_FREEZE_Pos)        /*!< 0x00010000 */
9325 #define DBGMCU_AHB5FZ1_NPU_DBG_FREEZE             DBGMCU_AHB5FZ1_NPU_DBG_FREEZE_Msk                   /*!< NPU stop in debug mode */
9326 
9327 /********************  Bit definition for DBGMCU_SR register  ***************/
9328 #define DBGMCU_SR_AP0_PRESENT_Pos            (0U)
9329 #define DBGMCU_SR_AP0_PRESENT_Msk            (0x1UL << DBGMCU_SR_AP0_PRESENT_Pos)           /*!< 0x00000001 */
9330 #define DBGMCU_SR_AP0_PRESENT                DBGMCU_SR_AP0_PRESENT_Msk                      /*!< Access point 0 presence */
9331 #define DBGMCU_SR_AP1_PRESENT_Pos            (1U)
9332 #define DBGMCU_SR_AP1_PRESENT_Msk            (0x1UL << DBGMCU_SR_AP1_PRESENT_Pos)           /*!< 0x00000002 */
9333 #define DBGMCU_SR_AP1_PRESENT                DBGMCU_SR_AP1_PRESENT_Msk                      /*!< Access point 1 presence */
9334 #define DBGMCU_SR_AP0_ENABLE_Pos             (16U)
9335 #define DBGMCU_SR_AP0_ENABLE_Msk             (0x1UL << DBGMCU_SR_AP0_ENABLE_Pos)            /*!< 0x00010000 */
9336 #define DBGMCU_SR_AP0_ENABLE                 DBGMCU_SR_AP0_ENABLE_Msk                       /*!< Access point 0 enable */
9337 #define DBGMCU_SR_AP1_ENABLE_Pos             (17U)
9338 #define DBGMCU_SR_AP1_ENABLE_Msk             (0x1UL << DBGMCU_SR_AP1_ENABLE_Pos)            /*!< 0x00020000 */
9339 #define DBGMCU_SR_AP1_ENABLE                 DBGMCU_SR_AP1_ENABLE_Msk                       /*!< Access point 1 enable */
9340 
9341 /******************  Bit definition for DBGMCU_DBG_AUTH_HOST register  **********************/
9342 #define DBGMCU_DBG_AUTH_HOST_MESSAGE_Pos     (0U)
9343 #define DBGMCU_DBG_AUTH_HOST_MESSAGE_Msk     (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_HOST_MESSAGE_Pos) /*!< 0xFFFFFFFF */
9344 #define DBGMCU_DBG_AUTH_HOST_MESSAGE         DBGMCU_DBG_AUTH_HOST_MESSAGE_Msk                   /*!< Message[31:0] */
9345 
9346 /******************  Bit definition for DBGMCU_DBG_AUTH_DEV register  ***********/
9347 #define DBGMCU_DBG_AUTH_DEV_MESSAGE_Pos      (0U)
9348 #define DBGMCU_DBG_AUTH_DEV_MESSAGE_Msk      (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_DEV_MESSAGE_Pos)  /*!< 0xFFFFFFFF */
9349 #define DBGMCU_DBG_AUTH_DEV_MESSAGE          DBGMCU_DBG_AUTH_DEV_MESSAGE_Msk                    /*!< Message[31:0] */
9350 
9351 /********************  Bit definition for DBGMCU_DBG_AUTH_ACK register  ***************/
9352 #define DBGMCU_DBG_AUTH_ACK_HOST_ACK_Pos     (0U)
9353 #define DBGMCU_DBG_AUTH_ACK_HOST_ACK_Msk     (0x1UL << DBGMCU_DBG_AUTH_ACK_HOST_ACK_Pos)    /*!< 0x00000001 */
9354 #define DBGMCU_DBG_AUTH_ACK_HOST_ACK         DBGMCU_DBG_AUTH_ACK_HOST_ACK_Msk               /*!< Access status to DBG_AUTH_HOST register */
9355 #define DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Pos   (1U)
9356 #define DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Msk   (0x1UL << DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Pos)  /*!< 0x00000002 */
9357 #define DBGMCU_DBG_AUTH_ACK_DEVICE_ACK       DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Msk             /*!< Access status to DBG_AUTH_DEV register */
9358 
9359 
9360 /******************************************************************************/
9361 /*                                                                            */
9362 /*                                    DCMI                                    */
9363 /*                                                                            */
9364 /******************************************************************************/
9365 /********************  Bits definition for DCMI_CR register  ******************/
9366 #define DCMI_CR_CAPTURE_Pos                 (0U)
9367 #define DCMI_CR_CAPTURE_Msk                 (0x1UL << DCMI_CR_CAPTURE_Pos)          /*!< 0x00000001 */
9368 #define DCMI_CR_CAPTURE                     DCMI_CR_CAPTURE_Msk
9369 #define DCMI_CR_CM_Pos                      (1U)
9370 #define DCMI_CR_CM_Msk                      (0x1UL << DCMI_CR_CM_Pos)               /*!< 0x00000002 */
9371 #define DCMI_CR_CM                          DCMI_CR_CM_Msk
9372 #define DCMI_CR_CROP_Pos                    (2U)
9373 #define DCMI_CR_CROP_Msk                    (0x1UL << DCMI_CR_CROP_Pos)             /*!< 0x00000004 */
9374 #define DCMI_CR_CROP                        DCMI_CR_CROP_Msk
9375 #define DCMI_CR_JPEG_Pos                    (3U)
9376 #define DCMI_CR_JPEG_Msk                    (0x1UL << DCMI_CR_JPEG_Pos)             /*!< 0x00000008 */
9377 #define DCMI_CR_JPEG                        DCMI_CR_JPEG_Msk
9378 #define DCMI_CR_ESS_Pos                     (4U)
9379 #define DCMI_CR_ESS_Msk                     (0x1UL << DCMI_CR_ESS_Pos)              /*!< 0x00000010 */
9380 #define DCMI_CR_ESS                         DCMI_CR_ESS_Msk
9381 #define DCMI_CR_PCKPOL_Pos                  (5U)
9382 #define DCMI_CR_PCKPOL_Msk                  (0x1UL << DCMI_CR_PCKPOL_Pos)           /*!< 0x00000020 */
9383 #define DCMI_CR_PCKPOL                      DCMI_CR_PCKPOL_Msk
9384 #define DCMI_CR_HSPOL_Pos                   (6U)
9385 #define DCMI_CR_HSPOL_Msk                   (0x1UL << DCMI_CR_HSPOL_Pos)            /*!< 0x00000040 */
9386 #define DCMI_CR_HSPOL                       DCMI_CR_HSPOL_Msk
9387 #define DCMI_CR_VSPOL_Pos                   (7U)
9388 #define DCMI_CR_VSPOL_Msk                   (0x1UL << DCMI_CR_VSPOL_Pos)            /*!< 0x00000080 */
9389 #define DCMI_CR_VSPOL                       DCMI_CR_VSPOL_Msk
9390 #define DCMI_CR_FCRC_Pos                    (8U)
9391 #define DCMI_CR_FCRC_Msk                    (0x3UL << DCMI_CR_FCRC_Pos)             /*!< 0x00000300 */
9392 #define DCMI_CR_FCRC                        DCMI_CR_FCRC_Msk                        /*!< DCMI Frame capture rate control FCRC[1:0] */
9393 #define DCMI_CR_FCRC_0                      (0x1UL << DCMI_CR_FCRC_Pos)             /*!< 0x00000100 */
9394 #define DCMI_CR_FCRC_1                      (0x2UL << DCMI_CR_FCRC_Pos)             /*!< 0x00000200 */
9395 #define DCMI_CR_EDM_Pos                     (10U)
9396 #define DCMI_CR_EDM_Msk                     (0x3UL << DCMI_CR_EDM_Pos)              /*!< 0x00000C00 */
9397 #define DCMI_CR_EDM                         DCMI_CR_EDM_Msk                         /*!< DCMI Extended data mode EDM[1:0] */
9398 #define DCMI_CR_EDM_0                       (0x1UL << DCMI_CR_EDM_Pos)              /*!< 0x00000400 */
9399 #define DCMI_CR_EDM_1                       (0x2UL << DCMI_CR_EDM_Pos)              /*!< 0x00000800 */
9400 #define DCMI_CR_ENABLE_Pos                  (14U)
9401 #define DCMI_CR_ENABLE_Msk                  (0x1UL << DCMI_CR_ENABLE_Pos)           /*!< 0x00004000 */
9402 #define DCMI_CR_ENABLE                      DCMI_CR_ENABLE_Msk
9403 #define DCMI_CR_BSM_Pos                     (16U)
9404 #define DCMI_CR_BSM_Msk                     (0x3UL << DCMI_CR_BSM_Pos)              /*!< 0x00030000 */
9405 #define DCMI_CR_BSM                         DCMI_CR_BSM_Msk
9406 #define DCMI_CR_BSM_0                       (0x1UL << DCMI_CR_BSM_Pos)              /*!< 0x00010000 */
9407 #define DCMI_CR_BSM_1                       (0x2UL << DCMI_CR_BSM_Pos)              /*!< 0x00020000 */
9408 #define DCMI_CR_OEBS_Pos                    (18U)
9409 #define DCMI_CR_OEBS_Msk                    (0x1UL << DCMI_CR_OEBS_Pos)             /*!< 0x00040000 */
9410 #define DCMI_CR_OEBS                        DCMI_CR_OEBS_Msk
9411 #define DCMI_CR_LSM_Pos                     (19U)
9412 #define DCMI_CR_LSM_Msk                     (0x1UL << DCMI_CR_LSM_Pos)              /*!< 0x00080000 */
9413 #define DCMI_CR_LSM                         DCMI_CR_LSM_Msk
9414 #define DCMI_CR_OELS_Pos                    (20U)
9415 #define DCMI_CR_OELS_Msk                    (0x1UL << DCMI_CR_OELS_Pos)             /*!< 0x00100000 */
9416 #define DCMI_CR_OELS                        DCMI_CR_OELS_Msk
9417 #define DCMI_CR_PSDM_Pos                    (31U)
9418 #define DCMI_CR_PSDM_Msk                    (0x0UL << DCMI_CR_PSDM_Pos)             /*!< 0x00000000 */
9419 #define DCMI_CR_PSDM                        DCMI_CR_PSDM_Msk                        /*PSDM: Parallel Synchronous raw Data Mode (PSDM = 0)*/
9420 
9421 /********************  Bits definition for DCMI_SR register  ******************/
9422 #define DCMI_SR_HSYNC_Pos                   (0U)
9423 #define DCMI_SR_HSYNC_Msk                   (0x1UL << DCMI_SR_HSYNC_Pos)            /*!< 0x00000001 */
9424 #define DCMI_SR_HSYNC                       DCMI_SR_HSYNC_Msk
9425 #define DCMI_SR_VSYNC_Pos                   (1U)
9426 #define DCMI_SR_VSYNC_Msk                   (0x1UL << DCMI_SR_VSYNC_Pos)            /*!< 0x00000002 */
9427 #define DCMI_SR_VSYNC                       DCMI_SR_VSYNC_Msk
9428 #define DCMI_SR_FNE_Pos                     (2U)
9429 #define DCMI_SR_FNE_Msk                     (0x1UL << DCMI_SR_FNE_Pos)              /*!< 0x00000004 */
9430 #define DCMI_SR_FNE                         DCMI_SR_FNE_Msk
9431 
9432 /********************  Bits definition for DCMI_RIS register   ****************/
9433 #define DCMI_RIS_FRAME_RIS_Pos              (0U)
9434 #define DCMI_RIS_FRAME_RIS_Msk              (0x1UL << DCMI_RIS_FRAME_RIS_Pos)       /*!< 0x00000001 */
9435 #define DCMI_RIS_FRAME_RIS                  DCMI_RIS_FRAME_RIS_Msk
9436 #define DCMI_RIS_OVR_RIS_Pos                (1U)
9437 #define DCMI_RIS_OVR_RIS_Msk                (0x1UL << DCMI_RIS_OVR_RIS_Pos)         /*!< 0x00000002 */
9438 #define DCMI_RIS_OVR_RIS                    DCMI_RIS_OVR_RIS_Msk
9439 #define DCMI_RIS_ERR_RIS_Pos                (2U)
9440 #define DCMI_RIS_ERR_RIS_Msk                (0x1UL << DCMI_RIS_ERR_RIS_Pos)         /*!< 0x00000004 */
9441 #define DCMI_RIS_ERR_RIS                    DCMI_RIS_ERR_RIS_Msk
9442 #define DCMI_RIS_VSYNC_RIS_Pos              (3U)
9443 #define DCMI_RIS_VSYNC_RIS_Msk              (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)       /*!< 0x00000008 */
9444 #define DCMI_RIS_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS_Msk
9445 #define DCMI_RIS_LINE_RIS_Pos               (4U)
9446 #define DCMI_RIS_LINE_RIS_Msk               (0x1UL << DCMI_RIS_LINE_RIS_Pos)        /*!< 0x00000010 */
9447 #define DCMI_RIS_LINE_RIS                   DCMI_RIS_LINE_RIS_Msk
9448 
9449 /********************  Bits definition for DCMI_IER register  *****************/
9450 #define DCMI_IER_FRAME_IE_Pos               (0U)
9451 #define DCMI_IER_FRAME_IE_Msk               (0x1UL << DCMI_IER_FRAME_IE_Pos)        /*!< 0x00000001 */
9452 #define DCMI_IER_FRAME_IE                   DCMI_IER_FRAME_IE_Msk
9453 #define DCMI_IER_OVR_IE_Pos                 (1U)
9454 #define DCMI_IER_OVR_IE_Msk                 (0x1UL << DCMI_IER_OVR_IE_Pos)          /*!< 0x00000002 */
9455 #define DCMI_IER_OVR_IE                     DCMI_IER_OVR_IE_Msk
9456 #define DCMI_IER_ERR_IE_Pos                 (2U)
9457 #define DCMI_IER_ERR_IE_Msk                 (0x1UL << DCMI_IER_ERR_IE_Pos)          /*!< 0x00000004 */
9458 #define DCMI_IER_ERR_IE                     DCMI_IER_ERR_IE_Msk
9459 #define DCMI_IER_VSYNC_IE_Pos               (3U)
9460 #define DCMI_IER_VSYNC_IE_Msk               (0x1UL << DCMI_IER_VSYNC_IE_Pos)        /*!< 0x00000008 */
9461 #define DCMI_IER_VSYNC_IE                   DCMI_IER_VSYNC_IE_Msk
9462 #define DCMI_IER_LINE_IE_Pos                (4U)
9463 #define DCMI_IER_LINE_IE_Msk                (0x1UL << DCMI_IER_LINE_IE_Pos)         /*!< 0x00000010 */
9464 #define DCMI_IER_LINE_IE                    DCMI_IER_LINE_IE_Msk
9465 
9466 /********************  Bits definition for DCMI_MIS register  *****************/
9467 #define DCMI_MIS_FRAME_MIS_Pos              (0U)
9468 #define DCMI_MIS_FRAME_MIS_Msk              (0x1UL << DCMI_MIS_FRAME_MIS_Pos)       /*!< 0x00000001 */
9469 #define DCMI_MIS_FRAME_MIS                  DCMI_MIS_FRAME_MIS_Msk
9470 #define DCMI_MIS_OVR_MIS_Pos                (1U)
9471 #define DCMI_MIS_OVR_MIS_Msk                (0x1UL << DCMI_MIS_OVR_MIS_Pos)         /*!< 0x00000002 */
9472 #define DCMI_MIS_OVR_MIS                    DCMI_MIS_OVR_MIS_Msk
9473 #define DCMI_MIS_ERR_MIS_Pos                (2U)
9474 #define DCMI_MIS_ERR_MIS_Msk                (0x1UL << DCMI_MIS_ERR_MIS_Pos)         /*!< 0x00000004 */
9475 #define DCMI_MIS_ERR_MIS                    DCMI_MIS_ERR_MIS_Msk
9476 #define DCMI_MIS_VSYNC_MIS_Pos              (3U)
9477 #define DCMI_MIS_VSYNC_MIS_Msk              (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)       /*!< 0x00000008 */
9478 #define DCMI_MIS_VSYNC_MIS                  DCMI_MIS_VSYNC_MIS_Msk
9479 #define DCMI_MIS_LINE_MIS_Pos               (4U)
9480 #define DCMI_MIS_LINE_MIS_Msk               (0x1UL << DCMI_MIS_LINE_MIS_Pos)        /*!< 0x00000010 */
9481 #define DCMI_MIS_LINE_MIS                   DCMI_MIS_LINE_MIS_Msk
9482 
9483 /********************  Bits definition for DCMI_ICR register  *****************/
9484 #define DCMI_ICR_FRAME_ISC_Pos              (0U)
9485 #define DCMI_ICR_FRAME_ISC_Msk              (0x1UL << DCMI_ICR_FRAME_ISC_Pos)       /*!< 0x00000001 */
9486 #define DCMI_ICR_FRAME_ISC                  DCMI_ICR_FRAME_ISC_Msk
9487 #define DCMI_ICR_OVR_ISC_Pos                (1U)
9488 #define DCMI_ICR_OVR_ISC_Msk                (0x1UL << DCMI_ICR_OVR_ISC_Pos)         /*!< 0x00000002 */
9489 #define DCMI_ICR_OVR_ISC                    DCMI_ICR_OVR_ISC_Msk
9490 #define DCMI_ICR_ERR_ISC_Pos                (2U)
9491 #define DCMI_ICR_ERR_ISC_Msk                (0x1UL << DCMI_ICR_ERR_ISC_Pos)         /*!< 0x00000004 */
9492 #define DCMI_ICR_ERR_ISC                    DCMI_ICR_ERR_ISC_Msk
9493 #define DCMI_ICR_VSYNC_ISC_Pos              (3U)
9494 #define DCMI_ICR_VSYNC_ISC_Msk              (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)       /*!< 0x00000008 */
9495 #define DCMI_ICR_VSYNC_ISC                  DCMI_ICR_VSYNC_ISC_Msk
9496 #define DCMI_ICR_LINE_ISC_Pos               (4U)
9497 #define DCMI_ICR_LINE_ISC_Msk               (0x1UL << DCMI_ICR_LINE_ISC_Pos)        /*!< 0x00000010 */
9498 #define DCMI_ICR_LINE_ISC                   DCMI_ICR_LINE_ISC_Msk
9499 
9500 /********************  Bits definition for DCMI_ESCR register  ******************/
9501 #define DCMI_ESCR_FSC_Pos                   (0U)
9502 #define DCMI_ESCR_FSC_Msk                   (0xFFUL << DCMI_ESCR_FSC_Pos)           /*!< 0x000000FF */
9503 #define DCMI_ESCR_FSC                       DCMI_ESCR_FSC_Msk
9504 #define DCMI_ESCR_LSC_Pos                   (8U)
9505 #define DCMI_ESCR_LSC_Msk                   (0xFFUL << DCMI_ESCR_LSC_Pos)           /*!< 0x0000FF00 */
9506 #define DCMI_ESCR_LSC                       DCMI_ESCR_LSC_Msk
9507 #define DCMI_ESCR_LEC_Pos                   (16U)
9508 #define DCMI_ESCR_LEC_Msk                   (0xFFUL << DCMI_ESCR_LEC_Pos)           /*!< 0x00FF0000 */
9509 #define DCMI_ESCR_LEC                       DCMI_ESCR_LEC_Msk
9510 #define DCMI_ESCR_FEC_Pos                   (24U)
9511 #define DCMI_ESCR_FEC_Msk                   (0xFFUL << DCMI_ESCR_FEC_Pos)           /*!< 0xFF000000 */
9512 #define DCMI_ESCR_FEC                       DCMI_ESCR_FEC_Msk
9513 
9514 /********************  Bits definition for DCMI_ESUR register  ******************/
9515 #define DCMI_ESUR_FSU_Pos                   (0U)
9516 #define DCMI_ESUR_FSU_Msk                   (0xFFUL << DCMI_ESUR_FSU_Pos)           /*!< 0x000000FF */
9517 #define DCMI_ESUR_FSU                       DCMI_ESUR_FSU_Msk
9518 #define DCMI_ESUR_LSU_Pos                   (8U)
9519 #define DCMI_ESUR_LSU_Msk                   (0xFFUL << DCMI_ESUR_LSU_Pos)           /*!< 0x0000FF00 */
9520 #define DCMI_ESUR_LSU                       DCMI_ESUR_LSU_Msk
9521 #define DCMI_ESUR_LEU_Pos                   (16U)
9522 #define DCMI_ESUR_LEU_Msk                   (0xFFUL << DCMI_ESUR_LEU_Pos)           /*!< 0x00FF0000 */
9523 #define DCMI_ESUR_LEU                       DCMI_ESUR_LEU_Msk
9524 #define DCMI_ESUR_FEU_Pos                   (24U)
9525 #define DCMI_ESUR_FEU_Msk                   (0xFFUL << DCMI_ESUR_FEU_Pos)           /*!< 0xFF000000 */
9526 #define DCMI_ESUR_FEU                       DCMI_ESUR_FEU_Msk
9527 
9528 /********************  Bits definition for DCMI_CWSTRT register  ******************/
9529 #define DCMI_CWSTRT_HOFFCNT_Pos             (0U)
9530 #define DCMI_CWSTRT_HOFFCNT_Msk             (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)   /*!< 0x00003FFF */
9531 #define DCMI_CWSTRT_HOFFCNT                 DCMI_CWSTRT_HOFFCNT_Msk
9532 #define DCMI_CWSTRT_VST_Pos                 (16U)
9533 #define DCMI_CWSTRT_VST_Msk                 (0x1FFFUL << DCMI_CWSTRT_VST_Pos)       /*!< 0x1FFF0000 */
9534 #define DCMI_CWSTRT_VST                     DCMI_CWSTRT_VST_Msk
9535 
9536 /********************  Bits definition for DCMI_CWSIZE register  ******************/
9537 #define DCMI_CWSIZE_CAPCNT_Pos              (0U)
9538 #define DCMI_CWSIZE_CAPCNT_Msk              (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)    /*!< 0x00003FFF */
9539 #define DCMI_CWSIZE_CAPCNT                  DCMI_CWSIZE_CAPCNT_Msk
9540 #define DCMI_CWSIZE_VLINE_Pos               (16U)
9541 #define DCMI_CWSIZE_VLINE_Msk               (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)     /*!< 0x3FFF0000 */
9542 #define DCMI_CWSIZE_VLINE                   DCMI_CWSIZE_VLINE_Msk
9543 
9544 /********************  Bits definition for DCMI_DR register  ******************/
9545 #define DCMI_DR_BYTE0_Pos                   (0U)
9546 #define DCMI_DR_BYTE0_Msk                   (0xFFUL << DCMI_DR_BYTE0_Pos)           /*!< 0x000000FF */
9547 #define DCMI_DR_BYTE0                       DCMI_DR_BYTE0_Msk
9548 #define DCMI_DR_BYTE1_Pos                   (8U)
9549 #define DCMI_DR_BYTE1_Msk                   (0xFFUL << DCMI_DR_BYTE1_Pos)           /*!< 0x0000FF00 */
9550 #define DCMI_DR_BYTE1                       DCMI_DR_BYTE1_Msk
9551 #define DCMI_DR_BYTE2_Pos                   (16U)
9552 #define DCMI_DR_BYTE2_Msk                   (0xFFUL << DCMI_DR_BYTE2_Pos)           /*!< 0x00FF0000 */
9553 #define DCMI_DR_BYTE2                       DCMI_DR_BYTE2_Msk
9554 #define DCMI_DR_BYTE3_Pos                   (24U)
9555 #define DCMI_DR_BYTE3_Msk                   (0xFFUL << DCMI_DR_BYTE3_Pos)           /*!< 0xFF000000 */
9556 #define DCMI_DR_BYTE3                       DCMI_DR_BYTE3_Msk
9557 
9558 
9559 /******************************************************************************/
9560 /*                                                                            */
9561 /*                                   DCMIPP                                   */
9562 /*                                                                            */
9563 /******************************************************************************/
9564 /*****************  Bit definition for DCMIPP_IPGR1 register  *****************/
9565 #define DCMIPP_IPGR1_MEMORYPAGE_Pos         (0U)
9566 #define DCMIPP_IPGR1_MEMORYPAGE_Msk         (0x7UL << DCMIPP_IPGR1_MEMORYPAGE_Pos)           /*!< 0x00000007 */
9567 #define DCMIPP_IPGR1_MEMORYPAGE             DCMIPP_IPGR1_MEMORYPAGE_Msk                     /*!< Memory page size, as power of 2 of 64-byte units: */
9568 #define DCMIPP_IPGR1_QOS_MODE_Pos           (24U)
9569 #define DCMIPP_IPGR1_QOS_MODE_Msk           (0x1UL << DCMIPP_IPGR1_QOS_MODE_Pos)             /*!< 0x01000000 */
9570 #define DCMIPP_IPGR1_QOS_MODE               DCMIPP_IPGR1_QOS_MODE_Msk                       /*!< Quality of service */
9571 
9572 /*****************  Bit definition for DCMIPP_IPGR2 register  *****************/
9573 #define DCMIPP_IPGR2_PSTART_Pos             (0U)
9574 #define DCMIPP_IPGR2_PSTART_Msk             (0x1UL << DCMIPP_IPGR2_PSTART_Pos)               /*!< 0x00000001 */
9575 #define DCMIPP_IPGR2_PSTART                 DCMIPP_IPGR2_PSTART_Msk                         /*!< Request to lock the IP-Plug, to allow reconfiguration */
9576 
9577 /*****************  Bit definition for DCMIPP_IPGR3 register  *****************/
9578 #define DCMIPP_IPGR3_IDLE_Pos               (0U)
9579 #define DCMIPP_IPGR3_IDLE_Msk               (0x1UL << DCMIPP_IPGR3_IDLE_Pos)                 /*!< 0x00000001 */
9580 #define DCMIPP_IPGR3_IDLE                   DCMIPP_IPGR3_IDLE_Msk                           /*!< Status of IP-Plug */
9581 
9582 /*****************  Bit definition for DCMIPP_IPGR8 register  *****************/
9583 #define DCMIPP_IPGR8_DID_Pos                (0U)
9584 #define DCMIPP_IPGR8_DID_Msk                (0x3FUL << DCMIPP_IPGR8_DID_Pos)                 /*!< 0x0000003F */
9585 #define DCMIPP_IPGR8_DID                    DCMIPP_IPGR8_DID_Msk                            /*!< Division identifier (0x14) */
9586 #define DCMIPP_IPGR8_REVID_Pos              (8U)
9587 #define DCMIPP_IPGR8_REVID_Msk              (0x1FUL << DCMIPP_IPGR8_REVID_Pos)               /*!< 0x00001F00 */
9588 #define DCMIPP_IPGR8_REVID                  DCMIPP_IPGR8_REVID_Msk                          /*!< Revision identifier (0x03) */
9589 #define DCMIPP_IPGR8_ARCHIID_Pos            (16U)
9590 #define DCMIPP_IPGR8_ARCHIID_Msk            (0x1FUL << DCMIPP_IPGR8_ARCHIID_Pos)             /*!< 0x001F0000 */
9591 #define DCMIPP_IPGR8_ARCHIID                DCMIPP_IPGR8_ARCHIID_Msk                        /*!< Architecture identifier (0x04) */
9592 #define DCMIPP_IPGR8_IPPID_Pos              (24U)
9593 #define DCMIPP_IPGR8_IPPID_Msk              (0xFFUL << DCMIPP_IPGR8_IPPID_Pos)               /*!< 0xFF000000 */
9594 #define DCMIPP_IPGR8_IPPID                  DCMIPP_IPGR8_IPPID_Msk                          /*!< IP identifier (0xAA) */
9595 
9596 /****************  Bit definition for DCMIPP_IPC1R1 register  *****************/
9597 #define DCMIPP_IPC1R1_TRAFFIC_Pos           (0U)
9598 #define DCMIPP_IPC1R1_TRAFFIC_Msk           (0x7UL << DCMIPP_IPC1R1_TRAFFIC_Pos)             /*!< 0x00000007 */
9599 #define DCMIPP_IPC1R1_TRAFFIC               DCMIPP_IPC1R1_TRAFFIC_Msk                       /*!< Burst size as power of 2 of 8 bytes units */
9600 #define DCMIPP_IPC1R1_OTR_Pos               (8U)
9601 #define DCMIPP_IPC1R1_OTR_Msk               (0xFUL << DCMIPP_IPC1R1_OTR_Pos)                 /*!< 0x00000F00 */
9602 #define DCMIPP_IPC1R1_OTR                   DCMIPP_IPC1R1_OTR_Msk                           /*!< max outstanding transactions: */
9603 
9604 /****************  Bit definition for DCMIPP_IPC1R2 register  *****************/
9605 #define DCMIPP_IPC1R2_WLRU_Pos              (16U)
9606 #define DCMIPP_IPC1R2_WLRU_Msk              (0xFUL << DCMIPP_IPC1R2_WLRU_Pos)                /*!< 0x000F0000 */
9607 #define DCMIPP_IPC1R2_WLRU                  DCMIPP_IPC1R2_WLRU_Msk                          /*!< Ratio for WLRU[3:0] arbitration: */
9608 
9609 /****************  Bit definition for DCMIPP_IPC1R3 register  *****************/
9610 #define DCMIPP_IPC1R3_DPREGSTART_Pos        (0U)
9611 #define DCMIPP_IPC1R3_DPREGSTART_Msk        (0x3FFUL << DCMIPP_IPC1R3_DPREGSTART_Pos)        /*!< 0x000003FF */
9612 #define DCMIPP_IPC1R3_DPREGSTART            DCMIPP_IPC1R3_DPREGSTART_Msk                    /*!< Start word (AXI width = 64 bits) of the FIFO of this client */
9613 #define DCMIPP_IPC1R3_DPREGEND_Pos          (16U)
9614 #define DCMIPP_IPC1R3_DPREGEND_Msk          (0x3FFUL << DCMIPP_IPC1R3_DPREGEND_Pos)          /*!< 0x03FF0000 */
9615 #define DCMIPP_IPC1R3_DPREGEND              DCMIPP_IPC1R3_DPREGEND_Msk                      /*!< End word (AXI width = 64 bits) of the FIFO of this client */
9616 
9617 /****************  Bit definition for DCMIPP_IPC2R1 register  *****************/
9618 #define DCMIPP_IPC2R1_TRAFFIC_Pos           (0U)
9619 #define DCMIPP_IPC2R1_TRAFFIC_Msk           (0x7UL << DCMIPP_IPC2R1_TRAFFIC_Pos)             /*!< 0x00000007 */
9620 #define DCMIPP_IPC2R1_TRAFFIC               DCMIPP_IPC2R1_TRAFFIC_Msk                       /*!< Burst size as power of 2 of 8 bytes units */
9621 #define DCMIPP_IPC2R1_OTR_Pos               (8U)
9622 #define DCMIPP_IPC2R1_OTR_Msk               (0xFUL << DCMIPP_IPC2R1_OTR_Pos)                 /*!< 0x00000F00 */
9623 #define DCMIPP_IPC2R1_OTR                   DCMIPP_IPC2R1_OTR_Msk                           /*!< max outstanding transactions: */
9624 
9625 /****************  Bit definition for DCMIPP_IPC2R2 register  *****************/
9626 #define DCMIPP_IPC2R2_WLRU_Pos              (16U)
9627 #define DCMIPP_IPC2R2_WLRU_Msk              (0xFUL << DCMIPP_IPC2R2_WLRU_Pos)                /*!< 0x000F0000 */
9628 #define DCMIPP_IPC2R2_WLRU                  DCMIPP_IPC2R2_WLRU_Msk                          /*!< Ratio for WLRU[3:0] arbitration: */
9629 
9630 /****************  Bit definition for DCMIPP_IPC2R3 register  *****************/
9631 #define DCMIPP_IPC2R3_DPREGSTART_Pos        (0U)
9632 #define DCMIPP_IPC2R3_DPREGSTART_Msk        (0x3FFUL << DCMIPP_IPC2R3_DPREGSTART_Pos)        /*!< 0x000003FF */
9633 #define DCMIPP_IPC2R3_DPREGSTART            DCMIPP_IPC2R3_DPREGSTART_Msk                    /*!< Start word (AXI width = 64 bits) of the FIFO of this client */
9634 #define DCMIPP_IPC2R3_DPREGEND_Pos          (16U)
9635 #define DCMIPP_IPC2R3_DPREGEND_Msk          (0x3FFUL << DCMIPP_IPC2R3_DPREGEND_Pos)          /*!< 0x03FF0000 */
9636 #define DCMIPP_IPC2R3_DPREGEND              DCMIPP_IPC2R3_DPREGEND_Msk                      /*!< End word (AXI width = 64 bits) of the FIFO of this client */
9637 
9638 /****************  Bit definition for DCMIPP_IPC3R1 register  *****************/
9639 #define DCMIPP_IPC3R1_TRAFFIC_Pos           (0U)
9640 #define DCMIPP_IPC3R1_TRAFFIC_Msk           (0x7UL << DCMIPP_IPC3R1_TRAFFIC_Pos)             /*!< 0x00000007 */
9641 #define DCMIPP_IPC3R1_TRAFFIC               DCMIPP_IPC3R1_TRAFFIC_Msk                       /*!< Burst size as power of 2 of 8 bytes units */
9642 #define DCMIPP_IPC3R1_OTR_Pos               (8U)
9643 #define DCMIPP_IPC3R1_OTR_Msk               (0xFUL << DCMIPP_IPC3R1_OTR_Pos)                 /*!< 0x00000F00 */
9644 #define DCMIPP_IPC3R1_OTR                   DCMIPP_IPC3R1_OTR_Msk                           /*!< max outstanding transactions: */
9645 
9646 /****************  Bit definition for DCMIPP_IPC3R2 register  *****************/
9647 #define DCMIPP_IPC3R2_WLRU_Pos              (16U)
9648 #define DCMIPP_IPC3R2_WLRU_Msk              (0xFUL << DCMIPP_IPC3R2_WLRU_Pos)                /*!< 0x000F0000 */
9649 #define DCMIPP_IPC3R2_WLRU                  DCMIPP_IPC3R2_WLRU_Msk                          /*!< Ratio for WLRU[3:0] arbitration: */
9650 
9651 /****************  Bit definition for DCMIPP_IPC3R3 register  *****************/
9652 #define DCMIPP_IPC3R3_DPREGSTART_Pos        (0U)
9653 #define DCMIPP_IPC3R3_DPREGSTART_Msk        (0x3FFUL << DCMIPP_IPC3R3_DPREGSTART_Pos)        /*!< 0x000003FF */
9654 #define DCMIPP_IPC3R3_DPREGSTART            DCMIPP_IPC3R3_DPREGSTART_Msk                    /*!< Start word (AXI width = 64 bits) of the FIFO of this client */
9655 #define DCMIPP_IPC3R3_DPREGEND_Pos          (16U)
9656 #define DCMIPP_IPC3R3_DPREGEND_Msk          (0x3FFUL << DCMIPP_IPC3R3_DPREGEND_Pos)          /*!< 0x03FF0000 */
9657 #define DCMIPP_IPC3R3_DPREGEND              DCMIPP_IPC3R3_DPREGEND_Msk                      /*!< End word (AXI width = 64 bits) of the FIFO of this client */
9658 
9659 /****************  Bit definition for DCMIPP_IPC4R1 register  *****************/
9660 #define DCMIPP_IPC4R1_TRAFFIC_Pos           (0U)
9661 #define DCMIPP_IPC4R1_TRAFFIC_Msk           (0x7UL << DCMIPP_IPC4R1_TRAFFIC_Pos)             /*!< 0x00000007 */
9662 #define DCMIPP_IPC4R1_TRAFFIC               DCMIPP_IPC4R1_TRAFFIC_Msk                       /*!< Burst size as power of 2 of 8 bytes units */
9663 #define DCMIPP_IPC4R1_OTR_Pos               (8U)
9664 #define DCMIPP_IPC4R1_OTR_Msk               (0xFUL << DCMIPP_IPC4R1_OTR_Pos)                 /*!< 0x00000F00 */
9665 #define DCMIPP_IPC4R1_OTR                   DCMIPP_IPC4R1_OTR_Msk                           /*!< max outstanding transactions: */
9666 
9667 /****************  Bit definition for DCMIPP_IPC4R2 register  *****************/
9668 #define DCMIPP_IPC4R2_WLRU_Pos              (16U)
9669 #define DCMIPP_IPC4R2_WLRU_Msk              (0xFUL << DCMIPP_IPC4R2_WLRU_Pos)                /*!< 0x000F0000 */
9670 #define DCMIPP_IPC4R2_WLRU                  DCMIPP_IPC4R2_WLRU_Msk                          /*!< Ratio for WLRU[3:0] arbitration: */
9671 
9672 /****************  Bit definition for DCMIPP_IPC4R3 register  *****************/
9673 #define DCMIPP_IPC4R3_DPREGSTART_Pos        (0U)
9674 #define DCMIPP_IPC4R3_DPREGSTART_Msk        (0x3FFUL << DCMIPP_IPC4R3_DPREGSTART_Pos)        /*!< 0x000003FF */
9675 #define DCMIPP_IPC4R3_DPREGSTART            DCMIPP_IPC4R3_DPREGSTART_Msk                    /*!< Start word (AXI width = 64 bits) of the FIFO of this client */
9676 #define DCMIPP_IPC4R3_DPREGEND_Pos          (16U)
9677 #define DCMIPP_IPC4R3_DPREGEND_Msk          (0x3FFUL << DCMIPP_IPC4R3_DPREGEND_Pos)          /*!< 0x03FF0000 */
9678 #define DCMIPP_IPC4R3_DPREGEND              DCMIPP_IPC4R3_DPREGEND_Msk                      /*!< End word (AXI width = 64 bits) of the FIFO of this client */
9679 
9680 /****************  Bit definition for DCMIPP_IPC5R1 register  *****************/
9681 #define DCMIPP_IPC5R1_TRAFFIC_Pos           (0U)
9682 #define DCMIPP_IPC5R1_TRAFFIC_Msk           (0x7UL << DCMIPP_IPC5R1_TRAFFIC_Pos)             /*!< 0x00000007 */
9683 #define DCMIPP_IPC5R1_TRAFFIC               DCMIPP_IPC5R1_TRAFFIC_Msk                       /*!< Burst size as power of 2 of 8 bytes units */
9684 #define DCMIPP_IPC5R1_OTR_Pos               (8U)
9685 #define DCMIPP_IPC5R1_OTR_Msk               (0xFUL << DCMIPP_IPC5R1_OTR_Pos)                 /*!< 0x00000F00 */
9686 #define DCMIPP_IPC5R1_OTR                   DCMIPP_IPC5R1_OTR_Msk                           /*!< max outstanding transactions: */
9687 
9688 /****************  Bit definition for DCMIPP_IPC5R2 register  *****************/
9689 #define DCMIPP_IPC5R2_WLRU_Pos              (16U)
9690 #define DCMIPP_IPC5R2_WLRU_Msk              (0xFUL << DCMIPP_IPC5R2_WLRU_Pos)                /*!< 0x000F0000 */
9691 #define DCMIPP_IPC5R2_WLRU                  DCMIPP_IPC5R2_WLRU_Msk                          /*!< Ratio for WLRU[3:0] arbitration: */
9692 
9693 /****************  Bit definition for DCMIPP_IPC5R3 register  *****************/
9694 #define DCMIPP_IPC5R3_DPREGSTART_Pos        (0U)
9695 #define DCMIPP_IPC5R3_DPREGSTART_Msk        (0x3FFUL << DCMIPP_IPC5R3_DPREGSTART_Pos)        /*!< 0x000003FF */
9696 #define DCMIPP_IPC5R3_DPREGSTART            DCMIPP_IPC5R3_DPREGSTART_Msk                    /*!< Start word (AXI width = 64 bits) of the FIFO of this client */
9697 #define DCMIPP_IPC5R3_DPREGEND_Pos          (16U)
9698 #define DCMIPP_IPC5R3_DPREGEND_Msk          (0x3FFUL << DCMIPP_IPC5R3_DPREGEND_Pos)          /*!< 0x03FF0000 */
9699 #define DCMIPP_IPC5R3_DPREGEND              DCMIPP_IPC5R3_DPREGEND_Msk                      /*!< End word (AXI width = 64 bits) of the FIFO of this client */
9700 
9701 /***************  Bit definition for DCMIPP_PRHWCFGR register  ****************/
9702 
9703 /*****************  Bit definition for DCMIPP_PRCR register  ******************/
9704 #define DCMIPP_PRCR_ESS_Pos                 (4U)
9705 #define DCMIPP_PRCR_ESS_Msk                 (0x1UL << DCMIPP_PRCR_ESS_Pos)                   /*!< 0x00000010 */
9706 #define DCMIPP_PRCR_ESS                     DCMIPP_PRCR_ESS_Msk                             /*!< Embedded synchronization select */
9707 #define DCMIPP_PRCR_PCKPOL_Pos              (5U)
9708 #define DCMIPP_PRCR_PCKPOL_Msk              (0x1UL << DCMIPP_PRCR_PCKPOL_Pos)                /*!< 0x00000020 */
9709 #define DCMIPP_PRCR_PCKPOL                  DCMIPP_PRCR_PCKPOL_Msk                          /*!< Pixel clock polarity */
9710 #define DCMIPP_PRCR_HSPOL_Pos               (6U)
9711 #define DCMIPP_PRCR_HSPOL_Msk               (0x1UL << DCMIPP_PRCR_HSPOL_Pos)                 /*!< 0x00000040 */
9712 #define DCMIPP_PRCR_HSPOL                   DCMIPP_PRCR_HSPOL_Msk                           /*!< Horizontal synchronization polarity */
9713 #define DCMIPP_PRCR_VSPOL_Pos               (7U)
9714 #define DCMIPP_PRCR_VSPOL_Msk               (0x1UL << DCMIPP_PRCR_VSPOL_Pos)                 /*!< 0x00000080 */
9715 #define DCMIPP_PRCR_VSPOL                   DCMIPP_PRCR_VSPOL_Msk                           /*!< Vertical synchronization polarity */
9716 #define DCMIPP_PRCR_EDM_Pos                 (10U)
9717 #define DCMIPP_PRCR_EDM_Msk                 (0x7UL << DCMIPP_PRCR_EDM_Pos)                   /*!< 0x00001C00 */
9718 #define DCMIPP_PRCR_EDM                     DCMIPP_PRCR_EDM_Msk                             /*!< Extended data mode */
9719 #define DCMIPP_PRCR_ENABLE_Pos              (14U)
9720 #define DCMIPP_PRCR_ENABLE_Msk              (0x1UL << DCMIPP_PRCR_ENABLE_Pos)                /*!< 0x00004000 */
9721 #define DCMIPP_PRCR_ENABLE                  DCMIPP_PRCR_ENABLE_Msk                          /*!< Parallel interface enable */
9722 #define DCMIPP_PRCR_FORMAT_Pos              (16U)
9723 #define DCMIPP_PRCR_FORMAT_Msk              (0xFFUL << DCMIPP_PRCR_FORMAT_Pos)               /*!< 0x00FF0000 */
9724 #define DCMIPP_PRCR_FORMAT                  DCMIPP_PRCR_FORMAT_Msk                          /*!< Other values: Data is captured and output as-is through the data/dump pipeline only (e */
9725 #define DCMIPP_PRCR_SWAPCYCLES_Pos          (25U)
9726 #define DCMIPP_PRCR_SWAPCYCLES_Msk          (0x1UL << DCMIPP_PRCR_SWAPCYCLES_Pos)            /*!< 0x02000000 */
9727 #define DCMIPP_PRCR_SWAPCYCLES              DCMIPP_PRCR_SWAPCYCLES_Msk                      /*!< Swap data from cycle 0 vs */
9728 #define DCMIPP_PRCR_SWAPBITS_Pos            (26U)
9729 #define DCMIPP_PRCR_SWAPBITS_Msk            (0x1UL << DCMIPP_PRCR_SWAPBITS_Pos)              /*!< 0x04000000 */
9730 #define DCMIPP_PRCR_SWAPBITS                DCMIPP_PRCR_SWAPBITS_Msk                        /*!< Swap LSB vs */
9731 
9732 /****************  Bit definition for DCMIPP_PRESCR register  *****************/
9733 #define DCMIPP_PRESCR_FSC_Pos               (0U)
9734 #define DCMIPP_PRESCR_FSC_Msk               (0xFFUL << DCMIPP_PRESCR_FSC_Pos)                /*!< 0x000000FF */
9735 #define DCMIPP_PRESCR_FSC                   DCMIPP_PRESCR_FSC_Msk                           /*!< Frame start delimiter code */
9736 #define DCMIPP_PRESCR_LSC_Pos               (8U)
9737 #define DCMIPP_PRESCR_LSC_Msk               (0xFFUL << DCMIPP_PRESCR_LSC_Pos)                /*!< 0x0000FF00 */
9738 #define DCMIPP_PRESCR_LSC                   DCMIPP_PRESCR_LSC_Msk                           /*!< Line start delimiter code */
9739 #define DCMIPP_PRESCR_LEC_Pos               (16U)
9740 #define DCMIPP_PRESCR_LEC_Msk               (0xFFUL << DCMIPP_PRESCR_LEC_Pos)                /*!< 0x00FF0000 */
9741 #define DCMIPP_PRESCR_LEC                   DCMIPP_PRESCR_LEC_Msk                           /*!< Line end delimiter code */
9742 #define DCMIPP_PRESCR_FEC_Pos               (24U)
9743 #define DCMIPP_PRESCR_FEC_Msk               (0xFFUL << DCMIPP_PRESCR_FEC_Pos)                /*!< 0xFF000000 */
9744 #define DCMIPP_PRESCR_FEC                   DCMIPP_PRESCR_FEC_Msk                           /*!< Frame end delimiter code */
9745 
9746 /****************  Bit definition for DCMIPP_PRESUR register  *****************/
9747 #define DCMIPP_PRESUR_FSU_Pos               (0U)
9748 #define DCMIPP_PRESUR_FSU_Msk               (0xFFUL << DCMIPP_PRESUR_FSU_Pos)                /*!< 0x000000FF */
9749 #define DCMIPP_PRESUR_FSU                   DCMIPP_PRESUR_FSU_Msk                           /*!< Frame start delimiter unmask */
9750 #define DCMIPP_PRESUR_LSU_Pos               (8U)
9751 #define DCMIPP_PRESUR_LSU_Msk               (0xFFUL << DCMIPP_PRESUR_LSU_Pos)                /*!< 0x0000FF00 */
9752 #define DCMIPP_PRESUR_LSU                   DCMIPP_PRESUR_LSU_Msk                           /*!< Line start delimiter unmask */
9753 #define DCMIPP_PRESUR_LEU_Pos               (16U)
9754 #define DCMIPP_PRESUR_LEU_Msk               (0xFFUL << DCMIPP_PRESUR_LEU_Pos)                /*!< 0x00FF0000 */
9755 #define DCMIPP_PRESUR_LEU                   DCMIPP_PRESUR_LEU_Msk                           /*!< Line end delimiter unmask */
9756 #define DCMIPP_PRESUR_FEU_Pos               (24U)
9757 #define DCMIPP_PRESUR_FEU_Msk               (0xFFUL << DCMIPP_PRESUR_FEU_Pos)                /*!< 0xFF000000 */
9758 #define DCMIPP_PRESUR_FEU                   DCMIPP_PRESUR_FEU_Msk                           /*!< Frame end delimiter unmask */
9759 
9760 /*****************  Bit definition for DCMIPP_PRIER register  *****************/
9761 #define DCMIPP_PRIER_ERRIE_Pos              (6U)
9762 #define DCMIPP_PRIER_ERRIE_Msk              (0x1UL << DCMIPP_PRIER_ERRIE_Pos)                /*!< 0x00000040 */
9763 #define DCMIPP_PRIER_ERRIE                  DCMIPP_PRIER_ERRIE_Msk                          /*!< Synchronization error interrupt enable */
9764 
9765 /*****************  Bit definition for DCMIPP_PRSR register  ******************/
9766 #define DCMIPP_PRSR_ERRF_Pos                (6U)
9767 #define DCMIPP_PRSR_ERRF_Msk                (0x1UL << DCMIPP_PRSR_ERRF_Pos)                  /*!< 0x00000040 */
9768 #define DCMIPP_PRSR_ERRF                    DCMIPP_PRSR_ERRF_Msk                            /*!< Synchronization error raw interrupt status */
9769 #define DCMIPP_PRSR_HSYNC_Pos               (16U)
9770 #define DCMIPP_PRSR_HSYNC_Msk               (0x1UL << DCMIPP_PRSR_HSYNC_Pos)                 /*!< 0x00010000 */
9771 #define DCMIPP_PRSR_HSYNC                   DCMIPP_PRSR_HSYNC_Msk                           /*!< This bit gives the state of the HSYNC pin with the correct programmed polarity if the ENABLE bit is */
9772 #define DCMIPP_PRSR_VSYNC_Pos               (17U)
9773 #define DCMIPP_PRSR_VSYNC_Msk               (0x1UL << DCMIPP_PRSR_VSYNC_Pos)                 /*!< 0x00020000 */
9774 #define DCMIPP_PRSR_VSYNC                   DCMIPP_PRSR_VSYNC_Msk                           /*!< This bit gives the state of the VSYNC pin with the correct programmed polarity if the ENABLE bit is */
9775 
9776 /*****************  Bit definition for DCMIPP_PRFCR register  *****************/
9777 #define DCMIPP_PRFCR_CERRF_Pos              (6U)
9778 #define DCMIPP_PRFCR_CERRF_Msk              (0x1UL << DCMIPP_PRFCR_CERRF_Pos)                /*!< 0x00000040 */
9779 #define DCMIPP_PRFCR_CERRF                  DCMIPP_PRFCR_CERRF_Msk                          /*!< Synchronization error interrupt status clear */
9780 
9781 /*****************  Bit definition for DCMIPP_CMCR register  ******************/
9782 #define DCMIPP_CMCR_INSEL_Pos               (0U)
9783 #define DCMIPP_CMCR_INSEL_Msk               (0x1UL << DCMIPP_CMCR_INSEL_Pos)                 /*!< 0x00000001 */
9784 #define DCMIPP_CMCR_INSEL                   DCMIPP_CMCR_INSEL_Msk                           /*!< input selection */
9785 #define DCMIPP_CMCR_PSFC_Pos                (1U)
9786 #define DCMIPP_CMCR_PSFC_Msk                (0x3UL << DCMIPP_CMCR_PSFC_Pos)                  /*!< 0x00000006 */
9787 #define DCMIPP_CMCR_PSFC                    DCMIPP_CMCR_PSFC_Msk                            /*!< Pipe selection for the frame counter */
9788 #define DCMIPP_CMCR_CFC_Pos                 (4U)
9789 #define DCMIPP_CMCR_CFC_Msk                 (0x1UL << DCMIPP_CMCR_CFC_Pos)                   /*!< 0x00000010 */
9790 #define DCMIPP_CMCR_CFC                     DCMIPP_CMCR_CFC_Msk                             /*!< Clear frame counter */
9791 #define DCMIPP_CMCR_SWAPRB_Pos              (7U)
9792 #define DCMIPP_CMCR_SWAPRB_Msk              (0x1UL << DCMIPP_CMCR_SWAPRB_Pos)                /*!< 0x00000080 */
9793 #define DCMIPP_CMCR_SWAPRB                  DCMIPP_CMCR_SWAPRB_Msk                          /*!< Swap R/U and B/V */
9794 
9795 /****************  Bit definition for DCMIPP_CMFRCR register  *****************/
9796 #define DCMIPP_CMFRCR_FRMCNT_Pos            (0U)
9797 #define DCMIPP_CMFRCR_FRMCNT_Msk            (0xFFFFFFFFUL << DCMIPP_CMFRCR_FRMCNT_Pos)       /*!< 0xFFFFFFFF */
9798 #define DCMIPP_CMFRCR_FRMCNT                DCMIPP_CMFRCR_FRMCNT_Msk                        /*!< Frame counter, read-only, loops around */
9799 
9800 /*****************  Bit definition for DCMIPP_CMIER register  *****************/
9801 #define DCMIPP_CMIER_ATXERRIE_Pos           (5U)
9802 #define DCMIPP_CMIER_ATXERRIE_Msk           (0x1UL << DCMIPP_CMIER_ATXERRIE_Pos)             /*!< 0x00000020 */
9803 #define DCMIPP_CMIER_ATXERRIE               DCMIPP_CMIER_ATXERRIE_Msk                       /*!< AXI Transfer error interrupt enable for IPPLUG */
9804 #define DCMIPP_CMIER_PRERRIE_Pos            (6U)
9805 #define DCMIPP_CMIER_PRERRIE_Msk            (0x1UL << DCMIPP_CMIER_PRERRIE_Pos)              /*!< 0x00000040 */
9806 #define DCMIPP_CMIER_PRERRIE                DCMIPP_CMIER_PRERRIE_Msk                        /*!< limit interrupt enable for the Parallel Interface */
9807 #define DCMIPP_CMIER_P0LINEIE_Pos           (8U)
9808 #define DCMIPP_CMIER_P0LINEIE_Msk           (0x1UL << DCMIPP_CMIER_P0LINEIE_Pos)             /*!< 0x00000100 */
9809 #define DCMIPP_CMIER_P0LINEIE               DCMIPP_CMIER_P0LINEIE_Msk                       /*!< multi-Line Capture complete interrupt enable for the Pipe0 */
9810 #define DCMIPP_CMIER_P0FRAMEIE_Pos          (9U)
9811 #define DCMIPP_CMIER_P0FRAMEIE_Msk          (0x1UL << DCMIPP_CMIER_P0FRAMEIE_Pos)            /*!< 0x00000200 */
9812 #define DCMIPP_CMIER_P0FRAMEIE              DCMIPP_CMIER_P0FRAMEIE_Msk                      /*!< Frame Capture complete interrupt enable for the Pipe0 */
9813 #define DCMIPP_CMIER_P0VSYNCIE_Pos          (10U)
9814 #define DCMIPP_CMIER_P0VSYNCIE_Msk          (0x1UL << DCMIPP_CMIER_P0VSYNCIE_Pos)            /*!< 0x00000400 */
9815 #define DCMIPP_CMIER_P0VSYNCIE              DCMIPP_CMIER_P0VSYNCIE_Msk                      /*!< Vertical sync interrupt enable for the Pipe0 */
9816 #define DCMIPP_CMIER_P0LIMITIE_Pos          (14U)
9817 #define DCMIPP_CMIER_P0LIMITIE_Msk          (0x1UL << DCMIPP_CMIER_P0LIMITIE_Pos)            /*!< 0x00004000 */
9818 #define DCMIPP_CMIER_P0LIMITIE              DCMIPP_CMIER_P0LIMITIE_Msk                      /*!< limit interrupt enable for the Pipe0 */
9819 #define DCMIPP_CMIER_P0OVRIE_Pos            (15U)
9820 #define DCMIPP_CMIER_P0OVRIE_Msk            (0x1UL << DCMIPP_CMIER_P0OVRIE_Pos)              /*!< 0x00008000 */
9821 #define DCMIPP_CMIER_P0OVRIE                DCMIPP_CMIER_P0OVRIE_Msk                        /*!< Overrun interrupt enable for the Pipe0 */
9822 #define DCMIPP_CMIER_P1LINEIE_Pos           (16U)
9823 #define DCMIPP_CMIER_P1LINEIE_Msk           (0x1UL << DCMIPP_CMIER_P1LINEIE_Pos)             /*!< 0x00010000 */
9824 #define DCMIPP_CMIER_P1LINEIE               DCMIPP_CMIER_P1LINEIE_Msk                       /*!< multi-Line Capture complete interrupt status clear for the Pipe1 */
9825 #define DCMIPP_CMIER_P1FRAMEIE_Pos          (17U)
9826 #define DCMIPP_CMIER_P1FRAMEIE_Msk          (0x1UL << DCMIPP_CMIER_P1FRAMEIE_Pos)            /*!< 0x00020000 */
9827 #define DCMIPP_CMIER_P1FRAMEIE              DCMIPP_CMIER_P1FRAMEIE_Msk                      /*!< Frame Capture complete interrupt enable for the Pipe1 */
9828 #define DCMIPP_CMIER_P1VSYNCIE_Pos          (18U)
9829 #define DCMIPP_CMIER_P1VSYNCIE_Msk          (0x1UL << DCMIPP_CMIER_P1VSYNCIE_Pos)            /*!< 0x00040000 */
9830 #define DCMIPP_CMIER_P1VSYNCIE              DCMIPP_CMIER_P1VSYNCIE_Msk                      /*!< Vertical sync interrupt enable for the Pipe1 */
9831 #define DCMIPP_CMIER_P1OVRIE_Pos            (23U)
9832 #define DCMIPP_CMIER_P1OVRIE_Msk            (0x1UL << DCMIPP_CMIER_P1OVRIE_Pos)              /*!< 0x00800000 */
9833 #define DCMIPP_CMIER_P1OVRIE                DCMIPP_CMIER_P1OVRIE_Msk                        /*!< Overrun interrupt enable for the Pipe1 */
9834 #define DCMIPP_CMIER_P2LINEIE_Pos           (24U)
9835 #define DCMIPP_CMIER_P2LINEIE_Msk           (0x1UL << DCMIPP_CMIER_P2LINEIE_Pos)             /*!< 0x01000000 */
9836 #define DCMIPP_CMIER_P2LINEIE               DCMIPP_CMIER_P2LINEIE_Msk                       /*!< multi-Line Capture complete interrupt enable for the Pipe2 */
9837 #define DCMIPP_CMIER_P2FRAMEIE_Pos          (25U)
9838 #define DCMIPP_CMIER_P2FRAMEIE_Msk          (0x1UL << DCMIPP_CMIER_P2FRAMEIE_Pos)            /*!< 0x02000000 */
9839 #define DCMIPP_CMIER_P2FRAMEIE              DCMIPP_CMIER_P2FRAMEIE_Msk                      /*!< Frame Capture complete interrupt enable for the Pipe2 */
9840 #define DCMIPP_CMIER_P2VSYNCIE_Pos          (26U)
9841 #define DCMIPP_CMIER_P2VSYNCIE_Msk          (0x1UL << DCMIPP_CMIER_P2VSYNCIE_Pos)            /*!< 0x04000000 */
9842 #define DCMIPP_CMIER_P2VSYNCIE              DCMIPP_CMIER_P2VSYNCIE_Msk                      /*!< Vertical sync interrupt enable for the Pipe2 */
9843 #define DCMIPP_CMIER_P2OVRIE_Pos            (31U)
9844 #define DCMIPP_CMIER_P2OVRIE_Msk            (0x1UL << DCMIPP_CMIER_P2OVRIE_Pos)              /*!< 0x80000000 */
9845 #define DCMIPP_CMIER_P2OVRIE                DCMIPP_CMIER_P2OVRIE_Msk                        /*!< Overrun interrupt status enable for the Pipe2 */
9846 
9847 /*****************  Bit definition for DCMIPP_CMSR1 register  *****************/
9848 #define DCMIPP_CMSR1_PRHSYNC_Pos            (0U)
9849 #define DCMIPP_CMSR1_PRHSYNC_Msk            (0x1UL << DCMIPP_CMSR1_PRHSYNC_Pos)              /*!< 0x00000001 */
9850 #define DCMIPP_CMSR1_PRHSYNC                DCMIPP_CMSR1_PRHSYNC_Msk                        /*!< This bit gives the state of the HSYNC pin with the correct programmed polarity on the parallel inte */
9851 #define DCMIPP_CMSR1_PRVSYNC_Pos            (1U)
9852 #define DCMIPP_CMSR1_PRVSYNC_Msk            (0x1UL << DCMIPP_CMSR1_PRVSYNC_Pos)              /*!< 0x00000002 */
9853 #define DCMIPP_CMSR1_PRVSYNC                DCMIPP_CMSR1_PRVSYNC_Msk                        /*!< This bit gives the state of the VSYNC pin with the correct programmed polarity on the parallel inte */
9854 #define DCMIPP_CMSR1_P0LSTLINE_Pos          (8U)
9855 #define DCMIPP_CMSR1_P0LSTLINE_Msk          (0x1UL << DCMIPP_CMSR1_P0LSTLINE_Pos)            /*!< 0x00000100 */
9856 #define DCMIPP_CMSR1_P0LSTLINE              DCMIPP_CMSR1_P0LSTLINE_Msk                      /*!< Last Line LSB bit, sampled at Frame capture complete event for Pipe0 */
9857 #define DCMIPP_CMSR1_P0LSTFRM_Pos           (9U)
9858 #define DCMIPP_CMSR1_P0LSTFRM_Msk           (0x1UL << DCMIPP_CMSR1_P0LSTFRM_Pos)             /*!< 0x00000200 */
9859 #define DCMIPP_CMSR1_P0LSTFRM               DCMIPP_CMSR1_P0LSTFRM_Msk                       /*!< Last frame LSB bit, sampled at Frame capture complete event for Pipe0 */
9860 #define DCMIPP_CMSR1_P0CPTACT_Pos           (15U)
9861 #define DCMIPP_CMSR1_P0CPTACT_Msk           (0x1UL << DCMIPP_CMSR1_P0CPTACT_Pos)             /*!< 0x00008000 */
9862 #define DCMIPP_CMSR1_P0CPTACT               DCMIPP_CMSR1_P0CPTACT_Msk                       /*!< Active frame capture (active from start-of-frame to frame complete) for Pipe0 */
9863 #define DCMIPP_CMSR1_P1LSTLINE_Pos          (16U)
9864 #define DCMIPP_CMSR1_P1LSTLINE_Msk          (0x1UL << DCMIPP_CMSR1_P1LSTLINE_Pos)            /*!< 0x00010000 */
9865 #define DCMIPP_CMSR1_P1LSTLINE              DCMIPP_CMSR1_P1LSTLINE_Msk                      /*!< Last Line LSB bit, sampled at Frame capture complete event for Pipe1 */
9866 #define DCMIPP_CMSR1_P1LSTFRM_Pos           (17U)
9867 #define DCMIPP_CMSR1_P1LSTFRM_Msk           (0x1UL << DCMIPP_CMSR1_P1LSTFRM_Pos)             /*!< 0x00020000 */
9868 #define DCMIPP_CMSR1_P1LSTFRM               DCMIPP_CMSR1_P1LSTFRM_Msk                       /*!< Last frame LSB bit, sampled at frame capture complete event for Pipe1 */
9869 #define DCMIPP_CMSR1_P1CPTACT_Pos           (23U)
9870 #define DCMIPP_CMSR1_P1CPTACT_Msk           (0x1UL << DCMIPP_CMSR1_P1CPTACT_Pos)             /*!< 0x00800000 */
9871 #define DCMIPP_CMSR1_P1CPTACT               DCMIPP_CMSR1_P1CPTACT_Msk                       /*!< Active frame capture (active from start-of-frame to frame complete) for Pipe1 */
9872 #define DCMIPP_CMSR1_P2LSTLINE_Pos          (24U)
9873 #define DCMIPP_CMSR1_P2LSTLINE_Msk          (0x1UL << DCMIPP_CMSR1_P2LSTLINE_Pos)            /*!< 0x01000000 */
9874 #define DCMIPP_CMSR1_P2LSTLINE              DCMIPP_CMSR1_P2LSTLINE_Msk                      /*!< Last line LSB bit, sampled at Frame capture complete event for Pipe2 */
9875 #define DCMIPP_CMSR1_P2LSTFRM_Pos           (25U)
9876 #define DCMIPP_CMSR1_P2LSTFRM_Msk           (0x1UL << DCMIPP_CMSR1_P2LSTFRM_Pos)             /*!< 0x02000000 */
9877 #define DCMIPP_CMSR1_P2LSTFRM               DCMIPP_CMSR1_P2LSTFRM_Msk                       /*!< Last frame LSB bit, sampled at frame capture complete event for Pipe2 */
9878 #define DCMIPP_CMSR1_P2CPTACT_Pos           (31U)
9879 #define DCMIPP_CMSR1_P2CPTACT_Msk           (0x1UL << DCMIPP_CMSR1_P2CPTACT_Pos)             /*!< 0x80000000 */
9880 #define DCMIPP_CMSR1_P2CPTACT               DCMIPP_CMSR1_P2CPTACT_Msk                       /*!< Active frame capture (active from start-of-frame to frame complete) for Pipe2 */
9881 
9882 /*****************  Bit definition for DCMIPP_CMSR2 register  *****************/
9883 #define DCMIPP_CMSR2_ATXERRF_Pos            (5U)
9884 #define DCMIPP_CMSR2_ATXERRF_Msk            (0x1UL << DCMIPP_CMSR2_ATXERRF_Pos)              /*!< 0x00000020 */
9885 #define DCMIPP_CMSR2_ATXERRF                DCMIPP_CMSR2_ATXERRF_Msk                        /*!< AXI transfer error interrupt status flag for the IPPLUG */
9886 #define DCMIPP_CMSR2_PRERRF_Pos             (6U)
9887 #define DCMIPP_CMSR2_PRERRF_Msk             (0x1UL << DCMIPP_CMSR2_PRERRF_Pos)               /*!< 0x00000040 */
9888 #define DCMIPP_CMSR2_PRERRF                 DCMIPP_CMSR2_PRERRF_Msk                         /*!< Synchronization error raw interrupt status for the parallel interface */
9889 #define DCMIPP_CMSR2_P0LINEF_Pos            (8U)
9890 #define DCMIPP_CMSR2_P0LINEF_Msk            (0x1UL << DCMIPP_CMSR2_P0LINEF_Pos)              /*!< 0x00000100 */
9891 #define DCMIPP_CMSR2_P0LINEF                DCMIPP_CMSR2_P0LINEF_Msk                        /*!< Multi-line capture completed raw interrupt status for Pipe0 */
9892 #define DCMIPP_CMSR2_P0FRAMEF_Pos           (9U)
9893 #define DCMIPP_CMSR2_P0FRAMEF_Msk           (0x1UL << DCMIPP_CMSR2_P0FRAMEF_Pos)             /*!< 0x00000200 */
9894 #define DCMIPP_CMSR2_P0FRAMEF               DCMIPP_CMSR2_P0FRAMEF_Msk                       /*!< Frame capture completed raw interrupt status for Pipe0 */
9895 #define DCMIPP_CMSR2_P0VSYNCF_Pos           (10U)
9896 #define DCMIPP_CMSR2_P0VSYNCF_Msk           (0x1UL << DCMIPP_CMSR2_P0VSYNCF_Pos)             /*!< 0x00000400 */
9897 #define DCMIPP_CMSR2_P0VSYNCF               DCMIPP_CMSR2_P0VSYNCF_Msk                       /*!< VSYNC raw interrupt status for Pipe0 */
9898 #define DCMIPP_CMSR2_P0LIMITF_Pos           (14U)
9899 #define DCMIPP_CMSR2_P0LIMITF_Msk           (0x1UL << DCMIPP_CMSR2_P0LIMITF_Pos)             /*!< 0x00004000 */
9900 #define DCMIPP_CMSR2_P0LIMITF               DCMIPP_CMSR2_P0LIMITF_Msk                       /*!< Limit raw interrupt status for Pipe0 */
9901 #define DCMIPP_CMSR2_P0OVRF_Pos             (15U)
9902 #define DCMIPP_CMSR2_P0OVRF_Msk             (0x1UL << DCMIPP_CMSR2_P0OVRF_Pos)               /*!< 0x00008000 */
9903 #define DCMIPP_CMSR2_P0OVRF                 DCMIPP_CMSR2_P0OVRF_Msk                         /*!< Overrun raw interrupt status for Pipe0 */
9904 #define DCMIPP_CMSR2_P1LINEF_Pos            (16U)
9905 #define DCMIPP_CMSR2_P1LINEF_Msk            (0x1UL << DCMIPP_CMSR2_P1LINEF_Pos)              /*!< 0x00010000 */
9906 #define DCMIPP_CMSR2_P1LINEF                DCMIPP_CMSR2_P1LINEF_Msk                        /*!< Multi-line capture completed raw interrupt status for Pipe1 */
9907 #define DCMIPP_CMSR2_P1FRAMEF_Pos           (17U)
9908 #define DCMIPP_CMSR2_P1FRAMEF_Msk           (0x1UL << DCMIPP_CMSR2_P1FRAMEF_Pos)             /*!< 0x00020000 */
9909 #define DCMIPP_CMSR2_P1FRAMEF               DCMIPP_CMSR2_P1FRAMEF_Msk                       /*!< Frame capture completed raw interrupt status for Pipe1 */
9910 #define DCMIPP_CMSR2_P1VSYNCF_Pos           (18U)
9911 #define DCMIPP_CMSR2_P1VSYNCF_Msk           (0x1UL << DCMIPP_CMSR2_P1VSYNCF_Pos)             /*!< 0x00040000 */
9912 #define DCMIPP_CMSR2_P1VSYNCF               DCMIPP_CMSR2_P1VSYNCF_Msk                       /*!< VSYNC raw interrupt status for Pipe1 */
9913 #define DCMIPP_CMSR2_P1OVRF_Pos             (23U)
9914 #define DCMIPP_CMSR2_P1OVRF_Msk             (0x1UL << DCMIPP_CMSR2_P1OVRF_Pos)               /*!< 0x00800000 */
9915 #define DCMIPP_CMSR2_P1OVRF                 DCMIPP_CMSR2_P1OVRF_Msk                         /*!< Overrun raw interrupt status for Pipe1 */
9916 #define DCMIPP_CMSR2_P2LINEF_Pos            (24U)
9917 #define DCMIPP_CMSR2_P2LINEF_Msk            (0x1UL << DCMIPP_CMSR2_P2LINEF_Pos)              /*!< 0x01000000 */
9918 #define DCMIPP_CMSR2_P2LINEF                DCMIPP_CMSR2_P2LINEF_Msk                        /*!< Multi-line capture completed raw interrupt status for Pipe2 */
9919 #define DCMIPP_CMSR2_P2FRAMEF_Pos           (25U)
9920 #define DCMIPP_CMSR2_P2FRAMEF_Msk           (0x1UL << DCMIPP_CMSR2_P2FRAMEF_Pos)             /*!< 0x02000000 */
9921 #define DCMIPP_CMSR2_P2FRAMEF               DCMIPP_CMSR2_P2FRAMEF_Msk                       /*!< Frame capture completed raw interrupt status for Pipe2 */
9922 #define DCMIPP_CMSR2_P2VSYNCF_Pos           (26U)
9923 #define DCMIPP_CMSR2_P2VSYNCF_Msk           (0x1UL << DCMIPP_CMSR2_P2VSYNCF_Pos)             /*!< 0x04000000 */
9924 #define DCMIPP_CMSR2_P2VSYNCF               DCMIPP_CMSR2_P2VSYNCF_Msk                       /*!< VSYNC raw interrupt status for Pipe2 */
9925 #define DCMIPP_CMSR2_P2OVRF_Pos             (31U)
9926 #define DCMIPP_CMSR2_P2OVRF_Msk             (0x1UL << DCMIPP_CMSR2_P2OVRF_Pos)               /*!< 0x80000000 */
9927 #define DCMIPP_CMSR2_P2OVRF                 DCMIPP_CMSR2_P2OVRF_Msk                         /*!< Overrun raw interrupt status for Pipe2 */
9928 
9929 /*****************  Bit definition for DCMIPP_CMFCR register  *****************/
9930 #define DCMIPP_CMFCR_CATXERRF_Pos           (5U)
9931 #define DCMIPP_CMFCR_CATXERRF_Msk           (0x1UL << DCMIPP_CMFCR_CATXERRF_Pos)             /*!< 0x00000020 */
9932 #define DCMIPP_CMFCR_CATXERRF               DCMIPP_CMFCR_CATXERRF_Msk                       /*!< AXI Transfer error interrupt status clear */
9933 #define DCMIPP_CMFCR_CPRERRF_Pos            (6U)
9934 #define DCMIPP_CMFCR_CPRERRF_Msk            (0x1UL << DCMIPP_CMFCR_CPRERRF_Pos)              /*!< 0x00000040 */
9935 #define DCMIPP_CMFCR_CPRERRF                DCMIPP_CMFCR_CPRERRF_Msk                        /*!< Synchronization error interrupt status clear */
9936 #define DCMIPP_CMFCR_CP0LINEF_Pos           (8U)
9937 #define DCMIPP_CMFCR_CP0LINEF_Msk           (0x1UL << DCMIPP_CMFCR_CP0LINEF_Pos)             /*!< 0x00000100 */
9938 #define DCMIPP_CMFCR_CP0LINEF               DCMIPP_CMFCR_CP0LINEF_Msk                       /*!< Multi-line capture complete interrupt status clear */
9939 #define DCMIPP_CMFCR_CP0FRAMEF_Pos          (9U)
9940 #define DCMIPP_CMFCR_CP0FRAMEF_Msk          (0x1UL << DCMIPP_CMFCR_CP0FRAMEF_Pos)            /*!< 0x00000200 */
9941 #define DCMIPP_CMFCR_CP0FRAMEF              DCMIPP_CMFCR_CP0FRAMEF_Msk                      /*!< Frame capture complete interrupt status clear */
9942 #define DCMIPP_CMFCR_CP0VSYNCF_Pos          (10U)
9943 #define DCMIPP_CMFCR_CP0VSYNCF_Msk          (0x1UL << DCMIPP_CMFCR_CP0VSYNCF_Pos)            /*!< 0x00000400 */
9944 #define DCMIPP_CMFCR_CP0VSYNCF              DCMIPP_CMFCR_CP0VSYNCF_Msk                      /*!< Vertical synchronization interrupt status clear */
9945 #define DCMIPP_CMFCR_CP0LIMITF_Pos          (14U)
9946 #define DCMIPP_CMFCR_CP0LIMITF_Msk          (0x1UL << DCMIPP_CMFCR_CP0LIMITF_Pos)            /*!< 0x00004000 */
9947 #define DCMIPP_CMFCR_CP0LIMITF              DCMIPP_CMFCR_CP0LIMITF_Msk                      /*!< limit interrupt status clear */
9948 #define DCMIPP_CMFCR_CP0OVRF_Pos            (15U)
9949 #define DCMIPP_CMFCR_CP0OVRF_Msk            (0x1UL << DCMIPP_CMFCR_CP0OVRF_Pos)              /*!< 0x00008000 */
9950 #define DCMIPP_CMFCR_CP0OVRF                DCMIPP_CMFCR_CP0OVRF_Msk                        /*!< Overrun interrupt status clear */
9951 #define DCMIPP_CMFCR_CP1LINEF_Pos           (16U)
9952 #define DCMIPP_CMFCR_CP1LINEF_Msk           (0x1UL << DCMIPP_CMFCR_CP1LINEF_Pos)             /*!< 0x00010000 */
9953 #define DCMIPP_CMFCR_CP1LINEF               DCMIPP_CMFCR_CP1LINEF_Msk                       /*!< Multi-line capture complete interrupt status clear */
9954 #define DCMIPP_CMFCR_CP1FRAMEF_Pos          (17U)
9955 #define DCMIPP_CMFCR_CP1FRAMEF_Msk          (0x1UL << DCMIPP_CMFCR_CP1FRAMEF_Pos)            /*!< 0x00020000 */
9956 #define DCMIPP_CMFCR_CP1FRAMEF              DCMIPP_CMFCR_CP1FRAMEF_Msk                      /*!< Frame capture complete interrupt status clear */
9957 #define DCMIPP_CMFCR_CP1VSYNCF_Pos          (18U)
9958 #define DCMIPP_CMFCR_CP1VSYNCF_Msk          (0x1UL << DCMIPP_CMFCR_CP1VSYNCF_Pos)            /*!< 0x00040000 */
9959 #define DCMIPP_CMFCR_CP1VSYNCF              DCMIPP_CMFCR_CP1VSYNCF_Msk                      /*!< Vertical synchronization interrupt status clear */
9960 #define DCMIPP_CMFCR_CP1OVRF_Pos            (23U)
9961 #define DCMIPP_CMFCR_CP1OVRF_Msk            (0x1UL << DCMIPP_CMFCR_CP1OVRF_Pos)              /*!< 0x00800000 */
9962 #define DCMIPP_CMFCR_CP1OVRF                DCMIPP_CMFCR_CP1OVRF_Msk                        /*!< Overrun interrupt status clear */
9963 #define DCMIPP_CMFCR_CP2LINEF_Pos           (24U)
9964 #define DCMIPP_CMFCR_CP2LINEF_Msk           (0x1UL << DCMIPP_CMFCR_CP2LINEF_Pos)             /*!< 0x01000000 */
9965 #define DCMIPP_CMFCR_CP2LINEF               DCMIPP_CMFCR_CP2LINEF_Msk                       /*!< Multi-line capture complete interrupt status clear */
9966 #define DCMIPP_CMFCR_CP2FRAMEF_Pos          (25U)
9967 #define DCMIPP_CMFCR_CP2FRAMEF_Msk          (0x1UL << DCMIPP_CMFCR_CP2FRAMEF_Pos)            /*!< 0x02000000 */
9968 #define DCMIPP_CMFCR_CP2FRAMEF              DCMIPP_CMFCR_CP2FRAMEF_Msk                      /*!< Frame capture complete interrupt status clear */
9969 #define DCMIPP_CMFCR_CP2VSYNCF_Pos          (26U)
9970 #define DCMIPP_CMFCR_CP2VSYNCF_Msk          (0x1UL << DCMIPP_CMFCR_CP2VSYNCF_Pos)            /*!< 0x04000000 */
9971 #define DCMIPP_CMFCR_CP2VSYNCF              DCMIPP_CMFCR_CP2VSYNCF_Msk                      /*!< Vertical synchronization interrupt status clear */
9972 #define DCMIPP_CMFCR_CP2OVRF_Pos            (31U)
9973 #define DCMIPP_CMFCR_CP2OVRF_Msk            (0x1UL << DCMIPP_CMFCR_CP2OVRF_Pos)              /*!< 0x80000000 */
9974 #define DCMIPP_CMFCR_CP2OVRF                DCMIPP_CMFCR_CP2OVRF_Msk                        /*!< Overrun interrupt status clear */
9975 
9976 /****************  Bit definition for DCMIPP_P0FSCR register  *****************/
9977 #define DCMIPP_P0FSCR_DTIDA_Pos             (0U)
9978 #define DCMIPP_P0FSCR_DTIDA_Msk             (0x3FUL << DCMIPP_P0FSCR_DTIDA_Pos)              /*!< 0x0000003F */
9979 #define DCMIPP_P0FSCR_DTIDA                 DCMIPP_P0FSCR_DTIDA_Msk                         /*!< Data type selection ID A */
9980 #define DCMIPP_P0FSCR_DTIDB_Pos             (8U)
9981 #define DCMIPP_P0FSCR_DTIDB_Msk             (0x3FUL << DCMIPP_P0FSCR_DTIDB_Pos)              /*!< 0x00003F00 */
9982 #define DCMIPP_P0FSCR_DTIDB                 DCMIPP_P0FSCR_DTIDB_Msk                         /*!< Data type selection ID B */
9983 #define DCMIPP_P0FSCR_DTMODE_Pos            (16U)
9984 #define DCMIPP_P0FSCR_DTMODE_Msk            (0x3UL << DCMIPP_P0FSCR_DTMODE_Pos)              /*!< 0x00030000 */
9985 #define DCMIPP_P0FSCR_DTMODE                DCMIPP_P0FSCR_DTMODE_Msk                        /*!< Flow selection mode */
9986 #define DCMIPP_P0FSCR_VC_Pos                (19U)
9987 #define DCMIPP_P0FSCR_VC_Msk                (0x3UL << DCMIPP_P0FSCR_VC_Pos)                  /*!< 0x00180000 */
9988 #define DCMIPP_P0FSCR_VC                    DCMIPP_P0FSCR_VC_Msk                            /*!< Flow selection mode */
9989 #define DCMIPP_P0FSCR_PIPEN_Pos             (31U)
9990 #define DCMIPP_P0FSCR_PIPEN_Msk             (0x1UL << DCMIPP_P0FSCR_PIPEN_Pos)               /*!< 0x80000000 */
9991 #define DCMIPP_P0FSCR_PIPEN                 DCMIPP_P0FSCR_PIPEN_Msk                         /*!< Activation of PipeN */
9992 
9993 /****************  Bit definition for DCMIPP_P0FCTCR register  ****************/
9994 #define DCMIPP_P0FCTCR_FRATE_Pos            (0U)
9995 #define DCMIPP_P0FCTCR_FRATE_Msk            (0x3UL << DCMIPP_P0FCTCR_FRATE_Pos)              /*!< 0x00000003 */
9996 #define DCMIPP_P0FCTCR_FRATE                DCMIPP_P0FCTCR_FRATE_Msk                        /*!< Frame capture rate control */
9997 #define DCMIPP_P0FCTCR_CPTMODE_Pos          (2U)
9998 #define DCMIPP_P0FCTCR_CPTMODE_Msk          (0x1UL << DCMIPP_P0FCTCR_CPTMODE_Pos)            /*!< 0x00000004 */
9999 #define DCMIPP_P0FCTCR_CPTMODE              DCMIPP_P0FCTCR_CPTMODE_Msk                      /*!< Capture mode */
10000 #define DCMIPP_P0FCTCR_CPTREQ_Pos           (3U)
10001 #define DCMIPP_P0FCTCR_CPTREQ_Msk           (0x1UL << DCMIPP_P0FCTCR_CPTREQ_Pos)             /*!< 0x00000008 */
10002 #define DCMIPP_P0FCTCR_CPTREQ               DCMIPP_P0FCTCR_CPTREQ_Msk                       /*!< Capture requested */
10003 
10004 /****************  Bit definition for DCMIPP_P0SCSTR register  ****************/
10005 #define DCMIPP_P0SCSTR_HSTART_Pos           (0U)
10006 #define DCMIPP_P0SCSTR_HSTART_Msk           (0xFFFUL << DCMIPP_P0SCSTR_HSTART_Pos)           /*!< 0x00000FFF */
10007 #define DCMIPP_P0SCSTR_HSTART               DCMIPP_P0SCSTR_HSTART_Msk                       /*!< Horizontal start, from 0 to 4094 words wide */
10008 #define DCMIPP_P0SCSTR_VSTART_Pos           (16U)
10009 #define DCMIPP_P0SCSTR_VSTART_Msk           (0xFFFUL << DCMIPP_P0SCSTR_VSTART_Pos)           /*!< 0x0FFF0000 */
10010 #define DCMIPP_P0SCSTR_VSTART               DCMIPP_P0SCSTR_VSTART_Msk                       /*!< Vertical start, from 0 to 4094 pixels high */
10011 
10012 /****************  Bit definition for DCMIPP_P0SCSZR register  ****************/
10013 #define DCMIPP_P0SCSZR_HSIZE_Pos            (0U)
10014 #define DCMIPP_P0SCSZR_HSIZE_Msk            (0xFFFUL << DCMIPP_P0SCSZR_HSIZE_Pos)            /*!< 0x00000FFF */
10015 #define DCMIPP_P0SCSZR_HSIZE                DCMIPP_P0SCSZR_HSIZE_Msk                        /*!< Horizontal size, from 0 to 4094 word wide (data 32-bit) */
10016 #define DCMIPP_P0SCSZR_VSIZE_Pos            (16U)
10017 #define DCMIPP_P0SCSZR_VSIZE_Msk            (0xFFFUL << DCMIPP_P0SCSZR_VSIZE_Pos)            /*!< 0x0FFF0000 */
10018 #define DCMIPP_P0SCSZR_VSIZE                DCMIPP_P0SCSZR_VSIZE_Msk                        /*!< Vertical size, from 0 to 4094 pixels high */
10019 #define DCMIPP_P0SCSZR_POSNEG_Pos           (30U)
10020 #define DCMIPP_P0SCSZR_POSNEG_Msk           (0x1UL << DCMIPP_P0SCSZR_POSNEG_Pos)             /*!< 0x40000000 */
10021 #define DCMIPP_P0SCSZR_POSNEG               DCMIPP_P0SCSZR_POSNEG_Msk                       /*!< This bit is set and cleared by software */
10022 #define DCMIPP_P0SCSZR_ENABLE_Pos           (31U)
10023 #define DCMIPP_P0SCSZR_ENABLE_Msk           (0x1UL << DCMIPP_P0SCSZR_ENABLE_Pos)             /*!< 0x80000000 */
10024 #define DCMIPP_P0SCSZR_ENABLE               DCMIPP_P0SCSZR_ENABLE_Msk                       /*!< This bit is set and cleared by software */
10025 
10026 /***************  Bit definition for DCMIPP_P0DCCNTR register  ****************/
10027 #define DCMIPP_P0DCCNTR_CNT_Pos             (0U)
10028 #define DCMIPP_P0DCCNTR_CNT_Msk             (0x3FFFFFFUL << DCMIPP_P0DCCNTR_CNT_Pos)         /*!< 0x03FFFFFF */
10029 #define DCMIPP_P0DCCNTR_CNT                 DCMIPP_P0DCCNTR_CNT_Msk                         /*!< Number of data dumped during the frame */
10030 
10031 /***************  Bit definition for DCMIPP_P0DCLMTR register  ****************/
10032 #define DCMIPP_P0DCLMTR_LIMIT_Pos           (0U)
10033 #define DCMIPP_P0DCLMTR_LIMIT_Msk           (0xFFFFFFUL << DCMIPP_P0DCLMTR_LIMIT_Pos)        /*!< 0x00FFFFFF */
10034 #define DCMIPP_P0DCLMTR_LIMIT               DCMIPP_P0DCLMTR_LIMIT_Msk                       /*!< Maximum number of 32-bit data that can be dumped during a frame, after the crop 2D operation */
10035 #define DCMIPP_P0DCLMTR_ENABLE_Pos          (31U)
10036 #define DCMIPP_P0DCLMTR_ENABLE_Msk          (0x1UL << DCMIPP_P0DCLMTR_ENABLE_Pos)            /*!< 0x80000000 */
10037 #define DCMIPP_P0DCLMTR_ENABLE              DCMIPP_P0DCLMTR_ENABLE_Msk                      /*!<  */
10038 
10039 /****************  Bit definition for DCMIPP_P0PPCR register  *****************/
10040 #define DCMIPP_P0PPCR_SWAPYUV_Pos           (0U)
10041 #define DCMIPP_P0PPCR_SWAPYUV_Msk           (0x1UL << DCMIPP_P0PPCR_SWAPYUV_Pos)             /*!< 0x00000001 */
10042 #define DCMIPP_P0PPCR_SWAPYUV               DCMIPP_P0PPCR_SWAPYUV_Msk                       /*!< SwapY vs UV bits, when the YUV mode is active */
10043 #define DCMIPP_P0PPCR_PAD_Pos               (5U)
10044 #define DCMIPP_P0PPCR_PAD_Msk               (0x1UL << DCMIPP_P0PPCR_PAD_Pos)                 /*!< 0x00000020 */
10045 #define DCMIPP_P0PPCR_PAD                   DCMIPP_P0PPCR_PAD_Msk                           /*!< Pad mode for monochrome and raw Bayer 10/12/14 bpp: MSB vs */
10046 #define DCMIPP_P0PPCR_HEADEREN_Pos          (6U)
10047 #define DCMIPP_P0PPCR_HEADEREN_Msk          (0x1UL << DCMIPP_P0PPCR_HEADEREN_Pos)            /*!< 0x00000040 */
10048 #define DCMIPP_P0PPCR_HEADEREN              DCMIPP_P0PPCR_HEADEREN_Msk                      /*!< CSI header dump enable */
10049 #define DCMIPP_P0PPCR_BSM_Pos               (7U)
10050 #define DCMIPP_P0PPCR_BSM_Msk               (0x3UL << DCMIPP_P0PPCR_BSM_Pos)                 /*!< 0x00000180 */
10051 #define DCMIPP_P0PPCR_BSM                   DCMIPP_P0PPCR_BSM_Msk                           /*!< Byte select mode */
10052 #define DCMIPP_P0PPCR_OEBS_Pos              (9U)
10053 #define DCMIPP_P0PPCR_OEBS_Msk              (0x1UL << DCMIPP_P0PPCR_OEBS_Pos)                /*!< 0x00000200 */
10054 #define DCMIPP_P0PPCR_OEBS                  DCMIPP_P0PPCR_OEBS_Msk                          /*!< Odd/even byte select (byte select start) */
10055 #define DCMIPP_P0PPCR_LSM_Pos               (10U)
10056 #define DCMIPP_P0PPCR_LSM_Msk               (0x1UL << DCMIPP_P0PPCR_LSM_Pos)                 /*!< 0x00000400 */
10057 #define DCMIPP_P0PPCR_LSM                   DCMIPP_P0PPCR_LSM_Msk                           /*!< Line select mode */
10058 #define DCMIPP_P0PPCR_OELS_Pos              (11U)
10059 #define DCMIPP_P0PPCR_OELS_Msk              (0x1UL << DCMIPP_P0PPCR_OELS_Pos)                /*!< 0x00000800 */
10060 #define DCMIPP_P0PPCR_OELS                  DCMIPP_P0PPCR_OELS_Msk                          /*!< Odd/even line select (line select start) */
10061 #define DCMIPP_P0PPCR_LINEMULT_Pos          (13U)
10062 #define DCMIPP_P0PPCR_LINEMULT_Msk          (0x7UL << DCMIPP_P0PPCR_LINEMULT_Pos)            /*!< 0x0000E000 */
10063 #define DCMIPP_P0PPCR_LINEMULT              DCMIPP_P0PPCR_LINEMULT_Msk                      /*!< Amount of capture completed lines for LINE Event and Interrupt */
10064 #define DCMIPP_P0PPCR_DBM_Pos               (16U)
10065 #define DCMIPP_P0PPCR_DBM_Msk               (0x1UL << DCMIPP_P0PPCR_DBM_Pos)                 /*!< 0x00010000 */
10066 #define DCMIPP_P0PPCR_DBM                   DCMIPP_P0PPCR_DBM_Msk                           /*!< Double buffer mode */
10067 
10068 /***************  Bit definition for DCMIPP_P0PPM0AR1 register  ***************/
10069 #define DCMIPP_P0PPM0AR1_M0A_Pos            (0U)
10070 #define DCMIPP_P0PPM0AR1_M0A_Msk            (0xFFFFFFFFUL << DCMIPP_P0PPM0AR1_M0A_Pos)       /*!< 0xFFFFFFFF */
10071 #define DCMIPP_P0PPM0AR1_M0A                DCMIPP_P0PPM0AR1_M0A_Msk                        /*!< Memory0 address */
10072 
10073 /***************  Bit definition for DCMIPP_P0PPM0AR2 register  ***************/
10074 #define DCMIPP_P0PPM0AR2_M0A_Pos            (0U)
10075 #define DCMIPP_P0PPM0AR2_M0A_Msk            (0xFFFFFFFFUL << DCMIPP_P0PPM0AR2_M0A_Pos)       /*!< 0xFFFFFFFF */
10076 #define DCMIPP_P0PPM0AR2_M0A                DCMIPP_P0PPM0AR2_M0A_Msk                        /*!< Memory0 address */
10077 
10078 /*****************  Bit definition for DCMIPP_P0IER register  *****************/
10079 #define DCMIPP_P0IER_LINEIE_Pos             (0U)
10080 #define DCMIPP_P0IER_LINEIE_Msk             (0x1UL << DCMIPP_P0IER_LINEIE_Pos)               /*!< 0x00000001 */
10081 #define DCMIPP_P0IER_LINEIE                 DCMIPP_P0IER_LINEIE_Msk                         /*!< Multi-line capture completed interrupt enable */
10082 #define DCMIPP_P0IER_FRAMEIE_Pos            (1U)
10083 #define DCMIPP_P0IER_FRAMEIE_Msk            (0x1UL << DCMIPP_P0IER_FRAMEIE_Pos)              /*!< 0x00000002 */
10084 #define DCMIPP_P0IER_FRAMEIE                DCMIPP_P0IER_FRAMEIE_Msk                        /*!< Frame capture completed interrupt enable */
10085 #define DCMIPP_P0IER_VSYNCIE_Pos            (2U)
10086 #define DCMIPP_P0IER_VSYNCIE_Msk            (0x1UL << DCMIPP_P0IER_VSYNCIE_Pos)              /*!< 0x00000004 */
10087 #define DCMIPP_P0IER_VSYNCIE                DCMIPP_P0IER_VSYNCIE_Msk                        /*!< VSYNC interrupt enable */
10088 #define DCMIPP_P0IER_LIMITIE_Pos            (6U)
10089 #define DCMIPP_P0IER_LIMITIE_Msk            (0x1UL << DCMIPP_P0IER_LIMITIE_Pos)              /*!< 0x00000040 */
10090 #define DCMIPP_P0IER_LIMITIE                DCMIPP_P0IER_LIMITIE_Msk                        /*!< Limit interrupt enable */
10091 #define DCMIPP_P0IER_OVRIE_Pos              (7U)
10092 #define DCMIPP_P0IER_OVRIE_Msk              (0x1UL << DCMIPP_P0IER_OVRIE_Pos)                /*!< 0x00000080 */
10093 #define DCMIPP_P0IER_OVRIE                  DCMIPP_P0IER_OVRIE_Msk                          /*!< Overrun interrupt enable */
10094 
10095 /*****************  Bit definition for DCMIPP_P0SR register  ******************/
10096 #define DCMIPP_P0SR_LINEF_Pos               (0U)
10097 #define DCMIPP_P0SR_LINEF_Msk               (0x1UL << DCMIPP_P0SR_LINEF_Pos)                 /*!< 0x00000001 */
10098 #define DCMIPP_P0SR_LINEF                   DCMIPP_P0SR_LINEF_Msk                           /*!< Multi-line capture completed raw interrupt status */
10099 #define DCMIPP_P0SR_FRAMEF_Pos              (1U)
10100 #define DCMIPP_P0SR_FRAMEF_Msk              (0x1UL << DCMIPP_P0SR_FRAMEF_Pos)                /*!< 0x00000002 */
10101 #define DCMIPP_P0SR_FRAMEF                  DCMIPP_P0SR_FRAMEF_Msk                          /*!< Frame capture completed raw interrupt status */
10102 #define DCMIPP_P0SR_VSYNCF_Pos              (2U)
10103 #define DCMIPP_P0SR_VSYNCF_Msk              (0x1UL << DCMIPP_P0SR_VSYNCF_Pos)                /*!< 0x00000004 */
10104 #define DCMIPP_P0SR_VSYNCF                  DCMIPP_P0SR_VSYNCF_Msk                          /*!< VSYNC raw interrupt status */
10105 #define DCMIPP_P0SR_LIMITF_Pos              (6U)
10106 #define DCMIPP_P0SR_LIMITF_Msk              (0x1UL << DCMIPP_P0SR_LIMITF_Pos)                /*!< 0x00000040 */
10107 #define DCMIPP_P0SR_LIMITF                  DCMIPP_P0SR_LIMITF_Msk                          /*!< Limit raw interrupt status */
10108 #define DCMIPP_P0SR_OVRF_Pos                (7U)
10109 #define DCMIPP_P0SR_OVRF_Msk                (0x1UL << DCMIPP_P0SR_OVRF_Pos)                  /*!< 0x00000080 */
10110 #define DCMIPP_P0SR_OVRF                    DCMIPP_P0SR_OVRF_Msk                            /*!< Overrun raw interrupt status */
10111 #define DCMIPP_P0SR_LSTLINE_Pos             (16U)
10112 #define DCMIPP_P0SR_LSTLINE_Msk             (0x1UL << DCMIPP_P0SR_LSTLINE_Pos)               /*!< 0x00010000 */
10113 #define DCMIPP_P0SR_LSTLINE                 DCMIPP_P0SR_LSTLINE_Msk                         /*!< Last line LSB bit, sampled at frame capture complete event */
10114 #define DCMIPP_P0SR_LSTFRM_Pos              (17U)
10115 #define DCMIPP_P0SR_LSTFRM_Msk              (0x1UL << DCMIPP_P0SR_LSTFRM_Pos)                /*!< 0x00020000 */
10116 #define DCMIPP_P0SR_LSTFRM                  DCMIPP_P0SR_LSTFRM_Msk                          /*!< Last frame LSB bit, sampled at frame capture complete event */
10117 #define DCMIPP_P0SR_CPTACT_Pos              (23U)
10118 #define DCMIPP_P0SR_CPTACT_Msk              (0x1UL << DCMIPP_P0SR_CPTACT_Pos)                /*!< 0x00800000 */
10119 #define DCMIPP_P0SR_CPTACT                  DCMIPP_P0SR_CPTACT_Msk                          /*!< Capture immediate status */
10120 
10121 /*****************  Bit definition for DCMIPP_P0FCR register  *****************/
10122 #define DCMIPP_P0FCR_CLINEF_Pos             (0U)
10123 #define DCMIPP_P0FCR_CLINEF_Msk             (0x1UL << DCMIPP_P0FCR_CLINEF_Pos)               /*!< 0x00000001 */
10124 #define DCMIPP_P0FCR_CLINEF                 DCMIPP_P0FCR_CLINEF_Msk                         /*!< Multi-line capture complete interrupt status clear */
10125 #define DCMIPP_P0FCR_CFRAMEF_Pos            (1U)
10126 #define DCMIPP_P0FCR_CFRAMEF_Msk            (0x1UL << DCMIPP_P0FCR_CFRAMEF_Pos)              /*!< 0x00000002 */
10127 #define DCMIPP_P0FCR_CFRAMEF                DCMIPP_P0FCR_CFRAMEF_Msk                        /*!< Frame capture complete interrupt status clear */
10128 #define DCMIPP_P0FCR_CVSYNCF_Pos            (2U)
10129 #define DCMIPP_P0FCR_CVSYNCF_Msk            (0x1UL << DCMIPP_P0FCR_CVSYNCF_Pos)              /*!< 0x00000004 */
10130 #define DCMIPP_P0FCR_CVSYNCF                DCMIPP_P0FCR_CVSYNCF_Msk                        /*!< Vertical synchronization interrupt status clear */
10131 #define DCMIPP_P0FCR_CLIMITF_Pos            (6U)
10132 #define DCMIPP_P0FCR_CLIMITF_Msk            (0x1UL << DCMIPP_P0FCR_CLIMITF_Pos)              /*!< 0x00000040 */
10133 #define DCMIPP_P0FCR_CLIMITF                DCMIPP_P0FCR_CLIMITF_Msk                        /*!< limit interrupt status clear */
10134 #define DCMIPP_P0FCR_COVRF_Pos              (7U)
10135 #define DCMIPP_P0FCR_COVRF_Msk              (0x1UL << DCMIPP_P0FCR_COVRF_Pos)                /*!< 0x00000080 */
10136 #define DCMIPP_P0FCR_COVRF                  DCMIPP_P0FCR_COVRF_Msk                          /*!< Overrun interrupt status clear */
10137 
10138 /****************  Bit definition for DCMIPP_P0CFSCR register  ****************/
10139 #define DCMIPP_P0CFSCR_DTIDA_Pos            (0U)
10140 #define DCMIPP_P0CFSCR_DTIDA_Msk            (0x3FUL << DCMIPP_P0CFSCR_DTIDA_Pos)             /*!< 0x0000003F */
10141 #define DCMIPP_P0CFSCR_DTIDA                DCMIPP_P0CFSCR_DTIDA_Msk                        /*!< Current Data type selection ID A */
10142 #define DCMIPP_P0CFSCR_DTIDB_Pos            (8U)
10143 #define DCMIPP_P0CFSCR_DTIDB_Msk            (0x3FUL << DCMIPP_P0CFSCR_DTIDB_Pos)             /*!< 0x00003F00 */
10144 #define DCMIPP_P0CFSCR_DTIDB                DCMIPP_P0CFSCR_DTIDB_Msk                        /*!< Current Data type selection ID B */
10145 #define DCMIPP_P0CFSCR_DTMODE_Pos           (16U)
10146 #define DCMIPP_P0CFSCR_DTMODE_Msk           (0x3UL << DCMIPP_P0CFSCR_DTMODE_Pos)             /*!< 0x00030000 */
10147 #define DCMIPP_P0CFSCR_DTMODE               DCMIPP_P0CFSCR_DTMODE_Msk                       /*!< Flow selection mode */
10148 #define DCMIPP_P0CFSCR_VC_Pos               (19U)
10149 #define DCMIPP_P0CFSCR_VC_Msk               (0x3UL << DCMIPP_P0CFSCR_VC_Pos)                 /*!< 0x00180000 */
10150 #define DCMIPP_P0CFSCR_VC                   DCMIPP_P0CFSCR_VC_Msk                           /*!< Current flow selection mode */
10151 #define DCMIPP_P0CFSCR_PIPEN_Pos            (31U)
10152 #define DCMIPP_P0CFSCR_PIPEN_Msk            (0x1UL << DCMIPP_P0CFSCR_PIPEN_Pos)              /*!< 0x80000000 */
10153 #define DCMIPP_P0CFSCR_PIPEN                DCMIPP_P0CFSCR_PIPEN_Msk                        /*!< Current activation of PipeN */
10154 
10155 /***************  Bit definition for DCMIPP_P0CFCTCR register  ****************/
10156 #define DCMIPP_P0CFCTCR_FRATE_Pos           (0U)
10157 #define DCMIPP_P0CFCTCR_FRATE_Msk           (0x3UL << DCMIPP_P0CFCTCR_FRATE_Pos)             /*!< 0x00000003 */
10158 #define DCMIPP_P0CFCTCR_FRATE               DCMIPP_P0CFCTCR_FRATE_Msk                       /*!< Frame capture rate control */
10159 #define DCMIPP_P0CFCTCR_CPTMODE_Pos         (2U)
10160 #define DCMIPP_P0CFCTCR_CPTMODE_Msk         (0x1UL << DCMIPP_P0CFCTCR_CPTMODE_Pos)           /*!< 0x00000004 */
10161 #define DCMIPP_P0CFCTCR_CPTMODE             DCMIPP_P0CFCTCR_CPTMODE_Msk                     /*!< Capture mode */
10162 #define DCMIPP_P0CFCTCR_CPTREQ_Pos          (3U)
10163 #define DCMIPP_P0CFCTCR_CPTREQ_Msk          (0x1UL << DCMIPP_P0CFCTCR_CPTREQ_Pos)            /*!< 0x00000008 */
10164 #define DCMIPP_P0CFCTCR_CPTREQ              DCMIPP_P0CFCTCR_CPTREQ_Msk                      /*!< Capture requested */
10165 
10166 /***************  Bit definition for DCMIPP_P0CSCSTR register  ****************/
10167 #define DCMIPP_P0CSCSTR_HSTART_Pos          (0U)
10168 #define DCMIPP_P0CSCSTR_HSTART_Msk          (0xFFFUL << DCMIPP_P0CSCSTR_HSTART_Pos)          /*!< 0x00000FFF */
10169 #define DCMIPP_P0CSCSTR_HSTART              DCMIPP_P0CSCSTR_HSTART_Msk                      /*!< Current horizontal start, from 0 to 4094 words wide */
10170 #define DCMIPP_P0CSCSTR_VSTART_Pos          (16U)
10171 #define DCMIPP_P0CSCSTR_VSTART_Msk          (0xFFFUL << DCMIPP_P0CSCSTR_VSTART_Pos)          /*!< 0x0FFF0000 */
10172 #define DCMIPP_P0CSCSTR_VSTART              DCMIPP_P0CSCSTR_VSTART_Msk                      /*!< Current vertical start, from 0 to 4094 pixels high */
10173 
10174 /***************  Bit definition for DCMIPP_P0CSCSZR register  ****************/
10175 #define DCMIPP_P0CSCSZR_HSIZE_Pos           (0U)
10176 #define DCMIPP_P0CSCSZR_HSIZE_Msk           (0xFFFUL << DCMIPP_P0CSCSZR_HSIZE_Pos)           /*!< 0x00000FFF */
10177 #define DCMIPP_P0CSCSZR_HSIZE               DCMIPP_P0CSCSZR_HSIZE_Msk                       /*!< Current horizontal size, from 0 to 4094 word wide (data 32-bit) */
10178 #define DCMIPP_P0CSCSZR_VSIZE_Pos           (16U)
10179 #define DCMIPP_P0CSCSZR_VSIZE_Msk           (0xFFFUL << DCMIPP_P0CSCSZR_VSIZE_Pos)           /*!< 0x0FFF0000 */
10180 #define DCMIPP_P0CSCSZR_VSIZE               DCMIPP_P0CSCSZR_VSIZE_Msk                       /*!< Current vertical size, from 0 to 4094 pixels high */
10181 #define DCMIPP_P0CSCSZR_POSNEG_Pos          (30U)
10182 #define DCMIPP_P0CSCSZR_POSNEG_Msk          (0x1UL << DCMIPP_P0CSCSZR_POSNEG_Pos)            /*!< 0x40000000 */
10183 #define DCMIPP_P0CSCSZR_POSNEG              DCMIPP_P0CSCSZR_POSNEG_Msk                      /*!< Current value of the POSNEG bit */
10184 #define DCMIPP_P0CSCSZR_ENABLE_Pos          (31U)
10185 #define DCMIPP_P0CSCSZR_ENABLE_Msk          (0x1UL << DCMIPP_P0CSCSZR_ENABLE_Pos)            /*!< 0x80000000 */
10186 #define DCMIPP_P0CSCSZR_ENABLE              DCMIPP_P0CSCSZR_ENABLE_Msk                      /*!< Current value of the ENABLE bit */
10187 
10188 /****************  Bit definition for DCMIPP_P0CPPCR register  ****************/
10189 #define DCMIPP_P0CPPCR_SWAPYUV_Pos          (0U)
10190 #define DCMIPP_P0CPPCR_SWAPYUV_Msk          (0x1UL << DCMIPP_P0CPPCR_SWAPYUV_Pos)            /*!< 0x00000001 */
10191 #define DCMIPP_P0CPPCR_SWAPYUV              DCMIPP_P0CPPCR_SWAPYUV_Msk                      /*!< SwapY vs UV bits, when the YUV mode is active */
10192 #define DCMIPP_P0CPPCR_PAD_Pos              (5U)
10193 #define DCMIPP_P0CPPCR_PAD_Msk              (0x1UL << DCMIPP_P0CPPCR_PAD_Pos)                /*!< 0x00000020 */
10194 #define DCMIPP_P0CPPCR_PAD                  DCMIPP_P0CPPCR_PAD_Msk                          /*!< Current Pad mode for monochrome and raw Bayer 10/12/14 bpp: MSB vs */
10195 #define DCMIPP_P0CPPCR_HEADEREN_Pos         (6U)
10196 #define DCMIPP_P0CPPCR_HEADEREN_Msk         (0x1UL << DCMIPP_P0CPPCR_HEADEREN_Pos)           /*!< 0x00000040 */
10197 #define DCMIPP_P0CPPCR_HEADEREN             DCMIPP_P0CPPCR_HEADEREN_Msk                     /*!< Current CSI header dump enable */
10198 #define DCMIPP_P0CPPCR_BSM_Pos              (7U)
10199 #define DCMIPP_P0CPPCR_BSM_Msk              (0x3UL << DCMIPP_P0CPPCR_BSM_Pos)                /*!< 0x00000180 */
10200 #define DCMIPP_P0CPPCR_BSM                  DCMIPP_P0CPPCR_BSM_Msk                          /*!< Current Byte select mode */
10201 #define DCMIPP_P0CPPCR_OEBS_Pos             (9U)
10202 #define DCMIPP_P0CPPCR_OEBS_Msk             (0x1UL << DCMIPP_P0CPPCR_OEBS_Pos)               /*!< 0x00000200 */
10203 #define DCMIPP_P0CPPCR_OEBS                 DCMIPP_P0CPPCR_OEBS_Msk                         /*!< Current odd/even byte select (Byte select start) */
10204 #define DCMIPP_P0CPPCR_LSM_Pos              (10U)
10205 #define DCMIPP_P0CPPCR_LSM_Msk              (0x1UL << DCMIPP_P0CPPCR_LSM_Pos)                /*!< 0x00000400 */
10206 #define DCMIPP_P0CPPCR_LSM                  DCMIPP_P0CPPCR_LSM_Msk                          /*!< Current Line select mode */
10207 #define DCMIPP_P0CPPCR_OELS_Pos             (11U)
10208 #define DCMIPP_P0CPPCR_OELS_Msk             (0x1UL << DCMIPP_P0CPPCR_OELS_Pos)               /*!< 0x00000800 */
10209 #define DCMIPP_P0CPPCR_OELS                 DCMIPP_P0CPPCR_OELS_Msk                         /*!< Current odd/even line select (Line select start) */
10210 #define DCMIPP_P0CPPCR_LINEMULT_Pos         (13U)
10211 #define DCMIPP_P0CPPCR_LINEMULT_Msk         (0x7UL << DCMIPP_P0CPPCR_LINEMULT_Pos)           /*!< 0x0000E000 */
10212 #define DCMIPP_P0CPPCR_LINEMULT             DCMIPP_P0CPPCR_LINEMULT_Msk                     /*!< Current amount of capture completed lines for LINE Event and Interrupt */
10213 #define DCMIPP_P0CPPCR_DBM_Pos              (16U)
10214 #define DCMIPP_P0CPPCR_DBM_Msk              (0x1UL << DCMIPP_P0CPPCR_LINEMULT_Pos)           /*!< 0x00010000 */
10215 #define DCMIPP_P0CPPCR_DBM                  DCMIPP_P0CPPCR_LINEMULT_Msk                     /*!< Double buffer mode */
10216 
10217 /**************  Bit definition for DCMIPP_P0CPPM0AR1 register  ***************/
10218 #define DCMIPP_P0CPPM0AR1_M0A_Pos           (0U)
10219 #define DCMIPP_P0CPPM0AR1_M0A_Msk           (0xFFFFFFFFUL << DCMIPP_P0CPPM0AR1_M0A_Pos)      /*!< 0xFFFFFFFF */
10220 #define DCMIPP_P0CPPM0AR1_M0A               DCMIPP_P0CPPM0AR1_M0A_Msk                       /*!< Memory0 address */
10221 
10222 /****************  Bit definition for DCMIPP_P1FSCR register  *****************/
10223 #define DCMIPP_P1FSCR_DTIDA_Pos             (0U)
10224 #define DCMIPP_P1FSCR_DTIDA_Msk             (0x3FUL << DCMIPP_P1FSCR_DTIDA_Pos)              /*!< 0x0000003F */
10225 #define DCMIPP_P1FSCR_DTIDA                 DCMIPP_P1FSCR_DTIDA_Msk                         /*!< Data type ID A */
10226 #define DCMIPP_P1FSCR_DTIDB_Pos             (8U)
10227 #define DCMIPP_P1FSCR_DTIDB_Msk             (0x3FUL << DCMIPP_P1FSCR_DTIDB_Pos)              /*!< 0x00003F00 */
10228 #define DCMIPP_P1FSCR_DTIDB                 DCMIPP_P1FSCR_DTIDB_Msk                         /*!< Data type ID B */
10229 #define DCMIPP_P1FSCR_DTMODE_Pos            (16U)
10230 #define DCMIPP_P1FSCR_DTMODE_Msk            (0x3UL << DCMIPP_P1FSCR_DTMODE_Pos)              /*!< 0x00030000 */
10231 #define DCMIPP_P1FSCR_DTMODE                DCMIPP_P1FSCR_DTMODE_Msk                        /*!< Flow selection mode */
10232 #define DCMIPP_P1FSCR_PIPEDIFF_Pos          (18U)
10233 #define DCMIPP_P1FSCR_PIPEDIFF_Msk          (0x1UL << DCMIPP_P1FSCR_PIPEDIFF_Pos)            /*!< 0x00040000 */
10234 #define DCMIPP_P1FSCR_PIPEDIFF              DCMIPP_P1FSCR_PIPEDIFF_Msk                      /*!< Differentiates Pipe2 vs */
10235 #define DCMIPP_P1FSCR_VC_Pos                (19U)
10236 #define DCMIPP_P1FSCR_VC_Msk                (0x3UL << DCMIPP_P1FSCR_VC_Pos)                  /*!< 0x00180000 */
10237 #define DCMIPP_P1FSCR_VC                    DCMIPP_P1FSCR_VC_Msk                            /*!< Flow selection mode */
10238 #define DCMIPP_P1FSCR_FDTF_Pos              (24U)
10239 #define DCMIPP_P1FSCR_FDTF_Msk              (0x3FUL << DCMIPP_P1FSCR_FDTF_Pos)               /*!< 0x3F000000 */
10240 #define DCMIPP_P1FSCR_FDTF                  DCMIPP_P1FSCR_FDTF_Msk                          /*!< Force Data type format */
10241 #define DCMIPP_P1FSCR_FDTFEN_Pos            (30U)
10242 #define DCMIPP_P1FSCR_FDTFEN_Msk            (0x1UL << DCMIPP_P1FSCR_FDTFEN_Pos)              /*!< 0x40000000 */
10243 #define DCMIPP_P1FSCR_FDTFEN                DCMIPP_P1FSCR_FDTFEN_Msk                        /*!< Force Data type format enable */
10244 #define DCMIPP_P1FSCR_PIPEN_Pos             (31U)
10245 #define DCMIPP_P1FSCR_PIPEN_Msk             (0x1UL << DCMIPP_P1FSCR_PIPEN_Pos)               /*!< 0x80000000 */
10246 #define DCMIPP_P1FSCR_PIPEN                 DCMIPP_P1FSCR_PIPEN_Msk                         /*!< Activation of PipeN */
10247 
10248 /****************  Bit definition for DCMIPP_P1SRCR register  *****************/
10249 #define DCMIPP_P1SRCR_LASTLINE_Pos          (0U)
10250 #define DCMIPP_P1SRCR_LASTLINE_Msk          (0xFFFUL << DCMIPP_P1SRCR_LASTLINE_Pos)          /*!< 0x00000FFF */
10251 #define DCMIPP_P1SRCR_LASTLINE              DCMIPP_P1SRCR_LASTLINE_Msk                      /*!< Number of the last line to be kept when CROPEN = 1 */
10252 #define DCMIPP_P1SRCR_FIRSTLINEDEL_Pos      (12U)
10253 #define DCMIPP_P1SRCR_FIRSTLINEDEL_Msk      (0x7UL << DCMIPP_P1SRCR_FIRSTLINEDEL_Pos)        /*!< 0x00007000 */
10254 #define DCMIPP_P1SRCR_FIRSTLINEDEL          DCMIPP_P1SRCR_FIRSTLINEDEL_Msk                  /*!< Number of lines to be deleted when CROPEN = 1 */
10255 #define DCMIPP_P1SRCR_CROPEN_Pos            (15U)
10256 #define DCMIPP_P1SRCR_CROPEN_Msk            (0x1UL << DCMIPP_P1SRCR_CROPEN_Pos)              /*!< 0x00008000 */
10257 #define DCMIPP_P1SRCR_CROPEN                DCMIPP_P1SRCR_CROPEN_Msk                        /*!< Crop line enable */
10258 
10259 /****************  Bit definition for DCMIPP_P1BPRCR register  ****************/
10260 #define DCMIPP_P1BPRCR_ENABLE_Pos           (0U)
10261 #define DCMIPP_P1BPRCR_ENABLE_Msk           (0x1UL << DCMIPP_P1BPRCR_ENABLE_Pos)             /*!< 0x00000001 */
10262 #define DCMIPP_P1BPRCR_ENABLE               DCMIPP_P1BPRCR_ENABLE_Msk                       /*!< Bad pixel detection must be enabled only for raw Bayer flows, as it corrupts RGB flows */
10263 #define DCMIPP_P1BPRCR_STRENGTH_Pos         (1U)
10264 #define DCMIPP_P1BPRCR_STRENGTH_Msk         (0x7UL << DCMIPP_P1BPRCR_STRENGTH_Pos)           /*!< 0x0000000E */
10265 #define DCMIPP_P1BPRCR_STRENGTH             DCMIPP_P1BPRCR_STRENGTH_Msk                     /*!< Strength (aggressivity) of the bad pixel detection: */
10266 
10267 /****************  Bit definition for DCMIPP_P1BPRSR register  ****************/
10268 #define DCMIPP_P1BPRSR_BADCNT_Pos           (0U)
10269 #define DCMIPP_P1BPRSR_BADCNT_Msk           (0xFFFUL << DCMIPP_P1BPRSR_BADCNT_Pos)           /*!< 0x00000FFF */
10270 #define DCMIPP_P1BPRSR_BADCNT               DCMIPP_P1BPRSR_BADCNT_Msk                       /*!< Amount of detected bad pixels */
10271 
10272 /****************  Bit definition for DCMIPP_P1DECR register  *****************/
10273 #define DCMIPP_P1DECR_ENABLE_Pos            (0U)
10274 #define DCMIPP_P1DECR_ENABLE_Msk            (0x1UL << DCMIPP_P1DECR_ENABLE_Pos)              /*!< 0x00000001 */
10275 #define DCMIPP_P1DECR_ENABLE                DCMIPP_P1DECR_ENABLE_Msk                        /*!<  */
10276 #define DCMIPP_P1DECR_HDEC_Pos              (1U)
10277 #define DCMIPP_P1DECR_HDEC_Msk              (0x3UL << DCMIPP_P1DECR_HDEC_Pos)                /*!< 0x00000006 */
10278 #define DCMIPP_P1DECR_HDEC                  DCMIPP_P1DECR_HDEC_Msk                          /*!< Horizontal decimation ratio */
10279 #define DCMIPP_P1DECR_VDEC_Pos              (3U)
10280 #define DCMIPP_P1DECR_VDEC_Msk              (0x3UL << DCMIPP_P1DECR_VDEC_Pos)                /*!< 0x00000018 */
10281 #define DCMIPP_P1DECR_VDEC                  DCMIPP_P1DECR_VDEC_Msk                          /*!< Vertical decimation ratio */
10282 
10283 /****************  Bit definition for DCMIPP_P1BLCCR register  ****************/
10284 #define DCMIPP_P1BLCCR_ENABLE_Pos           (0U)
10285 #define DCMIPP_P1BLCCR_ENABLE_Msk           (0x1UL << DCMIPP_P1BLCCR_ENABLE_Pos)             /*!< 0x00000001 */
10286 #define DCMIPP_P1BLCCR_ENABLE               DCMIPP_P1BLCCR_ENABLE_Msk                       /*!< Black level calibration */
10287 #define DCMIPP_P1BLCCR_BLCB_Pos             (8U)
10288 #define DCMIPP_P1BLCCR_BLCB_Msk             (0xFFUL << DCMIPP_P1BLCCR_BLCB_Pos)              /*!< 0x0000FF00 */
10289 #define DCMIPP_P1BLCCR_BLCB                 DCMIPP_P1BLCCR_BLCB_Msk                         /*!< Black level calibration - Blue */
10290 #define DCMIPP_P1BLCCR_BLCG_Pos             (16U)
10291 #define DCMIPP_P1BLCCR_BLCG_Msk             (0xFFUL << DCMIPP_P1BLCCR_BLCG_Pos)              /*!< 0x00FF0000 */
10292 #define DCMIPP_P1BLCCR_BLCG                 DCMIPP_P1BLCCR_BLCG_Msk                         /*!< Black level calibration - Green */
10293 #define DCMIPP_P1BLCCR_BLCR_Pos             (24U)
10294 #define DCMIPP_P1BLCCR_BLCR_Msk             (0xFFUL << DCMIPP_P1BLCCR_BLCR_Pos)              /*!< 0xFF000000 */
10295 #define DCMIPP_P1BLCCR_BLCR                 DCMIPP_P1BLCCR_BLCR_Msk                         /*!< Black level calibration - Red */
10296 
10297 /****************  Bit definition for DCMIPP_P1EXCR1 register  ****************/
10298 #define DCMIPP_P1EXCR1_ENABLE_Pos           (0U)
10299 #define DCMIPP_P1EXCR1_ENABLE_Msk           (0x1UL << DCMIPP_P1EXCR1_ENABLE_Pos)             /*!< 0x00000001 */
10300 #define DCMIPP_P1EXCR1_ENABLE               DCMIPP_P1EXCR1_ENABLE_Msk                       /*!< Exposure control (multiplication and shift) of all red, green and blue */
10301 #define DCMIPP_P1EXCR1_MULTR_Pos            (20U)
10302 #define DCMIPP_P1EXCR1_MULTR_Msk            (0xFFUL << DCMIPP_P1EXCR1_MULTR_Pos)             /*!< 0x0FF00000 */
10303 #define DCMIPP_P1EXCR1_MULTR                DCMIPP_P1EXCR1_MULTR_Msk                        /*!< Exposure multiplier - Red */
10304 #define DCMIPP_P1EXCR1_SHFR_Pos             (28U)
10305 #define DCMIPP_P1EXCR1_SHFR_Msk             (0x7UL << DCMIPP_P1EXCR1_SHFR_Pos)               /*!< 0x70000000 */
10306 #define DCMIPP_P1EXCR1_SHFR                 DCMIPP_P1EXCR1_SHFR_Msk                         /*!< Exposure shift - Red */
10307 
10308 /****************  Bit definition for DCMIPP_P1EXCR2 register  ****************/
10309 #define DCMIPP_P1EXCR2_MULTB_Pos            (4U)
10310 #define DCMIPP_P1EXCR2_MULTB_Msk            (0xFFUL << DCMIPP_P1EXCR2_MULTB_Pos)             /*!< 0x00000FF0 */
10311 #define DCMIPP_P1EXCR2_MULTB                DCMIPP_P1EXCR2_MULTB_Msk                        /*!< Exposure multiplier - Blue */
10312 #define DCMIPP_P1EXCR2_SHFB_Pos             (12U)
10313 #define DCMIPP_P1EXCR2_SHFB_Msk             (0x7UL << DCMIPP_P1EXCR2_SHFB_Pos)               /*!< 0x00007000 */
10314 #define DCMIPP_P1EXCR2_SHFB                 DCMIPP_P1EXCR2_SHFB_Msk                         /*!< Exposure shift - Blue */
10315 #define DCMIPP_P1EXCR2_MULTG_Pos            (20U)
10316 #define DCMIPP_P1EXCR2_MULTG_Msk            (0xFFUL << DCMIPP_P1EXCR2_MULTG_Pos)             /*!< 0x0FF00000 */
10317 #define DCMIPP_P1EXCR2_MULTG                DCMIPP_P1EXCR2_MULTG_Msk                        /*!< Exposure multiplier - Green */
10318 #define DCMIPP_P1EXCR2_SHFG_Pos             (28U)
10319 #define DCMIPP_P1EXCR2_SHFG_Msk             (0x7UL << DCMIPP_P1EXCR2_SHFG_Pos)               /*!< 0x70000000 */
10320 #define DCMIPP_P1EXCR2_SHFG                 DCMIPP_P1EXCR2_SHFG_Msk                         /*!< Exposure shift - Green */
10321 
10322 /****************  Bit definition for DCMIPP_P1ST1CR register  ****************/
10323 #define DCMIPP_P1ST1CR_ENABLE_Pos           (0U)
10324 #define DCMIPP_P1ST1CR_ENABLE_Msk           (0x1UL << DCMIPP_P1ST1CR_ENABLE_Pos)             /*!< 0x00000001 */
10325 #define DCMIPP_P1ST1CR_ENABLE               DCMIPP_P1ST1CR_ENABLE_Msk                       /*!<  */
10326 #define DCMIPP_P1ST1CR_BINS_Pos             (2U)
10327 #define DCMIPP_P1ST1CR_BINS_Msk             (0x3UL << DCMIPP_P1ST1CR_BINS_Pos)               /*!< 0x0000000C */
10328 #define DCMIPP_P1ST1CR_BINS                 DCMIPP_P1ST1CR_BINS_Msk                         /*!< Bin definition */
10329 #define DCMIPP_P1ST1CR_SRC_Pos              (4U)
10330 #define DCMIPP_P1ST1CR_SRC_Msk              (0x7UL << DCMIPP_P1ST1CR_SRC_Pos)                /*!< 0x00000070 */
10331 #define DCMIPP_P1ST1CR_SRC                  DCMIPP_P1ST1CR_SRC_Msk                          /*!< Statistics source */
10332 #define DCMIPP_P1ST1CR_MODE_Pos             (7U)
10333 #define DCMIPP_P1ST1CR_MODE_Msk             (0x1UL << DCMIPP_P1ST1CR_MODE_Pos)               /*!< 0x00000080 */
10334 #define DCMIPP_P1ST1CR_MODE                 DCMIPP_P1ST1CR_MODE_Msk                         /*!< Statistics mode */
10335 
10336 /****************  Bit definition for DCMIPP_P1ST2CR register  ****************/
10337 #define DCMIPP_P1ST2CR_ENABLE_Pos           (0U)
10338 #define DCMIPP_P1ST2CR_ENABLE_Msk           (0x1UL << DCMIPP_P1ST2CR_ENABLE_Pos)             /*!< 0x00000001 */
10339 #define DCMIPP_P1ST2CR_ENABLE               DCMIPP_P1ST2CR_ENABLE_Msk                       /*!<  */
10340 #define DCMIPP_P1ST2CR_BINS_Pos             (2U)
10341 #define DCMIPP_P1ST2CR_BINS_Msk             (0x3UL << DCMIPP_P1ST2CR_BINS_Pos)               /*!< 0x0000000C */
10342 #define DCMIPP_P1ST2CR_BINS                 DCMIPP_P1ST2CR_BINS_Msk                         /*!< Bin definition */
10343 #define DCMIPP_P1ST2CR_SRC_Pos              (4U)
10344 #define DCMIPP_P1ST2CR_SRC_Msk              (0x7UL << DCMIPP_P1ST2CR_SRC_Pos)                /*!< 0x00000070 */
10345 #define DCMIPP_P1ST2CR_SRC                  DCMIPP_P1ST2CR_SRC_Msk                          /*!< Statistics source */
10346 #define DCMIPP_P1ST2CR_MODE_Pos             (7U)
10347 #define DCMIPP_P1ST2CR_MODE_Msk             (0x1UL << DCMIPP_P1ST2CR_MODE_Pos)               /*!< 0x00000080 */
10348 #define DCMIPP_P1ST2CR_MODE                 DCMIPP_P1ST2CR_MODE_Msk                         /*!< Statistics mode */
10349 
10350 /****************  Bit definition for DCMIPP_P1ST3CR register  ****************/
10351 #define DCMIPP_P1ST3CR_ENABLE_Pos           (0U)
10352 #define DCMIPP_P1ST3CR_ENABLE_Msk           (0x1UL << DCMIPP_P1ST3CR_ENABLE_Pos)             /*!< 0x00000001 */
10353 #define DCMIPP_P1ST3CR_ENABLE               DCMIPP_P1ST3CR_ENABLE_Msk                       /*!<  */
10354 #define DCMIPP_P1ST3CR_BINS_Pos             (2U)
10355 #define DCMIPP_P1ST3CR_BINS_Msk             (0x3UL << DCMIPP_P1ST3CR_BINS_Pos)               /*!< 0x0000000C */
10356 #define DCMIPP_P1ST3CR_BINS                 DCMIPP_P1ST3CR_BINS_Msk                         /*!< Bin definition */
10357 #define DCMIPP_P1ST3CR_SRC_Pos              (4U)
10358 #define DCMIPP_P1ST3CR_SRC_Msk              (0x7UL << DCMIPP_P1ST3CR_SRC_Pos)                /*!< 0x00000070 */
10359 #define DCMIPP_P1ST3CR_SRC                  DCMIPP_P1ST3CR_SRC_Msk                          /*!< Statistics source */
10360 #define DCMIPP_P1ST3CR_MODE_Pos             (7U)
10361 #define DCMIPP_P1ST3CR_MODE_Msk             (0x1UL << DCMIPP_P1ST3CR_MODE_Pos)               /*!< 0x00000080 */
10362 #define DCMIPP_P1ST3CR_MODE                 DCMIPP_P1ST3CR_MODE_Msk                         /*!< Statistics mode */
10363 
10364 /****************  Bit definition for DCMIPP_P1STSTR register  ****************/
10365 #define DCMIPP_P1STSTR_HSTART_Pos           (0U)
10366 #define DCMIPP_P1STSTR_HSTART_Msk           (0xFFFUL << DCMIPP_P1STSTR_HSTART_Pos)           /*!< 0x00000FFF */
10367 #define DCMIPP_P1STSTR_HSTART               DCMIPP_P1STSTR_HSTART_Msk                       /*!< Horizontal start, from 0 to 4094 pixels wide */
10368 #define DCMIPP_P1STSTR_VSTART_Pos           (16U)
10369 #define DCMIPP_P1STSTR_VSTART_Msk           (0xFFFUL << DCMIPP_P1STSTR_VSTART_Pos)           /*!< 0x0FFF0000 */
10370 #define DCMIPP_P1STSTR_VSTART               DCMIPP_P1STSTR_VSTART_Msk                       /*!< Vertical start, from 0 to 4094 pixels high */
10371 
10372 /****************  Bit definition for DCMIPP_P1STSZR register  ****************/
10373 #define DCMIPP_P1STSZR_HSIZE_Pos            (0U)
10374 #define DCMIPP_P1STSZR_HSIZE_Msk            (0xFFFUL << DCMIPP_P1STSZR_HSIZE_Pos)            /*!< 0x00000FFF */
10375 #define DCMIPP_P1STSZR_HSIZE                DCMIPP_P1STSZR_HSIZE_Msk                        /*!< Horizontal size, from 0 to 4094 pixels wide */
10376 #define DCMIPP_P1STSZR_VSIZE_Pos            (16U)
10377 #define DCMIPP_P1STSZR_VSIZE_Msk            (0xFFFUL << DCMIPP_P1STSZR_VSIZE_Pos)            /*!< 0x0FFF0000 */
10378 #define DCMIPP_P1STSZR_VSIZE                DCMIPP_P1STSZR_VSIZE_Msk                        /*!< Vertical size, from 0 to 4094 pixels high */
10379 #define DCMIPP_P1STSZR_CROPEN_Pos           (31U)
10380 #define DCMIPP_P1STSZR_CROPEN_Msk           (0x1UL << DCMIPP_P1STSZR_CROPEN_Pos)             /*!< 0x80000000 */
10381 #define DCMIPP_P1STSZR_CROPEN               DCMIPP_P1STSZR_CROPEN_Msk                       /*!<  */
10382 
10383 /****************  Bit definition for DCMIPP_P1ST1SR register  ****************/
10384 #define DCMIPP_P1ST1SR_ACCU_Pos             (0U)
10385 #define DCMIPP_P1ST1SR_ACCU_Msk             (0xFFFFFFUL << DCMIPP_P1ST1SR_ACCU_Pos)          /*!< 0x00FFFFFF */
10386 #define DCMIPP_P1ST1SR_ACCU                 DCMIPP_P1ST1SR_ACCU_Msk                         /*!< Accumulation result, divided by 256 */
10387 
10388 /****************  Bit definition for DCMIPP_P1ST2SR register  ****************/
10389 #define DCMIPP_P1ST2SR_ACCU_Pos             (0U)
10390 #define DCMIPP_P1ST2SR_ACCU_Msk             (0xFFFFFFUL << DCMIPP_P1ST2SR_ACCU_Pos)          /*!< 0x00FFFFFF */
10391 #define DCMIPP_P1ST2SR_ACCU                 DCMIPP_P1ST2SR_ACCU_Msk                         /*!< accumulation result, divided by 256 */
10392 
10393 /****************  Bit definition for DCMIPP_P1ST3SR register  ****************/
10394 #define DCMIPP_P1ST3SR_ACCU_Pos             (0U)
10395 #define DCMIPP_P1ST3SR_ACCU_Msk             (0xFFFFFFUL << DCMIPP_P1ST3SR_ACCU_Pos)          /*!< 0x00FFFFFF */
10396 #define DCMIPP_P1ST3SR_ACCU                 DCMIPP_P1ST3SR_ACCU_Msk                         /*!< accumulation result, divided by 256 */
10397 
10398 /****************  Bit definition for DCMIPP_P1DMCR register  *****************/
10399 #define DCMIPP_P1DMCR_ENABLE_Pos            (0U)
10400 #define DCMIPP_P1DMCR_ENABLE_Msk            (0x1UL << DCMIPP_P1DMCR_ENABLE_Pos)              /*!< 0x00000001 */
10401 #define DCMIPP_P1DMCR_ENABLE                DCMIPP_P1DMCR_ENABLE_Msk                        /*!<  */
10402 #define DCMIPP_P1DMCR_TYPE_Pos              (1U)
10403 #define DCMIPP_P1DMCR_TYPE_Msk              (0x3UL << DCMIPP_P1DMCR_TYPE_Pos)                /*!< 0x00000006 */
10404 #define DCMIPP_P1DMCR_TYPE                  DCMIPP_P1DMCR_TYPE_Msk                          /*!< Raw Bayer type */
10405 #define DCMIPP_P1DMCR_PEAK_Pos              (16U)
10406 #define DCMIPP_P1DMCR_PEAK_Msk              (0x7UL << DCMIPP_P1DMCR_PEAK_Pos)                /*!< 0x00070000 */
10407 #define DCMIPP_P1DMCR_PEAK                  DCMIPP_P1DMCR_PEAK_Msk                          /*!< Strength of the peak detection */
10408 #define DCMIPP_P1DMCR_LINEV_Pos             (20U)
10409 #define DCMIPP_P1DMCR_LINEV_Msk             (0x7UL << DCMIPP_P1DMCR_LINEV_Pos)               /*!< 0x00700000 */
10410 #define DCMIPP_P1DMCR_LINEV                 DCMIPP_P1DMCR_LINEV_Msk                         /*!< Strength of the vertical line detection */
10411 #define DCMIPP_P1DMCR_LINEH_Pos             (24U)
10412 #define DCMIPP_P1DMCR_LINEH_Msk             (0x7UL << DCMIPP_P1DMCR_LINEH_Pos)               /*!< 0x07000000 */
10413 #define DCMIPP_P1DMCR_LINEH                 DCMIPP_P1DMCR_LINEH_Msk                         /*!< Strength of the horizontal line detection */
10414 #define DCMIPP_P1DMCR_EDGE_Pos              (28U)
10415 #define DCMIPP_P1DMCR_EDGE_Msk              (0x7UL << DCMIPP_P1DMCR_EDGE_Pos)                /*!< 0x70000000 */
10416 #define DCMIPP_P1DMCR_EDGE                  DCMIPP_P1DMCR_EDGE_Msk                          /*!< Strength of the edge detection */
10417 
10418 /****************  Bit definition for DCMIPP_P1CCCR register  *****************/
10419 #define DCMIPP_P1CCCR_ENABLE_Pos            (0U)
10420 #define DCMIPP_P1CCCR_ENABLE_Msk            (0x1UL << DCMIPP_P1CCCR_ENABLE_Pos)              /*!< 0x00000001 */
10421 #define DCMIPP_P1CCCR_ENABLE                DCMIPP_P1CCCR_ENABLE_Msk                        /*!<  */
10422 #define DCMIPP_P1CCCR_TYPE_Pos              (1U)
10423 #define DCMIPP_P1CCCR_TYPE_Msk              (0x1UL << DCMIPP_P1CCCR_TYPE_Pos)                /*!< 0x00000002 */
10424 #define DCMIPP_P1CCCR_TYPE                  DCMIPP_P1CCCR_TYPE_Msk                          /*!< output samples type used while CLAMP is activated */
10425 #define DCMIPP_P1CCCR_CLAMP_Pos             (2U)
10426 #define DCMIPP_P1CCCR_CLAMP_Msk             (0x1UL << DCMIPP_P1CCCR_CLAMP_Pos)               /*!< 0x00000004 */
10427 #define DCMIPP_P1CCCR_CLAMP                 DCMIPP_P1CCCR_CLAMP_Msk                         /*!< Clamp the output samples */
10428 
10429 /****************  Bit definition for DCMIPP_P1CCRR1 register  ****************/
10430 #define DCMIPP_P1CCRR1_RR_Pos               (0U)
10431 #define DCMIPP_P1CCRR1_RR_Msk               (0x7FFUL << DCMIPP_P1CCRR1_RR_Pos)               /*!< 0x000007FF */
10432 #define DCMIPP_P1CCRR1_RR                   DCMIPP_P1CCRR1_RR_Msk                           /*!< Coefficient row 1 column 1 of the matrix */
10433 #define DCMIPP_P1CCRR1_RG_Pos               (16U)
10434 #define DCMIPP_P1CCRR1_RG_Msk               (0x7FFUL << DCMIPP_P1CCRR1_RG_Pos)               /*!< 0x07FF0000 */
10435 #define DCMIPP_P1CCRR1_RG                   DCMIPP_P1CCRR1_RG_Msk                           /*!< Coefficient row 1 column 2 of the matrix */
10436 
10437 /****************  Bit definition for DCMIPP_P1CCRR2 register  ****************/
10438 #define DCMIPP_P1CCRR2_RB_Pos               (0U)
10439 #define DCMIPP_P1CCRR2_RB_Msk               (0x7FFUL << DCMIPP_P1CCRR2_RB_Pos)               /*!< 0x000007FF */
10440 #define DCMIPP_P1CCRR2_RB                   DCMIPP_P1CCRR2_RB_Msk                           /*!< Coefficient row 1 column 3 of the matrix */
10441 #define DCMIPP_P1CCRR2_RA_Pos               (16U)
10442 #define DCMIPP_P1CCRR2_RA_Msk               (0x3FFUL << DCMIPP_P1CCRR2_RA_Pos)               /*!< 0x03FF0000 */
10443 #define DCMIPP_P1CCRR2_RA                   DCMIPP_P1CCRR2_RA_Msk                           /*!< Coefficient row 1 of the added column (signed integer value) */
10444 
10445 /****************  Bit definition for DCMIPP_P1CCGR1 register  ****************/
10446 #define DCMIPP_P1CCGR1_GR_Pos               (0U)
10447 #define DCMIPP_P1CCGR1_GR_Msk               (0x7FFUL << DCMIPP_P1CCGR1_GR_Pos)               /*!< 0x000007FF */
10448 #define DCMIPP_P1CCGR1_GR                   DCMIPP_P1CCGR1_GR_Msk                           /*!< Coefficient row 2 column 1 of the matrix */
10449 #define DCMIPP_P1CCGR1_GG_Pos               (16U)
10450 #define DCMIPP_P1CCGR1_GG_Msk               (0x7FFUL << DCMIPP_P1CCGR1_GG_Pos)               /*!< 0x07FF0000 */
10451 #define DCMIPP_P1CCGR1_GG                   DCMIPP_P1CCGR1_GG_Msk                           /*!< Coefficient row 2 column 2 of the matrix */
10452 
10453 /****************  Bit definition for DCMIPP_P1CCGR2 register  ****************/
10454 #define DCMIPP_P1CCGR2_GB_Pos               (0U)
10455 #define DCMIPP_P1CCGR2_GB_Msk               (0x7FFUL << DCMIPP_P1CCGR2_GB_Pos)               /*!< 0x000007FF */
10456 #define DCMIPP_P1CCGR2_GB                   DCMIPP_P1CCGR2_GB_Msk                           /*!< Coefficient row 2 column 3 of the matrix */
10457 #define DCMIPP_P1CCGR2_GA_Pos               (16U)
10458 #define DCMIPP_P1CCGR2_GA_Msk               (0x3FFUL << DCMIPP_P1CCGR2_GA_Pos)               /*!< 0x03FF0000 */
10459 #define DCMIPP_P1CCGR2_GA                   DCMIPP_P1CCGR2_GA_Msk                           /*!< Coefficient row 2 of the added column (signed integer value) */
10460 
10461 /****************  Bit definition for DCMIPP_P1CCBR1 register  ****************/
10462 #define DCMIPP_P1CCBR1_BR_Pos               (0U)
10463 #define DCMIPP_P1CCBR1_BR_Msk               (0x7FFUL << DCMIPP_P1CCBR1_BR_Pos)               /*!< 0x000007FF */
10464 #define DCMIPP_P1CCBR1_BR                   DCMIPP_P1CCBR1_BR_Msk                           /*!< Coefficient row 3 column 1 of the matrix */
10465 #define DCMIPP_P1CCBR1_BG_Pos               (16U)
10466 #define DCMIPP_P1CCBR1_BG_Msk               (0x7FFUL << DCMIPP_P1CCBR1_BG_Pos)               /*!< 0x07FF0000 */
10467 #define DCMIPP_P1CCBR1_BG                   DCMIPP_P1CCBR1_BG_Msk                           /*!< Coefficient row 3 column 2 of the matrix */
10468 
10469 /****************  Bit definition for DCMIPP_P1CCBR2 register  ****************/
10470 #define DCMIPP_P1CCBR2_BB_Pos               (0U)
10471 #define DCMIPP_P1CCBR2_BB_Msk               (0x7FFUL << DCMIPP_P1CCBR2_BB_Pos)               /*!< 0x000007FF */
10472 #define DCMIPP_P1CCBR2_BB                   DCMIPP_P1CCBR2_BB_Msk                           /*!< Coefficient row 3 column 3 of the matrix */
10473 #define DCMIPP_P1CCBR2_BA_Pos               (16U)
10474 #define DCMIPP_P1CCBR2_BA_Msk               (0x3FFUL << DCMIPP_P1CCBR2_BA_Pos)               /*!< 0x03FF0000 */
10475 #define DCMIPP_P1CCBR2_BA                   DCMIPP_P1CCBR2_BA_Msk                           /*!< Coefficient row 3 of the added column (signed integer value) */
10476 
10477 /****************  Bit definition for DCMIPP_P1CTCR1 register  ****************/
10478 #define DCMIPP_P1CTCR1_ENABLE_Pos           (0U)
10479 #define DCMIPP_P1CTCR1_ENABLE_Msk           (0x1UL << DCMIPP_P1CTCR1_ENABLE_Pos)             /*!< 0x00000001 */
10480 #define DCMIPP_P1CTCR1_ENABLE               DCMIPP_P1CTCR1_ENABLE_Msk                       /*!<  */
10481 #define DCMIPP_P1CTCR1_LUM0_Pos             (9U)
10482 #define DCMIPP_P1CTCR1_LUM0_Msk             (0x3FUL << DCMIPP_P1CTCR1_LUM0_Pos)              /*!< 0x00007E00 */
10483 #define DCMIPP_P1CTCR1_LUM0                 DCMIPP_P1CTCR1_LUM0_Msk                         /*!< Luminance increase for input luminance of 0 (increase is idle with LUMx = 16) */
10484 
10485 /****************  Bit definition for DCMIPP_P1CTCR2 register  ****************/
10486 #define DCMIPP_P1CTCR2_LUM4_Pos             (1U)
10487 #define DCMIPP_P1CTCR2_LUM4_Msk             (0x3FUL << DCMIPP_P1CTCR2_LUM4_Pos)              /*!< 0x0000007E */
10488 #define DCMIPP_P1CTCR2_LUM4                 DCMIPP_P1CTCR2_LUM4_Msk                         /*!< Luminance increase for input luminance of 128 (increase is idle with LUMx = 16) */
10489 #define DCMIPP_P1CTCR2_LUM3_Pos             (9U)
10490 #define DCMIPP_P1CTCR2_LUM3_Msk             (0x3FUL << DCMIPP_P1CTCR2_LUM3_Pos)              /*!< 0x00007E00 */
10491 #define DCMIPP_P1CTCR2_LUM3                 DCMIPP_P1CTCR2_LUM3_Msk                         /*!< Luminance increase for input luminance of 96 (increase is idle with LUMx = 16) */
10492 #define DCMIPP_P1CTCR2_LUM2_Pos             (17U)
10493 #define DCMIPP_P1CTCR2_LUM2_Msk             (0x3FUL << DCMIPP_P1CTCR2_LUM2_Pos)              /*!< 0x007E0000 */
10494 #define DCMIPP_P1CTCR2_LUM2                 DCMIPP_P1CTCR2_LUM2_Msk                         /*!< Luminance increase for input luminance of 64 (increase is idle with LUMx = 16) */
10495 #define DCMIPP_P1CTCR2_LUM1_Pos             (25U)
10496 #define DCMIPP_P1CTCR2_LUM1_Msk             (0x3FUL << DCMIPP_P1CTCR2_LUM1_Pos)              /*!< 0x7E000000 */
10497 #define DCMIPP_P1CTCR2_LUM1                 DCMIPP_P1CTCR2_LUM1_Msk                         /*!< Luminance increase for input luminance of 32 (increase is idle with LUMx = 16) */
10498 
10499 /****************  Bit definition for DCMIPP_P1CTCR3 register  ****************/
10500 #define DCMIPP_P1CTCR3_LUM8_Pos             (1U)
10501 #define DCMIPP_P1CTCR3_LUM8_Msk             (0x3FUL << DCMIPP_P1CTCR3_LUM8_Pos)              /*!< 0x0000007E */
10502 #define DCMIPP_P1CTCR3_LUM8                 DCMIPP_P1CTCR3_LUM8_Msk                         /*!< Luminance increase for input luminance of 256 (increase is idle with LUMx = 16) */
10503 #define DCMIPP_P1CTCR3_LUM7_Pos             (9U)
10504 #define DCMIPP_P1CTCR3_LUM7_Msk             (0x3FUL << DCMIPP_P1CTCR3_LUM7_Pos)              /*!< 0x00007E00 */
10505 #define DCMIPP_P1CTCR3_LUM7                 DCMIPP_P1CTCR3_LUM7_Msk                         /*!< Luminance increase for input luminance of 224 (increase is idle with LUMx = 16) */
10506 #define DCMIPP_P1CTCR3_LUM6_Pos             (17U)
10507 #define DCMIPP_P1CTCR3_LUM6_Msk             (0x3FUL << DCMIPP_P1CTCR3_LUM6_Pos)              /*!< 0x007E0000 */
10508 #define DCMIPP_P1CTCR3_LUM6                 DCMIPP_P1CTCR3_LUM6_Msk                         /*!< Luminance increase for input luminance of 192 (increase is idle with LUMx = 16) */
10509 #define DCMIPP_P1CTCR3_LUM5_Pos             (25U)
10510 #define DCMIPP_P1CTCR3_LUM5_Msk             (0x3FUL << DCMIPP_P1CTCR3_LUM5_Pos)              /*!< 0x7E000000 */
10511 #define DCMIPP_P1CTCR3_LUM5                 DCMIPP_P1CTCR3_LUM5_Msk                         /*!< Luminance increase for input luminance of 160 (increase is idle with LUMx = 16) */
10512 
10513 /****************  Bit definition for DCMIPP_P1FCTCR register  ****************/
10514 #define DCMIPP_P1FCTCR_FRATE_Pos            (0U)
10515 #define DCMIPP_P1FCTCR_FRATE_Msk            (0x3UL << DCMIPP_P1FCTCR_FRATE_Pos)              /*!< 0x00000003 */
10516 #define DCMIPP_P1FCTCR_FRATE                DCMIPP_P1FCTCR_FRATE_Msk                        /*!< Frame capture rate control */
10517 #define DCMIPP_P1FCTCR_CPTMODE_Pos          (2U)
10518 #define DCMIPP_P1FCTCR_CPTMODE_Msk          (0x1UL << DCMIPP_P1FCTCR_CPTMODE_Pos)            /*!< 0x00000004 */
10519 #define DCMIPP_P1FCTCR_CPTMODE              DCMIPP_P1FCTCR_CPTMODE_Msk                      /*!< Capture mode */
10520 #define DCMIPP_P1FCTCR_CPTREQ_Pos           (3U)
10521 #define DCMIPP_P1FCTCR_CPTREQ_Msk           (0x1UL << DCMIPP_P1FCTCR_CPTREQ_Pos)             /*!< 0x00000008 */
10522 #define DCMIPP_P1FCTCR_CPTREQ               DCMIPP_P1FCTCR_CPTREQ_Msk                       /*!< Capture requested */
10523 
10524 /****************  Bit definition for DCMIPP_P1CRSTR register  ****************/
10525 #define DCMIPP_P1CRSTR_HSTART_Pos           (0U)
10526 #define DCMIPP_P1CRSTR_HSTART_Msk           (0xFFFUL << DCMIPP_P1CRSTR_HSTART_Pos)           /*!< 0x00000FFF */
10527 #define DCMIPP_P1CRSTR_HSTART               DCMIPP_P1CRSTR_HSTART_Msk                       /*!< Horizontal start, from 0 to 4094 pixels wide */
10528 #define DCMIPP_P1CRSTR_VSTART_Pos           (16U)
10529 #define DCMIPP_P1CRSTR_VSTART_Msk           (0xFFFUL << DCMIPP_P1CRSTR_VSTART_Pos)           /*!< 0x0FFF0000 */
10530 #define DCMIPP_P1CRSTR_VSTART               DCMIPP_P1CRSTR_VSTART_Msk                       /*!< Vertical start, from 0 to 4094 pixels high */
10531 
10532 /****************  Bit definition for DCMIPP_P1CRSZR register  ****************/
10533 #define DCMIPP_P1CRSZR_HSIZE_Pos            (0U)
10534 #define DCMIPP_P1CRSZR_HSIZE_Msk            (0xFFFUL << DCMIPP_P1CRSZR_HSIZE_Pos)            /*!< 0x00000FFF */
10535 #define DCMIPP_P1CRSZR_HSIZE                DCMIPP_P1CRSZR_HSIZE_Msk                        /*!< Horizontal size, from 0 to 4094 pixels wide */
10536 #define DCMIPP_P1CRSZR_VSIZE_Pos            (16U)
10537 #define DCMIPP_P1CRSZR_VSIZE_Msk            (0xFFFUL << DCMIPP_P1CRSZR_VSIZE_Pos)            /*!< 0x0FFF0000 */
10538 #define DCMIPP_P1CRSZR_VSIZE                DCMIPP_P1CRSZR_VSIZE_Msk                        /*!< Vertical size, from 0 to 4094 pixels high */
10539 #define DCMIPP_P1CRSZR_ENABLE_Pos           (31U)
10540 #define DCMIPP_P1CRSZR_ENABLE_Msk           (0x1UL << DCMIPP_P1CRSZR_ENABLE_Pos)             /*!< 0x80000000 */
10541 #define DCMIPP_P1CRSZR_ENABLE               DCMIPP_P1CRSZR_ENABLE_Msk                       /*!<  */
10542 
10543 /****************  Bit definition for DCMIPP_P1DCCR register  *****************/
10544 #define DCMIPP_P1DCCR_ENABLE_Pos            (0U)
10545 #define DCMIPP_P1DCCR_ENABLE_Msk            (0x1UL << DCMIPP_P1DCCR_ENABLE_Pos)             /*!< 0x00000001 */
10546 #define DCMIPP_P1DCCR_ENABLE                DCMIPP_P1DCCR_ENABLE_Msk                        /*!< Decimation enable */
10547 #define DCMIPP_P1DCCR_HDEC_Pos              (1U)
10548 #define DCMIPP_P1DCCR_HDEC_Msk              (0x3UL << DCMIPP_P1DCCR_HDEC_Pos)               /*!< 0x00000006 */
10549 #define DCMIPP_P1DCCR_HDEC                  DCMIPP_P1DCCR_HDEC_Msk                          /*!< Horizontal decimation ratio */
10550 #define DCMIPP_P1DCCR_VDEC_Pos              (3U)
10551 #define DCMIPP_P1DCCR_VDEC_Msk              (0x3UL << DCMIPP_P1DCCR_VDEC_Pos)               /*!< 0x00000018 */
10552 #define DCMIPP_P1DCCR_VDEC                  DCMIPP_P1DCCR_VDEC_Msk                          /*!< Vertical decimation ratio */
10553 
10554 /****************  Bit definition for DCMIPP_P1DSCR register  *****************/
10555 #define DCMIPP_P1DSCR_HDIV_Pos              (0U)
10556 #define DCMIPP_P1DSCR_HDIV_Msk              (0x3FFUL << DCMIPP_P1DSCR_HDIV_Pos)              /*!< 0x000003FF */
10557 #define DCMIPP_P1DSCR_HDIV                  DCMIPP_P1DSCR_HDIV_Msk                          /*!< Horizontal division factor, from 128 (8x) to 1023 (1x) */
10558 #define DCMIPP_P1DSCR_VDIV_Pos              (16U)
10559 #define DCMIPP_P1DSCR_VDIV_Msk              (0x3FFUL << DCMIPP_P1DSCR_VDIV_Pos)              /*!< 0x03FF0000 */
10560 #define DCMIPP_P1DSCR_VDIV                  DCMIPP_P1DSCR_VDIV_Msk                          /*!< Vertical division factor, from 128 (8x) to 1023 (1x) */
10561 #define DCMIPP_P1DSCR_ENABLE_Pos            (31U)
10562 #define DCMIPP_P1DSCR_ENABLE_Msk            (0x1UL << DCMIPP_P1DSCR_ENABLE_Pos)              /*!< 0x80000000 */
10563 #define DCMIPP_P1DSCR_ENABLE                DCMIPP_P1DSCR_ENABLE_Msk                        /*!<  Downscaler Enable */
10564 
10565 /***************  Bit definition for DCMIPP_P1DSRTIOR register  ***************/
10566 #define DCMIPP_P1DSRTIOR_HRATIO_Pos         (0U)
10567 #define DCMIPP_P1DSRTIOR_HRATIO_Msk         (0xFFFFUL << DCMIPP_P1DSRTIOR_HRATIO_Pos)        /*!< 0x0000FFFF */
10568 #define DCMIPP_P1DSRTIOR_HRATIO             DCMIPP_P1DSRTIOR_HRATIO_Msk                     /*!< Horizontal ratio, from 8192 (1x) to 65535 (8x) */
10569 #define DCMIPP_P1DSRTIOR_VRATIO_Pos         (16U)
10570 #define DCMIPP_P1DSRTIOR_VRATIO_Msk         (0xFFFFUL << DCMIPP_P1DSRTIOR_VRATIO_Pos)        /*!< 0xFFFF0000 */
10571 #define DCMIPP_P1DSRTIOR_VRATIO             DCMIPP_P1DSRTIOR_VRATIO_Msk                     /*!< Vertical ratio, from 8192 (1x) to 65535 (8x) */
10572 
10573 /****************  Bit definition for DCMIPP_P1DSSZR register  ****************/
10574 #define DCMIPP_P1DSSZR_HSIZE_Pos            (0U)
10575 #define DCMIPP_P1DSSZR_HSIZE_Msk            (0xFFFUL << DCMIPP_P1DSSZR_HSIZE_Pos)            /*!< 0x00000FFF */
10576 #define DCMIPP_P1DSSZR_HSIZE                DCMIPP_P1DSSZR_HSIZE_Msk                        /*!< Horizontal size, from 0 to 4094 pixels wide */
10577 #define DCMIPP_P1DSSZR_VSIZE_Pos            (16U)
10578 #define DCMIPP_P1DSSZR_VSIZE_Msk            (0xFFFUL << DCMIPP_P1DSSZR_VSIZE_Pos)            /*!< 0x0FFF0000 */
10579 #define DCMIPP_P1DSSZR_VSIZE                DCMIPP_P1DSSZR_VSIZE_Msk                        /*!< Vertical size, from 0 to 4094 pixels high */
10580 
10581 /***************  Bit definition for DCMIPP_P1CMRICR register  ***************/
10582 #define DCMIPP_P1CMRICR_ROILSZ_Pos          (0U)
10583 #define DCMIPP_P1CMRICR_ROILSZ_Msk          (0x3UL << DCMIPP_P1CMRICR_ROILSZ_Pos)           /*!< 0x00000003 */
10584 #define DCMIPP_P1CMRICR_ROILSZ              DCMIPP_P1CMRICR_ROILSZ_Msk                      /*!< Region of interest line size width */
10585 #define DCMIPP_P1CMRICR_ROI1EN_Pos          (16U)
10586 #define DCMIPP_P1CMRICR_ROI1EN_Msk          (0x1UL << DCMIPP_P1CMRICR_ROI1EN_Pos)           /*!< 0x00010000 */
10587 #define DCMIPP_P1CMRICR_ROI1EN              DCMIPP_P1CMRICR_ROI1EN_Msk                      /*!< Region Of Interest 1 Enable */
10588 #define DCMIPP_P1CMRICR_ROI2EN_Pos          (17U)
10589 #define DCMIPP_P1CMRICR_ROI2EN_Msk          (0x1UL << DCMIPP_P1CMRICR_ROI2EN_Pos)           /*!< 0x00020000 */
10590 #define DCMIPP_P1CMRICR_ROI2EN              DCMIPP_P1CMRICR_ROI2EN_Msk                      /*!< Region Of Interest 2 Enable */
10591 #define DCMIPP_P1CMRICR_ROI3EN_Pos          (18U)
10592 #define DCMIPP_P1CMRICR_ROI3EN_Msk          (0x1UL << DCMIPP_P1CMRICR_ROI3EN_Pos)           /*!< 0x00040000 */
10593 #define DCMIPP_P1CMRICR_ROI3EN              DCMIPP_P1CMRICR_ROI3EN_Msk                      /*!< Region Of Interest 3 Enable */
10594 #define DCMIPP_P1CMRICR_ROI4EN_Pos          (19U)
10595 #define DCMIPP_P1CMRICR_ROI4EN_Msk          (0x1UL << DCMIPP_P1CMRICR_ROI4EN_Pos)           /*!< 0x00080000 */
10596 #define DCMIPP_P1CMRICR_ROI4EN              DCMIPP_P1CMRICR_ROI4EN_Msk                      /*!< Region Of Interest 4 Enable */
10597 #define DCMIPP_P1CMRICR_ROI5EN_Pos          (20U)
10598 #define DCMIPP_P1CMRICR_ROI5EN_Msk          (0x1UL << DCMIPP_P1CMRICR_ROI5EN_Pos)           /*!< 0x00100000 */
10599 #define DCMIPP_P1CMRICR_ROI5EN              DCMIPP_P1CMRICR_ROI5EN_Msk                      /*!< Region Of Interest 5 Enable */
10600 #define DCMIPP_P1CMRICR_ROI6EN_Pos          (21U)
10601 #define DCMIPP_P1CMRICR_ROI6EN_Msk          (0x1UL << DCMIPP_P1CMRICR_ROI6EN_Pos)           /*!< 0x00200000 */
10602 #define DCMIPP_P1CMRICR_ROI6EN              DCMIPP_P1CMRICR_ROI6EN_Msk                      /*!< Region Of Interest 6 Enable */
10603 #define DCMIPP_P1CMRICR_ROI7EN_Pos          (22U)
10604 #define DCMIPP_P1CMRICR_ROI7EN_Msk          (0x1UL << DCMIPP_P1CMRICR_ROI7EN_Pos)           /*!< 0x00400000 */
10605 #define DCMIPP_P1CMRICR_ROI7EN              DCMIPP_P1CMRICR_ROI7EN_Msk                      /*!< Region Of Interest 7 Enable */
10606 #define DCMIPP_P1CMRICR_ROI8EN_Pos          (23U)
10607 #define DCMIPP_P1CMRICR_ROI8EN_Msk          (0x1UL << DCMIPP_P1CMRICR_ROI8EN_Pos)           /*!< 0x00800000 */
10608 #define DCMIPP_P1CMRICR_ROI8EN              DCMIPP_P1CMRICR_ROI8EN_Msk                      /*!< Region Of Interest 8 Enable */
10609 
10610 /***************  Bit definition for DCMIPP_P1RIxCR1 register  ***************/
10611 #define DCMIPP_P1RIxCR1_HSTART_Pos          (0U)
10612 #define DCMIPP_P1RIxCR1_HSTART_Msk          (0xFFFUL << DCMIPP_P1RIxCR1_HSTART_Pos)        /*!< 0x00000FFF */
10613 #define DCMIPP_P1RIxCR1_HSTART              DCMIPP_P1RIxCR1_HSTART_Msk                     /*!< Horizontal start */
10614 #define DCMIPP_P1RIxCR1_CLB_Pos             (12U)
10615 #define DCMIPP_P1RIxCR1_CLB_Msk             (0x3UL << DCMIPP_P1RIxCR1_CLB_Pos)             /*!< 0x00003000 */
10616 #define DCMIPP_P1RIxCR1_CLB                 DCMIPP_P1RIxCR1_CLB_Msk                        /*!< Color line blue */
10617 #define DCMIPP_P1RIxCR1_CLG_Pos             (14U)
10618 #define DCMIPP_P1RIxCR1_CLG_Msk             (0x3UL << DCMIPP_P1RIxCR1_CLG_Pos)             /*!< 0x0000C000 */
10619 #define DCMIPP_P1RIxCR1_CLG                 DCMIPP_P1RIxCR1_CLG_Msk                        /*!< Color line green */
10620 #define DCMIPP_P1RIxCR1_VSTART_Pos          (16U)
10621 #define DCMIPP_P1RIxCR1_VSTART_Msk          (0xFFFUL << DCMIPP_P1RIxCR1_VSTART_Pos)        /*!< 0x0FFF0000 */
10622 #define DCMIPP_P1RIxCR1_VSTART              DCMIPP_P1RIxCR1_VSTART_Msk                     /*!< Vertical start */
10623 #define DCMIPP_P1RIxCR1_CLR_Pos             (28U)
10624 #define DCMIPP_P1RIxCR1_CLR_Msk             (0x3UL << DCMIPP_P1RIxCR1_CLR_Pos)             /*!< 0x30000000 */
10625 #define DCMIPP_P1RIxCR1_CLR                 DCMIPP_P1RIxCR1_CLR_Msk                        /*!< Color line red */
10626 
10627 /***************  Bit definition for DCMIPP_P1RIxCR2 register  ***************/
10628 #define DCMIPP_P1RIxCR2_VSIZE_Pos           (0U)
10629 #define DCMIPP_P1RIxCR2_VSIZE_Msk           (0xFFFUL << DCMIPP_P1RIxCR2_VSIZE_Pos)        /*!<  0x00000FFF */
10630 #define DCMIPP_P1RIxCR2_VSIZE               DCMIPP_P1RIxCR2_VSIZE_Msk                     /*!< Vertical Size */
10631 #define DCMIPP_P1RIxCR2_HSIZE_Pos           (16U)
10632 #define DCMIPP_P1RIxCR2_HSIZE_Msk           (0xFFFUL << DCMIPP_P1RIxCR2_HSIZE_Pos)        /*!<  0x07FF8000 */
10633 #define DCMIPP_P1RIxCR2_HSIZE               DCMIPP_P1RIxCR2_HSIZE_Msk                     /*!< Horizontal Size */
10634 
10635 /****************  Bit definition for DCMIPP_P1GMCR register  *****************/
10636 #define DCMIPP_P1GMCR_ENABLE_Pos            (0U)
10637 #define DCMIPP_P1GMCR_ENABLE_Msk            (0x1UL << DCMIPP_P1GMCR_ENABLE_Pos)              /*!< 0x00000001   */
10638 #define DCMIPP_P1GMCR_ENABLE                DCMIPP_P1GMCR_ENABLE_Msk                        /*!<  Gamma  enable*/
10639 
10640 /****************  Bit definition for DCMIPP_P1YUVCR register  ****************/
10641 #define DCMIPP_P1YUVCR_ENABLE_Pos           (0U)
10642 #define DCMIPP_P1YUVCR_ENABLE_Msk           (0x1UL << DCMIPP_P1YUVCR_ENABLE_Pos)             /*!< 0x00000001 */
10643 #define DCMIPP_P1YUVCR_ENABLE               DCMIPP_P1YUVCR_ENABLE_Msk                       /*!<  */
10644 #define DCMIPP_P1YUVCR_TYPE_Pos             (1U)
10645 #define DCMIPP_P1YUVCR_TYPE_Msk             (0x1UL << DCMIPP_P1YUVCR_TYPE_Pos)               /*!< 0x00000002 */
10646 #define DCMIPP_P1YUVCR_TYPE                 DCMIPP_P1YUVCR_TYPE_Msk                         /*!< Output samples type used while CLAMP is activated */
10647 #define DCMIPP_P1YUVCR_CLAMP_Pos            (2U)
10648 #define DCMIPP_P1YUVCR_CLAMP_Msk            (0x1UL << DCMIPP_P1YUVCR_CLAMP_Pos)              /*!< 0x00000004 */
10649 #define DCMIPP_P1YUVCR_CLAMP                DCMIPP_P1YUVCR_CLAMP_Msk                        /*!< Clamp the output samples */
10650 
10651 /***************  Bit definition for DCMIPP_P1YUVRR1 register  ****************/
10652 #define DCMIPP_P1YUVRR1_RR_Pos              (0U)
10653 #define DCMIPP_P1YUVRR1_RR_Msk              (0x7FFUL << DCMIPP_P1YUVRR1_RR_Pos)              /*!< 0x000007FF */
10654 #define DCMIPP_P1YUVRR1_RR                  DCMIPP_P1YUVRR1_RR_Msk                          /*!< Coefficient row 1 column 1 of the matrix */
10655 #define DCMIPP_P1YUVRR1_RG_Pos              (16U)
10656 #define DCMIPP_P1YUVRR1_RG_Msk              (0x7FFUL << DCMIPP_P1YUVRR1_RG_Pos)              /*!< 0x07FF0000 */
10657 #define DCMIPP_P1YUVRR1_RG                  DCMIPP_P1YUVRR1_RG_Msk                          /*!< Coefficient row 1 column 2 of the matrix */
10658 
10659 /***************  Bit definition for DCMIPP_P1YUVRR2 register  ****************/
10660 #define DCMIPP_P1YUVRR2_RB_Pos              (0U)
10661 #define DCMIPP_P1YUVRR2_RB_Msk              (0x7FFUL << DCMIPP_P1YUVRR2_RB_Pos)              /*!< 0x000007FF */
10662 #define DCMIPP_P1YUVRR2_RB                  DCMIPP_P1YUVRR2_RB_Msk                          /*!< Coefficient row 1 column 3 of the matrix */
10663 #define DCMIPP_P1YUVRR2_RA_Pos              (16U)
10664 #define DCMIPP_P1YUVRR2_RA_Msk              (0x3FFUL << DCMIPP_P1YUVRR2_RA_Pos)              /*!< 0x03FF0000 */
10665 #define DCMIPP_P1YUVRR2_RA                  DCMIPP_P1YUVRR2_RA_Msk                          /*!< Coefficient row 1 of the added column (signed integer value) */
10666 
10667 /***************  Bit definition for DCMIPP_P1YUVGR1 register  ****************/
10668 #define DCMIPP_P1YUVGR1_GR_Pos              (0U)
10669 #define DCMIPP_P1YUVGR1_GR_Msk              (0x7FFUL << DCMIPP_P1YUVGR1_GR_Pos)              /*!< 0x000007FF */
10670 #define DCMIPP_P1YUVGR1_GR                  DCMIPP_P1YUVGR1_GR_Msk                          /*!< Coefficient row 2 column 1 of the matrix */
10671 #define DCMIPP_P1YUVGR1_GG_Pos              (16U)
10672 #define DCMIPP_P1YUVGR1_GG_Msk              (0x7FFUL << DCMIPP_P1YUVGR1_GG_Pos)              /*!< 0x07FF0000 */
10673 #define DCMIPP_P1YUVGR1_GG                  DCMIPP_P1YUVGR1_GG_Msk                          /*!< Coefficient row 2 column 2 of the matrix */
10674 
10675 /***************  Bit definition for DCMIPP_P1YUVGR2 register  ****************/
10676 #define DCMIPP_P1YUVGR2_GB_Pos              (0U)
10677 #define DCMIPP_P1YUVGR2_GB_Msk              (0x7FFUL << DCMIPP_P1YUVGR2_GB_Pos)              /*!< 0x000007FF */
10678 #define DCMIPP_P1YUVGR2_GB                  DCMIPP_P1YUVGR2_GB_Msk                          /*!< Coefficient row 2 column 3 of the matrix */
10679 #define DCMIPP_P1YUVGR2_GA_Pos              (16U)
10680 #define DCMIPP_P1YUVGR2_GA_Msk              (0x3FFUL << DCMIPP_P1YUVGR2_GA_Pos)              /*!< 0x03FF0000 */
10681 #define DCMIPP_P1YUVGR2_GA                  DCMIPP_P1YUVGR2_GA_Msk                          /*!< Coefficient row 2 of the added column (signed integer value) */
10682 
10683 /***************  Bit definition for DCMIPP_P1YUVBR1 register  ****************/
10684 #define DCMIPP_P1YUVBR1_BR_Pos              (0U)
10685 #define DCMIPP_P1YUVBR1_BR_Msk              (0x7FFUL << DCMIPP_P1YUVBR1_BR_Pos)              /*!< 0x000007FF */
10686 #define DCMIPP_P1YUVBR1_BR                  DCMIPP_P1YUVBR1_BR_Msk                          /*!< Coefficient row 3 column 1 of the matrix */
10687 #define DCMIPP_P1YUVBR1_BG_Pos              (16U)
10688 #define DCMIPP_P1YUVBR1_BG_Msk              (0x7FFUL << DCMIPP_P1YUVBR1_BG_Pos)              /*!< 0x07FF0000 */
10689 #define DCMIPP_P1YUVBR1_BG                  DCMIPP_P1YUVBR1_BG_Msk                          /*!< Coefficient row 3 column 2 of the matrix */
10690 
10691 /***************  Bit definition for DCMIPP_P1YUVBR2 register  ****************/
10692 #define DCMIPP_P1YUVBR2_BB_Pos              (0U)
10693 #define DCMIPP_P1YUVBR2_BB_Msk              (0x7FFUL << DCMIPP_P1YUVBR2_BB_Pos)              /*!< 0x000007FF */
10694 #define DCMIPP_P1YUVBR2_BB                  DCMIPP_P1YUVBR2_BB_Msk                          /*!< Coefficient row 3 column 3 of the matrix */
10695 #define DCMIPP_P1YUVBR2_BA_Pos              (16U)
10696 #define DCMIPP_P1YUVBR2_BA_Msk              (0x3FFUL << DCMIPP_P1YUVBR2_BA_Pos)              /*!< 0x03FF0000 */
10697 #define DCMIPP_P1YUVBR2_BA                  DCMIPP_P1YUVBR2_BA_Msk                          /*!< Coefficient row 3 of the added column (signed integer value) */
10698 
10699 /****************  Bit definition for DCMIPP_P1PPCR register  *****************/
10700 #define DCMIPP_P1PPCR_FORMAT_Pos            (0U)
10701 #define DCMIPP_P1PPCR_FORMAT_Msk            (0xFUL << DCMIPP_P1PPCR_FORMAT_Pos)              /*!< 0x0000000F */
10702 #define DCMIPP_P1PPCR_FORMAT                DCMIPP_P1PPCR_FORMAT_Msk                        /*!< Memory format */
10703 #define DCMIPP_P1PPCR_SWAPRB_Pos            (4U)
10704 #define DCMIPP_P1PPCR_SWAPRB_Msk            (0x1UL << DCMIPP_P1PPCR_SWAPRB_Pos)              /*!< 0x00000010 */
10705 #define DCMIPP_P1PPCR_SWAPRB                DCMIPP_P1PPCR_SWAPRB_Msk                        /*!< Swaps R-vs-B components if RGB, and U-vs-V components if YUV */
10706 #define DCMIPP_P1PPCR_LINEMULT_Pos          (13U)
10707 #define DCMIPP_P1PPCR_LINEMULT_Msk          (0x7UL << DCMIPP_P1PPCR_LINEMULT_Pos)            /*!< 0x0000E000 */
10708 #define DCMIPP_P1PPCR_LINEMULT              DCMIPP_P1PPCR_LINEMULT_Msk                      /*!< Amount of capture completed lines for LINE Event and Interrupt */
10709 #define DCMIPP_P1PPCR_DBM_Pos               (16U)
10710 #define DCMIPP_P1PPCR_DBM_Msk               (0x1UL << DCMIPP_P1PPCR_DBM_Pos)                 /*!< 0x00010000 */
10711 #define DCMIPP_P1PPCR_DBM                   DCMIPP_P1PPCR_DBM_Msk                           /*!< Double buffer mode */
10712 #define DCMIPP_P1PPCR_LMAWM_Pos             (17U)
10713 #define DCMIPP_P1PPCR_LMAWM_Msk             (0x7UL << DCMIPP_P1PPCR_LMAWM_Pos)                /*!< 0x000E0000 */
10714 #define DCMIPP_P1PPCR_LMAWM                 DCMIPP_P1PPCR_LMAWM_Msk                          /*!< Line multi address wrapping modulo */
10715 #define DCMIPP_P1PPCR_LMAWE_Pos             (20U)
10716 #define DCMIPP_P1PPCR_LMAWE_Msk             (0x1UL << DCMIPP_P1PPCR_LMAWE_Pos)                /*!< 0x00100000 */
10717 #define DCMIPP_P1PPCR_LMAWE                 DCMIPP_P1PPCR_LMAWE_Msk                           /*!< Line multi address wrapping enable */
10718 
10719 /***************  Bit definition for DCMIPP_P1PPM0AR1 register  ***************/
10720 #define DCMIPP_P1PPM0AR1_M0A_Pos            (0U)
10721 #define DCMIPP_P1PPM0AR1_M0A_Msk            (0xFFFFFFFFUL << DCMIPP_P1PPM0AR1_M0A_Pos)       /*!< 0xFFFFFFFF */
10722 #define DCMIPP_P1PPM0AR1_M0A                DCMIPP_P1PPM0AR1_M0A_Msk                        /*!< Memory0 address register 1*/
10723 
10724 /***************  Bit definition for DCMIPP_P1PPM0AR2 register  ***************/
10725 #define DCMIPP_P1PPM0AR2_M0A_Pos            (0U)
10726 #define DCMIPP_P1PPM0AR2_M0A_Msk            (0xFFFFFFFFUL << DCMIPP_P1PPM0AR2_M0A_Pos)       /*!< 0xFFFFFFFF */
10727 #define DCMIPP_P1PPM0AR2_M0A                DCMIPP_P1PPM0AR2_M0A_Msk                        /*!< Memory0 address register 2 */
10728 
10729 /***************  Bit definition for DCMIPP_P1PPM0PR register  ****************/
10730 #define DCMIPP_P1PPM0PR_PITCH_Pos           (0U)
10731 #define DCMIPP_P1PPM0PR_PITCH_Msk           (0x7FFFUL << DCMIPP_P1PPM0PR_PITCH_Pos)          /*!< 0x00007FFF */
10732 #define DCMIPP_P1PPM0PR_PITCH               DCMIPP_P1PPM0PR_PITCH_Msk                       /*!< Number of bytes between the address of two consecutive lines */
10733 
10734 /***************  Bit definition for DCMIPP_P1PPM1AR1 register  ***************/
10735 #define DCMIPP_P1PPM1AR1_M1A_Pos            (0U)
10736 #define DCMIPP_P1PPM1AR1_M1A_Msk            (0xFFFFFFFFUL << DCMIPP_P1PPM1AR1_M1A_Pos)       /*!< 0xFFFFFFFF */
10737 #define DCMIPP_P1PPM1AR1_M1A                DCMIPP_P1PPM1AR1_M1A_Msk                        /*!< Memory1 address */
10738 
10739 /***************  Bit definition for DCMIPP_P1PPM1AR2 register  ***************/
10740 #define DCMIPP_P1PPM1AR2_M1A_Pos            (0U)
10741 #define DCMIPP_P1PPM1AR2_M1A_Msk            (0xFFFFFFFFUL << DCMIPP_P1PPM1AR2_M1A_Pos)       /*!< 0xFFFFFFFF */
10742 #define DCMIPP_P1PPM1AR2_M1A                DCMIPP_P1PPM1AR2_M1A_Msk                        /*!< Memory1 address */
10743 
10744 /***************  Bit definition for DCMIPP_P1PPM1PR register  ****************/
10745 #define DCMIPP_P1PPM1PR_PITCH_Pos           (0U)
10746 #define DCMIPP_P1PPM1PR_PITCH_Msk           (0x7FFFUL << DCMIPP_P1PPM1PR_PITCH_Pos)          /*!< 0x00007FFF */
10747 #define DCMIPP_P1PPM1PR_PITCH               DCMIPP_P1PPM1PR_PITCH_Msk                       /*!< Number of bytes between the address of two consecutive lines */
10748 
10749 /***************  Bit definition for DCMIPP_P1STM1AR register  ****************/
10750 #define DCMIPP_P1STM1AR_M1A_Pos             (0U)
10751 #define DCMIPP_P1STM1AR_M1A_Msk             (0x7FFFUL << DCMIPP_P1STM1AR_M1A_Pos)           /*!< 0xFFFFFFFF */
10752 #define DCMIPP_P1STM1AR_M1A                 DCMIPP_P1STM1AR_M1A_Msk                         /*!< status Memory1 address register */
10753 
10754 /***************  Bit definition for DCMIPP_P1PPM2AR1 register  ***************/
10755 #define DCMIPP_P1PPM2AR1_M2A_Pos            (0U)
10756 #define DCMIPP_P1PPM2AR1_M2A_Msk            (0xFFFFFFFFUL << DCMIPP_P1PPM2AR1_M2A_Pos)       /*!< 0xFFFFFFFF */
10757 #define DCMIPP_P1PPM2AR1_M2A                DCMIPP_P1PPM2AR1_M2A_Msk                        /*!< Memory2 address register 1*/
10758 
10759 /***************  Bit definition for DCMIPP_P1PPM2AR2 register  ***************/
10760 #define DCMIPP_P1PPM2AR2_M2A_Pos            (0U)
10761 #define DCMIPP_P1PPM2AR2_M2A_Msk            (0xFFFFFFFFUL << DCMIPP_P1PPM2AR2_M2A_Pos)       /*!< 0xFFFFFFFF */
10762 #define DCMIPP_P1PPM2AR2_M2A                DCMIPP_P1PPM2AR2_M2A_Msk                        /*!< Memory2 address register 2 */
10763 
10764 /***************  Bit definition for DCMIPP_P1STM2AR register  ****************/
10765 #define DCMIPP_P1STM2AR_M2A_Pos             (0U)
10766 #define DCMIPP_P1STM2AR_M2A_Msk             (0xFFFFFFFFUL << DCMIPP_P1STM2AR_M2A_Pos)       /*!< 0xFFFFFFFF */
10767 #define DCMIPP_P1STM2AR_M2A                 DCMIPP_P1STM2AR_M2A_Msk                         /*!< status Memory2 address register */
10768 
10769 /*****************  Bit definition for DCMIPP_P1IER register  *****************/
10770 #define DCMIPP_P1IER_LINEIE_Pos             (0U)
10771 #define DCMIPP_P1IER_LINEIE_Msk             (0x1UL << DCMIPP_P1IER_LINEIE_Pos)               /*!< 0x00000001 */
10772 #define DCMIPP_P1IER_LINEIE                 DCMIPP_P1IER_LINEIE_Msk                         /*!< Multi-line capture completed interrupt enable */
10773 #define DCMIPP_P1IER_FRAMEIE_Pos            (1U)
10774 #define DCMIPP_P1IER_FRAMEIE_Msk            (0x1UL << DCMIPP_P1IER_FRAMEIE_Pos)              /*!< 0x00000002 */
10775 #define DCMIPP_P1IER_FRAMEIE                DCMIPP_P1IER_FRAMEIE_Msk                        /*!< Frame capture completed interrupt enable */
10776 #define DCMIPP_P1IER_VSYNCIE_Pos            (2U)
10777 #define DCMIPP_P1IER_VSYNCIE_Msk            (0x1UL << DCMIPP_P1IER_VSYNCIE_Pos)              /*!< 0x00000004 */
10778 #define DCMIPP_P1IER_VSYNCIE                DCMIPP_P1IER_VSYNCIE_Msk                        /*!< VSYNC interrupt enable */
10779 #define DCMIPP_P1IER_OVRIE_Pos              (7U)
10780 #define DCMIPP_P1IER_OVRIE_Msk              (0x1UL << DCMIPP_P1IER_OVRIE_Pos)                /*!< 0x00000080 */
10781 #define DCMIPP_P1IER_OVRIE                  DCMIPP_P1IER_OVRIE_Msk                          /*!< Overrun interrupt enable */
10782 
10783 /*****************  Bit definition for DCMIPP_P1SR register  ******************/
10784 #define DCMIPP_P1SR_LINEF_Pos               (0U)
10785 #define DCMIPP_P1SR_LINEF_Msk               (0x1UL << DCMIPP_P1SR_LINEF_Pos)                 /*!< 0x00000001 */
10786 #define DCMIPP_P1SR_LINEF                   DCMIPP_P1SR_LINEF_Msk                           /*!< Multi-line capture completed raw interrupt status */
10787 #define DCMIPP_P1SR_FRAMEF_Pos              (1U)
10788 #define DCMIPP_P1SR_FRAMEF_Msk              (0x1UL << DCMIPP_P1SR_FRAMEF_Pos)                /*!< 0x00000002 */
10789 #define DCMIPP_P1SR_FRAMEF                  DCMIPP_P1SR_FRAMEF_Msk                          /*!< Frame capture completed raw interrupt status */
10790 #define DCMIPP_P1SR_VSYNCF_Pos              (2U)
10791 #define DCMIPP_P1SR_VSYNCF_Msk              (0x1UL << DCMIPP_P1SR_VSYNCF_Pos)                /*!< 0x00000004 */
10792 #define DCMIPP_P1SR_VSYNCF                  DCMIPP_P1SR_VSYNCF_Msk                          /*!< VSYNC raw interrupt status */
10793 #define DCMIPP_P1SR_OVRF_Pos                (7U)
10794 #define DCMIPP_P1SR_OVRF_Msk                (0x1UL << DCMIPP_P1SR_OVRF_Pos)                  /*!< 0x00000080 */
10795 #define DCMIPP_P1SR_OVRF                    DCMIPP_P1SR_OVRF_Msk                            /*!< Overrun raw interrupt status */
10796 #define DCMIPP_P1SR_LSTLINE_Pos             (16U)
10797 #define DCMIPP_P1SR_LSTLINE_Msk             (0x1UL << DCMIPP_P1SR_LSTLINE_Pos)               /*!< 0x00010000 */
10798 #define DCMIPP_P1SR_LSTLINE                 DCMIPP_P1SR_LSTLINE_Msk                         /*!< Last line LSB bit, sampled at frame capture complete event */
10799 #define DCMIPP_P1SR_LSTFRM_Pos              (17U)
10800 #define DCMIPP_P1SR_LSTFRM_Msk              (0x1UL << DCMIPP_P1SR_LSTFRM_Pos)                /*!< 0x00020000 */
10801 #define DCMIPP_P1SR_LSTFRM                  DCMIPP_P1SR_LSTFRM_Msk                          /*!< Last frame LSB bit, sampled at frame capture complete event */
10802 #define DCMIPP_P1SR_CPTACT_Pos              (23U)
10803 #define DCMIPP_P1SR_CPTACT_Msk              (0x1UL << DCMIPP_P1SR_CPTACT_Pos)                /*!< 0x00800000 */
10804 #define DCMIPP_P1SR_CPTACT                  DCMIPP_P1SR_CPTACT_Msk                          /*!< Capture immediate status */
10805 
10806 /*****************  Bit definition for DCMIPP_P1FCR register  *****************/
10807 #define DCMIPP_P1FCR_CLINEF_Pos             (0U)
10808 #define DCMIPP_P1FCR_CLINEF_Msk             (0x1UL << DCMIPP_P1FCR_CLINEF_Pos)               /*!< 0x00000001 */
10809 #define DCMIPP_P1FCR_CLINEF                 DCMIPP_P1FCR_CLINEF_Msk                         /*!< Multi-line capture complete interrupt status clear */
10810 #define DCMIPP_P1FCR_CFRAMEF_Pos            (1U)
10811 #define DCMIPP_P1FCR_CFRAMEF_Msk            (0x1UL << DCMIPP_P1FCR_CFRAMEF_Pos)              /*!< 0x00000002 */
10812 #define DCMIPP_P1FCR_CFRAMEF                DCMIPP_P1FCR_CFRAMEF_Msk                        /*!< Frame capture complete interrupt status clear */
10813 #define DCMIPP_P1FCR_CVSYNCF_Pos            (2U)
10814 #define DCMIPP_P1FCR_CVSYNCF_Msk            (0x1UL << DCMIPP_P1FCR_CVSYNCF_Pos)              /*!< 0x00000004 */
10815 #define DCMIPP_P1FCR_CVSYNCF                DCMIPP_P1FCR_CVSYNCF_Msk                        /*!< Vertical synchronization interrupt status clear */
10816 #define DCMIPP_P1FCR_COVRF_Pos              (7U)
10817 #define DCMIPP_P1FCR_COVRF_Msk              (0x1UL << DCMIPP_P1FCR_COVRF_Pos)                /*!< 0x00000080 */
10818 #define DCMIPP_P1FCR_COVRF                  DCMIPP_P1FCR_COVRF_Msk                          /*!< Overrun interrupt status clear */
10819 
10820 /****************  Bit definition for DCMIPP_P1CFSCR register  ****************/
10821 #define DCMIPP_P1CFSCR_DTIDA_Pos            (0U)
10822 #define DCMIPP_P1CFSCR_DTIDA_Msk            (0x3FUL << DCMIPP_P1CFSCR_DTIDA_Pos)             /*!< 0x0000003F */
10823 #define DCMIPP_P1CFSCR_DTIDA                DCMIPP_P1CFSCR_DTIDA_Msk                        /*!< Current Data type ID A */
10824 #define DCMIPP_P1CFSCR_DTIDB_Pos            (8U)
10825 #define DCMIPP_P1CFSCR_DTIDB_Msk            (0x3FUL << DCMIPP_P1CFSCR_DTIDB_Pos)             /*!< 0x00003F00 */
10826 #define DCMIPP_P1CFSCR_DTIDB                DCMIPP_P1CFSCR_DTIDB_Msk                        /*!< Current Data type ID B */
10827 #define DCMIPP_P1CFSCR_DTMODE_Pos           (16U)
10828 #define DCMIPP_P1CFSCR_DTMODE_Msk           (0x3UL << DCMIPP_P1CFSCR_DTMODE_Pos)             /*!< 0x00030000 */
10829 #define DCMIPP_P1CFSCR_DTMODE               DCMIPP_P1CFSCR_DTMODE_Msk                       /*!< Flow selection mode */
10830 #define DCMIPP_P1CFSCR_PIPEDIFF_Pos         (18U)
10831 #define DCMIPP_P1CFSCR_PIPEDIFF_Msk         (0x1UL << DCMIPP_P1CFSCR_PIPEDIFF_Pos)           /*!< 0x00040000 */
10832 #define DCMIPP_P1CFSCR_PIPEDIFF             DCMIPP_P1CFSCR_PIPEDIFF_Msk                     /*!< Current differentiates Pipe2 vs */
10833 #define DCMIPP_P1CFSCR_VC_Pos               (19U)
10834 #define DCMIPP_P1CFSCR_VC_Msk               (0x3UL << DCMIPP_P1CFSCR_VC_Pos)                 /*!< 0x00180000 */
10835 #define DCMIPP_P1CFSCR_VC                   DCMIPP_P1CFSCR_VC_Msk                           /*!< Current flow selection mode */
10836 #define DCMIPP_P1CFSCR_FDTF_Pos             (24U)
10837 #define DCMIPP_P1CFSCR_FDTF_Msk             (0x3FUL << DCMIPP_P1CFSCR_FDTF_Pos)              /*!< 0x3F000000 */
10838 #define DCMIPP_P1CFSCR_FDTF                 DCMIPP_P1CFSCR_FDTF_Msk                         /*!< Current force Data type format */
10839 #define DCMIPP_P1CFSCR_FDTFEN_Pos           (30U)
10840 #define DCMIPP_P1CFSCR_FDTFEN_Msk           (0x1UL << DCMIPP_P1CFSCR_FDTFEN_Pos)             /*!< 0x40000000 */
10841 #define DCMIPP_P1CFSCR_FDTFEN               DCMIPP_P1CFSCR_FDTFEN_Msk                       /*!< Current force Data type format enable */
10842 #define DCMIPP_P1CFSCR_PIPEN_Pos            (31U)
10843 #define DCMIPP_P1CFSCR_PIPEN_Msk            (0x1UL << DCMIPP_P1CFSCR_PIPEN_Pos)              /*!< 0x80000000 */
10844 #define DCMIPP_P1CFSCR_PIPEN                DCMIPP_P1CFSCR_PIPEN_Msk                        /*!< Current activation of PipeN */
10845 
10846 /***************  Bit definition for DCMIPP_P1CBPRCR register  ****************/
10847 #define DCMIPP_P1CBPRCR_ENABLE_Pos          (0U)
10848 #define DCMIPP_P1CBPRCR_ENABLE_Msk          (0x1UL << DCMIPP_P1CBPRCR_ENABLE_Pos)            /*!< 0x00000001 */
10849 #define DCMIPP_P1CBPRCR_ENABLE              DCMIPP_P1CBPRCR_ENABLE_Msk                      /*!< Current status of enable bit */
10850 #define DCMIPP_P1CBPRCR_STRENGTH_Pos        (1U)
10851 #define DCMIPP_P1CBPRCR_STRENGTH_Msk        (0x7UL << DCMIPP_P1CBPRCR_STRENGTH_Pos)          /*!< 0x0000000E */
10852 #define DCMIPP_P1CBPRCR_STRENGTH            DCMIPP_P1CBPRCR_STRENGTH_Msk                    /*!< Current strength (aggressivity) of the bad pixel detection: */
10853 
10854 /***************  Bit definition for DCMIPP_P1CBLCCR register  ****************/
10855 #define DCMIPP_P1CBLCCR_ENABLE_Pos          (0U)
10856 #define DCMIPP_P1CBLCCR_ENABLE_Msk          (0x1UL << DCMIPP_P1CBLCCR_ENABLE_Pos)            /*!< 0x00000001 */
10857 #define DCMIPP_P1CBLCCR_ENABLE              DCMIPP_P1CBLCCR_ENABLE_Msk                      /*!< For current black level calibration */
10858 #define DCMIPP_P1CBLCCR_BLCB_Pos            (8U)
10859 #define DCMIPP_P1CBLCCR_BLCB_Msk            (0xFFUL << DCMIPP_P1CBLCCR_BLCB_Pos)             /*!< 0x0000FF00 */
10860 #define DCMIPP_P1CBLCCR_BLCB                DCMIPP_P1CBLCCR_BLCB_Msk                        /*!< Current black level calibration - Blue */
10861 #define DCMIPP_P1CBLCCR_BLCG_Pos            (16U)
10862 #define DCMIPP_P1CBLCCR_BLCG_Msk            (0xFFUL << DCMIPP_P1CBLCCR_BLCG_Pos)             /*!< 0x00FF0000 */
10863 #define DCMIPP_P1CBLCCR_BLCG                DCMIPP_P1CBLCCR_BLCG_Msk                        /*!< Current black level calibration - Green */
10864 #define DCMIPP_P1CBLCCR_BLCR_Pos            (24U)
10865 #define DCMIPP_P1CBLCCR_BLCR_Msk            (0xFFUL << DCMIPP_P1CBLCCR_BLCR_Pos)             /*!< 0xFF000000 */
10866 #define DCMIPP_P1CBLCCR_BLCR                DCMIPP_P1CBLCCR_BLCR_Msk                        /*!< Current black level calibration - Red */
10867 
10868 /***************  Bit definition for DCMIPP_P1CEXCR1 register  ****************/
10869 #define DCMIPP_P1CEXCR1_ENABLE_Pos          (0U)
10870 #define DCMIPP_P1CEXCR1_ENABLE_Msk          (0x1UL << DCMIPP_P1CEXCR1_ENABLE_Pos)            /*!< 0x00000001 */
10871 #define DCMIPP_P1CEXCR1_ENABLE              DCMIPP_P1CEXCR1_ENABLE_Msk                      /*!< for exposure control (multiplication and shift) */
10872 #define DCMIPP_P1CEXCR1_MULTR_Pos           (20U)
10873 #define DCMIPP_P1CEXCR1_MULTR_Msk           (0xFFUL << DCMIPP_P1CEXCR1_MULTR_Pos)            /*!< 0x0FF00000 */
10874 #define DCMIPP_P1CEXCR1_MULTR               DCMIPP_P1CEXCR1_MULTR_Msk                       /*!< Current exposure multiplier - Red */
10875 #define DCMIPP_P1CEXCR1_SHFR_Pos            (28U)
10876 #define DCMIPP_P1CEXCR1_SHFR_Msk            (0x7UL << DCMIPP_P1CEXCR1_SHFR_Pos)              /*!< 0x70000000 */
10877 #define DCMIPP_P1CEXCR1_SHFR                DCMIPP_P1CEXCR1_SHFR_Msk                        /*!< Current exposure shift - Red */
10878 
10879 /***************  Bit definition for DCMIPP_P1CEXCR2 register  ****************/
10880 #define DCMIPP_P1CEXCR2_MULTB_Pos           (4U)
10881 #define DCMIPP_P1CEXCR2_MULTB_Msk           (0xFFUL << DCMIPP_P1CEXCR2_MULTB_Pos)            /*!< 0x00000FF0 */
10882 #define DCMIPP_P1CEXCR2_MULTB               DCMIPP_P1CEXCR2_MULTB_Msk                       /*!< Current exposure multiplier - Blue */
10883 #define DCMIPP_P1CEXCR2_SHFB_Pos            (12U)
10884 #define DCMIPP_P1CEXCR2_SHFB_Msk            (0x7UL << DCMIPP_P1CEXCR2_SHFB_Pos)              /*!< 0x00007000 */
10885 #define DCMIPP_P1CEXCR2_SHFB                DCMIPP_P1CEXCR2_SHFB_Msk                        /*!< Current exposure shift - Blue */
10886 #define DCMIPP_P1CEXCR2_MULTG_Pos           (20U)
10887 #define DCMIPP_P1CEXCR2_MULTG_Msk           (0xFFUL << DCMIPP_P1CEXCR2_MULTG_Pos)            /*!< 0x0FF00000 */
10888 #define DCMIPP_P1CEXCR2_MULTG               DCMIPP_P1CEXCR2_MULTG_Msk                       /*!< Current exposure multiplier - Green */
10889 #define DCMIPP_P1CEXCR2_SHFG_Pos            (28U)
10890 #define DCMIPP_P1CEXCR2_SHFG_Msk            (0x7UL << DCMIPP_P1CEXCR2_SHFG_Pos)              /*!< 0x70000000 */
10891 #define DCMIPP_P1CEXCR2_SHFG                DCMIPP_P1CEXCR2_SHFG_Msk                        /*!< Current exposure shift - Green */
10892 
10893 /***************  Bit definition for DCMIPP_P1CST1CR register  ****************/
10894 #define DCMIPP_P1CST1CR_ENABLE_Pos          (0U)
10895 #define DCMIPP_P1CST1CR_ENABLE_Msk          (0x1UL << DCMIPP_P1CST1CR_ENABLE_Pos)            /*!< 0x00000001 */
10896 #define DCMIPP_P1CST1CR_ENABLE              DCMIPP_P1CST1CR_ENABLE_Msk                      /*!< Current enable bit value */
10897 #define DCMIPP_P1CST1CR_BINS_Pos            (2U)
10898 #define DCMIPP_P1CST1CR_BINS_Msk            (0x3UL << DCMIPP_P1CST1CR_BINS_Pos)              /*!< 0x0000000C */
10899 #define DCMIPP_P1CST1CR_BINS                DCMIPP_P1CST1CR_BINS_Msk                        /*!< Current bin definition */
10900 #define DCMIPP_P1CST1CR_SRC_Pos             (4U)
10901 #define DCMIPP_P1CST1CR_SRC_Msk             (0x7UL << DCMIPP_P1CST1CR_SRC_Pos)               /*!< 0x00000070 */
10902 #define DCMIPP_P1CST1CR_SRC                 DCMIPP_P1CST1CR_SRC_Msk                         /*!< Current source of statistics */
10903 #define DCMIPP_P1CST1CR_MODE_Pos            (7U)
10904 #define DCMIPP_P1CST1CR_MODE_Msk            (0x1UL << DCMIPP_P1CST1CR_MODE_Pos)              /*!< 0x00000080 */
10905 #define DCMIPP_P1CST1CR_MODE                DCMIPP_P1CST1CR_MODE_Msk                        /*!< Current statistics mode */
10906 #define DCMIPP_P1CST1CR_ACCU_Pos            (8U)
10907 #define DCMIPP_P1CST1CR_ACCU_Msk            (0xFFFFFFUL << DCMIPP_P1CST1CR_ACCU_Pos)         /*!< 0xFFFFFF00 */
10908 #define DCMIPP_P1CST1CR_ACCU                DCMIPP_P1CST1CR_ACCU_Msk                        /*!< Current accumulation result, divided by 256 */
10909 
10910 /***************  Bit definition for DCMIPP_P1CST2CR register  ****************/
10911 #define DCMIPP_P1CST2CR_ENABLE_Pos          (0U)
10912 #define DCMIPP_P1CST2CR_ENABLE_Msk          (0x1UL << DCMIPP_P1CST2CR_ENABLE_Pos)            /*!< 0x00000001 */
10913 #define DCMIPP_P1CST2CR_ENABLE              DCMIPP_P1CST2CR_ENABLE_Msk                      /*!<  */
10914 #define DCMIPP_P1CST2CR_BINS_Pos            (2U)
10915 #define DCMIPP_P1CST2CR_BINS_Msk            (0x3UL << DCMIPP_P1CST2CR_BINS_Pos)              /*!< 0x0000000C */
10916 #define DCMIPP_P1CST2CR_BINS                DCMIPP_P1CST2CR_BINS_Msk                        /*!< Bin definition */
10917 #define DCMIPP_P1CST2CR_SRC_Pos             (4U)
10918 #define DCMIPP_P1CST2CR_SRC_Msk             (0x7UL << DCMIPP_P1CST2CR_SRC_Pos)               /*!< 0x00000070 */
10919 #define DCMIPP_P1CST2CR_SRC                 DCMIPP_P1CST2CR_SRC_Msk                         /*!< source of stat */
10920 #define DCMIPP_P1CST2CR_MODE_Pos            (7U)
10921 #define DCMIPP_P1CST2CR_MODE_Msk            (0x1UL << DCMIPP_P1CST2CR_MODE_Pos)              /*!< 0x00000080 */
10922 #define DCMIPP_P1CST2CR_MODE                DCMIPP_P1CST2CR_MODE_Msk                        /*!< statistics mode */
10923 #define DCMIPP_P1CST2CR_ACCU_Pos            (8U)
10924 #define DCMIPP_P1CST2CR_ACCU_Msk            (0xFFFFFFUL << DCMIPP_P1CST2CR_ACCU_Pos)         /*!< 0xFFFFFF00 */
10925 #define DCMIPP_P1CST2CR_ACCU                DCMIPP_P1CST2CR_ACCU_Msk                        /*!< Accumulation result, divided by 256 */
10926 
10927 /***************  Bit definition for DCMIPP_P1CST3CR register  ****************/
10928 #define DCMIPP_P1CST3CR_ENABLE_Pos          (0U)
10929 #define DCMIPP_P1CST3CR_ENABLE_Msk          (0x1UL << DCMIPP_P1CST3CR_ENABLE_Pos)            /*!< 0x00000001 */
10930 #define DCMIPP_P1CST3CR_ENABLE              DCMIPP_P1CST3CR_ENABLE_Msk                      /*!<  */
10931 #define DCMIPP_P1CST3CR_BINS_Pos            (2U)
10932 #define DCMIPP_P1CST3CR_BINS_Msk            (0x3UL << DCMIPP_P1CST3CR_BINS_Pos)              /*!< 0x0000000C */
10933 #define DCMIPP_P1CST3CR_BINS                DCMIPP_P1CST3CR_BINS_Msk                        /*!< Bin definition */
10934 #define DCMIPP_P1CST3CR_SRC_Pos             (4U)
10935 #define DCMIPP_P1CST3CR_SRC_Msk             (0x7UL << DCMIPP_P1CST3CR_SRC_Pos)               /*!< 0x00000070 */
10936 #define DCMIPP_P1CST3CR_SRC                 DCMIPP_P1CST3CR_SRC_Msk                         /*!< Statistics source */
10937 #define DCMIPP_P1CST3CR_MODE_Pos            (7U)
10938 #define DCMIPP_P1CST3CR_MODE_Msk            (0x1UL << DCMIPP_P1CST3CR_MODE_Pos)              /*!< 0x00000080 */
10939 #define DCMIPP_P1CST3CR_MODE                DCMIPP_P1CST3CR_MODE_Msk                        /*!< Statistics mode */
10940 #define DCMIPP_P1CST3CR_ACCU_Pos            (8U)
10941 #define DCMIPP_P1CST3CR_ACCU_Msk            (0xFFFFFFUL << DCMIPP_P1CST3CR_ACCU_Pos)         /*!< 0xFFFFFF00 */
10942 #define DCMIPP_P1CST3CR_ACCU                DCMIPP_P1CST3CR_ACCU_Msk                        /*!< Accumulation result, divided by 256 */
10943 
10944 /***************  Bit definition for DCMIPP_P1CSTSTR register  ****************/
10945 #define DCMIPP_P1CSTSTR_HSTART_Pos          (0U)
10946 #define DCMIPP_P1CSTSTR_HSTART_Msk          (0xFFFUL << DCMIPP_P1CSTSTR_HSTART_Pos)          /*!< 0x00000FFF */
10947 #define DCMIPP_P1CSTSTR_HSTART              DCMIPP_P1CSTSTR_HSTART_Msk                      /*!< Current horizontal start, from 0 to 4094 pixels wide */
10948 #define DCMIPP_P1CSTSTR_VSTART_Pos          (16U)
10949 #define DCMIPP_P1CSTSTR_VSTART_Msk          (0xFFFUL << DCMIPP_P1CSTSTR_VSTART_Pos)          /*!< 0x0FFF0000 */
10950 #define DCMIPP_P1CSTSTR_VSTART              DCMIPP_P1CSTSTR_VSTART_Msk                      /*!< Current vertical start, from 0 to 4094 pixels high */
10951 
10952 /***************  Bit definition for DCMIPP_P1CSTSZR register  ****************/
10953 #define DCMIPP_P1CSTSZR_HSIZE_Pos           (0U)
10954 #define DCMIPP_P1CSTSZR_HSIZE_Msk           (0xFFFUL << DCMIPP_P1CSTSZR_HSIZE_Pos)           /*!< 0x00000FFF */
10955 #define DCMIPP_P1CSTSZR_HSIZE               DCMIPP_P1CSTSZR_HSIZE_Msk                       /*!< Current horizontal size, from 0 to 4094 pixels wide */
10956 #define DCMIPP_P1CSTSZR_VSIZE_Pos           (16U)
10957 #define DCMIPP_P1CSTSZR_VSIZE_Msk           (0xFFFUL << DCMIPP_P1CSTSZR_VSIZE_Pos)           /*!< 0x0FFF0000 */
10958 #define DCMIPP_P1CSTSZR_VSIZE               DCMIPP_P1CSTSZR_VSIZE_Msk                       /*!< Current vertical size, from 0 to 4094 pixels high */
10959 #define DCMIPP_P1CSTSZR_CROPEN_Pos          (31U)
10960 #define DCMIPP_P1CSTSZR_CROPEN_Msk          (0x1UL << DCMIPP_P1CSTSZR_CROPEN_Pos)            /*!< 0x80000000 */
10961 #define DCMIPP_P1CSTSZR_CROPEN              DCMIPP_P1CSTSZR_CROPEN_Msk                      /*!< Current CROPEN bit value */
10962 
10963 /****************  Bit definition for DCMIPP_P1CCCCR register  ****************/
10964 #define DCMIPP_P1CCCCR_ENABLE_Pos           (0U)
10965 #define DCMIPP_P1CCCCR_ENABLE_Msk           (0x1UL << DCMIPP_P1CCCCR_ENABLE_Pos)             /*!< 0x00000001 */
10966 #define DCMIPP_P1CCCCR_ENABLE               DCMIPP_P1CCCCR_ENABLE_Msk                       /*!< This bit indicates the current value applied */
10967 #define DCMIPP_P1CCCCR_TYPE_Pos             (1U)
10968 #define DCMIPP_P1CCCCR_TYPE_Msk             (0x1UL << DCMIPP_P1CCCCR_TYPE_Pos)               /*!< 0x00000002 */
10969 #define DCMIPP_P1CCCCR_TYPE                 DCMIPP_P1CCCCR_TYPE_Msk                         /*!< output samples type used while CLAMP is activated */
10970 #define DCMIPP_P1CCCCR_CLAMP_Pos            (2U)
10971 #define DCMIPP_P1CCCCR_CLAMP_Msk            (0x1UL << DCMIPP_P1CCCCR_CLAMP_Pos)              /*!< 0x00000004 */
10972 #define DCMIPP_P1CCCCR_CLAMP                DCMIPP_P1CCCCR_CLAMP_Msk                        /*!< Clamp the output samples */
10973 
10974 /***************  Bit definition for DCMIPP_P1CCCRR1 register  ****************/
10975 #define DCMIPP_P1CCCRR1_RR_Pos              (0U)
10976 #define DCMIPP_P1CCCRR1_RR_Msk              (0x7FFUL << DCMIPP_P1CCCRR1_RR_Pos)              /*!< 0x000007FF */
10977 #define DCMIPP_P1CCCRR1_RR                  DCMIPP_P1CCCRR1_RR_Msk                          /*!< Current coefficient row 1 column 1 of the matrix */
10978 #define DCMIPP_P1CCCRR1_RG_Pos              (16U)
10979 #define DCMIPP_P1CCCRR1_RG_Msk              (0x7FFUL << DCMIPP_P1CCCRR1_RG_Pos)              /*!< 0x07FF0000 */
10980 #define DCMIPP_P1CCCRR1_RG                  DCMIPP_P1CCCRR1_RG_Msk                          /*!< Current coefficient row 1 column 2 of the matrix */
10981 
10982 /***************  Bit definition for DCMIPP_P1CCCRR2 register  ****************/
10983 #define DCMIPP_P1CCCRR2_RB_Pos              (0U)
10984 #define DCMIPP_P1CCCRR2_RB_Msk              (0x7FFUL << DCMIPP_P1CCCRR2_RB_Pos)              /*!< 0x000007FF */
10985 #define DCMIPP_P1CCCRR2_RB                  DCMIPP_P1CCCRR2_RB_Msk                          /*!< Current coefficient row 1 column 3 of the matrix */
10986 #define DCMIPP_P1CCCRR2_RA_Pos              (16U)
10987 #define DCMIPP_P1CCCRR2_RA_Msk              (0x3FFUL << DCMIPP_P1CCCRR2_RA_Pos)              /*!< 0x03FF0000 */
10988 #define DCMIPP_P1CCCRR2_RA                  DCMIPP_P1CCCRR2_RA_Msk                          /*!< Current coefficient row 1 of the added column (signed integer value) */
10989 
10990 /***************  Bit definition for DCMIPP_P1CCCGR1 register  ****************/
10991 #define DCMIPP_P1CCCGR1_GR_Pos              (0U)
10992 #define DCMIPP_P1CCCGR1_GR_Msk              (0x7FFUL << DCMIPP_P1CCCGR1_GR_Pos)              /*!< 0x000007FF */
10993 #define DCMIPP_P1CCCGR1_GR                  DCMIPP_P1CCCGR1_GR_Msk                          /*!< Current coefficient row 2 column 1 of the matrix */
10994 #define DCMIPP_P1CCCGR1_GG_Pos              (16U)
10995 #define DCMIPP_P1CCCGR1_GG_Msk              (0x7FFUL << DCMIPP_P1CCCGR1_GG_Pos)              /*!< 0x07FF0000 */
10996 #define DCMIPP_P1CCCGR1_GG                  DCMIPP_P1CCCGR1_GG_Msk                          /*!< Current coefficient row 2 column 2 of the matrix */
10997 
10998 /***************  Bit definition for DCMIPP_P1CCCGR2 register  ****************/
10999 #define DCMIPP_P1CCCGR2_GB_Pos              (0U)
11000 #define DCMIPP_P1CCCGR2_GB_Msk              (0x7FFUL << DCMIPP_P1CCCGR2_GB_Pos)              /*!< 0x000007FF */
11001 #define DCMIPP_P1CCCGR2_GB                  DCMIPP_P1CCCGR2_GB_Msk                          /*!< Current coefficient row 2 column 3 of the matrix */
11002 #define DCMIPP_P1CCCGR2_GA_Pos              (16U)
11003 #define DCMIPP_P1CCCGR2_GA_Msk              (0x3FFUL << DCMIPP_P1CCCGR2_GA_Pos)              /*!< 0x03FF0000 */
11004 #define DCMIPP_P1CCCGR2_GA                  DCMIPP_P1CCCGR2_GA_Msk                          /*!< Current coefficient row 2 of the added column (signed integer value) */
11005 
11006 /***************  Bit definition for DCMIPP_P1CCCBR1 register  ****************/
11007 #define DCMIPP_P1CCCBR1_BR_Pos              (0U)
11008 #define DCMIPP_P1CCCBR1_BR_Msk              (0x7FFUL << DCMIPP_P1CCCBR1_BR_Pos)              /*!< 0x000007FF */
11009 #define DCMIPP_P1CCCBR1_BR                  DCMIPP_P1CCCBR1_BR_Msk                          /*!< Current coefficient row 3 column 1 of the matrix */
11010 #define DCMIPP_P1CCCBR1_BG_Pos              (16U)
11011 #define DCMIPP_P1CCCBR1_BG_Msk              (0x7FFUL << DCMIPP_P1CCCBR1_BG_Pos)              /*!< 0x07FF0000 */
11012 #define DCMIPP_P1CCCBR1_BG                  DCMIPP_P1CCCBR1_BG_Msk                          /*!< Current coefficient row 3 column 2 of the matrix */
11013 
11014 /***************  Bit definition for DCMIPP_P1CCCBR2 register  ****************/
11015 #define DCMIPP_P1CCCBR2_BB_Pos              (0U)
11016 #define DCMIPP_P1CCCBR2_BB_Msk              (0x7FFUL << DCMIPP_P1CCCBR2_BB_Pos)              /*!< 0x000007FF */
11017 #define DCMIPP_P1CCCBR2_BB                  DCMIPP_P1CCCBR2_BB_Msk                          /*!< Current coefficient row 3 column 3 of the matrix */
11018 #define DCMIPP_P1CCCBR2_BA_Pos              (16U)
11019 #define DCMIPP_P1CCCBR2_BA_Msk              (0x3FFUL << DCMIPP_P1CCCBR2_BA_Pos)              /*!< 0x03FF0000 */
11020 #define DCMIPP_P1CCCBR2_BA                  DCMIPP_P1CCCBR2_BA_Msk                          /*!< Current coefficient row 3 of the added column (signed integer value) */
11021 
11022 /***************  Bit definition for DCMIPP_P1CCTCR1 register  ****************/
11023 #define DCMIPP_P1CCTCR1_ENABLE_Pos          (0U)
11024 #define DCMIPP_P1CCTCR1_ENABLE_Msk          (0x1UL << DCMIPP_P1CCTCR1_ENABLE_Pos)            /*!< 0x00000001 */
11025 #define DCMIPP_P1CCTCR1_ENABLE              DCMIPP_P1CCTCR1_ENABLE_Msk                      /*!< Current ENABLE bit value */
11026 #define DCMIPP_P1CCTCR1_LUM0_Pos            (9U)
11027 #define DCMIPP_P1CCTCR1_LUM0_Msk            (0x3FUL << DCMIPP_P1CCTCR1_LUM0_Pos)             /*!< 0x00007E00 */
11028 #define DCMIPP_P1CCTCR1_LUM0                DCMIPP_P1CCTCR1_LUM0_Msk                        /*!< Current luminance increase for input luminance of 0 (increase is idle with LUMx = 16) */
11029 
11030 /***************  Bit definition for DCMIPP_P1CCTCR2 register  ****************/
11031 #define DCMIPP_P1CCTCR2_LUM4_Pos            (1U)
11032 #define DCMIPP_P1CCTCR2_LUM4_Msk            (0x3FUL << DCMIPP_P1CCTCR2_LUM4_Pos)             /*!< 0x0000007E */
11033 #define DCMIPP_P1CCTCR2_LUM4                DCMIPP_P1CCTCR2_LUM4_Msk                        /*!< Current luminance increase for input luminance of 128 (increase is idle with LUMx = 16) */
11034 #define DCMIPP_P1CCTCR2_LUM3_Pos            (9U)
11035 #define DCMIPP_P1CCTCR2_LUM3_Msk            (0x3FUL << DCMIPP_P1CCTCR2_LUM3_Pos)             /*!< 0x00007E00 */
11036 #define DCMIPP_P1CCTCR2_LUM3                DCMIPP_P1CCTCR2_LUM3_Msk                        /*!< Current luminance increase for input luminance of 96 (increase is idle with LUMx = 16) */
11037 #define DCMIPP_P1CCTCR2_LUM2_Pos            (17U)
11038 #define DCMIPP_P1CCTCR2_LUM2_Msk            (0x3FUL << DCMIPP_P1CCTCR2_LUM2_Pos)             /*!< 0x007E0000 */
11039 #define DCMIPP_P1CCTCR2_LUM2                DCMIPP_P1CCTCR2_LUM2_Msk                        /*!< Current luminance increase for input luminance of 64 (increase is idle with LUMx = 16) */
11040 #define DCMIPP_P1CCTCR2_LUM1_Pos            (25U)
11041 #define DCMIPP_P1CCTCR2_LUM1_Msk            (0x3FUL << DCMIPP_P1CCTCR2_LUM1_Pos)             /*!< 0x7E000000 */
11042 #define DCMIPP_P1CCTCR2_LUM1                DCMIPP_P1CCTCR2_LUM1_Msk                        /*!< Current luminance increase for input luminance of 32 (increase is idle with LUMx = 16) */
11043 
11044 /***************  Bit definition for DCMIPP_P1CCTCR3 register  ****************/
11045 #define DCMIPP_P1CCTCR3_LUM8_Pos            (1U)
11046 #define DCMIPP_P1CCTCR3_LUM8_Msk            (0x3FUL << DCMIPP_P1CCTCR3_LUM8_Pos)             /*!< 0x0000007E */
11047 #define DCMIPP_P1CCTCR3_LUM8                DCMIPP_P1CCTCR3_LUM8_Msk                        /*!< Luminance increase for input luminance of 256 (increase is idle with LUMx = 16) */
11048 #define DCMIPP_P1CCTCR3_LUM7_Pos            (9U)
11049 #define DCMIPP_P1CCTCR3_LUM7_Msk            (0x3FUL << DCMIPP_P1CCTCR3_LUM7_Pos)             /*!< 0x00007E00 */
11050 #define DCMIPP_P1CCTCR3_LUM7                DCMIPP_P1CCTCR3_LUM7_Msk                        /*!< Luminance increase for input luminance of 224 (increase is idle with LUMx = 16) */
11051 #define DCMIPP_P1CCTCR3_LUM6_Pos            (17U)
11052 #define DCMIPP_P1CCTCR3_LUM6_Msk            (0x3FUL << DCMIPP_P1CCTCR3_LUM6_Pos)             /*!< 0x007E0000 */
11053 #define DCMIPP_P1CCTCR3_LUM6                DCMIPP_P1CCTCR3_LUM6_Msk                        /*!< Luminance increase for input luminance of 192 (increase is idle with LUMx = 16) */
11054 #define DCMIPP_P1CCTCR3_LUM5_Pos            (25U)
11055 #define DCMIPP_P1CCTCR3_LUM5_Msk            (0x3FUL << DCMIPP_P1CCTCR3_LUM5_Pos)             /*!< 0x7E000000 */
11056 #define DCMIPP_P1CCTCR3_LUM5                DCMIPP_P1CCTCR3_LUM5_Msk                        /*!< Luminance increase for input luminance of 160 (increase is idle with LUMx = 16) */
11057 
11058 /***************  Bit definition for DCMIPP_P1CFCTCR register  ****************/
11059 #define DCMIPP_P1CFCTCR_FRATE_Pos           (0U)
11060 #define DCMIPP_P1CFCTCR_FRATE_Msk           (0x3UL << DCMIPP_P1CFCTCR_FRATE_Pos)             /*!< 0x00000003 */
11061 #define DCMIPP_P1CFCTCR_FRATE               DCMIPP_P1CFCTCR_FRATE_Msk                       /*!< Frame capture rate control */
11062 #define DCMIPP_P1CFCTCR_CPTMODE_Pos         (2U)
11063 #define DCMIPP_P1CFCTCR_CPTMODE_Msk         (0x1UL << DCMIPP_P1CFCTCR_CPTMODE_Pos)           /*!< 0x00000004 */
11064 #define DCMIPP_P1CFCTCR_CPTMODE             DCMIPP_P1CFCTCR_CPTMODE_Msk                     /*!< Capture mode */
11065 #define DCMIPP_P1CFCTCR_CPTREQ_Pos          (3U)
11066 #define DCMIPP_P1CFCTCR_CPTREQ_Msk          (0x1UL << DCMIPP_P1CFCTCR_CPTREQ_Pos)            /*!< 0x00000008 */
11067 #define DCMIPP_P1CFCTCR_CPTREQ              DCMIPP_P1CFCTCR_CPTREQ_Msk                      /*!< Capture requested */
11068 
11069 /***************  Bit definition for DCMIPP_P1CCRSTR register  ****************/
11070 #define DCMIPP_P1CCRSTR_HSTART_Pos          (0U)
11071 #define DCMIPP_P1CCRSTR_HSTART_Msk          (0xFFFUL << DCMIPP_P1CCRSTR_HSTART_Pos)          /*!< 0x00000FFF */
11072 #define DCMIPP_P1CCRSTR_HSTART              DCMIPP_P1CCRSTR_HSTART_Msk                      /*!< Current horizontal start, from 0 to 4094 pixels wide */
11073 #define DCMIPP_P1CCRSTR_VSTART_Pos          (16U)
11074 #define DCMIPP_P1CCRSTR_VSTART_Msk          (0xFFFUL << DCMIPP_P1CCRSTR_VSTART_Pos)          /*!< 0x0FFF0000 */
11075 #define DCMIPP_P1CCRSTR_VSTART              DCMIPP_P1CCRSTR_VSTART_Msk                      /*!< Current vertical start, from 0 to 4094 pixels high */
11076 
11077 /***************  Bit definition for DCMIPP_P1CCRSZR register  ****************/
11078 #define DCMIPP_P1CCRSZR_HSIZE_Pos           (0U)
11079 #define DCMIPP_P1CCRSZR_HSIZE_Msk           (0xFFFUL << DCMIPP_P1CCRSZR_HSIZE_Pos)           /*!< 0x00000FFF */
11080 #define DCMIPP_P1CCRSZR_HSIZE               DCMIPP_P1CCRSZR_HSIZE_Msk                       /*!< Current horizontal size, from 0 to 4094 pixels wide */
11081 #define DCMIPP_P1CCRSZR_VSIZE_Pos           (16U)
11082 #define DCMIPP_P1CCRSZR_VSIZE_Msk           (0xFFFUL << DCMIPP_P1CCRSZR_VSIZE_Pos)           /*!< 0x0FFF0000 */
11083 #define DCMIPP_P1CCRSZR_VSIZE               DCMIPP_P1CCRSZR_VSIZE_Msk                       /*!< Current vertical size, from 0 to 4094 pixels high */
11084 #define DCMIPP_P1CCRSZR_ENABLE_Pos          (31U)
11085 #define DCMIPP_P1CCRSZR_ENABLE_Msk          (0x1UL << DCMIPP_P1CCRSZR_ENABLE_Pos)            /*!< 0x80000000 */
11086 #define DCMIPP_P1CCRSZR_ENABLE              DCMIPP_P1CCRSZR_ENABLE_Msk                      /*!< Current ENABLE bit value */
11087 
11088 /****************  Bit definition for DCMIPP_P1CDCCR register  *****************/
11089 #define DCMIPP_P1CDCCR_ENABLE_Pos           (0U)
11090 #define DCMIPP_P1CDCCR_ENABLE_Msk           (0x1UL << DCMIPP_P1CDCCR_ENABLE_Pos)            /*!< 0x00000001 */
11091 #define DCMIPP_P1CDCCR_ENABLE               DCMIPP_P1CDCCR_ENABLE_Msk                       /*!< Decimation enable */
11092 #define DCMIPP_P1CDCCR_HDEC_Pos             (1U)
11093 #define DCMIPP_P1CDCCR_HDEC_Msk             (0x3UL << DCMIPP_P1CDCCR_HDEC_Pos)               /*!< 0x00000006 */
11094 #define DCMIPP_P1CDCCR_HDEC                 DCMIPP_P1CDCCR_HDEC_Msk                         /*!< Horizontal decimation ratio */
11095 #define DCMIPP_P1CDCCR_VDEC_Pos             (3U)
11096 #define DCMIPP_P1CDCCR_VDEC_Msk             (0x3UL << DCMIPP_P1CDCCR_VDEC_Pos)               /*!< 0x00000018 */
11097 #define DCMIPP_P1CDCCR_VDEC                 DCMIPP_P1CDCCR_VDEC_Msk                         /*!< Vertical decimation ratio */
11098 
11099 /****************  Bit definition for DCMIPP_P1CDSCR register  ****************/
11100 #define DCMIPP_P1CDSCR_HDIV_Pos             (0U)
11101 #define DCMIPP_P1CDSCR_HDIV_Msk             (0x3FFUL << DCMIPP_P1CDSCR_HDIV_Pos)             /*!< 0x000003FF */
11102 #define DCMIPP_P1CDSCR_HDIV                 DCMIPP_P1CDSCR_HDIV_Msk                         /*!< Current horizontal division factor, from 128 (8x) to 1023 (1x) */
11103 #define DCMIPP_P1CDSCR_VDIV_Pos             (16U)
11104 #define DCMIPP_P1CDSCR_VDIV_Msk             (0x3FFUL << DCMIPP_P1CDSCR_VDIV_Pos)             /*!< 0x03FF0000 */
11105 #define DCMIPP_P1CDSCR_VDIV                 DCMIPP_P1CDSCR_VDIV_Msk                         /*!< Current vertical division factor, from 128 (8x) to 1023 (1x) */
11106 #define DCMIPP_P1CDSCR_ENABLE_Pos           (31U)
11107 #define DCMIPP_P1CDSCR_ENABLE_Msk           (0x1UL << DCMIPP_P1CDSCR_ENABLE_Pos)             /*!< 0x80000000 */
11108 #define DCMIPP_P1CDSCR_ENABLE               DCMIPP_P1CDSCR_ENABLE_Msk                       /*!< Current value of the bit ENABLE */
11109 
11110 /**************  Bit definition for DCMIPP_P1CDSRTIOR register  ***************/
11111 #define DCMIPP_P1CDSRTIOR_HRATIO_Pos        (0U)
11112 #define DCMIPP_P1CDSRTIOR_HRATIO_Msk        (0xFFFFUL << DCMIPP_P1CDSRTIOR_HRATIO_Pos)       /*!< 0x0000FFFF */
11113 #define DCMIPP_P1CDSRTIOR_HRATIO            DCMIPP_P1CDSRTIOR_HRATIO_Msk                    /*!< Current horizontal ratio, from 8192 (1x) to 65535 (8x) */
11114 #define DCMIPP_P1CDSRTIOR_VRATIO_Pos        (16U)
11115 #define DCMIPP_P1CDSRTIOR_VRATIO_Msk        (0xFFFFUL << DCMIPP_P1CDSRTIOR_VRATIO_Pos)       /*!< 0xFFFF0000 */
11116 #define DCMIPP_P1CDSRTIOR_VRATIO            DCMIPP_P1CDSRTIOR_VRATIO_Msk                    /*!< Current vertical ratio, from 8192 (1x) to 65535 (8x) */
11117 
11118 /***************  Bit definition for DCMIPP_P1CDSSZR register  ****************/
11119 #define DCMIPP_P1CDSSZR_HSIZE_Pos           (0U)
11120 #define DCMIPP_P1CDSSZR_HSIZE_Msk           (0xFFFUL << DCMIPP_P1CDSSZR_HSIZE_Pos)           /*!< 0x00000FFF */
11121 #define DCMIPP_P1CDSSZR_HSIZE               DCMIPP_P1CDSSZR_HSIZE_Msk                       /*!< Current horizontal size, from 0 to 4094 pixels wide */
11122 #define DCMIPP_P1CDSSZR_VSIZE_Pos           (16U)
11123 #define DCMIPP_P1CDSSZR_VSIZE_Msk           (0xFFFUL << DCMIPP_P1CDSSZR_VSIZE_Pos)           /*!< 0x0FFF0000 */
11124 #define DCMIPP_P1CDSSZR_VSIZE               DCMIPP_P1CDSSZR_VSIZE_Msk                       /*!< Current vertical size, from 0 to 4094 pixels high */
11125 
11126 /****************  Bit definition for DCMIPP_P1CPPCR register  ****************/
11127 #define DCMIPP_P1CPPCR_FORMAT_Pos           (0U)
11128 #define DCMIPP_P1CPPCR_FORMAT_Msk           (0xFUL << DCMIPP_P1CPPCR_FORMAT_Pos)             /*!< 0x0000000F */
11129 #define DCMIPP_P1CPPCR_FORMAT               DCMIPP_P1CPPCR_FORMAT_Msk                       /*!< Memory format */
11130 #define DCMIPP_P1CPPCR_SWAPRB_Pos           (4U)
11131 #define DCMIPP_P1CPPCR_SWAPRB_Msk           (0x1UL << DCMIPP_P1CPPCR_SWAPRB_Pos)             /*!< 0x00000010 */
11132 #define DCMIPP_P1CPPCR_SWAPRB               DCMIPP_P1CPPCR_SWAPRB_Msk                       /*!< Swaps R-vs-B components if RGB, and U-vs-V components if YUV */
11133 #define DCMIPP_P1CPPCR_LINEMULT_Pos         (13U)
11134 #define DCMIPP_P1CPPCR_LINEMULT_Msk         (0x7UL << DCMIPP_P1CPPCR_LINEMULT_Pos)           /*!< 0x0000E000 */
11135 #define DCMIPP_P1CPPCR_LINEMULT             DCMIPP_P1CPPCR_LINEMULT_Msk                     /*!< Amount of capture completed lines for LINE Event and Interrupt */
11136 
11137 /**************  Bit definition for DCMIPP_P1CPPM0AR1 register  ***************/
11138 #define DCMIPP_P1CPPM0AR1_M0A_Pos           (0U)
11139 #define DCMIPP_P1CPPM0AR1_M0A_Msk           (0xFFFFFFFFUL << DCMIPP_P1CPPM0AR1_M0A_Pos)      /*!< 0xFFFFFFFF */
11140 #define DCMIPP_P1CPPM0AR1_M0A               DCMIPP_P1CPPM0AR1_M0A_Msk                       /*!< Memory0 address */
11141 
11142 /***************  Bit definition for DCMIPP_P1CPPM0PR register  ***************/
11143 #define DCMIPP_P1CPPM0PR_PITCH_Pos          (0U)
11144 #define DCMIPP_P1CPPM0PR_PITCH_Msk          (0x7FFFUL << DCMIPP_P1CPPM0PR_PITCH_Pos)         /*!< 0x00007FFF */
11145 #define DCMIPP_P1CPPM0PR_PITCH              DCMIPP_P1CPPM0PR_PITCH_Msk                      /*!< Number of bytes between the address of two consecutive lines */
11146 
11147 /**************  Bit definition for DCMIPP_P1CPPM1AR1 register  ***************/
11148 #define DCMIPP_P1CPPM1AR1_M1A_Pos           (0U)
11149 #define DCMIPP_P1CPPM1AR1_M1A_Msk           (0xFFFFFFFFUL << DCMIPP_P1CPPM1AR1_M1A_Pos)      /*!< 0xFFFFFFFF */
11150 #define DCMIPP_P1CPPM1AR1_M1A               DCMIPP_P1CPPM1AR1_M1A_Msk                       /*!< Memory1 address */
11151 
11152 /***************  Bit definition for DCMIPP_P1CPPM1PR register  ***************/
11153 #define DCMIPP_P1CPPM1PR_PITCH_Pos          (0U)
11154 #define DCMIPP_P1CPPM1PR_PITCH_Msk          (0x7FFFUL << DCMIPP_P1CPPM1PR_PITCH_Pos)         /*!< 0x00007FFF */
11155 #define DCMIPP_P1CPPM1PR_PITCH              DCMIPP_P1CPPM1PR_PITCH_Msk                      /*!< Number of bytes between the address of two consecutive lines */
11156 
11157 /**************  Bit definition for DCMIPP_P1CPPM2AR1 register  ***************/
11158 #define DCMIPP_P1CPPM2AR1_M2A_Pos           (0U)
11159 #define DCMIPP_P1CPPM2AR1_M2A_Msk           (0xFFFFFFFFUL << DCMIPP_P1CPPM2AR1_M2A_Pos)      /*!< 0xFFFFFFFF */
11160 #define DCMIPP_P1CPPM2AR1_M2A               DCMIPP_P1CPPM2AR1_M2A_Msk                       /*!< Memory 2 address */
11161 
11162 /****************  Bit definition for DCMIPP_P2FSCR register  *****************/
11163 #define DCMIPP_P2FSCR_DTIDA_Pos             (0U)
11164 #define DCMIPP_P2FSCR_DTIDA_Msk             (0x3FUL << DCMIPP_P2FSCR_DTIDA_Pos)              /*!< 0x0000003F */
11165 #define DCMIPP_P2FSCR_DTIDA                 DCMIPP_P2FSCR_DTIDA_Msk                         /*!< Data type ID */
11166 #define DCMIPP_P2FSCR_VC_Pos                (19U)
11167 #define DCMIPP_P2FSCR_VC_Msk                (0x3UL << DCMIPP_P2FSCR_VC_Pos)                  /*!< 0x00180000 */
11168 #define DCMIPP_P2FSCR_VC                    DCMIPP_P2FSCR_VC_Msk                            /*!< Flow selection mode */
11169 #define DCMIPP_P2FSCR_FDTF_Pos              (24U)
11170 #define DCMIPP_P2FSCR_FDTF_Msk              (0x3FUL << DCMIPP_P2FSCR_FDTF_Pos)               /*!< 0x3F000000 */
11171 #define DCMIPP_P2FSCR_FDTF                  DCMIPP_P2FSCR_FDTF_Msk                          /*!< Force Data type format */
11172 #define DCMIPP_P2FSCR_FDTFEN_Pos            (30U)
11173 #define DCMIPP_P2FSCR_FDTFEN_Msk            (0x1UL << DCMIPP_P2FSCR_FDTFEN_Pos)              /*!< 0x40000000 */
11174 #define DCMIPP_P2FSCR_FDTFEN                DCMIPP_P2FSCR_FDTFEN_Msk                        /*!< Force Data type format enable */
11175 #define DCMIPP_P2FSCR_PIPEN_Pos             (31U)
11176 #define DCMIPP_P2FSCR_PIPEN_Msk             (0x1UL << DCMIPP_P2FSCR_PIPEN_Pos)               /*!< 0x80000000 */
11177 #define DCMIPP_P2FSCR_PIPEN                 DCMIPP_P2FSCR_PIPEN_Msk                         /*!< Activation of PipeN */
11178 
11179 /****************  Bit definition for DCMIPP_P2FCTCR register  ****************/
11180 #define DCMIPP_P2FCTCR_FRATE_Pos            (0U)
11181 #define DCMIPP_P2FCTCR_FRATE_Msk            (0x3UL << DCMIPP_P2FCTCR_FRATE_Pos)              /*!< 0x00000003 */
11182 #define DCMIPP_P2FCTCR_FRATE                DCMIPP_P2FCTCR_FRATE_Msk                        /*!< Frame capture rate control */
11183 #define DCMIPP_P2FCTCR_CPTMODE_Pos          (2U)
11184 #define DCMIPP_P2FCTCR_CPTMODE_Msk          (0x1UL << DCMIPP_P2FCTCR_CPTMODE_Pos)            /*!< 0x00000004 */
11185 #define DCMIPP_P2FCTCR_CPTMODE              DCMIPP_P2FCTCR_CPTMODE_Msk                      /*!< Capture mode */
11186 #define DCMIPP_P2FCTCR_CPTREQ_Pos           (3U)
11187 #define DCMIPP_P2FCTCR_CPTREQ_Msk           (0x1UL << DCMIPP_P2FCTCR_CPTREQ_Pos)             /*!< 0x00000008 */
11188 #define DCMIPP_P2FCTCR_CPTREQ               DCMIPP_P2FCTCR_CPTREQ_Msk                       /*!< Capture requested */
11189 
11190 /****************  Bit definition for DCMIPP_P2CRSTR register  ****************/
11191 #define DCMIPP_P2CRSTR_HSTART_Pos           (0U)
11192 #define DCMIPP_P2CRSTR_HSTART_Msk           (0xFFFUL << DCMIPP_P2CRSTR_HSTART_Pos)           /*!< 0x00000FFF */
11193 #define DCMIPP_P2CRSTR_HSTART               DCMIPP_P2CRSTR_HSTART_Msk                       /*!< Horizontal start, from 0 to 4094 pixels wide */
11194 #define DCMIPP_P2CRSTR_VSTART_Pos           (16U)
11195 #define DCMIPP_P2CRSTR_VSTART_Msk           (0xFFFUL << DCMIPP_P2CRSTR_VSTART_Pos)           /*!< 0x0FFF0000 */
11196 #define DCMIPP_P2CRSTR_VSTART               DCMIPP_P2CRSTR_VSTART_Msk                       /*!< Vertical start, from 0 to 4094 pixels high */
11197 
11198 /****************  Bit definition for DCMIPP_P2CRSZR register  ****************/
11199 #define DCMIPP_P2CRSZR_HSIZE_Pos            (0U)
11200 #define DCMIPP_P2CRSZR_HSIZE_Msk            (0xFFFUL << DCMIPP_P2CRSZR_HSIZE_Pos)            /*!< 0x00000FFF */
11201 #define DCMIPP_P2CRSZR_HSIZE                DCMIPP_P2CRSZR_HSIZE_Msk                        /*!< Horizontal size, from 0 to 4094 pixels wide */
11202 #define DCMIPP_P2CRSZR_VSIZE_Pos            (16U)
11203 #define DCMIPP_P2CRSZR_VSIZE_Msk            (0xFFFUL << DCMIPP_P2CRSZR_VSIZE_Pos)            /*!< 0x0FFF0000 */
11204 #define DCMIPP_P2CRSZR_VSIZE                DCMIPP_P2CRSZR_VSIZE_Msk                        /*!< Vertical size, from 0 to 4094 pixels high */
11205 #define DCMIPP_P2CRSZR_ENABLE_Pos           (31U)
11206 #define DCMIPP_P2CRSZR_ENABLE_Msk           (0x1UL << DCMIPP_P2CRSZR_ENABLE_Pos)             /*!< 0x80000000 */
11207 #define DCMIPP_P2CRSZR_ENABLE               DCMIPP_P2CRSZR_ENABLE_Msk                       /*!<  */
11208 
11209 /****************  Bit definition for DCMIPP_P2DCCR register  *****************/
11210 #define DCMIPP_P2DCCR_ENABLE_Pos            (0U)
11211 #define DCMIPP_P2DCCR_ENABLE_Msk            (0x1UL << DCMIPP_P2DCCR_ENABLE_Pos)             /*!< 0x00000001 */
11212 #define DCMIPP_P2DCCR_ENABLE                DCMIPP_P2DCCR_ENABLE_Msk                        /*!< Decimation enable */
11213 #define DCMIPP_P2DCCR_HDEC_Pos              (1U)
11214 #define DCMIPP_P2DCCR_HDEC_Msk              (0x3UL << DCMIPP_P2DCCR_HDEC_Pos)               /*!< 0x00000006 */
11215 #define DCMIPP_P2DCCR_HDEC                  DCMIPP_P2DCCR_HDEC_Msk                          /*!< Horizontal decimation ratio */
11216 #define DCMIPP_P2DCCR_VDEC_Pos              (3U)
11217 #define DCMIPP_P2DCCR_VDEC_Msk              (0x3UL << DCMIPP_P2DCCR_VDEC_Pos)               /*!< 0x00000018 */
11218 #define DCMIPP_P2DCCR_VDEC                  DCMIPP_P2DCCR_VDEC_Msk                          /*!< Vertical decimation ratio */
11219 
11220 /****************  Bit definition for DCMIPP_P2DSCR register  *****************/
11221 #define DCMIPP_P2DSCR_HDIV_Pos              (0U)
11222 #define DCMIPP_P2DSCR_HDIV_Msk              (0x3FFUL << DCMIPP_P2DSCR_HDIV_Pos)              /*!< 0x000003FF */
11223 #define DCMIPP_P2DSCR_HDIV                  DCMIPP_P2DSCR_HDIV_Msk                          /*!< Horizontal division factor, from 128 (8x) to 1023 (1x) */
11224 #define DCMIPP_P2DSCR_VDIV_Pos              (16U)
11225 #define DCMIPP_P2DSCR_VDIV_Msk              (0x3FFUL << DCMIPP_P2DSCR_VDIV_Pos)              /*!< 0x03FF0000 */
11226 #define DCMIPP_P2DSCR_VDIV                  DCMIPP_P2DSCR_VDIV_Msk                          /*!< Vertical division factor, from 128 (8x) to 1023 (1x) */
11227 #define DCMIPP_P2DSCR_ENABLE_Pos            (31U)
11228 #define DCMIPP_P2DSCR_ENABLE_Msk            (0x1UL << DCMIPP_P2DSCR_ENABLE_Pos)              /*!< 0x80000000 */
11229 #define DCMIPP_P2DSCR_ENABLE                DCMIPP_P2DSCR_ENABLE_Msk                        /*!<  */
11230 
11231 /***************  Bit definition for DCMIPP_P2DSRTIOR register  ***************/
11232 #define DCMIPP_P2DSRTIOR_HRATIO_Pos         (0U)
11233 #define DCMIPP_P2DSRTIOR_HRATIO_Msk         (0xFFFFUL << DCMIPP_P2DSRTIOR_HRATIO_Pos)        /*!< 0x0000FFFF */
11234 #define DCMIPP_P2DSRTIOR_HRATIO             DCMIPP_P2DSRTIOR_HRATIO_Msk                     /*!< Horizontal ratio, from 8192 (1x) to 65535 (8x) */
11235 #define DCMIPP_P2DSRTIOR_VRATIO_Pos         (16U)
11236 #define DCMIPP_P2DSRTIOR_VRATIO_Msk         (0xFFFFUL << DCMIPP_P2DSRTIOR_VRATIO_Pos)        /*!< 0xFFFF0000 */
11237 #define DCMIPP_P2DSRTIOR_VRATIO             DCMIPP_P2DSRTIOR_VRATIO_Msk                     /*!< Vertical ratio, from 8192 (1x) to 65535 (8x) */
11238 
11239 /****************  Bit definition for DCMIPP_P2DSSZR register  ****************/
11240 #define DCMIPP_P2DSSZR_HSIZE_Pos            (0U)
11241 #define DCMIPP_P2DSSZR_HSIZE_Msk            (0xFFFUL << DCMIPP_P2DSSZR_HSIZE_Pos)            /*!< 0x00000FFF */
11242 #define DCMIPP_P2DSSZR_HSIZE                DCMIPP_P2DSSZR_HSIZE_Msk                        /*!< Horizontal size, from 0 to 4094 pixels wide */
11243 #define DCMIPP_P2DSSZR_VSIZE_Pos            (16U)
11244 #define DCMIPP_P2DSSZR_VSIZE_Msk            (0xFFFUL << DCMIPP_P2DSSZR_VSIZE_Pos)            /*!< 0x0FFF0000 */
11245 #define DCMIPP_P2DSSZR_VSIZE                DCMIPP_P2DSSZR_VSIZE_Msk                        /*!< Vertical size, from 0 to 4094 pixels high */
11246 
11247 /****************  Bit definition for DCMIPP_P2GMCR register  *****************/
11248 #define DCMIPP_P2GMCR_ENABLE_Pos            (0U)
11249 #define DCMIPP_P2GMCR_ENABLE_Msk            (0x1UL << DCMIPP_P2GMCR_ENABLE_Pos)              /*!< 0x00000001 */
11250 #define DCMIPP_P2GMCR_ENABLE                DCMIPP_P2GMCR_ENABLE_Msk                        /*!<  */
11251 
11252 /***************  Bit definition for DCMIPP_P2CMRICR register  ***************/
11253 #define DCMIPP_P2CMRICR_ROILSZ_Pos          (0U)
11254 #define DCMIPP_P2CMRICR_ROILSZ_Msk          (0x3UL << DCMIPP_P2CMRICR_ROILSZ_Pos)           /*!< 0x00000003 */
11255 #define DCMIPP_P2CMRICR_ROILSZ              DCMIPP_P2CMRICR_ROILSZ_Msk                      /*!< Region of interest line size width */
11256 #define DCMIPP_P2CMRICR_ROI1EN_Pos          (16U)
11257 #define DCMIPP_P2CMRICR_ROI1EN_Msk          (0x1UL << DCMIPP_P2CMRICR_ROI1EN_Pos)           /*!< 0x00010000 */
11258 #define DCMIPP_P2CMRICR_ROI1EN              DCMIPP_P2CMRICR_ROI1EN_Msk                      /*!< Region Of Interest 1 Enable */
11259 #define DCMIPP_P2CMRICR_ROI2EN_Pos          (17U)
11260 #define DCMIPP_P2CMRICR_ROI2EN_Msk          (0x1UL << DCMIPP_P2CMRICR_ROI2EN_Pos)           /*!< 0x00020000 */
11261 #define DCMIPP_P2CMRICR_ROI2EN              DCMIPP_P2CMRICR_ROI2EN_Msk                      /*!< Region Of Interest 2 Enable */
11262 #define DCMIPP_P2CMRICR_ROI3EN_Pos          (18U)
11263 #define DCMIPP_P2CMRICR_ROI3EN_Msk          (0x1UL << DCMIPP_P2CMRICR_ROI3EN_Pos)           /*!< 0x00040000 */
11264 #define DCMIPP_P2CMRICR_ROI3EN              DCMIPP_P2CMRICR_ROI3EN_Msk                      /*!< Region Of Interest 3 Enable */
11265 #define DCMIPP_P2CMRICR_ROI4EN_Pos          (19U)
11266 #define DCMIPP_P2CMRICR_ROI4EN_Msk          (0x1UL << DCMIPP_P2CMRICR_ROI4EN_Pos)           /*!< 0x00080000 */
11267 #define DCMIPP_P2CMRICR_ROI4EN              DCMIPP_P2CMRICR_ROI4EN_Msk                      /*!< Region Of Interest 4 Enable */
11268 #define DCMIPP_P2CMRICR_ROI5EN_Pos          (20U)
11269 #define DCMIPP_P2CMRICR_ROI5EN_Msk          (0x1UL << DCMIPP_P2CMRICR_ROI5EN_Pos)           /*!< 0x00100000 */
11270 #define DCMIPP_P2CMRICR_ROI5EN              DCMIPP_P2CMRICR_ROI5EN_Msk                      /*!< Region Of Interest 5 Enable */
11271 #define DCMIPP_P2CMRICR_ROI6EN_Pos          (21U)
11272 #define DCMIPP_P2CMRICR_ROI6EN_Msk          (0x1UL << DCMIPP_P2CMRICR_ROI6EN_Pos)           /*!< 0x00200000 */
11273 #define DCMIPP_P2CMRICR_ROI6EN              DCMIPP_P2CMRICR_ROI6EN_Msk                      /*!< Region Of Interest 6 Enable */
11274 #define DCMIPP_P2CMRICR_ROI7EN_Pos          (22U)
11275 #define DCMIPP_P2CMRICR_ROI7EN_Msk          (0x1UL << DCMIPP_P2CMRICR_ROI7EN_Pos)           /*!< 0x00400000 */
11276 #define DCMIPP_P2CMRICR_ROI7EN              DCMIPP_P2CMRICR_ROI7EN_Msk                      /*!< Region Of Interest 7 Enable */
11277 #define DCMIPP_P2CMRICR_ROI8EN_Pos          (23U)
11278 #define DCMIPP_P2CMRICR_ROI8EN_Msk          (0x1UL << DCMIPP_P2CMRICR_ROI8EN_Pos)           /*!< 0x00800000 */
11279 #define DCMIPP_P2CMRICR_ROI8EN              DCMIPP_P2CMRICR_ROI8EN_Msk                      /*!< Region Of Interest 8 Enable */
11280 
11281 /***************  Bit definition for DCMIPP_P2RIxCR1 register  ***************/
11282 #define DCMIPP_P2RIxCR1_HSTART_Pos          (0U)
11283 #define DCMIPP_P2RIxCR1_HSTART_Msk          (0xFFFUL << DCMIPP_P2RIxCR1_HSTART_Pos)        /*!< 0x00000FFF */
11284 #define DCMIPP_P2RIxCR1_HSTART              DCMIPP_P2RIxCR1_HSTART_Msk                     /*!< Horizontal start */
11285 #define DCMIPP_P2RIxCR1_CLB_Pos             (12U)
11286 #define DCMIPP_P2RIxCR1_CLB_Msk             (0x3UL << DCMIPP_P2RIxCR1_CLB_Pos)             /*!< 0x00003000 */
11287 #define DCMIPP_P2RIxCR1_CLB                 DCMIPP_P2RIxCR1_CLB_Msk                        /*!< Color line blue */
11288 #define DCMIPP_P2RIxCR1_CLG_Pos             (14U)
11289 #define DCMIPP_P2RIxCR1_CLG_Msk             (0x3UL << DCMIPP_P2RIxCR1_CLG_Pos)             /*!< 0x0000C000 */
11290 #define DCMIPP_P2RIxCR1_CLG                 DCMIPP_P2RIxCR1_CLG_Msk                        /*!< Color line green */
11291 #define DCMIPP_P2RIxCR1_VSTART_Pos          (16U)
11292 #define DCMIPP_P2RIxCR1_VSTART_Msk          (0xFFFUL << DCMIPP_P2RIxCR1_VSTART_Pos)        /*!< 0x0FFF0000 */
11293 #define DCMIPP_P2RIxCR1_VSTART              DCMIPP_P2RIxCR1_VSTART_Msk                     /*!< Vertical start */
11294 #define DCMIPP_P2RIxCR1_CLR_Pos             (28U)
11295 #define DCMIPP_P2RIxCR1_CLR_Msk             (0x3UL << DCMIPP_P2RIxCR1_CLR_Pos)             /*!< 0x30000000 */
11296 #define DCMIPP_P2RIxCR1_CLR                 DCMIPP_P2RIxCR1_CLR_Msk                        /*!< Color line red */
11297 
11298 /***************  Bit definition for DCMIPP_P2RIxCR2 register  ***************/
11299 #define DCMIPP_P2RIxCR2_VSIZE_Pos           (0U)
11300 #define DCMIPP_P2RIxCR2_VSIZE_Msk           (0xFFFUL << DCMIPP_P2RIxCR2_VSIZE_Pos)        /*!<  0x00000FFF */
11301 #define DCMIPP_P2RIxCR2_VSIZE               DCMIPP_P2RIxCR2_VSIZE_Msk                     /*!< Vertical Size */
11302 #define DCMIPP_P2RIxCR2_HSIZE_Pos           (16U)
11303 #define DCMIPP_P2RIxCR2_HSIZE_Msk           (0xFFFUL << DCMIPP_P2RIxCR2_HSIZE_Pos)        /*!<  0x07FF8000 */
11304 #define DCMIPP_P2RIxCR2_HSIZE               DCMIPP_P2RIxCR2_HSIZE_Msk                     /*!< Horizontal Size */
11305 
11306 /****************  Bit definition for DCMIPP_P2PPCR register  *****************/
11307 #define DCMIPP_P2PPCR_FORMAT_Pos            (0U)
11308 #define DCMIPP_P2PPCR_FORMAT_Msk            (0xFUL << DCMIPP_P2PPCR_FORMAT_Pos)              /*!< 0x0000000F */
11309 #define DCMIPP_P2PPCR_FORMAT                DCMIPP_P2PPCR_FORMAT_Msk                         /*!< Memory format (only coplanar formats are supported in Pipe2) */
11310 #define DCMIPP_P2PPCR_SWAPRB_Pos            (4U)
11311 #define DCMIPP_P2PPCR_SWAPRB_Msk            (0x1UL << DCMIPP_P2PPCR_SWAPRB_Pos)              /*!< 0x00000010 */
11312 #define DCMIPP_P2PPCR_SWAPRB                DCMIPP_P2PPCR_SWAPRB_Msk                         /*!< Swaps R-vs-B components if RGB, and if YUV, swaps U-vs-V components */
11313 #define DCMIPP_P2PPCR_LINEMULT_Pos          (13U)
11314 #define DCMIPP_P2PPCR_LINEMULT_Msk          (0x7UL << DCMIPP_P2PPCR_LINEMULT_Pos)            /*!< 0x0000E000 */
11315 #define DCMIPP_P2PPCR_LINEMULT              DCMIPP_P2PPCR_LINEMULT_Msk                       /*!< Amount of capture completed lines for LINE Event and Interrupt */
11316 #define DCMIPP_P2PPCR_DBM_Pos               (16U)
11317 #define DCMIPP_P2PPCR_DBM_Msk               (0x1UL << DCMIPP_P2PPCR_DBM_Pos)                 /*!< 0x00010000 */
11318 #define DCMIPP_P2PPCR_DBM                   DCMIPP_P2PPCR_DBM_Msk                            /*!< Double buffer mode */
11319 #define DCMIPP_P2PPCR_LMAWM_Pos             (17U)
11320 #define DCMIPP_P2PPCR_LMAWM_Msk             (0x7UL << DCMIPP_P2PPCR_LMAWM_Pos)               /*!< 0x000E0000 */
11321 #define DCMIPP_P2PPCR_LMAWM                 DCMIPP_P2PPCR_LMAWM_Msk                          /*!< Line multi address wrapping modulo */
11322 #define DCMIPP_P2PPCR_LMAWE_Pos             (20U)
11323 #define DCMIPP_P2PPCR_LMAWE_Msk             (0x7UL << DCMIPP_P2PPCR_LMAWE_Pos)               /*!< 0x00100000 */
11324 #define DCMIPP_P2PPCR_LMAWE                 DCMIPP_P2PPCR_LMAWE_Msk                          /*!< Line multi address wrapping enable */
11325 
11326 /***************  Bit definition for DCMIPP_P2PPM0AR1 register  ***************/
11327 #define DCMIPP_P2PPM0AR1_M0A_Pos            (0U)
11328 #define DCMIPP_P2PPM0AR1_M0A_Msk            (0xFFFFFFFFUL << DCMIPP_P2PPM0AR1_M0A_Pos)       /*!< 0xFFFFFFFF */
11329 #define DCMIPP_P2PPM0AR1_M0A                DCMIPP_P2PPM0AR1_M0A_Msk                        /*!< Memory0 address register 1 */
11330 
11331 /***************  Bit definition for DCMIPP_P2PPM0AR2 register  ***************/
11332 #define DCMIPP_P2PPM0AR2_M0A_Pos            (0U)
11333 #define DCMIPP_P2PPM0AR2_M0A_Msk            (0xFFFFFFFFUL << DCMIPP_P2PPM0AR2_M0A_Pos)       /*!< 0xFFFFFFFF */
11334 #define DCMIPP_P2PPM0AR2_M0A                DCMIPP_P2PPM0AR2_M0A_Msk                        /*!< Memory0 address register 2*/
11335 
11336 /***************  Bit definition for DCMIPP_P2PPM0PR register  ****************/
11337 #define DCMIPP_P2PPM0PR_PITCH_Pos           (0U)
11338 #define DCMIPP_P2PPM0PR_PITCH_Msk           (0x7FFFUL << DCMIPP_P2PPM0PR_PITCH_Pos)          /*!< 0x00007FFF */
11339 #define DCMIPP_P2PPM0PR_PITCH               DCMIPP_P2PPM0PR_PITCH_Msk                       /*!< Number of bytes between the address of two consecutive lines */
11340 
11341 /***************  Bit definition for DCMIPP_P2PPM0PR register  ****************/
11342 #define DCMIPP_P2STM0AR_Pos                 (0U)
11343 #define DCMIPP_P2STM0AR_Msk                 (0xFFFFFFFFUL << DCMIPP_P2STM0AR_Pos)           /*!< 0xFFFFFFFF */
11344 #define DCMIPP_P2STM0AR                     DCMIPP_P2STM0AR_Msk                             /*!< Pipe2 status Memory0 address register */
11345 
11346 /*****************  Bit definition for DCMIPP_P2IER register  *****************/
11347 #define DCMIPP_P2IER_LINEIE_Pos             (0U)
11348 #define DCMIPP_P2IER_LINEIE_Msk             (0x1UL << DCMIPP_P2IER_LINEIE_Pos)               /*!< 0x00000001 */
11349 #define DCMIPP_P2IER_LINEIE                 DCMIPP_P2IER_LINEIE_Msk                         /*!< Multi-line capture completed interrupt enable */
11350 #define DCMIPP_P2IER_FRAMEIE_Pos            (1U)
11351 #define DCMIPP_P2IER_FRAMEIE_Msk            (0x1UL << DCMIPP_P2IER_FRAMEIE_Pos)              /*!< 0x00000002 */
11352 #define DCMIPP_P2IER_FRAMEIE                DCMIPP_P2IER_FRAMEIE_Msk                        /*!< Frame capture completed interrupt enable */
11353 #define DCMIPP_P2IER_VSYNCIE_Pos            (2U)
11354 #define DCMIPP_P2IER_VSYNCIE_Msk            (0x1UL << DCMIPP_P2IER_VSYNCIE_Pos)              /*!< 0x00000004 */
11355 #define DCMIPP_P2IER_VSYNCIE                DCMIPP_P2IER_VSYNCIE_Msk                        /*!< VSYNC interrupt enable */
11356 #define DCMIPP_P2IER_OVRIE_Pos              (7U)
11357 #define DCMIPP_P2IER_OVRIE_Msk              (0x1UL << DCMIPP_P2IER_OVRIE_Pos)                /*!< 0x00000080 */
11358 #define DCMIPP_P2IER_OVRIE                  DCMIPP_P2IER_OVRIE_Msk                          /*!< Overrun interrupt enable */
11359 
11360 /*****************  Bit definition for DCMIPP_P2SR register  ******************/
11361 #define DCMIPP_P2SR_LINEF_Pos               (0U)
11362 #define DCMIPP_P2SR_LINEF_Msk               (0x1UL << DCMIPP_P2SR_LINEF_Pos)                 /*!< 0x00000001 */
11363 #define DCMIPP_P2SR_LINEF                   DCMIPP_P2SR_LINEF_Msk                           /*!< Multi-line capture completed raw interrupt status */
11364 #define DCMIPP_P2SR_FRAMEF_Pos              (1U)
11365 #define DCMIPP_P2SR_FRAMEF_Msk              (0x1UL << DCMIPP_P2SR_FRAMEF_Pos)                /*!< 0x00000002 */
11366 #define DCMIPP_P2SR_FRAMEF                  DCMIPP_P2SR_FRAMEF_Msk                          /*!< Frame capture completed raw interrupt status */
11367 #define DCMIPP_P2SR_VSYNCF_Pos              (2U)
11368 #define DCMIPP_P2SR_VSYNCF_Msk              (0x1UL << DCMIPP_P2SR_VSYNCF_Pos)                /*!< 0x00000004 */
11369 #define DCMIPP_P2SR_VSYNCF                  DCMIPP_P2SR_VSYNCF_Msk                          /*!< VSYNC raw interrupt status */
11370 #define DCMIPP_P2SR_OVRF_Pos                (7U)
11371 #define DCMIPP_P2SR_OVRF_Msk                (0x1UL << DCMIPP_P2SR_OVRF_Pos)                  /*!< 0x00000080 */
11372 #define DCMIPP_P2SR_OVRF                    DCMIPP_P2SR_OVRF_Msk                            /*!< Overrun raw interrupt status */
11373 #define DCMIPP_P2SR_LSTLINE_Pos             (16U)
11374 #define DCMIPP_P2SR_LSTLINE_Msk             (0x1UL << DCMIPP_P2SR_LSTLINE_Pos)               /*!< 0x00010000 */
11375 #define DCMIPP_P2SR_LSTLINE                 DCMIPP_P2SR_LSTLINE_Msk                         /*!< Last line LSB bit, sampled at frame capture complete event */
11376 #define DCMIPP_P2SR_LSTFRM_Pos              (17U)
11377 #define DCMIPP_P2SR_LSTFRM_Msk              (0x1UL << DCMIPP_P2SR_LSTFRM_Pos)                /*!< 0x00020000 */
11378 #define DCMIPP_P2SR_LSTFRM                  DCMIPP_P2SR_LSTFRM_Msk                          /*!< Last frame LSB bit, sampled at frame capture complete event */
11379 #define DCMIPP_P2SR_CPTACT_Pos              (23U)
11380 #define DCMIPP_P2SR_CPTACT_Msk              (0x1UL << DCMIPP_P2SR_CPTACT_Pos)                /*!< 0x00800000 */
11381 #define DCMIPP_P2SR_CPTACT                  DCMIPP_P2SR_CPTACT_Msk                          /*!< Capture immediate status */
11382 
11383 /*****************  Bit definition for DCMIPP_P2FCR register  *****************/
11384 #define DCMIPP_P2FCR_CLINEF_Pos             (0U)
11385 #define DCMIPP_P2FCR_CLINEF_Msk             (0x1UL << DCMIPP_P2FCR_CLINEF_Pos)               /*!< 0x00000001 */
11386 #define DCMIPP_P2FCR_CLINEF                 DCMIPP_P2FCR_CLINEF_Msk                         /*!< Multi-line capture complete interrupt status clear */
11387 #define DCMIPP_P2FCR_CFRAMEF_Pos            (1U)
11388 #define DCMIPP_P2FCR_CFRAMEF_Msk            (0x1UL << DCMIPP_P2FCR_CFRAMEF_Pos)              /*!< 0x00000002 */
11389 #define DCMIPP_P2FCR_CFRAMEF                DCMIPP_P2FCR_CFRAMEF_Msk                        /*!< Frame capture complete interrupt status clear */
11390 #define DCMIPP_P2FCR_CVSYNCF_Pos            (2U)
11391 #define DCMIPP_P2FCR_CVSYNCF_Msk            (0x1UL << DCMIPP_P2FCR_CVSYNCF_Pos)              /*!< 0x00000004 */
11392 #define DCMIPP_P2FCR_CVSYNCF                DCMIPP_P2FCR_CVSYNCF_Msk                        /*!< Vertical synchronization interrupt status clear */
11393 #define DCMIPP_P2FCR_COVRF_Pos              (7U)
11394 #define DCMIPP_P2FCR_COVRF_Msk              (0x1UL << DCMIPP_P2FCR_COVRF_Pos)                /*!< 0x00000080 */
11395 #define DCMIPP_P2FCR_COVRF                  DCMIPP_P2FCR_COVRF_Msk                          /*!< Overrun interrupt status clear */
11396 
11397 /****************  Bit definition for DCMIPP_P2CFSCR register  ****************/
11398 #define DCMIPP_P2CFSCR_DTID_Pos             (0U)
11399 #define DCMIPP_P2CFSCR_DTID_Msk             (0x3FUL << DCMIPP_P2CFSCR_DTID_Pos)              /*!< 0x0000003F */
11400 #define DCMIPP_P2CFSCR_DTID                 DCMIPP_P2CFSCR_DTID_Msk                         /*!< Current Data type ID */
11401 #define DCMIPP_P2CFSCR_VC_Pos               (19U)
11402 #define DCMIPP_P2CFSCR_VC_Msk               (0x3UL << DCMIPP_P2CFSCR_VC_Pos)                 /*!< 0x00180000 */
11403 #define DCMIPP_P2CFSCR_VC                   DCMIPP_P2CFSCR_VC_Msk                           /*!< Current flow selection mode */
11404 #define DCMIPP_P2CFSCR_FDTF_Pos             (24U)
11405 #define DCMIPP_P2CFSCR_FDTF_Msk             (0x3FUL << DCMIPP_P2CFSCR_FDTF_Pos)              /*!< 0x3F000000 */
11406 #define DCMIPP_P2CFSCR_FDTF                 DCMIPP_P2CFSCR_FDTF_Msk                         /*!< Current force Data type format */
11407 #define DCMIPP_P2CFSCR_FDTFEN_Pos           (30U)
11408 #define DCMIPP_P2CFSCR_FDTFEN_Msk           (0x1UL << DCMIPP_P2CFSCR_FDTFEN_Pos)             /*!< 0x40000000 */
11409 #define DCMIPP_P2CFSCR_FDTFEN               DCMIPP_P2CFSCR_FDTFEN_Msk                       /*!< Current force Data type format enable */
11410 #define DCMIPP_P2CFSCR_PIPEN_Pos            (31U)
11411 #define DCMIPP_P2CFSCR_PIPEN_Msk            (0x1UL << DCMIPP_P2CFSCR_PIPEN_Pos)              /*!< 0x80000000 */
11412 #define DCMIPP_P2CFSCR_PIPEN                DCMIPP_P2CFSCR_PIPEN_Msk                        /*!< Current activation of PipeN */
11413 
11414 /***************  Bit definition for DCMIPP_P2CFCTCR register  ****************/
11415 #define DCMIPP_P2CFCTCR_FRATE_Pos           (0U)
11416 #define DCMIPP_P2CFCTCR_FRATE_Msk           (0x3UL << DCMIPP_P2CFCTCR_FRATE_Pos)             /*!< 0x00000003 */
11417 #define DCMIPP_P2CFCTCR_FRATE               DCMIPP_P2CFCTCR_FRATE_Msk                       /*!< Frame capture rate control */
11418 #define DCMIPP_P2CFCTCR_CPTMODE_Pos         (2U)
11419 #define DCMIPP_P2CFCTCR_CPTMODE_Msk         (0x1UL << DCMIPP_P2CFCTCR_CPTMODE_Pos)           /*!< 0x00000004 */
11420 #define DCMIPP_P2CFCTCR_CPTMODE             DCMIPP_P2CFCTCR_CPTMODE_Msk                     /*!< Capture mode */
11421 #define DCMIPP_P2CFCTCR_CPTREQ_Pos          (3U)
11422 #define DCMIPP_P2CFCTCR_CPTREQ_Msk          (0x1UL << DCMIPP_P2CFCTCR_CPTREQ_Pos)            /*!< 0x00000008 */
11423 #define DCMIPP_P2CFCTCR_CPTREQ              DCMIPP_P2CFCTCR_CPTREQ_Msk                      /*!< Capture requested */
11424 
11425 /***************  Bit definition for DCMIPP_P2CCRSTR register  ****************/
11426 #define DCMIPP_P2CCRSTR_HSTART_Pos          (0U)
11427 #define DCMIPP_P2CCRSTR_HSTART_Msk          (0xFFFUL << DCMIPP_P2CCRSTR_HSTART_Pos)          /*!< 0x00000FFF */
11428 #define DCMIPP_P2CCRSTR_HSTART              DCMIPP_P2CCRSTR_HSTART_Msk                      /*!< Current horizontal start, from 0 to 4094 pixels wide */
11429 #define DCMIPP_P2CCRSTR_VSTART_Pos          (16U)
11430 #define DCMIPP_P2CCRSTR_VSTART_Msk          (0xFFFUL << DCMIPP_P2CCRSTR_VSTART_Pos)          /*!< 0x0FFF0000 */
11431 #define DCMIPP_P2CCRSTR_VSTART              DCMIPP_P2CCRSTR_VSTART_Msk                      /*!< Current vertical start, from 0 to 4094 pixels high */
11432 
11433 /***************  Bit definition for DCMIPP_P2CCRSZR register  ****************/
11434 #define DCMIPP_P2CCRSZR_HSIZE_Pos           (0U)
11435 #define DCMIPP_P2CCRSZR_HSIZE_Msk           (0xFFFUL << DCMIPP_P2CCRSZR_HSIZE_Pos)           /*!< 0x00000FFF */
11436 #define DCMIPP_P2CCRSZR_HSIZE               DCMIPP_P2CCRSZR_HSIZE_Msk                       /*!< Current horizontal size, from 0 to 4094 pixels wide */
11437 #define DCMIPP_P2CCRSZR_VSIZE_Pos           (16U)
11438 #define DCMIPP_P2CCRSZR_VSIZE_Msk           (0xFFFUL << DCMIPP_P2CCRSZR_VSIZE_Pos)           /*!< 0x0FFF0000 */
11439 #define DCMIPP_P2CCRSZR_VSIZE               DCMIPP_P2CCRSZR_VSIZE_Msk                       /*!< Current vertical size, from 0 to 4094 pixels high */
11440 #define DCMIPP_P2CCRSZR_ENABLE_Pos          (31U)
11441 #define DCMIPP_P2CCRSZR_ENABLE_Msk          (0x1UL << DCMIPP_P2CCRSZR_ENABLE_Pos)            /*!< 0x80000000 */
11442 #define DCMIPP_P2CCRSZR_ENABLE              DCMIPP_P2CCRSZR_ENABLE_Msk                      /*!< Current ENABLE bit value */
11443 
11444 /****************  Bit definition for DCMIPP_P2CDCCR register  *****************/
11445 #define DCMIPP_P2CDCCR_ENABLE_Pos           (0U)
11446 #define DCMIPP_P2CDCCR_ENABLE_Msk           (0x1UL << DCMIPP_P2CDCCR_ENABLE_Pos)            /*!< 0x00000001 */
11447 #define DCMIPP_P2CDCCR_ENABLE               DCMIPP_P2CDCCR_ENABLE_Msk                       /*!< Decimation enable */
11448 #define DCMIPP_P2CDCCR_HDEC_Pos             (1U)
11449 #define DCMIPP_P2CDCCR_HDEC_Msk             (0x3UL << DCMIPP_P2CDCCR_HDEC_Pos)              /*!< 0x00000006 */
11450 #define DCMIPP_P2CDCCR_HDEC                 DCMIPP_P2CDCCR_HDEC_Msk                         /*!< Horizontal decimation ratio */
11451 #define DCMIPP_P2CDCCR_VDEC_Pos             (3U)
11452 #define DCMIPP_P2CDCCR_VDEC_Msk             (0x3UL << DCMIPP_P2CDCCR_VDEC_Pos)              /*!< 0x00000018 */
11453 #define DCMIPP_P2CDCCR_VDEC                 DCMIPP_P2CDCCR_VDEC_Msk                         /*!< Vertical decimation ratio */
11454 
11455 /****************  Bit definition for DCMIPP_P2CDSCR register  ****************/
11456 #define DCMIPP_P2CDSCR_HDIV_Pos             (0U)
11457 #define DCMIPP_P2CDSCR_HDIV_Msk             (0x3FFUL << DCMIPP_P2CDSCR_HDIV_Pos)             /*!< 0x000003FF */
11458 #define DCMIPP_P2CDSCR_HDIV                 DCMIPP_P2CDSCR_HDIV_Msk                         /*!< Current horizontal division factor, from 128 (8x) to 1023 (1x) */
11459 #define DCMIPP_P2CDSCR_VDIV_Pos             (16U)
11460 #define DCMIPP_P2CDSCR_VDIV_Msk             (0x3FFUL << DCMIPP_P2CDSCR_VDIV_Pos)             /*!< 0x03FF0000 */
11461 #define DCMIPP_P2CDSCR_VDIV                 DCMIPP_P2CDSCR_VDIV_Msk                         /*!< Current vertical division factor, from 128 (8x) to 1023 (1x) */
11462 #define DCMIPP_P2CDSCR_ENABLE_Pos           (31U)
11463 #define DCMIPP_P2CDSCR_ENABLE_Msk           (0x1UL << DCMIPP_P2CDSCR_ENABLE_Pos)             /*!< 0x80000000 */
11464 #define DCMIPP_P2CDSCR_ENABLE               DCMIPP_P2CDSCR_ENABLE_Msk                       /*!< Current value of the bit ENABLE */
11465 
11466 /**************  Bit definition for DCMIPP_P2CDSRTIOR register  ***************/
11467 #define DCMIPP_P2CDSRTIOR_HRATIO_Pos        (0U)
11468 #define DCMIPP_P2CDSRTIOR_HRATIO_Msk        (0xFFFFUL << DCMIPP_P2CDSRTIOR_HRATIO_Pos)       /*!< 0x0000FFFF */
11469 #define DCMIPP_P2CDSRTIOR_HRATIO            DCMIPP_P2CDSRTIOR_HRATIO_Msk                    /*!< Current horizontal ratio, from 8192 (1x) to 65535 (8x) */
11470 #define DCMIPP_P2CDSRTIOR_VRATIO_Pos        (16U)
11471 #define DCMIPP_P2CDSRTIOR_VRATIO_Msk        (0xFFFFUL << DCMIPP_P2CDSRTIOR_VRATIO_Pos)       /*!< 0xFFFF0000 */
11472 #define DCMIPP_P2CDSRTIOR_VRATIO            DCMIPP_P2CDSRTIOR_VRATIO_Msk                    /*!< Current vertical ratio, from 8192 (1x) to 65535 (8x) */
11473 
11474 /***************  Bit definition for DCMIPP_P2CDSSZR register  ****************/
11475 #define DCMIPP_P2CDSSZR_HSIZE_Pos           (0U)
11476 #define DCMIPP_P2CDSSZR_HSIZE_Msk           (0xFFFUL << DCMIPP_P2CDSSZR_HSIZE_Pos)           /*!< 0x00000FFF */
11477 #define DCMIPP_P2CDSSZR_HSIZE               DCMIPP_P2CDSSZR_HSIZE_Msk                       /*!< Current horizontal size, from 0 to 4094 pixels wide */
11478 #define DCMIPP_P2CDSSZR_VSIZE_Pos           (16U)
11479 #define DCMIPP_P2CDSSZR_VSIZE_Msk           (0xFFFUL << DCMIPP_P2CDSSZR_VSIZE_Pos)           /*!< 0x0FFF0000 */
11480 #define DCMIPP_P2CDSSZR_VSIZE               DCMIPP_P2CDSSZR_VSIZE_Msk                       /*!< Current vertical size, from 0 to 4094 pixels high */
11481 
11482 /****************  Bit definition for DCMIPP_P2CPPCR register  ****************/
11483 #define DCMIPP_P2CPPCR_FORMAT_Pos           (0U)
11484 #define DCMIPP_P2CPPCR_FORMAT_Msk           (0xFUL << DCMIPP_P2CPPCR_FORMAT_Pos)             /*!< 0x0000000F */
11485 #define DCMIPP_P2CPPCR_FORMAT               DCMIPP_P2CPPCR_FORMAT_Msk                       /*!< Memory format (only coplanar formats are supported in Pipe2) */
11486 #define DCMIPP_P2CPPCR_SWAPRB_Pos           (4U)
11487 #define DCMIPP_P2CPPCR_SWAPRB_Msk           (0x1UL << DCMIPP_P2CPPCR_SWAPRB_Pos)             /*!< 0x00000010 */
11488 #define DCMIPP_P2CPPCR_SWAPRB               DCMIPP_P2CPPCR_SWAPRB_Msk                       /*!< Swaps R-vs-B components if RGB, and if YUV, swaps U-vs-V components */
11489 #define DCMIPP_P2CPPCR_LINEMULT_Pos         (13U)
11490 #define DCMIPP_P2CPPCR_LINEMULT_Msk         (0x7UL << DCMIPP_P2CPPCR_LINEMULT_Pos)           /*!< 0x0000E000 */
11491 #define DCMIPP_P2CPPCR_LINEMULT             DCMIPP_P2CPPCR_LINEMULT_Msk                     /*!< Amount of capture completed lines for LINE Event and Interrupt */
11492 #define DCMIPP_P2CPPCR_DBM_Pos              (16U)
11493 #define DCMIPP_P2CPPCR_DBM_Msk              (0x1UL << DCMIPP_P2CPPCR_DBM_Pos)                /*!< 0x00010000 */
11494 #define DCMIPP_P2CPPCR_DBM                  DCMIPP_P2CPPCR_DBM_Msk                           /*!< Double buffer mode */
11495 #define DCMIPP_P2CPPCR_LMAWM_Pos            (17U)
11496 #define DCMIPP_P2CPPCR_LMAWM_Msk            (0x7UL << DCMIPP_P2CPPCR_LMAWM_Pos)              /*!< 0x000E0000 */
11497 #define DCMIPP_P2CPPCR_LMAWM                DCMIPP_P2CPPCR_LMAWM_Msk                         /*!< Line multi address wrapping modulo */
11498 #define DCMIPP_P2CPPCR_LMAWE_Pos            (20U)
11499 #define DCMIPP_P2CPPCR_LMAWE_Msk            (0x7UL << DCMIPP_P2CPPCR_LMAWE_Pos)              /*!< 0x00100000 */
11500 #define DCMIPP_P2CPPCR_LMAWE                DCMIPP_P2CPPCR_LMAWE_Msk                         /*!< Line multi address wrapping enable */
11501 
11502 /**************  Bit definition for DCMIPP_P2CPPM0AR1 register  ***************/
11503 #define DCMIPP_P2CPPM0AR1_M0A_Pos           (0U)
11504 #define DCMIPP_P2CPPM0AR1_M0A_Msk           (0xFFFFFFFFUL << DCMIPP_P2CPPM0AR1_M0A_Pos)      /*!< 0xFFFFFFFF */
11505 #define DCMIPP_P2CPPM0AR1_M0A               DCMIPP_P2CPPM0AR1_M0A_Msk                       /*!< Memory0 address */
11506 
11507 /**************  Bit definition for DCMIPP_P2CPPM0AR2 register  ***************/
11508 #define DCMIPP_P2CPPM0AR2_M0A_Pos           (0U)
11509 #define DCMIPP_P2CPPM0AR2_M0A_Msk           (0xFFFFFFFFUL << DCMIPP_P2CPPM0AR1_M0A_Pos)      /*!< 0xFFFFFFFF */
11510 #define DCMIPP_P2CPPM0AR2_M0A               DCMIPP_P2CPPM0AR1_M0A_Msk                       /*!< Memory0 address Register 2 */
11511 
11512 /***************  Bit definition for DCMIPP_P2CPPM0PR register  ***************/
11513 #define DCMIPP_P2CPPM0PR_PITCH_Pos          (0U)
11514 #define DCMIPP_P2CPPM0PR_PITCH_Msk          (0x7FFFUL << DCMIPP_P2CPPM0PR_PITCH_Pos)         /*!< 0x00007FFF */
11515 #define DCMIPP_P2CPPM0PR_PITCH              DCMIPP_P2CPPM0PR_PITCH_Msk                      /*!< Number of bytes between the address of two consecutive lines */
11516 
11517 /****************  Bit definition for DCMIPP_HWCFGR2 register  ****************/
11518 #define DCMIPP_HWCFGR2_VPFT_Pos             (0U)
11519 #define DCMIPP_HWCFGR2_VPFT_Msk             (0x7U << DCMIPP_HWCFGR2_VPFT_Pos)               /*!< 0x00000007 */
11520 #define DCMIPP_HWCFGR2_VPFT                 DCMIPP_HWCFGR2_VPFT_Msk                         /*!< Virtual pipe function */
11521 #define DCMIPP_HWCFGR2_DBMFT_Pos            (4U)
11522 #define DCMIPP_HWCFGR2_DBMFT_Msk            (0x1U << DCMIPP_HWCFGR2_DBMFT_Pos)              /*!< 0x00000010 */
11523 #define DCMIPP_HWCFGR2_DBMFT                DCMIPP_HWCFGR2_DBMFT_Msk                        /*!< Double buffer mode featured */
11524 #define DCMIPP_HWCFGR2_PROCCLK_Pos          (8U)
11525 #define DCMIPP_HWCFGR2_PROCCLK_Msk          (0x1U << DCMIPP_HWCFGR2_PROCCLK_Pos)            /*!< 0x00000100 */
11526 #define DCMIPP_HWCFGR2_PROCCLK              DCMIPP_HWCFGR2_PROCCLK_Msk                      /*!< Processing clock linked to AXI clock featured */
11527 #define DCMIPP_HWCFGR2_ADDMOD_Pos           (12U)
11528 #define DCMIPP_HWCFGR2_ADDMOD_Msk           (0x1U << DCMIPP_HWCFGR2_ADDMOD_Pos)             /*!< 0x00001000 */
11529 #define DCMIPP_HWCFGR2_ADDMOD               DCMIPP_HWCFGR2_ADDMOD_Msk                       /*!< Address modulo computation to access a small buffer in streaming featured */
11530 #define DCMIPP_HWCFGR2_DEC1_Pos             (16U)
11531 #define DCMIPP_HWCFGR2_DEC1_Msk             (0x1U << DCMIPP_HWCFGR2_DEC1_Pos)               /*!< 0x00010000 */
11532 #define DCMIPP_HWCFGR2_DEC1                 DCMIPP_HWCFGR2_DEC1_Msk                         /*!< Decimation on Pipe1 before downsize */
11533 #define DCMIPP_HWCFGR2_DEC2_Pos             (17U)
11534 #define DCMIPP_HWCFGR2_DEC2_Msk             (0x1U << DCMIPP_HWCFGR2_DEC2_Pos)               /*!< 0x00020000 */
11535 #define DCMIPP_HWCFGR2_DEC2                 DCMIPP_HWCFGR2_DEC2_Msk                         /*!< Decimation on Pipe2 before downsize */
11536 #define DCMIPP_HWCFGR2_MCU_Pos              (20U)
11537 #define DCMIPP_HWCFGR2_MCU_Msk              (0x1U << DCMIPP_HWCFGR2_MCU_Pos)                /*!< 0x00100000 */
11538 #define DCMIPP_HWCFGR2_MCU                  DCMIPP_HWCFGR2_MCU_Msk                          /*!< Macroblock unit as pixel format  */
11539 #define DCMIPP_HWCFGR2_TPG_Pos              (24U)
11540 #define DCMIPP_HWCFGR2_TPG_Msk              (0x1U << DCMIPP_HWCFGR2_TPG_Pos)                /*!< 0x01000000 */
11541 #define DCMIPP_HWCFGR2_TPG                  DCMIPP_HWCFGR2_TPG_Msk                          /*!< Test Pattern Generator */
11542 #define DCMIPP_HWCFGR2_STV_Pos              (28U)
11543 #define DCMIPP_HWCFGR2_STV_Msk              (0x1U << DCMIPP_HWCFGR2_STV_Pos)                /*!< 0x10000000 */
11544 #define DCMIPP_HWCFGR2_STV                  DCMIPP_HWCFGR2_STV_Msk                          /*!< Statistic Version */
11545 
11546 /****************  Bit definition for DCMIPP_HWCFGR1 register  ****************/
11547 #define DCMIPP_HWCFGR1_CSIFT_Pos            (0U)
11548 #define DCMIPP_HWCFGR1_CSIFT_Msk            (0x1U << DCMIPP_HWCFGR1_CSIFT_Pos)              /*!< 0x00000001 */
11549 #define DCMIPP_HWCFGR1_CSIFT                DCMIPP_HWCFGR1_CSIFT_Msk                        /*!< CSI2 host protocol compliant */
11550 #define DCMIPP_HWCFGR1_PIPENB_Pos           (4U)
11551 #define DCMIPP_HWCFGR1_PIPENB_Msk           (0x3U << DCMIPP_HWCFGR1_PIPENB_Pos)             /*!< 0x00000030 */
11552 #define DCMIPP_HWCFGR1_PIPENB               DCMIPP_HWCFGR1_PIPENB_Msk                       /*!< Number of pipes */
11553 #define DCMIPP_HWCFGR1_IPPLUGCFG_Pos        (8U)
11554 #define DCMIPP_HWCFGR1_IPPLUGCFG_Msk        (0x1U << DCMIPP_HWCFGR1_IPPLUGCFG_Pos)          /*!< 0x00000100 */
11555 #define DCMIPP_HWCFGR1_IPPLUGCFG            DCMIPP_HWCFGR1_IPPLUGCFG_Msk                    /*!< IP-Plug configuration */
11556 #define DCMIPP_HWCFGR1_DSP1FT_Pos           (12U)
11557 #define DCMIPP_HWCFGR1_DSP1FT_Msk           (0x1U << DCMIPP_HWCFGR1_DSP1FT_Pos)             /*!< 0x00001000 */
11558 #define DCMIPP_HWCFGR1_DSP1FT               DCMIPP_HWCFGR1_DSP1FT_Msk                       /*!< Down-sampling feature for the pixel Pipe1 */
11559 #define DCMIPP_HWCFGR1_DSP2FT_Pos           (13U)
11560 #define DCMIPP_HWCFGR1_DSP2FT_Msk           (0x1U << DCMIPP_HWCFGR1_DSP2FT_Pos)             /*!< 0x00002000 */
11561 #define DCMIPP_HWCFGR1_DSP2FT               DCMIPP_HWCFGR1_DSP2FT_Msk                       /*!< Down-sampling feature for the pixel Pipe2 */
11562 #define DCMIPP_HWCFGR1_RB2RGB_Pos           (16U)
11563 #define DCMIPP_HWCFGR1_RB2RGB_Msk           (0x1U << DCMIPP_HWCFGR1_RB2RGB_Pos)             /*!< 0x00010000 */
11564 #define DCMIPP_HWCFGR1_RB2RGB               DCMIPP_HWCFGR1_RB2RGB_Msk                       /*!< Raw Bayer to RGB feature (demosaicer) */
11565 #define DCMIPP_HWCFGR1_PLANARFT_Pos         (20U)
11566 #define DCMIPP_HWCFGR1_PLANARFT_Msk         (0x3U << DCMIPP_HWCFGR1_PLANARFT_Pos)           /*!< 0x00300000 */
11567 #define DCMIPP_HWCFGR1_PLANARFT             DCMIPP_HWCFGR1_PLANARFT_Msk                     /*!< Buffer features for Pipe1 */
11568 #define DCMIPP_HWCFGR1_ROI1NB_Pos           (24U)
11569 #define DCMIPP_HWCFGR1_ROI1NB_Msk           (0xFU << DCMIPP_HWCFGR1_ROI1NB_Pos)             /*!< 0x0F000000 */
11570 #define DCMIPP_HWCFGR1_ROI1NB               DCMIPP_HWCFGR1_ROI1NB_Msk                       /*!< Number of ROIs for Pipe1 */
11571 #define DCMIPP_HWCFGR1_ROI2NB_Pos           (28U)
11572 #define DCMIPP_HWCFGR1_ROI2NB_Msk           (0xFU << DCMIPP_HWCFGR1_ROI2NB_Pos)             /*!< 0xF0000000 */
11573 #define DCMIPP_HWCFGR1_ROI2NB               DCMIPP_HWCFGR1_ROI2NB_Msk                       /*!< Number of ROIs for Pipe2 */
11574 
11575 /*****************  Bit definition for DCMIPP_VERR register  ******************/
11576 #define DCMIPP_VERR_MINREV_Pos              (0U)
11577 #define DCMIPP_VERR_MINREV_Msk              (0xFU << DCMIPP_VERR_MINREV_Pos)                /*!< 0x0000000F */
11578 #define DCMIPP_VERR_MINREV                  DCMIPP_VERR_MINREV_Msk                          /*!< DCMIPP minor revision */
11579 #define DCMIPP_VERR_MAJREV_Pos              (4U)
11580 #define DCMIPP_VERR_MAJREV_Msk              (0xFU << DCMIPP_VERR_MAJREV_Pos)                /*!< 0x000000F0 */
11581 #define DCMIPP_VERR_MAJREV                  DCMIPP_VERR_MAJREV_Msk                          /*!< DCMIPP major revision */
11582 
11583 /*****************  Bit definition for DCMIPP_IPIDR register  *****************/
11584 #define DCMIPP_IPIDR_IDR_Pos                (0U)
11585 #define DCMIPP_IPIDR_IDR_Msk                (0xFFFFFFFFU << DCMIPP_IPIDR_IDR_Pos)           /*!< 0xFFFFFFFF */
11586 #define DCMIPP_IPIDR_IDR                    DCMIPP_IPIDR_IDR_Msk                            /*!< Parallel camera interface (DCMI) and optional pixel processing (PP) */
11587 
11588 /*****************  Bit definition for DCMIPP_SIDR register  ******************/
11589 #define DCMIPP_SIDR_SID_Pos                 (0U)
11590 #define DCMIPP_SIDR_SID_Msk                 (0xFFFFFFFFU << DCMIPP_SIDR_SID_Pos)            /*!< 0xFFFFFFFF */
11591 #define DCMIPP_SIDR_SID                     DCMIPP_SIDR_SID_Msk                             /*!< 4-Kbyte decoding space */
11592 
11593 /******************************************************************************/
11594 /*                                                                            */
11595 /*                        Delay Block Interface (DLYB)                        */
11596 /*                                                                            */
11597 /******************************************************************************/
11598 /*******************  Bit definition for DLYB_CR register  ********************/
11599 #define DLYB_CR_DEN_Pos                     (0U)
11600 #define DLYB_CR_DEN_Msk                     (0x1UL << DLYB_CR_DEN_Pos)              /*!< 0x00000001 */
11601 #define DLYB_CR_DEN                         DLYB_CR_DEN_Msk                         /*!<Delay Block enable */
11602 #define DLYB_CR_SEN_Pos                     (1U)
11603 #define DLYB_CR_SEN_Msk                     (0x1UL << DLYB_CR_SEN_Pos)              /*!< 0x00000002 */
11604 #define DLYB_CR_SEN                         DLYB_CR_SEN_Msk                         /*!<Sampler length enable */
11605 
11606 /*******************  Bit definition for DLYB_CFGR register  ********************/
11607 #define DLYB_CFGR_SEL_Pos                   (0U)
11608 #define DLYB_CFGR_SEL_Msk                   (0xFUL << DLYB_CFGR_SEL_Pos)            /*!< 0x0000000F */
11609 #define DLYB_CFGR_SEL                       DLYB_CFGR_SEL_Msk                       /*!<Select the phase for the Output clock[3:0] */
11610 #define DLYB_CFGR_SEL_0                     (0x1UL << DLYB_CFGR_SEL_Pos)            /*!< 0x00000001 */
11611 #define DLYB_CFGR_SEL_1                     (0x2UL << DLYB_CFGR_SEL_Pos)            /*!< 0x00000002 */
11612 #define DLYB_CFGR_SEL_2                     (0x3UL << DLYB_CFGR_SEL_Pos)            /*!< 0x00000003 */
11613 #define DLYB_CFGR_SEL_3                     (0x8UL << DLYB_CFGR_SEL_Pos)            /*!< 0x00000008 */
11614 
11615 #define DLYB_CFGR_UNIT_Pos                  (8U)
11616 #define DLYB_CFGR_UNIT_Msk                  (0x7FUL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00007F00 */
11617 #define DLYB_CFGR_UNIT                      DLYB_CFGR_UNIT_Msk                      /*!<Delay Defines the delay of a Unit delay cell[6:0] */
11618 #define DLYB_CFGR_UNIT_0                    (0x01UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00000100 */
11619 #define DLYB_CFGR_UNIT_1                    (0x02UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00000200 */
11620 #define DLYB_CFGR_UNIT_2                    (0x04UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00000400 */
11621 #define DLYB_CFGR_UNIT_3                    (0x08UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00000800 */
11622 #define DLYB_CFGR_UNIT_4                    (0x10UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00001000 */
11623 #define DLYB_CFGR_UNIT_5                    (0x20UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00002000 */
11624 #define DLYB_CFGR_UNIT_6                    (0x40UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00004000 */
11625 
11626 #define DLYB_CFGR_LNG_Pos                   (16U)
11627 #define DLYB_CFGR_LNG_Msk                   (0xFFFUL << DLYB_CFGR_LNG_Pos)          /*!< 0x0FFF0000 */
11628 #define DLYB_CFGR_LNG                       DLYB_CFGR_LNG_Msk                       /*!<Delay line length value[11:0] */
11629 #define DLYB_CFGR_LNG_0                     (0x001UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00010000 */
11630 #define DLYB_CFGR_LNG_1                     (0x002UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00020000 */
11631 #define DLYB_CFGR_LNG_2                     (0x004UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00040000 */
11632 #define DLYB_CFGR_LNG_3                     (0x008UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00080000 */
11633 #define DLYB_CFGR_LNG_4                     (0x010UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00100000 */
11634 #define DLYB_CFGR_LNG_5                     (0x020UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00200000 */
11635 #define DLYB_CFGR_LNG_6                     (0x040UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00400000 */
11636 #define DLYB_CFGR_LNG_7                     (0x080UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00800000 */
11637 #define DLYB_CFGR_LNG_8                     (0x100UL << DLYB_CFGR_LNG_Pos)          /*!< 0x01000000 */
11638 #define DLYB_CFGR_LNG_9                     (0x200UL << DLYB_CFGR_LNG_Pos)          /*!< 0x02000000 */
11639 #define DLYB_CFGR_LNG_10                    (0x400UL << DLYB_CFGR_LNG_Pos)          /*!< 0x04000000 */
11640 #define DLYB_CFGR_LNG_11                    (0x800UL << DLYB_CFGR_LNG_Pos)          /*!< 0x08000000 */
11641 
11642 #define DLYB_CFGR_LNGF_Pos                  (31U)
11643 #define DLYB_CFGR_LNGF_Msk                  (0x1UL << DLYB_CFGR_LNGF_Pos)            /*!< 0x80000000 */
11644 #define DLYB_CFGR_LNGF                      DLYB_CFGR_LNGF_Msk                       /*!<Length valid flag */
11645 
11646 
11647 /******************************************************************************/
11648 /*                                                                            */
11649 /*                           DMA Controller (DMA)                             */
11650 /*                                                                            */
11651 /******************************************************************************/
11652 /*******************  Bit definition for DMA_SECCFGR register  ****************/
11653 #define DMA_SECCFGR_SEC0_Pos     (0U)
11654 #define DMA_SECCFGR_SEC0_Msk     (0x1UL << DMA_SECCFGR_SEC0_Pos)                /*!< 0x00000001 */
11655 #define DMA_SECCFGR_SEC0         DMA_SECCFGR_SEC0_Msk                          /*!< Secure State of Channel 0 */
11656 #define DMA_SECCFGR_SEC1_Pos     (1U)
11657 #define DMA_SECCFGR_SEC1_Msk     (0x1UL << DMA_SECCFGR_SEC1_Pos)                /*!< 0x00000002 */
11658 #define DMA_SECCFGR_SEC1         DMA_SECCFGR_SEC1_Msk                          /*!< Secure State of Channel 1 */
11659 #define DMA_SECCFGR_SEC2_Pos     (2U)
11660 #define DMA_SECCFGR_SEC2_Msk     (0x1UL << DMA_SECCFGR_SEC2_Pos)                /*!< 0x00000004 */
11661 #define DMA_SECCFGR_SEC2         DMA_SECCFGR_SEC2_Msk                          /*!< Secure State of Channel 2 */
11662 #define DMA_SECCFGR_SEC3_Pos     (3U)
11663 #define DMA_SECCFGR_SEC3_Msk     (0x1UL << DMA_SECCFGR_SEC3_Pos)                /*!< 0x00000008 */
11664 #define DMA_SECCFGR_SEC3         DMA_SECCFGR_SEC3_Msk                          /*!< Secure State of Channel 3 */
11665 #define DMA_SECCFGR_SEC4_Pos     (4U)
11666 #define DMA_SECCFGR_SEC4_Msk     (0x1UL << DMA_SECCFGR_SEC4_Pos)                /*!< 0x00000010 */
11667 #define DMA_SECCFGR_SEC4         DMA_SECCFGR_SEC4_Msk                          /*!< Secure State of Channel 4 */
11668 #define DMA_SECCFGR_SEC5_Pos     (5U)
11669 #define DMA_SECCFGR_SEC5_Msk     (0x1UL << DMA_SECCFGR_SEC5_Pos)                /*!< 0x00000020 */
11670 #define DMA_SECCFGR_SEC5         DMA_SECCFGR_SEC5_Msk                          /*!< Secure State of Channel 5 */
11671 #define DMA_SECCFGR_SEC6_Pos     (6U)
11672 #define DMA_SECCFGR_SEC6_Msk     (0x1UL << DMA_SECCFGR_SEC6_Pos)                /*!< 0x00000040 */
11673 #define DMA_SECCFGR_SEC6         DMA_SECCFGR_SEC6_Msk                          /*!< Secure State of Channel 6 */
11674 #define DMA_SECCFGR_SEC7_Pos     (7U)
11675 #define DMA_SECCFGR_SEC7_Msk     (0x1UL << DMA_SECCFGR_SEC7_Pos)                /*!< 0x00000080 */
11676 #define DMA_SECCFGR_SEC7         DMA_SECCFGR_SEC7_Msk                          /*!< Secure State of Channel 7 */
11677 #define DMA_SECCFGR_SEC8_Pos     (8U)
11678 #define DMA_SECCFGR_SEC8_Msk     (0x1UL << DMA_SECCFGR_SEC8_Pos)                /*!< 0x00000100 */
11679 #define DMA_SECCFGR_SEC8         DMA_SECCFGR_SEC8_Msk                          /*!< Secure State of Channel 8 */
11680 #define DMA_SECCFGR_SEC9_Pos     (9U)
11681 #define DMA_SECCFGR_SEC9_Msk     (0x1UL << DMA_SECCFGR_SEC9_Pos)                /*!< 0x00000200 */
11682 #define DMA_SECCFGR_SEC9         DMA_SECCFGR_SEC9_Msk                          /*!< Secure State of Channel 9 */
11683 #define DMA_SECCFGR_SEC10_Pos    (10U)
11684 #define DMA_SECCFGR_SEC10_Msk    (0x1UL << DMA_SECCFGR_SEC10_Pos)               /*!< 0x00000400 */
11685 #define DMA_SECCFGR_SEC10        DMA_SECCFGR_SEC10_Msk                         /*!< Secure State of Channel 10 */
11686 #define DMA_SECCFGR_SEC11_Pos    (11U)
11687 #define DMA_SECCFGR_SEC11_Msk    (0x1UL << DMA_SECCFGR_SEC11_Pos)               /*!< 0x00000800 */
11688 #define DMA_SECCFGR_SEC11        DMA_SECCFGR_SEC11_Msk                         /*!< Secure State of Channel 11 */
11689 #define DMA_SECCFGR_SEC12_Pos    (12U)
11690 #define DMA_SECCFGR_SEC12_Msk    (0x1UL << DMA_SECCFGR_SEC12_Pos)               /*!< 0x00001000 */
11691 #define DMA_SECCFGR_SEC12        DMA_SECCFGR_SEC12_Msk                         /*!< Secure State of Channel 12 */
11692 #define DMA_SECCFGR_SEC13_Pos    (13U)
11693 #define DMA_SECCFGR_SEC13_Msk    (0x1UL << DMA_SECCFGR_SEC13_Pos)               /*!< 0x00002000 */
11694 #define DMA_SECCFGR_SEC13        DMA_SECCFGR_SEC13_Msk                         /*!< Secure State of Channel 13 */
11695 #define DMA_SECCFGR_SEC14_Pos    (14U)
11696 #define DMA_SECCFGR_SEC14_Msk    (0x1UL << DMA_SECCFGR_SEC14_Pos)               /*!< 0x00004000 */
11697 #define DMA_SECCFGR_SEC14        DMA_SECCFGR_SEC14_Msk                         /*!< Secure State of Channel 14 */
11698 #define DMA_SECCFGR_SEC15_Pos    (15U)
11699 #define DMA_SECCFGR_SEC15_Msk    (0x1UL << DMA_SECCFGR_SEC15_Pos)               /*!< 0x00008000 */
11700 #define DMA_SECCFGR_SEC15        DMA_SECCFGR_SEC14_Msk                         /*!< Secure State of Channel 15 */
11701 
11702 /*******************  Bit definition for DMA_PRIVCFGR register  ****************/
11703 #define DMA_PRIVCFGR_PRIV0_Pos              (0U)
11704 #define DMA_PRIVCFGR_PRIV0_Msk              (0x1UL << DMA_PRIVCFGR_PRIV0_Pos)       /*!< 0x00000001 */
11705 #define DMA_PRIVCFGR_PRIV0                  DMA_PRIVCFGR_PRIV0_Msk                  /*!< Privileged State of Channel 0 */
11706 #define DMA_PRIVCFGR_PRIV1_Pos              (1U)
11707 #define DMA_PRIVCFGR_PRIV1_Msk              (0x1UL << DMA_PRIVCFGR_PRIV1_Pos)       /*!< 0x00000002 */
11708 #define DMA_PRIVCFGR_PRIV1                  DMA_PRIVCFGR_PRIV1_Msk                  /*!< Privileged State of Channel 1 */
11709 #define DMA_PRIVCFGR_PRIV2_Pos              (2U)
11710 #define DMA_PRIVCFGR_PRIV2_Msk              (0x1UL << DMA_PRIVCFGR_PRIV2_Pos)       /*!< 0x00000004 */
11711 #define DMA_PRIVCFGR_PRIV2                  DMA_PRIVCFGR_PRIV2_Msk                  /*!< Privileged State of Channel 2 */
11712 #define DMA_PRIVCFGR_PRIV3_Pos              (3U)
11713 #define DMA_PRIVCFGR_PRIV3_Msk              (0x1UL << DMA_PRIVCFGR_PRIV3_Pos)       /*!< 0x00000008 */
11714 #define DMA_PRIVCFGR_PRIV3                  DMA_PRIVCFGR_PRIV3_Msk                  /*!< Privileged State of Channel 3 */
11715 #define DMA_PRIVCFGR_PRIV4_Pos              (4U)
11716 #define DMA_PRIVCFGR_PRIV4_Msk              (0x1UL << DMA_PRIVCFGR_PRIV4_Pos)       /*!< 0x00000010 */
11717 #define DMA_PRIVCFGR_PRIV4                  DMA_PRIVCFGR_PRIV4_Msk                  /*!< Privileged State of Channel 4 */
11718 #define DMA_PRIVCFGR_PRIV5_Pos              (5U)
11719 #define DMA_PRIVCFGR_PRIV5_Msk              (0x1UL << DMA_PRIVCFGR_PRIV5_Pos)       /*!< 0x00000020 */
11720 #define DMA_PRIVCFGR_PRIV5                  DMA_PRIVCFGR_PRIV5_Msk                  /*!< Privileged State of Channel 5 */
11721 #define DMA_PRIVCFGR_PRIV6_Pos              (6U)
11722 #define DMA_PRIVCFGR_PRIV6_Msk              (0x1UL << DMA_PRIVCFGR_PRIV6_Pos)       /*!< 0x00000040 */
11723 #define DMA_PRIVCFGR_PRIV6                  DMA_PRIVCFGR_PRIV6_Msk                  /*!< Privileged State of Channel 6 */
11724 #define DMA_PRIVCFGR_PRIV7_Pos              (7U)
11725 #define DMA_PRIVCFGR_PRIV7_Msk              (0x1UL << DMA_PRIVCFGR_PRIV7_Pos)       /*!< 0x00000080 */
11726 #define DMA_PRIVCFGR_PRIV7                  DMA_PRIVCFGR_PRIV7_Msk                  /*!< Privileged State of Channel 7 */
11727 #define DMA_PRIVCFGR_PRIV8_Pos              (8U)
11728 #define DMA_PRIVCFGR_PRIV8_Msk              (0x1UL << DMA_PRIVCFGR_PRIV8_Pos)       /*!< 0x00000100 */
11729 #define DMA_PRIVCFGR_PRIV8                  DMA_PRIVCFGR_PRIV8_Msk                  /*!< Privileged State of Channel 8 */
11730 #define DMA_PRIVCFGR_PRIV9_Pos              (9U)
11731 #define DMA_PRIVCFGR_PRIV9_Msk              (0x1UL << DMA_PRIVCFGR_PRIV9_Pos)       /*!< 0x00000200 */
11732 #define DMA_PRIVCFGR_PRIV9                  DMA_PRIVCFGR_PRIV9_Msk                  /*!< Privileged State of Channel 9 */
11733 #define DMA_PRIVCFGR_PRIV10_Pos             (10U)
11734 #define DMA_PRIVCFGR_PRIV10_Msk             (0x1UL << DMA_PRIVCFGR_PRIV10_Pos)      /*!< 0x00000400 */
11735 #define DMA_PRIVCFGR_PRIV10                 DMA_PRIVCFGR_PRIV10_Msk                 /*!< Privileged State of Channel 10 */
11736 #define DMA_PRIVCFGR_PRIV11_Pos             (11U)
11737 #define DMA_PRIVCFGR_PRIV11_Msk             (0x1UL << DMA_PRIVCFGR_PRIV11_Pos)      /*!< 0x00000800 */
11738 #define DMA_PRIVCFGR_PRIV11                 DMA_PRIVCFGR_PRIV11_Msk                 /*!< Privileged State of Channel 11 */
11739 #define DMA_PRIVCFGR_PRIV12_Pos             (12U)
11740 #define DMA_PRIVCFGR_PRIV12_Msk             (0x1UL << DMA_PRIVCFGR_PRIV12_Pos)      /*!< 0x00001000 */
11741 #define DMA_PRIVCFGR_PRIV12                 DMA_PRIVCFGR_PRIV12_Msk                 /*!< Privileged State of Channel 12 */
11742 #define DMA_PRIVCFGR_PRIV13_Pos             (13U)
11743 #define DMA_PRIVCFGR_PRIV13_Msk             (0x1UL << DMA_PRIVCFGR_PRIV13_Pos)      /*!< 0x00002000 */
11744 #define DMA_PRIVCFGR_PRIV13                 DMA_PRIVCFGR_PRIV13_Msk                 /*!< Privileged State of Channel 13 */
11745 #define DMA_PRIVCFGR_PRIV14_Pos             (14U)
11746 #define DMA_PRIVCFGR_PRIV14_Msk             (0x1UL << DMA_PRIVCFGR_PRIV14_Pos)      /*!< 0x00004000 */
11747 #define DMA_PRIVCFGR_PRIV14                 DMA_PRIVCFGR_PRIV14_Msk                 /*!< Privileged State of Channel 14 */
11748 #define DMA_PRIVCFGR_PRIV15_Pos             (15U)
11749 #define DMA_PRIVCFGR_PRIV15_Msk             (0x1UL << DMA_PRIVCFGR_PRIV15_Pos)      /*!< 0x00008000 */
11750 #define DMA_PRIVCFGR_PRIV15                 DMA_PRIVCFGR_PRIV15_Msk                 /*!< Privileged State of Channel 15 */
11751 
11752 /*******************  Bit definition for DMA_RCFGLOCKR register  ****************/
11753 #define DMA_RCFGLOCKR_LOCK0_Pos              (0U)
11754 #define DMA_RCFGLOCKR_LOCK0_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK0_Pos)       /*!< 0x00000001 */
11755 #define DMA_RCFGLOCKR_LOCK0                  DMA_RCFGLOCKR_LOCK0_Msk                  /*!< Lock the configuration of Channel 0  */
11756 #define DMA_RCFGLOCKR_LOCK1_Pos              (1U)
11757 #define DMA_RCFGLOCKR_LOCK1_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK1_Pos)       /*!< 0x00000002 */
11758 #define DMA_RCFGLOCKR_LOCK1                  DMA_RCFGLOCKR_LOCK1_Msk                  /*!< Lock the configuration of Channel 1  */
11759 #define DMA_RCFGLOCKR_LOCK2_Pos              (2U)
11760 #define DMA_RCFGLOCKR_LOCK2_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK2_Pos)       /*!< 0x00000004 */
11761 #define DMA_RCFGLOCKR_LOCK2                  DMA_RCFGLOCKR_LOCK2_Msk                  /*!< Lock the configuration of Channel 2  */
11762 #define DMA_RCFGLOCKR_LOCK3_Pos              (3U)
11763 #define DMA_RCFGLOCKR_LOCK3_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK3_Pos)       /*!< 0x00000008 */
11764 #define DMA_RCFGLOCKR_LOCK3                  DMA_RCFGLOCKR_LOCK3_Msk                  /*!< Lock the configuration of Channel 3  */
11765 #define DMA_RCFGLOCKR_LOCK4_Pos              (4U)
11766 #define DMA_RCFGLOCKR_LOCK4_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK4_Pos)       /*!< 0x00000010 */
11767 #define DMA_RCFGLOCKR_LOCK4                  DMA_RCFGLOCKR_LOCK4_Msk                  /*!< Lock the configuration of Channel 4  */
11768 #define DMA_RCFGLOCKR_LOCK5_Pos              (5U)
11769 #define DMA_RCFGLOCKR_LOCK5_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK5_Pos)       /*!< 0x00000020 */
11770 #define DMA_RCFGLOCKR_LOCK5                  DMA_RCFGLOCKR_LOCK5_Msk                  /*!< Lock the configuration of Channel 5  */
11771 #define DMA_RCFGLOCKR_LOCK6_Pos              (6U)
11772 #define DMA_RCFGLOCKR_LOCK6_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK6_Pos)       /*!< 0x00000040 */
11773 #define DMA_RCFGLOCKR_LOCK6                  DMA_RCFGLOCKR_LOCK6_Msk                  /*!< Lock the configuration of Channel 6  */
11774 #define DMA_RCFGLOCKR_LOCK7_Pos              (7U)
11775 #define DMA_RCFGLOCKR_LOCK7_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK7_Pos)       /*!< 0x00000080 */
11776 #define DMA_RCFGLOCKR_LOCK7                  DMA_RCFGLOCKR_LOCK7_Msk                  /*!< Lock the configuration of Channel 7  */
11777 #define DMA_RCFGLOCKR_LOCK8_Pos              (8U)
11778 #define DMA_RCFGLOCKR_LOCK8_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK8_Pos)       /*!< 0x00000100 */
11779 #define DMA_RCFGLOCKR_LOCK8                  DMA_RCFGLOCKR_LOCK8_Msk                  /*!< Lock the configuration of Channel 8  */
11780 #define DMA_RCFGLOCKR_LOCK9_Pos              (9U)
11781 #define DMA_RCFGLOCKR_LOCK9_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK9_Pos)       /*!< 0x00000200 */
11782 #define DMA_RCFGLOCKR_LOCK9                  DMA_RCFGLOCKR_LOCK9_Msk                  /*!< Lock the configuration of Channel 9  */
11783 #define DMA_RCFGLOCKR_LOCK10_Pos             (10U)
11784 #define DMA_RCFGLOCKR_LOCK10_Msk             (0x1UL << DMA_RCFGLOCKR_LOCK10_Pos)      /*!< 0x00000400 */
11785 #define DMA_RCFGLOCKR_LOCK10                 DMA_RCFGLOCKR_LOCK10_Msk                 /*!< Lock the configuration of Channel 10 */
11786 #define DMA_RCFGLOCKR_LOCK11_Pos             (11U)
11787 #define DMA_RCFGLOCKR_LOCK11_Msk             (0x1UL << DMA_RCFGLOCKR_LOCK11_Pos)      /*!< 0x00000800 */
11788 #define DMA_RCFGLOCKR_LOCK11                 DMA_RCFGLOCKR_LOCK11_Msk                 /*!< Lock the configuration of Channel 11 */
11789 #define DMA_RCFGLOCKR_LOCK12_Pos             (12U)
11790 #define DMA_RCFGLOCKR_LOCK12_Msk             (0x1UL << DMA_RCFGLOCKR_LOCK12_Pos)      /*!< 0x00001000 */
11791 #define DMA_RCFGLOCKR_LOCK12                 DMA_RCFGLOCKR_LOCK12_Msk                 /*!< Lock the configuration of Channel 12 */
11792 #define DMA_RCFGLOCKR_LOCK13_Pos             (13U)
11793 #define DMA_RCFGLOCKR_LOCK13_Msk             (0x1UL << DMA_RCFGLOCKR_LOCK13_Pos)      /*!< 0x00002000 */
11794 #define DMA_RCFGLOCKR_LOCK13                 DMA_RCFGLOCKR_LOCK13_Msk                 /*!< Lock the configuration of Channel 13 */
11795 #define DMA_RCFGLOCKR_LOCK14_Pos             (14U)
11796 #define DMA_RCFGLOCKR_LOCK14_Msk             (0x1UL << DMA_RCFGLOCKR_LOCK14_Pos)      /*!< 0x00004000 */
11797 #define DMA_RCFGLOCKR_LOCK14                 DMA_RCFGLOCKR_LOCK14_Msk                 /*!< Lock the configuration of Channel 14 */
11798 #define DMA_RCFGLOCKR_LOCK15_Pos             (15U)
11799 #define DMA_RCFGLOCKR_LOCK15_Msk             (0x1UL << DMA_RCFGLOCKR_LOCK15_Pos)      /*!< 0x00008000 */
11800 #define DMA_RCFGLOCKR_LOCK15                 DMA_RCFGLOCKR_LOCK15_Msk                 /*!< Lock the configuration of Channel 15 */
11801 
11802 /*******************  Bit definition for DMA_MISR register  ****************/
11803 #define DMA_MISR_MIS0_Pos                   (0U)
11804 #define DMA_MISR_MIS0_Msk                   (0x1UL << DMA_MISR_MIS0_Pos)            /*!< 0x00000001 */
11805 #define DMA_MISR_MIS0                       DMA_MISR_MIS0_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 0 */
11806 #define DMA_MISR_MIS1_Pos                   (1U)
11807 #define DMA_MISR_MIS1_Msk                   (0x1UL << DMA_MISR_MIS1_Pos)            /*!< 0x00000002 */
11808 #define DMA_MISR_MIS1                       DMA_MISR_MIS1_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 1 */
11809 #define DMA_MISR_MIS2_Pos                   (2U)
11810 #define DMA_MISR_MIS2_Msk                   (0x1UL << DMA_MISR_MIS2_Pos)            /*!< 0x00000004 */
11811 #define DMA_MISR_MIS2                       DMA_MISR_MIS2_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 2 */
11812 #define DMA_MISR_MIS3_Pos                   (3U)
11813 #define DMA_MISR_MIS3_Msk                   (0x1UL << DMA_MISR_MIS3_Pos)            /*!< 0x00000008 */
11814 #define DMA_MISR_MIS3                       DMA_MISR_MIS3_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 3 */
11815 #define DMA_MISR_MIS4_Pos                   (4U)
11816 #define DMA_MISR_MIS4_Msk                   (0x1UL << DMA_MISR_MIS4_Pos)            /*!< 0x00000010 */
11817 #define DMA_MISR_MIS4                       DMA_MISR_MIS4_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 4 */
11818 #define DMA_MISR_MIS5_Pos                   (5U)
11819 #define DMA_MISR_MIS5_Msk                   (0x1UL << DMA_MISR_MIS5_Pos)            /*!< 0x00000020 */
11820 #define DMA_MISR_MIS5                       DMA_MISR_MIS5_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 5 */
11821 #define DMA_MISR_MIS6_Pos                   (6U)
11822 #define DMA_MISR_MIS6_Msk                   (0x1UL << DMA_MISR_MIS6_Pos)            /*!< 0x00000040 */
11823 #define DMA_MISR_MIS6                       DMA_MISR_MIS6_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 6 */
11824 #define DMA_MISR_MIS7_Pos                   (7U)
11825 #define DMA_MISR_MIS7_Msk                   (0x1UL << DMA_MISR_MIS7_Pos)            /*!< 0x00000080 */
11826 #define DMA_MISR_MIS7                       DMA_MISR_MIS7_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 7 */
11827 #define DMA_MISR_MIS8_Pos                   (8U)
11828 #define DMA_MISR_MIS8_Msk                   (0x1UL << DMA_MISR_MIS8_Pos)            /*!< 0x00000100 */
11829 #define DMA_MISR_MIS8                       DMA_MISR_MIS8_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 8 */
11830 #define DMA_MISR_MIS9_Pos                   (9U)
11831 #define DMA_MISR_MIS9_Msk                   (0x1UL << DMA_MISR_MIS9_Pos)            /*!< 0x00000200 */
11832 #define DMA_MISR_MIS9                       DMA_MISR_MIS9_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 9 */
11833 #define DMA_MISR_MIS10_Pos                  (10U)
11834 #define DMA_MISR_MIS10_Msk                  (0x1UL << DMA_MISR_MIS10_Pos)           /*!< 0x00000400 */
11835 #define DMA_MISR_MIS10                      DMA_MISR_MIS10_Msk                      /*!< Masked Interrupt State of Non-Secure Channel 10 */
11836 #define DMA_MISR_MIS11_Pos                  (11U)
11837 #define DMA_MISR_MIS11_Msk                  (0x1UL << DMA_MISR_MIS11_Pos)           /*!< 0x00000800 */
11838 #define DMA_MISR_MIS11                      DMA_MISR_MIS11_Msk                      /*!< Masked Interrupt State of Non-Secure Channel 11 */
11839 #define DMA_MISR_MIS12_Pos                  (12U)
11840 #define DMA_MISR_MIS12_Msk                  (0x1UL << DMA_MISR_MIS12_Pos)           /*!< 0x00001000 */
11841 #define DMA_MISR_MIS12                      DMA_MISR_MIS12_Msk                      /*!< Masked Interrupt State of Non-Secure Channel 12 */
11842 #define DMA_MISR_MIS13_Pos                  (13U)
11843 #define DMA_MISR_MIS13_Msk                  (0x1UL << DMA_MISR_MIS13_Pos)           /*!< 0x00002000 */
11844 #define DMA_MISR_MIS13                      DMA_MISR_MIS13_Msk                      /*!< Masked Interrupt State of Non-Secure Channel 13 */
11845 #define DMA_MISR_MIS14_Pos                  (14U)
11846 #define DMA_MISR_MIS14_Msk                  (0x1UL << DMA_MISR_MIS14_Pos)           /*!< 0x00004000 */
11847 #define DMA_MISR_MIS14                      DMA_MISR_MIS14_Msk                      /*!< Masked Interrupt State of Non-Secure Channel 14 */
11848 #define DMA_MISR_MIS15_Pos                  (15U)
11849 #define DMA_MISR_MIS15_Msk                  (0x1UL << DMA_MISR_MIS15_Pos)           /*!< 0x00008000 */
11850 #define DMA_MISR_MIS15                      DMA_MISR_MIS14_Msk                      /*!< Masked Interrupt State of Non-Secure Channel 15 */
11851 
11852 /*******************  Bit definition for DMA_SMISR register  ****************/
11853 #define DMA_SMISR_MIS0_Pos       (0U)
11854 #define DMA_SMISR_MIS0_Msk       (0x1UL << DMA_SMISR_MIS0_Pos)                  /*!< 0x00000001 */
11855 #define DMA_SMISR_MIS0           DMA_SMISR_MIS0_Msk                            /*!< Masked Interrupt State of Secure Channel 0 */
11856 #define DMA_SMISR_MIS1_Pos       (1U)
11857 #define DMA_SMISR_MIS1_Msk       (0x1UL << DMA_SMISR_MIS1_Pos)                  /*!< 0x00000002 */
11858 #define DMA_SMISR_MIS1           DMA_SMISR_MIS1_Msk                            /*!< Masked Interrupt State of Secure Channel 1 */
11859 #define DMA_SMISR_MIS2_Pos       (2U)
11860 #define DMA_SMISR_MIS2_Msk       (0x1UL << DMA_SMISR_MIS2_Pos)                  /*!< 0x00000004 */
11861 #define DMA_SMISR_MIS2           DMA_SMISR_MIS2_Msk                            /*!< Masked Interrupt State of Secure Channel 2 */
11862 #define DMA_SMISR_MIS3_Pos       (3U)
11863 #define DMA_SMISR_MIS3_Msk       (0x1UL << DMA_SMISR_MIS3_Pos)                  /*!< 0x00000008 */
11864 #define DMA_SMISR_MIS3           DMA_SMISR_MIS3_Msk                            /*!< Masked Interrupt State of Secure Channel 3 */
11865 #define DMA_SMISR_MIS4_Pos       (4U)
11866 #define DMA_SMISR_MIS4_Msk       (0x1UL << DMA_SMISR_MIS4_Pos)                  /*!< 0x00000010 */
11867 #define DMA_SMISR_MIS4           DMA_SMISR_MIS4_Msk                            /*!< Masked Interrupt State of Secure Channel 4 */
11868 #define DMA_SMISR_MIS5_Pos       (5U)
11869 #define DMA_SMISR_MIS5_Msk       (0x1UL << DMA_SMISR_MIS5_Pos)                  /*!< 0x00000020 */
11870 #define DMA_SMISR_MIS5           DMA_SMISR_MIS5_Msk                            /*!< Masked Interrupt State of Secure Channel 5 */
11871 #define DMA_SMISR_MIS6_Pos       (6U)
11872 #define DMA_SMISR_MIS6_Msk       (0x1UL << DMA_SMISR_MIS6_Pos)                  /*!< 0x00000040 */
11873 #define DMA_SMISR_MIS6           DMA_SMISR_MIS6_Msk                            /*!< Masked Interrupt State of Secure Channel 6 */
11874 #define DMA_SMISR_MIS7_Pos       (7U)
11875 #define DMA_SMISR_MIS7_Msk       (0x1UL << DMA_SMISR_MIS7_Pos)                  /*!< 0x00000080 */
11876 #define DMA_SMISR_MIS7           DMA_SMISR_MIS7_Msk                            /*!< Masked Interrupt State of Secure Channel 7 */
11877 #define DMA_SMISR_MIS8_Pos       (8U)
11878 #define DMA_SMISR_MIS8_Msk       (0x1UL << DMA_SMISR_MIS8_Pos)                  /*!< 0x00000100 */
11879 #define DMA_SMISR_MIS8           DMA_SMISR_MIS8_Msk                            /*!< Masked Interrupt State of Secure Channel 8 */
11880 #define DMA_SMISR_MIS9_Pos       (9U)
11881 #define DMA_SMISR_MIS9_Msk       (0x1UL << DMA_SMISR_MIS9_Pos)                  /*!< 0x00000200 */
11882 #define DMA_SMISR_MIS9           DMA_SMISR_MIS9_Msk                            /*!< Masked Interrupt State of Secure Channel 9 */
11883 #define DMA_SMISR_MIS10_Pos      (10U)
11884 #define DMA_SMISR_MIS10_Msk      (0x1UL << DMA_SMISR_MIS10_Pos)                 /*!< 0x00000400 */
11885 #define DMA_SMISR_MIS10          DMA_SMISR_MIS10_Msk                           /*!< Masked Interrupt State of Secure Channel 10 */
11886 #define DMA_SMISR_MIS11_Pos      (11U)
11887 #define DMA_SMISR_MIS11_Msk      (0x1UL << DMA_SMISR_MIS11_Pos)                 /*!< 0x00000800 */
11888 #define DMA_SMISR_MIS11          DMA_SMISR_MIS11_Msk                           /*!< Masked Interrupt State of Secure Channel 11 */
11889 #define DMA_SMISR_MIS12_Pos      (12U)
11890 #define DMA_SMISR_MIS12_Msk      (0x1UL << DMA_SMISR_MIS12_Pos)                 /*!< 0x00001000 */
11891 #define DMA_SMISR_MIS12          DMA_SMISR_MIS12_Msk                           /*!< Masked Interrupt State of Secure Channel 12 */
11892 #define DMA_SMISR_MIS13_Pos      (13U)
11893 #define DMA_SMISR_MIS13_Msk      (0x1UL << DMA_SMISR_MIS13_Pos)                 /*!< 0x00002000 */
11894 #define DMA_SMISR_MIS13          DMA_SMISR_MIS13_Msk                           /*!< Masked Interrupt State of Secure Channel 13 */
11895 #define DMA_SMISR_MIS14_Pos      (14U)
11896 #define DMA_SMISR_MIS14_Msk      (0x1UL << DMA_SMISR_MIS14_Pos)                 /*!< 0x00004000 */
11897 #define DMA_SMISR_MIS14          DMA_SMISR_MIS14_Msk                           /*!< Masked Interrupt State of Secure Channel 14 */
11898 #define DMA_SMISR_MIS15_Pos      (15U)
11899 #define DMA_SMISR_MIS15_Msk      (0x1UL << DMA_SMISR_MIS15_Pos)                 /*!< 0x00008000 */
11900 #define DMA_SMISR_MIS15          DMA_SMISR_MIS14_Msk                           /*!< Masked Interrupt State of Secure Channel 15 */
11901 
11902 /*******************  Bit definition for DMA_CLBAR register  ****************/
11903 #define DMA_CLBAR_LBA_Pos                   (16U)
11904 #define DMA_CLBAR_LBA_Msk                   (0xFFFFUL << DMA_CLBAR_LBA_Pos)         /*!< 0xFFFF0000 */
11905 #define DMA_CLBAR_LBA                       DMA_CLBAR_LBA_Msk                       /*!< Linked-list Base Address of DMA channel x */
11906 
11907 /*******************  Bit definition for DMA_CCIDCFGR register  *******************/
11908 #define DMA_CCIDCFGR_CFEN_Pos           (0U)
11909 #define DMA_CCIDCFGR_CFEN_Msk           (0x1UL << DMA_CCIDCFGR_CFEN_Pos)         /*!< 0x00000001 */
11910 #define DMA_CCIDCFGR_CFEN               DMA_CCIDCFGR_CFEN_Msk                   /*!< CID filtering enable of the channel x */
11911 #define DMA_CCIDCFGR_SCID_Pos           (4U)
11912 #define DMA_CCIDCFGR_SCID_Msk           (0x7UL << DMA_CCIDCFGR_SCID_Pos)         /*!< 0x00000070 */
11913 #define DMA_CCIDCFGR_SCID               DMA_CCIDCFGR_SCID_Msk                   /*!< select a static CID to the channel x */
11914 
11915 /*******************  Bit definition for DMA_CFCR register  *******************/
11916 #define DMA_CFCR_TCF_Pos                    (8U)
11917 #define DMA_CFCR_TCF_Msk                    (0x1UL << DMA_CFCR_TCF_Pos)             /*!< 0x00000100 */
11918 #define DMA_CFCR_TCF                        DMA_CFCR_TCF_Msk                        /*!< Transfer complete flag clear */
11919 #define DMA_CFCR_HTF_Pos                    (9U)
11920 #define DMA_CFCR_HTF_Msk                    (0x1UL << DMA_CFCR_HTF_Pos)             /*!< 0x00000200 */
11921 #define DMA_CFCR_HTF                        DMA_CFCR_HTF_Msk                        /*!< Half transfer complete flag clear */
11922 #define DMA_CFCR_DTEF_Pos                   (10U)
11923 #define DMA_CFCR_DTEF_Msk                   (0x1UL << DMA_CFCR_DTEF_Pos)            /*!< 0x00000400 */
11924 #define DMA_CFCR_DTEF                       DMA_CFCR_DTEF_Msk                       /*!< Data transfer error flag clear */
11925 #define DMA_CFCR_ULEF_Pos                   (11U)
11926 #define DMA_CFCR_ULEF_Msk                   (0x1UL << DMA_CFCR_ULEF_Pos)            /*!< 0x00000800 */
11927 #define DMA_CFCR_ULEF                       DMA_CFCR_ULEF_Msk                       /*!< Update linked-list item error flag clear */
11928 #define DMA_CFCR_USEF_Pos                   (12U)
11929 #define DMA_CFCR_USEF_Msk                   (0x1UL << DMA_CFCR_USEF_Pos)            /*!< 0x00001000 */
11930 #define DMA_CFCR_USEF                       DMA_CFCR_USEF_Msk                       /*!< User setting error flag clear */
11931 #define DMA_CFCR_SUSPF_Pos                  (13U)
11932 #define DMA_CFCR_SUSPF_Msk                  (0x1UL << DMA_CFCR_SUSPF_Pos)           /*!< 0x00002000 */
11933 #define DMA_CFCR_SUSPF                      DMA_CFCR_SUSPF_Msk                      /*!< Completed suspension flag clear */
11934 #define DMA_CFCR_TOF_Pos                    (14U)
11935 #define DMA_CFCR_TOF_Msk                    (0x1UL << DMA_CFCR_TOF_Pos)             /*!< 0x00004000 */
11936 #define DMA_CFCR_TOF                        DMA_CFCR_TOF_Msk                        /*!< Trigger overrun clear flag */
11937 
11938 /*******************  Bit definition for DMA_CSR register  *******************/
11939 #define DMA_CSR_IDLEF_Pos                   (0U)
11940 #define DMA_CSR_IDLEF_Msk                   (0x1UL << DMA_CSR_IDLEF_Pos)            /*!< 0x00000001 */
11941 #define DMA_CSR_IDLEF                       DMA_CSR_IDLEF_Msk                       /*!< Idle flag */
11942 #define DMA_CSR_TCF_Pos                     (8U)
11943 #define DMA_CSR_TCF_Msk                     (0x1UL << DMA_CSR_TCF_Pos)              /*!< 0x00000100 */
11944 #define DMA_CSR_TCF                         DMA_CSR_TCF_Msk                         /*!< Transfer complete flag */
11945 #define DMA_CSR_HTF_Pos                     (9U)
11946 #define DMA_CSR_HTF_Msk                     (0x1UL << DMA_CSR_HTF_Pos)              /*!< 0x00000200 */
11947 #define DMA_CSR_HTF                         DMA_CSR_HTF_Msk                         /*!< Half transfer complete flag */
11948 #define DMA_CSR_DTEF_Pos                    (10U)
11949 #define DMA_CSR_DTEF_Msk                    (0x1UL << DMA_CSR_DTEF_Pos)             /*!< 0x00000400 */
11950 #define DMA_CSR_DTEF                        DMA_CSR_DTEF_Msk                        /*!< Data transfer error flag */
11951 #define DMA_CSR_ULEF_Pos                    (11U)
11952 #define DMA_CSR_ULEF_Msk                    (0x1UL << DMA_CSR_ULEF_Pos)             /*!< 0x00000800 */
11953 #define DMA_CSR_ULEF                        DMA_CSR_ULEF_Msk                        /*!< Update linked-list item error flag */
11954 #define DMA_CSR_USEF_Pos                    (12U)
11955 #define DMA_CSR_USEF_Msk                    (0x1UL << DMA_CSR_USEF_Pos)             /*!< 0x00001000 */
11956 #define DMA_CSR_USEF                        DMA_CSR_USEF_Msk                        /*!< User setting error flag */
11957 #define DMA_CSR_SUSPF_Pos                   (13U)
11958 #define DMA_CSR_SUSPF_Msk                   (0x1UL << DMA_CSR_SUSPF_Pos)            /*!< 0x00002000 */
11959 #define DMA_CSR_SUSPF                       DMA_CSR_SUSPF_Msk                       /*!< User setting error flag */
11960 #define DMA_CSR_TOF_Pos                     (14U)
11961 #define DMA_CSR_TOF_Msk                     (0x1UL << DMA_CSR_TOF_Pos)              /*!< 0x00004000 */
11962 #define DMA_CSR_TOF                         DMA_CSR_TOF_Msk                         /*!< Trigger overrun flag */
11963 #define DMA_CSR_FIFOL_Pos                   (16U)
11964 #define DMA_CSR_FIFOL_Msk                   (0xFFUL << DMA_CSR_FIFOL_Pos)           /*!< 0x00FF0000 */
11965 #define DMA_CSR_FIFOL                       DMA_CSR_FIFOL_Msk                       /*!< Monitored FIFO level in bytes */
11966 
11967 /*******************  Bit definition for DMA_CCR register  ********************/
11968 #define DMA_CCR_EN_Pos                      (0U)
11969 #define DMA_CCR_EN_Msk                      (0x1UL << DMA_CCR_EN_Pos)               /*!< 0x00000001 */
11970 #define DMA_CCR_EN                          DMA_CCR_EN_Msk                          /*!< Channel enable */
11971 #define DMA_CCR_RESET_Pos                   (1U)
11972 #define DMA_CCR_RESET_Msk                   (0x1UL << DMA_CCR_RESET_Pos)            /*!< 0x00000002 */
11973 #define DMA_CCR_RESET                       DMA_CCR_RESET_Msk                       /*!< Channel reset */
11974 #define DMA_CCR_SUSP_Pos                    (2U)
11975 #define DMA_CCR_SUSP_Msk                    (0x1UL << DMA_CCR_SUSP_Pos)             /*!< 0x00000004 */
11976 #define DMA_CCR_SUSP                        DMA_CCR_SUSP_Msk                        /*!< Channel suspend */
11977 #define DMA_CCR_TCIE_Pos                    (8U)
11978 #define DMA_CCR_TCIE_Msk                    (0x1UL << DMA_CCR_TCIE_Pos)             /*!< 0x00000100 */
11979 #define DMA_CCR_TCIE                        DMA_CCR_TCIE_Msk                        /*!< Transfer complete interrupt enable */
11980 #define DMA_CCR_HTIE_Pos                    (9U)
11981 #define DMA_CCR_HTIE_Msk                    (0x1UL << DMA_CCR_HTIE_Pos)             /*!< 0x00000200 */
11982 #define DMA_CCR_HTIE                        DMA_CCR_HTIE_Msk                        /*!< Half transfer complete interrupt enable */
11983 #define DMA_CCR_DTEIE_Pos                   (10U)
11984 #define DMA_CCR_DTEIE_Msk                   (0x1UL << DMA_CCR_DTEIE_Pos)            /*!< 0x00000400 */
11985 #define DMA_CCR_DTEIE                       DMA_CCR_DTEIE_Msk                       /*!< Data transfer error interrupt enable */
11986 #define DMA_CCR_ULEIE_Pos                   (11U)
11987 #define DMA_CCR_ULEIE_Msk                   (0x1UL << DMA_CCR_ULEIE_Pos)            /*!< 0x00000800 */
11988 #define DMA_CCR_ULEIE                       DMA_CCR_ULEIE_Msk                       /*!< Update linked-list item error interrupt enable */
11989 #define DMA_CCR_USEIE_Pos                   (12U)
11990 #define DMA_CCR_USEIE_Msk                   (0x1UL << DMA_CCR_USEIE_Pos)            /*!< 0x00001000 */
11991 #define DMA_CCR_USEIE                       DMA_CCR_USEIE_Msk                       /*!< User setting error interrupt enable */
11992 #define DMA_CCR_SUSPIE_Pos                  (13U)
11993 #define DMA_CCR_SUSPIE_Msk                  (0x1UL << DMA_CCR_SUSPIE_Pos)           /*!< 0x00002000 */
11994 #define DMA_CCR_SUSPIE                      DMA_CCR_SUSPIE_Msk                      /*!< Completed suspension interrupt enable */
11995 #define DMA_CCR_TOIE_Pos                    (14U)
11996 #define DMA_CCR_TOIE_Msk                    (0x1UL << DMA_CCR_TOIE_Pos)             /*!< 0x00004000 */
11997 #define DMA_CCR_TOIE                        DMA_CCR_TOIE_Msk                        /*!< Trigger overrun interrupt enable */
11998 #define DMA_CCR_LSM_Pos                     (16U)
11999 #define DMA_CCR_LSM_Msk                     (0x1UL << DMA_CCR_LSM_Pos)              /*!< 0x00010000 */
12000 #define DMA_CCR_LSM                         DMA_CCR_LSM_Msk                         /*!< Link step mode */
12001 #define DMA_CCR_LAP_Pos                     (17U)
12002 #define DMA_CCR_LAP_Msk                     (0x1UL << DMA_CCR_LAP_Pos)              /*!< 0x00020000 */
12003 #define DMA_CCR_LAP                         DMA_CCR_LAP_Msk                         /*!< Linked-list allocated port */
12004 #define DMA_CCR_PRIO_Pos                    (22U)
12005 #define DMA_CCR_PRIO_Msk                    (0x3UL << DMA_CCR_PRIO_Pos)             /*!< 0x00C00000 */
12006 #define DMA_CCR_PRIO                        DMA_CCR_PRIO_Msk                        /*!< Priority level */
12007 #define DMA_CCR_PRIO_0                      (0x1UL << DMA_CCR_PRIO_Pos)             /*!< 0x00400000 */
12008 #define DMA_CCR_PRIO_1                      (0x2UL << DMA_CCR_PRIO_Pos)             /*!< 0x00800000 */
12009 
12010 /*******************  Bit definition for DMA_CTR1 register  *******************/
12011 #define DMA_CTR1_SDW_LOG2_Pos               (0U)
12012 #define DMA_CTR1_SDW_LOG2_Msk               (0x3UL << DMA_CTR1_SDW_LOG2_Pos)        /*!< 0x00000003 */
12013 #define DMA_CTR1_SDW_LOG2                   DMA_CTR1_SDW_LOG2_Msk                   /*!< Binary logarithm of the source data width of a burst */
12014 #define DMA_CTR1_SDW_LOG2_0                 (0x1UL << DMA_CTR1_SDW_LOG2_Pos)        /*!< Bit 0 */
12015 #define DMA_CTR1_SDW_LOG2_1                 (0x2UL << DMA_CTR1_SDW_LOG2_Pos)        /*!< Bit 1 */
12016 #define DMA_CTR1_SINC_Pos                   (3U)
12017 #define DMA_CTR1_SINC_Msk                   (0x1UL << DMA_CTR1_SINC_Pos)            /*!< 0x00000008 */
12018 #define DMA_CTR1_SINC                       DMA_CTR1_SINC_Msk                       /*!< Source incrementing burst */
12019 #define DMA_CTR1_SBL_1_Pos                  (4U)
12020 #define DMA_CTR1_SBL_1_Msk                  (0x3FUL << DMA_CTR1_SBL_1_Pos)          /*!< 0x000003F0 */
12021 #define DMA_CTR1_SBL_1                      DMA_CTR1_SBL_1_Msk                      /*!< Source burst length minus 1 */
12022 #define DMA_CTR1_PAM_Pos                    (11U)
12023 #define DMA_CTR1_PAM_Msk                    (0x3UL << DMA_CTR1_PAM_Pos)             /*!< 0x0001800 */
12024 #define DMA_CTR1_PAM                        DMA_CTR1_PAM_Msk                        /*!< Padding / alignment mode */
12025 #define DMA_CTR1_PAM_0                      (0x1UL << DMA_CTR1_PAM_Pos)             /*!< Bit 0 */
12026 #define DMA_CTR1_PAM_1                      (0x2UL << DMA_CTR1_PAM_Pos)             /*!< Bit 1 */
12027 #define DMA_CTR1_SBX_Pos                    (13U)
12028 #define DMA_CTR1_SBX_Msk                    (0x1UL << DMA_CTR1_SBX_Pos)             /*!< 0x00002000 */
12029 #define DMA_CTR1_SBX                        DMA_CTR1_SBX_Msk                        /*!< Source byte exchange within the unaligned half-word of each source word */
12030 #define DMA_CTR1_SAP_Pos                    (14U)
12031 #define DMA_CTR1_SAP_Msk                    (0x1UL << DMA_CTR1_SAP_Pos)             /*!< 0x00004000 */
12032 #define DMA_CTR1_SAP                        DMA_CTR1_SAP_Msk                        /*!< Source allocated port */
12033 #define DMA_CTR1_SSEC_Pos                   (15U)
12034 #define DMA_CTR1_SSEC_Msk                   (0x1UL << DMA_CTR1_SSEC_Pos)            /*!< 0x00008000 */
12035 #define DMA_CTR1_SSEC                       DMA_CTR1_SSEC_Msk                       /*!< Security attribute of the DMA transfer from the source */
12036 #define DMA_CTR1_DDW_LOG2_Pos               (16U)
12037 #define DMA_CTR1_DDW_LOG2_Msk               (0x3UL << DMA_CTR1_DDW_LOG2_Pos)        /*!< 0x00030000 */
12038 #define DMA_CTR1_DDW_LOG2                   DMA_CTR1_DDW_LOG2_Msk                   /*!< Binary logarithm of the destination data width of a burst */
12039 #define DMA_CTR1_DDW_LOG2_0                 (0x1UL << DMA_CTR1_DDW_LOG2_Pos)        /*!< Bit 0 */
12040 #define DMA_CTR1_DDW_LOG2_1                 (0x2UL << DMA_CTR1_DDW_LOG2_Pos)        /*!< Bit 1 */
12041 #define DMA_CTR1_DINC_Pos                   (19U)
12042 #define DMA_CTR1_DINC_Msk                   (0x1UL << DMA_CTR1_DINC_Pos)            /*!< 0x00080000 */
12043 #define DMA_CTR1_DINC                       DMA_CTR1_DINC_Msk                       /*!< Destination incrementing burst */
12044 #define DMA_CTR1_DBL_1_Pos                  (20U)
12045 #define DMA_CTR1_DBL_1_Msk                  (0x3FUL << DMA_CTR1_DBL_1_Pos)          /*!< 0x03F00000 */
12046 #define DMA_CTR1_DBL_1                      DMA_CTR1_DBL_1_Msk                      /*!< Destination burst length minus 1 */
12047 #define DMA_CTR1_DBX_Pos                    (26U)
12048 #define DMA_CTR1_DBX_Msk                    (0x1UL << DMA_CTR1_DBX_Pos)             /*!< 0x04000000 */
12049 #define DMA_CTR1_DBX                        DMA_CTR1_DBX_Msk                        /*!< Destination byte exchange */
12050 #define DMA_CTR1_DHX_Pos                    (27U)
12051 #define DMA_CTR1_DHX_Msk                    (0x1UL << DMA_CTR1_DHX_Pos)             /*!< 0x08000000 */
12052 #define DMA_CTR1_DHX                        DMA_CTR1_DHX_Msk                        /*!< Destination half-word exchange */
12053 #define DMA_CTR1_DWX_Pos                    (28U)
12054 #define DMA_CTR1_DWX_Msk                    (0x1UL << DMA_CTR1_DWX_Pos)             /*!< 0x10000000 */
12055 #define DMA_CTR1_DWX                        DMA_CTR1_DWX_Msk                        /*!< Destination word-word exchange */
12056 #define DMA_CTR1_DAP_Pos                    (30U)
12057 #define DMA_CTR1_DAP_Msk                    (0x1UL << DMA_CTR1_DAP_Pos)             /*!< 0x40000000 */
12058 #define DMA_CTR1_DAP                        DMA_CTR1_DAP_Msk                        /*!< Destination allocated port */
12059 #define DMA_CTR1_DSEC_Pos                   (31U)
12060 #define DMA_CTR1_DSEC_Msk                   (0x1UL << DMA_CTR1_DSEC_Pos)            /*!< 0x80000000 */
12061 #define DMA_CTR1_DSEC                       DMA_CTR1_DSEC_Msk                       /*!< Security attribute of the DMA transfer from the destination */
12062 
12063 /******************  Bit definition for DMA_CTR2 register  *******************/
12064 #define DMA_CTR2_REQSEL_Pos                 (0U)
12065 #define DMA_CTR2_REQSEL_Msk                 (0xFFUL << DMA_CTR2_REQSEL_Pos)         /*!< 0x000000FF */
12066 #define DMA_CTR2_REQSEL                     DMA_CTR2_REQSEL_Msk                     /*!< DMA hardware request selection */
12067 #define DMA_CTR2_SWREQ_Pos                  (9U)
12068 #define DMA_CTR2_SWREQ_Msk                  (0x1UL << DMA_CTR2_SWREQ_Pos)           /*!< 0x00000200 */
12069 #define DMA_CTR2_SWREQ                      DMA_CTR2_SWREQ_Msk                      /*!< Software request */
12070 #define DMA_CTR2_DREQ_Pos                   (10U)
12071 #define DMA_CTR2_DREQ_Msk                   (0x1UL << DMA_CTR2_DREQ_Pos)            /*!< 0x00000400 */
12072 #define DMA_CTR2_DREQ                       DMA_CTR2_DREQ_Msk                       /*!< Destination hardware request */
12073 #define DMA_CTR2_BREQ_Pos                   (11U)
12074 #define DMA_CTR2_BREQ_Msk                   (0x1UL << DMA_CTR2_BREQ_Pos)            /*!< 0x00000800 */
12075 #define DMA_CTR2_BREQ                       DMA_CTR2_BREQ_Msk                       /*!< Block hardware request */
12076 #define DMA_CTR2_PFREQ_Pos                  (12U)
12077 #define DMA_CTR2_PFREQ_Msk                  (0x1UL << DMA_CTR2_PFREQ_Pos)           /*!< 0x00001000 */
12078 #define DMA_CTR2_PFREQ                      DMA_CTR2_PFREQ_Msk                      /*!< Hardware request in peripheral flow control mode */
12079 #define DMA_CTR2_TRIGM_Pos                  (14U)
12080 #define DMA_CTR2_TRIGM_Msk                  (0x3UL << DMA_CTR2_TRIGM_Pos)           /*!< 0x0000C000 */
12081 #define DMA_CTR2_TRIGM                      DMA_CTR2_TRIGM_Msk                      /*!< Trigger mode */
12082 #define DMA_CTR2_TRIGM_0                    (0x1UL << DMA_CTR2_TRIGM_Pos)           /*!< Bit 0 */
12083 #define DMA_CTR2_TRIGM_1                    (0x2UL << DMA_CTR2_TRIGM_Pos)           /*!< Bit 1 */
12084 #define DMA_CTR2_TRIGSEL_Pos                (16U)
12085 #define DMA_CTR2_TRIGSEL_Msk                (0x7FUL << DMA_CTR2_TRIGSEL_Pos)        /*!< 0x007F0000 */
12086 #define DMA_CTR2_TRIGSEL                    DMA_CTR2_TRIGSEL_Msk                    /*!< Trigger event input selection */
12087 #define DMA_CTR2_TRIGPOL_Pos                (24U)
12088 #define DMA_CTR2_TRIGPOL_Msk                (0x3UL << DMA_CTR2_TRIGPOL_Pos)         /*!< 0x03000000 */
12089 #define DMA_CTR2_TRIGPOL                    DMA_CTR2_TRIGPOL_Msk                    /*!< Trigger event polarity */
12090 #define DMA_CTR2_TRIGPOL_0                  (0x1UL << DMA_CTR2_TRIGPOL_Pos)         /*!< Bit 0 */
12091 #define DMA_CTR2_TRIGPOL_1                  (0x2UL << DMA_CTR2_TRIGPOL_Pos)         /*!< Bit 1 */
12092 #define DMA_CTR2_TCEM_Pos                   (30U)
12093 #define DMA_CTR2_TCEM_Msk                   (0x3UL << DMA_CTR2_TCEM_Pos)            /*!< 0xC0000000 */
12094 #define DMA_CTR2_TCEM                       DMA_CTR2_TCEM_Msk                       /*!< Transfer complete event mode */
12095 #define DMA_CTR2_TCEM_0                     (0x1UL << DMA_CTR2_TCEM_Pos)            /*!< Bit 0 */
12096 #define DMA_CTR2_TCEM_1                     (0x2UL << DMA_CTR2_TCEM_Pos)            /*!< Bit 1 */
12097 
12098 /******************  Bit definition for DMA_CBR1 register  *******************/
12099 #define DMA_CBR1_BNDT_Pos                   (0U)
12100 #define DMA_CBR1_BNDT_Msk                   (0xFFFFUL << DMA_CBR1_BNDT_Pos)         /*!< 0x0000FFFF */
12101 #define DMA_CBR1_BNDT                       DMA_CBR1_BNDT_Msk                       /*!< Block number of data bytes to transfer from the source */
12102 #define DMA_CBR1_BRC_Pos                    (16U)
12103 #define DMA_CBR1_BRC_Msk                    (0x7FFUL << DMA_CBR1_BRC_Pos)           /*!< 0x07FF0000 */
12104 #define DMA_CBR1_BRC                        DMA_CBR1_BRC_Msk                        /*!< Block repeat counter */
12105 #define DMA_CBR1_SDEC_Pos                   (28U)
12106 #define DMA_CBR1_SDEC_Msk                   (0x1UL << DMA_CBR1_SDEC_Pos)            /*!< 0x10000000 */
12107 #define DMA_CBR1_SDEC                       DMA_CBR1_SDEC_Msk                       /*!< Source address decrement */
12108 #define DMA_CBR1_DDEC_Pos                   (29U)
12109 #define DMA_CBR1_DDEC_Msk                   (0x1UL << DMA_CBR1_DDEC_Pos)            /*!< 0x20000000 */
12110 #define DMA_CBR1_DDEC                       DMA_CBR1_DDEC_Msk                       /*!< Destination address decrement */
12111 #define DMA_CBR1_BRSDEC_Pos                 (30U)
12112 #define DMA_CBR1_BRSDEC_Msk                 (0x1UL << DMA_CBR1_BRSDEC_Pos)          /*!< 0x40000000 */
12113 #define DMA_CBR1_BRSDEC                     DMA_CBR1_BRSDEC_Msk                     /*!< Block repeat source address decrement */
12114 #define DMA_CBR1_BRDDEC_Pos                 (31U)
12115 #define DMA_CBR1_BRDDEC_Msk                 (0x1UL << DMA_CBR1_BRDDEC_Pos)          /*!< 0x80000000 */
12116 #define DMA_CBR1_BRDDEC                     DMA_CBR1_BRDDEC_Msk                     /*!< Block repeat destination address decrement */
12117 
12118 /******************  Bit definition for DMA_CSAR register  ********************/
12119 #define DMA_CSAR_SA_Pos                     (0U)
12120 #define DMA_CSAR_SA_Msk                     (0xFFFFFFFFUL << DMA_CSAR_SA_Pos)       /*!< 0xFFFFFFFF */
12121 #define DMA_CSAR_SA                         DMA_CSAR_SA_Msk                         /*!< Source Address */
12122 
12123 /******************  Bit definition for DMA_CDAR register  *******************/
12124 #define DMA_CDAR_DA_Pos                     (0U)
12125 #define DMA_CDAR_DA_Msk                     (0xFFFFFFFFUL << DMA_CDAR_DA_Pos)       /*!< 0xFFFFFFFF */
12126 #define DMA_CDAR_DA                         DMA_CDAR_DA_Msk                         /*!< Destination address */
12127 
12128 /******************  Bit definition for DMA_CTR3 register  *******************/
12129 #define DMA_CTR3_SAO_Pos                    (0U)
12130 #define DMA_CTR3_SAO_Msk                    (0x1FFFUL << DMA_CTR3_SAO_Pos)          /*!< 0x00001FFF */
12131 #define DMA_CTR3_SAO                        DMA_CTR3_SAO_Msk                        /*!< Source address offset increment */
12132 #define DMA_CTR3_DAO_Pos                    (16U)
12133 #define DMA_CTR3_DAO_Msk                    (0x1FFFUL << DMA_CTR3_DAO_Pos)          /*!< 0x1FFF0000 */
12134 #define DMA_CTR3_DAO                        DMA_CTR3_DAO_Msk                        /*!< Destination address offset increment */
12135 
12136 /******************  Bit definition for DMA_CBR2 register  *******************/
12137 #define DMA_CBR2_BRSAO_Pos                  (0U)
12138 #define DMA_CBR2_BRSAO_Msk                  (0xFFFFUL << DMA_CBR2_BRSAO_Pos)        /*!< 0x0000FFFF */
12139 #define DMA_CBR2_BRSAO                      DMA_CBR2_BRSAO_Msk                      /*!< Block repeated source address offset */
12140 #define DMA_CBR2_BRDAO_Pos                  (16U)
12141 #define DMA_CBR2_BRDAO_Msk                  (0xFFFFUL << DMA_CBR2_BRDAO_Pos)        /*!< 0xFFFF0000 */
12142 #define DMA_CBR2_BRDAO                      DMA_CBR2_BRDAO_Msk                      /*!< Block repeated destination address offset */
12143 
12144 /******************  Bit definition for DMA_CLLR register  *******************/
12145 #define DMA_CLLR_LA_Pos                     (2U)
12146 #define DMA_CLLR_LA_Msk                     (0x3FFFUL << DMA_CLLR_LA_Pos)           /*!< 0x0000FFFC */
12147 #define DMA_CLLR_LA                         DMA_CLLR_LA_Msk                         /*!< Pointer to the next linked-list data structure */
12148 #define DMA_CLLR_ULL_Pos                    (16U)
12149 #define DMA_CLLR_ULL_Msk                    (0x1UL << DMA_CLLR_ULL_Pos)             /*!< 0x00010000 */
12150 #define DMA_CLLR_ULL                        DMA_CLLR_ULL_Msk                        /*!< Update link address register from memory */
12151 #define DMA_CLLR_UB2_Pos                    (25U)
12152 #define DMA_CLLR_UB2_Msk                    (0x1UL << DMA_CLLR_UB2_Pos)             /*!< 0x02000000 */
12153 #define DMA_CLLR_UB2                        DMA_CLLR_UB2_Msk                        /*!< Update block register 2 from memory */
12154 #define DMA_CLLR_UT3_Pos                    (26U)
12155 #define DMA_CLLR_UT3_Msk                    (0x1UL << DMA_CLLR_UT3_Pos)             /*!< 0x04000000 */
12156 #define DMA_CLLR_UT3                        DMA_CLLR_UT3_Msk                        /*!< Update transfer register 3 from SRAM */
12157 #define DMA_CLLR_UDA_Pos                    (27U)
12158 #define DMA_CLLR_UDA_Msk                    (0x1UL << DMA_CLLR_UDA_Pos)             /*!< 0x08000000 */
12159 #define DMA_CLLR_UDA                        DMA_CLLR_UDA_Msk                        /*!< Update destination address register from SRAM */
12160 #define DMA_CLLR_USA_Pos                    (28U)
12161 #define DMA_CLLR_USA_Msk                    (0x1UL << DMA_CLLR_USA_Pos)             /*!< 0x10000000 */
12162 #define DMA_CLLR_USA                        DMA_CLLR_USA_Msk                        /*!< Update source address register from SRAM */
12163 #define DMA_CLLR_UB1_Pos                    (29U)
12164 #define DMA_CLLR_UB1_Msk                    (0x1UL << DMA_CLLR_UB1_Pos)             /*!< 0x20000000 */
12165 #define DMA_CLLR_UB1                        DMA_CLLR_UB1_Msk                        /*!< Update block register 1 from SRAM */
12166 #define DMA_CLLR_UT2_Pos                    (30U)
12167 #define DMA_CLLR_UT2_Msk                    (0x1UL << DMA_CLLR_UT2_Pos)             /*!< 0x40000000 */
12168 #define DMA_CLLR_UT2                        DMA_CLLR_UT2_Msk                        /*!< Update transfer register 2 from SRAM */
12169 #define DMA_CLLR_UT1_Pos                    (31U)
12170 #define DMA_CLLR_UT1_Msk                    (0x1UL << DMA_CLLR_UT1_Pos)             /*!< 0x80000000 */
12171 #define DMA_CLLR_UT1                        DMA_CLLR_UT1_Msk                        /*!< Update transfer register 1 from SRAM */
12172 
12173 
12174 /******************************************************************************/
12175 /*                                                                            */
12176 /*                          DMA2D Controller (DMA2D)                          */
12177 /*                                                                            */
12178 /******************************************************************************/
12179 /********************  Bit definition for DMA2D_CR register  ******************/
12180 #define DMA2D_CR_START_Pos         (0U)
12181 #define DMA2D_CR_START_Msk         (0x1UL << DMA2D_CR_START_Pos)               /*!< 0x00000001 */
12182 #define DMA2D_CR_START             DMA2D_CR_START_Msk                          /*!< Start transfer */
12183 #define DMA2D_CR_SUSP_Pos          (1U)
12184 #define DMA2D_CR_SUSP_Msk          (0x1UL << DMA2D_CR_SUSP_Pos)                /*!< 0x00000002 */
12185 #define DMA2D_CR_SUSP              DMA2D_CR_SUSP_Msk                           /*!< Suspend transfer */
12186 #define DMA2D_CR_ABORT_Pos         (2U)
12187 #define DMA2D_CR_ABORT_Msk         (0x1UL << DMA2D_CR_ABORT_Pos)               /*!< 0x00000004 */
12188 #define DMA2D_CR_ABORT             DMA2D_CR_ABORT_Msk                          /*!< Abort transfer */
12189 #define DMA2D_CR_LOM_Pos           (6U)
12190 #define DMA2D_CR_LOM_Msk           (0x1UL << DMA2D_CR_LOM_Pos)                 /*!< 0x00000040 */
12191 #define DMA2D_CR_LOM               DMA2D_CR_LOM_Msk                            /*!< Line Offset Mode */
12192 #define DMA2D_CR_TEIE_Pos          (8U)
12193 #define DMA2D_CR_TEIE_Msk          (0x1UL << DMA2D_CR_TEIE_Pos)                /*!< 0x00000100 */
12194 #define DMA2D_CR_TEIE              DMA2D_CR_TEIE_Msk                           /*!< Transfer Error Interrupt Enable */
12195 #define DMA2D_CR_TCIE_Pos          (9U)
12196 #define DMA2D_CR_TCIE_Msk          (0x1UL << DMA2D_CR_TCIE_Pos)                /*!< 0x00000200 */
12197 #define DMA2D_CR_TCIE              DMA2D_CR_TCIE_Msk                           /*!< Transfer Complete Interrupt Enable */
12198 #define DMA2D_CR_TWIE_Pos          (10U)
12199 #define DMA2D_CR_TWIE_Msk          (0x1UL << DMA2D_CR_TWIE_Pos)                /*!< 0x00000400 */
12200 #define DMA2D_CR_TWIE              DMA2D_CR_TWIE_Msk                           /*!< Transfer Watermark Interrupt Enable */
12201 #define DMA2D_CR_CAEIE_Pos         (11U)
12202 #define DMA2D_CR_CAEIE_Msk         (0x1UL << DMA2D_CR_CAEIE_Pos)               /*!< 0x00000800 */
12203 #define DMA2D_CR_CAEIE             DMA2D_CR_CAEIE_Msk                          /*!< CLUT Access Error Interrupt Enable */
12204 #define DMA2D_CR_CTCIE_Pos         (12U)
12205 #define DMA2D_CR_CTCIE_Msk         (0x1UL << DMA2D_CR_CTCIE_Pos)               /*!< 0x00001000 */
12206 #define DMA2D_CR_CTCIE             DMA2D_CR_CTCIE_Msk                          /*!< CLUT Transfer Complete Interrupt Enable */
12207 #define DMA2D_CR_CEIE_Pos          (13U)
12208 #define DMA2D_CR_CEIE_Msk          (0x1UL << DMA2D_CR_CEIE_Pos)                /*!< 0x00002000 */
12209 #define DMA2D_CR_CEIE              DMA2D_CR_CEIE_Msk                           /*!< Configuration Error Interrupt Enable */
12210 #define DMA2D_CR_MODE_Pos          (16U)
12211 #define DMA2D_CR_MODE_Msk          (0x7UL << DMA2D_CR_MODE_Pos)                /*!< 0x00070000 */
12212 #define DMA2D_CR_MODE              DMA2D_CR_MODE_Msk                           /*!< DMA2D Mode[2:0] */
12213 #define DMA2D_CR_MODE_0            (0x1UL << DMA2D_CR_MODE_Pos)                /*!< 0x00010000 */
12214 #define DMA2D_CR_MODE_1            (0x2UL << DMA2D_CR_MODE_Pos)                /*!< 0x00020000 */
12215 #define DMA2D_CR_MODE_2            (0x4UL << DMA2D_CR_MODE_Pos)                /*!< 0x00040000 */
12216 
12217 /********************  Bit definition for DMA2D_ISR register  *****************/
12218 #define DMA2D_ISR_TEIF_Pos         (0U)
12219 #define DMA2D_ISR_TEIF_Msk         (0x1UL << DMA2D_ISR_TEIF_Pos)               /*!< 0x00000001 */
12220 #define DMA2D_ISR_TEIF             DMA2D_ISR_TEIF_Msk                          /*!< Transfer Error Interrupt Flag */
12221 #define DMA2D_ISR_TCIF_Pos         (1U)
12222 #define DMA2D_ISR_TCIF_Msk         (0x1UL << DMA2D_ISR_TCIF_Pos)               /*!< 0x00000002 */
12223 #define DMA2D_ISR_TCIF             DMA2D_ISR_TCIF_Msk                          /*!< Transfer Complete Interrupt Flag */
12224 #define DMA2D_ISR_TWIF_Pos         (2U)
12225 #define DMA2D_ISR_TWIF_Msk         (0x1UL << DMA2D_ISR_TWIF_Pos)               /*!< 0x00000004 */
12226 #define DMA2D_ISR_TWIF             DMA2D_ISR_TWIF_Msk                          /*!< Transfer Watermark Interrupt Flag */
12227 #define DMA2D_ISR_CAEIF_Pos        (3U)
12228 #define DMA2D_ISR_CAEIF_Msk        (0x1UL << DMA2D_ISR_CAEIF_Pos)              /*!< 0x00000008 */
12229 #define DMA2D_ISR_CAEIF            DMA2D_ISR_CAEIF_Msk                         /*!< CLUT Access Error Interrupt Flag */
12230 #define DMA2D_ISR_CTCIF_Pos        (4U)
12231 #define DMA2D_ISR_CTCIF_Msk        (0x1UL << DMA2D_ISR_CTCIF_Pos)              /*!< 0x00000010 */
12232 #define DMA2D_ISR_CTCIF            DMA2D_ISR_CTCIF_Msk                         /*!< CLUT Transfer Complete Interrupt Flag */
12233 #define DMA2D_ISR_CEIF_Pos         (5U)
12234 #define DMA2D_ISR_CEIF_Msk         (0x1UL << DMA2D_ISR_CEIF_Pos)               /*!< 0x00000020 */
12235 #define DMA2D_ISR_CEIF             DMA2D_ISR_CEIF_Msk                          /*!< Configuration Error Interrupt Flag */
12236 
12237 /********************  Bit definition for DMA2D_IFCR register  ****************/
12238 #define DMA2D_IFCR_CTEIF_Pos       (0U)
12239 #define DMA2D_IFCR_CTEIF_Msk       (0x1UL << DMA2D_IFCR_CTEIF_Pos)             /*!< 0x00000001 */
12240 #define DMA2D_IFCR_CTEIF           DMA2D_IFCR_CTEIF_Msk                        /*!< Clears Transfer Error Interrupt Flag */
12241 #define DMA2D_IFCR_CTCIF_Pos       (1U)
12242 #define DMA2D_IFCR_CTCIF_Msk       (0x1UL << DMA2D_IFCR_CTCIF_Pos)             /*!< 0x00000002 */
12243 #define DMA2D_IFCR_CTCIF           DMA2D_IFCR_CTCIF_Msk                        /*!< Clears Transfer Complete Interrupt Flag */
12244 #define DMA2D_IFCR_CTWIF_Pos       (2U)
12245 #define DMA2D_IFCR_CTWIF_Msk       (0x1UL << DMA2D_IFCR_CTWIF_Pos)             /*!< 0x00000004 */
12246 #define DMA2D_IFCR_CTWIF           DMA2D_IFCR_CTWIF_Msk                        /*!< Clears Transfer Watermark Interrupt Flag */
12247 #define DMA2D_IFCR_CAECIF_Pos      (3U)
12248 #define DMA2D_IFCR_CAECIF_Msk      (0x1UL << DMA2D_IFCR_CAECIF_Pos)            /*!< 0x00000008 */
12249 #define DMA2D_IFCR_CAECIF          DMA2D_IFCR_CAECIF_Msk                       /*!< Clears CLUT Access Error Interrupt Flag */
12250 #define DMA2D_IFCR_CCTCIF_Pos      (4U)
12251 #define DMA2D_IFCR_CCTCIF_Msk      (0x1UL << DMA2D_IFCR_CCTCIF_Pos)            /*!< 0x00000010 */
12252 #define DMA2D_IFCR_CCTCIF          DMA2D_IFCR_CCTCIF_Msk                       /*!< Clears CLUT Transfer Complete Interrupt Flag */
12253 #define DMA2D_IFCR_CCEIF_Pos       (5U)
12254 #define DMA2D_IFCR_CCEIF_Msk       (0x1UL << DMA2D_IFCR_CCEIF_Pos)             /*!< 0x00000020 */
12255 #define DMA2D_IFCR_CCEIF           DMA2D_IFCR_CCEIF_Msk                        /*!< Clears Configuration Error Interrupt Flag */
12256 
12257 /********************  Bit definition for DMA2D_FGMAR register  ***************/
12258 #define DMA2D_FGMAR_MA_Pos         (0U)
12259 #define DMA2D_FGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)        /*!< 0xFFFFFFFF */
12260 #define DMA2D_FGMAR_MA             DMA2D_FGMAR_MA_Msk                          /*!< Memory Address */
12261 
12262 /********************  Bit definition for DMA2D_FGOR register  ****************/
12263 #define DMA2D_FGOR_LO_Pos          (0U)
12264 #define DMA2D_FGOR_LO_Msk          (0xFFFFUL << DMA2D_FGOR_LO_Pos)             /*!< 0x0000FFFF */
12265 #define DMA2D_FGOR_LO              DMA2D_FGOR_LO_Msk                           /*!< Line Offset */
12266 
12267 /********************  Bit definition for DMA2D_BGMAR register  ***************/
12268 #define DMA2D_BGMAR_MA_Pos         (0U)
12269 #define DMA2D_BGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)        /*!< 0xFFFFFFFF */
12270 #define DMA2D_BGMAR_MA             DMA2D_BGMAR_MA_Msk                          /*!< Memory Address */
12271 
12272 /********************  Bit definition for DMA2D_BGOR register  ****************/
12273 #define DMA2D_BGOR_LO_Pos          (0U)
12274 #define DMA2D_BGOR_LO_Msk          (0xFFFFUL << DMA2D_BGOR_LO_Pos)             /*!< 0x0000FFFF */
12275 #define DMA2D_BGOR_LO              DMA2D_BGOR_LO_Msk                           /*!< Line Offset */
12276 
12277 /********************  Bit definition for DMA2D_FGPFCCR register  *************/
12278 #define DMA2D_FGPFCCR_CM_Pos       (0U)
12279 #define DMA2D_FGPFCCR_CM_Msk       (0xFUL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x0000000F */
12280 #define DMA2D_FGPFCCR_CM           DMA2D_FGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */
12281 #define DMA2D_FGPFCCR_CM_0         (0x1UL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x00000001 */
12282 #define DMA2D_FGPFCCR_CM_1         (0x2UL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x00000002 */
12283 #define DMA2D_FGPFCCR_CM_2         (0x4UL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x00000004 */
12284 #define DMA2D_FGPFCCR_CM_3         (0x8UL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x00000008 */
12285 #define DMA2D_FGPFCCR_CCM_Pos      (4U)
12286 #define DMA2D_FGPFCCR_CCM_Msk      (0x1UL << DMA2D_FGPFCCR_CCM_Pos)            /*!< 0x00000010 */
12287 #define DMA2D_FGPFCCR_CCM          DMA2D_FGPFCCR_CCM_Msk                       /*!< CLUT Color mode */
12288 #define DMA2D_FGPFCCR_START_Pos    (5U)
12289 #define DMA2D_FGPFCCR_START_Msk    (0x1UL << DMA2D_FGPFCCR_START_Pos)          /*!< 0x00000020 */
12290 #define DMA2D_FGPFCCR_START        DMA2D_FGPFCCR_START_Msk                     /*!< Start */
12291 #define DMA2D_FGPFCCR_CS_Pos       (8U)
12292 #define DMA2D_FGPFCCR_CS_Msk       (0xFFUL << DMA2D_FGPFCCR_CS_Pos)            /*!< 0x0000FF00 */
12293 #define DMA2D_FGPFCCR_CS           DMA2D_FGPFCCR_CS_Msk                        /*!< CLUT size */
12294 #define DMA2D_FGPFCCR_AM_Pos       (16U)
12295 #define DMA2D_FGPFCCR_AM_Msk       (0x3UL << DMA2D_FGPFCCR_AM_Pos)             /*!< 0x00030000 */
12296 #define DMA2D_FGPFCCR_AM           DMA2D_FGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */
12297 #define DMA2D_FGPFCCR_AM_0         (0x1UL << DMA2D_FGPFCCR_AM_Pos)             /*!< 0x00010000 */
12298 #define DMA2D_FGPFCCR_AM_1         (0x2UL << DMA2D_FGPFCCR_AM_Pos)             /*!< 0x00020000 */
12299 #define DMA2D_FGPFCCR_CSS_Pos      (18U)
12300 #define DMA2D_FGPFCCR_CSS_Msk      (0x3UL << DMA2D_FGPFCCR_CSS_Pos)            /*!< 0x000C0000 */
12301 #define DMA2D_FGPFCCR_CSS          DMA2D_FGPFCCR_CSS_Msk                       /*!< Chroma Sub-Sampling */
12302 #define DMA2D_FGPFCCR_CSS_0        (0x1UL << DMA2D_FGPFCCR_CSS_Pos)            /*!< 0x00040000 */
12303 #define DMA2D_FGPFCCR_CSS_1        (0x2UL << DMA2D_FGPFCCR_CSS_Pos)            /*!< 0x00080000 */
12304 #define DMA2D_FGPFCCR_AI_Pos       (20U)
12305 #define DMA2D_FGPFCCR_AI_Msk       (0x1UL << DMA2D_FGPFCCR_AI_Pos)             /*!< 0x00100000 */
12306 #define DMA2D_FGPFCCR_AI           DMA2D_FGPFCCR_AI_Msk                        /*!< Alpha Inverted */
12307 #define DMA2D_FGPFCCR_RBS_Pos      (21U)
12308 #define DMA2D_FGPFCCR_RBS_Msk      (0x1UL << DMA2D_FGPFCCR_RBS_Pos)            /*!< 0x00200000 */
12309 #define DMA2D_FGPFCCR_RBS          DMA2D_FGPFCCR_RBS_Msk                       /*!< Red Blue Swap */
12310 #define DMA2D_FGPFCCR_ALPHA_Pos    (24U)
12311 #define DMA2D_FGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */
12312 #define DMA2D_FGPFCCR_ALPHA        DMA2D_FGPFCCR_ALPHA_Msk                     /*!< Alpha value */
12313 
12314 /********************  Bit definition for DMA2D_FGCOLR register  **************/
12315 #define DMA2D_FGCOLR_BLUE_Pos      (0U)
12316 #define DMA2D_FGCOLR_BLUE_Msk      (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)           /*!< 0x000000FF */
12317 #define DMA2D_FGCOLR_BLUE          DMA2D_FGCOLR_BLUE_Msk                       /*!< Blue Value */
12318 #define DMA2D_FGCOLR_GREEN_Pos     (8U)
12319 #define DMA2D_FGCOLR_GREEN_Msk     (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */
12320 #define DMA2D_FGCOLR_GREEN         DMA2D_FGCOLR_GREEN_Msk                      /*!< Green Value */
12321 #define DMA2D_FGCOLR_RED_Pos       (16U)
12322 #define DMA2D_FGCOLR_RED_Msk       (0xFFUL << DMA2D_FGCOLR_RED_Pos)            /*!< 0x00FF0000 */
12323 #define DMA2D_FGCOLR_RED           DMA2D_FGCOLR_RED_Msk                        /*!< Red Value */
12324 
12325 /********************  Bit definition for DMA2D_BGPFCCR register  *************/
12326 #define DMA2D_BGPFCCR_CM_Pos       (0U)
12327 #define DMA2D_BGPFCCR_CM_Msk       (0xFUL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x0000000F */
12328 #define DMA2D_BGPFCCR_CM           DMA2D_BGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */
12329 #define DMA2D_BGPFCCR_CM_0         (0x1UL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x00000001 */
12330 #define DMA2D_BGPFCCR_CM_1         (0x2UL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x00000002 */
12331 #define DMA2D_BGPFCCR_CM_2         (0x4UL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x00000004 */
12332 #define DMA2D_BGPFCCR_CM_3         (0x8UL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x00000008 */
12333 #define DMA2D_BGPFCCR_CCM_Pos      (4U)
12334 #define DMA2D_BGPFCCR_CCM_Msk      (0x1UL << DMA2D_BGPFCCR_CCM_Pos)            /*!< 0x00000010 */
12335 #define DMA2D_BGPFCCR_CCM          DMA2D_BGPFCCR_CCM_Msk                       /*!< CLUT Color mode */
12336 #define DMA2D_BGPFCCR_START_Pos    (5U)
12337 #define DMA2D_BGPFCCR_START_Msk    (0x1UL << DMA2D_BGPFCCR_START_Pos)          /*!< 0x00000020 */
12338 #define DMA2D_BGPFCCR_START        DMA2D_BGPFCCR_START_Msk                     /*!< Start */
12339 #define DMA2D_BGPFCCR_CS_Pos       (8U)
12340 #define DMA2D_BGPFCCR_CS_Msk       (0xFFUL << DMA2D_BGPFCCR_CS_Pos)            /*!< 0x0000FF00 */
12341 #define DMA2D_BGPFCCR_CS           DMA2D_BGPFCCR_CS_Msk                        /*!< CLUT size */
12342 #define DMA2D_BGPFCCR_AM_Pos       (16U)
12343 #define DMA2D_BGPFCCR_AM_Msk       (0x3UL << DMA2D_BGPFCCR_AM_Pos)             /*!< 0x00030000 */
12344 #define DMA2D_BGPFCCR_AM           DMA2D_BGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */
12345 #define DMA2D_BGPFCCR_AM_0         (0x1UL << DMA2D_BGPFCCR_AM_Pos)             /*!< 0x00010000 */
12346 #define DMA2D_BGPFCCR_AM_1         (0x2UL << DMA2D_BGPFCCR_AM_Pos)             /*!< 0x00020000 */
12347 #define DMA2D_BGPFCCR_AI_Pos       (20U)
12348 #define DMA2D_BGPFCCR_AI_Msk       (0x1UL << DMA2D_BGPFCCR_AI_Pos)             /*!< 0x00100000 */
12349 #define DMA2D_BGPFCCR_AI           DMA2D_BGPFCCR_AI_Msk                        /*!< Alpha Inverted */
12350 #define DMA2D_BGPFCCR_RBS_Pos      (21U)
12351 #define DMA2D_BGPFCCR_RBS_Msk      (0x1UL << DMA2D_BGPFCCR_RBS_Pos)            /*!< 0x00200000 */
12352 #define DMA2D_BGPFCCR_RBS          DMA2D_BGPFCCR_RBS_Msk                       /*!< Red Blue Swap */
12353 #define DMA2D_BGPFCCR_ALPHA_Pos    (24U)
12354 #define DMA2D_BGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */
12355 #define DMA2D_BGPFCCR_ALPHA        DMA2D_BGPFCCR_ALPHA_Msk                     /*!< Alpha value */
12356 
12357 /********************  Bit definition for DMA2D_BGCOLR register  **************/
12358 #define DMA2D_BGCOLR_BLUE_Pos      (0U)
12359 #define DMA2D_BGCOLR_BLUE_Msk      (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)           /*!< 0x000000FF */
12360 #define DMA2D_BGCOLR_BLUE          DMA2D_BGCOLR_BLUE_Msk                       /*!< Blue Value */
12361 #define DMA2D_BGCOLR_GREEN_Pos     (8U)
12362 #define DMA2D_BGCOLR_GREEN_Msk     (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */
12363 #define DMA2D_BGCOLR_GREEN         DMA2D_BGCOLR_GREEN_Msk                      /*!< Green Value */
12364 #define DMA2D_BGCOLR_RED_Pos       (16U)
12365 #define DMA2D_BGCOLR_RED_Msk       (0xFFUL << DMA2D_BGCOLR_RED_Pos)            /*!< 0x00FF0000 */
12366 #define DMA2D_BGCOLR_RED           DMA2D_BGCOLR_RED_Msk                        /*!< Red Value */
12367 
12368 /********************  Bit definition for DMA2D_FGCMAR register  **************/
12369 #define DMA2D_FGCMAR_MA_Pos        (0U)
12370 #define DMA2D_FGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */
12371 #define DMA2D_FGCMAR_MA            DMA2D_FGCMAR_MA_Msk                         /*!< Memory Address */
12372 
12373 /********************  Bit definition for DMA2D_BGCMAR register  **************/
12374 #define DMA2D_BGCMAR_MA_Pos        (0U)
12375 #define DMA2D_BGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */
12376 #define DMA2D_BGCMAR_MA            DMA2D_BGCMAR_MA_Msk                         /*!< Memory Address */
12377 
12378 /********************  Bit definition for DMA2D_OPFCCR register  **************/
12379 #define DMA2D_OPFCCR_CM_Pos        (0U)
12380 #define DMA2D_OPFCCR_CM_Msk        (0x7UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000007 */
12381 #define DMA2D_OPFCCR_CM            DMA2D_OPFCCR_CM_Msk                         /*!< Color mode CM[2:0] */
12382 #define DMA2D_OPFCCR_CM_0          (0x1UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000001 */
12383 #define DMA2D_OPFCCR_CM_1          (0x2UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000002 */
12384 #define DMA2D_OPFCCR_CM_2          (0x4UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000004 */
12385 #define DMA2D_OPFCCR_SB_Pos        (8U)
12386 #define DMA2D_OPFCCR_SB_Msk        (0x1UL << DMA2D_OPFCCR_SB_Pos)              /*!< 0x00000100 */
12387 #define DMA2D_OPFCCR_SB            DMA2D_OPFCCR_SB_Msk                         /*!< Swap Bytes */
12388 #define DMA2D_OPFCCR_AI_Pos        (20U)
12389 #define DMA2D_OPFCCR_AI_Msk        (0x1UL << DMA2D_OPFCCR_AI_Pos)              /*!< 0x00100000 */
12390 #define DMA2D_OPFCCR_AI            DMA2D_OPFCCR_AI_Msk                         /*!< Alpha Inverted */
12391 #define DMA2D_OPFCCR_RBS_Pos       (21U)
12392 #define DMA2D_OPFCCR_RBS_Msk       (0x1UL << DMA2D_OPFCCR_RBS_Pos)             /*!< 0x00200000 */
12393 #define DMA2D_OPFCCR_RBS           DMA2D_OPFCCR_RBS_Msk                        /*!< Red Blue Swap */
12394 
12395 /********************  Bit definition for DMA2D_OCOLR register  ***************/
12396 /*!<Mode_ARGB8888/RGB888 */
12397 #define DMA2D_OCOLR_BLUE_1         (0x000000FFUL)                              /*!< Blue Value */
12398 #define DMA2D_OCOLR_GREEN_1        (0x0000FF00UL)                              /*!< Green Value  */
12399 #define DMA2D_OCOLR_RED_1          (0x00FF0000UL)                              /*!< Red Value */
12400 #define DMA2D_OCOLR_ALPHA_1        (0xFF000000UL)                              /*!< Alpha Channel Value */
12401 
12402 /*!<Mode_RGB565 */
12403 #define DMA2D_OCOLR_BLUE_2         (0x0000001FUL)                              /*!< Blue Value */
12404 #define DMA2D_OCOLR_GREEN_2        (0x000007E0UL)                              /*!< Green Value  */
12405 #define DMA2D_OCOLR_RED_2          (0x0000F800UL)                              /*!< Red Value */
12406 
12407 /*!<Mode_ARGB1555 */
12408 #define DMA2D_OCOLR_BLUE_3         (0x0000001FUL)                              /*!< Blue Value */
12409 #define DMA2D_OCOLR_GREEN_3        (0x000003E0UL)                              /*!< Green Value  */
12410 #define DMA2D_OCOLR_RED_3          (0x00007C00UL)                              /*!< Red Value */
12411 #define DMA2D_OCOLR_ALPHA_3        (0x00008000UL)                              /*!< Alpha Channel Value */
12412 
12413 /*!<Mode_ARGB4444 */
12414 #define DMA2D_OCOLR_BLUE_4         (0x0000000FUL)                              /*!< Blue Value */
12415 #define DMA2D_OCOLR_GREEN_4        (0x000000F0UL)                              /*!< Green Value  */
12416 #define DMA2D_OCOLR_RED_4          (0x00000F00UL)                              /*!< Red Value */
12417 #define DMA2D_OCOLR_ALPHA_4        (0x0000F000UL)                              /*!< Alpha Channel Value */
12418 
12419 /********************  Bit definition for DMA2D_OMAR register  ****************/
12420 #define DMA2D_OMAR_MA_Pos          (0U)
12421 #define DMA2D_OMAR_MA_Msk          (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)         /*!< 0xFFFFFFFF */
12422 #define DMA2D_OMAR_MA              DMA2D_OMAR_MA_Msk                           /*!< Memory Address */
12423 
12424 /********************  Bit definition for DMA2D_OOR register  *****************/
12425 #define DMA2D_OOR_LO_Pos           (0U)
12426 #define DMA2D_OOR_LO_Msk           (0xFFFFUL << DMA2D_OOR_LO_Pos)              /*!< 0x0000FFFF */
12427 #define DMA2D_OOR_LO               DMA2D_OOR_LO_Msk                            /*!< Line Offset */
12428 
12429 /********************  Bit definition for DMA2D_NLR register  *****************/
12430 #define DMA2D_NLR_NL_Pos           (0U)
12431 #define DMA2D_NLR_NL_Msk           (0xFFFFUL << DMA2D_NLR_NL_Pos)              /*!< 0x0000FFFF */
12432 #define DMA2D_NLR_NL               DMA2D_NLR_NL_Msk                            /*!< Number of Lines */
12433 #define DMA2D_NLR_PL_Pos           (16U)
12434 #define DMA2D_NLR_PL_Msk           (0x3FFFUL << DMA2D_NLR_PL_Pos)              /*!< 0x3FFF0000 */
12435 #define DMA2D_NLR_PL               DMA2D_NLR_PL_Msk                            /*!< Pixel per Lines */
12436 
12437 /********************  Bit definition for DMA2D_LWR register  *****************/
12438 #define DMA2D_LWR_LW_Pos           (0U)
12439 #define DMA2D_LWR_LW_Msk           (0xFFFFUL << DMA2D_LWR_LW_Pos)              /*!< 0x0000FFFF */
12440 #define DMA2D_LWR_LW               DMA2D_LWR_LW_Msk                            /*!< Line Watermark */
12441 
12442 /********************  Bit definition for DMA2D_AMTCR register  ***************/
12443 #define DMA2D_AMTCR_EN_Pos         (0U)
12444 #define DMA2D_AMTCR_EN_Msk         (0x1UL << DMA2D_AMTCR_EN_Pos)               /*!< 0x00000001 */
12445 #define DMA2D_AMTCR_EN             DMA2D_AMTCR_EN_Msk                          /*!< Enable */
12446 #define DMA2D_AMTCR_DT_Pos         (8U)
12447 #define DMA2D_AMTCR_DT_Msk         (0xFFUL << DMA2D_AMTCR_DT_Pos)              /*!< 0x0000FF00 */
12448 #define DMA2D_AMTCR_DT             DMA2D_AMTCR_DT_Msk                          /*!< Dead Time */
12449 
12450 /********************  Bit definition for DMA2D_FGCLUT register  **************/
12451 
12452 /********************  Bit definition for DMA2D_BGCLUT register  **************/
12453 
12454 
12455 /******************************************************************************/
12456 /*                                                                            */
12457 /*                    Digital Temperature Sensor                              */
12458 /*                                                                            */
12459 /******************************************************************************/
12460 /*******************  Bit definition for DTS_PVTREG_LOCKR register  *****************/
12461 #define DTS_PVTREG_LOCKR_LOCK_Pos                 (0U)
12462 #define DTS_PVTREG_LOCKR_LOCK_Msk                 (0xFFFFFFFFUL << DTS_PVTREG_LOCKR_LOCK_Pos)         /*!< 0xFFFFFFFF */
12463 #define DTS_PVTREG_LOCKR_LOCK                     DTS_PVTREG_LOCKR_LOCK_Msk                           /*!< PVT software lock */
12464 
12465 /*******************  Bit definition for DTS_PVTLOCK_SR register  *****************/
12466 #define DTS_PVTLOCK_SR_SW_LOCK_STATUS_Pos         (0U)
12467 #define DTS_PVTLOCK_SR_SW_LOCK_STATUS_Msk         (0x1UL << DTS_PVTLOCK_SR_SW_LOCK_STATUS_Pos)        /*!< 0x00000001 */
12468 #define DTS_PVTLOCK_SR_SW_LOCK_STATUS             DTS_PVTLOCK_SR_SW_LOCK_STATUS_Msk                   /*!< Software lock status */
12469 #define DTS_PVTLOCK_SR_HW_LOCK_STATUS_Pos         (1U)
12470 #define DTS_PVTLOCK_SR_HW_LOCK_STATUS_Msk         (0x1UL << DTS_PVTLOCK_SR_HW_LOCK_STATUS_Pos)        /*!< 0x00000002 */
12471 #define DTS_PVTLOCK_SR_HW_LOCK_STATUS             DTS_PVTLOCK_SR_HW_LOCK_STATUS_Msk                   /*!< Hardware lock status */
12472 
12473 /*******************  Bit definition for DTS_PVTTMR_CR register  *****************/
12474 #define DTS_PVTTMR_CR_TMR_DELAY_Pos               (0U)
12475 #define DTS_PVTTMR_CR_TMR_DELAY_Msk               (0xFFFFUL << DTS_PVTTMR_CR_TMR_DELAY_Pos)           /*!< 0x0000FFFF */
12476 #define DTS_PVTTMR_CR_TMR_DELAY                   DTS_PVTTMR_CR_TMR_DELAY_Msk                         /*!< Timer delay */
12477 #define DTS_PVTTMR_CR_TMR_RUN_Pos                 (16U)
12478 #define DTS_PVTTMR_CR_TMR_RUN_Msk                 (0x1UL << DTS_PVTTMR_CR_TMR_RUN_Pos)                /*!< 0x00010000 */
12479 #define DTS_PVTTMR_CR_TMR_RUN                     DTS_PVTTMR_CR_TMR_RUN_Msk                           /*!< Enable */
12480 
12481 /*******************  Bit definition for DTS_PVTTMR_SR register  *****************/
12482 #define DTS_PVTTMR_SR_TMR_BUSY_Pos                (0U)
12483 #define DTS_PVTTMR_SR_TMR_BUSY_Msk                (0x1UL << DTS_PVTTMR_SR_TMR_BUSY_Pos)               /*!< 0x00000001 */
12484 #define DTS_PVTTMR_SR_TMR_BUSY                    DTS_PVTTMR_SR_TMR_BUSY_Msk                          /*!< Counter busy flag */
12485 #define DTS_PVTTMR_SR_TMR_DONE_Pos                (1U)
12486 #define DTS_PVTTMR_SR_TMR_DONE_Msk                (0x1UL << DTS_PVTTMR_SR_TMR_DONE_Pos)               /*!< 0x00000002 */
12487 #define DTS_PVTTMR_SR_TMR_DONE                    DTS_PVTTMR_SR_TMR_DONE_Msk                          /*!< Cnt delay timeout */
12488 
12489 /*******************  Bit definition for DTS_PVT_IER register  *****************/
12490 #define DTS_PVT_IER_TMR_IRQ_ENABLE_Pos            (0U)
12491 #define DTS_PVT_IER_TMR_IRQ_ENABLE_Msk            (0x1UL << DTS_PVT_IER_TMR_IRQ_ENABLE_Pos)           /*!< 0x00000001 */
12492 #define DTS_PVT_IER_TMR_IRQ_ENABLE                DTS_PVT_IER_TMR_IRQ_ENABLE_Msk                      /*!< Timer IRQ enable */
12493 #define DTS_PVT_IER_TS_IRQ_ENABLE_Pos             (1U)
12494 #define DTS_PVT_IER_TS_IRQ_ENABLE_Msk             (0x1UL << DTS_PVT_IER_TS_IRQ_ENABLE_Pos)            /*!< 0x00000002 */
12495 #define DTS_PVT_IER_TS_IRQ_ENABLE                 DTS_PVT_IER_TS_IRQ_ENABLE_Msk                       /*!< TS IRQ enable */
12496 
12497 /*******************  Bit definition for DTS_PVTIRQTRMASKR register  *****************/
12498 #define DTS_PVTIRQTRMASKR_TMR_IRQ_MASK_Pos        (0U)
12499 #define DTS_PVTIRQTRMASKR_TMR_IRQ_MASK_Msk        (0x1UL << DTS_PVTIRQTRMASKR_TMR_IRQ_MASK_Pos)       /*!< 0x00000001 */
12500 #define DTS_PVTIRQTRMASKR_TMR_IRQ_MASK            DTS_PVTIRQTRMASKR_TMR_IRQ_MASK_Msk                  /*!< Timer IRQ mask */
12501 
12502 /*******************  Bit definition for DTS_TS_MR register  *****************/
12503 #define DTS_TS_MR_TS0_IRQ_MASK_Pos                (0U)
12504 #define DTS_TS_MR_TS0_IRQ_MASK_Msk                (0x1UL << DTS_TS_MR_TS0_IRQ_MASK_Pos)               /*!< 0x00000001 */
12505 #define DTS_TS_MR_TS0_IRQ_MASK                    DTS_TS_MR_TS0_IRQ_MASK_Msk                          /*!< TS0 IRQ mask */
12506 #define DTS_TS_MR_TS1_IRQ_MASK_Pos                (1U)
12507 #define DTS_TS_MR_TS1_IRQ_MASK_Msk                (0x1UL << DTS_TS_MR_TS1_IRQ_MASK_Pos)               /*!< 0x00000002 */
12508 #define DTS_TS_MR_TS1_IRQ_MASK                    DTS_TS_MR_TS1_IRQ_MASK_Msk                          /*!< TS1 IRQ mask */
12509 
12510 /*******************  Bit definition for DTS_PVTTR_SR register  *****************/
12511 #define DTS_PVTTR_SR_TMR_IRQ_STATUS_Pos           (0U)
12512 #define DTS_PVTTR_SR_TMR_IRQ_STATUS_Msk           (0x1UL << DTS_PVTTR_SR_TMR_IRQ_STATUS_Pos)          /*!< 0x00000001 */
12513 #define DTS_PVTTR_SR_TMR_IRQ_STATUS               DTS_PVTTR_SR_TMR_IRQ_STATUS_Msk                     /*!< Timer IRQ status after masking */
12514 
12515 /*******************  Bit definition for DTS_TS_ISR register  *****************/
12516 #define DTS_TS_ISR_TS0_IRQ_STATUS_Pos             (0U)
12517 #define DTS_TS_ISR_TS0_IRQ_STATUS_Msk             (0x1UL << DTS_TS_ISR_TS0_IRQ_STATUS_Pos)            /*!< 0x00000001 */
12518 #define DTS_TS_ISR_TS0_IRQ_STATUS                 DTS_TS_ISR_TS0_IRQ_STATUS_Msk                       /*!< TS0 IRQ status after masking */
12519 #define DTS_TS_ISR_TS1_IRQ_STATUS_Pos             (1U)
12520 #define DTS_TS_ISR_TS1_IRQ_STATUS_Msk             (0x1UL << DTS_TS_ISR_TS1_IRQ_STATUS_Pos)            /*!< 0x00000002 */
12521 #define DTS_TS_ISR_TS1_IRQ_STATUS                 DTS_TS_ISR_TS1_IRQ_STATUS_Msk                       /*!< TS1 IRQ status after masking */
12522 
12523 /*******************  Bit definition for DTS_PVTTMRRAW_ISR register  *****************/
12524 #define DTS_PVTTMRRAW_ISR_TMR_IRQ_RAW_STATUS_Pos  (0U)
12525 #define DTS_PVTTMRRAW_ISR_TMR_IRQ_RAW_STATUS_Msk  (0x1UL << DTS_PVTTMRRAW_ISR_TMR_IRQ_RAW_STATUS_Pos) /*!< 0x00000001 */
12526 #define DTS_PVTTMRRAW_ISR_TMR_IRQ_RAW_STATUS      DTS_PVTTMRRAW_ISR_TMR_IRQ_RAW_STATUS_Msk            /*!< Timer IRQ status before masking */
12527 
12528 /*******************  Bit definition for DTS_TSRAW_ISR register  *****************/
12529 #define DTS_TSRAW_ISR_TS0_IRQ_RAW_STATUS_Pos      (0U)
12530 #define DTS_TSRAW_ISR_TS0_IRQ_RAW_STATUS_Msk      (0x1UL << DTS_TSRAW_ISR_TS0_IRQ_RAW_STATUS_Pos)     /*!< 0x00000001 */
12531 #define DTS_TSRAW_ISR_TS0_IRQ_RAW_STATUS          DTS_TSRAW_ISR_TS0_RAW_IRQ_STATUS_Msk                /*!< TS0 IRQ status before masking */
12532 #define DTS_TSRAW_ISR_TS1_IRQ_RAW_STATUS_Pos      (1U)
12533 #define DTS_TSRAW_ISR_TS1_IRQ_RAW_STATUS_Msk      (0x1UL << DTS_TSRAW_ISR_TS1_IRQ_RAW_STATUS_Pos)     /*!< 0x00000002 */
12534 #define DTS_TSRAW_ISR_TS1_IRQ_RAW_STATUS          DTS_TSRAW_ISR_TS1_IRQ_RAW_STATUS_Msk                /*!< TS1 IRQ status before masking */
12535 
12536 /*******************  Bit definition for DTS_TSCCLKSYNTHR register  *****************/
12537 #define DTS_TSCCLKSYNTHR_CLK_SYNTH_LO_Pos         (0U)
12538 #define DTS_TSCCLKSYNTHR_CLK_SYNTH_LO_Msk         (0xFFUL << DTS_TSCCLKSYNTHR_CLK_SYNTH_LO_Pos)       /*!< 0x000000FF */
12539 #define DTS_TSCCLKSYNTHR_CLK_SYNTH_LO             DTS_TSCCLKSYNTHR_CLK_SYNTH_LO_Msk                   /*!< Synthesized clk_ts low period */
12540 #define DTS_TSCCLKSYNTHR_CLK_SYNTH_HI_Pos         (8U)
12541 #define DTS_TSCCLKSYNTHR_CLK_SYNTH_HI_Msk         (0xFFUL << DTS_TSCCLKSYNTHR_CLK_SYNTH_HI_Pos)       /*!< 0x0000FF00 */
12542 #define DTS_TSCCLKSYNTHR_CLK_SYNTH_HI             DTS_TSCCLKSYNTHR_CLK_SYNTH_HI_Msk                   /*!< Synthesized clk_ts ghigh period */
12543 #define DTS_TSCCLKSYNTHR_CLK_SYNTH_HOLD_Pos       (16U)
12544 #define DTS_TSCCLKSYNTHR_CLK_SYNTH_HOLD_Msk       (0xFUL << DTS_TSCCLKSYNTHR_CLK_SYNTH_HOLD_Pos)      /*!< 0x000F0000 */
12545 #define DTS_TSCCLKSYNTHR_CLK_SYNTH_HOLD           DTS_TSCCLKSYNTHR_CLK_SYNTH_HOLD_Msk                 /*!< Hold input or output delay */
12546 #define DTS_TSCCLKSYNTHR_CLK_SYNTH_EN_Pos         (24U)
12547 #define DTS_TSCCLKSYNTHR_CLK_SYNTH_EN_Msk         (0x1UL << DTS_TSCCLKSYNTHR_CLK_SYNTH_EN_Pos)        /*!< 0x01000000 */
12548 #define DTS_TSCCLKSYNTHR_CLK_SYNTH_EN             DTS_TSCCLKSYNTHR_CLK_SYNTH_EN_Msk                   /*!< Synthesized enable */
12549 
12550 /*******************  Bit definition for DTS_TSCSDIFDISABLER register  *****************/
12551 #define DTS_TSCSDIFDISABLER_TS0_SDIF_DISABLE_Pos  (0U)
12552 #define DTS_TSCSDIFDISABLER_TS0_SDIF_DISABLE_Msk  (0x1UL << DTS_TSCSDIFDISABLER_TS0_SDIF_DISABLE_Pos) /*!< 0x00000001 */
12553 #define DTS_TSCSDIFDISABLER_TS0_SDIF_DISABLE      DTS_TSCSDIFDISABLER_TS0_SDIF_DISABLE_Msk            /*!< TS0 SDIF disable */
12554 #define DTS_TSCSDIFDISABLER_TS1_SDIF_DISABLE_Pos  (1U)
12555 #define DTS_TSCSDIFDISABLER_TS1_SDIF_DISABLE_Msk  (0x1UL << DTS_TSCSDIFDISABLER_TS1_SDIF_DISABLE_Pos) /*!< 0x00000002 */
12556 #define DTS_TSCSDIFDISABLER_TS1_SDIF_DISABLE      DTS_TSCSDIFDISABLER_TS1_SDIF_DISABLE_Msk            /*!< TS1 SDIF disable */
12557 
12558 /*******************  Bit definition for DTS_TSCSDIF_SR register  *****************/
12559 #define DTS_TSCSDIF_SR_SDIF_BUSY_Pos              (0U)
12560 #define DTS_TSCSDIF_SR_SDIF_BUSY_Msk              (0x1UL << DTS_TSCSDIF_SR_SDIF_BUSY_Pos)             /*!< 0x00000001 */
12561 #define DTS_TSCSDIF_SR_SDIF_BUSY                  DTS_TSCSDIF_SR_SDIF_BUSY_Msk                        /*!< SDIF busy flag */
12562 #define DTS_TSCSDIF_SR_SDIF_LOCK_Pos              (1U)
12563 #define DTS_TSCSDIF_SR_SDIF_LOCK_Msk              (0x1UL << DTS_TSCSDIF_SR_SDIF_LOCK_Pos)             /*!< 0x00000002 */
12564 #define DTS_TSCSDIF_SR_SDIF_LOCK                  DTS_TSCSDIF_SR_SDIF_LOCK_Msk                        /*!< SDIF locked flag */
12565 
12566 /*******************  Bit definition for DTS_TSCSDIF_CR register  *****************/
12567 #define DTS_TSCSDIF_CR_SDIF_WDATA_Pos             (0U)
12568 #define DTS_TSCSDIF_CR_SDIF_WDATA_Msk             (0xFFFFFFUL << DTS_TSCSDIF_CR_SDIF_WDATA_Pos)       /*!< 0x00FFFFFF */
12569 #define DTS_TSCSDIF_CR_SDIF_WDATA                 DTS_TSCSDIF_CR_SDIF_WDATA_Msk                       /*!< SDIF write data */
12570 #define DTS_TSCSDIF_CR_SDIF_ADDR_Pos              (24U)
12571 #define DTS_TSCSDIF_CR_SDIF_ADDR_Msk              (0x7UL << DTS_TSCSDIF_CR_SDIF_ADDR_Pos)             /*!< 0x07000000 */
12572 #define DTS_TSCSDIF_CR_SDIF_ADDR                  DTS_TSCSDIF_CR_SDIF_ADDR_Msk                        /*!< SDIF register address */
12573 #define DTS_TSCSDIF_CR_SDIF_WRN_Pos               (27U)
12574 #define DTS_TSCSDIF_CR_SDIF_WRN_Msk               (0x1UL << DTS_TSCSDIF_CR_SDIF_WRN_Pos)              /*!< 0x08000000 */
12575 #define DTS_TSCSDIF_CR_SDIF_WRN                   DTS_TSCSDIF_CR_SDIF_WRN_Msk                         /*!< SDIF write no read control */
12576 #define DTS_TSCSDIF_CR_SDIF_PROG_Pos              (31U)
12577 #define DTS_TSCSDIF_CR_SDIF_PROG_Msk              (0x1UL << DTS_TSCSDIF_CR_SDIF_PROG_Pos)             /*!< 0x80000000 */
12578 #define DTS_TSCSDIF_CR_SDIF_PROG                  DTS_TSCSDIF_CR_SDIF_PROG_Msk                        /*!< SDIF program request */
12579 
12580 /*******************  Bit definition for DTS_TSCSDIFHALTR register  *****************/
12581 #define DTS_TSCSDIFHALTR_SDIF_STOP_Pos            (0U)
12582 #define DTS_TSCSDIFHALTR_SDIF_STOP_Msk            (0x1UL << DTS_TSCSDIFHALTR_SDIF_STOP_Pos)           /*!< 0x00000001 */
12583 #define DTS_TSCSDIFHALTR_SDIF_STOP                DTS_TSCSDIFHALTR_SDIF_STOP_Msk                      /*!< SDIF stop */
12584 
12585 /*******************  Bit definition for DTS_TSCSDIF_CFGR register  *****************/
12586 #define DTS_TSCSDIF_CFGR_SDIF_INHIBIT_Pos         (0U)
12587 #define DTS_TSCSDIF_CFGR_SDIF_INHIBIT_Msk         (0x3UL << DTS_TSCSDIF_CFGR_SDIF_INHIBIT_Pos)        /*!< 0x00000003 */
12588 #define DTS_TSCSDIF_CFGR_SDIF_INHIBIT             DTS_TSCSDIF_CFGR_SDIF_INHIBIT_Msk                   /*!< SDIF programming inhibit */
12589 #define DTS_TSCSDIF_CFGR_SDIF_INHIBIT_0           (0x1UL << DTS_TSCSDIF_CFGR_SDIF_INHIBIT_Pos)        /*!< 0x00000001 */
12590 #define DTS_TSCSDIF_CFGR_SDIF_INHIBIT_1           (0x2UL << DTS_TSCSDIF_CFGR_SDIF_INHIBIT_Pos)        /*!< 0x00000002 */
12591 
12592 /*******************  Bit definition for DTS_TSCSMPL_CR register  *****************/
12593 #define DTS_TSCSMPL_CR_SMPL_CTR_DISABLE_Pos       (0U)
12594 #define DTS_TSCSMPL_CR_SMPL_CTR_DISABLE_Msk       (0x1UL << DTS_TSCSMPL_CR_SMPL_CTR_DISABLE_Pos)      /*!< 0x00000001 */
12595 #define DTS_TSCSMPL_CR_SMPL_CTR_DISABLE           DTS_TSCSMPL_CR_SMPL_CTR_DISABLE_Msk                 /*!< Sample counter disable */
12596 #define DTS_TSCSMPL_CR_SMPL_CTR_HOLD_Pos          (1U)
12597 #define DTS_TSCSMPL_CR_SMPL_CTR_HOLD_Msk          (0x1UL << DTS_TSCSMPL_CR_SMPL_CTR_HOLD_Pos)         /*!< 0x00000002 */
12598 #define DTS_TSCSMPL_CR_SMPL_CTR_HOLD              DTS_TSCSMPL_CR_SMPL_CTR_HOLD_Msk                    /*!< Sample counter hold */
12599 #define DTS_TSCSMPL_CR_SMPL_DISCARD_Pos           (2U)
12600 #define DTS_TSCSMPL_CR_SMPL_DISCARD_Msk           (0x1UL << DTS_TSCSMPL_CR_SMPL_DISCARD_Pos)          /*!< 0x00000004 */
12601 #define DTS_TSCSMPL_CR_SMPL_DISCARD               DTS_TSCSMPL_CR_SMPL_DISCARD_Msk                     /*!< Sample discard */
12602 
12603 /*******************  Bit definition for DTS_TSCSDIFSMPLCLRR register  *****************/
12604 #define DTS_TSCSDIFSMPLCLRR_SMPL_CNTER_CLEAR_Pos  (0U)
12605 #define DTS_TSCSDIFSMPLCLRR_SMPL_CNTER_CLEAR_Msk  (0x1UL << DTS_TSCSDIFSMPLCLRR_SMPL_CNTER_CLEAR_Pos) /*!< 0x00000001 */
12606 #define DTS_TSCSDIFSMPLCLRR_SMPL_CNTER_CLEAR      DTS_TSCSDIFSMPLCLRR_SMPL_CNTER_CLEAR_Msk            /*!< Sample counter clear */
12607 
12608 /*******************  Bit definition for DTS_TSCSMPLCNTR register  *****************/
12609 #define DTS_TSCSMPLCNTR_SMPL_COUNT_Pos            (0U)
12610 #define DTS_TSCSMPLCNTR_SMPL_COUNT_Msk            (0xFFFFUL << DTS_TSCSMPLCNTR_SMPL_COUNT_Pos)        /*!< 0x0000FFFF */
12611 #define DTS_TSCSMPLCNTR_SMPL_COUNT                DTS_TSCSMPLCNTR_SMPL_COUNT_Msk                      /*!< Sample counter  */
12612 
12613 /*******************  Bit definition for DTS_TS_IER register  *****************/
12614 #define DTS_TS_IER_IRQ_EN_FAULT_Pos               (0U)
12615 #define DTS_TS_IER_IRQ_EN_FAULT_Msk               (0x1UL << DTS_TS_IER_IRQ_EN_FAULT_Pos)              /*!< 0x00000001 */
12616 #define DTS_TS_IER_IRQ_EN_FAULT                   DTS_TS_IER_IRQ_EN_FAULT_Msk                         /*!< TS Fault IRQ enable */
12617 #define DTS_TS_IER_IRQ_EN_DONE_Pos                (1U)
12618 #define DTS_TS_IER_IRQ_EN_DONE_Msk                (0x1UL << DTS_TS_IER_IRQ_EN_DONE_Pos)               /*!< 0x00000002 */
12619 #define DTS_TS_IER_IRQ_EN_DONE                    DTS_TS_IER_IRQ_EN_DONE_Msk                          /*!< TS Sample done IRQ enable */
12620 #define DTS_TS_IER_IRQ_EN_ALARMA_Pos              (3U)
12621 #define DTS_TS_IER_IRQ_EN_ALARMA_Msk              (0x1UL << DTS_TS_IER_IRQ_EN_ALARMA_Pos)             /*!< 0x00000008 */
12622 #define DTS_TS_IER_IRQ_EN_ALARMA                  DTS_TS_IER_IRQ_EN_ALARMA_Msk                        /*!< TS Alarm A IRQ enable */
12623 #define DTS_TS_IER_IRQ_EN_ALARMB_Pos              (4U)
12624 #define DTS_TS_IER_IRQ_EN_ALARMB_Msk              (0x1UL << DTS_TS_IER_IRQ_EN_ALARMB_Pos)             /*!< 0x00000010 */
12625 #define DTS_TS_IER_IRQ_EN_ALARMB                  DTS_TS_IER_IRQ_EN_ALARMB_Msk                        /*!< TS Alarm B IRQ enable */
12626 
12627 /*******************  Bit definition for DTS_TS_ISR register  *****************/
12628 #define DTS_TS_ISR_IRQ_STATUS_FAULT_Pos           (0U)
12629 #define DTS_TS_ISR_IRQ_STATUS_FAULT_Msk           (0x1UL << DTS_TS_ISR_IRQ_STATUS_FAULT_Pos)          /*!< 0x00000001 */
12630 #define DTS_TS_ISR_IRQ_STATUS_FAULT               DTS_TS_ISR_IRQ_STATUS_FAULT_Msk                     /*!< TS Fault IRQ status */
12631 #define DTS_TS_ISR_IRQ_STATUS_DONE_Pos            (1U)
12632 #define DTS_TS_ISR_IRQ_STATUS_DONE_Msk            (0x1UL << DTS_TS_ISR_IRQ_STATUS_DONE_Pos)           /*!< 0x00000002 */
12633 #define DTS_TS_ISR_IRQ_STATUS_DONE                DTS_TS_ISR_IRQ_STATUS_DONE_Msk                      /*!< TS Sample done IRQ status */
12634 #define DTS_TS_ISR_IRQ_STATUS_ALARMA_Pos          (3U)
12635 #define DTS_TS_ISR_IRQ_STATUS_ALARMA_Msk          (0x1UL << DTS_TS_ISR_IRQ_STATUS_ALARMA_Pos)         /*!< 0x00000008 */
12636 #define DTS_TS_ISR_IRQ_STATUS_ALARMA              DTS_TS_ISR_IRQ_STATUS_ALARMA_Msk                    /*!< TS Alarm A IRQ status */
12637 #define DTS_TS_ISR_IRQ_STATUS_ALARMB_Pos          (4U)
12638 #define DTS_TS_ISR_IRQ_STATUS_ALARMB_Msk          (0x1UL << DTS_TS_ISR_IRQ_STATUS_ALARMB_Pos)         /*!< 0x00000010 */
12639 #define DTS_TS_ISR_IRQ_STATUS_ALARMB              DTS_TS_ISR_IRQ_STATUS_ALARMB_Msk                    /*!< TS Alarm B IRQ status */
12640 
12641 /*******************  Bit definition for DTS_TS_ICR register  *****************/
12642 #define DTS_TS_ICR_IRQ_CLEAR_FAULT_Pos            (0U)
12643 #define DTS_TS_ICR_IRQ_CLEAR_FAULT_Msk            (0x1UL << DTS_TS_ICR_IRQ_CLEAR_FAULT_Pos)           /*!< 0x00000001 */
12644 #define DTS_TS_ICR_IRQ_CLEAR_FAULT                DTS_TS_ICR_IRQ_CLEAR_FAULT_Msk                      /*!< TS Fault IRQ clear */
12645 #define DTS_TS_ICR_IRQ_CLEAR_DONE_Pos             (1U)
12646 #define DTS_TS_ICR_IRQ_CLEAR_DONE_Msk             (0x1UL << DTS_TS_ICR_IRQ_CLEAR_DONE_Pos)            /*!< 0x00000002 */
12647 #define DTS_TS_ICR_IRQ_CLEAR_DONE                 DTS_TS_ICR_IRQ_CLEAR_DONE_Msk                       /*!< TS Sample done IRQ clear */
12648 #define DTS_TS_ICR_IRQ_CLEAR_ALARMA_Pos           (3U)
12649 #define DTS_TS_ICR_IRQ_CLEAR_ALARMA_Msk           (0x1UL << DTS_TS_ICR_IRQ_CLEAR_ALARMA_Pos)          /*!< 0x00000008 */
12650 #define DTS_TS_ICR_IRQ_CLEAR_ALARMA               DTS_TS_ICR_IRQ_CLEAR_ALARMA_Msk                     /*!< TS Alarm A IRQ clear */
12651 #define DTS_TS_ICR_IRQ_CLEAR_ALARMB_Pos           (4U)
12652 #define DTS_TS_ICR_IRQ_CLEAR_ALARMB_Msk           (0x1UL << DTS_TS_ICR_IRQ_CLEAR_ALARMB_Pos)          /*!< 0x00000010 */
12653 #define DTS_TS_ICR_IRQ_CLEAR_ALARMB               DTS_TS_ICR_IRQ_CLEAR_ALARMB_Msk                     /*!< TS Alarm B IRQ clear */
12654 
12655 /*******************  Bit definition for DTS_TSIRQTESTR register  *****************/
12656 #define DTS_TSIRQTESTR_IRQ_TEST_FAULT_Pos         (0U)
12657 #define DTS_TSIRQTESTR_IRQ_TEST_FAULT_Msk         (0x1UL << DTS_TSIRQTESTR_IRQ_TEST_FAULT_Pos)        /*!< 0x00000001 */
12658 #define DTS_TSIRQTESTR_IRQ_TEST_FAULT             DTS_TSIRQTESTR_IRQ_TEST_FAULT_Msk                   /*!< TS Fault IRQ test */
12659 #define DTS_TSIRQTESTR_IRQ_TEST_DONE_Pos          (1U)
12660 #define DTS_TSIRQTESTR_IRQ_TEST_DONE_Msk          (0x1UL << DTS_TSIRQTESTR_IRQ_TEST_DONE_Pos)         /*!< 0x00000002 */
12661 #define DTS_TSIRQTESTR_IRQ_TEST_DONE              DTS_TSIRQTESTR_IRQ_TEST_DONE_Msk                    /*!< TS Sample done IRQ test */
12662 #define DTS_TSIRQTESTR_IRQ_TEST_ALARMA_Pos        (3U)
12663 #define DTS_TSIRQTESTR_IRQ_TEST_ALARMA_Msk        (0x1UL << DTS_TSIRQTESTR_IRQ_TEST_ALARMA_Pos)       /*!< 0x00000008 */
12664 #define DTS_TSIRQTESTR_IRQ_TEST_ALARMA            DTS_TSIRQTESTR_IRQ_TEST_ALARMA_Msk                  /*!< TS Alarm A IRQ test */
12665 #define DTS_TSIRQTESTR_IRQ_TEST_ALARMB_Pos        (4U)
12666 #define DTS_TSIRQTESTR_IRQ_TEST_ALARMB_Msk        (0x1UL << DTS_TSIRQTESTR_IRQ_TEST_ALARMB_Pos)       /*!< 0x00000010 */
12667 #define DTS_TSIRQTESTR_IRQ_TEST_ALARMB            DTS_TSIRQTESTR_IRQ_TEST_ALARMB_Msk                  /*!< TS Alarm B IRQ test */
12668 
12669 /*******************  Bit definition for DTS_TSSDIFRDATAR register  *****************/
12670 #define DTS_TSSDIFRDATAR_SDIF_RDATA_Pos           (0U)
12671 #define DTS_TSSDIFRDATAR_SDIF_RDATA_Msk           (0xFFFFFFUL << DTS_TSSDIFRDATAR_SDIF_RDATA_Pos)     /*!< 0x00FFFFFF */
12672 #define DTS_TSSDIFRDATAR_SDIF_RDATA               DTS_TSSDIFRDATAR_SDIF_RDATA_Msk                     /*!< TS SDIF read data */
12673 
12674 /*******************  Bit definition for DTS_TSSDIFDONER register  *****************/
12675 #define DTS_TSSDIFDONER_SDIF_SMPL_DONE_Pos        (0U)
12676 #define DTS_TSSDIFDONER_SDIF_SMPL_DONE_Msk        (0x1UL << DTS_TSSDIFDONER_SDIF_SMPL_DONE_Pos)       /*!< 0x00000001 */
12677 #define DTS_TSSDIFDONER_SDIF_SMPL_DONE            DTS_TSSDIFDONER_SDIF_SMPL_DONE_Msk                  /*!< TS Sample done flag */
12678 
12679 /*******************  Bit definition for DTS_TSSDIFDATAR register  *****************/
12680 #define DTS_TSSDIFDATAR_SAMPLE_DATA_Pos           (0U)
12681 #define DTS_TSSDIFDATAR_SAMPLE_DATA_Msk           (0xFFFFUL << DTS_TSSDIFDATAR_SAMPLE_DATA_Pos)       /*!< 0x0000FFFF */
12682 #define DTS_TSSDIFDATAR_SAMPLE_DATA               DTS_TSSDIFDATAR_SAMPLE_DATA_Msk                     /*!< TS Sample data */
12683 #define DTS_TSSDIFDATAR_SAMPLE_TYPE_Pos           (16U)
12684 #define DTS_TSSDIFDATAR_SAMPLE_TYPE_Msk           (0x1UL << DTS_TSSDIFDATAR_SAMPLE_TYPE_Pos)          /*!< 0x00010000 */
12685 #define DTS_TSSDIFDATAR_SAMPLE_TYPE               DTS_TSSDIFDATAR_SAMPLE_TYPE_Msk                     /*!< TS Sample type */
12686 #define DTS_TSSDIFDATAR_SAMPLE_FAULT_Pos          (17U)
12687 #define DTS_TSSDIFDATAR_SAMPLE_FAULT_Msk          (0x1UL << DTS_TSSDIFDATAR_SAMPLE_FAULT_Pos)         /*!< 0x00020000 */
12688 #define DTS_TSSDIFDATAR_SAMPLE_FAULT              DTS_TSSDIFDATAR_SAMPLE_FAULT_Msk                    /*!< TS Sample fault */
12689 
12690 /*******************  Bit definition for DTS_TSALARMA_CFGR register  *****************/
12691 #define DTS_TSALARMA_CFGR_HYSTA_THRESH_Pos        (0U)
12692 #define DTS_TSALARMA_CFGR_HYSTA_THRESH_Msk        (0xFFFFUL << DTS_TSALARMA_CFGR_HYSTA_THRESH_Pos)    /*!< 0x0000FFFF */
12693 #define DTS_TSALARMA_CFGR_HYSTA_THRESH            DTS_TSALARMA_CFGR_HYSTA_THRESH_Msk                  /*!< TS Alarm A hysteresis threshold */
12694 #define DTS_TSALARMA_CFGR_ALARMA_THRESH_Pos       (16U)
12695 #define DTS_TSALARMA_CFGR_ALARMA_THRESH_Msk       (0xFFFFUL << DTS_TSALARMA_CFGR_ALARMA_THRESH_Pos)   /*!< 0xFFFF0000 */
12696 #define DTS_TSALARMA_CFGR_ALARMA_THRESH           DTS_TSALARMA_CFGR_ALARMA_THRESH_Msk                 /*!< TS Alarm A threshold */
12697 
12698 /*******************  Bit definition for DTS_TSALARMB_CFGR register  *****************/
12699 #define DTS_TSALARMB_CFGR_HYSTB_THRESH_Pos        (0U)
12700 #define DTS_TSALARMB_CFGR_HYSTB_THRESH_Msk        (0xFFFFUL << DTS_TSALARMB_CFGR_HYSTB_THRESH_Pos)    /*!< 0x0000FFFF */
12701 #define DTS_TSALARMB_CFGR_HYSTB_THRESH            DTS_TSALARMB_CFGR_HYSTB_THRESH_Msk                  /*!< TS Alarm B hysteresis threshold */
12702 #define DTS_TSALARMB_CFGR_ALARMB_THRESH_Pos       (16U)
12703 #define DTS_TSALARMB_CFGR_ALARMB_THRESH_Msk       (0xFFFFUL << DTS_TSALARMB_CFGR_ALARMB_THRESH_Pos)   /*!< 0xFFFF0000 */
12704 #define DTS_TSALARMB_CFGR_ALARMB_THRESH           DTS_TSALARMB_CFGR_ALARMB_THRESH_Msk                 /*!< TS Alarm B threshold */
12705 
12706 /*******************  Bit definition for DTS_TSHLSAMPLER register  *****************/
12707 #define DTS_TSHLSAMPLER_SMPL_LO_Pos               (0U)
12708 #define DTS_TSHLSAMPLER_SMPL_LO_Msk               (0xFFFFUL << DTS_TSHLSAMPLER_SMPL_LO_Pos)           /*!< 0x0000FFFF */
12709 #define DTS_TSHLSAMPLER_SMPL_LO                   DTS_TSHLSAMPLER_SMPL_LO_Msk                         /*!< TS Lowest valid data sample value received */
12710 #define DTS_TSHLSAMPLER_SMPL_HI_Pos               (16U)
12711 #define DTS_TSHLSAMPLER_SMPL_HI_Msk               (0xFFFFUL << DTS_TSHLSAMPLER_SMPL_HI_Pos)           /*!< 0xFFFF0000 */
12712 #define DTS_TSHLSAMPLER_SMPL_HI                   DTS_TSHLSAMPLER_SMPL_HI_Msk                         /*!< TS Highest valid data sample value received */
12713 
12714 /*******************  Bit definition for DTS_TSHILORESETR register  *****************/
12715 #define DTS_TSHILORESETR_SMPL_LO_SET_Pos          (0U)
12716 #define DTS_TSHILORESETR_SMPL_LO_SET_Msk          (0x1UL << DTS_TSHILORESETR_SMPL_LO_SET_Pos)         /*!< 0x00000001 */
12717 #define DTS_TSHILORESETR_SMPL_LO_SET              DTS_TSHILORESETR_SMPL_LO_SET_Msk                    /*!< TS Sample Low Set */
12718 #define DTS_TSHILORESETR_SMPL_HI_CLR_Pos          (1U)
12719 #define DTS_TSHILORESETR_SMPL_HI_CLR_Msk          (0x1UL << DTS_TSHILORESETR_SMPL_HI_CLR_Pos)         /*!< 0x00000002 */
12720 #define DTS_TSHILORESETR_SMPL_HI_CLR              DTS_TSHILORESETR_SMPL_HI_CLR_Msk                    /*!< TS Sample high clear 0 */
12721 
12722 
12723 /******************************************************************************/
12724 /*                                                                            */
12725 /*                              Ethernet MAC                                  */
12726 /*                                                                            */
12727 /******************************************************************************/
12728 /******  Bit definition for Ethernet MAC Configuration Register  **************/
12729 #define ETH_MACCR_ARP_Pos                             (31U)
12730 #define ETH_MACCR_ARP_Msk                             (0x1UL << ETH_MACCR_ARP_Pos) /*!< 0x80000000 */
12731 #define ETH_MACCR_ARP                                 ETH_MACCR_ARP_Msk        /* ARP Offload Enable */
12732 #define ETH_MACCR_SARC_Pos                            (28U)
12733 #define ETH_MACCR_SARC_Msk                            (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
12734 #define ETH_MACCR_SARC                                ETH_MACCR_SARC_Msk       /* Source Address Insertion or Replacement Control */
12735 #define ETH_MACCR_SARC_MTIATI                         ((uint32_t)0x00000000)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
12736 #define ETH_MACCR_SARC_INSADDR0_Pos                   (29U)
12737 #define ETH_MACCR_SARC_INSADDR0_Msk                   (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
12738 #define ETH_MACCR_SARC_INSADDR0                       ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
12739 #define ETH_MACCR_SARC_INSADDR1_Pos                   (29U)
12740 #define ETH_MACCR_SARC_INSADDR1_Msk                   (0x3UL << ETH_MACCR_SARC_INSADDR1_Pos) /*!< 0x60000000 */
12741 #define ETH_MACCR_SARC_INSADDR1                       ETH_MACCR_SARC_INSADDR1_Msk /* Insert MAC Address1 in the SA field of all transmitted packets. */
12742 #define ETH_MACCR_SARC_REPADDR0_Pos                   (28U)
12743 #define ETH_MACCR_SARC_REPADDR0_Msk                   (0x3UL << ETH_MACCR_SARC_REPADDR0_Pos) /*!< 0x30000000 */
12744 #define ETH_MACCR_SARC_REPADDR0                       ETH_MACCR_SARC_REPADDR0_Msk /* Replace MAC Address0 in the SA field of all transmitted packets. */
12745 #define ETH_MACCR_SARC_REPADDR1_Pos                   (28U)
12746 #define ETH_MACCR_SARC_REPADDR1_Msk                   (0x7UL << ETH_MACCR_SARC_REPADDR1_Pos) /*!< 0x70000000 */
12747 #define ETH_MACCR_SARC_REPADDR1                       ETH_MACCR_SARC_REPADDR1_Msk /* Replace MAC Address1 in the SA field of all transmitted packets. */
12748 #define ETH_MACCR_IPC_Pos                             (27U)
12749 #define ETH_MACCR_IPC_Msk                             (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */
12750 #define ETH_MACCR_IPC                                 ETH_MACCR_IPC_Msk        /* Checksum Offload */
12751 #define ETH_MACCR_IPG_Pos                             (24U)
12752 #define ETH_MACCR_IPG_Msk                             (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
12753 #define ETH_MACCR_IPG                                 ETH_MACCR_IPG_Msk        /* Inter-Packet Gap */
12754 #define ETH_MACCR_IPG_96BIT                           ((uint32_t)0x00000000)   /* Minimum IFG between Packets during transmission is 96Bit */
12755 #define ETH_MACCR_IPG_88BIT                           ((uint32_t)0x01000000)   /* Minimum IFG between Packets during transmission is 88Bit */
12756 #define ETH_MACCR_IPG_80BIT                           ((uint32_t)0x02000000)   /* Minimum IFG between Packets during transmission is 80Bit */
12757 #define ETH_MACCR_IPG_72BIT                           ((uint32_t)0x03000000)   /* Minimum IFG between Packets during transmission is 72Bit */
12758 #define ETH_MACCR_IPG_64BIT                           ((uint32_t)0x04000000)   /* Minimum IFG between Packets during transmission is 64Bit */
12759 #define ETH_MACCR_IPG_56BIT                           ((uint32_t)0x05000000)   /* Minimum IFG between Packets during transmission is 56Bit */
12760 #define ETH_MACCR_IPG_48BIT                           ((uint32_t)0x06000000)   /* Minimum IFG between Packets during transmission is 48Bit */
12761 #define ETH_MACCR_IPG_40BIT                           ((uint32_t)0x07000000)   /* Minimum IFG between Packets during transmission is 40Bit */
12762 #define ETH_MACCR_GPSLCE_Pos                          (23U)
12763 #define ETH_MACCR_GPSLCE_Msk                          (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
12764 #define ETH_MACCR_GPSLCE                              ETH_MACCR_GPSLCE_Msk     /* Giant Packet Size Limit Control Enable */
12765 #define ETH_MACCR_S2KP_Pos                            (22U)
12766 #define ETH_MACCR_S2KP_Msk                            (0x1UL << ETH_MACCR_S2KP_Pos) /*!< 0x00400000 */
12767 #define ETH_MACCR_S2KP                                ETH_MACCR_S2KP_Msk       /* IEEE 802.3as Support for 2K Packets */
12768 #define ETH_MACCR_CST_Pos                             (21U)
12769 #define ETH_MACCR_CST_Msk                             (0x1UL << ETH_MACCR_CST_Pos) /*!< 0x00200000 */
12770 #define ETH_MACCR_CST                                 ETH_MACCR_CST_Msk        /* CRC stripping for Type packets */
12771 #define ETH_MACCR_ACS_Pos                             (20U)
12772 #define ETH_MACCR_ACS_Msk                             (0x1UL << ETH_MACCR_ACS_Pos) /*!< 0x00100000 */
12773 #define ETH_MACCR_ACS                                 ETH_MACCR_ACS_Msk        /* Automatic Pad or CRC Stripping */
12774 #define ETH_MACCR_WD_Pos                              (19U)
12775 #define ETH_MACCR_WD_Msk                              (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00080000 */
12776 #define ETH_MACCR_WD                                  ETH_MACCR_WD_Msk         /* Watchdog disable */
12777 #define ETH_MACCR_PB_Pos                              (18U)
12778 #define ETH_MACCR_PB_Msk                              (0x1UL << ETH_MACCR_PB_Pos) /*!< 0x00040000 */
12779 #define ETH_MACCR_PB                                  ETH_MACCR_PB_Msk         /* Packet Burst Enable */
12780 #define ETH_MACCR_JD_Pos                              (17U)
12781 #define ETH_MACCR_JD_Msk                              (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00020000 */
12782 #define ETH_MACCR_JD                                  ETH_MACCR_JD_Msk         /* Jabber disable */
12783 #define ETH_MACCR_JE_Pos                              (16U)
12784 #define ETH_MACCR_JE_Msk                              (0x1UL << ETH_MACCR_JE_Pos) /*!< 0x00010000 */
12785 #define ETH_MACCR_JE                                  ETH_MACCR_JE_Msk         /* Jumbo Packet Enable */
12786 #define ETH_MACCR_PS_Pos                              (15U)
12787 #define ETH_MACCR_PS_Msk                              (0x1UL << ETH_MACCR_PS_Pos) /*!< 0x00008000 */
12788 #define ETH_MACCR_PS                                  ETH_MACCR_PS_Msk         /* Port Select */
12789 #define ETH_MACCR_FES_Pos                             (14U)
12790 #define ETH_MACCR_FES_Msk                             (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
12791 #define ETH_MACCR_FES                                 ETH_MACCR_FES_Msk        /* MAC speed */
12792 #define ETH_MACCR_DM_Pos                              (13U)
12793 #define ETH_MACCR_DM_Msk                              (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00002000 */
12794 #define ETH_MACCR_DM                                  ETH_MACCR_DM_Msk         /* Duplex mode */
12795 #define ETH_MACCR_LM_Pos                              (12U)
12796 #define ETH_MACCR_LM_Msk                              (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
12797 #define ETH_MACCR_LM                                  ETH_MACCR_LM_Msk         /* loopback mode */
12798 #define ETH_MACCR_ECRSFD_Pos                          (11U)
12799 #define ETH_MACCR_ECRSFD_Msk                          (0x1UL << ETH_MACCR_ECRSFD_Pos) /*!< 0x00000800 */
12800 #define ETH_MACCR_ECRSFD                              ETH_MACCR_ECRSFD_Msk     /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */
12801 #define ETH_MACCR_DO_Pos                              (10U)
12802 #define ETH_MACCR_DO_Msk                              (0x1UL << ETH_MACCR_DO_Pos) /*!< 0x00000400 */
12803 #define ETH_MACCR_DO                                  ETH_MACCR_DO_Msk         /* Disable Receive own  */
12804 #define ETH_MACCR_DCRS_Pos                            (9U)
12805 #define ETH_MACCR_DCRS_Msk                            (0x1UL << ETH_MACCR_DCRS_Pos) /*!< 0x00000200 */
12806 #define ETH_MACCR_DCRS                                ETH_MACCR_DCRS_Msk       /* Disable Carrier Sense During Transmission */
12807 #define ETH_MACCR_DR_Pos                              (8U)
12808 #define ETH_MACCR_DR_Msk                              (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */
12809 #define ETH_MACCR_DR                                  ETH_MACCR_DR_Msk         /* Disable Retry */
12810 #define ETH_MACCR_BL_Pos                              (5U)
12811 #define ETH_MACCR_BL_Msk                              (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
12812 #define ETH_MACCR_BL                                  ETH_MACCR_BL_Msk         /* Back-off limit mask */
12813 #define ETH_MACCR_BL_10                               (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */
12814 #define ETH_MACCR_BL_8                                (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */
12815 #define ETH_MACCR_BL_4                                (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */
12816 #define ETH_MACCR_BL_1                                (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
12817 #define ETH_MACCR_DC_Pos                              (4U)
12818 #define ETH_MACCR_DC_Msk                              (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
12819 #define ETH_MACCR_DC                                  ETH_MACCR_DC_Msk         /* Defferal check */
12820 #define ETH_MACCR_PRELEN_Pos                          (2U)
12821 #define ETH_MACCR_PRELEN_Msk                          (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */
12822 #define ETH_MACCR_PRELEN                              ETH_MACCR_PRELEN_Msk     /* Preamble Length for Transmit packets */
12823 #define ETH_MACCR_PRELEN_7                            (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */
12824 #define ETH_MACCR_PRELEN_5                            (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */
12825 #define ETH_MACCR_PRELEN_3                            (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */
12826 #define ETH_MACCR_TE_Pos                              (1U)
12827 #define ETH_MACCR_TE_Msk                              (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000002 */
12828 #define ETH_MACCR_TE                                  ETH_MACCR_TE_Msk         /* Transmitter enable */
12829 #define ETH_MACCR_RE_Pos                              (0U)
12830 #define ETH_MACCR_RE_Msk                              (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000001 */
12831 #define ETH_MACCR_RE                                  ETH_MACCR_RE_Msk         /* Receiver enable */
12832 
12833 /******  Bit definition for Ethernet MAC Extended Configuration Register  ***********/
12834 #define ETH_MACECR_APDIM_Pos                          (30U)
12835 #define ETH_MACECR_APDIM_Msk                          (0x1FUL << ETH_MACECR_APDIM_Pos) /*!< 0x40000000 */
12836 #define ETH_MACECR_APDIM                              ETH_MACECR_APDIM_Msk      /* ARP Packet Drop if IP Address Mismatch */
12837 #define ETH_MACECR_EIPG_Pos                           (25U)
12838 #define ETH_MACECR_EIPG_Msk                           (0x1FUL << ETH_MACECR_EIPG_Pos) /*!< 0x3E000000 */
12839 #define ETH_MACECR_EIPG                               ETH_MACECR_EIPG_Msk      /* Extended Inter-Packet Gap */
12840 #define ETH_MACECR_EIPGEN_Pos                         (24U)
12841 #define ETH_MACECR_EIPGEN_Msk                         (0x1UL << ETH_MACECR_EIPGEN_Pos) /*!< 0x01000000 */
12842 #define ETH_MACECR_EIPGEN                             ETH_MACECR_EIPGEN_Msk    /* Extended Inter-Packet Gap Enable */
12843 #define ETH_MACECR_USP_Pos                            (18U)
12844 #define ETH_MACECR_USP_Msk                            (0x1UL << ETH_MACECR_USP_Pos) /*!< 0x00040000 */
12845 #define ETH_MACECR_USP                                ETH_MACECR_USP_Msk       /* Unicast Slow Protocol Packet Detect */
12846 #define ETH_MACECR_SPEN_Pos                           (17U)
12847 #define ETH_MACECR_SPEN_Msk                           (0x1UL << ETH_MACECR_SPEN_Pos) /*!< 0x00020000 */
12848 #define ETH_MACECR_SPEN                               ETH_MACECR_SPEN_Msk      /* Slow Protocol Detection Enable */
12849 #define ETH_MACECR_DCRCC_Pos                          (16U)
12850 #define ETH_MACECR_DCRCC_Msk                          (0x1UL << ETH_MACECR_DCRCC_Pos) /*!< 0x00010000 */
12851 #define ETH_MACECR_DCRCC                              ETH_MACECR_DCRCC_Msk     /* Disable CRC Checking for Received Packets */
12852 #define ETH_MACECR_GPSL_Pos                           (0U)
12853 #define ETH_MACECR_GPSL_Msk                           (0x3FFFUL << ETH_MACECR_GPSL_Pos) /*!< 0x00003FFF */
12854 #define ETH_MACECR_GPSL                               ETH_MACECR_GPSL_Msk      /* Giant Packet Size Limit */
12855 
12856 /************  Bit definition for Ethernet MAC Packet Filter Register  ***************/
12857 #define ETH_MACPFR_RA_Pos                             (31U)
12858 #define ETH_MACPFR_RA_Msk                             (0x1UL << ETH_MACPFR_RA_Pos) /*!< 0x80000000 */
12859 #define ETH_MACPFR_RA                                 ETH_MACPFR_RA_Msk        /* Receive all */
12860 #define ETH_MACPFR_DNTU_Pos                           (21U)
12861 #define ETH_MACPFR_DNTU_Msk                           (0x1UL << ETH_MACPFR_DNTU_Pos) /*!< 0x00200000 */
12862 #define ETH_MACPFR_DNTU                               ETH_MACPFR_DNTU_Msk      /* Drop Non-TCP/UDP over IP Packets */
12863 #define ETH_MACPFR_IPFE_Pos                           (20U)
12864 #define ETH_MACPFR_IPFE_Msk                           (0x1UL << ETH_MACPFR_IPFE_Pos) /*!< 0x00100000 */
12865 #define ETH_MACPFR_IPFE                               ETH_MACPFR_IPFE_Msk      /* Layer 3 and Layer 4 Filter Enable */
12866 #define ETH_MACPFR_VTFE_Pos                           (16U)
12867 #define ETH_MACPFR_VTFE_Msk                           (0x1UL << ETH_MACPFR_VTFE_Pos) /*!< 0x00010000 */
12868 #define ETH_MACPFR_VTFE                               ETH_MACPFR_VTFE_Msk      /* VLAN Tag Filter Enable */
12869 #define ETH_MACPFR_HPF_Pos                            (10U)
12870 #define ETH_MACPFR_HPF_Msk                            (0x1UL << ETH_MACPFR_HPF_Pos) /*!< 0x00000400 */
12871 #define ETH_MACPFR_HPF                                ETH_MACPFR_HPF_Msk       /* Hash or perfect filter */
12872 #define ETH_MACPFR_SAF_Pos                            (9U)
12873 #define ETH_MACPFR_SAF_Msk                            (0x1UL << ETH_MACPFR_SAF_Pos) /*!< 0x00000200 */
12874 #define ETH_MACPFR_SAF                                ETH_MACPFR_SAF_Msk       /* Source address filter enable */
12875 #define ETH_MACPFR_SAIF_Pos                           (8U)
12876 #define ETH_MACPFR_SAIF_Msk                           (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */
12877 #define ETH_MACPFR_SAIF                               ETH_MACPFR_SAIF_Msk      /* SA inverse filtering */
12878 #define ETH_MACPFR_PCF_Pos                            (6U)
12879 #define ETH_MACPFR_PCF_Msk                            (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
12880 #define ETH_MACPFR_PCF                                ETH_MACPFR_PCF_Msk       /* Pass control frames: 4 cases */
12881 #define ETH_MACPFR_PCF_BLOCKALL                       ((uint32_t)0x00000000)   /* MAC filters all control frames from reaching the application */
12882 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos         (6U)
12883 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk         (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
12884 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA             ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
12885 #define ETH_MACPFR_PCF_FORWARDALL_Pos                 (7U)
12886 #define ETH_MACPFR_PCF_FORWARDALL_Msk                 (0x1UL << ETH_MACPFR_PCF_FORWARDALL_Pos) /*!< 0x00000080 */
12887 #define ETH_MACPFR_PCF_FORWARDALL                     ETH_MACPFR_PCF_FORWARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
12888 #define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos    (6U)
12889 #define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk    (0x3UL << ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos) /*!< 0x000000C0 */
12890 #define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER        ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk /* MAC forwards control frames that pass the Address Filter. */
12891 #define ETH_MACPFR_DBF_Pos                            (5U)
12892 #define ETH_MACPFR_DBF_Msk                            (0x1UL << ETH_MACPFR_DBF_Pos) /*!< 0x00000020 */
12893 #define ETH_MACPFR_DBF                                ETH_MACPFR_DBF_Msk       /* Disable Broadcast Packets */
12894 #define ETH_MACPFR_PM_Pos                             (4U)
12895 #define ETH_MACPFR_PM_Msk                             (0x1UL << ETH_MACPFR_PM_Pos) /*!< 0x00000010 */
12896 #define ETH_MACPFR_PM                                 ETH_MACPFR_PM_Msk        /* Pass all mutlicast */
12897 #define ETH_MACPFR_DAIF_Pos                           (3U)
12898 #define ETH_MACPFR_DAIF_Msk                           (0x1UL << ETH_MACPFR_DAIF_Pos) /*!< 0x00000008 */
12899 #define ETH_MACPFR_DAIF                               ETH_MACPFR_DAIF_Msk      /* DA Inverse filtering */
12900 #define ETH_MACPFR_HMC_Pos                            (2U)
12901 #define ETH_MACPFR_HMC_Msk                            (0x1UL << ETH_MACPFR_HMC_Pos) /*!< 0x00000004 */
12902 #define ETH_MACPFR_HMC                                ETH_MACPFR_HMC_Msk       /* Hash multicast */
12903 #define ETH_MACPFR_HUC_Pos                            (1U)
12904 #define ETH_MACPFR_HUC_Msk                            (0x1UL << ETH_MACPFR_HUC_Pos) /*!< 0x00000002 */
12905 #define ETH_MACPFR_HUC                                ETH_MACPFR_HUC_Msk       /* Hash unicast */
12906 #define ETH_MACPFR_PR_Pos                             (0U)
12907 #define ETH_MACPFR_PR_Msk                             (0x1UL << ETH_MACPFR_PR_Pos) /*!< 0x00000001 */
12908 #define ETH_MACPFR_PR                                 ETH_MACPFR_PR_Msk        /* Promiscuous mode */
12909 
12910 /************  Bit definition for Ethernet MAC Watchdog Timeout Register  ***************/
12911 #define ETH_MACWTR_PWE_Pos                            (8U)
12912 #define ETH_MACWTR_PWE_Msk                            (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */
12913 #define ETH_MACWTR_PWE                                ETH_MACWTR_PWE_Msk       /* Programmable Watchdog Enable */
12914 #define ETH_MACWTR_WTO_Pos                            (0U)
12915 #define ETH_MACWTR_WTO_Msk                            (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
12916 #define ETH_MACWTR_WTO                                ETH_MACWTR_WTO_Msk       /* Watchdog Timeout */
12917 #define ETH_MACWTR_WTO_2KB                            ((uint32_t)0x00000000)   /* Maximum received packet length 2KB*/
12918 #define ETH_MACWTR_WTO_3KB                            ((uint32_t)0x00000001)   /* Maximum received packet length 3KB */
12919 #define ETH_MACWTR_WTO_4KB                            ((uint32_t)0x00000002)   /* Maximum received packet length 4KB */
12920 #define ETH_MACWTR_WTO_5KB                            ((uint32_t)0x00000003)   /* Maximum received packet length 5KB */
12921 #define ETH_MACWTR_WTO_6KB                            ((uint32_t)0x00000004)   /* Maximum received packet length 6KB */
12922 #define ETH_MACWTR_WTO_7KB                            ((uint32_t)0x00000005)   /* Maximum received packet length 7KB */
12923 #define ETH_MACWTR_WTO_8KB                            ((uint32_t)0x00000006)   /* Maximum received packet length 8KB */
12924 #define ETH_MACWTR_WTO_9KB                            ((uint32_t)0x00000007)   /* Maximum received packet length 9KB */
12925 #define ETH_MACWTR_WTO_10KB                           ((uint32_t)0x00000008)   /* Maximum received packet length 10KB */
12926 #define ETH_MACWTR_WTO_11KB                           ((uint32_t)0x00000009)   /* Maximum received packet length 11KB */
12927 #define ETH_MACWTR_WTO_12KB                           ((uint32_t)0x0000000A)   /* Maximum received packet length 12KB */
12928 #define ETH_MACWTR_WTO_13KB                           ((uint32_t)0x0000000B)   /* Maximum received packet length 13KB */
12929 #define ETH_MACWTR_WTO_14KB                           ((uint32_t)0x0000000C)   /* Maximum received packet length 14KB */
12930 #define ETH_MACWTR_WTO_15KB                           ((uint32_t)0x0000000D)   /* Maximum received packet length 15KB */
12931 #define ETH_MACWTR_WTO_16KB                           ((uint32_t)0x0000000E)   /* Maximum received packet length 16KB */
12932 
12933 /************  Bit definition for Ethernet MAC Hash Table 0 register  ***************/
12934 #define ETH_MACHT0R_HTH_Pos                           (0U)
12935 #define ETH_MACHT0R_HTH_Msk                           (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
12936 #define ETH_MACHT0R_HTH                               ETH_MACHTHR_HTH_Msk      /* Hash table high */
12937 
12938 /************  Bit definition for Ethernet MAC Hash Table 1 register  ***************/
12939 #define ETH_MACHT1R_HTL_Pos                           (0U)
12940 #define ETH_MACHT1R_HTL_Msk                           (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
12941 #define ETH_MACHT1R_HTL                               ETH_MACHTLR_HTL_Msk      /* Hash table low */
12942 
12943 /************  Bit definition for Ethernet MAC VLAN tag Control register  ***************/
12944 #define ETH_MACVTCR_EIVLRXS_Pos                        (31U)
12945 #define ETH_MACVTCR_EIVLRXS_Msk                        (0x1UL << ETH_MACVTCR_EIVLRXS_Pos) /*!< 0x80000000 */
12946 #define ETH_MACVTCR_EIVLRXS                            ETH_MACVTCR_EIVLRXS_Msk   /* Enable Inner VLAN Tag in Rx Status */
12947 #define ETH_MACVTCR_EIVLS_Pos                          (28U)
12948 #define ETH_MACVTCR_EIVLS_Msk                          (0x3UL << ETH_MACVTCR_EIVLS_Pos) /*!< 0x30000000 */
12949 #define ETH_MACVTCR_EIVLS                              ETH_MACVTCR_EIVLS_Msk     /* Enable Inner VLAN Tag Stripping on Receive */
12950 #define ETH_MACVTCR_EIVLS_DONOTSTRIP                   ((uint32_t)0x00000000)   /* Do not strip */
12951 #define ETH_MACVTCR_EIVLS_STRIPIFPASS_Pos              (28U)
12952 #define ETH_MACVTCR_EIVLS_STRIPIFPASS_Msk              (0x1UL << ETH_MACVTCR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
12953 #define ETH_MACVTCR_EIVLS_STRIPIFPASS                  ETH_MACVTCR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
12954 #define ETH_MACVTCR_EIVLS_STRIPIFFAILS_Pos             (29U)
12955 #define ETH_MACVTCR_EIVLS_STRIPIFFAILS_Msk             (0x1UL << ETH_MACVTCR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */
12956 #define ETH_MACVTCR_EIVLS_STRIPIFFAILS                 ETH_MACVTCR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
12957 #define ETH_MACVTCR_EIVLS_ALWAYSSTRIP_Pos              (28U)
12958 #define ETH_MACVTCR_EIVLS_ALWAYSSTRIP_Msk              (0x3UL << ETH_MACVTCR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */
12959 #define ETH_MACVTCR_EIVLS_ALWAYSSTRIP                  ETH_MACVTCR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */
12960 #define ETH_MACVTCR_ERIVLT_Pos                         (27U)
12961 #define ETH_MACVTCR_ERIVLT_Msk                         (0x1UL << ETH_MACVTCR_ERIVLT_Pos) /*!< 0x08000000 */
12962 #define ETH_MACVTCR_ERIVLT                             ETH_MACVTCR_ERIVLT_Msk    /* Enable Inner VLAN Tag */
12963 #define ETH_MACVTCR_EDVLP_Pos                          (26U)
12964 #define ETH_MACVTCR_EDVLP_Msk                          (0x1UL << ETH_MACVTCR_EDVLP_Pos) /*!< 0x04000000 */
12965 #define ETH_MACVTCR_EDVLP                              ETH_MACVTCR_EDVLP_Msk     /* Enable Double VLAN Processing */
12966 #define ETH_MACVTCR_VTHM_Pos                           (25U)
12967 #define ETH_MACVTCR_VTHM_Msk                           (0x1UL << ETH_MACVTCR_VTHM_Pos) /*!< 0x02000000 */
12968 #define ETH_MACVTCR_VTHM                               ETH_MACVTCR_VTHM_Msk      /* VLAN Tag Hash Table Match Enable */
12969 #define ETH_MACVTCR_EVLRXS_Pos                         (24U)
12970 #define ETH_MACVTCR_EVLRXS_Msk                         (0x1UL << ETH_MACVTCR_EVLRXS_Pos) /*!< 0x01000000 */
12971 #define ETH_MACVTCR_EVLRXS                             ETH_MACVTCR_EVLRXS_Msk    /* Enable VLAN Tag in Rx status */
12972 #define ETH_MACVTCR_EVLS_Pos                           (21U)
12973 #define ETH_MACVTCR_EVLS_Msk                           (0x3UL << ETH_MACVTCR_EVLS_Pos) /*!< 0x00600000 */
12974 #define ETH_MACVTCR_EVLS                               ETH_MACVTCR_EVLS_Msk      /* Enable VLAN Tag Stripping on Receive */
12975 #define ETH_MACVTCR_EVLS_DONOTSTRIP                    ((uint32_t)0x00000000)   /* Do not strip */
12976 #define ETH_MACVTCR_EVLS_STRIPIFPASS_Pos               (21U)
12977 #define ETH_MACVTCR_EVLS_STRIPIFPASS_Msk               (0x1UL << ETH_MACVTCR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
12978 #define ETH_MACVTCR_EVLS_STRIPIFPASS                   ETH_MACVTCR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
12979 #define ETH_MACVTCR_EVLS_STRIPIFFAILS_Pos              (22U)
12980 #define ETH_MACVTCR_EVLS_STRIPIFFAILS_Msk              (0x1UL << ETH_MACVTCR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */
12981 #define ETH_MACVTCR_EVLS_STRIPIFFAILS                  ETH_MACVTCR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
12982 #define ETH_MACVTCR_EVLS_ALWAYSSTRIP_Pos               (21U)
12983 #define ETH_MACVTCR_EVLS_ALWAYSSTRIP_Msk               (0x3UL << ETH_MACVTCR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */
12984 #define ETH_MACVTCR_EVLS_ALWAYSSTRIP                   ETH_MACVTCR_EVLS_ALWAYSSTRIP_Msk /* Always strip */
12985 #define ETH_MACVTCR_DOVLTC_Pos                         (20U)
12986 #define ETH_MACVTCR_DOVLTC_Msk                         (0x1UL << ETH_MACVTCR_DOVLTC_Pos) /*!< 0x00100000 */
12987 #define ETH_MACVTCR_DOVLTC                             ETH_MACVTCR_DOVLTC_Msk    /* Disable VLAN Type Check */
12988 #define ETH_MACVTCR_ERSVLM_Pos                         (19U)
12989 #define ETH_MACVTCR_ERSVLM_Msk                         (0x1UL << ETH_MACVTCR_ERSVLM_Pos) /*!< 0x00080000 */
12990 #define ETH_MACVTCR_ERSVLM                             ETH_MACVTCR_ERSVLM_Msk    /* Enable Receive S-VLAN Match */
12991 #define ETH_MACVTCR_ESVL_Pos                           (18U)
12992 #define ETH_MACVTCR_ESVL_Msk                           (0x1UL << ETH_MACVTCR_ESVL_Pos) /*!< 0x00040000 */
12993 #define ETH_MACVTCR_ESVL                               ETH_MACVTCR_ESVL_Msk      /* Enable S-VLAN */
12994 #define ETH_MACVTCR_VTIM_Pos                           (17U)
12995 #define ETH_MACVTCR_VTIM_Msk                           (0x1UL << ETH_MACVTCR_VTIM_Pos) /*!< 0x00020000 */
12996 #define ETH_MACVTCR_VTIM                               ETH_MACVTCR_VTIM_Msk      /* VLAN Tag Inverse Match Enable */
12997 #define ETH_MACVTCR_ETV_Pos                            (16U)
12998 #define ETH_MACVTCR_ETV_Msk                            (0x1UL << ETH_MACVTCR_ETV_Pos) /*!< 0x00010000 */
12999 #define ETH_MACVTCR_ETV                                ETH_MACVTCR_ETV_Msk       /* Enable 12-Bit VLAN Tag Comparison */
13000 #define ETH_MACVTCR_OFS_Pos                            (2U)
13001 #define ETH_MACVTCR_OFS_Msk                            (0x3UL << ETH_MACVTCR_OFS_Pos) /*!< 0x0000000C */
13002 #define ETH_MACVTCR_OFS                                ETH_MACVTCR_EVLS_Msk      /* Offset */
13003 #define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER0             ((uint32_t)0x00000000)   /* holds MAC VLAN Tag Filter0 content */
13004 #define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER1_Pos         (2U)
13005 #define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER1_Msk         (0x1UL << ETH_MACVTCR_OFS_HOLDVLANTAGFILTER1_Pos) /*!< 0x00000004 */
13006 #define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER1             ETH_MACVTCR_OFS_HOLDVLANTAGFILTER1_Msk /* holds MAC VLAN Tag Filter1 content */
13007 #define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER2_Pos         (3U)
13008 #define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER2_Msk         (0x1UL << ETH_MACVTCR_OFS_HOLDVLANTAGFILTER2_Pos) /*!< 0x00000008 */
13009 #define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER2             ETH_MACVTCR_OFS_HOLDVLANTAGFILTER2_Msk /* holds MAC VLAN Tag Filter2 content */
13010 #define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER3_Pos         (2U)
13011 #define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER3_Msk         (0x3UL << ETH_MACVTCR_OFS_HOLDVLANTAGFILTER3_Pos) /*!< 0x0000000C */
13012 #define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER3             ETH_MACVTCR_OFS_HOLDVLANTAGFILTER3_Msk /* holds MAC VLAN Tag Filter3 content */
13013 #define ETH_MACVTCR_CT_Pos                             (1U)
13014 #define ETH_MACVTCR_CT_Msk                             (0x1UL << ETH_MACVTCR_CT_Pos) /*!< 0x00000002 */
13015 #define ETH_MACVTCR_CT                                 ETH_MACVTCR_CT_Msk       /* Command Type */
13016 #define ETH_MACVTCR_OB_Pos                             (0U)
13017 #define ETH_MACVTCR_OB_Msk                             (0x1UL << ETH_MACVTCR_OB_Pos) /*!< 0x00000001 */
13018 #define ETH_MACVTCR_OB                                 ETH_MACVTCR_OB_Msk       /* Operation Busy */
13019 
13020 /************  Bit definition for Ethernet MAC VLAN tag data register  ***************/
13021 #define ETH_MACVTDR_DMACHN_Pos                        (25U)
13022 #define ETH_MACVTDR_DMACHN_Msk                        (0x1UL << ETH_MACVTDR_DMACHN_Pos) /*!< 0x02000000 */
13023 #define ETH_MACVTDR_DMACHN                            ETH_MACVTDR_DMACHN_Msk   /* DMA Channel Number */
13024 #define ETH_MACVTDR_DMACHEN_Pos                       (24U)
13025 #define ETH_MACVTDR_DMACHEN_Msk                       (0x1UL << ETH_MACVTDR_DMACHEN_Pos) /*!< 0x01000000 */
13026 #define ETH_MACVTDR_DMACHEN                           ETH_MACVTDR_DMACHEN_Msk   /* DMA Channel Number Enable */
13027 #define ETH_MACVTDR_ERIVLT_Pos                        (20U)
13028 #define ETH_MACVTDR_ERIVLT_Msk                        (0x1UL << ETH_MACVTDR_ERIVLT_Pos) /*!< 0x00100000 */
13029 #define ETH_MACVTDR_ERIVLT                            ETH_MACVTDR_ERIVLT_Msk   /* Enable Inner VLAN Tag Comparison */
13030 #define ETH_MACVTDR_ERSVLM_Pos                        (19U)
13031 #define ETH_MACVTDR_ERSVLM_Msk                        (0x1UL << ETH_MACVTDR_ERSVLM_Pos) /*!< 0x00080000 */
13032 #define ETH_MACVTDR_ERSVLM                            ETH_MACVTDR_ERSVLM_Msk   /* Enable S-VLAN Match for received Frames */
13033 #define ETH_MACVTDR_DOVLTC_Pos                        (18U)
13034 #define ETH_MACVTDR_DOVLTC_Msk                        (0x1UL << ETH_MACVTDR_DOVLTC_Pos) /*!< 0x00080000 */
13035 #define ETH_MACVTDR_DOVLTC                            ETH_MACVTDR_DOVLTC_Msk   /* Disable VLAN Type Comparison */
13036 #define ETH_MACVTDR_ETV_Pos                           (17U)
13037 #define ETH_MACVTDR_ETV_Msk                           (0x1UL << ETH_MACVTDR_ETV_Pos) /*!< 0x00020000 */
13038 #define ETH_MACVTDR_ETV                               ETH_MACVTDR_ETV_Msk   /* 12-bit or 16-bit VLAN comparison */
13039 #define ETH_MACVTDR_ETV_VLAN16B                       ((uint32_t)0x00000000)   /* 16-bit VLAN */
13040 #define ETH_MACVTDR_ETV_VLAN12B_Pos                   (17U)
13041 #define ETH_MACVTDR_ETV_VLAN12B_Msk                   (0x1UL << ETH_MACVTDR_ETV_VLAN12B_Pos) /*!< 0x00020000 */
13042 #define ETH_MACVTDR_ETV_VLAN12B                       ETH_MACVTDR_ETV_VLAN12B_Msk   /* 12-bit VLAN */
13043 #define ETH_MACVTDR_VEN_Pos                           (16U)
13044 #define ETH_MACVTDR_VEN_Msk                           (0x1UL << ETH_MACVTDR_VEN_Pos) /*!< 0x00010000 */
13045 #define ETH_MACVTDR_VEN                               ETH_MACVTDR_VEN_Msk   /* VLAN Tag Enable */
13046 #define ETH_MACVTDR_VID_Pos                           (0U)
13047 #define ETH_MACVTDR_VID_Msk                           (0xFFFFUL << ETH_MACVTDR_VID_Pos) /*!< 0x0000FFFF */
13048 #define ETH_MACVTDR_VID                               ETH_MACVTDR_VID_Msk        /* VLAN Tag ID */
13049 #define ETH_MACVTDR_VID_12BIT_Msk                     (0xFFFU << ETH_MACVTDR_VID_Pos)                     /*!< 0x00000FFF */
13050 #define ETH_MACVTDR_VID_12BIT                         ETH_MACVTDR_VID_12BIT_Msk                           /*!< VLAN Tag Identifier field of VLAN tag 12bit */
13051 #define ETH_MACVTDR_VID_16BIT_Msk                     (0xFFFFU << ETH_MACVTDR_VID_Pos)                    /*!< 0x0000FFFF */
13052 #define ETH_MACVTDR_VID_16BIT                         ETH_MACVTDR_VID_16BIT_Msk                           /*!< VLAN Tag Identifier field of VLAN tag 16bit */
13053 #define ETH_MACVTDR_VID_0                             (0x1U << ETH_MACVTDR_VID_Pos)                       /*!< 0x00000001 */
13054 #define ETH_MACVTDR_VID_1                             (0x2U << ETH_MACVTDR_VID_Pos)                       /*!< 0x00000002 */
13055 #define ETH_MACVTDR_VID_2                             (0x4U << ETH_MACVTDR_VID_Pos)                       /*!< 0x00000004 */
13056 #define ETH_MACVTDR_VID_3                             (0x8U << ETH_MACVTDR_VID_Pos)                       /*!< 0x00000008 */
13057 #define ETH_MACVTDR_VID_4                             (0x10U << ETH_MACVTDR_VID_Pos)                      /*!< 0x00000010 */
13058 #define ETH_MACVTDR_VID_5                             (0x20U << ETH_MACVTDR_VID_Pos)                      /*!< 0x00000020 */
13059 #define ETH_MACVTDR_VID_6                             (0x40U << ETH_MACVTDR_VID_Pos)                      /*!< 0x00000040 */
13060 #define ETH_MACVTDR_VID_7                             (0x80U << ETH_MACVTDR_VID_Pos)                      /*!< 0x00000080 */
13061 #define ETH_MACVTDR_VID_8                             (0x100U << ETH_MACVTDR_VID_Pos)                     /*!< 0x00000100 */
13062 #define ETH_MACVTDR_VID_9                             (0x200U << ETH_MACVTDR_VID_Pos)                     /*!< 0x00000200 */
13063 #define ETH_MACVTDR_VID_10                            (0x400U << ETH_MACVTDR_VID_Pos)                     /*!< 0x00000400 */
13064 #define ETH_MACVTDR_VID_11                            (0x800U << ETH_MACVTDR_VID_Pos)                     /*!< 0x00000800 */
13065 #define ETH_MACVTDR_VID_12                            (0x1000U << ETH_MACVTDR_VID_Pos)                    /*!< 0x00001000 */
13066 #define ETH_MACVTDR_VID_13                            (0x2000U << ETH_MACVTDR_VID_Pos)                    /*!< 0x00002000 */
13067 #define ETH_MACVTDR_VID_14                            (0x4000U << ETH_MACVTDR_VID_Pos)                    /*!< 0x00004000 */
13068 #define ETH_MACVTDR_VID_15                            (0x8000U << ETH_MACVTDR_VID_Pos)                    /*!< 0x00008000 */
13069 
13070 /************  Bit definition for Ethernet MAC VLAN Hash Table Register  ***************/
13071 #define ETH_MACVHTR_VLHT_Pos                          (0U)
13072 #define ETH_MACVHTR_VLHT_Msk                          (0xFFFFUL << ETH_MACVHTR_VLHT_Pos) /*!< 0x0000FFFF */
13073 #define ETH_MACVHTR_VLHT                              ETH_MACVHTR_VLHT_Msk     /* VLAN Hash Table */
13074 
13075 /************  Bit definition for Ethernet MAC VLAN inclusion Register  ***************/
13076 #define ETH_MACVIR_BUSY_Pos                           (31U)
13077 #define ETH_MACVIR_BUSY_Msk                           (0x1UL << ETH_MACVIR_BUSY_Pos) /*!< 0x80000000 */
13078 #define ETH_MACVIR_BUSY                               ETH_MACVIR_BUSY_Msk      /* Busy */
13079 #define ETH_MACVIR_RDWR_Pos                           (30U)
13080 #define ETH_MACVIR_RDWR_Msk                           (0x1UL << ETH_MACVIR_RDWR_Pos) /*!< 0x40000000 */
13081 #define ETH_MACVIR_RDWR                               ETH_MACVIR_RDWR_Msk      /* Read write control */
13082 #define ETH_MACVIR_ADDR_Pos                           (24U)
13083 #define ETH_MACVIR_ADDR_Msk                           (0x1UL << ETH_MACVIR_ADDR_Pos) /*!< 0x01000000 */
13084 #define ETH_MACVIR_ADDR                               ETH_MACVIR_ADDR_Msk      /* Address */
13085 #define ETH_MACVIR_ADDR_VLANINSTXQ0                   ((uint32_t)0x00000000)   /* VLAN tag for insertion in the Transmit packets from Tx Queue 0 */
13086 #define ETH_MACVIR_ADDR_VLANINSTXQ1_Pos               (24U)
13087 #define ETH_MACVIR_ADDR_VLANINSTXQ1_Msk               (0x1UL << ETH_MACVIR_ADDR_VLANINSTXQ1_Pos) /*!< 0x01000000 */
13088 #define ETH_MACVIR_ADDR_VLANINSTXQ1                   ETH_MACVIR_ADDR_VLANINSTXQ1_Msk   /* VLAN tag for insertion in the Transmit packets from Tx Queue 1 */
13089 #define ETH_MACVIR_CBTI_Pos                           (21U)
13090 #define ETH_MACVIR_CBTI_Msk                           (0x1UL << ETH_MACVIR_CBTI_Pos) /*!< 0x00200000 */
13091 #define ETH_MACVIR_CBTI                               ETH_MACVIR_CBTI_Msk      /* Channel based tag insertion */
13092 #define ETH_MACVIR_VLTI_Pos                           (20U)
13093 #define ETH_MACVIR_VLTI_Msk                           (0x1UL << ETH_MACVIR_VLTI_Pos) /*!< 0x00100000 */
13094 #define ETH_MACVIR_VLTI                               ETH_MACVIR_VLTI_Msk      /* VLAN Tag Input */
13095 #define ETH_MACVIR_CSVL_Pos                           (19U)
13096 #define ETH_MACVIR_CSVL_Msk                           (0x1UL << ETH_MACVIR_CSVL_Pos) /*!< 0x00080000 */
13097 #define ETH_MACVIR_CSVL                               ETH_MACVIR_CSVL_Msk      /* C-VLAN or S-VLAN */
13098 #define ETH_MACVIR_VLP_Pos                            (18U)
13099 #define ETH_MACVIR_VLP_Msk                            (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */
13100 #define ETH_MACVIR_VLP                                ETH_MACVIR_VLP_Msk       /* VLAN Priority Control */
13101 #define ETH_MACVIR_VLC_Pos                            (16U)
13102 #define ETH_MACVIR_VLC_Msk                            (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
13103 #define ETH_MACVIR_VLC                                ETH_MACVIR_VLC_Msk       /* VLAN Tag Control in Transmit Packets */
13104 #define ETH_MACVIR_VLC_NOVLANTAG                      ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
13105 #define ETH_MACVIR_VLC_VLANTAGDELETE_Pos              (16U)
13106 #define ETH_MACVIR_VLC_VLANTAGDELETE_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
13107 #define ETH_MACVIR_VLC_VLANTAGDELETE                  ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
13108 #define ETH_MACVIR_VLC_VLANTAGINSERT_Pos              (17U)
13109 #define ETH_MACVIR_VLC_VLANTAGINSERT_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */
13110 #define ETH_MACVIR_VLC_VLANTAGINSERT                  ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
13111 #define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos             (16U)
13112 #define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk             (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */
13113 #define ETH_MACVIR_VLC_VLANTAGREPLACE                 ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
13114 #define ETH_MACVIR_VLT_Pos                            (0U)
13115 #define ETH_MACVIR_VLT_Msk                            (0xFFFFUL << ETH_MACVIR_VLT_Pos) /*!< 0x0000FFFF */
13116 #define ETH_MACVIR_VLT                                ETH_MACVIR_VLT_Msk       /* VLAN Tag for Transmit Packets */
13117 #define ETH_MACVIR_VLT_UP_Pos                         (13U)
13118 #define ETH_MACVIR_VLT_UP_Msk                         (0x7UL << ETH_MACVIR_VLT_UP_Pos) /*!< 0x0000E000 */
13119 #define ETH_MACVIR_VLT_UP                             ETH_MACVIR_VLT_UP_Msk    /* User Priority */
13120 #define ETH_MACVIR_VLT_CFIDEI_Pos                     (12U)
13121 #define ETH_MACVIR_VLT_CFIDEI_Msk                     (0x1UL << ETH_MACVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */
13122 #define ETH_MACVIR_VLT_CFIDEI                         ETH_MACVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
13123 #define ETH_MACVIR_VLT_VID_Pos                        (0U)
13124 #define ETH_MACVIR_VLT_VID_Msk                        (0xFFFUL << ETH_MACVIR_VLT_VID_Pos) /*!< 0x00000FFF */
13125 #define ETH_MACVIR_VLT_VID                            ETH_MACVIR_VLT_VID_Msk   /* VLAN Identifier field of VLAN tag */
13126 
13127 /************ Bit definition for Ethernet MAC Inner_VLAN Incl Register   ***************/
13128 #define ETH_MACIVIR_VLTI_Pos                          (20U)
13129 #define ETH_MACIVIR_VLTI_Msk                          (0x1UL << ETH_MACIVIR_VLTI_Pos) /*!< 0x00100000 */
13130 #define ETH_MACIVIR_VLTI                              ETH_MACIVIR_VLTI_Msk     /* VLAN Tag Input */
13131 #define ETH_MACIVIR_CSVL_Pos                          (19U)
13132 #define ETH_MACIVIR_CSVL_Msk                          (0x1UL << ETH_MACIVIR_CSVL_Pos) /*!< 0x00080000 */
13133 #define ETH_MACIVIR_CSVL                              ETH_MACIVIR_CSVL_Msk     /* C-VLAN or S-VLAN */
13134 #define ETH_MACIVIR_VLP_Pos                           (18U)
13135 #define ETH_MACIVIR_VLP_Msk                           (0x1UL << ETH_MACIVIR_VLP_Pos) /*!< 0x00040000 */
13136 #define ETH_MACIVIR_VLP                               ETH_MACIVIR_VLP_Msk      /* VLAN Priority Control */
13137 #define ETH_MACIVIR_VLC_Pos                           (16U)
13138 #define ETH_MACIVIR_VLC_Msk                           (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
13139 #define ETH_MACIVIR_VLC                               ETH_MACIVIR_VLC_Msk      /* VLAN Tag Control in Transmit Packets */
13140 #define ETH_MACIVIR_VLC_NOVLANTAG                     ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
13141 #define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos             (16U)
13142 #define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
13143 #define ETH_MACIVIR_VLC_VLANTAGDELETE                 ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
13144 #define ETH_MACIVIR_VLC_VLANTAGINSERT_Pos             (17U)
13145 #define ETH_MACIVIR_VLC_VLANTAGINSERT_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */
13146 #define ETH_MACIVIR_VLC_VLANTAGINSERT                 ETH_MACIVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
13147 #define ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos            (16U)
13148 #define ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk            (0x3UL << ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */
13149 #define ETH_MACIVIR_VLC_VLANTAGREPLACE                ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
13150 #define ETH_MACIVIR_VLT_Pos                           (0U)
13151 #define ETH_MACIVIR_VLT_Msk                           (0xFFFFUL << ETH_MACIVIR_VLT_Pos) /*!< 0x0000FFFF */
13152 #define ETH_MACIVIR_VLT                               ETH_MACIVIR_VLT_Msk      /* VLAN Tag for Transmit Packets */
13153 #define ETH_MACIVIR_VLT_UP_Pos                        (13U)
13154 #define ETH_MACIVIR_VLT_UP_Msk                        (0x7UL << ETH_MACIVIR_VLT_UP_Pos) /*!< 0x0000E000 */
13155 #define ETH_MACIVIR_VLT_UP                            ETH_MACIVIR_VLT_UP_Msk   /* User Priority */
13156 #define ETH_MACIVIR_VLT_CFIDEI_Pos                    (12U)
13157 #define ETH_MACIVIR_VLT_CFIDEI_Msk                    (0x1UL << ETH_MACIVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */
13158 #define ETH_MACIVIR_VLT_CFIDEI                        ETH_MACIVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
13159 #define ETH_MACIVIR_VLT_VID_Pos                       (0U)
13160 #define ETH_MACIVIR_VLT_VID_Msk                       (0xFFFUL << ETH_MACIVIR_VLT_VID_Pos) /*!< 0x00000FFF */
13161 #define ETH_MACIVIR_VLT_VID                           ETH_MACIVIR_VLT_VID_Msk  /* VLAN Identifier field of VLAN tag */
13162 
13163 /************ Bit definition for Ethernet MAC Tx Queue 0 flow control Register   ***************/
13164 #define ETH_MACQ0TXFCR_PT_Pos                         (16U)
13165 #define ETH_MACQ0TXFCR_PT_Msk                         (0xFFFFUL << ETH_MACQ0TXFCR_PT_Pos) /*!< 0xFFFF0000 */
13166 #define ETH_MACQ0TXFCR_PT                             ETH_MACQ0TXFCR_PT_Msk       /* Pause Time */
13167 #define ETH_MACQ0TXFCR_DZPQ_Pos                       (7U)
13168 #define ETH_MACQ0TXFCR_DZPQ_Msk                       (0x1UL << ETH_MACQ0TXFCR_DZPQ_Pos) /*!< 0x00000080 */
13169 #define ETH_MACQ0TXFCR_DZPQ                           ETH_MACQ0TXFCR_DZPQ_Msk     /* Disable Zero-Quanta Pause */
13170 #define ETH_MACQ0TXFCR_PLT_Pos                        (4U)
13171 #define ETH_MACQ0TXFCR_PLT_Msk                        (0x7UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000070 */
13172 #define ETH_MACQ0TXFCR_PLT                            ETH_MACQ0TXFCR_PLT_Msk      /* Pause Low Threshold */
13173 #define ETH_MACQ0TXFCR_PLT_MINUS4                     ((uint32_t)0x00000000)   /* Pause time minus 4 slot times */
13174 #define ETH_MACQ0TXFCR_PLT_MINUS28_Pos                (4U)
13175 #define ETH_MACQ0TXFCR_PLT_MINUS28_Msk                (0x1UL << ETH_MACQ0TXFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
13176 #define ETH_MACQ0TXFCR_PLT_MINUS28                    ETH_MACQ0TXFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
13177 #define ETH_MACQ0TXFCR_PLT_MINUS36_Pos                (5U)
13178 #define ETH_MACQ0TXFCR_PLT_MINUS36_Msk                (0x1UL << ETH_MACQ0TXFCR_PLT_MINUS36_Pos) /*!< 0x00000020 */
13179 #define ETH_MACQ0TXFCR_PLT_MINUS36                    ETH_MACQ0TXFCR_PLT_MINUS36_Msk /* Pause time minus 36 slot times */
13180 #define ETH_MACQ0TXFCR_PLT_MINUS144_Pos               (4U)
13181 #define ETH_MACQ0TXFCR_PLT_MINUS144_Msk               (0x3UL << ETH_MACQ0TXFCR_PLT_MINUS144_Pos) /*!< 0x00000030 */
13182 #define ETH_MACQ0TXFCR_PLT_MINUS144                   ETH_MACQ0TXFCR_PLT_MINUS144_Msk /* Pause time minus 144 slot times */
13183 #define ETH_MACQ0TXFCR_PLT_MINUS256_Pos               (6U)
13184 #define ETH_MACQ0TXFCR_PLT_MINUS256_Msk               (0x1UL << ETH_MACQ0TXFCR_PLT_MINUS256_Pos) /*!< 0x00000040 */
13185 #define ETH_MACQ0TXFCR_PLT_MINUS256                   ETH_MACQ0TXFCR_PLT_MINUS256_Msk /* Pause time minus 256 slot times */
13186 #define ETH_MACQ0TXFCR_PLT_MINUS512_Pos               (4U)
13187 #define ETH_MACQ0TXFCR_PLT_MINUS512_Msk               (0x5UL << ETH_MACQ0TXFCR_PLT_MINUS512_Pos) /*!< 0x00000050 */
13188 #define ETH_MACQ0TXFCR_PLT_MINUS512                   ETH_MACQ0TXFCR_PLT_MINUS512_Msk /* Pause time minus 512 slot times */
13189 #define ETH_MACQ0TXFCR_TFE_Pos                        (1U)
13190 #define ETH_MACQ0TXFCR_TFE_Msk                        (0x1UL << ETH_MACQ0TXFCR_TFE_Pos) /*!< 0x00000002 */
13191 #define ETH_MACQ0TXFCR_TFE                            ETH_MACQ0TXFCR_TFE_Msk      /* Transmit Flow Control Enable */
13192 #define ETH_MACQ0TXFCR_FCB_Pos                        (0U)
13193 #define ETH_MACQ0TXFCR_FCB_Msk                        (0x1UL << ETH_MACQ0TXFCR_FCB_Pos) /*!< 0x00000001 */
13194 #define ETH_MACQ0TXFCR_FCB                            ETH_MACQ0TXFCR_FCB_Msk      /* Flow Control Busy or Backpressure Activate */
13195 
13196 /************ Bit definition for Ethernet MAC Rx flow control Register   ***************/
13197 #define ETH_MACRXFCR_UP_Pos                            (1U)
13198 #define ETH_MACRXFCR_UP_Msk                            (0x1UL << ETH_MACRXFCR_UP_Pos) /*!< 0x00000002 */
13199 #define ETH_MACRXFCR_UP                                ETH_MACRXFCR_UP_Msk       /* Unicast Pause Packet Detect */
13200 #define ETH_MACRXFCR_RFE_Pos                           (0U)
13201 #define ETH_MACRXFCR_RFE_Msk                           (0x1UL << ETH_MACRXFCR_RFE_Pos) /*!< 0x00000001 */
13202 #define ETH_MACRXFCR_RFE                               ETH_MACRXFCR_RFE_Msk      /* Receive Flow Control Enable */
13203 
13204 /************ Bit definition for Ethernet MAC Rx Queue control Register  ***************/
13205 #define ETH_MACRXQCR_VFFQ_Pos                         (17U)
13206 #define ETH_MACRXQCR_VFFQ_Msk                         (0x1UL << ETH_MACRXQCR_VFFQ_Pos) /*!< 0x00020000 */
13207 #define ETH_MACRXQCR_VFFQ                             ETH_MACRXQCR_VFFQ_Msk       /* VLAN Tag Filter Fail Packets Queue */
13208 #define ETH_MACRXQCR_VFFQ_Q0                          ((uint32_t)0x00000000)      /* Queue 0 */
13209 #define ETH_MACRXQCR_VFFQ_Q1_Pos                      (17U)
13210 #define ETH_MACRXQCR_VFFQ_Q1_Msk                      (0x1UL << ETH_MACRXQCR_VFFQ_Q1_Pos) /*!< 0x00020000 */
13211 #define ETH_MACRXQCR_VFFQ_Q1                          ETH_MACRXQCR_VFFQ_Q1_Msk    /* Queue 1 */
13212 #define ETH_MACRXQCR_VFFQE_Pos                        (16U)
13213 #define ETH_MACRXQCR_VFFQE_Msk                        (0x1UL << ETH_MACRXQCR_VFFQE_Pos) /*!< 0x00010000 */
13214 #define ETH_MACRXQCR_VFFQE                            ETH_MACRXQCR_VFFQE_Msk       /* VLAN Tag Filter Fail Packets Queuing Enable */
13215 #define ETH_MACRXQCR_MFFQ_Pos                         (9U)
13216 #define ETH_MACRXQCR_MFFQ_Msk                         (0x1UL << ETH_MACRXQCR_MFFQ_Pos) /*!< 0x00000200 */
13217 #define ETH_MACRXQCR_MFFQ                             ETH_MACRXQCR_MFFQ_Msk       /* Multicast Address Filter Fail Packets Queue */
13218 #define ETH_MACRXQCR_MFFQ_Q0                          ((uint32_t)0x00000000)      /* Queue 0 */
13219 #define ETH_MACRXQCR_MFFQ_Q1_Pos                      (9U)
13220 #define ETH_MACRXQCR_MFFQ_Q1_Msk                      (0x1UL << ETH_MACRXQCR_MFFQ_Q1_Pos) /*!< 0x00000200 */
13221 #define ETH_MACRXQCR_MFFQ_Q1                          ETH_MACRXQCR_MFFQ_Q1_Msk    /* Queue 1 */
13222 #define ETH_MACRXQCR_MFFQE_Pos                        (8U)
13223 #define ETH_MACRXQCR_MFFQE_Msk                        (0x1UL << ETH_MACRXQCR_MFFQE_Pos) /*!< 0x00000100 */
13224 #define ETH_MACRXQCR_MFFQE                            ETH_MACRXQCR_MFFQE_Msk       /* Multicast Address Filter Fail Packets Queuing Enable */
13225 #define ETH_MACRXQCR_UFFQ_Pos                         (1U)
13226 #define ETH_MACRXQCR_UFFQ_Msk                         (0x1UL << ETH_MACRXQCR_UFFQ_Pos) /*!< 0x00000002 */
13227 #define ETH_MACRXQCR_UFFQ                             ETH_MACRXQCR_UFFQ_Msk       /* Unicast Address Filter Fail Packets Queue */
13228 #define ETH_MACRXQCR_UFFQ_Q0                          ((uint32_t)0x00000000)      /* Queue 0 */
13229 #define ETH_MACRXQCR_UFFQ_Q1_Pos                      (9U)
13230 #define ETH_MACRXQCR_UFFQ_Q1_Msk                      (0x1UL << ETH_MACRXQCR_UFFQ_Q1_Pos) /*!< 0x00000002 */
13231 #define ETH_MACRXQCR_UFFQ_Q1                          ETH_MACRXQCR_UFFQ_Q1_Msk    /* Queue 1 */
13232 #define ETH_MACRXQCR_UFFQE_Pos                        (0U)
13233 #define ETH_MACRXQCR_UFFQE_Msk                        (0x1UL << ETH_MACRXQCR_UFFQE_Pos) /*!< 0x00000001 */
13234 #define ETH_MACRXQCR_UFFQE                            ETH_MACRXQCR_UFFQE_Msk       /* Unicast Address Filter Fail Packets Queuing Enable */
13235 
13236 /************ Bit definition for Ethernet MAC Rx queue control 0 Register   ***************/
13237 #define ETH_MACRXQC0R_RXQ1EN_Pos                      (2U)
13238 #define ETH_MACRXQC0R_RXQ1EN_Msk                      (0x3UL << ETH_MACRXQC0R_RXQ1EN_Pos) /*!< 0x0000000C */
13239 #define ETH_MACRXQC0R_RXQ1EN                          ETH_MACRXQC0R_RXQ1EN_Msk       /* Receive Queue 1 Enable */
13240 #define ETH_MACRXQC0R_RXQ1EN_NOT                      ((uint32_t)0x00000000)        /* Queue 1 Not enabled */
13241 #define ETH_MACRXQC0R_RXQ1EN_AV_Pos                   (2U)
13242 #define ETH_MACRXQC0R_RXQ1EN_AV_Msk                   (0x1UL << ETH_MACRXQC0R_RXQ1EN_AV_Pos) /*!< 0x00000004 */
13243 #define ETH_MACRXQC0R_RXQ1EN_AV                       ETH_MACRXQC0R_RXQ1EN_AV_Msk   /* Queue 1 enabled for AV */
13244 #define ETH_MACRXQC0R_RXQ1EN_GT_Pos                   (3U)
13245 #define ETH_MACRXQC0R_RXQ1EN_GT_Msk                   (0x1UL << ETH_MACRXQC0R_RXQ1EN_GT_Pos) /*!< 0x00000008 */
13246 #define ETH_MACRXQC0R_RXQ1EN_GT                       ETH_MACRXQC0R_RXQ1EN_GT_Msk   /* Queue 1 enabled for Generic traffic */
13247 #define ETH_MACRXQC0R_RXQ0EN_Pos                      (0U)
13248 #define ETH_MACRXQC0R_RXQ0EN_Msk                      (0x3UL << ETH_MACRXQC0R_RXQ0EN_Pos) /*!< 0x00000003 */
13249 #define ETH_MACRXQC0R_RXQ0EN                          ETH_MACRXQC0R_RXQ0EN_Msk       /* Receive Queue 0 Enable */
13250 #define ETH_MACRXQC0R_RXQ0EN_NOT                      ((uint32_t)0x00000000)        /* Queue 0 Not enabled */
13251 #define ETH_MACRXQC0R_RXQ0EN_AV_Pos                   (0U)
13252 #define ETH_MACRXQC0R_RXQ0EN_AV_Msk                   (0x1UL << ETH_MACRXQC0R_RXQ0EN_AV_Pos) /*!< 0x00000001 */
13253 #define ETH_MACRXQC0R_RXQ0EN_AV                       ETH_MACRXQC0R_RXQ0EN_AV_Msk   /* Queue 0 enabled for AV */
13254 #define ETH_MACRXQC0R_RXQ0EN_GT_Pos                   (1U)
13255 #define ETH_MACRXQC0R_RXQ0EN_GT_Msk                   (0x1UL << ETH_MACRXQC0R_RXQ0EN_GT_Pos) /*!< 0x00000002 */
13256 #define ETH_MACRXQC0R_RXQ0EN_GT                       ETH_MACRXQC0R_RXQ0EN_GT_Msk   /* Queue 0 enabled for Generic traffic */
13257 
13258 /************ Bit definition for Ethernet MAC Rx queue control 1 Register   ***************/
13259 #define ETH_MACRXQC1R_TBRQE_Pos                       (29U)
13260 #define ETH_MACRXQC1R_TBRQE_Msk                       (0x1UL << ETH_MACRXQC1R_TBRQE_Pos) /*!< 0x20000000 */
13261 #define ETH_MACRXQC1R_TBRQE                           ETH_MACRXQC1R_TBRQE_Msk       /* Type Field Based Rx Queuing Enable */
13262 #define ETH_MACRXQC1R_OMCBCQ_Pos                      (28U)
13263 #define ETH_MACRXQC1R_OMCBCQ_Msk                      (0x1UL << ETH_MACRXQC1R_OMCBCQ_Pos) /*!< 0x10000000 */
13264 #define ETH_MACRXQC1R_OMCBCQ                          ETH_MACRXQC1R_OMCBCQ_Msk       /* Overriding MC-BC queue priority select */
13265 #define ETH_MACRXQC1R_FPRQ_Pos                        (24U)
13266 #define ETH_MACRXQC1R_FPRQ_Msk                        (0x7UL << ETH_MACRXQC1R_FPRQ_Pos) /*!< 0x07000000 */
13267 #define ETH_MACRXQC1R_FPRQ                            ETH_MACRXQC1R_FPRQ_Msk       /* Frame Preemption Residue Queue */
13268 #define ETH_MACRXQC1R_FPRQ_RXQ1_Pos                   (24U)
13269 #define ETH_MACRXQC1R_FPRQ_RXQ1_Msk                   (0x1UL << ETH_MACRXQC1R_FPRQ_RXQ1_Pos) /*!< 0x01000000 */
13270 #define ETH_MACRXQC1R_FPRQ_RXQ1                       ETH_MACRXQC1R_FPRQ_RXQ1_Msk       /* Rx queue 1 */
13271 #define ETH_MACRXQC1R_TPQC_Pos                        (22U)
13272 #define ETH_MACRXQC1R_TPQC_Msk                        (0x3UL << ETH_MACRXQC1R_TPQC_Pos) /*!< 0x07000000 */
13273 #define ETH_MACRXQC1R_TPQC                            ETH_MACRXQC1R_TPQC_Msk   /* Tagged PTP over Ethernet Packets Queuing Control */
13274 #define ETH_MACRXQC1R_TPQC_PTPGENVLANTAG              ((uint32_t)0x00000000)   /* VLAN tagged PTPoE packets are routed as generic VLAN tagged packet */
13275 #define ETH_MACRXQC1R_TPQC_PTPRXQPTPQ_Pos             (22U)
13276 #define ETH_MACRXQC1R_TPQC_PTPRXQPTPQ_Msk             (0x1UL << ETH_MACRXQC1R_TPQC_PTPRXQPTPQ_Pos) /*!< 0x000400000 */
13277 #define ETH_MACRXQC1R_TPQC_PTPRXQPTPQ                 ETH_MACRXQC1R_TPQC_PTPRXQPTPQ_Msk /* VLAN tagged PTPoE packets are routed to Rx Queue specified by PTPQ field */
13278 #define ETH_MACRXQC1R_TPQC_PTPAVRXQPSRQ_Pos           (23U)
13279 #define ETH_MACRXQC1R_TPQC_PTPAVRXQPSRQ_Msk           (0x1UL << ETH_MACRXQC1R_TPQC_PTPAVRXQPSRQ_Pos) /*!< 0x00080000 */
13280 #define ETH_MACRXQC1R_TPQC_PTPAVRXQPSRQ               ETH_MACRXQC1R_TPQC_PTPAVRXQPSRQ_Msk /* VLAN tagged PTPoE packets are routed to only AV enabled Rx queues based on PSRQ */
13281 #define ETH_MACRXQC1R_TACPQE_Pos                      (21U)
13282 #define ETH_MACRXQC1R_TACPQE_Msk                      (0x1UL << ETH_MACRXQC1R_TACPQE_Pos) /*!< 0x00200000 */
13283 #define ETH_MACRXQC1R_TACPQE                          ETH_MACRXQC1R_TACPQE_Msk       /* Tagged AV Control Packets Queuing Enable */
13284 #define ETH_MACRXQC1R_MCBCQEN_Pos                     (20U)
13285 #define ETH_MACRXQC1R_MCBCQEN_Msk                     (0x1UL << ETH_MACRXQC1R_MCBCQEN_Pos) /*!< 0x00100000 */
13286 #define ETH_MACRXQC1R_MCBCQEN                         ETH_MACRXQC1R_MCBCQEN_Msk     /* Multicast and Broadcast Queue Enable */
13287 #define ETH_MACRXQC1R_MCBCQ_Pos                       (16U)
13288 #define ETH_MACRXQC1R_MCBCQ_Msk                       (0x7UL << ETH_MACRXQC1R_MCBCQ_Pos) /*!< 0x00070000 */
13289 #define ETH_MACRXQC1R_MCBCQ                           ETH_MACRXQC1R_MCBCQ_Msk       /* Multicast and Broadcast Queue */
13290 #define ETH_MACRXQC1R_MCBCQ_RXQ0                      ((uint32_t)0x00000000)   /* Rx queue 0 */
13291 #define ETH_MACRXQC1R_MCBCQ_RXQ1_Pos                  (16U)
13292 #define ETH_MACRXQC1R_MCBCQ_RXQ1_Msk                  (0x1UL << ETH_MACRXQC1R_MCBCQ_RXQ1_Pos) /*!< 0x00010000 */
13293 #define ETH_MACRXQC1R_MCBCQ_RXQ1                      ETH_MACRXQC1R_MCBCQ_RXQ1_Msk  /* Rx queue 1 */
13294 #define ETH_MACRXQC1R_UPQ_Pos                         (12U)
13295 #define ETH_MACRXQC1R_UPQ_Msk                         (0x7UL << ETH_MACRXQC1R_UPQ_Pos) /*!< 0x00007000 */
13296 #define ETH_MACRXQC1R_UPQ                             ETH_MACRXQC1R_UPQ_Msk       /* Untagged Packet Queue */
13297 #define ETH_MACRXQC1R_UPQ_RXQ0                        ((uint32_t)0x00000000)   /* Rx queue 0 */
13298 #define ETH_MACRXQC1R_UPQ_RXQ1_Pos                    (12U)
13299 #define ETH_MACRXQC1R_UPQ_RXQ1_Msk                    (0x1UL << ETH_MACRXQC1R_UPQ_RXQ1_Pos) /*!< 0x00001000 */
13300 #define ETH_MACRXQC1R_UPQ_RXQ1                        ETH_MACRXQC1R_UPQ_RXQ1_Msk  /* Rx queue 1 */
13301 #define ETH_MACRXQC1R_PTPQ_Pos                        (4U)
13302 #define ETH_MACRXQC1R_PTPQ_Msk                        (0x7UL << ETH_MACRXQC1R_PTPQ_Pos) /*!< 0x00000070 */
13303 #define ETH_MACRXQC1R_PTPQ                            ETH_MACRXQC1R_PTPQ_Msk       /* PTP Packets Queue */
13304 #define ETH_MACRXQC1R_PTPQ_RXQ0                       ((uint32_t)0x00000000)   /* Rx queue 0 */
13305 #define ETH_MACRXQC1R_PTPQ_RXQ1_Pos                   (4U)
13306 #define ETH_MACRXQC1R_PTPQ_RXQ1_Msk                   (0x1UL << ETH_MACRXQC1R_PTPQ_RXQ1_Pos) /*!< 0x00000010 */
13307 #define ETH_MACRXQC1R_PTPQ_RXQ1                       ETH_MACRXQC1R_PTPQ_RXQ1_Msk  /* Rx queue 1 */
13308 #define ETH_MACRXQC1R_AVCPQ_Pos                       (0U)
13309 #define ETH_MACRXQC1R_AVCPQ_Msk                       (0x7UL << ETH_MACRXQC1R_AVCPQ_Pos) /*!< 0x00000007 */
13310 #define ETH_MACRXQC1R_AVCPQ                           ETH_MACRXQC1R_AVCPQ_Msk       /* AV Untagged Control Packets Queue */
13311 #define ETH_MACRXQC1R_AVCPQ_RXQ0                      ((uint32_t)0x00000000)   /* Rx queue 0 */
13312 #define ETH_MACRXQC1R_AVCPQ_RXQ1_Pos                  (0U)
13313 #define ETH_MACRXQC1R_AVCPQ_RXQ1_Msk                  (0x1UL << ETH_MACRXQC1R_AVCPQ_RXQ1_Pos) /*!< 0x00000001 */
13314 #define ETH_MACRXQC1R_AVCPQ_RXQ1                      ETH_MACRXQC1R_AVCPQ_RXQ1_Msk  /* Rx queue 1 */
13315 
13316 /************ Bit definition for Ethernet MAC Rx queue control 2 Register   ***************/
13317 #define ETH_MACRXQC2R_PSRQ1_Pos                       (8U)
13318 #define ETH_MACRXQC2R_PSRQ1_Msk                       (0xFFUL << ETH_MACRXQC2R_PSRQ1_Pos) /*!< 0x0000FF00 */
13319 #define ETH_MACRXQC2R_PSRQ1                           ETH_MACRXQC2R_PSRQ1_Msk       /* Priorities Selected in the Receive Queue 1 */
13320 #define ETH_MACRXQC2R_PSRQ0_Pos                       (0U)
13321 #define ETH_MACRXQC2R_PSRQ0_Msk                       (0xFFUL << ETH_MACRXQC2R_PSRQ0_Pos) /*!< 0x000000FF */
13322 #define ETH_MACRXQC2R_PSRQ0                           ETH_MACRXQC2R_PSRQ0_Msk       /* Priorities Selected in the Receive Queue 0 */
13323 
13324 /************ Bit definition for Ethernet MAC Interrupt Status Register   ***************/
13325 #define ETH_MACISR_MFRIS_Pos                          (20U)
13326 #define ETH_MACISR_MFRIS_Msk                          (0x1UL << ETH_MACISR_MFRIS_Pos) /*!< 0x00100000 */
13327 #define ETH_MACISR_MFRIS                              ETH_MACISR_MFRIS_Msk   /* MMC FPE Receive Interrupt Status */
13328 #define ETH_MACISR_MFTIS_Pos                          (19U)
13329 #define ETH_MACISR_MFTIS_Msk                          (0x1UL << ETH_MACISR_MFTIS_Pos) /*!< 0x00080000 */
13330 #define ETH_MACISR_MFTIS                              ETH_MACISR_MFTIS_Msk   /* MMC FPE Transmit Interrupt Status */
13331 #define ETH_MACISR_MDIOIS_Pos                         (18U)
13332 #define ETH_MACISR_MDIOIS_Msk                         (0x1UL << ETH_MACISR_MDIOIS_Pos) /*!< 0x00040000 */
13333 #define ETH_MACISR_MDIOIS                             ETH_MACISR_MDIOIS_Msk   /* MDIO Interrupt Status*/
13334 #define ETH_MACISR_FPEIS_Pos                          (17U)
13335 #define ETH_MACISR_FPEIS_Msk                          (0x1UL << ETH_MACISR_FPEIS_Pos) /*!< 0x00020000 */
13336 #define ETH_MACISR_FPEIS                              ETH_MACISR_FPEIS_Msk   /* Frame Preemption Interrupt Status */
13337 #define ETH_MACISR_RXSTSIS_Pos                        (14U)
13338 #define ETH_MACISR_RXSTSIS_Msk                        (0x1UL << ETH_MACISR_RXSTSIS_Pos) /*!< 0x00004000 */
13339 #define ETH_MACISR_RXSTSIS                            ETH_MACISR_RXSTSIS_Msk   /* Receive Status Interrupt */
13340 #define ETH_MACISR_TXSTSIS_Pos                        (13U)
13341 #define ETH_MACISR_TXSTSIS_Msk                        (0x1UL << ETH_MACISR_TXSTSIS_Pos) /*!< 0x00002000 */
13342 #define ETH_MACISR_TXSTSIS                            ETH_MACISR_TXSTSIS_Msk   /* Transmit Status Interrupt */
13343 #define ETH_MACISR_TSIS_Pos                           (12U)
13344 #define ETH_MACISR_TSIS_Msk                           (0x1UL << ETH_MACISR_TSIS_Pos) /*!< 0x00001000 */
13345 #define ETH_MACISR_TSIS                               ETH_MACISR_TSIS_Msk      /* Timestamp Interrupt Status */
13346 #define ETH_MACISR_MMCTXIS_Pos                        (10U)
13347 #define ETH_MACISR_MMCTXIS_Msk                        (0x1UL << ETH_MACISR_MMCTXIS_Pos) /*!< 0x00000400 */
13348 #define ETH_MACISR_MMCTXIS                            ETH_MACISR_MMCTXIS_Msk   /* MMC Transmit Interrupt Status */
13349 #define ETH_MACISR_MMCRXIS_Pos                        (9U)
13350 #define ETH_MACISR_MMCRXIS_Msk                        (0x1UL << ETH_MACISR_MMCRXIS_Pos) /*!< 0x00000200 */
13351 #define ETH_MACISR_MMCRXIS                            ETH_MACISR_MMCRXIS_Msk   /* MMC Receive Interrupt Status */
13352 #define ETH_MACISR_MMCIS_Pos                          (8U)
13353 #define ETH_MACISR_MMCIS_Msk                          (0x1UL << ETH_MACISR_MMCIS_Pos) /*!< 0x00000100 */
13354 #define ETH_MACISR_MMCIS                              ETH_MACISR_MMCIS_Msk     /* MMC Interrupt Status */
13355 #define ETH_MACISR_LPIIS_Pos                          (5U)
13356 #define ETH_MACISR_LPIIS_Msk                          (0x1UL << ETH_MACISR_LPIIS_Pos) /*!< 0x00000020 */
13357 #define ETH_MACISR_LPIIS                              ETH_MACISR_LPIIS_Msk     /* LPI Interrupt Status */
13358 #define ETH_MACISR_PMTIS_Pos                          (4U)
13359 #define ETH_MACISR_PMTIS_Msk                          (0x1UL << ETH_MACISR_PMTIS_Pos) /*!< 0x00000010 */
13360 #define ETH_MACISR_PMTIS                              ETH_MACISR_PMTIS_Msk     /* PMT Interrupt Status */
13361 #define ETH_MACISR_PHYIS_Pos                          (3U)
13362 #define ETH_MACISR_PHYIS_Msk                          (0x1UL << ETH_MACISR_PHYIS_Pos) /*!< 0x00000008 */
13363 #define ETH_MACISR_PHYIS                              ETH_MACISR_PHYIS_Msk     /* PHY Interrupt */
13364 #define ETH_MACISR_RGSMIIIS_Pos                       (0U)
13365 #define ETH_MACISR_RGSMIIIS_Msk                       (0x1UL << ETH_MACISR_RGSMIIIS_Pos) /*!< 0x00000001 */
13366 #define ETH_MACISR_RGSMIIIS                           ETH_MACISR_RGSMIIIS_Msk     /* RGMII Interrupt Status */
13367 
13368 /************ Bit definition for Ethernet MAC Interrupt Status Register   ***************/
13369 #define ETH_MACISR_MDIOIE_Pos                         (18U)
13370 #define ETH_MACISR_MDIOIE_Msk                         (0x1UL << ETH_MACISR_MDIOIE_Pos) /*!< 0x00040000 */
13371 #define ETH_MACISR_MDIOIE                             ETH_MACISR_MDIOIE_Msk   /* Receive Interrupt Enable*/
13372 #define ETH_MACISR_FPEIE_Pos                          (17U)
13373 #define ETH_MACISR_FPEIE_Msk                          (0x1UL << ETH_MACISR_FPEIE_Pos) /*!< 0x00020000 */
13374 #define ETH_MACISR_FPEIE                              ETH_MACISR_FPEIE_Msk   /* Frame Preemption Interrupt Enable */
13375 #define ETH_MACIER_RXSTSIE_Pos                        (14U)
13376 #define ETH_MACIER_RXSTSIE_Msk                        (0x1UL << ETH_MACIER_RXSTSIE_Pos) /*!< 0x00004000 */
13377 #define ETH_MACIER_RXSTSIE                            ETH_MACIER_RXSTSIE_Msk   /* Receive Status Interrupt Enable */
13378 #define ETH_MACIER_TXSTSIE_Pos                        (13U)
13379 #define ETH_MACIER_TXSTSIE_Msk                        (0x1UL << ETH_MACIER_TXSTSIE_Pos) /*!< 0x00002000 */
13380 #define ETH_MACIER_TXSTSIE                            ETH_MACIER_TXSTSIE_Msk   /* Transmit Status Interrupt Enable */
13381 #define ETH_MACIER_TSIE_Pos                           (12U)
13382 #define ETH_MACIER_TSIE_Msk                           (0x1UL << ETH_MACIER_TSIE_Pos) /*!< 0x00001000 */
13383 #define ETH_MACIER_TSIE                               ETH_MACIER_TSIE_Msk      /* Timestamp Interrupt Enable */
13384 #define ETH_MACIER_LPIIE_Pos                          (5U)
13385 #define ETH_MACIER_LPIIE_Msk                          (0x1UL << ETH_MACIER_LPIIE_Pos) /*!< 0x00000020 */
13386 #define ETH_MACIER_LPIIE                              ETH_MACIER_LPIIE_Msk     /* LPI Interrupt Enable */
13387 #define ETH_MACIER_PMTIE_Pos                          (4U)
13388 #define ETH_MACIER_PMTIE_Msk                          (0x1UL << ETH_MACIER_PMTIE_Pos) /*!< 0x00000010 */
13389 #define ETH_MACIER_PMTIE                              ETH_MACIER_PMTIE_Msk     /* PMT Interrupt Enable */
13390 #define ETH_MACIER_PHYIE_Pos                          (3U)
13391 #define ETH_MACIER_PHYIE_Msk                          (0x1UL << ETH_MACIER_PHYIE_Pos) /*!< 0x00000008 */
13392 #define ETH_MACIER_PHYIE                              ETH_MACIER_PHYIE_Msk     /* PHY Interrupt Enable */
13393 #define ETH_MACISR_RGSMIIIE_Pos                       (0U)
13394 #define ETH_MACISR_RGSMIIIE_Msk                       (0x1UL << ETH_MACISR_RGSMIIIE_Pos) /*!< 0x00000001 */
13395 #define ETH_MACISR_RGSMIIIE                           ETH_MACISR_RGSMIIIE_Msk     /* RGMII Interrupt Enable */
13396 
13397 /************ Bit definition for Ethernet MAC Rx Tx Status Register   ***************/
13398 #define ETH_MACRXTXSR_RWT_Pos                         (8U)
13399 #define ETH_MACRXTXSR_RWT_Msk                         (0x1UL << ETH_MACRXTXSR_RWT_Pos) /*!< 0x00000100 */
13400 #define ETH_MACRXTXSR_RWT                             ETH_MACRXTXSR_RWT_Msk    /* Receive Watchdog Timeout */
13401 #define ETH_MACRXTXSR_EXCOL_Pos                       (5U)
13402 #define ETH_MACRXTXSR_EXCOL_Msk                       (0x1UL << ETH_MACRXTXSR_EXCOL_Pos) /*!< 0x00000020 */
13403 #define ETH_MACRXTXSR_EXCOL                           ETH_MACRXTXSR_EXCOL_Msk  /* Excessive Collisions */
13404 #define ETH_MACRXTXSR_LCOL_Pos                        (4U)
13405 #define ETH_MACRXTXSR_LCOL_Msk                        (0x1UL << ETH_MACRXTXSR_LCOL_Pos) /*!< 0x00000010 */
13406 #define ETH_MACRXTXSR_LCOL                            ETH_MACRXTXSR_LCOL_Msk   /* Late Collision */
13407 #define ETH_MACRXTXSR_EXDEF_Pos                       (3U)
13408 #define ETH_MACRXTXSR_EXDEF_Msk                       (0x1UL << ETH_MACRXTXSR_EXDEF_Pos) /*!< 0x00000008 */
13409 #define ETH_MACRXTXSR_EXDEF                           ETH_MACRXTXSR_EXDEF_Msk  /* Excessive Deferral */
13410 #define ETH_MACRXTXSR_LCARR_Pos                       (2U)
13411 #define ETH_MACRXTXSR_LCARR_Msk                       (0x1UL << ETH_MACRXTXSR_LCARR_Pos) /*!< 0x00000004 */
13412 #define ETH_MACRXTXSR_LCARR                           ETH_MACRXTXSR_LCARR_Msk  /* Loss of Carrier */
13413 #define ETH_MACRXTXSR_NCARR_Pos                       (1U)
13414 #define ETH_MACRXTXSR_NCARR_Msk                       (0x1UL << ETH_MACRXTXSR_NCARR_Pos) /*!< 0x00000002 */
13415 #define ETH_MACRXTXSR_NCARR                           ETH_MACRXTXSR_NCARR_Msk  /* No Carrier */
13416 #define ETH_MACRXTXSR_TJT_Pos                         (0U)
13417 #define ETH_MACRXTXSR_TJT_Msk                         (0x1UL << ETH_MACRXTXSR_TJT_Pos) /*!< 0x00000001 */
13418 #define ETH_MACRXTXSR_TJT                             ETH_MACRXTXSR_TJT_Msk    /* Transmit Jabber Timeout */
13419 
13420 /************ Bit definition for Ethernet MAC PMT Control Status Register   ***************/
13421 #define ETH_MACPCSR_RWKFILTRST_Pos                    (31U)
13422 #define ETH_MACPCSR_RWKFILTRST_Msk                    (0x1UL << ETH_MACPCSR_RWKFILTRST_Pos) /*!< 0x80000000 */
13423 #define ETH_MACPCSR_RWKFILTRST                        ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up Packet Filter Register Pointer Reset */
13424 #define ETH_MACPCSR_RWKPTR_Pos                        (24U)
13425 #define ETH_MACPCSR_RWKPTR_Msk                        (0x1FUL << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x1F000000 */
13426 #define ETH_MACPCSR_RWKPTR                            ETH_MACPCSR_RWKPTR_Msk   /* Remote Wake-up FIFO Pointer */
13427 #define ETH_MACPCSR_RWKPFE_Pos                        (10U)
13428 #define ETH_MACPCSR_RWKPFE_Msk                        (0x1UL << ETH_MACPCSR_RWKPFE_Pos) /*!< 0x00000400 */
13429 #define ETH_MACPCSR_RWKPFE                            ETH_MACPCSR_RWKPFE_Msk   /* Remote Wake-up Packet Forwarding Enable */
13430 #define ETH_MACPCSR_GLBLUCAST_Pos                     (9U)
13431 #define ETH_MACPCSR_GLBLUCAST_Msk                     (0x1UL << ETH_MACPCSR_GLBLUCAST_Pos) /*!< 0x00000200 */
13432 #define ETH_MACPCSR_GLBLUCAST                         ETH_MACPCSR_GLBLUCAST_Msk /* Global Unicast */
13433 #define ETH_MACPCSR_RWKPRCVD_Pos                      (6U)
13434 #define ETH_MACPCSR_RWKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_RWKPRCVD_Pos) /*!< 0x00000040 */
13435 #define ETH_MACPCSR_RWKPRCVD                          ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Packet Received */
13436 #define ETH_MACPCSR_MGKPRCVD_Pos                      (5U)
13437 #define ETH_MACPCSR_MGKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_MGKPRCVD_Pos) /*!< 0x00000020 */
13438 #define ETH_MACPCSR_MGKPRCVD                          ETH_MACPCSR_MGKPRCVD_Msk /* Magic Packet Received */
13439 #define ETH_MACPCSR_RWKPKTEN_Pos                      (2U)
13440 #define ETH_MACPCSR_RWKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_RWKPKTEN_Pos) /*!< 0x00000004 */
13441 #define ETH_MACPCSR_RWKPKTEN                          ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Packet Enable */
13442 #define ETH_MACPCSR_MGKPKTEN_Pos                      (1U)
13443 #define ETH_MACPCSR_MGKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_MGKPKTEN_Pos) /*!< 0x00000002 */
13444 #define ETH_MACPCSR_MGKPKTEN                          ETH_MACPCSR_MGKPKTEN_Msk /* Magic Packet Enable */
13445 #define ETH_MACPCSR_PWRDWN_Pos                        (0U)
13446 #define ETH_MACPCSR_PWRDWN_Msk                        (0x1UL << ETH_MACPCSR_PWRDWN_Pos) /*!< 0x00000001 */
13447 #define ETH_MACPCSR_PWRDWN                            ETH_MACPCSR_PWRDWN_Msk   /* Power Down */
13448 
13449 /************ Bit definition for Ethernet MAC Remote Wake-Up Packet Filter Register   ***************/
13450 #define ETH_MACRWKPFR_MACRWKPFR_Pos                   (0U)
13451 #define ETH_MACRWKPFR_MACRWKPFR_Msk                   (0xFFFFFFFFUL << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0xFFFFFFFF */
13452 #define ETH_MACRWKPFR_MACRWKPFR                       ETH_MACRWKPFR_MACRWKPFR_Msk  /* Wake-up Packet filter register data */
13453 
13454 /************ Bit definition for Ethernet MAC LPI Control Status Register   ***************/
13455 #define ETH_MACLCSR_LPITCSE_Pos                       (21U)
13456 #define ETH_MACLCSR_LPITCSE_Msk                       (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */
13457 #define ETH_MACLCSR_LPITCSE                           ETH_MACLCSR_LPITCSE_Msk  /* LPI Tx Clock Stop Enable */
13458 #define ETH_MACLCSR_LPITE_Pos                         (20U)
13459 #define ETH_MACLCSR_LPITE_Msk                         (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */
13460 #define ETH_MACLCSR_LPITE                             ETH_MACLCSR_LPITE_Msk    /* LPI Timer Enable */
13461 #define ETH_MACLCSR_LPITXA_Pos                        (19U)
13462 #define ETH_MACLCSR_LPITXA_Msk                        (0x1UL << ETH_MACLCSR_LPITXA_Pos) /*!< 0x00080000 */
13463 #define ETH_MACLCSR_LPITXA                            ETH_MACLCSR_LPITXA_Msk   /* LPI Tx Automate */
13464 #define ETH_MACLCSR_PLSEN_Pos                         (18U)
13465 #define ETH_MACLCSR_PLSEN_Msk                         (0x1UL << ETH_MACLCSR_PLSEN_Pos) /*!< 0x00040000 */
13466 #define ETH_MACLCSR_PLSEN                             ETH_MACLCSR_PLSEN_Msk      /* PHY Link Status Enable */
13467 #define ETH_MACLCSR_PLS_Pos                           (17U)
13468 #define ETH_MACLCSR_PLS_Msk                           (0x1UL << ETH_MACLCSR_PLS_Pos) /*!< 0x00020000 */
13469 #define ETH_MACLCSR_PLS                               ETH_MACLCSR_PLS_Msk      /* PHY Link Status */
13470 #define ETH_MACLCSR_LPIEN_Pos                         (16U)
13471 #define ETH_MACLCSR_LPIEN_Msk                         (0x1UL << ETH_MACLCSR_LPIEN_Pos) /*!< 0x00010000 */
13472 #define ETH_MACLCSR_LPIEN                             ETH_MACLCSR_LPIEN_Msk    /* LPI Enable */
13473 #define ETH_MACLCSR_RLPIST_Pos                        (9U)
13474 #define ETH_MACLCSR_RLPIST_Msk                        (0x1UL << ETH_MACLCSR_RLPIST_Pos) /*!< 0x00000200 */
13475 #define ETH_MACLCSR_RLPIST                            ETH_MACLCSR_RLPIST_Msk   /* Receive LPI State */
13476 #define ETH_MACLCSR_TLPIST_Pos                        (8U)
13477 #define ETH_MACLCSR_TLPIST_Msk                        (0x1UL << ETH_MACLCSR_TLPIST_Pos) /*!< 0x00000100 */
13478 #define ETH_MACLCSR_TLPIST                            ETH_MACLCSR_TLPIST_Msk   /* Transmit LPI State */
13479 #define ETH_MACLCSR_RLPIEX_Pos                        (3U)
13480 #define ETH_MACLCSR_RLPIEX_Msk                        (0x1UL << ETH_MACLCSR_RLPIEX_Pos) /*!< 0x00000008 */
13481 #define ETH_MACLCSR_RLPIEX                            ETH_MACLCSR_RLPIEX_Msk   /* Receive LPI Exit */
13482 #define ETH_MACLCSR_RLPIEN_Pos                        (2U)
13483 #define ETH_MACLCSR_RLPIEN_Msk                        (0x1UL << ETH_MACLCSR_RLPIEN_Pos) /*!< 0x00000004 */
13484 #define ETH_MACLCSR_RLPIEN                            ETH_MACLCSR_RLPIEN_Msk   /* Receive LPI Entry */
13485 #define ETH_MACLCSR_TLPIEX_Pos                        (1U)
13486 #define ETH_MACLCSR_TLPIEX_Msk                        (0x1UL << ETH_MACLCSR_TLPIEX_Pos) /*!< 0x00000002 */
13487 #define ETH_MACLCSR_TLPIEX                            ETH_MACLCSR_TLPIEX_Msk   /* Transmit LPI Exit */
13488 #define ETH_MACLCSR_TLPIEN_Pos                        (0U)
13489 #define ETH_MACLCSR_TLPIEN_Msk                        (0x1UL << ETH_MACLCSR_TLPIEN_Pos) /*!< 0x00000001 */
13490 #define ETH_MACLCSR_TLPIEN                            ETH_MACLCSR_TLPIEN_Msk   /* Transmit LPI Entry */
13491 
13492 /************ Bit definition for Ethernet MAC LPI Timers Control Register   ***************/
13493 #define ETH_MACLTCR_LST_Pos                           (16U)
13494 #define ETH_MACLTCR_LST_Msk                           (0x3FFUL << ETH_MACLTCR_LST_Pos) /*!< 0x03FF0000 */
13495 #define ETH_MACLTCR_LST                               ETH_MACLTCR_LST_Msk      /* LPI LS TIMER */
13496 #define ETH_MACLTCR_TWT_Pos                           (0U)
13497 #define ETH_MACLTCR_TWT_Msk                           (0xFFFFUL << ETH_MACLTCR_TWT_Pos) /*!< 0x0000FFFF */
13498 #define ETH_MACLTCR_TWT                               ETH_MACLTCR_TWT_Msk      /* LPI TW TIMER */
13499 
13500 /************ Bit definition for Ethernet MAC LPI Entry Timer Register   ***************/
13501 #define ETH_MACLETR_LPIET_Pos                         (0U)
13502 #define ETH_MACLETR_LPIET_Msk                         (0xFFFFFUL << ETH_MACLETR_LPIET_Pos) /*!< 0x000FFFFF */
13503 #define ETH_MACLETR_LPIET                             ETH_MACLETR_LPIET_Msk    /* LPI Entry Timer */
13504 
13505 /************ Bit definition for Ethernet MAC 1US Tic Counter Register   ***************/
13506 #define ETH_MAC1USTCR_TIC1USCNTR_Pos                  (0U)
13507 #define ETH_MAC1USTCR_TIC1USCNTR_Msk                  (0xFFFUL << ETH_MAC1USTCR_TIC1USCNTR_Pos) /*!< 0x00000FFF */
13508 #define ETH_MAC1USTCR_TIC1USCNTR                      ETH_MAC1USTCR_TIC1USCNTR_Msk /* 1US TIC Counter */
13509 
13510 /************ Bit definition for Ethernet MAC PHYIF control status Register   ***************/
13511 #define ETH_MACPHYCSR_LNKSTS_Pos                      (19U)
13512 #define ETH_MACPHYCSR_LNKSTS_Msk                      (0x1UL << ETH_MACPHYCSR_LNKSTS_Pos) /*!< 0x00080000 */
13513 #define ETH_MACPHYCSR_LNKSTS                          ETH_MACPHYCSR_LNKSTS_Msk  /* Link Status */
13514 #define ETH_MACPHYCSR_LNKSTS_LD                       ((uint32_t)0x00000000)    /* Link down */
13515 #define ETH_MACPHYCSR_LNKSTS_LU_Pos                   (19U)
13516 #define ETH_MACPHYCSR_LNKSTS_LU_Msk                   (0x1UL << ETH_MACPHYCSR_LNKSTS_LU_Pos) /*!< 0x00080000 */
13517 #define ETH_MACPHYCSR_LNKSTS_LU                       ETH_MACPHYCSR_LNKSTS_LU_Msk  /* Link up */
13518 #define ETH_MACPHYCSR_LNKSPEED_Pos                    (17U)
13519 #define ETH_MACPHYCSR_LNKSPEED_Msk                    (0x3UL << ETH_MACPHYCSR_LNKSPEED_Pos) /*!< 0x00060000 */
13520 #define ETH_MACPHYCSR_LNKSPEED                        ETH_MACPHYCSR_LNKSPEED_Msk  /* Link Speed */
13521 #define ETH_MACPHYCSR_LNKSPEED_2_5MHZ                 ((uint32_t)0x00000000)    /* 2.5 MHz */
13522 #define ETH_MACPHYCSR_LNKSPEED_25MHZ_Pos              (17U)
13523 #define ETH_MACPHYCSR_LNKSPEED_25MHZ_Msk              (0x1UL << ETH_MACPHYCSR_LNKSPEED_25MHZ_Pos) /*!< 0x00020000 */
13524 #define ETH_MACPHYCSR_LNKSPEED_25MHZ                  ETH_MACPHYCSR_LNKSPEED_25MHZ_Msk   /* 25 MHz */
13525 #define ETH_MACPHYCSR_LNKSPEED_125MHZ_Pos             (18U)
13526 #define ETH_MACPHYCSR_LNKSPEED_125MHZ_Msk             (0x1UL << ETH_MACPHYCSR_LNKSPEED_125MHZ_Pos) /*!< 0x00040000 */
13527 #define ETH_MACPHYCSR_LNKSPEED_125MHZ                 ETH_MACPHYCSR_LNKSPEED_125MHZ_Msk  /* 125 MHz */
13528 #define ETH_MACPHYCSR_LNKMOD_Pos                      (16U)
13529 #define ETH_MACPHYCSR_LNKMOD_Msk                      (0x1UL << ETH_MACPHYCSR_LNKMOD_Pos) /*!< 0x00080000 */
13530 #define ETH_MACPHYCSR_LNKMOD                          ETH_MACPHYCSR_LNKMOD_Msk  /* Link Mode */
13531 #define ETH_MACPHYCSR_LNKMOD_HD                       ((uint32_t)0x00000000)    /* Half-duplex mode */
13532 #define ETH_MACPHYCSR_LNKMOD_FD_Pos                   (16U)
13533 #define ETH_MACPHYCSR_LNKMOD_FD_Msk                   (0x1UL << ETH_MACPHYCSR_LNKMOD_FD_Pos) /*!< 0x00010000 */
13534 #define ETH_MACPHYCSR_LNKMOD_FD                       ETH_MACPHYCSR_LNKMOD_FD_Msk  /* Full-duplex mode */
13535 #define ETH_MACPHYCSR_LUD_Pos                         (1U)
13536 #define ETH_MACPHYCSR_LUD_Msk                         (0x1UL << ETH_MACPHYCSR_LUD_Pos) /*!< 0x00000002 */
13537 #define ETH_MACPHYCSR_LUD                             ETH_MACPHYCSR_LUD_Msk  /* Link Up or Down */
13538 #define ETH_MACPHYCSR_LUD_LD                          ((uint32_t)0x00000000)    /* Link down */
13539 #define ETH_MACPHYCSR_LUD_LU_Pos                      (1U)
13540 #define ETH_MACPHYCSR_LUD_LU_Msk                      (0x1UL << ETH_MACPHYCSR_LUD_LU_Pos) /*!< 0x00000002 */
13541 #define ETH_MACPHYCSR_LUD_LU                          ETH_MACPHYCSR_LUD_LU_Msk  /* Link up */
13542 #define ETH_MACPHYCSR_TC_Pos                          (0U)
13543 #define ETH_MACPHYCSR_TC_Msk                          (0x1UL << ETH_MACPHYCSR_TC_Pos) /*!< 0x00000001 */
13544 #define ETH_MACPHYCSR_TC                              ETH_MACPHYCSR_TC_Msk  /* Transmit Configuration in RGMII */
13545 
13546 /************ Bit definition for Ethernet MAC Version Register   ***************/
13547 #define ETH_MACVR_USERVER_Pos                         (8U)
13548 #define ETH_MACVR_USERVER_Msk                         (0xFFUL << ETH_MACVR_USERVER_Pos) /*!< 0x0000FF00 */
13549 #define ETH_MACVR_USERVER                             ETH_MACVR_USERVER_Msk    /* User-defined Version */
13550 #define ETH_MACVR_SNPSVER_Pos                         (0U)
13551 #define ETH_MACVR_SNPSVER_Msk                         (0xFFUL << ETH_MACVR_SNPSVER_Pos) /*!< 0x000000FF */
13552 #define ETH_MACVR_SNPSVER                             ETH_MACVR_SNPSVER_Msk    /* Synopsys-defined Version */
13553 
13554 /************ Bit definition for Ethernet MAC Debug Register   ***************/
13555 #define ETH_MACDR_TFCSTS_Pos                          (17U)
13556 #define ETH_MACDR_TFCSTS_Msk                          (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
13557 #define ETH_MACDR_TFCSTS                              ETH_MACDR_TFCSTS_Msk     /* MAC Transmit Packet Controller Status */
13558 #define ETH_MACDR_TFCSTS_IDLE                         ((uint32_t)0x00000000)   /* Idle state */
13559 #define ETH_MACDR_TFCSTS_WAIT_Pos                     (17U)
13560 #define ETH_MACDR_TFCSTS_WAIT_Msk                     (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
13561 #define ETH_MACDR_TFCSTS_WAIT                         ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
13562 #define ETH_MACDR_TFCSTS_GENERATEPCP_Pos              (18U)
13563 #define ETH_MACDR_TFCSTS_GENERATEPCP_Msk              (0x1UL << ETH_MACDR_TFCSTS_GENERATEPCP_Pos) /*!< 0x00040000 */
13564 #define ETH_MACDR_TFCSTS_GENERATEPCP                  ETH_MACDR_TFCSTS_GENERATEPCP_Msk /* Generating and transmitting a Pause control packet */
13565 #define ETH_MACDR_TFCSTS_TRASFERIP_Pos                (17U)
13566 #define ETH_MACDR_TFCSTS_TRASFERIP_Msk                (0x3UL << ETH_MACDR_TFCSTS_TRASFERIP_Pos) /*!< 0x00060000 */
13567 #define ETH_MACDR_TFCSTS_TRASFERIP                    ETH_MACDR_TFCSTS_TRASFERIP_Msk /* Transferring input packet for transmission */
13568 #define ETH_MACDR_TPESTS_Pos                          (16U)
13569 #define ETH_MACDR_TPESTS_Msk                          (0x1UL << ETH_MACDR_TPESTS_Pos) /*!< 0x00010000 */
13570 #define ETH_MACDR_TPESTS                              ETH_MACDR_TPESTS_Msk     /* MAC Receive Packet Controller FIFO Status */
13571 #define ETH_MACDR_RFCFCSTS_Pos                        (1U)
13572 #define ETH_MACDR_RFCFCSTS_Msk                        (0x3UL << ETH_MACDR_RFCFCSTS_Pos) /*!< 0x00000006 */
13573 #define ETH_MACDR_RFCFCSTS                            ETH_MACDR_RFCFCSTS_Msk   /* MAC MII Transmit Protocol Engine Status */
13574 #define ETH_MACDR_RPESTS_Pos                          (0U)
13575 #define ETH_MACDR_RPESTS_Msk                          (0x1UL << ETH_MACDR_RPESTS_Pos) /*!< 0x00000001 */
13576 #define ETH_MACDR_RPESTS                              ETH_MACDR_RPESTS_Msk     /* MAC MII Receive Protocol Engine Status */
13577 
13578 /************ Bit definition for Ethernet MAC HW Feature 0 Register   ***************/
13579 #define ETH_MACHWF0R_ACTPHYSEL_Pos                    (28U)
13580 #define ETH_MACHWF0R_ACTPHYSEL_Msk                    (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
13581 #define ETH_MACHWF0R_ACTPHYSEL                        ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
13582 #define ETH_MACHWF0R_ACTPHYSEL_MII                    ((uint32_t)0x00000000)   /* MII */
13583 #define ETH_MACHWF0R_ACTPHYSEL_RGMII_Pos              (28U)
13584 #define ETH_MACHWF0R_ACTPHYSEL_RGMII_Msk              (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RGMII_Pos) /*!< 0x10000000 */
13585 #define ETH_MACHWF0R_ACTPHYSEL_RGMII                  ETH_MACHWF0R_ACTPHYSEL_RGMII_Msk /* RGMII */
13586 #define ETH_MACHWF0R_ACTPHYSEL_SGMII_Pos              (29U)
13587 #define ETH_MACHWF0R_ACTPHYSEL_SGMII_Msk              (0x1UL << ETH_MACHWF0R_ACTPHYSEL_SGMII_Pos) /*!< 0x20000000 */
13588 #define ETH_MACHWF0R_ACTPHYSEL_SGMII                  ETH_MACHWF0R_ACTPHYSEL_SGMII_Msk /* SGMII */
13589 #define ETH_MACHWF0R_ACTPHYSEL_TBI_Pos                (28U)
13590 #define ETH_MACHWF0R_ACTPHYSEL_TBI_Msk                (0x3UL << ETH_MACHWF0R_ACTPHYSEL_TBI_Pos) /*!< 0x30000000 */
13591 #define ETH_MACHWF0R_ACTPHYSEL_TBI                    ETH_MACHWF0R_ACTPHYSEL_TBI_Msk /* TBI */
13592 #define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos               (30U)
13593 #define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk               (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
13594 #define ETH_MACHWF0R_ACTPHYSEL_RMII                   ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
13595 #define ETH_MACHWF0R_ACTPHYSEL_RTBI_Pos               (28U)
13596 #define ETH_MACHWF0R_ACTPHYSEL_RTBI_Msk               (0x5UL << ETH_MACHWF0R_ACTPHYSEL_RTBI_Pos) /*!< 0x50000000 */
13597 #define ETH_MACHWF0R_ACTPHYSEL_RTBI                   ETH_MACHWF0R_ACTPHYSEL_RTBI_Msk /* RTBI */
13598 #define ETH_MACHWF0R_ACTPHYSEL_SMII_Pos               (29U)
13599 #define ETH_MACHWF0R_ACTPHYSEL_SMII_Msk               (0x3UL << ETH_MACHWF0R_ACTPHYSEL_SMII_Pos) /*!< 0x60000000 */
13600 #define ETH_MACHWF0R_ACTPHYSEL_SMII                   ETH_MACHWF0R_ACTPHYSEL_SGMII_Msk /* SMII */
13601 #define ETH_MACHWF0R_SAVLANINS_Pos                    (27U)
13602 #define ETH_MACHWF0R_SAVLANINS_Msk                    (0x1UL << ETH_MACHWF0R_SAVLANINS_Pos) /*!< 0x08000000 */
13603 #define ETH_MACHWF0R_SAVLANINS                        ETH_MACHWF0R_SAVLANINS_Msk /* Source Address or VLAN Insertion Enable */
13604 #define ETH_MACHWF0R_TSSTSSEL_Pos                     (25U)
13605 #define ETH_MACHWF0R_TSSTSSEL_Msk                     (0x3UL << ETH_MACHWF0R_TSSTSSEL_Pos) /*!< 0x06000000 */
13606 #define ETH_MACHWF0R_TSSTSSEL                         ETH_MACHWF0R_TSSTSSEL_Msk /* Timestamp System Time Source */
13607 #define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos            (25U)
13608 #define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos) /*!< 0x02000000 */
13609 #define ETH_MACHWF0R_TSSTSSEL_INTERNAL                ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk /* Timestamp System Time Source: Internal */
13610 #define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos            (26U)
13611 #define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos) /*!< 0x04000000 */
13612 #define ETH_MACHWF0R_TSSTSSEL_EXTERNAL                ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk /* Timestamp System Time Source: External */
13613 #define ETH_MACHWF0R_TSSTSSEL_BOTH_Pos                (25U)
13614 #define ETH_MACHWF0R_TSSTSSEL_BOTH_Msk                (0x3UL << ETH_MACHWF0R_TSSTSSEL_BOTH_Pos) /*!< 0x06000000 */
13615 #define ETH_MACHWF0R_TSSTSSEL_BOTH                    ETH_MACHWF0R_TSSTSSEL_BOTH_Msk /* Timestamp System Time Source: Internal & External */
13616 #define ETH_MACHWF0R_MACADR64SEL_Pos                  (24U)
13617 #define ETH_MACHWF0R_MACADR64SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR64SEL_Pos) /*!< 0x01000000 */
13618 #define ETH_MACHWF0R_MACADR64SEL                      ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64-127 Selected */
13619 #define ETH_MACHWF0R_MACADR32SEL_Pos                  (23U)
13620 #define ETH_MACHWF0R_MACADR32SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR32SEL_Pos) /*!< 0x00800000 */
13621 #define ETH_MACHWF0R_MACADR32SEL                      ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32-63 Selected */
13622 #define ETH_MACHWF0R_ADDMACADRSEL_Pos                 (18U)
13623 #define ETH_MACHWF0R_ADDMACADRSEL_Msk                 (0x1FUL << ETH_MACHWF0R_ADDMACADRSEL_Pos) /*!< 0x007C0000 */
13624 #define ETH_MACHWF0R_ADDMACADRSEL                     ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1- 31 Selected */
13625 #define ETH_MACHWF0R_RXCOESEL_Pos                     (16U)
13626 #define ETH_MACHWF0R_RXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_RXCOESEL_Pos) /*!< 0x00010000 */
13627 #define ETH_MACHWF0R_RXCOESEL                         ETH_MACHWF0R_RXCOESEL_Msk /* Receive Checksum Offload Enabled */
13628 #define ETH_MACHWF0R_TXCOESEL_Pos                     (14U)
13629 #define ETH_MACHWF0R_TXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_TXCOESEL_Pos) /*!< 0x00004000 */
13630 #define ETH_MACHWF0R_TXCOESEL                         ETH_MACHWF0R_TXCOESEL_Msk /* Transmit Checksum Offload Enabled */
13631 #define ETH_MACHWF0R_EEESEL_Pos                       (13U)
13632 #define ETH_MACHWF0R_EEESEL_Msk                       (0x1UL << ETH_MACHWF0R_EEESEL_Pos) /*!< 0x00002000 */
13633 #define ETH_MACHWF0R_EEESEL                           ETH_MACHWF0R_EEESEL_Msk  /* Energy Efficient Ethernet Enabled */
13634 #define ETH_MACHWF0R_TSSEL_Pos                        (12U)
13635 #define ETH_MACHWF0R_TSSEL_Msk                        (0x1UL << ETH_MACHWF0R_TSSEL_Pos) /*!< 0x00001000 */
13636 #define ETH_MACHWF0R_TSSEL                            ETH_MACHWF0R_TSSEL_Msk   /* IEEE 1588-2008 Timestamp Enabled */
13637 #define ETH_MACHWF0R_ARPOFFSEL_Pos                    (9U)
13638 #define ETH_MACHWF0R_ARPOFFSEL_Msk                    (0x1UL << ETH_MACHWF0R_ARPOFFSEL_Pos) /*!< 0x00000200 */
13639 #define ETH_MACHWF0R_ARPOFFSEL                        ETH_MACHWF0R_ARPOFFSEL_Msk /* ARP Offload Enabled */
13640 #define ETH_MACHWF0R_MMCSEL_Pos                       (8U)
13641 #define ETH_MACHWF0R_MMCSEL_Msk                       (0x1UL << ETH_MACHWF0R_MMCSEL_Pos) /*!< 0x00000100 */
13642 #define ETH_MACHWF0R_MMCSEL                           ETH_MACHWF0R_MMCSEL_Msk  /* RMON Module Enable */
13643 #define ETH_MACHWF0R_MGKSEL_Pos                       (7U)
13644 #define ETH_MACHWF0R_MGKSEL_Msk                       (0x1UL << ETH_MACHWF0R_MGKSEL_Pos) /*!< 0x00000080 */
13645 #define ETH_MACHWF0R_MGKSEL                           ETH_MACHWF0R_MGKSEL_Msk  /* PMT Magic Packet Enable */
13646 #define ETH_MACHWF0R_RWKSEL_Pos                       (6U)
13647 #define ETH_MACHWF0R_RWKSEL_Msk                       (0x1UL << ETH_MACHWF0R_RWKSEL_Pos) /*!< 0x00000040 */
13648 #define ETH_MACHWF0R_RWKSEL                           ETH_MACHWF0R_RWKSEL_Msk  /* PMT Remote Wake-up Packet Enable */
13649 #define ETH_MACHWF0R_SMASEL_Pos                       (5U)
13650 #define ETH_MACHWF0R_SMASEL_Msk                       (0x1UL << ETH_MACHWF0R_SMASEL_Pos) /*!< 0x00000020 */
13651 #define ETH_MACHWF0R_SMASEL                           ETH_MACHWF0R_SMASEL_Msk  /* SMA (MDIO) Interface */
13652 #define ETH_MACHWF0R_VLHASH_Pos                       (4U)
13653 #define ETH_MACHWF0R_VLHASH_Msk                       (0x1UL << ETH_MACHWF0R_VLHASH_Pos) /*!< 0x00000010 */
13654 #define ETH_MACHWF0R_VLHASH                           ETH_MACHWF0R_VLHASH_Msk  /* VLAN Hash Filter Selected */
13655 #define ETH_MACHWF0R_PCSSEL_Pos                       (3U)
13656 #define ETH_MACHWF0R_PCSSEL_Msk                       (0x1UL << ETH_MACHWF0R_PCSSEL_Pos) /*!< 0x00000008 */
13657 #define ETH_MACHWF0R_PCSSEL                           ETH_MACHWF0R_PCSSEL_Msk  /* PCS Registers (TBI, SGMII, or RTBI PHY interface) */
13658 #define ETH_MACHWF0R_HDSEL_Pos                        (2U)
13659 #define ETH_MACHWF0R_HDSEL_Msk                        (0x1UL << ETH_MACHWF0R_HDSEL_Pos) /*!< 0x00000004 */
13660 #define ETH_MACHWF0R_HDSEL                            ETH_MACHWF0R_HDSEL_Msk   /* Half-duplex Support */
13661 #define ETH_MACHWF0R_GMIISEL_Pos                      (1U)
13662 #define ETH_MACHWF0R_GMIISEL_Msk                      (0x1UL << ETH_MACHWF0R_GMIISEL_Pos) /*!< 0x00000002 */
13663 #define ETH_MACHWF0R_GMIISEL                          ETH_MACHWF0R_GMIISEL_Msk /* 1000 Mbps Support */
13664 #define ETH_MACHWF0R_MIISEL_Pos                       (0U)
13665 #define ETH_MACHWF0R_MIISEL_Msk                       (0x1UL << ETH_MACHWF0R_MIISEL_Pos) /*!< 0x00000001 */
13666 #define ETH_MACHWF0R_MIISEL                           ETH_MACHWF0R_MIISEL_Msk  /* 10 or 100 Mbps Support */
13667 
13668 /************ Bit definition for Ethernet MAC HW Feature 1 Register   ***************/
13669 #define ETH_MACHWF1R_L3L4FNUM_Pos                     (27U)
13670 #define ETH_MACHWF1R_L3L4FNUM_Msk                     (0xFUL << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x78000000 */
13671 #define ETH_MACHWF1R_L3L4FNUM                         ETH_MACHWF1R_L3L4FNUM_Msk /* Total number of L3 or L4 Filters */
13672 #define ETH_MACHWF1R_HASHTBLSZ_Pos                    (24U)
13673 #define ETH_MACHWF1R_HASHTBLSZ_Msk                    (0x3UL << ETH_MACHWF1R_HASHTBLSZ_Pos) /*!< 0x03000000 */
13674 #define ETH_MACHWF1R_HASHTBLSZ                        ETH_MACHWF1R_HASHTBLSZ_Msk /* Hash Table Size */
13675 #define ETH_MACHWF1R_HASHTBLSZ_NOHASH                 ((uint32_t)0x00000000)   /* No Hash table */
13676 #define ETH_MACHWF1R_HASHTBLSZ_64_Pos                 (24U)
13677 #define ETH_MACHWF1R_HASHTBLSZ_64_Msk                 (0x1UL << ETH_MACHWF1R_HASHTBLSZ_64_Pos) /*!< 0x03000000 */
13678 #define ETH_MACHWF1R_HASHTBLSZ_64                     ETH_MACHWF1R_HASHTBLSZ_64_Msk /* 64 */
13679 #define ETH_MACHWF1R_HASHTBLSZ_128_Pos                (25U)
13680 #define ETH_MACHWF1R_HASHTBLSZ_128_Msk                (0x1UL << ETH_MACHWF1R_HASHTBLSZ_128_Pos) /*!< 0x03000000 */
13681 #define ETH_MACHWF1R_HASHTBLSZ_128                    ETH_MACHWF1R_HASHTBLSZ_128_Msk /* 128 */
13682 #define ETH_MACHWF1R_HASHTBLSZ_256_Pos                (24U)
13683 #define ETH_MACHWF1R_HASHTBLSZ_256_Msk                (0x3UL << ETH_MACHWF1R_HASHTBLSZ_256_Pos) /*!< 0x03000000 */
13684 #define ETH_MACHWF1R_HASHTBLSZ_256                    ETH_MACHWF1R_HASHTBLSZ_256_Msk /* 256 */
13685 #define ETH_MACHWF1R_POUOST_Pos                       (23U)
13686 #define ETH_MACHWF1R_POUOST_Msk                       (0x1UL << ETH_MACHWF1R_POUOST_Pos) /*!< 0x00100000 */
13687 #define ETH_MACHWF1R_POUOST                           ETH_MACHWF1R_POUOST_Msk   /* One Step for PTP over UDP/IP Feature Enable */
13688 #define ETH_MACHWF1R_RAVSEL_Pos                       (21U)
13689 #define ETH_MACHWF1R_RAVSEL_Msk                       (0x1UL << ETH_MACHWF1R_RAVSEL_Pos) /*!< 0x00100000 */
13690 #define ETH_MACHWF1R_RAVSEL                           ETH_MACHWF1R_RAVSEL_Msk   /* Rx Side Only AV Feature Enable */
13691 #define ETH_MACHWF1R_AVSEL_Pos                        (20U)
13692 #define ETH_MACHWF1R_AVSEL_Msk                        (0x1UL << ETH_MACHWF1R_AVSEL_Pos) /*!< 0x00100000 */
13693 #define ETH_MACHWF1R_AVSEL                            ETH_MACHWF1R_AVSEL_Msk   /* AV Feature Enabled */
13694 #define ETH_MACHWF1R_DBGMEMA_Pos                      (19U)
13695 #define ETH_MACHWF1R_DBGMEMA_Msk                      (0x1UL << ETH_MACHWF1R_DBGMEMA_Pos) /*!< 0x00080000 */
13696 #define ETH_MACHWF1R_DBGMEMA                          ETH_MACHWF1R_DBGMEMA_Msk /* Debug Memory Interface Enabled */
13697 #define ETH_MACHWF1R_TSOEN_Pos                        (18U)
13698 #define ETH_MACHWF1R_TSOEN_Msk                        (0x1UL << ETH_MACHWF1R_TSOEN_Pos) /*!< 0x00040000 */
13699 #define ETH_MACHWF1R_TSOEN                            ETH_MACHWF1R_TSOEN_Msk   /* TCP Segmentation Offload Enable */
13700 #define ETH_MACHWF1R_SPHEN_Pos                        (17U)
13701 #define ETH_MACHWF1R_SPHEN_Msk                        (0x1UL << ETH_MACHWF1R_SPHEN_Pos) /*!< 0x00020000 */
13702 #define ETH_MACHWF1R_SPHEN                            ETH_MACHWF1R_SPHEN_Msk   /* Split Header Feature Enable */
13703 #define ETH_MACHWF1R_DCBEN_Pos                        (16U)
13704 #define ETH_MACHWF1R_DCBEN_Msk                        (0x1UL << ETH_MACHWF1R_DCBEN_Pos) /*!< 0x00010000 */
13705 #define ETH_MACHWF1R_DCBEN                            ETH_MACHWF1R_DCBEN_Msk   /* DCB Feature Enable */
13706 #define ETH_MACHWF1R_ADDR64_Pos                       (14U)
13707 #define ETH_MACHWF1R_ADDR64_Msk                       (0x3UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x0000C000 */
13708 #define ETH_MACHWF1R_ADDR64                           ETH_MACHWF1R_ADDR64_Msk  /* Address Width */
13709 #define ETH_MACHWF1R_ADDR64_32                        (0x0UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00000000 */
13710 #define ETH_MACHWF1R_ADDR64_40                        (0x1UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00004000 */
13711 #define ETH_MACHWF1R_ADDR64_48                        (0x2UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00008000 */
13712 #define ETH_MACHWF1R_ADVTHWORD_Pos                    (13U)
13713 #define ETH_MACHWF1R_ADVTHWORD_Msk                    (0x1UL << ETH_MACHWF1R_ADVTHWORD_Pos) /*!< 0x00002000 */
13714 #define ETH_MACHWF1R_ADVTHWORD                        ETH_MACHWF1R_ADVTHWORD_Msk /* IEEE 1588 High Word Register Enable */
13715 #define ETH_MACHWF1R_PTOEN_Pos                        (12U)
13716 #define ETH_MACHWF1R_PTOEN_Msk                        (0x1UL << ETH_MACHWF1R_PTOEN_Pos) /*!< 0x00001000 */
13717 #define ETH_MACHWF1R_PTOEN                            ETH_MACHWF1R_PTOEN_Msk   /* PTP Offload Enable */
13718 #define ETH_MACHWF1R_OSTEN_Pos                        (11U)
13719 #define ETH_MACHWF1R_OSTEN_Msk                        (0x1UL << ETH_MACHWF1R_OSTEN_Pos) /*!< 0x00000800 */
13720 #define ETH_MACHWF1R_OSTEN                            ETH_MACHWF1R_OSTEN_Msk   /* One-Step Timestamping Enable */
13721 #define ETH_MACHWF1R_TXFIFOSIZE_Pos                   (6U)
13722 #define ETH_MACHWF1R_TXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x000007C0 */
13723 #define ETH_MACHWF1R_TXFIFOSIZE                       ETH_MACHWF1R_TXFIFOSIZE_Msk /* MTL Transmit FIFO Size */
13724 #define ETH_MACHWF1R_SPRAM_Pos                        (5U)
13725 #define ETH_MACHWF1R_SPRAM_Msk                        (0x1FUL << ETH_MACHWF1R_SPRAM_Pos) /*!< 0x00000020 */
13726 #define ETH_MACHWF1R_SPRAM                            ETH_MACHWF1R_SPRAM_Msk /* MTL Receive FIFO Size */
13727 #define ETH_MACHWF1R_RXFIFOSIZE_Pos                   (0U)
13728 #define ETH_MACHWF1R_RXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x0000001F */
13729 #define ETH_MACHWF1R_RXFIFOSIZE                       ETH_MACHWF1R_RXFIFOSIZE_Msk /* MTL Receive FIFO Size */
13730 
13731 /************ Bit definition for Ethernet MAC HW Feature 2 Register   ***************/
13732 #define ETH_MACHWF2R_AUXSNAPNUM_Pos                   (28U)
13733 #define ETH_MACHWF2R_AUXSNAPNUM_Msk                   (0x7UL << ETH_MACHWF2R_AUXSNAPNUM_Pos) /*!< 0x70000000 */
13734 #define ETH_MACHWF2R_AUXSNAPNUM                       ETH_MACHWF2R_AUXSNAPNUM_Msk /* Number of Auxiliary Snapshot Inputs */
13735 #define ETH_MACHWF2R_PPSOUTNUM_Pos                    (24U)
13736 #define ETH_MACHWF2R_PPSOUTNUM_Msk                    (0x7UL << ETH_MACHWF2R_PPSOUTNUM_Pos) /*!< 0x07000000 */
13737 #define ETH_MACHWF2R_PPSOUTNUM                        ETH_MACHWF2R_PPSOUTNUM_Msk /*  Number of PPS Outputs */
13738 #define ETH_MACHWF2R_TDCSZ_Pos                        (22U)
13739 #define ETH_MACHWF2R_TDCSZ_Msk                        (0x3UL << ETH_MACHWF2R_TDCSZ_Pos) /*!< 0x00C00000 */
13740 #define ETH_MACHWF2R_TDCSZ                            ETH_MACHWF2R_TDCSZ_Msk /* Tx DMA Descriptor Cache Size in terms of 16-byte descriptors */
13741 #define ETH_MACHWF2R_TXCHCNT_Pos                      (18U)
13742 #define ETH_MACHWF2R_TXCHCNT_Msk                      (0xFUL << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x003C0000 */
13743 #define ETH_MACHWF2R_TXCHCNT                          ETH_MACHWF2R_TXCHCNT_Msk /* Number of DMA Transmit Channels */
13744 #define ETH_MACHWF2R_TXCHCNT_1DMATXCH                 ((uint32_t)0x00000000) /* 1 DMA Tx Channel */
13745 #define ETH_MACHWF2R_TXCHCNT_2DMATXCH_Pos             (18U)
13746 #define ETH_MACHWF2R_TXCHCNT_2DMATXCH_Msk             (0x1UL << ETH_MACHWF2R_TXCHCNT_2DMATXCH_Pos) /*!< 0x00040000 */
13747 #define ETH_MACHWF2R_TXCHCNT_2DMATXCH                 ETH_MACHWF2R_TXCHCNT_2DMATXCH_Msk  /* 2 DMA Tx Channels */
13748 #define ETH_MACHWF2R_RDCSZ_Pos                        (16U)
13749 #define ETH_MACHWF2R_RDCSZ_Msk                        (0x3UL << ETH_MACHWF2R_RDCSZ_Pos) /*!< 0x00C00000 */
13750 #define ETH_MACHWF2R_RDCSZ                            ETH_MACHWF2R_RDCSZ_Msk /* Rx DMA Descriptor Cache Size in terms of 16-byte descriptors */
13751 #define ETH_MACHWF2R_RXCHCNT_Pos                      (12U)
13752 #define ETH_MACHWF2R_RXCHCNT_Msk                      (0xFUL << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x0000F000 */
13753 #define ETH_MACHWF2R_RXCHCNT                          ETH_MACHWF2R_RXCHCNT_Msk /* Number of DMA Receive Channels */
13754 #define ETH_MACHWF2R_RXCHCNT_1DMARXCH                 ((uint32_t)0x00000000) /* 1 DMA Rx Channel */
13755 #define ETH_MACHWF2R_RXCHCNT_2DMARXCH_Pos             (12U)
13756 #define ETH_MACHWF2R_RXCHCNT_2DMARXCH_Msk             (0x1UL << ETH_MACHWF2R_RXCHCNT_2DMARXCH_Pos) /*!< 0x00040000 */
13757 #define ETH_MACHWF2R_RXCHCNT_2DMARXCH                 ETH_MACHWF2R_RXCHCNT_2DMARXCH_Msk  /* 2 DMA Rx Channels */
13758 #define ETH_MACHWF2R_TXQCNT_Pos                       (6U)
13759 #define ETH_MACHWF2R_TXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x000003C0 */
13760 #define ETH_MACHWF2R_TXQCNT                           ETH_MACHWF2R_TXQCNT_Msk  /* Number of MTL Transmit Queues */
13761 #define ETH_MACHWF2R_TXQCNT_1MTLTXQ                   ((uint32_t)0x00000000) /* 1 MTL Tx queue */
13762 #define ETH_MACHWF2R_TXQCNT_2MTLTXQ_Pos               (6U)
13763 #define ETH_MACHWF2R_TXQCNT_2MTLTXQ_Msk               (0x1UL << ETH_MACHWF2R_TXQCNT_2MTLTXQ_Pos) /*!< 0x00000040 */
13764 #define ETH_MACHWF2R_TXQCNT_2MTLTXQ                   ETH_MACHWF2R_TXQCNT_2MTLTXQ_Msk  /* 2 MTL Tx queue */
13765 #define ETH_MACHWF2R_RXQCNT_Pos                       (0U)
13766 #define ETH_MACHWF2R_RXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x0000000F */
13767 #define ETH_MACHWF2R_RXQCNT                           ETH_MACHWF2R_RXQCNT_Msk  /* Number of MTL Receive Queues */
13768 #define ETH_MACHWF2R_RXQCNT_1MTLRXQ                   ((uint32_t)0x00000000) /* 1 MTL Rx queue */
13769 #define ETH_MACHWF2R_RXQCNT_2MTLRXQ_Pos               (0U)
13770 #define ETH_MACHWF2R_RXQCNT_2MTLRXQ_Msk               (0x1UL << ETH_MACHWF2R_RXQCNT_2MTLRXQ_Pos) /*!< 0x00000001 */
13771 #define ETH_MACHWF2R_RXQCNT_2MTLRXQ                   ETH_MACHWF2R_RXQCNT_2MTLRXQ_Msk  /* 2 MTL Rx queue */
13772 
13773 /************ Bit definition for Ethernet MAC HW Feature 3 Register    ***************/
13774 #define ETH_MACHWF3R_ASP_Pos                          (28U)
13775 #define ETH_MACHWF3R_ASP_Msk                          (0x3UL << ETH_MACHWF3R_ASP_Pos) /*!< 0x30000000 */
13776 #define ETH_MACHWF3R_ASP                              ETH_MACHWF3R_ASP_Msk /* Automotive Safety Package */
13777 #define ETH_MACHWF3R_ASP_NONE                         ((uint32_t)0x00000000) /* None */
13778 #define ETH_MACHWF3R_ASP_ECC_Pos                      (28U)
13779 #define ETH_MACHWF3R_ASP_ECC_Msk                      (0x1UL << ETH_MACHWF3R_ASP_ECC_Pos) /*!< 0x10000000 */
13780 #define ETH_MACHWF3R_ASP_ECC                          ETH_MACHWF3R_ASP_ECC_Msk  /* ECC only */
13781 #define ETH_MACHWF3R_ASP_ASNPPE_Pos                   (29U)
13782 #define ETH_MACHWF3R_ASP_ASNPPE_Msk                   (0x1UL << ETH_MACHWF3R_ASP_ASNPPE_Pos) /*!< 0x20000000 */
13783 #define ETH_MACHWF3R_ASP_ASNPPE                       ETH_MACHWF3R_ASP_ASNPPE_Msk  /* AS_NPPE */
13784 #define ETH_MACHWF3R_ASP_ASPPE_Pos                    (28U)
13785 #define ETH_MACHWF3R_ASP_ASPPE_Msk                    (0x3UL << ETH_MACHWF3R_ASP_ASPPE_Pos) /*!< 0x30000000 */
13786 #define ETH_MACHWF3R_ASP_ASPPE                        ETH_MACHWF3R_ASP_ASPPE_Msk  /* AS_PPE */
13787 #define ETH_MACHWF3R_TBSSEL_Pos                       (27U)
13788 #define ETH_MACHWF3R_TBSSEL_Msk                       (0x1UL << ETH_MACHWF3R_TBSSEL_Pos) /*!< 0x08000000 */
13789 #define ETH_MACHWF3R_TBSSEL                           ETH_MACHWF3R_TBSSEL_Msk /* Time-based scheduling Enable */
13790 #define ETH_MACHWF3R_FPESEL_Pos                       (26U)
13791 #define ETH_MACHWF3R_FPESEL_Msk                       (0x1UL << ETH_MACHWF3R_FPESEL_Pos) /*!< 0x04000000 */
13792 #define ETH_MACHWF3R_FPESEL                           ETH_MACHWF3R_FPESEL_Msk /* Frame Preemption Enable */
13793 #define ETH_MACHWF3R_ESTWID_Pos                       (20U)
13794 #define ETH_MACHWF3R_ESTWID_Msk                       (0x3UL << ETH_MACHWF3R_ESTWID_Pos) /*!< 0x00300000 */
13795 #define ETH_MACHWF3R_ESTWID                           ETH_MACHWF3R_ESTWID_Msk /* Width of the Time Interval field in the Gate Control List */
13796 #define ETH_MACHWF3R_ESTWID_NOWIDTH                   ((uint32_t)0x00000000) /* No Width */
13797 #define ETH_MACHWF3R_ESTWID_16_Pos                    (20U)
13798 #define ETH_MACHWF3R_ESTWID_16_Msk                    (0x1UL << ETH_MACHWF3R_ESTWID_16_Pos) /*!< 0x00100000 */
13799 #define ETH_MACHWF3R_ESTWID_16                        ETH_MACHWF3R_ESTWID_16_Msk  /* 16 Width */
13800 #define ETH_MACHWF3R_ESTWID_20_Pos                    (21U)
13801 #define ETH_MACHWF3R_ESTWID_20_Msk                    (0x1UL << ETH_MACHWF3R_ESTWID_20_Pos) /*!< 0x00200000 */
13802 #define ETH_MACHWF3R_ESTWID_20                        ETH_MACHWF3R_ESTWID_20_Msk  /* 20 Width */
13803 #define ETH_MACHWF3R_ESTWID_24_Pos                    (20U)
13804 #define ETH_MACHWF3R_ESTWID_24_Msk                    (0x3UL << ETH_MACHWF3R_ESTWID_24_Pos) /*!< 0x00300000 */
13805 #define ETH_MACHWF3R_ESTWID_24                        ETH_MACHWF3R_ESTWID_24_Msk  /* 24 Width */
13806 #define ETH_MACHWF3R_ESTDEP_Pos                       (17U)
13807 #define ETH_MACHWF3R_ESTDEP_Msk                       (0x7UL << ETH_MACHWF3R_ESTDEP_Pos) /*!< 0x000E0000 */
13808 #define ETH_MACHWF3R_ESTDEP                           ETH_MACHWF3R_ESTDEP_Msk /* Depth of the Gate Control List */
13809 #define ETH_MACHWF3R_ESTDEP_NODEPTH                   ((uint32_t)0x00000000) /* No depth */
13810 #define ETH_MACHWF3R_ESTDEP_64_Pos                    (17U)
13811 #define ETH_MACHWF3R_ESTDEP_64_Msk                    (0x1UL << ETH_MACHWF3R_ESTDEP_64_Pos) /*!< 0x00020000 */
13812 #define ETH_MACHWF3R_ESTDEP_64                        ETH_MACHWF3R_ESTDEP_64_Msk  /* 64 depth */
13813 #define ETH_MACHWF3R_ESTDEP_128_Pos                   (18U)
13814 #define ETH_MACHWF3R_ESTDEP_128_Msk                   (0x1UL << ETH_MACHWF3R_ESTDEP_128_Pos) /*!< 0x00040000 */
13815 #define ETH_MACHWF3R_ESTDEP_128                       ETH_MACHWF3R_ESTDEP_128_Msk  /* 128 depth */
13816 #define ETH_MACHWF3R_ESTDEP_256_Pos                   (17U)
13817 #define ETH_MACHWF3R_ESTDEP_256_Msk                   (0x3UL << ETH_MACHWF3R_ESTDEP_256_Pos) /*!< 0x00060000 */
13818 #define ETH_MACHWF3R_ESTDEP_256                       ETH_MACHWF3R_ESTDEP_256_Msk  /* 256 depth */
13819 #define ETH_MACHWF3R_ESTDEP_512_Pos                   (19U)
13820 #define ETH_MACHWF3R_ESTDEP_512_Msk                   (0x1UL << ETH_MACHWF3R_ESTDEP_512_Pos) /*!< 0x00080000 */
13821 #define ETH_MACHWF3R_ESTDEP_512                       ETH_MACHWF3R_ESTDEP_512_Msk  /* 512 depth */
13822 #define ETH_MACHWF3R_ESTDEP_1024_Pos                  (17U)
13823 #define ETH_MACHWF3R_ESTDEP_1024_Msk                  (0x5UL << ETH_MACHWF3R_ESTDEP_1024_Pos) /*!< 0x000A0000 */
13824 #define ETH_MACHWF3R_ESTDEP_1024                      ETH_MACHWF3R_ESTDEP_1024_Msk  /* 1024 depth */
13825 #define ETH_MACHWF3R_ESTSEL_Pos                       (16U)
13826 #define ETH_MACHWF3R_ESTSEL_Msk                       (0x1UL << ETH_MACHWF3R_ESTSEL_Pos) /*!< 0x00010000 */
13827 #define ETH_MACHWF3R_ESTSEL                           ETH_MACHWF3R_ESTSEL_Msk  /* Enhancements to Scheduled Traffic Enable */
13828 #define ETH_MACHWF3R_FRPES_Pos                        (13U)
13829 #define ETH_MACHWF3R_FRPES_Msk                        (0x3UL << ETH_MACHWF3R_FRPES_Pos) /*!< 0x00006000 */
13830 #define ETH_MACHWF3R_FRPES                            ETH_MACHWF3R_FRPES_Msk  /* Flexible Receive Parser Table Entries size */
13831 #define ETH_MACHWF3R_FRPES_64                         ((uint32_t)0x00000000) /* 64 entries */
13832 #define ETH_MACHWF3R_FRPES_128_Pos                    (13U)
13833 #define ETH_MACHWF3R_FRPES_128_Msk                    (0x1UL << ETH_MACHWF3R_FRPES_128_Pos) /*!< 0x00002000 */
13834 #define ETH_MACHWF3R_FRPES_128                        ETH_MACHWF3R_FRPES_128_Msk  /* 128 entries */
13835 #define ETH_MACHWF3R_FRPES_256_Pos                    (14U)
13836 #define ETH_MACHWF3R_FRPES_256_Msk                    (0x1UL << ETH_MACHWF3R_FRPES_256_Pos) /*!< 0x00004000 */
13837 #define ETH_MACHWF3R_FRPES_256                        ETH_MACHWF3R_FRPES_256_Msk  /* 256 entries */
13838 #define ETH_MACHWF3R_FRPBS_Pos                        (11U)
13839 #define ETH_MACHWF3R_FRPBS_Msk                        (0x3UL << ETH_MACHWF3R_FRPBS_Pos) /*!< 0x00001800 */
13840 #define ETH_MACHWF3R_FRPBS                            ETH_MACHWF3R_FRPBS_Msk  /* Flexible Receive Parser Buffer size */
13841 #define ETH_MACHWF3R_FRPBS_64                         ((uint32_t)0x00000000) /* 64 entries */
13842 #define ETH_MACHWF3R_FRPBS_128_Pos                    (11U)
13843 #define ETH_MACHWF3R_FRPBS_128_Msk                    (0x1UL << ETH_MACHWF3R_FRPBS_128_Pos) /*!< 0x00000100 */
13844 #define ETH_MACHWF3R_FRPBS_128                        ETH_MACHWF3R_FRPBS_128_Msk  /* 128 entries */
13845 #define ETH_MACHWF3R_FRPBS_256_Pos                    (12U)
13846 #define ETH_MACHWF3R_FRPBS_256_Msk                    (0x1UL << ETH_MACHWF3R_FRPBS_256_Pos) /*!< 0x00001000 */
13847 #define ETH_MACHWF3R_FRPBS_256                        ETH_MACHWF3R_FRPBS_256_Msk  /* 256 entries */
13848 #define ETH_MACHWF3R_FRPSEL_Pos                       (10U)
13849 #define ETH_MACHWF3R_FRPSEL_Msk                       (0x1UL << ETH_MACHWF3R_FRPSEL_Pos) /*!< 0x00000400 */
13850 #define ETH_MACHWF3R_FRPSEL                           ETH_MACHWF3R_FRPSEL_Msk  /* Flexible Receive Parser Selected */
13851 #define ETH_MACHWF3R_PDUPSEL_Pos                      (9U)
13852 #define ETH_MACHWF3R_PDUPSEL_Msk                      (0x1UL << ETH_MACHWF3R_PDUPSEL_Pos) /*!< 0x00000200 */
13853 #define ETH_MACHWF3R_PDUPSEL                          ETH_MACHWF3R_PDUPSEL_Msk  /* Broadcast/Multicast Packet Duplication */
13854 #define ETH_MACHWF3R_DVLAN_Pos                        (5U)
13855 #define ETH_MACHWF3R_DVLAN_Msk                        (0x1UL << ETH_MACHWF3R_DVLAN_Pos) /*!< 0x00000020 */
13856 #define ETH_MACHWF3R_DVLAN                            ETH_MACHWF3R_DVLAN_Msk  /* Double VLAN processing enable */
13857 #define ETH_MACHWF3R_CBTISEL_Pos                      (4U)
13858 #define ETH_MACHWF3R_CBTISEL_Msk                      (0x1UL << ETH_MACHWF3R_CBTISEL_Pos) /*!< 0x00000010 */
13859 #define ETH_MACHWF3R_CBTISEL                          ETH_MACHWF3R_CBTISEL_Msk  /* Queue/Channel based VLAN tag insertion on Tx enable */
13860 #define ETH_MACHWF3R_NRVF_Pos                         (0U)
13861 #define ETH_MACHWF3R_NRVF_Msk                         (0x7UL << ETH_MACHWF3R_NRVF_Pos) /*!< 0x00000007 */
13862 #define ETH_MACHWF3R_NRVF                             ETH_MACHWF3R_NRVF_Msk  /* Number of Extended VLAN Tag Filters Enabled */
13863 #define ETH_MACHWF3R_NRVF_NOEXRXVLANFLTR              ((uint32_t)0x00000000) /* No Extended Rx VLAN Filters */
13864 #define ETH_MACHWF3R_NRVF_4EXRXVLANFLTR_Pos           (0U)
13865 #define ETH_MACHWF3R_NRVF_4EXRXVLANFLTR_Msk           (0x1UL << ETH_MACHWF3R_NRVF_4EXRXVLANFLTR_Pos) /*!< 0x00000001 */
13866 #define ETH_MACHWF3R_NRVF_4EXRXVLANFLTR               ETH_MACHWF3R_NRVF_4EXRXVLANFLTR_Msk
13867 #define ETH_MACHWF3R_NRVF_8EXRXVLANFLTR_Pos           (1U)
13868 #define ETH_MACHWF3R_NRVF_8EXRXVLANFLTR_Msk           (0x1UL << ETH_MACHWF3R_NRVF_8EXRXVLANFLTR_Pos) /*!< 0x00000002 */
13869 #define ETH_MACHWF3R_NRVF_8EXRXVLANFLTR               ETH_MACHWF3R_NRVF_8EXRXVLANFLTR_Msk
13870 #define ETH_MACHWF3R_NRVF_16EXRXVLANFLTR_Pos          (0U)
13871 #define ETH_MACHWF3R_NRVF_16EXRXVLANFLTR_Msk          (0x3UL << ETH_MACHWF3R_NRVF_16EXRXVLANFLTR_Pos) /*!< 0x00000003 */
13872 #define ETH_MACHWF3R_NRVF_16EXRXVLANFLTR              ETH_MACHWF3R_NRVF_16EXRXVLANFLTR_Msk
13873 #define ETH_MACHWF3R_NRVF_24EXRXVLANFLTR_Pos          (2U)
13874 #define ETH_MACHWF3R_NRVF_24EXRXVLANFLTR_Msk          (0x1UL << ETH_MACHWF3R_NRVF_24EXRXVLANFLTR_Pos) /*!< 0x00000004 */
13875 #define ETH_MACHWF3R_NRVF_24EXRXVLANFLTR              ETH_MACHWF3R_NRVF_24EXRXVLANFLTR_Msk
13876 #define ETH_MACHWF3R_NRVF_32EXRXVLANFLTR_Pos          (0U)
13877 #define ETH_MACHWF3R_NRVF_32EXRXVLANFLTR_Msk          (0x5UL << ETH_MACHWF3R_NRVF_32EXRXVLANFLTR_Pos) /*!< 0x00000005 */
13878 #define ETH_MACHWF3R_NRVF_32EXRXVLANFLTR              ETH_MACHWF3R_NRVF_32EXRXVLANFLTR_Msk
13879 
13880 /************ Bit definition for Ethernet MAC MDIO Address Register   ***************/
13881 #define ETH_MACMDIOAR_PSE_Pos                         (27U)
13882 #define ETH_MACMDIOAR_PSE_Msk                         (0x1UL << ETH_MACMDIOAR_PSE_Pos) /*!< 0x08000000 */
13883 #define ETH_MACMDIOAR_PSE                             ETH_MACMDIOAR_PSE_Msk    /* Preamble Suppression Enable */
13884 #define ETH_MACMDIOAR_BTB_Pos                         (26U)
13885 #define ETH_MACMDIOAR_BTB_Msk                         (0x1UL << ETH_MACMDIOAR_BTB_Pos) /*!< 0x04000000 */
13886 #define ETH_MACMDIOAR_BTB                             ETH_MACMDIOAR_BTB_Msk    /* Back to Back transactions */
13887 #define ETH_MACMDIOAR_PA_Pos                          (21U)
13888 #define ETH_MACMDIOAR_PA_Msk                          (0x1FUL << ETH_MACMDIOAR_PA_Pos) /*!< 0x03E00000 */
13889 #define ETH_MACMDIOAR_PA                              ETH_MACMDIOAR_PA_Msk     /* Physical Layer Address */
13890 #define ETH_MACMDIOAR_RDA_Pos                         (16U)
13891 #define ETH_MACMDIOAR_RDA_Msk                         (0x1FUL << ETH_MACMDIOAR_RDA_Pos) /*!< 0x001F0000 */
13892 #define ETH_MACMDIOAR_RDA                             ETH_MACMDIOAR_RDA_Msk    /* Register/Device Address */
13893 #define ETH_MACMDIOAR_NTC_Pos                         (12U)
13894 #define ETH_MACMDIOAR_NTC_Msk                         (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */
13895 #define ETH_MACMDIOAR_NTC                             ETH_MACMDIOAR_NTC_Msk    /* Number of Trailing Clocks */
13896 #define ETH_MACMDIOAR_CR_Pos                          (8U)
13897 #define ETH_MACMDIOAR_CR_Msk                          (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
13898 #define ETH_MACMDIOAR_CR                              ETH_MACMDIOAR_CR_Msk     /* CSR Clock Range */
13899 #define ETH_MACMDIOAR_CR_DIV42                        ((uint32_t)0x00000000)   /* CSR clock/42 */
13900 #define ETH_MACMDIOAR_CR_DIV62_Pos                    (8U)
13901 #define ETH_MACMDIOAR_CR_DIV62_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
13902 #define ETH_MACMDIOAR_CR_DIV62                        ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
13903 #define ETH_MACMDIOAR_CR_DIV16_Pos                    (9U)
13904 #define ETH_MACMDIOAR_CR_DIV16_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV16_Pos) /*!< 0x00000200 */
13905 #define ETH_MACMDIOAR_CR_DIV16                        ETH_MACMDIOAR_CR_DIV16_Msk /* CSR clock/16 */
13906 #define ETH_MACMDIOAR_CR_DIV26_Pos                    (8U)
13907 #define ETH_MACMDIOAR_CR_DIV26_Msk                    (0x3UL << ETH_MACMDIOAR_CR_DIV26_Pos) /*!< 0x00000300 */
13908 #define ETH_MACMDIOAR_CR_DIV26                        ETH_MACMDIOAR_CR_DIV26_Msk /* CSR clock/26 */
13909 #define ETH_MACMDIOAR_CR_DIV102_Pos                   (10U)
13910 #define ETH_MACMDIOAR_CR_DIV102_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV102_Pos) /*!< 0x00000400 */
13911 #define ETH_MACMDIOAR_CR_DIV102                       ETH_MACMDIOAR_CR_DIV102_Msk /* CSR clock/102 */
13912 #define ETH_MACMDIOAR_CR_DIV124_Pos                   (8U)
13913 #define ETH_MACMDIOAR_CR_DIV124_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV124_Pos) /*!< 0x00000500 */
13914 #define ETH_MACMDIOAR_CR_DIV124                       ETH_MACMDIOAR_CR_DIV124_Msk /* CSR clock/124 */
13915 #define ETH_MACMDIOAR_CR_DIV204_Pos                   (9U)
13916 #define ETH_MACMDIOAR_CR_DIV204_Msk                   (0x3UL << ETH_MACMDIOAR_CR_DIV204_Pos) /*!< 0x00000600 */
13917 #define ETH_MACMDIOAR_CR_DIV204                       ETH_MACMDIOAR_CR_DIV204_Msk /* CSR clock/204 */
13918 #define ETH_MACMDIOAR_CR_DIV324_Pos                   (8U)
13919 #define ETH_MACMDIOAR_CR_DIV324_Msk                   (0x7UL << ETH_MACMDIOAR_CR_DIV324_Pos) /*!< 0x00000700 */
13920 #define ETH_MACMDIOAR_CR_DIV324                       ETH_MACMDIOAR_CR_DIV324_Msk /* CSR clock/304 */
13921 #define ETH_MACMDIOAR_CR_DIV4AR_Pos                   (11U)
13922 #define ETH_MACMDIOAR_CR_DIV4AR_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV4AR_Pos) /*!< 0x00000800 */
13923 #define ETH_MACMDIOAR_CR_DIV4AR                       ETH_MACMDIOAR_CR_DIV4AR_Msk /* CSR clock/4: MDC clock above range specified in IEEE */
13924 #define ETH_MACMDIOAR_CR_DIV6AR_Pos                   (8U)
13925 #define ETH_MACMDIOAR_CR_DIV6AR_Msk                   (0x9UL << ETH_MACMDIOAR_CR_DIV6AR_Pos) /*!< 0x00000900 */
13926 #define ETH_MACMDIOAR_CR_DIV6AR                       ETH_MACMDIOAR_CR_DIV6AR_Msk /* CSR clock/6: MDC clock above range specified in IEEE */
13927 #define ETH_MACMDIOAR_CR_DIV8AR_Pos                   (9U)
13928 #define ETH_MACMDIOAR_CR_DIV8AR_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV8AR_Pos) /*!< 0x00000A00 */
13929 #define ETH_MACMDIOAR_CR_DIV8AR                       ETH_MACMDIOAR_CR_DIV8AR_Msk /* CSR clock/8: MDC clock above range specified in IEEE */
13930 #define ETH_MACMDIOAR_CR_DIV10AR_Pos                  (8U)
13931 #define ETH_MACMDIOAR_CR_DIV10AR_Msk                  (0xBUL << ETH_MACMDIOAR_CR_DIV10AR_Pos) /*!< 0x00000B00 */
13932 #define ETH_MACMDIOAR_CR_DIV10AR                      ETH_MACMDIOAR_CR_DIV10AR_Msk /* CSR clock/10: MDC clock above range specified in IEEE */
13933 #define ETH_MACMDIOAR_CR_DIV12AR_Pos                  (10U)
13934 #define ETH_MACMDIOAR_CR_DIV12AR_Msk                  (0x3UL << ETH_MACMDIOAR_CR_DIV12AR_Pos) /*!< 0x00000C00 */
13935 #define ETH_MACMDIOAR_CR_DIV12AR                      ETH_MACMDIOAR_CR_DIV12AR_Msk /* CSR clock/12: MDC clock above range specified in IEEE */
13936 #define ETH_MACMDIOAR_CR_DIV14AR_Pos                  (8U)
13937 #define ETH_MACMDIOAR_CR_DIV14AR_Msk                  (0xDUL << ETH_MACMDIOAR_CR_DIV14AR_Pos) /*!< 0x00000D00 */
13938 #define ETH_MACMDIOAR_CR_DIV14AR                      ETH_MACMDIOAR_CR_DIV14AR_Msk /* CSR clock/14: MDC clock above range specified in IEEE */
13939 #define ETH_MACMDIOAR_CR_DIV16AR_Pos                  (9U)
13940 #define ETH_MACMDIOAR_CR_DIV16AR_Msk                  (0x7UL << ETH_MACMDIOAR_CR_DIV16AR_Pos) /*!< 0x00000E00 */
13941 #define ETH_MACMDIOAR_CR_DIV16AR                      ETH_MACMDIOAR_CR_DIV16AR_Msk /* CSR clock/16: MDC clock above range specified in IEEE */
13942 #define ETH_MACMDIOAR_CR_DIV18AR_Pos                  (8U)
13943 #define ETH_MACMDIOAR_CR_DIV18AR_Msk                  (0xFUL << ETH_MACMDIOAR_CR_DIV18AR_Pos) /*!< 0x00000F00 */
13944 #define ETH_MACMDIOAR_CR_DIV18AR                      ETH_MACMDIOAR_CR_DIV18AR_Msk /* CSR clock/18: MDC clock above range specified in IEEE */
13945 #define ETH_MACMDIOAR_SKAP_Pos                        (4U)
13946 #define ETH_MACMDIOAR_SKAP_Msk                        (0x1UL << ETH_MACMDIOAR_SKAP_Pos) /*!< 0x00000010 */
13947 #define ETH_MACMDIOAR_SKAP                            ETH_MACMDIOAR_SKAP_Msk   /* Skip Address Packet */
13948 #define ETH_MACMDIOAR_GOC_Pos                         (2U)
13949 #define ETH_MACMDIOAR_GOC_Msk                         (0x3UL << ETH_MACMDIOAR_GOC_Pos) /*!< 0x0000000C */
13950 #define ETH_MACMDIOAR_GOC_0                           (0x1U << ETH_MACMDIOAR_GOC_Pos)                     /*!< 0x00000004 */
13951 #define ETH_MACMDIOAR_GOC_1                           (0x2U << ETH_MACMDIOAR_GOC_Pos)                     /*!< 0x00000008 */
13952 #define ETH_MACMDIOAR_GOC                             ETH_MACMDIOAR_GOC_Msk    /* GMII Operation Command */
13953 #define ETH_MACMDIOAR_C45E_Pos                        (1U)
13954 #define ETH_MACMDIOAR_C45E_Msk                        (0x1UL << ETH_MACMDIOAR_C45E_Pos) /*!< 0x00000002 */
13955 #define ETH_MACMDIOAR_C45E                            ETH_MACMDIOAR_C45E_Msk   /* Clause 45 PHY Enable */
13956 #define ETH_MACMDIOAR_GB_Pos                          (0U)
13957 #define ETH_MACMDIOAR_GB_Msk                          (0x1UL << ETH_MACMDIOAR_GB_Pos) /*!< 0x00000001 */
13958 #define ETH_MACMDIOAR_GB                              ETH_MACMDIOAR_GB_Msk     /* GMII Busy */
13959 
13960 /************ Bit definition for Ethernet MAC MDIO Data Register   ***************/
13961 #define ETH_MACMDIODR_RA_Pos                          (16U)
13962 #define ETH_MACMDIODR_RA_Msk                          (0xFFFFUL << ETH_MACMDIODR_RA_Pos) /*!< 0xFFFF0000 */
13963 #define ETH_MACMDIODR_RA                              ETH_MACMDIODR_RA_Msk     /* Register Address */
13964 #define ETH_MACMDIODR_GD_Pos                          (0U)
13965 #define ETH_MACMDIODR_GD_Msk                          (0xFFFFUL << ETH_MACMDIODR_GD_Pos) /*!< 0x0000FFFF */
13966 #define ETH_MACMDIODR_GD                              ETH_MACMDIODR_GD_Msk     /* GMII Data */
13967 
13968 /************ Bit definition for Ethernet ARP Address Register    ***************/
13969 #define ETH_MACARPAR_ARPPA_Pos                        (0U)
13970 #define ETH_MACARPAR_ARPPA_Msk                        (0xFFFFFFFFUL << ETH_MACARPAR_ARPPA_Pos) /*!< 0xFFFFFFFF */
13971 #define ETH_MACARPAR_ARPPA                            ETH_MACARPAR_ARPPA_Msk     /* ARP Protocol Address */
13972 
13973 /************ Bit definition for Ethernet MAC CSR software control Register   ***************/
13974 #define ETH_MACCSRSWCR_SEEN_Pos                       (8U)
13975 #define ETH_MACCSRSWCR_SEEN_Msk                       (0x1UL << ETH_MACCSRSWCR_SEEN_Pos) /*!< 0x00000100 */
13976 #define ETH_MACCSRSWCR_SEEN                           ETH_MACCSRSWCR_SEEN_Msk /* Slave Error Response Enable */
13977 #define ETH_MACCSRSWCR_RCWE_Pos                       (0U)
13978 #define ETH_MACCSRSWCR_RCWE_Msk                       (0x1UL << ETH_MACCSRSWCR_RCWE_Pos) /*!< 0x00000001 */
13979 #define ETH_MACCSRSWCR_RCWE                           ETH_MACCSRSWCR_RCWE_Msk /* Register Clear on Write 1 Enable */
13980 
13981 /************ Bit definition for Ethernet MAC FPE control and status Register   ***************/
13982 #define ETH_MACFPECSR_TRSP_Pos                        (19U)
13983 #define ETH_MACFPECSR_TRSP_Msk                        (0x1UL << ETH_MACFPECSR_TRSP_Pos) /*!< 0x00080000 */
13984 #define ETH_MACFPECSR_TRSP                            ETH_MACFPECSR_TRSP_Msk /* Transmitted Respond Frame */
13985 #define ETH_MACFPECSR_TVER_Pos                        (18U)
13986 #define ETH_MACFPECSR_TVER_Msk                        (0x1UL << ETH_MACFPECSR_TVER_Pos) /*!< 0x00040000 */
13987 #define ETH_MACFPECSR_TVER                            ETH_MACFPECSR_TVER_Msk /* Transmitted Verify Frame */
13988 #define ETH_MACFPECSR_RRSP_Pos                        (17U)
13989 #define ETH_MACFPECSR_RRSP_Msk                        (0x1UL << ETH_MACFPECSR_RRSP_Pos) /*!< 0x00020000 */
13990 #define ETH_MACFPECSR_RRSP                            ETH_MACFPECSR_RRSP_Msk /* Received Respond Frame */
13991 #define ETH_MACFPECSR_RVER_Pos                        (16U)
13992 #define ETH_MACFPECSR_RVER_Msk                        (0x1UL << ETH_MACFPECSR_RVER_Pos) /*!< 0x00010000 */
13993 #define ETH_MACFPECSR_RVER                            ETH_MACFPECSR_RVER_Msk /* Received Verify Frame */
13994 #define ETH_MACFPECSR_SRSP_Pos                        (2U)
13995 #define ETH_MACFPECSR_SRSP_Msk                        (0x1UL << ETH_MACFPECSR_SRSP_Pos) /*!< 0x00000004 */
13996 #define ETH_MACFPECSR_SRSP                            ETH_MACFPECSR_SRSP_Msk /* Send Respond mPacket */
13997 #define ETH_MACFPECSR_SVER_Pos                        (1U)
13998 #define ETH_MACFPECSR_SVER_Msk                        (0x1UL << ETH_MACFPECSR_SVER_Pos) /*!< 0x00000002 */
13999 #define ETH_MACFPECSR_SVER                            ETH_MACFPECSR_SVER_Msk /* Send Verify mPacket */
14000 #define ETH_MACFPECSR_EFPE_Pos                        (0U)
14001 #define ETH_MACFPECSR_EFPE_Msk                        (0x1UL << ETH_MACFPECSR_EFPE_Pos) /*!< 0x00000001 */
14002 #define ETH_MACFPECSR_EFPE                            ETH_MACFPECSR_EFPE_Msk /* Enable Tx Frame Preemption */
14003 
14004 /************ Bit definition for Ethernet MAC presentation time Register   ***************/
14005 #define ETH_MACPRSTIMR_MPTN_Pos                        (0U)
14006 #define ETH_MACPRSTIMR_MPTN_Msk                        (0xFFFFFFFFUL << ETH_MACPRSTIMR_MPTN_Pos) /*!< 0xFFFFFFFF */
14007 #define ETH_MACPRSTIMR_MPTN                            ETH_MACPRSTIMR_MPTN_Msk /* MAC 1722 Presentation Time in ns */
14008 
14009 /************ Bit definition for Ethernet MAC presentation time Register   ***************/
14010 #define ETH_MACPRSTIMUR_MPTU_Pos                       (0U)
14011 #define ETH_MACPRSTIMUR_MPTU_Msk                       (0xFFFFFFFFUL << ETH_MACPRSTIMUR_MPTU_Pos) /*!< 0xFFFFFFFF */
14012 #define ETH_MACPRSTIMUR_MPTU                           ETH_MACPRSTIMUR_MPTU_Msk /* MAC 1722 Presentation Time Update */
14013 
14014 /************ Bit definition for Ethernet MAC Address 0 High Register   ***************/
14015 #define ETH_MACA0HR_AE_Pos                            (31U)
14016 #define ETH_MACA0HR_AE_Msk                            (0x1UL << ETH_MACA0HR_AE_Pos) /*!< 0x80000000 */
14017 #define ETH_MACA0HR_AE                                ETH_MACA0HR_AE_Msk /* Address Enable*/
14018 #define ETH_MACA0HR_DCS_Pos                           (16U)
14019 #define ETH_MACA0HR_DCS_Msk                           (0x1UL << ETH_MACA0HR_DCS_Pos) /*!< 0x80000000 */
14020 #define ETH_MACA0HR_DCS                               ETH_MACA0HR_DCS_Msk /* DMA Channel Select */
14021 #define ETH_MACA0HR_ADDRHI_Pos                        (0U)
14022 #define ETH_MACA0HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x0000FFFF */
14023 #define ETH_MACA0HR_ADDRHI                            ETH_MACA0HR_ADDRHI_Msk   /* MAC Address 0*/
14024 
14025 /************ Bit definition for Ethernet MAC Address x Low Register   ***************/
14026 #define ETH_MACAxLR_ADDRLO_Pos                        (0U)
14027 #define ETH_MACAxLR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACAxLR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
14028 #define ETH_MACAxLR_ADDRLO                            ETH_MACAxLR_ADDRLO_Msk   /* MAC Address x*/
14029 
14030 /************ Bit definition for Ethernet MAC Address x High Register  ***************/
14031 #define ETH_MACAxHR_AE_Pos                            (31U)
14032 #define ETH_MACAxHR_AE_Msk                            (0x1UL << ETH_MACAxHR_AE_Pos) /*!< 0x80000000 */
14033 #define ETH_MACAxHR_AE                                ETH_MACAxHR_AE_Msk /* Address Enable*/
14034 #define ETH_MACAxHR_SA_Pos                            (30U)
14035 #define ETH_MACAxHR_SA_Msk                            (0x1UL << ETH_MACAxHR_SA_Pos) /*!< 0x40000000 */
14036 #define ETH_MACAxHR_SA                                ETH_MACAxHR_SA_Msk /* Source Address */
14037 #define ETH_MACAxHR_MBC_Pos                           (24U)
14038 #define ETH_MACAxHR_MBC_Msk                           (0x3FUL << ETH_MACAxHR_MBC_Pos) /*!< 0x3F000000 */
14039 #define ETH_MACAxHR_MBC                               ETH_MACAxHR_MBC_Msk /* Mask Byte Control */
14040 #define ETH_MACAxHR_DCS_Pos                           (16U)
14041 #define ETH_MACAxHR_DCS_Msk                           (0x1UL << ETH_MACAxHR_DCS_Pos) /*!< 0x00010000 */
14042 #define ETH_MACAxHR_DCS                               ETH_MACAxHR_DCS_Msk /* DMA Channel Select */
14043 #define ETH_MACAxHR_ADDRHI_Pos                        (0U)
14044 #define ETH_MACAxHR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACAxHR_ADDRHI_Pos) /*!< 0x0000FFFF */
14045 #define ETH_MACAxHR_ADDRHI                            ETH_MACAxHR_ADDRHI_Msk   /* MAC Address 1*/
14046 
14047 /************ Bit definition for Ethernet MMC Control Register   ***************/
14048 #define ETH_MMCCR_UCDBC_Pos                           (8U)
14049 #define ETH_MMCCR_UCDBC_Msk                           (0x1UL << ETH_MMCCR_UCDBC_Pos) /*!< 0x00000100 */
14050 #define ETH_MMCCR_UCDBC                               ETH_MMCCR_UCDBC_Msk  /* Update MMC Counters for Dropped Broadcast Packets */
14051 #define ETH_MMCCR_CNTPRSTLVL_Pos                      (5U)
14052 #define ETH_MMCCR_CNTPRSTLVL_Msk                      (0x1UL << ETH_MMCCR_CNTPRSTLVL_Pos) /*!< 0x00000020 */
14053 #define ETH_MMCCR_CNTPRSTLVL                          ETH_MMCCR_CNTPRSTLVL_Msk  /* Full-Half Preset */
14054 #define ETH_MMCCR_CNTPRST_Pos                         (4U)
14055 #define ETH_MMCCR_CNTPRST_Msk                         (0x1UL << ETH_MMCCR_CNTPRST_Pos) /*!< 0x00000010 */
14056 #define ETH_MMCCR_CNTPRST                             ETH_MMCCR_CNTPRST_Msk  /* Counters Reset */
14057 #define ETH_MMCCR_CNTFREEZ_Pos                        (3U)
14058 #define ETH_MMCCR_CNTFREEZ_Msk                        (0x1UL << ETH_MMCCR_CNTFREEZ_Pos) /*!< 0x00000008 */
14059 #define ETH_MMCCR_CNTFREEZ                            ETH_MMCCR_CNTFREEZ_Msk  /* MMC Counter Freeze */
14060 #define ETH_MMCCR_RSTONRD_Pos                         (2U)
14061 #define ETH_MMCCR_RSTONRD_Msk                         (0x1UL << ETH_MMCCR_RSTONRD_Pos) /*!< 0x00000004 */
14062 #define ETH_MMCCR_RSTONRD                             ETH_MMCCR_RSTONRD_Msk  /* Reset On Read */
14063 #define ETH_MMCCR_CNTSTOPRO_Pos                       (1U)
14064 #define ETH_MMCCR_CNTSTOPRO_Msk                       (0x1UL << ETH_MMCCR_CNTSTOPRO_Pos) /*!< 0x00000002 */
14065 #define ETH_MMCCR_CNTSTOPRO                           ETH_MMCCR_CNTSTOPRO_Msk  /* Counter Stop Rollover */
14066 #define ETH_MMCCR_CNTRST_Pos                          (0U)
14067 #define ETH_MMCCR_CNTRST_Msk                          (0x1UL << ETH_MMCCR_CNTRST_Pos) /*!< 0x00000001 */
14068 #define ETH_MMCCR_CNTRST                              ETH_MMCCR_CNTRST_Msk  /* Counters Reset */
14069 
14070 /************ Bit definition for Ethernet MMC Rx Interrupt Register  ***************/
14071 #define ETH_MMCRIR_RXLPITRCIS_Pos                     (27U)
14072 #define ETH_MMCRIR_RXLPITRCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPITRCIS_Pos) /*!< 0x08000000 */
14073 #define ETH_MMCRIR_RXLPITRCIS                         ETH_MMCRIR_RXLPITRCIS_Msk  /* MMC Receive LPI transition counter interrupt status */
14074 #define ETH_MMCRIR_RXLPIUSCIS_Pos                     (26U)
14075 #define ETH_MMCRIR_RXLPIUSCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPIUSCIS_Pos) /*!< 0x04000000 */
14076 #define ETH_MMCRIR_RXLPIUSCIS                         ETH_MMCRIR_RXLPIUSCIS_Msk  /* MMC Receive LPI microsecond counter interrupt status */
14077 #define ETH_MMCRIR_RXUCGPIS_Pos                       (17U)
14078 #define ETH_MMCRIR_RXUCGPIS_Msk                       (0x1UL << ETH_MMCRIR_RXUCGPIS_Pos) /*!< 0x00020000 */
14079 #define ETH_MMCRIR_RXUCGPIS                           ETH_MMCRIR_RXUCGPIS_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Status */
14080 #define ETH_MMCRIR_RXALGNERPIS_Pos                    (6U)
14081 #define ETH_MMCRIR_RXALGNERPIS_Msk                    (0x1UL << ETH_MMCRIR_RXALGNERPIS_Pos) /*!< 0x00000040 */
14082 #define ETH_MMCRIR_RXALGNERPIS                        ETH_MMCRIR_RXALGNERPIS_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Status */
14083 #define ETH_MMCRIR_RXCRCERPIS_Pos                     (5U)
14084 #define ETH_MMCRIR_RXCRCERPIS_Msk                     (0x1UL << ETH_MMCRIR_RXCRCERPIS_Pos) /*!< 0x00000020 */
14085 #define ETH_MMCRIR_RXCRCERPIS                         ETH_MMCRIR_RXCRCERPIS_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Status */
14086 
14087 /************ Bit definition for Ethernet MMC Tx Interrupt Register   ***************/
14088 #define ETH_MMCTIR_TXLPITRCIS_Pos                     (27U)
14089 #define ETH_MMCTIR_TXLPITRCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPITRCIS_Pos) /*!< 0x08000000 */
14090 #define ETH_MMCTIR_TXLPITRCIS                         ETH_MMCTIR_TXLPITRCIS_Msk  /* MMC Transmit LPI transition counter interrupt status */
14091 #define ETH_MMCTIR_TXLPIUSCIS_Pos                     (26U)
14092 #define ETH_MMCTIR_TXLPIUSCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPIUSCIS_Pos) /*!< 0x04000000 */
14093 #define ETH_MMCTIR_TXLPIUSCIS                         ETH_MMCTIR_TXLPIUSCIS_Msk  /* MMC Transmit LPI microsecond counter interrupt status */
14094 #define ETH_MMCTIR_TXGPKTIS_Pos                       (21U)
14095 #define ETH_MMCTIR_TXGPKTIS_Msk                       (0x1UL << ETH_MMCTIR_TXGPKTIS_Pos) /*!< 0x00200000 */
14096 #define ETH_MMCTIR_TXGPKTIS                           ETH_MMCTIR_TXGPKTIS_Msk  /* MMC Transmit Good Packet Counter Interrupt Status */
14097 #define ETH_MMCTIR_TXMCOLGPIS_Pos                     (15U)
14098 #define ETH_MMCTIR_TXMCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXMCOLGPIS_Pos) /*!< 0x00008000 */
14099 #define ETH_MMCTIR_TXMCOLGPIS                         ETH_MMCTIR_TXMCOLGPIS_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */
14100 #define ETH_MMCTIR_TXSCOLGPIS_Pos                     (14U)
14101 #define ETH_MMCTIR_TXSCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXSCOLGPIS_Pos) /*!< 0x00004000 */
14102 #define ETH_MMCTIR_TXSCOLGPIS                         ETH_MMCTIR_TXSCOLGPIS_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Status */
14103 
14104 /************ Bit definition for Ethernet MMC Rx interrupt Mask Register   ***************/
14105 #define ETH_MMCRIMR_RXLPITRCIM_Pos                    (27U)
14106 #define ETH_MMCRIMR_RXLPITRCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPITRCIM_Pos) /*!< 0x08000000 */
14107 #define ETH_MMCRIMR_RXLPITRCIM                        ETH_MMCRIMR_RXLPITRCIM_Msk  /* MMC Receive LPI transition counter interrupt Mask */
14108 #define ETH_MMCRIMR_RXLPIUSCIM_Pos                    (26U)
14109 #define ETH_MMCRIMR_RXLPIUSCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPIUSCIM_Pos) /*!< 0x04000000 */
14110 #define ETH_MMCRIMR_RXLPIUSCIM                        ETH_MMCRIMR_RXLPIUSCIM_Msk  /* MMC Receive LPI microsecond counter interrupt Mask */
14111 #define ETH_MMCRIMR_RXUCGPIM_Pos                      (17U)
14112 #define ETH_MMCRIMR_RXUCGPIM_Msk                      (0x1UL << ETH_MMCRIMR_RXUCGPIM_Pos) /*!< 0x00020000 */
14113 #define ETH_MMCRIMR_RXUCGPIM                          ETH_MMCRIMR_RXUCGPIM_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Mask */
14114 #define ETH_MMCRIMR_RXALGNERPIM_Pos                   (6U)
14115 #define ETH_MMCRIMR_RXALGNERPIM_Msk                   (0x1UL << ETH_MMCRIMR_RXALGNERPIM_Pos) /*!< 0x00000040 */
14116 #define ETH_MMCRIMR_RXALGNERPIM                       ETH_MMCRIMR_RXALGNERPIM_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Mask */
14117 #define ETH_MMCRIMR_RXCRCERPIM_Pos                    (5U)
14118 #define ETH_MMCRIMR_RXCRCERPIM_Msk                    (0x1UL << ETH_MMCRIMR_RXCRCERPIM_Pos) /*!< 0x00000020 */
14119 #define ETH_MMCRIMR_RXCRCERPIM                        ETH_MMCRIMR_RXCRCERPIM_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Mask */
14120 
14121 /************ Bit definition for Ethernet MMC Tx Interrupt Mask Register   ***************/
14122 #define ETH_MMCTIMR_TXLPITRCIM_Pos                    (27U)
14123 #define ETH_MMCTIMR_TXLPITRCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */
14124 #define ETH_MMCTIMR_TXLPITRCIM                        ETH_MMCTIMR_TXLPITRCIM_Msk  /* MMC Transmit LPI transition counter interrupt Mask*/
14125 #define ETH_MMCTIMR_TXLPIUSCIM_Pos                    (26U)
14126 #define ETH_MMCTIMR_TXLPIUSCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPIUSCIM_Pos) /*!< 0x04000000 */
14127 #define ETH_MMCTIMR_TXLPIUSCIM                        ETH_MMCTIMR_TXLPIUSCIM_Msk  /* MMC Transmit LPI microsecond counter interrupt Mask*/
14128 #define ETH_MMCTIMR_TXGPKTIM_Pos                      (21U)
14129 #define ETH_MMCTIMR_TXGPKTIM_Msk                      (0x1UL << ETH_MMCTIMR_TXGPKTIM_Pos) /*!< 0x00200000 */
14130 #define ETH_MMCTIMR_TXGPKTIM                          ETH_MMCTIMR_TXGPKTIM_Msk  /* MMC Transmit Good Packet Counter Interrupt Mask*/
14131 #define ETH_MMCTIMR_TXMCOLGPIM_Pos                    (15U)
14132 #define ETH_MMCTIMR_TXMCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXMCOLGPIM_Pos) /*!< 0x00008000 */
14133 #define ETH_MMCTIMR_TXMCOLGPIM                        ETH_MMCTIMR_TXMCOLGPIM_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */
14134 #define ETH_MMCTIMR_TXSCOLGPIM_Pos                    (14U)
14135 #define ETH_MMCTIMR_TXSCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXSCOLGPIM_Pos) /*!< 0x00004000 */
14136 #define ETH_MMCTIMR_TXSCOLGPIM                        ETH_MMCTIMR_TXSCOLGPIM_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Mask */
14137 
14138 /************ Bit definition for Ethernet MMC Tx Single Collision Good Packets Register   ***************/
14139 #define ETH_MMCTSCGPR_TXSNGLCOLG_Pos                  (0U)
14140 #define ETH_MMCTSCGPR_TXSNGLCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTSCGPR_TXSNGLCOLG_Pos) /*!< 0xFFFFFFFF */
14141 #define ETH_MMCTSCGPR_TXSNGLCOLG                      ETH_MMCTSCGPR_TXSNGLCOLG_msk /* Tx Single Collision Good Packets */
14142 
14143 /************ Bit definition for Ethernet MMC Tx Multiple Collision Good Packets Register   ***************/
14144 #define ETH_MMCTMCGPR_TXMULTCOLG_Pos                  (0U)
14145 #define ETH_MMCTMCGPR_TXMULTCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTMCGPR_TXMULTCOLG_Pos) /*!< 0xFFFFFFFF */
14146 #define ETH_MMCTMCGPR_TXMULTCOLG                      ETH_MMCTMCGPR_TXMULTCOLG_msk /* Tx Multiple Collision Good Packets */
14147 
14148 /************ Bit definition for Ethernet MMC Tx Packet Count Good Register  ***************/
14149 #define ETH_MMCTPCGR_TXPKTG_Pos                       (0U)
14150 #define ETH_MMCTPCGR_TXPKTG_msk                       (0xFFFFFFFFUL <<  ETH_MMCTPCGR_TXPKTG_Pos) /*!< 0xFFFFFFFF */
14151 #define ETH_MMCTPCGR_TXPKTG                           ETH_MMCTPCGR_TXPKTG_msk /* Tx Packet Count Good */
14152 
14153 /************ Bit definition for Ethernet MMC Rx CRC Error Packets Register  ***************/
14154 #define ETH_MMCRCRCEPR_RXCRCERR_Pos                   (0U)
14155 #define ETH_MMCRCRCEPR_RXCRCERR_msk                   (0xFFFFFFFFUL <<  ETH_MMCRCRCEPR_RXCRCERR_Pos) /*!< 0xFFFFFFFF */
14156 #define ETH_MMCRCRCEPR_RXCRCERR                       ETH_MMCRCRCEPR_RXCRCERR_msk /* Rx CRC Error Packets */
14157 
14158 /************ Bit definition for Ethernet MMC Rx alignment error packets Register   ***************/
14159 #define ETH_MMCRAEPR_RXALGNERR_Pos                    (0U)
14160 #define ETH_MMCRAEPR_RXALGNERR_msk                    (0xFFFFFFFFUL <<  ETH_MMCRAEPR_RXALGNERR_Pos) /*!< 0xFFFFFFFF */
14161 #define ETH_MMCRAEPR_RXALGNERR                        ETH_MMCRAEPR_RXALGNERR_msk /* Rx Alignment Error Packets */
14162 
14163 /************ Bit definition for Ethernet MMC Rx Unicast Packets Good Register   ***************/
14164 #define ETH_MMCRUPGR_RXUCASTG_Pos                     (0U)
14165 #define ETH_MMCRUPGR_RXUCASTG_msk                     (0xFFFFFFFFUL <<  ETH_MMCRUPGR_RXUCASTG_Pos) /*!< 0xFFFFFFFF */
14166 #define ETH_MMCRUPGR_RXUCASTG                         ETH_MMCRUPGR_RXUCASTG_msk /* Rx Unicast Packets Good */
14167 
14168 /************ Bit definition for Ethernet MMC Tx LPI Microsecond Timer Register   ***************/
14169 #define ETH_MMCTLPIMSTR_TXLPIUSC_Pos                  (0U)
14170 #define ETH_MMCTLPIMSTR_TXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCTLPIMSTR_TXLPIUSC_Pos) /*!< 0xFFFFFFFF */
14171 #define ETH_MMCTLPIMSTR_TXLPIUSC                      ETH_MMCTLPIMSTR_TXLPIUSC_msk /* Tx LPI Microseconds Counter */
14172 
14173 /************ Bit definition for Ethernet MMC Tx LPI Transition Counter Register   ***************/
14174 #define ETH_MMCTLPITCR_TXLPITRC_Pos                   (0U)
14175 #define ETH_MMCTLPITCR_TXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCTLPITCR_TXLPITRC_Pos) /*!< 0xFFFFFFFF */
14176 #define ETH_MMCTLPITCR_TXLPITRC                       ETH_MMCTLPITCR_TXLPITRC_msk /* Tx LPI Transition counter */
14177 
14178 /************ Bit definition for Ethernet MMC Rx LPI Microsecond Counter Register   ***************/
14179 #define ETH_MMCRLPIMSTR_RXLPIUSC_Pos                  (0U)
14180 #define ETH_MMCRLPIMSTR_RXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCRLPIMSTR_RXLPIUSC_Pos) /*!< 0xFFFFFFFF */
14181 #define ETH_MMCRLPIMSTR_RXLPIUSC                      ETH_MMCRLPIMSTR_RXLPIUSC_msk /* Rx LPI Microseconds Counter */
14182 
14183 /************ Bit definition for Ethernet MMC Rx LPI Transition Counter Register   ***************/
14184 #define ETH_MMCRLPITCR_RXLPITRC_Pos                   (0U)
14185 #define ETH_MMCRLPITCR_RXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCRLPITCR_RXLPITRC_Pos) /*!< 0xFFFFFFFF */
14186 #define ETH_MMCRLPITCR_RXLPITRC                       ETH_MMCRLPITCR_RXLPITRC_msk /* Rx LPI Transition counter */
14187 
14188 /************ Bit definition for Ethernet MMC FPE Tx interrupt status Register   ***************/
14189 #define ETH_MMCFPETISR_HRCIS_Pos                      (1U)
14190 #define ETH_MMCFPETISR_HRCIS_msk                      (0x1UL <<  ETH_MMCFPETISR_HRCIS_Pos) /*!< 0x00000002 */
14191 #define ETH_MMCFPETISR_HRCIS                          ETH_MMCFPETISR_HRCIS_msk /* MMC Tx Hold Request Counter Interrupt Status */
14192 #define ETH_MMCFPETISR_FCIS_Pos                       (0U)
14193 #define ETH_MMCFPETISR_FCIS_msk                       (0x1UL <<  ETH_MMCFPETISR_FCIS_Pos) /*!< 0x00000001 */
14194 #define ETH_MMCFPETISR_FCIS                           ETH_MMCFPETISR_FCIS_msk /* MMC Tx FPE Fragment Counter Interrupt status */
14195 
14196 /************ Bit definition for Ethernet MMC FPE Tx interrupt mask Register   ***************/
14197 #define ETH_MMCFPETIMR_HRCIM_Pos                      (1U)
14198 #define ETH_MMCFPETIMR_HRCIM_msk                      (0x1UL <<  ETH_MMCFPETIMR_HRCIM_Pos) /*!< 0x00000002 */
14199 #define ETH_MMCFPETIMR_HRCIM                          ETH_MMCFPETIMR_HRCIM_msk /* MMC transmit Hold Request Counter Interrupt Mask */
14200 #define ETH_MMCFPETIMR_FCIM_Pos                       (0U)
14201 #define ETH_MMCFPETIMR_FCIM_msk                       (0x1UL <<  ETH_MMCFPETIMR_FCIM_Pos) /*!< 0x00000001 */
14202 #define ETH_MMCFPETIMR_FCIM                           ETH_MMCFPETIMR_FCIM_msk /* MMC Transmit Fragment Counter Interrupt Mask */
14203 
14204 /************ Bit definition for Ethernet MMC FPE Tx fragment counter Register   ***************/
14205 #define ETH_MMCFPETFCR_TXFFC_Pos                      (0U)
14206 #define ETH_MMCFPETFCR_TXFFC_msk                      (0xFFFFFFFFUL <<  ETH_MMCFPETFCR_TXFFC_Pos) /*!< 0xFFFFFFFF */
14207 #define ETH_MMCFPETFCR_TXFFC                          ETH_MMCFPETFCR_TXFFC_msk /* MMC transmit Hold Request Counter Interrupt Mask */
14208 
14209 /************ Bit definition for Ethernet MMC Tx hold request counter Register   ***************/
14210 #define ETH_MMCTHRCR_TXHRC_Pos                        (0U)
14211 #define ETH_MMCTHRCR_TXHRC_msk                        (0xFFFFFFFFUL <<  ETH_MMCTHRCR_TXHRC_Pos) /*!< 0xFFFFFFFF */
14212 #define ETH_MMCTHRCR_TXHRC                            ETH_MMCTHRCR_TXHRC_msk /* Tx hold request counter */
14213 
14214 /************ Bit definition for Ethernet MMC FPE Rx interrupt status Register   ***************/
14215 #define ETH_MMCFPERISR_FCIS_Pos                       (3U)
14216 #define ETH_MMCFPERISR_FCIS_msk                       (0x1UL <<  ETH_MMCFPERISR_FCIS_Pos) /*!< 0x00000008 */
14217 #define ETH_MMCFPERISR_FCIS                           ETH_MMCFPERISR_FCIS_msk /* MMC Rx FPE Fragment Counter Interrupt Status */
14218 #define ETH_MMCFPERISR_PAOCIS_Pos                     (2U)
14219 #define ETH_MMCFPERISR_PAOCIS_msk                     (0x1UL <<  ETH_MMCFPERISR_PAOCIS_Pos) /*!< 0x00000004 */
14220 #define ETH_MMCFPERISR_PAOCIS                         ETH_MMCFPERISR_PAOCIS_msk /* MMC Rx Packet Assembly OK counter interrupt status */
14221 #define ETH_MMCFPERISR_PSECIS_Pos                     (1U)
14222 #define ETH_MMCFPERISR_PSECIS_msk                     (0x1UL <<  ETH_MMCFPERISR_PSECIS_Pos) /*!< 0x00000002 */
14223 #define ETH_MMCFPERISR_PSECIS                         ETH_MMCFPERISR_PSECIS_msk /* MMC Rx Packet SMD Error counter interrupt status */
14224 #define ETH_MMCFPERISR_PAECIS_Pos                     (0U)
14225 #define ETH_MMCFPERISR_PAECIS_msk                     (0x1UL <<  ETH_MMCFPERISR_PAECIS_Pos) /*!< 0x00000001 */
14226 #define ETH_MMCFPERISR_PAECIS                         ETH_MMCFPERISR_PAECIS_msk /* MMC Rx Packet Assembly Error counter interrupt status */
14227 
14228 /************ Bit definition for Ethernet MMC FPE Rx interrupt mask Register   ***************/
14229 #define ETH_MMCFPERIMR_FCIM_Pos                       (3U)
14230 #define ETH_MMCFPERIMR_FCIM_msk                       (0x1UL <<  ETH_MMCFPERIMR_FCIM_Pos) /*!< 0x00000008 */
14231 #define ETH_MMCFPERIMR_FCIM                           ETH_MMCFPERIMR_FCIM_msk /* MMC Rx FPE Fragment Counter Interrupt Mask */
14232 #define ETH_MMCFPERIMR_PAOCIS_Pos                     (2U)
14233 #define ETH_MMCFPERIMR_PAOCIS_msk                     (0x1UL <<  ETH_MMCFPERIMR_PAOCIS_Pos) /*!< 0x00000004 */
14234 #define ETH_MMCFPERIMR_PAOCIS                         ETH_MMCFPERIMR_PAOCIS_msk /* MMC Rx Packet Assembly OK counter interrupt Mask */
14235 #define ETH_MMCFPERIMR_PSECIS_Pos                     (1U)
14236 #define ETH_MMCFPERIMR_PSECIS_msk                     (0x1UL <<  ETH_MMCFPERIMR_PSECIS_Pos) /*!< 0x00000002 */
14237 #define ETH_MMCFPERIMR_PSECIS                         ETH_MMCFPERIMR_PSECIS_msk /* MMC Rx Packet SMD Error counter interrupt Mask */
14238 #define ETH_MMCFPERIMR_PAECIS_Pos                     (0U)
14239 #define ETH_MMCFPERIMR_PAECIS_msk                     (0x1UL <<  ETH_MMCFPERIMR_PAECIS_Pos) /*!< 0x00000001 */
14240 #define ETH_MMCFPERIMR_PAECIS                         ETH_MMCFPERIMR_PAECIS_msk /* MMC Rx Packet Assembly Error counter interrupt Mask */
14241 
14242 /************ Bit definition for Ethernet MMC Rx packet assembly error Register   ***************/
14243 #define ETH_MMCRPAER_PAEC_Pos                         (0U)
14244 #define ETH_MMCRPAER_PAEC_msk                         (0xFFFFFFFFUL <<  ETH_MMCRPAER_PAEC_Pos) /*!< 0xFFFFFFFF */
14245 #define ETH_MMCRPAER_PAEC                             ETH_MMCRPAER_PAEC_msk /* Rx Packet Assembly Error Counter */
14246 
14247 /************ Bit definition for Ethernet MMC Rx packet SMD error Register   ***************/
14248 #define ETH_MMCRPSMDER_PSEC_Pos                       (0U)
14249 #define ETH_MMCRPSMDER_PSEC_msk                       (0xFFFFFFFFUL <<  ETH_MMCRPSMDER_PSEC_Pos) /*!< 0xFFFFFFFF */
14250 #define ETH_MMCRPSMDER_PSEC                           ETH_MMCRPSMDER_PSEC_msk /* Rx Packet SMD Error Counter */
14251 
14252 /************ Bit definition for Ethernet MMC Rx packet assembly OK Register   ***************/
14253 #define ETH_MMCRPAOKR_PAOC_Pos                        (0U)
14254 #define ETH_MMCRPAOKR_PAOC_msk                        (0xFFFFFFFFUL <<  ETH_MMCRPAOKR_PAOC_Pos) /*!< 0xFFFFFFFF */
14255 #define ETH_MMCRPAOKR_PAOC                            ETH_MMCRPAOKR_PAOC_msk /* Rx Packet Assembly OK Counter */
14256 
14257 /************ Bit definition for Ethernet MMC Rx FPE fragments counter Register   ***************/
14258 #define ETH_MMCFPERFCR_FFC_Pos                        (0U)
14259 #define ETH_MMCFPERFCR_FFC_msk                        (0xFFFFFFFFUL <<  ETH_MMCFPERFCR_FFC_Pos) /*!< 0xFFFFFFFF */
14260 #define ETH_MMCFPERFCR_FFC                            ETH_MMCFPERFCR_FFC_msk /* Rx FPE Fragment Counter */
14261 
14262 /************ Bit definition for Ethernet MAC L3 and L4 control 0 Register   ***************/
14263 #define ETH_MACL3L4C0R_DMCHEN0_Pos                     (28U)
14264 #define ETH_MACL3L4C0R_DMCHEN0_Msk                     (0x1UL << ETH_MACL3L4C0R_DMCHEN0_Pos) /*!< 0x10000000 */
14265 #define ETH_MACL3L4C0R_DMCHEN0                         ETH_MACL3L4C0R_DMCHEN0_Msk /* DMA Channel Select Enable */
14266 #define ETH_MACL3L4C0R_DMCHN0_Pos                      (24U)
14267 #define ETH_MACL3L4C0R_DMCHN0_Msk                      (0x1UL << ETH_MACL3L4C0R_DMCHN0_Pos) /*!< 0x01000000 */
14268 #define ETH_MACL3L4C0R_DMCHN0                          ETH_MACL3L4C0R_DMCHN0_Msk /* DMA Channel Number */
14269 #define ETH_MACL3L4C0R_L4DPIM0_Pos                     (21U)
14270 #define ETH_MACL3L4C0R_L4DPIM0_Msk                     (0x1UL << ETH_MACL3L4C0R_L4DPIM0_Pos) /*!< 0x00200000 */
14271 #define ETH_MACL3L4C0R_L4DPIM0                         ETH_MACL3L4C0R_L4DPIM0_Msk /* Layer 4 Destination Port Inverse Match Enable */
14272 #define ETH_MACL3L4C0R_L4DPM0_Pos                      (20U)
14273 #define ETH_MACL3L4C0R_L4DPM0_Msk                      (0x1UL << ETH_MACL3L4C0R_L4DPM0_Pos) /*!< 0x00100000 */
14274 #define ETH_MACL3L4C0R_L4DPM0                          ETH_MACL3L4C0R_L4DPM0_Msk  /* Layer 4 Destination Port Match Enable */
14275 #define ETH_MACL3L4C0R_L4SPIM0_Pos                     (19U)
14276 #define ETH_MACL3L4C0R_L4SPIM0_Msk                     (0x1UL << ETH_MACL3L4C0R_L4SPIM0_Pos) /*!< 0x00080000 */
14277 #define ETH_MACL3L4C0R_L4SPIM0                         ETH_MACL3L4C0R_L4SPIM0_Msk /* Layer 4 Source Port Inverse Match Enable */
14278 #define ETH_MACL3L4C0R_L4SPM0_Pos                      (18U)
14279 #define ETH_MACL3L4C0R_L4SPM0_Msk                      (0x1UL << ETH_MACL3L4C0R_L4SPM0_Pos) /*!< 0x00040000 */
14280 #define ETH_MACL3L4C0R_L4SPM0                          ETH_MACL3L4C0R_L4SPM0_Msk  /* Layer 4 Source Port Match Enable */
14281 #define ETH_MACL3L4C0R_L4PEN0_Pos                      (16U)
14282 #define ETH_MACL3L4C0R_L4PEN0_Msk                      (0x1UL << ETH_MACL3L4C0R_L4PEN0_Pos) /*!< 0x00010000 */
14283 #define ETH_MACL3L4C0R_L4PEN0                          ETH_MACL3L4C0R_L4PEN0_Msk  /* Layer 4 Protocol Enable */
14284 #define ETH_MACL3L4C0R_L3HDBM0_Pos                     (11U)
14285 #define ETH_MACL3L4C0R_L3HDBM0_Msk                     (0x1FUL << ETH_MACL3L4C0R_L3HDBM0_Pos) /*!< 0x0000F800 */
14286 #define ETH_MACL3L4C0R_L3HDBM0                         ETH_MACL3L4C0R_L3HDBM0_Msk /* Layer 3 IP DA Higher Bits Match */
14287 #define ETH_MACL3L4C0R_L3HSBM0_Pos                     (6U)
14288 #define ETH_MACL3L4C0R_L3HSBM0_Msk                     (0x1FUL << ETH_MACL3L4C0R_L3HSBM0_Pos) /*!< 0x000007C0 */
14289 #define ETH_MACL3L4C0R_L3HSBM0                         ETH_MACL3L4C0R_L3HSBM0_Msk /* Layer 3 IP SA Higher Bits Match */
14290 #define ETH_MACL3L4C0R_L3DAIM0_Pos                     (5U)
14291 #define ETH_MACL3L4C0R_L3DAIM0_Msk                     (0x1UL << ETH_MACL3L4C0R_L3DAIM0_Pos) /*!< 0x00000020 */
14292 #define ETH_MACL3L4C0R_L3DAIM0                         ETH_MACL3L4C0R_L3DAIM0_Msk /* Layer 3 IP DA Inverse Match Enable */
14293 #define ETH_MACL3L4C0R_L3DAM0_Pos                      (4U)
14294 #define ETH_MACL3L4C0R_L3DAM0_Msk                      (0x1UL << ETH_MACL3L4C0R_L3DAM0_Pos) /*!< 0x00000010 */
14295 #define ETH_MACL3L4C0R_L3DAM0                          ETH_MACL3L4C0R_L3DAM0_Msk  /* Layer 3 IP DA Match Enable */
14296 #define ETH_MACL3L4C0R_L3SAIM0_Pos                     (3U)
14297 #define ETH_MACL3L4C0R_L3SAIM0_Msk                     (0x1UL << ETH_MACL3L4C0R_L3SAIM0_Pos) /*!< 0x00000008 */
14298 #define ETH_MACL3L4C0R_L3SAIM0                         ETH_MACL3L4C0R_L3SAIM0_Msk /* Layer 3 IP SA Inverse Match Enable */
14299 #define ETH_MACL3L4C0R_L3SAM0_Pos                      (2U)
14300 #define ETH_MACL3L4C0R_L3SAM0_Msk                      (0x1UL << ETH_MACL3L4C0R_L3SAM0_Pos) /*!< 0x00000004 */
14301 #define ETH_MACL3L4C0R_L3SAM0                          ETH_MACL3L4C0R_L3SAM0_Msk  /* Layer 3 IP SA Match Enable*/
14302 #define ETH_MACL3L4C0R_L3PEN0_Pos                      (0U)
14303 #define ETH_MACL3L4C0R_L3PEN0_Msk                      (0x1UL << ETH_MACL3L4C0R_L3PEN0_Pos) /*!< 0x00000001 */
14304 #define ETH_MACL3L4C0R_L3PEN0                          ETH_MACL3L4C0R_L3PEN0_Msk  /* Layer 3 Protocol Enable */
14305 
14306 /************ Bit definition for Ethernet MAC Layer4 Address filter Register   ***************/
14307 #define ETH_MACL4A0R_L4DP0_Pos                        (16U)
14308 #define ETH_MACL4A0R_L4DP0_Msk                        (0xFFFFUL << ETH_MACL4A0R_L4DP0_Pos) /*!< 0xFFFF0000 */
14309 #define ETH_MACL4A0R_L4DP0                            ETH_MACL4A0R_L4DP0_Msk     /* Layer 4 Destination Port Number Field */
14310 #define ETH_MACL4A0R_L4SP0_Pos                        (0U)
14311 #define ETH_MACL4A0R_L4SP0_Msk                        (0xFFFFUL << ETH_MACL4A0R_L4SP0_Pos) /*!< 0x0000FFFF */
14312 #define ETH_MACL4A0R_L4SP0                            ETH_MACL4A0R_L4SP0_Msk     /* Layer 4 Source Port Number Field */
14313 
14314 /************ Bit definition for Ethernet MAC Layer3 Address 0 Register   ***************/
14315 #define ETH_MACL3A0R_L3A0_Pos                         (0U)
14316 #define ETH_MACL3A0R_L3A0_Msk                         (0xFFFFFFFFUL << ETH_MACL3A0R_L3A0_Pos) /*!< 0xFFFFFFFF */
14317 #define ETH_MACL3A0R_L3A0                             ETH_MACL3A0R_L3A0_Msk    /* Layer 3 Address 0 Field */
14318 
14319 /************ Bit definition for Ethernet MAC Layer3 Address 1 Register   ***************/
14320 #define ETH_MACL3A1R_L3A1_Pos                         (0U)
14321 #define ETH_MACL3A1R_L3A1_Msk                         (0xFFFFFFFFUL << ETH_MACL3A1R_L3A1_Pos) /*!< 0xFFFFFFFF */
14322 #define ETH_MACL3A1R_L3A1                             ETH_MACL3A1R_L3A1_Msk    /* Layer 3 Address 1 Field */
14323 
14324 /************ Bit definition for Ethernet MAC Layer3 Address 2 Register   ***************/
14325 #define ETH_MACL3A2R_L3A2_Pos                         (0U)
14326 #define ETH_MACL3A2R_L3A2_Msk                         (0xFFFFFFFFUL << ETH_MACL3A2R_L3A2_Pos) /*!< 0xFFFFFFFF */
14327 #define ETH_MACL3A2R_L3A2                             ETH_MACL3A2R_L3A2_Msk    /* Layer 3 Address 2 Field */
14328 
14329 /************ Bit definition for Ethernet MAC Layer3 Address 3 Register   ***************/
14330 #define ETH_MACL3A3R_L3A3_Pos                         (0U)
14331 #define ETH_MACL3A3R_L3A3_Msk                         (0xFFFFFFFFUL << ETH_MACL3A3R_L3A3_Pos) /*!< 0xFFFFFFFF */
14332 #define ETH_MACL3A3R_L3A3                             ETH_MACL3A3R_L3A3_Msk    /* Layer 3 Address 3 Field */
14333 
14334 /************ Bit definition for Ethernet MAC Indirect Access Control Register   ***************/
14335 #define ETH_MACIACR_MSEL_Pos                           (16U)
14336 #define ETH_MACIACR_MSEL_Msk                           (0xFUL << ETH_MACIACR_MSEL_Pos) /*!< 0x000F0000 */
14337 #define ETH_MACIACR_MSEL                               ETH_MACIACR_MSEL_Msk    /* Mode Select */
14338 #define ETH_MACIACR_MSEL_RXQ                           ((uint32_t)0x00000000)   /* Type-based RXQ mapping */
14339 #define ETH_MACIACR_AOFF_Pos                           (8U)
14340 #define ETH_MACIACR_AOFF_Msk                           (0xFFUL << ETH_MACIACR_AOFF_Pos) /*!< 0x0000FF00 */
14341 #define ETH_MACIACR_AOFF                               ETH_MACIACR_AOFF_Msk    /* Address Offset */
14342 #define ETH_MACIACR_AOFF_IndReg0                       ((uint32_t)0x00000000)   /* Indirect register 0 */
14343 #define ETH_MACIACR_AOFF_IndReg1_Pos                   (8U)
14344 #define ETH_MACIACR_AOFF_IndReg1_Msk                   (0x1UL << ETH_MACIACR_AOFF_IndReg1_Pos) /*!< 0x00000100 */
14345 #define ETH_MACIACR_AOFF_IndReg1                       ETH_MACIACR_AOFF_IndReg1_Msk  /* Indirect register 1 */
14346 #define ETH_MACIACR_AOFF_IndReg2_Pos                   (9U)
14347 #define ETH_MACIACR_AOFF_IndReg2_Msk                   (0x1UL << ETH_MACIACR_AOFF_IndReg2_Pos) /*!< 0x00000200 */
14348 #define ETH_MACIACR_AOFF_IndReg2                       ETH_MACIACR_AOFF_IndReg2_Msk  /* Indirect register 2 */
14349 #define ETH_MACIACR_AOFF_IndReg3_Pos                   (8U)
14350 #define ETH_MACIACR_AOFF_IndReg3_Msk                   (0x3UL << ETH_MACIACR_AOFF_IndReg3_Pos) /*!< 0x00000300 */
14351 #define ETH_MACIACR_AOFF_IndReg3                       ETH_MACIACR_AOFF_IndReg3_Msk  /* Indirect register 3 */
14352 #define ETH_MACIACR_AOFF_IndReg4_Pos                   (10U)
14353 #define ETH_MACIACR_AOFF_IndReg4_Msk                   (0x1UL << ETH_MACIACR_AOFF_IndReg4_Pos) /*!< 0x00000400 */
14354 #define ETH_MACIACR_AOFF_IndReg4                       ETH_MACIACR_AOFF_IndReg4_Msk  /* Indirect register 4 */
14355 #define ETH_MACIACR_AOFF_IndReg5_Pos                   (8U)
14356 #define ETH_MACIACR_AOFF_IndReg5_Msk                   (0x5UL << ETH_MACIACR_AOFF_IndReg5_Pos) /*!< 0x00000500 */
14357 #define ETH_MACIACR_AOFF_IndReg5                       ETH_MACIACR_AOFF_IndReg5_Msk  /* Indirect register 5 */
14358 #define ETH_MACIACR_AOFF_IndReg6_Pos                   (9U)
14359 #define ETH_MACIACR_AOFF_IndReg6_Msk                   (0x3UL << ETH_MACIACR_AOFF_IndReg6_Pos) /*!< 0x00000600 */
14360 #define ETH_MACIACR_AOFF_IndReg6                       ETH_MACIACR_AOFF_IndReg6_Msk  /* Indirect register 6 */
14361 #define ETH_MACIACR_AOFF_IndReg7_Pos                   (8U)
14362 #define ETH_MACIACR_AOFF_IndReg7_Msk                   (0x7UL << ETH_MACIACR_AOFF_IndReg7_Pos) /*!< 0x00000700 */
14363 #define ETH_MACIACR_AOFF_IndReg7                       ETH_MACIACR_AOFF_IndReg7_Msk  /* Indirect register 7 */
14364 #define ETH_MACIACR_AUTO_Pos                           (5U)
14365 #define ETH_MACIACR_AUTO_Msk                           (0x1UL << ETH_MACIACR_AUTO_Pos) /*!< 0x00000020 */
14366 #define ETH_MACIACR_AUTO                               ETH_MACIACR_AUTO_Msk    /* Auto-increment */
14367 #define ETH_MACIACR_COM_Pos                            (1U)
14368 #define ETH_MACIACR_COM_Msk                            (0x1UL << ETH_MACIACR_COM_Pos) /*!< 0x00000002 */
14369 #define ETH_MACIACR_COM                                ETH_MACIACR_COM_Msk    /* Command type: 1: read operation / 0: write operation */
14370 #define ETH_MACIACR_OB_Pos                             (0U)
14371 #define ETH_MACIACR_OB_Msk                             (0x1UL << ETH_MACIACR_OB_Pos) /*!< 0x00000001 */
14372 #define ETH_MACIACR_OB                                 ETH_MACIACR_OB_Msk    /* Operation Busy */
14373 
14374 /************ Bit definition for Ethernet MAC type-based Rx Queue mapping Register   ***************/
14375 #define ETH_MACTMRQR_PFEX_Pos                          (20U)
14376 #define ETH_MACTMRQR_PFEX_Msk                          (0x1UL << ETH_MACTMRQR_PFEX_Pos) /*!< 0x00100000 */
14377 #define ETH_MACTMRQR_PFEX                              ETH_MACTMRQR_PFEX_Msk    /* Preemption or Express Packet */
14378 #define ETH_MACTMRQR_TMRQ_Pos                          (16U)
14379 #define ETH_MACTMRQR_TMRQ_Msk                          (0x7UL << ETH_MACTMRQR_TMRQ_Pos) /*!< 0x00070000 */
14380 #define ETH_MACTMRQR_TMRQ                              ETH_MACTMRQR_TMRQ_Msk    /* Type Match Rx Queue Number */
14381 #define ETH_MACTMRQR_TYP_Pos                           (0U)
14382 #define ETH_MACTMRQR_TYP_Msk                           (0xFFFFUL << ETH_MACTMRQR_TYP_Pos) /*!< 0x0000FFFF */
14383 #define ETH_MACTMRQR_TYP                               ETH_MACTMRQR_TYP_Msk    /* Type field Value */
14384 
14385 /************ Bit definition for Ethernet MAC Timestamp Control Register   ***************/
14386 #define ETH_MACTSCR_AV8021ASMEN_Pos                   (28U)
14387 #define ETH_MACTSCR_AV8021ASMEN_Msk                   (0x1UL << ETH_MACTSCR_AV8021ASMEN_Pos) /*!< 0x10000000 */
14388 #define ETH_MACTSCR_AV8021ASMEN                       ETH_MACTSCR_AV8021ASMEN_Msk  /* AV 802.1AS Mode Enable */
14389 #define ETH_MACTSCR_TXTSSTSM_Pos                      (24U)
14390 #define ETH_MACTSCR_TXTSSTSM_Msk                      (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */
14391 #define ETH_MACTSCR_TXTSSTSM                          ETH_MACTSCR_TXTSSTSM_Msk  /* Transmit Timestamp Status Mode */
14392 #define ETH_MACTSCR_ESTI_Pos                          (20U)
14393 #define ETH_MACTSCR_ESTI_Msk                          (0x1UL << ETH_MACTSCR_ESTI_Pos) /*!< 0x00100000 */
14394 #define ETH_MACTSCR_ESTI                              ETH_MACTSCR_ESTI_Msk  /* External System Time Input */
14395 #define ETH_MACTSCR_TSENMACADDR_Pos                   (18U)
14396 #define ETH_MACTSCR_TSENMACADDR_Msk                   (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */
14397 #define ETH_MACTSCR_TSENMACADDR                       ETH_MACTSCR_TSENMACADDR_Msk  /* Enable MAC Address for PTP Packet Filtering */
14398 #define ETH_MACTSCR_SNAPTYPSEL_Pos                    (16U)
14399 #define ETH_MACTSCR_SNAPTYPSEL_Msk                    (0x3UL << ETH_MACTSCR_SNAPTYPSEL_Pos) /*!< 0x00030000 */
14400 #define ETH_MACTSCR_SNAPTYPSEL                        ETH_MACTSCR_SNAPTYPSEL_Msk  /* Select PTP packets for Taking Snapshots */
14401 #define ETH_MACTSCR_TSMSTRENA_Pos                     (15U)
14402 #define ETH_MACTSCR_TSMSTRENA_Msk                     (0x1UL << ETH_MACTSCR_TSMSTRENA_Pos) /*!< 0x00008000 */
14403 #define ETH_MACTSCR_TSMSTRENA                         ETH_MACTSCR_TSMSTRENA_Msk  /* Enable Snapshot for Messages Relevant to Master */
14404 #define ETH_MACTSCR_TSEVNTENA_Pos                     (14U)
14405 #define ETH_MACTSCR_TSEVNTENA_Msk                     (0x1UL << ETH_MACTSCR_TSEVNTENA_Pos) /*!< 0x00004000 */
14406 #define ETH_MACTSCR_TSEVNTENA                         ETH_MACTSCR_TSEVNTENA_Msk  /* Enable Timestamp Snapshot for Event Messages */
14407 #define ETH_MACTSCR_TSIPV4ENA_Pos                     (13U)
14408 #define ETH_MACTSCR_TSIPV4ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV4ENA_Pos) /*!< 0x00002000 */
14409 #define ETH_MACTSCR_TSIPV4ENA                         ETH_MACTSCR_TSIPV4ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv4-UDP */
14410 #define ETH_MACTSCR_TSIPV6ENA_Pos                     (12U)
14411 #define ETH_MACTSCR_TSIPV6ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV6ENA_Pos) /*!< 0x00001000 */
14412 #define ETH_MACTSCR_TSIPV6ENA                         ETH_MACTSCR_TSIPV6ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv6-UDP */
14413 #define ETH_MACTSCR_TSIPENA_Pos                       (11U)
14414 #define ETH_MACTSCR_TSIPENA_Msk                       (0x1UL << ETH_MACTSCR_TSIPENA_Pos) /*!< 0x00000800 */
14415 #define ETH_MACTSCR_TSIPENA                           ETH_MACTSCR_TSIPENA_Msk  /* Enable Processing of PTP over Ethernet Packets */
14416 #define ETH_MACTSCR_TSVER2ENA_Pos                     (10U)
14417 #define ETH_MACTSCR_TSVER2ENA_Msk                     (0x1UL << ETH_MACTSCR_TSVER2ENA_Pos) /*!< 0x00000400 */
14418 #define ETH_MACTSCR_TSVER2ENA                         ETH_MACTSCR_TSVER2ENA_Msk  /* Enable PTP Packet Processing for Version 2 Format */
14419 #define ETH_MACTSCR_TSCTRLSSR_Pos                     (9U)
14420 #define ETH_MACTSCR_TSCTRLSSR_Msk                     (0x1UL << ETH_MACTSCR_TSCTRLSSR_Pos) /*!< 0x00000200 */
14421 #define ETH_MACTSCR_TSCTRLSSR                         ETH_MACTSCR_TSCTRLSSR_Msk  /* Timestamp Digital or Binary Rollover Control */
14422 #define ETH_MACTSCR_TSENALL_Pos                       (8U)
14423 #define ETH_MACTSCR_TSENALL_Msk                       (0x1UL << ETH_MACTSCR_TSENALL_Pos) /*!< 0x00000100 */
14424 #define ETH_MACTSCR_TSENALL                           ETH_MACTSCR_TSENALL_Msk  /* Enable Timestamp for All Packets */
14425 #define ETH_MACTSCR_PTGE_Pos                          (6U)
14426 #define ETH_MACTSCR_PTGE_Msk                          (0x1UL << ETH_MACTSCR_PTGE_Pos) /*!< 0x00000040 */
14427 #define ETH_MACTSCR_PTGE                              ETH_MACTSCR_PTGE_Msk  /* Presentation Time Generation Enable */
14428 #define ETH_MACTSCR_TSADDREG_Pos                      (5U)
14429 #define ETH_MACTSCR_TSADDREG_Msk                      (0x1UL << ETH_MACTSCR_TSADDREG_Pos) /*!< 0x00000020 */
14430 #define ETH_MACTSCR_TSADDREG                          ETH_MACTSCR_TSADDREG_Msk  /* Update Addend Register */
14431 #define ETH_MACTSCR_TSUPDT_Pos                        (3U)
14432 #define ETH_MACTSCR_TSUPDT_Msk                        (0x1UL << ETH_MACTSCR_TSUPDT_Pos) /*!< 0x00000008 */
14433 #define ETH_MACTSCR_TSUPDT                            ETH_MACTSCR_TSUPDT_Msk  /* Update Timestamp */
14434 #define ETH_MACTSCR_TSINIT_Pos                        (2U)
14435 #define ETH_MACTSCR_TSINIT_Msk                        (0x1UL << ETH_MACTSCR_TSINIT_Pos) /*!< 0x00000004 */
14436 #define ETH_MACTSCR_TSINIT                             ETH_MACTSCR_TSINIT_Msk  /* Initialize Timestamp */
14437 #define ETH_MACTSCR_TSCFUPDT_Pos                      (1U)
14438 #define ETH_MACTSCR_TSCFUPDT_Msk                      (0x1UL << ETH_MACTSCR_TSCFUPDT_Pos) /*!< 0x00000002 */
14439 #define ETH_MACTSCR_TSCFUPDT                          ETH_MACTSCR_TSCFUPDT_Msk  /* Fine or Coarse Timestamp Update*/
14440 #define ETH_MACTSCR_TSENA_Pos                         (0U)
14441 #define ETH_MACTSCR_TSENA_Msk                         (0x1UL << ETH_MACTSCR_TSENA_Pos) /*!< 0x00000001 */
14442 #define ETH_MACTSCR_TSENA                             ETH_MACTSCR_TSENA_Msk  /* Enable Timestamp */
14443 
14444 /************ Bit definition for Ethernet MAC Sub-second Increment Register   ***************/
14445 #define ETH_MACMACSSIR_SSINC_Pos                      (16U)
14446 #define ETH_MACMACSSIR_SSINC_Msk                      (0xFFUL << ETH_MACMACSSIR_SSINC_Pos) /*!< 0x0000FF00 */
14447 #define ETH_MACMACSSIR_SSINC                          ETH_MACMACSSIR_SSINC_Msk  /* Sub-second Increment Value */
14448 
14449 /************ Bit definition for Ethernet MAC System Time Seconds Register   ***************/
14450 #define ETH_MACSTSR_TSS_Pos                           (0U)
14451 #define ETH_MACSTSR_TSS_Msk                           (0xFFFFFFFFUL << ETH_MACSTSR_TSS_Pos) /*!< 0xFFFFFFFF */
14452 #define ETH_MACSTSR_TSS                               ETH_MACSTSR_TSS_Msk  /* Timestamp Second */
14453 
14454 /************ Bit definition for Ethernet MAC System Time Nanoseconds Register   ***************/
14455 #define ETH_MACSTNR_TSSS_Pos                          (0U)
14456 #define ETH_MACSTNR_TSSS_Msk                          (0x7FFFFFFFUL << ETH_MACSTNR_TSSS_Pos) /*!< 0x7FFFFFFF */
14457 #define ETH_MACSTNR_TSSS                              ETH_MACSTNR_TSSS_Msk  /* Timestamp Sub-seconds */
14458 
14459 /************ Bit definition for Ethernet MAC System Time Seconds Update Register   ***************/
14460 #define ETH_MACSTSUR_TSS_Pos                          (0U)
14461 #define ETH_MACSTSUR_TSS_Msk                          (0xFFFFFFFFUL << ETH_MACSTSUR_TSS_Pos) /*!< 0xFFFFFFFF */
14462 #define ETH_MACSTSUR_TSS                              ETH_MACSTSUR_TSS_Msk  /* Timestamp Seconds */
14463 
14464 /************ Bit definition for Ethernet MAC System Time Nanoseconds Update Register   ***************/
14465 #define ETH_MACSTNUR_ADDSUB_Pos                       (31U)
14466 #define ETH_MACSTNUR_ADDSUB_Msk                       (0x1UL << ETH_MACSTNUR_ADDSUB_Pos) /*!< 0x80000000 */
14467 #define ETH_MACSTNUR_ADDSUB                           ETH_MACSTNUR_ADDSUB_Msk  /* Add or Subtract Time */
14468 #define ETH_MACSTNUR_TSSS_Pos                         (0U)
14469 #define ETH_MACSTNUR_TSSS_Msk                         (0x7FFFFFFFUL << ETH_MACSTNUR_TSSS_Pos) /*!< 0x7FFFFFFF */
14470 #define ETH_MACSTNUR_TSSS                             ETH_MACSTNUR_TSSS_Msk  /* Timestamp Sub-seconds */
14471 
14472 /************ Bit definition for Ethernet MAC Timestamp Addend Register   ***************/
14473 #define ETH_MACTSAR_TSAR_Pos                          (0U)
14474 #define ETH_MACTSAR_TSAR_Msk                          (0xFFFFFFFFUL << ETH_MACTSAR_TSAR_Pos) /*!< 0xFFFFFFFF */
14475 #define ETH_MACTSAR_TSAR                              ETH_MACTSAR_TSAR_Msk  /* Timestamp Addend Register */
14476 
14477 /************ Bit definition for Ethernet MAC Timestamp Status Register   ***************/
14478 #define ETH_MACTSSR_ATSNS_Pos                         (25U)
14479 #define ETH_MACTSSR_ATSNS_Msk                         (0x1FUL << ETH_MACTSSR_ATSNS_Pos) /*!< 0x3E000000 */
14480 #define ETH_MACTSSR_ATSNS                             ETH_MACTSSR_ATSNS_Msk  /* Number of Auxiliary Timestamp Snapshots */
14481 #define ETH_MACTSSR_ATSSTM_Pos                        (24U)
14482 #define ETH_MACTSSR_ATSSTM_Msk                        (0x1UL << ETH_MACTSSR_ATSSTM_Pos) /*!< 0x01000000 */
14483 #define ETH_MACTSSR_ATSSTM                            ETH_MACTSSR_ATSSTM_Msk  /* Auxiliary Timestamp Snapshot Trigger Missed */
14484 #define ETH_MACTSSR_ATSSTN_Pos                        (16U)
14485 #define ETH_MACTSSR_ATSSTN_Msk                        (0xFUL << ETH_MACTSSR_ATSSTN_Pos) /*!< 0x000F0000 */
14486 #define ETH_MACTSSR_ATSSTN                            ETH_MACTSSR_ATSSTN_Msk  /* Auxiliary Timestamp Snapshot Trigger Identifier */
14487 #define ETH_MACTSSR_TXTSSIS_Pos                       (15U)
14488 #define ETH_MACTSSR_TXTSSIS_Msk                       (0x1UL << ETH_MACTSSR_TXTSSIS_Pos) /*!< 0x00008000 */
14489 #define ETH_MACTSSR_TXTSSIS                           ETH_MACTSSR_TXTSSIS_Msk  /* Tx Timestamp Status Interrupt Status */
14490 #define ETH_MACTSSR_TSTRGTERR1_Pos                    (5U)
14491 #define ETH_MACTSSR_TSTRGTERR1_Msk                    (0x1UL << ETH_MACTSSR_TSTRGTERR1_Pos) /*!< 0x00000020 */
14492 #define ETH_MACTSSR_TSTRGTERR1                        ETH_MACTSSR_TSTRGTERR1_Msk  /* Timestamp Target Time Error */
14493 #define ETH_MACTSSR_TSTARGT1_Pos                      (4U)
14494 #define ETH_MACTSSR_TSTARGT1_Msk                      (0x1UL << ETH_MACTSSR_TSTARGT1_Pos) /*!< 0x00000010 */
14495 #define ETH_MACTSSR_TSTARGT1                          ETH_MACTSSR_TSTARGT1_Msk  /* Timestamp Target Time Reached */
14496 #define ETH_MACTSSR_TSTRGTERR0_Pos                    (3U)
14497 #define ETH_MACTSSR_TSTRGTERR0_Msk                    (0x1UL << ETH_MACTSSR_TSTRGTERR0_Pos) /*!< 0x00000008 */
14498 #define ETH_MACTSSR_TSTRGTERR0                        ETH_MACTSSR_TSTRGTERR0_Msk  /* Timestamp Target Time Error */
14499 #define ETH_MACTSSR_AUXTSTRIG_Pos                     (2U)
14500 #define ETH_MACTSSR_AUXTSTRIG_Msk                     (0x1UL << ETH_MACTSSR_AUXTSTRIG_Pos) /*!< 0x00000004 */
14501 #define ETH_MACTSSR_AUXTSTRIG                         ETH_MACTSSR_AUXTSTRIG_Msk  /* Auxiliary Timestamp Trigger Snapshot*/
14502 #define ETH_MACTSSR_TSTARGT0_Pos                      (1U)
14503 #define ETH_MACTSSR_TSTARGT0_Msk                      (0x1UL << ETH_MACTSSR_TSTARGT0_Pos) /*!< 0x00000002 */
14504 #define ETH_MACTSSR_TSTARGT0                          ETH_MACTSSR_TSTARGT0_Msk  /* Timestamp Target Time Reached */
14505 #define ETH_MACTSSR_TSSOVF_Pos                        (0U)
14506 #define ETH_MACTSSR_TSSOVF_Msk                        (0x1UL << ETH_MACTSSR_TSSOVF_Pos) /*!< 0x00000001 */
14507 #define ETH_MACTSSR_TSSOVF                            ETH_MACTSSR_TSSOVF_Msk  /* Timestamp Seconds Overflow */
14508 
14509 /************ Bit definition for Ethernet MAC Tx Timestamp Status Nanoseconds Register   ***************/
14510 #define ETH_MACTXTSSNR_TXTSSMIS_Pos                    (31U)
14511 #define ETH_MACTXTSSNR_TXTSSMIS_Msk                    (0x1UL << ETH_MACTXTSSNR_TXTSSMIS_Pos) /*!< 0x80000000 */
14512 #define ETH_MACTXTSSNR_TXTSSMIS                        ETH_MACTXTSSNR_TXTSSMIS_Msk  /* Transmit Timestamp Status Missed */
14513 #define ETH_MACTXTSSNR_TXTSSLO_Pos                     (0U)
14514 #define ETH_MACTXTSSNR_TXTSSLO_Msk                     (0x7FFFFFFFUL << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x7FFFFFFF */
14515 #define ETH_MACTXTSSNR_TXTSSLO                         ETH_MACTXTSSNR_TXTSSLO_Msk  /* Transmit Timestamp Status Low */
14516 /************ Bit definition for Ethernet MAC Tx Timestamp Status Seconds Register   ***************/
14517 #define ETH_MACTXTSSSR_TXTSSHI_Pos                     (0U)
14518 #define ETH_MACTXTSSSR_TXTSSHI_Msk                     (0xFFFFFFFFUL << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0xFFFFFFFF */
14519 #define ETH_MACTXTSSSR_TXTSSHI                         ETH_MACTXTSSSR_TXTSSHI_Msk  /* Transmit Timestamp Status High */
14520 
14521 /************ Bit definition for Ethernet MAC Auxiliary Control Register   ***************/
14522 #define ETH_MACACR_ATSEN3_Pos                         (7U)
14523 #define ETH_MACACR_ATSEN3_Msk                         (0x1UL << ETH_MACACR_ATSEN3_Pos) /*!< 0x00000080 */
14524 #define ETH_MACACR_ATSEN3                             ETH_MACACR_ATSEN3_Msk  /* Auxiliary Snapshot 3 Enable */
14525 #define ETH_MACACR_ATSEN2_Pos                         (6U)
14526 #define ETH_MACACR_ATSEN2_Msk                         (0x1UL << ETH_MACACR_ATSEN2_Pos) /*!< 0x00000040 */
14527 #define ETH_MACACR_ATSEN2                             ETH_MACACR_ATSEN2_Msk  /* Auxiliary Snapshot 2 Enable */
14528 #define ETH_MACACR_ATSEN1_Pos                         (5U)
14529 #define ETH_MACACR_ATSEN1_Msk                         (0x1UL << ETH_MACACR_ATSEN1_Pos) /*!< 0x00000020 */
14530 #define ETH_MACACR_ATSEN1                             ETH_MACACR_ATSEN1_Msk  /* Auxiliary Snapshot 1 Enable */
14531 #define ETH_MACACR_ATSEN0_Pos                         (4U)
14532 #define ETH_MACACR_ATSEN0_Msk                         (0x1UL << ETH_MACACR_ATSEN0_Pos) /*!< 0x00000010 */
14533 #define ETH_MACACR_ATSEN0                             ETH_MACACR_ATSEN0_Msk  /* Auxiliary Snapshot 0 Enable */
14534 #define ETH_MACACR_ATSFC_Pos                          (0U)
14535 #define ETH_MACACR_ATSFC_Msk                          (0x1UL << ETH_MACACR_ATSFC_Pos) /*!< 0x00000001 */
14536 #define ETH_MACACR_ATSFC                              ETH_MACACR_ATSFC_Msk  /* Auxiliary Snapshot FIFO Clear */
14537 
14538 /************ Bit definition for Ethernet MAC Auxiliary Timestamp Nanoseconds Register   ***************/
14539 #define ETH_MACATSNR_AUXTSLO_Pos                      (0U)
14540 #define ETH_MACATSNR_AUXTSLO_Msk                      (0x7FFFFFFFUL << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x7FFFFFFF */
14541 #define ETH_MACATSNR_AUXTSLO                          ETH_MACATSNR_AUXTSLO_Msk  /* Auxiliary Timestamp */
14542 
14543 /************ Bit definition for Ethernet MAC Auxiliary Timestamp Seconds Register   ***************/
14544 #define ETH_MACATSSR_AUXTSHI_Pos                      (0U)
14545 #define ETH_MACATSSR_AUXTSHI_Msk                      (0xFFFFFFFFUL << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0xFFFFFFFF */
14546 #define ETH_MACATSSR_AUXTSHI                          ETH_MACATSSR_AUXTSHI_Msk  /* Auxiliary Timestamp */
14547 
14548 /************ Bit definition for Ethernet MAC Timestamp Ingress Asymmetric Correction Register   ***************/
14549 #define ETH_MACTSIACR_OSTIAC_Pos                      (0U)
14550 #define ETH_MACTSIACR_OSTIAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0xFFFFFFFF */
14551 #define ETH_MACTSIACR_OSTIAC                          ETH_MACTSIACR_OSTIAC_Msk  /* One-Step Timestamp Ingress Asymmetry Correction */
14552 
14553 /************ Bit definition for Ethernet MAC Timestamp Egress Asymmetric Correction  ***************/
14554 #define ETH_MACTSEACR_OSTEAC_Pos                      (0U)
14555 #define ETH_MACTSEACR_OSTEAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0xFFFFFFFF */
14556 #define ETH_MACTSEACR_OSTEAC                          ETH_MACTSEACR_OSTEAC_Msk  /* One-Step Timestamp Egress Asymmetry Correction */
14557 
14558 /************ Bit definition for Ethernet MAC Timestamp Ingress Correction Nanosecond   ***************/
14559 #define ETH_MACTSICNR_TSIC_Pos                        (0U)
14560 #define ETH_MACTSICNR_TSIC_Msk                        (0xFFFFFFFFUL << ETH_MACTSICNR_TSIC_Pos) /*!< 0xFFFFFFFF */
14561 #define ETH_MACTSICNR_TSIC                            ETH_MACTSICNR_TSIC_Msk  /* Timestamp Ingress Correction */
14562 
14563 /************ Bit definition for Ethernet MAC Timestamp Egress correction Nanosecond   ***************/
14564 #define ETH_MACTSECNR_TSEC_Pos                        (0U)
14565 #define ETH_MACTSECNR_TSEC_Msk                        (0xFFFFFFFFUL << ETH_MACTSECNR_TSEC_Pos) /*!< 0xFFFFFFFF */
14566 #define ETH_MACTSECNR_TSEC                            ETH_MACTSECNR_TSEC_Msk  /* Timestamp Egress Correction */
14567 
14568 /************ Bit definition for Ethernet MAC Timestamp Ingress Latency   ***************/
14569 #define ETH_MACTSILR_ITLNS_Pos                        (16U)
14570 #define ETH_MACTSILR_ITLNS_Msk                        (0xFFFUL << ETH_MACTSILR_ITLNS_Pos) /*!< 0x0FFF0000 */
14571 #define ETH_MACTSILR_ITLNS                            ETH_MACTSILR_ITLNS_Msk  /* Ingress Timestamp Latency, in nanoseconds */
14572 #define ETH_MACTSILR_ITLSNS_Pos                       (8U)
14573 #define ETH_MACTSILR_ITLSNS_Msk                       (0xFFUL << ETH_MACTSILR_ITLSNS_Pos) /*!< 0x0000FF00 */
14574 #define ETH_MACTSILR_ITLSNS                           ETH_MACTSILR_ITLSNS_Msk  /* Ingress Timestamp Latency, in subnanoseconds */
14575 
14576 /************ Bit definition for Ethernet MAC Timestamp Egress Latency Register   ***************/
14577 #define ETH_MACTSELR_ETLNS_Pos                        (16U)
14578 #define ETH_MACTSELR_ETLNS_Msk                        (0xFFFUL << ETH_MACTSILR_ITLNS_Pos) /*!< 0x0FFF0000 */
14579 #define ETH_MACTSELR_ETLNS                            ETH_MACTSILR_ITLNS_Msk  /* Egress Timestamp Latency, in nanoseconds */
14580 #define ETH_MACTSELR_ETLSNS_Pos                       (8U)
14581 #define ETH_MACTSELR_ETLSNS_Msk                       (0xFFUL << ETH_MACTSILR_ITLSNS_Pos) /*!< 0x0000FF00 */
14582 #define ETH_MACTSELR_ETLSNS                           ETH_MACTSILR_ITLSNS_Msk  /* Egress Timestamp Latency, in subnanoseconds */
14583 
14584 /************ Bit definition for Ethernet MAC PPS Control Register   ***************/
14585 #define ETH_MACPPSCR_TIMESEL_Pos                      (28U)
14586 #define ETH_MACPPSCR_TIMESEL_Msk                      (0x1UL << ETH_MACPPSCR_TIMESEL_Pos) /*!< 0x10000000 */
14587 #define ETH_MACPPSCR_TIMESEL                          ETH_MACPPSCR_TIMESEL_Msk  /* Time Select */
14588 #define ETH_MACPPSCR_MCGREN0_Pos                      (7U)
14589 #define ETH_MACPPSCR_MCGREN0_Msk                      (0x1UL << ETH_MACPPSCR_MCGREN0_Pos) /*!< 0x00000080 */
14590 #define ETH_MACPPSCR_MCGREN0                          ETH_MACPPSCR_MCGREN0_Msk  /* MCGR Mode Enable for PPS0 Output */
14591 #define ETH_MACPPSCR_MCGREN0_PPS                      ((uint32_t)0x00000000)   /* PPS mode */
14592 #define ETH_MACPPSCR_MCGREN0_MCGR_Pos                 (7U)
14593 #define ETH_MACPPSCR_MCGREN0_MCGR_Msk                 (0x1UL << ETH_MACPPSCR_MCGREN0_MCGR_Pos) /*!< 0x00000080 */
14594 #define ETH_MACPPSCR_MCGREN0_MCGR                     ETH_MACPPSCR_MCGREN0_MCGR_Msk  /* MCGR mode */
14595 #define ETH_MACPPSCR_TRGTMODSEL0_Pos                  (5U)
14596 #define ETH_MACPPSCR_TRGTMODSEL0_Msk                  (0x3UL << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000060 */
14597 #define ETH_MACPPSCR_TRGTMODSEL0                      ETH_MACPPSCR_TRGTMODSEL0_Msk  /* Target Time Register Mode for PPS Output */
14598 #define ETH_MACPPSCR_PPSEN0_Pos                       (4U)
14599 #define ETH_MACPPSCR_PPSEN0_Msk                       (0x1UL << ETH_MACPPSCR_PPSEN0_Pos) /*!< 0x00000010 */
14600 #define ETH_MACPPSCR_PPSEN0                           ETH_MACPPSCR_PPSEN0_Msk  /* Flexible PPS Output Mode Enable */
14601 #define ETH_MACPPSCR_PPSCTRL_Pos                      (0U)
14602 #define ETH_MACPPSCR_PPSCTRL_Msk                      (0xFUL << ETH_MACPPSCR_PPSCTRL_Pos) /*!< 0x0000000F */
14603 #define ETH_MACPPSCR_PPSCTRL                          ETH_MACPPSCR_PPSCTRL_Msk  /* PPS Output Frequency Control */
14604 
14605 /************ Bit definition for Ethernet MAC PPS x target time seconds Register   ***************/
14606 #define ETH_MACPPSTTSxR_TSTRH0_Pos                    (0U)
14607 #define ETH_MACPPSTTSxR_TSTRH0_Msk                    (0xFFFFFFFFUL << ETH_MACPPSTTSxR_TSTRH0_Pos) /*!< 0xFFFFFFFF */
14608 #define ETH_MACPPSTTSxR_TSTRH0                        ETH_MACPPSTTSxR_TSTRH0_Msk  /* PPS Target Time Seconds Register */
14609 
14610 /************ Bit definition for Ethernet MAC PPS x target time nanoseconds Register   ***************/
14611 #define ETH_MACPPSTTNxR_TRGTBUSY0_Pos                 (31U)
14612 #define ETH_MACPPSTTNxR_TRGTBUSY0_Msk                 (0x1UL << ETH_MACPPSTTNxR_TRGTBUSY0_Pos) /*!< 0x80000000 */
14613 #define ETH_MACPPSTTNxR_TRGTBUSY0                     ETH_MACPPSTTNxR_TRGTBUSY0_Msk  /* PPS Target Time Register Busy */
14614 #define ETH_MACPPSTTNxR_TTSL0_Pos                     (0U)
14615 #define ETH_MACPPSTTNxR_TTSL0_Msk                     (0x7FFFFFFFUL << ETH_MACPPSTTNxR_TTSL0_Pos) /*!< 0x7FFFFFFF */
14616 #define ETH_MACPPSTTNxR_TTSL0                         ETH_MACPPSTTNxR_TTSL0_Msk  /* Target Time Low for PPS Register */
14617 
14618 /************ Bit definition for Ethernet MAC PPS x Interval Register   ***************/
14619 #define ETH_MACPPSIxR_PPSINT0_Pos                     (0U)
14620 #define ETH_MACPPSIxR_PPSINT0_Msk                     (0xFFFFFFFFUL << ETH_MACPPSIxR_PPSINT0_Pos) /*!< 0xFFFFFFFF */
14621 #define ETH_MACPPSIxR_PPSINT0                         ETH_MACPPSIxR_PPSINT0_Msk  /* PPS Output Signal Interval */
14622 
14623 /************ Bit definition for Ethernet MAC PPS x Width Register   ***************/
14624 #define ETH_MACPPSWxR_PPSWIDTH0_Pos                   (0U)
14625 #define ETH_MACPPSWxR_PPSWIDTH0_Msk                   (0xFFFFFFFFUL << ETH_MACPPSWxR_PPSWIDTH0_Pos) /*!< 0xFFFFFFFF */
14626 #define ETH_MACPPSWxR_PPSWIDTH0                       ETH_MACPPSWxR_PPSWIDTH0_Msk  /* PPS Output Signal Width */
14627 
14628 /************ Bit definition for Ethernet MAC PTP Offload Control Register   ***************/
14629 #define ETH_MACPOCR_DN_Pos                            (8U)
14630 #define ETH_MACPOCR_DN_Msk                            (0xFFUL << ETH_MACPOCR_DN_Pos) /*!< 0x0000FF00 */
14631 #define ETH_MACPOCR_DN                                ETH_MACPOCR_DN_Msk  /* Domain Number */
14632 #define ETH_MACPOCR_PDRDIS_Pos                        (7U)
14633 #define ETH_MACPOCR_PDRDIS_Msk                        (0x1UL << ETH_MACPOCR_PDRDIS_Pos) /*!< 0x00000080 */
14634 #define ETH_MACPOCR_PDRDIS                            ETH_MACPOCR_PDRDIS_Msk  /* Disable Peer Delay Response response generation */
14635 #define ETH_MACPOCR_DRRDIS_Pos                        (6U)
14636 #define ETH_MACPOCR_DRRDIS_Msk                        (0x1UL << ETH_MACPOCR_DRRDIS_Pos) /*!< 0x00000040 */
14637 #define ETH_MACPOCR_DRRDIS                            ETH_MACPOCR_DRRDIS_Msk  /* Disable PTO Delay Request/Response response generation */
14638 #define ETH_MACPOCR_APDREQTRIG_Pos                    (5U)
14639 #define ETH_MACPOCR_APDREQTRIG_Msk                    (0x1UL << ETH_MACPOCR_APDREQTRIG_Pos) /*!< 0x00000020 */
14640 #define ETH_MACPOCR_APDREQTRIG                        ETH_MACPOCR_APDREQTRIG_Msk  /* Automatic PTP Pdelay_Req message Trigger */
14641 #define ETH_MACPOCR_ASYNCTRIG_Pos                     (4U)
14642 #define ETH_MACPOCR_ASYNCTRIG_Msk                     (0x1UL << ETH_MACPOCR_ASYNCTRIG_Pos) /*!< 0x00000010 */
14643 #define ETH_MACPOCR_ASYNCTRIG                         ETH_MACPOCR_ASYNCTRIG_Msk  /* Automatic PTP SYNC message Trigger */
14644 #define ETH_MACPOCR_APDREQEN_Pos                      (2U)
14645 #define ETH_MACPOCR_APDREQEN_Msk                      (0x1UL << ETH_MACPOCR_APDREQEN_Pos) /*!< 0x00000004 */
14646 #define ETH_MACPOCR_APDREQEN                          ETH_MACPOCR_APDREQEN_Msk  /* Automatic PTP Pdelay_Req message Enable */
14647 #define ETH_MACPOCR_ASYNCEN_Pos                       (1U)
14648 #define ETH_MACPOCR_ASYNCEN_Msk                       (0x1UL << ETH_MACPOCR_ASYNCEN_Pos) /*!< 0x00000002 */
14649 #define ETH_MACPOCR_ASYNCEN                           ETH_MACPOCR_ASYNCEN_Msk  /* Automatic PTP SYNC message Enable */
14650 #define ETH_MACPOCR_PTOEN_Pos                         (0U)
14651 #define ETH_MACPOCR_PTOEN_Msk                         (0x1UL << ETH_MACPOCR_PTOEN_Pos) /*!< 0x00000001 */
14652 #define ETH_MACPOCR_PTOEN                             ETH_MACPOCR_PTOEN_Msk  /* PTP Offload Enable */
14653 
14654 /************ Bit definition for Ethernet MAC PTP Source Port Identity 0 Register   ***************/
14655 #define ETH_MACSPI0R_SPI0_Pos                         (0U)
14656 #define ETH_MACSPI0R_SPI0_Msk                         (0xFFFFFFFFUL << ETH_MACSPI0R_SPI0_Pos) /*!< 0xFFFFFFFF */
14657 #define ETH_MACSPI0R_SPI0                             ETH_MACSPI0R_SPI0_Msk  /* Source Port Identity 0 */
14658 
14659 /************ Bit definition for Ethernet MAC PTP Source Port Identity 1 Register   ***************/
14660 #define ETH_MACSPI1R_SPI1_Pos                        (0U)
14661 #define ETH_MACSPI1R_SPI1_Msk                        (0xFFFFFFFFUL << ETH_MACSPI1R_SPI1_Pos) /*!< 0xFFFFFFFF */
14662 #define ETH_MACSPI1R_SPI1                            ETH_MACSPI1R_SPI1_Msk  /* Source Port Identity 1 */
14663 
14664 /************ Bit definition for Ethernet MAC PTP Source Port Identity 2 Register   ***************/
14665 #define ETH_MACSPI2R_SPI2_Pos                        (0U)
14666 #define ETH_MACSPI2R_SPI2_Msk                        (0xFFFFUL << ETH_MACSPI2R_SPI2_Pos) /*!< 0x0000FFFF */
14667 #define ETH_MACSPI2R_SPI2                            ETH_MACSPI2R_SPI2_Msk  /* Source Port Identity 2 */
14668 
14669 /************ Bit definition for Ethernet MAC Log Message Interval Register   ***************/
14670 #define ETH_MACLMIR_LMPDRI_Pos                       (24U)
14671 #define ETH_MACLMIR_LMPDRI_Msk                       (0xFFUL << ETH_MACLMIR_LMPDRI_Pos) /*!< 0xFF000000 */
14672 #define ETH_MACLMIR_LMPDRI                            ETH_MACLMIR_LMPDRI_Msk  /* Log Min Pdelay_Req Interval */
14673 #define ETH_MACLMIR_DRSYNCR_Pos                      (8U)
14674 #define ETH_MACLMIR_DRSYNCR_Msk                      (0x7UL << ETH_MACLMIR_DRSYNCR_Pos) /*!< 0x00000700 */
14675 #define ETH_MACLMIR_DRSYNCR                          ETH_MACLMIR_DRSYNCR_Msk  /* Delay_Req to SYNC Ratio */
14676 #define ETH_MACLMIR_LSI_Pos                          (0U)
14677 #define ETH_MACLMIR_LSI_Msk                          (0xFFUL << ETH_MACLMIR_LSI_Pos) /*!< 0x000000FF */
14678 #define ETH_MACLMIR_LSI                              ETH_MACLMIR_LSI_Msk  /* Log Sync Interval */
14679 
14680 /************ Bit definition for Ethernet MTL Operation Mode Register   ***************/
14681 #define ETH_MTLOMR_CNTCLR_Pos                        (9U)
14682 #define ETH_MTLOMR_CNTCLR_Msk                        (0x1UL << ETH_MTLOMR_CNTCLR_Pos) /*!< 0x00000200 */
14683 #define ETH_MTLOMR_CNTCLR                            ETH_MTLOMR_CNTCLR_Msk    /* Counters Reset */
14684 #define ETH_MTLOMR_CNTPRST_Pos                       (8U)
14685 #define ETH_MTLOMR_CNTPRST_Msk                       (0x1UL << ETH_MTLOMR_CNTPRST_Pos) /*!< 0x00000100 */
14686 #define ETH_MTLOMR_CNTPRST                           ETH_MTLOMR_CNTPRST_Msk   /* Counters Preset */
14687 #define ETH_MTLOMR_SCHALG_Pos                        (5U)
14688 #define ETH_MTLOMR_SCHALG_Msk                        (0x3UL << ETH_MTLOMR_SCHALG_Pos) /*!< 0x00000020 */
14689 #define ETH_MTLOMR_SCHALG                            ETH_MTLOMR_SCHALG_Msk   /* Tx Scheduling Algorithm */
14690 #define ETH_MTLOMR_SCHALG_WRR                        ((uint32_t)0x00000000)   /* Weighted round robin (WRR) algorithm */
14691 #define ETH_MTLOMR_SCHALG_SP_Pos                     (5U)
14692 #define ETH_MTLOMR_SCHALG_SP_Msk                     (0x3UL << ETH_MTLOMR_SCHALG_SP_Pos) /*!< 0x00000020 */
14693 #define ETH_MTLOMR_SCHALG_SP                         ETH_MTLOMR_SCHALG_SP_Msk  /* Strict priority (SP) algorithm */
14694 #define ETH_MTLOMR_RAA_Pos                           (2U)
14695 #define ETH_MTLOMR_RAA_Msk                           (0x1UL << ETH_MTLOMR_RAA_Pos) /*!< 0x00000004 */
14696 #define ETH_MTLOMR_RAA                               ETH_MTLOMR_RAA_Msk   /* Tx Scheduling Algorithm */
14697 #define ETH_MTLOMR_RAA_SP                            ((uint32_t)0x00000000)   /* Strict priority (SP). Queue 0 has the lowest priority and the last queue has the highest */
14698 #define ETH_MTLOMR_RAA_WSP_Pos                       (2U)
14699 #define ETH_MTLOMR_RAA_WSP_Msk                       (0x1UL << ETH_MTLOMR_RAA_WSP_Pos) /*!< 0x00000004 */
14700 #define ETH_MTLOMR_RAA_WSP                           ETH_MTLOMR_RAA_WSP_Msk  /* Weighted Strict priority (WSP) */
14701 #define ETH_MTLOMR_DTXSTS_Pos                        (1U)
14702 #define ETH_MTLOMR_DTXSTS_Msk                        (0x1UL << ETH_MTLOMR_DTXSTS_Pos) /*!< 0x00000002 */
14703 #define ETH_MTLOMR_DTXSTS                            ETH_MTLOMR_DTXSTS_Msk  /* Drop Transmit Status */
14704 
14705 /************ Bit definition for Ethernet MTL Interrupt Status Register   ***************/
14706 #define ETH_MTLISR_ESTIS_Pos                          (18U)
14707 #define ETH_MTLISR_ESTIS_Msk                          (0x1UL << ETH_MTLISR_ESTIS_Pos) /*!< 0x00040000 */
14708 #define ETH_MTLISR_ESTIS                              ETH_MTLISR_ESTIS_Msk     /* EST (TAS- 802.1Qbv) Interrupt Status */
14709 #define ETH_MTLISR_Q1IS_Pos                           (1U)
14710 #define ETH_MTLISR_Q1IS_Msk                           (0x1UL << ETH_MTLISR_Q1IS_Pos) /*!< 0x00000002 */
14711 #define ETH_MTLISR_Q1IS                               ETH_MTLISR_Q1IS_Msk       /* Queue 1 Interrupt status */
14712 #define ETH_MTLISR_Q0IS_Pos                           (0U)
14713 #define ETH_MTLISR_Q0IS_Msk                           (0x1UL << ETH_MTLISR_Q0IS_Pos) /*!< 0x00000001 */
14714 #define ETH_MTLISR_Q0IS                               ETH_MTLISR_Q0IS_Msk       /* Queue 0 Interrupt status */
14715 
14716 /************ Bit definition for Ethernet MTL Rx Queue and DMA Channel Mapping   ***************/
14717 #define ETH_MTLRXQDMAMR_Q1DDMACH_Pos                 (12U)
14718 #define ETH_MTLRXQDMAMR_Q1DDMACH_Msk                 (0x1UL << ETH_MTLRXQDMAMR_Q1DDMACH_Pos) /*!< 0x00001000 */
14719 #define ETH_MTLRXQDMAMR_Q1DDMACH                     ETH_MTLRXQDMAMR_Q1DDMACH_Msk /* Queue 1 Enabled for DA-based DMA Channel Selection */
14720 #define ETH_MTLRXQDMAMR_Q1MDMACH_Pos                 (8U)
14721 #define ETH_MTLRXQDMAMR_Q1MDMACH_Msk                 (0x1UL << ETH_MTLRXQDMAMR_Q1MDMACH_Pos) /*!< 0x00000100 */
14722 #define ETH_MTLRXQDMAMR_Q1MDMACH                     ETH_MTLRXQDMAMR_Q1MDMACH_Msk /* Queue 1 Mapped to DMA Channel */
14723 #define ETH_MTLRXQDMAMR_Q1MDMACH_DMACH0              ((uint32_t)0x00000000)   /* DMA Channel 0 */
14724 #define ETH_MTLRXQDMAMR_Q1MDMACH_DMACH1_Pos          (8U)
14725 #define ETH_MTLRXQDMAMR_Q1MDMACH_DMACH1_Msk          (0x1UL << ETH_MTLRXQDMAMR_Q1MDMACH_DMACH1_Pos) /*!< 0x00000100 */
14726 #define ETH_MTLRXQDMAMR_Q1MDMACH_DMACH1              ETH_MTLRXQDMAMR_Q1MDMACH_DMACH1_Msk /* DMA Channel 1 */
14727 #define ETH_MTLRXQDMAMR_Q0DDMACH_Pos                 (4U)
14728 #define ETH_MTLRXQDMAMR_Q0DDMACH_Msk                 (0x1UL << ETH_MTLRXQDMAMR_Q0DDMACH_Pos) /*!< 0x00000010 */
14729 #define ETH_MTLRXQDMAMR_Q0DDMACH                     ETH_MTLRXQDMAMR_Q0DDMACH_Msk /* Queue 0 Enabled for DA-based DMA Channel Selection */
14730 #define ETH_MTLRXQDMAMR_Q0MDMACH_Pos                 (0U)
14731 #define ETH_MTLRXQDMAMR_Q0MDMACH_Msk                 (0x1UL << ETH_MTLRXQDMAMR_Q0MDMACH_Pos) /*!< 0x00000001 */
14732 #define ETH_MTLRXQDMAMR_Q0MDMACH                     ETH_MTLRXQDMAMR_Q0MDMACH_Msk /* Queue 0 Mapped to DMA Channel */
14733 #define ETH_MTLRXQDMAMR_Q0MDMACH_DMACH0              ((uint32_t)0x00000000)   /* DMA Channel 0 */
14734 #define ETH_MTLRXQDMAMR_Q0MDMACH_DMACH1_Pos          (0U)
14735 #define ETH_MTLRXQDMAMR_Q0MDMACH_DMACH1_Msk          (0x1UL << ETH_MTLRXQDMAMR_Q0MDMACH_DMACH1_Pos) /*!< 0x00000001 */
14736 #define ETH_MTLRXQDMAMR_Q0MDMACH_DMACH1              ETH_MTLRXQDMAMR_Q0MDMACH_DMACH1_Msk /* DMA Channel 1 */
14737 
14738 /************ Bit definition for Ethernet MTL TBS control Register   ***************/
14739 #define ETH_MTLTBSCR_LEOS_Pos                       (8U)
14740 #define ETH_MTLTBSCR_LEOS_Msk                       (0xFFFFFFUL << ETH_MTLTBSCR_LEOS_Pos) /*!< 0xFFFFFF00 */
14741 #define ETH_MTLTBSCR_LEOS                           ETH_MTLTBSCR_LEOS_Msk /* Launch Expiry Offset */
14742 #define ETH_MTLTBSCR_LEGOS_Pos                      (4U)
14743 #define ETH_MTLTBSCR_LEGOS_Msk                      (0x7UL << ETH_MTLTBSCR_LEGOS_Pos) /*!< 0xFFFFFF00 */
14744 #define ETH_MTLTBSCR_LEGOS                          ETH_MTLTBSCR_LEGOS_Msk /* Launch Expiry GSN Offset */
14745 #define ETH_MTLTBSCR_LEOV_Pos                       (1U)
14746 #define ETH_MTLTBSCR_LEOV_Msk                       (0x1UL << ETH_MTLTBSCR_LEOV_Pos) /*!< 0x00000002 */
14747 #define ETH_MTLTBSCR_LEOV                           ETH_MTLTBSCR_LEOV_Msk /* Launch expiry offset valid */
14748 #define ETH_MTLTBSCR_ESTM_Pos                       (0U)
14749 #define ETH_MTLTBSCR_ESTM_Msk                       (0x1UL << ETH_MTLTBSCR_ESTM_Pos) /*!< 0x00000001 */
14750 #define ETH_MTLTBSCR_ESTM                           ETH_MTLTBSCR_ESTM_Msk /* EST offset mode */
14751 #define ETH_MTLTBSCR_ESTM_ESTOFFDIS                 ((uint32_t)0x00000000)   /* EST offset mode disabled */
14752 #define ETH_MTLTBSCR_ESTM_ESTOFFEN_Pos              (0U)
14753 #define ETH_MTLTBSCR_ESTM_ESTOFFEN_Msk              (0x1UL << ETH_MTLTBSCR_ESTM_ESTOFFEN_Pos) /*!< 0x00000001 */
14754 #define ETH_MTLTBSCR_ESTM_ESTOFFEN                   ETH_MTLTBSCR_ESTM_ESTOFFEN_Msk  /* EST offset mode enabled */
14755 
14756 /************ Bit definition for Ethernet MTL EST Control Register   ***************/
14757 #define ETH_MTLESTCR_PTOV_Pos                       (24U)
14758 #define ETH_MTLESTCR_PTOV_Msk                       (0xFFFFFFUL << ETH_MTLESTCR_PTOV_Pos) /*!< 0xFF000000 */
14759 #define ETH_MTLESTCR_PTOV                           ETH_MTLESTCR_PTOV_Msk /* PTP Time Offset Value */
14760 #define ETH_MTLESTCR_CTOV_Pos                       (12U)
14761 #define ETH_MTLESTCR_CTOV_Msk                       (0xFFFUL << ETH_MTLESTCR_CTOV_Pos) /*!< 0x00FFF000 */
14762 #define ETH_MTLESTCR_CTOV                           ETH_MTLESTCR_CTOV_Msk /* Current Time Offset Value */
14763 #define ETH_MTLESTCR_TILS_Pos                       (8U)
14764 #define ETH_MTLESTCR_TILS_Msk                       (0x7UL << ETH_MTLESTCR_TILS_Pos) /*!< 0x00000700 */
14765 #define ETH_MTLESTCR_TILS                           ETH_MTLESTCR_TILS_Msk /* Time Interval Left Shift Amount */
14766 #define ETH_MTLESTCR_LCSE_Pos                       (6U)
14767 #define ETH_MTLESTCR_LCSE_Msk                       (0x3UL << ETH_MTLESTCR_LCSE_Pos) /*!< 0x000000C0 */
14768 #define ETH_MTLESTCR_LCSE                           ETH_MTLESTCR_LCSE_Msk /* Loop Count to report Scheduling Error */
14769 #define ETH_MTLESTCR_LCSE_4IT                       ((uint32_t)0x00000000)   /* 4 iterations */
14770 #define ETH_MTLESTCR_LCSE_8IT_Pos                   (6U)
14771 #define ETH_MTLESTCR_LCSE_8IT_Msk                   (0x1UL << ETH_MTLESTCR_LCSE_8IT_Pos) /*!< 0x00000040 */
14772 #define ETH_MTLESTCR_LCSE_8IT                       ETH_MTLESTCR_LCSE_8IT_Msk   /* 8 iterations */
14773 #define ETH_MTLESTCR_LCSE_16IT_Pos                  (7U)
14774 #define ETH_MTLESTCR_LCSE_16IT_Msk                  (0x1UL << ETH_MTLESTCR_LCSE_16IT_Pos) /*!< 0x00000080 */
14775 #define ETH_MTLESTCR_LCSE_16IT                      ETH_MTLESTCR_LCSE_16IT_Msk  /* 16 iterations */
14776 #define ETH_MTLESTCR_LCSE_32IT_Pos                  (6U)
14777 #define ETH_MTLESTCR_LCSE_32IT_Msk                  (0x3UL << ETH_MTLESTCR_LCSE_32IT_Pos) /*!< 0x000000C0 */
14778 #define ETH_MTLESTCR_LCSE_32IT                      ETH_MTLESTCR_LCSE_32IT_Msk  /* 32 iterations */
14779 #define ETH_MTLESTCR_DFBS_Pos                       (5U)
14780 #define ETH_MTLESTCR_DFBS_Msk                       (0x1UL << ETH_MTLESTCR_DFBS_Pos) /*!< 0x00000020 */
14781 #define ETH_MTLESTCR_DFBS                           ETH_MTLESTCR_DFBS_Msk /* Drop Frames causing Scheduling Error */
14782 #define ETH_MTLESTCR_DDBF_Pos                       (4U)
14783 #define ETH_MTLESTCR_DDBF_Msk                       (0x1UL << ETH_MTLESTCR_DDBF_Pos) /*!< 0x00000010 */
14784 #define ETH_MTLESTCR_DDBF                           ETH_MTLESTCR_DDBF_Msk /* Do not Drop frames during Frame Size Error */
14785 #define ETH_MTLESTCR_SSWL_Pos                       (1U)
14786 #define ETH_MTLESTCR_SSWL_Msk                       (0x1UL << ETH_MTLESTCR_SSWL_Pos) /*!< 0x00000002 */
14787 #define ETH_MTLESTCR_SSWL                           ETH_MTLESTCR_SSWL_Msk /* Switch to S/W owned list */
14788 #define ETH_MTLESTCR_EEST_Pos                       (0U)
14789 #define ETH_MTLESTCR_EEST_Msk                       (0x1UL << ETH_MTLESTCR_EEST_Pos) /*!< 0x00000001 */
14790 #define ETH_MTLESTCR_EEST                           ETH_MTLESTCR_EEST_Msk /* Enable EST */
14791 
14792 /************ Bit definition for Ethernet MTL EST Extended Control Register   ***************/
14793 /* Bit definition for Ethernet MTL EST Extended Control Register */
14794 #define ETH_MTLESTECR_OVHD_Pos                       (0U)
14795 #define ETH_MTLESTECR_OVHD_Msk                       (0x3FUL << ETH_MTLESTECR_OVHD_Pos) /*!< 0x0000003F */
14796 #define ETH_MTLESTECR_OVHD                           ETH_MTLESTECR_OVHD_Msk /* Overhead Bytes Value */
14797 
14798 /************ Bit definition for Ethernet MTL EST Status Register   ***************/
14799 #define ETH_MTLESTSR_CGSN_Pos                       (16U)
14800 #define ETH_MTLESTSR_CGSN_Msk                       (0xFUL << ETH_MTLESTSR_CGSN_Pos) /*!< 0x000F0000 */
14801 #define ETH_MTLESTSR_CGSN                           ETH_MTLESTSR_CGSN_Msk /* Current GCL slot number */
14802 #define ETH_MTLESTSR_BTRL_Pos                       (8U)
14803 #define ETH_MTLESTSR_BTRL_Msk                       (0xFFUL << ETH_MTLESTSR_BTRL_Pos) /*!< 0x00000F00 */
14804 #define ETH_MTLESTSR_BTRL                           ETH_MTLESTSR_CGSN_Msk /* BTR Error Loop Count */
14805 #define ETH_MTLESTSR_SWOL_Pos                       (7U)
14806 #define ETH_MTLESTSR_SWOL_Msk                       (0x1UL << ETH_MTLESTSR_SWOL_Pos) /*!< 0x00000080 */
14807 #define ETH_MTLESTSR_SWOL                           ETH_MTLESTSR_SWOL_Msk /* S/W owned list */
14808 #define ETH_MTLESTSR_CGCE_Pos                       (4U)
14809 #define ETH_MTLESTSR_CGCE_Msk                       (0x1UL << ETH_MTLESTSR_CGCE_Pos) /*!< 0x00000010 */
14810 #define ETH_MTLESTSR_CGCE                           ETH_MTLESTSR_CGCE_Msk /* Constant Gate Control Error */
14811 #define ETH_MTLESTSR_HLBS_Pos                       (3U)
14812 #define ETH_MTLESTSR_HLBS_Msk                       (0x1UL << ETH_MTLESTSR_HLBS_Pos) /*!< 0x00000008 */
14813 #define ETH_MTLESTSR_HLBS                           ETH_MTLESTSR_HLBS_Msk /* Head-Of-Line Blocking due to Scheduling */
14814 #define ETH_MTLESTSR_HLBF_Pos                       (2U)
14815 #define ETH_MTLESTSR_HLBF_Msk                       (0x1UL << ETH_MTLESTSR_HLBF_Pos) /*!< 0x00000004 */
14816 #define ETH_MTLESTSR_HLBF                           ETH_MTLESTSR_HLBF_Msk /* Head-Of-Line Blocking due to Frame Size */
14817 #define ETH_MTLESTSR_BTRE_Pos                       (1U)
14818 #define ETH_MTLESTSR_BTRE_Msk                       (0x1UL << ETH_MTLESTSR_BTRE_Pos) /*!< 0x00000002 */
14819 #define ETH_MTLESTSR_BTRE                           ETH_MTLESTSR_BTRE_Msk /* BTR Error */
14820 #define ETH_MTLESTSR_SWLC_Pos                       (0U)
14821 #define ETH_MTLESTSR_SWLC_Msk                       (0x1UL << ETH_MTLESTSR_SWLC_Pos) /*!< 0x00000001 */
14822 #define ETH_MTLESTSR_SWLC                           ETH_MTLESTSR_SWLC_Msk /* Switch to S/W owned list Complete */
14823 
14824 /************ Bit definition for Ethernet MTL EST Schedule Error Register   ***************/
14825 /* Bit definition for Ethernet MTL EST Schedule Error Register */
14826 #define ETH_MTLESTSCHER_SEQN_Pos                       (0U)
14827 #define ETH_MTLESTSCHER_SEQN_Msk                       (0x3UL << ETH_MTLESTSCHER_SEQN_Pos) /*!< 0x00000003 */
14828 #define ETH_MTLESTSCHER_SEQN                           ETH_MTLESTSCHER_SEQN_Msk /* Schedule Error Queue Number */
14829 
14830 /************ Bit definition for Ethernet MTL EST Frame size Error Register   ***************/
14831 #define ETH_MTLESTFSER_FEQN_Pos                       (0U)
14832 #define ETH_MTLESTFSER_FEQN_Msk                       (0x3UL << ETH_MTLESTFSER_FEQN_Pos) /*!< 0x00000003 */
14833 #define ETH_MTLESTFSER_FEQN                           ETH_MTLESTFSER_FEQN_Msk /* Frame Size Error Queue Number */
14834 
14835 /************ Bit definition for Ethernet MTL EST Frame size Capture Register   ***************/
14836 #define ETH_MTLESTFSCR_HBFQ_Pos                       (16U)
14837 #define ETH_MTLESTFSCR_HBFQ_Msk                       (0x1UL << ETH_MTLESTFSCR_HBFQ_Pos) /*!< 0x00010000 */
14838 #define ETH_MTLESTFSCR_HBFQ                           ETH_MTLESTFSCR_HBFQ_Msk /* Queue Number of HLBF */
14839 #define ETH_MTLESTFSCR_HBFS_Pos                       (0U)
14840 #define ETH_MTLESTFSCR_HBFS_Msk                       (0x7FFFUL << ETH_MTLESTFSCR_HBFS_Pos) /*!< 0x00007FFF */
14841 #define ETH_MTLESTFSCR_HBFS                           ETH_MTLESTFSCR_HBFS_Msk /* Frame Size of HLBF */
14842 
14843 /************ Bit definition for Ethernet MTL EST Interrupt Enable Register   ***************/
14844 /* Bit definition for Ethernet MTL EST Interrupt Enable Register */
14845 #define ETH_MTLESTIER_CGCE_Pos                       (4U)
14846 #define ETH_MTLESTIER_CGCE_Msk                       (0x1UL << ETH_MTLESTIER_CGCE_Pos) /*!< 0x00000010 */
14847 #define ETH_MTLESTIER_CGCE                           ETH_MTLESTIER_CGCE_Msk /* Interrupt Enable for CGCE */
14848 #define ETH_MTLESTIER_IEHS_Pos                       (3U)
14849 #define ETH_MTLESTIER_IEHS_Msk                       (0x1UL << ETH_MTLESTIER_IEHS_Pos) /*!< 0x00000008 */
14850 #define ETH_MTLESTIER_IEHS                           ETH_MTLESTIER_IEHS_Msk /* Interrupt Enable for HLBS */
14851 #define ETH_MTLESTIER_IEHF_Pos                       (2U)
14852 #define ETH_MTLESTIER_IEHF_Msk                       (0x1UL << ETH_MTLESTIER_IEHF_Pos) /*!< 0x00000004 */
14853 #define ETH_MTLESTIER_IEHF                           ETH_MTLESTIER_IEHF_Msk /* Interrupt Enable for HLBF */
14854 #define ETH_MTLESTIER_IEBE_Pos                       (1U)
14855 #define ETH_MTLESTIER_IEBE_Msk                       (0x1UL << ETH_MTLESTIER_IEBE_Pos) /*!< 0x00000002 */
14856 #define ETH_MTLESTIER_IEBE                           ETH_MTLESTIER_IEBE_Msk /* Interrupt Enable for BTR Error */
14857 #define ETH_MTLESTIER_IECC_Pos                       (0U)
14858 #define ETH_MTLESTIER_IECC_Msk                       (0x1UL << ETH_MTLESTIER_IECC_Pos) /*!< 0x00000001 */
14859 #define ETH_MTLESTIER_IECC                           ETH_MTLESTIER_IECC_Msk /* Interrupt Enable for Switch List */
14860 
14861 /************ Bit definition for Ethernet MTL EST Gate Control List Register   ***************/
14862 #define ETH_MTLESTGCLCR_ADDR_Pos                       (8U)
14863 #define ETH_MTLESTGCLCR_ADDR_Msk                       (0x3FUL << ETH_MTLESTGCLCR_ADDR_Pos) /*!< 0x00003F00 */
14864 #define ETH_MTLESTGCLCR_ADDR                           ETH_MTLESTGCLCR_ADDR_Msk /* Gate Control List Address */
14865 #define ETH_MTLESTGCLCR_ADDR_BTRLOW                    ((uint32_t)0x00000000)   /* BTR Low (31:0) */
14866 #define ETH_MTLESTGCLCR_ADDR_BTRHIGH_Pos               (8U)
14867 #define ETH_MTLESTGCLCR_ADDR_BTRHIGH_Msk               (0x1UL << ETH_MTLESTGCLCR_ADDR_BTRHIGH_Pos) /*!< 0x00000100 */
14868 #define ETH_MTLESTGCLCR_ADDR_BTRHIGH                   ETH_MTLESTGCLCR_ADDR_BTRHIGH_Msk /* BTR High (63:31) */
14869 #define ETH_MTLESTGCLCR_ADDR_CTRLOW_Pos                (9U)
14870 #define ETH_MTLESTGCLCR_ADDR_CTRLOW_Msk                (0x1UL << ETH_MTLESTGCLCR_ADDR_CTRLOW_Pos) /*!< 0x00000200 */
14871 #define ETH_MTLESTGCLCR_ADDR_CTRLOW                    ETH_MTLESTGCLCR_ADDR_CTRLOW_Msk /* CTR Low (31:0) */
14872 #define ETH_MTLESTGCLCR_ADDR_CTRHIGH_Pos               (8U)
14873 #define ETH_MTLESTGCLCR_ADDR_CTRHIGH_Msk               (0x3UL << ETH_MTLESTGCLCR_ADDR_CTRHIGH_Pos) /*!< 0x00000300 */
14874 #define ETH_MTLESTGCLCR_ADDR_CTRHIGH                   ETH_MTLESTGCLCR_ADDR_CTRHIGH_Msk /* CTR High (39:32) */
14875 #define ETH_MTLESTGCLCR_ADDR_TER_Pos                   (10U)
14876 #define ETH_MTLESTGCLCR_ADDR_TER_Msk                   (0x1UL << ETH_MTLESTGCLCR_ADDR_TER_Pos) /*!< 0x00000400 */
14877 #define ETH_MTLESTGCLCR_ADDR_TER                       ETH_MTLESTGCLCR_ADDR_TER_Msk /* TER (30:0) */
14878 #define ETH_MTLESTGCLCR_ADDR_LLR_Pos                   (8U)
14879 #define ETH_MTLESTGCLCR_ADDR_LLR_Msk                   (0x5UL << ETH_MTLESTGCLCR_ADDR_LLR_Pos) /*!< 0x00000500 */
14880 #define ETH_MTLESTGCLCR_ADDR_LLR                       ETH_MTLESTGCLCR_ADDR_LLR_Msk /* LLR (6:0) */
14881 #define ETH_MTLESTGCLCR_DBGB_Pos                       (5U)
14882 #define ETH_MTLESTGCLCR_DBGB_Msk                       (0x1UL << ETH_MTLESTGCLCR_DBGB_Pos) /*!< 0x00000020 */
14883 #define ETH_MTLESTGCLCR_DBGB                           ETH_MTLESTGCLCR_DBGB_Msk /* Debug Mode Bank Select */
14884 #define ETH_MTLESTGCLCR_DBGM_Pos                       (4U)
14885 #define ETH_MTLESTGCLCR_DBGM_Msk                       (0x1UL << ETH_MTLESTGCLCR_DBGM_Pos) /*!< 0x00000010 */
14886 #define ETH_MTLESTGCLCR_DBGM                           ETH_MTLESTGCLCR_DBGM_Msk /* Debug Mode */
14887 #define ETH_MTLESTGCLCR_GCRR_Pos                       (2U)
14888 #define ETH_MTLESTGCLCR_GCRR_Msk                       (0x1UL << ETH_MTLESTGCLCR_GCRR_Pos) /*!< 0x00000004 */
14889 #define ETH_MTLESTGCLCR_GCRR                           ETH_MTLESTGCLCR_GCRR_Msk /* Gate Control Related Registers */
14890 #define ETH_MTLESTGCLCR_R1W0_Pos                       (1U)
14891 #define ETH_MTLESTGCLCR_R1W0_Msk                       (0x1UL << ETH_MTLESTGCLCR_R1W0_Pos) /*!< 0x00000002 */
14892 #define ETH_MTLESTGCLCR_R1W0                           ETH_MTLESTGCLCR_R1W0_Msk /* Read 1, Write 0 */
14893 #define ETH_MTLESTGCLCR_SRWO_Pos                       (0U)
14894 #define ETH_MTLESTGCLCR_SRWO_Msk                       (0x1UL << ETH_MTLESTGCLCR_SRWO_Pos) /*!< 0x00000001 */
14895 #define ETH_MTLESTGCLCR_SRWO                           ETH_MTLESTGCLCR_SRWO_Msk /* Start Read/Write Operation */
14896 
14897 /************ Bit definition for Ethernet MTL EST Gate Control List Data Register   ***************/
14898 #define ETH_MTLESTGCLDR_GCD_Pos                        (0U)
14899 #define ETH_MTLESTGCLDR_GCD_Msk                        (0xFFFFFFFFUL << ETH_MTLESTGCLDR_GCD_Pos) /*!< 0xFFFFFFFF */
14900 #define ETH_MTLESTGCLDR_GCD                            ETH_MTLESTGCLDR_GCD_Msk /* Gate Control Data */
14901 
14902 /************ Bit definition for Ethernet MTL FPE Frame Preemption Control Status Register   ***************/
14903 #define ETH_MTLFPECSR_HRS_Pos                          (28U)
14904 #define ETH_MTLFPECSR_HRS_Msk                          (0x1UL << ETH_MTLFPECSR_HRS_Pos) /*!< 0x10000000 */
14905 #define ETH_MTLFPECSR_HRS                              ETH_MTLFPECSR_HRS_Msk /* Hold/Release Status */
14906 #define ETH_MTLFPECSR_PEC_Pos                          (8U)
14907 #define ETH_MTLFPECSR_PEC_Msk                          (0x3UL << ETH_MTLFPECSR_PEC_Pos) /*!< 0x00000300 */
14908 #define ETH_MTLFPECSR_PEC                              ETH_MTLFPECSR_PEC_Msk /* Preemption Classification */
14909 #define ETH_MTLFPECSR_AFSZ_Pos                         (0U)
14910 #define ETH_MTLFPECSR_AFSZ_Msk                         (0x3UL << ETH_MTLFPECSR_AFSZ_Pos) /*!< 0x00000003 */
14911 #define ETH_MTLFPECSR_AFSZ                             ETH_MTLFPECSR_AFSZ_Msk /* Additional Fragment Size */
14912 
14913 /************ Bit definition for Ethernet MTL FPE Frame Preemption Advance Register   ***************/
14914 #define ETH_MTLFPEAR_RADV_Pos                          (16U)
14915 #define ETH_MTLFPEAR_RADV_Msk                          (0xFFFFUL << ETH_MTLFPEAR_RADV_Pos) /*!< 0xFFFF0000 */
14916 #define ETH_MTLFPEAR_RADV                              ETH_MTLFPEAR_RADV_Msk /* Release Advance */
14917 #define ETH_MTLFPEAR_HADV_Pos                          (0U)
14918 #define ETH_MTLFPEAR_HADV_Msk                          (0xFFFFUL << ETH_MTLFPEAR_HADV_Pos) /*!< 0x0000FFFF */
14919 #define ETH_MTLFPEAR_HADV                              ETH_MTLFPEAR_HADV_Msk /* Hold Advance */
14920 
14921 /************ Bit definition for Ethernet MTL Tx queue x operating mode Register   ***************/
14922 #define ETH_MTLTXQxOMR_TQS_Pos                          (16U)
14923 #define ETH_MTLTXQxOMR_TQS_Msk                          (0xFUL << ETH_MTLTXQxOMR_TQS_Pos) /*!< 0x000F0000 */
14924 #define ETH_MTLTXQxOMR_TQS                              ETH_MTLTXQxOMR_TQS_Msk     /* Transmit queue size */
14925 #define ETH_MTLTXQxOMR_TQS_0                            (0x1UL << ETH_MTLTXQxOMR_TQS_Pos)                /*!< 0x00010000 */
14926 #define ETH_MTLTXQxOMR_TQS_1                            (0x2UL << ETH_MTLTXQxOMR_TQS_Pos)                /*!< 0x00020000 */
14927 #define ETH_MTLTXQxOMR_TQS_2                            (0x4UL << ETH_MTLTXQxOMR_TQS_Pos)                /*!< 0x00040000 */
14928 #define ETH_MTLTXQxOMR_TQS_3                            (0x8UL << ETH_MTLTXQxOMR_TQS_Pos)                /*!< 0x00080000 */
14929 #define ETH_MTLTXQxOMR_TTC_Pos                          (4U)
14930 #define ETH_MTLTXQxOMR_TTC_Msk                          (0x7UL << ETH_MTLTXQxOMR_TTC_Pos) /*!< 0x00000070 */
14931 #define ETH_MTLTXQxOMR_TTC                              ETH_MTLTXQxOMR_TTC_Msk     /* Transmit Threshold Control */
14932 #define ETH_MTLTXQxOMR_TTC_32BITS                       ((uint32_t)0x00000000)   /* 32 bits Threshold */
14933 #define ETH_MTLTXQxOMR_TTC_64BITS                       ((uint32_t)0x00000010)   /* 64  bits Threshold */
14934 #define ETH_MTLTXQxOMR_TTC_96BITS                       ((uint32_t)0x00000020)   /* 96 bits Threshold */
14935 #define ETH_MTLTXQxOMR_TTC_128BITS                      ((uint32_t)0x00000030)   /* 128 bits Threshold */
14936 #define ETH_MTLTXQxOMR_TTC_192BITS                      ((uint32_t)0x00000040)   /* 192 bits Threshold */
14937 #define ETH_MTLTXQxOMR_TTC_256BITS                      ((uint32_t)0x00000050)   /* 256 bits Threshold */
14938 #define ETH_MTLTXQxOMR_TTC_384BITS                      ((uint32_t)0x00000060)   /* 384 bits Threshold */
14939 #define ETH_MTLTXQxOMR_TTC_512BITS                      ((uint32_t)0x00000070)   /* 512 bits Threshold */
14940 #define ETH_MTLTXQxOMR_TXQEN_Pos                        (2U)
14941 #define ETH_MTLTXQxOMR_TXQEN_Msk                        (0x3UL << ETH_MTLTXQxOMR_TXQEN_Pos) /*!< 0x0000000C */
14942 #define ETH_MTLTXQxOMR_TXQEN                            ETH_MTLTXQxOMR_TXQEN_Msk     /* Transmit Queue Enable */
14943 #define ETH_MTLTXQxOMR_TXQEN_NOT                        ((uint32_t)0x00000000)   /* Not enabled */
14944 #define ETH_MTLTXQxOMR_TXQEN_AVMODE_Pos                 (2U)
14945 #define ETH_MTLTXQxOMR_TXQEN_AVMODE_Msk                 (0x1UL << ETH_MTLTXQxOMR_TXQEN_AVMODE_Pos) /*!< 0x00000004 */
14946 #define ETH_MTLTXQxOMR_TXQEN_AVMODE                     ETH_MTLTXQxOMR_TXQEN_AVMODE_Msk     /* Enable in AV mode */
14947 #define ETH_MTLTXQxOMR_TXQEN_EN_Pos                     (3U)
14948 #define ETH_MTLTXQxOMR_TXQEN_EN_Msk                     (0x1UL << ETH_MTLTXQxOMR_TXQEN_EN_Pos) /*!< 0x00000008 */
14949 #define ETH_MTLTXQxOMR_TXQEN_EN                         ETH_MTLTXQxOMR_TXQEN_EN_Msk     /* Enabled */
14950 #define ETH_MTLTXQxOMR_TSF_Pos                          (1U)
14951 #define ETH_MTLTXQxOMR_TSF_Msk                          (0x1UL << ETH_MTLTXQxOMR_TSF_Pos) /*!< 0x00000002 */
14952 #define ETH_MTLTXQxOMR_TSF                              ETH_MTLTXQxOMR_TSF_Msk     /* Transmit Store and Forward */
14953 #define ETH_MTLTXQxOMR_FTQ_Pos                          (0U)
14954 #define ETH_MTLTXQxOMR_FTQ_Msk                          (0x1UL << ETH_MTLTXQxOMR_FTQ_Pos) /*!< 0x00000001 */
14955 #define ETH_MTLTXQxOMR_FTQ                              ETH_MTLTXQxOMR_FTQ_Msk     /* Flush Transmit Queue */
14956 
14957 /************ Bit definition for Ethernet MTL Tx Queue x Underflow Register   ***************/
14958 #define ETH_MTLTXQxUR_UFCNTOVF_Pos                     (11U)
14959 #define ETH_MTLTXQxUR_UFCNTOVF_Msk                     (0x1UL << ETH_MTLTXQxUR_UFCNTOVF_Pos) /*!< 0x00000800 */
14960 #define ETH_MTLTXQxUR_UFCNTOVF                         ETH_MTLTXQxUR_UFCNTOVF_Msk /* Overflow Bit for Underflow Packet Counter */
14961 #define ETH_MTLTXQxUR_UFPKTCNT_Pos                     (0U)
14962 #define ETH_MTLTXQxUR_UFPKTCNT_Msk                     (0x7FFUL << ETH_MTLTXQxUR_UFPKTCNT_Pos) /*!< 0x000007FF */
14963 #define ETH_MTLTXQxUR_UFPKTCNT                         ETH_MTLTXQxUR_UFPKTCNT_Msk /* Underflow Packet Counter */
14964 
14965 /************ Bit definition for Ethernet MTL Tx Queue x Debug Register   ***************/
14966 #define ETH_MTLTXQxDR_STXSTSF_Pos                       (20U)
14967 #define ETH_MTLTXQxDR_STXSTSF_Msk                       (0x7UL << ETH_MTLTXQxDR_STXSTSF_Pos) /*!< 0x00700000 */
14968 #define ETH_MTLTXQxDR_STXSTSF                           ETH_MTLTXQxDR_STXSTSF_Msk  /* Number of Status Words in the Tx Status FIFO of Queue */
14969 #define ETH_MTLTXQxDR_PTXQ_Pos                          (16U)
14970 #define ETH_MTLTXQxDR_PTXQ_Msk                          (0x7UL << ETH_MTLTXQxDR_PTXQ_Pos) /*!< 0x00070000 */
14971 #define ETH_MTLTXQxDR_PTXQ                              ETH_MTLTXQxDR_PTXQ_Msk     /* Number of Packets in the Transmit Queue */
14972 #define ETH_MTLTXQxDR_TXSTSFSTS_Pos                     (5U)
14973 #define ETH_MTLTXQxDR_TXSTSFSTS_Msk                     (0x1UL << ETH_MTLTXQxDR_TXSTSFSTS_Pos) /*!< 0x00000020 */
14974 #define ETH_MTLTXQxDR_TXSTSFSTS                         ETH_MTLTXQxDR_TXSTSFSTS_Msk /* MTL Tx Status FIFO Full Status */
14975 #define ETH_MTLTXQxDR_TXQSTS_Pos                        (4U)
14976 #define ETH_MTLTXQxDR_TXQSTS_Msk                        (0x1UL << ETH_MTLTXQxDR_TXQSTS_Pos) /*!< 0x00000010 */
14977 #define ETH_MTLTXQxDR_TXQSTS                            ETH_MTLTXQxDR_TXQSTS_Msk   /* MTL Tx Queue Not Empty Status */
14978 #define ETH_MTLTXQxDR_TWCSTS_Pos                        (3U)
14979 #define ETH_MTLTXQxDR_TWCSTS_Msk                        (0x1UL << ETH_MTLTXQxDR_TWCSTS_Pos) /*!< 0x00000008 */
14980 #define ETH_MTLTXQxDR_TWCSTS                            ETH_MTLTXQxDR_TWCSTS_Msk   /* MTL Tx Queue Write Controller Status */
14981 #define ETH_MTLTXQxDR_TRCSTS_Pos                        (1U)
14982 #define ETH_MTLTXQxDR_TRCSTS_Msk                        (0x3UL << ETH_MTLTXQxDR_TRCSTS_Pos) /*!< 0x00000006 */
14983 #define ETH_MTLTXQxDR_TRCSTS                            ETH_MTLTXQ0DR_TRCSTS_Msk  /* MTL Tx Queue Read Controller Status */
14984 #define ETH_MTLTXQxDR_TRCSTS_IDLE                       ((uint32_t)0x00000000)  /* Idle state */
14985 #define ETH_MTLTXQxDR_TRCSTS_READ                       ((uint32_t)0x00000002)  /* Read state (transferring data to the MAC transmitter) */
14986 #define ETH_MTLTXQxDR_TRCSTS_WAITING                    ((uint32_t)0x00000004)  /* Waiting for pending Tx Status from the MAC transmitter */
14987 #define ETH_MTLTXQxDR_TRCSTS_FLUSHING                   ((uint32_t)0x00000006)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */
14988 #define ETH_MTLTXQxDR_TXQPAUSED_Pos                     (0U)
14989 #define ETH_MTLTXQxDR_TXQPAUSED_Msk                     (0x1UL << ETH_MTLTXQxDR_TXQPAUSED_Pos) /*!< 0x00000001 */
14990 #define ETH_MTLTXQxDR_TXQPAUSED                         ETH_MTLTXQxDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
14991 
14992 /************ Bit definition for Ethernet MTL Tx queue x ETS status Register   ***************/
14993 #define ETH_MTLTXQxESR_ABS_Pos                       (0U)
14994 #define ETH_MTLTXQxESR_ABS_Msk                       (0xFFFFFFUL << ETH_MTLTXQxESR_ABS_Pos) /*!< 0x00FFFFFF */
14995 #define ETH_MTLTXQxESR_ABS                           ETH_MTLTXQxESR_ABS_Msk  /* Average Bits per Slot */
14996 
14997 /************ Bit definition for Ethernet MTL Tx queue 0 quantum weight Register   ***************/
14998 #define ETH_MTLTXQ0QWR_ISCQW_Pos                       (0U)
14999 #define ETH_MTLTXQ0QWR_ISCQW_Msk                       (0x7FUL << ETH_MTLTXQ0QWR_ISCQW_Pos) /*!< 0x0000007F */
15000 #define ETH_MTLTXQ0QWR_ISCQW                           ETH_MTLTXQ0QWR_ISCQW_Msk  /* Weights */
15001 
15002 /************ Bit definition for Ethernet MTL Queue x Interrupt Control Status Register   ***************/
15003 #define ETH_MTLQxICSR_RXOIE_Pos                        (24U)
15004 #define ETH_MTLQxICSR_RXOIE_Msk                        (0x1UL << ETH_MTLQxICSR_RXOIE_Pos) /*!< 0x01000000 */
15005 #define ETH_MTLQxICSR_RXOIE                            ETH_MTLQxICSR_RXOIE_Msk   /* Receive Queue Overflow Interrupt Enable */
15006 #define ETH_MTLQxICSR_RXOVFIS_Pos                      (16U)
15007 #define ETH_MTLQxICSR_RXOVFIS_Msk                      (0x1UL << ETH_MTLQxICSR_RXOVFIS_Pos) /*!< 0x00010000 */
15008 #define ETH_MTLQxICSR_RXOVFIS                          ETH_MTLQxICSR_RXOVFIS_Msk /* Receive Queue Overflow Interrupt Status */
15009 #define ETH_MTLQxICSR_ABPSIE_Pos                       (9U)
15010 #define ETH_MTLQxICSR_ABPSIE_Msk                       (0x1UL << ETH_MTLQxICSR_ABPSIE_Pos) /*!< 0x00000200 */
15011 #define ETH_MTLQxICSR_ABPSIE                           ETH_MTLQxICSR_ABPSIE_Msk   /* Average Bits Per Slot Interrupt Enable */
15012 #define ETH_MTLQxICSR_TXUIE_Pos                        (8U)
15013 #define ETH_MTLQxICSR_TXUIE_Msk                        (0x1UL << ETH_MTLQxICSR_TXUIE_Pos) /*!< 0x00000100 */
15014 #define ETH_MTLQxICSR_TXUIE                            ETH_MTLQxICSR_TXUIE_Msk   /* Transmit Queue Underflow Interrupt Enable */
15015 #define ETH_MTLQxICSR_ABPSIS_Pos                       (1U)
15016 #define ETH_MTLQxICSR_ABPSIS_Msk                       (0x1UL << ETH_MTLQxICSR_ABPSIS_Pos) /*!< 0x00000002 */
15017 #define ETH_MTLQxICSR_ABPSIS                           ETH_MTLQxICSR_ABPSIS_Msk /* Average Bits Per Slot Interrupt Status */
15018 #define ETH_MTLQxICSR_TXUNFIS_Pos                      (0U)
15019 #define ETH_MTLQxICSR_TXUNFIS_Msk                      (0x1UL << ETH_MTLQxICSR_TXUNFIS_Pos) /*!< 0x00000001 */
15020 #define ETH_MTLQxICSR_TXUNFIS                          ETH_MTLQxICSR_TXUNFIS_Msk /* Transmit Queue Underflow Interrupt Status */
15021 
15022 /************ Bit definition for Ethernet MTL Rx Queue x Operation Mode Register   ***************/
15023 #define ETH_MTLRXQxOMR_RQS_Pos                          (20U)
15024 #define ETH_MTLRXQxOMR_RQS_Msk                          (0xFUL << ETH_MTLRXQxOMR_RQS_Pos) /*!< 0x00F00000 */
15025 #define ETH_MTLRXQxOMR_RQS                              ETH_MTLRXQxOMR_RQS_Msk /* Receive Queue Size */
15026 #define ETH_MTLRXQxOMR_RQS_0                            (0x1UL << ETH_MTLRXQxOMR_RQS_Pos)               /*!< 0x00100000 */
15027 #define ETH_MTLRXQxOMR_RQS_1                            (0x2UL << ETH_MTLRXQxOMR_RQS_Pos)               /*!< 0x00200000 */
15028 #define ETH_MTLRXQxOMR_RQS_2                            (0x4UL << ETH_MTLRXQxOMR_RQS_Pos)               /*!< 0x00400000 */
15029 #define ETH_MTLRXQxOMR_RQS_3                            (0x8UL << ETH_MTLRXQxOMR_RQS_Pos)               /*!< 0x00800000 */
15030 #define ETH_MTLRXQxOMR_RFD_Pos                          (14U)
15031 #define ETH_MTLRXQxOMR_RFD_Msk                          (0x7UL << ETH_MTLRXQxOMR_RFD_Pos) /*!< 0x0001C000 */
15032 #define ETH_MTLRXQxOMR_RFD                              ETH_MTLRXQxOMR_RFD_Msk /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */
15033 #define ETH_MTLRXQxOMR_RFA_Pos                          (8U)
15034 #define ETH_MTLRXQxOMR_RFA_Msk                          (0x7UL << ETH_MTLRXQ0OMR_RFA_Pos) /*!< 0x00000700 */
15035 #define ETH_MTLRXQxOMR_RFA                              ETH_MTLRXQxOMR_RFA_Pos /* Threshold for Activating Flow Control (in half-duplex and full-duplex */
15036 #define ETH_MTLRXQxOMR_EHFC_Pos                         (7U)
15037 #define ETH_MTLRXQxOMR_EHFC_Msk                         (0x1UL << ETH_MTLRXQxOMR_EHFC_Pos) /*!< 0x00000080 */
15038 #define ETH_MTLRXQxOMR_EHFC                             ETH_MTLRXQxOMR_EHFC_Msk /* DEnable Hardware Flow Control */
15039 #define ETH_MTLRXQxOMR_DISTCPEF_Pos                     (6U)
15040 #define ETH_MTLRXQxOMR_DISTCPEF_Msk                     (0x1UL << ETH_MTLRXQxOMR_DISTCPEF_Pos) /*!< 0x00000040 */
15041 #define ETH_MTLRXQxOMR_DISTCPEF                         ETH_MTLRXQxOMR_DISTCPEF_Msk /* Disable Dropping of TCP/IP Checksum Error Packets */
15042 #define ETH_MTLRXQxOMR_RSF_Pos                          (5U)
15043 #define ETH_MTLRXQxOMR_RSF_Msk                          (0x1UL << ETH_MTLRXQxOMR_RSF_Pos) /*!< 0x00000020 */
15044 #define ETH_MTLRXQxOMR_RSF                              ETH_MTLRXQxOMR_RSF_Msk     /* Receive Queue Store and Forward */
15045 #define ETH_MTLRXQxOMR_FEP_Pos                          (4U)
15046 #define ETH_MTLRXQxOMR_FEP_Msk                          (0x1UL << ETH_MTLRXQxOMR_FEP_Pos) /*!< 0x00000010 */
15047 #define ETH_MTLRXQxOMR_FEP                              ETH_MTLRXQxOMR_FEP_Msk     /* Forward Error Packets */
15048 #define ETH_MTLRXQxOMR_FUP_Pos                          (3U)
15049 #define ETH_MTLRXQxOMR_FUP_Msk                          (0x1UL << ETH_MTLRXQxOMR_FUP_Pos) /*!< 0x00000008 */
15050 #define ETH_MTLRXQxOMR_FUP                              ETH_MTLRXQxOMR_FUP_Msk     /* Forward Undersized Good Packets */
15051 #define ETH_MTLRXQxOMR_RTC_Pos                          (0U)
15052 #define ETH_MTLRXQxOMR_RTC_Msk                          (0x3UL << ETH_MTLRXQxOMR_RTC_Pos) /*!< 0x00000003 */
15053 #define ETH_MTLRXQxOMR_RTC                              ETH_MTLRXQxOMR_RTC_Msk     /* Receive Queue Threshold Control */
15054 #define ETH_MTLRXQxOMR_RTC_64BITS                       ((uint32_t)0x00000000)   /* 64 bits Threshold */
15055 #define ETH_MTLRXQxOMR_RTC_32BITS                       ((uint32_t)0x00000001)   /* 32 bits Threshold */
15056 #define ETH_MTLRXQxOMR_RTC_96BITS                       ((uint32_t)0x00000002)   /* 96 bits Threshold */
15057 #define ETH_MTLRXQxOMR_RTC_128BITS                      ((uint32_t)0x00000003)   /* 128 bits Threshold */
15058 
15059 /************ Bit definition for Ethernet MTL Rx Queue x Missed Packet Overflow Cnt Register   ***************/
15060 #define ETH_MTLRXQxMPOCR_MISCNTOVF_Pos                  (27U)
15061 #define ETH_MTLRXQxMPOCR_MISCNTOVF_Msk                  (0x1UL << ETH_MTLRXQxMPOCR_MISCNTOVF_Pos) /*!< 0x08000000 */
15062 #define ETH_MTLRXQxMPOCR_MISCNTOVF                      ETH_MTLRXQxMPOCR_MISCNTOVF_Msk /* Missed Packet Counter Overflow Bit */
15063 #define ETH_MTLRXQxMPOCR_MISPKTCNT_Pos                  (16U)
15064 #define ETH_MTLRXQxMPOCR_MISPKTCNT_Msk                  (0x7FFUL << ETH_MTLRXQxMPOCR_MISPKTCNT_Pos) /*!< 0x07FF0000 */
15065 #define ETH_MTLRXQxMPOCR_MISPKTCNT                      ETH_MTLRXQxMPOCR_MISPKTCNT_Msk /* Missed Packet Counter */
15066 #define ETH_MTLRXQxMPOCR_OVFCNTOVF_Pos                  (11U)
15067 #define ETH_MTLRXQxMPOCR_OVFCNTOVF_Msk                  (0x1UL << ETH_MTLRXQxMPOCR_OVFCNTOVF_Pos) /*!< 0x00000800 */
15068 #define ETH_MTLRXQxMPOCR_OVFCNTOVF                      ETH_MTLRXQxMPOCR_OVFCNTOVF_Msk /* Overflow Counter Overflow Bit */
15069 #define ETH_MTLRXQxMPOCR_OVFPKTCNT_Pos                  (0U)
15070 #define ETH_MTLRXQxMPOCR_OVFPKTCNT_Msk                  (0x7FFUL << ETH_MTLRXQxMPOCR_OVFPKTCNT_Pos) /*!< 0x000007FF */
15071 #define ETH_MTLRXQxMPOCR_OVFPKTCNT                      ETH_MTLRXQxMPOCR_OVFPKTCNT_Msk /* Overflow Packet Counter */
15072 
15073 /************ Bit definition for Ethernet MTL Rx Queue x Debug Register   ***************/
15074 #define ETH_MTLRXQxDR_PRXQ_Pos                          (16U)
15075 #define ETH_MTLRXQxDR_PRXQ_Msk                          (0x3FFFUL << ETH_MTLRXQxDR_PRXQ_Pos) /*!< 0x3FFF0000 */
15076 #define ETH_MTLRXQxDR_PRXQ                              ETH_MTLRXQxDR_PRXQ_Msk     /* Number of Packets in Receive Queue */
15077 #define ETH_MTLRXQxDR_RXQSTS_Pos                        (4U)
15078 #define ETH_MTLRXQxDR_RXQSTS_Msk                        (0x3UL << ETH_MTLRXQxDR_RXQSTS_Pos) /*!< 0x00000030 */
15079 #define ETH_MTLRXQxDR_RXQSTS                            ETH_MTLRXQxDR_RXQSTS_Msk   /* MTL Rx Queue Fill-Level Status */
15080 #define ETH_MTLRXQxDR_RXQSTS_EMPTY                      ((uint32_t)0x00000000)   /* Rx Queue empty */
15081 #define ETH_MTLRXQxDR_RXQSTS_BELOWTHRESHOLD_Pos         (4U)
15082 #define ETH_MTLRXQxDR_RXQSTS_BELOWTHRESHOLD_Msk         (0x1UL << ETH_MTLRXQxDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
15083 #define ETH_MTLRXQxDR_RXQSTS_BELOWTHRESHOLD             ETH_MTLRXQxDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
15084 #define ETH_MTLRXQxDR_RXQSTS_ABOVETHRESHOLD_Pos         (5U)
15085 #define ETH_MTLRXQxDR_RXQSTS_ABOVETHRESHOLD_Msk         (0x1UL << ETH_MTLRXQxDR_RXQSTS_ABOVETHRESHOLD_Pos) /*!< 0x00000020 */
15086 #define ETH_MTLRXQxDR_RXQSTS_ABOVETHRESHOLD             ETH_MTLRXQxDR_RXQSTS_ABOVETHRESHOLD_Msk /* Rx Queue fill-level above flow-control activate threshold */
15087 #define ETH_MTLRXQxDR_RXQSTS_FULL_Pos                   (4U)
15088 #define ETH_MTLRXQxDR_RXQSTS_FULL_Msk                   (0x3UL << ETH_MTLRXQxDR_RXQSTS_FULL_Pos) /*!< 0x00000030 */
15089 #define ETH_MTLRXQxDR_RXQSTS_FULL                       ETH_MTLRXQxDR_RXQSTS_FULL_Msk /* Rx Queue full */
15090 #define ETH_MTLRXQxDR_RRCSTS_Pos                        (1U)
15091 #define ETH_MTLRXQxDR_RRCSTS_Msk                        (0x3UL << ETH_MTLRXQxDR_RRCSTS_Pos) /*!< 0x00000006 */
15092 #define ETH_MTLRXQxDR_RRCSTS                            ETH_MTLRXQxDR_RRCSTS_Msk   /* MTL Rx Queue Read Controller State */
15093 #define ETH_MTLRXQxDR_RRCSTS_IDLE                       ((uint32_t)0x00000000)   /* Idle state */
15094 #define ETH_MTLRXQxDR_RRCSTS_READINGDATA_Pos            (1U)
15095 #define ETH_MTLRXQxDR_RRCSTS_READINGDATA_Msk            (0x1UL << ETH_MTLRXQxDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
15096 #define ETH_MTLRXQxDR_RRCSTS_READINGDATA                ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
15097 #define ETH_MTLRXQxDR_RRCSTS_READINGSTATUS_Pos          (2U)
15098 #define ETH_MTLRXQxDR_RRCSTS_READINGSTATUS_Msk          (0x1UL << ETH_MTLRXQxDR_RRCSTS_READINGSTATUS_Pos) /*!< 0x00000004 */
15099 #define ETH_MTLRXQxDR_RRCSTS_READINGSTATUS              ETH_MTLRXQxDR_RRCSTS_READINGSTATUS_Msk /* Reading packet status (or timestamp) */
15100 #define ETH_MTLRXQxDR_RRCSTS_FLUSHING_Pos               (1U)
15101 #define ETH_MTLRXQxDR_RRCSTS_FLUSHING_Msk               (0x3UL << ETH_MTLRXQxDR_RRCSTS_FLUSHING_Pos) /*!< 0x00000006 */
15102 #define ETH_MTLRXQxDR_RRCSTS_FLUSHING                   ETH_MTLRXQxDR_RRCSTS_FLUSHING_Msk /* Flushing the packet data and status */
15103 #define ETH_MTLRXQxDR_RWCSTS_Pos                        (0U)
15104 #define ETH_MTLRXQxDR_RWCSTS_Msk                        (0x1UL << ETH_MTLRXQxDR_RWCSTS_Pos) /*!< 0x00000001 */
15105 #define ETH_MTLRXQxDR_RWCSTS                            ETH_MTLRXQxDR_RWCSTS_Msk   /* MTL Rx Queue Write Controller Active Status */
15106 
15107 /************ Bit definition for Ethernet MTL Rx Queue x Control Register   ***************/
15108 #define ETH_MTLRXQxCR_RQPA_Pos                          (3U)
15109 #define ETH_MTLRXQxCR_RQPA_Msk                          (0x1UL << ETH_MTLRXQxCR_RQPA_Pos) /*!< 0x00000008 */
15110 #define ETH_MTLRXQxCR_RQPA                              ETH_MTLRXQxCR_RQPA_Msk     /* Receive Queue Packet Arbitration */
15111 #define ETH_MTLRXQxCR_RQW_Pos                           (0U)
15112 #define ETH_MTLRXQxCR_RQW_Msk                           (0x7UL << ETH_MTLRXQxCR_RQW_Pos) /*!< 0x00000007 */
15113 #define ETH_MTLRXQxCR_RQW                               ETH_MTLRXQxCR_RQW_Msk      /* Receive Queue Weight */
15114 
15115 /************ Bit definition for Ethernet MTL Tx queue 1 ETS control Register   ***************/
15116 #define ETH_MTLTXQ1ECR_SLC_Pos                         (4U)
15117 #define ETH_MTLTXQ1ECR_SLC_Msk                         (0x7UL << ETH_MTLTXQ1ECR_SLC_Pos) /*!< 0x00000070 */
15118 #define ETH_MTLTXQ1ECR_SLC                             ETH_MTLTXQ1ECR_SLC_Msk     /* Slot Count */
15119 #define ETH_MTLTXQ1ECR_SLC_1SLOT                       ((uint32_t)0x00000000)   /* 1 Slot */
15120 #define ETH_MTLTXQ1ECR_SLC_2SLOT_Pos                   (4U)
15121 #define ETH_MTLTXQ1ECR_SLC_2SLOT_Msk                   (0x1UL << ETH_MTLTXQ1ECR_SLC_2SLOT_Pos) /*!< 0x00000010 */
15122 #define ETH_MTLTXQ1ECR_SLC_2SLOT                       ETH_MTLTXQ1ECR_SLC_2SLOT_Msk     /* 2 Slots */
15123 #define ETH_MTLTXQ1ECR_SLC_4SLOT_Pos                   (5U)
15124 #define ETH_MTLTXQ1ECR_SLC_4SLOT_Msk                   (0x1UL << ETH_MTLTXQ1ECR_SLC_4SLOT_Pos) /*!< 0x00000020 */
15125 #define ETH_MTLTXQ1ECR_SLC_4SLOT                       ETH_MTLTXQ1ECR_SLC_4SLOT_Msk     /* 4 Slots */
15126 #define ETH_MTLTXQ1ECR_SLC_8SLOT_Pos                   (4U)
15127 #define ETH_MTLTXQ1ECR_SLC_8SLOT_Msk                   (0x3UL << ETH_MTLTXQ1ECR_SLC_8SLOT_Pos) /*!< 0x00000030 */
15128 #define ETH_MTLTXQ1ECR_SLC_8SLOT                       ETH_MTLTXQ1ECR_SLC_8SLOT_Msk     /* 8 Slots */
15129 #define ETH_MTLTXQ1ECR_SLC_16SLOT_Pos                  (6U)
15130 #define ETH_MTLTXQ1ECR_SLC_16SLOT_Msk                  (0x1UL << ETH_MTLTXQ1ECR_SLC_16SLOT_Pos) /*!< 0x00000040 */
15131 #define ETH_MTLTXQ1ECR_SLC_16SLOT                      ETH_MTLTXQ1ECR_SLC_16SLOT_Msk     /* 16 Slots */
15132 #define ETH_MTLTXQ1ECR_CC_Pos                          (3U)
15133 #define ETH_MTLTXQ1ECR_CC_Msk                          (0x1UL << ETH_MTLTXQ1ECR_CC_Pos) /*!< 0x00000008 */
15134 #define ETH_MTLTXQ1ECR_CC                              ETH_MTLTXQ1ECR_CC_Msk     /* Credit Control */
15135 #define ETH_MTLTXQ1ECR_AVALG_Pos                       (2U)
15136 #define ETH_MTLTXQ1ECR_AVALG_Msk                       (0x1UL << ETH_MTLTXQ1ECR_AVALG_Pos) /*!< 0x00000004 */
15137 #define ETH_MTLTXQ1ECR_AVALG                           ETH_MTLTXQ1ECR_AVALG_Msk     /* Credit Control */
15138 
15139 /************ Bit definition for Ethernet MTL Tx queue 1 quantum weight Register   ***************/
15140 #define ETH_MTLTXQ1QWR_ISCQW_Pos                       (0U)
15141 #define ETH_MTLTXQ1QWR_ISCQW_Msk                       (0x3FFFUL << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00003FFF */
15142 #define ETH_MTLTXQ1QWR_ISCQW                           ETH_MTLTXQ1QWR_ISCQW_Msk     /* IdleSlopeCredit or Weights */
15143 
15144 /************ Bit definition for Ethernet MTL Tx queue 1 send slope credit Register   ***************/
15145 #define ETH_MTLTXQ1SSCR_SSC_Pos                        (0U)
15146 #define ETH_MTLTXQ1SSCR_SSC_Msk                        (0x3FFFUL << ETH_MTLTXQ1SSCR_SSC_Pos) /*!< 0x00003FFF */
15147 #define ETH_MTLTXQ1SSCR_SSC                            ETH_MTLTXQ1SSCR_SSC_Msk     /* sendSlopeCredit Value */
15148 
15149 /************ Bit definition for Ethernet MTL Tx Queue 1 hiCredit Register   ***************/
15150 #define ETH_MTLTXQ1HCR_HC_Pos                          (0U)
15151 #define ETH_MTLTXQ1HCR_HC_Msk                          (0x1FFFFFFFUL << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x1FFFFFFF */
15152 #define ETH_MTLTXQ1HCR_HC                              ETH_MTLTXQ1HCR_HC_Msk     /* hiCredit Value */
15153 
15154 /************ Bit definition for Ethernet MTL Tx queue 1 loCredit Register   ***************/
15155 #define ETH_MTLTXQ1LCR_LC_Pos                          (0U)
15156 #define ETH_MTLTXQ1LCR_LC_Msk                          (0x1FFFFFFFUL << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x1FFFFFFF */
15157 #define ETH_MTLTXQ1LCR_LC                              ETH_MTLTXQ1LCR_LC_Msk     /* loCredit Value */
15158 
15159 /************ Bit definition for Ethernet DMA Mode Register   ***************/
15160 #define ETH_DMAMR_INTM_Pos                            (16U)
15161 #define ETH_DMAMR_INTM_Msk                            (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */
15162 #define ETH_DMAMR_INTM                                ETH_DMAMR_INTM_Msk       /* This field defines the interrupt mode */
15163 #define ETH_DMAMR_INTM_0                              (0x0UL << ETH_DMAMR_INTM_Pos) /*!< 0x00000000 */
15164 #define ETH_DMAMR_INTM_1                              (0x1UL << ETH_DMAMR_INTM_Pos) /*!< 0x00010000 */
15165 #define ETH_DMAMR_INTM_2                              (0x2UL << ETH_DMAMR_INTM_Pos) /*!< 0x00020000 */
15166 #define ETH_DMAMR_TXPR_Pos                            (11U)
15167 #define ETH_DMAMR_TXPR_Msk                            (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
15168 #define ETH_DMAMR_TXPR                                ETH_DMAMR_TXPR_Msk         /* Transmit priority */
15169 #define ETH_DMAMR_DSPW_Pos                            (8U)
15170 #define ETH_DMAMR_DSPW_Msk                            (0x1UL << ETH_DMAMR_DSPW_Pos) /*!< 0x00000100 */
15171 #define ETH_DMAMR_DSPW                                ETH_DMAMR_DSPW_Msk         /* Descriptor Posted Write */
15172 #define ETH_DMAMR_TAA_Pos                             (2U)
15173 #define ETH_DMAMR_TAA_Msk                             (0x7UL << ETH_DMAMR_TAA_Pos) /*!< 0x000001C0 */
15174 #define ETH_DMAMR_TAA                                 ETH_DMAMR_TAA_Msk         /* Transmit Arbitration Algorithm */
15175 #define ETH_DMAMR_TAA_FP                              ((uint32_t)0x00000000)    /* Fixed priority */
15176 #define ETH_DMAMR_TAA_WSP_Pos                         (2U)
15177 #define ETH_DMAMR_TAA_WSP_Msk                         (0x1UL << ETH_DMAMR_TAA_WSP_Pos) /*!< 0x00000004 */
15178 #define ETH_DMAMR_TAA_WSP                             ETH_DMAMR_TAA_WSP_Msk  /* Weighted Strict priority (WSP) */
15179 #define ETH_DMAMR_TAA_WRR_Pos                         (3U)
15180 #define ETH_DMAMR_TAA_WRR_Msk                         (0x1UL << ETH_DMAMR_TAA_WRR_Pos) /*!< 0x00000008 */
15181 #define ETH_DMAMR_TAA_WRR                             ETH_DMAMR_TAA_WRR_Msk  /* Weighted Round-Robin (WRR) */
15182 #define ETH_DMAMR_SWR_Pos                             (0U)
15183 #define ETH_DMAMR_SWR_Msk                             (0x1UL << ETH_DMAMR_SWR_Pos) /*!< 0x00000001 */
15184 #define ETH_DMAMR_SWR                                 ETH_DMAMR_SWR_Msk  /* Software Reset */
15185 
15186 /************ Bit definition for Ethernet DMA System bus mode Register   ***************/
15187 #define ETH_DMASBMR_ENLPI_Pos                         (31U)
15188 #define ETH_DMASBMR_ENLPI_Msk                         (0x1UL << ETH_DMASBMR_ENLPI_Pos) /*!< 0x80000000 */
15189 #define ETH_DMASBMR_ENLPI                             ETH_DMASBMR_ENLPI_Msk       /* Enable Low Power Interface (LPI) */
15190 #define ETH_DMASBMR_LPIXPKT_Pos                       (30U)
15191 #define ETH_DMASBMR_LPIXPKT_Msk                       (0x1UL << ETH_DMASBMR_LPIXPKT_Pos) /*!< 0x40000000 */
15192 #define ETH_DMASBMR_LPIXPKT                           ETH_DMASBMR_LPIXPKT_Msk       /* Unlock on Magic Packet or Remote wakeup Packet */
15193 #define ETH_DMASBMR_WR_OSR_LMT_Pos                    (24U)
15194 #define ETH_DMASBMR_WR_OSR_LMT_Msk                    (0x3UL << ETH_DMASBMR_WR_OSR_LMT_Pos) /*!< 0x03000000 */
15195 #define ETH_DMASBMR_WR_OSR_LMT                        ETH_DMASBMR_WR_OSR_LMT_Msk            /*!< AXI Maximum Write Outstanding Request Limit */
15196 #define ETH_DMASBMR_WR_OSR_LMT_0                      (0x1UL << ETH_DMASBMR_WR_OSR_LMT_Pos) /*!< 0x01000000 */
15197 #define ETH_DMASBMR_WR_OSR_LMT_1                      (0x2UL << ETH_DMASBMR_WR_OSR_LMT_Pos) /*!< 0x02000000 */
15198 #define ETH_DMASBMR_RD_OSR_LMT_Pos                    (16U)
15199 #define ETH_DMASBMR_RD_OSR_LMT_Msk                    (0x3UL << ETH_DMASBMR_RD_OSR_LMT_Pos) /*!< 0x00030000 */
15200 #define ETH_DMASBMR_RD_OSR_LMT                        ETH_DMASBMR_RD_OSR_LMT_Msk            /*!< AXI Maximum Read Outstanding Request Limit */
15201 #define ETH_DMASBMR_RD_OSR_LMT_0                      (0x1UL << ETH_DMASBMR_RD_OSR_LMT_Pos) /*!< 0x00010000 */
15202 #define ETH_DMASBMR_RD_OSR_LMT_1                      (0x2UL << ETH_DMASBMR_RD_OSR_LMT_Pos) /*!< 0x00020000 */
15203 #define ETH_DMASBMR_ONEKBBE_Pos                       (13U)
15204 #define ETH_DMASBMR_ONEKBBE_Msk                       (0x1UL << ETH_DMASBMR_ONEKBBE_Pos) /*!< 0x00002000 */
15205 #define ETH_DMASBMR_ONEKBBE                           ETH_DMASBMR_ONEKBBE_Msk       /* 1 Kbyte Boundary Crossing Enable for the AXI Master */
15206 #define ETH_DMASBMR_AAL_Pos                           (12U)
15207 #define ETH_DMASBMR_AAL_Msk                           (0x1UL << ETH_DMASBMR_AAL_Pos) /*!< 0x00001000 */
15208 #define ETH_DMASBMR_AAL                               ETH_DMASBMR_AAL_Msk      /* Address-Aligned Beats */
15209 #define ETH_DMASBMR_AALE_Pos                          (10U)
15210 #define ETH_DMASBMR_AALE_Msk                          (0x1UL << ETH_DMASBMR_AALE_Pos) /*!< 0x00000400 */
15211 #define ETH_DMASBMR_AALE                              ETH_DMASBMR_AALE_Msk       /* Automatic AXI LPI enable */
15212 #define ETH_DMASBMR_BLEN256_Pos                       (7U)
15213 #define ETH_DMASBMR_BLEN256_Msk                       (0x1UL << ETH_DMASBMR_BLEN256_Pos) /*!< 0x00000080 */
15214 #define ETH_DMASBMR_BLEN256                           ETH_DMASBMR_BLEN256_Msk       /* AXI Burst Length 256 */
15215 #define ETH_DMASBMR_BLEN128_Pos                       (6U)
15216 #define ETH_DMASBMR_BLEN128_Msk                       (0x1UL << ETH_DMASBMR_BLEN128_Pos) /*!< 0x00000040 */
15217 #define ETH_DMASBMR_BLEN128                           ETH_DMASBMR_BLEN128_Msk       /* AXI Burst Length 128 */
15218 #define ETH_DMASBMR_BLEN64_Pos                        (5U)
15219 #define ETH_DMASBMR_BLEN64_Msk                        (0x1UL << ETH_DMASBMR_BLEN64_Pos) /*!< 0x00000020 */
15220 #define ETH_DMASBMR_BLEN64                            ETH_DMASBMR_BLEN64_Msk       /* AXI Burst Length 64 */
15221 #define ETH_DMASBMR_BLEN32_Pos                        (4U)
15222 #define ETH_DMASBMR_BLEN32_Msk                        (0x1UL << ETH_DMASBMR_BLEN32_Pos) /*!< 0x00000010 */
15223 #define ETH_DMASBMR_BLEN32                            ETH_DMASBMR_BLEN32_Msk       /* AXI Burst Length 32 */
15224 #define ETH_DMASBMR_BLEN16_Pos                        (3U)
15225 #define ETH_DMASBMR_BLEN16_Msk                        (0x1UL << ETH_DMASBMR_BLEN16_Pos) /*!< 0x00000008 */
15226 #define ETH_DMASBMR_BLEN16                            ETH_DMASBMR_BLEN16_Msk       /* AXI Burst Length 16 */
15227 #define ETH_DMASBMR_BLEN8_Pos                         (2U)
15228 #define ETH_DMASBMR_BLEN8_Msk                         (0x1UL << ETH_DMASBMR_BLEN8_Pos) /*!< 0x00000004 */
15229 #define ETH_DMASBMR_BLEN8                             ETH_DMASBMR_BLEN8_Msk       /* AXI Burst Length 8 */
15230 #define ETH_DMASBMR_BLEN4_Pos                         (1U)
15231 #define ETH_DMASBMR_BLEN4_Msk                         (0x1UL << ETH_DMASBMR_BLEN4_Pos) /*!< 0x00000002 */
15232 #define ETH_DMASBMR_BLEN4                             ETH_DMASBMR_BLEN4_Msk       /* AXI Burst Length 4 */
15233 #define ETH_DMASBMR_FB_Pos                            (0U)
15234 #define ETH_DMASBMR_FB_Msk                            (0x1UL << ETH_DMASBMR_FB_Pos) /*!< 0x00000001 */
15235 #define ETH_DMASBMR_FB                                ETH_DMASBMR_FB_Msk       /* Fixed Burst Length */
15236 
15237 /************ Bit definition for Ethernet DMA Interrupt Status Register   ***************/
15238 #define ETH_DMAISR_MACIS_Pos                          (17U)
15239 #define ETH_DMAISR_MACIS_Msk                          (0x1UL << ETH_DMAISR_MACIS_Pos) /*!< 0x00020000 */
15240 #define ETH_DMAISR_MACIS                              ETH_DMAISR_MACIS_Msk     /* MAC Interrupt Status */
15241 #define ETH_DMAISR_MTLIS_Pos                          (16U)
15242 #define ETH_DMAISR_MTLIS_Msk                          (0x1UL << ETH_DMAISR_MTLIS_Pos) /*!< 0x00010000 */
15243 #define ETH_DMAISR_MTLIS                              ETH_DMAISR_MTLIS_Msk     /* MAC Interrupt Status */
15244 #define ETH_DMAISR_DMAC1IS_Pos                        (1U)
15245 #define ETH_DMAISR_DMAC1IS_Msk                        (0x1UL << ETH_DMAISR_DMAC1IS_Pos) /*!< 0x00000001 */
15246 #define ETH_DMAISR_DMAC1IS                            ETH_DMAISR_DMAC1IS_Msk    /* DMA Channel 1 Interrupt Status */
15247 #define ETH_DMAISR_DMAC0IS_Pos                        (0U)
15248 #define ETH_DMAISR_DMAC0IS_Msk                        (0x1UL << ETH_DMAISR_DMAC0IS_Pos) /*!< 0x00000001 */
15249 #define ETH_DMAISR_DMAC0IS                            ETH_DMAISR_DMAC0IS_Msk    /* DMA Channel 0 Interrupt Status */
15250 
15251 /************ Bit definition for Ethernet DMA Debug Status Register   ***************/
15252 #define ETH_DMADSR_TPS1_Pos                            (20U)
15253 #define ETH_DMADSR_TPS1_Msk                            (0xFUL << ETH_DMADSR_TPS1_Pos) /*!< 0x00F00000 */
15254 #define ETH_DMADSR_TPS1                                ETH_DMADSR_TPS1_Msk       /* DMA Channel 1 Transmit Process State */
15255 #define ETH_DMADSR_TPS1_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Transmit Command issued) */
15256 #define ETH_DMADSR_TPS1_FETCHING_Pos                   (20U)
15257 #define ETH_DMADSR_TPS1_FETCHING_Msk                   (0x1UL << ETH_DMADSR_TPS1_FETCHING_Pos) /*!< 0x00100000 */
15258 #define ETH_DMADSR_TPS1_FETCHING                       ETH_DMADSR_TPS1_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
15259 #define ETH_DMADSR_TPS1_WAITING_Pos                    (21U)
15260 #define ETH_DMADSR_TPS1_WAITING_Msk                    (0x1UL << ETH_DMADSR_TPS1_WAITING_Pos) /*!< 0x00200000 */
15261 #define ETH_DMADSR_TPS1_WAITING                        ETH_DMADSR_TPS1_WAITING_Msk /* Running (Waiting for status) */
15262 #define ETH_DMADSR_TPS1_READING_Pos                    (20U)
15263 #define ETH_DMADSR_TPS1_READING_Msk                    (0x3UL << ETH_DMADSR_TPS1_READING_Pos) /*!< 0x00300000 */
15264 #define ETH_DMADSR_TPS1_READING                        ETH_DMADSR_TPS1_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */
15265 #define ETH_DMADSR_TPS1_TIMESTAMP_WR_Pos               (22U)
15266 #define ETH_DMADSR_TPS1_TIMESTAMP_WR_Msk               (0x1UL << ETH_DMADSR_TPS1_TIMESTAMP_WR_Pos) /*!< 0x00400000 */
15267 #define ETH_DMADSR_TPS1_TIMESTAMP_WR                   ETH_DMADSR_TPS1_TIMESTAMP_WR_Msk /* Timestamp write state */
15268 #define ETH_DMADSR_TPS1_SUSPENDED_Pos                  (21U)
15269 #define ETH_DMADSR_TPS1_SUSPENDED_Msk                  (0x3UL << ETH_DMADSR_TPS1_SUSPENDED_Pos) /*!< 0x00600000 */
15270 #define ETH_DMADSR_TPS1_SUSPENDED                      ETH_DMADSR_TPS1_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */
15271 #define ETH_DMADSR_TPS1_CLOSING_Pos                    (20U)
15272 #define ETH_DMADSR_TPS1_CLOSING_Msk                    (0x7UL << ETH_DMADSR_TPS1_CLOSING_Pos) /*!< 0x00700000 */
15273 #define ETH_DMADSR_TPS1_CLOSING                        ETH_DMADSR_TPS1_CLOSING_Msk /* Running (Closing Tx Descriptor) */
15274 #define ETH_DMADSR_RPS1_Pos                            (16U)
15275 #define ETH_DMADSR_RPS1_Msk                            (0xFUL << ETH_DMADSR_RPS1_Pos) /*!< 0x000F0000 */
15276 #define ETH_DMADSR_RPS1                                ETH_DMADSR_RPS1_Msk       /* DMA Channel 1 Receive Process State */
15277 #define ETH_DMADSR_RPS1_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Receive Command issued) */
15278 #define ETH_DMADSR_RPS1_FETCHING_Pos                   (16U)
15279 #define ETH_DMADSR_RPS1_FETCHING_Msk                   (0x1UL << ETH_DMADSR_RPS1_FETCHING_Pos) /*!< 0x00010000 */
15280 #define ETH_DMADSR_RPS1_FETCHING                       ETH_DMADSR_RPS1_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
15281 #define ETH_DMADSR_RPS1_WAITING_Pos                    (16U)
15282 #define ETH_DMADSR_RPS1_WAITING_Msk                    (0x3UL << ETH_DMADSR_RPS1_WAITING_Pos) /*!< 0x00030000 */
15283 #define ETH_DMADSR_RPS1_WAITING                        ETH_DMADSR_RPS1_WAITING_Msk /* Running (Waiting for status) */
15284 #define ETH_DMADSR_RPS1_SUSPENDED_Pos                  (18U)
15285 #define ETH_DMADSR_RPS1_SUSPENDED_Msk                  (0x1UL << ETH_DMADSR_RPS1_SUSPENDED_Pos) /*!< 0x00040000 */
15286 #define ETH_DMADSR_RPS1_SUSPENDED                      ETH_DMADSR_RPS1_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */
15287 #define ETH_DMADSR_RPS1_CLOSING_Pos                    (16U)
15288 #define ETH_DMADSR_RPS1_CLOSING_Msk                    (0x5UL << ETH_DMADSR_RPS1_CLOSING_Pos) /*!< 0x00050000 */
15289 #define ETH_DMADSR_RPS1_CLOSING                        ETH_DMADSR_RPS1_CLOSING_Msk /* Running (Closing the Rx Descriptor) */
15290 #define ETH_DMADSR_RPS1_TIMESTAMP_WR_Pos               (17U)
15291 #define ETH_DMADSR_RPS1_TIMESTAMP_WR_Msk               (0x3UL << ETH_DMADSR_RPS1_TIMESTAMP_WR_Pos) /*!< 0x00060000 */
15292 #define ETH_DMADSR_RPS1_TIMESTAMP_WR                   ETH_DMADSR_RPS1_TIMESTAMP_WR_Msk /* Timestamp write state */
15293 #define ETH_DMADSR_RPS1_TRANSFERRING_Pos               (16U)
15294 #define ETH_DMADSR_RPS1_TRANSFERRING_Msk               (0x7UL << ETH_DMADSR_RPS1_TRANSFERRING_Pos) /*!< 0x00070000 */
15295 #define ETH_DMADSR_RPS1_TRANSFERRING                   ETH_DMADSR_RPS1_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */
15296 #define ETH_DMADSR_TPS0_Pos                            (12U)
15297 #define ETH_DMADSR_TPS0_Msk                            (0xFUL << ETH_DMADSR_TPS0_Pos) /*!< 0x0000F000 */
15298 #define ETH_DMADSR_TPS0                                ETH_DMADSR_TPS0_Msk       /* DMA Channel 0 Transmit Process State */
15299 #define ETH_DMADSR_TPS0_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Transmit Command issued) */
15300 #define ETH_DMADSR_TPS0_FETCHING_Pos                   (12U)
15301 #define ETH_DMADSR_TPS0_FETCHING_Msk                   (0x1UL << ETH_DMADSR_TPS0_FETCHING_Pos) /*!< 0x00001000 */
15302 #define ETH_DMADSR_TPS0_FETCHING                       ETH_DMADSR_TPS0_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
15303 #define ETH_DMADSR_TPS0_WAITING_Pos                    (13U)
15304 #define ETH_DMADSR_TPS0_WAITING_Msk                    (0x1UL << ETH_DMADSR_TPS0_WAITING_Pos) /*!< 0x00002000 */
15305 #define ETH_DMADSR_TPS0_WAITING                        ETH_DMADSR_TPS0_WAITING_Msk /* Running (Waiting for status) */
15306 #define ETH_DMADSR_TPS0_READING_Pos                    (12U)
15307 #define ETH_DMADSR_TPS0_READING_Msk                    (0x3UL << ETH_DMADSR_TPS0_READING_Pos) /*!< 0x00003000 */
15308 #define ETH_DMADSR_TPS0_READING                        ETH_DMADSR_TPS0_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */
15309 #define ETH_DMADSR_TPS0_TIMESTAMP_WR_Pos               (14U)
15310 #define ETH_DMADSR_TPS0_TIMESTAMP_WR_Msk               (0x1UL << ETH_DMADSR_TPS0_TIMESTAMP_WR_Pos) /*!< 0x00004000 */
15311 #define ETH_DMADSR_TPS0_TIMESTAMP_WR                   ETH_DMADSR_TPS0_TIMESTAMP_WR_Msk /* Timestamp write state */
15312 #define ETH_DMADSR_TPS0_SUSPENDED_Pos                  (13U)
15313 #define ETH_DMADSR_TPS0_SUSPENDED_Msk                  (0x3UL << ETH_DMADSR_TPS0_SUSPENDED_Pos) /*!< 0x00006000 */
15314 #define ETH_DMADSR_TPS0_SUSPENDED                      ETH_DMADSR_TPS0_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */
15315 #define ETH_DMADSR_TPS0_CLOSING_Pos                    (12U)
15316 #define ETH_DMADSR_TPS0_CLOSING_Msk                    (0x7UL << ETH_DMADSR_TPS0_CLOSING_Pos) /*!< 0x00007000 */
15317 #define ETH_DMADSR_TPS0_CLOSING                        ETH_DMADSR_TPS0_CLOSING_Msk /* Running (Closing Tx Descriptor) */
15318 #define ETH_DMADSR_RPS0_Pos                            (8U)
15319 #define ETH_DMADSR_RPS0_Msk                            (0xFUL << ETH_DMADSR_RPS0_Pos) /*!< 0x00000F00 */
15320 #define ETH_DMADSR_RPS0                                ETH_DMADSR_RPS0_Msk       /* DMA Channel 0 Receive Process State */
15321 #define ETH_DMADSR_RPS0_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Receive Command issued) */
15322 #define ETH_DMADSR_RPS0_FETCHING_Pos                   (8U)
15323 #define ETH_DMADSR_RPS0_FETCHING_Msk                   (0x1UL << ETH_DMADSR_RPS0_FETCHING_Pos) /*!< 0x00000100 */
15324 #define ETH_DMADSR_RPS0_FETCHING                       ETH_DMADSR_RPS0_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
15325 #define ETH_DMADSR_RPS0_WAITING_Pos                    (8U)
15326 #define ETH_DMADSR_RPS0_WAITING_Msk                    (0x3UL << ETH_DMADSR_RPS0_WAITING_Pos) /*!< 0x00000300 */
15327 #define ETH_DMADSR_RPS0_WAITING                        ETH_DMADSR_RPS0_WAITING_Msk /* Running (Waiting for status) */
15328 #define ETH_DMADSR_RPS0_SUSPENDED_Pos                  (10U)
15329 #define ETH_DMADSR_RPS0_SUSPENDED_Msk                  (0x1UL << ETH_DMADSR_RPS0_SUSPENDED_Pos) /*!< 0x00000400 */
15330 #define ETH_DMADSR_RPS0_SUSPENDED                      ETH_DMADSR_RPS0_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */
15331 #define ETH_DMADSR_RPS0_CLOSING_Pos                    (8U)
15332 #define ETH_DMADSR_RPS0_CLOSING_Msk                    (0x5UL << ETH_DMADSR_RPS0_CLOSING_Pos) /*!< 0x00000500 */
15333 #define ETH_DMADSR_RPS0_CLOSING                        ETH_DMADSR_RPS0_CLOSING_Msk /* Running (Closing the Rx Descriptor) */
15334 #define ETH_DMADSR_RPS0_TIMESTAMP_WR_Pos               (9U)
15335 #define ETH_DMADSR_RPS0_TIMESTAMP_WR_Msk               (0x3UL << ETH_DMADSR_RPS0_TIMESTAMP_WR_Pos) /*!< 0x00000600 */
15336 #define ETH_DMADSR_RPS0_TIMESTAMP_WR                   ETH_DMADSR_RPS0_TIMESTAMP_WR_Msk /* Timestamp write state */
15337 #define ETH_DMADSR_RPS0_TRANSFERRING_Pos               (8U)
15338 #define ETH_DMADSR_RPS0_TRANSFERRING_Msk               (0x7UL << ETH_DMADSR_RPS0_TRANSFERRING_Pos) /*!< 0x00000700 */
15339 #define ETH_DMADSR_RPS0_TRANSFERRING                   ETH_DMADSR_RPS0_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */
15340 #define ETH_DMADSR_AXRHSTS_Pos                         (1U)
15341 #define ETH_DMADSR_AXRHSTS_Msk                         (0x1UL << ETH_DMADSR_AXRHSTS_Pos) /*!< 0x00000002 */
15342 #define ETH_DMADSR_AXRHSTS                             ETH_DMADSR_AXRHSTS_Msk /* AXI Master Read Channel Status */
15343 #define ETH_DMADSR_AXWHSTS_Pos                         (1U)
15344 #define ETH_DMADSR_AXWHSTS_Msk                         (0x1UL << ETH_DMADSR_AXWHSTS_Pos) /*!< 0x00000001 */
15345 #define ETH_DMADSR_AXWHSTS                             ETH_DMADSR_AXWHSTS_Msk /* AXI Master Write Channel */
15346 
15347 /************ Bit definition for Ethernet DMA AXI4 transmit channel ACE control Register   ***************/
15348 #define ETH_DMAA4TXACR_THC_Pos                         (16U)
15349 #define ETH_DMAA4TXACR_THC_Msk                         (0xFUL << ETH_DMAA4TXACR_THC_Pos) /*!< 0x000F0000 */
15350 #define ETH_DMAA4TXACR_THC                             ETH_DMAA4TXACR_THC_Msk       /* Transmit DMA First Packet Buffer or TSO Header Cache Control */
15351 #define ETH_DMAA4TXACR_TEC_Pos                         (8U)
15352 #define ETH_DMAA4TXACR_TEC_Msk                         (0xFUL << ETH_DMAA4TXACR_TEC_Pos) /*!< 0x00000F00 */
15353 #define ETH_DMAA4TXACR_TEC                             ETH_DMAA4TXACR_TEC_Msk       /* Transmit DMA Extended Packet Buffer or TSO Payload Cache Control */
15354 #define ETH_DMAA4TXACR_TDRC_Pos                        (0U)
15355 #define ETH_DMAA4TXACR_TDRC_Msk                        (0xFUL << ETH_DMAA4TXACR_TDRC_Pos) /*!< 0x0000000F */
15356 #define ETH_DMAA4TXACR_TDRC                            ETH_DMAA4TXACR_TDRC_Msk       /* Transmit DMA Extended Packet Buffer or TSO Payload Cache Control */
15357 
15358 /************ Bit definition for Ethernet DMA AXI4 receive channel ACE control Register   ***************/
15359 #define ETH_DMAA4RXACR_RDC_Pos                         (24U)
15360 #define ETH_DMAA4RXACR_RDC_Msk                         (0xFUL << ETH_DMAA4RXACR_RDC_Pos) /*!< 0x0F000000 */
15361 #define ETH_DMAA4RXACR_RDC                             ETH_DMAA4RXACR_RDC_Msk       /* Receive DMA Buffer Cache Control */
15362 #define ETH_DMAA4RXACR_RHC_Pos                         (16U)
15363 #define ETH_DMAA4RXACR_RHC_Msk                         (0xFUL << ETH_DMAA4RXACR_RHC_Pos) /*!< 0x000F0000 */
15364 #define ETH_DMAA4RXACR_RHC                             ETH_DMAA4RXACR_RHC_Msk       /* Receive DMA Header Cache Control */
15365 #define ETH_DMAA4RXACR_RPC_Pos                         (8U)
15366 #define ETH_DMAA4RXACR_RPC_Msk                         (0xFUL << ETH_DMAA4RXACR_RPC_Pos) /*!< 0x00000F00 */
15367 #define ETH_DMAA4RXACR_RPC                             ETH_DMAA4RXACR_RPC_Msk       /* Receive DMA Payload Cache Control */
15368 #define ETH_DMAA4RXACR_RDWC_Pos                        (0U)
15369 #define ETH_DMAA4RXACR_RDWC_Msk                        (0xFUL << ETH_DMAA4RXACR_RDWC_Pos) /*!< 0x0000000F */
15370 #define ETH_DMAA4RXACR_RDWC                            ETH_DMAA4RXACR_RDWC_Msk   /* Receive DMA Write Descriptor Cache Control */
15371 
15372 /************ Bit definition for Ethernet DMA AXI4 descriptor ACE control Register   ***************/
15373 #define ETH_DMAA4DACR_RDRC_Pos                         (8U)
15374 #define ETH_DMAA4DACR_RDRC_Msk                         (0xFUL << ETH_DMAA4DACR_RDRC_Pos) /*!< 0x00000F00 */
15375 #define ETH_DMAA4DACR_RDRC                             ETH_DMAA4DACR_RDRC_Msk       /* Receive DMA Read Descriptor Cache control */
15376 #define ETH_DMAA4DACR_TDWD_Pos                         (4U)
15377 #define ETH_DMAA4DACR_TDWD_Msk                         (0xFUL << ETH_DMAA4DACR_TDWD_Pos) /*!< 0x00000030 */
15378 #define ETH_DMAA4DACR_TDWD                             ETH_DMAA4DACR_TDWD_Msk       /* Transmit DMA Write Descriptor Domain control */
15379 #define ETH_DMAA4DACR_TDWC_Pos                         (0U)
15380 #define ETH_DMAA4DACR_TDWC_Msk                         (0xFUL << ETH_DMAA4DACR_TDWC_Pos) /*!< 0x0000000F */
15381 #define ETH_DMAA4DACR_TDWC                             ETH_DMAA4DACR_TDWC_Msk       /* Transmit DMA Write Descriptor Cache control */
15382 
15383 /************ Bit definition for Ethernet DMA AXI4 LPI Entry Interval Register   ***************/
15384 /* Bit definition for Ethernet DMA AXI4 LPI Entry Interval register */
15385 #define ETH_DMALPIEI_LPIEI_Pos                         (0U)
15386 #define ETH_DMALPIEI_LPIEI_Msk                         (0xFUL << ETH_DMALPIEI_LPIEI_Pos) /*!< 0x0000000F */
15387 #define ETH_DMALPIEI_LPIEI                             ETH_DMALPIEI_LPIEI_Msk   /* LPI Entry Interval */
15388 
15389 /************ Bit definition for Ethernet DMA TBS control Register   ***************/
15390 #define ETH_DMATBSCTRL0R_FTOS_Pos                      (8U)
15391 #define ETH_DMATBSCTRL0R_FTOS_Msk                      (0xFFFFFFUL << ETH_DMATBSCTRL0R_FTOS_Pos) /*!< 0xFFFFFF00 */
15392 #define ETH_DMATBSCTRL0R_FTOS                          ETH_DMATBSCTRL0R_FTOS_Msk   /* Fetch time offset */
15393 #define ETH_DMATBSCTRL0R_FGOS_Pos                      (4U)
15394 #define ETH_DMATBSCTRL0R_FGOS_Msk                      (0x7UL << ETH_DMATBSCTRL0R_FGOS_Pos) /*!< 0x00000070 */
15395 #define ETH_DMATBSCTRL0R_FGOS                          ETH_DMATBSCTRL0R_FGOS_Msk   /* Fetch GSN offset */
15396 #define ETH_DMATBSCTRL0R_FTOV_Pos                      (0U)
15397 #define ETH_DMATBSCTRL0R_FTOV_Msk                      (0x1UL << ETH_DMATBSCTRL0R_FTOV_Pos) /*!< 0x00000001 */
15398 #define ETH_DMATBSCTRL0R_FTOV                          ETH_DMATBSCTRL0R_FTOV_Msk   /* Fetch time offset valid */
15399 
15400 /************ Bit definition for Ethernet DMA Channel x Control Register   ***************/
15401 #define ETH_DMACxCR_DSL_Pos                            (18U)
15402 #define ETH_DMACxCR_DSL_Msk                            (0x7UL << ETH_DMACxCR_DSL_Pos) /*!< 0x001C0000 */
15403 #define ETH_DMACxCR_DSL                                ETH_DMACxCR_DSL_Msk       /* Descriptor Skip Length */
15404 #define ETH_DMACxCR_DSL_0BIT                           ((uint32_t)0x00000000)
15405 #define ETH_DMACxCR_DSL_32BIT                          ((uint32_t)0x00040000)
15406 #define ETH_DMACxCR_DSL_64BIT                          ((uint32_t)0x00080000)
15407 #define ETH_DMACxCR_DSL_128BIT                         ((uint32_t)0x00100000)
15408 #define ETH_DMACxCR_PBLX8_Pos                          (16U)
15409 #define ETH_DMACxCR_PBLX8_Msk                          (0x1UL << ETH_DMACxCR_PBLX8_Pos) /*!< 0x00010000 */
15410 #define ETH_DMACxCR_PBLX8                              ETH_DMACxCR_PBLX8_Msk  /* 8xPBL mode */
15411 #define ETH_DMACxCR_MSS_Pos                            (0U)
15412 #define ETH_DMACxCR_MSS_Msk                            (0x3FFFUL << ETH_DMACxCR_MSS_Pos) /*!< 0x00003FFF */
15413 #define ETH_DMACxCR_MSS                                ETH_DMACxCR_MSS_Msk       /* Maximum Segment Size */
15414 
15415 /************ Bit definition for Ethernet DMA Channel x transmit control Register   ***************/
15416 #define ETH_DMACxTXCR_EDSE_Pos                         (28U)
15417 #define ETH_DMACxTXCR_EDSE_Msk                         (0x1UL << ETH_DMACxTXCR_EDSE_Pos) /*!< 0x10000000 */
15418 #define ETH_DMACxTXCR_EDSE                             ETH_DMACxTXCR_EDSE_Msk       /* Enhanced Descriptor Enable */
15419 #define ETH_DMACxTXCR_TQOS_Pos                         (24U)
15420 #define ETH_DMACxTXCR_TQOS_Msk                         (0xFUL << ETH_DMACxTXCR_TQOS_Pos) /*!< 0x0F000000 */
15421 #define ETH_DMACxTXCR_TQOS                             ETH_DMACxTXCR_TQOS_Msk       /* Transmit QOS */
15422 #define ETH_DMACxTXCR_TXPBL_Pos                        (16U)
15423 #define ETH_DMACxTXCR_TXPBL_Msk                        (0x3FUL << ETH_DMACxTXCR_TXPBL_Pos) /*!< 0x003F0000 */
15424 #define ETH_DMACxTXCR_TXPBL                            ETH_DMACxTXCR_TXPBL_Msk       /* Transmit Programmable Burst Length */
15425 #define ETH_DMACxTXCR_TXPBL_1PBL                       (0x1U << ETH_DMACxTXCR_TXPBL_Pos)                   /*!< 0x00010000 */
15426 #define ETH_DMACxTXCR_TXPBL_2PBL                       (0x2U << ETH_DMACxTXCR_TXPBL_Pos)                   /*!< 0x00020000 */
15427 #define ETH_DMACxTXCR_TXPBL_4PBL                       (0x4U << ETH_DMACxTXCR_TXPBL_Pos)                   /*!< 0x00040000 */
15428 #define ETH_DMACxTXCR_TXPBL_8PBL                       (0x8U << ETH_DMACxTXCR_TXPBL_Pos)                   /*!< 0x00080000 */
15429 #define ETH_DMACxTXCR_TXPBL_16PBL                      (0x10U << ETH_DMACxTXCR_TXPBL_Pos)                  /*!< 0x00100000 */
15430 #define ETH_DMACxTXCR_TXPBL_32PBL                      (0x20U << ETH_DMACxTXCR_TXPBL_Pos)                  /*!< 0x00200000 */
15431 #define ETH_DMACxTXCR_IPBL_Pos                         (15U)
15432 #define ETH_DMACxTXCR_IPBL_Msk                         (0x1UL << ETH_DMACxTXCR_IPBL_Pos) /*!< 0x00008000 */
15433 #define ETH_DMACxTXCR_IPBL                             ETH_DMACxTXCR_IPBL_Msk       /* Ignore PBL Requirement */
15434 #define ETH_DMACxTXCR_TSE_Pos                          (12U)
15435 #define ETH_DMACxTXCR_TSE_Msk                          (0x1UL << ETH_DMACxTXCR_TSE_Pos) /*!< 0x00001000 */
15436 #define ETH_DMACxTXCR_TSE                              ETH_DMACxTXCR_TSE_Msk       /* TCP Segmentation Enabled */
15437 #define ETH_DMACxTXCR_OSF_Pos                          (4U)
15438 #define ETH_DMACxTXCR_OSF_Msk                          (0x1UL << ETH_DMACxTXCR_OSF_Pos) /*!< 0x00000010 */
15439 #define ETH_DMACxTXCR_OSF                              ETH_DMACxTXCR_OSF_Msk       /* Operate on Second Packet */
15440 #define ETH_DMACxTXCR_TCW_Pos                          (1U)
15441 #define ETH_DMACxTXCR_TCW_Msk                          (0x7UL << ETH_DMACxTXCR_TCW_Pos) /*!< 0x0000000E */
15442 #define ETH_DMACxTXCR_TCW                              ETH_DMACxTXCR_TCW_Msk       /* Transmit Channel Weight */
15443 #define ETH_DMACxTXCR_TCW_1                            (0x1U << ETH_DMACxTXCR_TCW_Pos)  /*!< 0x00000002 */
15444 #define ETH_DMACxTXCR_TCW_2                            (0x2U << ETH_DMACxTXCR_TCW_Pos)  /*!< 0x00000004 */
15445 #define ETH_DMACxTXCR_TCW_3                            (0x3U << ETH_DMACxTXCR_TCW_Pos)  /*!< 0x00000006 */
15446 #define ETH_DMACxTXCR_TCW_4                            (0x4U << ETH_DMACxTXCR_TCW_Pos)  /*!< 0x00000008 */
15447 #define ETH_DMACxTXCR_TCW_5                            (0x5U << ETH_DMACxTXCR_TCW_Pos)  /*!< 0x0000000A */
15448 #define ETH_DMACxTXCR_TCW_6                            (0x6U << ETH_DMACxTXCR_TCW_Pos)  /*!< 0x0000000C */
15449 #define ETH_DMACxTXCR_TCW_7                            (0x7U << ETH_DMACxTXCR_TCW_Pos)  /*!< 0x0000000E */
15450 #define ETH_DMACxTXCR_ST_Pos                           (0U)
15451 #define ETH_DMACxTXCR_ST_Msk                           (0x1UL << ETH_DMACxTXCR_ST_Pos) /*!< 0x00000001 */
15452 #define ETH_DMACxTXCR_ST                               ETH_DMACxTXCR_ST_Msk       /* Start or Stop Transmission Command */
15453 
15454 /************ Bit definition for Ethernet DMA Channel x receive control Register   ***************/
15455 #define ETH_DMACxRXCR_RPF_Pos                         (31U)
15456 #define ETH_DMACxRXCR_RPF_Msk                         (0x1UL << ETH_DMACxRXCR_RPF_Pos) /*!< 0x80000000 */
15457 #define ETH_DMACxRXCR_RPF                             ETH_DMACxRXCR_RPF_Msk       /* DMA Rx Channel Packet Flush */
15458 #define ETH_DMACxRXCR_RQOS_Pos                        (24U)
15459 #define ETH_DMACxRXCR_RQOS_Msk                        (0xFUL << ETH_DMACxRXCR_RQOS_Pos) /*!< 0x0F000000 */
15460 #define ETH_DMACxRXCR_RQOS                            ETH_DMACxRXCR_RQOS_Msk       /* Rx AXI4 QOS */
15461 #define ETH_DMACxRXCR_RXPBL_Pos                       (16U)
15462 #define ETH_DMACxRXCR_RXPBL_Msk                       (0x3FUL << ETH_DMACxRXCR_RXPBL_Pos) /*!< 0x003F0000 */
15463 #define ETH_DMACxRXCR_RXPBL                           ETH_DMACxRXCR_RXPBL_Msk       /* Rx AXI4 QOS */
15464 #define ETH_DMACxRXCR_RXPBL_1PBL                      (0x1U << ETH_DMACxRXCR_RXPBL_Pos)     /*!< 0x00010000 */
15465 #define ETH_DMACxRXCR_RXPBL_2PBL                      (0x2U << ETH_DMACxRXCR_RXPBL_Pos)     /*!< 0x00020000 */
15466 #define ETH_DMACxRXCR_RXPBL_4PBL                      (0x4U << ETH_DMACxRXCR_RXPBL_Pos)     /*!< 0x00040000 */
15467 #define ETH_DMACxRXCR_RXPBL_8PBL                      (0x8U << ETH_DMACxRXCR_RXPBL_Pos)     /*!< 0x00080000 */
15468 #define ETH_DMACxRXCR_RXPBL_16PBL                     (0x10U << ETH_DMACxRXCR_RXPBL_Pos)    /*!< 0x00100000 */
15469 #define ETH_DMACxRXCR_RXPBL_32PBL                     (0x20U << ETH_DMACxRXCR_RXPBL_Pos)    /*!< 0x00200000 */
15470 #define ETH_DMACxRXCR_RBSZ_Pos                        (1U)
15471 #define ETH_DMACxRXCR_RBSZ_Msk                        (0x1FFFUL << ETH_DMACxRXCR_RBSZ_Pos) /*!< 0x00003FFE */
15472 #define ETH_DMACxRXCR_RBSZ                            ETH_DMACxRXCR_RBSZ_Msk       /* Receive Buffer size */
15473 #define ETH_DMACxRXCR_SR_Pos                          (0U)
15474 #define ETH_DMACxRXCR_SR_Msk                          (0x1UL << ETH_DMACxRXCR_SR_Pos) /*!< 0x00000001 */
15475 #define ETH_DMACxRXCR_SR                              ETH_DMACxRXCR_SR_Msk       /* Start or Stop Receive */
15476 
15477 /************ Bit definition for Ethernet DMA Channel x Tx descriptor list address Register   ***************/
15478 #define ETH_DMACxTXDLAR_TDESLA_Pos                    (0U)
15479 #define ETH_DMACxTXDLAR_TDESLA_Msk                    (0xFFFFFFFFUL << ETH_DMACxTXDLAR_TDESLA_Pos) /*!< 0xFFFFFFFF */
15480 #define ETH_DMACxTXDLAR_TDESLA                        ETH_DMACxTXDLAR_TDESLA_Msk   /* Start of Transmit List */
15481 
15482 /************ Bit definition for Ethernet DMA Channel x Rx descriptor list address Register   ***************/
15483 #define ETH_DMACxRXDLAR_RDESLA_Pos                    (0U)
15484 #define ETH_DMACxRXDLAR_RDESLA_Msk                    (0xFFFFFFFFUL << ETH_DMACxRXDLAR_RDESLA_Pos) /*!< 0xFFFFFFFF */
15485 #define ETH_DMACxRXDLAR_RDESLA                        ETH_DMACxRXDLAR_RDESLA_Msk   /* Start of Receive List */
15486 
15487 /************ Bit definition for Ethernet DMA Channel x Tx descriptor tail pointer Register   ***************/
15488 #define ETH_DMACxTXDTPR_TDT_Pos                       (0U)
15489 #define ETH_DMACxTXDTPR_TDT_Msk                       (0xFFFFFFFFUL << ETH_DMACxTXDTPR_TDT_Pos) /*!< 0xFFFFFFFF */
15490 #define ETH_DMACxTXDTPR_TDT                           ETH_DMACxTXDTPR_TDT_Msk   /* Transmit Descriptor Tail Pointer */
15491 
15492 /************ Bit definition for Ethernet DMA Channel x Rx descriptor tail pointer Register   ***************/
15493 #define ETH_DMACxRXDTPR_TDT_Pos                      (0U)
15494 #define ETH_DMACxRXDTPR_TDT_Msk                      (0xFFFFFFFFUL << ETH_DMACxRXDTPR_TDT_Pos) /*!< 0xFFFFFFFF */
15495 #define ETH_DMACxRXDTPR_TDT                          ETH_DMACxRXDTPR_TDT_Msk   /* Receive Descriptor Tail Pointer */
15496 
15497 /************ Bit definition for Ethernet DMA Channel x Tx descriptor ring length Register   ***************/
15498 #define ETH_DMACxTXRLR_TDRL_Pos                       (0U)
15499 #define ETH_DMACxTXRLR_TDRL_Msk                       (0x3FFUL << ETH_DMACxTXRLR_TDRL_Pos) /*!< 0x0000003FF */
15500 #define ETH_DMACxTXRLR_TDRL                           ETH_DMACxTXRLR_TDRL_Msk   /* Transmit Descriptor Ring Length */
15501 
15502 /************ Bit definition for Ethernet DMA Channel x Rx descriptor ring length Register   ***************/
15503 #define ETH_DMACxRXRLR_ARBS_Pos                       (17U)
15504 #define ETH_DMACxRXRLR_ARBS_Msk                       (0x7FUL << ETH_DMACxRXRLR_ARBS_Pos) /*!< 0x000FE0000 */
15505 #define ETH_DMACxRXRLR_ARBS                           ETH_DMACxRXRLR_ARBS_Msk   /* Alternate Receive Buffer Size */
15506 #define ETH_DMACxRXRLR_RDRL_Pos                       (0U)
15507 #define ETH_DMACxRXRLR_RDRL_Msk                       (0x3FFUL << ETH_DMACxRXRLR_RDRL_Pos) /*!< 0x0000003FF */
15508 #define ETH_DMACxRXRLR_RDRL                           ETH_DMACxRXRLR_RDRL_Msk   /* Receive Descriptor Ring Length */
15509 
15510 /************ Bit definition for Ethernet DMA Channel x Interrupt Enable Register   ***************/
15511 #define ETH_DMACxIER_NIE_Pos                           (15U)
15512 #define ETH_DMACxIER_NIE_Msk                           (0x1UL << ETH_DMACxIER_NIE_Pos) /*!< 0x00008000 */
15513 #define ETH_DMACxIER_NIE                               ETH_DMACxIER_NIE_Msk      /* Normal Interrupt Summary Enable */
15514 #define ETH_DMACxIER_AIE_Pos                           (14U)
15515 #define ETH_DMACxIER_AIE_Msk                           (0x1UL << ETH_DMACxIER_AIE_Pos) /*!< 0x00004000 */
15516 #define ETH_DMACxIER_AIE                               ETH_DMACxIER_AIE_Msk      /* Abnormal Interrupt Summary Enable */
15517 #define ETH_DMACxIER_CDEE_Pos                          (13U)
15518 #define ETH_DMACxIER_CDEE_Msk                          (0x1UL << ETH_DMACxIER_CDEE_Pos) /*!< 0x00002000 */
15519 #define ETH_DMACxIER_CDEE                              ETH_DMACxIER_CDEE_Msk     /* Context Descriptor Error Enable */
15520 #define ETH_DMACxIER_FBEE_Pos                          (12U)
15521 #define ETH_DMACxIER_FBEE_Msk                          (0x1UL << ETH_DMACxIER_FBEE_Pos) /*!< 0x00001000 */
15522 #define ETH_DMACxIER_FBEE                              ETH_DMACxIER_FBEE_Msk     /* Fatal Bus Error Enable */
15523 #define ETH_DMACxIER_ERIE_Pos                          (11U)
15524 #define ETH_DMACxIER_ERIE_Msk                          (0x1UL << ETH_DMACxIER_ERIE_Pos) /*!< 0x00000800 */
15525 #define ETH_DMACxIER_ERIE                              ETH_DMACxIER_ERIE_Msk     /* Early Receive Interrupt Enable */
15526 #define ETH_DMACxIER_ETIE_Pos                          (10U)
15527 #define ETH_DMACxIER_ETIE_Msk                          (0x1UL << ETH_DMACxIER_ETIE_Pos) /*!< 0x00000400 */
15528 #define ETH_DMACxIER_ETIE                              ETH_DMACxIER_ETIE_Msk     /* Early Transmit Interrupt Enable */
15529 #define ETH_DMACxIER_RWTE_Pos                          (9U)
15530 #define ETH_DMACxIER_RWTE_Msk                          (0x1UL << ETH_DMACxIER_RWTE_Pos) /*!< 0x00000200 */
15531 #define ETH_DMACxIER_RWTE                              ETH_DMACxIER_RWTE_Msk     /* Receive Watchdog Timeout Enable */
15532 #define ETH_DMACxIER_RSE_Pos                           (8U)
15533 #define ETH_DMACxIER_RSE_Msk                           (0x1UL << ETH_DMACxIER_RSE_Pos) /*!< 0x00000100 */
15534 #define ETH_DMACxIER_RSE                               ETH_DMACxIER_RSE_Msk      /* Receive Stopped Enable */
15535 #define ETH_DMACxIER_RBUE_Pos                          (7U)
15536 #define ETH_DMACxIER_RBUE_Msk                          (0x1UL << ETH_DMACxIER_RBUE_Pos) /*!< 0x00000080 */
15537 #define ETH_DMACxIER_RBUE                              ETH_DMACxIER_RBUE_Msk     /* Receive Buffer Unavailable Enable */
15538 #define ETH_DMACxIER_RIE_Pos                           (6U)
15539 #define ETH_DMACxIER_RIE_Msk                           (0x1UL << ETH_DMACxIER_RIE_Pos) /*!< 0x00000040 */
15540 #define ETH_DMACxIER_RIE                               ETH_DMACxIER_RIE_Msk      /* Receive Interrupt Enable */
15541 #define ETH_DMACxIER_TBUE_Pos                          (2U)
15542 #define ETH_DMACxIER_TBUE_Msk                          (0x1UL << ETH_DMACxIER_TBUE_Pos) /*!< 0x00000004 */
15543 #define ETH_DMACxIER_TBUE                              ETH_DMACxIER_TBUE_Msk     /* Transmit Buffer Unavailable Enable */
15544 #define ETH_DMACxIER_TXSE_Pos                          (1U)
15545 #define ETH_DMACxIER_TXSE_Msk                          (0x1UL << ETH_DMACxIER_TXSE_Pos) /*!< 0x00000002 */
15546 #define ETH_DMACxIER_TXSE                              ETH_DMACxIER_TXSE_Msk     /* Transmit Stopped Enable */
15547 #define ETH_DMACxIER_TIE_Pos                           (0U)
15548 #define ETH_DMACxIER_TIE_Msk                           (0x1UL << ETH_DMACxIER_TIE_Pos) /*!< 0x00000001 */
15549 #define ETH_DMACxIER_TIE                               ETH_DMACxIER_TIE_Msk      /* Transmit Interrupt Enable */
15550 
15551 /************ Bit definition for Ethernet DMA Channel x Rx Interrupt Watchdog Timer Register   ***************/
15552 #define ETH_DMACxRXIWTR_RWTU_Pos                        (16U)
15553 #define ETH_DMACxRXIWTR_RWTU_Msk                        (0x3UL << ETH_DMACxRXIWTR_RWTU_Pos) /*!< 0x00030000 */
15554 #define ETH_DMACxRXIWTR_RWTU                            ETH_DMACxRXIWTR_RWTU_Msk    /* Receive Interrupt Watchdog Timer Count Units */
15555 #define ETH_DMACxRXIWTR_RWTU_256                        ((uint32_t)0x00000000)   /* 256 */
15556 #define ETH_DMACxRXIWTR_RWTU_512_Pos                    (16U)
15557 #define ETH_DMACxRXIWTR_RWTU_512_Msk                    (0x1UL << ETH_DMACxRXIWTR_RWTU_512_Pos) /*!< 0x00010000 */
15558 #define ETH_DMACxRXIWTR_RWTU_512                        ETH_DMACxRXIWTR_RWTU_512_Msk    /* 512 */
15559 #define ETH_DMACxRXIWTR_RWTU_1024_Pos                   (17U)
15560 #define ETH_DMACxRXIWTR_RWTU_1024_Msk                   (0x1UL << ETH_DMACxRXIWTR_RWTU_1024_Pos) /*!< 0x00020000 */
15561 #define ETH_DMACxRXIWTR_RWTU_1024                       ETH_DMACxRXIWTR_RWTU_1024_Msk    /* 1024 */
15562 #define ETH_DMACxRXIWTR_RWTU_2048_Pos                   (16U)
15563 #define ETH_DMACxRXIWTR_RWTU_2048_Msk                   (0x3UL << ETH_DMACxRXIWTR_RWTU_2048_Pos) /*!< 0x00030000 */
15564 #define ETH_DMACxRXIWTR_RWTU_2048                       ETH_DMACxRXIWTR_RWTU_2048_Msk    /* 2048 */
15565 #define ETH_DMACxRXIWTR_RWT_Pos                         (0U)
15566 #define ETH_DMACxRXIWTR_RWT_Msk                         (0xFFUL << ETH_DMACxRXIWTR_RWT_Pos) /*!< 0x000000FF */
15567 #define ETH_DMACxRXIWTR_RWT                             ETH_DMACxRXIWTR_RWT_Msk    /* Receive Interrupt Watchdog Timer Count */
15568 
15569 /************ Bit definition for Ethernet DMA Channel x slot function control status Register   ***************/
15570 #define ETH_DMACxSFCSR_RSN_Pos                        (16U)
15571 #define ETH_DMACxSFCSR_RSN_Msk                        (0xFUL << ETH_DMACxSFCSR_RSN_Pos) /*!< 0x000F0000 */
15572 #define ETH_DMACxSFCSR_RSN                            ETH_DMACxSFCSR_RSN_Msk    /* Reference Slot Number */
15573 #define ETH_DMACxSFCSR_SIV_Pos                        (4U)
15574 #define ETH_DMACxSFCSR_SIV_Msk                        (0xFFFUL << ETH_DMACxSFCSR_SIV_Pos) /*!< 0x0000FFF0 */
15575 #define ETH_DMACxSFCSR_SIV                            ETH_DMACxSFCSR_SIV_Msk    /* Slot Interval Value */
15576 #define ETH_DMACxSFCSR_ASC_Pos                        (1U)
15577 #define ETH_DMACxSFCSR_ASC_Msk                        (0x1UL << ETH_DMACxSFCSR_ASC_Pos) /*!< 0x00000002 */
15578 #define ETH_DMACxSFCSR_ASC                            ETH_DMACxSFCSR_ASC_Msk    /* Advance Slot Check */
15579 #define ETH_DMACxSFCSR_ESC_Pos                        (0U)
15580 #define ETH_DMACxSFCSR_ESC_Msk                        (0x1UL << ETH_DMACxSFCSR_ESC_Pos) /*!< 0x00000001 */
15581 #define ETH_DMACxSFCSR_ESC                            ETH_DMACxSFCSR_ESC_Msk    /* Enable Slot Comparison */
15582 
15583 /************ Bit definition for Ethernet DMA Channel x Current App Tx Desc Register   ***************/
15584 #define ETH_DMACxCATXDR_CURTDESAPTR_Pos                 (0U)
15585 #define ETH_DMACxCATXDR_CURTDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACxCATXDR_CURTDESAPTR_Pos) /*!< 0xFFFFFFFF */
15586 #define ETH_DMACxCATXDR_CURTDESAPTR                     ETH_DMACxCATXDR_CURTDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */
15587 
15588 /************ Bit definition for Ethernet DMA Channel x Current App Rx Desc Register   ***************/
15589 #define ETH_DMACxCARXDR_CURRDESAPTR_Pos                 (0U)
15590 #define ETH_DMACxCARXDR_CURRDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACxCARXDR_CURRDESAPTR_Pos) /*!< 0xFFFFFFFF */
15591 #define ETH_DMACxCARXDR_CURRDESAPTR                     ETH_DMACxCARXDR_CURRDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */
15592 
15593 /************ Bit definition for Ethernet DMA Channel x Current App Tx Buffer Register   ***************/
15594 #define ETH_DMACxCATXBR_CURTBUFAPTR_Pos                 (0U)
15595 #define ETH_DMACxCATXBR_CURTBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACxCATXBR_CURTBUFAPTR_Pos) /*!< 0xFFFFFFFF */
15596 #define ETH_DMACxCATXBR_CURTBUFAPTR                     ETH_DMACxCATXBR_CURTBUFAPTR_Msk /* Application Transmit Buffer Address Pointer */
15597 
15598 /************ Bit definition for Ethernet DMA Channel x Current App Rx Buffer Register   ***************/
15599 #define ETH_DMACxCARXBR_CURRBUFAPTR_Pos                 (0U)
15600 #define ETH_DMACxCARXBR_CURRBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACxCARXBR_CURRBUFAPTR_Pos) /*!< 0xFFFFFFFF */
15601 #define ETH_DMACxCARXBR_CURRBUFAPTR                     ETH_DMACxCARXBR_CURRBUFAPTR_Msk /* Application Receive Buffer Address Pointer */
15602 
15603 /************ Bit definition for Ethernet DMA Channel x Status Register   ***************/
15604 #define ETH_DMACxSR_REB_Pos                            (19U)
15605 #define ETH_DMACxSR_REB_Msk                            (0x7UL << ETH_DMACxSR_REB_Pos) /*!< 0x00380000 */
15606 #define ETH_DMACxSR_REB                                ETH_DMACxSR_REB_Msk       /* Rx DMA Error Bits */
15607 #define ETH_DMACxSR_TEB_Pos                            (16U)
15608 #define ETH_DMACxSR_TEB_Msk                            (0x7UL << ETH_DMACxSR_TEB_Pos) /*!< 0x00070000 */
15609 #define ETH_DMACxSR_TEB                                ETH_DMACxSR_TEB_Msk       /* Tx DMA Error Bits */
15610 #define ETH_DMACxSR_NIS_Pos                            (15U)
15611 #define ETH_DMACxSR_NIS_Msk                            (0x1UL << ETH_DMACxSR_NIS_Pos) /*!< 0x00008000 */
15612 #define ETH_DMACxSR_NIS                                ETH_DMACxSR_NIS_Msk       /* Normal Interrupt Summary */
15613 #define ETH_DMACxSR_AIS_Pos                            (14U)
15614 #define ETH_DMACxSR_AIS_Msk                            (0x1UL << ETH_DMACxSR_AIS_Pos) /*!< 0x00004000 */
15615 #define ETH_DMACxSR_AIS                                ETH_DMACxSR_AIS_Msk       /* Abnormal Interrupt Summary */
15616 #define ETH_DMACxSR_CDE_Pos                            (13U)
15617 #define ETH_DMACxSR_CDE_Msk                            (0x1UL << ETH_DMACxSR_CDE_Pos) /*!< 0x00002000 */
15618 #define ETH_DMACxSR_CDE                                ETH_DMACxSR_CDE_Msk       /* Context Descriptor Error */
15619 #define ETH_DMACxSR_FBE_Pos                            (12U)
15620 #define ETH_DMACxSR_FBE_Msk                            (0x1UL << ETH_DMACxSR_FBE_Pos) /*!< 0x00001000 */
15621 #define ETH_DMACxSR_FBE                                ETH_DMACxSR_FBE_Msk       /* Fatal Bus Error */
15622 #define ETH_DMACxSR_ERI_Pos                            (11U)
15623 #define ETH_DMACxSR_ERI_Msk                            (0x1UL << ETH_DMACxSR_ERI_Pos) /*!< 0x00000800 */
15624 #define ETH_DMACxSR_ERI                                ETH_DMACxSR_ERI_Msk       /* Early Receive Interrupt */
15625 #define ETH_DMACxSR_ETI_Pos                            (10U)
15626 #define ETH_DMACxSR_ETI_Msk                            (0x1UL << ETH_DMACxSR_ETI_Pos) /*!< 0x00000400 */
15627 #define ETH_DMACxSR_ETI                                ETH_DMACxSR_ETI_Msk       /* Early Transmit Interrupt */
15628 #define ETH_DMACxSR_RWT_Pos                            (9U)
15629 #define ETH_DMACxSR_RWT_Msk                            (0x1UL << ETH_DMACxSR_RWT_Pos) /*!< 0x00000200 */
15630 #define ETH_DMACxSR_RWT                                ETH_DMACxSR_RWT_Msk       /* Receive Watchdog Timeout */
15631 #define ETH_DMACxSR_RPS_Pos                            (8U)
15632 #define ETH_DMACxSR_RPS_Msk                            (0x1UL << ETH_DMACxSR_RPS_Pos) /*!< 0x00000100 */
15633 #define ETH_DMACxSR_RPS                                ETH_DMACxSR_RPS_Msk       /* Receive Process Stopped */
15634 #define ETH_DMACxSR_RBU_Pos                            (7U)
15635 #define ETH_DMACxSR_RBU_Msk                            (0x1UL << ETH_DMACxSR_RBU_Pos) /*!< 0x00000080 */
15636 #define ETH_DMACxSR_RBU                                ETH_DMACxSR_RBU_Msk       /* Receive Buffer Unavailable */
15637 #define ETH_DMACxSR_RI_Pos                             (6U)
15638 #define ETH_DMACxSR_RI_Msk                             (0x1UL << ETH_DMACxSR_RI_Pos) /*!< 0x00000040 */
15639 #define ETH_DMACxSR_RI                                 ETH_DMACxSR_RI_Msk        /* Receive Interrupt */
15640 #define ETH_DMACxSR_TBU_Pos                            (2U)
15641 #define ETH_DMACxSR_TBU_Msk                            (0x1UL << ETH_DMACxSR_TBU_Pos) /*!< 0x00000004 */
15642 #define ETH_DMACxSR_TBU                                ETH_DMACxSR_TBU_Msk       /* Transmit Buffer Unavailable */
15643 #define ETH_DMACxSR_TPS_Pos                            (1U)
15644 #define ETH_DMACxSR_TPS_Msk                            (0x1UL << ETH_DMACxSR_TPS_Pos) /*!< 0x00000002 */
15645 #define ETH_DMACxSR_TPS                                ETH_DMACxSR_TPS_Msk       /* Transmit Process Stopped */
15646 #define ETH_DMACxSR_TI_Pos                             (0U)
15647 #define ETH_DMACxSR_TI_Msk                             (0x1UL << ETH_DMACxSR_TI_Pos) /*!< 0x00000001 */
15648 #define ETH_DMACxSR_TI                                 ETH_DMACxSR_TI_Msk        /* Transmit Interrupt */
15649 
15650 /************ Bit definition for Ethernet DMA Channel x missed frame count Register   ***************/
15651 #define ETH_DMACxMFCR_MFCO_Pos                         (15U)
15652 #define ETH_DMACxMFCR_MFCO_Msk                         (0x1UL << ETH_DMACxMFCR_MFCO_Pos) /*!< 0x00008000 */
15653 #define ETH_DMACxMFCR_MFCO                             ETH_DMACxMFCR_MFCO_Msk    /* Overflow status of the MFC Counter */
15654 #define ETH_DMACxMFCR_MFC_Pos                          (0U)
15655 #define ETH_DMACxMFCR_MFC_Msk                          (0x7FFUL << ETH_DMACxMFCR_MFC_Pos) /*!< 0x000007FF */
15656 #define ETH_DMACxMFCR_MFC                              ETH_DMACxMFCR_MFC_Msk     /* The number of packet counters dropped by the DMA */
15657 
15658 
15659 /******************************************************************************/
15660 /*                                                                            */
15661 /*                    External Interrupt/Event Controller                     */
15662 /*                                                                            */
15663 /******************************************************************************/
15664 /*******************  Bit definition for EXTI_RTSR1 register  *****************/
15665 #define EXTI_RTSR1_RT0_Pos           (0U)
15666 #define EXTI_RTSR1_RT0_Msk           (0x1UL << EXTI_RTSR1_RT0_Pos)             /*!< 0x00000001 */
15667 #define EXTI_RTSR1_RT0               EXTI_RTSR1_RT0_Msk                        /*!< Rising trigger configuration for input line 0 */
15668 #define EXTI_RTSR1_RT1_Pos           (1U)
15669 #define EXTI_RTSR1_RT1_Msk           (0x1UL << EXTI_RTSR1_RT1_Pos)             /*!< 0x00000002 */
15670 #define EXTI_RTSR1_RT1               EXTI_RTSR1_RT1_Msk                        /*!< Rising trigger configuration for input line 1 */
15671 #define EXTI_RTSR1_RT2_Pos           (2U)
15672 #define EXTI_RTSR1_RT2_Msk           (0x1UL << EXTI_RTSR1_RT2_Pos)             /*!< 0x00000004 */
15673 #define EXTI_RTSR1_RT2               EXTI_RTSR1_RT2_Msk                        /*!< Rising trigger configuration for input line 2 */
15674 #define EXTI_RTSR1_RT3_Pos           (3U)
15675 #define EXTI_RTSR1_RT3_Msk           (0x1UL << EXTI_RTSR1_RT3_Pos)             /*!< 0x00000008 */
15676 #define EXTI_RTSR1_RT3               EXTI_RTSR1_RT3_Msk                        /*!< Rising trigger configuration for input line 3 */
15677 #define EXTI_RTSR1_RT4_Pos           (4U)
15678 #define EXTI_RTSR1_RT4_Msk           (0x1UL << EXTI_RTSR1_RT4_Pos)             /*!< 0x00000010 */
15679 #define EXTI_RTSR1_RT4               EXTI_RTSR1_RT4_Msk                        /*!< Rising trigger configuration for input line 4 */
15680 #define EXTI_RTSR1_RT5_Pos           (5U)
15681 #define EXTI_RTSR1_RT5_Msk           (0x1UL << EXTI_RTSR1_RT5_Pos)             /*!< 0x00000020 */
15682 #define EXTI_RTSR1_RT5               EXTI_RTSR1_RT5_Msk                        /*!< Rising trigger configuration for input line 5 */
15683 #define EXTI_RTSR1_RT6_Pos           (6U)
15684 #define EXTI_RTSR1_RT6_Msk           (0x1UL << EXTI_RTSR1_RT6_Pos)             /*!< 0x00000040 */
15685 #define EXTI_RTSR1_RT6               EXTI_RTSR1_RT6_Msk                        /*!< Rising trigger configuration for input line 6 */
15686 #define EXTI_RTSR1_RT7_Pos           (7U)
15687 #define EXTI_RTSR1_RT7_Msk           (0x1UL << EXTI_RTSR1_RT7_Pos)             /*!< 0x00000080 */
15688 #define EXTI_RTSR1_RT7               EXTI_RTSR1_RT7_Msk                        /*!< Rising trigger configuration for input line 7 */
15689 #define EXTI_RTSR1_RT8_Pos           (8U)
15690 #define EXTI_RTSR1_RT8_Msk           (0x1UL << EXTI_RTSR1_RT8_Pos)             /*!< 0x00000100 */
15691 #define EXTI_RTSR1_RT8               EXTI_RTSR1_RT8_Msk                        /*!< Rising trigger configuration for input line 8 */
15692 #define EXTI_RTSR1_RT9_Pos           (9U)
15693 #define EXTI_RTSR1_RT9_Msk           (0x1UL << EXTI_RTSR1_RT9_Pos)             /*!< 0x00000200 */
15694 #define EXTI_RTSR1_RT9               EXTI_RTSR1_RT9_Msk                        /*!< Rising trigger configuration for input line 9 */
15695 #define EXTI_RTSR1_RT10_Pos          (10U)
15696 #define EXTI_RTSR1_RT10_Msk          (0x1UL << EXTI_RTSR1_RT10_Pos)            /*!< 0x00000400 */
15697 #define EXTI_RTSR1_RT10              EXTI_RTSR1_RT10_Msk                       /*!< Rising trigger configuration for input line 10 */
15698 #define EXTI_RTSR1_RT11_Pos          (11U)
15699 #define EXTI_RTSR1_RT11_Msk          (0x1UL << EXTI_RTSR1_RT11_Pos)            /*!< 0x00000800 */
15700 #define EXTI_RTSR1_RT11              EXTI_RTSR1_RT11_Msk                       /*!< Rising trigger configuration for input line 11 */
15701 #define EXTI_RTSR1_RT12_Pos          (12U)
15702 #define EXTI_RTSR1_RT12_Msk          (0x1UL << EXTI_RTSR1_RT12_Pos)            /*!< 0x00001000 */
15703 #define EXTI_RTSR1_RT12              EXTI_RTSR1_RT12_Msk                       /*!< Rising trigger configuration for input line 12 */
15704 #define EXTI_RTSR1_RT13_Pos          (13U)
15705 #define EXTI_RTSR1_RT13_Msk          (0x1UL << EXTI_RTSR1_RT13_Pos)            /*!< 0x00002000 */
15706 #define EXTI_RTSR1_RT13              EXTI_RTSR1_RT13_Msk                       /*!< Rising trigger configuration for input line 13 */
15707 #define EXTI_RTSR1_RT14_Pos          (14U)
15708 #define EXTI_RTSR1_RT14_Msk          (0x1UL << EXTI_RTSR1_RT14_Pos)            /*!< 0x00004000 */
15709 #define EXTI_RTSR1_RT14              EXTI_RTSR1_RT14_Msk                       /*!< Rising trigger configuration for input line 14 */
15710 #define EXTI_RTSR1_RT15_Pos          (15U)
15711 #define EXTI_RTSR1_RT15_Msk          (0x1UL << EXTI_RTSR1_RT15_Pos)            /*!< 0x00008000 */
15712 #define EXTI_RTSR1_RT15              EXTI_RTSR1_RT15_Msk                       /*!< Rising trigger configuration for input line 15 */
15713 #define EXTI_RTSR1_RT20_Pos          (20U)
15714 #define EXTI_RTSR1_RT20_Msk          (0x1UL << EXTI_RTSR1_RT20_Pos)            /*!< 0x00100000 */
15715 #define EXTI_RTSR1_RT20              EXTI_RTSR1_RT20_Msk                       /*!< Rising trigger configuration for input line 20 */
15716 #define EXTI_RTSR1_RT21_Pos          (21U)
15717 #define EXTI_RTSR1_RT21_Msk          (0x1UL << EXTI_RTSR1_RT21_Pos)            /*!< 0x00200000 */
15718 #define EXTI_RTSR1_RT21              EXTI_RTSR1_RT21_Msk                       /*!< Rising trigger configuration for input line 21 */
15719 
15720 /*******************  Bit definition for EXTI_FTSR1 register  *****************/
15721 #define EXTI_FTSR1_FT0_Pos           (0U)
15722 #define EXTI_FTSR1_FT0_Msk           (0x1UL << EXTI_FTSR1_FT0_Pos)             /*!< 0x00000001 */
15723 #define EXTI_FTSR1_FT0               EXTI_FTSR1_FT0_Msk                        /*!< Falling trigger configuration for input line 0 */
15724 #define EXTI_FTSR1_FT1_Pos           (1U)
15725 #define EXTI_FTSR1_FT1_Msk           (0x1UL << EXTI_FTSR1_FT1_Pos)             /*!< 0x00000002 */
15726 #define EXTI_FTSR1_FT1               EXTI_FTSR1_FT1_Msk                        /*!< Falling trigger configuration for input line 1 */
15727 #define EXTI_FTSR1_FT2_Pos           (2U)
15728 #define EXTI_FTSR1_FT2_Msk           (0x1UL << EXTI_FTSR1_FT2_Pos)             /*!< 0x00000004 */
15729 #define EXTI_FTSR1_FT2               EXTI_FTSR1_FT2_Msk                        /*!< Falling trigger configuration for input line 2 */
15730 #define EXTI_FTSR1_FT3_Pos           (3U)
15731 #define EXTI_FTSR1_FT3_Msk           (0x1UL << EXTI_FTSR1_FT3_Pos)             /*!< 0x00000008 */
15732 #define EXTI_FTSR1_FT3               EXTI_FTSR1_FT3_Msk                        /*!< Falling trigger configuration for input line 3 */
15733 #define EXTI_FTSR1_FT4_Pos           (4U)
15734 #define EXTI_FTSR1_FT4_Msk           (0x1UL << EXTI_FTSR1_FT4_Pos)             /*!< 0x00000010 */
15735 #define EXTI_FTSR1_FT4               EXTI_FTSR1_FT4_Msk                        /*!< Falling trigger configuration for input line 4 */
15736 #define EXTI_FTSR1_FT5_Pos           (5U)
15737 #define EXTI_FTSR1_FT5_Msk           (0x1UL << EXTI_FTSR1_FT5_Pos)             /*!< 0x00000020 */
15738 #define EXTI_FTSR1_FT5               EXTI_FTSR1_FT5_Msk                        /*!< Falling trigger configuration for input line 5 */
15739 #define EXTI_FTSR1_FT6_Pos           (6U)
15740 #define EXTI_FTSR1_FT6_Msk           (0x1UL << EXTI_FTSR1_FT6_Pos)             /*!< 0x00000040 */
15741 #define EXTI_FTSR1_FT6               EXTI_FTSR1_FT6_Msk                        /*!< Falling trigger configuration for input line 6 */
15742 #define EXTI_FTSR1_FT7_Pos           (7U)
15743 #define EXTI_FTSR1_FT7_Msk           (0x1UL << EXTI_FTSR1_FT7_Pos)             /*!< 0x00000080 */
15744 #define EXTI_FTSR1_FT7               EXTI_FTSR1_FT7_Msk                        /*!< Falling trigger configuration for input line 7 */
15745 #define EXTI_FTSR1_FT8_Pos           (8U)
15746 #define EXTI_FTSR1_FT8_Msk           (0x1UL << EXTI_FTSR1_FT8_Pos)             /*!< 0x00000100 */
15747 #define EXTI_FTSR1_FT8               EXTI_FTSR1_FT8_Msk                        /*!< Falling trigger configuration for input line 8 */
15748 #define EXTI_FTSR1_FT9_Pos           (9U)
15749 #define EXTI_FTSR1_FT9_Msk           (0x1UL << EXTI_FTSR1_FT9_Pos)             /*!< 0x00000200 */
15750 #define EXTI_FTSR1_FT9               EXTI_FTSR1_FT9_Msk                        /*!< Falling trigger configuration for input line 9 */
15751 #define EXTI_FTSR1_FT10_Pos          (10U)
15752 #define EXTI_FTSR1_FT10_Msk          (0x1UL << EXTI_FTSR1_FT10_Pos)            /*!< 0x00000400 */
15753 #define EXTI_FTSR1_FT10              EXTI_FTSR1_FT10_Msk                       /*!< Falling trigger configuration for input line 10 */
15754 #define EXTI_FTSR1_FT11_Pos          (11U)
15755 #define EXTI_FTSR1_FT11_Msk          (0x1UL << EXTI_FTSR1_FT11_Pos)            /*!< 0x00000800 */
15756 #define EXTI_FTSR1_FT11              EXTI_FTSR1_FT11_Msk                       /*!< Falling trigger configuration for input line 11 */
15757 #define EXTI_FTSR1_FT12_Pos          (12U)
15758 #define EXTI_FTSR1_FT12_Msk          (0x1UL << EXTI_FTSR1_FT12_Pos)            /*!< 0x00001000 */
15759 #define EXTI_FTSR1_FT12              EXTI_FTSR1_FT12_Msk                       /*!< Falling trigger configuration for input line 12 */
15760 #define EXTI_FTSR1_FT13_Pos          (13U)
15761 #define EXTI_FTSR1_FT13_Msk          (0x1UL << EXTI_FTSR1_FT13_Pos)            /*!< 0x00002000 */
15762 #define EXTI_FTSR1_FT13              EXTI_FTSR1_FT13_Msk                       /*!< Falling trigger configuration for input line 13 */
15763 #define EXTI_FTSR1_FT14_Pos          (14U)
15764 #define EXTI_FTSR1_FT14_Msk          (0x1UL << EXTI_FTSR1_FT14_Pos)            /*!< 0x00004000 */
15765 #define EXTI_FTSR1_FT14              EXTI_FTSR1_FT14_Msk                       /*!< Falling trigger configuration for input line 14 */
15766 #define EXTI_FTSR1_FT15_Pos          (15U)
15767 #define EXTI_FTSR1_FT15_Msk          (0x1UL << EXTI_FTSR1_FT15_Pos)            /*!< 0x00008000 */
15768 #define EXTI_FTSR1_FT15              EXTI_FTSR1_FT15_Msk                       /*!< Falling trigger configuration for input line 15 */
15769 #define EXTI_FTSR1_FT20_Pos          (20U)
15770 #define EXTI_FTSR1_FT20_Msk          (0x1UL << EXTI_FTSR1_FT20_Pos)            /*!< 0x00100000 */
15771 #define EXTI_FTSR1_FT20              EXTI_FTSR1_FT20_Msk                       /*!< Falling trigger configuration for input line 20 */
15772 #define EXTI_FTSR1_FT21_Pos          (21U)
15773 #define EXTI_FTSR1_FT21_Msk          (0x1UL << EXTI_FTSR1_FT21_Pos)            /*!< 0x00200000 */
15774 #define EXTI_FTSR1_FT21              EXTI_FTSR1_FT21_Msk                       /*!< Falling trigger configuration for input line 21 */
15775 
15776 /*******************  Bit definition for EXTI_SWIER1 register  ****************/
15777 #define EXTI_SWIER1_SWI0_Pos         (0U)
15778 #define EXTI_SWIER1_SWI0_Msk         (0x1UL << EXTI_SWIER1_SWI0_Pos)           /*!< 0x00000001 */
15779 #define EXTI_SWIER1_SWI0             EXTI_SWIER1_SWI0_Msk                      /*!< Software Interrupt on line 0 */
15780 #define EXTI_SWIER1_SWI1_Pos         (1U)
15781 #define EXTI_SWIER1_SWI1_Msk         (0x1UL << EXTI_SWIER1_SWI1_Pos)           /*!< 0x00000002 */
15782 #define EXTI_SWIER1_SWI1             EXTI_SWIER1_SWI1_Msk                      /*!< Software Interrupt on line 1 */
15783 #define EXTI_SWIER1_SWI2_Pos         (2U)
15784 #define EXTI_SWIER1_SWI2_Msk         (0x1UL << EXTI_SWIER1_SWI2_Pos)           /*!< 0x00000004 */
15785 #define EXTI_SWIER1_SWI2             EXTI_SWIER1_SWI2_Msk                      /*!< Software Interrupt on line 2 */
15786 #define EXTI_SWIER1_SWI3_Pos         (3U)
15787 #define EXTI_SWIER1_SWI3_Msk         (0x1UL << EXTI_SWIER1_SWI3_Pos)           /*!< 0x00000008 */
15788 #define EXTI_SWIER1_SWI3             EXTI_SWIER1_SWI3_Msk                      /*!< Software Interrupt on line 3 */
15789 #define EXTI_SWIER1_SWI4_Pos         (4U)
15790 #define EXTI_SWIER1_SWI4_Msk         (0x1UL << EXTI_SWIER1_SWI4_Pos)           /*!< 0x00000010 */
15791 #define EXTI_SWIER1_SWI4             EXTI_SWIER1_SWI4_Msk                      /*!< Software Interrupt on line 4 */
15792 #define EXTI_SWIER1_SWI5_Pos         (5U)
15793 #define EXTI_SWIER1_SWI5_Msk         (0x1UL << EXTI_SWIER1_SWI5_Pos)           /*!< 0x00000020 */
15794 #define EXTI_SWIER1_SWI5             EXTI_SWIER1_SWI5_Msk                      /*!< Software Interrupt on line 5 */
15795 #define EXTI_SWIER1_SWI6_Pos         (6U)
15796 #define EXTI_SWIER1_SWI6_Msk         (0x1UL << EXTI_SWIER1_SWI6_Pos)           /*!< 0x00000040 */
15797 #define EXTI_SWIER1_SWI6             EXTI_SWIER1_SWI6_Msk                      /*!< Software Interrupt on line 6 */
15798 #define EXTI_SWIER1_SWI7_Pos         (7U)
15799 #define EXTI_SWIER1_SWI7_Msk         (0x1UL << EXTI_SWIER1_SWI7_Pos)           /*!< 0x00000080 */
15800 #define EXTI_SWIER1_SWI7             EXTI_SWIER1_SWI7_Msk                      /*!< Software Interrupt on line 7 */
15801 #define EXTI_SWIER1_SWI8_Pos         (8U)
15802 #define EXTI_SWIER1_SWI8_Msk         (0x1UL << EXTI_SWIER1_SWI8_Pos)           /*!< 0x00000100 */
15803 #define EXTI_SWIER1_SWI8             EXTI_SWIER1_SWI8_Msk                      /*!< Software Interrupt on line 8 */
15804 #define EXTI_SWIER1_SWI9_Pos         (9U)
15805 #define EXTI_SWIER1_SWI9_Msk         (0x1UL << EXTI_SWIER1_SWI9_Pos)           /*!< 0x00000200 */
15806 #define EXTI_SWIER1_SWI9             EXTI_SWIER1_SWI9_Msk                      /*!< Software Interrupt on line 9 */
15807 #define EXTI_SWIER1_SWI10_Pos        (10U)
15808 #define EXTI_SWIER1_SWI10_Msk        (0x1UL << EXTI_SWIER1_SWI10_Pos)          /*!< 0x00000400 */
15809 #define EXTI_SWIER1_SWI10            EXTI_SWIER1_SWI10_Msk                     /*!< Software Interrupt on line 10 */
15810 #define EXTI_SWIER1_SWI11_Pos        (11U)
15811 #define EXTI_SWIER1_SWI11_Msk        (0x1UL << EXTI_SWIER1_SWI11_Pos)          /*!< 0x00000800 */
15812 #define EXTI_SWIER1_SWI11            EXTI_SWIER1_SWI11_Msk                     /*!< Software Interrupt on line 11 */
15813 #define EXTI_SWIER1_SWI12_Pos        (12U)
15814 #define EXTI_SWIER1_SWI12_Msk        (0x1UL << EXTI_SWIER1_SWI12_Pos)          /*!< 0x00001000 */
15815 #define EXTI_SWIER1_SWI12            EXTI_SWIER1_SWI12_Msk                     /*!< Software Interrupt on line 12 */
15816 #define EXTI_SWIER1_SWI13_Pos        (13U)
15817 #define EXTI_SWIER1_SWI13_Msk        (0x1UL << EXTI_SWIER1_SWI13_Pos)          /*!< 0x00002000 */
15818 #define EXTI_SWIER1_SWI13            EXTI_SWIER1_SWI13_Msk                     /*!< Software Interrupt on line 13 */
15819 #define EXTI_SWIER1_SWI14_Pos        (14U)
15820 #define EXTI_SWIER1_SWI14_Msk        (0x1UL << EXTI_SWIER1_SWI14_Pos)          /*!< 0x00004000 */
15821 #define EXTI_SWIER1_SWI14            EXTI_SWIER1_SWI14_Msk                     /*!< Software Interrupt on line 14 */
15822 #define EXTI_SWIER1_SWI15_Pos        (15U)
15823 #define EXTI_SWIER1_SWI15_Msk        (0x1UL << EXTI_SWIER1_SWI15_Pos)          /*!< 0x00008000 */
15824 #define EXTI_SWIER1_SWI15            EXTI_SWIER1_SWI15_Msk                     /*!< Software Interrupt on line 15 */
15825 #define EXTI_SWIER1_SWI20_Pos        (20U)
15826 #define EXTI_SWIER1_SWI20_Msk        (0x1UL << EXTI_SWIER1_SWI20_Pos)          /*!< 0x00100000 */
15827 #define EXTI_SWIER1_SWI20            EXTI_SWIER1_SWI20_Msk                     /*!< Software Interrupt on line 20 */
15828 #define EXTI_SWIER1_SWI21_Pos        (21U)
15829 #define EXTI_SWIER1_SWI21_Msk        (0x1UL << EXTI_SWIER1_SWI21_Pos)          /*!< 0x00200000 */
15830 #define EXTI_SWIER1_SWI21            EXTI_SWIER1_SWI21_Msk                     /*!< Software Interrupt on line 21 */
15831 
15832 /*******************  Bit definition for EXTI_RPR1 register  ******************/
15833 #define EXTI_RPR1_RPIF0_Pos          (0U)
15834 #define EXTI_RPR1_RPIF0_Msk          (0x1UL << EXTI_RPR1_RPIF0_Pos)            /*!< 0x00000001 */
15835 #define EXTI_RPR1_RPIF0              EXTI_RPR1_RPIF0_Msk                       /*!< Rising Pending Interrupt Flag on line 0 */
15836 #define EXTI_RPR1_RPIF1_Pos          (1U)
15837 #define EXTI_RPR1_RPIF1_Msk          (0x1UL << EXTI_RPR1_RPIF1_Pos)            /*!< 0x00000002 */
15838 #define EXTI_RPR1_RPIF1              EXTI_RPR1_RPIF1_Msk                       /*!< Rising Pending Interrupt Flag on line 1 */
15839 #define EXTI_RPR1_RPIF2_Pos          (2U)
15840 #define EXTI_RPR1_RPIF2_Msk          (0x1UL << EXTI_RPR1_RPIF2_Pos)            /*!< 0x00000004 */
15841 #define EXTI_RPR1_RPIF2              EXTI_RPR1_RPIF2_Msk                       /*!< Rising Pending Interrupt Flag on line 2 */
15842 #define EXTI_RPR1_RPIF3_Pos          (3U)
15843 #define EXTI_RPR1_RPIF3_Msk          (0x1UL << EXTI_RPR1_RPIF3_Pos)            /*!< 0x00000008 */
15844 #define EXTI_RPR1_RPIF3              EXTI_RPR1_RPIF3_Msk                       /*!< Rising Pending Interrupt Flag on line 3 */
15845 #define EXTI_RPR1_RPIF4_Pos          (4U)
15846 #define EXTI_RPR1_RPIF4_Msk          (0x1UL << EXTI_RPR1_RPIF4_Pos)            /*!< 0x00000010 */
15847 #define EXTI_RPR1_RPIF4              EXTI_RPR1_RPIF4_Msk                       /*!< Rising Pending Interrupt Flag on line 4 */
15848 #define EXTI_RPR1_RPIF5_Pos          (5U)
15849 #define EXTI_RPR1_RPIF5_Msk          (0x1UL << EXTI_RPR1_RPIF5_Pos)            /*!< 0x00000020 */
15850 #define EXTI_RPR1_RPIF5              EXTI_RPR1_RPIF5_Msk                       /*!< Rising Pending Interrupt Flag on line 5 */
15851 #define EXTI_RPR1_RPIF6_Pos          (6U)
15852 #define EXTI_RPR1_RPIF6_Msk          (0x1UL << EXTI_RPR1_RPIF6_Pos)            /*!< 0x00000040 */
15853 #define EXTI_RPR1_RPIF6              EXTI_RPR1_RPIF6_Msk                       /*!< Rising Pending Interrupt Flag on line 6 */
15854 #define EXTI_RPR1_RPIF7_Pos          (7U)
15855 #define EXTI_RPR1_RPIF7_Msk          (0x1UL << EXTI_RPR1_RPIF7_Pos)            /*!< 0x00000080 */
15856 #define EXTI_RPR1_RPIF7              EXTI_RPR1_RPIF7_Msk                       /*!< Rising Pending Interrupt Flag on line 7 */
15857 #define EXTI_RPR1_RPIF8_Pos          (8U)
15858 #define EXTI_RPR1_RPIF8_Msk          (0x1UL << EXTI_RPR1_RPIF8_Pos)            /*!< 0x00000100 */
15859 #define EXTI_RPR1_RPIF8              EXTI_RPR1_RPIF8_Msk                       /*!< Rising Pending Interrupt Flag on line 8 */
15860 #define EXTI_RPR1_RPIF9_Pos          (9U)
15861 #define EXTI_RPR1_RPIF9_Msk          (0x1UL << EXTI_RPR1_RPIF9_Pos)            /*!< 0x00000200 */
15862 #define EXTI_RPR1_RPIF9              EXTI_RPR1_RPIF9_Msk                       /*!< Rising Pending Interrupt Flag on line 9 */
15863 #define EXTI_RPR1_RPIF10_Pos         (10U)
15864 #define EXTI_RPR1_RPIF10_Msk         (0x1UL << EXTI_RPR1_RPIF10_Pos)           /*!< 0x00000400 */
15865 #define EXTI_RPR1_RPIF10             EXTI_RPR1_RPIF10_Msk                      /*!< Rising Pending Interrupt Flag on line 10 */
15866 #define EXTI_RPR1_RPIF11_Pos         (11U)
15867 #define EXTI_RPR1_RPIF11_Msk         (0x1UL << EXTI_RPR1_RPIF11_Pos)           /*!< 0x00000800 */
15868 #define EXTI_RPR1_RPIF11             EXTI_RPR1_RPIF11_Msk                      /*!< Rising Pending Interrupt Flag on line 11 */
15869 #define EXTI_RPR1_RPIF12_Pos         (12U)
15870 #define EXTI_RPR1_RPIF12_Msk         (0x1UL << EXTI_RPR1_RPIF12_Pos)           /*!< 0x00001000 */
15871 #define EXTI_RPR1_RPIF12             EXTI_RPR1_RPIF12_Msk                      /*!< Rising Pending Interrupt Flag on line 12 */
15872 #define EXTI_RPR1_RPIF13_Pos         (13U)
15873 #define EXTI_RPR1_RPIF13_Msk         (0x1UL << EXTI_RPR1_RPIF13_Pos)           /*!< 0x00002000 */
15874 #define EXTI_RPR1_RPIF13             EXTI_RPR1_RPIF13_Msk                      /*!< Rising Pending Interrupt Flag on line 13 */
15875 #define EXTI_RPR1_RPIF14_Pos         (14U)
15876 #define EXTI_RPR1_RPIF14_Msk         (0x1UL << EXTI_RPR1_RPIF14_Pos)           /*!< 0x00004000 */
15877 #define EXTI_RPR1_RPIF14             EXTI_RPR1_RPIF14_Msk                      /*!< Rising Pending Interrupt Flag on line 14 */
15878 #define EXTI_RPR1_RPIF15_Pos         (15U)
15879 #define EXTI_RPR1_RPIF15_Msk         (0x1UL << EXTI_RPR1_RPIF15_Pos)           /*!< 0x00008000 */
15880 #define EXTI_RPR1_RPIF15             EXTI_RPR1_RPIF15_Msk                      /*!< Rising Pending Interrupt Flag on line 15 */
15881 #define EXTI_RPR1_RPIF20_Pos         (20U)
15882 #define EXTI_RPR1_RPIF20_Msk         (0x1UL << EXTI_RPR1_RPIF20_Pos)           /*!< 0x00020000 */
15883 #define EXTI_RPR1_RPIF20             EXTI_RPR1_RPIF20_Msk                      /*!< Rising Pending Interrupt Flag on line 20 */
15884 #define EXTI_RPR1_RPIF21_Pos         (21U)
15885 #define EXTI_RPR1_RPIF21_Msk         (0x1UL << EXTI_RPR1_RPIF21_Pos)           /*!< 0x00040000 */
15886 #define EXTI_RPR1_RPIF21             EXTI_RPR1_RPIF21_Msk                      /*!< Rising Pending Interrupt Flag on line 21 */
15887 
15888 /*******************  Bit definition for EXTI_FPR1 register  ******************/
15889 #define EXTI_FPR1_FPIF0_Pos          (0U)
15890 #define EXTI_FPR1_FPIF0_Msk          (0x1UL << EXTI_FPR1_FPIF0_Pos)            /*!< 0x00000001 */
15891 #define EXTI_FPR1_FPIF0              EXTI_FPR1_FPIF0_Msk                       /*!< Falling Pending Interrupt Flag on line 0 */
15892 #define EXTI_FPR1_FPIF1_Pos          (1U)
15893 #define EXTI_FPR1_FPIF1_Msk          (0x1UL << EXTI_FPR1_FPIF1_Pos)            /*!< 0x00000002 */
15894 #define EXTI_FPR1_FPIF1              EXTI_FPR1_FPIF1_Msk                       /*!< Falling Pending Interrupt Flag on line 1 */
15895 #define EXTI_FPR1_FPIF2_Pos          (2U)
15896 #define EXTI_FPR1_FPIF2_Msk          (0x1UL << EXTI_FPR1_FPIF2_Pos)            /*!< 0x00000004 */
15897 #define EXTI_FPR1_FPIF2              EXTI_FPR1_FPIF2_Msk                       /*!< Falling Pending Interrupt Flag on line 2 */
15898 #define EXTI_FPR1_FPIF3_Pos          (3U)
15899 #define EXTI_FPR1_FPIF3_Msk          (0x1UL << EXTI_FPR1_FPIF3_Pos)            /*!< 0x00000008 */
15900 #define EXTI_FPR1_FPIF3              EXTI_FPR1_FPIF3_Msk                       /*!< Falling Pending Interrupt Flag on line 3 */
15901 #define EXTI_FPR1_FPIF4_Pos          (4U)
15902 #define EXTI_FPR1_FPIF4_Msk          (0x1UL << EXTI_FPR1_FPIF4_Pos)            /*!< 0x00000010 */
15903 #define EXTI_FPR1_FPIF4              EXTI_FPR1_FPIF4_Msk                       /*!< Falling Pending Interrupt Flag on line 4 */
15904 #define EXTI_FPR1_FPIF5_Pos          (5U)
15905 #define EXTI_FPR1_FPIF5_Msk          (0x1UL << EXTI_FPR1_FPIF5_Pos)            /*!< 0x00000020 */
15906 #define EXTI_FPR1_FPIF5              EXTI_FPR1_FPIF5_Msk                       /*!< Falling Pending Interrupt Flag on line 5 */
15907 #define EXTI_FPR1_FPIF6_Pos          (6U)
15908 #define EXTI_FPR1_FPIF6_Msk          (0x1UL << EXTI_FPR1_FPIF6_Pos)            /*!< 0x00000040 */
15909 #define EXTI_FPR1_FPIF6              EXTI_FPR1_FPIF6_Msk                       /*!< Falling Pending Interrupt Flag on line 6 */
15910 #define EXTI_FPR1_FPIF7_Pos          (7U)
15911 #define EXTI_FPR1_FPIF7_Msk           (0x1UL << EXTI_FPR1_FPIF7_Pos)            /*!< 0x00000080 */
15912 #define EXTI_FPR1_FPIF7              EXTI_FPR1_FPIF7_Msk                       /*!< Falling Pending Interrupt Flag on line 7 */
15913 #define EXTI_FPR1_FPIF8_Pos          (8U)
15914 #define EXTI_FPR1_FPIF8_Msk          (0x1UL << EXTI_FPR1_FPIF8_Pos)            /*!< 0x00000100 */
15915 #define EXTI_FPR1_FPIF8              EXTI_FPR1_FPIF8_Msk                       /*!< Falling Pending Interrupt Flag on line 8 */
15916 #define EXTI_FPR1_FPIF9_Pos          (9U)
15917 #define EXTI_FPR1_FPIF9_Msk          (0x1UL << EXTI_FPR1_FPIF9_Pos)            /*!< 0x00000200 */
15918 #define EXTI_FPR1_FPIF9              EXTI_FPR1_FPIF9_Msk                       /*!< Falling Pending Interrupt Flag on line 9 */
15919 #define EXTI_FPR1_FPIF10_Pos         (10U)
15920 #define EXTI_FPR1_FPIF10_Msk         (0x1UL << EXTI_FPR1_FPIF10_Pos)           /*!< 0x00000400 */
15921 #define EXTI_FPR1_FPIF10             EXTI_FPR1_FPIF10_Msk                      /*!< Falling Pending Interrupt Flag on line 10 */
15922 #define EXTI_FPR1_FPIF11_Pos         (11U)
15923 #define EXTI_FPR1_FPIF11_Msk         (0x1UL << EXTI_FPR1_FPIF11_Pos)           /*!< 0x00000800 */
15924 #define EXTI_FPR1_FPIF11             EXTI_FPR1_FPIF11_Msk                      /*!< Falling Pending Interrupt Flag on line 11 */
15925 #define EXTI_FPR1_FPIF12_Pos         (12U)
15926 #define EXTI_FPR1_FPIF12_Msk         (0x1UL << EXTI_FPR1_FPIF12_Pos)           /*!< 0x00001000 */
15927 #define EXTI_FPR1_FPIF12             EXTI_FPR1_FPIF12_Msk                      /*!< Falling Pending Interrupt Flag on line 12 */
15928 #define EXTI_FPR1_FPIF13_Pos         (13U)
15929 #define EXTI_FPR1_FPIF13_Msk         (0x1UL << EXTI_FPR1_FPIF13_Pos)           /*!< 0x00002000 */
15930 #define EXTI_FPR1_FPIF13             EXTI_FPR1_FPIF13_Msk                      /*!< Falling Pending Interrupt Flag on line 13 */
15931 #define EXTI_FPR1_FPIF14_Pos         (14U)
15932 #define EXTI_FPR1_FPIF14_Msk         (0x1UL << EXTI_FPR1_FPIF14_Pos)           /*!< 0x00004000 */
15933 #define EXTI_FPR1_FPIF14             EXTI_FPR1_FPIF14_Msk                      /*!< Falling Pending Interrupt Flag on line 14 */
15934 #define EXTI_FPR1_FPIF15_Pos         (15U)
15935 #define EXTI_FPR1_FPIF15_Msk         (0x1UL << EXTI_FPR1_FPIF15_Pos)           /*!< 0x00008000 */
15936 #define EXTI_FPR1_FPIF15             EXTI_FPR1_FPIF15_Msk                      /*!< Falling Pending Interrupt Flag on line 15 */
15937 #define EXTI_FPR1_FPIF20_Pos         (20U)
15938 #define EXTI_FPR1_FPIF20_Msk         (0x1UL << EXTI_FPR1_FPIF20_Pos)           /*!< 0x00020000 */
15939 #define EXTI_FPR1_FPIF20             EXTI_FPR1_FPIF20_Msk                      /*!< Falling Pending Interrupt Flag on line 20 */
15940 #define EXTI_FPR1_FPIF21_Pos         (21U)
15941 #define EXTI_FPR1_FPIF21_Msk         (0x1UL << EXTI_FPR1_FPIF21_Pos)           /*!< 0x00040000 */
15942 #define EXTI_FPR1_FPIF21             EXTI_FPR1_FPIF21_Msk                      /*!< Falling Pending Interrupt Flag on line 21 */
15943 
15944 /*******************  Bit definition for EXTI_SECCFGR1 register  ******************/
15945 #define EXTI_SECCFGR1_SEC0_Pos       (0U)
15946 #define EXTI_SECCFGR1_SEC0_Msk       (0x1UL << EXTI_SECCFGR1_SEC0_Pos)         /*!< 0x00000001 */
15947 #define EXTI_SECCFGR1_SEC0           EXTI_SECCFGR1_SEC0_Msk                    /*!< Security enable on line 0 */
15948 #define EXTI_SECCFGR1_SEC1_Pos       (1U)
15949 #define EXTI_SECCFGR1_SEC1_Msk       (0x1UL << EXTI_SECCFGR1_SEC1_Pos)         /*!< 0x00000002 */
15950 #define EXTI_SECCFGR1_SEC1           EXTI_SECCFGR1_SEC1_Msk                    /*!< Security enable on line 1 */
15951 #define EXTI_SECCFGR1_SEC2_Pos       (2U)
15952 #define EXTI_SECCFGR1_SEC2_Msk       (0x1UL << EXTI_SECCFGR1_SEC2_Pos)         /*!< 0x00000004 */
15953 #define EXTI_SECCFGR1_SEC2           EXTI_SECCFGR1_SEC2_Msk                    /*!< Security enable on line 2 */
15954 #define EXTI_SECCFGR1_SEC3_Pos       (3U)
15955 #define EXTI_SECCFGR1_SEC3_Msk       (0x1UL << EXTI_SECCFGR1_SEC3_Pos)         /*!< 0x00000008 */
15956 #define EXTI_SECCFGR1_SEC3           EXTI_SECCFGR1_SEC3_Msk                    /*!< Security enable on line 3 */
15957 #define EXTI_SECCFGR1_SEC4_Pos       (4U)
15958 #define EXTI_SECCFGR1_SEC4_Msk       (0x1UL << EXTI_SECCFGR1_SEC4_Pos)         /*!< 0x00000010 */
15959 #define EXTI_SECCFGR1_SEC4           EXTI_SECCFGR1_SEC4_Msk                    /*!< Security enable on line 4 */
15960 #define EXTI_SECCFGR1_SEC5_Pos       (5U)
15961 #define EXTI_SECCFGR1_SEC5_Msk       (0x1UL << EXTI_SECCFGR1_SEC5_Pos)         /*!< 0x00000020 */
15962 #define EXTI_SECCFGR1_SEC5           EXTI_SECCFGR1_SEC5_Msk                    /*!< Security enable on line 5 */
15963 #define EXTI_SECCFGR1_SEC6_Pos       (6U)
15964 #define EXTI_SECCFGR1_SEC6_Msk       (0x1UL << EXTI_SECCFGR1_SEC6_Pos)         /*!< 0x00000040 */
15965 #define EXTI_SECCFGR1_SEC6           EXTI_SECCFGR1_SEC6_Msk                    /*!< Security enable on line 6 */
15966 #define EXTI_SECCFGR1_SEC7_Pos       (7U)
15967 #define EXTI_SECCFGR1_SEC7_Msk       (0x1UL << EXTI_SECCFGR1_SEC7_Pos)         /*!< 0x00000080 */
15968 #define EXTI_SECCFGR1_SEC7           EXTI_SECCFGR1_SEC7_Msk                    /*!< Security enable on line 7 */
15969 #define EXTI_SECCFGR1_SEC8_Pos       (8U)
15970 #define EXTI_SECCFGR1_SEC8_Msk       (0x1UL << EXTI_SECCFGR1_SEC8_Pos)         /*!< 0x00000100 */
15971 #define EXTI_SECCFGR1_SEC8           EXTI_SECCFGR1_SEC8_Msk                    /*!< Security enable on line 8 */
15972 #define EXTI_SECCFGR1_SEC9_Pos       (9U)
15973 #define EXTI_SECCFGR1_SEC9_Msk       (0x1UL << EXTI_SECCFGR1_SEC9_Pos)         /*!< 0x00000200 */
15974 #define EXTI_SECCFGR1_SEC9           EXTI_SECCFGR1_SEC9_Msk                    /*!< Security enable on line 9 */
15975 #define EXTI_SECCFGR1_SEC10_Pos      (10U)
15976 #define EXTI_SECCFGR1_SEC10_Msk      (0x1UL << EXTI_SECCFGR1_SEC10_Pos)        /*!< 0x00000400 */
15977 #define EXTI_SECCFGR1_SEC10          EXTI_SECCFGR1_SEC10_Msk                   /*!< Security enable on line 10 */
15978 #define EXTI_SECCFGR1_SEC11_Pos      (11U)
15979 #define EXTI_SECCFGR1_SEC11_Msk      (0x1UL << EXTI_SECCFGR1_SEC11_Pos)        /*!< 0x00000800 */
15980 #define EXTI_SECCFGR1_SEC11          EXTI_SECCFGR1_SEC11_Msk                   /*!< Security enable on line 11 */
15981 #define EXTI_SECCFGR1_SEC12_Pos      (12U)
15982 #define EXTI_SECCFGR1_SEC12_Msk      (0x1UL << EXTI_SECCFGR1_SEC12_Pos)        /*!< 0x00001000 */
15983 #define EXTI_SECCFGR1_SEC12          EXTI_SECCFGR1_SEC12_Msk                   /*!< Security enable on line 12 */
15984 #define EXTI_SECCFGR1_SEC13_Pos      (13U)
15985 #define EXTI_SECCFGR1_SEC13_Msk      (0x1UL << EXTI_SECCFGR1_SEC13_Pos)        /*!< 0x00002000 */
15986 #define EXTI_SECCFGR1_SEC13          EXTI_SECCFGR1_SEC13_Msk                   /*!< Security enable on line 13 */
15987 #define EXTI_SECCFGR1_SEC14_Pos      (14U)
15988 #define EXTI_SECCFGR1_SEC14_Msk      (0x1UL << EXTI_SECCFGR1_SEC14_Pos)        /*!< 0x00004000 */
15989 #define EXTI_SECCFGR1_SEC14          EXTI_SECCFGR1_SEC14_Msk                   /*!< Security enable on line 14 */
15990 #define EXTI_SECCFGR1_SEC15_Pos      (15U)
15991 #define EXTI_SECCFGR1_SEC15_Msk      (0x1UL << EXTI_SECCFGR1_SEC15_Pos)        /*!< 0x00008000 */
15992 #define EXTI_SECCFGR1_SEC15          EXTI_SECCFGR1_SEC15_Msk                   /*!< Security enable on line 15 */
15993 #define EXTI_SECCFGR1_SEC17_Pos      (17U)
15994 #define EXTI_SECCFGR1_SEC17_Msk      (0x1UL << EXTI_SECCFGR1_SEC17_Pos)        /*!< 0x00020000 */
15995 #define EXTI_SECCFGR1_SEC17          EXTI_SECCFGR1_SEC17_Msk                   /*!< Security enable on line 17 */
15996 #define EXTI_SECCFGR1_SEC18_Pos      (18U)
15997 #define EXTI_SECCFGR1_SEC18_Msk      (0x1UL << EXTI_SECCFGR1_SEC18_Pos)        /*!< 0x00040000 */
15998 #define EXTI_SECCFGR1_SEC18          EXTI_SECCFGR1_SEC18_Msk                   /*!< Security enable on line 18 */
15999 #define EXTI_SECCFGR1_SEC19_Pos      (19U)
16000 #define EXTI_SECCFGR1_SEC19_Msk      (0x1UL << EXTI_SECCFGR1_SEC19_Pos)        /*!< 0x00080000 */
16001 #define EXTI_SECCFGR1_SEC19          EXTI_SECCFGR1_SEC19_Msk                   /*!< Security enable on line 19 */
16002 #define EXTI_SECCFGR1_SEC20_Pos      (20U)
16003 #define EXTI_SECCFGR1_SEC20_Msk      (0x1UL << EXTI_SECCFGR1_SEC20_Pos)        /*!< 0x00100000 */
16004 #define EXTI_SECCFGR1_SEC20          EXTI_SECCFGR1_SEC20_Msk                   /*!< Security enable on line 20 */
16005 #define EXTI_SECCFGR1_SEC21_Pos      (21U)
16006 #define EXTI_SECCFGR1_SEC21_Msk      (0x1UL << EXTI_SECCFGR1_SEC21_Pos)        /*!< 0x00200000 */
16007 #define EXTI_SECCFGR1_SEC21          EXTI_SECCFGR1_SEC21_Msk                   /*!< Security enable on line 21 */
16008 #define EXTI_SECCFGR1_SEC22_Pos      (22U)
16009 #define EXTI_SECCFGR1_SEC22_Msk      (0x1UL << EXTI_SECCFGR1_SEC22_Pos)        /*!< 0x00400000 */
16010 #define EXTI_SECCFGR1_SEC22          EXTI_SECCFGR1_SEC22_Msk                   /*!< Security enable on line 22 */
16011 #define EXTI_SECCFGR1_SEC23_Pos      (23U)
16012 #define EXTI_SECCFGR1_SEC23_Msk      (0x1UL << EXTI_SECCFGR1_SEC23_Pos)        /*!< 0x00800000 */
16013 #define EXTI_SECCFGR1_SEC23          EXTI_SECCFGR1_SEC23_Msk                   /*!< Security enable on line 23 */
16014 #define EXTI_SECCFGR1_SEC24_Pos      (24U)
16015 #define EXTI_SECCFGR1_SEC24_Msk      (0x1UL << EXTI_SECCFGR1_SEC24_Pos)        /*!< 0x01000000 */
16016 #define EXTI_SECCFGR1_SEC24          EXTI_SECCFGR1_SEC24_Msk                   /*!< Security enable on line 24 */
16017 #define EXTI_SECCFGR1_SEC25_Pos      (25U)
16018 #define EXTI_SECCFGR1_SEC25_Msk      (0x1UL << EXTI_SECCFGR1_SEC25_Pos)        /*!< 0x02000000 */
16019 #define EXTI_SECCFGR1_SEC25          EXTI_SECCFGR1_SEC25_Msk                   /*!< Security enable on line 25 */
16020 #define EXTI_SECCFGR1_SEC26_Pos      (26U)
16021 #define EXTI_SECCFGR1_SEC26_Msk      (0x1UL << EXTI_SECCFGR1_SEC26_Pos)        /*!< 0x04000000 */
16022 #define EXTI_SECCFGR1_SEC26          EXTI_SECCFGR1_SEC26_Msk                   /*!< Security enable on line 26 */
16023 #define EXTI_SECCFGR1_SEC27_Pos      (27U)
16024 #define EXTI_SECCFGR1_SEC27_Msk      (0x1UL << EXTI_SECCFGR1_SEC27_Pos)        /*!< 0x08000000 */
16025 #define EXTI_SECCFGR1_SEC27          EXTI_SECCFGR1_SEC27_Msk                   /*!< Security enable on line 27 */
16026 #define EXTI_SECCFGR1_SEC28_Pos      (28U)
16027 #define EXTI_SECCFGR1_SEC28_Msk      (0x1UL << EXTI_SECCFGR1_SEC28_Pos)        /*!< 0x10000000 */
16028 #define EXTI_SECCFGR1_SEC28          EXTI_SECCFGR1_SEC28_Msk                   /*!< Security enable on line 28 */
16029 #define EXTI_SECCFGR1_SEC29_Pos      (29U)
16030 #define EXTI_SECCFGR1_SEC29_Msk      (0x1UL << EXTI_SECCFGR1_SEC29_Pos)        /*!< 0x20000000 */
16031 #define EXTI_SECCFGR1_SEC29          EXTI_SECCFGR1_SEC29_Msk                   /*!< Security enable on line 29 */
16032 #define EXTI_SECCFGR1_SEC30_Pos      (30U)
16033 #define EXTI_SECCFGR1_SEC30_Msk      (0x1UL << EXTI_SECCFGR1_SEC30_Pos)        /*!< 0x40000000 */
16034 #define EXTI_SECCFGR1_SEC30          EXTI_SECCFGR1_SEC30_Msk                   /*!< Security enable on line 30 */
16035 #define EXTI_SECCFGR1_SEC31_Pos      (31U)
16036 #define EXTI_SECCFGR1_SEC31_Msk      (0x1UL << EXTI_SECCFGR1_SEC31_Pos)        /*!< 0x80000000 */
16037 #define EXTI_SECCFGR1_SEC31          EXTI_SECCFGR1_SEC31_Msk                   /*!< Security enable on line 31 */
16038 
16039 /*******************  Bit definition for EXTI_PRIVCFGR1 register  ******************/
16040 #define EXTI_PRIVCFGR1_PRIV0_Pos     (0U)
16041 #define EXTI_PRIVCFGR1_PRIV0_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV0_Pos)       /*!< 0x00000001 */
16042 #define EXTI_PRIVCFGR1_PRIV0         EXTI_PRIVCFGR1_PRIV0_Msk                  /*!< Privilege enable on line 0 */
16043 #define EXTI_PRIVCFGR1_PRIV1_Pos     (1U)
16044 #define EXTI_PRIVCFGR1_PRIV1_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV1_Pos)       /*!< 0x00000002 */
16045 #define EXTI_PRIVCFGR1_PRIV1         EXTI_PRIVCFGR1_PRIV1_Msk                  /*!< Privilege enable on line 1 */
16046 #define EXTI_PRIVCFGR1_PRIV2_Pos     (2U)
16047 #define EXTI_PRIVCFGR1_PRIV2_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV2_Pos)       /*!< 0x00000004 */
16048 #define EXTI_PRIVCFGR1_PRIV2         EXTI_PRIVCFGR1_PRIV2_Msk                  /*!< Privilege enable on line 2 */
16049 #define EXTI_PRIVCFGR1_PRIV3_Pos     (3U)
16050 #define EXTI_PRIVCFGR1_PRIV3_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV3_Pos)       /*!< 0x00000008 */
16051 #define EXTI_PRIVCFGR1_PRIV3         EXTI_PRIVCFGR1_PRIV3_Msk                  /*!< Privilege enable on line 3 */
16052 #define EXTI_PRIVCFGR1_PRIV4_Pos     (4U)
16053 #define EXTI_PRIVCFGR1_PRIV4_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV4_Pos)       /*!< 0x00000010 */
16054 #define EXTI_PRIVCFGR1_PRIV4         EXTI_PRIVCFGR1_PRIV4_Msk                  /*!< Privilege enable on line 4 */
16055 #define EXTI_PRIVCFGR1_PRIV5_Pos     (5U)
16056 #define EXTI_PRIVCFGR1_PRIV5_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV5_Pos)       /*!< 0x00000020 */
16057 #define EXTI_PRIVCFGR1_PRIV5         EXTI_PRIVCFGR1_PRIV5_Msk                  /*!< Privilege enable on line 5 */
16058 #define EXTI_PRIVCFGR1_PRIV6_Pos     (6U)
16059 #define EXTI_PRIVCFGR1_PRIV6_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV6_Pos)       /*!< 0x00000040 */
16060 #define EXTI_PRIVCFGR1_PRIV6         EXTI_PRIVCFGR1_PRIV6_Msk                  /*!< Privilege enable on line 6 */
16061 #define EXTI_PRIVCFGR1_PRIV7_Pos     (7U)
16062 #define EXTI_PRIVCFGR1_PRIV7_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV7_Pos)       /*!< 0x00000080 */
16063 #define EXTI_PRIVCFGR1_PRIV7         EXTI_PRIVCFGR1_PRIV7_Msk                  /*!< Privilege enable on line 7 */
16064 #define EXTI_PRIVCFGR1_PRIV8_Pos     (8U)
16065 #define EXTI_PRIVCFGR1_PRIV8_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV8_Pos)       /*!< 0x00000100 */
16066 #define EXTI_PRIVCFGR1_PRIV8         EXTI_PRIVCFGR1_PRIV8_Msk                  /*!< Privilege enable on line 8 */
16067 #define EXTI_PRIVCFGR1_PRIV9_Pos     (9U)
16068 #define EXTI_PRIVCFGR1_PRIV9_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV9_Pos)       /*!< 0x00000200 */
16069 #define EXTI_PRIVCFGR1_PRIV9         EXTI_PRIVCFGR1_PRIV9_Msk                  /*!< Privilege enable on line 9 */
16070 #define EXTI_PRIVCFGR1_PRIV10_Pos    (10U)
16071 #define EXTI_PRIVCFGR1_PRIV10_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV10_Pos)      /*!< 0x00000400 */
16072 #define EXTI_PRIVCFGR1_PRIV10        EXTI_PRIVCFGR1_PRIV10_Msk                 /*!< Privilege enable on line 10 */
16073 #define EXTI_PRIVCFGR1_PRIV11_Pos    (11U)
16074 #define EXTI_PRIVCFGR1_PRIV11_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV11_Pos)      /*!< 0x00000800 */
16075 #define EXTI_PRIVCFGR1_PRIV11        EXTI_PRIVCFGR1_PRIV11_Msk                 /*!< Privilege enable on line 11 */
16076 #define EXTI_PRIVCFGR1_PRIV12_Pos    (12U)
16077 #define EXTI_PRIVCFGR1_PRIV12_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV12_Pos)      /*!< 0x00001000 */
16078 #define EXTI_PRIVCFGR1_PRIV12        EXTI_PRIVCFGR1_PRIV12_Msk                 /*!< Privilege enable on line 12 */
16079 #define EXTI_PRIVCFGR1_PRIV13_Pos    (13U)
16080 #define EXTI_PRIVCFGR1_PRIV13_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV13_Pos)      /*!< 0x00002000 */
16081 #define EXTI_PRIVCFGR1_PRIV13        EXTI_PRIVCFGR1_PRIV13_Msk                 /*!< Privilege enable on line 13 */
16082 #define EXTI_PRIVCFGR1_PRIV14_Pos    (14U)
16083 #define EXTI_PRIVCFGR1_PRIV14_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV14_Pos)      /*!< 0x00004000 */
16084 #define EXTI_PRIVCFGR1_PRIV14        EXTI_PRIVCFGR1_PRIV14_Msk                 /*!< Privilege enable on line 14 */
16085 #define EXTI_PRIVCFGR1_PRIV15_Pos    (15U)
16086 #define EXTI_PRIVCFGR1_PRIV15_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV15_Pos)      /*!< 0x00008000 */
16087 #define EXTI_PRIVCFGR1_PRIV15        EXTI_PRIVCFGR1_PRIV15_Msk                 /*!< Privilege enable on line 15 */
16088 #define EXTI_PRIVCFGR1_PRIV17_Pos    (17U)
16089 #define EXTI_PRIVCFGR1_PRIV17_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV17_Pos)      /*!< 0x00020000 */
16090 #define EXTI_PRIVCFGR1_PRIV17        EXTI_PRIVCFGR1_PRIV17_Msk                 /*!< Privilege enable on line 17 */
16091 #define EXTI_PRIVCFGR1_PRIV18_Pos    (18U)
16092 #define EXTI_PRIVCFGR1_PRIV18_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV18_Pos)      /*!< 0x00040000 */
16093 #define EXTI_PRIVCFGR1_PRIV18        EXTI_PRIVCFGR1_PRIV18_Msk                 /*!< Privilege enable on line 18 */
16094 #define EXTI_PRIVCFGR1_PRIV19_Pos    (19U)
16095 #define EXTI_PRIVCFGR1_PRIV19_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV19_Pos)      /*!< 0x00080000 */
16096 #define EXTI_PRIVCFGR1_PRIV19        EXTI_PRIVCFGR1_PRIV19_Msk                 /*!< Privilege enable on line 19 */
16097 #define EXTI_PRIVCFGR1_PRIV20_Pos    (20U)
16098 #define EXTI_PRIVCFGR1_PRIV20_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV20_Pos)      /*!< 0x00100000 */
16099 #define EXTI_PRIVCFGR1_PRIV20        EXTI_PRIVCFGR1_PRIV20_Msk                 /*!< Privilege enable on line 20 */
16100 #define EXTI_PRIVCFGR1_PRIV21_Pos    (21U)
16101 #define EXTI_PRIVCFGR1_PRIV21_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV21_Pos)      /*!< 0x00200000 */
16102 #define EXTI_PRIVCFGR1_PRIV21        EXTI_PRIVCFGR1_PRIV21_Msk                 /*!< Privilege enable on line 21 */
16103 #define EXTI_PRIVCFGR1_PRIV22_Pos    (22U)
16104 #define EXTI_PRIVCFGR1_PRIV22_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV22_Pos)      /*!< 0x00400000 */
16105 #define EXTI_PRIVCFGR1_PRIV22        EXTI_PRIVCFGR1_PRIV22_Msk                 /*!< Privilege enable on line 22 */
16106 #define EXTI_PRIVCFGR1_PRIV23_Pos    (23U)
16107 #define EXTI_PRIVCFGR1_PRIV23_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV23_Pos)      /*!< 0x00800000 */
16108 #define EXTI_PRIVCFGR1_PRIV23        EXTI_PRIVCFGR1_PRIV23_Msk                 /*!< Privilege enable on line 23 */
16109 #define EXTI_PRIVCFGR1_PRIV24_Pos    (24U)
16110 #define EXTI_PRIVCFGR1_PRIV24_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV24_Pos)      /*!< 0x01000000 */
16111 #define EXTI_PRIVCFGR1_PRIV24        EXTI_PRIVCFGR1_PRIV24_Msk                 /*!< Privilege enable on line 24 */
16112 #define EXTI_PRIVCFGR1_PRIV25_Pos    (25U)
16113 #define EXTI_PRIVCFGR1_PRIV25_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV25_Pos)      /*!< 0x02000000 */
16114 #define EXTI_PRIVCFGR1_PRIV25        EXTI_PRIVCFGR1_PRIV25_Msk                 /*!< Privilege enable on line 25 */
16115 #define EXTI_PRIVCFGR1_PRIV26_Pos    (26U)
16116 #define EXTI_PRIVCFGR1_PRIV26_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV26_Pos)      /*!< 0x04000000 */
16117 #define EXTI_PRIVCFGR1_PRIV26        EXTI_PRIVCFGR1_PRIV26_Msk                 /*!< Privilege enable on line 26 */
16118 #define EXTI_PRIVCFGR1_PRIV27_Pos    (27U)
16119 #define EXTI_PRIVCFGR1_PRIV27_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV27_Pos)      /*!< 0x08000000 */
16120 #define EXTI_PRIVCFGR1_PRIV27        EXTI_PRIVCFGR1_PRIV27_Msk                 /*!< Privilege enable on line 27 */
16121 #define EXTI_PRIVCFGR1_PRIV28_Pos    (28U)
16122 #define EXTI_PRIVCFGR1_PRIV28_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV28_Pos)      /*!< 0x10000000 */
16123 #define EXTI_PRIVCFGR1_PRIV28        EXTI_PRIVCFGR1_PRIV28_Msk                 /*!< Privilege enable on line 28 */
16124 #define EXTI_PRIVCFGR1_PRIV29_Pos    (29U)
16125 #define EXTI_PRIVCFGR1_PRIV29_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV29_Pos)      /*!< 0x20000000 */
16126 #define EXTI_PRIVCFGR1_PRIV29        EXTI_PRIVCFGR1_PRIV29_Msk                 /*!< Privilege enable on line 29 */
16127 #define EXTI_PRIVCFGR1_PRIV30_Pos    (30U)
16128 #define EXTI_PRIVCFGR1_PRIV30_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV30_Pos)      /*!< 0x40000000 */
16129 #define EXTI_PRIVCFGR1_PRIV30        EXTI_PRIVCFGR1_PRIV30_Msk                 /*!< Privilege enable on line 30 */
16130 #define EXTI_PRIVCFGR1_PRIV31_Pos    (31U)
16131 #define EXTI_PRIVCFGR1_PRIV31_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV31_Pos)      /*!< 0x80000000 */
16132 #define EXTI_PRIVCFGR1_PRIV31        EXTI_PRIVCFGR1_PRIV31_Msk                 /*!< Privilege enable on line 31 */
16133 
16134 /*******************  Bit definition for EXTI_RTSR2 register  *****************/
16135 #define EXTI_RTSR2_RT39_Pos          (7U)
16136 #define EXTI_RTSR2_RT39_Msk          (0x1UL << EXTI_RTSR2_RT39_Pos)            /*!< 0x00000080 */
16137 #define EXTI_RTSR2_RT39              EXTI_RTSR2_RT39_Msk                       /*!< Rising trigger configuration for input line 39 */
16138 #define EXTI_RTSR2_RT40_Pos          (8U)
16139 #define EXTI_RTSR2_RT40_Msk          (0x1UL << EXTI_RTSR2_RT40_Pos)            /*!< 0x00000100 */
16140 #define EXTI_RTSR2_RT40              EXTI_RTSR2_RT40_Msk                       /*!< Rising trigger configuration for input line 40 */
16141 #define EXTI_RTSR2_RT51_Pos          (19U)
16142 #define EXTI_RTSR2_RT51_Msk          (0x1UL << EXTI_RTSR2_RT51_Pos)            /*!< 0x00080000 */
16143 #define EXTI_RTSR2_RT51              EXTI_RTSR2_RT51_Msk                       /*!< Rising trigger configuration for input line 51 */
16144 #define EXTI_RTSR2_RT54_Pos          (22U)
16145 #define EXTI_RTSR2_RT54_Msk          (0x1UL << EXTI_RTSR2_RT54_Pos)            /*!< 0x00400000 */
16146 #define EXTI_RTSR2_RT54              EXTI_RTSR2_RT54_Msk                       /*!< Rising trigger configuration for input line 54 */
16147 #define EXTI_RTSR2_RT56_Pos          (24U)
16148 #define EXTI_RTSR2_RT56_Msk          (0x1UL << EXTI_RTSR2_RT56_Pos)            /*!< 0x00100000 */
16149 #define EXTI_RTSR2_RT56              EXTI_RTSR2_RT56_Msk                       /*!< Rising trigger configuration for input line 56 */
16150 
16151 /*******************  Bit definition for EXTI_FTSR2 register  *****************/
16152 #define EXTI_FTSR2_FT39_Pos          (7U)
16153 #define EXTI_FTSR2_FT39_Msk          (0x1UL << EXTI_FTSR2_FT39_Pos)            /*!< 0x00000080 */
16154 #define EXTI_FTSR2_FT39              EXTI_FTSR2_FT39_Msk                       /*!< Falling trigger configuration for input line 39 */
16155 #define EXTI_FTSR2_FT40_Pos          (8U)
16156 #define EXTI_FTSR2_FT40_Msk          (0x1UL << EXTI_FTSR2_FT40_Pos)            /*!< 0x00000100 */
16157 #define EXTI_FTSR2_FT40              EXTI_FTSR2_FT40_Msk                       /*!< Falling trigger configuration for input line 40 */
16158 #define EXTI_FTSR2_FT51_Pos          (19U)
16159 #define EXTI_FTSR2_FT51_Msk          (0x1UL << EXTI_FTSR2_FT51_Pos)            /*!< 0x00080000 */
16160 #define EXTI_FTSR2_FT51              EXTI_FTSR2_FT51_Msk                       /*!< Falling trigger configuration for input line 51 */
16161 #define EXTI_FTSR2_FT54_Pos          (22U)
16162 #define EXTI_FTSR2_FT54_Msk          (0x1UL << EXTI_FTSR2_FT54_Pos)            /*!< 0x00400000 */
16163 #define EXTI_FTSR2_FT54              EXTI_FTSR2_FT54_Msk                       /*!< Falling trigger configuration for input line 54 */
16164 #define EXTI_FTSR2_FT56_Pos          (24U)
16165 #define EXTI_FTSR2_FT56_Msk          (0x1UL << EXTI_FTSR2_FT56_Pos)            /*!< 0x00100000 */
16166 #define EXTI_FTSR2_FT56              EXTI_FTSR2_FT56_Msk                       /*!< Falling trigger configuration for input line 56 */
16167 
16168 /*******************  Bit definition for EXTI_SWIER2 register  ****************/
16169 #define EXTI_SWIER2_SWI39_Pos        (7U)
16170 #define EXTI_SWIER2_SWI39_Msk        (0x1UL << EXTI_SWIER2_SWI39_Pos)          /*!< 0x00000080 */
16171 #define EXTI_SWIER2_SWI39            EXTI_SWIER2_SWI39_Msk                     /*!< Software Interrupt on line 39 */
16172 #define EXTI_SWIER2_SWI40_Pos        (8U)
16173 #define EXTI_SWIER2_SWI40_Msk        (0x1UL << EXTI_SWIER2_SWI40_Pos)          /*!< 0x00000100 */
16174 #define EXTI_SWIER2_SWI40            EXTI_SWIER2_SWI40_Msk                     /*!< Software Interrupt on line 40 */
16175 #define EXTI_SWIER2_SWI51_Pos        (19U)
16176 #define EXTI_SWIER2_SWI51_Msk        (0x1UL << EXTI_SWIER2_SWI51_Pos)          /*!< 0x00080000 */
16177 #define EXTI_SWIER2_SWI51            EXTI_SWIER2_SWI51_Msk                     /*!< Software Interrupt on line 51 */
16178 #define EXTI_SWIER2_SWI54_Pos        (22U)
16179 #define EXTI_SWIER2_SWI54_Msk        (0x1UL << EXTI_SWIER2_SWI54_Pos)          /*!< 0x00400000 */
16180 #define EXTI_SWIER2_SWI54            EXTI_SWIER2_SWI54_Msk                     /*!< Software Interrupt on line 54 */
16181 #define EXTI_SWIER2_SWI56_Pos        (24U)
16182 #define EXTI_SWIER2_SWI56_Msk        (0x1UL << EXTI_SWIER2_SWI56_Pos)          /*!< 0x00100000 */
16183 #define EXTI_SWIER2_SWI56            EXTI_SWIER2_SWI56_Msk                     /*!< Software Interrupt on line 56 */
16184 
16185 /*******************  Bit definition for EXTI_RPR2 register  ******************/
16186 #define EXTI_RPR2_RPIF39_Pos         (7U)
16187 #define EXTI_RPR2_RPIF39_Msk         (0x1UL << EXTI_RPR2_RPIF39_Pos)           /*!< 0x00000080 */
16188 #define EXTI_RPR2_RPIF39             EXTI_RPR2_RPIF39_Msk                      /*!< Rising Pending Interrupt Flag on line 39 */
16189 #define EXTI_RPR2_RPIF40_Pos         (8U)
16190 #define EXTI_RPR2_RPIF40_Msk         (0x1UL << EXTI_RPR2_RPIF40_Pos)           /*!< 0x00000100 */
16191 #define EXTI_RPR2_RPIF40             EXTI_RPR2_RPIF40_Msk                      /*!< Rising Pending Interrupt Flag on line 40 */
16192 #define EXTI_RPR2_RPIF51_Pos         (19U)
16193 #define EXTI_RPR2_RPIF51_Msk         (0x1UL << EXTI_RPR2_RPIF51_Pos)           /*!< 0x00080000 */
16194 #define EXTI_RPR2_RPIF51             EXTI_RPR2_RPIF51_Msk                      /*!< Rising Pending Interrupt Flag on line 51 */
16195 #define EXTI_RPR2_RPIF54_Pos         (22U)
16196 #define EXTI_RPR2_RPIF54_Msk         (0x1UL << EXTI_RPR2_RPIF54_Pos)           /*!< 0x00400000 */
16197 #define EXTI_RPR2_RPIF54             EXTI_RPR2_RPIF54_Msk                      /*!< Rising Pending Interrupt Flag on line 54 */
16198 #define EXTI_RPR2_RPIF56_Pos         (24U)
16199 #define EXTI_RPR2_RPIF56_Msk         (0x1UL << EXTI_RPR2_RPIF56_Pos)           /*!< 0x00100000 */
16200 #define EXTI_RPR2_RPIF56             EXTI_RPR2_RPIF56_Msk                      /*!< Rising Pending Interrupt Flag on line 56 */
16201 
16202 /*******************  Bit definition for EXTI_FPR2 register  ******************/
16203 #define EXTI_FPR2_FPIF39_Pos         (7U)
16204 #define EXTI_FPR2_FPIF39_Msk         (0x1UL << EXTI_FPR2_FPIF39_Pos)           /*!< 0x00000080 */
16205 #define EXTI_FPR2_FPIF39             EXTI_FPR2_FPIF39_Msk                      /*!< Falling Pending Interrupt Flag on line 39 */
16206 #define EXTI_FPR2_FPIF40_Pos         (8U)
16207 #define EXTI_FPR2_FPIF40_Msk         (0x1UL << EXTI_FPR2_FPIF40_Pos)           /*!< 0x00000100 */
16208 #define EXTI_FPR2_FPIF40             EXTI_FPR2_FPIF40_Msk                      /*!< Falling Pending Interrupt Flag on line 40 */
16209 #define EXTI_FPR2_FPIF51_Pos         (19U)
16210 #define EXTI_FPR2_FPIF51_Msk         (0x1UL << EXTI_FPR2_FPIF51_Pos)           /*!< 0x00080000 */
16211 #define EXTI_FPR2_FPIF51             EXTI_FPR2_FPIF51_Msk                      /*!< Falling Pending Interrupt Flag on line 51 */
16212 #define EXTI_FPR2_FPIF54_Pos         (22U)
16213 #define EXTI_FPR2_FPIF54_Msk         (0x1UL << EXTI_FPR2_FPIF54_Pos)           /*!< 0x00400000 */
16214 #define EXTI_FPR2_FPIF54             EXTI_FPR2_FPIF54_Msk                      /*!< Falling Pending Interrupt Flag on line 54 */
16215 #define EXTI_FPR2_FPIF56_Pos         (24U)
16216 #define EXTI_FPR2_FPIF56_Msk         (0x1UL << EXTI_FPR2_FPIF56_Pos)           /*!< 0x00100000 */
16217 #define EXTI_FPR2_FPIF56             EXTI_FPR2_FPIF56_Msk                      /*!< Falling Pending Interrupt Flag on line 56 */
16218 
16219 /*******************  Bit definition for EXTI_SECCFGR2 register  ******************/
16220 #define EXTI_SECCFGR2_SEC32_Pos      (0U)
16221 #define EXTI_SECCFGR2_SEC32_Msk      (0x1UL << EXTI_SECCFGR2_SEC32_Pos)        /*!< 0x00000001 */
16222 #define EXTI_SECCFGR2_SEC32          EXTI_SECCFGR2_SEC32_Msk                   /*!< Security enable on line 32 */
16223 #define EXTI_SECCFGR2_SEC33_Pos      (1U)
16224 #define EXTI_SECCFGR2_SEC33_Msk      (0x1UL << EXTI_SECCFGR2_SEC33_Pos)        /*!< 0x00000002 */
16225 #define EXTI_SECCFGR2_SEC33          EXTI_SECCFGR2_SEC33_Msk                   /*!< Security enable on line 33 */
16226 #define EXTI_SECCFGR2_SEC34_Pos      (2U)
16227 #define EXTI_SECCFGR2_SEC34_Msk      (0x1UL << EXTI_SECCFGR2_SEC34_Pos)        /*!< 0x00000004 */
16228 #define EXTI_SECCFGR2_SEC34          EXTI_SECCFGR2_SEC34_Msk                   /*!< Security enable on line 34 */
16229 #define EXTI_SECCFGR2_SEC35_Pos      (3U)
16230 #define EXTI_SECCFGR2_SEC35_Msk      (0x1UL << EXTI_SECCFGR2_SEC35_Pos)        /*!< 0x00000008 */
16231 #define EXTI_SECCFGR2_SEC35          EXTI_SECCFGR2_SEC35_Msk                   /*!< Security enable on line 35 */
16232 #define EXTI_SECCFGR2_SEC36_Pos      (4U)
16233 #define EXTI_SECCFGR2_SEC36_Msk      (0x1UL << EXTI_SECCFGR2_SEC36_Pos)        /*!< 0x00000010 */
16234 #define EXTI_SECCFGR2_SEC36          EXTI_SECCFGR2_SEC36_Msk                   /*!< Security enable on line 36 */
16235 #define EXTI_SECCFGR2_SEC37_Pos      (5U)
16236 #define EXTI_SECCFGR2_SEC37_Msk      (0x1UL << EXTI_SECCFGR2_SEC37_Pos)        /*!< 0x00000020 */
16237 #define EXTI_SECCFGR2_SEC37          EXTI_SECCFGR2_SEC37_Msk                   /*!< Security enable on line 37 */
16238 #define EXTI_SECCFGR2_SEC38_Pos      (6U)
16239 #define EXTI_SECCFGR2_SEC38_Msk      (0x1UL << EXTI_SECCFGR2_SEC38_Pos)        /*!< 0x00000040 */
16240 #define EXTI_SECCFGR2_SEC38          EXTI_SECCFGR2_SEC38_Msk                   /*!< Security enable on line 38 */
16241 #define EXTI_SECCFGR2_SEC39_Pos      (7U)
16242 #define EXTI_SECCFGR2_SEC39_Msk      (0x1UL << EXTI_SECCFGR2_SEC39_Pos)        /*!< 0x00000080 */
16243 #define EXTI_SECCFGR2_SEC39          EXTI_SECCFGR2_SEC39_Msk                   /*!< Security enable on line 39 */
16244 #define EXTI_SECCFGR2_SEC40_Pos      (8U)
16245 #define EXTI_SECCFGR2_SEC40_Msk      (0x1UL << EXTI_SECCFGR2_SEC40_Pos)        /*!< 0x00000100 */
16246 #define EXTI_SECCFGR2_SEC40          EXTI_SECCFGR2_SEC40_Msk                   /*!< Security enable on line 40 */
16247 #define EXTI_SECCFGR2_SEC41_Pos      (9U)
16248 #define EXTI_SECCFGR2_SEC41_Msk      (0x1UL << EXTI_SECCFGR2_SEC41_Pos)        /*!< 0x00000200 */
16249 #define EXTI_SECCFGR2_SEC41          EXTI_SECCFGR2_SEC41_Msk                   /*!< Security enable on line 41 */
16250 #define EXTI_SECCFGR2_SEC42_Pos      (10U)
16251 #define EXTI_SECCFGR2_SEC42_Msk      (0x1UL << EXTI_SECCFGR2_SEC42_Pos)        /*!< 0x00000400 */
16252 #define EXTI_SECCFGR2_SEC42          EXTI_SECCFGR2_SEC42_Msk                   /*!< Security enable on line 42 */
16253 #define EXTI_SECCFGR2_SEC43_Pos      (11U)
16254 #define EXTI_SECCFGR2_SEC43_Msk      (0x1UL << EXTI_SECCFGR2_SEC43_Pos)        /*!< 0x00000800 */
16255 #define EXTI_SECCFGR2_SEC43          EXTI_SECCFGR2_SEC43_Msk                   /*!< Security enable on line 43 */
16256 #define EXTI_SECCFGR2_SEC44_Pos      (12U)
16257 #define EXTI_SECCFGR2_SEC44_Msk      (0x1UL << EXTI_SECCFGR2_SEC44_Pos)        /*!< 0x00001000 */
16258 #define EXTI_SECCFGR2_SEC44          EXTI_SECCFGR2_SEC44_Msk                   /*!< Security enable on line 44 */
16259 #define EXTI_SECCFGR2_SEC45_Pos      (13U)
16260 #define EXTI_SECCFGR2_SEC45_Msk      (0x1UL << EXTI_SECCFGR2_SEC45_Pos)        /*!< 0x00002000 */
16261 #define EXTI_SECCFGR2_SEC45          EXTI_SECCFGR2_SEC45                       /*!< Security enable on line 45 */
16262 #define EXTI_SECCFGR2_SEC46_Pos      (14U)
16263 #define EXTI_SECCFGR2_SEC46_Msk      (0x1UL << EXTI_SECCFGR2_SEC46_Pos)        /*!< 0x00004000 */
16264 #define EXTI_SECCFGR2_SEC46          EXTI_SECCFGR2_SEC46_Msk                   /*!< Security enable on line 46 */
16265 #define EXTI_SECCFGR2_SEC47_Pos      (15U)
16266 #define EXTI_SECCFGR2_SEC47_Msk      (0x1UL << EXTI_SECCFGR2_SEC47_Pos)        /*!< 0x00008000 */
16267 #define EXTI_SECCFGR2_SEC47          EXTI_SECCFGR2_SEC47_Msk                   /*!< Security enable on line 47 */
16268 #define EXTI_SECCFGR2_SEC48_Pos      (16U)
16269 #define EXTI_SECCFGR2_SEC48_Msk      (0x1UL << EXTI_SECCFGR2_SEC48_Pos)        /*!< 0x00010000 */
16270 #define EXTI_SECCFGR2_SEC48          EXTI_SECCFGR2_SEC48_Msk                   /*!< Security enable on line 48 */
16271 #define EXTI_SECCFGR2_SEC49_Pos      (17U)
16272 #define EXTI_SECCFGR2_SEC49_Msk      (0x1UL << EXTI_SECCFGR2_SEC49_Pos)        /*!< 0x00020000 */
16273 #define EXTI_SECCFGR2_SEC49          EXTI_SECCFGR2_SEC49_Msk                   /*!< Security enable on line 49 */
16274 #define EXTI_SECCFGR2_SEC50_Pos      (18U)
16275 #define EXTI_SECCFGR2_SEC50_Msk      (0x1UL << EXTI_SECCFGR2_SEC50_Pos)        /*!< 0x00040000 */
16276 #define EXTI_SECCFGR2_SEC50          EXTI_SECCFGR2_SEC50_Msk                   /*!< Security enable on line 50 */
16277 #define EXTI_SECCFGR2_SEC51_Pos      (19U)
16278 #define EXTI_SECCFGR2_SEC51_Msk      (0x1UL << EXTI_SECCFGR2_SEC51_Pos)        /*!< 0x00080000 */
16279 #define EXTI_SECCFGR2_SEC51          EXTI_SECCFGR2_SEC51_Msk                   /*!< Security enable on line 51 */
16280 #define EXTI_SECCFGR2_SEC52_Pos      (20U)
16281 #define EXTI_SECCFGR2_SEC52_Msk      (0x1UL << EXTI_SECCFGR2_SEC52_Pos)        /*!< 0x00100000 */
16282 #define EXTI_SECCFGR2_SEC52          EXTI_SECCFGR2_SEC52_Msk                   /*!< Security enable on line 52 */
16283 #define EXTI_SECCFGR2_SEC53_Pos      (21U)
16284 #define EXTI_SECCFGR2_SEC53_Msk      (0x1UL << EXTI_SECCFGR2_SEC53_Pos)        /*!< 0x00200000 */
16285 #define EXTI_SECCFGR2_SEC53          EXTI_SECCFGR2_SEC53_Msk                   /*!< Security enable on line 53 */
16286 #define EXTI_SECCFGR2_SEC54_Pos      (22U)
16287 #define EXTI_SECCFGR2_SEC54_Msk      (0x1UL << EXTI_SECCFGR2_SEC54_Pos)        /*!< 0x00400000 */
16288 #define EXTI_SECCFGR2_SEC54          EXTI_SECCFGR2_SEC54_Msk                   /*!< Security enable on line 54 */
16289 #define EXTI_SECCFGR2_SEC55_Pos      (23U)
16290 #define EXTI_SECCFGR2_SEC55_Msk      (0x1UL << EXTI_SECCFGR2_SEC55_Pos)        /*!< 0x00800000 */
16291 #define EXTI_SECCFGR2_SEC55          EXTI_SECCFGR2_SEC55_Msk                   /*!< Security enable on line 55 */
16292 #define EXTI_SECCFGR2_SEC56_Pos      (24U)
16293 #define EXTI_SECCFGR2_SEC56_Msk      (0x1UL << EXTI_SECCFGR2_SEC56_Pos)        /*!< 0x01000000 */
16294 #define EXTI_SECCFGR2_SEC56          EXTI_SECCFGR2_SEC56_Msk                   /*!< Security enable on line 56 */
16295 #define EXTI_SECCFGR2_SEC57_Pos      (25U)
16296 #define EXTI_SECCFGR2_SEC57_Msk      (0x1UL << EXTI_SECCFGR2_SEC57_Pos)        /*!< 0x02000000 */
16297 #define EXTI_SECCFGR2_SEC57          EXTI_SECCFGR2_SEC57_Msk                   /*!< Security enable on line 57 */
16298 #define EXTI_SECCFGR2_SEC58_Pos      (26U)
16299 #define EXTI_SECCFGR2_SEC58_Msk      (0x1UL << EXTI_SECCFGR2_SEC58_Pos)        /*!< 0x04000000 */
16300 #define EXTI_SECCFGR2_SEC58          EXTI_SECCFGR2_SEC58_Msk                   /*!< Security enable on line 58 */
16301 #define EXTI_SECCFGR2_SEC60_Pos      (28U)
16302 #define EXTI_SECCFGR2_SEC60_Msk      (0x1UL << EXTI_SECCFGR2_SEC60_Pos)        /*!< 0x10000000 */
16303 #define EXTI_SECCFGR2_SEC60          EXTI_SECCFGR2_SEC60_Msk                   /*!< Security enable on line 60 */
16304 #define EXTI_SECCFGR2_SEC61_Pos      (29U)
16305 #define EXTI_SECCFGR2_SEC61_Msk      (0x1UL << EXTI_SECCFGR2_SEC61_Pos)        /*!< 0x20000000 */
16306 #define EXTI_SECCFGR2_SEC61          EXTI_SECCFGR2_SEC61_Msk                   /*!< Security enable on line 61 */
16307 #define EXTI_SECCFGR2_SEC62_Pos      (30U)
16308 #define EXTI_SECCFGR2_SEC62_Msk      (0x1UL << EXTI_SECCFGR2_SEC62_Pos)        /*!< 0x40000000 */
16309 #define EXTI_SECCFGR2_SEC62          EXTI_SECCFGR2_SEC62_Msk                   /*!< Security enable on line 62 */
16310 #define EXTI_SECCFGR2_SEC63_Pos      (31U)
16311 #define EXTI_SECCFGR2_SEC63_Msk      (0x1UL << EXTI_SECCFGR2_SEC63_Pos)        /*!< 0x80000000 */
16312 #define EXTI_SECCFGR2_SEC63          EXTI_SECCFGR2_SEC63_Msk                   /*!< Security enable on line 63 */
16313 
16314 /*******************  Bit definition for EXTI_PRIVCFGR2 register  ******************/
16315 #define EXTI_PRIVCFGR2_PRIV32_Pos    (0U)
16316 #define EXTI_PRIVCFGR2_PRIV32_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV32_Pos)      /*!< 0x00000001 */
16317 #define EXTI_PRIVCFGR2_PRIV32        EXTI_PRIVCFGR2_PRIV32_Msk                 /*!< Privilege enable on line 32 */
16318 #define EXTI_PRIVCFGR2_PRIV33_Pos    (1U)
16319 #define EXTI_PRIVCFGR2_PRIV33_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV33_Pos)      /*!< 0x00000002 */
16320 #define EXTI_PRIVCFGR2_PRIV33        EXTI_PRIVCFGR2_PRIV33_Msk                 /*!< Privilege enable on line 33 */
16321 #define EXTI_PRIVCFGR2_PRIV34_Pos    (2U)
16322 #define EXTI_PRIVCFGR2_PRIV34_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV34_Pos)      /*!< 0x00000004 */
16323 #define EXTI_PRIVCFGR2_PRIV34        EXTI_PRIVCFGR2_PRIV34_Msk                 /*!< Privilege enable on line 34 */
16324 #define EXTI_PRIVCFGR2_PRIV35_Pos    (3U)
16325 #define EXTI_PRIVCFGR2_PRIV35_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV35_Pos)      /*!< 0x00000008 */
16326 #define EXTI_PRIVCFGR2_PRIV35        EXTI_PRIVCFGR2_PRIV35_Msk                 /*!< Privilege enable on line 35 */
16327 #define EXTI_PRIVCFGR2_PRIV36_Pos    (4U)
16328 #define EXTI_PRIVCFGR2_PRIV36_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV36_Pos)      /*!< 0x00000010 */
16329 #define EXTI_PRIVCFGR2_PRIV36        EXTI_PRIVCFGR2_PRIV36_Msk                 /*!< Privilege enable on line 36 */
16330 #define EXTI_PRIVCFGR2_PRIV37_Pos    (5U)
16331 #define EXTI_PRIVCFGR2_PRIV37_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV37_Pos)      /*!< 0x00000020 */
16332 #define EXTI_PRIVCFGR2_PRIV37        EXTI_PRIVCFGR2_PRIV37_Msk                 /*!< Privilege enable on line 37 */
16333 #define EXTI_PRIVCFGR2_PRIV38_Pos    (6U)
16334 #define EXTI_PRIVCFGR2_PRIV38_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV38_Pos)      /*!< 0x00000040 */
16335 #define EXTI_PRIVCFGR2_PRIV38        EXTI_PRIVCFGR2_PRIV38_Msk                 /*!< Privilege enable on line 38 */
16336 #define EXTI_PRIVCFGR2_PRIV39_Pos    (7U)
16337 #define EXTI_PRIVCFGR2_PRIV39_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV39_Pos)      /*!< 0x00000080 */
16338 #define EXTI_PRIVCFGR2_PRIV39        EXTI_PRIVCFGR2_PRIV39_Msk                 /*!< Privilege enable on line 39 */
16339 #define EXTI_PRIVCFGR2_PRIV40_Pos    (8U)
16340 #define EXTI_PRIVCFGR2_PRIV40_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV40_Pos)      /*!< 0x00000100 */
16341 #define EXTI_PRIVCFGR2_PRIV40        EXTI_PRIVCFGR2_PRIV40_Msk                 /*!< Privilege enable on line 40 */
16342 #define EXTI_PRIVCFGR2_PRIV41_Pos    (9U)
16343 #define EXTI_PRIVCFGR2_PRIV41_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV41_Pos)      /*!< 0x00000200 */
16344 #define EXTI_PRIVCFGR2_PRIV41        EXTI_PRIVCFGR2_PRIV41_Msk                 /*!< Privilege enable on line 41 */
16345 #define EXTI_PRIVCFGR2_PRIV42_Pos    (10U)
16346 #define EXTI_PRIVCFGR2_PRIV42_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV42_Pos)      /*!< 0x00000400 */
16347 #define EXTI_PRIVCFGR2_PRIV42        EXTI_PRIVCFGR2_PRIV42_Msk                 /*!< Privilege enable on line 42 */
16348 #define EXTI_PRIVCFGR2_PRIV43_Pos    (11U)
16349 #define EXTI_PRIVCFGR2_PRIV43_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV43_Pos)      /*!< 0x00000800 */
16350 #define EXTI_PRIVCFGR2_PRIV43        EXTI_PRIVCFGR2_PRIV43_Msk                 /*!< Privilege enable on line 43 */
16351 #define EXTI_PRIVCFGR2_PRIV44_Pos    (12U)
16352 #define EXTI_PRIVCFGR2_PRIV44_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV44_Pos)      /*!< 0x00001000 */
16353 #define EXTI_PRIVCFGR2_PRIV44        EXTI_PRIVCFGR2_PRIV44_Msk                 /*!< Privilege enable on line 44 */
16354 #define EXTI_PRIVCFGR2_PRIV45_Pos    (13U)
16355 #define EXTI_PRIVCFGR2_PRIV45_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV45_Pos)      /*!< 0x00002000 */
16356 #define EXTI_PRIVCFGR2_PRIV45        EXTI_PRIVCFGR2_PRIV45                     /*!< Privilege enable on line 45 */
16357 #define EXTI_PRIVCFGR2_PRIV46_Pos    (14U)
16358 #define EXTI_PRIVCFGR2_PRIV46_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV46_Pos)      /*!< 0x00004000 */
16359 #define EXTI_PRIVCFGR2_PRIV46        EXTI_PRIVCFGR2_PRIV46_Msk                 /*!< Privilege enable on line 46 */
16360 #define EXTI_PRIVCFGR2_PRIV47_Pos    (15U)
16361 #define EXTI_PRIVCFGR2_PRIV47_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV47_Pos)      /*!< 0x00008000 */
16362 #define EXTI_PRIVCFGR2_PRIV47        EXTI_PRIVCFGR2_PRIV47_Msk                 /*!< Privilege enable on line 47 */
16363 #define EXTI_PRIVCFGR2_PRIV48_Pos    (16U)
16364 #define EXTI_PRIVCFGR2_PRIV48_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV48_Pos)      /*!< 0x00010000 */
16365 #define EXTI_PRIVCFGR2_PRIV48        EXTI_PRIVCFGR2_PRIV48_Msk                 /*!< Privilege enable on line 48 */
16366 #define EXTI_PRIVCFGR2_PRIV49_Pos    (17U)
16367 #define EXTI_PRIVCFGR2_PRIV49_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV49_Pos)      /*!< 0x00020000 */
16368 #define EXTI_PRIVCFGR2_PRIV49        EXTI_PRIVCFGR2_PRIV49_Msk                 /*!< Privilege enable on line 49 */
16369 #define EXTI_PRIVCFGR2_PRIV50_Pos    (18U)
16370 #define EXTI_PRIVCFGR2_PRIV50_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV50_Pos)      /*!< 0x00040000 */
16371 #define EXTI_PRIVCFGR2_PRIV50        EXTI_PRIVCFGR2_PRIV50_Msk                 /*!< Privilege enable on line 50 */
16372 #define EXTI_PRIVCFGR2_PRIV51_Pos    (19U)
16373 #define EXTI_PRIVCFGR2_PRIV51_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV51_Pos)      /*!< 0x00080000 */
16374 #define EXTI_PRIVCFGR2_PRIV51        EXTI_PRIVCFGR2_PRIV51_Msk                 /*!< Privilege enable on line 51 */
16375 #define EXTI_PRIVCFGR2_PRIV52_Pos    (20U)
16376 #define EXTI_PRIVCFGR2_PRIV52_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV52_Pos)      /*!< 0x00100000 */
16377 #define EXTI_PRIVCFGR2_PRIV52        EXTI_PRIVCFGR2_PRIV52_Msk                 /*!< Privilege enable on line 52 */
16378 #define EXTI_PRIVCFGR2_PRIV53_Pos    (21U)
16379 #define EXTI_PRIVCFGR2_PRIV53_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV53_Pos)      /*!< 0x00200000 */
16380 #define EXTI_PRIVCFGR2_PRIV53        EXTI_PRIVCFGR2_PRIV53_Msk                 /*!< Privilege enable on line 53 */
16381 #define EXTI_PRIVCFGR2_PRIV54_Pos    (22U)
16382 #define EXTI_PRIVCFGR2_PRIV54_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV54_Pos)      /*!< 0x00400000 */
16383 #define EXTI_PRIVCFGR2_PRIV54        EXTI_PRIVCFGR2_PRIV54_Msk                 /*!< Privilege enable on line 54 */
16384 #define EXTI_PRIVCFGR2_PRIV55_Pos    (23U)
16385 #define EXTI_PRIVCFGR2_PRIV55_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV55_Pos)      /*!< 0x00800000 */
16386 #define EXTI_PRIVCFGR2_PRIV55        EXTI_PRIVCFGR2_PRIV55_Msk                 /*!< Privilege enable on line 55 */
16387 #define EXTI_PRIVCFGR2_PRIV56_Pos    (24U)
16388 #define EXTI_PRIVCFGR2_PRIV56_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV56_Pos)      /*!< 0x01000000 */
16389 #define EXTI_PRIVCFGR2_PRIV56        EXTI_PRIVCFGR2_PRIV56_Msk                 /*!< Privilege enable on line 56 */
16390 #define EXTI_PRIVCFGR2_PRIV57_Pos    (25U)
16391 #define EXTI_PRIVCFGR2_PRIV57_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV57_Pos)      /*!< 0x02000000 */
16392 #define EXTI_PRIVCFGR2_PRIV57        EXTI_PRIVCFGR2_PRIV57_Msk                 /*!< Privilege enable on line 57 */
16393 #define EXTI_PRIVCFGR2_PRIV58_Pos    (26U)
16394 #define EXTI_PRIVCFGR2_PRIV58_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV58_Pos)      /*!< 0x04000000 */
16395 #define EXTI_PRIVCFGR2_PRIV58        EXTI_PRIVCFGR2_PRIV58_Msk                 /*!< Privilege enable on line 58 */
16396 #define EXTI_PRIVCFGR2_PRIV60_Pos    (28U)
16397 #define EXTI_PRIVCFGR2_PRIV60_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV60_Pos)      /*!< 0x10000000 */
16398 #define EXTI_PRIVCFGR2_PRIV60        EXTI_PRIVCFGR2_PRIV60_Msk                 /*!< Privilege enable on line 60 */
16399 #define EXTI_PRIVCFGR2_PRIV61_Pos    (29U)
16400 #define EXTI_PRIVCFGR2_PRIV61_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV61_Pos)      /*!< 0x20000000 */
16401 #define EXTI_PRIVCFGR2_PRIV61        EXTI_PRIVCFGR2_PRIV61_Msk                 /*!< Privilege enable on line 61 */
16402 #define EXTI_PRIVCFGR2_PRIV62_Pos    (30U)
16403 #define EXTI_PRIVCFGR2_PRIV62_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV62_Pos)      /*!< 0x40000000 */
16404 #define EXTI_PRIVCFGR2_PRIV62        EXTI_PRIVCFGR2_PRIV62_Msk                 /*!< Privilege enable on line 62 */
16405 #define EXTI_PRIVCFGR2_PRIV63_Pos    (31U)
16406 #define EXTI_PRIVCFGR2_PRIV63_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV63_Pos)      /*!< 0x80000000 */
16407 #define EXTI_PRIVCFGR2_PRIV63        EXTI_PRIVCFGR2_PRIV63_Msk                 /*!< Privilege enable on line 63 */
16408 
16409 /*******************  Bit definition for EXTI_RTSR3 register  *****************/
16410 #define EXTI_RTSR3_RT66_Pos          (2U)
16411 #define EXTI_RTSR3_RT66_Msk          (0x1UL << EXTI_RTSR3_RT66_Pos)            /*!< 0x00000004 */
16412 #define EXTI_RTSR3_RT66              EXTI_RTSR3_RT66_Msk                       /*!< Rising trigger configuration for input line 66 */
16413 #define EXTI_RTSR3_RT68_Pos          (4U)
16414 #define EXTI_RTSR3_RT68_Msk          (0x1UL << EXTI_RTSR3_RT68_Pos)            /*!< 0x00000010 */
16415 #define EXTI_RTSR3_RT68              EXTI_RTSR3_RT68_Msk                       /*!< Rising trigger configuration for input line 68 */
16416 #define EXTI_RTSR3_RT69_Pos          (5U)
16417 #define EXTI_RTSR3_RT69_Msk          (0x1UL << EXTI_RTSR3_RT69_Pos)            /*!< 0x00000020 */
16418 #define EXTI_RTSR3_RT69              EXTI_RTSR3_RT69_Msk                       /*!< Rising trigger configuration for input line 69 */
16419 #define EXTI_RTSR3_RT70_Pos          (6U)
16420 #define EXTI_RTSR3_RT70_Msk          (0x1UL << EXTI_RTSR3_RT70_Pos)            /*!< 0x00000040 */
16421 #define EXTI_RTSR3_RT70              EXTI_RTSR3_RT70_Msk                       /*!< Rising trigger configuration for input line 70 */
16422 #define EXTI_RTSR3_RT71_Pos          (7U)
16423 #define EXTI_RTSR3_RT71_Msk          (0x1UL << EXTI_RTSR3_RT71_Pos)            /*!< 0x00000080 */
16424 #define EXTI_RTSR3_RT71              EXTI_RTSR3_RT71_Msk                       /*!< Rising trigger configuration for input line 71 */
16425 #define EXTI_RTSR3_RT72_Pos          (8U)
16426 #define EXTI_RTSR3_RT72_Msk          (0x1UL << EXTI_RTSR3_RT72_Pos)            /*!< 0x00000100 */
16427 #define EXTI_RTSR3_RT72              EXTI_RTSR3_RT72_Msk                       /*!< Rising trigger configuration for input line 72 */
16428 #define EXTI_RTSR3_RT73_Pos          (9U)
16429 #define EXTI_RTSR3_RT73_Msk          (0x1UL << EXTI_RTSR3_RT73_Pos)            /*!< 0x00000200 */
16430 #define EXTI_RTSR3_RT73              EXTI_RTSR3_RT73_Msk                       /*!< Rising trigger configuration for input line 73 */
16431 #define EXTI_RTSR3_RT74_Pos          (10U)
16432 #define EXTI_RTSR3_RT74_Msk          (0x1UL << EXTI_RTSR3_RT74_Pos)            /*!< 0x00000400 */
16433 #define EXTI_RTSR3_RT74              EXTI_RTSR3_RT74_Msk                       /*!< Rising trigger configuration for input line 74 */
16434 
16435 /*******************  Bit definition for EXTI_FTSR3 register  *****************/
16436 #define EXTI_FTSR3_FT66_Pos          (2U)
16437 #define EXTI_FTSR3_FT66_Msk          (0x1UL << EXTI_FTSR3_FT66_Pos)            /*!< 0x00000004 */
16438 #define EXTI_FTSR3_FT66              EXTI_FTSR3_FT66_Msk                       /*!< Falling trigger configuration for input line 66 */
16439 #define EXTI_FTSR3_FT68_Pos          (4U)
16440 #define EXTI_FTSR3_FT68_Msk          (0x1UL << EXTI_FTSR3_FT68_Pos)            /*!< 0x00000010 */
16441 #define EXTI_FTSR3_FT68              EXTI_FTSR3_FT68_Msk                       /*!< Falling trigger configuration for input line 68 */
16442 #define EXTI_FTSR3_FT69_Pos          (5U)
16443 #define EXTI_FTSR3_FT69_Msk          (0x1UL << EXTI_FTSR3_FT69_Pos)            /*!< 0x00000020 */
16444 #define EXTI_FTSR3_FT69              EXTI_FTSR3_FT69_Msk                       /*!< Falling trigger configuration for input line 69 */
16445 #define EXTI_FTSR3_FT70_Pos          (6U)
16446 #define EXTI_FTSR3_FT70_Msk          (0x1UL << EXTI_FTSR3_FT70_Pos)            /*!< 0x00000040 */
16447 #define EXTI_FTSR3_FT70              EXTI_FTSR3_FT70_Msk                       /*!< Falling trigger configuration for input line 70 */
16448 #define EXTI_FTSR3_FT71_Pos          (7U)
16449 #define EXTI_FTSR3_FT71_Msk          (0x1UL << EXTI_FTSR3_FT71_Pos)            /*!< 0x00000080 */
16450 #define EXTI_FTSR3_FT71              EXTI_FTSR3_FT71_Msk                       /*!< Falling trigger configuration for input line 71 */
16451 #define EXTI_FTSR3_FT72_Pos          (8U)
16452 #define EXTI_FTSR3_FT72_Msk          (0x1UL << EXTI_FTSR3_FT72_Pos)            /*!< 0x00000100 */
16453 #define EXTI_FTSR3_FT72              EXTI_FTSR3_FT72_Msk                       /*!< Falling trigger configuration for input line 72 */
16454 #define EXTI_FTSR3_FT73_Pos          (9U)
16455 #define EXTI_FTSR3_FT73_Msk          (0x1UL << EXTI_FTSR3_FT73_Pos)            /*!< 0x00000200 */
16456 #define EXTI_FTSR3_FT73              EXTI_FTSR3_FT73_Msk                       /*!< Falling trigger configuration for input line 73 */
16457 #define EXTI_FTSR3_FT74_Pos          (10U)
16458 #define EXTI_FTSR3_FT74_Msk          (0x1UL << EXTI_FTSR3_FT74_Pos)            /*!< 0x00000400 */
16459 #define EXTI_FTSR3_FT74              EXTI_FTSR3_FT74_Msk                       /*!< Falling trigger configuration for input line 74 */
16460 
16461 /*******************  Bit definition for EXTI_SWIER3 register  ****************/
16462 #define EXTI_SWIER3_SWI66_Pos        (2U)
16463 #define EXTI_SWIER3_SWI66_Msk        (0x1UL << EXTI_SWIER3_SWI66_Pos)          /*!< 0x00000004 */
16464 #define EXTI_SWIER3_SWI66            EXTI_SWIER3_SWI66_Msk                     /*!< Software Interrupt on line 66 */
16465 #define EXTI_SWIER3_SWI68_Pos        (4U)
16466 #define EXTI_SWIER3_SWI68_Msk        (0x1UL << EXTI_SWIER3_SWI68_Pos)          /*!< 0x00000010 */
16467 #define EXTI_SWIER3_SWI68            EXTI_SWIER3_SWI68_Msk                     /*!< Software Interrupt on line 68 */
16468 #define EXTI_SWIER3_SWI69_Pos        (5U)
16469 #define EXTI_SWIER3_SWI69_Msk        (0x1UL << EXTI_SWIER3_SWI69_Pos)          /*!< 0x00000020 */
16470 #define EXTI_SWIER3_SWI69            EXTI_SWIER3_SWI69_Msk                     /*!< Software Interrupt on line 69 */
16471 #define EXTI_SWIER3_SWI70_Pos        (6U)
16472 #define EXTI_SWIER3_SWI70_Msk        (0x1UL << EXTI_SWIER3_SWI70_Pos)          /*!< 0x00000040 */
16473 #define EXTI_SWIER3_SWI70            EXTI_SWIER3_SWI70_Msk                     /*!< Software Interrupt on line 70 */
16474 #define EXTI_SWIER3_SWI71_Pos        (7U)
16475 #define EXTI_SWIER3_SWI71_Msk        (0x1UL << EXTI_SWIER3_SWI71_Pos)          /*!< 0x00000080 */
16476 #define EXTI_SWIER3_SWI71            EXTI_SWIER3_SWI71_Msk                     /*!< Software Interrupt on line 71 */
16477 #define EXTI_SWIER3_SWI72_Pos        (8U)
16478 #define EXTI_SWIER3_SWI72_Msk        (0x1UL << EXTI_SWIER3_SWI72_Pos)          /*!< 0x00000100 */
16479 #define EXTI_SWIER3_SWI72            EXTI_SWIER3_SWI72_Msk                     /*!< Software Interrupt on line 72 */
16480 #define EXTI_SWIER3_SWI73_Pos        (9U)
16481 #define EXTI_SWIER3_SWI73_Msk        (0x1UL << EXTI_SWIER3_SWI73_Pos)          /*!< 0x00000200 */
16482 #define EXTI_SWIER3_SWI73            EXTI_SWIER3_SWI73_Msk                     /*!< Software Interrupt on line 73 */
16483 #define EXTI_SWIER3_SWI74_Pos        (10U)
16484 #define EXTI_SWIER3_SWI74_Msk        (0x1UL << EXTI_SWIER3_SWI74_Pos)          /*!< 0x00000400 */
16485 #define EXTI_SWIER3_SWI74            EXTI_SWIER3_SWI74_Msk                     /*!< Software Interrupt on line 74 */
16486 
16487 /*******************  Bit definition for EXTI_RPR3 register  ******************/
16488 #define EXTI_RPR3_RPIF66_Pos         (2U)
16489 #define EXTI_RPR3_RPIF66_Msk         (0x1UL << EXTI_RPR3_RPIF66_Pos)           /*!< 0x00000004 */
16490 #define EXTI_RPR3_RPIF66             EXTI_RPR3_RPIF66_Msk                      /*!< Rising Pending Interrupt Flag on line 66 */
16491 #define EXTI_RPR3_RPIF68_Pos         (4U)
16492 #define EXTI_RPR3_RPIF68_Msk         (0x1UL << EXTI_RPR3_RPIF68_Pos)           /*!< 0x00000010 */
16493 #define EXTI_RPR3_RPIF68             EXTI_RPR3_RPIF68_Msk                      /*!< Rising Pending Interrupt Flag on line 68 */
16494 #define EXTI_RPR3_RPIF69_Pos         (5U)
16495 #define EXTI_RPR3_RPIF69_Msk         (0x1UL << EXTI_RPR3_RPIF69_Pos)           /*!< 0x00000020 */
16496 #define EXTI_RPR3_RPIF69             EXTI_RPR3_RPIF69_Msk                      /*!< Rising Pending Interrupt Flag on line 69 */
16497 #define EXTI_RPR3_RPIF70_Pos         (6U)
16498 #define EXTI_RPR3_RPIF70_Msk         (0x1UL << EXTI_RPR3_RPIF70_Pos)           /*!< 0x00000040 */
16499 #define EXTI_RPR3_RPIF70             EXTI_RPR3_RPIF70_Msk                      /*!< Rising Pending Interrupt Flag on line 70 */
16500 #define EXTI_RPR3_RPIF71_Pos         (7U)
16501 #define EXTI_RPR3_RPIF71_Msk         (0x1UL << EXTI_RPR3_RPIF71_Pos)           /*!< 0x00000080 */
16502 #define EXTI_RPR3_RPIF71             EXTI_RPR3_RPIF71_Msk                      /*!< Rising Pending Interrupt Flag on line 71 */
16503 #define EXTI_RPR3_RPIF72_Pos         (8U)
16504 #define EXTI_RPR3_RPIF72_Msk         (0x1UL << EXTI_RPR3_RPIF72_Pos)           /*!< 0x00000100 */
16505 #define EXTI_RPR3_RPIF72             EXTI_RPR3_RPIF72_Msk                      /*!< Rising Pending Interrupt Flag on line 72 */
16506 #define EXTI_RPR3_RPIF73_Pos         (9U)
16507 #define EXTI_RPR3_RPIF73_Msk         (0x1UL << EXTI_RPR3_RPIF73_Pos)           /*!< 0x00000200 */
16508 #define EXTI_RPR3_RPIF73             EXTI_RPR3_RPIF73_Msk                      /*!< Rising Pending Interrupt Flag on line 73 */
16509 #define EXTI_RPR3_RPIF74_Pos         (10U)
16510 #define EXTI_RPR3_RPIF74_Msk         (0x1UL << EXTI_RPR3_RPIF74_Pos)           /*!< 0x00000400 */
16511 #define EXTI_RPR3_RPIF74             EXTI_RPR3_RPIF74_Msk                      /*!< Rising Pending Interrupt Flag on line 74 */
16512 
16513 /*******************  Bit definition for EXTI_FPR3 register  ******************/
16514 #define EXTI_FPR3_FPIF66_Pos         (2U)
16515 #define EXTI_FPR3_FPIF66_Msk         (0x1UL << EXTI_FPR3_FPIF66_Pos)           /*!< 0x00000004 */
16516 #define EXTI_FPR3_FPIF66             EXTI_FPR3_FPIF66_Msk                      /*!< Falling Pending Interrupt Flag on line 66 */
16517 #define EXTI_FPR3_FPIF68_Pos         (4U)
16518 #define EXTI_FPR3_FPIF68_Msk         (0x1UL << EXTI_FPR3_FPIF68_Pos)           /*!< 0x00000010 */
16519 #define EXTI_FPR3_FPIF68             EXTI_FPR3_FPIF68_Msk                      /*!< Falling Pending Interrupt Flag on line 68 */
16520 #define EXTI_FPR3_FPIF69_Pos         (5U)
16521 #define EXTI_FPR3_FPIF69_Msk         (0x1UL << EXTI_FPR3_FPIF69_Pos)           /*!< 0x00000020 */
16522 #define EXTI_FPR3_FPIF69             EXTI_FPR3_FPIF69_Msk                      /*!< Falling Pending Interrupt Flag online  69 */
16523 #define EXTI_FPR3_FPIF70_Pos         (6U)
16524 #define EXTI_FPR3_FPIF70_Msk         (0x1UL << EXTI_FPR3_FPIF70_Pos)           /*!< 0x00000040 */
16525 #define EXTI_FPR3_FPIF70             EXTI_FPR3_FPIF70_Msk                      /*!< Falling Pending Interrupt Flag on line 70 */
16526 #define EXTI_FPR3_FPIF71_Pos         (7U)
16527 #define EXTI_FPR3_FPIF71_Msk         (0x1UL << EXTI_FPR3_FPIF71_Pos)           /*!< 0x00000080 */
16528 #define EXTI_FPR3_FPIF71             EXTI_FPR3_FPIF71_Msk                      /*!< Falling Pending Interrupt Flag on line 71 */
16529 #define EXTI_FPR3_FPIF72_Pos         (8U)
16530 #define EXTI_FPR3_FPIF72_Msk         (0x1UL << EXTI_FPR3_FPIF72_Pos)           /*!< 0x00000100 */
16531 #define EXTI_FPR3_FPIF72             EXTI_FPR3_FPIF72_Msk                      /*!< Falling Pending Interrupt Flag on line 72 */
16532 #define EXTI_FPR3_FPIF73_Pos         (9U)
16533 #define EXTI_FPR3_FPIF73_Msk         (0x1UL << EXTI_FPR3_FPIF73_Pos)           /*!< 0x00000200 */
16534 #define EXTI_FPR3_FPIF73             EXTI_FPR3_FPIF73_Msk                      /*!< Falling Pending Interrupt Flag on line 73 */
16535 #define EXTI_FPR3_FPIF74_Pos         (10U)
16536 #define EXTI_FPR3_FPIF74_Msk         (0x1UL << EXTI_FPR3_FPIF74_Pos)           /*!< 0x00000400 */
16537 #define EXTI_FPR3_FPIF74             EXTI_FPR3_FPIF74_Msk                      /*!< Falling Pending Interrupt Flag on line 74 */
16538 
16539 /*******************  Bit definition for EXTI_SECCFGR3 register  ******************/
16540 #define EXTI_SECCFGR3_SEC64_Pos      (0U)
16541 #define EXTI_SECCFGR3_SEC64_Msk      (0x1UL << EXTI_SECCFGR3_SEC64_Pos)        /*!< 0x00000001 */
16542 #define EXTI_SECCFGR3_SEC64          EXTI_SECCFGR3_SEC64_Msk                   /*!< Security enable on line 64 */
16543 #define EXTI_SECCFGR3_SEC65_Pos      (1U)
16544 #define EXTI_SECCFGR3_SEC65_Msk      (0x1UL << EXTI_SECCFGR3_SEC65_Pos)        /*!< 0x00000002 */
16545 #define EXTI_SECCFGR3_SEC65          EXTI_SECCFGR3_SEC65_Msk                   /*!< Security enable on line 65 */
16546 #define EXTI_SECCFGR3_SEC66_Pos      (2U)
16547 #define EXTI_SECCFGR3_SEC66_Msk      (0x1UL << EXTI_SECCFGR3_SEC66_Pos)        /*!< 0x00000004 */
16548 #define EXTI_SECCFGR3_SEC66          EXTI_SECCFGR3_SEC66_Msk                   /*!< Security enable on line 66  */
16549 #define EXTI_SECCFGR3_SEC68_Pos      (4U)
16550 #define EXTI_SECCFGR3_SEC68_Msk      (0x1UL << EXTI_SECCFGR3_SEC68_Pos)        /*!< 0x00000010 */
16551 #define EXTI_SECCFGR3_SEC68          EXTI_SECCFGR3_SEC68_Msk                   /*!< Security enable on line 68 */
16552 #define EXTI_SECCFGR3_SEC69_Pos      (5U)
16553 #define EXTI_SECCFGR3_SEC69_Msk      (0x1UL << EXTI_SECCFGR3_SEC69_Pos)        /*!< 0x00000020 */
16554 #define EXTI_SECCFGR3_SEC69          EXTI_SECCFGR3_SEC69_Msk                   /*!< Security enable on line 69 */
16555 #define EXTI_SECCFGR3_SEC70_Pos      (6U)
16556 #define EXTI_SECCFGR3_SEC70_Msk      (0x1UL << EXTI_SECCFGR3_SEC70_Pos)        /*!< 0x00000040 */
16557 #define EXTI_SECCFGR3_SEC70          EXTI_SECCFGR3_SEC70_Msk                   /*!< Security enable on line 70 */
16558 #define EXTI_SECCFGR3_SEC71_Pos      (7U)
16559 #define EXTI_SECCFGR3_SEC71_Msk      (0x1UL << EXTI_SECCFGR3_SEC71_Pos)        /*!< 0x00000080 */
16560 #define EXTI_SECCFGR3_SEC71          EXTI_SECCFGR3_SEC71_Msk                   /*!< Security enable on line 71 */
16561 #define EXTI_SECCFGR3_SEC72_Pos      (8U)
16562 #define EXTI_SECCFGR3_SEC72_Msk      (0x1UL << EXTI_SECCFGR3_SEC72_Pos)        /*!< 0x00000100 */
16563 #define EXTI_SECCFGR3_SEC72          EXTI_SECCFGR3_SEC72_Msk                   /*!< Security enable on line 72 */
16564 #define EXTI_SECCFGR3_SEC73_Pos      (9U)
16565 #define EXTI_SECCFGR3_SEC73_Msk      (0x1UL << EXTI_SECCFGR3_SEC73_Pos)        /*!< 0x00000200 */
16566 #define EXTI_SECCFGR3_SEC73          EXTI_SECCFGR3_SEC73_Msk                   /*!< Security enable on line 73 */
16567 #define EXTI_SECCFGR3_SEC74_Pos      (10U)
16568 #define EXTI_SECCFGR3_SEC74_Msk      (0x1UL << EXTI_SECCFGR3_SEC74_Pos)        /*!< 0x00000400 */
16569 #define EXTI_SECCFGR3_SEC74          EXTI_SECCFGR3_SEC74_Msk                   /*!< Security enable on line 74 */
16570 #define EXTI_SECCFGR3_SEC77_Pos      (13U)
16571 #define EXTI_SECCFGR3_SEC77_Msk      (0x1UL << EXTI_SECCFGR3_SEC77_Pos)        /*!< 0x00002000 */
16572 #define EXTI_SECCFGR3_SEC77          EXTI_SECCFGR3_SEC77_Msk                   /*!< Security enable on line 77 */
16573 
16574 /*******************  Bit definition for EXTI_PRIVCFGR3 register  ******************/
16575 #define EXTI_PRIVCFGR3_PRIV64_Pos    (0U)
16576 #define EXTI_PRIVCFGR3_PRIV64_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV64_Pos)      /*!< 0x00000001 */
16577 #define EXTI_PRIVCFGR3_PRIV64        EXTI_PRIVCFGR3_PRIV64_Msk                 /*!< Privilege enable on line 64 */
16578 #define EXTI_PRIVCFGR3_PRIV65_Pos    (1U)
16579 #define EXTI_PRIVCFGR3_PRIV65_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV65_Pos)      /*!< 0x00000002 */
16580 #define EXTI_PRIVCFGR3_PRIV65        EXTI_PRIVCFGR3_PRIV65_Msk                 /*!< Privilege enable on line 65 */
16581 #define EXTI_PRIVCFGR3_PRIV66_Pos    (2U)
16582 #define EXTI_PRIVCFGR3_PRIV66_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV66_Pos)      /*!< 0x00000004 */
16583 #define EXTI_PRIVCFGR3_PRIV66        EXTI_PRIVCFGR3_PRIV66_Msk                 /*!< Privilege enable on line 66  */
16584 #define EXTI_PRIVCFGR3_PRIV68_Pos    (4U)
16585 #define EXTI_PRIVCFGR3_PRIV68_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV68_Pos)      /*!< 0x00000010 */
16586 #define EXTI_PRIVCFGR3_PRIV68        EXTI_PRIVCFGR3_PRIV68_Msk                 /*!< Privilege enable on line 68 */
16587 #define EXTI_PRIVCFGR3_PRIV69_Pos    (5U)
16588 #define EXTI_PRIVCFGR3_PRIV69_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV69_Pos)      /*!< 0x00000020 */
16589 #define EXTI_PRIVCFGR3_PRIV69        EXTI_PRIVCFGR3_PRIV69_Msk                 /*!< Privilege enable on line 69 */
16590 #define EXTI_PRIVCFGR3_PRIV70_Pos    (6U)
16591 #define EXTI_PRIVCFGR3_PRIV70_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV70_Pos)      /*!< 0x00000040 */
16592 #define EXTI_PRIVCFGR3_PRIV70        EXTI_PRIVCFGR3_PRIV70_Msk                 /*!< Privilege enable on line 70 */
16593 #define EXTI_PRIVCFGR3_PRIV71_Pos    (7U)
16594 #define EXTI_PRIVCFGR3_PRIV71_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV71_Pos)      /*!< 0x00000080 */
16595 #define EXTI_PRIVCFGR3_PRIV71        EXTI_PRIVCFGR3_PRIV71_Msk                 /*!< Privilege enable on line 71 */
16596 #define EXTI_PRIVCFGR3_PRIV72_Pos    (8U)
16597 #define EXTI_PRIVCFGR3_PRIV72_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV72_Pos)      /*!< 0x00000100 */
16598 #define EXTI_PRIVCFGR3_PRIV72        EXTI_PRIVCFGR3_PRIV72_Msk                 /*!< Privilege enable on line 72 */
16599 #define EXTI_PRIVCFGR3_PRIV73_Pos    (9U)
16600 #define EXTI_PRIVCFGR3_PRIV73_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV73_Pos)      /*!< 0x00000200 */
16601 #define EXTI_PRIVCFGR3_PRIV73        EXTI_PRIVCFGR3_PRIV73_Msk                 /*!< Privilege enable on line 73 */
16602 #define EXTI_PRIVCFGR3_PRIV74_Pos    (10U)
16603 #define EXTI_PRIVCFGR3_PRIV74_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV74_Pos)      /*!< 0x00000400 */
16604 #define EXTI_PRIVCFGR3_PRIV74        EXTI_PRIVCFGR3_PRIV74_Msk                 /*!< Privilege enable on line 74 */
16605 #define EXTI_PRIVCFGR3_PRIV77_Pos    (13U)
16606 #define EXTI_PRIVCFGR3_PRIV77_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV77_Pos)      /*!< 0x00002000 */
16607 #define EXTI_PRIVCFGR3_PRIV77        EXTI_PRIVCFGR3_PRIV77_Msk                 /*!< Privilege enable on line 77 */
16608 
16609 /*****************  Bit definition for EXTI_EXTICR1 register  **************/
16610 #define EXTI_EXTICR1_EXTI0_Pos       (0U)
16611 #define EXTI_EXTICR1_EXTI0_Msk       (0xFFUL << EXTI_EXTICR1_EXTI0_Pos)        /*!< 0x000000FF */
16612 #define EXTI_EXTICR1_EXTI0           EXTI_EXTICR1_EXTI0_Msk                    /*!< EXTI 0 configuration */
16613 #define EXTI_EXTICR1_EXTI0_0         (0x1UL << EXTI_EXTICR1_EXTI0_Pos)         /*!< 0x00000001 */
16614 #define EXTI_EXTICR1_EXTI0_1         (0x2UL << EXTI_EXTICR1_EXTI0_Pos)         /*!< 0x00000002 */
16615 #define EXTI_EXTICR1_EXTI0_2         (0x4UL << EXTI_EXTICR1_EXTI0_Pos)         /*!< 0x00000004 */
16616 #define EXTI_EXTICR1_EXTI0_3         (0x8UL << EXTI_EXTICR1_EXTI0_Pos)         /*!< 0x00000008 */
16617 #define EXTI_EXTICR1_EXTI0_4         (0x10UL << EXTI_EXTICR1_EXTI0_Pos)        /*!< 0x00000010 */
16618 #define EXTI_EXTICR1_EXTI0_5         (0x20UL << EXTI_EXTICR1_EXTI0_Pos)        /*!< 0x00000020 */
16619 #define EXTI_EXTICR1_EXTI0_6         (0x40UL << EXTI_EXTICR1_EXTI0_Pos)        /*!< 0x00000040 */
16620 #define EXTI_EXTICR1_EXTI0_7         (0x80UL << EXTI_EXTICR1_EXTI0_Pos)        /*!< 0x00000080 */
16621 #define EXTI_EXTICR1_EXTI1_Pos       (8U)
16622 #define EXTI_EXTICR1_EXTI1_Msk       (0xFFUL << EXTI_EXTICR1_EXTI1_Pos)        /*!< 0x0000FF00 */
16623 #define EXTI_EXTICR1_EXTI1           EXTI_EXTICR1_EXTI1_Msk                    /*!< EXTI 1 configuration */
16624 #define EXTI_EXTICR1_EXTI1_0         (0x1UL << EXTI_EXTICR1_EXTI1_Pos)         /*!< 0x00000100 */
16625 #define EXTI_EXTICR1_EXTI1_1         (0x2UL << EXTI_EXTICR1_EXTI1_Pos)         /*!< 0x00000200 */
16626 #define EXTI_EXTICR1_EXTI1_2         (0x4UL << EXTI_EXTICR1_EXTI1_Pos)         /*!< 0x00000400 */
16627 #define EXTI_EXTICR1_EXTI1_3         (0x8UL << EXTI_EXTICR1_EXTI1_Pos)         /*!< 0x00000800 */
16628 #define EXTI_EXTICR1_EXTI1_4         (0x10UL << EXTI_EXTICR1_EXTI1_Pos)        /*!< 0x00001000 */
16629 #define EXTI_EXTICR1_EXTI1_5         (0x20UL << EXTI_EXTICR1_EXTI1_Pos)        /*!< 0x00002000 */
16630 #define EXTI_EXTICR1_EXTI1_6         (0x40UL << EXTI_EXTICR1_EXTI1_Pos)        /*!< 0x00004000 */
16631 #define EXTI_EXTICR1_EXTI1_7         (0x80UL << EXTI_EXTICR1_EXTI1_Pos)        /*!< 0x00008000 */
16632 #define EXTI_EXTICR1_EXTI2_Pos       (16U)
16633 #define EXTI_EXTICR1_EXTI2_Msk       (0xFFUL << EXTI_EXTICR1_EXTI2_Pos)        /*!< 0x00FF0000 */
16634 #define EXTI_EXTICR1_EXTI2           EXTI_EXTICR1_EXTI2_Msk                    /*!< EXTI 2 configuration */
16635 #define EXTI_EXTICR1_EXTI2_0         (0x1UL << EXTI_EXTICR1_EXTI2_Pos)         /*!< 0x00010000 */
16636 #define EXTI_EXTICR1_EXTI2_1         (0x2UL << EXTI_EXTICR1_EXTI2_Pos)         /*!< 0x00020000 */
16637 #define EXTI_EXTICR1_EXTI2_2         (0x4UL << EXTI_EXTICR1_EXTI2_Pos)         /*!< 0x00040000 */
16638 #define EXTI_EXTICR1_EXTI2_3         (0x8UL << EXTI_EXTICR1_EXTI2_Pos)         /*!< 0x00080000 */
16639 #define EXTI_EXTICR1_EXTI2_4         (0x10UL << EXTI_EXTICR1_EXTI2_Pos)        /*!< 0x00100000 */
16640 #define EXTI_EXTICR1_EXTI2_5         (0x20UL << EXTI_EXTICR1_EXTI2_Pos)        /*!< 0x00200000 */
16641 #define EXTI_EXTICR1_EXTI2_6         (0x40UL << EXTI_EXTICR1_EXTI2_Pos)        /*!< 0x00400000 */
16642 #define EXTI_EXTICR1_EXTI2_7         (0x80UL << EXTI_EXTICR1_EXTI2_Pos)        /*!< 0x00800000 */
16643 #define EXTI_EXTICR1_EXTI3_Pos       (24U)
16644 #define EXTI_EXTICR1_EXTI3_Msk       (0xFFUL << EXTI_EXTICR1_EXTI3_Pos)        /*!< 0xFF000000 */
16645 #define EXTI_EXTICR1_EXTI3           EXTI_EXTICR1_EXTI3_Msk                    /*!< EXTI 3 configuration */
16646 #define EXTI_EXTICR1_EXTI3_0         (0x1UL << EXTI_EXTICR1_EXTI3_Pos)         /*!< 0x01000000 */
16647 #define EXTI_EXTICR1_EXTI3_1         (0x2UL << EXTI_EXTICR1_EXTI3_Pos)         /*!< 0x02000000 */
16648 #define EXTI_EXTICR1_EXTI3_2         (0x4UL << EXTI_EXTICR1_EXTI3_Pos)         /*!< 0x04000000 */
16649 #define EXTI_EXTICR1_EXTI3_3         (0x8UL << EXTI_EXTICR1_EXTI3_Pos)         /*!< 0x08000000 */
16650 #define EXTI_EXTICR1_EXTI3_4         (0x10UL << EXTI_EXTICR1_EXTI3_Pos)        /*!< 0x10000000 */
16651 #define EXTI_EXTICR1_EXTI3_5         (0x20UL << EXTI_EXTICR1_EXTI3_Pos)        /*!< 0x20000000 */
16652 #define EXTI_EXTICR1_EXTI3_6         (0x40UL << EXTI_EXTICR1_EXTI3_Pos)        /*!< 0x40000000 */
16653 #define EXTI_EXTICR1_EXTI3_7         (0x80UL << EXTI_EXTICR1_EXTI3_Pos)        /*!< 0x80000000 */
16654 
16655 /*****************  Bit definition for EXTI_EXTICR2 register  **************/
16656 #define EXTI_EXTICR2_EXTI4_Pos       (0U)
16657 #define EXTI_EXTICR2_EXTI4_Msk       (0xFFUL << EXTI_EXTICR2_EXTI4_Pos)        /*!< 0x000000FF */
16658 #define EXTI_EXTICR2_EXTI4           EXTI_EXTICR2_EXTI4_Msk                    /*!< EXTI 4 configuration */
16659 #define EXTI_EXTICR2_EXTI4_0         (0x1UL << EXTI_EXTICR2_EXTI4_Pos)         /*!< 0x00000001 */
16660 #define EXTI_EXTICR2_EXTI4_1         (0x2UL << EXTI_EXTICR2_EXTI4_Pos)         /*!< 0x00000002 */
16661 #define EXTI_EXTICR2_EXTI4_2         (0x4UL << EXTI_EXTICR2_EXTI4_Pos)         /*!< 0x00000004 */
16662 #define EXTI_EXTICR2_EXTI4_3         (0x8UL << EXTI_EXTICR2_EXTI4_Pos)         /*!< 0x00000008 */
16663 #define EXTI_EXTICR2_EXTI4_4         (0x10UL << EXTI_EXTICR2_EXTI4_Pos)        /*!< 0x00000010 */
16664 #define EXTI_EXTICR2_EXTI4_5         (0x20UL << EXTI_EXTICR2_EXTI4_Pos)        /*!< 0x00000020 */
16665 #define EXTI_EXTICR2_EXTI4_6         (0x40UL << EXTI_EXTICR2_EXTI4_Pos)        /*!< 0x00000040 */
16666 #define EXTI_EXTICR2_EXTI4_7         (0x80UL << EXTI_EXTICR2_EXTI4_Pos)        /*!< 0x00000080 */
16667 #define EXTI_EXTICR2_EXTI5_Pos       (8U)
16668 #define EXTI_EXTICR2_EXTI5_Msk       (0xFFUL << EXTI_EXTICR2_EXTI5_Pos)        /*!< 0x0000FF00 */
16669 #define EXTI_EXTICR2_EXTI5           EXTI_EXTICR2_EXTI5_Msk                    /*!< EXTI 5 configuration */
16670 #define EXTI_EXTICR2_EXTI5_0         (0x1UL << EXTI_EXTICR2_EXTI5_Pos)         /*!< 0x00000100 */
16671 #define EXTI_EXTICR2_EXTI5_1         (0x2UL << EXTI_EXTICR2_EXTI5_Pos)         /*!< 0x00000200 */
16672 #define EXTI_EXTICR2_EXTI5_2         (0x4UL << EXTI_EXTICR2_EXTI5_Pos)         /*!< 0x00000400 */
16673 #define EXTI_EXTICR2_EXTI5_3         (0x8UL << EXTI_EXTICR2_EXTI5_Pos)         /*!< 0x00000800 */
16674 #define EXTI_EXTICR2_EXTI5_4         (0x10UL << EXTI_EXTICR2_EXTI5_Pos)        /*!< 0x00001000 */
16675 #define EXTI_EXTICR2_EXTI5_5         (0x20UL << EXTI_EXTICR2_EXTI5_Pos)        /*!< 0x00002000 */
16676 #define EXTI_EXTICR2_EXTI5_6         (0x40UL << EXTI_EXTICR2_EXTI5_Pos)        /*!< 0x00004000 */
16677 #define EXTI_EXTICR2_EXTI5_7         (0x80UL << EXTI_EXTICR2_EXTI5_Pos)        /*!< 0x00008000 */
16678 #define EXTI_EXTICR2_EXTI6_Pos       (16U)
16679 #define EXTI_EXTICR2_EXTI6_Msk       (0xFFUL << EXTI_EXTICR2_EXTI6_Pos)        /*!< 0x00FF0000 */
16680 #define EXTI_EXTICR2_EXTI6           EXTI_EXTICR2_EXTI6_Msk                    /*!< EXTI 6 configuration */
16681 #define EXTI_EXTICR2_EXTI6_0         (0x1UL << EXTI_EXTICR2_EXTI6_Pos)         /*!< 0x00010000 */
16682 #define EXTI_EXTICR2_EXTI6_1         (0x2UL << EXTI_EXTICR2_EXTI6_Pos)         /*!< 0x00020000 */
16683 #define EXTI_EXTICR2_EXTI6_2         (0x4UL << EXTI_EXTICR2_EXTI6_Pos)         /*!< 0x00040000 */
16684 #define EXTI_EXTICR2_EXTI6_3         (0x8UL << EXTI_EXTICR2_EXTI6_Pos)         /*!< 0x00080000 */
16685 #define EXTI_EXTICR2_EXTI6_4         (0x10UL << EXTI_EXTICR2_EXTI6_Pos)        /*!< 0x00100000 */
16686 #define EXTI_EXTICR2_EXTI6_5         (0x20UL << EXTI_EXTICR2_EXTI6_Pos)        /*!< 0x00200000 */
16687 #define EXTI_EXTICR2_EXTI6_6         (0x40UL << EXTI_EXTICR2_EXTI6_Pos)        /*!< 0x00400000 */
16688 #define EXTI_EXTICR2_EXTI6_7         (0x80UL << EXTI_EXTICR2_EXTI6_Pos)        /*!< 0x00800000 */
16689 #define EXTI_EXTICR2_EXTI7_Pos       (24U)
16690 #define EXTI_EXTICR2_EXTI7_Msk       (0xFFUL << EXTI_EXTICR2_EXTI7_Pos)        /*!< 0xFF000000 */
16691 #define EXTI_EXTICR2_EXTI7           EXTI_EXTICR2_EXTI7_Msk                    /*!< EXTI 7 configuration */
16692 #define EXTI_EXTICR2_EXTI7_0         (0x1UL << EXTI_EXTICR2_EXTI7_Pos)         /*!< 0x01000000 */
16693 #define EXTI_EXTICR2_EXTI7_1         (0x2UL << EXTI_EXTICR2_EXTI7_Pos)         /*!< 0x02000000 */
16694 #define EXTI_EXTICR2_EXTI7_2         (0x4UL << EXTI_EXTICR2_EXTI7_Pos)         /*!< 0x04000000 */
16695 #define EXTI_EXTICR2_EXTI7_3         (0x8UL << EXTI_EXTICR2_EXTI7_Pos)         /*!< 0x08000000 */
16696 #define EXTI_EXTICR2_EXTI7_4         (0x10UL << EXTI_EXTICR2_EXTI7_Pos)        /*!< 0x10000000 */
16697 #define EXTI_EXTICR2_EXTI7_5         (0x20UL << EXTI_EXTICR2_EXTI7_Pos)        /*!< 0x20000000 */
16698 #define EXTI_EXTICR2_EXTI7_6         (0x40UL << EXTI_EXTICR2_EXTI7_Pos)        /*!< 0x40000000 */
16699 #define EXTI_EXTICR2_EXTI7_7         (0x80UL << EXTI_EXTICR2_EXTI7_Pos)        /*!< 0x80000000 */
16700 
16701 /*****************  Bit definition for EXTI_EXTICR3 register  **************/
16702 #define EXTI_EXTICR3_EXTI8_Pos       (0U)
16703 #define EXTI_EXTICR3_EXTI8_Msk       (0xFFUL << EXTI_EXTICR3_EXTI8_Pos)        /*!< 0x000000FF */
16704 #define EXTI_EXTICR3_EXTI8           EXTI_EXTICR3_EXTI8_Msk                    /*!< EXTI 8 configuration */
16705 #define EXTI_EXTICR3_EXTI8_0         (0x1UL << EXTI_EXTICR3_EXTI8_Pos)         /*!< 0x00000001 */
16706 #define EXTI_EXTICR3_EXTI8_1         (0x2UL << EXTI_EXTICR3_EXTI8_Pos)         /*!< 0x00000002 */
16707 #define EXTI_EXTICR3_EXTI8_2         (0x4UL << EXTI_EXTICR3_EXTI8_Pos)         /*!< 0x00000004 */
16708 #define EXTI_EXTICR3_EXTI8_3         (0x8UL << EXTI_EXTICR3_EXTI8_Pos)         /*!< 0x00000008 */
16709 #define EXTI_EXTICR3_EXTI8_4         (0x10UL << EXTI_EXTICR3_EXTI8_Pos)        /*!< 0x00000010 */
16710 #define EXTI_EXTICR3_EXTI8_5         (0x20UL << EXTI_EXTICR3_EXTI8_Pos)        /*!< 0x00000020 */
16711 #define EXTI_EXTICR3_EXTI8_6         (0x40UL << EXTI_EXTICR3_EXTI8_Pos)        /*!< 0x00000040 */
16712 #define EXTI_EXTICR3_EXTI8_7         (0x80UL << EXTI_EXTICR3_EXTI8_Pos)        /*!< 0x00000080 */
16713 #define EXTI_EXTICR3_EXTI9_Pos       (8U)
16714 #define EXTI_EXTICR3_EXTI9_Msk       (0xFFUL << EXTI_EXTICR3_EXTI9_Pos)        /*!< 0x0000FF00 */
16715 #define EXTI_EXTICR3_EXTI9           EXTI_EXTICR3_EXTI9_Msk                    /*!< EXTI 9 configuration */
16716 #define EXTI_EXTICR3_EXTI9_0         (0x1UL << EXTI_EXTICR3_EXTI9_Pos)         /*!< 0x00000100 */
16717 #define EXTI_EXTICR3_EXTI9_1         (0x2UL << EXTI_EXTICR3_EXTI9_Pos)         /*!< 0x00000200 */
16718 #define EXTI_EXTICR3_EXTI9_2         (0x4UL << EXTI_EXTICR3_EXTI9_Pos)         /*!< 0x00000400 */
16719 #define EXTI_EXTICR3_EXTI9_3         (0x8UL << EXTI_EXTICR3_EXTI9_Pos)         /*!< 0x00000800 */
16720 #define EXTI_EXTICR3_EXTI9_4         (0x10UL << EXTI_EXTICR3_EXTI9_Pos)        /*!< 0x00001000 */
16721 #define EXTI_EXTICR3_EXTI9_5         (0x20UL << EXTI_EXTICR3_EXTI9_Pos)        /*!< 0x00002000 */
16722 #define EXTI_EXTICR3_EXTI9_6         (0x40UL << EXTI_EXTICR3_EXTI9_Pos)        /*!< 0x00004000 */
16723 #define EXTI_EXTICR3_EXTI9_7         (0x80UL << EXTI_EXTICR3_EXTI9_Pos)        /*!< 0x00008000 */
16724 #define EXTI_EXTICR3_EXTI10_Pos      (16U)
16725 #define EXTI_EXTICR3_EXTI10_Msk      (0xFFUL << EXTI_EXTICR3_EXTI10_Pos)       /*!< 0x00FF0000 */
16726 #define EXTI_EXTICR3_EXTI10          EXTI_EXTICR3_EXTI10_Msk                   /*!< EXTI 10 configuration */
16727 #define EXTI_EXTICR3_EXTI10_0        (0x1UL << EXTI_EXTICR3_EXTI10_Pos)        /*!< 0x00010000 */
16728 #define EXTI_EXTICR3_EXTI10_1        (0x2UL << EXTI_EXTICR3_EXTI10_Pos)        /*!< 0x00020000 */
16729 #define EXTI_EXTICR3_EXTI10_2        (0x4UL << EXTI_EXTICR3_EXTI10_Pos)        /*!< 0x00040000 */
16730 #define EXTI_EXTICR3_EXTI10_3        (0x8UL << EXTI_EXTICR3_EXTI10_Pos)        /*!< 0x00080000 */
16731 #define EXTI_EXTICR3_EXTI10_4        (0x10UL << EXTI_EXTICR3_EXTI10_Pos)       /*!< 0x00100000 */
16732 #define EXTI_EXTICR3_EXTI10_5        (0x20UL << EXTI_EXTICR3_EXTI10_Pos)       /*!< 0x00200000 */
16733 #define EXTI_EXTICR3_EXTI10_6        (0x40UL << EXTI_EXTICR3_EXTI10_Pos)       /*!< 0x00400000 */
16734 #define EXTI_EXTICR3_EXTI10_7        (0x80UL << EXTI_EXTICR3_EXTI10_Pos)       /*!< 0x00800000 */
16735 #define EXTI_EXTICR3_EXTI11_Pos      (24U)
16736 #define EXTI_EXTICR3_EXTI11_Msk      (0xFFUL << EXTI_EXTICR3_EXTI11_Pos)       /*!< 0xFF000000 */
16737 #define EXTI_EXTICR3_EXTI11          EXTI_EXTICR3_EXTI11_Msk                   /*!< EXTI 11 configuration */
16738 #define EXTI_EXTICR3_EXTI11_0        (0x1UL << EXTI_EXTICR3_EXTI11_Pos)        /*!< 0x01000000 */
16739 #define EXTI_EXTICR3_EXTI11_1        (0x2UL << EXTI_EXTICR3_EXTI11_Pos)        /*!< 0x02000000 */
16740 #define EXTI_EXTICR3_EXTI11_2        (0x4UL << EXTI_EXTICR3_EXTI11_Pos)        /*!< 0x04000000 */
16741 #define EXTI_EXTICR3_EXTI11_3        (0x8UL << EXTI_EXTICR3_EXTI11_Pos)        /*!< 0x08000000 */
16742 #define EXTI_EXTICR3_EXTI11_4        (0x10UL << EXTI_EXTICR3_EXTI11_Pos)       /*!< 0x10000000 */
16743 #define EXTI_EXTICR3_EXTI11_5        (0x20UL << EXTI_EXTICR3_EXTI11_Pos)       /*!< 0x20000000 */
16744 #define EXTI_EXTICR3_EXTI11_6        (0x40UL << EXTI_EXTICR3_EXTI11_Pos)       /*!< 0x40000000 */
16745 #define EXTI_EXTICR3_EXTI11_7        (0x80UL << EXTI_EXTICR3_EXTI11_Pos)       /*!< 0x80000000 */
16746 
16747 /*****************  Bit definition for EXTI_EXTICR4 register  **************/
16748 #define EXTI_EXTICR4_EXTI12_Pos      (0U)
16749 #define EXTI_EXTICR4_EXTI12_Msk      (0xFFUL << EXTI_EXTICR4_EXTI12_Pos)       /*!< 0x000000FF */
16750 #define EXTI_EXTICR4_EXTI12          EXTI_EXTICR4_EXTI12_Msk                   /*!< EXTI 12 configuration */
16751 #define EXTI_EXTICR4_EXTI12_0        (0x1UL << EXTI_EXTICR4_EXTI12_Pos)        /*!< 0x00000001 */
16752 #define EXTI_EXTICR4_EXTI12_1        (0x2UL << EXTI_EXTICR4_EXTI12_Pos)        /*!< 0x00000002 */
16753 #define EXTI_EXTICR4_EXTI12_2        (0x4UL << EXTI_EXTICR4_EXTI12_Pos)        /*!< 0x00000004 */
16754 #define EXTI_EXTICR4_EXTI12_3        (0x8UL << EXTI_EXTICR4_EXTI12_Pos)        /*!< 0x00000008 */
16755 #define EXTI_EXTICR4_EXTI12_4        (0x10UL << EXTI_EXTICR4_EXTI12_Pos)       /*!< 0x00000010 */
16756 #define EXTI_EXTICR4_EXTI12_5        (0x20UL << EXTI_EXTICR4_EXTI12_Pos)       /*!< 0x00000020 */
16757 #define EXTI_EXTICR4_EXTI12_6        (0x40UL << EXTI_EXTICR4_EXTI12_Pos)       /*!< 0x00000040 */
16758 #define EXTI_EXTICR4_EXTI12_7        (0x80UL << EXTI_EXTICR4_EXTI12_Pos)       /*!< 0x00000080 */
16759 #define EXTI_EXTICR4_EXTI13_Pos      (8U)
16760 #define EXTI_EXTICR4_EXTI13_Msk      (0xFFUL << EXTI_EXTICR4_EXTI13_Pos)       /*!< 0x0000FF00 */
16761 #define EXTI_EXTICR4_EXTI13          EXTI_EXTICR4_EXTI13_Msk                   /*!< EXTI 13 configuration */
16762 #define EXTI_EXTICR4_EXTI13_0        (0x1UL << EXTI_EXTICR4_EXTI13_Pos)        /*!< 0x00000100 */
16763 #define EXTI_EXTICR4_EXTI13_1        (0x2UL << EXTI_EXTICR4_EXTI13_Pos)        /*!< 0x00000200 */
16764 #define EXTI_EXTICR4_EXTI13_2        (0x4UL << EXTI_EXTICR4_EXTI13_Pos)        /*!< 0x00000400 */
16765 #define EXTI_EXTICR4_EXTI13_3        (0x8UL << EXTI_EXTICR4_EXTI13_Pos)        /*!< 0x00000800 */
16766 #define EXTI_EXTICR4_EXTI13_4        (0x10UL << EXTI_EXTICR4_EXTI13_Pos)       /*!< 0x00001000 */
16767 #define EXTI_EXTICR4_EXTI13_5        (0x20UL << EXTI_EXTICR4_EXTI13_Pos)       /*!< 0x00002000 */
16768 #define EXTI_EXTICR4_EXTI13_6        (0x40UL << EXTI_EXTICR4_EXTI13_Pos)       /*!< 0x00004000 */
16769 #define EXTI_EXTICR4_EXTI13_7        (0x80UL << EXTI_EXTICR4_EXTI13_Pos)       /*!< 0x00008000 */
16770 #define EXTI_EXTICR4_EXTI14_Pos      (16U)
16771 #define EXTI_EXTICR4_EXTI14_Msk      (0xFFUL << EXTI_EXTICR4_EXTI14_Pos)       /*!< 0x00FF0000 */
16772 #define EXTI_EXTICR4_EXTI14          EXTI_EXTICR4_EXTI14_Msk                   /*!< EXTI 14 configuration */
16773 #define EXTI_EXTICR4_EXTI14_0        (0x1UL << EXTI_EXTICR4_EXTI14_Pos)        /*!< 0x00010000 */
16774 #define EXTI_EXTICR4_EXTI14_1        (0x2UL << EXTI_EXTICR4_EXTI14_Pos)        /*!< 0x00020000 */
16775 #define EXTI_EXTICR4_EXTI14_2        (0x4UL << EXTI_EXTICR4_EXTI14_Pos)        /*!< 0x00040000 */
16776 #define EXTI_EXTICR4_EXTI14_3        (0x8UL << EXTI_EXTICR4_EXTI14_Pos)        /*!< 0x00080000 */
16777 #define EXTI_EXTICR4_EXTI14_4        (0x10UL << EXTI_EXTICR4_EXTI14_Pos)       /*!< 0x00100000 */
16778 #define EXTI_EXTICR4_EXTI14_5        (0x20UL << EXTI_EXTICR4_EXTI14_Pos)       /*!< 0x00200000 */
16779 #define EXTI_EXTICR4_EXTI14_6        (0x40UL << EXTI_EXTICR4_EXTI14_Pos)       /*!< 0x00400000 */
16780 #define EXTI_EXTICR4_EXTI14_7        (0x80UL << EXTI_EXTICR4_EXTI14_Pos)       /*!< 0x00800000 */
16781 #define EXTI_EXTICR4_EXTI15_Pos      (24U)
16782 #define EXTI_EXTICR4_EXTI15_Msk      (0xFFUL << EXTI_EXTICR4_EXTI15_Pos)       /*!< 0xFF000000 */
16783 #define EXTI_EXTICR4_EXTI15          EXTI_EXTICR4_EXTI15_Msk                   /*!< EXTI 15 configuration */
16784 #define EXTI_EXTICR4_EXTI15_0        (0x1UL << EXTI_EXTICR4_EXTI15_Pos)        /*!< 0x01000000 */
16785 #define EXTI_EXTICR4_EXTI15_1        (0x2UL << EXTI_EXTICR4_EXTI15_Pos)        /*!< 0x02000000 */
16786 #define EXTI_EXTICR4_EXTI15_2        (0x4UL << EXTI_EXTICR4_EXTI15_Pos)        /*!< 0x04000000 */
16787 #define EXTI_EXTICR4_EXTI15_3        (0x8UL << EXTI_EXTICR4_EXTI15_Pos)        /*!< 0x08000000 */
16788 #define EXTI_EXTICR4_EXTI15_4        (0x10UL << EXTI_EXTICR4_EXTI15_Pos)       /*!< 0x10000000 */
16789 #define EXTI_EXTICR4_EXTI15_5        (0x20UL << EXTI_EXTICR4_EXTI15_Pos)       /*!< 0x20000000 */
16790 #define EXTI_EXTICR4_EXTI15_6        (0x40UL << EXTI_EXTICR4_EXTI15_Pos)       /*!< 0x40000000 */
16791 #define EXTI_EXTICR4_EXTI15_7        (0x80UL << EXTI_EXTICR4_EXTI15_Pos)       /*!< 0x80000000 */
16792 
16793 /*******************  Bit definition I_LOCKR register  ******************/
16794 #define EXTI_LOCKR_LOCK_Pos          (0U)
16795 #define EXTI_LOCKR_LOCK_Msk          (0x1UL << EXTI_LOCKR_LOCK_Pos)            /*!< 0x00000001 */
16796 #define EXTI_LOCKR_LOCK              EXTI_LOCKR_LOCK_Msk                       /*!< Security and privilege configuration lock */
16797 
16798 /*******************  Bit definition for EXTI_IMR1 register  ******************/
16799 #define EXTI_IMR1_IM0_Pos            (0U)
16800 #define EXTI_IMR1_IM0_Msk            (0x1UL << EXTI_IMR1_IM0_Pos)              /*!< 0x00000001 */
16801 #define EXTI_IMR1_IM0                EXTI_IMR1_IM0_Msk                         /*!< Interrupt Mask on line 0 */
16802 #define EXTI_IMR1_IM1_Pos            (1U)
16803 #define EXTI_IMR1_IM1_Msk            (0x1UL << EXTI_IMR1_IM1_Pos)              /*!< 0x00000002 */
16804 #define EXTI_IMR1_IM1                EXTI_IMR1_IM1_Msk                         /*!< Interrupt Mask on line 1 */
16805 #define EXTI_IMR1_IM2_Pos            (2U)
16806 #define EXTI_IMR1_IM2_Msk            (0x1UL << EXTI_IMR1_IM2_Pos)              /*!< 0x00000004 */
16807 #define EXTI_IMR1_IM2                EXTI_IMR1_IM2_Msk                         /*!< Interrupt Mask on line 2 */
16808 #define EXTI_IMR1_IM3_Pos            (3U)
16809 #define EXTI_IMR1_IM3_Msk            (0x1UL << EXTI_IMR1_IM3_Pos)              /*!< 0x00000008 */
16810 #define EXTI_IMR1_IM3                EXTI_IMR1_IM3_Msk                         /*!< Interrupt Mask on line 3 */
16811 #define EXTI_IMR1_IM4_Pos            (4U)
16812 #define EXTI_IMR1_IM4_Msk            (0x1UL << EXTI_IMR1_IM4_Pos)              /*!< 0x00000010 */
16813 #define EXTI_IMR1_IM4                EXTI_IMR1_IM4_Msk                         /*!< Interrupt Mask on line 4 */
16814 #define EXTI_IMR1_IM5_Pos            (5U)
16815 #define EXTI_IMR1_IM5_Msk            (0x1UL << EXTI_IMR1_IM5_Pos)              /*!< 0x00000020 */
16816 #define EXTI_IMR1_IM5                EXTI_IMR1_IM5_Msk                         /*!< Interrupt Mask on line 5 */
16817 #define EXTI_IMR1_IM6_Pos            (6U)
16818 #define EXTI_IMR1_IM6_Msk            (0x1UL << EXTI_IMR1_IM6_Pos)              /*!< 0x00000040 */
16819 #define EXTI_IMR1_IM6                EXTI_IMR1_IM6_Msk                         /*!< Interrupt Mask on line 6 */
16820 #define EXTI_IMR1_IM7_Pos            (7U)
16821 #define EXTI_IMR1_IM7_Msk            (0x1UL << EXTI_IMR1_IM7_Pos)              /*!< 0x00000080 */
16822 #define EXTI_IMR1_IM7                EXTI_IMR1_IM7_Msk                         /*!< Interrupt Mask on line 7 */
16823 #define EXTI_IMR1_IM8_Pos            (8U)
16824 #define EXTI_IMR1_IM8_Msk            (0x1UL << EXTI_IMR1_IM8_Pos)              /*!< 0x00000100 */
16825 #define EXTI_IMR1_IM8                EXTI_IMR1_IM8_Msk                         /*!< Interrupt Mask on line 8 */
16826 #define EXTI_IMR1_IM9_Pos            (9U)
16827 #define EXTI_IMR1_IM9_Msk            (0x1UL << EXTI_IMR1_IM9_Pos)              /*!< 0x00000200 */
16828 #define EXTI_IMR1_IM9                EXTI_IMR1_IM9_Msk                         /*!< Interrupt Mask on line 9 */
16829 #define EXTI_IMR1_IM10_Pos           (10U)
16830 #define EXTI_IMR1_IM10_Msk           (0x1UL << EXTI_IMR1_IM10_Pos)             /*!< 0x00000400 */
16831 #define EXTI_IMR1_IM10               EXTI_IMR1_IM10_Msk                        /*!< Interrupt Mask on line 10 */
16832 #define EXTI_IMR1_IM11_Pos           (11U)
16833 #define EXTI_IMR1_IM11_Msk           (0x1UL << EXTI_IMR1_IM11_Pos)             /*!< 0x00000800 */
16834 #define EXTI_IMR1_IM11               EXTI_IMR1_IM11_Msk                        /*!< Interrupt Mask on line 11 */
16835 #define EXTI_IMR1_IM12_Pos           (12U)
16836 #define EXTI_IMR1_IM12_Msk           (0x1UL << EXTI_IMR1_IM12_Pos)             /*!< 0x00001000 */
16837 #define EXTI_IMR1_IM12               EXTI_IMR1_IM12_Msk                        /*!< Interrupt Mask on line 12 */
16838 #define EXTI_IMR1_IM13_Pos           (13U)
16839 #define EXTI_IMR1_IM13_Msk           (0x1UL << EXTI_IMR1_IM13_Pos)             /*!< 0x00002000 */
16840 #define EXTI_IMR1_IM13               EXTI_IMR1_IM13_Msk                        /*!< Interrupt Mask on line 13 */
16841 #define EXTI_IMR1_IM14_Pos           (14U)
16842 #define EXTI_IMR1_IM14_Msk           (0x1UL << EXTI_IMR1_IM14_Pos)             /*!< 0x00004000 */
16843 #define EXTI_IMR1_IM14               EXTI_IMR1_IM14_Msk                        /*!< Interrupt Mask on line 14 */
16844 #define EXTI_IMR1_IM15_Pos           (15U)
16845 #define EXTI_IMR1_IM15_Msk           (0x1UL << EXTI_IMR1_IM15_Pos)             /*!< 0x00008000 */
16846 #define EXTI_IMR1_IM15               EXTI_IMR1_IM15_Msk                        /*!< Interrupt Mask on line 15 */
16847 #define EXTI_IMR1_IM17_Pos           (17U)
16848 #define EXTI_IMR1_IM17_Msk           (0x1UL << EXTI_IMR1_IM17_Pos)             /*!< 0x00020000 */
16849 #define EXTI_IMR1_IM17               EXTI_IMR1_IM17_Msk                        /*!< Interrupt Mask on line 17 */
16850 #define EXTI_IMR1_IM18_Pos           (18U)
16851 #define EXTI_IMR1_IM18_Msk           (0x1UL << EXTI_IMR1_IM18_Pos)             /*!< 0x00040000 */
16852 #define EXTI_IMR1_IM18               EXTI_IMR1_IM18_Msk                        /*!< Interrupt Mask on line 18 */
16853 #define EXTI_IMR1_IM19_Pos           (19U)
16854 #define EXTI_IMR1_IM19_Msk           (0x1UL << EXTI_IMR1_IM19_Pos)             /*!< 0x00080000 */
16855 #define EXTI_IMR1_IM19               EXTI_IMR1_IM19_Msk                        /*!< Interrupt Mask on line 19 */
16856 #define EXTI_IMR1_IM20_Pos           (20U)
16857 #define EXTI_IMR1_IM20_Msk           (0x1UL << EXTI_IMR1_IM20_Pos)             /*!< 0x00100000 */
16858 #define EXTI_IMR1_IM20               EXTI_IMR1_IM20_Msk                        /*!< Interrupt Mask on line 20 */
16859 #define EXTI_IMR1_IM21_Pos           (21U)
16860 #define EXTI_IMR1_IM21_Msk           (0x1UL << EXTI_IMR1_IM21_Pos)             /*!< 0x00200000 */
16861 #define EXTI_IMR1_IM21               EXTI_IMR1_IM21_Msk                        /*!< Interrupt Mask on line 21 */
16862 #define EXTI_IMR1_IM22_Pos           (22U)
16863 #define EXTI_IMR1_IM22_Msk           (0x1UL << EXTI_IMR1_IM22_Pos)             /*!< 0x00400000 */
16864 #define EXTI_IMR1_IM22               EXTI_IMR1_IM22_Msk                        /*!< Interrupt Mask on line 22 */
16865 #define EXTI_IMR1_IM23_Pos           (23U)
16866 #define EXTI_IMR1_IM23_Msk           (0x1UL << EXTI_IMR1_IM23_Pos)             /*!< 0x00800000 */
16867 #define EXTI_IMR1_IM23               EXTI_IMR1_IM23_Msk                        /*!< Interrupt Mask on line 23 */
16868 #define EXTI_IMR1_IM24_Pos           (24U)
16869 #define EXTI_IMR1_IM24_Msk           (0x1UL << EXTI_IMR1_IM24_Pos)             /*!< 0x01000000 */
16870 #define EXTI_IMR1_IM24               EXTI_IMR1_IM24_Msk                        /*!< Interrupt Mask on line 24 */
16871 #define EXTI_IMR1_IM25_Pos           (25U)
16872 #define EXTI_IMR1_IM25_Msk           (0x1UL << EXTI_IMR1_IM25_Pos)             /*!< 0x02000000 */
16873 #define EXTI_IMR1_IM25               EXTI_IMR1_IM25_Msk                        /*!< Interrupt Mask on line 25 */
16874 #define EXTI_IMR1_IM26_Pos           (26U)
16875 #define EXTI_IMR1_IM26_Msk           (0x1UL << EXTI_IMR1_IM26_Pos)             /*!< 0x04000000 */
16876 #define EXTI_IMR1_IM26               EXTI_IMR1_IM26_Msk                        /*!< Interrupt Mask on line 26 */
16877 #define EXTI_IMR1_IM27_Pos           (27U)
16878 #define EXTI_IMR1_IM27_Msk           (0x1UL << EXTI_IMR1_IM27_Pos)             /*!< 0x08000000 */
16879 #define EXTI_IMR1_IM27               EXTI_IMR1_IM27_Msk                        /*!< Interrupt Mask on line 27 */
16880 #define EXTI_IMR1_IM28_Pos           (28U)
16881 #define EXTI_IMR1_IM28_Msk           (0x1UL << EXTI_IMR1_IM28_Pos)             /*!< 0x10000000 */
16882 #define EXTI_IMR1_IM28               EXTI_IMR1_IM28_Msk                        /*!< Interrupt Mask on line 28 */
16883 #define EXTI_IMR1_IM29_Pos           (29U)
16884 #define EXTI_IMR1_IM29_Msk           (0x1UL << EXTI_IMR1_IM29_Pos)             /*!< 0x20000000 */
16885 #define EXTI_IMR1_IM29               EXTI_IMR1_IM29_Msk                        /*!< Interrupt Mask on line 29 */
16886 #define EXTI_IMR1_IM30_Pos           (30U)
16887 #define EXTI_IMR1_IM30_Msk           (0x1UL << EXTI_IMR1_IM30_Pos)             /*!< 0x40000000 */
16888 #define EXTI_IMR1_IM30               EXTI_IMR1_IM30_Msk                        /*!< Interrupt Mask on line 30 */
16889 #define EXTI_IMR1_IM31_Pos           (31U)
16890 #define EXTI_IMR1_IM31_Msk           (0x1UL << EXTI_IMR1_IM31_Pos)             /*!< 0x80000000 */
16891 #define EXTI_IMR1_IM31               EXTI_IMR1_IM31_Msk                        /*!< Interrupt Mask on line 31 */
16892 #define EXTI_IMR1_IM_Pos             (0U)
16893 #define EXTI_IMR1_IM_Msk             (0xFFFEFFFFUL << EXTI_IMR1_IM_Pos)        /*!< 0xFFFEFFFF */
16894 #define EXTI_IMR1_IM                 EXTI_IMR1_IM_Msk                          /*!< Interrupt Mask All */
16895 
16896 /*******************  Bit definition for EXTI_EMR1 register  ******************/
16897 #define EXTI_EMR1_EM0_Pos            (0U)
16898 #define EXTI_EMR1_EM0_Msk            (0x1UL << EXTI_EMR1_EM0_Pos)              /*!< 0x00000001 */
16899 #define EXTI_EMR1_EM0                EXTI_EMR1_EM0_Msk                         /*!< Event Mask on line 0 */
16900 #define EXTI_EMR1_EM1_Pos            (1U)
16901 #define EXTI_EMR1_EM1_Msk            (0x1UL << EXTI_EMR1_EM1_Pos)              /*!< 0x00000002 */
16902 #define EXTI_EMR1_EM1                EXTI_EMR1_EM1_Msk                         /*!< Event Mask on line 1 */
16903 #define EXTI_EMR1_EM2_Pos            (2U)
16904 #define EXTI_EMR1_EM2_Msk            (0x1UL << EXTI_EMR1_EM2_Pos)              /*!< 0x00000004 */
16905 #define EXTI_EMR1_EM2                EXTI_EMR1_EM2_Msk                         /*!< Event Mask on line 2 */
16906 #define EXTI_EMR1_EM3_Pos            (3U)
16907 #define EXTI_EMR1_EM3_Msk            (0x1UL << EXTI_EMR1_EM3_Pos)              /*!< 0x00000008 */
16908 #define EXTI_EMR1_EM3                EXTI_EMR1_EM3_Msk                         /*!< Event Mask on line 3 */
16909 #define EXTI_EMR1_EM4_Pos            (4U)
16910 #define EXTI_EMR1_EM4_Msk            (0x1UL << EXTI_EMR1_EM4_Pos)              /*!< 0x00000010 */
16911 #define EXTI_EMR1_EM4                EXTI_EMR1_EM4_Msk                         /*!< Event Mask on line 4 */
16912 #define EXTI_EMR1_EM5_Pos            (5U)
16913 #define EXTI_EMR1_EM5_Msk            (0x1UL << EXTI_EMR1_EM5_Pos)              /*!< 0x00000020 */
16914 #define EXTI_EMR1_EM5                EXTI_EMR1_EM5_Msk                         /*!< Event Mask on line 5 */
16915 #define EXTI_EMR1_EM6_Pos            (6U)
16916 #define EXTI_EMR1_EM6_Msk            (0x1UL << EXTI_EMR1_EM6_Pos)              /*!< 0x00000040 */
16917 #define EXTI_EMR1_EM6                EXTI_EMR1_EM6_Msk                         /*!< Event Mask on line 6 */
16918 #define EXTI_EMR1_EM7_Pos            (7U)
16919 #define EXTI_EMR1_EM7_Msk            (0x1UL << EXTI_EMR1_EM7_Pos)              /*!< 0x00000080 */
16920 #define EXTI_EMR1_EM7                EXTI_EMR1_EM7_Msk                         /*!< Event Mask on line 7 */
16921 #define EXTI_EMR1_EM8_Pos            (8U)
16922 #define EXTI_EMR1_EM8_Msk            (0x1UL << EXTI_EMR1_EM8_Pos)              /*!< 0x00000100 */
16923 #define EXTI_EMR1_EM8                EXTI_EMR1_EM8_Msk                         /*!< Event Mask on line 8 */
16924 #define EXTI_EMR1_EM9_Pos            (9U)
16925 #define EXTI_EMR1_EM9_Msk            (0x1UL << EXTI_EMR1_EM9_Pos)              /*!< 0x00000200 */
16926 #define EXTI_EMR1_EM9                EXTI_EMR1_EM9_Msk                         /*!< Event Mask on line 9 */
16927 #define EXTI_EMR1_EM10_Pos           (10U)
16928 #define EXTI_EMR1_EM10_Msk           (0x1UL << EXTI_EMR1_EM10_Pos)             /*!< 0x00000400 */
16929 #define EXTI_EMR1_EM10               EXTI_EMR1_EM10_Msk                        /*!< Event Mask on line 10 */
16930 #define EXTI_EMR1_EM11_Pos           (11U)
16931 #define EXTI_EMR1_EM11_Msk           (0x1UL << EXTI_EMR1_EM11_Pos)             /*!< 0x00000800 */
16932 #define EXTI_EMR1_EM11               EXTI_EMR1_EM11_Msk                        /*!< Event Mask on line 11 */
16933 #define EXTI_EMR1_EM12_Pos           (12U)
16934 #define EXTI_EMR1_EM12_Msk           (0x1UL << EXTI_EMR1_EM12_Pos)             /*!< 0x00001000 */
16935 #define EXTI_EMR1_EM12               EXTI_EMR1_EM12_Msk                        /*!< Event Mask on line 12 */
16936 #define EXTI_EMR1_EM13_Pos           (13U)
16937 #define EXTI_EMR1_EM13_Msk           (0x1UL << EXTI_EMR1_EM13_Pos)             /*!< 0x00002000 */
16938 #define EXTI_EMR1_EM13               EXTI_EMR1_EM13_Msk                        /*!< Event Mask on line 13 */
16939 #define EXTI_EMR1_EM14_Pos           (14U)
16940 #define EXTI_EMR1_EM14_Msk           (0x1UL << EXTI_EMR1_EM14_Pos)             /*!< 0x00004000 */
16941 #define EXTI_EMR1_EM14               EXTI_EMR1_EM14_Msk                        /*!< Event Mask on line 14 */
16942 #define EXTI_EMR1_EM15_Pos           (15U)
16943 #define EXTI_EMR1_EM15_Msk           (0x1UL << EXTI_EMR1_EM15_Pos)             /*!< 0x00008000 */
16944 #define EXTI_EMR1_EM15               EXTI_EMR1_EM15_Msk                        /*!< Event Mask on line 15 */
16945 #define EXTI_EMR1_EM17_Pos           (17U)
16946 #define EXTI_EMR1_EM17_Msk           (0x1UL << EXTI_EMR1_EM17_Pos)             /*!< 0x00020000 */
16947 #define EXTI_EMR1_EM17               EXTI_EMR1_EM17_Msk                        /*!< Event Mask on line 17 */
16948 #define EXTI_EMR1_EM18_Pos           (18U)
16949 #define EXTI_EMR1_EM18_Msk           (0x1UL << EXTI_EMR1_EM18_Pos)             /*!< 0x00040000 */
16950 #define EXTI_EMR1_EM18               EXTI_EMR1_EM18_Msk                        /*!< Event Mask on line 18 */
16951 #define EXTI_EMR1_EM19_Pos           (19U)
16952 #define EXTI_EMR1_EM19_Msk           (0x1UL << EXTI_EMR1_EM19_Pos)             /*!< 0x00080000 */
16953 #define EXTI_EMR1_EM19               EXTI_EMR1_EM19_Msk                        /*!< Event Mask on line 19 */
16954 #define EXTI_EMR1_EM20_Pos           (20U)
16955 #define EXTI_EMR1_EM20_Msk           (0x1UL << EXTI_EMR1_EM20_Pos)             /*!< 0x00100000 */
16956 #define EXTI_EMR1_EM20               EXTI_EMR1_EM20_Msk                        /*!< Event Mask on line 20 */
16957 #define EXTI_EMR1_EM21_Pos           (21U)
16958 #define EXTI_EMR1_EM21_Msk           (0x1UL << EXTI_EMR1_EM21_Pos)             /*!< 0x00200000 */
16959 #define EXTI_EMR1_EM21               EXTI_EMR1_EM21_Msk                        /*!< Event Mask on line 21 */
16960 #define EXTI_EMR1_EM22_Pos           (22U)
16961 #define EXTI_EMR1_EM22_Msk           (0x1UL << EXTI_EMR1_EM22_Pos)             /*!< 0x00400000 */
16962 #define EXTI_EMR1_EM22               EXTI_EMR1_EM22_Msk                        /*!< Event Mask on line 22 */
16963 #define EXTI_EMR1_EM23_Pos           (23U)
16964 #define EXTI_EMR1_EM23_Msk           (0x1UL << EXTI_EMR1_EM23_Pos)             /*!< 0x00800000 */
16965 #define EXTI_EMR1_EM23               EXTI_EMR1_EM23_Msk                        /*!< Event Mask on line 23 */
16966 #define EXTI_EMR1_EM24_Pos           (24U)
16967 #define EXTI_EMR1_EM24_Msk           (0x1UL << EXTI_EMR1_EM24_Pos)             /*!< 0x01000000 */
16968 #define EXTI_EMR1_EM24               EXTI_EMR1_EM24_Msk                        /*!< Event Mask on line 24 */
16969 #define EXTI_EMR1_EM25_Pos           (25U)
16970 #define EXTI_EMR1_EM25_Msk           (0x1UL << EXTI_EMR1_EM25_Pos)             /*!< 0x02000000 */
16971 #define EXTI_EMR1_EM25               EXTI_EMR1_EM25_Msk                        /*!< Event Mask on line 25 */
16972 #define EXTI_EMR1_EM26_Pos           (26U)
16973 #define EXTI_EMR1_EM26_Msk           (0x1UL << EXTI_EMR1_EM26_Pos)             /*!< 0x04000000 */
16974 #define EXTI_EMR1_EM26               EXTI_EMR1_EM26_Msk                        /*!< Event Mask on line 26 */
16975 #define EXTI_EMR1_EM27_Pos           (27U)
16976 #define EXTI_EMR1_EM27_Msk           (0x1UL << EXTI_EMR1_EM27_Pos)             /*!< 0x08000000 */
16977 #define EXTI_EMR1_EM27               EXTI_EMR1_EM27_Msk                        /*!< Event Mask on line 27 */
16978 #define EXTI_EMR1_EM28_Pos           (28U)
16979 #define EXTI_EMR1_EM28_Msk           (0x1UL << EXTI_EMR1_EM28_Pos)             /*!< 0x10000000 */
16980 #define EXTI_EMR1_EM28               EXTI_EMR1_EM28_Msk                        /*!< Event Mask on line 28 */
16981 #define EXTI_EMR1_EM29_Pos           (29U)
16982 #define EXTI_EMR1_EM29_Msk           (0x1UL << EXTI_EMR1_EM29_Pos)             /*!< 0x20000000 */
16983 #define EXTI_EMR1_EM29               EXTI_EMR1_EM29_Msk                        /*!< Event Mask on line 29 */
16984 #define EXTI_EMR1_EM30_Pos           (30U)
16985 #define EXTI_EMR1_EM30_Msk           (0x1UL << EXTI_EMR1_EM30_Pos)             /*!< 0x40000000 */
16986 #define EXTI_EMR1_EM30               EXTI_EMR1_EM30_Msk                        /*!< Event Mask on line 30 */
16987 #define EXTI_EMR1_EM31_Pos           (31U)
16988 #define EXTI_EMR1_EM31_Msk           (0x1UL << EXTI_EMR1_EM31_Pos)             /*!< 0x80000000 */
16989 #define EXTI_EMR1_EM31               EXTI_EMR1_EM31_Msk                        /*!< Event Mask on line 31 */
16990 #define EXTI_EMR1_EM_Pos             (0U)
16991 #define EXTI_EMR1_EM_Msk             (0xFFFEFFFFUL << EXTI_EMR1_EM_Pos)        /*!< 0xFFFEFFFF */
16992 #define EXTI_EMR1_EM                 EXTI_EMR1_EM_Msk                          /*!< Event Mask All */
16993 
16994 /*******************  Bit definition for EXTI_IMR2 register  ******************/
16995 #define EXTI_IMR2_IM32_Pos           (0U)
16996 #define EXTI_IMR2_IM32_Msk           (0x1UL << EXTI_IMR2_IM32_Pos)             /*!< 0x00000001 */
16997 #define EXTI_IMR2_IM32               EXTI_IMR2_IM32_Msk                        /*!< Interrupt Mask on line 32 */
16998 #define EXTI_IMR2_IM33_Pos           (1U)
16999 #define EXTI_IMR2_IM33_Msk           (0x1UL << EXTI_IMR2_IM33_Pos)             /*!< 0x00000002 */
17000 #define EXTI_IMR2_IM33               EXTI_IMR2_IM33_Msk                        /*!< Interrupt Mask on line 33 */
17001 #define EXTI_IMR2_IM34_Pos           (2U)
17002 #define EXTI_IMR2_IM34_Msk           (0x1UL << EXTI_IMR2_IM34_Pos)             /*!< 0x00000004 */
17003 #define EXTI_IMR2_IM34               EXTI_IMR2_IM34_Msk                        /*!< Interrupt Mask on line 34 */
17004 #define EXTI_IMR2_IM35_Pos           (3U)
17005 #define EXTI_IMR2_IM35_Msk           (0x1UL << EXTI_IMR2_IM35_Pos)             /*!< 0x00000008 */
17006 #define EXTI_IMR2_IM35               EXTI_IMR2_IM35_Msk                        /*!< Interrupt Mask on line 35 */
17007 #define EXTI_IMR2_IM36_Pos           (4U)
17008 #define EXTI_IMR2_IM36_Msk           (0x1UL << EXTI_IMR2_IM36_Pos)             /*!< 0x00000010 */
17009 #define EXTI_IMR2_IM36               EXTI_IMR2_IM36_Msk                        /*!< Interrupt Mask on line 36 */
17010 #define EXTI_IMR2_IM37_Pos           (5U)
17011 #define EXTI_IMR2_IM37_Msk           (0x1UL << EXTI_IMR2_IM37_Pos)             /*!< 0x00000020 */
17012 #define EXTI_IMR2_IM37               EXTI_IMR2_IM37_Msk                        /*!< Interrupt Mask on line 37 */
17013 #define EXTI_IMR2_IM38_Pos           (6U)
17014 #define EXTI_IMR2_IM38_Msk           (0x1UL << EXTI_IMR2_IM38_Pos)             /*!< 0x00000040 */
17015 #define EXTI_IMR2_IM38               EXTI_IMR2_IM38_Msk                        /*!< Interrupt Mask on line 38 */
17016 #define EXTI_IMR2_IM39_Pos           (7U)
17017 #define EXTI_IMR2_IM39_Msk           (0x1UL << EXTI_IMR2_IM39_Pos)             /*!< 0x00000080 */
17018 #define EXTI_IMR2_IM39               EXTI_IMR2_IM39_Msk                        /*!< Interrupt Mask on line 39 */
17019 #define EXTI_IMR2_IM40_Pos           (8U)
17020 #define EXTI_IMR2_IM40_Msk           (0x1UL << EXTI_IMR2_IM40_Pos)             /*!< 0x00000100 */
17021 #define EXTI_IMR2_IM40               EXTI_IMR2_IM40_Msk                        /*!< Interrupt Mask on line 40 */
17022 #define EXTI_IMR2_IM41_Pos           (9U)
17023 #define EXTI_IMR2_IM41_Msk           (0x1UL << EXTI_IMR2_IM41_Pos)             /*!< 0x00000200 */
17024 #define EXTI_IMR2_IM41               EXTI_IMR2_IM41_Msk                        /*!< Interrupt Mask on line 41 */
17025 #define EXTI_IMR2_IM42_Pos           (10U)
17026 #define EXTI_IMR2_IM42_Msk           (0x1UL << EXTI_IMR2_IM42_Pos)             /*!< 0x00000400 */
17027 #define EXTI_IMR2_IM42               EXTI_IMR2_IM42_Msk                        /*!< Interrupt Mask on line 42 */
17028 #define EXTI_IMR2_IM43_Pos           (11U)
17029 #define EXTI_IMR2_IM43_Msk           (0x1UL << EXTI_IMR2_IM43_Pos)             /*!< 0x00000800 */
17030 #define EXTI_IMR2_IM43               EXTI_IMR2_IM43_Msk                        /*!< Interrupt Mask on line 43 */
17031 #define EXTI_IMR2_IM44_Pos           (12U)
17032 #define EXTI_IMR2_IM44_Msk           (0x1UL << EXTI_IMR2_IM44_Pos)             /*!< 0x00001000 */
17033 #define EXTI_IMR2_IM44               EXTI_IMR2_IM44_Msk                        /*!< Interrupt Mask on line 44 */
17034 #define EXTI_IMR2_IM45_Pos           (13U)
17035 #define EXTI_IMR2_IM45_Msk           (0x1UL << EXTI_IMR2_IM45_Pos)             /*!< 0x00002000 */
17036 #define EXTI_IMR2_IM45               EXTI_IMR2_IM45_Msk                        /*!< Interrupt Mask on line 45 */
17037 #define EXTI_IMR2_IM46_Pos           (14U)
17038 #define EXTI_IMR2_IM46_Msk           (0x1UL << EXTI_IMR2_IM46_Pos)             /*!< 0x00004000 */
17039 #define EXTI_IMR2_IM46               EXTI_IMR2_IM46_Msk                        /*!< Interrupt Mask on line 46 */
17040 #define EXTI_IMR2_IM47_Pos           (15U)
17041 #define EXTI_IMR2_IM47_Msk           (0x1UL << EXTI_IMR2_IM47_Pos)             /*!< 0x00008000 */
17042 #define EXTI_IMR2_IM47               EXTI_IMR2_IM47_Msk                        /*!< Interrupt Mask on line 47 */
17043 #define EXTI_IMR2_IM48_Pos           (16U)
17044 #define EXTI_IMR2_IM48_Msk           (0x1UL << EXTI_IMR2_IM48_Pos)             /*!< 0x00010000 */
17045 #define EXTI_IMR2_IM48               EXTI_IMR2_IM48_Msk                        /*!< Interrupt Mask on line 48 */
17046 #define EXTI_IMR2_IM49_Pos           (17U)
17047 #define EXTI_IMR2_IM49_Msk           (0x1UL << EXTI_IMR2_IM49_Pos)             /*!< 0x00020000 */
17048 #define EXTI_IMR2_IM49               EXTI_IMR2_IM49_Msk                        /*!< Interrupt Mask on line 49 */
17049 #define EXTI_IMR2_IM50_Pos           (18U)
17050 #define EXTI_IMR2_IM50_Msk           (0x1UL << EXTI_IMR2_IM50_Pos)             /*!< 0x00040000 */
17051 #define EXTI_IMR2_IM50               EXTI_IMR2_IM50_Msk                        /*!< Interrupt Mask on line 50 */
17052 #define EXTI_IMR2_IM51_Pos           (19U)
17053 #define EXTI_IMR2_IM51_Msk           (0x1UL << EXTI_IMR2_IM51_Pos)             /*!< 0x00080000 */
17054 #define EXTI_IMR2_IM51               EXTI_IMR2_IM51_Msk                        /*!< Interrupt Mask on line 51 */
17055 #define EXTI_IMR2_IM52_Pos           (20U)
17056 #define EXTI_IMR2_IM52_Msk           (0x1UL << EXTI_IMR2_IM52_Pos)             /*!< 0x00100000 */
17057 #define EXTI_IMR2_IM52               EXTI_IMR2_IM52_Msk                        /*!< Interrupt Mask on line 52 */
17058 #define EXTI_IMR2_IM53_Pos           (21U)
17059 #define EXTI_IMR2_IM53_Msk           (0x1UL << EXTI_IMR2_IM53_Pos)             /*!< 0x00200000 */
17060 #define EXTI_IMR2_IM53               EXTI_IMR2_IM53_Msk                        /*!< Interrupt Mask on line 53 */
17061 #define EXTI_IMR2_IM54_Pos           (22U)
17062 #define EXTI_IMR2_IM54_Msk           (0x1UL << EXTI_IMR2_IM54_Pos)             /*!< 0x00400000 */
17063 #define EXTI_IMR2_IM54               EXTI_IMR2_IM54_Msk                        /*!< Interrupt Mask on line 54 */
17064 #define EXTI_IMR2_IM55_Pos           (23U)
17065 #define EXTI_IMR2_IM55_Msk           (0x1UL << EXTI_IMR2_IM55_Pos)             /*!< 0x00800000 */
17066 #define EXTI_IMR2_IM55               EXTI_IMR2_IM55_Msk                        /*!< Interrupt Mask on line 55 */
17067 #define EXTI_IMR2_IM56_Pos           (24U)
17068 #define EXTI_IMR2_IM56_Msk           (0x1UL << EXTI_IMR2_IM56_Pos)             /*!< 0x01000000 */
17069 #define EXTI_IMR2_IM56               EXTI_IMR2_IM56_Msk                        /*!< Interrupt Mask on line 56 */
17070 #define EXTI_IMR2_IM57_Pos           (25U)
17071 #define EXTI_IMR2_IM57_Msk           (0x1UL << EXTI_IMR2_IM57_Pos)             /*!< 0x02000000 */
17072 #define EXTI_IMR2_IM57               EXTI_IMR2_IM57_Msk                        /*!< Interrupt Mask on line 57 */
17073 #define EXTI_IMR2_IM58_Pos           (26U)
17074 #define EXTI_IMR2_IM58_Msk           (0x1UL << EXTI_IMR2_IM58_Pos)             /*!< 0x04000000 */
17075 #define EXTI_IMR2_IM58               EXTI_IMR2_IM58_Msk                        /*!< Interrupt Mask on line 58 */
17076 #define EXTI_IMR2_IM60_Pos           (28U)
17077 #define EXTI_IMR2_IM60_Msk           (0x1UL << EXTI_IMR2_IM60_Pos)             /*!< 0x10000000 */
17078 #define EXTI_IMR2_IM60               EXTI_IMR2_IM60_Msk                        /*!< Interrupt Mask on line 60 */
17079 #define EXTI_IMR2_IM61_Pos           (29U)
17080 #define EXTI_IMR2_IM61_Msk           (0x1UL << EXTI_IMR2_IM61_Pos)             /*!< 0x20000000 */
17081 #define EXTI_IMR2_IM61               EXTI_IMR2_IM61_Msk                        /*!< Interrupt Mask on line 61 */
17082 #define EXTI_IMR2_IM62_Pos           (30U)
17083 #define EXTI_IMR2_IM62_Msk           (0x1UL << EXTI_IMR2_IM62_Pos)             /*!< 0x40000000 */
17084 #define EXTI_IMR2_IM62               EXTI_IMR2_IM62_Msk                        /*!< Interrupt Mask on line 62 */
17085 #define EXTI_IMR2_IM63_Pos           (31U)
17086 #define EXTI_IMR2_IM63_Msk           (0x1UL << EXTI_IMR2_IM63_Pos)             /*!< 0x80000000 */
17087 #define EXTI_IMR2_IM63               EXTI_IMR2_IM63_Msk                        /*!< Interrupt Mask on line 63 */
17088 #define EXTI_IMR2_IM_Pos             (0U)
17089 #define EXTI_IMR2_IM_Msk             (0xF7FFFFFFUL << EXTI_IMR2_IM_Pos)        /*!< 0xF7FFFFFF */
17090 #define EXTI_IMR2_IM                 EXTI_IMR2_IM_Msk                          /*!< Interrupt Mask All */
17091 
17092 /*******************  Bit definition for EXTI_EMR2 register  ******************/
17093 #define EXTI_EMR2_EM32_Pos           (0U)
17094 #define EXTI_EMR2_EM32_Msk           (0x1UL << EXTI_EMR2_EM32_Pos)             /*!< 0x00000001 */
17095 #define EXTI_EMR2_EM32               EXTI_EMR2_EM32_Msk                        /*!< Event Mask on line 32 */
17096 #define EXTI_EMR2_EM33_Pos           (1U)
17097 #define EXTI_EMR2_EM33_Msk           (0x1UL << EXTI_EMR2_EM33_Pos)             /*!< 0x00000002 */
17098 #define EXTI_EMR2_EM33               EXTI_EMR2_EM33_Msk                        /*!< Event Mask on line 33 */
17099 #define EXTI_EMR2_EM34_Pos           (2U)
17100 #define EXTI_EMR2_EM34_Msk           (0x1UL << EXTI_EMR2_EM34_Pos)             /*!< 0x00000004 */
17101 #define EXTI_EMR2_EM34               EXTI_EMR2_EM34_Msk                        /*!< Event Mask on line 34 */
17102 #define EXTI_EMR2_EM35_Pos           (3U)
17103 #define EXTI_EMR2_EM35_Msk           (0x1UL << EXTI_EMR2_EM35_Pos)             /*!< 0x00000008 */
17104 #define EXTI_EMR2_EM35               EXTI_EMR2_EM35_Msk                        /*!< Event Mask on line 35 */
17105 #define EXTI_EMR2_EM36_Pos           (4U)
17106 #define EXTI_EMR2_EM36_Msk           (0x1UL << EXTI_EMR2_EM36_Pos)             /*!< 0x00000010 */
17107 #define EXTI_EMR2_EM36               EXTI_EMR2_EM36_Msk                        /*!< Event Mask on line 36 */
17108 #define EXTI_EMR2_EM37_Pos           (5U)
17109 #define EXTI_EMR2_EM37_Msk           (0x1UL << EXTI_EMR2_EM37_Pos)             /*!< 0x00000020 */
17110 #define EXTI_EMR2_EM37               EXTI_EMR2_EM37_Msk                        /*!< Event Mask on line 37 */
17111 #define EXTI_EMR2_EM38_Pos           (6U)
17112 #define EXTI_EMR2_EM38_Msk           (0x1UL << EXTI_EMR2_EM38_Pos)             /*!< 0x00000040 */
17113 #define EXTI_EMR2_EM38               EXTI_EMR2_EM38_Msk                        /*!< Event Mask on line 38 */
17114 #define EXTI_EMR2_EM39_Pos           (7U)
17115 #define EXTI_EMR2_EM39_Msk           (0x1UL << EXTI_EMR2_EM39_Pos)             /*!< 0x00000080 */
17116 #define EXTI_EMR2_EM39               EXTI_EMR2_EM39_Msk                        /*!< Event Mask on line 39 */
17117 #define EXTI_EMR2_EM40_Pos           (8U)
17118 #define EXTI_EMR2_EM40_Msk           (0x1UL << EXTI_EMR2_EM40_Pos)             /*!< 0x00000100 */
17119 #define EXTI_EMR2_EM40               EXTI_EMR2_EM40_Msk                        /*!< Event Mask on line 40 */
17120 #define EXTI_EMR2_EM41_Pos           (9U)
17121 #define EXTI_EMR2_EM41_Msk           (0x1UL << EXTI_EMR2_EM41_Pos)             /*!< 0x00000200 */
17122 #define EXTI_EMR2_EM41               EXTI_EMR2_EM41_Msk                        /*!< Event Mask on line 41 */
17123 #define EXTI_EMR2_EM42_Pos           (10U)
17124 #define EXTI_EMR2_EM42_Msk           (0x1UL << EXTI_EMR2_EM42_Pos)             /*!< 0x00000400 */
17125 #define EXTI_EMR2_EM42               EXTI_EMR2_EM42_Msk                        /*!< Event Mask on line 42 */
17126 #define EXTI_EMR2_EM43_Pos           (11U)
17127 #define EXTI_EMR2_EM43_Msk           (0x1UL << EXTI_EMR2_EM43_Pos)             /*!< 0x00000800 */
17128 #define EXTI_EMR2_EM43               EXTI_EMR2_EM43_Msk                        /*!< Event Mask on line 43 */
17129 #define EXTI_EMR2_EM44_Pos           (12U)
17130 #define EXTI_EMR2_EM44_Msk           (0x1UL << EXTI_EMR2_EM44_Pos)             /*!< 0x00001000 */
17131 #define EXTI_EMR2_EM44               EXTI_EMR2_EM44_Msk                        /*!< Event Mask on line 44 */
17132 #define EXTI_EMR2_EM45_Pos           (13U)
17133 #define EXTI_EMR2_EM45_Msk           (0x1UL << EXTI_EMR2_EM45_Pos)             /*!< 0x00002000 */
17134 #define EXTI_EMR2_EM45               EXTI_EMR2_EM45_Msk                        /*!< Event Mask on line 45 */
17135 #define EXTI_EMR2_EM46_Pos           (14U)
17136 #define EXTI_EMR2_EM46_Msk           (0x1UL << EXTI_EMR2_EM46_Pos)             /*!< 0x00004000 */
17137 #define EXTI_EMR2_EM46               EXTI_EMR2_EM46_Msk                        /*!< Event Mask on line 46 */
17138 #define EXTI_EMR2_EM47_Pos           (15U)
17139 #define EXTI_EMR2_EM47_Msk           (0x1UL << EXTI_EMR2_EM47_Pos)             /*!< 0x00008000 */
17140 #define EXTI_EMR2_EM47               EXTI_EMR2_EM47_Msk                        /*!< Event Mask on line 47 */
17141 #define EXTI_EMR2_EM48_Pos           (16U)
17142 #define EXTI_EMR2_EM48_Msk           (0x1UL << EXTI_EMR2_EM48_Pos)             /*!< 0x00010000 */
17143 #define EXTI_EMR2_EM48               EXTI_EMR2_EM48_Msk                        /*!< Event Mask on line 48 */
17144 #define EXTI_EMR2_EM49_Pos           (17U)
17145 #define EXTI_EMR2_EM49_Msk           (0x1UL << EXTI_EMR2_EM49_Pos)             /*!< 0x00020000 */
17146 #define EXTI_EMR2_EM49               EXTI_EMR2_EM49_Msk                        /*!< Event Mask on line 49 */
17147 #define EXTI_EMR2_EM50_Pos           (18U)
17148 #define EXTI_EMR2_EM50_Msk           (0x1UL << EXTI_EMR2_EM50_Pos)             /*!< 0x00040000 */
17149 #define EXTI_EMR2_EM50               EXTI_EMR2_EM50_Msk                        /*!< Event Mask on line 50 */
17150 #define EXTI_EMR2_EM51_Pos           (19U)
17151 #define EXTI_EMR2_EM51_Msk           (0x1UL << EXTI_EMR2_EM51_Pos)             /*!< 0x00080000 */
17152 #define EXTI_EMR2_EM51               EXTI_EMR2_EM51_Msk                        /*!< Event Mask on line 51 */
17153 #define EXTI_EMR2_EM52_Pos           (20U)
17154 #define EXTI_EMR2_EM52_Msk           (0x1UL << EXTI_EMR2_EM52_Pos)             /*!< 0x00100000 */
17155 #define EXTI_EMR2_EM52               EXTI_EMR2_EM52_Msk                        /*!< Event Mask on line 52 */
17156 #define EXTI_EMR2_EM53_Pos           (21U)
17157 #define EXTI_EMR2_EM53_Msk           (0x1UL << EXTI_EMR2_EM53_Pos)             /*!< 0x00200000 */
17158 #define EXTI_EMR2_EM53               EXTI_EMR2_EM53_Msk                        /*!< Event Mask on line 53 */
17159 #define EXTI_EMR2_EM54_Pos           (22U)
17160 #define EXTI_EMR2_EM54_Msk           (0x1UL << EXTI_EMR2_EM54_Pos)             /*!< 0x00400000 */
17161 #define EXTI_EMR2_EM54               EXTI_EMR2_EM54_Msk                        /*!< Event Mask on line 54 */
17162 #define EXTI_EMR2_EM55_Pos           (23U)
17163 #define EXTI_EMR2_EM55_Msk           (0x1UL << EXTI_EMR2_EM55_Pos)             /*!< 0x00800000 */
17164 #define EXTI_EMR2_EM55               EXTI_EMR2_EM55_Msk                        /*!< Event Mask on line 55 */
17165 #define EXTI_EMR2_EM56_Pos           (24U)
17166 #define EXTI_EMR2_EM56_Msk           (0x1UL << EXTI_EMR2_EM56_Pos)             /*!< 0x01000000 */
17167 #define EXTI_EMR2_EM56               EXTI_EMR2_EM56_Msk                        /*!< Event Mask on line 56 */
17168 #define EXTI_EMR2_EM57_Pos           (25U)
17169 #define EXTI_EMR2_EM57_Msk           (0x1UL << EXTI_EMR2_EM57_Pos)             /*!< 0x02000000 */
17170 #define EXTI_EMR2_EM57               EXTI_EMR2_EM57_Msk                        /*!< Event Mask on line 57 */
17171 #define EXTI_EMR2_EM58_Pos           (26U)
17172 #define EXTI_EMR2_EM58_Msk           (0x1UL << EXTI_EMR2_EM58_Pos)             /*!< 0x04000000 */
17173 #define EXTI_EMR2_EM58               EXTI_EMR2_EM58_Msk                        /*!< Event Mask on line 58 */
17174 #define EXTI_EMR2_EM60_Pos           (28U)
17175 #define EXTI_EMR2_EM60_Msk           (0x1UL << EXTI_EMR2_EM60_Pos)             /*!< 0x10000000 */
17176 #define EXTI_EMR2_EM60               EXTI_EMR2_EM60_Msk                        /*!< Event Mask on line 60 */
17177 #define EXTI_EMR2_EM61_Pos           (29U)
17178 #define EXTI_EMR2_EM61_Msk           (0x1UL << EXTI_EMR2_EM60_Pos)             /*!< 0x20000000 */
17179 #define EXTI_EMR2_EM61               EXTI_EMR2_EM60_Msk                        /*!< Event Mask on line 61 */
17180 #define EXTI_EMR2_EM62_Pos           (30U)
17181 #define EXTI_EMR2_EM62_Msk           (0x1UL << EXTI_EMR2_EM60_Pos)             /*!< 0x40000000 */
17182 #define EXTI_EMR2_EM62               EXTI_EMR2_EM60_Msk                        /*!< Event Mask on line 62 */
17183 #define EXTI_EMR2_EM63_Pos           (31U)
17184 #define EXTI_EMR2_EM63_Msk           (0x1UL << EXTI_EMR2_EM60_Pos)             /*!< 0x80000000 */
17185 #define EXTI_EMR2_EM63               EXTI_EMR2_EM60_Msk                        /*!< Event Mask on line 63 */
17186 #define EXTI_EMR2_EM_Pos             (0U)
17187 #define EXTI_EMR2_EM_Msk             (0xF7FFFFFFUL << EXTI_EMR2_EM_Pos)        /*!< 0xF7FFFFFF */
17188 #define EXTI_EMR2_EM                 EXTI_EMR2_EM_Msk                          /*!< Event Mask All */
17189 
17190 /*******************  Bit definition for EXTI_IMR3 register  ******************/
17191 #define EXTI_IMR3_IM64_Pos           (0U)
17192 #define EXTI_IMR3_IM64_Msk           (0x1UL << EXTI_IMR3_IM64_Pos)             /*!< 0x00000001 */
17193 #define EXTI_IMR3_IM64               EXTI_IMR3_IM64_Msk                        /*!< Interrupt Mask on line 64 */
17194 #define EXTI_IMR3_IM65_Pos           (1U)
17195 #define EXTI_IMR3_IM65_Msk           (0x1UL << EXTI_IMR3_IM65_Pos)             /*!< 0x00000002 */
17196 #define EXTI_IMR3_IM65               EXTI_IMR3_IM65_Msk                        /*!< Interrupt Mask on line 65 */
17197 #define EXTI_IMR3_IM66_Pos           (2U)
17198 #define EXTI_IMR3_IM66_Msk           (0x1UL << EXTI_IMR3_IM66_Pos)             /*!< 0x00000004 */
17199 #define EXTI_IMR3_IM66               EXTI_IMR3_IM66_Msk                        /*!< Interrupt Mask on line 66  */
17200 #define EXTI_IMR3_IM68_Pos           (4U)
17201 #define EXTI_IMR3_IM68_Msk           (0x1UL << EXTI_IMR3_IM68_Pos)             /*!< 0x00000010 */
17202 #define EXTI_IMR3_IM68               EXTI_IMR3_IM68_Msk                        /*!< Interrupt Mask on line 68 */
17203 #define EXTI_IMR3_IM69_Pos           (5U)
17204 #define EXTI_IMR3_IM69_Msk           (0x1UL << EXTI_IMR3_IM69_Pos)             /*!< 0x00000020 */
17205 #define EXTI_IMR3_IM69               EXTI_IMR3_IM69_Msk                        /*!< Interrupt Mask on line 69 */
17206 #define EXTI_IMR3_IM70_Pos           (6U)
17207 #define EXTI_IMR3_IM70_Msk           (0x1UL << EXTI_IMR3_IM70_Pos)             /*!< 0x00000040 */
17208 #define EXTI_IMR3_IM70               EXTI_IMR3_IM70_Msk                        /*!< Interrupt Mask on line 70 */
17209 #define EXTI_IMR3_IM71_Pos           (7U)
17210 #define EXTI_IMR3_IM71_Msk           (0x1UL << EXTI_IMR3_IM71_Pos)             /*!< 0x00000080 */
17211 #define EXTI_IMR3_IM71               EXTI_IMR3_IM71_Msk                        /*!< Interrupt Mask on line 71 */
17212 #define EXTI_IMR3_IM72_Pos           (8U)
17213 #define EXTI_IMR3_IM72_Msk           (0x1UL << EXTI_IMR3_IM72_Pos)             /*!< 0x00000100 */
17214 #define EXTI_IMR3_IM72               EXTI_IMR3_IM72_Msk                        /*!< Interrupt Mask on line 72 */
17215 #define EXTI_IMR3_IM73_Pos           (9U)
17216 #define EXTI_IMR3_IM73_Msk           (0x1UL << EXTI_IMR3_IM73_Pos)             /*!< 0x00000200 */
17217 #define EXTI_IMR3_IM73               EXTI_IMR3_IM73_Msk                        /*!< Interrupt Mask on line 73 */
17218 #define EXTI_IMR3_IM74_Pos           (10U)
17219 #define EXTI_IMR3_IM74_Msk           (0x1UL << EXTI_IMR3_IM74_Pos)             /*!< 0x00000400 */
17220 #define EXTI_IMR3_IM74               EXTI_IMR3_IM74_Msk                        /*!< Interrupt Mask on line 74 */
17221 #define EXTI_IMR3_IM77_Pos           (13U)
17222 #define EXTI_IMR3_IM77_Msk           (0x1UL << EXTI_IMR3_IM77_Pos)             /*!< 0x00002000 */
17223 #define EXTI_IMR3_IM77               EXTI_IMR3_IM77_Msk                        /*!< Interrupt Mask on line 77 */
17224 #define EXTI_IMR3_IM_Pos             (0U)
17225 #define EXTI_IMR3_IM_Msk             (0x27F7UL << EXTI_IMR3_IM_Pos)             /*!< 0x000027F7 */
17226 #define EXTI_IMR3_IM                 EXTI_IMR3_IM_Msk                           /*!< Interrupt Mask All */
17227 
17228 /*******************  Bit definition for EXTI_EMR3 register  ******************/
17229 #define EXTI_EMR3_EM64_Pos           (0U)
17230 #define EXTI_EMR3_EM64_Msk           (0x1UL << EXTI_EMR3_EM64_Pos)             /*!< 0x00000001 */
17231 #define EXTI_EMR3_EM64               EXTI_EMR3_EM64_Msk                        /*!< Event Mask on line 64 */
17232 #define EXTI_EMR3_EM65_Pos           (1U)
17233 #define EXTI_EMR3_EM65_Msk           (0x1UL << EXTI_EMR3_EM65_Pos)             /*!< 0x00000002 */
17234 #define EXTI_EMR3_EM65               EXTI_EMR3_EM65_Msk                        /*!< Event Mask on line 65 */
17235 #define EXTI_EMR3_EM66_Pos           (2U)
17236 #define EXTI_EMR3_EM66_Msk           (0x1UL << EXTI_EMR3_EM66_Pos)             /*!< 0x00000004 */
17237 #define EXTI_EMR3_EM66               EXTI_EMR3_EM66_Msk                        /*!< Event Mask on line 66  */
17238 #define EXTI_EMR3_EM68_Pos           (4U)
17239 #define EXTI_EMR3_EM68_Msk           (0x1UL << EXTI_EMR3_EM68_Pos)             /*!< 0x00000010 */
17240 #define EXTI_EMR3_EM68               EXTI_EMR3_EM68_Msk                        /*!< Event Mask on line 68 */
17241 #define EXTI_EMR3_EM69_Pos           (5U)
17242 #define EXTI_EMR3_EM69_Msk           (0x1UL << EXTI_EMR3_EM69_Pos)             /*!< 0x00000020 */
17243 #define EXTI_EMR3_EM69               EXTI_EMR3_EM69_Msk                        /*!< Event Mask on line 69 */
17244 #define EXTI_EMR3_EM70_Pos           (6U)
17245 #define EXTI_EMR3_EM70_Msk           (0x1UL << EXTI_EMR3_EM70_Pos)             /*!< 0x00000040 */
17246 #define EXTI_EMR3_EM70               EXTI_EMR3_EM70_Msk                        /*!< Event Mask on line 70 */
17247 #define EXTI_EMR3_EM71_Pos           (7U)
17248 #define EXTI_EMR3_EM71_Msk           (0x1UL << EXTI_EMR3_EM71_Pos)             /*!< 0x00000080 */
17249 #define EXTI_EMR3_EM71               EXTI_EMR3_EM71_Msk                        /*!< Event Mask on line 71 */
17250 #define EXTI_EMR3_EM72_Pos           (8U)
17251 #define EXTI_EMR3_EM72_Msk           (0x1UL << EXTI_EMR3_EM72_Pos)             /*!< 0x00000100 */
17252 #define EXTI_EMR3_EM72               EXTI_EMR3_EM72_Msk                        /*!< Event Mask on line 72 */
17253 #define EXTI_EMR3_EM73_Pos           (9U)
17254 #define EXTI_EMR3_EM73_Msk           (0x1UL << EXTI_EMR3_EM73_Pos)             /*!< 0x00000200 */
17255 #define EXTI_EMR3_EM73               EXTI_EMR3_EM73_Msk                        /*!< Event Mask on line 73 */
17256 #define EXTI_EMR3_EM74_Pos           (10U)
17257 #define EXTI_EMR3_EM74_Msk           (0x1UL << EXTI_EMR3_EM74_Pos)             /*!< 0x00000400 */
17258 #define EXTI_EMR3_EM74               EXTI_EMR3_EM74_Msk                        /*!< Event Mask on line 74 */
17259 #define EXTI_EMR3_EM77_Pos           (13U)
17260 #define EXTI_EMR3_EM77_Msk           (0x1UL << EXTI_EMR3_EM77_Pos)             /*!< 0x00002000 */
17261 #define EXTI_EMR3_EM77               EXTI_EMR3_EM77_Msk                        /*!< Event Mask on line 77 */
17262 #define EXTI_EMR3_EM_Pos             (0U)
17263 #define EXTI_EMR3_EM_Msk             (0x27F7UL << EXTI_EMR3_EM_Pos)             /*!< 0x000027F7 */
17264 #define EXTI_EMR3_EM                 EXTI_EMR3_EM_Msk                           /*!< Event Mask All */
17265 
17266 
17267 /******************************************************************************/
17268 /*                                                                            */
17269 /*                 Flexible Datarate Controller Area Network                  */
17270 /*                                                                            */
17271 /******************************************************************************/
17272 /*!<FDCAN control and status registers */
17273 /*****************  Bit definition for FDCAN_CREL register  *******************/
17274 #define FDCAN_CREL_DAY_Pos           (0U)
17275 #define FDCAN_CREL_DAY_Msk           (0xFFUL << FDCAN_CREL_DAY_Pos)            /*!< 0x000000FF */
17276 #define FDCAN_CREL_DAY               FDCAN_CREL_DAY_Msk                        /*!<Timestamp Day                           */
17277 #define FDCAN_CREL_MON_Pos           (8U)
17278 #define FDCAN_CREL_MON_Msk           (0xFFUL << FDCAN_CREL_MON_Pos)            /*!< 0x0000FF00 */
17279 #define FDCAN_CREL_MON               FDCAN_CREL_MON_Msk                        /*!<Timestamp Month                         */
17280 #define FDCAN_CREL_YEAR_Pos          (16U)
17281 #define FDCAN_CREL_YEAR_Msk          (0xFUL << FDCAN_CREL_YEAR_Pos)            /*!< 0x000F0000 */
17282 #define FDCAN_CREL_YEAR              FDCAN_CREL_YEAR_Msk                       /*!<Timestamp Year                          */
17283 #define FDCAN_CREL_SUBSTEP_Pos       (20U)
17284 #define FDCAN_CREL_SUBSTEP_Msk       (0xFUL << FDCAN_CREL_SUBSTEP_Pos)         /*!< 0x00F00000 */
17285 #define FDCAN_CREL_SUBSTEP           FDCAN_CREL_SUBSTEP_Msk                    /*!<Sub-step of Core release                */
17286 #define FDCAN_CREL_STEP_Pos          (24U)
17287 #define FDCAN_CREL_STEP_Msk          (0xFUL << FDCAN_CREL_STEP_Pos)            /*!< 0x0F000000 */
17288 #define FDCAN_CREL_STEP              FDCAN_CREL_STEP_Msk                       /*!<Step of Core release                    */
17289 #define FDCAN_CREL_REL_Pos           (28U)
17290 #define FDCAN_CREL_REL_Msk           (0xFUL << FDCAN_CREL_REL_Pos)             /*!< 0xF0000000 */
17291 #define FDCAN_CREL_REL               FDCAN_CREL_REL_Msk                        /*!<Core release                            */
17292 
17293 /*****************  Bit definition for FDCAN_ENDN register  *******************/
17294 #define FDCAN_ENDN_ETV_Pos           (0U)
17295 #define FDCAN_ENDN_ETV_Msk           (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)      /*!< 0xFFFFFFFF */
17296 #define FDCAN_ENDN_ETV               FDCAN_ENDN_ETV_Msk                        /*!<Endianness Test Value                   */
17297 
17298 /*****************  Bit definition for FDCAN_DBTP register  *******************/
17299 #define FDCAN_DBTP_DSJW_Pos          (0U)
17300 #define FDCAN_DBTP_DSJW_Msk          (0xFUL << FDCAN_DBTP_DSJW_Pos)            /*!< 0x0000000F */
17301 #define FDCAN_DBTP_DSJW              FDCAN_DBTP_DSJW_Msk                       /*!<Synchronization Jump Width              */
17302 #define FDCAN_DBTP_DTSEG2_Pos        (4U)
17303 #define FDCAN_DBTP_DTSEG2_Msk        (0xFUL << FDCAN_DBTP_DTSEG2_Pos)          /*!< 0x000000F0 */
17304 #define FDCAN_DBTP_DTSEG2            FDCAN_DBTP_DTSEG2_Msk                     /*!<Data time segment after sample point    */
17305 #define FDCAN_DBTP_DTSEG1_Pos        (8U)
17306 #define FDCAN_DBTP_DTSEG1_Msk        (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)         /*!< 0x00001F00 */
17307 #define FDCAN_DBTP_DTSEG1            FDCAN_DBTP_DTSEG1_Msk                     /*!<Data time segment before sample point   */
17308 #define FDCAN_DBTP_DBRP_Pos          (16U)
17309 #define FDCAN_DBTP_DBRP_Msk          (0x1FUL << FDCAN_DBTP_DBRP_Pos)           /*!< 0x001F0000 */
17310 #define FDCAN_DBTP_DBRP              FDCAN_DBTP_DBRP_Msk                       /*!<Data BIt Rate Prescaler                 */
17311 #define FDCAN_DBTP_TDC_Pos           (23U)
17312 #define FDCAN_DBTP_TDC_Msk           (0x1UL << FDCAN_DBTP_TDC_Pos)             /*!< 0x00800000 */
17313 #define FDCAN_DBTP_TDC               FDCAN_DBTP_TDC_Msk                        /*!<Transceiver Delay Compensation          */
17314 
17315 /*****************  Bit definition for FDCAN_TEST register  *******************/
17316 #define FDCAN_TEST_LBCK_Pos          (4U)
17317 #define FDCAN_TEST_LBCK_Msk          (0x1UL << FDCAN_TEST_LBCK_Pos)            /*!< 0x00000010 */
17318 #define FDCAN_TEST_LBCK              FDCAN_TEST_LBCK_Msk                       /*!<Loop Back mode                           */
17319 #define FDCAN_TEST_TX_Pos            (5U)
17320 #define FDCAN_TEST_TX_Msk            (0x3UL << FDCAN_TEST_TX_Pos)              /*!< 0x00000060 */
17321 #define FDCAN_TEST_TX                FDCAN_TEST_TX_Msk                         /*!<Control of Transmit Pin                  */
17322 #define FDCAN_TEST_RX_Pos            (7U)
17323 #define FDCAN_TEST_RX_Msk            (0x1UL << FDCAN_TEST_RX_Pos)              /*!< 0x00000080 */
17324 #define FDCAN_TEST_RX                FDCAN_TEST_RX_Msk                         /*!<Receive Pin                              */
17325 
17326 /*****************  Bit definition for FDCAN_RWD register  ********************/
17327 #define FDCAN_RWD_WDC_Pos            (0U)
17328 #define FDCAN_RWD_WDC_Msk            (0xFFUL << FDCAN_RWD_WDC_Pos)             /*!< 0x000000FF */
17329 #define FDCAN_RWD_WDC                FDCAN_RWD_WDC_Msk                         /*!<Watchdog configuration                   */
17330 #define FDCAN_RWD_WDV_Pos            (8U)
17331 #define FDCAN_RWD_WDV_Msk            (0xFFUL << FDCAN_RWD_WDV_Pos)             /*!< 0x0000FF00 */
17332 #define FDCAN_RWD_WDV                FDCAN_RWD_WDV_Msk                         /*!<Watchdog value                           */
17333 
17334 /*****************  Bit definition for FDCAN_CCCR register  *******************/
17335 #define FDCAN_CCCR_INIT_Pos          (0U)
17336 #define FDCAN_CCCR_INIT_Msk          (0x1UL << FDCAN_CCCR_INIT_Pos)            /*!< 0x00000001 */
17337 #define FDCAN_CCCR_INIT              FDCAN_CCCR_INIT_Msk                       /*!<Initialization                           */
17338 #define FDCAN_CCCR_CCE_Pos           (1U)
17339 #define FDCAN_CCCR_CCE_Msk           (0x1UL << FDCAN_CCCR_CCE_Pos)             /*!< 0x00000002 */
17340 #define FDCAN_CCCR_CCE               FDCAN_CCCR_CCE_Msk                        /*!<Configuration Change Enable              */
17341 #define FDCAN_CCCR_ASM_Pos           (2U)
17342 #define FDCAN_CCCR_ASM_Msk           (0x1UL << FDCAN_CCCR_ASM_Pos)             /*!< 0x00000004 */
17343 #define FDCAN_CCCR_ASM               FDCAN_CCCR_ASM_Msk                        /*!<ASM Restricted Operation Mode            */
17344 #define FDCAN_CCCR_CSA_Pos           (3U)
17345 #define FDCAN_CCCR_CSA_Msk           (0x1UL << FDCAN_CCCR_CSA_Pos)             /*!< 0x00000008 */
17346 #define FDCAN_CCCR_CSA               FDCAN_CCCR_CSA_Msk                        /*!<Clock Stop Acknowledge                   */
17347 #define FDCAN_CCCR_CSR_Pos           (4U)
17348 #define FDCAN_CCCR_CSR_Msk           (0x1UL << FDCAN_CCCR_CSR_Pos)             /*!< 0x00000010 */
17349 #define FDCAN_CCCR_CSR               FDCAN_CCCR_CSR_Msk                        /*!<Clock Stop Request                       */
17350 #define FDCAN_CCCR_MON_Pos           (5U)
17351 #define FDCAN_CCCR_MON_Msk           (0x1UL << FDCAN_CCCR_MON_Pos)             /*!< 0x00000020 */
17352 #define FDCAN_CCCR_MON               FDCAN_CCCR_MON_Msk                        /*!<Bus Monitoring Mode                      */
17353 #define FDCAN_CCCR_DAR_Pos           (6U)
17354 #define FDCAN_CCCR_DAR_Msk           (0x1UL << FDCAN_CCCR_DAR_Pos)             /*!< 0x00000040 */
17355 #define FDCAN_CCCR_DAR               FDCAN_CCCR_DAR_Msk                        /*!<Disable Automatic Retransmission         */
17356 #define FDCAN_CCCR_TEST_Pos          (7U)
17357 #define FDCAN_CCCR_TEST_Msk          (0x1UL << FDCAN_CCCR_TEST_Pos)            /*!< 0x00000080 */
17358 #define FDCAN_CCCR_TEST              FDCAN_CCCR_TEST_Msk                       /*!<Test Mode Enable                         */
17359 #define FDCAN_CCCR_FDOE_Pos          (8U)
17360 #define FDCAN_CCCR_FDOE_Msk          (0x1UL << FDCAN_CCCR_FDOE_Pos)            /*!< 0x00000100 */
17361 #define FDCAN_CCCR_FDOE              FDCAN_CCCR_FDOE_Msk                       /*!<FD Operation Enable                      */
17362 #define FDCAN_CCCR_BRSE_Pos          (9U)
17363 #define FDCAN_CCCR_BRSE_Msk          (0x1UL << FDCAN_CCCR_BRSE_Pos)            /*!< 0x00000200 */
17364 #define FDCAN_CCCR_BRSE              FDCAN_CCCR_BRSE_Msk                       /*!<FDCAN Bit Rate Switching                 */
17365 #define FDCAN_CCCR_PXHD_Pos          (12U)
17366 #define FDCAN_CCCR_PXHD_Msk          (0x1UL << FDCAN_CCCR_PXHD_Pos)            /*!< 0x00001000 */
17367 #define FDCAN_CCCR_PXHD              FDCAN_CCCR_PXHD_Msk                       /*!<Protocol Exception Handling Disable      */
17368 #define FDCAN_CCCR_EFBI_Pos          (13U)
17369 #define FDCAN_CCCR_EFBI_Msk          (0x1UL << FDCAN_CCCR_EFBI_Pos)            /*!< 0x00002000 */
17370 #define FDCAN_CCCR_EFBI              FDCAN_CCCR_EFBI_Msk                       /*!<Edge Filtering during Bus Integration    */
17371 #define FDCAN_CCCR_TXP_Pos           (14U)
17372 #define FDCAN_CCCR_TXP_Msk           (0x1UL << FDCAN_CCCR_TXP_Pos)             /*!< 0x00004000 */
17373 #define FDCAN_CCCR_TXP               FDCAN_CCCR_TXP_Msk                        /*!<Two CAN bit times Pause                  */
17374 #define FDCAN_CCCR_NISO_Pos          (15U)
17375 #define FDCAN_CCCR_NISO_Msk          (0x1UL << FDCAN_CCCR_NISO_Pos)            /*!< 0x00008000 */
17376 #define FDCAN_CCCR_NISO              FDCAN_CCCR_NISO_Msk                       /*!<Non ISO Operation                        */
17377 
17378 /*****************  Bit definition for FDCAN_NBTP register  *******************/
17379 #define FDCAN_NBTP_NTSEG2_Pos        (0U)
17380 #define FDCAN_NBTP_NTSEG2_Msk        (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)         /*!< 0x0000007F */
17381 #define FDCAN_NBTP_NTSEG2            FDCAN_NBTP_NTSEG2_Msk                     /*!<Nominal Time segment after sample point  */
17382 #define FDCAN_NBTP_NTSEG1_Pos        (8U)
17383 #define FDCAN_NBTP_NTSEG1_Msk        (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)         /*!< 0x0000FF00 */
17384 #define FDCAN_NBTP_NTSEG1            FDCAN_NBTP_NTSEG1_Msk                     /*!<Nominal Time segment before sample point */
17385 #define FDCAN_NBTP_NBRP_Pos          (16U)
17386 #define FDCAN_NBTP_NBRP_Msk          (0x1FFUL << FDCAN_NBTP_NBRP_Pos)          /*!< 0x01FF0000 */
17387 #define FDCAN_NBTP_NBRP              FDCAN_NBTP_NBRP_Msk                       /*!<Bit Rate Prescaler                       */
17388 #define FDCAN_NBTP_NSJW_Pos          (25U)
17389 #define FDCAN_NBTP_NSJW_Msk          (0x7FUL << FDCAN_NBTP_NSJW_Pos)           /*!< 0xFE000000 */
17390 #define FDCAN_NBTP_NSJW              FDCAN_NBTP_NSJW_Msk                       /*!<Nominal (Re)Synchronization Jump Width   */
17391 
17392 /*****************  Bit definition for FDCAN_TSCC register  *******************/
17393 #define FDCAN_TSCC_TSS_Pos           (0U)
17394 #define FDCAN_TSCC_TSS_Msk           (0x3UL << FDCAN_TSCC_TSS_Pos)             /*!< 0x00000003 */
17395 #define FDCAN_TSCC_TSS               FDCAN_TSCC_TSS_Msk                        /*!<Timestamp Select                         */
17396 #define FDCAN_TSCC_TCP_Pos           (16U)
17397 #define FDCAN_TSCC_TCP_Msk           (0xFUL << FDCAN_TSCC_TCP_Pos)             /*!< 0x000F0000 */
17398 #define FDCAN_TSCC_TCP               FDCAN_TSCC_TCP_Msk                        /*!<Timestamp Counter Prescaler              */
17399 
17400 /*****************  Bit definition for FDCAN_TSCV register  *******************/
17401 #define FDCAN_TSCV_TSC_Pos           (0U)
17402 #define FDCAN_TSCV_TSC_Msk           (0xFFFFUL << FDCAN_TSCV_TSC_Pos)          /*!< 0x0000FFFF */
17403 #define FDCAN_TSCV_TSC               FDCAN_TSCV_TSC_Msk                        /*!<Timestamp Counter                        */
17404 
17405 /*****************  Bit definition for FDCAN_TOCC register  *******************/
17406 #define FDCAN_TOCC_ETOC_Pos          (0U)
17407 #define FDCAN_TOCC_ETOC_Msk          (0x1UL << FDCAN_TOCC_ETOC_Pos)            /*!< 0x00000001 */
17408 #define FDCAN_TOCC_ETOC              FDCAN_TOCC_ETOC_Msk                       /*!<Enable Timeout Counter                   */
17409 #define FDCAN_TOCC_TOS_Pos           (1U)
17410 #define FDCAN_TOCC_TOS_Msk           (0x3UL << FDCAN_TOCC_TOS_Pos)             /*!< 0x00000006 */
17411 #define FDCAN_TOCC_TOS               FDCAN_TOCC_TOS_Msk                        /*!<Timeout Select                           */
17412 #define FDCAN_TOCC_TOP_Pos           (16U)
17413 #define FDCAN_TOCC_TOP_Msk           (0xFFFFUL << FDCAN_TOCC_TOP_Pos)          /*!< 0xFFFF0000 */
17414 #define FDCAN_TOCC_TOP               FDCAN_TOCC_TOP_Msk                        /*!<Timeout Period                           */
17415 
17416 /*****************  Bit definition for FDCAN_TOCV register  *******************/
17417 #define FDCAN_TOCV_TOC_Pos           (0U)
17418 #define FDCAN_TOCV_TOC_Msk           (0xFFFFUL << FDCAN_TOCV_TOC_Pos)          /*!< 0x0000FFFF */
17419 #define FDCAN_TOCV_TOC               FDCAN_TOCV_TOC_Msk                        /*!<Timeout Counter                          */
17420 
17421 /*****************  Bit definition for FDCAN_ECR register  ********************/
17422 #define FDCAN_ECR_TEC_Pos            (0U)
17423 #define FDCAN_ECR_TEC_Msk            (0xFFUL << FDCAN_ECR_TEC_Pos)             /*!< 0x000000FF */
17424 #define FDCAN_ECR_TEC                FDCAN_ECR_TEC_Msk                         /*!<Transmit Error Counter                   */
17425 #define FDCAN_ECR_REC_Pos            (8U)
17426 #define FDCAN_ECR_REC_Msk            (0x7FUL << FDCAN_ECR_REC_Pos)             /*!< 0x00007F00 */
17427 #define FDCAN_ECR_REC                FDCAN_ECR_REC_Msk                         /*!<Receive Error Counter                    */
17428 #define FDCAN_ECR_RP_Pos             (15U)
17429 #define FDCAN_ECR_RP_Msk             (0x1UL << FDCAN_ECR_RP_Pos)               /*!< 0x00008000 */
17430 #define FDCAN_ECR_RP                 FDCAN_ECR_RP_Msk                          /*!<Receive Error Passive                    */
17431 #define FDCAN_ECR_CEL_Pos            (16U)
17432 #define FDCAN_ECR_CEL_Msk            (0xFFUL << FDCAN_ECR_CEL_Pos)             /*!< 0x00FF0000 */
17433 #define FDCAN_ECR_CEL                FDCAN_ECR_CEL_Msk                         /*!<CAN Error Logging                        */
17434 
17435 /*****************  Bit definition for FDCAN_PSR register  ********************/
17436 #define FDCAN_PSR_LEC_Pos            (0U)
17437 #define FDCAN_PSR_LEC_Msk            (0x7UL << FDCAN_PSR_LEC_Pos)              /*!< 0x00000007 */
17438 #define FDCAN_PSR_LEC                FDCAN_PSR_LEC_Msk                         /*!<Last Error Code                          */
17439 #define FDCAN_PSR_ACT_Pos            (3U)
17440 #define FDCAN_PSR_ACT_Msk            (0x3UL << FDCAN_PSR_ACT_Pos)              /*!< 0x00000018 */
17441 #define FDCAN_PSR_ACT                FDCAN_PSR_ACT_Msk                         /*!<Activity                                 */
17442 #define FDCAN_PSR_EP_Pos             (5U)
17443 #define FDCAN_PSR_EP_Msk             (0x1UL << FDCAN_PSR_EP_Pos)               /*!< 0x00000020 */
17444 #define FDCAN_PSR_EP                 FDCAN_PSR_EP_Msk                          /*!<Error Passive                            */
17445 #define FDCAN_PSR_EW_Pos             (6U)
17446 #define FDCAN_PSR_EW_Msk             (0x1UL << FDCAN_PSR_EW_Pos)               /*!< 0x00000040 */
17447 #define FDCAN_PSR_EW                 FDCAN_PSR_EW_Msk                          /*!<Warning Status                           */
17448 #define FDCAN_PSR_BO_Pos             (7U)
17449 #define FDCAN_PSR_BO_Msk             (0x1UL << FDCAN_PSR_BO_Pos)               /*!< 0x00000080 */
17450 #define FDCAN_PSR_BO                 FDCAN_PSR_BO_Msk                          /*!<Bus_Off Status                           */
17451 #define FDCAN_PSR_DLEC_Pos           (8U)
17452 #define FDCAN_PSR_DLEC_Msk           (0x7UL << FDCAN_PSR_DLEC_Pos)             /*!< 0x00000700 */
17453 #define FDCAN_PSR_DLEC               FDCAN_PSR_DLEC_Msk                        /*!<Data Last Error Code                     */
17454 #define FDCAN_PSR_RESI_Pos           (11U)
17455 #define FDCAN_PSR_RESI_Msk           (0x1UL << FDCAN_PSR_RESI_Pos)             /*!< 0x00000800 */
17456 #define FDCAN_PSR_RESI               FDCAN_PSR_RESI_Msk                        /*!<ESI flag of last received FDCAN Message  */
17457 #define FDCAN_PSR_RBRS_Pos           (12U)
17458 #define FDCAN_PSR_RBRS_Msk           (0x1UL << FDCAN_PSR_RBRS_Pos)             /*!< 0x00001000 */
17459 #define FDCAN_PSR_RBRS               FDCAN_PSR_RBRS_Msk                        /*!<BRS flag of last received FDCAN Message  */
17460 #define FDCAN_PSR_REDL_Pos           (13U)
17461 #define FDCAN_PSR_REDL_Msk           (0x1UL << FDCAN_PSR_REDL_Pos)             /*!< 0x00002000 */
17462 #define FDCAN_PSR_REDL               FDCAN_PSR_REDL_Msk                        /*!<Received FDCAN Message                   */
17463 #define FDCAN_PSR_PXE_Pos            (14U)
17464 #define FDCAN_PSR_PXE_Msk            (0x1UL << FDCAN_PSR_PXE_Pos)              /*!< 0x00004000 */
17465 #define FDCAN_PSR_PXE                FDCAN_PSR_PXE_Msk                         /*!<Protocol Exception Event                 */
17466 #define FDCAN_PSR_TDCV_Pos           (16U)
17467 #define FDCAN_PSR_TDCV_Msk           (0x7FUL << FDCAN_PSR_TDCV_Pos)            /*!< 0x007F0000 */
17468 #define FDCAN_PSR_TDCV               FDCAN_PSR_TDCV_Msk                        /*!<Transmitter Delay Compensation Value     */
17469 
17470 /*****************  Bit definition for FDCAN_TDCR register  *******************/
17471 #define FDCAN_TDCR_TDCF_Pos          (0U)
17472 #define FDCAN_TDCR_TDCF_Msk          (0x7FUL << FDCAN_TDCR_TDCF_Pos)           /*!< 0x0000007F */
17473 #define FDCAN_TDCR_TDCF              FDCAN_TDCR_TDCF_Msk                       /*!<Transmitter Delay Compensation Filter    */
17474 #define FDCAN_TDCR_TDCO_Pos          (8U)
17475 #define FDCAN_TDCR_TDCO_Msk          (0x7FUL << FDCAN_TDCR_TDCO_Pos)           /*!< 0x00007F00 */
17476 #define FDCAN_TDCR_TDCO              FDCAN_TDCR_TDCO_Msk                       /*!<Transmitter Delay Compensation Offset    */
17477 
17478 /*****************  Bit definition for FDCAN_IR register  *********************/
17479 #define FDCAN_IR_RF0N_Pos            (0U)
17480 #define FDCAN_IR_RF0N_Msk            (0x1UL << FDCAN_IR_RF0N_Pos)              /*!< 0x00000001 */
17481 #define FDCAN_IR_RF0N                FDCAN_IR_RF0N_Msk                         /*!<Rx FIFO 0 New Message                    */
17482 #define FDCAN_IR_RF0W_Pos            (1U)
17483 #define FDCAN_IR_RF0W_Msk            (0x1UL << FDCAN_IR_RF0W_Pos)              /*!< 0x00000002 */
17484 #define FDCAN_IR_RF0W                FDCAN_IR_RF0W_Msk                         /*!<Rx FIFO 0 Watermark Reached              */
17485 #define FDCAN_IR_RF0F_Pos            (2U)
17486 #define FDCAN_IR_RF0F_Msk            (0x1UL << FDCAN_IR_RF0F_Pos)              /*!< 0x00000004 */
17487 #define FDCAN_IR_RF0F                FDCAN_IR_RF0F_Msk                         /*!<Rx FIFO 0 Full                           */
17488 #define FDCAN_IR_RF0L_Pos            (3U)
17489 #define FDCAN_IR_RF0L_Msk            (0x1UL << FDCAN_IR_RF0L_Pos)              /*!< 0x00000008 */
17490 #define FDCAN_IR_RF0L                FDCAN_IR_RF0L_Msk                         /*!<Rx FIFO 0 Message Lost                   */
17491 #define FDCAN_IR_RF1N_Pos            (4U)
17492 #define FDCAN_IR_RF1N_Msk            (0x1UL << FDCAN_IR_RF1N_Pos)              /*!< 0x00000010 */
17493 #define FDCAN_IR_RF1N                FDCAN_IR_RF1N_Msk                         /*!<Rx FIFO 1 New Message                    */
17494 #define FDCAN_IR_RF1W_Pos            (5U)
17495 #define FDCAN_IR_RF1W_Msk            (0x1UL << FDCAN_IR_RF1W_Pos)              /*!< 0x00000020 */
17496 #define FDCAN_IR_RF1W                FDCAN_IR_RF1W_Msk                         /*!<Rx FIFO 1 Watermark Reached              */
17497 #define FDCAN_IR_RF1F_Pos            (6U)
17498 #define FDCAN_IR_RF1F_Msk            (0x1UL << FDCAN_IR_RF1F_Pos)              /*!< 0x00000040 */
17499 #define FDCAN_IR_RF1F                FDCAN_IR_RF1F_Msk                         /*!<Rx FIFO 1 Full                           */
17500 #define FDCAN_IR_RF1L_Pos            (7U)
17501 #define FDCAN_IR_RF1L_Msk            (0x1UL << FDCAN_IR_RF1L_Pos)              /*!< 0x00000080 */
17502 #define FDCAN_IR_RF1L                FDCAN_IR_RF1L_Msk                         /*!<Rx FIFO 1 Message Lost                   */
17503 #define FDCAN_IR_HPM_Pos             (8U)
17504 #define FDCAN_IR_HPM_Msk             (0x1UL << FDCAN_IR_HPM_Pos)               /*!< 0x00000100 */
17505 #define FDCAN_IR_HPM                 FDCAN_IR_HPM_Msk                          /*!<High Priority Message                    */
17506 #define FDCAN_IR_TC_Pos              (9U)
17507 #define FDCAN_IR_TC_Msk              (0x1UL << FDCAN_IR_TC_Pos)                /*!< 0x00000200 */
17508 #define FDCAN_IR_TC                  FDCAN_IR_TC_Msk                           /*!<Transmission Completed                   */
17509 #define FDCAN_IR_TCF_Pos             (10U)
17510 #define FDCAN_IR_TCF_Msk             (0x1UL << FDCAN_IR_TCF_Pos)               /*!< 0x00000400 */
17511 #define FDCAN_IR_TCF                 FDCAN_IR_TCF_Msk                          /*!<Transmission Cancellation Finished       */
17512 #define FDCAN_IR_TFE_Pos             (11U)
17513 #define FDCAN_IR_TFE_Msk             (0x1UL << FDCAN_IR_TFE_Pos)               /*!< 0x00000800 */
17514 #define FDCAN_IR_TFE                 FDCAN_IR_TFE_Msk                          /*!<Tx FIFO Empty                            */
17515 #define FDCAN_IR_TEFN_Pos            (12U)
17516 #define FDCAN_IR_TEFN_Msk            (0x1UL << FDCAN_IR_TEFN_Pos)              /*!< 0x00001000 */
17517 #define FDCAN_IR_TEFN                FDCAN_IR_TEFN_Msk                         /*!<Tx Event FIFO New Entry                  */
17518 #define FDCAN_IR_TEFW_Pos            (13U)
17519 #define FDCAN_IR_TEFW_Msk            (0x1UL << FDCAN_IR_TEFW_Pos)              /*!< 0x00002000 */
17520 #define FDCAN_IR_TEFW                FDCAN_IR_TEFW_Msk                         /*!<Tx Event FIFO Watermark Reached          */
17521 #define FDCAN_IR_TEFF_Pos            (14U)
17522 #define FDCAN_IR_TEFF_Msk            (0x1UL << FDCAN_IR_TEFF_Pos)              /*!< 0x00004000 */
17523 #define FDCAN_IR_TEFF                FDCAN_IR_TEFF_Msk                         /*!<Tx Event FIFO Full                       */
17524 #define FDCAN_IR_TEFL_Pos            (15U)
17525 #define FDCAN_IR_TEFL_Msk            (0x1UL << FDCAN_IR_TEFL_Pos)              /*!< 0x00008000 */
17526 #define FDCAN_IR_TEFL                FDCAN_IR_TEFL_Msk                         /*!<Tx Event FIFO Element Lost               */
17527 #define FDCAN_IR_TSW_Pos             (16U)
17528 #define FDCAN_IR_TSW_Msk             (0x1UL << FDCAN_IR_TSW_Pos)               /*!< 0x00010000 */
17529 #define FDCAN_IR_TSW                 FDCAN_IR_TSW_Msk                          /*!<Timestamp Wraparound                     */
17530 #define FDCAN_IR_MRAF_Pos            (17U)
17531 #define FDCAN_IR_MRAF_Msk            (0x1UL << FDCAN_IR_MRAF_Pos)              /*!< 0x00020000 */
17532 #define FDCAN_IR_MRAF                FDCAN_IR_MRAF_Msk                         /*!<Message RAM Access Failure               */
17533 #define FDCAN_IR_TOO_Pos             (18U)
17534 #define FDCAN_IR_TOO_Msk             (0x1UL << FDCAN_IR_TOO_Pos)               /*!< 0x00040000 */
17535 #define FDCAN_IR_TOO                 FDCAN_IR_TOO_Msk                          /*!<Timeout Occurred                         */
17536 #define FDCAN_IR_DRX_Pos             (19U)
17537 #define FDCAN_IR_DRX_Msk             (0x1UL << FDCAN_IR_DRX_Pos)               /*!< 0x00080000 */
17538 #define FDCAN_IR_DRX                 FDCAN_IR_DRX_Msk                          /*!<Message stored to Dedicated Rx Buffer    */
17539 #define FDCAN_IR_ELO_Pos             (22U)
17540 #define FDCAN_IR_ELO_Msk             (0x1UL << FDCAN_IR_ELO_Pos)               /*!< 0x00400000 */
17541 #define FDCAN_IR_ELO                 FDCAN_IR_ELO_Msk                          /*!<Error Logging Overflow                   */
17542 #define FDCAN_IR_EP_Pos              (23U)
17543 #define FDCAN_IR_EP_Msk              (0x1UL << FDCAN_IR_EP_Pos)                /*!< 0x00800000 */
17544 #define FDCAN_IR_EP                  FDCAN_IR_EP_Msk                           /*!<Error Passive                            */
17545 #define FDCAN_IR_EW_Pos              (24U)
17546 #define FDCAN_IR_EW_Msk              (0x1UL << FDCAN_IR_EW_Pos)                /*!< 0x01000000 */
17547 #define FDCAN_IR_EW                  FDCAN_IR_EW_Msk                           /*!<Warning Status                           */
17548 #define FDCAN_IR_BO_Pos              (25U)
17549 #define FDCAN_IR_BO_Msk              (0x1UL << FDCAN_IR_BO_Pos)                /*!< 0x02000000 */
17550 #define FDCAN_IR_BO                  FDCAN_IR_BO_Msk                           /*!<Bus_Off Status                           */
17551 #define FDCAN_IR_WDI_Pos             (26U)
17552 #define FDCAN_IR_WDI_Msk             (0x1UL << FDCAN_IR_WDI_Pos)               /*!< 0x04000000 */
17553 #define FDCAN_IR_WDI                 FDCAN_IR_WDI_Msk                          /*!<Watchdog Interrupt                       */
17554 #define FDCAN_IR_PEA_Pos             (27U)
17555 #define FDCAN_IR_PEA_Msk             (0x1UL << FDCAN_IR_PEA_Pos)               /*!< 0x08000000 */
17556 #define FDCAN_IR_PEA                 FDCAN_IR_PEA_Msk                          /*!<Protocol Error in Arbitration Phase      */
17557 #define FDCAN_IR_PED_Pos             (28U)
17558 #define FDCAN_IR_PED_Msk             (0x1UL << FDCAN_IR_PED_Pos)               /*!< 0x10000000 */
17559 #define FDCAN_IR_PED                 FDCAN_IR_PED_Msk                          /*!<Protocol Error in Data Phase             */
17560 #define FDCAN_IR_ARA_Pos             (29U)
17561 #define FDCAN_IR_ARA_Msk             (0x1UL << FDCAN_IR_ARA_Pos)               /*!< 0x20000000 */
17562 #define FDCAN_IR_ARA                 FDCAN_IR_ARA_Msk                          /*!<Access to Reserved Address               */
17563 
17564 /*****************  Bit definition for FDCAN_IE register  *********************/
17565 #define FDCAN_IE_RF0NE_Pos           (0U)
17566 #define FDCAN_IE_RF0NE_Msk           (0x1UL << FDCAN_IE_RF0NE_Pos)             /*!< 0x00000001 */
17567 #define FDCAN_IE_RF0NE               FDCAN_IE_RF0NE_Msk                        /*!<Rx FIFO 0 New Message Enable             */
17568 #define FDCAN_IE_RF0WE_Pos           (1U)
17569 #define FDCAN_IE_RF0WE_Msk           (0x1UL << FDCAN_IE_RF0WE_Pos)             /*!< 0x00000002 */
17570 #define FDCAN_IE_RF0WE               FDCAN_IE_RF0WE_Msk                        /*!<Rx FIFO 0 Watermark Reached Enable           */
17571 #define FDCAN_IE_RF0FE_Pos           (2U)
17572 #define FDCAN_IE_RF0FE_Msk           (0x1UL << FDCAN_IE_RF0FE_Pos)             /*!< 0x00000004 */
17573 #define FDCAN_IE_RF0FE               FDCAN_IE_RF0FE_Msk                        /*!<Rx FIFO 0 Full Enable                    */
17574 #define FDCAN_IE_RF0LE_Pos           (3U)
17575 #define FDCAN_IE_RF0LE_Msk           (0x1UL << FDCAN_IE_RF0LE_Pos)             /*!< 0x00000008 */
17576 #define FDCAN_IE_RF0LE               FDCAN_IE_RF0LE_Msk                        /*!<Rx FIFO 0 Message Lost Enable            */
17577 #define FDCAN_IE_RF1NE_Pos           (4U)
17578 #define FDCAN_IE_RF1NE_Msk           (0x1UL << FDCAN_IE_RF1NE_Pos)             /*!< 0x00000010 */
17579 #define FDCAN_IE_RF1NE               FDCAN_IE_RF1NE_Msk                        /*!<Rx FIFO 1 New Message Enable             */
17580 #define FDCAN_IE_RF1WE_Pos           (5U)
17581 #define FDCAN_IE_RF1WE_Msk           (0x1UL << FDCAN_IE_RF1WE_Pos)             /*!< 0x00000020 */
17582 #define FDCAN_IE_RF1WE               FDCAN_IE_RF1WE_Msk                        /*!<Rx FIFO 1 Watermark Reached Enable           */
17583 #define FDCAN_IE_RF1FE_Pos           (6U)
17584 #define FDCAN_IE_RF1FE_Msk           (0x1UL << FDCAN_IE_RF1FE_Pos)             /*!< 0x00000040 */
17585 #define FDCAN_IE_RF1FE               FDCAN_IE_RF1FE_Msk                        /*!<Rx FIFO 1 Full Enable                    */
17586 #define FDCAN_IE_RF1LE_Pos           (7U)
17587 #define FDCAN_IE_RF1LE_Msk           (0x1UL << FDCAN_IE_RF1LE_Pos)             /*!< 0x00000080 */
17588 #define FDCAN_IE_RF1LE               FDCAN_IE_RF1LE_Msk                        /*!<Rx FIFO 1 Message Lost Enable            */
17589 #define FDCAN_IE_HPME_Pos            (8U)
17590 #define FDCAN_IE_HPME_Msk            (0x1UL << FDCAN_IE_HPME_Pos)              /*!< 0x00000100 */
17591 #define FDCAN_IE_HPME                FDCAN_IE_HPME_Msk                         /*!<High Priority Message Enable             */
17592 #define FDCAN_IE_TCE_Pos             (9U)
17593 #define FDCAN_IE_TCE_Msk             (0x1UL << FDCAN_IE_TCE_Pos)               /*!< 0x00000200 */
17594 #define FDCAN_IE_TCE                 FDCAN_IE_TCE_Msk                          /*!<Transmission Completed Enable            */
17595 #define FDCAN_IE_TCFE_Pos            (10U)
17596 #define FDCAN_IE_TCFE_Msk            (0x1UL << FDCAN_IE_TCFE_Pos)              /*!< 0x00000400 */
17597 #define FDCAN_IE_TCFE                FDCAN_IE_TCFE_Msk                         /*!<Transmission Cancellation Finished Enable    */
17598 #define FDCAN_IE_TFEE_Pos            (11U)
17599 #define FDCAN_IE_TFEE_Msk            (0x1UL << FDCAN_IE_TFEE_Pos)              /*!< 0x00000800 */
17600 #define FDCAN_IE_TFEE                FDCAN_IE_TFEE_Msk                         /*!<Tx FIFO Empty Enable                     */
17601 #define FDCAN_IE_TEFNE_Pos           (12U)
17602 #define FDCAN_IE_TEFNE_Msk           (0x1UL << FDCAN_IE_TEFNE_Pos)             /*!< 0x00001000 */
17603 #define FDCAN_IE_TEFNE               FDCAN_IE_TEFNE_Msk                        /*!<Tx Event FIFO New Entry Enable           */
17604 #define FDCAN_IE_TEFWE_Pos           (13U)
17605 #define FDCAN_IE_TEFWE_Msk           (0x1UL << FDCAN_IE_TEFWE_Pos)             /*!< 0x00002000 */
17606 #define FDCAN_IE_TEFWE               FDCAN_IE_TEFWE_Msk                        /*!<Tx Event FIFO Watermark Reached Enable       */
17607 #define FDCAN_IE_TEFFE_Pos           (14U)
17608 #define FDCAN_IE_TEFFE_Msk           (0x1UL << FDCAN_IE_TEFFE_Pos)             /*!< 0x00004000 */
17609 #define FDCAN_IE_TEFFE               FDCAN_IE_TEFFE_Msk                        /*!<Tx Event FIFO Full Enable                */
17610 #define FDCAN_IE_TEFLE_Pos           (15U)
17611 #define FDCAN_IE_TEFLE_Msk           (0x1UL << FDCAN_IE_TEFLE_Pos)             /*!< 0x00008000 */
17612 #define FDCAN_IE_TEFLE               FDCAN_IE_TEFLE_Msk                        /*!<Tx Event FIFO Element Lost Enable        */
17613 #define FDCAN_IE_TSWE_Pos            (16U)
17614 #define FDCAN_IE_TSWE_Msk            (0x1UL << FDCAN_IE_TSWE_Pos)              /*!< 0x00010000 */
17615 #define FDCAN_IE_TSWE                FDCAN_IE_TSWE_Msk                         /*!<Timestamp Wraparound Enable              */
17616 #define FDCAN_IE_MRAFE_Pos           (17U)
17617 #define FDCAN_IE_MRAFE_Msk           (0x1UL << FDCAN_IE_MRAFE_Pos)             /*!< 0x00020000 */
17618 #define FDCAN_IE_MRAFE               FDCAN_IE_MRAFE_Msk                        /*!<Message RAM Access Failure Enable        */
17619 #define FDCAN_IE_TOOE_Pos            (18U)
17620 #define FDCAN_IE_TOOE_Msk            (0x1UL << FDCAN_IE_TOOE_Pos)              /*!< 0x00040000 */
17621 #define FDCAN_IE_TOOE                FDCAN_IE_TOOE_Msk                         /*!<Timeout Occurred Enable                  */
17622 #define FDCAN_IE_DRXE_Pos            (19U)
17623 #define FDCAN_IE_DRXE_Msk            (0x1UL << FDCAN_IE_DRXE_Pos)              /*!< 0x00080000 */
17624 #define FDCAN_IE_DRXE                FDCAN_IE_DRXE_Msk                         /*!<Message stored to Dedicated Rx Buffer Enable */
17625 #define FDCAN_IE_BECE_Pos            (20U)
17626 #define FDCAN_IE_BECE_Msk            (0x1UL << FDCAN_IE_BECE_Pos)              /*!< 0x00100000 */
17627 #define FDCAN_IE_BECE                FDCAN_IE_BECE_Msk                         /*!<Bit Error Corrected Interrupt Enable         */
17628 #define FDCAN_IE_BEUE_Pos            (21U)
17629 #define FDCAN_IE_BEUE_Msk            (0x1UL << FDCAN_IE_BEUE_Pos)              /*!< 0x00200000 */
17630 #define FDCAN_IE_BEUE                FDCAN_IE_BEUE_Msk                         /*!<Bit Error Uncorrected Interrupt Enable       */
17631 #define FDCAN_IE_ELOE_Pos            (22U)
17632 #define FDCAN_IE_ELOE_Msk            (0x1UL << FDCAN_IE_ELOE_Pos)              /*!< 0x00400000 */
17633 #define FDCAN_IE_ELOE                FDCAN_IE_ELOE_Msk                         /*!<Error Logging Overflow Enable            */
17634 #define FDCAN_IE_EPE_Pos             (23U)
17635 #define FDCAN_IE_EPE_Msk             (0x1UL << FDCAN_IE_EPE_Pos)               /*!< 0x00800000 */
17636 #define FDCAN_IE_EPE                 FDCAN_IE_EPE_Msk                          /*!<Error Passive Enable                     */
17637 #define FDCAN_IE_EWE_Pos             (24U)
17638 #define FDCAN_IE_EWE_Msk             (0x1UL << FDCAN_IE_EWE_Pos)               /*!< 0x01000000 */
17639 #define FDCAN_IE_EWE                 FDCAN_IE_EWE_Msk                          /*!<Warning Status Enable                    */
17640 #define FDCAN_IE_BOE_Pos             (25U)
17641 #define FDCAN_IE_BOE_Msk             (0x1UL << FDCAN_IE_BOE_Pos)               /*!< 0x02000000 */
17642 #define FDCAN_IE_BOE                 FDCAN_IE_BOE_Msk                          /*!<Bus_Off Status Enable                    */
17643 #define FDCAN_IE_WDIE_Pos            (26U)
17644 #define FDCAN_IE_WDIE_Msk            (0x1UL << FDCAN_IE_WDIE_Pos)              /*!< 0x04000000 */
17645 #define FDCAN_IE_WDIE                FDCAN_IE_WDIE_Msk                         /*!<Watchdog Interrupt Enable                */
17646 #define FDCAN_IE_PEAE_Pos            (27U)
17647 #define FDCAN_IE_PEAE_Msk            (0x1UL << FDCAN_IE_PEAE_Pos)              /*!< 0x08000000 */
17648 #define FDCAN_IE_PEAE                FDCAN_IE_PEAE_Msk                         /*!<Protocol Error in Arbitration Phase Enable   */
17649 #define FDCAN_IE_PEDE_Pos            (28U)
17650 #define FDCAN_IE_PEDE_Msk            (0x1UL << FDCAN_IE_PEDE_Pos)              /*!< 0x10000000 */
17651 #define FDCAN_IE_PEDE                FDCAN_IE_PEDE_Msk                         /*!<Protocol Error in Data Phase Enable      */
17652 #define FDCAN_IE_ARAE_Pos            (29U)
17653 #define FDCAN_IE_ARAE_Msk            (0x1UL << FDCAN_IE_ARAE_Pos)              /*!< 0x20000000 */
17654 #define FDCAN_IE_ARAE                FDCAN_IE_ARAE_Msk                         /*!<Access to Reserved Address Enable        */
17655 
17656 /*****************  Bit definition for FDCAN_ILS register  ********************/
17657 #define FDCAN_ILS_RF0NL_Pos          (0U)
17658 #define FDCAN_ILS_RF0NL_Msk          (0x1UL << FDCAN_ILS_RF0NL_Pos)            /*!< 0x00000001 */
17659 #define FDCAN_ILS_RF0NL              FDCAN_ILS_RF0NL_Msk                       /*!<Rx FIFO 0 New Message Line                  */
17660 #define FDCAN_ILS_RF0WL_Pos          (1U)
17661 #define FDCAN_ILS_RF0WL_Msk          (0x1UL << FDCAN_ILS_RF0WL_Pos)            /*!< 0x00000002 */
17662 #define FDCAN_ILS_RF0WL              FDCAN_ILS_RF0WL_Msk                       /*!<Rx FIFO 0 Watermark Reached Line            */
17663 #define FDCAN_ILS_RF0FL_Pos          (2U)
17664 #define FDCAN_ILS_RF0FL_Msk          (0x1UL << FDCAN_ILS_RF0FL_Pos)            /*!< 0x00000004 */
17665 #define FDCAN_ILS_RF0FL              FDCAN_ILS_RF0FL_Msk                       /*!<Rx FIFO 0 Full Line                         */
17666 #define FDCAN_ILS_RF0LL_Pos          (3U)
17667 #define FDCAN_ILS_RF0LL_Msk          (0x1UL << FDCAN_ILS_RF0LL_Pos)            /*!< 0x00000008 */
17668 #define FDCAN_ILS_RF0LL              FDCAN_ILS_RF0LL_Msk                       /*!<Rx FIFO 0 Message Lost Line                 */
17669 #define FDCAN_ILS_RF1NL_Pos          (4U)
17670 #define FDCAN_ILS_RF1NL_Msk          (0x1UL << FDCAN_ILS_RF1NL_Pos)            /*!< 0x00000010 */
17671 #define FDCAN_ILS_RF1NL              FDCAN_ILS_RF1NL_Msk                       /*!<Rx FIFO 1 New Message Line                  */
17672 #define FDCAN_ILS_RF1WL_Pos          (5U)
17673 #define FDCAN_ILS_RF1WL_Msk          (0x1UL << FDCAN_ILS_RF1WL_Pos)            /*!< 0x00000020 */
17674 #define FDCAN_ILS_RF1WL              FDCAN_ILS_RF1WL_Msk                       /*!<Rx FIFO 1 Watermark Reached Line            */
17675 #define FDCAN_ILS_RF1FL_Pos          (6U)
17676 #define FDCAN_ILS_RF1FL_Msk          (0x1UL << FDCAN_ILS_RF1FL_Pos)            /*!< 0x00000040 */
17677 #define FDCAN_ILS_RF1FL              FDCAN_ILS_RF1FL_Msk                       /*!<Rx FIFO 1 Full Line                         */
17678 #define FDCAN_ILS_RF1LL_Pos          (7U)
17679 #define FDCAN_ILS_RF1LL_Msk          (0x1UL << FDCAN_ILS_RF1LL_Pos)            /*!< 0x00000080 */
17680 #define FDCAN_ILS_RF1LL              FDCAN_ILS_RF1LL_Msk                       /*!<Rx FIFO 1 Message Lost Line                 */
17681 #define FDCAN_ILS_HPML_Pos           (8U)
17682 #define FDCAN_ILS_HPML_Msk           (0x1UL << FDCAN_ILS_HPML_Pos)             /*!< 0x00000100 */
17683 #define FDCAN_ILS_HPML               FDCAN_ILS_HPML_Msk                        /*!<High Priority Message Line                  */
17684 #define FDCAN_ILS_TCL_Pos            (9U)
17685 #define FDCAN_ILS_TCL_Msk            (0x1UL << FDCAN_ILS_TCL_Pos)              /*!< 0x00000200 */
17686 #define FDCAN_ILS_TCL                FDCAN_ILS_TCL_Msk                         /*!<Transmission Completed Line                 */
17687 #define FDCAN_ILS_TCFL_Pos           (10U)
17688 #define FDCAN_ILS_TCFL_Msk           (0x1UL << FDCAN_ILS_TCFL_Pos)             /*!< 0x00000400 */
17689 #define FDCAN_ILS_TCFL               FDCAN_ILS_TCFL_Msk                        /*!<Transmission Cancellation Finished Line     */
17690 #define FDCAN_ILS_TFEL_Pos           (11U)
17691 #define FDCAN_ILS_TFEL_Msk           (0x1UL << FDCAN_ILS_TFEL_Pos)             /*!< 0x00000800 */
17692 #define FDCAN_ILS_TFEL               FDCAN_ILS_TFEL_Msk                        /*!<Tx FIFO Empty Line                          */
17693 #define FDCAN_ILS_TEFNL_Pos          (12U)
17694 #define FDCAN_ILS_TEFNL_Msk          (0x1UL << FDCAN_ILS_TEFNL_Pos)            /*!< 0x00001000 */
17695 #define FDCAN_ILS_TEFNL              FDCAN_ILS_TEFNL_Msk                       /*!<Tx Event FIFO New Entry Line                */
17696 #define FDCAN_ILS_TEFWL_Pos          (13U)
17697 #define FDCAN_ILS_TEFWL_Msk          (0x1UL << FDCAN_ILS_TEFWL_Pos)            /*!< 0x00002000 */
17698 #define FDCAN_ILS_TEFWL              FDCAN_ILS_TEFWL_Msk                       /*!<Tx Event FIFO Watermark Reached Line        */
17699 #define FDCAN_ILS_TEFFL_Pos          (14U)
17700 #define FDCAN_ILS_TEFFL_Msk          (0x1UL << FDCAN_ILS_TEFFL_Pos)            /*!< 0x00004000 */
17701 #define FDCAN_ILS_TEFFL              FDCAN_ILS_TEFFL_Msk                       /*!<Tx Event FIFO Full Line                     */
17702 #define FDCAN_ILS_TEFLL_Pos          (15U)
17703 #define FDCAN_ILS_TEFLL_Msk          (0x1UL << FDCAN_ILS_TEFLL_Pos)            /*!< 0x00008000 */
17704 #define FDCAN_ILS_TEFLL              FDCAN_ILS_TEFLL_Msk                       /*!<Tx Event FIFO Element Lost Line             */
17705 #define FDCAN_ILS_TSWL_Pos           (16U)
17706 #define FDCAN_ILS_TSWL_Msk           (0x1UL << FDCAN_ILS_TSWL_Pos)             /*!< 0x00010000 */
17707 #define FDCAN_ILS_TSWL               FDCAN_ILS_TSWL_Msk                        /*!<Timestamp Wraparound Line                   */
17708 #define FDCAN_ILS_MRAFL_Pos          (17U)
17709 #define FDCAN_ILS_MRAFL_Msk          (0x1UL << FDCAN_ILS_MRAFL_Pos)            /*!< 0x00020000 */
17710 #define FDCAN_ILS_MRAFL              FDCAN_ILS_MRAFL_Msk                       /*!<Message RAM Access Failure Line             */
17711 #define FDCAN_ILS_TOOL_Pos           (18U)
17712 #define FDCAN_ILS_TOOL_Msk           (0x1UL << FDCAN_ILS_TOOL_Pos)             /*!< 0x00040000 */
17713 #define FDCAN_ILS_TOOL               FDCAN_ILS_TOOL_Msk                        /*!<Timeout Occurred Line                       */
17714 #define FDCAN_ILS_DRXL_Pos           (19U)
17715 #define FDCAN_ILS_DRXL_Msk           (0x1UL << FDCAN_ILS_DRXL_Pos)             /*!< 0x00080000 */
17716 #define FDCAN_ILS_DRXL               FDCAN_ILS_DRXL_Msk                        /*!<Message stored to Dedicated Rx Buffer Line  */
17717 #define FDCAN_ILS_ELOL_Pos           (22U)
17718 #define FDCAN_ILS_ELOL_Msk           (0x1UL << FDCAN_ILS_ELOL_Pos)             /*!< 0x00400000 */
17719 #define FDCAN_ILS_ELOL               FDCAN_ILS_ELOL_Msk                        /*!<Error Logging Overflow Line                 */
17720 #define FDCAN_ILS_EPL_Pos            (23U)
17721 #define FDCAN_ILS_EPL_Msk            (0x1UL << FDCAN_ILS_EPL_Pos)              /*!< 0x00800000 */
17722 #define FDCAN_ILS_EPL                FDCAN_ILS_EPL_Msk                         /*!<Error Passive Line                          */
17723 #define FDCAN_ILS_EWL_Pos            (24U)
17724 #define FDCAN_ILS_EWL_Msk            (0x1UL << FDCAN_ILS_EWL_Pos)              /*!< 0x01000000 */
17725 #define FDCAN_ILS_EWL                FDCAN_ILS_EWL_Msk                         /*!<Warning Status Line                         */
17726 #define FDCAN_ILS_BOL_Pos            (25U)
17727 #define FDCAN_ILS_BOL_Msk            (0x1UL << FDCAN_ILS_BOL_Pos)              /*!< 0x02000000 */
17728 #define FDCAN_ILS_BOL                FDCAN_ILS_BOL_Msk                         /*!<Bus_Off Status Line                         */
17729 #define FDCAN_ILS_WDIL_Pos           (26U)
17730 #define FDCAN_ILS_WDIL_Msk           (0x1UL << FDCAN_ILS_WDIL_Pos)             /*!< 0x04000000 */
17731 #define FDCAN_ILS_WDIL               FDCAN_ILS_WDIL_Msk                        /*!<Watchdog Interrupt Line                     */
17732 #define FDCAN_ILS_PEAL_Pos           (27U)
17733 #define FDCAN_ILS_PEAL_Msk           (0x1UL << FDCAN_ILS_PEAL_Pos)             /*!< 0x08000000 */
17734 #define FDCAN_ILS_PEAL               FDCAN_ILS_PEAL_Msk                        /*!<Protocol Error in Arbitration Phase Line    */
17735 #define FDCAN_ILS_PEDL_Pos           (28U)
17736 #define FDCAN_ILS_PEDL_Msk           (0x1UL << FDCAN_ILS_PEDL_Pos)             /*!< 0x10000000 */
17737 #define FDCAN_ILS_PEDL               FDCAN_ILS_PEDL_Msk                        /*!<Protocol Error in Data Phase Line           */
17738 #define FDCAN_ILS_ARAL_Pos           (29U)
17739 #define FDCAN_ILS_ARAL_Msk           (0x1UL << FDCAN_ILS_ARAL_Pos)             /*!< 0x20000000 */
17740 #define FDCAN_ILS_ARAL               FDCAN_ILS_ARAL_Msk                        /*!<Access to Reserved Address Line             */
17741 
17742 /*****************  Bit definition for FDCAN_ILE register  ********************/
17743 #define FDCAN_ILE_EINT0_Pos          (0U)
17744 #define FDCAN_ILE_EINT0_Msk          (0x1UL << FDCAN_ILE_EINT0_Pos)            /*!< 0x00000001 */
17745 #define FDCAN_ILE_EINT0              FDCAN_ILE_EINT0_Msk                       /*!<Enable Interrupt Line 0                  */
17746 #define FDCAN_ILE_EINT1_Pos          (1U)
17747 #define FDCAN_ILE_EINT1_Msk          (0x1UL << FDCAN_ILE_EINT1_Pos)            /*!< 0x00000002 */
17748 #define FDCAN_ILE_EINT1              FDCAN_ILE_EINT1_Msk                       /*!<Enable Interrupt Line 1                  */
17749 
17750 /*****************  Bit definition for FDCAN_GFC register  ******************/
17751 #define FDCAN_GFC_RRFE_Pos           (0U)
17752 #define FDCAN_GFC_RRFE_Msk           (0x1UL << FDCAN_GFC_RRFE_Pos)             /*!< 0x00000001 */
17753 #define FDCAN_GFC_RRFE               FDCAN_GFC_RRFE_Msk                        /*!<Reject Remote Frames Extended             */
17754 #define FDCAN_GFC_RRFS_Pos           (1U)
17755 #define FDCAN_GFC_RRFS_Msk           (0x1UL << FDCAN_GFC_RRFS_Pos)             /*!< 0x00000002 */
17756 #define FDCAN_GFC_RRFS               FDCAN_GFC_RRFS_Msk                        /*!<Reject Remote Frames Standard             */
17757 #define FDCAN_GFC_ANFE_Pos           (2U)
17758 #define FDCAN_GFC_ANFE_Msk           (0x3UL << FDCAN_GFC_ANFE_Pos)             /*!< 0x0000000C */
17759 #define FDCAN_GFC_ANFE               FDCAN_GFC_ANFE_Msk                        /*!<Accept Non-matching Frames Extended       */
17760 #define FDCAN_GFC_ANFS_Pos           (4U)
17761 #define FDCAN_GFC_ANFS_Msk           (0x3UL << FDCAN_GFC_ANFS_Pos)             /*!< 0x00000030 */
17762 #define FDCAN_GFC_ANFS               FDCAN_GFC_ANFS_Msk                        /*!<Accept Non-matching Frames Standard       */
17763 
17764 /*****************  Bit definition for FDCAN_SIDFC register  ********************/
17765 #define FDCAN_SIDFC_FLSSA_Pos        (2U)
17766 #define FDCAN_SIDFC_FLSSA_Msk        (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos)       /*!< 0x0000FFFC */
17767 #define FDCAN_SIDFC_FLSSA            FDCAN_SIDFC_FLSSA_Msk                     /*!<Filter List Standard Start Address        */
17768 #define FDCAN_SIDFC_LSS_Pos          (16U)
17769 #define FDCAN_SIDFC_LSS_Msk          (0xFFUL << FDCAN_SIDFC_LSS_Pos)           /*!< 0x00FF0000 */
17770 #define FDCAN_SIDFC_LSS              FDCAN_SIDFC_LSS_Msk                       /*!<List Size Standard                        */
17771 
17772 /*****************  Bit definition for FDCAN_XIDFC register  ********************/
17773 #define FDCAN_XIDFC_FLESA_Pos        (2U)
17774 #define FDCAN_XIDFC_FLESA_Msk        (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos)       /*!< 0x0000FFFC */
17775 #define FDCAN_XIDFC_FLESA            FDCAN_XIDFC_FLESA_Msk                     /*!<Filter List Standard Start Address        */
17776 #define FDCAN_XIDFC_LSE_Pos          (16U)
17777 #define FDCAN_XIDFC_LSE_Msk          (0x7FUL << FDCAN_XIDFC_LSE_Pos)           /*!< 0x007F0000 */
17778 #define FDCAN_XIDFC_LSE              FDCAN_XIDFC_LSE_Msk                       /*!<List Size Extended                        */
17779 
17780 /*****************  Bit definition for FDCAN_XIDAM register  ******************/
17781 #define FDCAN_XIDAM_EIDM_Pos         (0U)
17782 #define FDCAN_XIDAM_EIDM_Msk         (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)    /*!< 0x1FFFFFFF */
17783 #define FDCAN_XIDAM_EIDM             FDCAN_XIDAM_EIDM_Msk                      /*!<Extended ID Mask                         */
17784 
17785 /*****************  Bit definition for FDCAN_HPMS register  *******************/
17786 #define FDCAN_HPMS_BIDX_Pos          (0U)
17787 #define FDCAN_HPMS_BIDX_Msk          (0x3FUL << FDCAN_HPMS_BIDX_Pos)           /*!< 0x0000003F */
17788 #define FDCAN_HPMS_BIDX              FDCAN_HPMS_BIDX_Msk                       /*!<Buffer Index                             */
17789 #define FDCAN_HPMS_MSI_Pos           (6U)
17790 #define FDCAN_HPMS_MSI_Msk           (0x3UL << FDCAN_HPMS_MSI_Pos)             /*!< 0x000000C0 */
17791 #define FDCAN_HPMS_MSI               FDCAN_HPMS_MSI_Msk                        /*!<Message Storage Indicator                */
17792 #define FDCAN_HPMS_FIDX_Pos          (8U)
17793 #define FDCAN_HPMS_FIDX_Msk          (0x7FUL << FDCAN_HPMS_FIDX_Pos)           /*!< 0x00007F00 */
17794 #define FDCAN_HPMS_FIDX              FDCAN_HPMS_FIDX_Msk                       /*!<Filter Index                             */
17795 #define FDCAN_HPMS_FLST_Pos          (15U)
17796 #define FDCAN_HPMS_FLST_Msk          (0x1UL << FDCAN_HPMS_FLST_Pos)            /*!< 0x00008000 */
17797 #define FDCAN_HPMS_FLST              FDCAN_HPMS_FLST_Msk                       /*!<Filter List                              */
17798 
17799 /*****************  Bit definition for FDCAN_NDAT1 register  ********************/
17800 #define FDCAN_NDAT1_ND0_Pos          (0U)
17801 #define FDCAN_NDAT1_ND0_Msk          (0x1UL << FDCAN_NDAT1_ND0_Pos)            /*!< 0x00000001 */
17802 #define FDCAN_NDAT1_ND0              FDCAN_NDAT1_ND0_Msk                       /*!<New Data flag of Rx Buffer 0              */
17803 #define FDCAN_NDAT1_ND1_Pos          (1U)
17804 #define FDCAN_NDAT1_ND1_Msk          (0x1UL << FDCAN_NDAT1_ND1_Pos)            /*!< 0x00000002 */
17805 #define FDCAN_NDAT1_ND1              FDCAN_NDAT1_ND1_Msk                       /*!<New Data flag of Rx Buffer 1              */
17806 #define FDCAN_NDAT1_ND2_Pos          (2U)
17807 #define FDCAN_NDAT1_ND2_Msk          (0x1UL << FDCAN_NDAT1_ND2_Pos)            /*!< 0x00000004 */
17808 #define FDCAN_NDAT1_ND2              FDCAN_NDAT1_ND2_Msk                       /*!<New Data flag of Rx Buffer 2              */
17809 #define FDCAN_NDAT1_ND3_Pos          (3U)
17810 #define FDCAN_NDAT1_ND3_Msk          (0x1UL << FDCAN_NDAT1_ND3_Pos)            /*!< 0x00000008 */
17811 #define FDCAN_NDAT1_ND3              FDCAN_NDAT1_ND3_Msk                       /*!<New Data flag of Rx Buffer 3              */
17812 #define FDCAN_NDAT1_ND4_Pos          (4U)
17813 #define FDCAN_NDAT1_ND4_Msk          (0x1UL << FDCAN_NDAT1_ND4_Pos)            /*!< 0x00000010 */
17814 #define FDCAN_NDAT1_ND4              FDCAN_NDAT1_ND4_Msk                       /*!<New Data flag of Rx Buffer 4              */
17815 #define FDCAN_NDAT1_ND5_Pos          (5U)
17816 #define FDCAN_NDAT1_ND5_Msk          (0x1UL << FDCAN_NDAT1_ND5_Pos)            /*!< 0x00000020 */
17817 #define FDCAN_NDAT1_ND5              FDCAN_NDAT1_ND5_Msk                       /*!<New Data flag of Rx Buffer 5              */
17818 #define FDCAN_NDAT1_ND6_Pos          (6U)
17819 #define FDCAN_NDAT1_ND6_Msk          (0x1UL << FDCAN_NDAT1_ND6_Pos)            /*!< 0x00000040 */
17820 #define FDCAN_NDAT1_ND6              FDCAN_NDAT1_ND6_Msk                       /*!<New Data flag of Rx Buffer 6              */
17821 #define FDCAN_NDAT1_ND7_Pos          (7U)
17822 #define FDCAN_NDAT1_ND7_Msk          (0x1UL << FDCAN_NDAT1_ND7_Pos)            /*!< 0x00000080 */
17823 #define FDCAN_NDAT1_ND7              FDCAN_NDAT1_ND7_Msk                       /*!<New Data flag of Rx Buffer 7              */
17824 #define FDCAN_NDAT1_ND8_Pos          (8U)
17825 #define FDCAN_NDAT1_ND8_Msk          (0x1UL << FDCAN_NDAT1_ND8_Pos)            /*!< 0x00000100 */
17826 #define FDCAN_NDAT1_ND8              FDCAN_NDAT1_ND8_Msk                       /*!<New Data flag of Rx Buffer 8              */
17827 #define FDCAN_NDAT1_ND9_Pos              (9U)
17828 #define FDCAN_NDAT1_ND9_Msk          (0x1UL << FDCAN_NDAT1_ND9_Pos)            /*!< 0x00000200 */
17829 #define FDCAN_NDAT1_ND9              FDCAN_NDAT1_ND9_Msk                       /*!<New Data flag of Rx Buffer 9              */
17830 #define FDCAN_NDAT1_ND10_Pos            (10U)
17831 #define FDCAN_NDAT1_ND10_Msk         (0x1UL << FDCAN_NDAT1_ND10_Pos)           /*!< 0x00000400 */
17832 #define FDCAN_NDAT1_ND10             FDCAN_NDAT1_ND10_Msk                      /*!<New Data flag of Rx Buffer 10             */
17833 #define FDCAN_NDAT1_ND11_Pos         (11U)
17834 #define FDCAN_NDAT1_ND11_Msk         (0x1UL << FDCAN_NDAT1_ND11_Pos)           /*!< 0x00000800 */
17835 #define FDCAN_NDAT1_ND11             FDCAN_NDAT1_ND11_Msk                      /*!<New Data flag of Rx Buffer 11             */
17836 #define FDCAN_NDAT1_ND12_Pos         (12U)
17837 #define FDCAN_NDAT1_ND12_Msk         (0x1UL << FDCAN_NDAT1_ND12_Pos)           /*!< 0x00001000 */
17838 #define FDCAN_NDAT1_ND12             FDCAN_NDAT1_ND12_Msk                      /*!<New Data flag of Rx Buffer 12             */
17839 #define FDCAN_NDAT1_ND13_Pos         (13U)
17840 #define FDCAN_NDAT1_ND13_Msk         (0x1UL << FDCAN_NDAT1_ND13_Pos)           /*!< 0x00002000 */
17841 #define FDCAN_NDAT1_ND13             FDCAN_NDAT1_ND13_Msk                      /*!<New Data flag of Rx Buffer 13             */
17842 #define FDCAN_NDAT1_ND14_Pos         (14U)
17843 #define FDCAN_NDAT1_ND14_Msk         (0x1UL << FDCAN_NDAT1_ND14_Pos)           /*!< 0x00004000 */
17844 #define FDCAN_NDAT1_ND14             FDCAN_NDAT1_ND14_Msk                      /*!<New Data flag of Rx Buffer 14             */
17845 #define FDCAN_NDAT1_ND15_Pos         (15U)
17846 #define FDCAN_NDAT1_ND15_Msk         (0x1UL << FDCAN_NDAT1_ND15_Pos)           /*!< 0x00008000 */
17847 #define FDCAN_NDAT1_ND15             FDCAN_NDAT1_ND15_Msk                      /*!<New Data flag of Rx Buffer 15             */
17848 #define FDCAN_NDAT1_ND16_Pos         (16U)
17849 #define FDCAN_NDAT1_ND16_Msk         (0x1UL << FDCAN_NDAT1_ND16_Pos)           /*!< 0x00010000 */
17850 #define FDCAN_NDAT1_ND16             FDCAN_NDAT1_ND16_Msk                      /*!<New Data flag of Rx Buffer 16             */
17851 #define FDCAN_NDAT1_ND17_Pos         (17U)
17852 #define FDCAN_NDAT1_ND17_Msk         (0x1UL << FDCAN_NDAT1_ND17_Pos)           /*!< 0x00020000 */
17853 #define FDCAN_NDAT1_ND17             FDCAN_NDAT1_ND17_Msk                      /*!<New Data flag of Rx Buffer 17             */
17854 #define FDCAN_NDAT1_ND18_Pos         (18U)
17855 #define FDCAN_NDAT1_ND18_Msk         (0x1UL << FDCAN_NDAT1_ND18_Pos)           /*!< 0x00040000 */
17856 #define FDCAN_NDAT1_ND18             FDCAN_NDAT1_ND18_Msk                      /*!<New Data flag of Rx Buffer 18             */
17857 #define FDCAN_NDAT1_ND19_Pos         (19U)
17858 #define FDCAN_NDAT1_ND19_Msk         (0x1UL << FDCAN_NDAT1_ND19_Pos)           /*!< 0x00080000 */
17859 #define FDCAN_NDAT1_ND19             FDCAN_NDAT1_ND19_Msk                      /*!<New Data flag of Rx Buffer 19             */
17860 #define FDCAN_NDAT1_ND20_Pos         (20U)
17861 #define FDCAN_NDAT1_ND20_Msk         (0x1UL << FDCAN_NDAT1_ND20_Pos)           /*!< 0x00100000 */
17862 #define FDCAN_NDAT1_ND20             FDCAN_NDAT1_ND20_Msk                      /*!<New Data flag of Rx Buffer 20             */
17863 #define FDCAN_NDAT1_ND21_Pos         (21U)
17864 #define FDCAN_NDAT1_ND21_Msk         (0x1UL << FDCAN_NDAT1_ND21_Pos)           /*!< 0x00200000 */
17865 #define FDCAN_NDAT1_ND21             FDCAN_NDAT1_ND21_Msk                      /*!<New Data flag of Rx Buffer 21             */
17866 #define FDCAN_NDAT1_ND22_Pos         (22U)
17867 #define FDCAN_NDAT1_ND22_Msk         (0x1UL << FDCAN_NDAT1_ND22_Pos)           /*!< 0x00400000 */
17868 #define FDCAN_NDAT1_ND22             FDCAN_NDAT1_ND22_Msk                      /*!<New Data flag of Rx Buffer 22             */
17869 #define FDCAN_NDAT1_ND23_Pos         (23U)
17870 #define FDCAN_NDAT1_ND23_Msk         (0x1UL << FDCAN_NDAT1_ND23_Pos)           /*!< 0x00800000 */
17871 #define FDCAN_NDAT1_ND23             FDCAN_NDAT1_ND23_Msk                      /*!<New Data flag of Rx Buffer 23             */
17872 #define FDCAN_NDAT1_ND24_Pos         (24U)
17873 #define FDCAN_NDAT1_ND24_Msk         (0x1UL << FDCAN_NDAT1_ND24_Pos)           /*!< 0x01000000 */
17874 #define FDCAN_NDAT1_ND24             FDCAN_NDAT1_ND24_Msk                      /*!<New Data flag of Rx Buffer 24             */
17875 #define FDCAN_NDAT1_ND25_Pos         (25U)
17876 #define FDCAN_NDAT1_ND25_Msk         (0x1UL << FDCAN_NDAT1_ND25_Pos)           /*!< 0x02000000 */
17877 #define FDCAN_NDAT1_ND25             FDCAN_NDAT1_ND25_Msk                      /*!<New Data flag of Rx Buffer 25             */
17878 #define FDCAN_NDAT1_ND26_Pos         (26U)
17879 #define FDCAN_NDAT1_ND26_Msk         (0x1UL << FDCAN_NDAT1_ND26_Pos)           /*!< 0x04000000 */
17880 #define FDCAN_NDAT1_ND26             FDCAN_NDAT1_ND26_Msk                      /*!<New Data flag of Rx Buffer 26             */
17881 #define FDCAN_NDAT1_ND27_Pos         (27U)
17882 #define FDCAN_NDAT1_ND27_Msk         (0x1UL << FDCAN_NDAT1_ND27_Pos)           /*!< 0x08000000 */
17883 #define FDCAN_NDAT1_ND27             FDCAN_NDAT1_ND27_Msk                      /*!<New Data flag of Rx Buffer 27             */
17884 #define FDCAN_NDAT1_ND28_Pos         (28U)
17885 #define FDCAN_NDAT1_ND28_Msk         (0x1UL << FDCAN_NDAT1_ND28_Pos)           /*!< 0x10000000 */
17886 #define FDCAN_NDAT1_ND28             FDCAN_NDAT1_ND28_Msk                      /*!<New Data flag of Rx Buffer 28             */
17887 #define FDCAN_NDAT1_ND29_Pos         (29U)
17888 #define FDCAN_NDAT1_ND29_Msk         (0x1UL << FDCAN_NDAT1_ND29_Pos)           /*!< 0x20000000 */
17889 #define FDCAN_NDAT1_ND29             FDCAN_NDAT1_ND29_Msk                      /*!<New Data flag of Rx Buffer 29             */
17890 #define FDCAN_NDAT1_ND30_Pos         (30U)
17891 #define FDCAN_NDAT1_ND30_Msk         (0x1UL << FDCAN_NDAT1_ND30_Pos)           /*!< 0x40000000 */
17892 #define FDCAN_NDAT1_ND30             FDCAN_NDAT1_ND30_Msk                      /*!<New Data flag of Rx Buffer 30             */
17893 #define FDCAN_NDAT1_ND31_Pos         (31U)
17894 #define FDCAN_NDAT1_ND31_Msk         (0x1UL << FDCAN_NDAT1_ND31_Pos)           /*!< 0x80000000 */
17895 #define FDCAN_NDAT1_ND31             FDCAN_NDAT1_ND31_Msk                      /*!<New Data flag of Rx Buffer 31             */
17896 
17897 /*****************  Bit definition for FDCAN_NDAT2 register  ********************/
17898 #define FDCAN_NDAT2_ND32_Pos         (0U)
17899 #define FDCAN_NDAT2_ND32_Msk         (0x1UL << FDCAN_NDAT2_ND32_Pos)           /*!< 0x00000001 */
17900 #define FDCAN_NDAT2_ND32             FDCAN_NDAT2_ND32_Msk                      /*!<New Data flag of Rx Buffer 32             */
17901 #define FDCAN_NDAT2_ND33_Pos         (1U)
17902 #define FDCAN_NDAT2_ND33_Msk         (0x1UL << FDCAN_NDAT2_ND33_Pos)           /*!< 0x00000002 */
17903 #define FDCAN_NDAT2_ND33             FDCAN_NDAT2_ND33_Msk                      /*!<New Data flag of Rx Buffer 33             */
17904 #define FDCAN_NDAT2_ND34_Pos         (2U)
17905 #define FDCAN_NDAT2_ND34_Msk         (0x1UL << FDCAN_NDAT2_ND34_Pos)           /*!< 0x00000004 */
17906 #define FDCAN_NDAT2_ND34             FDCAN_NDAT2_ND34_Msk                      /*!<New Data flag of Rx Buffer 34             */
17907 #define FDCAN_NDAT2_ND35_Pos         (3U)
17908 #define FDCAN_NDAT2_ND35_Msk         (0x1UL << FDCAN_NDAT2_ND35_Pos)           /*!< 0x00000008 */
17909 #define FDCAN_NDAT2_ND35             FDCAN_NDAT2_ND35_Msk                      /*!<New Data flag of Rx Buffer 35             */
17910 #define FDCAN_NDAT2_ND36_Pos         (4U)
17911 #define FDCAN_NDAT2_ND36_Msk         (0x1UL << FDCAN_NDAT2_ND36_Pos)           /*!< 0x00000010 */
17912 #define FDCAN_NDAT2_ND36             FDCAN_NDAT2_ND36_Msk                      /*!<New Data flag of Rx Buffer 36             */
17913 #define FDCAN_NDAT2_ND37_Pos         (5U)
17914 #define FDCAN_NDAT2_ND37_Msk         (0x1UL << FDCAN_NDAT2_ND37_Pos)           /*!< 0x00000020 */
17915 #define FDCAN_NDAT2_ND37             FDCAN_NDAT2_ND37_Msk                      /*!<New Data flag of Rx Buffer 37             */
17916 #define FDCAN_NDAT2_ND38_Pos         (6U)
17917 #define FDCAN_NDAT2_ND38_Msk         (0x1UL << FDCAN_NDAT2_ND38_Pos)           /*!< 0x00000040 */
17918 #define FDCAN_NDAT2_ND38             FDCAN_NDAT2_ND38_Msk                      /*!<New Data flag of Rx Buffer 38             */
17919 #define FDCAN_NDAT2_ND39_Pos         (7U)
17920 #define FDCAN_NDAT2_ND39_Msk         (0x1UL << FDCAN_NDAT2_ND39_Pos)           /*!< 0x00000080 */
17921 #define FDCAN_NDAT2_ND39             FDCAN_NDAT2_ND39_Msk                      /*!<New Data flag of Rx Buffer 39             */
17922 #define FDCAN_NDAT2_ND40_Pos         (8U)
17923 #define FDCAN_NDAT2_ND40_Msk         (0x1UL << FDCAN_NDAT2_ND40_Pos)           /*!< 0x00000100 */
17924 #define FDCAN_NDAT2_ND40             FDCAN_NDAT2_ND40_Msk                      /*!<New Data flag of Rx Buffer 40             */
17925 #define FDCAN_NDAT2_ND41_Pos         (9U)
17926 #define FDCAN_NDAT2_ND41_Msk         (0x1UL << FDCAN_NDAT2_ND41_Pos)           /*!< 0x00000200 */
17927 #define FDCAN_NDAT2_ND41             FDCAN_NDAT2_ND41_Msk                      /*!<New Data flag of Rx Buffer 41             */
17928 #define FDCAN_NDAT2_ND42_Pos         (10U)
17929 #define FDCAN_NDAT2_ND42_Msk         (0x1UL << FDCAN_NDAT2_ND42_Pos)           /*!< 0x00000400 */
17930 #define FDCAN_NDAT2_ND42             FDCAN_NDAT2_ND42_Msk                      /*!<New Data flag of Rx Buffer 42             */
17931 #define FDCAN_NDAT2_ND43_Pos         (11U)
17932 #define FDCAN_NDAT2_ND43_Msk         (0x1UL << FDCAN_NDAT2_ND43_Pos)           /*!< 0x00000800 */
17933 #define FDCAN_NDAT2_ND43             FDCAN_NDAT2_ND43_Msk                      /*!<New Data flag of Rx Buffer 43             */
17934 #define FDCAN_NDAT2_ND44_Pos         (12U)
17935 #define FDCAN_NDAT2_ND44_Msk         (0x1UL << FDCAN_NDAT2_ND44_Pos)           /*!< 0x00001000 */
17936 #define FDCAN_NDAT2_ND44             FDCAN_NDAT2_ND44_Msk                      /*!<New Data flag of Rx Buffer 44             */
17937 #define FDCAN_NDAT2_ND45_Pos         (13U)
17938 #define FDCAN_NDAT2_ND45_Msk         (0x1UL << FDCAN_NDAT2_ND45_Pos)           /*!< 0x00002000 */
17939 #define FDCAN_NDAT2_ND45             FDCAN_NDAT2_ND45_Msk                      /*!<New Data flag of Rx Buffer 45             */
17940 #define FDCAN_NDAT2_ND46_Pos         (14U)
17941 #define FDCAN_NDAT2_ND46_Msk         (0x1UL << FDCAN_NDAT2_ND46_Pos)           /*!< 0x00004000 */
17942 #define FDCAN_NDAT2_ND46             FDCAN_NDAT2_ND46_Msk                      /*!<New Data flag of Rx Buffer 46             */
17943 #define FDCAN_NDAT2_ND47_Pos         (15U)
17944 #define FDCAN_NDAT2_ND47_Msk         (0x1UL << FDCAN_NDAT2_ND47_Pos)           /*!< 0x00008000 */
17945 #define FDCAN_NDAT2_ND47             FDCAN_NDAT2_ND47_Msk                      /*!<New Data flag of Rx Buffer 47             */
17946 #define FDCAN_NDAT2_ND48_Pos         (16U)
17947 #define FDCAN_NDAT2_ND48_Msk         (0x1UL << FDCAN_NDAT2_ND48_Pos)           /*!< 0x00010000 */
17948 #define FDCAN_NDAT2_ND48             FDCAN_NDAT2_ND48_Msk                      /*!<New Data flag of Rx Buffer 48             */
17949 #define FDCAN_NDAT2_ND49_Pos         (17U)
17950 #define FDCAN_NDAT2_ND49_Msk         (0x1UL << FDCAN_NDAT2_ND49_Pos)           /*!< 0x00020000 */
17951 #define FDCAN_NDAT2_ND49             FDCAN_NDAT2_ND49_Msk                      /*!<New Data flag of Rx Buffer 49             */
17952 #define FDCAN_NDAT2_ND50_Pos         (18U)
17953 #define FDCAN_NDAT2_ND50_Msk         (0x1UL << FDCAN_NDAT2_ND50_Pos)           /*!< 0x00040000 */
17954 #define FDCAN_NDAT2_ND50             FDCAN_NDAT2_ND50_Msk                      /*!<New Data flag of Rx Buffer 50             */
17955 #define FDCAN_NDAT2_ND51_Pos         (19U)
17956 #define FDCAN_NDAT2_ND51_Msk         (0x1UL << FDCAN_NDAT2_ND51_Pos)           /*!< 0x00080000 */
17957 #define FDCAN_NDAT2_ND51             FDCAN_NDAT2_ND51_Msk                      /*!<New Data flag of Rx Buffer 51             */
17958 #define FDCAN_NDAT2_ND52_Pos         (20U)
17959 #define FDCAN_NDAT2_ND52_Msk         (0x1UL << FDCAN_NDAT2_ND52_Pos)           /*!< 0x00100000 */
17960 #define FDCAN_NDAT2_ND52             FDCAN_NDAT2_ND52_Msk                      /*!<New Data flag of Rx Buffer 52             */
17961 #define FDCAN_NDAT2_ND53_Pos         (21U)
17962 #define FDCAN_NDAT2_ND53_Msk         (0x1UL << FDCAN_NDAT2_ND53_Pos)           /*!< 0x00200000 */
17963 #define FDCAN_NDAT2_ND53             FDCAN_NDAT2_ND53_Msk                      /*!<New Data flag of Rx Buffer 53             */
17964 #define FDCAN_NDAT2_ND54_Pos         (22U)
17965 #define FDCAN_NDAT2_ND54_Msk         (0x1UL << FDCAN_NDAT2_ND54_Pos)           /*!< 0x00400000 */
17966 #define FDCAN_NDAT2_ND54             FDCAN_NDAT2_ND54_Msk                      /*!<New Data flag of Rx Buffer 54             */
17967 #define FDCAN_NDAT2_ND55_Pos         (23U)
17968 #define FDCAN_NDAT2_ND55_Msk         (0x1UL << FDCAN_NDAT2_ND55_Pos)           /*!< 0x00800000 */
17969 #define FDCAN_NDAT2_ND55             FDCAN_NDAT2_ND55_Msk                      /*!<New Data flag of Rx Buffer 55             */
17970 #define FDCAN_NDAT2_ND56_Pos         (24U)
17971 #define FDCAN_NDAT2_ND56_Msk         (0x1UL << FDCAN_NDAT2_ND56_Pos)           /*!< 0x01000000 */
17972 #define FDCAN_NDAT2_ND56             FDCAN_NDAT2_ND56_Msk                      /*!<New Data flag of Rx Buffer 56             */
17973 #define FDCAN_NDAT2_ND57_Pos         (25U)
17974 #define FDCAN_NDAT2_ND57_Msk         (0x1UL << FDCAN_NDAT2_ND57_Pos)           /*!< 0x02000000 */
17975 #define FDCAN_NDAT2_ND57             FDCAN_NDAT2_ND57_Msk                      /*!<New Data flag of Rx Buffer 57             */
17976 #define FDCAN_NDAT2_ND58_Pos         (26U)
17977 #define FDCAN_NDAT2_ND58_Msk         (0x1UL << FDCAN_NDAT2_ND58_Pos)           /*!< 0x04000000 */
17978 #define FDCAN_NDAT2_ND58             FDCAN_NDAT2_ND58_Msk                      /*!<New Data flag of Rx Buffer 58             */
17979 #define FDCAN_NDAT2_ND59_Pos         (27U)
17980 #define FDCAN_NDAT2_ND59_Msk         (0x1UL << FDCAN_NDAT2_ND59_Pos)           /*!< 0x08000000 */
17981 #define FDCAN_NDAT2_ND59             FDCAN_NDAT2_ND59_Msk                      /*!<New Data flag of Rx Buffer 59             */
17982 #define FDCAN_NDAT2_ND60_Pos         (28U)
17983 #define FDCAN_NDAT2_ND60_Msk         (0x1UL << FDCAN_NDAT2_ND60_Pos)           /*!< 0x10000000 */
17984 #define FDCAN_NDAT2_ND60             FDCAN_NDAT2_ND60_Msk                      /*!<New Data flag of Rx Buffer 60             */
17985 #define FDCAN_NDAT2_ND61_Pos         (29U)
17986 #define FDCAN_NDAT2_ND61_Msk         (0x1UL << FDCAN_NDAT2_ND61_Pos)           /*!< 0x20000000 */
17987 #define FDCAN_NDAT2_ND61             FDCAN_NDAT2_ND61_Msk                      /*!<New Data flag of Rx Buffer 61             */
17988 #define FDCAN_NDAT2_ND62_Pos         (30U)
17989 #define FDCAN_NDAT2_ND62_Msk         (0x1UL << FDCAN_NDAT2_ND62_Pos)           /*!< 0x40000000 */
17990 #define FDCAN_NDAT2_ND62             FDCAN_NDAT2_ND62_Msk                      /*!<New Data flag of Rx Buffer 62             */
17991 #define FDCAN_NDAT2_ND63_Pos         (31U)
17992 #define FDCAN_NDAT2_ND63_Msk         (0x1UL << FDCAN_NDAT2_ND63_Pos)           /*!< 0x80000000 */
17993 #define FDCAN_NDAT2_ND63             FDCAN_NDAT2_ND63_Msk                      /*!<New Data flag of Rx Buffer 63             */
17994 
17995 /*****************  Bit definition for FDCAN_RXF0C register  ********************/
17996 #define FDCAN_RXF0C_F0SA_Pos         (2U)
17997 #define FDCAN_RXF0C_F0SA_Msk         (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos)        /*!< 0x0000FFFC */
17998 #define FDCAN_RXF0C_F0SA             FDCAN_RXF0C_F0SA_Msk                      /*!<Rx FIFO 0 Start Address                   */
17999 #define FDCAN_RXF0C_F0S_Pos          (16U)
18000 #define FDCAN_RXF0C_F0S_Msk          (0x7FUL << FDCAN_RXF0C_F0S_Pos)           /*!< 0x007F0000 */
18001 #define FDCAN_RXF0C_F0S              FDCAN_RXF0C_F0S_Msk                       /*!<Number of Rx FIFO 0 elements              */
18002 #define FDCAN_RXF0C_F0WM_Pos         (24U)
18003 #define FDCAN_RXF0C_F0WM_Msk         (0x7FUL << FDCAN_RXF0C_F0WM_Pos)          /*!< 0x7F000000 */
18004 #define FDCAN_RXF0C_F0WM             FDCAN_RXF0C_F0WM_Msk                      /*!<FIFO 0 Watermark                          */
18005 #define FDCAN_RXF0C_F0OM_Pos         (31U)
18006 #define FDCAN_RXF0C_F0OM_Msk         (0x1UL << FDCAN_RXF0C_F0OM_Pos)           /*!< 0x80000000 */
18007 #define FDCAN_RXF0C_F0OM             FDCAN_RXF0C_F0OM_Msk                      /*!<FIFO 0 Operation Mode                     */
18008 
18009 /*****************  Bit definition for FDCAN_RXF0S register  ******************/
18010 #define FDCAN_RXF0S_F0FL_Pos         (0U)
18011 #define FDCAN_RXF0S_F0FL_Msk         (0x7FUL << FDCAN_RXF0S_F0FL_Pos)          /*!< 0x0000007F */
18012 #define FDCAN_RXF0S_F0FL             FDCAN_RXF0S_F0FL_Msk                      /*!<Rx FIFO 0 Fill Level                     */
18013 #define FDCAN_RXF0S_F0GI_Pos         (8U)
18014 #define FDCAN_RXF0S_F0GI_Msk         (0x3FUL << FDCAN_RXF0S_F0GI_Pos)          /*!< 0x00003F00 */
18015 #define FDCAN_RXF0S_F0GI             FDCAN_RXF0S_F0GI_Msk                      /*!<Rx FIFO 0 Get Index                      */
18016 #define FDCAN_RXF0S_F0PI_Pos         (16U)
18017 #define FDCAN_RXF0S_F0PI_Msk         (0x3FUL << FDCAN_RXF0S_F0PI_Pos)          /*!< 0x003F0000 */
18018 #define FDCAN_RXF0S_F0PI             FDCAN_RXF0S_F0PI_Msk                      /*!<Rx FIFO 0 Put Index                      */
18019 #define FDCAN_RXF0S_F0F_Pos          (24U)
18020 #define FDCAN_RXF0S_F0F_Msk          (0x1UL << FDCAN_RXF0S_F0F_Pos)            /*!< 0x01000000 */
18021 #define FDCAN_RXF0S_F0F              FDCAN_RXF0S_F0F_Msk                       /*!<Rx FIFO 0 Full                           */
18022 #define FDCAN_RXF0S_RF0L_Pos         (25U)
18023 #define FDCAN_RXF0S_RF0L_Msk         (0x1UL << FDCAN_RXF0S_RF0L_Pos)           /*!< 0x02000000 */
18024 #define FDCAN_RXF0S_RF0L             FDCAN_RXF0S_RF0L_Msk                      /*!<Rx FIFO 0 Message Lost                   */
18025 
18026 /*****************  Bit definition for FDCAN_RXF0A register  ******************/
18027 #define FDCAN_RXF0A_F0AI_Pos         (0U)
18028 #define FDCAN_RXF0A_F0AI_Msk         (0x3FUL << FDCAN_RXF0A_F0AI_Pos)          /*!< 0x0000003F */
18029 #define FDCAN_RXF0A_F0AI             FDCAN_RXF0A_F0AI_Msk                      /*!<Rx FIFO 0 Acknowledge Index              */
18030 
18031 /*****************  Bit definition for FDCAN_RXBC register  ********************/
18032 #define FDCAN_RXBC_RBSA_Pos          (2U)
18033 #define FDCAN_RXBC_RBSA_Msk          (0x3FFFUL << FDCAN_RXBC_RBSA_Pos)         /*!< 0x0000FFFC */
18034 #define FDCAN_RXBC_RBSA              FDCAN_RXBC_RBSA_Msk                       /*!<Rx Buffer Start Address                   */
18035 
18036 /*****************  Bit definition for FDCAN_RXF1C register  ******************/
18037 #define FDCAN_RXF1C_F1SA_Pos         (2U)
18038 #define FDCAN_RXF1C_F1SA_Msk         (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos)        /*!< 0x0000FFFC */
18039 #define FDCAN_RXF1C_F1SA             FDCAN_RXF1C_F1SA_Msk                      /*!<Rx FIFO 1 Start Address                   */
18040 #define FDCAN_RXF1C_F1S_Pos          (16U)
18041 #define FDCAN_RXF1C_F1S_Msk          (0x7FUL << FDCAN_RXF1C_F1S_Pos)           /*!< 0x007F0000 */
18042 #define FDCAN_RXF1C_F1S              FDCAN_RXF1C_F1S_Msk                       /*!<Number of Rx FIFO 1 elements              */
18043 #define FDCAN_RXF1C_F1WM_Pos         (24U)
18044 #define FDCAN_RXF1C_F1WM_Msk         (0x7FUL << FDCAN_RXF1C_F1WM_Pos)          /*!< 0x7F000000 */
18045 #define FDCAN_RXF1C_F1WM             FDCAN_RXF1C_F1WM_Msk                      /*!<Rx FIFO 1 Watermark                       */
18046 #define FDCAN_RXF1C_F1OM_Pos         (31U)
18047 #define FDCAN_RXF1C_F1OM_Msk         (0x1UL << FDCAN_RXF1C_F1OM_Pos)           /*!< 0x80000000 */
18048 #define FDCAN_RXF1C_F1OM             FDCAN_RXF1C_F1OM_Msk                      /*!<FIFO 1 Operation Mode                     */
18049 
18050 /*****************  Bit definition for FDCAN_RXF1S register  ******************/
18051 #define FDCAN_RXF1S_F1FL_Pos         (0U)
18052 #define FDCAN_RXF1S_F1FL_Msk         (0x7FUL << FDCAN_RXF1S_F1FL_Pos)          /*!< 0x0000007F */
18053 #define FDCAN_RXF1S_F1FL             FDCAN_RXF1S_F1FL_Msk                      /*!<Rx FIFO 1 Fill Level                     */
18054 #define FDCAN_RXF1S_F1GI_Pos         (8U)
18055 #define FDCAN_RXF1S_F1GI_Msk         (0x3FUL << FDCAN_RXF1S_F1GI_Pos)          /*!< 0x00003F00 */
18056 #define FDCAN_RXF1S_F1GI             FDCAN_RXF1S_F1GI_Msk                      /*!<Rx FIFO 1 Get Index                      */
18057 #define FDCAN_RXF1S_F1PI_Pos         (16U)
18058 #define FDCAN_RXF1S_F1PI_Msk         (0x3FUL << FDCAN_RXF1S_F1PI_Pos)          /*!< 0x003F0000 */
18059 #define FDCAN_RXF1S_F1PI             FDCAN_RXF1S_F1PI_Msk                      /*!<Rx FIFO 1 Put Index                      */
18060 #define FDCAN_RXF1S_F1F_Pos          (24U)
18061 #define FDCAN_RXF1S_F1F_Msk          (0x1UL << FDCAN_RXF1S_F1F_Pos)            /*!< 0x01000000 */
18062 #define FDCAN_RXF1S_F1F              FDCAN_RXF1S_F1F_Msk                       /*!<Rx FIFO 1 Full                           */
18063 #define FDCAN_RXF1S_RF1L_Pos         (25U)
18064 #define FDCAN_RXF1S_RF1L_Msk         (0x1UL << FDCAN_RXF1S_RF1L_Pos)           /*!< 0x02000000 */
18065 #define FDCAN_RXF1S_RF1L             FDCAN_RXF1S_RF1L_Msk                      /*!<Rx FIFO 1 Message Lost                   */
18066 
18067 /*****************  Bit definition for FDCAN_RXF1A register  ******************/
18068 #define FDCAN_RXF1A_F1AI_Pos         (0U)
18069 #define FDCAN_RXF1A_F1AI_Msk         (0x3FUL << FDCAN_RXF1A_F1AI_Pos)          /*!< 0x0000003F */
18070 #define FDCAN_RXF1A_F1AI             FDCAN_RXF1A_F1AI_Msk                      /*!<Rx FIFO 1 Acknowledge Index              */
18071 
18072 /*****************  Bit definition for FDCAN_RXESC register  ******************/
18073 #define FDCAN_RXESC_F0DS_Pos         (0U)
18074 #define FDCAN_RXESC_F0DS_Msk         (0x7UL << FDCAN_RXESC_F0DS_Pos)           /*!< 0x00000007 */
18075 #define FDCAN_RXESC_F0DS             FDCAN_RXESC_F0DS_Msk                      /*!<Rx FIFO 1 Data Field Size                 */
18076 #define FDCAN_RXESC_F1DS_Pos         (4U)
18077 #define FDCAN_RXESC_F1DS_Msk         (0x7UL << FDCAN_RXESC_F1DS_Pos)           /*!< 0x00000070 */
18078 #define FDCAN_RXESC_F1DS             FDCAN_RXESC_F1DS_Msk                      /*!<Rx FIFO 0 Data Field Size                 */
18079 #define FDCAN_RXESC_RBDS_Pos         (8U)
18080 #define FDCAN_RXESC_RBDS_Msk         (0x7UL << FDCAN_RXESC_RBDS_Pos)           /*!< 0x00000700 */
18081 #define FDCAN_RXESC_RBDS             FDCAN_RXESC_RBDS_Msk                      /*!<Rx Buffer Data Field Size                 */
18082 
18083 /*****************  Bit definition for FDCAN_TXBC register  *******************/
18084 #define FDCAN_TXBC_TBSA_Pos          (2U)
18085 #define FDCAN_TXBC_TBSA_Msk          (0x3FFFUL << FDCAN_TXBC_TBSA_Pos)         /*!< 0x0000FFFC */
18086 #define FDCAN_TXBC_TBSA              FDCAN_TXBC_TBSA_Msk                       /*!<Tx Buffers Start Address                  */
18087 #define FDCAN_TXBC_NDTB_Pos          (16U)
18088 #define FDCAN_TXBC_NDTB_Msk          (0x3FUL << FDCAN_TXBC_NDTB_Pos)           /*!< 0x003F0000 */
18089 #define FDCAN_TXBC_NDTB              FDCAN_TXBC_NDTB_Msk                       /*!<Number of Dedicated Transmit Buffers      */
18090 #define FDCAN_TXBC_TFQS_Pos          (24U)
18091 #define FDCAN_TXBC_TFQS_Msk          (0x3FUL << FDCAN_TXBC_TFQS_Pos)           /*!< 0x3F000000 */
18092 #define FDCAN_TXBC_TFQS              FDCAN_TXBC_TFQS_Msk                       /*!<Transmit FIFO/Queue Size                  */
18093 #define FDCAN_TXBC_TFQM_Pos          (30U)
18094 #define FDCAN_TXBC_TFQM_Msk          (0x1UL << FDCAN_TXBC_TFQM_Pos)            /*!< 0x40000000 */
18095 #define FDCAN_TXBC_TFQM              FDCAN_TXBC_TFQM_Msk                       /*!<Tx FIFO/Queue Mode                        */
18096 
18097 /*****************  Bit definition for FDCAN_TXFQS register  ******************/
18098 #define FDCAN_TXFQS_TFFL_Pos         (0U)
18099 #define FDCAN_TXFQS_TFFL_Msk         (0x3FUL << FDCAN_TXFQS_TFFL_Pos)          /*!< 0x0000003F */
18100 #define FDCAN_TXFQS_TFFL             FDCAN_TXFQS_TFFL_Msk                      /*!<Tx FIFO Free Level                        */
18101 #define FDCAN_TXFQS_TFGI_Pos         (8U)
18102 #define FDCAN_TXFQS_TFGI_Msk         (0x1FUL << FDCAN_TXFQS_TFGI_Pos)          /*!< 0x00001F00 */
18103 #define FDCAN_TXFQS_TFGI             FDCAN_TXFQS_TFGI_Msk                      /*!<Tx FIFO Get Index                         */
18104 #define FDCAN_TXFQS_TFQPI_Pos        (16U)
18105 #define FDCAN_TXFQS_TFQPI_Msk        (0x1FUL << FDCAN_TXFQS_TFQPI_Pos)         /*!< 0x001F0000 */
18106 #define FDCAN_TXFQS_TFQPI            FDCAN_TXFQS_TFQPI_Msk                     /*!<Tx FIFO/Queue Put Index                   */
18107 #define FDCAN_TXFQS_TFQF_Pos         (21U)
18108 #define FDCAN_TXFQS_TFQF_Msk         (0x1UL << FDCAN_TXFQS_TFQF_Pos)           /*!< 0x00200000 */
18109 #define FDCAN_TXFQS_TFQF             FDCAN_TXFQS_TFQF_Msk                      /*!<Tx FIFO/Queue Full                        */
18110 
18111 /*****************  Bit definition for FDCAN_TXESC register  ******************/
18112 #define FDCAN_TXESC_TBDS_Pos         (0U)
18113 #define FDCAN_TXESC_TBDS_Msk         (0x7UL << FDCAN_TXESC_TBDS_Pos)           /*!< 0x00000007 */
18114 #define FDCAN_TXESC_TBDS             FDCAN_TXESC_TBDS_Msk                      /*!<Tx Buffer Data Field Size                 */
18115 
18116 /*****************  Bit definition for FDCAN_TXBRP register  ******************/
18117 #define FDCAN_TXBRP_TRP_Pos          (0U)
18118 #define FDCAN_TXBRP_TRP_Msk          (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos)     /*!< 0xFFFFFFFF */
18119 #define FDCAN_TXBRP_TRP              FDCAN_TXBRP_TRP_Msk                       /*!<Transmission Request Pending             */
18120 
18121 /*****************  Bit definition for FDCAN_TXBAR register  ******************/
18122 #define FDCAN_TXBAR_AR_Pos           (0U)
18123 #define FDCAN_TXBAR_AR_Msk           (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos)      /*!< 0xFFFFFFFF */
18124 #define FDCAN_TXBAR_AR               FDCAN_TXBAR_AR_Msk                        /*!<Add Request                              */
18125 
18126 /*****************  Bit definition for FDCAN_TXBCR register  ******************/
18127 #define FDCAN_TXBCR_CR_Pos           (0U)
18128 #define FDCAN_TXBCR_CR_Msk           (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos)      /*!< 0xFFFFFFFF */
18129 #define FDCAN_TXBCR_CR               FDCAN_TXBCR_CR_Msk                        /*!<Cancellation Request                     */
18130 
18131 /*****************  Bit definition for FDCAN_TXBTO register  ******************/
18132 #define FDCAN_TXBTO_TO_Pos           (0U)
18133 #define FDCAN_TXBTO_TO_Msk           (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos)      /*!< 0xFFFFFFFF */
18134 #define FDCAN_TXBTO_TO               FDCAN_TXBTO_TO_Msk                        /*!<Transmission Occurred                    */
18135 
18136 /*****************  Bit definition for FDCAN_TXBCF register  ******************/
18137 #define FDCAN_TXBCF_CF_Pos           (0U)
18138 #define FDCAN_TXBCF_CF_Msk           (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos)      /*!< 0xFFFFFFFF */
18139 #define FDCAN_TXBCF_CF               FDCAN_TXBCF_CF_Msk                        /*!<Cancellation Finished                    */
18140 
18141 /*****************  Bit definition for FDCAN_TXBTIE register  *****************/
18142 #define FDCAN_TXBTIE_TIE_Pos         (0U)
18143 #define FDCAN_TXBTIE_TIE_Msk         (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos)    /*!< 0xFFFFFFFF */
18144 #define FDCAN_TXBTIE_TIE             FDCAN_TXBTIE_TIE_Msk                      /*!<Transmission Interrupt Enable            */
18145 
18146 /*****************  Bit definition for FDCAN_ TXBCIE register  ****************/
18147 #define FDCAN_TXBCIE_CFIE_Pos        (0U)
18148 #define FDCAN_TXBCIE_CFIE_Msk        (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos)   /*!< 0xFFFFFFFF */
18149 #define FDCAN_TXBCIE_CFIE            FDCAN_TXBCIE_CFIE_Msk                     /*!<Cancellation Finished Interrupt Enable   */
18150 
18151 /*****************  Bit definition for FDCAN_TXEFC register  ******************/
18152 #define FDCAN_TXEFC_EFSA_Pos         (2U)
18153 #define FDCAN_TXEFC_EFSA_Msk         (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos)        /*!< 0x0000FFFC */
18154 #define FDCAN_TXEFC_EFSA             FDCAN_TXEFC_EFSA_Msk                      /*!<Event FIFO Start Address                  */
18155 #define FDCAN_TXEFC_EFS_Pos          (16U)
18156 #define FDCAN_TXEFC_EFS_Msk          (0x3FUL << FDCAN_TXEFC_EFS_Pos)           /*!< 0x003F0000 */
18157 #define FDCAN_TXEFC_EFS              FDCAN_TXEFC_EFS_Msk                       /*!<Event FIFO Size                           */
18158 #define FDCAN_TXEFC_EFWM_Pos         (24U)
18159 #define FDCAN_TXEFC_EFWM_Msk         (0x3FUL << FDCAN_TXEFC_EFWM_Pos)          /*!< 0x3F000000 */
18160 #define FDCAN_TXEFC_EFWM             FDCAN_TXEFC_EFWM_Msk                      /*!<Event FIFO Watermark                      */
18161 
18162 /*****************  Bit definition for FDCAN_TXEFS register  ******************/
18163 #define FDCAN_TXEFS_EFFL_Pos         (0U)
18164 #define FDCAN_TXEFS_EFFL_Msk         (0x3FUL << FDCAN_TXEFS_EFFL_Pos)          /*!< 0x0000003F */
18165 #define FDCAN_TXEFS_EFFL             FDCAN_TXEFS_EFFL_Msk                      /*!<Event FIFO Fill Level                    */
18166 #define FDCAN_TXEFS_EFGI_Pos         (8U)
18167 #define FDCAN_TXEFS_EFGI_Msk         (0x1FUL << FDCAN_TXEFS_EFGI_Pos)          /*!< 0x00001F00 */
18168 #define FDCAN_TXEFS_EFGI             FDCAN_TXEFS_EFGI_Msk                      /*!<Event FIFO Get Index                     */
18169 #define FDCAN_TXEFS_EFPI_Pos         (16U)
18170 #define FDCAN_TXEFS_EFPI_Msk         (0x1FUL << FDCAN_TXEFS_EFPI_Pos)          /*!< 0x001F0000 */
18171 #define FDCAN_TXEFS_EFPI             FDCAN_TXEFS_EFPI_Msk                      /*!<Event FIFO Put Index                     */
18172 #define FDCAN_TXEFS_EFF_Pos          (24U)
18173 #define FDCAN_TXEFS_EFF_Msk          (0x1UL << FDCAN_TXEFS_EFF_Pos)            /*!< 0x01000000 */
18174 #define FDCAN_TXEFS_EFF              FDCAN_TXEFS_EFF_Msk                       /*!<Event FIFO Full                          */
18175 #define FDCAN_TXEFS_TEFL_Pos         (25U)
18176 #define FDCAN_TXEFS_TEFL_Msk         (0x1UL << FDCAN_TXEFS_TEFL_Pos)           /*!< 0x02000000 */
18177 #define FDCAN_TXEFS_TEFL             FDCAN_TXEFS_TEFL_Msk                      /*!<Tx Event FIFO Element Lost               */
18178 
18179 /*****************  Bit definition for FDCAN_TXEFA register  ******************/
18180 #define FDCAN_TXEFA_EFAI_Pos         (0U)
18181 #define FDCAN_TXEFA_EFAI_Msk         (0x1FUL << FDCAN_TXEFA_EFAI_Pos)          /*!< 0x0000001F */
18182 #define FDCAN_TXEFA_EFAI             FDCAN_TXEFA_EFAI_Msk                      /*!<Event FIFO Acknowledge Index             */
18183 
18184 /*****************  Bit definition for FDCAN_TTTMC register  ******************/
18185 #define FDCAN_TTTMC_TMSA_Pos         (2U)
18186 #define FDCAN_TTTMC_TMSA_Msk         (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos)        /*!< 0x0000FFFC */
18187 #define FDCAN_TTTMC_TMSA             FDCAN_TTTMC_TMSA_Msk                      /*!<Trigger Memory Start Address              */
18188 #define FDCAN_TTTMC_TME_Pos          (16U)
18189 #define FDCAN_TTTMC_TME_Msk          (0x7FUL << FDCAN_TTTMC_TME_Pos)           /*!< 0x007F0000 */
18190 #define FDCAN_TTTMC_TME              FDCAN_TTTMC_TME_Msk                       /*!<Trigger Memory Elements                   */
18191 
18192 /*****************  Bit definition for FDCAN_TTRMC register  ******************/
18193 #define FDCAN_TTRMC_RID_Pos          (0U)
18194 #define FDCAN_TTRMC_RID_Msk          (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos)     /*!< 0x1FFFFFFF */
18195 #define FDCAN_TTRMC_RID              FDCAN_TTRMC_RID_Msk                       /*!<Reference Identifier                      */
18196 #define FDCAN_TTRMC_XTD_Pos          (30U)
18197 #define FDCAN_TTRMC_XTD_Msk          (0x1UL << FDCAN_TTRMC_XTD_Pos)            /*!< 0x40000000 */
18198 #define FDCAN_TTRMC_XTD              FDCAN_TTRMC_XTD_Msk                       /*!< Extended Identifier                      */
18199 #define FDCAN_TTRMC_RMPS_Pos         (31U)
18200 #define FDCAN_TTRMC_RMPS_Msk         (0x1UL << FDCAN_TTRMC_RMPS_Pos)           /*!< 0x80000000 */
18201 #define FDCAN_TTRMC_RMPS             FDCAN_TTRMC_RMPS_Msk                      /*!<Reference Message Payload Select          */
18202 
18203 /*****************  Bit definition for FDCAN_TTOCF register  ******************/
18204 #define FDCAN_TTOCF_OM_Pos           (0U)
18205 #define FDCAN_TTOCF_OM_Msk           (0x3UL << FDCAN_TTOCF_OM_Pos)             /*!< 0x00000003 */
18206 #define FDCAN_TTOCF_OM               FDCAN_TTOCF_OM_Msk                        /*!<Operation Mode                            */
18207 #define FDCAN_TTOCF_GEN_Pos          (3U)
18208 #define FDCAN_TTOCF_GEN_Msk          (0x1UL << FDCAN_TTOCF_GEN_Pos)            /*!< 0x00000008 */
18209 #define FDCAN_TTOCF_GEN              FDCAN_TTOCF_GEN_Msk                       /*!<Gap Enable                                */
18210 #define FDCAN_TTOCF_TM_Pos           (4U)
18211 #define FDCAN_TTOCF_TM_Msk           (0x1UL << FDCAN_TTOCF_TM_Pos)             /*!< 0x00000010 */
18212 #define FDCAN_TTOCF_TM               FDCAN_TTOCF_TM_Msk                        /*!<Time Master                               */
18213 #define FDCAN_TTOCF_LDSDL_Pos        (5U)
18214 #define FDCAN_TTOCF_LDSDL_Msk        (0x7UL << FDCAN_TTOCF_LDSDL_Pos)          /*!< 0x000000E0 */
18215 #define FDCAN_TTOCF_LDSDL            FDCAN_TTOCF_LDSDL_Msk                     /*!<LD of Synchronization Deviation Limit     */
18216 #define FDCAN_TTOCF_IRTO_Pos         (8U)
18217 #define FDCAN_TTOCF_IRTO_Msk         (0x7FUL << FDCAN_TTOCF_IRTO_Pos)          /*!< 0x00007F00 */
18218 #define FDCAN_TTOCF_IRTO             FDCAN_TTOCF_IRTO_Msk                      /*!<Initial Reference Trigger Offset          */
18219 #define FDCAN_TTOCF_EECS_Pos         (15U)
18220 #define FDCAN_TTOCF_EECS_Msk         (0x1UL << FDCAN_TTOCF_EECS_Pos)           /*!< 0x00008000 */
18221 #define FDCAN_TTOCF_EECS             FDCAN_TTOCF_EECS_Msk                      /*!<Enable External Clock Synchronization     */
18222 #define FDCAN_TTOCF_AWL_Pos          (16U)
18223 #define FDCAN_TTOCF_AWL_Msk          (0xFFUL << FDCAN_TTOCF_AWL_Pos)           /*!< 0x00FF0000 */
18224 #define FDCAN_TTOCF_AWL              FDCAN_TTOCF_AWL_Msk                       /*!<Application Watchdog Limit                */
18225 #define FDCAN_TTOCF_EGTF_Pos         (24U)
18226 #define FDCAN_TTOCF_EGTF_Msk         (0x1UL << FDCAN_TTOCF_EGTF_Pos)           /*!< 0x01000000 */
18227 #define FDCAN_TTOCF_EGTF             FDCAN_TTOCF_EGTF_Msk                      /*!<Enable Global Time Filtering              */
18228 #define FDCAN_TTOCF_ECC_Pos          (25U)
18229 #define FDCAN_TTOCF_ECC_Msk          (0x1UL << FDCAN_TTOCF_ECC_Pos)            /*!< 0x02000000 */
18230 #define FDCAN_TTOCF_ECC              FDCAN_TTOCF_ECC_Msk                       /*!<Enable Clock Calibration                  */
18231 #define FDCAN_TTOCF_EVTP_Pos         (26U)
18232 #define FDCAN_TTOCF_EVTP_Msk         (0x1UL << FDCAN_TTOCF_EVTP_Pos)           /*!< 0x04000000 */
18233 #define FDCAN_TTOCF_EVTP             FDCAN_TTOCF_EVTP_Msk                      /*!<Event Trigger Polarity                    */
18234 
18235 /*****************  Bit definition for FDCAN_TTMLM register  ******************/
18236 #define FDCAN_TTMLM_CCM_Pos          (0U)
18237 #define FDCAN_TTMLM_CCM_Msk          (0x3FUL << FDCAN_TTMLM_CCM_Pos)           /*!< 0x0000003F */
18238 #define FDCAN_TTMLM_CCM              FDCAN_TTMLM_CCM_Msk                       /*!<Cycle Count Max                           */
18239 #define FDCAN_TTMLM_CSS_Pos          (6U)
18240 #define FDCAN_TTMLM_CSS_Msk          (0x3UL << FDCAN_TTMLM_CSS_Pos)            /*!< 0x000000C0 */
18241 #define FDCAN_TTMLM_CSS              FDCAN_TTMLM_CSS_Msk                       /*!<Cycle Start Synchronization               */
18242 #define FDCAN_TTMLM_TXEW_Pos         (8U)
18243 #define FDCAN_TTMLM_TXEW_Msk         (0xFUL << FDCAN_TTMLM_TXEW_Pos)           /*!< 0x00000F00 */
18244 #define FDCAN_TTMLM_TXEW             FDCAN_TTMLM_TXEW_Msk                      /*!<Tx Enable Window                          */
18245 #define FDCAN_TTMLM_ENTT_Pos         (16U)
18246 #define FDCAN_TTMLM_ENTT_Msk         (0xFFFUL << FDCAN_TTMLM_ENTT_Pos)         /*!< 0x0FFF0000 */
18247 #define FDCAN_TTMLM_ENTT             FDCAN_TTMLM_ENTT_Msk                      /*!<Expected Number of Tx Triggers            */
18248 
18249 /*****************  Bit definition for FDCAN_TURCF register  ******************/
18250 #define FDCAN_TURCF_NCL_Pos          (0U)
18251 #define FDCAN_TURCF_NCL_Msk          (0xFFFFUL << FDCAN_TURCF_NCL_Pos)         /*!< 0x0000FFFF */
18252 #define FDCAN_TURCF_NCL              FDCAN_TURCF_NCL_Msk                       /*!<Numerator Configuration Low               */
18253 #define FDCAN_TURCF_DC_Pos           (16U)
18254 #define FDCAN_TURCF_DC_Msk           (0x3FFFUL << FDCAN_TURCF_DC_Pos)          /*!< 0x3FFF0000 */
18255 #define FDCAN_TURCF_DC               FDCAN_TURCF_DC_Msk                        /*!<Denominator Configuration                 */
18256 #define FDCAN_TURCF_ELT_Pos          (31U)
18257 #define FDCAN_TURCF_ELT_Msk          (0x1UL << FDCAN_TURCF_ELT_Pos)            /*!< 0x80000000 */
18258 #define FDCAN_TURCF_ELT              FDCAN_TURCF_ELT_Msk                       /*!<Enable Local Time                         */
18259 
18260 /*****************  Bit definition for FDCAN_TTOCN register  ******************/
18261 #define FDCAN_TTOCN_SGT_Pos          (0U)
18262 #define FDCAN_TTOCN_SGT_Msk          (0x1UL << FDCAN_TTOCN_SGT_Pos)            /*!< 0x00000001 */
18263 #define FDCAN_TTOCN_SGT              FDCAN_TTOCN_SGT_Msk                       /*!<Set Global time                           */
18264 #define FDCAN_TTOCN_ECS_Pos          (1U)
18265 #define FDCAN_TTOCN_ECS_Msk          (0x1UL << FDCAN_TTOCN_ECS_Pos)            /*!< 0x00000002 */
18266 #define FDCAN_TTOCN_ECS              FDCAN_TTOCN_ECS_Msk                       /*!<External Clock Synchronization            */
18267 #define FDCAN_TTOCN_SWP_Pos          (2U)
18268 #define FDCAN_TTOCN_SWP_Msk          (0x1UL << FDCAN_TTOCN_SWP_Pos)            /*!< 0x00000004 */
18269 #define FDCAN_TTOCN_SWP              FDCAN_TTOCN_SWP_Msk                       /*!<Stop Watch Polarity                       */
18270 #define FDCAN_TTOCN_SWS_Pos          (3U)
18271 #define FDCAN_TTOCN_SWS_Msk          (0x3UL << FDCAN_TTOCN_SWS_Pos)            /*!< 0x00000018 */
18272 #define FDCAN_TTOCN_SWS              FDCAN_TTOCN_SWS_Msk                       /*!<Stop Watch Source                         */
18273 #define FDCAN_TTOCN_RTIE_Pos         (5U)
18274 #define FDCAN_TTOCN_RTIE_Msk         (0x1UL << FDCAN_TTOCN_RTIE_Pos)           /*!< 0x00000020 */
18275 #define FDCAN_TTOCN_RTIE             FDCAN_TTOCN_RTIE_Msk                      /*!<Register Time Mark Interrupt Pulse Enable */
18276 #define FDCAN_TTOCN_TMC_Pos          (6U)
18277 #define FDCAN_TTOCN_TMC_Msk          (0x3UL << FDCAN_TTOCN_TMC_Pos)            /*!< 0x000000C0 */
18278 #define FDCAN_TTOCN_TMC              FDCAN_TTOCN_TMC_Msk                       /*!<Register Time Mark Compare                */
18279 #define FDCAN_TTOCN_TTIE_Pos         (8U)
18280 #define FDCAN_TTOCN_TTIE_Msk         (0x1UL << FDCAN_TTOCN_TTIE_Pos)           /*!< 0x00000100 */
18281 #define FDCAN_TTOCN_TTIE             FDCAN_TTOCN_TTIE_Msk                      /*!<Trigger Time Mark Interrupt Pulse Enable  */
18282 #define FDCAN_TTOCN_GCS_Pos          (9U)
18283 #define FDCAN_TTOCN_GCS_Msk          (0x1UL << FDCAN_TTOCN_GCS_Pos)            /*!< 0x00000200 */
18284 #define FDCAN_TTOCN_GCS              FDCAN_TTOCN_GCS_Msk                       /*!<Gap Control Select                        */
18285 #define FDCAN_TTOCN_FGP_Pos          (10U)
18286 #define FDCAN_TTOCN_FGP_Msk          (0x1UL << FDCAN_TTOCN_FGP_Pos)            /*!< 0x00000400 */
18287 #define FDCAN_TTOCN_FGP              FDCAN_TTOCN_FGP_Msk                       /*!<Finish Gap                                */
18288 #define FDCAN_TTOCN_TMG_Pos          (11U)
18289 #define FDCAN_TTOCN_TMG_Msk          (0x1UL << FDCAN_TTOCN_TMG_Pos)            /*!< 0x00000800 */
18290 #define FDCAN_TTOCN_TMG              FDCAN_TTOCN_TMG_Msk                       /*!<Time Mark Gap                             */
18291 #define FDCAN_TTOCN_NIG_Pos          (12U)
18292 #define FDCAN_TTOCN_NIG_Msk          (0x1UL << FDCAN_TTOCN_NIG_Pos)            /*!< 0x00001000 */
18293 #define FDCAN_TTOCN_NIG              FDCAN_TTOCN_NIG_Msk                       /*!<Next is Gap                               */
18294 #define FDCAN_TTOCN_ESCN_Pos         (13U)
18295 #define FDCAN_TTOCN_ESCN_Msk         (0x1UL << FDCAN_TTOCN_ESCN_Pos)           /*!< 0x00002000 */
18296 #define FDCAN_TTOCN_ESCN             FDCAN_TTOCN_ESCN_Msk                      /*!<External Synchronization Control          */
18297 #define FDCAN_TTOCN_LCKC_Pos         (15U)
18298 #define FDCAN_TTOCN_LCKC_Msk         (0x1UL << FDCAN_TTOCN_LCKC_Pos)           /*!< 0x00008000 */
18299 #define FDCAN_TTOCN_LCKC             FDCAN_TTOCN_LCKC_Msk                      /*!<TT Operation Control Register Locked      */
18300 
18301 /*****************  Bit definition for FDCAN_TTGTP register  ******************/
18302 #define FDCAN_TTGTP_TP_Pos           (0U)
18303 #define FDCAN_TTGTP_TP_Msk           (0xFFFFUL << FDCAN_TTGTP_TP_Pos)          /*!< 0x0000FFFF */
18304 #define FDCAN_TTGTP_TP               FDCAN_TTGTP_TP_Msk                        /*!<Time Preset                               */
18305 #define FDCAN_TTGTP_CTP_Pos          (16U)
18306 #define FDCAN_TTGTP_CTP_Msk          (0xFFFFUL << FDCAN_TTGTP_CTP_Pos)         /*!< 0xFFFF0000 */
18307 #define FDCAN_TTGTP_CTP              FDCAN_TTGTP_CTP_Msk                       /*!<Cycle Time Target Phase                   */
18308 
18309 /*****************  Bit definition for FDCAN_TTTMK register  ******************/
18310 #define FDCAN_TTTMK_TM_Pos           (0U)
18311 #define FDCAN_TTTMK_TM_Msk           (0xFFFFUL << FDCAN_TTTMK_TM_Pos)          /*!< 0x0000FFFF */
18312 #define FDCAN_TTTMK_TM               FDCAN_TTTMK_TM_Msk                        /*!<Time Mark                                 */
18313 #define FDCAN_TTTMK_TICC_Pos         (16U)
18314 #define FDCAN_TTTMK_TICC_Msk         (0x7FUL << FDCAN_TTTMK_TICC_Pos)          /*!< 0x007F0000 */
18315 #define FDCAN_TTTMK_TICC             FDCAN_TTTMK_TICC_Msk                      /*!<Time Mark Cycle Code                      */
18316 #define FDCAN_TTTMK_LCKM_Pos         (31U)
18317 #define FDCAN_TTTMK_LCKM_Msk         (0x1UL << FDCAN_TTTMK_LCKM_Pos)           /*!< 0x80000000 */
18318 #define FDCAN_TTTMK_LCKM             FDCAN_TTTMK_LCKM_Msk                      /*!<TT Time Mark Register Locked              */
18319 
18320 /*****************  Bit definition for FDCAN_TTIR register  *******************/
18321 #define FDCAN_TTIR_SBC_Pos           (0U)
18322 #define FDCAN_TTIR_SBC_Msk           (0x1UL << FDCAN_TTIR_SBC_Pos)             /*!< 0x00000001 */
18323 #define FDCAN_TTIR_SBC               FDCAN_TTIR_SBC_Msk                        /*!<Start of Basic Cycle                      */
18324 #define FDCAN_TTIR_SMC_Pos           (1U)
18325 #define FDCAN_TTIR_SMC_Msk           (0x1UL << FDCAN_TTIR_SMC_Pos)             /*!< 0x00000002 */
18326 #define FDCAN_TTIR_SMC               FDCAN_TTIR_SMC_Msk                        /*!<Start of Matrix Cycle                     */
18327 #define FDCAN_TTIR_CSM_Pos           (2U)
18328 #define FDCAN_TTIR_CSM_Msk           (0x1UL << FDCAN_TTIR_CSM_Pos)             /*!< 0x00000004 */
18329 #define FDCAN_TTIR_CSM               FDCAN_TTIR_CSM_Msk                        /*!<Change of Synchronization Mode            */
18330 #define FDCAN_TTIR_SOG_Pos           (3U)
18331 #define FDCAN_TTIR_SOG_Msk           (0x1UL << FDCAN_TTIR_SOG_Pos)             /*!< 0x00000008 */
18332 #define FDCAN_TTIR_SOG               FDCAN_TTIR_SOG_Msk                        /*!<Start of Gap                              */
18333 #define FDCAN_TTIR_RTMI_Pos          (4U)
18334 #define FDCAN_TTIR_RTMI_Msk          (0x1UL << FDCAN_TTIR_RTMI_Pos)            /*!< 0x00000010 */
18335 #define FDCAN_TTIR_RTMI              FDCAN_TTIR_RTMI_Msk                       /*!<Register Time Mark Interrupt              */
18336 #define FDCAN_TTIR_TTMI_Pos          (5U)
18337 #define FDCAN_TTIR_TTMI_Msk          (0x1UL << FDCAN_TTIR_TTMI_Pos)            /*!< 0x00000020 */
18338 #define FDCAN_TTIR_TTMI              FDCAN_TTIR_TTMI_Msk                       /*!<Trigger Time Mark Event Internal          */
18339 #define FDCAN_TTIR_SWE_Pos           (6U)
18340 #define FDCAN_TTIR_SWE_Msk           (0x1UL << FDCAN_TTIR_SWE_Pos)             /*!< 0x00000040 */
18341 #define FDCAN_TTIR_SWE               FDCAN_TTIR_SWE_Msk                        /*!<Stop Watch Event                          */
18342 #define FDCAN_TTIR_GTW_Pos           (7U)
18343 #define FDCAN_TTIR_GTW_Msk           (0x1UL << FDCAN_TTIR_GTW_Pos)             /*!< 0x00000080 */
18344 #define FDCAN_TTIR_GTW               FDCAN_TTIR_GTW_Msk                        /*!<Global Time Wrap                          */
18345 #define FDCAN_TTIR_GTD_Pos           (8U)
18346 #define FDCAN_TTIR_GTD_Msk           (0x1UL << FDCAN_TTIR_GTD_Pos)             /*!< 0x00000100 */
18347 #define FDCAN_TTIR_GTD               FDCAN_TTIR_GTD_Msk                        /*!<Global Time Discontinuity                 */
18348 #define FDCAN_TTIR_GTE_Pos           (9U)
18349 #define FDCAN_TTIR_GTE_Msk           (0x1UL << FDCAN_TTIR_GTE_Pos)             /*!< 0x00000200 */
18350 #define FDCAN_TTIR_GTE               FDCAN_TTIR_GTE_Msk                        /*!<Global Time Error                         */
18351 #define FDCAN_TTIR_TXU_Pos           (10U)
18352 #define FDCAN_TTIR_TXU_Msk           (0x1UL << FDCAN_TTIR_TXU_Pos)             /*!< 0x00000400 */
18353 #define FDCAN_TTIR_TXU               FDCAN_TTIR_TXU_Msk                        /*!<Tx Count Underflow                        */
18354 #define FDCAN_TTIR_TXO_Pos           (11U)
18355 #define FDCAN_TTIR_TXO_Msk           (0x1UL << FDCAN_TTIR_TXO_Pos)             /*!< 0x00000800 */
18356 #define FDCAN_TTIR_TXO               FDCAN_TTIR_TXO_Msk                        /*!<Tx Count Overflow                         */
18357 #define FDCAN_TTIR_SE1_Pos           (12U)
18358 #define FDCAN_TTIR_SE1_Msk           (0x1UL << FDCAN_TTIR_SE1_Pos)             /*!< 0x00001000 */
18359 #define FDCAN_TTIR_SE1               FDCAN_TTIR_SE1_Msk                        /*!<Scheduling Error 1                        */
18360 #define FDCAN_TTIR_SE2_Pos           (13U)
18361 #define FDCAN_TTIR_SE2_Msk           (0x1UL << FDCAN_TTIR_SE2_Pos)             /*!< 0x00002000 */
18362 #define FDCAN_TTIR_SE2               FDCAN_TTIR_SE2_Msk                        /*!<Scheduling Error 2                        */
18363 #define FDCAN_TTIR_ELC_Pos           (14U)
18364 #define FDCAN_TTIR_ELC_Msk           (0x1UL << FDCAN_TTIR_ELC_Pos)             /*!< 0x00004000 */
18365 #define FDCAN_TTIR_ELC               FDCAN_TTIR_ELC_Msk                        /*!<Error Level Changed                       */
18366 #define FDCAN_TTIR_IWT_Pos           (15U)
18367 #define FDCAN_TTIR_IWT_Msk           (0x1UL << FDCAN_TTIR_IWT_Pos)             /*!< 0x00008000 */
18368 #define FDCAN_TTIR_IWT               FDCAN_TTIR_IWT_Msk                        /*!<Initialization Watch Trigger              */
18369 #define FDCAN_TTIR_WT_Pos            (16U)
18370 #define FDCAN_TTIR_WT_Msk            (0x1UL << FDCAN_TTIR_WT_Pos)              /*!< 0x00010000 */
18371 #define FDCAN_TTIR_WT                FDCAN_TTIR_WT_Msk                         /*!<Watch Trigger                             */
18372 #define FDCAN_TTIR_AW_Pos            (17U)
18373 #define FDCAN_TTIR_AW_Msk            (0x1UL << FDCAN_TTIR_AW_Pos)              /*!< 0x00020000 */
18374 #define FDCAN_TTIR_AW                FDCAN_TTIR_AW_Msk                         /*!<Application Watchdog                      */
18375 #define FDCAN_TTIR_CER_Pos           (18U)
18376 #define FDCAN_TTIR_CER_Msk           (0x1UL << FDCAN_TTIR_CER_Pos)             /*!< 0x00040000 */
18377 #define FDCAN_TTIR_CER               FDCAN_TTIR_CER_Msk                        /*!<Configuration Error                       */
18378 
18379 /*****************  Bit definition for FDCAN_TTIE register  *******************/
18380 #define FDCAN_TTIE_SBCE_Pos          (0U)
18381 #define FDCAN_TTIE_SBCE_Msk          (0x1UL << FDCAN_TTIE_SBCE_Pos)            /*!< 0x00000001 */
18382 #define FDCAN_TTIE_SBCE              FDCAN_TTIE_SBCE_Msk                       /*!<Start of Basic Cycle Interrupt Enable             */
18383 #define FDCAN_TTIE_SMCE_Pos          (1U)
18384 #define FDCAN_TTIE_SMCE_Msk          (0x1UL << FDCAN_TTIE_SMCE_Pos)            /*!< 0x00000002 */
18385 #define FDCAN_TTIE_SMCE              FDCAN_TTIE_SMCE_Msk                       /*!<Start of Matrix Cycle Interrupt Enable            */
18386 #define FDCAN_TTIE_CSME_Pos          (2U)
18387 #define FDCAN_TTIE_CSME_Msk          (0x1UL << FDCAN_TTIE_CSME_Pos)            /*!< 0x00000004 */
18388 #define FDCAN_TTIE_CSME              FDCAN_TTIE_CSME_Msk                       /*!<Change of Synchronization Mode Interrupt Enable   */
18389 #define FDCAN_TTIE_SOGE_Pos          (3U)
18390 #define FDCAN_TTIE_SOGE_Msk          (0x1UL << FDCAN_TTIE_SOGE_Pos)            /*!< 0x00000008 */
18391 #define FDCAN_TTIE_SOGE              FDCAN_TTIE_SOGE_Msk                       /*!<Start of Gap Interrupt Enable                     */
18392 #define FDCAN_TTIE_RTMIE_Pos         (4U)
18393 #define FDCAN_TTIE_RTMIE_Msk         (0x1UL << FDCAN_TTIE_RTMIE_Pos)           /*!< 0x00000010 */
18394 #define FDCAN_TTIE_RTMIE             FDCAN_TTIE_RTMIE_Msk                      /*!<Register Time Mark Interrupt Interrupt Enable     */
18395 #define FDCAN_TTIE_TTMIE_Pos         (5U)
18396 #define FDCAN_TTIE_TTMIE_Msk         (0x1UL << FDCAN_TTIE_TTMIE_Pos)           /*!< 0x00000020 */
18397 #define FDCAN_TTIE_TTMIE             FDCAN_TTIE_TTMIE_Msk                      /*!<Trigger Time Mark Event Internal Interrupt Enable */
18398 #define FDCAN_TTIE_SWEE_Pos          (6U)
18399 #define FDCAN_TTIE_SWEE_Msk          (0x1UL << FDCAN_TTIE_SWEE_Pos)            /*!< 0x00000040 */
18400 #define FDCAN_TTIE_SWEE              FDCAN_TTIE_SWEE_Msk                       /*!<Stop Watch Event Interrupt Enable                 */
18401 #define FDCAN_TTIE_GTWE_Pos          (7U)
18402 #define FDCAN_TTIE_GTWE_Msk          (0x1UL << FDCAN_TTIE_GTWE_Pos)            /*!< 0x00000080 */
18403 #define FDCAN_TTIE_GTWE              FDCAN_TTIE_GTWE_Msk                       /*!<Global Time Wrap Interrupt Enable                 */
18404 #define FDCAN_TTIE_GTDE_Pos          (8U)
18405 #define FDCAN_TTIE_GTDE_Msk          (0x1UL << FDCAN_TTIE_GTDE_Pos)            /*!< 0x00000100 */
18406 #define FDCAN_TTIE_GTDE              FDCAN_TTIE_GTDE_Msk                       /*!<Global Time Discontinuity Interrupt Enable        */
18407 #define FDCAN_TTIE_GTEE_Pos          (9U)
18408 #define FDCAN_TTIE_GTEE_Msk          (0x1UL << FDCAN_TTIE_GTEE_Pos)            /*!< 0x00000200 */
18409 #define FDCAN_TTIE_GTEE              FDCAN_TTIE_GTEE_Msk                       /*!<Global Time Error Interrupt Enable                */
18410 #define FDCAN_TTIE_TXUE_Pos          (10U)
18411 #define FDCAN_TTIE_TXUE_Msk          (0x1UL << FDCAN_TTIE_TXUE_Pos)            /*!< 0x00000400 */
18412 #define FDCAN_TTIE_TXUE              FDCAN_TTIE_TXUE_Msk                       /*!<Tx Count Underflow Interrupt Enable               */
18413 #define FDCAN_TTIE_TXOE_Pos          (11U)
18414 #define FDCAN_TTIE_TXOE_Msk          (0x1UL << FDCAN_TTIE_TXOE_Pos)            /*!< 0x00000800 */
18415 #define FDCAN_TTIE_TXOE              FDCAN_TTIE_TXOE_Msk                       /*!<Tx Count Overflow Interrupt Enable                */
18416 #define FDCAN_TTIE_SE1E_Pos          (12U)
18417 #define FDCAN_TTIE_SE1E_Msk          (0x1UL << FDCAN_TTIE_SE1E_Pos)            /*!< 0x00001000 */
18418 #define FDCAN_TTIE_SE1E              FDCAN_TTIE_SE1E_Msk                       /*!<Scheduling Error 1 Interrupt Enable               */
18419 #define FDCAN_TTIE_SE2E_Pos          (13U)
18420 #define FDCAN_TTIE_SE2E_Msk          (0x1UL << FDCAN_TTIE_SE2E_Pos)            /*!< 0x00002000 */
18421 #define FDCAN_TTIE_SE2E              FDCAN_TTIE_SE2E_Msk                       /*!<Scheduling Error 2 Interrupt Enable               */
18422 #define FDCAN_TTIE_ELCE_Pos          (14U)
18423 #define FDCAN_TTIE_ELCE_Msk          (0x1UL << FDCAN_TTIE_ELCE_Pos)            /*!< 0x00004000 */
18424 #define FDCAN_TTIE_ELCE              FDCAN_TTIE_ELCE_Msk                       /*!<Error Level Changed Interrupt Enable              */
18425 #define FDCAN_TTIE_IWTE_Pos          (15U)
18426 #define FDCAN_TTIE_IWTE_Msk          (0x1UL << FDCAN_TTIE_IWTE_Pos)            /*!< 0x00008000 */
18427 #define FDCAN_TTIE_IWTE              FDCAN_TTIE_IWTE_Msk                       /*!<Initialization Watch Trigger Interrupt Enable     */
18428 #define FDCAN_TTIE_WTE_Pos           (16U)
18429 #define FDCAN_TTIE_WTE_Msk           (0x1UL << FDCAN_TTIE_WTE_Pos)             /*!< 0x00010000 */
18430 #define FDCAN_TTIE_WTE               FDCAN_TTIE_WTE_Msk                        /*!<Watch Trigger Interrupt Enable                    */
18431 #define FDCAN_TTIE_AWE_Pos           (17U)
18432 #define FDCAN_TTIE_AWE_Msk           (0x1UL << FDCAN_TTIE_AWE_Pos)             /*!< 0x00020000 */
18433 #define FDCAN_TTIE_AWE               FDCAN_TTIE_AWE_Msk                        /*!<Application Watchdog Interrupt Enable             */
18434 #define FDCAN_TTIE_CERE_Pos          (18U)
18435 #define FDCAN_TTIE_CERE_Msk          (0x1UL << FDCAN_TTIE_CERE_Pos)            /*!< 0x00040000 */
18436 #define FDCAN_TTIE_CERE              FDCAN_TTIE_CERE_Msk                       /*!<Configuration Error Interrupt Enable              */
18437 
18438 /*****************  Bit definition for FDCAN_TTILS register  ******************/
18439 #define FDCAN_TTILS_SBCS_Pos         (0U)
18440 #define FDCAN_TTILS_SBCS_Msk         (0x1UL << FDCAN_TTILS_SBCS_Pos)           /*!< 0x00000001 */
18441 #define FDCAN_TTILS_SBCS             FDCAN_TTILS_SBCS_Msk                      /*!<Start of Basic Cycle Interrupt Line               */
18442 #define FDCAN_TTILS_SMCS_Pos         (1U)
18443 #define FDCAN_TTILS_SMCS_Msk         (0x1UL << FDCAN_TTILS_SMCS_Pos)           /*!< 0x00000002 */
18444 #define FDCAN_TTILS_SMCS             FDCAN_TTILS_SMCS_Msk                      /*!<Start of Matrix Cycle Interrupt Line              */
18445 #define FDCAN_TTILS_CSMS_Pos         (2U)
18446 #define FDCAN_TTILS_CSMS_Msk         (0x1UL << FDCAN_TTILS_CSMS_Pos)           /*!< 0x00000004 */
18447 #define FDCAN_TTILS_CSMS             FDCAN_TTILS_CSMS_Msk                      /*!<Change of Synchronization Mode Interrupt Line     */
18448 #define FDCAN_TTILS_SOGS_Pos         (3U)
18449 #define FDCAN_TTILS_SOGS_Msk         (0x1UL << FDCAN_TTILS_SOGS_Pos)           /*!< 0x00000008 */
18450 #define FDCAN_TTILS_SOGS             FDCAN_TTILS_SOGS_Msk                      /*!<Start of Gap Interrupt Line                       */
18451 #define FDCAN_TTILS_RTMIS_Pos        (4U)
18452 #define FDCAN_TTILS_RTMIS_Msk        (0x1UL << FDCAN_TTILS_RTMIS_Pos)          /*!< 0x00000010 */
18453 #define FDCAN_TTILS_RTMIS            FDCAN_TTILS_RTMIS_Msk                     /*!<Register Time Mark Interrupt Interrupt Line       */
18454 #define FDCAN_TTILS_TTMIS_Pos        (5U)
18455 #define FDCAN_TTILS_TTMIS_Msk        (0x1UL << FDCAN_TTILS_TTMIS_Pos)          /*!< 0x00000020 */
18456 #define FDCAN_TTILS_TTMIS            FDCAN_TTILS_TTMIS_Msk                     /*!<Trigger Time Mark Event Internal Interrupt Line   */
18457 #define FDCAN_TTILS_SWES_Pos         (6U)
18458 #define FDCAN_TTILS_SWES_Msk         (0x1UL << FDCAN_TTILS_SWES_Pos)           /*!< 0x00000040 */
18459 #define FDCAN_TTILS_SWES             FDCAN_TTILS_SWES_Msk                      /*!<Stop Watch Event Interrupt Line                   */
18460 #define FDCAN_TTILS_GTWS_Pos         (7U)
18461 #define FDCAN_TTILS_GTWS_Msk         (0x1UL << FDCAN_TTILS_GTWS_Pos)           /*!< 0x00000080 */
18462 #define FDCAN_TTILS_GTWS             FDCAN_TTILS_GTWS_Msk                      /*!<Global Time Wrap Interrupt Line                   */
18463 #define FDCAN_TTILS_GTDS_Pos         (8U)
18464 #define FDCAN_TTILS_GTDS_Msk         (0x1UL << FDCAN_TTILS_GTDS_Pos)           /*!< 0x00000100 */
18465 #define FDCAN_TTILS_GTDS             FDCAN_TTILS_GTDS_Msk                      /*!<Global Time Discontinuity Interrupt Line          */
18466 #define FDCAN_TTILS_GTES_Pos         (9U)
18467 #define FDCAN_TTILS_GTES_Msk         (0x1UL << FDCAN_TTILS_GTES_Pos)           /*!< 0x00000200 */
18468 #define FDCAN_TTILS_GTES             FDCAN_TTILS_GTES_Msk                      /*!<Global Time Error Interrupt Line                  */
18469 #define FDCAN_TTILS_TXUS_Pos         (10U)
18470 #define FDCAN_TTILS_TXUS_Msk         (0x1UL << FDCAN_TTILS_TXUS_Pos)           /*!< 0x00000400 */
18471 #define FDCAN_TTILS_TXUS             FDCAN_TTILS_TXUS_Msk                      /*!<Tx Count Underflow Interrupt Line                 */
18472 #define FDCAN_TTILS_TXOS_Pos         (11U)
18473 #define FDCAN_TTILS_TXOS_Msk         (0x1UL << FDCAN_TTILS_TXOS_Pos)           /*!< 0x00000800 */
18474 #define FDCAN_TTILS_TXOS             FDCAN_TTILS_TXOS_Msk                      /*!<Tx Count Overflow Interrupt Line                  */
18475 #define FDCAN_TTILS_SE1S_Pos         (12U)
18476 #define FDCAN_TTILS_SE1S_Msk         (0x1UL << FDCAN_TTILS_SE1S_Pos)           /*!< 0x00001000 */
18477 #define FDCAN_TTILS_SE1S             FDCAN_TTILS_SE1S_Msk                      /*!<Scheduling Error 1 Interrupt Line                 */
18478 #define FDCAN_TTILS_SE2S_Pos         (13U)
18479 #define FDCAN_TTILS_SE2S_Msk         (0x1UL << FDCAN_TTILS_SE2S_Pos)           /*!< 0x00002000 */
18480 #define FDCAN_TTILS_SE2S             FDCAN_TTILS_SE2S_Msk                      /*!<Scheduling Error 2 Interrupt Line                 */
18481 #define FDCAN_TTILS_ELCS_Pos         (14U)
18482 #define FDCAN_TTILS_ELCS_Msk         (0x1UL << FDCAN_TTILS_ELCS_Pos)           /*!< 0x00004000 */
18483 #define FDCAN_TTILS_ELCS             FDCAN_TTILS_ELCS_Msk                      /*!<Error Level Changed Interrupt Line                */
18484 #define FDCAN_TTILS_IWTS_Pos         (15U)
18485 #define FDCAN_TTILS_IWTS_Msk         (0x1UL << FDCAN_TTILS_IWTS_Pos)           /*!< 0x00008000 */
18486 #define FDCAN_TTILS_IWTS             FDCAN_TTILS_IWTS_Msk                      /*!<Initialization Watch Trigger Interrupt Line       */
18487 #define FDCAN_TTILS_WTS_Pos          (16U)
18488 #define FDCAN_TTILS_WTS_Msk          (0x1UL << FDCAN_TTILS_WTS_Pos)            /*!< 0x00010000 */
18489 #define FDCAN_TTILS_WTS              FDCAN_TTILS_WTS_Msk                       /*!<Watch Trigger Interrupt Line                      */
18490 #define FDCAN_TTILS_AWS_Pos          (17U)
18491 #define FDCAN_TTILS_AWS_Msk          (0x1UL << FDCAN_TTILS_AWS_Pos)            /*!< 0x00020000 */
18492 #define FDCAN_TTILS_AWS              FDCAN_TTILS_AWS_Msk                       /*!<Application Watchdog Interrupt Line               */
18493 #define FDCAN_TTILS_CERS_Pos         (18U)
18494 #define FDCAN_TTILS_CERS_Msk         (0x1UL << FDCAN_TTILS_CERS_Pos)           /*!< 0x00040000 */
18495 #define FDCAN_TTILS_CERS             FDCAN_TTILS_CERS_Msk                      /*!<Configuration Error Interrupt Line                */
18496 
18497 /*****************  Bit definition for FDCAN_TTOST register  ******************/
18498 #define FDCAN_TTOST_EL_Pos           (0U)
18499 #define FDCAN_TTOST_EL_Msk           (0x3UL << FDCAN_TTOST_EL_Pos)             /*!< 0x00000003 */
18500 #define FDCAN_TTOST_EL               FDCAN_TTOST_EL_Msk                        /*!<Error Level                              */
18501 #define FDCAN_TTOST_MS_Pos           (2U)
18502 #define FDCAN_TTOST_MS_Msk           (0x3UL << FDCAN_TTOST_MS_Pos)             /*!< 0x0000000C */
18503 #define FDCAN_TTOST_MS               FDCAN_TTOST_MS_Msk                        /*!<Master State                             */
18504 #define FDCAN_TTOST_SYS_Pos          (4U)
18505 #define FDCAN_TTOST_SYS_Msk          (0x3UL << FDCAN_TTOST_SYS_Pos)            /*!< 0x00000030 */
18506 #define FDCAN_TTOST_SYS              FDCAN_TTOST_SYS_Msk                       /*!<Synchronization State                    */
18507 #define FDCAN_TTOST_QGTP_Pos         (6U)
18508 #define FDCAN_TTOST_QGTP_Msk         (0x1UL << FDCAN_TTOST_QGTP_Pos)           /*!< 0x00000040 */
18509 #define FDCAN_TTOST_QGTP             FDCAN_TTOST_QGTP_Msk                      /*!<Quality of Global Time Phase             */
18510 #define FDCAN_TTOST_QCS_Pos          (7U)
18511 #define FDCAN_TTOST_QCS_Msk          (0x1UL << FDCAN_TTOST_QCS_Pos)            /*!< 0x00000080 */
18512 #define FDCAN_TTOST_QCS              FDCAN_TTOST_QCS_Msk                       /*!<Quality of Clock Speed                   */
18513 #define FDCAN_TTOST_RTO_Pos          (8U)
18514 #define FDCAN_TTOST_RTO_Msk          (0xFFUL << FDCAN_TTOST_RTO_Pos)           /*!< 0x0000FF00 */
18515 #define FDCAN_TTOST_RTO              FDCAN_TTOST_RTO_Msk                       /*!<Reference Trigger Offset                 */
18516 #define FDCAN_TTOST_WGTD_Pos         (22U)
18517 #define FDCAN_TTOST_WGTD_Msk         (0x1UL << FDCAN_TTOST_WGTD_Pos)           /*!< 0x00400000 */
18518 #define FDCAN_TTOST_WGTD             FDCAN_TTOST_WGTD_Msk                      /*!<Wait for Global Time Discontinuity       */
18519 #define FDCAN_TTOST_GFI_Pos          (23U)
18520 #define FDCAN_TTOST_GFI_Msk          (0x1UL << FDCAN_TTOST_GFI_Pos)            /*!< 0x00800000 */
18521 #define FDCAN_TTOST_GFI              FDCAN_TTOST_GFI_Msk                       /*!<Gap Finished Indicator                   */
18522 #define FDCAN_TTOST_TMP_Pos          (24U)
18523 #define FDCAN_TTOST_TMP_Msk          (0x7UL << FDCAN_TTOST_TMP_Pos)            /*!< 0x07000000 */
18524 #define FDCAN_TTOST_TMP              FDCAN_TTOST_TMP_Msk                       /*!<Time Master Priority                     */
18525 #define FDCAN_TTOST_GSI_Pos          (27U)
18526 #define FDCAN_TTOST_GSI_Msk          (0x1UL << FDCAN_TTOST_GSI_Pos)            /*!< 0x08000000 */
18527 #define FDCAN_TTOST_GSI              FDCAN_TTOST_GSI_Msk                       /*!<Gap Started Indicator                    */
18528 #define FDCAN_TTOST_WFE_Pos          (28U)
18529 #define FDCAN_TTOST_WFE_Msk          (0x1UL << FDCAN_TTOST_WFE_Pos)            /*!< 0x10000000 */
18530 #define FDCAN_TTOST_WFE              FDCAN_TTOST_WFE_Msk                       /*!<Wait for Event                           */
18531 #define FDCAN_TTOST_AWE_Pos          (29U)
18532 #define FDCAN_TTOST_AWE_Msk          (0x1UL << FDCAN_TTOST_AWE_Pos)            /*!< 0x20000000 */
18533 #define FDCAN_TTOST_AWE              FDCAN_TTOST_AWE_Msk                       /*!<Application Watchdog Event               */
18534 #define FDCAN_TTOST_WECS_Pos         (30U)
18535 #define FDCAN_TTOST_WECS_Msk         (0x1UL << FDCAN_TTOST_WECS_Pos)           /*!< 0x40000000 */
18536 #define FDCAN_TTOST_WECS             FDCAN_TTOST_WECS_Msk                      /*!<Wait for External Clock Synchronization  */
18537 #define FDCAN_TTOST_SPL_Pos          (31U)
18538 #define FDCAN_TTOST_SPL_Msk          (0x1UL << FDCAN_TTOST_SPL_Pos)            /*!< 0x80000000 */
18539 #define FDCAN_TTOST_SPL              FDCAN_TTOST_SPL_Msk                       /*!<Schedule Phase Lock                      */
18540 
18541 /*****************  Bit definition for FDCAN_TURNA register  ******************/
18542 #define FDCAN_TURNA_NAV_Pos          (0U)
18543 #define FDCAN_TURNA_NAV_Msk          (0x3FFFFUL << FDCAN_TURNA_NAV_Pos)        /*!< 0x0003FFFF */
18544 #define FDCAN_TURNA_NAV              FDCAN_TURNA_NAV_Msk                       /*!<Numerator Actual Value                   */
18545 
18546 /*****************  Bit definition for FDCAN_TTLGT register  ******************/
18547 #define FDCAN_TTLGT_LT_Pos           (0U)
18548 #define FDCAN_TTLGT_LT_Msk           (0xFFFFUL << FDCAN_TTLGT_LT_Pos)          /*!< 0x0000FFFF */
18549 #define FDCAN_TTLGT_LT               FDCAN_TTLGT_LT_Msk                        /*!<Local Time                               */
18550 #define FDCAN_TTLGT_GT_Pos           (16U)
18551 #define FDCAN_TTLGT_GT_Msk           (0xFFFFUL << FDCAN_TTLGT_GT_Pos)          /*!< 0xFFFF0000 */
18552 #define FDCAN_TTLGT_GT               FDCAN_TTLGT_GT_Msk                        /*!<Global Time                              */
18553 
18554 /*****************  Bit definition for FDCAN_TTCTC register  ******************/
18555 #define FDCAN_TTCTC_CT_Pos           (0U)
18556 #define FDCAN_TTCTC_CT_Msk           (0xFFFFUL << FDCAN_TTCTC_CT_Pos)          /*!< 0x0000FFFF */
18557 #define FDCAN_TTCTC_CT               FDCAN_TTCTC_CT_Msk                        /*!<Cycle Time                               */
18558 #define FDCAN_TTCTC_CC_Pos           (16U)
18559 #define FDCAN_TTCTC_CC_Msk           (0x3FUL << FDCAN_TTCTC_CC_Pos)            /*!< 0x003F0000 */
18560 #define FDCAN_TTCTC_CC               FDCAN_TTCTC_CC_Msk                        /*!<Cycle Count                              */
18561 
18562 /*****************  Bit definition for FDCAN_TTCPT register  ******************/
18563 #define FDCAN_TTCPT_CCV_Pos          (0U)
18564 #define FDCAN_TTCPT_CCV_Msk          (0x3FUL << FDCAN_TTCPT_CCV_Pos)           /*!< 0x0000003F */
18565 #define FDCAN_TTCPT_CCV              FDCAN_TTCPT_CCV_Msk                       /*!<Cycle Count Value                        */
18566 #define FDCAN_TTCPT_SWV_Pos          (16U)
18567 #define FDCAN_TTCPT_SWV_Msk          (0xFFFFUL << FDCAN_TTCPT_SWV_Pos)         /*!< 0xFFFF0000 */
18568 #define FDCAN_TTCPT_SWV              FDCAN_TTCPT_SWV_Msk                       /*!<Stop Watch Value                         */
18569 
18570 /*****************  Bit definition for FDCAN_TTCSM register  ******************/
18571 #define FDCAN_TTCSM_CSM_Pos          (0U)
18572 #define FDCAN_TTCSM_CSM_Msk          (0xFFFFUL << FDCAN_TTCSM_CSM_Pos)         /*!< 0x0000FFFF */
18573 #define FDCAN_TTCSM_CSM              FDCAN_TTCSM_CSM_Msk                       /*!<Cycle Sync Mark                          */
18574 
18575 /*****************  Bit definition for FDCAN_TTTS register  *******************/
18576 #define FDCAN_TTTS_SWTSEL_Pos        (0U)
18577 #define FDCAN_TTTS_SWTSEL_Msk        (0x3UL << FDCAN_TTTS_SWTSEL_Pos)          /*!< 0x00000003 */
18578 #define FDCAN_TTTS_SWTSEL            FDCAN_TTTS_SWTSEL_Msk                     /*!<Stop watch trigger input selection       */
18579 #define FDCAN_TTTS_EVTSEL_Pos        (4U)
18580 #define FDCAN_TTTS_EVTSEL_Msk        (0x3UL << FDCAN_TTTS_EVTSEL_Pos)          /*!< 0x00000030 */
18581 #define FDCAN_TTTS_EVTSEL            FDCAN_TTTS_EVTSEL_Msk                     /*!<Event trigger input selection            */
18582 
18583 /******************************************************************************/
18584 /*                                                                            */
18585 /*                      FDCANCCU (Clock Calibration unit)                     */
18586 /*                                                                            */
18587 /******************************************************************************/
18588 
18589 /*****************  Bit definition for FDCANCCU_CREL register  ****************/
18590 #define FDCANCCU_CREL_DAY_Pos        (0U)
18591 #define FDCANCCU_CREL_DAY_Msk        (0xFFUL << FDCANCCU_CREL_DAY_Pos)         /*!< 0x000000FF */
18592 #define FDCANCCU_CREL_DAY            FDCANCCU_CREL_DAY_Msk                     /*!<Timestamp Day                           */
18593 #define FDCANCCU_CREL_MON_Pos        (8U)
18594 #define FDCANCCU_CREL_MON_Msk        (0xFFUL << FDCANCCU_CREL_MON_Pos)         /*!< 0x0000FF00 */
18595 #define FDCANCCU_CREL_MON            FDCANCCU_CREL_MON_Msk                     /*!<Timestamp Month                         */
18596 #define FDCANCCU_CREL_YEAR_Pos       (16U)
18597 #define FDCANCCU_CREL_YEAR_Msk       (0xFUL << FDCANCCU_CREL_YEAR_Pos)         /*!< 0x000F0000 */
18598 #define FDCANCCU_CREL_YEAR           FDCANCCU_CREL_YEAR_Msk                    /*!<Timestamp Year                          */
18599 #define FDCANCCU_CREL_SUBSTEP_Pos    (20U)
18600 #define FDCANCCU_CREL_SUBSTEP_Msk    (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos)      /*!< 0x00F00000 */
18601 #define FDCANCCU_CREL_SUBSTEP        FDCANCCU_CREL_SUBSTEP_Msk                 /*!<Sub-step of Core release                */
18602 #define FDCANCCU_CREL_STEP_Pos       (24U)
18603 #define FDCANCCU_CREL_STEP_Msk       (0xFUL << FDCANCCU_CREL_STEP_Pos)         /*!< 0x0F000000 */
18604 #define FDCANCCU_CREL_STEP           FDCANCCU_CREL_STEP_Msk                    /*!<Step of Core release                    */
18605 #define FDCANCCU_CREL_REL_Pos        (28U)
18606 #define FDCANCCU_CREL_REL_Msk        (0xFUL << FDCANCCU_CREL_REL_Pos)          /*!< 0xF0000000 */
18607 #define FDCANCCU_CREL_REL            FDCANCCU_CREL_REL_Msk                     /*!<Core release                            */
18608 
18609 /*****************  Bit definition for FDCANCCU_CCFG register  ****************/
18610 #define FDCANCCU_CCFG_TQBT_Pos       (0U)
18611 #define FDCANCCU_CCFG_TQBT_Msk       (0x1FUL << FDCANCCU_CCFG_TQBT_Pos)        /*!< 0x0000001F */
18612 #define FDCANCCU_CCFG_TQBT           FDCANCCU_CCFG_TQBT_Msk                    /*!<Time Quanta per Bit Time                */
18613 #define FDCANCCU_CCFG_BCC_Pos        (6U)
18614 #define FDCANCCU_CCFG_BCC_Msk        (0x1UL << FDCANCCU_CCFG_BCC_Pos)          /*!< 0x00000040 */
18615 #define FDCANCCU_CCFG_BCC            FDCANCCU_CCFG_BCC_Msk                     /*!<Bypass Clock Calibration                */
18616 #define FDCANCCU_CCFG_CFL_Pos        (7U)
18617 #define FDCANCCU_CCFG_CFL_Msk        (0x1UL << FDCANCCU_CCFG_CFL_Pos)          /*!< 0x00000080 */
18618 #define FDCANCCU_CCFG_CFL            FDCANCCU_CCFG_CFL_Msk                     /*!<Calibration Field Length                */
18619 #define FDCANCCU_CCFG_OCPM_Pos       (8U)
18620 #define FDCANCCU_CCFG_OCPM_Msk       (0xFFUL << FDCANCCU_CCFG_OCPM_Pos)        /*!< 0x0000FF00 */
18621 #define FDCANCCU_CCFG_OCPM           FDCANCCU_CCFG_OCPM_Msk                    /*!<Oscillator Clock Periods Minimum        */
18622 #define FDCANCCU_CCFG_CDIV_Pos       (16U)
18623 #define FDCANCCU_CCFG_CDIV_Msk       (0xFUL << FDCANCCU_CCFG_CDIV_Pos)         /*!< 0x000F0000 */
18624 #define FDCANCCU_CCFG_CDIV           FDCANCCU_CCFG_CDIV_Msk                    /*!<Clock Divider                           */
18625 #define FDCANCCU_CCFG_SWR_Pos        (31U)
18626 #define FDCANCCU_CCFG_SWR_Msk        (0x1UL << FDCANCCU_CCFG_SWR_Pos)          /*!< 0x80000000 */
18627 #define FDCANCCU_CCFG_SWR            FDCANCCU_CCFG_SWR_Msk                     /*!<Software Reset                          */
18628 
18629 /*****************  Bit definition for FDCANCCU_CSTAT register  ***************/
18630 #define FDCANCCU_CSTAT_OCPC_Pos      (0U)
18631 #define FDCANCCU_CSTAT_OCPC_Msk      (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos)    /*!< 0x0003FFFF */
18632 #define FDCANCCU_CSTAT_OCPC          FDCANCCU_CSTAT_OCPC_Msk                   /*!<Oscillator Clock Period Counter        */
18633 #define FDCANCCU_CSTAT_TQC_Pos       (18U)
18634 #define FDCANCCU_CSTAT_TQC_Msk       (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos)       /*!< 0x1FFC0000 */
18635 #define FDCANCCU_CSTAT_TQC           FDCANCCU_CSTAT_TQC_Msk                    /*!<Time Quanta Counter                    */
18636 #define FDCANCCU_CSTAT_CALS_Pos      (30U)
18637 #define FDCANCCU_CSTAT_CALS_Msk      (0x3UL << FDCANCCU_CSTAT_CALS_Pos)        /*!< 0xC0000000 */
18638 #define FDCANCCU_CSTAT_CALS          FDCANCCU_CSTAT_CALS_Msk                   /*!<Calibration State                      */
18639 
18640 /******************  Bit definition for FDCANCCU_CWD register  ****************/
18641 #define FDCANCCU_CWD_WDC_Pos         (0U)
18642 #define FDCANCCU_CWD_WDC_Msk         (0xFFFFUL << FDCANCCU_CWD_WDC_Pos)        /*!< 0x0000FFFF */
18643 #define FDCANCCU_CWD_WDC             FDCANCCU_CWD_WDC_Msk                      /*!<Watchdog Configuration                 */
18644 #define FDCANCCU_CWD_WDV_Pos         (16U)
18645 #define FDCANCCU_CWD_WDV_Msk         (0xFFFFUL << FDCANCCU_CWD_WDV_Pos)        /*!< 0xFFFF0000 */
18646 #define FDCANCCU_CWD_WDV             FDCANCCU_CWD_WDV_Msk                      /*!<Watchdog Value                         */
18647 
18648 /******************  Bit definition for FDCANCCU_IR register  *****************/
18649 #define FDCANCCU_IR_CWE_Pos          (0U)
18650 #define FDCANCCU_IR_CWE_Msk          (0x1UL << FDCANCCU_IR_CWE_Pos)            /*!< 0x00000001 */
18651 #define FDCANCCU_IR_CWE              FDCANCCU_IR_CWE_Msk                       /*!<Calibration Watchdog Event             */
18652 #define FDCANCCU_IR_CSC_Pos          (1U)
18653 #define FDCANCCU_IR_CSC_Msk          (0x1UL << FDCANCCU_IR_CSC_Pos)            /*!< 0x00000002 */
18654 #define FDCANCCU_IR_CSC              FDCANCCU_IR_CSC_Msk                       /*!<Calibration State Changed              */
18655 
18656 /******************  Bit definition for FDCANCCU_IE register  *****************/
18657 #define FDCANCCU_IE_CWEE_Pos         (0U)
18658 #define FDCANCCU_IE_CWEE_Msk         (0x1UL << FDCANCCU_IE_CWEE_Pos)           /*!< 0x00000001 */
18659 #define FDCANCCU_IE_CWEE             FDCANCCU_IE_CWEE_Msk                      /*!<Calibration Watchdog Event Enable      */
18660 #define FDCANCCU_IE_CSCE_Pos         (1U)
18661 #define FDCANCCU_IE_CSCE_Msk         (0x1UL << FDCANCCU_IE_CSCE_Pos)           /*!< 0x00000002 */
18662 #define FDCANCCU_IE_CSCE             FDCANCCU_IE_CSCE_Msk                      /*!<Calibration State Changed Enable       */
18663 
18664 
18665 /******************************************************************************/
18666 /*                                                                            */
18667 /*                          Flexible Memory Controller                        */
18668 /*                                                                            */
18669 /******************************************************************************/
18670 /******************  Bit definition for FMC_BCRx registers (x=1..4)  **********/
18671 #define FMC_BCRx_MBKEN_Pos         (0U)
18672 #define FMC_BCRx_MBKEN_Msk         (0x1UL << FMC_BCRx_MBKEN_Pos)               /*!< 0x00000001 */
18673 #define FMC_BCRx_MBKEN             FMC_BCRx_MBKEN_Msk                          /*!< Memory bank enable bit */
18674 #define FMC_BCRx_MUXEN_Pos         (1U)
18675 #define FMC_BCRx_MUXEN_Msk         (0x1UL << FMC_BCRx_MUXEN_Pos)               /*!< 0x00000002 */
18676 #define FMC_BCRx_MUXEN             FMC_BCRx_MUXEN_Msk                          /*!< Address/data multiplexing enable bit */
18677 #define FMC_BCRx_MTYP_Pos          (2U)
18678 #define FMC_BCRx_MTYP_Msk          (0x3UL << FMC_BCRx_MTYP_Pos)                /*!< 0x0000000C */
18679 #define FMC_BCRx_MTYP              FMC_BCRx_MTYP_Msk                           /*!< Memory type */
18680 #define FMC_BCRx_MTYP_0            (0x1UL << FMC_BCRx_MTYP_Pos)                /*!< 0x00000004 */
18681 #define FMC_BCRx_MTYP_1            (0x2UL << FMC_BCRx_MTYP_Pos)                /*!< 0x00000008 */
18682 #define FMC_BCRx_MWID_Pos          (4U)
18683 #define FMC_BCRx_MWID_Msk          (0x3UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000030 */
18684 #define FMC_BCRx_MWID              FMC_BCRx_MWID_Msk                           /*!< Memory data bus width */
18685 #define FMC_BCRx_MWID_0            (0x1UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000010 */
18686 #define FMC_BCRx_MWID_1            (0x2UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000020 */
18687 #define FMC_BCRx_FACCEN_Pos        (6U)
18688 #define FMC_BCRx_FACCEN_Msk        (0x1UL << FMC_BCRx_FACCEN_Pos)              /*!< 0x00000040 */
18689 #define FMC_BCRx_FACCEN            FMC_BCRx_FACCEN_Msk                         /*!< Flash access enable */
18690 #define FMC_BCRx_BURSTEN_Pos       (8U)
18691 #define FMC_BCRx_BURSTEN_Msk       (0x1UL << FMC_BCRx_BURSTEN_Pos)             /*!< 0x00000100 */
18692 #define FMC_BCRx_BURSTEN           FMC_BCRx_BURSTEN_Msk                        /*!< Burst enable bit */
18693 #define FMC_BCRx_WAITPOL_Pos       (9U)
18694 #define FMC_BCRx_WAITPOL_Msk       (0x1UL << FMC_BCRx_WAITPOL_Pos)             /*!< 0x00000200 */
18695 #define FMC_BCRx_WAITPOL           FMC_BCRx_WAITPOL_Msk                        /*!< Wait signal polarity bit */
18696 #define FMC_BCRx_WAITCFG_Pos       (11U)
18697 #define FMC_BCRx_WAITCFG_Msk       (0x1UL << FMC_BCRx_WAITCFG_Pos)             /*!< 0x00000800 */
18698 #define FMC_BCRx_WAITCFG           FMC_BCRx_WAITCFG_Msk                        /*!< Wait timing configuration */
18699 #define FMC_BCRx_WREN_Pos          (12U)
18700 #define FMC_BCRx_WREN_Msk          (0x1UL << FMC_BCRx_WREN_Pos)                /*!< 0x00001000 */
18701 #define FMC_BCRx_WREN              FMC_BCRx_WREN_Msk                           /*!< Write enable bit */
18702 #define FMC_BCRx_WAITEN_Pos        (13U)
18703 #define FMC_BCRx_WAITEN_Msk        (0x1UL << FMC_BCRx_WAITEN_Pos)              /*!< 0x00002000 */
18704 #define FMC_BCRx_WAITEN            FMC_BCRx_WAITEN_Msk                         /*!< Wait enable bit */
18705 #define FMC_BCRx_EXTMOD_Pos        (14U)
18706 #define FMC_BCRx_EXTMOD_Msk        (0x1UL << FMC_BCRx_EXTMOD_Pos)              /*!< 0x00004000 */
18707 #define FMC_BCRx_EXTMOD            FMC_BCRx_EXTMOD_Msk                         /*!< Extended mode enable */
18708 #define FMC_BCRx_ASYNCWAIT_Pos     (15U)
18709 #define FMC_BCRx_ASYNCWAIT_Msk     (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)           /*!< 0x00008000 */
18710 #define FMC_BCRx_ASYNCWAIT         FMC_BCRx_ASYNCWAIT_Msk                      /*!< Wait signal during asynchronous transfers */
18711 #define FMC_BCRx_CPSIZE_Pos        (16U)
18712 #define FMC_BCRx_CPSIZE_Msk        (0x7UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00070000 */
18713 #define FMC_BCRx_CPSIZE            FMC_BCRx_CPSIZE_Msk                         /*!< CRAM page size */
18714 #define FMC_BCRx_CPSIZE_0          (0x1UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00010000 */
18715 #define FMC_BCRx_CPSIZE_1          (0x2UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00020000 */
18716 #define FMC_BCRx_CPSIZE_2          (0x4UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00040000 */
18717 #define FMC_BCRx_CBURSTRW_Pos      (19U)
18718 #define FMC_BCRx_CBURSTRW_Msk      (0x1UL << FMC_BCRx_CBURSTRW_Pos)            /*!< 0x00080000 */
18719 #define FMC_BCRx_CBURSTRW          FMC_BCRx_CBURSTRW_Msk                       /*!< Write burst enable */
18720 #define FMC_BCRx_CSCOUNT_Pos       (20U)
18721 #define FMC_BCRx_CSCOUNT_Msk       (0x3UL << FMC_BCRx_CSCOUNT_Pos)             /*!< 0x00300000 */
18722 #define FMC_BCRx_CSCOUNT           FMC_BCRx_CSCOUNT_Msk                        /*!< Chip Select (CS) counter */
18723 #define FMC_BCRx_CSCOUNT_0         (0x1UL << FMC_BCRx_CSCOUNT_Pos)             /*!< 0x00100000 */
18724 #define FMC_BCRx_CSCOUNT_1         (0x2UL << FMC_BCRx_CSCOUNT_Pos)             /*!< 0x00200000 */
18725 #define FMC_BCRx_NBLSET_Pos        (22U)
18726 #define FMC_BCRx_NBLSET_Msk        (0x3UL << FMC_BCRx_NBLSET_Pos)              /*!< 0x00C00000 */
18727 #define FMC_BCRx_NBLSET            FMC_BCRx_NBLSET_Msk                         /*!< Byte lane (NBL) setup */
18728 #define FMC_BCRx_NBLSET_0          (0x1UL << FMC_BCRx_NBLSET_Pos)              /*!< 0x00400000 */
18729 #define FMC_BCRx_NBLSET_1          (0x2UL << FMC_BCRx_NBLSET_Pos)              /*!< 0x00800000 */
18730 
18731 /******************  Bit definition for FMC_BTRx registers (x=1..4)  **********/
18732 #define FMC_BTRx_ADDSET_Pos        (0U)
18733 #define FMC_BTRx_ADDSET_Msk        (0xFUL << FMC_BTRx_ADDSET_Pos)              /*!< 0x0000000F */
18734 #define FMC_BTRx_ADDSET            FMC_BTRx_ADDSET_Msk                         /*!< Address setup phase duration */
18735 #define FMC_BTRx_ADDSET_0          (0x1UL << FMC_BTRx_ADDSET_Pos)              /*!< 0x00000001 */
18736 #define FMC_BTRx_ADDSET_1          (0x2UL << FMC_BTRx_ADDSET_Pos)              /*!< 0x00000002 */
18737 #define FMC_BTRx_ADDSET_2          (0x4UL << FMC_BTRx_ADDSET_Pos)              /*!< 0x00000004 */
18738 #define FMC_BTRx_ADDSET_3          (0x8UL << FMC_BTRx_ADDSET_Pos)              /*!< 0x00000008 */
18739 #define FMC_BTRx_ADDHLD_Pos        (4U)
18740 #define FMC_BTRx_ADDHLD_Msk        (0xFUL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x000000F0 */
18741 #define FMC_BTRx_ADDHLD            FMC_BTRx_ADDHLD_Msk                         /*!< Address-hold phase duration */
18742 #define FMC_BTRx_ADDHLD_0          (0x1UL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x00000010 */
18743 #define FMC_BTRx_ADDHLD_1          (0x2UL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x00000020 */
18744 #define FMC_BTRx_ADDHLD_2          (0x4UL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x00000040 */
18745 #define FMC_BTRx_ADDHLD_3          (0x8UL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x00000080 */
18746 #define FMC_BTRx_DATAST_Pos        (8U)
18747 #define FMC_BTRx_DATAST_Msk        (0xFFUL << FMC_BTRx_DATAST_Pos)             /*!< 0x0000FF00 */
18748 #define FMC_BTRx_DATAST            FMC_BTRx_DATAST_Msk                         /*!< Data-phase duration */
18749 #define FMC_BTRx_DATAST_0          (0x01UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00000100 */
18750 #define FMC_BTRx_DATAST_1          (0x02UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00000200 */
18751 #define FMC_BTRx_DATAST_2          (0x04UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00000400 */
18752 #define FMC_BTRx_DATAST_3          (0x08UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00000800 */
18753 #define FMC_BTRx_DATAST_4          (0x10UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00001000 */
18754 #define FMC_BTRx_DATAST_5          (0x20UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00002000 */
18755 #define FMC_BTRx_DATAST_6          (0x40UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00004000 */
18756 #define FMC_BTRx_DATAST_7          (0x80UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00008000 */
18757 #define FMC_BTRx_BUSTURN_Pos       (16U)
18758 #define FMC_BTRx_BUSTURN_Msk       (0xFUL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x000F0000 */
18759 #define FMC_BTRx_BUSTURN           FMC_BTRx_BUSTURN_Msk                        /*!< Bus turnaround phase duration */
18760 #define FMC_BTRx_BUSTURN_0         (0x1UL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x00010000 */
18761 #define FMC_BTRx_BUSTURN_1         (0x2UL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x00020000 */
18762 #define FMC_BTRx_BUSTURN_2         (0x4UL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x00040000 */
18763 #define FMC_BTRx_BUSTURN_3         (0x8UL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x00080000 */
18764 #define FMC_BTRx_CLKDIV_Pos        (20U)
18765 #define FMC_BTRx_CLKDIV_Msk        (0xFUL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00F00000 */
18766 #define FMC_BTRx_CLKDIV            FMC_BTRx_CLKDIV_Msk                         /*!< Clock divide ratio */
18767 #define FMC_BTRx_CLKDIV_0          (0x1UL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00100000 */
18768 #define FMC_BTRx_CLKDIV_1          (0x2UL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00200000 */
18769 #define FMC_BTRx_CLKDIV_2          (0x4UL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00400000 */
18770 #define FMC_BTRx_CLKDIV_3          (0x8UL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00800000 */
18771 #define FMC_BTRx_DATLAT_Pos        (24U)
18772 #define FMC_BTRx_DATLAT_Msk        (0xFUL << FMC_BTRx_DATLAT_Pos)              /*!< 0x0F000000 */
18773 #define FMC_BTRx_DATLAT            FMC_BTRx_DATLAT_Msk                         /*!< Data latency for synchronous memory */
18774 #define FMC_BTRx_DATLAT_0          (0x1UL << FMC_BTRx_DATLAT_Pos)              /*!< 0x01000000 */
18775 #define FMC_BTRx_DATLAT_1          (0x2UL << FMC_BTRx_DATLAT_Pos)              /*!< 0x02000000 */
18776 #define FMC_BTRx_DATLAT_2          (0x4UL << FMC_BTRx_DATLAT_Pos)              /*!< 0x04000000 */
18777 #define FMC_BTRx_DATLAT_3          (0x8UL << FMC_BTRx_DATLAT_Pos)              /*!< 0x08000000 */
18778 #define FMC_BTRx_ACCMOD_Pos        (28U)
18779 #define FMC_BTRx_ACCMOD_Msk        (0x3UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x30000000 */
18780 #define FMC_BTRx_ACCMOD            FMC_BTRx_ACCMOD_Msk                         /*!< Access mode */
18781 #define FMC_BTRx_ACCMOD_0          (0x1UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x10000000 */
18782 #define FMC_BTRx_ACCMOD_1          (0x2UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x20000000 */
18783 #define FMC_BTRx_DATAHLD_Pos       (30U)
18784 #define FMC_BTRx_DATAHLD_Msk       (0x3UL << FMC_BTRx_DATAHLD_Pos)              /*!< 0xC0000000 */
18785 #define FMC_BTRx_DATAHLD           FMC_BTRx_DATAHLD_Msk                        /*!< Data Hold phase duration */
18786 #define FMC_BTRx_DATAHLD_0         (0x1UL << FMC_BTRx_DATAHLD_Pos)             /*!< 0x40000000 */
18787 #define FMC_BTRx_DATAHLD_1         (0x2UL << FMC_BTRx_DATAHLD_Pos)             /*!< 0x80000000 */
18788 
18789 /*****************  Bit definition for FMC_CFGR register  *****************/
18790 #define FMC_CFGR_CLKDIV_Pos        (16U)
18791 #define FMC_CFGR_CLKDIV_Msk        (0xFUL << FMC_CFGR_CLKDIV_Pos)               /*!< 0x000F0000 */
18792 #define FMC_CFGR_CLKDIV            FMC_CFGR_CLKDIV_Msk                         /*!< Clock divide ratio (for FMC_CLK signal) */
18793 #define FMC_CFGR_CLKDIV_0          (0x1UL << FMC_CFGR_CLKDIV_Pos)              /*!< 0x00010000 */
18794 #define FMC_CFGR_CLKDIV_1          (0x2UL << FMC_CFGR_CLKDIV_Pos)              /*!< 0x00020000 */
18795 #define FMC_CFGR_CLKDIV_2          (0x4UL << FMC_CFGR_CLKDIV_Pos)              /*!< 0x00040000 */
18796 #define FMC_CFGR_CLKDIV_3          (0x8UL << FMC_CFGR_CLKDIV_Pos)              /*!< 0x00080000 */
18797 #define FMC_CFGR_CCLKEN_Pos        (20U)
18798 #define FMC_CFGR_CCLKEN_Msk        (0x1UL << FMC_CFGR_CCLKEN_Pos)               /*!< 0x00100000 */
18799 #define FMC_CFGR_CCLKEN            FMC_CFGR_CCLKEN_Msk                         /*!< Continuous clock enable */
18800 #define FMC_CFGR_BMAP_Pos          (24U)
18801 #define FMC_CFGR_BMAP_Msk          (0x3UL << FMC_CFGR_BMAP_Pos)                 /*!< 0x03000000 */
18802 #define FMC_CFGR_BMAP              FMC_CFGR_BMAP_Msk                           /*!< FMC memory region mapping */
18803 #define FMC_CFGR_BMAP_0            (0x1UL << FMC_CFGR_BMAP_Pos)                /*!< 0x01000000 */
18804 #define FMC_CFGR_BMAP_1            (0x2UL << FMC_CFGR_BMAP_Pos)                /*!< 0x02000000 */
18805 #define FMC_CFGR_FMCEN_Pos         (31U)
18806 #define FMC_CFGR_FMCEN_Msk         (0x1UL << FMC_CFGR_FMCEN_Pos)                /*!< 0x80000000 */
18807 #define FMC_CFGR_FMCEN             FMC_CFGR_FMCEN_Msk                          /*!< FMC controller enable */
18808 
18809 /******************  Bit definition for FMC_PCR register  *********************/
18810 #define FMC_PCR_PWAITEN_Pos        (1U)
18811 #define FMC_PCR_PWAITEN_Msk        (0x1UL << FMC_PCR_PWAITEN_Pos)              /*!< 0x00000002 */
18812 #define FMC_PCR_PWAITEN            FMC_PCR_PWAITEN_Msk                         /*!< Wait feature enable bit */
18813 #define FMC_PCR_PBKEN_Pos          (2U)
18814 #define FMC_PCR_PBKEN_Msk          (0x1UL << FMC_PCR_PBKEN_Pos)                /*!< 0x00000004 */
18815 #define FMC_PCR_PBKEN              FMC_PCR_PBKEN_Msk                           /*!< NAND Flash memory bank enable bit */
18816 #define FMC_PCR_PWID_Pos           (4U)
18817 #define FMC_PCR_PWID_Msk           (0x3UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000030 */
18818 #define FMC_PCR_PWID               FMC_PCR_PWID_Msk                            /*!< Data bus width */
18819 #define FMC_PCR_PWID_0             (0x1UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000010 */
18820 #define FMC_PCR_PWID_1             (0x2UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000020 */
18821 #define FMC_PCR_ECCEN_Pos          (6U)
18822 #define FMC_PCR_ECCEN_Msk          (0x1UL << FMC_PCR_ECCEN_Pos)                /*!< 0x00000040 */
18823 #define FMC_PCR_ECCEN              FMC_PCR_ECCEN_Msk                           /*!< ECC computation logic enable bit */
18824 #define FMC_PCR_ECCALG_Pos         (8U)
18825 #define FMC_PCR_ECCALG_Msk         (0x1UL << FMC_PCR_ECCALG_Pos)               /*!< 0x00000100 */
18826 #define FMC_PCR_ECCALG             FMC_PCR_ECCALG_Msk                          /*!< ECC algorithm */
18827 #define FMC_PCR_TCLR_Pos           (9U)
18828 #define FMC_PCR_TCLR_Msk           (0xFUL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001E00 */
18829 #define FMC_PCR_TCLR               FMC_PCR_TCLR_Msk                            /*!< CLE to RE delay */
18830 #define FMC_PCR_TCLR_0             (0x1UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00000200 */
18831 #define FMC_PCR_TCLR_1             (0x2UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00000400 */
18832 #define FMC_PCR_TCLR_2             (0x4UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00000800 */
18833 #define FMC_PCR_TCLR_3             (0x8UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001000 */
18834 #define FMC_PCR_TAR_Pos            (13U)
18835 #define FMC_PCR_TAR_Msk            (0xFUL << FMC_PCR_TAR_Pos)                  /*!< 0x0001E000 */
18836 #define FMC_PCR_TAR                FMC_PCR_TAR_Msk                             /*!< ALE to RE delay */
18837 #define FMC_PCR_TAR_0              (0x1UL << FMC_PCR_TAR_Pos)                  /*!< 0x00002000 */
18838 #define FMC_PCR_TAR_1              (0x2UL << FMC_PCR_TAR_Pos)                  /*!< 0x00004000 */
18839 #define FMC_PCR_TAR_2              (0x4UL << FMC_PCR_TAR_Pos)                  /*!< 0x00008000 */
18840 #define FMC_PCR_TAR_3              (0x8UL << FMC_PCR_TAR_Pos)                  /*!< 0x00010000 */
18841 #define FMC_PCR_ECCSS_Pos          (17U)
18842 #define FMC_PCR_ECCSS_Msk          (0x7UL << FMC_PCR_ECCSS_Pos)                /*!< 0x000E0000 */
18843 #define FMC_PCR_ECCSS              FMC_PCR_ECCSS_Msk                           /*!< ECC page size */
18844 #define FMC_PCR_ECCSS_0            (0x1UL << FMC_PCR_ECCSS_Pos)                /*!< 0x00020000 */
18845 #define FMC_PCR_ECCSS_1            (0x2UL << FMC_PCR_ECCSS_Pos)                /*!< 0x00040000 */
18846 #define FMC_PCR_ECCSS_2            (0x4UL << FMC_PCR_ECCSS_Pos)                /*!< 0x00080000 */
18847 #define FMC_PCR_BCHECC_Pos         (24U)
18848 #define FMC_PCR_BCHECC_Msk         (0x1UL << FMC_PCR_BCHECC_Pos)                /*!< 0x01000000 */
18849 #define FMC_PCR_BCHECC             FMC_PCR_BCHECC_Msk                          /*!< BCH error correction capability */
18850 #define FMC_PCR_WEN_Pos            (25U)
18851 #define FMC_PCR_WEN_Msk            (0x1UL << FMC_PCR_WEN_Pos)                   /*!< 0x02000000 */
18852 #define FMC_PCR_WEN                FMC_PCR_WEN_Msk                             /*!< Write enable */
18853 
18854 /******************  Bit definition for FMC_SR register  ******************/
18855 #define FMC_SR_ISOST_Pos           (0U)
18856 #define FMC_SR_ISOST_Msk           (0x3UL << FMC_SR_ISOST_Pos)                  /*!< 0x00000003 */
18857 #define FMC_SR_ISOST               FMC_SR_ISOST_Msk                            /*!< FMC isolation state with respect to the AXI interface */
18858 #define FMC_SR_PEF_Pos             (4U)
18859 #define FMC_SR_PEF_Msk             (0x1UL << FMC_SR_PEF_Pos)                    /*!< 0x00000010 */
18860 #define FMC_SR_PEF                 FMC_SR_PEF_Msk                              /*!< Pipe Empty Flag */
18861 #define FMC_SR_NWRF_Pos            (6U)
18862 #define FMC_SR_NWRF_Msk            (0x1UL << FMC_SR_NWRF_Pos)                   /*!< 0x00000040 */
18863 #define FMC_SR_NWRF                FMC_SR_NWRF_Msk                             /*!< NAND write request flag */
18864 
18865 /******************  Bit definition for FMC_PMEM register  ********************/
18866 #define FMC_PMEM_MEMSET_Pos        (0U)
18867 #define FMC_PMEM_MEMSET_Msk        (0xFFUL << FMC_PMEM_MEMSET_Pos)             /*!< 0x000000FF */
18868 #define FMC_PMEM_MEMSET            FMC_PMEM_MEMSET_Msk                         /*!< Common memory setup time */
18869 #define FMC_PMEM_MEMSET_0          (0x01UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000001 */
18870 #define FMC_PMEM_MEMSET_1          (0x02UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000002 */
18871 #define FMC_PMEM_MEMSET_2          (0x04UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000004 */
18872 #define FMC_PMEM_MEMSET_3          (0x08UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000008 */
18873 #define FMC_PMEM_MEMSET_4          (0x10UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000010 */
18874 #define FMC_PMEM_MEMSET_5          (0x20UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000020 */
18875 #define FMC_PMEM_MEMSET_6          (0x40UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000040 */
18876 #define FMC_PMEM_MEMSET_7          (0x80UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000080 */
18877 #define FMC_PMEM_MEMWAIT_Pos       (8U)
18878 #define FMC_PMEM_MEMWAIT_Msk       (0xFFUL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x0000FF00 */
18879 #define FMC_PMEM_MEMWAIT           FMC_PMEM_MEMWAIT_Msk                        /*!< Common memory wait time */
18880 #define FMC_PMEM_MEMWAIT_0         (0x01UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000100 */
18881 #define FMC_PMEM_MEMWAIT_1         (0x02UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000200 */
18882 #define FMC_PMEM_MEMWAIT_2         (0x04UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000400 */
18883 #define FMC_PMEM_MEMWAIT_3         (0x08UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000800 */
18884 #define FMC_PMEM_MEMWAIT_4         (0x10UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00001000 */
18885 #define FMC_PMEM_MEMWAIT_5         (0x20UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00002000 */
18886 #define FMC_PMEM_MEMWAIT_6         (0x40UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00004000 */
18887 #define FMC_PMEM_MEMWAIT_7         (0x80UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00008000 */
18888 #define FMC_PMEM_MEMHOLD_Pos       (16U)
18889 #define FMC_PMEM_MEMHOLD_Msk       (0xFFUL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00FF0000 */
18890 #define FMC_PMEM_MEMHOLD           FMC_PMEM_MEMHOLD_Msk                        /*!< Common memory hold time */
18891 #define FMC_PMEM_MEMHOLD_0         (0x01UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00010000 */
18892 #define FMC_PMEM_MEMHOLD_1         (0x02UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00020000 */
18893 #define FMC_PMEM_MEMHOLD_2         (0x04UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00040000 */
18894 #define FMC_PMEM_MEMHOLD_3         (0x08UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00080000 */
18895 #define FMC_PMEM_MEMHOLD_4         (0x10UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00100000 */
18896 #define FMC_PMEM_MEMHOLD_5         (0x20UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00200000 */
18897 #define FMC_PMEM_MEMHOLD_6         (0x40UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00400000 */
18898 #define FMC_PMEM_MEMHOLD_7         (0x80UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00800000 */
18899 #define FMC_PMEM_MEMHIZ_Pos        (24U)
18900 #define FMC_PMEM_MEMHIZ_Msk        (0xFFUL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0xFF000000 */
18901 #define FMC_PMEM_MEMHIZ            FMC_PMEM_MEMHIZ_Msk                         /*!< Common memory databus Hi-Z time */
18902 #define FMC_PMEM_MEMHIZ_0          (0x01UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x01000000 */
18903 #define FMC_PMEM_MEMHIZ_1          (0x02UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x02000000 */
18904 #define FMC_PMEM_MEMHIZ_2          (0x04UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x04000000 */
18905 #define FMC_PMEM_MEMHIZ_3          (0x08UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x08000000 */
18906 #define FMC_PMEM_MEMHIZ_4          (0x10UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x10000000 */
18907 #define FMC_PMEM_MEMHIZ_5          (0x20UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x20000000 */
18908 #define FMC_PMEM_MEMHIZ_6          (0x40UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x40000000 */
18909 #define FMC_PMEM_MEMHIZ_7          (0x80UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x80000000 */
18910 
18911 /******************  Bit definition for FMC_PATT register  ********************/
18912 #define FMC_PATT_ATTSET_Pos        (0U)
18913 #define FMC_PATT_ATTSET_Msk        (0xFFUL << FMC_PATT_ATTSET_Pos)             /*!< 0x000000FF */
18914 #define FMC_PATT_ATTSET            FMC_PATT_ATTSET_Msk                         /*!< Attribute memory setup time */
18915 #define FMC_PATT_ATTSET_0          (0x01UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000001 */
18916 #define FMC_PATT_ATTSET_1          (0x02UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000002 */
18917 #define FMC_PATT_ATTSET_2          (0x04UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000004 */
18918 #define FMC_PATT_ATTSET_3          (0x08UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000008 */
18919 #define FMC_PATT_ATTSET_4          (0x10UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000010 */
18920 #define FMC_PATT_ATTSET_5          (0x20UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000020 */
18921 #define FMC_PATT_ATTSET_6          (0x40UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000040 */
18922 #define FMC_PATT_ATTSET_7          (0x80UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000080 */
18923 #define FMC_PATT_ATTWAIT_Pos       (8U)
18924 #define FMC_PATT_ATTWAIT_Msk       (0xFFUL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x0000FF00 */
18925 #define FMC_PATT_ATTWAIT           FMC_PATT_ATTWAIT_Msk                        /*!< Attribute memory wait time */
18926 #define FMC_PATT_ATTWAIT_0         (0x01UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000100 */
18927 #define FMC_PATT_ATTWAIT_1         (0x02UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000200 */
18928 #define FMC_PATT_ATTWAIT_2         (0x04UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000400 */
18929 #define FMC_PATT_ATTWAIT_3         (0x08UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000800 */
18930 #define FMC_PATT_ATTWAIT_4         (0x10UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00001000 */
18931 #define FMC_PATT_ATTWAIT_5         (0x20UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00002000 */
18932 #define FMC_PATT_ATTWAIT_6         (0x40UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00004000 */
18933 #define FMC_PATT_ATTWAIT_7         (0x80UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00008000 */
18934 #define FMC_PATT_ATTHOLD_Pos       (16U)
18935 #define FMC_PATT_ATTHOLD_Msk       (0xFFUL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00FF0000 */
18936 #define FMC_PATT_ATTHOLD           FMC_PATT_ATTHOLD_Msk                        /*!< Attribute memory hold time */
18937 #define FMC_PATT_ATTHOLD_0         (0x01UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00010000 */
18938 #define FMC_PATT_ATTHOLD_1         (0x02UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00020000 */
18939 #define FMC_PATT_ATTHOLD_2         (0x04UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00040000 */
18940 #define FMC_PATT_ATTHOLD_3         (0x08UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00080000 */
18941 #define FMC_PATT_ATTHOLD_4         (0x10UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00100000 */
18942 #define FMC_PATT_ATTHOLD_5         (0x20UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00200000 */
18943 #define FMC_PATT_ATTHOLD_6         (0x40UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00400000 */
18944 #define FMC_PATT_ATTHOLD_7         (0x80UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00800000 */
18945 #define FMC_PATT_ATTHIZ_Pos        (24U)
18946 #define FMC_PATT_ATTHIZ_Msk        (0xFFUL << FMC_PATT_ATTHIZ_Pos)             /*!< 0xFF000000 */
18947 #define FMC_PATT_ATTHIZ            FMC_PATT_ATTHIZ_Msk                         /*!< Attribute memory data bus Hi-Z time */
18948 #define FMC_PATT_ATTHIZ_0          (0x01UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x01000000 */
18949 #define FMC_PATT_ATTHIZ_1          (0x02UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x02000000 */
18950 #define FMC_PATT_ATTHIZ_2          (0x04UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x04000000 */
18951 #define FMC_PATT_ATTHIZ_3          (0x08UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x08000000 */
18952 #define FMC_PATT_ATTHIZ_4          (0x10UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x10000000 */
18953 #define FMC_PATT_ATTHIZ_5          (0x20UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x20000000 */
18954 #define FMC_PATT_ATTHIZ_6          (0x40UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x40000000 */
18955 #define FMC_PATT_ATTHIZ_7          (0x80UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x80000000 */
18956 
18957 /*****************  Bit definition for FMC_HPR register  ******************/
18958 #define FMC_HPR_HPR_Pos            (0U)
18959 #define FMC_HPR_HPR_Msk            (0xFFFFFFFFUL << FMC_HPR_HPR_Pos)            /*!< 0xFFFFFFFF */
18960 #define FMC_HPR_HPR                FMC_HPR_HPR_Msk                             /*!< Hamming parity result */
18961 
18962 /****************  Bit definition for FMC_HECCR register  *****************/
18963 #define FMC_HECCR_HECC_Pos         (0U)
18964 #define FMC_HECCR_HECC_Msk         (0xFFFFFFFFUL << FMC_HECCR_HECC_Pos)         /*!< 0xFFFFFFFF */
18965 #define FMC_HECCR_HECC             FMC_HECCR_HECC_Msk                          /*!< ECC result */
18966 
18967 /******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/
18968 #define FMC_BWTRx_ADDSET_Pos       (0U)
18969 #define FMC_BWTRx_ADDSET_Msk       (0xFUL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x0000000F */
18970 #define FMC_BWTRx_ADDSET           FMC_BWTRx_ADDSET_Msk                        /*!< Address setup phase duration */
18971 #define FMC_BWTRx_ADDSET_0         (0x1UL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x00000001 */
18972 #define FMC_BWTRx_ADDSET_1         (0x2UL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x00000002 */
18973 #define FMC_BWTRx_ADDSET_2         (0x4UL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x00000004 */
18974 #define FMC_BWTRx_ADDSET_3         (0x8UL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x00000008 */
18975 #define FMC_BWTRx_ADDHLD_Pos       (4U)
18976 #define FMC_BWTRx_ADDHLD_Msk       (0xFUL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x000000F0 */
18977 #define FMC_BWTRx_ADDHLD           FMC_BWTRx_ADDHLD_Msk                        /*!< Address-hold phase duration */
18978 #define FMC_BWTRx_ADDHLD_0         (0x1UL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x00000010 */
18979 #define FMC_BWTRx_ADDHLD_1         (0x2UL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x00000020 */
18980 #define FMC_BWTRx_ADDHLD_2         (0x4UL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x00000040 */
18981 #define FMC_BWTRx_ADDHLD_3         (0x8UL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x00000080 */
18982 #define FMC_BWTRx_DATAST_Pos       (8U)
18983 #define FMC_BWTRx_DATAST_Msk       (0xFFUL << FMC_BWTRx_DATAST_Pos)            /*!< 0x0000FF00 */
18984 #define FMC_BWTRx_DATAST           FMC_BWTRx_DATAST_Msk                        /*!< Data-phase duration */
18985 #define FMC_BWTRx_DATAST_0         (0x01UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00000100 */
18986 #define FMC_BWTRx_DATAST_1         (0x02UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00000200 */
18987 #define FMC_BWTRx_DATAST_2         (0x04UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00000400 */
18988 #define FMC_BWTRx_DATAST_3         (0x08UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00000800 */
18989 #define FMC_BWTRx_DATAST_4         (0x10UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00001000 */
18990 #define FMC_BWTRx_DATAST_5         (0x20UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00002000 */
18991 #define FMC_BWTRx_DATAST_6         (0x40UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00004000 */
18992 #define FMC_BWTRx_DATAST_7         (0x80UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00008000 */
18993 #define FMC_BWTRx_BUSTURN_Pos      (16U)
18994 #define FMC_BWTRx_BUSTURN_Msk      (0xFUL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x000F0000 */
18995 #define FMC_BWTRx_BUSTURN          FMC_BWTRx_BUSTURN_Msk                       /*!< Bus turnaround phase duration */
18996 #define FMC_BWTRx_BUSTURN_0        (0x1UL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x00010000 */
18997 #define FMC_BWTRx_BUSTURN_1        (0x2UL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x00020000 */
18998 #define FMC_BWTRx_BUSTURN_2        (0x4UL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x00040000 */
18999 #define FMC_BWTRx_BUSTURN_3        (0x8UL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x00080000 */
19000 #define FMC_BWTRx_ACCMOD_Pos       (28U)
19001 #define FMC_BWTRx_ACCMOD_Msk       (0x3UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x30000000 */
19002 #define FMC_BWTRx_ACCMOD           FMC_BWTRx_ACCMOD_Msk                        /*!< Access mode */
19003 #define FMC_BWTRx_ACCMOD_0         (0x1UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x10000000 */
19004 #define FMC_BWTRx_ACCMOD_1         (0x2UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x20000000 */
19005 #define FMC_BWTRx_DATAHLD_Pos      (30U)
19006 #define FMC_BWTRx_DATAHLD_Msk      (0x3UL << FMC_BWTRx_DATAHLD_Pos)             /*!< 0xC0000000 */
19007 #define FMC_BWTRx_DATAHLD          FMC_BWTRx_DATAHLD_Msk                       /*!< Data Hold phase duration */
19008 #define FMC_BWTRx_DATAHLD_0        (0x1UL << FMC_BWTRx_DATAHLD_Pos)            /*!< 0x40000000 */
19009 #define FMC_BWTRx_DATAHLD_1        (0x2UL << FMC_BWTRx_DATAHLD_Pos)            /*!< 0x80000000 */
19010 
19011 /******************  Bit definition for FMC_SDCRx registers (x=1..4)  *********/
19012 #define FMC_SDCRx_NC_Pos           (0U)
19013 #define FMC_SDCRx_NC_Msk           (0x3UL << FMC_SDCRx_NC_Pos)                 /*!< 0x00000003 */
19014 #define FMC_SDCRx_NC               FMC_SDCRx_NC_Msk                            /*!< Number of column address bits */
19015 #define FMC_SDCRx_NC_0             (0x1UL << FMC_SDCRx_NC_Pos)                 /*!< 0x00000001 */
19016 #define FMC_SDCRx_NC_1             (0x2UL << FMC_SDCRx_NC_Pos)                 /*!< 0x00000002 */
19017 #define FMC_SDCRx_NR_Pos           (2U)
19018 #define FMC_SDCRx_NR_Msk           (0x3UL << FMC_SDCRx_NR_Pos)                 /*!< 0x0000000C */
19019 #define FMC_SDCRx_NR               FMC_SDCRx_NR_Msk                            /*!< Number of row address bits */
19020 #define FMC_SDCRx_NR_0             (0x1UL << FMC_SDCRx_NR_Pos)                 /*!< 0x00000004 */
19021 #define FMC_SDCRx_NR_1             (0x2UL << FMC_SDCRx_NR_Pos)                 /*!< 0x00000008 */
19022 #define FMC_SDCRx_MWID_Pos         (4U)
19023 #define FMC_SDCRx_MWID_Msk         (0x3UL << FMC_SDCRx_MWID_Pos)               /*!< 0x00000030 */
19024 #define FMC_SDCRx_MWID             FMC_SDCRx_MWID_Msk                          /*!< Memory data bus width */
19025 #define FMC_SDCRx_MWID_0           (0x1UL << FMC_SDCRx_MWID_Pos)               /*!< 0x00000010 */
19026 #define FMC_SDCRx_MWID_1           (0x2UL << FMC_SDCRx_MWID_Pos)               /*!< 0x00000020 */
19027 #define FMC_SDCRx_NB_Pos           (6U)
19028 #define FMC_SDCRx_NB_Msk           (0x1UL << FMC_SDCRx_NB_Pos)                 /*!< 0x00000040 */
19029 #define FMC_SDCRx_NB               FMC_SDCRx_NB_Msk                            /*!< Number of internal banks */
19030 #define FMC_SDCRx_CAS_Pos          (7U)
19031 #define FMC_SDCRx_CAS_Msk          (0x3UL << FMC_SDCRx_CAS_Pos)                /*!< 0x00000180 */
19032 #define FMC_SDCRx_CAS              FMC_SDCRx_CAS_Msk                           /*!< CAS latency */
19033 #define FMC_SDCRx_CAS_0            (0x1UL << FMC_SDCRx_CAS_Pos)                /*!< 0x00000080 */
19034 #define FMC_SDCRx_CAS_1            (0x2UL << FMC_SDCRx_CAS_Pos)                /*!< 0x00000100 */
19035 #define FMC_SDCRx_WP_Pos           (9U)
19036 #define FMC_SDCRx_WP_Msk           (0x1UL << FMC_SDCRx_WP_Pos)                 /*!< 0x00000200 */
19037 #define FMC_SDCRx_WP               FMC_SDCRx_WP_Msk                            /*!< Write protection */
19038 #define FMC_SDCRx_SDCLK_Pos        (10U)
19039 #define FMC_SDCRx_SDCLK_Msk        (0x3UL << FMC_SDCRx_SDCLK_Pos)              /*!< 0x00000C00 */
19040 #define FMC_SDCRx_SDCLK            FMC_SDCRx_SDCLK_Msk                         /*!< SDRAM clock configuration */
19041 #define FMC_SDCRx_SDCLK_0          (0x1UL << FMC_SDCRx_SDCLK_Pos)              /*!< 0x00000400 */
19042 #define FMC_SDCRx_SDCLK_1          (0x2UL << FMC_SDCRx_SDCLK_Pos)              /*!< 0x00000800 */
19043 #define FMC_SDCRx_RPIPE_Pos        (13U)
19044 #define FMC_SDCRx_RPIPE_Msk        (0x3UL << FMC_SDCRx_RPIPE_Pos)              /*!< 0x00006000 */
19045 #define FMC_SDCRx_RPIPE            FMC_SDCRx_RPIPE_Msk                         /*!< Read pipe */
19046 #define FMC_SDCRx_RPIPE_0          (0x1UL << FMC_SDCRx_RPIPE_Pos)              /*!< 0x00002000 */
19047 #define FMC_SDCRx_RPIPE_1          (0x2UL << FMC_SDCRx_RPIPE_Pos)              /*!< 0x00004000 */
19048 #define FMC_SDCRx_SDEN_Pos         (16U)
19049 #define FMC_SDCRx_SDEN_Msk         (0x1UL << FMC_SDCRx_SDEN_Pos)               /*!< 0x00010000 */
19050 #define FMC_SDCRx_SDEN             FMC_SDCRx_SDEN_Msk                          /*!< SDRAM device enable */
19051 #define FMC_SDCRx_SDINIT_Pos       (17U)
19052 #define FMC_SDCRx_SDINIT_Msk       (0x1UL << FMC_SDCRx_SDINIT_Pos)             /*!< 0x00020000 */
19053 #define FMC_SDCRx_SDINIT           FMC_SDCRx_SDINIT_Msk                        /*!< SDRAM device initialization */
19054 
19055 /******************  Bit definition for FMC_SDTRx(1,2) register  **************/
19056 #define FMC_SDTRx_TMRD_Pos         (0U)
19057 #define FMC_SDTRx_TMRD_Msk         (0xFUL << FMC_SDTRx_TMRD_Pos)               /*!< 0x0000000F */
19058 #define FMC_SDTRx_TMRD             FMC_SDTRx_TMRD_Msk                          /*!< Load mode register to active */
19059 #define FMC_SDTRx_TMRD_0           (0x1UL << FMC_SDTRx_TMRD_Pos)               /*!< 0x00000001 */
19060 #define FMC_SDTRx_TMRD_1           (0x2UL << FMC_SDTRx_TMRD_Pos)               /*!< 0x00000002 */
19061 #define FMC_SDTRx_TMRD_2           (0x4UL << FMC_SDTRx_TMRD_Pos)               /*!< 0x00000004 */
19062 #define FMC_SDTRx_TMRD_3           (0x8UL << FMC_SDTRx_TMRD_Pos)               /*!< 0x00000008 */
19063 #define FMC_SDTRx_TXSR_Pos         (4U)
19064 #define FMC_SDTRx_TXSR_Msk         (0xFUL << FMC_SDTRx_TXSR_Pos)               /*!< 0x000000F0 */
19065 #define FMC_SDTRx_TXSR             FMC_SDTRx_TXSR_Msk                          /*!<Exit self-refresh delay */
19066 #define FMC_SDTRx_TXSR_0           (0x1UL << FMC_SDTRx_TXSR_Pos)               /*!< 0x00000010 */
19067 #define FMC_SDTRx_TXSR_1           (0x2UL << FMC_SDTRx_TXSR_Pos)               /*!< 0x00000020 */
19068 #define FMC_SDTRx_TXSR_2           (0x4UL << FMC_SDTRx_TXSR_Pos)               /*!< 0x00000040 */
19069 #define FMC_SDTRx_TXSR_3           (0x8UL << FMC_SDTRx_TXSR_Pos)               /*!< 0x00000080 */
19070 #define FMC_SDTRx_TRAS_Pos         (8U)
19071 #define FMC_SDTRx_TRAS_Msk         (0xFUL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000F00 */
19072 #define FMC_SDTRx_TRAS             FMC_SDTRx_TRAS_Msk                          /*!< Self refresh time */
19073 #define FMC_SDTRx_TRAS_0           (0x1UL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000100 */
19074 #define FMC_SDTRx_TRAS_1           (0x2UL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000200 */
19075 #define FMC_SDTRx_TRAS_2           (0x4UL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000400 */
19076 #define FMC_SDTRx_TRAS_3           (0x8UL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000800 */
19077 #define FMC_SDTRx_TRC_Pos          (12U)
19078 #define FMC_SDTRx_TRC_Msk          (0xFUL << FMC_SDTRx_TRC_Pos)                /*!< 0x0000F000 */
19079 #define FMC_SDTRx_TRC              FMC_SDTRx_TRC_Msk                           /*!< Row cycle delay */
19080 #define FMC_SDTRx_TRC_0            (0x1UL << FMC_SDTRx_TRC_Pos)                /*!< 0x00001000 */
19081 #define FMC_SDTRx_TRC_1            (0x2UL << FMC_SDTRx_TRC_Pos)                /*!< 0x00002000 */
19082 #define FMC_SDTRx_TRC_2            (0x4UL << FMC_SDTRx_TRC_Pos)                /*!< 0x00004000 */
19083 #define FMC_SDTRx_TRC_3            (0x8UL << FMC_SDTRx_TRC_Pos)                /*!< 0x00008000 */
19084 #define FMC_SDTRx_TWR_Pos          (16U)
19085 #define FMC_SDTRx_TWR_Msk          (0xFUL << FMC_SDTRx_TWR_Pos)                /*!< 0x000F0000 */
19086 #define FMC_SDTRx_TWR              FMC_SDTRx_TWR_Msk                           /*!< Recovery delay */
19087 #define FMC_SDTRx_TWR_0            (0x1UL << FMC_SDTRx_TWR_Pos)                /*!< 0x00010000 */
19088 #define FMC_SDTRx_TWR_1            (0x2UL << FMC_SDTRx_TWR_Pos)                /*!< 0x00020000 */
19089 #define FMC_SDTRx_TWR_2            (0x4UL << FMC_SDTRx_TWR_Pos)                /*!< 0x00040000 */
19090 #define FMC_SDTRx_TWR_3            (0x8UL << FMC_SDTRx_TWR_Pos)                /*!< 0x00080000 */
19091 #define FMC_SDTRx_TRP_Pos          (20U)
19092 #define FMC_SDTRx_TRP_Msk          (0xFUL << FMC_SDTRx_TRP_Pos)                /*!< 0x00F00000 */
19093 #define FMC_SDTRx_TRP              FMC_SDTRx_TRP_Msk                           /*!< Row precharge delay */
19094 #define FMC_SDTRx_TRP_0            (0x1UL << FMC_SDTRx_TRP_Pos)                /*!< 0x00100000 */
19095 #define FMC_SDTRx_TRP_1            (0x2UL << FMC_SDTRx_TRP_Pos)                /*!< 0x00200000 */
19096 #define FMC_SDTRx_TRP_2            (0x4UL << FMC_SDTRx_TRP_Pos)                /*!< 0x00400000 */
19097 #define FMC_SDTRx_TRP_3            (0x8UL << FMC_SDTRx_TRP_Pos)                /*!< 0x00800000 */
19098 #define FMC_SDTRx_TRCD_Pos         (24U)
19099 #define FMC_SDTRx_TRCD_Msk         (0xFUL << FMC_SDTRx_TRCD_Pos)               /*!< 0x0F000000 */
19100 #define FMC_SDTRx_TRCD             FMC_SDTRx_TRCD_Msk                          /*!< Row to column delay */
19101 #define FMC_SDTRx_TRCD_0           (0x1UL << FMC_SDTRx_TRCD_Pos)               /*!< 0x01000000 */
19102 #define FMC_SDTRx_TRCD_1           (0x2UL << FMC_SDTRx_TRCD_Pos)               /*!< 0x02000000 */
19103 #define FMC_SDTRx_TRCD_2           (0x4UL << FMC_SDTRx_TRCD_Pos)               /*!< 0x04000000 */
19104 #define FMC_SDTRx_TRCD_3           (0x8UL << FMC_SDTRx_TRCD_Pos)               /*!< 0x08000000 */
19105 
19106 /******************  Bit definition for FMC_SDCMR register  *******************/
19107 #define FMC_SDCMR_MODE_Pos         (0U)
19108 #define FMC_SDCMR_MODE_Msk         (0x7UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000007 */
19109 #define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!< Command mode */
19110 #define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000001 */
19111 #define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000002 */
19112 #define FMC_SDCMR_MODE_2           (0x4UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000004 */
19113 #define FMC_SDCMR_DS2_Pos          (3U)
19114 #define FMC_SDCMR_DS2_Msk          (0x1UL << FMC_SDCMR_DS2_Pos)                /*!< 0x00000008 */
19115 #define FMC_SDCMR_DS2              FMC_SDCMR_DS2_Msk                           /*!< Command targeting SDRAM device 2 */
19116 #define FMC_SDCMR_DS1_Pos          (4U)
19117 #define FMC_SDCMR_DS1_Msk          (0x1UL << FMC_SDCMR_DS1_Pos)                /*!< 0x00000010 */
19118 #define FMC_SDCMR_DS1              FMC_SDCMR_DS1_Msk                           /*!< Command targeting SDRAM device 1 */
19119 #define FMC_SDCMR_NRFS_Pos         (5U)
19120 #define FMC_SDCMR_NRFS_Msk         (0xFUL << FMC_SDCMR_NRFS_Pos)               /*!< 0x000001E0 */
19121 #define FMC_SDCMR_NRFS             FMC_SDCMR_NRFS_Msk                          /*!< Number of auto-refresh */
19122 #define FMC_SDCMR_NRFS_0           (0x1UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000020 */
19123 #define FMC_SDCMR_NRFS_1           (0x2UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000040 */
19124 #define FMC_SDCMR_NRFS_2           (0x4UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000080 */
19125 #define FMC_SDCMR_NRFS_3           (0x8UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000100 */
19126 #define FMC_SDCMR_MRD_Pos          (9U)
19127 #define FMC_SDCMR_MRD_Msk          (0x3FFFUL << FMC_SDCMR_MRD_Pos)             /*!< 0x007FFE00 */
19128 #define FMC_SDCMR_MRD              FMC_SDCMR_MRD_Msk                           /*!< Mode register definition */
19129 
19130 /******************  Bit definition for FMC_SDRTR register  *******************/
19131 #define FMC_SDRTR_CRE_Pos          (0U)
19132 #define FMC_SDRTR_CRE_Msk          (0x1UL << FMC_SDRTR_CRE_Pos)                /*!< 0x00000001 */
19133 #define FMC_SDRTR_CRE              FMC_SDRTR_CRE_Msk                           /*!< Clear refresh error flag */
19134 #define FMC_SDRTR_RFSCNT_Pos       (1U)
19135 #define FMC_SDRTR_RFSCNT_Msk       (0x1FFFUL << FMC_SDRTR_RFSCNT_Pos)          /*!< 0x00003FFE */
19136 #define FMC_SDRTR_RFSCNT           FMC_SDRTR_RFSCNT_Msk                        /*!< Refresh timer count */
19137 #define FMC_SDRTR_REIE_Pos         (14U)
19138 #define FMC_SDRTR_REIE_Msk         (0x1UL << FMC_SDRTR_REIE_Pos)               /*!< 0x00004000 */
19139 #define FMC_SDRTR_REIE             FMC_SDRTR_REIE_Msk                          /*!< RES interrupt enable */
19140 
19141 /******************  Bit definition for FMC_SDSR register  ********************/
19142 #define FMC_SDSR_RE_Pos            (0U)
19143 #define FMC_SDSR_RE_Msk            (0x1UL << FMC_SDSR_RE_Pos)                  /*!< 0x00000001 */
19144 #define FMC_SDSR_RE                FMC_SDSR_RE_Msk                             /*!< Refresh error flag */
19145 #define FMC_SDSR_MODES1_Pos        (1U)
19146 #define FMC_SDSR_MODES1_Msk        (0x3UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000006 */
19147 #define FMC_SDSR_MODES1            FMC_SDSR_MODES1_Msk                         /*!< Status mode for bank 1 */
19148 #define FMC_SDSR_MODES1_0          (0x1UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000002 */
19149 #define FMC_SDSR_MODES1_1          (0x2UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000004 */
19150 #define FMC_SDSR_MODES2_Pos        (3U)
19151 #define FMC_SDSR_MODES2_Msk        (0x3UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000018 */
19152 #define FMC_SDSR_MODES2            FMC_SDSR_MODES2_Msk                         /*!< Status mode for bank 2 */
19153 #define FMC_SDSR_MODES2_0          (0x1UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000008 */
19154 #define FMC_SDSR_MODES2_1          (0x2UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000010 */
19155 #define FMC_SDSR_CMDOK_Pos         (15U)
19156 #define FMC_SDSR_CMDOK_Msk         (0x1UL << FMC_SDSR_CMDOK_Pos)               /*!< 0x00004000 */
19157 #define FMC_SDSR_CMDOK             FMC_SDSR_CMDOK_Msk                          /*!< Previous command status */
19158 
19159 /*******************  Bit definition for FMC_IER register  ********************/
19160 #define FMC_IER_IREE_Pos              (0U)
19161 #define FMC_IER_IREE_Msk              (0x1UL << FMC_IER_IREE_Pos)               /*!< 0x00000001 */
19162 #define FMC_IER_IREE                  FMC_IER_IREE_Msk                         /*!< Interrupt rising edge detection enable bit */
19163 #define FMC_IER_IHLE_Pos              (1U)
19164 #define FMC_IER_IHLE_Msk              (0x1UL << FMC_IER_IHLE_Pos)               /*!< 0x00000002 */
19165 #define FMC_IER_IHLE                  FMC_IER_IHLE_Msk                         /*!< Interrupt high-level detection enable bit */
19166 #define FMC_IER_IFEE_Pos              (2U)
19167 #define FMC_IER_IFEE_Msk              (0x1UL << FMC_IER_IFEE_Pos)               /*!< 0x00000004 */
19168 #define FMC_IER_IFEE                  FMC_IER_IFEE_Msk                         /*!< Interrupt falling edge detection enable bit */
19169 
19170 /*******************  Bit definition for FMC_ISR register  ********************/
19171 #define FMC_ISR_IREF_Pos              (0U)
19172 #define FMC_ISR_IREF_Msk              (0x1UL << FMC_ISR_IREF_Pos)               /*!< 0x00000001 */
19173 #define FMC_ISR_IREF                  FMC_ISR_IREF_Msk                         /*!< Interrupt rising edge flag */
19174 #define FMC_ISR_IHLF_Pos              (1U)
19175 #define FMC_ISR_IHLF_Msk              (0x1UL << FMC_ISR_IHLF_Pos)               /*!< 0x00000002 */
19176 #define FMC_ISR_IHLF                  FMC_ISR_IHLF_Msk                         /*!< Interrupt high-level flag */
19177 #define FMC_ISR_IFEF_Pos              (2U)
19178 #define FMC_ISR_IFEF_Msk              (0x1UL << FMC_ISR_IFEF_Pos)               /*!< 0x00000004 */
19179 #define FMC_ISR_IFEF                  FMC_ISR_IFEF_Msk                         /*!< Interrupt falling edge flag */
19180 
19181 /*******************  Bit definition for FMC_ICR register  ********************/
19182 #define FMC_ICR_CIREF_Pos             (0U)
19183 #define FMC_ICR_CIREF_Msk             (0x1UL << FMC_ICR_CIREF_Pos)              /*!< 0x00000001 */
19184 #define FMC_ICR_CIREF                 FMC_ICR_CIREF_Msk                        /*!< Clear Interrupt rising edge flag */
19185 #define FMC_ICR_CIHLF_Pos             (1U)
19186 #define FMC_ICR_CIHLF_Msk             (0x1UL << FMC_ICR_CIHLF_Pos)              /*!< 0x00000002 */
19187 #define FMC_ICR_CIHLF                 FMC_ICR_CIHLF_Msk                        /*!< Clear Interrupt high-level flag */
19188 #define FMC_ICR_CIFEF_Pos             (2U)
19189 #define FMC_ICR_CIFEF_Msk             (0x1UL << FMC_ICR_CIFEF_Pos)              /*!< 0x00000004 */
19190 #define FMC_ICR_CIFEF                 FMC_ICR_CIFEF_Msk                        /*!< Clear Interrupt falling edge flag */
19191 
19192 /****************  Bit definition for FMC_CSQCR register  *****************/
19193 #define FMC_CSQCR_CSQSTART_Pos        (0U)
19194 #define FMC_CSQCR_CSQSTART_Msk        (0x1UL << FMC_CSQCR_CSQSTART_Pos)         /*!< 0x00000001 */
19195 #define FMC_CSQCR_CSQSTART            FMC_CSQCR_CSQSTART_Msk                   /*!< Command Sequencer Enable */
19196 
19197 /***************  Bit definition for FMC_CSQCFGR1 register  ***************/
19198 #define FMC_CSQCFGR1_CMD2EN_Pos       (1U)
19199 #define FMC_CSQCFGR1_CMD2EN_Msk       (0x1UL << FMC_CSQCFGR1_CMD2EN_Pos)        /*!< 0x00000002 */
19200 #define FMC_CSQCFGR1_CMD2EN           FMC_CSQCFGR1_CMD2EN_Msk                  /*!< Command cycle 2 Enable */
19201 #define FMC_CSQCFGR1_DMADEN_Pos       (2U)
19202 #define FMC_CSQCFGR1_DMADEN_Msk       (0x1UL << FMC_CSQCFGR1_DMADEN_Pos)        /*!< 0x00000004 */
19203 #define FMC_CSQCFGR1_DMADEN           FMC_CSQCFGR1_DMADEN_Msk                  /*!< Command sequencer DMA request data enable */
19204 #define FMC_CSQCFGR1_ACYNBR_Pos       (4U)
19205 #define FMC_CSQCFGR1_ACYNBR_Msk       (0x7UL << FMC_CSQCFGR1_ACYNBR_Pos)        /*!< 0x00000070 */
19206 #define FMC_CSQCFGR1_ACYNBR           FMC_CSQCFGR1_ACYNBR_Msk                  /*!< Address Cycle number */
19207 #define FMC_CSQCFGR1_CMD1_Pos         (8U)
19208 #define FMC_CSQCFGR1_CMD1_Msk         (0xFFUL << FMC_CSQCFGR1_CMD1_Pos)         /*!< 0x0000FF00 */
19209 #define FMC_CSQCFGR1_CMD1             FMC_CSQCFGR1_CMD1_Msk                    /*!< Command 1 sequencer */
19210 #define FMC_CSQCFGR1_CMD2_Pos         (16U)
19211 #define FMC_CSQCFGR1_CMD2_Msk         (0xFFUL << FMC_CSQCFGR1_CMD2_Pos)         /*!< 0x00FF0000 */
19212 #define FMC_CSQCFGR1_CMD2             FMC_CSQCFGR1_CMD2_Msk                    /*!< Command 2 sequencer */
19213 #define FMC_CSQCFGR1_CMD1T_Pos        (24U)
19214 #define FMC_CSQCFGR1_CMD1T_Msk        (0x1UL << FMC_CSQCFGR1_CMD1T_Pos)         /*!< 0x01000000 */
19215 #define FMC_CSQCFGR1_CMD1T            FMC_CSQCFGR1_CMD1T_Msk                   /*!< Command 1 Sequencer timings */
19216 #define FMC_CSQCFGR1_CMD2T_Pos        (25U)
19217 #define FMC_CSQCFGR1_CMD2T_Msk        (0x1UL << FMC_CSQCFGR1_CMD2T_Pos)         /*!< 0x02000000 */
19218 #define FMC_CSQCFGR1_CMD2T            FMC_CSQCFGR1_CMD2T_Msk                   /*!< Command 2 Sequencer timings */
19219 
19220 /***************  Bit definition for FMC_CSQCFGR2 register  ***************/
19221 #define FMC_CSQCFGR2_SQSDTEN_Pos      (0U)
19222 #define FMC_CSQCFGR2_SQSDTEN_Msk      (0x1UL << FMC_CSQCFGR2_SQSDTEN_Pos)       /*!< 0x00000001 */
19223 #define FMC_CSQCFGR2_SQSDTEN          FMC_CSQCFGR2_SQSDTEN_Msk                 /*!< Sequencer spare data transfer enable */
19224 #define FMC_CSQCFGR2_RCMD2EN_Pos      (1U)
19225 #define FMC_CSQCFGR2_RCMD2EN_Msk      (0x1UL << FMC_CSQCFGR2_RCMD2EN_Pos)       /*!< 0x00000002 */
19226 #define FMC_CSQCFGR2_RCMD2EN          FMC_CSQCFGR2_RCMD2EN_Msk                 /*!< Random Command 2 sequencer enable */
19227 #define FMC_CSQCFGR2_DMASEN_Pos       (2U)
19228 #define FMC_CSQCFGR2_DMASEN_Msk       (0x1UL << FMC_CSQCFGR2_DMASEN_Pos)        /*!< 0x00000004 */
19229 #define FMC_CSQCFGR2_DMASEN           FMC_CSQCFGR2_DMASEN_Msk                  /*!< Command sequencer DMA request decoding status enable */
19230 #define FMC_CSQCFGR2_RCMD1_Pos        (8U)
19231 #define FMC_CSQCFGR2_RCMD1_Msk        (0xFFUL << FMC_CSQCFGR2_RCMD1_Pos)        /*!< 0x0000FF00 */
19232 #define FMC_CSQCFGR2_RCMD1            FMC_CSQCFGR2_RCMD1_Msk                   /*!< Random Command 1 sequencer */
19233 #define FMC_CSQCFGR2_RCMD2_Pos        (16U)
19234 #define FMC_CSQCFGR2_RCMD2_Msk        (0xFFUL << FMC_CSQCFGR2_RCMD2_Pos)        /*!< 0x00FF0000 */
19235 #define FMC_CSQCFGR2_RCMD2            FMC_CSQCFGR2_RCMD2_Msk                   /*!< Random Command 2 sequencer */
19236 #define FMC_CSQCFGR2_RCMD1T_Pos       (24U)
19237 #define FMC_CSQCFGR2_RCMD1T_Msk       (0x1UL << FMC_CSQCFGR2_RCMD1T_Pos)        /*!< 0x01000000 */
19238 #define FMC_CSQCFGR2_RCMD1T           FMC_CSQCFGR2_RCMD1T_Msk                  /*!< Command 1 sequencer timings */
19239 #define FMC_CSQCFGR2_RCMD2T_Pos       (25U)
19240 #define FMC_CSQCFGR2_RCMD2T_Msk       (0x1UL << FMC_CSQCFGR2_RCMD2T_Pos)        /*!< 0x02000000 */
19241 #define FMC_CSQCFGR2_RCMD2T           FMC_CSQCFGR2_RCMD2T_Msk                  /*!< Command 1 sequencer timings */
19242 
19243 /***************  Bit definition for FMC_CSQCFGR3 register  ***************/
19244 #define FMC_CSQCFGR3_SNBR_Pos         (8U)
19245 #define FMC_CSQCFGR3_SNBR_Msk         (0x3FUL << FMC_CSQCFGR3_SNBR_Pos)         /*!< 0x00003F00 */
19246 #define FMC_CSQCFGR3_SNBR             FMC_CSQCFGR3_SNBR_Msk                    /*!< Number of sectors to be read/written */
19247 #define FMC_CSQCFGR3_AC1T_Pos         (16U)
19248 #define FMC_CSQCFGR3_AC1T_Msk         (0x1UL << FMC_CSQCFGR3_AC1T_Pos)          /*!< 0x00010000 */
19249 #define FMC_CSQCFGR3_AC1T             FMC_CSQCFGR3_AC1T_Msk                    /*!< Address cycle 1 sequencer timings */
19250 #define FMC_CSQCFGR3_AC2T_Pos         (17U)
19251 #define FMC_CSQCFGR3_AC2T_Msk         (0x1UL << FMC_CSQCFGR3_AC2T_Pos)          /*!< 0x00020000 */
19252 #define FMC_CSQCFGR3_AC2T             FMC_CSQCFGR3_AC2T_Msk                    /*!< Address cycle 2 sequencer timings */
19253 #define FMC_CSQCFGR3_AC3T_Pos         (18U)
19254 #define FMC_CSQCFGR3_AC3T_Msk         (0x1UL << FMC_CSQCFGR3_AC3T_Pos)          /*!< 0x00040000 */
19255 #define FMC_CSQCFGR3_AC3T             FMC_CSQCFGR3_AC3T_Msk                    /*!< Address cycle 3 sequencer timings */
19256 #define FMC_CSQCFGR3_AC4T_Pos         (19U)
19257 #define FMC_CSQCFGR3_AC4T_Msk         (0x1UL << FMC_CSQCFGR3_AC4T_Pos)          /*!< 0x00080000 */
19258 #define FMC_CSQCFGR3_AC4T             FMC_CSQCFGR3_AC4T_Msk                    /*!< Address cycle 4sequencer timings */
19259 #define FMC_CSQCFGR3_AC5T_Pos         (20U)
19260 #define FMC_CSQCFGR3_AC5T_Msk         (0x1UL << FMC_CSQCFGR3_AC5T_Pos)          /*!< 0x00100000 */
19261 #define FMC_CSQCFGR3_AC5T             FMC_CSQCFGR3_AC5T_Msk                    /*!< Address cycle 5 sequencer timings */
19262 #define FMC_CSQCFGR3_SDT_Pos          (21U)
19263 #define FMC_CSQCFGR3_SDT_Msk          (0x1UL << FMC_CSQCFGR3_SDT_Pos)           /*!< 0x00200000 */
19264 #define FMC_CSQCFGR3_SDT              FMC_CSQCFGR3_SDT_Msk                     /*!< Spare data transfer sequencer timings */
19265 #define FMC_CSQCFGR3_RAC1T_Pos        (22U)
19266 #define FMC_CSQCFGR3_RAC1T_Msk        (0x1UL << FMC_CSQCFGR3_RAC1T_Pos)         /*!< 0x00400000 */
19267 #define FMC_CSQCFGR3_RAC1T            FMC_CSQCFGR3_RAC1T_Msk                   /*!< Random Address cycle 1 sequencer timings */
19268 #define FMC_CSQCFGR3_RAC2T_Pos        (23U)
19269 #define FMC_CSQCFGR3_RAC2T_Msk        (0x1UL << FMC_CSQCFGR3_RAC2T_Pos)         /*!< 0x00800000 */
19270 #define FMC_CSQCFGR3_RAC2T            FMC_CSQCFGR3_RAC2T_Msk                   /*!< Random Address cycle 2 sequencer timings */
19271 
19272 /****************  Bit definition for FMC_CSQAR1 register  ****************/
19273 #define FMC_CSQAR1_ADDC1_Pos          (0U)
19274 #define FMC_CSQAR1_ADDC1_Msk          (0xFFUL << FMC_CSQAR1_ADDC1_Pos)          /*!< 0x000000FF */
19275 #define FMC_CSQAR1_ADDC1              FMC_CSQAR1_ADDC1_Msk                     /*!< Address Cycle 1 */
19276 #define FMC_CSQAR1_ADDC2_Pos          (8U)
19277 #define FMC_CSQAR1_ADDC2_Msk          (0xFFUL << FMC_CSQAR1_ADDC2_Pos)          /*!< 0x0000FF00 */
19278 #define FMC_CSQAR1_ADDC2              FMC_CSQAR1_ADDC2_Msk                     /*!< Address Cycle 2 */
19279 #define FMC_CSQAR1_ADDC3_Pos          (16U)
19280 #define FMC_CSQAR1_ADDC3_Msk          (0xFFUL << FMC_CSQAR1_ADDC3_Pos)          /*!< 0x00FF0000 */
19281 #define FMC_CSQAR1_ADDC3              FMC_CSQAR1_ADDC3_Msk                     /*!< Address Cycle 3 */
19282 #define FMC_CSQAR1_ADDC4_Pos          (24U)
19283 #define FMC_CSQAR1_ADDC4_Msk          (0xFFUL << FMC_CSQAR1_ADDC4_Pos)          /*!< 0xFF000000 */
19284 #define FMC_CSQAR1_ADDC4              FMC_CSQAR1_ADDC4_Msk                     /*!< Address Cycle 4 */
19285 
19286 /****************  Bit definition for FMC_CSQAR2 register  ****************/
19287 #define FMC_CSQAR2_ADDC5_Pos          (0U)
19288 #define FMC_CSQAR2_ADDC5_Msk          (0xFFUL << FMC_CSQAR2_ADDC5_Pos)          /*!< 0x000000FF */
19289 #define FMC_CSQAR2_ADDC5              FMC_CSQAR2_ADDC5_Msk                     /*!< Address Cycle 5 */
19290 #define FMC_CSQAR2_SAO_Pos            (16U)
19291 #define FMC_CSQAR2_SAO_Msk            (0xFFFFUL << FMC_CSQAR2_SAO_Pos)          /*!< 0xFFFF0000 */
19292 #define FMC_CSQAR2_SAO                FMC_CSQAR2_SAO_Msk                       /*!< Spare Area Address Offset. */
19293 
19294 /****************  Bit definition for FMC_CSQIER register  ****************/
19295 #define FMC_CSQIER_TCIE_Pos           (0U)
19296 #define FMC_CSQIER_TCIE_Msk           (0x1UL << FMC_CSQIER_TCIE_Pos)            /*!< 0x00000001 */
19297 #define FMC_CSQIER_TCIE               FMC_CSQIER_TCIE_Msk                      /*!< Transfer Complete Interrupt enable */
19298 #define FMC_CSQIER_SCIE_Pos           (1U)
19299 #define FMC_CSQIER_SCIE_Msk           (0x1UL << FMC_CSQIER_SCIE_Pos)            /*!< 0x00000002 */
19300 #define FMC_CSQIER_SCIE               FMC_CSQIER_SCIE_Msk                      /*!< Sector Complete interrupt enable */
19301 #define FMC_CSQIER_SEIE_Pos           (2U)
19302 #define FMC_CSQIER_SEIE_Msk           (0x1UL << FMC_CSQIER_SEIE_Pos)            /*!< 0x00000004 */
19303 #define FMC_CSQIER_SEIE               FMC_CSQIER_SEIE_Msk                      /*!< Sector Error interrupt enable */
19304 #define FMC_CSQIER_SUEIE_Pos          (3U)
19305 #define FMC_CSQIER_SUEIE_Msk          (0x1UL << FMC_CSQIER_SUEIE_Pos)           /*!< 0x00000008 */
19306 #define FMC_CSQIER_SUEIE              FMC_CSQIER_SUEIE_Msk                     /*!< Sector Uncorrectable Error interrupt enable */
19307 #define FMC_CSQIER_CMDTCIE_Pos        (4U)
19308 #define FMC_CSQIER_CMDTCIE_Msk        (0x1UL << FMC_CSQIER_CMDTCIE_Pos)         /*!< 0x00000010 */
19309 #define FMC_CSQIER_CMDTCIE            FMC_CSQIER_CMDTCIE_Msk                   /*!< Command Transfer Complete interrupt enable */
19310 
19311 /****************  Bit definition for FMC_CSQISR register  ****************/
19312 #define FMC_CSQISR_TCF_Pos            (0U)
19313 #define FMC_CSQISR_TCF_Msk            (0x1UL << FMC_CSQISR_TCF_Pos)             /*!< 0x00000001 */
19314 #define FMC_CSQISR_TCF                FMC_CSQISR_TCF_Msk                       /*!< Transfer Complete flag */
19315 #define FMC_CSQISR_SCF_Pos            (1U)
19316 #define FMC_CSQISR_SCF_Msk            (0x1UL << FMC_CSQISR_SCF_Pos)             /*!< 0x00000002 */
19317 #define FMC_CSQISR_SCF                FMC_CSQISR_SCF_Msk                       /*!< Sector Complete flag */
19318 #define FMC_CSQISR_SEF_Pos            (2U)
19319 #define FMC_CSQISR_SEF_Msk            (0x1UL << FMC_CSQISR_SEF_Pos)             /*!< 0x00000004 */
19320 #define FMC_CSQISR_SEF                FMC_CSQISR_SEF_Msk                       /*!< Sector Error flag */
19321 #define FMC_CSQISR_SUEF_Pos           (3U)
19322 #define FMC_CSQISR_SUEF_Msk           (0x1UL << FMC_CSQISR_SUEF_Pos)            /*!< 0x00000008 */
19323 #define FMC_CSQISR_SUEF               FMC_CSQISR_SUEF_Msk                      /*!< Sector Uncorrectable Error flag */
19324 #define FMC_CSQISR_CMDTCF_Pos         (4U)
19325 #define FMC_CSQISR_CMDTCF_Msk         (0x1UL << FMC_CSQISR_CMDTCF_Pos)          /*!< 0x00000010 */
19326 #define FMC_CSQISR_CMDTCF             FMC_CSQISR_CMDTCF_Msk                    /*!< Command Transfer Complete flag */
19327 
19328 /****************  Bit definition for FMC_CSQICR register  ****************/
19329 #define FMC_CSQICR_CTCF_Pos           (0U)
19330 #define FMC_CSQICR_CTCF_Msk           (0x1UL << FMC_CSQICR_CTCF_Pos)            /*!< 0x00000001 */
19331 #define FMC_CSQICR_CTCF               FMC_CSQICR_CTCF_Msk                      /*!< Clear Transfer Complete flag */
19332 #define FMC_CSQICR_CSCF_Pos           (1U)
19333 #define FMC_CSQICR_CSCF_Msk           (0x1UL << FMC_CSQICR_CSCF_Pos)            /*!< 0x00000002 */
19334 #define FMC_CSQICR_CSCF               FMC_CSQICR_CSCF_Msk                      /*!< Clear Sector Complete flag */
19335 #define FMC_CSQICR_CSEF_Pos           (2U)
19336 #define FMC_CSQICR_CSEF_Msk           (0x1UL << FMC_CSQICR_CSEF_Pos)            /*!< 0x00000004 */
19337 #define FMC_CSQICR_CSEF               FMC_CSQICR_CSEF_Msk                      /*!< Clear Sector Error flag */
19338 #define FMC_CSQICR_CSUEF_Pos          (3U)
19339 #define FMC_CSQICR_CSUEF_Msk          (0x1UL << FMC_CSQICR_CSUEF_Pos)           /*!< 0x00000008 */
19340 #define FMC_CSQICR_CSUEF              FMC_CSQICR_CSUEF_Msk                     /*!< Clear Sector uncorrectable Error flag */
19341 #define FMC_CSQICR_CCMDTCF_Pos        (4U)
19342 #define FMC_CSQICR_CCMDTCF_Msk        (0x1UL << FMC_CSQICR_CCMDTCF_Pos)         /*!< 0x00000010 */
19343 #define FMC_CSQICR_CCMDTCF            FMC_CSQICR_CCMDTCF_Msk                   /*!< Clear Command Transfer Complete flag */
19344 
19345 /***************  Bit definition for FMC_CSQEMSR register  ****************/
19346 #define FMC_CSQEMSR_SEM_Pos           (0U)
19347 #define FMC_CSQEMSR_SEM_Msk           (0xFFFFUL << FMC_CSQEMSR_SEM_Pos)         /*!< 0x0000FFFF */
19348 #define FMC_CSQEMSR_SEM               FMC_CSQEMSR_SEM_Msk                      /*!< Sector Error mapping */
19349 
19350 /****************  Bit definition for FMC_BCHIER register  ****************/
19351 #define FMC_BCHIER_DUEIE_Pos          (0U)
19352 #define FMC_BCHIER_DUEIE_Msk          (0x1UL << FMC_BCHIER_DUEIE_Pos)           /*!< 0x00000001 */
19353 #define FMC_BCHIER_DUEIE              FMC_BCHIER_DUEIE_Msk                     /*!< Decoder Uncorrectable Errors Interrupt enable */
19354 #define FMC_BCHIER_DERIE_Pos          (1U)
19355 #define FMC_BCHIER_DERIE_Msk          (0x1UL << FMC_BCHIER_DERIE_Pos)           /*!< 0x00000002 */
19356 #define FMC_BCHIER_DERIE              FMC_BCHIER_DERIE_Msk                     /*!< Decoder Error Ready Interrupt enable */
19357 #define FMC_BCHIER_DEFIE_Pos          (2U)
19358 #define FMC_BCHIER_DEFIE_Msk          (0x1UL << FMC_BCHIER_DEFIE_Pos)           /*!< 0x00000004 */
19359 #define FMC_BCHIER_DEFIE              FMC_BCHIER_DEFIE_Msk                     /*!< Decoder Error Found Interrupt enable */
19360 #define FMC_BCHIER_DSRIE_Pos          (3U)
19361 #define FMC_BCHIER_DSRIE_Msk          (0x1UL << FMC_BCHIER_DSRIE_Pos)           /*!< 0x00000008 */
19362 #define FMC_BCHIER_DSRIE              FMC_BCHIER_DSRIE_Msk                     /*!< Decoder Syndrome Ready Interrupt enable */
19363 #define FMC_BCHIER_EPBRIE_Pos         (4U)
19364 #define FMC_BCHIER_EPBRIE_Msk         (0x1UL << FMC_BCHIER_EPBRIE_Pos)          /*!< 0x00000010 */
19365 #define FMC_BCHIER_EPBRIE             FMC_BCHIER_EPBRIE_Msk                    /*!< Decoder Parity Bits Ready Interrupt enable */
19366 
19367 /****************  Bit definition for FMC_BCHISR register  ****************/
19368 #define FMC_BCHISR_DUEF_Pos           (0U)
19369 #define FMC_BCHISR_DUEF_Msk           (0x1UL << FMC_BCHISR_DUEF_Pos)            /*!< 0x00000001 */
19370 #define FMC_BCHISR_DUEF               FMC_BCHISR_DUEF_Msk                      /*!< Decoder Uncorrectable Errors flag */
19371 #define FMC_BCHISR_DERF_Pos           (1U)
19372 #define FMC_BCHISR_DERF_Msk           (0x1UL << FMC_BCHISR_DERF_Pos)            /*!< 0x00000002 */
19373 #define FMC_BCHISR_DERF               FMC_BCHISR_DERF_Msk                      /*!< Decoder Error Ready flag */
19374 #define FMC_BCHISR_DEFF_Pos           (2U)
19375 #define FMC_BCHISR_DEFF_Msk           (0x1UL << FMC_BCHISR_DEFF_Pos)            /*!< 0x00000004 */
19376 #define FMC_BCHISR_DEFF               FMC_BCHISR_DEFF_Msk                      /*!< Decoder Error Found flag */
19377 #define FMC_BCHISR_DSRF_Pos           (3U)
19378 #define FMC_BCHISR_DSRF_Msk           (0x1UL << FMC_BCHISR_DSRF_Pos)            /*!< 0x00000008 */
19379 #define FMC_BCHISR_DSRF               FMC_BCHISR_DSRF_Msk                      /*!< Decoder Syndrome Ready flag */
19380 #define FMC_BCHISR_EPBRF_Pos          (4U)
19381 #define FMC_BCHISR_EPBRF_Msk          (0x1UL << FMC_BCHISR_EPBRF_Pos)           /*!< 0x00000010 */
19382 #define FMC_BCHISR_EPBRF              FMC_BCHISR_EPBRF_Msk                     /*!< Encoder Parity Bits Ready flag */
19383 
19384 /****************  Bit definition for FMC_BCHICR register  ****************/
19385 #define FMC_BCHICR_CDUEF_Pos          (0U)
19386 #define FMC_BCHICR_CDUEF_Msk          (0x1UL << FMC_BCHICR_CDUEF_Pos)           /*!< 0x00000001 */
19387 #define FMC_BCHICR_CDUEF              FMC_BCHICR_CDUEF_Msk                     /*!< Clear Decoder Uncorrectable Error flag */
19388 #define FMC_BCHICR_CDERF_Pos          (1U)
19389 #define FMC_BCHICR_CDERF_Msk          (0x1UL << FMC_BCHICR_CDERF_Pos)           /*!< 0x00000002 */
19390 #define FMC_BCHICR_CDERF              FMC_BCHICR_CDERF_Msk                     /*!< Clear Decoder Error ready flag */
19391 #define FMC_BCHICR_CDEFF_Pos          (2U)
19392 #define FMC_BCHICR_CDEFF_Msk          (0x1UL << FMC_BCHICR_CDEFF_Pos)           /*!< 0x00000004 */
19393 #define FMC_BCHICR_CDEFF              FMC_BCHICR_CDEFF_Msk                     /*!< Clear Decoder Error Found flag */
19394 #define FMC_BCHICR_CDSRF_Pos          (3U)
19395 #define FMC_BCHICR_CDSRF_Msk          (0x1UL << FMC_BCHICR_CDSRF_Pos)           /*!< 0x00000008 */
19396 #define FMC_BCHICR_CDSRF              FMC_BCHICR_CDSRF_Msk                     /*!< Clear Decoder Syndrome Ready flag */
19397 #define FMC_BCHICR_CEPBRF_Pos         (4U)
19398 #define FMC_BCHICR_CEPBRF_Msk         (0x1UL << FMC_BCHICR_CEPBRF_Pos)          /*!< 0x00000010 */
19399 #define FMC_BCHICR_CEPBRF             FMC_BCHICR_CEPBRF_Msk                    /*!< Clear Encoder Parity Bits Ready flag */
19400 
19401 /***************  Bit definition for FMC_BCHPBR1 register  ****************/
19402 #define FMC_BCHPBR1_BCHPB_Pos         (0U)
19403 #define FMC_BCHPBR1_BCHPB_Msk         (0xFFFFFFFFUL << FMC_BCHPBR1_BCHPB_Pos)   /*!< 0xFFFFFFFF */
19404 #define FMC_BCHPBR1_BCHPB             FMC_BCHPBR1_BCHPB_Msk                    /*!< BCH parity bits */
19405 
19406 /***************  Bit definition for FMC_BCHPBR2 register  ****************/
19407 #define FMC_BCHPBR2_BCHPB_Pos         (0U)
19408 #define FMC_BCHPBR2_BCHPB_Msk         (0xFFFFFFFFUL << FMC_BCHPBR2_BCHPB_Pos)   /*!< 0xFFFFFFFF */
19409 #define FMC_BCHPBR2_BCHPB             FMC_BCHPBR2_BCHPB_Msk                    /*!< BCH parity bits */
19410 
19411 /***************  Bit definition for FMC_BCHPBR3 register  ****************/
19412 #define FMC_BCHPBR3_BCHPB_Pos         (0U)
19413 #define FMC_BCHPBR3_BCHPB_Msk         (0xFFFFFFFFUL << FMC_BCHPBR3_BCHPB_Pos)   /*!< 0xFFFFFFFF */
19414 #define FMC_BCHPBR3_BCHPB             FMC_BCHPBR3_BCHPB_Msk                    /*!< BCH parity bits */
19415 
19416 /***************  Bit definition for FMC_BCHPBR4 register  ****************/
19417 #define FMC_BCHPBR4_BCHPB_Pos         (0U)
19418 #define FMC_BCHPBR4_BCHPB_Msk         (0xFFUL << FMC_BCHPBR4_BCHPB_Pos)         /*!< 0x000000FF */
19419 #define FMC_BCHPBR4_BCHPB             FMC_BCHPBR4_BCHPB_Msk                    /*!< BCH parity bits */
19420 
19421 /***************  Bit definition for FMC_BCHDSR0 register  ****************/
19422 #define FMC_BCHDSR0_DUE_Pos           (0U)
19423 #define FMC_BCHDSR0_DUE_Msk           (0x1UL << FMC_BCHDSR0_DUE_Pos)            /*!< 0x00000001 */
19424 #define FMC_BCHDSR0_DUE               FMC_BCHDSR0_DUE_Msk                      /*!< Decoder uncorrectable error */
19425 #define FMC_BCHDSR0_DEF_Pos           (1U)
19426 #define FMC_BCHDSR0_DEF_Msk           (0x1UL << FMC_BCHDSR0_DEF_Pos)            /*!< 0x00000002 */
19427 #define FMC_BCHDSR0_DEF               FMC_BCHDSR0_DEF_Msk                      /*!< Decoder error found */
19428 #define FMC_BCHDSR0_DEN_Pos           (4U)
19429 #define FMC_BCHDSR0_DEN_Msk           (0xFUL << FMC_BCHDSR0_DEN_Pos)            /*!< 0x000000F0 */
19430 #define FMC_BCHDSR0_DEN               FMC_BCHDSR0_DEN_Msk                      /*!< Decoder error number */
19431 
19432 /***************  Bit definition for FMC_BCHDSR1 register  ****************/
19433 #define FMC_BCHDSR1_EBP1_Pos          (0U)
19434 #define FMC_BCHDSR1_EBP1_Msk          (0x1FFFUL << FMC_BCHDSR1_EBP1_Pos)        /*!< 0x00001FFF */
19435 #define FMC_BCHDSR1_EBP1              FMC_BCHDSR1_EBP1_Msk                     /*!< Error bit position for error number 1 */
19436 #define FMC_BCHDSR1_EBP2_Pos          (16U)
19437 #define FMC_BCHDSR1_EBP2_Msk          (0x1FFFUL << FMC_BCHDSR1_EBP2_Pos)        /*!< 0x1FFF0000 */
19438 #define FMC_BCHDSR1_EBP2              FMC_BCHDSR1_EBP2_Msk                     /*!< Error bit position for error number 2 */
19439 
19440 /***************  Bit definition for FMC_BCHDSR2 register  ****************/
19441 #define FMC_BCHDSR2_EBP3_Pos          (0U)
19442 #define FMC_BCHDSR2_EBP3_Msk          (0x1FFFUL << FMC_BCHDSR2_EBP3_Pos)        /*!< 0x00001FFF */
19443 #define FMC_BCHDSR2_EBP3              FMC_BCHDSR2_EBP3_Msk                     /*!< Error bit position for error number 3 */
19444 #define FMC_BCHDSR2_EBP4_Pos          (16U)
19445 #define FMC_BCHDSR2_EBP4_Msk          (0x1FFFUL << FMC_BCHDSR2_EBP4_Pos)        /*!< 0x1FFF0000 */
19446 #define FMC_BCHDSR2_EBP4              FMC_BCHDSR2_EBP4_Msk                     /*!< Error bit position for error number 4 */
19447 
19448 /***************  Bit definition for FMC_BCHDSR3 register  ****************/
19449 #define FMC_BCHDSR3_EBP5_Pos          (0U)
19450 #define FMC_BCHDSR3_EBP5_Msk          (0x1FFFUL << FMC_BCHDSR3_EBP5_Pos)        /*!< 0x00001FFF */
19451 #define FMC_BCHDSR3_EBP5              FMC_BCHDSR3_EBP5_Msk                     /*!< Error bit position for error number 5 */
19452 #define FMC_BCHDSR3_EBP6_Pos          (16U)
19453 #define FMC_BCHDSR3_EBP6_Msk          (0x1FFFUL << FMC_BCHDSR3_EBP6_Pos)        /*!< 0x1FFF0000 */
19454 #define FMC_BCHDSR3_EBP6              FMC_BCHDSR3_EBP6_Msk                     /*!< Error bit position for error number 6 */
19455 
19456 /***************  Bit definition for FMC_BCHDSR4 register  ****************/
19457 #define FMC_BCHDSR4_EBP7_Pos          (0U)
19458 #define FMC_BCHDSR4_EBP7_Msk          (0x1FFFUL << FMC_BCHDSR4_EBP7_Pos)        /*!< 0x00001FFF */
19459 #define FMC_BCHDSR4_EBP7              FMC_BCHDSR4_EBP7_Msk                     /*!< Error bit position for error number 7 */
19460 #define FMC_BCHDSR4_EBP8_Pos          (16U)
19461 #define FMC_BCHDSR4_EBP8_Msk          (0x1FFFUL << FMC_BCHDSR4_EBP8_Pos)        /*!< 0x1FFF0000 */
19462 #define FMC_BCHDSR4_EBP8              FMC_BCHDSR4_EBP8_Msk                     /*!< Error bit position for error number 8 */
19463 
19464 
19465 /******************************************************************************/
19466 /*                                                                            */
19467 /*                       Graphic MMU (GFXMMU)                                 */
19468 /*                                                                            */
19469 /******************************************************************************/
19470 /****************** Bits definition for GFXMMU_CR register ********************/
19471 #define GFXMMU_CR_B0OIE_Pos                (0U)
19472 #define GFXMMU_CR_B0OIE_Msk                (0x1UL << GFXMMU_CR_B0OIE_Pos)      /*!< 0x00000001 */
19473 #define GFXMMU_CR_B0OIE                    GFXMMU_CR_B0OIE_Msk                 /*!< Buffer 0 overflow interrupt enable */
19474 #define GFXMMU_CR_B1OIE_Pos                (1U)
19475 #define GFXMMU_CR_B1OIE_Msk                (0x1UL << GFXMMU_CR_B1OIE_Pos)      /*!< 0x00000002 */
19476 #define GFXMMU_CR_B1OIE                    GFXMMU_CR_B1OIE_Msk                 /*!< Buffer 1 overflow interrupt enable */
19477 #define GFXMMU_CR_B2OIE_Pos                (2U)
19478 #define GFXMMU_CR_B2OIE_Msk                (0x1UL << GFXMMU_CR_B2OIE_Pos)      /*!< 0x00000004 */
19479 #define GFXMMU_CR_B2OIE                    GFXMMU_CR_B2OIE_Msk                 /*!< Buffer 2 overflow interrupt enable */
19480 #define GFXMMU_CR_B3OIE_Pos                (3U)
19481 #define GFXMMU_CR_B3OIE_Msk                (0x1UL << GFXMMU_CR_B3OIE_Pos)      /*!< 0x00000008 */
19482 #define GFXMMU_CR_B3OIE                    GFXMMU_CR_B3OIE_Msk                 /*!< Buffer 3 overflow interrupt enable */
19483 #define GFXMMU_CR_AMEIE_Pos                (4U)
19484 #define GFXMMU_CR_AMEIE_Msk                (0x1UL << GFXMMU_CR_AMEIE_Pos)      /*!< 0x00000010 */
19485 #define GFXMMU_CR_AMEIE                    GFXMMU_CR_AMEIE_Msk                 /*!< AHB master error interrupt enable */
19486 #define GFXMMU_CR_BS_Pos                   (6U)
19487 #define GFXMMU_CR_BS_Msk                   (0x1UL << GFXMMU_CR_BS_Pos)         /*!< 0x00000040 */
19488 #define GFXMMU_CR_BS                       GFXMMU_CR_BS_Msk                    /*!< Block size */
19489 #define GFXMMU_CR_ATE_Pos                  (15U)
19490 #define GFXMMU_CR_ATE_Msk                  (0x1UL << GFXMMU_CR_ATE_Pos)        /*!< 0x00008000 */
19491 #define GFXMMU_CR_ATE                      GFXMMU_CR_ATE_Msk                   /*!< Address translation enable */
19492 #define GFXMMU_CR_B0PE_Pos                 (24U)
19493 #define GFXMMU_CR_B0PE_Msk                 (0x1UL << GFXMMU_CR_B0PE_Pos)       /*!< 0x01000000 */
19494 #define GFXMMU_CR_B0PE                     GFXMMU_CR_B0PE_Msk                  /*!< Buffer 0 packing enable */
19495 #define GFXMMU_CR_B0PM_Pos                 (25U)
19496 #define GFXMMU_CR_B0PM_Msk                 (0x1UL << GFXMMU_CR_B0PM_Pos)       /*!< 0x02000000 */
19497 #define GFXMMU_CR_B0PM                     GFXMMU_CR_B0PM_Msk                  /*!< Buffer 0 packing mode */
19498 #define GFXMMU_CR_B1PE_Pos                 (26U)
19499 #define GFXMMU_CR_B1PE_Msk                 (0x1UL << GFXMMU_CR_B1PE_Pos)       /*!< 0x04000000 */
19500 #define GFXMMU_CR_B1PE                     GFXMMU_CR_B1PE_Msk                  /*!< Buffer 1 packing enable */
19501 #define GFXMMU_CR_B1PM_Pos                 (27U)
19502 #define GFXMMU_CR_B1PM_Msk                 (0x1UL << GFXMMU_CR_B1PM_Pos)       /*!< 0x08000000 */
19503 #define GFXMMU_CR_B1PM                     GFXMMU_CR_B1PM_Msk                  /*!< Buffer 1 packing mode */
19504 #define GFXMMU_CR_B2PE_Pos                 (28U)
19505 #define GFXMMU_CR_B2PE_Msk                 (0x1UL << GFXMMU_CR_B2PE_Pos)       /*!< 0x10000000 */
19506 #define GFXMMU_CR_B2PE                     GFXMMU_CR_B2PE_Msk                  /*!< Buffer 0 packing enable */
19507 #define GFXMMU_CR_B2PM_Pos                 (29U)
19508 #define GFXMMU_CR_B2PM_Msk                 (0x1UL << GFXMMU_CR_B2PM_Pos)       /*!< 0x20000000 */
19509 #define GFXMMU_CR_B2PM                     GFXMMU_CR_B2PM_Msk                  /*!< Buffer 0 packing mode */
19510 #define GFXMMU_CR_B3PE_Pos                 (30U)
19511 #define GFXMMU_CR_B3PE_Msk                 (0x1UL << GFXMMU_CR_B3PE_Pos)       /*!< 0x40000000 */
19512 #define GFXMMU_CR_B3PE                     GFXMMU_CR_B3PE_Msk                  /*!< Buffer 0 packing enable */
19513 #define GFXMMU_CR_B3PM_Pos                 (31U)
19514 #define GFXMMU_CR_B3PM_Msk                 (0x1UL << GFXMMU_CR_B3PM_Pos)       /*!< 0x80000000 */
19515 #define GFXMMU_CR_B3PM                     GFXMMU_CR_B3PM_Msk                  /*!< Buffer 0 packing mode */
19516 
19517 /****************** Bits definition for GFXMMU_SR register ********************/
19518 #define GFXMMU_SR_B0OF_Pos                 (0U)
19519 #define GFXMMU_SR_B0OF_Msk                 (0x1UL << GFXMMU_SR_B0OF_Pos)       /*!< 0x00000001 */
19520 #define GFXMMU_SR_B0OF                     GFXMMU_SR_B0OF_Msk                  /*!< Buffer 0 overflow flag */
19521 #define GFXMMU_SR_B1OF_Pos                 (1U)
19522 #define GFXMMU_SR_B1OF_Msk                 (0x1UL << GFXMMU_SR_B1OF_Pos)       /*!< 0x00000002 */
19523 #define GFXMMU_SR_B1OF                     GFXMMU_SR_B1OF_Msk                  /*!< Buffer 1 overflow flag */
19524 #define GFXMMU_SR_B2OF_Pos                 (2U)
19525 #define GFXMMU_SR_B2OF_Msk                 (0x1UL << GFXMMU_SR_B2OF_Pos)       /*!< 0x00000004 */
19526 #define GFXMMU_SR_B2OF                     GFXMMU_SR_B2OF_Msk                  /*!< Buffer 2 overflow flag */
19527 #define GFXMMU_SR_B3OF_Pos                 (3U)
19528 #define GFXMMU_SR_B3OF_Msk                 (0x1UL << GFXMMU_SR_B3OF_Pos)       /*!< 0x00000008 */
19529 #define GFXMMU_SR_B3OF                     GFXMMU_SR_B3OF_Msk                  /*!< Buffer 3 overflow flag */
19530 #define GFXMMU_SR_AMEF_Pos                 (4U)
19531 #define GFXMMU_SR_AMEF_Msk                 (0x1UL << GFXMMU_SR_AMEF_Pos)       /*!< 0x00000010 */
19532 #define GFXMMU_SR_AMEF                     GFXMMU_SR_AMEF_Msk                  /*!< AXI master error flag */
19533 
19534 /****************** Bits definition for GFXMMU_FCR register *******************/
19535 #define GFXMMU_FCR_CB0OF_Pos               (0U)
19536 #define GFXMMU_FCR_CB0OF_Msk               (0x1UL << GFXMMU_FCR_CB0OF_Pos)     /*!< 0x00000001 */
19537 #define GFXMMU_FCR_CB0OF                   GFXMMU_FCR_CB0OF_Msk                /*!< Clear buffer 0 overflow flag */
19538 #define GFXMMU_FCR_CB1OF_Pos               (1U)
19539 #define GFXMMU_FCR_CB1OF_Msk               (0x1UL << GFXMMU_FCR_CB1OF_Pos)     /*!< 0x00000002 */
19540 #define GFXMMU_FCR_CB1OF                   GFXMMU_FCR_CB1OF_Msk                /*!< Clear buffer 1 overflow flag */
19541 #define GFXMMU_FCR_CB2OF_Pos               (2U)
19542 #define GFXMMU_FCR_CB2OF_Msk               (0x1UL << GFXMMU_FCR_CB2OF_Pos)     /*!< 0x00000004 */
19543 #define GFXMMU_FCR_CB2OF                   GFXMMU_FCR_CB2OF_Msk                /*!< Clear buffer 2 overflow flag */
19544 #define GFXMMU_FCR_CB3OF_Pos               (3U)
19545 #define GFXMMU_FCR_CB3OF_Msk               (0x1UL << GFXMMU_FCR_CB3OF_Pos)     /*!< 0x00000008 */
19546 #define GFXMMU_FCR_CB3OF                   GFXMMU_FCR_CB3OF_Msk                /*!< Clear buffer 3 overflow flag */
19547 #define GFXMMU_FCR_CAMEF_Pos               (4U)
19548 #define GFXMMU_FCR_CAMEF_Msk               (0x1UL << GFXMMU_FCR_CAMEF_Pos)     /*!< 0x00000010 */
19549 #define GFXMMU_FCR_CAMEF                   GFXMMU_FCR_CAMEF_Msk                /*!< Clear AHB master error flag */
19550 
19551 /****************** Bits definition for GFXMMU_DVR register *******************/
19552 #define GFXMMU_DVR_DV_Pos                  (0U)
19553 #define GFXMMU_DVR_DV_Msk                  (0xFFFFFFFFUL << GFXMMU_DVR_DV_Pos) /*!< 0xFFFFFFFF */
19554 #define GFXMMU_DVR_DV                      GFXMMU_DVR_DV_Msk                   /*!< DV[31:0] bits (Default value) */
19555 
19556 /****************** Bits definition for GFXMMU_DAR register *******************/
19557 #define GFXMMU_DAR_DA_Pos                  (0U)
19558 #define GFXMMU_DAR_DA_Msk                  (0xFFUL << GFXMMU_DVR_DA_Pos)       /*!< 0x000000FF */
19559 #define GFXMMU_DAR_DA                      GFXMMU_DVR_DA_Msk                   /*!< DA[7:0] bits (Default alpha) */
19560 
19561 /****************** Bits definition for GFXMMU_B0CR register ******************/
19562 #define GFXMMU_B0CR_PBO_Pos                (4U)
19563 #define GFXMMU_B0CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B0CR_PBO_Pos)  /*!< 0x007FFFF0 */
19564 #define GFXMMU_B0CR_PBO                    GFXMMU_B0CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */
19565 #define GFXMMU_B0CR_PBBA_Pos               (23U)
19566 #define GFXMMU_B0CR_PBBA_Msk               (0x1FFUL << GFXMMU_B0CR_PBBA_Pos)   /*!< 0xFF800000 */
19567 #define GFXMMU_B0CR_PBBA                   GFXMMU_B0CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */
19568 
19569 /****************** Bits definition for GFXMMU_B1CR register ******************/
19570 #define GFXMMU_B1CR_PBO_Pos                (4U)
19571 #define GFXMMU_B1CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B1CR_PBO_Pos)  /*!< 0x007FFFF0 */
19572 #define GFXMMU_B1CR_PBO                    GFXMMU_B1CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */
19573 #define GFXMMU_B1CR_PBBA_Pos               (23U)
19574 #define GFXMMU_B1CR_PBBA_Msk               (0x1FFUL << GFXMMU_B1CR_PBBA_Pos)   /*!< 0xFF800000 */
19575 #define GFXMMU_B1CR_PBBA                   GFXMMU_B1CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */
19576 
19577 /****************** Bits definition for GFXMMU_B2CR register ******************/
19578 #define GFXMMU_B2CR_PBO_Pos                (4U)
19579 #define GFXMMU_B2CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B2CR_PBO_Pos)  /*!< 0x007FFFF0 */
19580 #define GFXMMU_B2CR_PBO                    GFXMMU_B2CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */
19581 #define GFXMMU_B2CR_PBBA_Pos               (23U)
19582 #define GFXMMU_B2CR_PBBA_Msk               (0x1FFUL << GFXMMU_B2CR_PBBA_Pos)   /*!< 0xFF800000 */
19583 #define GFXMMU_B2CR_PBBA                   GFXMMU_B2CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */
19584 
19585 /****************** Bits definition for GFXMMU_B3CR register ******************/
19586 #define GFXMMU_B3CR_PBO_Pos                (4U)
19587 #define GFXMMU_B3CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B3CR_PBO_Pos)  /*!< 0x007FFFF0 */
19588 #define GFXMMU_B3CR_PBO                    GFXMMU_B3CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */
19589 #define GFXMMU_B3CR_PBBA_Pos               (23U)
19590 #define GFXMMU_B3CR_PBBA_Msk               (0x1FFUL << GFXMMU_B3CR_PBBA_Pos)   /*!< 0xFF800000 */
19591 #define GFXMMU_B3CR_PBBA                   GFXMMU_B3CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */
19592 
19593 /****************** Bits definition for GFXMMU_LUTxL register *****************/
19594 #define GFXMMU_LUTxL_EN_Pos                (0U)
19595 #define GFXMMU_LUTxL_EN_Msk                (0x1UL << GFXMMU_LUTxL_EN_Pos)      /*!< 0x00000001 */
19596 #define GFXMMU_LUTxL_EN                    GFXMMU_LUTxL_EN_Msk                 /*!< Enable */
19597 #define GFXMMU_LUTxL_FVB_Pos               (8U)
19598 #define GFXMMU_LUTxL_FVB_Msk               (0xFFUL << GFXMMU_LUTxL_FVB_Pos)    /*!< 0x0000FF00 */
19599 #define GFXMMU_LUTxL_FVB                   GFXMMU_LUTxL_FVB_Msk                /*!< FVB[7:0] bits (First visible block) */
19600 #define GFXMMU_LUTxL_LVB_Pos               (16U)
19601 #define GFXMMU_LUTxL_LVB_Msk               (0xFFUL << GFXMMU_LUTxL_LVB_Pos)    /*!< 0x00FF0000 */
19602 #define GFXMMU_LUTxL_LVB                   GFXMMU_LUTxL_LVB_Msk                /*!< LVB[7:0] bits (Last visible block) */
19603 
19604 /****************** Bits definition for GFXMMU_LUTxH register *****************/
19605 #define GFXMMU_LUTxH_LO_Pos                (0U)
19606 #define GFXMMU_LUTxH_LO_Msk                (0x3FFFFUL << GFXMMU_LUTxH_LO_Pos)  /*!< 0x0003FFFF */
19607 #define GFXMMU_LUTxH_LO                    GFXMMU_LUTxH_LO_Msk                 /*!< LO[17:0] bits (Line offset) */
19608 
19609 
19610 /******************************************************************************/
19611 /*                                                                            */
19612 /*                       Graphic Timer (GFXTIM)                               */
19613 /*                                                                            */
19614 /******************************************************************************/
19615 /******************  Bits definition for GFXTIM_CR register  ******************/
19616 #define GFXTIM_CR_TES_Pos              (0U)
19617 #define GFXTIM_CR_TES_Msk              (0x3UL << GFXTIM_CR_TES_Pos)            /*!< 0x00000003 */
19618 #define GFXTIM_CR_TES                  GFXTIM_CR_TES_Msk
19619 #define GFXTIM_CR_TES_0                (0x1UL << GFXTIM_CR_TES_Pos)            /*!< 0x00000001 */
19620 #define GFXTIM_CR_TES_1                (0x2UL << GFXTIM_CR_TES_Pos)            /*!< 0x00000002 */
19621 
19622 #define GFXTIM_CR_TEPOL_Pos            (4U)
19623 #define GFXTIM_CR_TEPOL_Msk            (0x1UL << GFXTIM_CR_TEPOL_Pos)          /*!< 0x00000010 */
19624 #define GFXTIM_CR_TEPOL                GFXTIM_CR_TEPOL_Msk
19625 
19626 #define GFXTIM_CR_SYNCS_Pos            (8U)
19627 #define GFXTIM_CR_SYNCS_Msk            (0x3UL << GFXTIM_CR_SYNCS_Pos)          /*!< 0x00000300 */
19628 #define GFXTIM_CR_SYNCS                GFXTIM_CR_SYNCS_Msk
19629 #define GFXTIM_CR_SYNCS_0              (0x1UL << GFXTIM_CR_SYNCS_Pos)          /*!< 0x00000100 */
19630 #define GFXTIM_CR_SYNCS_1              (0x2UL << GFXTIM_CR_SYNCS_Pos)          /*!< 0x00000200 */
19631 
19632 #define GFXTIM_CR_FCCOE_Pos            (16U)
19633 #define GFXTIM_CR_FCCOE_Msk            (0x1UL << GFXTIM_CR_FCCOE_Pos)          /*!< 0x00010000 */
19634 #define GFXTIM_CR_FCCOE                GFXTIM_CR_FCCOE_Msk
19635 
19636 #define GFXTIM_CR_LCCOE_Pos            (17U)
19637 #define GFXTIM_CR_LCCOE_Msk            (0x1UL << GFXTIM_CR_LCCOE_Pos)          /*!< 0x00020000 */
19638 #define GFXTIM_CR_LCCOE                GFXTIM_CR_LCCOE_Msk
19639 
19640 /******************  Bits definition for GFXTIM_CR register  ******************/
19641 #define GFXTIM_CGCR_LCS_Pos           (0U)
19642 #define GFXTIM_CGCR_LCS_Msk           (0x7UL << GFXTIM_CGCR_LCS_Pos)           /*!< 0x00000007 */
19643 #define GFXTIM_CGCR_LCS               GFXTIM_CGCR_LCS_Msk
19644 #define GFXTIM_CGCR_LCS_0             (0x1UL << GFXTIM_CGCR_LCS_Pos)           /*!< 0x00000001 */
19645 #define GFXTIM_CGCR_LCS_1             (0x2UL << GFXTIM_CGCR_LCS_Pos)           /*!< 0x00000002 */
19646 #define GFXTIM_CGCR_LCS_2             (0x4UL << GFXTIM_CGCR_LCS_Pos)           /*!< 0x00000004 */
19647 
19648 #define GFXTIM_CGCR_LCCCS_Pos         (4U)
19649 #define GFXTIM_CGCR_LCCCS_Msk         (0x1UL << GFXTIM_CGCR_LCCCS_Pos)         /*!< 0x00000010 */
19650 #define GFXTIM_CGCR_LCCCS             GFXTIM_CGCR_LCCCS_Msk
19651 
19652 #define GFXTIM_CGCR_LCCFR_Pos         (8U)
19653 #define GFXTIM_CGCR_LCCFR_Msk         (0x1UL << GFXTIM_CGCR_LCCFR_Pos)         /*!< 0x00000100 */
19654 #define GFXTIM_CGCR_LCCFR             GFXTIM_CGCR_LCCFR_Msk
19655 
19656 #define GFXTIM_CGCR_LCCHRS_Pos        (12U)
19657 #define GFXTIM_CGCR_LCCHRS_Msk        (0x7UL << GFXTIM_CGCR_LCCHRS_Pos)        /*!< 0x00007000 */
19658 #define GFXTIM_CGCR_LCCHRS            GFXTIM_CGCR_LCCHRS_Msk
19659 #define GFXTIM_CGCR_LCCHRS_0          (0x1UL << GFXTIM_CGCR_LCCHRS_Pos)        /*!< 0x00001000 */
19660 #define GFXTIM_CGCR_LCCHRS_1          (0x2UL << GFXTIM_CGCR_LCCHRS_Pos)        /*!< 0x00002000 */
19661 #define GFXTIM_CGCR_LCCHRS_2          (0x4UL << GFXTIM_CGCR_LCCHRS_Pos)        /*!< 0x00004000 */
19662 
19663 #define GFXTIM_CGCR_FCS_Pos           (16U)
19664 #define GFXTIM_CGCR_FCS_Msk           (0x7UL << GFXTIM_CGCR_FCS_Pos)           /*!< 0x00000007 */
19665 #define GFXTIM_CGCR_FCS               GFXTIM_CGCR_FCS_Msk
19666 #define GFXTIM_CGCR_FCS_0             (0x1UL << GFXTIM_CGCR_FCS_Pos)           /*!< 0x00001000 */
19667 #define GFXTIM_CGCR_FCS_1             (0x2UL << GFXTIM_CGCR_FCS_Pos)           /*!< 0x00002000 */
19668 #define GFXTIM_CGCR_FCS_2             (0x4UL << GFXTIM_CGCR_FCS_Pos)           /*!< 0x00004000 */
19669 
19670 #define GFXTIM_CGCR_FCCCS_Pos         (20U)
19671 #define GFXTIM_CGCR_FCCCS_Msk         (0x7UL << GFXTIM_CGCR_FCCCS_Pos)         /*!< 0x00070000 */
19672 #define GFXTIM_CGCR_FCCCS             GFXTIM_CGCR_FCCCS_Msk
19673 #define GFXTIM_CGCR_FCCCS_0           (0x1UL << GFXTIM_CGCR_FCCCS_Pos)         /*!< 0x00010000 */
19674 #define GFXTIM_CGCR_FCCCS_1           (0x2UL << GFXTIM_CGCR_FCCCS_Pos)         /*!< 0x00020000 */
19675 #define GFXTIM_CGCR_FCCCS_2           (0x4UL << GFXTIM_CGCR_FCCCS_Pos)         /*!< 0x00040000 */
19676 
19677 #define GFXTIM_CGCR_FCCFR_Pos         (24U)
19678 #define GFXTIM_CGCR_FCCFR_Msk         (0x1UL << GFXTIM_CGCR_FCCFR_Pos)         /*!< 0x00100000 */
19679 #define GFXTIM_CGCR_FCCFR             GFXTIM_CGCR_FCCFR_Msk
19680 
19681 #define GFXTIM_CGCR_FCCHRS_Pos        (28U)
19682 #define GFXTIM_CGCR_FCCHRS_Msk        (0x7UL << GFXTIM_CGCR_FCCHRS_Pos)        /*!< 0x70000000 */
19683 #define GFXTIM_CGCR_FCCHRS            GFXTIM_CGCR_FCCHRS_Msk
19684 #define GFXTIM_CGCR_FCCHRS_0          (0x1UL << GFXTIM_CGCR_FCCHRS_Pos)        /*!< 0x10000000 */
19685 #define GFXTIM_CGCR_FCCHRS_1          (0x2UL << GFXTIM_CGCR_FCCHRS_Pos)        /*!< 0x20000000 */
19686 #define GFXTIM_CGCR_FCCHRS_2          (0x4UL << GFXTIM_CGCR_FCCHRS_Pos)        /*!< 0x40000000 */
19687 
19688 /******************  Bits definition for GFXTIM_TCR register  *****************/
19689 #define GFXTIM_TCR_AFCEN_Pos           (0U)
19690 #define GFXTIM_TCR_AFCEN_Msk           (0x1UL << GFXTIM_TCR_AFCEN_Pos)         /*!< 0x00000001 */
19691 #define GFXTIM_TCR_AFCEN               GFXTIM_TCR_AFCEN_Msk
19692 
19693 #define GFXTIM_TCR_FAFCR_Pos           (1U)
19694 #define GFXTIM_TCR_FAFCR_Msk           (0x1UL << GFXTIM_TCR_FAFCR_Pos)         /*!< 0x00000002 */
19695 #define GFXTIM_TCR_FAFCR               GFXTIM_TCR_FAFCR_Msk
19696 
19697 #define GFXTIM_TCR_ALCEN_Pos           (4U)
19698 #define GFXTIM_TCR_ALCEN_Msk           (0x1UL << GFXTIM_TCR_ALCEN_Pos)         /*!< 0x00000010 */
19699 #define GFXTIM_TCR_ALCEN               GFXTIM_TCR_ALCEN_Msk
19700 
19701 #define GFXTIM_TCR_FALCR_Pos           (5U)
19702 #define GFXTIM_TCR_FALCR_Msk           (0x1UL << GFXTIM_TCR_FALCR_Pos)         /*!< 0x00000020 */
19703 #define GFXTIM_TCR_FALCR               GFXTIM_TCR_FALCR_Msk
19704 
19705 #define GFXTIM_TCR_RFC1EN_Pos          (16U)
19706 #define GFXTIM_TCR_RFC1EN_Msk          (0x1UL << GFXTIM_TCR_RFC1EN_Pos)        /*!< 0x00010000 */
19707 #define GFXTIM_TCR_RFC1EN              GFXTIM_TCR_RFC1EN_Msk
19708 
19709 #define GFXTIM_TCR_RFC1CM_Pos          (17U)
19710 #define GFXTIM_TCR_RFC1CM_Msk          (0x1UL << GFXTIM_TCR_RFC1CM_Pos)        /*!< 0x00020000 */
19711 #define GFXTIM_TCR_RFC1CM              GFXTIM_TCR_RFC1CM_Msk
19712 
19713 #define GFXTIM_TCR_FRFC1R_Pos          (18U)
19714 #define GFXTIM_TCR_FRFC1R_Msk          (0x1UL << GFXTIM_TCR_FRFC1R_Pos)        /*!< 0x00040000 */
19715 #define GFXTIM_TCR_FRFC1R              GFXTIM_TCR_FRFC1R_Msk
19716 
19717 #define GFXTIM_TCR_RFC2EN_Pos          (20U)
19718 #define GFXTIM_TCR_RFC2EN_Msk          (0x1UL << GFXTIM_TCR_RFC2EN_Pos)        /*!< 0x00100000 */
19719 #define GFXTIM_TCR_RFC2EN              GFXTIM_TCR_RFC2EN_Msk
19720 
19721 #define GFXTIM_TCR_RFC2CM_Pos          (21U)
19722 #define GFXTIM_TCR_RFC2CM_Msk          (0x1UL << GFXTIM_TCR_RFC2CM_Pos)        /*!< 0x00200000 */
19723 #define GFXTIM_TCR_RFC2CM              GFXTIM_TCR_RFC2CM_Msk
19724 
19725 #define GFXTIM_TCR_FRFC2R_Pos          (22U)
19726 #define GFXTIM_TCR_FRFC2R_Msk          (0x1UL << GFXTIM_TCR_FRFC2R_Pos)        /*!< 0x00400000 */
19727 #define GFXTIM_TCR_FRFC2R              GFXTIM_TCR_FRFC2R_Msk
19728 
19729 /******************  Bits definition for GFXTIM_TDR register  *****************/
19730 #define GFXTIM_TDR_AFCDIS_Pos          (0U)
19731 #define GFXTIM_TDR_AFCDIS_Msk          (0x1UL << GFXTIM_TDR_AFCDIS_Pos)        /*!< 0x00000001 */
19732 #define GFXTIM_TDR_AFCDIS              GFXTIM_TDR_AFCDIS_Msk
19733 
19734 #define GFXTIM_TDR_ALCDIS_Pos          (4U)
19735 #define GFXTIM_TDR_ALCDIS_Msk          (0x1UL << GFXTIM_TDR_ALCDIS_Pos)        /*!< 0x00000010 */
19736 #define GFXTIM_TDR_ALCDIS              GFXTIM_TDR_ALCDIS_Msk
19737 
19738 #define GFXTIM_TDR_RFC1DIS_Pos         (16U)
19739 #define GFXTIM_TDR_RFC1DIS_Msk         (0x1UL << GFXTIM_TDR_RFC1DIS_Pos)       /*!< 0x00010000 */
19740 #define GFXTIM_TDR_RFC1DIS             GFXTIM_TDR_RFC1DIS_Msk
19741 
19742 #define GFXTIM_TDR_RFC2DIS_Pos         (20U)
19743 #define GFXTIM_TDR_RFC2DIS_Msk         (0x1UL << GFXTIM_TDR_RFC2DIS_Pos)       /*!< 0x00100000 */
19744 #define GFXTIM_TDR_RFC2DIS             GFXTIM_TDR_RFC2DIS_Msk
19745 
19746 /******************  Bits definition for GFXTIM_EVCR register  ****************/
19747 #define GFXTIM_EVCR_EV1EN_Pos          (0U)
19748 #define GFXTIM_EVCR_EV1EN_Msk          (0x1UL << GFXTIM_EVCR_EV1EN_Pos)        /*!< 0x00000001 */
19749 #define GFXTIM_EVCR_EV1EN              GFXTIM_EVCR_EV1EN_Msk
19750 
19751 #define GFXTIM_EVCR_EV2EN_Pos          (1U)
19752 #define GFXTIM_EVCR_EV2EN_Msk          (0x1UL << GFXTIM_EVCR_EV2EN_Pos)        /*!< 0x00000002 */
19753 #define GFXTIM_EVCR_EV2EN              GFXTIM_EVCR_EV2EN_Msk
19754 
19755 #define GFXTIM_EVCR_EV3EN_Pos          (2U)
19756 #define GFXTIM_EVCR_EV3EN_Msk          (0x1UL << GFXTIM_EVCR_EV3EN_Pos)        /*!< 0x00000004 */
19757 #define GFXTIM_EVCR_EV3EN              GFXTIM_EVCR_EV3EN_Msk
19758 
19759 #define GFXTIM_EVCR_EV4EN_Pos          (3U)
19760 #define GFXTIM_EVCR_EV4EN_Msk          (0x1UL << GFXTIM_EVCR_EV4EN_Pos)        /*!< 0x00000008 */
19761 #define GFXTIM_EVCR_EV4EN              GFXTIM_EVCR_EV4EN_Msk
19762 
19763 /******************  Bits definition for GFXTIM_EVSR register  ****************/
19764 #define GFXTIM_EVSR_LES1_Pos           (0U)
19765 #define GFXTIM_EVSR_LES1_Msk           (0x7UL << GFXTIM_EVSR_LES1_Pos)         /*!< 0x00000007 */
19766 #define GFXTIM_EVSR_LES1               GFXTIM_EVSR_LES1_Msk
19767 #define GFXTIM_EVSR_LES1_0             (0x1UL << GFXTIM_EVSR_LES1_Pos)         /*!< 0x00000001 */
19768 #define GFXTIM_EVSR_LES1_1             (0x2UL << GFXTIM_EVSR_LES1_Pos)         /*!< 0x00000002 */
19769 #define GFXTIM_EVSR_LES1_2             (0x4UL << GFXTIM_EVSR_LES1_Pos)         /*!< 0x00000004 */
19770 
19771 #define GFXTIM_EVSR_FES1_Pos           (4U)
19772 #define GFXTIM_EVSR_FES1_Msk           (0x7UL << GFXTIM_EVSR_FES1_Pos)         /*!< 0x00000070 */
19773 #define GFXTIM_EVSR_FES1               GFXTIM_EVSR_FES1_Msk
19774 #define GFXTIM_EVSR_FES1_0             (0x1UL << GFXTIM_EVSR_FES1_Pos)         /*!< 0x00000010 */
19775 #define GFXTIM_EVSR_FES1_1             (0x2UL << GFXTIM_EVSR_FES1_Pos)         /*!< 0x00000020 */
19776 #define GFXTIM_EVSR_FES1_2             (0x4UL << GFXTIM_EVSR_FES1_Pos)         /*!< 0x00000040 */
19777 
19778 #define GFXTIM_EVSR_LES2_Pos           (8U)
19779 #define GFXTIM_EVSR_LES2_Msk           (0x7UL << GFXTIM_EVSR_LES2_Pos)         /*!< 0x00000700 */
19780 #define GFXTIM_EVSR_LES2               GFXTIM_EVSR_LES2_Msk
19781 #define GFXTIM_EVSR_LES2_0             (0x1UL << GFXTIM_EVSR_LES2_Pos)         /*!< 0x00000100 */
19782 #define GFXTIM_EVSR_LES2_1             (0x2UL << GFXTIM_EVSR_LES2_Pos)         /*!< 0x00000200 */
19783 #define GFXTIM_EVSR_LES2_2             (0x4UL << GFXTIM_EVSR_LES2_Pos)         /*!< 0x00000400 */
19784 
19785 #define GFXTIM_EVSR_FES2_Pos           (12U)
19786 #define GFXTIM_EVSR_FES2_Msk           (0x7UL << GFXTIM_EVSR_FES2_Pos)         /*!< 0x00007000 */
19787 #define GFXTIM_EVSR_FES2               GFXTIM_EVSR_FES2_Msk
19788 #define GFXTIM_EVSR_FES2_0             (0x1UL << GFXTIM_EVSR_FES2_Pos)         /*!< 0x00001000 */
19789 #define GFXTIM_EVSR_FES2_1             (0x2UL << GFXTIM_EVSR_FES2_Pos)         /*!< 0x00002000 */
19790 #define GFXTIM_EVSR_FES2_2             (0x4UL << GFXTIM_EVSR_FES2_Pos)         /*!< 0x00004000 */
19791 
19792 #define GFXTIM_EVSR_LES3_Pos           (16U)
19793 #define GFXTIM_EVSR_LES3_Msk           (0x7UL << GFXTIM_EVSR_LES3_Pos)         /*!< 0x00070000 */
19794 #define GFXTIM_EVSR_LES3               GFXTIM_EVSR_LES3_Msk
19795 #define GFXTIM_EVSR_LES3_0             (0x1UL << GFXTIM_EVSR_LES3_Pos)         /*!< 0x00010000 */
19796 #define GFXTIM_EVSR_LES3_1             (0x2UL << GFXTIM_EVSR_LES3_Pos)         /*!< 0x00020000 */
19797 #define GFXTIM_EVSR_LES3_2             (0x4UL << GFXTIM_EVSR_LES3_Pos)         /*!< 0x00040000 */
19798 
19799 #define GFXTIM_EVSR_FES3_Pos           (20U)
19800 #define GFXTIM_EVSR_FES3_Msk           (0x7UL << GFXTIM_EVSR_FES3_Pos)         /*!< 0x00700000 */
19801 #define GFXTIM_EVSR_FES3               GFXTIM_EVSR_FES3_Msk
19802 #define GFXTIM_EVSR_FES3_0             (0x1UL << GFXTIM_EVSR_FES3_Pos)         /*!< 0x00100000 */
19803 #define GFXTIM_EVSR_FES3_1             (0x2UL << GFXTIM_EVSR_FES3_Pos)         /*!< 0x00200000 */
19804 #define GFXTIM_EVSR_FES3_2             (0x4UL << GFXTIM_EVSR_FES3_Pos)         /*!< 0x00400000 */
19805 
19806 #define GFXTIM_EVSR_LES4_Pos           (24U)
19807 #define GFXTIM_EVSR_LES4_Msk           (0x7UL << GFXTIM_EVSR_LES4_Pos)         /*!< 0x07000000 */
19808 #define GFXTIM_EVSR_LES4               GFXTIM_EVSR_LES4_Msk
19809 #define GFXTIM_EVSR_LES4_0             (0x1UL << GFXTIM_EVSR_LES4_Pos)         /*!< 0x01000000 */
19810 #define GFXTIM_EVSR_LES4_1             (0x2UL << GFXTIM_EVSR_LES4_Pos)         /*!< 0x02000000 */
19811 #define GFXTIM_EVSR_LES4_2             (0x4UL << GFXTIM_EVSR_LES4_Pos)         /*!< 0x04000000 */
19812 
19813 #define GFXTIM_EVSR_FES4_Pos           (28U)
19814 #define GFXTIM_EVSR_FES4_Msk           (0x7UL << GFXTIM_EVSR_FES4_Pos)         /*!< 0x70000000 */
19815 #define GFXTIM_EVSR_FES4               GFXTIM_EVSR_FES4_Msk
19816 #define GFXTIM_EVSR_FES4_0             (0x1UL << GFXTIM_EVSR_FES4_Pos)         /*!< 0x10000000 */
19817 #define GFXTIM_EVSR_FES4_1             (0x2UL << GFXTIM_EVSR_FES4_Pos)         /*!< 0x20000000 */
19818 #define GFXTIM_EVSR_FES4_2             (0x4UL << GFXTIM_EVSR_FES4_Pos)         /*!< 0x40000000 */
19819 
19820 /******************  Bits definition for GFXTIM_WDGTCR register  **************/
19821 #define GFXTIM_WDGTCR_WDGEN_Pos        (0U)
19822 #define GFXTIM_WDGTCR_WDGEN_Msk        (0x1UL << GFXTIM_WDGTCR_WDGEN_Pos)      /*!< 0x00000001 */
19823 #define GFXTIM_WDGTCR_WDGEN            GFXTIM_WDGTCR_WDGEN_Msk
19824 
19825 #define GFXTIM_WDGTCR_WDGDIS_Pos       (1U)
19826 #define GFXTIM_WDGTCR_WDGDIS_Msk       (0x1UL << GFXTIM_WDGTCR_WDGDIS_Pos)     /*!< 0x00000002 */
19827 #define GFXTIM_WDGTCR_WDGDIS           GFXTIM_WDGTCR_WDGDIS_Msk
19828 
19829 #define GFXTIM_WDGTCR_WDGS_Pos         (2U)
19830 #define GFXTIM_WDGTCR_WDGS_Msk         (0x1UL << GFXTIM_WDGTCR_WDGS_Pos)       /*!< 0x00000004 */
19831 #define GFXTIM_WDGTCR_WDGS             GFXTIM_WDGTCR_WDGS_Msk
19832 
19833 #define GFXTIM_WDGTCR_WDGHRC_Pos       (4U)
19834 #define GFXTIM_WDGTCR_WDGHRC_Msk       (0x3UL << GFXTIM_WDGTCR_WDGHRC_Pos)     /*!< 0x00000030 */
19835 #define GFXTIM_WDGTCR_WDGHRC           GFXTIM_WDGTCR_WDGHRC_Msk
19836 #define GFXTIM_WDGTCR_WDGHRC_0         (0x1UL << GFXTIM_WDGTCR_WDGHRC_Pos)     /*!< 0x00000010 */
19837 #define GFXTIM_WDGTCR_WDGHRC_1         (0x2UL << GFXTIM_WDGTCR_WDGHRC_Pos)     /*!< 0x00000020 */
19838 
19839 #define GFXTIM_WDGTCR_WDGCS_Pos        (8U)
19840 #define GFXTIM_WDGTCR_WDGCS_Msk        (0xFUL << GFXTIM_WDGTCR_WDGCS_Pos)      /*!< 0x00000700 */
19841 #define GFXTIM_WDGTCR_WDGCS            GFXTIM_WDGTCR_WDGCS_Msk
19842 #define GFXTIM_WDGTCR_WDGCS_0          (0x1UL << GFXTIM_WDGTCR_WDGCS_Pos)      /*!< 0x00000100 */
19843 #define GFXTIM_WDGTCR_WDGCS_1          (0x2UL << GFXTIM_WDGTCR_WDGCS_Pos)      /*!< 0x00000200 */
19844 #define GFXTIM_WDGTCR_WDGCS_2          (0x4UL << GFXTIM_WDGTCR_WDGCS_Pos)      /*!< 0x00000400 */
19845 #define GFXTIM_WDGTCR_WDGCS_3          (0x8UL << GFXTIM_WDGTCR_WDGCS_Pos)      /*!< 0x00000800 */
19846 
19847 #define GFXTIM_WDGTCR_FWDGR_Pos        (16U)
19848 #define GFXTIM_WDGTCR_FWDGR_Msk        (0x1UL << GFXTIM_WDGTCR_FWDGR_Pos)      /*!< 0x00010000 */
19849 #define GFXTIM_WDGTCR_FWDGR            GFXTIM_WDGTCR_FWDGR_Msk
19850 
19851 /******************  Bits definition for GFXTIM_ISR register  *****************/
19852 #define GFXTIM_ISR_AFCOF_Pos           (0U)
19853 #define GFXTIM_ISR_AFCOF_Msk           (0x1UL << GFXTIM_ISR_AFCOF_Pos)         /*!< 0x00000001 */
19854 #define GFXTIM_ISR_AFCOF               GFXTIM_ISR_AFCOF_Msk
19855 
19856 #define GFXTIM_ISR_ALCOF_Pos           (1U)
19857 #define GFXTIM_ISR_ALCOF_Msk           (0x1UL << GFXTIM_ISR_ALCOF_Pos)         /*!< 0x00000002 */
19858 #define GFXTIM_ISR_ALCOF               GFXTIM_ISR_ALCOF_Msk
19859 
19860 #define GFXTIM_ISR_TEF_Pos             (2U)
19861 #define GFXTIM_ISR_TEF_Msk             (0x1UL << GFXTIM_ISR_TEF_Pos)           /*!< 0x00000004 */
19862 #define GFXTIM_ISR_TEF                 GFXTIM_ISR_TEF_Msk
19863 
19864 #define GFXTIM_ISR_AFCC1F_Pos          (4U)
19865 #define GFXTIM_ISR_AFCC1F_Msk          (0x1UL << GFXTIM_ISR_AFCC1F_Pos)        /*!< 0x00000010 */
19866 #define GFXTIM_ISR_AFCC1F              GFXTIM_ISR_AFCC1F_Msk
19867 
19868 #define GFXTIM_ISR_ALCC1F_Pos          (8U)
19869 #define GFXTIM_ISR_ALCC1F_Msk          (0x1UL << GFXTIM_ISR_ALCC1F_Pos)        /*!< 0x00000100 */
19870 #define GFXTIM_ISR_ALCC1F              GFXTIM_ISR_ALCC1F_Msk
19871 
19872 #define GFXTIM_ISR_ALCC2F_Pos          (9U)
19873 #define GFXTIM_ISR_ALCC2F_Msk          (0x1UL << GFXTIM_ISR_ALCC2F_Pos)        /*!< 0x00000200 */
19874 #define GFXTIM_ISR_ALCC2F              GFXTIM_ISR_ALCC2F_Msk
19875 
19876 #define GFXTIM_ISR_RFC1RF_Pos          (12U)
19877 #define GFXTIM_ISR_RFC1RF_Msk          (0x1UL << GFXTIM_ISR_RFC1RF_Pos)        /*!< 0x00001000 */
19878 #define GFXTIM_ISR_RFC1RF              GFXTIM_ISR_RFC1RF_Msk
19879 
19880 #define GFXTIM_ISR_RFC2RF_Pos          (13U)
19881 #define GFXTIM_ISR_RFC2RF_Msk          (0x1UL << GFXTIM_ISR_RFC2RF_Pos)        /*!< 0x00002000 */
19882 #define GFXTIM_ISR_RFC2RF              GFXTIM_ISR_RFC2RF_Msk
19883 
19884 #define GFXTIM_ISR_EV1F_Pos            (16U)
19885 #define GFXTIM_ISR_EV1F_Msk            (0x1UL << GFXTIM_ISR_EV1F_Pos)          /*!< 0x00010000 */
19886 #define GFXTIM_ISR_EV1F                GFXTIM_ISR_EV1F_Msk
19887 
19888 #define GFXTIM_ISR_EV2F_Pos            (17U)
19889 #define GFXTIM_ISR_EV2F_Msk            (0x1UL << GFXTIM_ISR_EV2F_Pos)          /*!< 0x00020000 */
19890 #define GFXTIM_ISR_EV2F                GFXTIM_ISR_EV2F_Msk
19891 
19892 #define GFXTIM_ISR_EV3F_Pos            (18U)
19893 #define GFXTIM_ISR_EV3F_Msk            (0x1UL << GFXTIM_ISR_EV3F_Pos)          /*!< 0x00040000 */
19894 #define GFXTIM_ISR_EV3F                GFXTIM_ISR_EV3F_Msk
19895 
19896 #define GFXTIM_ISR_EV4F_Pos            (19U)
19897 #define GFXTIM_ISR_EV4F_Msk            (0x1UL << GFXTIM_ISR_EV4F_Pos)          /*!< 0x00080000 */
19898 #define GFXTIM_ISR_EV4F                GFXTIM_ISR_EV4F_Msk
19899 
19900 #define GFXTIM_ISR_WDGAF_Pos           (24U)
19901 #define GFXTIM_ISR_WDGAF_Msk           (0x1UL << GFXTIM_ISR_WDGAF_Pos)         /*!< 0x01000000 */
19902 #define GFXTIM_ISR_WDGAF               GFXTIM_ISR_WDGAF_Msk
19903 
19904 #define GFXTIM_ISR_WDGPF_Pos           (25U)
19905 #define GFXTIM_ISR_WDGPF_Msk           (0x1UL << GFXTIM_ISR_WDGPF_Pos)         /*!< 0x02000000 */
19906 #define GFXTIM_ISR_WDGPF               GFXTIM_ISR_WDGPF_Msk
19907 
19908 /******************  Bits definition for GFXTIM_ICR register  *****************/
19909 #define GFXTIM_ICR_CAFCOF_Pos          (0U)
19910 #define GFXTIM_ICR_CAFCOF_Msk          (0x1UL << GFXTIM_ICR_CAFCOF_Pos)        /*!< 0x00000001 */
19911 #define GFXTIM_ICR_CAFCOF              GFXTIM_ICR_CAFCOF_Msk
19912 
19913 #define GFXTIM_ICR_CALCOF_Pos          (1U)
19914 #define GFXTIM_ICR_CALCOF_Msk          (0x1UL << GFXTIM_ICR_CALCOF_Pos)        /*!< 0x00000002 */
19915 #define GFXTIM_ICR_CALCOF              GFXTIM_ICR_CALCOF_Msk
19916 
19917 #define GFXTIM_ICR_CTEF_Pos            (2U)
19918 #define GFXTIM_ICR_CTEF_Msk            (0x1UL << GFXTIM_ICR_CTEF_Pos)          /*!< 0x00000004 */
19919 #define GFXTIM_ICR_CTEF                GFXTIM_ICR_CTEF_Msk
19920 
19921 #define GFXTIM_ICR_CAFCC1F_Pos         (4U)
19922 #define GFXTIM_ICR_CAFCC1F_Msk         (0x1UL << GFXTIM_ICR_CAFCC1F_Pos)       /*!< 0x00000010 */
19923 #define GFXTIM_ICR_CAFCC1F             GFXTIM_ICR_CAFCC1F_Msk
19924 
19925 #define GFXTIM_ICR_CALCC1F_Pos         (8U)
19926 #define GFXTIM_ICR_CALCC1F_Msk         (0x1UL << GFXTIM_ICR_CALCC1F_Pos)       /*!< 0x00000100 */
19927 #define GFXTIM_ICR_CALCC1F             GFXTIM_ICR_CALCC1F_Msk
19928 
19929 #define GFXTIM_ICR_CALCC2F_Pos         (9U)
19930 #define GFXTIM_ICR_CALCC2F_Msk         (0x1UL << GFXTIM_ICR_CALCC2F_Pos)       /*!< 0x00000200 */
19931 #define GFXTIM_ICR_CALCC2F             GFXTIM_ICR_CALCC2F_Msk
19932 
19933 #define GFXTIM_ICR_CRFC1RF_Pos         (12U)
19934 #define GFXTIM_ICR_CRFC1RF_Msk         (0x1UL << GFXTIM_ICR_CRFC1RF_Pos)       /*!< 0x00001000 */
19935 #define GFXTIM_ICR_CRFC1RF             GFXTIM_ICR_CRFC1RF_Msk
19936 
19937 #define GFXTIM_ICR_CRFC2RF_Pos         (13U)
19938 #define GFXTIM_ICR_CRFC2RF_Msk         (0x1UL << GFXTIM_ICR_CRFC2RF_Pos)       /*!< 0x00002000 */
19939 #define GFXTIM_ICR_CRFC2RF             GFXTIM_ICR_CRFC2RF_Msk
19940 
19941 #define GFXTIM_ICR_CEV1F_Pos           (16U)
19942 #define GFXTIM_ICR_CEV1F_Msk           (0x1UL << GFXTIM_ICR_CEV1F_Pos)         /*!< 0x00010000 */
19943 #define GFXTIM_ICR_CEV1F               GFXTIM_ICR_CEV1F_Msk
19944 
19945 #define GFXTIM_ICR_CEV2F_Pos           (17U)
19946 #define GFXTIM_ICR_CEV2F_Msk           (0x1UL << GFXTIM_ICR_CEV2F_Pos)         /*!< 0x00020000 */
19947 #define GFXTIM_ICR_CEV2F               GFXTIM_ICR_CEV2F_Msk
19948 
19949 #define GFXTIM_ICR_CEV3F_Pos           (18U)
19950 #define GFXTIM_ICR_CEV3F_Msk           (0x1UL << GFXTIM_ICR_CEV3F_Pos)         /*!< 0x00040000 */
19951 #define GFXTIM_ICR_CEV3F               GFXTIM_ICR_CEV3F_Msk
19952 
19953 #define GFXTIM_ICR_CEV4F_Pos           (19U)
19954 #define GFXTIM_ICR_CEV4F_Msk           (0x1UL << GFXTIM_ICR_CEV4F_Pos)         /*!< 0x00080000 */
19955 #define GFXTIM_ICR_CEV4F               GFXTIM_ICR_CEV4F_Msk
19956 
19957 #define GFXTIM_ICR_CWDGAF_Pos          (24U)
19958 #define GFXTIM_ICR_CWDGAF_Msk          (0x1UL << GFXTIM_ICR_CWDGAF_Pos)        /*!< 0x01000000 */
19959 #define GFXTIM_ICR_CWDGAF              GFXTIM_ICR_CWDGAF_Msk
19960 
19961 #define GFXTIM_ICR_CWDGPF_Pos          (25U)
19962 #define GFXTIM_ICR_CWDGPF_Msk          (0x1UL << GFXTIM_ICR_CWDGPF_Pos)        /*!< 0x02000000 */
19963 #define GFXTIM_ICR_CWDGPF              GFXTIM_ICR_CWDGPF_Msk
19964 
19965 /******************  Bits definition for GFXTIM_IER register  *****************/
19966 #define GFXTIM_IER_AFCOIE_Pos          (0U)
19967 #define GFXTIM_IER_AFCOIE_Msk          (0x1UL << GFXTIM_IER_AFCOIE_Pos)        /*!< 0x00000001 */
19968 #define GFXTIM_IER_AFCOIE              GFXTIM_IER_AFCOIE_Msk
19969 
19970 #define GFXTIM_IER_ALCOIE_Pos          (1U)
19971 #define GFXTIM_IER_ALCOIE_Msk          (0x1UL << GFXTIM_IER_ALCOIE_Pos)        /*!< 0x00000002 */
19972 #define GFXTIM_IER_ALCOIE              GFXTIM_IER_ALCOIE_Msk
19973 
19974 #define GFXTIM_IER_TEIE_Pos            (2U)
19975 #define GFXTIM_IER_TEIE_Msk            (0x1UL << GFXTIM_IER_TEIE_Pos)          /*!< 0x00000004 */
19976 #define GFXTIM_IER_TEIE                GFXTIM_IER_TEIE_Msk
19977 
19978 #define GFXTIM_IER_AFCC1IE_Pos         (4U)
19979 #define GFXTIM_IER_AFCC1IE_Msk         (0x1UL << GFXTIM_IER_AFCC1IE_Pos)       /*!< 0x00000010 */
19980 #define GFXTIM_IER_AFCC1IE             GFXTIM_IER_AFCC1IE_Msk
19981 
19982 #define GFXTIM_IER_ALCC1IE_Pos         (8U)
19983 #define GFXTIM_IER_ALCC1IE_Msk         (0x1UL << GFXTIM_IER_ALCC1IE_Pos)       /*!< 0x00000100 */
19984 #define GFXTIM_IER_ALCC1IE             GFXTIM_IER_ALCC1IE_Msk
19985 
19986 #define GFXTIM_IER_ALCC2IE_Pos         (9U)
19987 #define GFXTIM_IER_ALCC2IE_Msk         (0x1UL << GFXTIM_IER_ALCC2IE_Pos)       /*!< 0x00000200 */
19988 #define GFXTIM_IER_ALCC2IE             GFXTIM_IER_ALCC2IE_Msk
19989 
19990 #define GFXTIM_IER_RFC1RIE_Pos         (12U)
19991 #define GFXTIM_IER_RFC1RIE_Msk         (0x1UL << GFXTIM_IER_RFC1RIE_Pos)       /*!< 0x00001000 */
19992 #define GFXTIM_IER_RFC1RIE             GFXTIM_IER_RFC1RIE_Msk
19993 
19994 #define GFXTIM_IER_RFC2RIE_Pos         (13U)
19995 #define GFXTIM_IER_RFC2RIE_Msk         (0x1UL << GFXTIM_IER_RFC2RIE_Pos)       /*!< 0x00002000 */
19996 #define GFXTIM_IER_RFC2RIE             GFXTIM_IER_RFC2RIE_Msk
19997 
19998 #define GFXTIM_IER_EV1IE_Pos           (16U)
19999 #define GFXTIM_IER_EV1IE_Msk           (0x1UL << GFXTIM_IER_EV1IE_Pos)         /*!< 0x00010000 */
20000 #define GFXTIM_IER_EV1IE               GFXTIM_IER_EV1IE_Msk
20001 
20002 #define GFXTIM_IER_EV2IE_Pos           (17U)
20003 #define GFXTIM_IER_EV2IE_Msk           (0x1UL << GFXTIM_IER_EV2IE_Pos)         /*!< 0x00020000 */
20004 #define GFXTIM_IER_EV2IE               GFXTIM_IER_EV2IE_Msk
20005 
20006 #define GFXTIM_IER_EV3IE_Pos           (18U)
20007 #define GFXTIM_IER_EV3IE_Msk           (0x1UL << GFXTIM_IER_EV3IE_Pos)         /*!< 0x00040000 */
20008 #define GFXTIM_IER_EV3IE               GFXTIM_IER_EV3IE_Msk
20009 
20010 #define GFXTIM_IER_EV4IE_Pos           (19U)
20011 #define GFXTIM_IER_EV4IE_Msk           (0x1UL << GFXTIM_IER_EV4IE_Pos)         /*!< 0x00080000 */
20012 #define GFXTIM_IER_EV4IE               GFXTIM_IER_EV4IE_Msk
20013 
20014 #define GFXTIM_IER_WDGAIE_Pos          (24U)
20015 #define GFXTIM_IER_WDGAIE_Msk          (0x1UL << GFXTIM_IER_WDGAIE_Pos)        /*!< 0x01000000 */
20016 #define GFXTIM_IER_WDGAIE              GFXTIM_IER_WDGAIE_Msk
20017 
20018 #define GFXTIM_IER_WDGPIE_Pos          (25U)
20019 #define GFXTIM_IER_WDGPIE_Msk          (0x1UL << GFXTIM_IER_WDGPIE_Pos)        /*!< 0x02000000 */
20020 #define GFXTIM_IER_WDGPIE              GFXTIM_IER_WDGPIE_Msk
20021 
20022 /******************  Bits definition for GFXTIM_TSR register  *****************/
20023 #define GFXTIM_TSR_AFCS_Pos            (0U)
20024 #define GFXTIM_TSR_AFCS_Msk            (0x1UL << GFXTIM_TSR_AFCS_Pos)          /*!< 0x00000001 */
20025 #define GFXTIM_TSR_AFCS                GFXTIM_TSR_AFCS_Msk
20026 
20027 #define GFXTIM_TSR_ALCS_Pos            (4U)
20028 #define GFXTIM_TSR_ALCS_Msk            (0x1UL << GFXTIM_TSR_ALCS_Pos)          /*!< 0x00000010 */
20029 #define GFXTIM_TSR_ALCS                GFXTIM_TSR_ALCS_Msk
20030 
20031 #define GFXTIM_TSR_RFC1S_Pos           (16U)
20032 #define GFXTIM_TSR_RFC1S_Msk           (0x1UL << GFXTIM_TSR_RFC1S_Pos)         /*!< 0x00010000 */
20033 #define GFXTIM_TSR_RFC1S               GFXTIM_TSR_RFC1S_Msk
20034 
20035 #define GFXTIM_TSR_RFC2S_Pos           (20U)
20036 #define GFXTIM_TSR_RFC2S_Msk           (0x1UL << GFXTIM_TSR_RFC2S_Pos)         /*!< 0x00100000 */
20037 #define GFXTIM_TSR_RFC2S               GFXTIM_TSR_RFC2S_Msk
20038 
20039 /******************  Bits definition for GFXTIM_LCCRR register  ***************/
20040 #define GFXTIM_LCCRR_RELOAD_Pos        (0U)
20041 #define GFXTIM_LCCRR_RELOAD_Msk        (0x3FFFFFUL << GFXTIM_LCCRR_RELOAD_Pos) /*!< 0x003FFFFF */
20042 #define GFXTIM_LCCRR_RELOAD            GFXTIM_LCCRR_RELOAD_Msk
20043 
20044 /******************  Bits definition for GFXTIM_FCCRR register  ***************/
20045 #define GFXTIM_FCCRR_RELOAD_Pos        (0U)
20046 #define GFXTIM_FCCRR_RELOAD_Msk        (0xFFFUL << GFXTIM_FCCRR_RELOAD_Pos)    /*!< 0x00000FFF */
20047 #define GFXTIM_FCCRR_RELOAD            GFXTIM_FCCRR_RELOAD_Msk
20048 
20049 /******************  Bits definition for GFXTIM_ATR register  *****************/
20050 #define GFXTIM_ATR_LINE_Pos            (0U)
20051 #define GFXTIM_ATR_LINE_Msk            (0xFFFUL << GFXTIM_ATR_LINE_Pos)        /*!< 0x00000FFF */
20052 #define GFXTIM_ATR_LINE                GFXTIM_ATR_LINE_Msk
20053 
20054 #define GFXTIM_ATR_FRAME_Pos           (12U)
20055 #define GFXTIM_ATR_FRAME_Msk           (0xFFFFFUL << GFXTIM_ATR_FRAME_Pos)     /*!< 0xFFFFF000 */
20056 #define GFXTIM_ATR_FRAME               GFXTIM_ATR_FRAME_Msk
20057 
20058 /******************  Bits definition for GFXTIM_AFCR register  ****************/
20059 #define GFXTIM_AFCR_FRAME_Pos          (0U)
20060 #define GFXTIM_AFCR_FRAME_Msk          (0xFFFFFUL << GFXTIM_AFCR_FRAME_Pos)    /*!< 0x000FFFFF */
20061 #define GFXTIM_AFCR_FRAME              GFXTIM_AFCR_FRAME_Msk
20062 
20063 /******************  Bits definition for GFXTIM_ALCR register  ****************/
20064 #define GFXTIM_ALCR_LINE_Pos           (0U)
20065 #define GFXTIM_ALCR_LINE_Msk           (0xFFFUL << GFXTIM_ALCR_LINE_Pos)       /*!< 0x00000FFF */
20066 #define GFXTIM_ALCR_LINE               GFXTIM_ALCR_LINE_Msk
20067 
20068 /******************  Bits definition for GFXTIM_AFCC1R register  **************/
20069 #define GFXTIM_AFCC1R_FRAME_Pos        (0U)
20070 #define GFXTIM_AFCC1R_FRAME_Msk        (0xFFFFFUL << GFXTIM_AFCC1R_FRAME_Pos)  /*!< 0x000FFFFF */
20071 #define GFXTIM_AFCC1R_FRAME            GFXTIM_AFCC1R_FRAME_Msk
20072 
20073 /******************  Bits definition for GFXTIM_ALCC1R register  **************/
20074 #define GFXTIM_ALCC1R_LINE_Pos         (0U)
20075 #define GFXTIM_ALCC1R_LINE_Msk         (0xFFFUL << GFXTIM_ALCC1R_LINE_Pos)     /*!< 0x00000FFF */
20076 #define GFXTIM_ALCC1R_LINE             GFXTIM_ALCC1R_LINE_Msk
20077 
20078 /******************  Bits definition for GFXTIM_ALCC2R register  **************/
20079 #define GFXTIM_ALCC2R_LINE_Pos         (0U)
20080 #define GFXTIM_ALCC2R_LINE_Msk         (0xFFFUL << GFXTIM_ALCC2R_LINE_Pos)     /*!< 0x00000FFF */
20081 #define GFXTIM_ALCC2R_LINE             GFXTIM_ALCC2R_LINE_Msk
20082 
20083 /******************  Bits definition for GFXTIM_RFC1R register  ***************/
20084 #define GFXTIM_RFC1R_FRAME_Pos         (0U)
20085 #define GFXTIM_RFC1R_FRAME_Msk         (0xFFFUL << GFXTIM_RFC1R_FRAME_Pos)     /*!< 0x00000FFF */
20086 #define GFXTIM_RFC1R_FRAME             GFXTIM_RFC1R_FRAME_Msk
20087 
20088 /******************  Bits definition for GFXTIM_RFC1RR register  **************/
20089 #define GFXTIM_RFC1RR_FRAME_Pos        (0U)
20090 #define GFXTIM_RFC1RR_FRAME_Msk        (0xFFFUL << GFXTIM_RFC1RR_FRAME_Pos)    /*!< 0x00000FFF */
20091 #define GFXTIM_RFC1RR_FRAME            GFXTIM_RFC1RR_FRAME_Msk
20092 
20093 /******************  Bits definition for GFXTIM_RFC2R register  ***************/
20094 #define GFXTIM_RFC2R_FRAME_Pos         (0U)
20095 #define GFXTIM_RFC2R_FRAME_Msk         (0xFFFUL << GFXTIM_RFC2R_FRAME_Pos)     /*!< 0x00000FFF */
20096 #define GFXTIM_RFC2R_FRAME             GFXTIM_RFC2R_FRAME_Msk
20097 
20098 /******************  Bits definition for GFXTIM_RFC2RR register  **************/
20099 #define GFXTIM_RFC2RR_FRAME_Pos        (0U)
20100 #define GFXTIM_RFC2RR_FRAME_Msk        (0xFFFUL << GFXTIM_RFC2RR_FRAME_Pos)    /*!< 0x00000FFF */
20101 #define GFXTIM_RFC2RR_FRAME            GFXTIM_RFC2RR_FRAME_Msk
20102 
20103 /******************  Bits definition for GFXTIM_WDGCR register  ***************/
20104 #define GFXTIM_WDGCR_VALUE_Pos         (0U)
20105 #define GFXTIM_WDGCR_VALUE_Msk         (0xFFFFUL << GFXTIM_WDGCR_VALUE_Pos)    /*!< 0x0000FFFF */
20106 #define GFXTIM_WDGCR_VALUE             GFXTIM_WDGCR_VALUE_Msk
20107 
20108 /******************  Bits definition for GFXTIM_WDGRR register  ***************/
20109 #define GFXTIM_WDGRR_RELOAD_Pos        (0U)
20110 #define GFXTIM_WDGRR_RELOAD_Msk        (0xFFFFUL << GFXTIM_WDGRR_RELOAD_Pos)   /*!< 0x0000FFFF */
20111 #define GFXTIM_WDGRR_RELOAD            GFXTIM_WDGRR_RELOAD_Msk
20112 
20113 /******************  Bits definition for GFXTIM_WDGPAR register  **************/
20114 #define GFXTIM_WDGPAR_PREALARM_Pos      (0U)
20115 #define GFXTIM_WDGPAR_PREALARM_Msk     (0xFFFFUL << GFXTIM_WDGPAR_PREALARM_Pos)/*!< 0x0000FFFF */
20116 #define GFXTIM_WDGPAR_PREALARM          GFXTIM_WDGPAR_PREALARM_Msk
20117 
20118 /******************  Bits definition for GFXTIM_HWCFGR register  **************/
20119 
20120 /******************  Bits definition for GFXTIM_VERR register  ****************/
20121 #define GFXTIM_VERR_MINREV_Pos         (0U)
20122 #define GFXTIM_VERR_MINREV_Msk         (0xFUL << GFXTIM_VERR_MINREV_Pos)       /*!< 0x0000000F */
20123 #define GFXTIM_VERR_MINREV             GFXTIM_VERR_MINREV_Msk
20124 
20125 #define GFXTIM_VERR_MAJREV_Pos         (4U)
20126 #define GFXTIM_VERR_MAJREV_Msk         (0xFUL << GFXTIM_VERR_MAJREV_Pos)       /*!< 0x000000F0 */
20127 #define GFXTIM_VERR_MAJREV             GFXTIM_VERR_MAJREV_Msk
20128 
20129 /******************  Bits definition for GFXTIM_IPIDR register  ***************/
20130 #define GFXTIM_IPIDR_ID_Pos            (0U)
20131 #define GFXTIM_IPIDR_ID_Msk            (0xFFFFFFFFUL << GFXTIM_IPIDR_ID_Pos)   /*!< 0xFFFFFFFF */
20132 #define GFXTIM_IPIDR_ID                GFXTIM_IPIDR_ID_Msk
20133 
20134 /******************  Bits definition for GFXTIM_SIDR register  ****************/
20135 #define GFXTIM_SIDR_SID_Pos            (0U)
20136 #define GFXTIM_SIDR_SID_Msk            (0xFFFFFFFFUL << GFXTIM_SIDR_SID_Pos)   /*!< 0xFFFFFFFF */
20137 #define GFXTIM_SIDR_SID                GFXTIM_SIDR_SID_Msk
20138 
20139 
20140 /******************************************************************************/
20141 /*                                                                            */
20142 /*                       General Purpose IOs (GPIO)                           */
20143 /*                                                                            */
20144 /******************************************************************************/
20145 /******************  Bits definition for GPIO_MODER register  *****************/
20146 #define GPIO_MODER_MODE0_Pos           (0U)
20147 #define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
20148 #define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk
20149 #define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
20150 #define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
20151 #define GPIO_MODER_MODE1_Pos           (2U)
20152 #define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
20153 #define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk
20154 #define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
20155 #define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
20156 #define GPIO_MODER_MODE2_Pos           (4U)
20157 #define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
20158 #define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk
20159 #define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
20160 #define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
20161 #define GPIO_MODER_MODE3_Pos           (6U)
20162 #define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
20163 #define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk
20164 #define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
20165 #define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
20166 #define GPIO_MODER_MODE4_Pos           (8U)
20167 #define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
20168 #define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk
20169 #define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
20170 #define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
20171 #define GPIO_MODER_MODE5_Pos           (10U)
20172 #define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
20173 #define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk
20174 #define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
20175 #define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
20176 #define GPIO_MODER_MODE6_Pos           (12U)
20177 #define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
20178 #define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk
20179 #define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
20180 #define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
20181 #define GPIO_MODER_MODE7_Pos           (14U)
20182 #define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
20183 #define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk
20184 #define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
20185 #define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
20186 #define GPIO_MODER_MODE8_Pos           (16U)
20187 #define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
20188 #define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk
20189 #define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
20190 #define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
20191 #define GPIO_MODER_MODE9_Pos           (18U)
20192 #define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
20193 #define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk
20194 #define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
20195 #define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
20196 #define GPIO_MODER_MODE10_Pos          (20U)
20197 #define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
20198 #define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk
20199 #define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
20200 #define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
20201 #define GPIO_MODER_MODE11_Pos          (22U)
20202 #define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
20203 #define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk
20204 #define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
20205 #define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
20206 #define GPIO_MODER_MODE12_Pos          (24U)
20207 #define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
20208 #define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk
20209 #define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
20210 #define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
20211 #define GPIO_MODER_MODE13_Pos          (26U)
20212 #define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
20213 #define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk
20214 #define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
20215 #define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
20216 #define GPIO_MODER_MODE14_Pos          (28U)
20217 #define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
20218 #define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk
20219 #define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
20220 #define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
20221 #define GPIO_MODER_MODE15_Pos          (30U)
20222 #define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
20223 #define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk
20224 #define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
20225 #define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
20226 
20227 /******************  Bits definition for GPIO_OTYPER register  ****************/
20228 #define GPIO_OTYPER_OT0_Pos            (0U)
20229 #define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */
20230 #define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk
20231 #define GPIO_OTYPER_OT1_Pos            (1U)
20232 #define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */
20233 #define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk
20234 #define GPIO_OTYPER_OT2_Pos            (2U)
20235 #define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */
20236 #define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk
20237 #define GPIO_OTYPER_OT3_Pos            (3U)
20238 #define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */
20239 #define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk
20240 #define GPIO_OTYPER_OT4_Pos            (4U)
20241 #define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */
20242 #define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk
20243 #define GPIO_OTYPER_OT5_Pos            (5U)
20244 #define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */
20245 #define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk
20246 #define GPIO_OTYPER_OT6_Pos            (6U)
20247 #define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */
20248 #define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk
20249 #define GPIO_OTYPER_OT7_Pos            (7U)
20250 #define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */
20251 #define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk
20252 #define GPIO_OTYPER_OT8_Pos            (8U)
20253 #define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */
20254 #define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk
20255 #define GPIO_OTYPER_OT9_Pos            (9U)
20256 #define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */
20257 #define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk
20258 #define GPIO_OTYPER_OT10_Pos           (10U)
20259 #define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */
20260 #define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk
20261 #define GPIO_OTYPER_OT11_Pos           (11U)
20262 #define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */
20263 #define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk
20264 #define GPIO_OTYPER_OT12_Pos           (12U)
20265 #define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */
20266 #define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk
20267 #define GPIO_OTYPER_OT13_Pos           (13U)
20268 #define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */
20269 #define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk
20270 #define GPIO_OTYPER_OT14_Pos           (14U)
20271 #define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */
20272 #define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk
20273 #define GPIO_OTYPER_OT15_Pos           (15U)
20274 #define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */
20275 #define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk
20276 
20277 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
20278 #define GPIO_OSPEEDR_OSPEED0_Pos       (0U)
20279 #define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */
20280 #define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk
20281 #define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000001 */
20282 #define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000002 */
20283 #define GPIO_OSPEEDR_OSPEED1_Pos       (2U)
20284 #define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */
20285 #define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk
20286 #define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000004 */
20287 #define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000008 */
20288 #define GPIO_OSPEEDR_OSPEED2_Pos       (4U)
20289 #define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */
20290 #define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk
20291 #define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000010 */
20292 #define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000020 */
20293 #define GPIO_OSPEEDR_OSPEED3_Pos       (6U)
20294 #define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */
20295 #define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk
20296 #define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000040 */
20297 #define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000080 */
20298 #define GPIO_OSPEEDR_OSPEED4_Pos       (8U)
20299 #define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */
20300 #define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk
20301 #define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000100 */
20302 #define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000200 */
20303 #define GPIO_OSPEEDR_OSPEED5_Pos       (10U)
20304 #define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */
20305 #define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk
20306 #define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000400 */
20307 #define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000800 */
20308 #define GPIO_OSPEEDR_OSPEED6_Pos       (12U)
20309 #define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */
20310 #define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk
20311 #define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00001000 */
20312 #define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00002000 */
20313 #define GPIO_OSPEEDR_OSPEED7_Pos       (14U)
20314 #define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */
20315 #define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk
20316 #define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00004000 */
20317 #define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00008000 */
20318 #define GPIO_OSPEEDR_OSPEED8_Pos       (16U)
20319 #define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */
20320 #define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk
20321 #define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00010000 */
20322 #define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00020000 */
20323 #define GPIO_OSPEEDR_OSPEED9_Pos       (18U)
20324 #define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */
20325 #define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk
20326 #define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00040000 */
20327 #define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00080000 */
20328 #define GPIO_OSPEEDR_OSPEED10_Pos      (20U)
20329 #define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */
20330 #define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk
20331 #define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00100000 */
20332 #define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00200000 */
20333 #define GPIO_OSPEEDR_OSPEED11_Pos      (22U)
20334 #define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */
20335 #define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk
20336 #define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00400000 */
20337 #define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00800000 */
20338 #define GPIO_OSPEEDR_OSPEED12_Pos      (24U)
20339 #define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */
20340 #define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk
20341 #define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x01000000 */
20342 #define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x02000000 */
20343 #define GPIO_OSPEEDR_OSPEED13_Pos      (26U)
20344 #define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */
20345 #define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk
20346 #define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x04000000 */
20347 #define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x08000000 */
20348 #define GPIO_OSPEEDR_OSPEED14_Pos      (28U)
20349 #define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */
20350 #define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk
20351 #define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x10000000 */
20352 #define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x20000000 */
20353 #define GPIO_OSPEEDR_OSPEED15_Pos      (30U)
20354 #define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */
20355 #define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk
20356 #define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x40000000 */
20357 #define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x80000000 */
20358 
20359 /******************  Bits definition for GPIO_PUPDR register  *****************/
20360 #define GPIO_PUPDR_PUPD0_Pos           (0U)
20361 #define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
20362 #define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk
20363 #define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
20364 #define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
20365 #define GPIO_PUPDR_PUPD1_Pos           (2U)
20366 #define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
20367 #define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk
20368 #define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
20369 #define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
20370 #define GPIO_PUPDR_PUPD2_Pos           (4U)
20371 #define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
20372 #define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk
20373 #define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
20374 #define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
20375 #define GPIO_PUPDR_PUPD3_Pos           (6U)
20376 #define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
20377 #define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk
20378 #define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
20379 #define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
20380 #define GPIO_PUPDR_PUPD4_Pos           (8U)
20381 #define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
20382 #define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk
20383 #define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
20384 #define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
20385 #define GPIO_PUPDR_PUPD5_Pos           (10U)
20386 #define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
20387 #define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk
20388 #define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
20389 #define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
20390 #define GPIO_PUPDR_PUPD6_Pos           (12U)
20391 #define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
20392 #define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk
20393 #define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
20394 #define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
20395 #define GPIO_PUPDR_PUPD7_Pos           (14U)
20396 #define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
20397 #define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk
20398 #define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
20399 #define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
20400 #define GPIO_PUPDR_PUPD8_Pos           (16U)
20401 #define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
20402 #define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk
20403 #define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
20404 #define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
20405 #define GPIO_PUPDR_PUPD9_Pos           (18U)
20406 #define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
20407 #define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk
20408 #define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
20409 #define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
20410 #define GPIO_PUPDR_PUPD10_Pos          (20U)
20411 #define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
20412 #define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk
20413 #define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
20414 #define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
20415 #define GPIO_PUPDR_PUPD11_Pos          (22U)
20416 #define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
20417 #define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk
20418 #define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
20419 #define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
20420 #define GPIO_PUPDR_PUPD12_Pos          (24U)
20421 #define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
20422 #define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk
20423 #define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
20424 #define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
20425 #define GPIO_PUPDR_PUPD13_Pos          (26U)
20426 #define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
20427 #define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk
20428 #define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
20429 #define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
20430 #define GPIO_PUPDR_PUPD14_Pos          (28U)
20431 #define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
20432 #define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk
20433 #define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
20434 #define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
20435 #define GPIO_PUPDR_PUPD15_Pos          (30U)
20436 #define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
20437 #define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk
20438 #define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
20439 #define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
20440 
20441 /******************  Bits definition for GPIO_IDR register  *******************/
20442 #define GPIO_IDR_ID0_Pos               (0U)
20443 #define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
20444 #define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk
20445 #define GPIO_IDR_ID1_Pos               (1U)
20446 #define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
20447 #define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk
20448 #define GPIO_IDR_ID2_Pos               (2U)
20449 #define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
20450 #define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk
20451 #define GPIO_IDR_ID3_Pos               (3U)
20452 #define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
20453 #define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk
20454 #define GPIO_IDR_ID4_Pos               (4U)
20455 #define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
20456 #define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk
20457 #define GPIO_IDR_ID5_Pos               (5U)
20458 #define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
20459 #define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk
20460 #define GPIO_IDR_ID6_Pos               (6U)
20461 #define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
20462 #define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk
20463 #define GPIO_IDR_ID7_Pos               (7U)
20464 #define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
20465 #define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk
20466 #define GPIO_IDR_ID8_Pos               (8U)
20467 #define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
20468 #define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk
20469 #define GPIO_IDR_ID9_Pos               (9U)
20470 #define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
20471 #define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk
20472 #define GPIO_IDR_ID10_Pos              (10U)
20473 #define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
20474 #define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk
20475 #define GPIO_IDR_ID11_Pos              (11U)
20476 #define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
20477 #define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk
20478 #define GPIO_IDR_ID12_Pos              (12U)
20479 #define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
20480 #define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk
20481 #define GPIO_IDR_ID13_Pos              (13U)
20482 #define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
20483 #define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk
20484 #define GPIO_IDR_ID14_Pos              (14U)
20485 #define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
20486 #define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk
20487 #define GPIO_IDR_ID15_Pos              (15U)
20488 #define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
20489 #define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk
20490 
20491 /******************  Bits definition for GPIO_ODR register  *******************/
20492 #define GPIO_ODR_OD0_Pos               (0U)
20493 #define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
20494 #define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk
20495 #define GPIO_ODR_OD1_Pos               (1U)
20496 #define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
20497 #define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk
20498 #define GPIO_ODR_OD2_Pos               (2U)
20499 #define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
20500 #define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk
20501 #define GPIO_ODR_OD3_Pos               (3U)
20502 #define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
20503 #define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk
20504 #define GPIO_ODR_OD4_Pos               (4U)
20505 #define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
20506 #define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk
20507 #define GPIO_ODR_OD5_Pos               (5U)
20508 #define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
20509 #define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk
20510 #define GPIO_ODR_OD6_Pos               (6U)
20511 #define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
20512 #define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk
20513 #define GPIO_ODR_OD7_Pos               (7U)
20514 #define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
20515 #define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk
20516 #define GPIO_ODR_OD8_Pos               (8U)
20517 #define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
20518 #define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk
20519 #define GPIO_ODR_OD9_Pos               (9U)
20520 #define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
20521 #define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk
20522 #define GPIO_ODR_OD10_Pos              (10U)
20523 #define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
20524 #define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk
20525 #define GPIO_ODR_OD11_Pos              (11U)
20526 #define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
20527 #define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk
20528 #define GPIO_ODR_OD12_Pos              (12U)
20529 #define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
20530 #define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk
20531 #define GPIO_ODR_OD13_Pos              (13U)
20532 #define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
20533 #define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk
20534 #define GPIO_ODR_OD14_Pos              (14U)
20535 #define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
20536 #define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk
20537 #define GPIO_ODR_OD15_Pos              (15U)
20538 #define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
20539 #define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk
20540 
20541 /******************  Bits definition for GPIO_BSRR register  ******************/
20542 #define GPIO_BSRR_BS0_Pos              (0U)
20543 #define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */
20544 #define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk
20545 #define GPIO_BSRR_BS1_Pos              (1U)
20546 #define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */
20547 #define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk
20548 #define GPIO_BSRR_BS2_Pos              (2U)
20549 #define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */
20550 #define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk
20551 #define GPIO_BSRR_BS3_Pos              (3U)
20552 #define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */
20553 #define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk
20554 #define GPIO_BSRR_BS4_Pos              (4U)
20555 #define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */
20556 #define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk
20557 #define GPIO_BSRR_BS5_Pos              (5U)
20558 #define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */
20559 #define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk
20560 #define GPIO_BSRR_BS6_Pos              (6U)
20561 #define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */
20562 #define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk
20563 #define GPIO_BSRR_BS7_Pos              (7U)
20564 #define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */
20565 #define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk
20566 #define GPIO_BSRR_BS8_Pos              (8U)
20567 #define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */
20568 #define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk
20569 #define GPIO_BSRR_BS9_Pos              (9U)
20570 #define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */
20571 #define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk
20572 #define GPIO_BSRR_BS10_Pos             (10U)
20573 #define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */
20574 #define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk
20575 #define GPIO_BSRR_BS11_Pos             (11U)
20576 #define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */
20577 #define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk
20578 #define GPIO_BSRR_BS12_Pos             (12U)
20579 #define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */
20580 #define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk
20581 #define GPIO_BSRR_BS13_Pos             (13U)
20582 #define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */
20583 #define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk
20584 #define GPIO_BSRR_BS14_Pos             (14U)
20585 #define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */
20586 #define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk
20587 #define GPIO_BSRR_BS15_Pos             (15U)
20588 #define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */
20589 #define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk
20590 #define GPIO_BSRR_BR0_Pos              (16U)
20591 #define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */
20592 #define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk
20593 #define GPIO_BSRR_BR1_Pos              (17U)
20594 #define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */
20595 #define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk
20596 #define GPIO_BSRR_BR2_Pos              (18U)
20597 #define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */
20598 #define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk
20599 #define GPIO_BSRR_BR3_Pos              (19U)
20600 #define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */
20601 #define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk
20602 #define GPIO_BSRR_BR4_Pos              (20U)
20603 #define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */
20604 #define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk
20605 #define GPIO_BSRR_BR5_Pos              (21U)
20606 #define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */
20607 #define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk
20608 #define GPIO_BSRR_BR6_Pos              (22U)
20609 #define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */
20610 #define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk
20611 #define GPIO_BSRR_BR7_Pos              (23U)
20612 #define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */
20613 #define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk
20614 #define GPIO_BSRR_BR8_Pos              (24U)
20615 #define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */
20616 #define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk
20617 #define GPIO_BSRR_BR9_Pos              (25U)
20618 #define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */
20619 #define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk
20620 #define GPIO_BSRR_BR10_Pos             (26U)
20621 #define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */
20622 #define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk
20623 #define GPIO_BSRR_BR11_Pos             (27U)
20624 #define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */
20625 #define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk
20626 #define GPIO_BSRR_BR12_Pos             (28U)
20627 #define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */
20628 #define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk
20629 #define GPIO_BSRR_BR13_Pos             (29U)
20630 #define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */
20631 #define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk
20632 #define GPIO_BSRR_BR14_Pos             (30U)
20633 #define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */
20634 #define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk
20635 #define GPIO_BSRR_BR15_Pos             (31U)
20636 #define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */
20637 #define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk
20638 
20639 /****************** Bit definition for GPIO_LCKR register *********************/
20640 #define GPIO_LCKR_LCK0_Pos             (0U)
20641 #define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
20642 #define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk
20643 #define GPIO_LCKR_LCK1_Pos             (1U)
20644 #define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
20645 #define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk
20646 #define GPIO_LCKR_LCK2_Pos             (2U)
20647 #define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
20648 #define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk
20649 #define GPIO_LCKR_LCK3_Pos             (3U)
20650 #define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
20651 #define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk
20652 #define GPIO_LCKR_LCK4_Pos             (4U)
20653 #define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
20654 #define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk
20655 #define GPIO_LCKR_LCK5_Pos             (5U)
20656 #define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
20657 #define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk
20658 #define GPIO_LCKR_LCK6_Pos             (6U)
20659 #define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
20660 #define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk
20661 #define GPIO_LCKR_LCK7_Pos             (7U)
20662 #define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
20663 #define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk
20664 #define GPIO_LCKR_LCK8_Pos             (8U)
20665 #define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
20666 #define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk
20667 #define GPIO_LCKR_LCK9_Pos             (9U)
20668 #define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
20669 #define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk
20670 #define GPIO_LCKR_LCK10_Pos            (10U)
20671 #define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
20672 #define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk
20673 #define GPIO_LCKR_LCK11_Pos            (11U)
20674 #define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
20675 #define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk
20676 #define GPIO_LCKR_LCK12_Pos            (12U)
20677 #define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
20678 #define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk
20679 #define GPIO_LCKR_LCK13_Pos            (13U)
20680 #define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
20681 #define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk
20682 #define GPIO_LCKR_LCK14_Pos            (14U)
20683 #define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
20684 #define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk
20685 #define GPIO_LCKR_LCK15_Pos            (15U)
20686 #define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
20687 #define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk
20688 #define GPIO_LCKR_LCKK_Pos             (16U)
20689 #define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
20690 #define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk
20691 
20692 /****************** Bit definition for GPIO_AFRL register *********************/
20693 #define GPIO_AFRL_AFSEL0_Pos           (0U)
20694 #define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */
20695 #define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk
20696 #define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000001 */
20697 #define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000002 */
20698 #define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000004 */
20699 #define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000008 */
20700 #define GPIO_AFRL_AFSEL1_Pos           (4U)
20701 #define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */
20702 #define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk
20703 #define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000010 */
20704 #define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000020 */
20705 #define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000040 */
20706 #define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000080 */
20707 #define GPIO_AFRL_AFSEL2_Pos           (8U)
20708 #define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */
20709 #define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk
20710 #define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000100 */
20711 #define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000200 */
20712 #define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000400 */
20713 #define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000800 */
20714 #define GPIO_AFRL_AFSEL3_Pos           (12U)
20715 #define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */
20716 #define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk
20717 #define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00001000 */
20718 #define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00002000 */
20719 #define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00004000 */
20720 #define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00008000 */
20721 #define GPIO_AFRL_AFSEL4_Pos           (16U)
20722 #define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */
20723 #define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk
20724 #define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00010000 */
20725 #define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00020000 */
20726 #define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00040000 */
20727 #define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00080000 */
20728 #define GPIO_AFRL_AFSEL5_Pos           (20U)
20729 #define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */
20730 #define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk
20731 #define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00100000 */
20732 #define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00200000 */
20733 #define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00400000 */
20734 #define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00800000 */
20735 #define GPIO_AFRL_AFSEL6_Pos           (24U)
20736 #define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */
20737 #define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk
20738 #define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x01000000 */
20739 #define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x02000000 */
20740 #define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x04000000 */
20741 #define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x08000000 */
20742 #define GPIO_AFRL_AFSEL7_Pos           (28U)
20743 #define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */
20744 #define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk
20745 #define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x10000000 */
20746 #define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x20000000 */
20747 #define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x40000000 */
20748 #define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x80000000 */
20749 
20750 /****************** Bit definition for GPIO_AFRH register *********************/
20751 #define GPIO_AFRH_AFSEL8_Pos           (0U)
20752 #define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */
20753 #define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk
20754 #define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000001 */
20755 #define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000002 */
20756 #define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000004 */
20757 #define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000008 */
20758 #define GPIO_AFRH_AFSEL9_Pos           (4U)
20759 #define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */
20760 #define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk
20761 #define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000010 */
20762 #define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000020 */
20763 #define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000040 */
20764 #define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000080 */
20765 #define GPIO_AFRH_AFSEL10_Pos          (8U)
20766 #define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */
20767 #define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk
20768 #define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000100 */
20769 #define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000200 */
20770 #define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000400 */
20771 #define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000800 */
20772 #define GPIO_AFRH_AFSEL11_Pos          (12U)
20773 #define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */
20774 #define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk
20775 #define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00001000 */
20776 #define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00002000 */
20777 #define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00004000 */
20778 #define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00008000 */
20779 #define GPIO_AFRH_AFSEL12_Pos          (16U)
20780 #define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */
20781 #define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk
20782 #define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00010000 */
20783 #define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00020000 */
20784 #define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00040000 */
20785 #define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00080000 */
20786 #define GPIO_AFRH_AFSEL13_Pos          (20U)
20787 #define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */
20788 #define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk
20789 #define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00100000 */
20790 #define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00200000 */
20791 #define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00400000 */
20792 #define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00800000 */
20793 #define GPIO_AFRH_AFSEL14_Pos          (24U)
20794 #define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */
20795 #define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk
20796 #define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x01000000 */
20797 #define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x02000000 */
20798 #define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x04000000 */
20799 #define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x08000000 */
20800 #define GPIO_AFRH_AFSEL15_Pos          (28U)
20801 #define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */
20802 #define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk
20803 #define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x10000000 */
20804 #define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x20000000 */
20805 #define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x40000000 */
20806 #define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x80000000 */
20807 
20808 /******************  Bits definition for GPIO_BRR register  ******************/
20809 #define GPIO_BRR_BR0_Pos               (0U)
20810 #define GPIO_BRR_BR0_Msk               (0x1UL << GPIO_BRR_BR0_Pos)             /*!< 0x00000001 */
20811 #define GPIO_BRR_BR0                   GPIO_BRR_BR0_Msk
20812 #define GPIO_BRR_BR1_Pos               (1U)
20813 #define GPIO_BRR_BR1_Msk               (0x1UL << GPIO_BRR_BR1_Pos)             /*!< 0x00000002 */
20814 #define GPIO_BRR_BR1                   GPIO_BRR_BR1_Msk
20815 #define GPIO_BRR_BR2_Pos               (2U)
20816 #define GPIO_BRR_BR2_Msk               (0x1UL << GPIO_BRR_BR2_Pos)             /*!< 0x00000004 */
20817 #define GPIO_BRR_BR2                   GPIO_BRR_BR2_Msk
20818 #define GPIO_BRR_BR3_Pos               (3U)
20819 #define GPIO_BRR_BR3_Msk               (0x1UL << GPIO_BRR_BR3_Pos)             /*!< 0x00000008 */
20820 #define GPIO_BRR_BR3                   GPIO_BRR_BR3_Msk
20821 #define GPIO_BRR_BR4_Pos               (4U)
20822 #define GPIO_BRR_BR4_Msk               (0x1UL << GPIO_BRR_BR4_Pos)             /*!< 0x00000010 */
20823 #define GPIO_BRR_BR4                   GPIO_BRR_BR4_Msk
20824 #define GPIO_BRR_BR5_Pos               (5U)
20825 #define GPIO_BRR_BR5_Msk               (0x1UL << GPIO_BRR_BR5_Pos)             /*!< 0x00000020 */
20826 #define GPIO_BRR_BR5                   GPIO_BRR_BR5_Msk
20827 #define GPIO_BRR_BR6_Pos               (6U)
20828 #define GPIO_BRR_BR6_Msk               (0x1UL << GPIO_BRR_BR6_Pos)             /*!< 0x00000040 */
20829 #define GPIO_BRR_BR6                   GPIO_BRR_BR6_Msk
20830 #define GPIO_BRR_BR7_Pos               (7U)
20831 #define GPIO_BRR_BR7_Msk               (0x1UL << GPIO_BRR_BR7_Pos)             /*!< 0x00000080 */
20832 #define GPIO_BRR_BR7                   GPIO_BRR_BR7_Msk
20833 #define GPIO_BRR_BR8_Pos               (8U)
20834 #define GPIO_BRR_BR8_Msk               (0x1UL << GPIO_BRR_BR8_Pos)             /*!< 0x00000100 */
20835 #define GPIO_BRR_BR8                   GPIO_BRR_BR8_Msk
20836 #define GPIO_BRR_BR9_Pos               (9U)
20837 #define GPIO_BRR_BR9_Msk               (0x1UL << GPIO_BRR_BR9_Pos)             /*!< 0x00000200 */
20838 #define GPIO_BRR_BR9                   GPIO_BRR_BR9_Msk
20839 #define GPIO_BRR_BR10_Pos              (10U)
20840 #define GPIO_BRR_BR10_Msk              (0x1UL << GPIO_BRR_BR10_Pos)            /*!< 0x00000400 */
20841 #define GPIO_BRR_BR10                  GPIO_BRR_BR10_Msk
20842 #define GPIO_BRR_BR11_Pos              (11U)
20843 #define GPIO_BRR_BR11_Msk              (0x1UL << GPIO_BRR_BR11_Pos)            /*!< 0x00000800 */
20844 #define GPIO_BRR_BR11                  GPIO_BRR_BR11_Msk
20845 #define GPIO_BRR_BR12_Pos              (12U)
20846 #define GPIO_BRR_BR12_Msk              (0x1UL << GPIO_BRR_BR12_Pos)            /*!< 0x00001000 */
20847 #define GPIO_BRR_BR12                  GPIO_BRR_BR12_Msk
20848 #define GPIO_BRR_BR13_Pos              (13U)
20849 #define GPIO_BRR_BR13_Msk              (0x1UL << GPIO_BRR_BR13_Pos)            /*!< 0x00002000 */
20850 #define GPIO_BRR_BR13                  GPIO_BRR_BR13_Msk
20851 #define GPIO_BRR_BR14_Pos              (14U)
20852 #define GPIO_BRR_BR14_Msk              (0x1UL << GPIO_BRR_BR14_Pos)            /*!< 0x00004000 */
20853 #define GPIO_BRR_BR14                  GPIO_BRR_BR14_Msk
20854 #define GPIO_BRR_BR15_Pos              (15U)
20855 #define GPIO_BRR_BR15_Msk              (0x1UL << GPIO_BRR_BR15_Pos)            /*!< 0x00008000 */
20856 #define GPIO_BRR_BR15                  GPIO_BRR_BR15_Msk
20857 
20858 /******************  Bits definition for GPIO_SECCFGR register  ******************/
20859 #define GPIO_SECCFGR_SEC0_Pos          (0U)
20860 #define GPIO_SECCFGR_SEC0_Msk          (0x1UL << GPIO_SECCFGR_SEC0_Pos)        /*!< 0x00000001 */
20861 #define GPIO_SECCFGR_SEC0              GPIO_SECCFGR_SEC0_Msk
20862 #define GPIO_SECCFGR_SEC1_Pos          (1U)
20863 #define GPIO_SECCFGR_SEC1_Msk          (0x1UL << GPIO_SECCFGR_SEC1_Pos)        /*!< 0x00000002 */
20864 #define GPIO_SECCFGR_SEC1              GPIO_SECCFGR_SEC1_Msk
20865 #define GPIO_SECCFGR_SEC2_Pos          (2U)
20866 #define GPIO_SECCFGR_SEC2_Msk          (0x1UL << GPIO_SECCFGR_SEC2_Pos)        /*!< 0x00000004 */
20867 #define GPIO_SECCFGR_SEC2              GPIO_SECCFGR_SEC2_Msk
20868 #define GPIO_SECCFGR_SEC3_Pos          (3U)
20869 #define GPIO_SECCFGR_SEC3_Msk          (0x1UL << GPIO_SECCFGR_SEC3_Pos)        /*!< 0x00000008 */
20870 #define GPIO_SECCFGR_SEC3              GPIO_SECCFGR_SEC3_Msk
20871 #define GPIO_SECCFGR_SEC4_Pos          (4U)
20872 #define GPIO_SECCFGR_SEC4_Msk          (0x1UL << GPIO_SECCFGR_SEC4_Pos)        /*!< 0x00000010 */
20873 #define GPIO_SECCFGR_SEC4              GPIO_SECCFGR_SEC4_Msk
20874 #define GPIO_SECCFGR_SEC5_Pos          (5U)
20875 #define GPIO_SECCFGR_SEC5_Msk          (0x1UL << GPIO_SECCFGR_SEC5_Pos)        /*!< 0x00000020 */
20876 #define GPIO_SECCFGR_SEC5              GPIO_SECCFGR_SEC5_Msk
20877 #define GPIO_SECCFGR_SEC6_Pos          (6U)
20878 #define GPIO_SECCFGR_SEC6_Msk          (0x1UL << GPIO_SECCFGR_SEC6_Pos)        /*!< 0x00000040 */
20879 #define GPIO_SECCFGR_SEC6              GPIO_SECCFGR_SEC6_Msk
20880 #define GPIO_SECCFGR_SEC7_Pos          (7U)
20881 #define GPIO_SECCFGR_SEC7_Msk          (0x1UL << GPIO_SECCFGR_SEC7_Pos)        /*!< 0x00000080 */
20882 #define GPIO_SECCFGR_SEC7              GPIO_SECCFGR_SEC7_Msk
20883 #define GPIO_SECCFGR_SEC8_Pos          (8U)
20884 #define GPIO_SECCFGR_SEC8_Msk          (0x1UL << GPIO_SECCFGR_SEC8_Pos)        /*!< 0x00000100 */
20885 #define GPIO_SECCFGR_SEC8              GPIO_SECCFGR_SEC8_Msk
20886 #define GPIO_SECCFGR_SEC9_Pos          (9U)
20887 #define GPIO_SECCFGR_SEC9_Msk          (0x1UL << GPIO_SECCFGR_SEC9_Pos)        /*!< 0x00000200 */
20888 #define GPIO_SECCFGR_SEC9              GPIO_SECCFGR_SEC9_Msk
20889 #define GPIO_SECCFGR_SEC10_Pos         (10U)
20890 #define GPIO_SECCFGR_SEC10_Msk         (0x1UL << GPIO_SECCFGR_SEC10_Pos)       /*!< 0x00000400 */
20891 #define GPIO_SECCFGR_SEC10             GPIO_SECCFGR_SEC10_Msk
20892 #define GPIO_SECCFGR_SEC11_Pos         (11U)
20893 #define GPIO_SECCFGR_SEC11_Msk         (0x1UL << GPIO_SECCFGR_SEC11_Pos)       /*!< 0x00000800 */
20894 #define GPIO_SECCFGR_SEC11             GPIO_SECCFGR_SEC11_Msk
20895 #define GPIO_SECCFGR_SEC12_Pos         (12U)
20896 #define GPIO_SECCFGR_SEC12_Msk         (0x1UL << GPIO_SECCFGR_SEC12_Pos)       /*!< 0x00001000 */
20897 #define GPIO_SECCFGR_SEC12             GPIO_SECCFGR_SEC12_Msk
20898 #define GPIO_SECCFGR_SEC13_Pos         (13U)
20899 #define GPIO_SECCFGR_SEC13_Msk         (0x1UL << GPIO_SECCFGR_SEC13_Pos)       /*!< 0x00002000 */
20900 #define GPIO_SECCFGR_SEC13             GPIO_SECCFGR_SEC13_Msk
20901 #define GPIO_SECCFGR_SEC14_Pos         (14U)
20902 #define GPIO_SECCFGR_SEC14_Msk         (0x1UL << GPIO_SECCFGR_SEC14_Pos)       /*!< 0x00004000 */
20903 #define GPIO_SECCFGR_SEC14             GPIO_SECCFGR_SEC14_Msk
20904 #define GPIO_SECCFGR_SEC15_Pos         (15U)
20905 #define GPIO_SECCFGR_SEC15_Msk         (0x1UL << GPIO_SECCFGR_SEC15_Pos)       /*!< 0x00008000 */
20906 #define GPIO_SECCFGR_SEC15             GPIO_SECCFGR_SEC15_Msk
20907 
20908 /******************  Bits definition for GPIO_PRIVCFGR register  ******************/
20909 #define GPIO_PRIVCFGR_PRIV0_Pos        (0U)
20910 #define GPIO_PRIVCFGR_PRIV0_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV0_Pos)      /*!< 0x00000001 */
20911 #define GPIO_PRIVCFGR_PRIV0            GPIO_PRIVCFGR_PRIV0_Msk
20912 #define GPIO_PRIVCFGR_PRIV1_Pos        (1U)
20913 #define GPIO_PRIVCFGR_PRIV1_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV1_Pos)      /*!< 0x00000002 */
20914 #define GPIO_PRIVCFGR_PRIV1            GPIO_PRIVCFGR_PRIV1_Msk
20915 #define GPIO_PRIVCFGR_PRIV2_Pos        (2U)
20916 #define GPIO_PRIVCFGR_PRIV2_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV2_Pos)      /*!< 0x00000004 */
20917 #define GPIO_PRIVCFGR_PRIV2            GPIO_PRIVCFGR_PRIV2_Msk
20918 #define GPIO_PRIVCFGR_PRIV3_Pos        (3U)
20919 #define GPIO_PRIVCFGR_PRIV3_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV3_Pos)      /*!< 0x00000008 */
20920 #define GPIO_PRIVCFGR_PRIV3            GPIO_PRIVCFGR_PRIV3_Msk
20921 #define GPIO_PRIVCFGR_PRIV4_Pos        (4U)
20922 #define GPIO_PRIVCFGR_PRIV4_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV4_Pos)      /*!< 0x00000010 */
20923 #define GPIO_PRIVCFGR_PRIV4            GPIO_PRIVCFGR_PRIV4_Msk
20924 #define GPIO_PRIVCFGR_PRIV5_Pos        (5U)
20925 #define GPIO_PRIVCFGR_PRIV5_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV5_Pos)      /*!< 0x00000020 */
20926 #define GPIO_PRIVCFGR_PRIV5            GPIO_PRIVCFGR_PRIV5_Msk
20927 #define GPIO_PRIVCFGR_PRIV6_Pos        (6U)
20928 #define GPIO_PRIVCFGR_PRIV6_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV6_Pos)      /*!< 0x00000040 */
20929 #define GPIO_PRIVCFGR_PRIV6            GPIO_PRIVCFGR_PRIV6_Msk
20930 #define GPIO_PRIVCFGR_PRIV7_Pos        (7U)
20931 #define GPIO_PRIVCFGR_PRIV7_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV7_Pos)      /*!< 0x00000080 */
20932 #define GPIO_PRIVCFGR_PRIV7            GPIO_PRIVCFGR_PRIV7_Msk
20933 #define GPIO_PRIVCFGR_PRIV8_Pos        (8U)
20934 #define GPIO_PRIVCFGR_PRIV8_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV8_Pos)      /*!< 0x00000100 */
20935 #define GPIO_PRIVCFGR_PRIV8            GPIO_PRIVCFGR_PRIV8_Msk
20936 #define GPIO_PRIVCFGR_PRIV9_Pos        (9U)
20937 #define GPIO_PRIVCFGR_PRIV9_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV9_Pos)      /*!< 0x00000200 */
20938 #define GPIO_PRIVCFGR_PRIV9            GPIO_PRIVCFGR_PRIV9_Msk
20939 #define GPIO_PRIVCFGR_PRIV10_Pos       (10U)
20940 #define GPIO_PRIVCFGR_PRIV10_Msk       (0x1UL << GPIO_PRIVCFGR_PRIV10_Pos)     /*!< 0x00000400 */
20941 #define GPIO_PRIVCFGR_PRIV10           GPIO_PRIVCFGR_PRIV10_Msk
20942 #define GPIO_PRIVCFGR_PRIV11_Pos       (11U)
20943 #define GPIO_PRIVCFGR_PRIV11_Msk       (0x1UL << GPIO_PRIVCFGR_PRIV11_Pos)     /*!< 0x00000800 */
20944 #define GPIO_PRIVCFGR_PRIV11           GPIO_PRIVCFGR_PRIV11_Msk
20945 #define GPIO_PRIVCFGR_PRIV12_Pos       (12U)
20946 #define GPIO_PRIVCFGR_PRIV12_Msk       (0x1UL << GPIO_PRIVCFGR_PRIV12_Pos)     /*!< 0x00001000 */
20947 #define GPIO_PRIVCFGR_PRIV12           GPIO_PRIVCFGR_PRIV12_Msk
20948 #define GPIO_PRIVCFGR_PRIV13_Pos       (13U)
20949 #define GPIO_PRIVCFGR_PRIV13_Msk       (0x1UL << GPIO_PRIVCFGR_PRIV13_Pos)     /*!< 0x00002000 */
20950 #define GPIO_PRIVCFGR_PRIV13           GPIO_PRIVCFGR_PRIV13_Msk
20951 #define GPIO_PRIVCFGR_PRIV14_Pos       (14U)
20952 #define GPIO_PRIVCFGR_PRIV14_Msk       (0x1UL << GPIO_PRIVCFGR_PRIV14_Pos)     /*!< 0x00004000 */
20953 #define GPIO_PRIVCFGR_PRIV14           GPIO_PRIVCFGR_PRIV14_Msk
20954 #define GPIO_PRIVCFGR_PRIV15_Pos       (15U)
20955 #define GPIO_PRIVCFGR_PRIV15_Msk       (0x1UL << GPIO_PRIVCFGR_PRIV15_Pos)     /*!< 0x00008000 */
20956 #define GPIO_PRIVCFGR_PRIV15           GPIO_PRIVCFGR_PRIV15_Msk
20957 
20958 /******************  Bits definition for GPIO_RCFGLOCKR register  ******************/
20959 #define GPIO_RCFGLOCKR_RLOCK0_Pos      (0U)
20960 #define GPIO_RCFGLOCKR_RLOCK0_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK0_Pos)    /*!< 0x00000001 */
20961 #define GPIO_RCFGLOCKR_RLOCK0          GPIO_RCFGLOCKR_RLOCK0_Msk
20962 #define GPIO_RCFGLOCKR_RLOCK1_Pos      (1U)
20963 #define GPIO_RCFGLOCKR_RLOCK1_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK1_Pos)    /*!< 0x00000002 */
20964 #define GPIO_RCFGLOCKR_RLOCK1          GPIO_RCFGLOCKR_RLOCK1_Msk
20965 #define GPIO_RCFGLOCKR_RLOCK2_Pos      (2U)
20966 #define GPIO_RCFGLOCKR_RLOCK2_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK2_Pos)    /*!< 0x00000004 */
20967 #define GPIO_RCFGLOCKR_RLOCK2          GPIO_RCFGLOCKR_RLOCK2_Msk
20968 #define GPIO_RCFGLOCKR_RLOCK3_Pos      (3U)
20969 #define GPIO_RCFGLOCKR_RLOCK3_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK3_Pos)    /*!< 0x00000008 */
20970 #define GPIO_RCFGLOCKR_RLOCK3          GPIO_RCFGLOCKR_RLOCK3_Msk
20971 #define GPIO_RCFGLOCKR_RLOCK4_Pos      (4U)
20972 #define GPIO_RCFGLOCKR_RLOCK4_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK4_Pos)    /*!< 0x00000010 */
20973 #define GPIO_RCFGLOCKR_RLOCK4          GPIO_RCFGLOCKR_RLOCK4_Msk
20974 #define GPIO_RCFGLOCKR_RLOCK5_Pos      (5U)
20975 #define GPIO_RCFGLOCKR_RLOCK5_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK5_Pos)    /*!< 0x00000020 */
20976 #define GPIO_RCFGLOCKR_RLOCK5          GPIO_RCFGLOCKR_RLOCK5_Msk
20977 #define GPIO_RCFGLOCKR_RLOCK6_Pos      (6U)
20978 #define GPIO_RCFGLOCKR_RLOCK6_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK6_Pos)    /*!< 0x00000040 */
20979 #define GPIO_RCFGLOCKR_RLOCK6          GPIO_RCFGLOCKR_RLOCK6_Msk
20980 #define GPIO_RCFGLOCKR_RLOCK7_Pos      (7U)
20981 #define GPIO_RCFGLOCKR_RLOCK7_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK7_Pos)    /*!< 0x00000080 */
20982 #define GPIO_RCFGLOCKR_RLOCK7          GPIO_RCFGLOCKR_RLOCK7_Msk
20983 #define GPIO_RCFGLOCKR_RLOCK8_Pos      (8U)
20984 #define GPIO_RCFGLOCKR_RLOCK8_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK8_Pos)    /*!< 0x00000100 */
20985 #define GPIO_RCFGLOCKR_RLOCK8          GPIO_RCFGLOCKR_RLOCK8_Msk
20986 #define GPIO_RCFGLOCKR_RLOCK9_Pos      (9U)
20987 #define GPIO_RCFGLOCKR_RLOCK9_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK9_Pos)    /*!< 0x00000200 */
20988 #define GPIO_RCFGLOCKR_RLOCK9          GPIO_RCFGLOCKR_RLOCK9_Msk
20989 #define GPIO_RCFGLOCKR_RLOCK10_Pos     (10U)
20990 #define GPIO_RCFGLOCKR_RLOCK10_Msk     (0x1UL << GPIO_RCFGLOCKR_RLOCK10_Pos)   /*!< 0x00000400 */
20991 #define GPIO_RCFGLOCKR_RLOCK10         GPIO_RCFGLOCKR_RLOCK10_Msk
20992 #define GPIO_RCFGLOCKR_RLOCK11_Pos     (11U)
20993 #define GPIO_RCFGLOCKR_RLOCK11_Msk     (0x1UL << GPIO_RCFGLOCKR_RLOCK11_Pos)   /*!< 0x00000800 */
20994 #define GPIO_RCFGLOCKR_RLOCK11         GPIO_RCFGLOCKR_RLOCK11_Msk
20995 #define GPIO_RCFGLOCKR_RLOCK12_Pos     (12U)
20996 #define GPIO_RCFGLOCKR_RLOCK12_Msk     (0x1UL << GPIO_RCFGLOCKR_RLOCK12_Pos)   /*!< 0x00001000 */
20997 #define GPIO_RCFGLOCKR_RLOCK12         GPIO_RCFGLOCKR_RLOCK12_Msk
20998 #define GPIO_RCFGLOCKR_RLOCK13_Pos     (13U)
20999 #define GPIO_RCFGLOCKR_RLOCK13_Msk     (0x1UL << GPIO_RCFGLOCKR_RLOCK13_Pos)   /*!< 0x00002000 */
21000 #define GPIO_RCFGLOCKR_RLOCK13         GPIO_RCFGLOCKR_RLOCK13_Msk
21001 #define GPIO_RCFGLOCKR_RLOCK14_Pos     (14U)
21002 #define GPIO_RCFGLOCKR_RLOCK14_Msk     (0x1UL << GPIO_RCFGLOCKR_RLOCK14_Pos)   /*!< 0x00004000 */
21003 #define GPIO_RCFGLOCKR_RLOCK14         GPIO_RCFGLOCKR_RLOCK14_Msk
21004 #define GPIO_RCFGLOCKR_RLOCK15_Pos     (15U)
21005 #define GPIO_RCFGLOCKR_RLOCK15_Msk     (0x1UL << GPIO_RCFGLOCKR_RLOCK15_Pos)   /*!< 0x00008000 */
21006 #define GPIO_RCFGLOCKR_RLOCK15         GPIO_RCFGLOCKR_RLOCK15_Msk
21007 
21008 /****************** Bit definition for GPIO_DELAYRL register *********************/
21009 #define GPIO_DELAYRL_DLY0_Pos        (0U)
21010 #define GPIO_DELAYRL_DLY0_Msk        (0xFUL << GPIO_DELAYRL_DLY0_Pos)          /*!< 0x0000000F */
21011 #define GPIO_DELAYRL_DLY0            GPIO_DELAYRL_DLY0_Msk
21012 #define GPIO_DELAYRL_DLY0_0          (0x1UL << GPIO_DELAYRL_DLY0_Pos)          /*!< 0x00000001 */
21013 #define GPIO_DELAYRL_DLY0_1          (0x2UL << GPIO_DELAYRL_DLY0_Pos)          /*!< 0x00000002 */
21014 #define GPIO_DELAYRL_DLY0_2          (0x4UL << GPIO_DELAYRL_DLY0_Pos)          /*!< 0x00000004 */
21015 #define GPIO_DELAYRL_DLY0_3          (0x8UL << GPIO_DELAYRL_DLY0_Pos)          /*!< 0x00000008 */
21016 #define GPIO_DELAYRL_DLY1_Pos        (4U)
21017 #define GPIO_DELAYRL_DLY1_Msk        (0xFUL << GPIO_DELAYRL_DLY1_Pos)          /*!< 0x000000F0 */
21018 #define GPIO_DELAYRL_DLY1            GPIO_DELAYRL_DLY1_Msk
21019 #define GPIO_DELAYRL_DLY1_0          (0x1UL << GPIO_DELAYRL_DLY1_Pos)          /*!< 0x00000010 */
21020 #define GPIO_DELAYRL_DLY1_1          (0x2UL << GPIO_DELAYRL_DLY1_Pos)          /*!< 0x00000020 */
21021 #define GPIO_DELAYRL_DLY1_2          (0x4UL << GPIO_DELAYRL_DLY1_Pos)          /*!< 0x00000040 */
21022 #define GPIO_DELAYRL_DLY1_3          (0x8UL << GPIO_DELAYRL_DLY1_Pos)          /*!< 0x00000080 */
21023 #define GPIO_DELAYRL_DLY2_Pos        (8U)
21024 #define GPIO_DELAYRL_DLY2_Msk        (0xFUL << GPIO_DELAYRL_DLY2_Pos)          /*!< 0x00000F00 */
21025 #define GPIO_DELAYRL_DLY2            GPIO_DELAYRL_DLY2_Msk
21026 #define GPIO_DELAYRL_DLY2_0          (0x1UL << GPIO_DELAYRL_DLY2_Pos)          /*!< 0x00000100 */
21027 #define GPIO_DELAYRL_DLY2_1          (0x2UL << GPIO_DELAYRL_DLY2_Pos)          /*!< 0x00000200 */
21028 #define GPIO_DELAYRL_DLY2_2          (0x4UL << GPIO_DELAYRL_DLY2_Pos)          /*!< 0x00000400 */
21029 #define GPIO_DELAYRL_DLY2_3          (0x8UL << GPIO_DELAYRL_DLY2_Pos)          /*!< 0x00000800 */
21030 #define GPIO_DELAYRL_DLY3_Pos        (12U)
21031 #define GPIO_DELAYRL_DLY3_Msk        (0xFUL << GPIO_DELAYRL_DLY3_Pos)          /*!< 0x0000F000 */
21032 #define GPIO_DELAYRL_DLY3            GPIO_DELAYRL_DLY3_Msk
21033 #define GPIO_DELAYRL_DLY3_0          (0x1UL << GPIO_DELAYRL_DLY3_Pos)          /*!< 0x00001000 */
21034 #define GPIO_DELAYRL_DLY3_1          (0x2UL << GPIO_DELAYRL_DLY3_Pos)          /*!< 0x00002000 */
21035 #define GPIO_DELAYRL_DLY3_2          (0x4UL << GPIO_DELAYRL_DLY3_Pos)          /*!< 0x00004000 */
21036 #define GPIO_DELAYRL_DLY3_3          (0x8UL << GPIO_DELAYRL_DLY3_Pos)          /*!< 0x00008000 */
21037 #define GPIO_DELAYRL_DLY4_Pos        (16U)
21038 #define GPIO_DELAYRL_DLY4_Msk        (0xFUL << GPIO_DELAYRL_DLY4_Pos)          /*!< 0x000F0000 */
21039 #define GPIO_DELAYRL_DLY4            GPIO_DELAYRL_DLY4_Msk
21040 #define GPIO_DELAYRL_DLY4_0          (0x1UL << GPIO_DELAYRL_DLY4_Pos)          /*!< 0x00010000 */
21041 #define GPIO_DELAYRL_DLY4_1          (0x2UL << GPIO_DELAYRL_DLY4_Pos)          /*!< 0x00020000 */
21042 #define GPIO_DELAYRL_DLY4_2          (0x4UL << GPIO_DELAYRL_DLY4_Pos)          /*!< 0x00040000 */
21043 #define GPIO_DELAYRL_DLY4_3          (0x8UL << GPIO_DELAYRL_DLY4_Pos)          /*!< 0x00080000 */
21044 #define GPIO_DELAYRL_DLY5_Pos        (20U)
21045 #define GPIO_DELAYRL_DLY5_Msk        (0xFUL << GPIO_DELAYRL_DLY5_Pos)          /*!< 0x00F00000 */
21046 #define GPIO_DELAYRL_DLY5            GPIO_DELAYRL_DLY5_Msk
21047 #define GPIO_DELAYRL_DLY5_0          (0x1UL << GPIO_DELAYRL_DLY5_Pos)          /*!< 0x00100000 */
21048 #define GPIO_DELAYRL_DLY5_1          (0x2UL << GPIO_DELAYRL_DLY5_Pos)          /*!< 0x00200000 */
21049 #define GPIO_DELAYRL_DLY5_2          (0x4UL << GPIO_DELAYRL_DLY5_Pos)          /*!< 0x00400000 */
21050 #define GPIO_DELAYRL_DLY5_3          (0x8UL << GPIO_DELAYRL_DLY5_Pos)          /*!< 0x00800000 */
21051 #define GPIO_DELAYRL_DLY6_Pos        (24U)
21052 #define GPIO_DELAYRL_DLY6_Msk        (0xFUL << GPIO_DELAYRL_DLY6_Pos)          /*!< 0x0F000000 */
21053 #define GPIO_DELAYRL_DLY6            GPIO_DELAYRL_DLY6_Msk
21054 #define GPIO_DELAYRL_DLY6_0          (0x1UL << GPIO_DELAYRL_DLY6_Pos)          /*!< 0x01000000 */
21055 #define GPIO_DELAYRL_DLY6_1          (0x2UL << GPIO_DELAYRL_DLY6_Pos)          /*!< 0x02000000 */
21056 #define GPIO_DELAYRL_DLY6_2          (0x4UL << GPIO_DELAYRL_DLY6_Pos)          /*!< 0x04000000 */
21057 #define GPIO_DELAYRL_DLY6_3          (0x8UL << GPIO_DELAYRL_DLY6_Pos)          /*!< 0x08000000 */
21058 #define GPIO_DELAYRL_DLY7_Pos        (28U)
21059 #define GPIO_DELAYRL_DLY7_Msk        (0xFUL << GPIO_DELAYRL_DLY7_Pos)          /*!< 0xF0000000 */
21060 #define GPIO_DELAYRL_DLY7            GPIO_DELAYRL_DLY7_Msk
21061 #define GPIO_DELAYRL_DLY7_0          (0x1UL << GPIO_DELAYRL_DLY7_Pos)          /*!< 0x10000000 */
21062 #define GPIO_DELAYRL_DLY7_1          (0x2UL << GPIO_DELAYRL_DLY7_Pos)          /*!< 0x20000000 */
21063 #define GPIO_DELAYRL_DLY7_2          (0x4UL << GPIO_DELAYRL_DLY7_Pos)          /*!< 0x40000000 */
21064 #define GPIO_DELAYRL_DLY7_3          (0x8UL << GPIO_DELAYRL_DLY7_Pos)          /*!< 0x80000000 */
21065 
21066 /****************** Bit definition for GPIO_DELAYRH register *********************/
21067 #define GPIO_DELAYRH_DLY8_Pos        (0U)
21068 #define GPIO_DELAYRH_DLY8_Msk        (0xFUL << GPIO_DELAYRH_DLY8_Pos)          /*!< 0x0000000F */
21069 #define GPIO_DELAYRH_DLY8            GPIO_DELAYRH_DLY8_Msk
21070 #define GPIO_DELAYRH_DLY8_0          (0x1UL << GPIO_DELAYRH_DLY8_Pos)          /*!< 0x00000001 */
21071 #define GPIO_DELAYRH_DLY8_1          (0x2UL << GPIO_DELAYRH_DLY8_Pos)          /*!< 0x00000002 */
21072 #define GPIO_DELAYRH_DLY8_2          (0x4UL << GPIO_DELAYRH_DLY8_Pos)          /*!< 0x00000004 */
21073 #define GPIO_DELAYRH_DLY8_3          (0x8UL << GPIO_DELAYRH_DLY8_Pos)          /*!< 0x00000008 */
21074 #define GPIO_DELAYRH_DLY9_Pos        (4U)
21075 #define GPIO_DELAYRH_DLY9_Msk        (0xFUL << GPIO_DELAYRH_DLY9_Pos)          /*!< 0x000000F0 */
21076 #define GPIO_DELAYRH_DLY9            GPIO_DELAYRH_DLY9_Msk
21077 #define GPIO_DELAYRH_DLY9_0          (0x1UL << GPIO_DELAYRH_DLY9_Pos)          /*!< 0x00000010 */
21078 #define GPIO_DELAYRH_DLY9_1          (0x2UL << GPIO_DELAYRH_DLY9_Pos)          /*!< 0x00000020 */
21079 #define GPIO_DELAYRH_DLY9_2          (0x4UL << GPIO_DELAYRH_DLY9_Pos)          /*!< 0x00000040 */
21080 #define GPIO_DELAYRH_DLY9_3          (0x8UL << GPIO_DELAYRH_DLY9_Pos)          /*!< 0x00000080 */
21081 #define GPIO_DELAYRH_DLY10_Pos       (8U)
21082 #define GPIO_DELAYRH_DLY10_Msk       (0xFUL << GPIO_DELAYRH_DLY10_Pos)         /*!< 0x00000F00 */
21083 #define GPIO_DELAYRH_DLY10           GPIO_DELAYRH_DLY10_Msk
21084 #define GPIO_DELAYRH_DLY10_0         (0x1UL << GPIO_DELAYRH_DLY10_Pos)         /*!< 0x00000100 */
21085 #define GPIO_DELAYRH_DLY10_1         (0x2UL << GPIO_DELAYRH_DLY10_Pos)         /*!< 0x00000200 */
21086 #define GPIO_DELAYRH_DLY10_2         (0x4UL << GPIO_DELAYRH_DLY10_Pos)         /*!< 0x00000400 */
21087 #define GPIO_DELAYRH_DLY10_3         (0x8UL << GPIO_DELAYRH_DLY10_Pos)         /*!< 0x00000800 */
21088 #define GPIO_DELAYRH_DLY11_Pos       (12U)
21089 #define GPIO_DELAYRH_DLY11_Msk       (0xFUL << GPIO_DELAYRH_DLY11_Pos)         /*!< 0x0000F000 */
21090 #define GPIO_DELAYRH_DLY11           GPIO_DELAYRH_DLY11_Msk
21091 #define GPIO_DELAYRH_DLY11_0         (0x1UL << GPIO_DELAYRH_DLY11_Pos)         /*!< 0x00001000 */
21092 #define GPIO_DELAYRH_DLY11_1         (0x2UL << GPIO_DELAYRH_DLY11_Pos)         /*!< 0x00002000 */
21093 #define GPIO_DELAYRH_DLY11_2         (0x4UL << GPIO_DELAYRH_DLY11_Pos)         /*!< 0x00004000 */
21094 #define GPIO_DELAYRH_DLY11_3         (0x8UL << GPIO_DELAYRH_DLY11_Pos)         /*!< 0x00008000 */
21095 #define GPIO_DELAYRH_DLY12_Pos       (16U)
21096 #define GPIO_DELAYRH_DLY12_Msk       (0xFUL << GPIO_DELAYRH_DLY12_Pos)         /*!< 0x000F0000 */
21097 #define GPIO_DELAYRH_DLY12           GPIO_DELAYRH_DLY12_Msk
21098 #define GPIO_DELAYRH_DLY12_0         (0x1UL << GPIO_DELAYRH_DLY12_Pos)         /*!< 0x00010000 */
21099 #define GPIO_DELAYRH_DLY12_1         (0x2UL << GPIO_DELAYRH_DLY12_Pos)         /*!< 0x00020000 */
21100 #define GPIO_DELAYRH_DLY12_2         (0x4UL << GPIO_DELAYRH_DLY12_Pos)         /*!< 0x00040000 */
21101 #define GPIO_DELAYRH_DLY12_3         (0x8UL << GPIO_DELAYRH_DLY12_Pos)         /*!< 0x00080000 */
21102 #define GPIO_DELAYRH_DLY13_Pos       (20U)
21103 #define GPIO_DELAYRH_DLY13_Msk       (0xFUL << GPIO_DELAYRH_DLY13_Pos)         /*!< 0x00F00000 */
21104 #define GPIO_DELAYRH_DLY13           GPIO_DELAYRH_DLY13_Msk
21105 #define GPIO_DELAYRH_DLY13_0         (0x1UL << GPIO_DELAYRH_DLY13_Pos)         /*!< 0x00100000 */
21106 #define GPIO_DELAYRH_DLY13_1         (0x2UL << GPIO_DELAYRH_DLY13_Pos)         /*!< 0x00200000 */
21107 #define GPIO_DELAYRH_DLY13_2         (0x4UL << GPIO_DELAYRH_DLY13_Pos)         /*!< 0x00400000 */
21108 #define GPIO_DELAYRH_DLY13_3         (0x8UL << GPIO_DELAYRH_DLY13_Pos)         /*!< 0x00800000 */
21109 #define GPIO_DELAYRH_DLY14_Pos       (24U)
21110 #define GPIO_DELAYRH_DLY14_Msk       (0xFUL << GPIO_DELAYRH_DLY14_Pos)         /*!< 0x0F000000 */
21111 #define GPIO_DELAYRH_DLY14           GPIO_DELAYRH_DLY14_Msk
21112 #define GPIO_DELAYRH_DLY14_0         (0x1UL << GPIO_DELAYRH_DLY14_Pos)         /*!< 0x01000000 */
21113 #define GPIO_DELAYRH_DLY14_1         (0x2UL << GPIO_DELAYRH_DLY14_Pos)         /*!< 0x02000000 */
21114 #define GPIO_DELAYRH_DLY14_2         (0x4UL << GPIO_DELAYRH_DLY14_Pos)         /*!< 0x04000000 */
21115 #define GPIO_DELAYRH_DLY14_3         (0x8UL << GPIO_DELAYRH_DLY14_Pos)         /*!< 0x08000000 */
21116 #define GPIO_DELAYRH_DLY15_Pos       (28U)
21117 #define GPIO_DELAYRH_DLY15_Msk       (0xFUL << GPIO_DELAYRH_DLY15_Pos)         /*!< 0xF0000000 */
21118 #define GPIO_DELAYRH_DLY15           GPIO_DELAYRH_DLY15_Msk
21119 #define GPIO_DELAYRH_DLY15_0         (0x1UL << GPIO_DELAYRH_DLY15_Pos)         /*!< 0x10000000 */
21120 #define GPIO_DELAYRH_DLY15_1         (0x2UL << GPIO_DELAYRH_DLY15_Pos)         /*!< 0x20000000 */
21121 #define GPIO_DELAYRH_DLY15_2         (0x4UL << GPIO_DELAYRH_DLY15_Pos)         /*!< 0x40000000 */
21122 #define GPIO_DELAYRH_DLY15_3         (0x8UL << GPIO_DELAYRH_DLY15_Pos)         /*!< 0x80000000 */
21123 
21124 /****************** Bit definition for GPIO_ADVCFGRL register *********************/
21125 #define GPIO_ADVCFGRL_0_Pos            (0U)
21126 #define GPIO_ADVCFGRL_0_Msk            (0xFUL << GPIO_ADVCFGRL_0_Pos)          /*!< 0x0000000F */
21127 #define GPIO_ADVCFGRL_0                GPIO_ADVCFGRL_0_Msk
21128 #define GPIO_ADVCFGRL_DLYPATH0         (0x1UL << GPIO_ADVCFGRL_0_Pos)          /*!< 0x00000001 */
21129 #define GPIO_ADVCFGRL_DE0              (0x2UL << GPIO_ADVCFGRL_0_Pos)          /*!< 0x00000002 */
21130 #define GPIO_ADVCFGRL_INVCLK0          (0x4UL << GPIO_ADVCFGRL_0_Pos)          /*!< 0x00000004 */
21131 #define GPIO_ADVCFGRL_RET0             (0x8UL << GPIO_ADVCFGRL_0_Pos)          /*!< 0x00000008 */
21132 #define GPIO_ADVCFGRL_1_Pos            (4U)
21133 #define GPIO_ADVCFGRL_1_Msk            (0xFUL << GPIO_ADVCFGRL_1_Pos)          /*!< 0x000000F0 */
21134 #define GPIO_ADVCFGRL_1                GPIO_ADVCFGRL_1_Msk
21135 #define GPIO_ADVCFGRL_DLYPATH1         (0x1UL << GPIO_ADVCFGRL_1_Pos)          /*!< 0x00000010 */
21136 #define GPIO_ADVCFGRL_DE1              (0x2UL << GPIO_ADVCFGRL_1_Pos)          /*!< 0x00000020 */
21137 #define GPIO_ADVCFGRL_INVCLK1          (0x4UL << GPIO_ADVCFGRL_1_Pos)          /*!< 0x00000040 */
21138 #define GPIO_ADVCFGRL_RET1             (0x8UL << GPIO_ADVCFGRL_1_Pos)          /*!< 0x00000080 */
21139 #define GPIO_ADVCFGRL_2_Pos            (8U)
21140 #define GPIO_ADVCFGRL_2_Msk            (0xFUL << GPIO_ADVCFGRL_2_Pos)          /*!< 0x00000F00 */
21141 #define GPIO_ADVCFGRL_2                GPIO_ADVCFGRL_2_Msk
21142 #define GPIO_ADVCFGRL_DLYPATH2         (0x1UL << GPIO_ADVCFGRL_2_Pos)          /*!< 0x00000100 */
21143 #define GPIO_ADVCFGRL_DE2              (0x2UL << GPIO_ADVCFGRL_2_Pos)          /*!< 0x00000200 */
21144 #define GPIO_ADVCFGRL_INVCLK2          (0x4UL << GPIO_ADVCFGRL_2_Pos)          /*!< 0x00000400 */
21145 #define GPIO_ADVCFGRL_RET2             (0x8UL << GPIO_ADVCFGRL_2_Pos)          /*!< 0x00000800 */
21146 #define GPIO_ADVCFGRL_3_Pos            (12U)
21147 #define GPIO_ADVCFGRL_3_Msk            (0xFUL << GPIO_ADVCFGRL_3_Pos)          /*!< 0x0000F000 */
21148 #define GPIO_ADVCFGRL_3                GPIO_ADVCFGRL_3_Msk
21149 #define GPIO_ADVCFGRL_DLYPATH3         (0x1UL << GPIO_ADVCFGRL_3_Pos)          /*!< 0x00001000 */
21150 #define GPIO_ADVCFGRL_DE3              (0x2UL << GPIO_ADVCFGRL_3_Pos)          /*!< 0x00002000 */
21151 #define GPIO_ADVCFGRL_INVCLK3          (0x4UL << GPIO_ADVCFGRL_3_Pos)          /*!< 0x00004000 */
21152 #define GPIO_ADVCFGRL_RET3             (0x8UL << GPIO_ADVCFGRL_3_Pos)          /*!< 0x00008000 */
21153 #define GPIO_ADVCFGRL_4_Pos            (16U)
21154 #define GPIO_ADVCFGRL_4_Msk            (0xFUL << GPIO_ADVCFGRL_4_Pos)          /*!< 0x000F0000 */
21155 #define GPIO_ADVCFGRL_4                GPIO_ADVCFGRL_4_Msk
21156 #define GPIO_ADVCFGRL_DLYPATH4         (0x1UL << GPIO_ADVCFGRL_4_Pos)          /*!< 0x00010000 */
21157 #define GPIO_ADVCFGRL_DE4              (0x2UL << GPIO_ADVCFGRL_4_Pos)          /*!< 0x00020000 */
21158 #define GPIO_ADVCFGRL_INVCLK4          (0x4UL << GPIO_ADVCFGRL_4_Pos)          /*!< 0x00040000 */
21159 #define GPIO_ADVCFGRL_RET4             (0x8UL << GPIO_ADVCFGRL_4_Pos)          /*!< 0x00080000 */
21160 #define GPIO_ADVCFGRL_5_Pos            (20U)
21161 #define GPIO_ADVCFGRL_5_Msk            (0xFUL << GPIO_ADVCFGRL_5_Pos)          /*!< 0x00F00000 */
21162 #define GPIO_ADVCFGRL_5                GPIO_ADVCFGRL_5_Msk
21163 #define GPIO_ADVCFGRL_DLYPATH5         (0x1UL << GPIO_ADVCFGRL_5_Pos)          /*!< 0x00100000 */
21164 #define GPIO_ADVCFGRL_DE5              (0x2UL << GPIO_ADVCFGRL_5_Pos)          /*!< 0x00200000 */
21165 #define GPIO_ADVCFGRL_INVCLK5          (0x4UL << GPIO_ADVCFGRL_5_Pos)          /*!< 0x00400000 */
21166 #define GPIO_ADVCFGRL_RET5             (0x8UL << GPIO_ADVCFGRL_5_Pos)          /*!< 0x00800000 */
21167 #define GPIO_ADVCFGRL_6_Pos            (24U)
21168 #define GPIO_ADVCFGRL_6_Msk            (0xFUL << GPIO_ADVCFGRL_6_Pos)          /*!< 0x0F000000 */
21169 #define GPIO_ADVCFGRL_6                GPIO_ADVCFGRL_6_Msk
21170 #define GPIO_ADVCFGRL_DLYPATH6         (0x1UL << GPIO_ADVCFGRL_6_Pos)          /*!< 0x01000000 */
21171 #define GPIO_ADVCFGRL_DE6              (0x2UL << GPIO_ADVCFGRL_6_Pos)          /*!< 0x02000000 */
21172 #define GPIO_ADVCFGRL_INVCLK6          (0x4UL << GPIO_ADVCFGRL_6_Pos)          /*!< 0x04000000 */
21173 #define GPIO_ADVCFGRL_RET6             (0x8UL << GPIO_ADVCFGRL_6_Pos)          /*!< 0x08000000 */
21174 #define GPIO_ADVCFGRL_7_Pos            (28U)
21175 #define GPIO_ADVCFGRL_7_Msk            (0xFUL << GPIO_ADVCFGRL_7_Pos)          /*!< 0xF0000000 */
21176 #define GPIO_ADVCFGRL_7                GPIO_ADVCFGRL_7_Msk
21177 #define GPIO_ADVCFGRL_DLYPATH7         (0x1UL << GPIO_ADVCFGRL_7_Pos)          /*!< 0x10000000 */
21178 #define GPIO_ADVCFGRL_DE7              (0x2UL << GPIO_ADVCFGRL_7_Pos)          /*!< 0x20000000 */
21179 #define GPIO_ADVCFGRL_INVCLK7          (0x4UL << GPIO_ADVCFGRL_7_Pos)          /*!< 0x40000000 */
21180 #define GPIO_ADVCFGRL_RET7             (0x8UL << GPIO_ADVCFGRL_7_Pos)          /*!< 0x80000000 */
21181 
21182 /****************** Bit definition for GPIO_ADVCFGRH register *********************/
21183 #define GPIO_ADVCFGRH_8_Pos            (0U)
21184 #define GPIO_ADVCFGRH_8_Msk            (0xFUL << GPIO_ADVCFGRH_8_Pos)          /*!< 0x0000000F */
21185 #define GPIO_ADVCFGRH_8                GPIO_ADVCFGRH_8_Msk
21186 #define GPIO_ADVCFGRH_DLYPATH8         (0x1UL << GPIO_ADVCFGRH_8_Pos)          /*!< 0x00000001 */
21187 #define GPIO_ADVCFGRH_DE8              (0x2UL << GPIO_ADVCFGRH_8_Pos)          /*!< 0x00000002 */
21188 #define GPIO_ADVCFGRH_INVCLK8          (0x4UL << GPIO_ADVCFGRH_8_Pos)          /*!< 0x00000004 */
21189 #define GPIO_ADVCFGRH_RET8             (0x8UL << GPIO_ADVCFGRH_8_Pos)          /*!< 0x00000008 */
21190 #define GPIO_ADVCFGRH_9_Pos            (4U)
21191 #define GPIO_ADVCFGRH_9_Msk            (0xFUL << GPIO_ADVCFGRH_9_Pos)          /*!< 0x000000F0 */
21192 #define GPIO_ADVCFGRH_9                GPIO_ADVCFGRH_9_Msk
21193 #define GPIO_ADVCFGRH_DLYPATH9         (0x1UL << GPIO_ADVCFGRH_9_Pos)          /*!< 0x00000010 */
21194 #define GPIO_ADVCFGRH_DE9              (0x2UL << GPIO_ADVCFGRH_9_Pos)          /*!< 0x00000020 */
21195 #define GPIO_ADVCFGRH_INVCLK9          (0x4UL << GPIO_ADVCFGRH_9_Pos)          /*!< 0x00000040 */
21196 #define GPIO_ADVCFGRH_RET9             (0x8UL << GPIO_ADVCFGRH_9_Pos)          /*!< 0x00000080 */
21197 #define GPIO_ADVCFGRH_10_Pos           (8U)
21198 #define GPIO_ADVCFGRH_10_Msk           (0xFUL << GPIO_ADVCFGRH_10_Pos)         /*!< 0x00000F00 */
21199 #define GPIO_ADVCFGRH_10               GPIO_ADVCFGRH_10_Msk
21200 #define GPIO_ADVCFGRH_DLYPATH10        (0x1UL << GPIO_ADVCFGRH_10_Pos)         /*!< 0x00000100 */
21201 #define GPIO_ADVCFGRH_DE10             (0x2UL << GPIO_ADVCFGRH_10_Pos)         /*!< 0x00000200 */
21202 #define GPIO_ADVCFGRH_INVCLK10         (0x4UL << GPIO_ADVCFGRH_10_Pos)         /*!< 0x00000400 */
21203 #define GPIO_ADVCFGRH_RET10            (0x8UL << GPIO_ADVCFGRH_10_Pos)         /*!< 0x00000800 */
21204 #define GPIO_ADVCFGRH_11_Pos           (12U)
21205 #define GPIO_ADVCFGRH_11_Msk           (0xFUL << GPIO_ADVCFGRH_11_Pos)         /*!< 0x0000F000 */
21206 #define GPIO_ADVCFGRH_11               GPIO_ADVCFGRH_11_Msk
21207 #define GPIO_ADVCFGRH_DLYPATH11        (0x1UL << GPIO_ADVCFGRH_11_Pos)         /*!< 0x00001000 */
21208 #define GPIO_ADVCFGRH_DE11             (0x2UL << GPIO_ADVCFGRH_11_Pos)         /*!< 0x00002000 */
21209 #define GPIO_ADVCFGRH_INVCLK11         (0x4UL << GPIO_ADVCFGRH_11_Pos)         /*!< 0x00004000 */
21210 #define GPIO_ADVCFGRH_RET11            (0x8UL << GPIO_ADVCFGRH_11_Pos)         /*!< 0x00008000 */
21211 #define GPIO_ADVCFGRH_12_Pos           (16U)
21212 #define GPIO_ADVCFGRH_12_Msk           (0xFUL << GPIO_ADVCFGRH_12_Pos)         /*!< 0x000F0000 */
21213 #define GPIO_ADVCFGRH_12               GPIO_ADVCFGRH_12_Msk
21214 #define GPIO_ADVCFGRH_DLYPATH12        (0x1UL << GPIO_ADVCFGRH_12_Pos)         /*!< 0x00010000 */
21215 #define GPIO_ADVCFGRH_DE12             (0x2UL << GPIO_ADVCFGRH_12_Pos)         /*!< 0x00020000 */
21216 #define GPIO_ADVCFGRH_INVCLK12         (0x4UL << GPIO_ADVCFGRH_12_Pos)         /*!< 0x00040000 */
21217 #define GPIO_ADVCFGRH_RET12            (0x8UL << GPIO_ADVCFGRH_12_Pos)         /*!< 0x00080000 */
21218 #define GPIO_ADVCFGRH_13_Pos           (20U)
21219 #define GPIO_ADVCFGRH_13_Msk           (0xFUL << GPIO_ADVCFGRH_13_Pos)         /*!< 0x00F00000 */
21220 #define GPIO_ADVCFGRH_13               GPIO_ADVCFGRH_13_Msk
21221 #define GPIO_ADVCFGRH_DLYPATH13        (0x1UL << GPIO_ADVCFGRH_13_Pos)         /*!< 0x00100000 */
21222 #define GPIO_ADVCFGRH_DE13             (0x2UL << GPIO_ADVCFGRH_13_Pos)         /*!< 0x00200000 */
21223 #define GPIO_ADVCFGRH_INVCLK13         (0x4UL << GPIO_ADVCFGRH_13_Pos)         /*!< 0x00400000 */
21224 #define GPIO_ADVCFGRH_RET13            (0x8UL << GPIO_ADVCFGRH_13_Pos)         /*!< 0x00800000 */
21225 #define GPIO_ADVCFGRH_14_Pos           (24U)
21226 #define GPIO_ADVCFGRH_14_Msk           (0xFUL << GPIO_ADVCFGRH_14_Pos)         /*!< 0x0F000000 */
21227 #define GPIO_ADVCFGRH_14               GPIO_ADVCFGRH_14_Msk
21228 #define GPIO_ADVCFGRH_DLYPATH14        (0x1UL << GPIO_ADVCFGRH_14_Pos)         /*!< 0x01000000 */
21229 #define GPIO_ADVCFGRH_DE14             (0x2UL << GPIO_ADVCFGRH_14_Pos)         /*!< 0x02000000 */
21230 #define GPIO_ADVCFGRH_INVCLK14         (0x4UL << GPIO_ADVCFGRH_14_Pos)         /*!< 0x04000000 */
21231 #define GPIO_ADVCFGRH_RET14            (0x8UL << GPIO_ADVCFGRH_14_Pos)         /*!< 0x08000000 */
21232 #define GPIO_ADVCFGRH_15_Pos           (28U)
21233 #define GPIO_ADVCFGRH_15_Msk           (0xFUL << GPIO_ADVCFGRH_15_Pos)         /*!< 0xF0000000 */
21234 #define GPIO_ADVCFGRH_15               GPIO_ADVCFGRH_15_Msk
21235 #define GPIO_ADVCFGRH_DLYPATH15        (0x1UL << GPIO_ADVCFGRH_15_Pos)         /*!< 0x10000000 */
21236 #define GPIO_ADVCFGRH_DE15             (0x2UL << GPIO_ADVCFGRH_15_Pos)         /*!< 0x20000000 */
21237 #define GPIO_ADVCFGRH_INVCLK15         (0x4UL << GPIO_ADVCFGRH_15_Pos)         /*!< 0x40000000 */
21238 #define GPIO_ADVCFGRH_RET15            (0x8UL << GPIO_ADVCFGRH_15_Pos)         /*!< 0x80000000 */
21239 
21240 
21241 /******************************************************************************/
21242 /*                                                                            */
21243 /*                                    HASH                                    */
21244 /*                                                                            */
21245 /******************************************************************************/
21246 /******************  Bits definition for HASH_CR register  ********************/
21247 #define HASH_CR_INIT_Pos                    (2U)
21248 #define HASH_CR_INIT_Msk                    (0x1UL << HASH_CR_INIT_Pos)             /*!< 0x00000004 */
21249 #define HASH_CR_INIT                        HASH_CR_INIT_Msk
21250 #define HASH_CR_DMAE_Pos                    (3U)
21251 #define HASH_CR_DMAE_Msk                    (0x1UL << HASH_CR_DMAE_Pos)             /*!< 0x00000008 */
21252 #define HASH_CR_DMAE                        HASH_CR_DMAE_Msk
21253 #define HASH_CR_DATATYPE_Pos                (4U)
21254 #define HASH_CR_DATATYPE_Msk                (0x3UL << HASH_CR_DATATYPE_Pos)         /*!< 0x00000030 */
21255 #define HASH_CR_DATATYPE                    HASH_CR_DATATYPE_Msk
21256 #define HASH_CR_DATATYPE_0                  (0x1UL << HASH_CR_DATATYPE_Pos)         /*!< 0x00000010 */
21257 #define HASH_CR_DATATYPE_1                  (0x2UL << HASH_CR_DATATYPE_Pos)         /*!< 0x00000020 */
21258 #define HASH_CR_MODE_Pos                    (6U)
21259 #define HASH_CR_MODE_Msk                    (0x1UL << HASH_CR_MODE_Pos)             /*!< 0x00000040 */
21260 #define HASH_CR_MODE                        HASH_CR_MODE_Msk
21261 #define HASH_CR_NBW_Pos                     (8U)
21262 #define HASH_CR_NBW_Msk                     (0xFUL << HASH_CR_NBW_Pos)              /*!< 0x00000F00 */
21263 #define HASH_CR_NBW                         HASH_CR_NBW_Msk
21264 #define HASH_CR_NBW_0                       (0x1UL << HASH_CR_NBW_Pos)              /*!< 0x00000100 */
21265 #define HASH_CR_NBW_1                       (0x2UL << HASH_CR_NBW_Pos)              /*!< 0x00000200 */
21266 #define HASH_CR_NBW_2                       (0x4UL << HASH_CR_NBW_Pos)              /*!< 0x00000400 */
21267 #define HASH_CR_NBW_3                       (0x8UL << HASH_CR_NBW_Pos)              /*!< 0x00000800 */
21268 #define HASH_CR_DINNE_Pos                   (12U)
21269 #define HASH_CR_DINNE_Msk                   (0x1UL << HASH_CR_DINNE_Pos)            /*!< 0x00001000 */
21270 #define HASH_CR_DINNE                       HASH_CR_DINNE_Msk
21271 #define HASH_CR_MDMAT_Pos                   (13U)
21272 #define HASH_CR_MDMAT_Msk                   (0x1UL << HASH_CR_MDMAT_Pos)            /*!< 0x00002000 */
21273 #define HASH_CR_MDMAT                       HASH_CR_MDMAT_Msk
21274 #define HASH_CR_LKEY_Pos                    (16U)
21275 #define HASH_CR_LKEY_Msk                    (0x1UL << HASH_CR_LKEY_Pos)             /*!< 0x00010000 */
21276 #define HASH_CR_LKEY                        HASH_CR_LKEY_Msk
21277 #define HASH_CR_ALGO_Pos                    (17U)
21278 #define HASH_CR_ALGO_Msk                    (0xFUL << HASH_CR_ALGO_Pos)             /*!< 0x001E0000 */
21279 #define HASH_CR_ALGO                        HASH_CR_ALGO_Msk
21280 #define HASH_CR_ALGO_0                      (0x1UL << HASH_CR_ALGO_Pos)             /*!< 0x00020000 */
21281 #define HASH_CR_ALGO_1                      (0x2UL << HASH_CR_ALGO_Pos)             /*!< 0x00040000 */
21282 #define HASH_CR_ALGO_2                      (0x4UL << HASH_CR_ALGO_Pos)             /*!< 0x00080000 */
21283 #define HASH_CR_ALGO_3                      (0x8UL << HASH_CR_ALGO_Pos)             /*!< 0x00100000 */
21284 
21285 /******************  Bits definition for HASH_STR register  *******************/
21286 #define HASH_STR_NBLW_Pos                   (0U)
21287 #define HASH_STR_NBLW_Msk                   (0x1FUL << HASH_STR_NBLW_Pos)           /*!< 0x0000001F */
21288 #define HASH_STR_NBLW                       HASH_STR_NBLW_Msk
21289 #define HASH_STR_NBLW_0                     (0x01UL << HASH_STR_NBLW_Pos)           /*!< 0x00000001 */
21290 #define HASH_STR_NBLW_1                     (0x02UL << HASH_STR_NBLW_Pos)           /*!< 0x00000002 */
21291 #define HASH_STR_NBLW_2                     (0x04UL << HASH_STR_NBLW_Pos)           /*!< 0x00000004 */
21292 #define HASH_STR_NBLW_3                     (0x08UL << HASH_STR_NBLW_Pos)           /*!< 0x00000008 */
21293 #define HASH_STR_NBLW_4                     (0x10UL << HASH_STR_NBLW_Pos)           /*!< 0x00000010 */
21294 #define HASH_STR_DCAL_Pos                   (8U)
21295 #define HASH_STR_DCAL_Msk                   (0x1UL << HASH_STR_DCAL_Pos)            /*!< 0x00000100 */
21296 #define HASH_STR_DCAL                       HASH_STR_DCAL_Msk
21297 
21298 /******************  Bits definition for HASH_IMR register  *******************/
21299 #define HASH_IMR_DINIE_Pos                  (0U)
21300 #define HASH_IMR_DINIE_Msk                  (0x1UL << HASH_IMR_DINIE_Pos)           /*!< 0x00000001 */
21301 #define HASH_IMR_DINIE                      HASH_IMR_DINIE_Msk
21302 #define HASH_IMR_DCIE_Pos                   (1U)
21303 #define HASH_IMR_DCIE_Msk                   (0x1UL << HASH_IMR_DCIE_Pos)            /*!< 0x00000002 */
21304 #define HASH_IMR_DCIE                       HASH_IMR_DCIE_Msk
21305 
21306 /******************  Bits definition for HASH_SR register  ********************/
21307 #define HASH_SR_DINIS_Pos                   (0U)
21308 #define HASH_SR_DINIS_Msk                   (0x1UL << HASH_SR_DINIS_Pos)            /*!< 0x00000001 */
21309 #define HASH_SR_DINIS                       HASH_SR_DINIS_Msk
21310 #define HASH_SR_DCIS_Pos                    (1U)
21311 #define HASH_SR_DCIS_Msk                    (0x1UL << HASH_SR_DCIS_Pos)             /*!< 0x00000002 */
21312 #define HASH_SR_DCIS                        HASH_SR_DCIS_Msk
21313 #define HASH_SR_DMAS_Pos                    (2U)
21314 #define HASH_SR_DMAS_Msk                    (0x1UL << HASH_SR_DMAS_Pos)             /*!< 0x00000004 */
21315 #define HASH_SR_DMAS                        HASH_SR_DMAS_Msk
21316 #define HASH_SR_BUSY_Pos                    (3U)
21317 #define HASH_SR_BUSY_Msk                    (0x1UL << HASH_SR_BUSY_Pos)             /*!< 0x00000008 */
21318 #define HASH_SR_BUSY                        HASH_SR_BUSY_Msk
21319 #define HASH_SR_NBWE_Pos                    (16U)
21320 #define HASH_SR_NBWE_Msk                    (0xFUL << HASH_SR_NBWE_Pos)             /*!< 0x000F0000 */
21321 #define HASH_SR_NBWE                        HASH_SR_NBWE_Msk
21322 #define HASH_SR_NBWE_0                      (0x01UL << HASH_SR_NBWE_Pos)            /*!< 0x00010000 */
21323 #define HASH_SR_NBWE_1                      (0x02UL << HASH_SR_NBWE_Pos)            /*!< 0x00020000 */
21324 #define HASH_SR_NBWE_2                      (0x04UL << HASH_SR_NBWE_Pos)            /*!< 0x00040000 */
21325 #define HASH_SR_NBWE_3                      (0x08UL << HASH_SR_NBWE_Pos)            /*!< 0x00080000 */
21326 #define HASH_SR_DINNE_Pos                   (15U)
21327 #define HASH_SR_DINNE_Msk                   (0x1UL << HASH_SR_DINNE_Pos)            /*!< 0x00008000 */
21328 #define HASH_SR_DINNE                       HASH_SR_DINNE_Msk
21329 #define HASH_SR_NBWP_Pos                    (9U)
21330 #define HASH_SR_NBWP_Msk                    (0xFUL << HASH_SR_NBWP_Pos)             /*!< 0x000F0000 */
21331 #define HASH_SR_NBWP                        HASH_SR_NBWP_Msk
21332 #define HASH_SR_NBWP_0                      (0x01UL << HASH_SR_NBWP_Pos)            /*!< 0x000O0200 */
21333 #define HASH_SR_NBWP_1                      (0x02UL << HASH_SR_NBWP_Pos)            /*!< 0x00000400 */
21334 #define HASH_SR_NBWP_2                      (0x04UL << HASH_SR_NBWP_Pos)            /*!< 0x00000800 */
21335 #define HASH_SR_NBWP_3                      (0x08UL << HASH_SR_NBWP_Pos)            /*!< 0x00001000 */
21336 
21337 
21338 /******************************************************************************/
21339 /*                                                                            */
21340 /*                      Inter-integrated Circuit Interface (I2C)              */
21341 /*                                                                            */
21342 /******************************************************************************/
21343 /*******************  Bit definition for I2C_CR1 register  *******************/
21344 #define I2C_CR1_PE_Pos                      (0U)
21345 #define I2C_CR1_PE_Msk                      (0x1UL << I2C_CR1_PE_Pos)               /*!< 0x00000001 */
21346 #define I2C_CR1_PE                          I2C_CR1_PE_Msk                          /*!< Peripheral enable */
21347 #define I2C_CR1_TXIE_Pos                    (1U)
21348 #define I2C_CR1_TXIE_Msk                    (0x1UL << I2C_CR1_TXIE_Pos)             /*!< 0x00000002 */
21349 #define I2C_CR1_TXIE                        I2C_CR1_TXIE_Msk                        /*!< TX interrupt enable */
21350 #define I2C_CR1_RXIE_Pos                    (2U)
21351 #define I2C_CR1_RXIE_Msk                    (0x1UL << I2C_CR1_RXIE_Pos)             /*!< 0x00000004 */
21352 #define I2C_CR1_RXIE                        I2C_CR1_RXIE_Msk                        /*!< RX interrupt enable */
21353 #define I2C_CR1_ADDRIE_Pos                  (3U)
21354 #define I2C_CR1_ADDRIE_Msk                  (0x1UL << I2C_CR1_ADDRIE_Pos)           /*!< 0x00000008 */
21355 #define I2C_CR1_ADDRIE                      I2C_CR1_ADDRIE_Msk                      /*!< Address match interrupt enable */
21356 #define I2C_CR1_NACKIE_Pos                  (4U)
21357 #define I2C_CR1_NACKIE_Msk                  (0x1UL << I2C_CR1_NACKIE_Pos)           /*!< 0x00000010 */
21358 #define I2C_CR1_NACKIE                      I2C_CR1_NACKIE_Msk                      /*!< NACK received interrupt enable */
21359 #define I2C_CR1_STOPIE_Pos                  (5U)
21360 #define I2C_CR1_STOPIE_Msk                  (0x1UL << I2C_CR1_STOPIE_Pos)           /*!< 0x00000020 */
21361 #define I2C_CR1_STOPIE                      I2C_CR1_STOPIE_Msk                      /*!< STOP detection interrupt enable */
21362 #define I2C_CR1_TCIE_Pos                    (6U)
21363 #define I2C_CR1_TCIE_Msk                    (0x1UL << I2C_CR1_TCIE_Pos)             /*!< 0x00000040 */
21364 #define I2C_CR1_TCIE                        I2C_CR1_TCIE_Msk                        /*!< Transfer complete interrupt enable */
21365 #define I2C_CR1_ERRIE_Pos                   (7U)
21366 #define I2C_CR1_ERRIE_Msk                   (0x1UL << I2C_CR1_ERRIE_Pos)            /*!< 0x00000080 */
21367 #define I2C_CR1_ERRIE                       I2C_CR1_ERRIE_Msk                       /*!< Errors interrupt enable */
21368 #define I2C_CR1_DNF_Pos                     (8U)
21369 #define I2C_CR1_DNF_Msk                     (0xFUL << I2C_CR1_DNF_Pos)              /*!< 0x00000F00 */
21370 #define I2C_CR1_DNF                         I2C_CR1_DNF_Msk                         /*!< Digital noise filter */
21371 #define I2C_CR1_ANFOFF_Pos                  (12U)
21372 #define I2C_CR1_ANFOFF_Msk                  (0x1UL << I2C_CR1_ANFOFF_Pos)           /*!< 0x00001000 */
21373 #define I2C_CR1_ANFOFF                      I2C_CR1_ANFOFF_Msk                      /*!< Analog noise filter OFF */
21374 #define I2C_CR1_SWRST_Pos                   (13U)
21375 #define I2C_CR1_SWRST_Msk                   (0x1UL << I2C_CR1_SWRST_Pos)            /*!< 0x00002000 */
21376 #define I2C_CR1_SWRST                       I2C_CR1_SWRST_Msk                       /*!< Software reset */
21377 #define I2C_CR1_TXDMAEN_Pos                 (14U)
21378 #define I2C_CR1_TXDMAEN_Msk                 (0x1UL << I2C_CR1_TXDMAEN_Pos)          /*!< 0x00004000 */
21379 #define I2C_CR1_TXDMAEN                     I2C_CR1_TXDMAEN_Msk                     /*!< DMA transmission requests enable */
21380 #define I2C_CR1_RXDMAEN_Pos                 (15U)
21381 #define I2C_CR1_RXDMAEN_Msk                 (0x1UL << I2C_CR1_RXDMAEN_Pos)          /*!< 0x00008000 */
21382 #define I2C_CR1_RXDMAEN                     I2C_CR1_RXDMAEN_Msk                     /*!< DMA reception requests enable */
21383 #define I2C_CR1_SBC_Pos                     (16U)
21384 #define I2C_CR1_SBC_Msk                     (0x1UL << I2C_CR1_SBC_Pos)              /*!< 0x00010000 */
21385 #define I2C_CR1_SBC                         I2C_CR1_SBC_Msk                         /*!< Slave byte control */
21386 #define I2C_CR1_NOSTRETCH_Pos               (17U)
21387 #define I2C_CR1_NOSTRETCH_Msk               (0x1UL << I2C_CR1_NOSTRETCH_Pos)        /*!< 0x00020000 */
21388 #define I2C_CR1_NOSTRETCH                   I2C_CR1_NOSTRETCH_Msk                   /*!< Clock stretching disable */
21389 #define I2C_CR1_WUPEN_Pos                   (18U)
21390 #define I2C_CR1_WUPEN_Msk                   (0x1UL << I2C_CR1_WUPEN_Pos)            /*!< 0x00040000 */
21391 #define I2C_CR1_WUPEN                       I2C_CR1_WUPEN_Msk                       /*!< Wakeup from STOP enable */
21392 #define I2C_CR1_GCEN_Pos                    (19U)
21393 #define I2C_CR1_GCEN_Msk                    (0x1UL << I2C_CR1_GCEN_Pos)             /*!< 0x00080000 */
21394 #define I2C_CR1_GCEN                        I2C_CR1_GCEN_Msk                        /*!< General call enable */
21395 #define I2C_CR1_SMBHEN_Pos                  (20U)
21396 #define I2C_CR1_SMBHEN_Msk                  (0x1UL << I2C_CR1_SMBHEN_Pos)           /*!< 0x00100000 */
21397 #define I2C_CR1_SMBHEN                      I2C_CR1_SMBHEN_Msk                      /*!< SMBus host address enable */
21398 #define I2C_CR1_SMBDEN_Pos                  (21U)
21399 #define I2C_CR1_SMBDEN_Msk                  (0x1UL << I2C_CR1_SMBDEN_Pos)           /*!< 0x00200000 */
21400 #define I2C_CR1_SMBDEN                      I2C_CR1_SMBDEN_Msk                      /*!< SMBus device default address enable */
21401 #define I2C_CR1_ALERTEN_Pos                 (22U)
21402 #define I2C_CR1_ALERTEN_Msk                 (0x1UL << I2C_CR1_ALERTEN_Pos)          /*!< 0x00400000 */
21403 #define I2C_CR1_ALERTEN                     I2C_CR1_ALERTEN_Msk                     /*!< SMBus alert enable */
21404 #define I2C_CR1_PECEN_Pos                   (23U)
21405 #define I2C_CR1_PECEN_Msk                   (0x1UL << I2C_CR1_PECEN_Pos)            /*!< 0x00800000 */
21406 #define I2C_CR1_PECEN                       I2C_CR1_PECEN_Msk                       /*!< PEC enable */
21407 #define I2C_CR1_FMP_Pos                     (24U)
21408 #define I2C_CR1_FMP_Msk                     (0x1UL << I2C_CR1_FMP_Pos)            /*!< 0x01000000 */
21409 #define I2C_CR1_FMP                         I2C_CR1_FMP_Msk                       /*!< Fast-mode Plus 20 mA drive enable */
21410 #define I2C_CR1_ADDRACLR_Pos                (30U)
21411 #define I2C_CR1_ADDRACLR_Msk                (0x1UL << I2C_CR1_ADDRACLR_Pos)         /*!< 0x40000000 */
21412 #define I2C_CR1_ADDRACLR                    I2C_CR1_ADDRACLR_Msk                    /*!< ADDRACLR enable */
21413 #define I2C_CR1_STOPFACLR_Pos               (31U)
21414 #define I2C_CR1_STOPFACLR_Msk               (0x1UL << I2C_CR1_STOPFACLR_Pos)        /*!< 0x80000000 */
21415 #define I2C_CR1_STOPFACLR                   I2C_CR1_STOPFACLR_Msk                   /*!< STOPFACLR enable */
21416 
21417 /******************  Bit definition for I2C_CR2 register  ********************/
21418 #define I2C_CR2_SADD_Pos                    (0U)
21419 #define I2C_CR2_SADD_Msk                    (0x3FFUL << I2C_CR2_SADD_Pos)           /*!< 0x000003FF */
21420 #define I2C_CR2_SADD                        I2C_CR2_SADD_Msk                        /*!< Slave address (master mode) */
21421 #define I2C_CR2_RD_WRN_Pos                  (10U)
21422 #define I2C_CR2_RD_WRN_Msk                  (0x1UL << I2C_CR2_RD_WRN_Pos)           /*!< 0x00000400 */
21423 #define I2C_CR2_RD_WRN                      I2C_CR2_RD_WRN_Msk                      /*!< Transfer direction (master mode) */
21424 #define I2C_CR2_ADD10_Pos                   (11U)
21425 #define I2C_CR2_ADD10_Msk                   (0x1UL << I2C_CR2_ADD10_Pos)            /*!< 0x00000800 */
21426 #define I2C_CR2_ADD10                       I2C_CR2_ADD10_Msk                       /*!< 10-bit addressing mode (master mode) */
21427 #define I2C_CR2_HEAD10R_Pos                 (12U)
21428 #define I2C_CR2_HEAD10R_Msk                 (0x1UL << I2C_CR2_HEAD10R_Pos)          /*!< 0x00001000 */
21429 #define I2C_CR2_HEAD10R                     I2C_CR2_HEAD10R_Msk                     /*!< 10-bit address header only read direction (master mode) */
21430 #define I2C_CR2_START_Pos                   (13U)
21431 #define I2C_CR2_START_Msk                   (0x1UL << I2C_CR2_START_Pos)            /*!< 0x00002000 */
21432 #define I2C_CR2_START                       I2C_CR2_START_Msk                       /*!< START generation */
21433 #define I2C_CR2_STOP_Pos                    (14U)
21434 #define I2C_CR2_STOP_Msk                    (0x1UL << I2C_CR2_STOP_Pos)             /*!< 0x00004000 */
21435 #define I2C_CR2_STOP                        I2C_CR2_STOP_Msk                        /*!< STOP generation (master mode) */
21436 #define I2C_CR2_NACK_Pos                    (15U)
21437 #define I2C_CR2_NACK_Msk                    (0x1UL << I2C_CR2_NACK_Pos)             /*!< 0x00008000 */
21438 #define I2C_CR2_NACK                        I2C_CR2_NACK_Msk                        /*!< NACK generation (slave mode) */
21439 #define I2C_CR2_NBYTES_Pos                  (16U)
21440 #define I2C_CR2_NBYTES_Msk                  (0xFFUL << I2C_CR2_NBYTES_Pos)          /*!< 0x00FF0000 */
21441 #define I2C_CR2_NBYTES                      I2C_CR2_NBYTES_Msk                      /*!< Number of bytes */
21442 #define I2C_CR2_RELOAD_Pos                  (24U)
21443 #define I2C_CR2_RELOAD_Msk                  (0x1UL << I2C_CR2_RELOAD_Pos)           /*!< 0x01000000 */
21444 #define I2C_CR2_RELOAD                      I2C_CR2_RELOAD_Msk                      /*!< NBYTES reload mode */
21445 #define I2C_CR2_AUTOEND_Pos                 (25U)
21446 #define I2C_CR2_AUTOEND_Msk                 (0x1UL << I2C_CR2_AUTOEND_Pos)          /*!< 0x02000000 */
21447 #define I2C_CR2_AUTOEND                     I2C_CR2_AUTOEND_Msk                     /*!< Automatic end mode (master mode) */
21448 #define I2C_CR2_PECBYTE_Pos                 (26U)
21449 #define I2C_CR2_PECBYTE_Msk                 (0x1UL << I2C_CR2_PECBYTE_Pos)          /*!< 0x04000000 */
21450 #define I2C_CR2_PECBYTE                     I2C_CR2_PECBYTE_Msk                     /*!< Packet error checking byte */
21451 
21452 /*******************  Bit definition for I2C_OAR1 register  ******************/
21453 #define I2C_OAR1_OA1_Pos                    (0U)
21454 #define I2C_OAR1_OA1_Msk                    (0x3FFUL << I2C_OAR1_OA1_Pos)           /*!< 0x000003FF */
21455 #define I2C_OAR1_OA1                        I2C_OAR1_OA1_Msk                        /*!< Interface own address 1 */
21456 #define I2C_OAR1_OA1MODE_Pos                (10U)
21457 #define I2C_OAR1_OA1MODE_Msk                (0x1UL << I2C_OAR1_OA1MODE_Pos)         /*!< 0x00000400 */
21458 #define I2C_OAR1_OA1MODE                    I2C_OAR1_OA1MODE_Msk                    /*!< Own address 1 10-bit mode */
21459 #define I2C_OAR1_OA1EN_Pos                  (15U)
21460 #define I2C_OAR1_OA1EN_Msk                  (0x1UL << I2C_OAR1_OA1EN_Pos)           /*!< 0x00008000 */
21461 #define I2C_OAR1_OA1EN                      I2C_OAR1_OA1EN_Msk                      /*!< Own address 1 enable */
21462 
21463 /*******************  Bit definition for I2C_OAR2 register  ******************/
21464 #define I2C_OAR2_OA2_Pos                    (1U)
21465 #define I2C_OAR2_OA2_Msk                    (0x7FUL << I2C_OAR2_OA2_Pos)            /*!< 0x000000FE */
21466 #define I2C_OAR2_OA2                        I2C_OAR2_OA2_Msk                        /*!< Interface own address 2 */
21467 #define I2C_OAR2_OA2MSK_Pos                 (8U)
21468 #define I2C_OAR2_OA2MSK_Msk                 (0x7UL << I2C_OAR2_OA2MSK_Pos)          /*!< 0x00000700 */
21469 #define I2C_OAR2_OA2MSK                     I2C_OAR2_OA2MSK_Msk                     /*!< Own address 2 masks */
21470 #define I2C_OAR2_OA2NOMASK                  (0x00000000UL)                          /*!< No mask                                        */
21471 #define I2C_OAR2_OA2MASK01_Pos              (8U)
21472 #define I2C_OAR2_OA2MASK01_Msk              (0x1UL << I2C_OAR2_OA2MASK01_Pos)       /*!< 0x00000100 */
21473 #define I2C_OAR2_OA2MASK01                  I2C_OAR2_OA2MASK01_Msk                  /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
21474 #define I2C_OAR2_OA2MASK02_Pos              (9U)
21475 #define I2C_OAR2_OA2MASK02_Msk              (0x1UL << I2C_OAR2_OA2MASK02_Pos)       /*!< 0x00000200 */
21476 #define I2C_OAR2_OA2MASK02                  I2C_OAR2_OA2MASK02_Msk                  /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
21477 #define I2C_OAR2_OA2MASK03_Pos              (8U)
21478 #define I2C_OAR2_OA2MASK03_Msk              (0x3UL << I2C_OAR2_OA2MASK03_Pos)       /*!< 0x00000300 */
21479 #define I2C_OAR2_OA2MASK03                  I2C_OAR2_OA2MASK03_Msk                  /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
21480 #define I2C_OAR2_OA2MASK04_Pos              (10U)
21481 #define I2C_OAR2_OA2MASK04_Msk              (0x1UL << I2C_OAR2_OA2MASK04_Pos)       /*!< 0x00000400 */
21482 #define I2C_OAR2_OA2MASK04                  I2C_OAR2_OA2MASK04_Msk                  /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
21483 #define I2C_OAR2_OA2MASK05_Pos              (8U)
21484 #define I2C_OAR2_OA2MASK05_Msk              (0x5UL << I2C_OAR2_OA2MASK05_Pos)       /*!< 0x00000500 */
21485 #define I2C_OAR2_OA2MASK05                  I2C_OAR2_OA2MASK05_Msk                  /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
21486 #define I2C_OAR2_OA2MASK06_Pos              (9U)
21487 #define I2C_OAR2_OA2MASK06_Msk              (0x3UL << I2C_OAR2_OA2MASK06_Pos)       /*!< 0x00000600 */
21488 #define I2C_OAR2_OA2MASK06                  I2C_OAR2_OA2MASK06_Msk                  /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
21489 #define I2C_OAR2_OA2MASK07_Pos              (8U)
21490 #define I2C_OAR2_OA2MASK07_Msk              (0x7UL << I2C_OAR2_OA2MASK07_Pos)       /*!< 0x00000700 */
21491 #define I2C_OAR2_OA2MASK07                  I2C_OAR2_OA2MASK07_Msk                  /*!< OA2[7:1] is masked, No comparison is done      */
21492 #define I2C_OAR2_OA2EN_Pos                  (15U)
21493 #define I2C_OAR2_OA2EN_Msk                  (0x1UL << I2C_OAR2_OA2EN_Pos)           /*!< 0x00008000 */
21494 #define I2C_OAR2_OA2EN                      I2C_OAR2_OA2EN_Msk                      /*!< Own address 2 enable */
21495 
21496 /*******************  Bit definition for I2C_TIMINGR register *******************/
21497 #define I2C_TIMINGR_SCLL_Pos                (0U)
21498 #define I2C_TIMINGR_SCLL_Msk                (0xFFUL << I2C_TIMINGR_SCLL_Pos)        /*!< 0x000000FF */
21499 #define I2C_TIMINGR_SCLL                    I2C_TIMINGR_SCLL_Msk                    /*!< SCL low period (master mode) */
21500 #define I2C_TIMINGR_SCLH_Pos                (8U)
21501 #define I2C_TIMINGR_SCLH_Msk                (0xFFUL << I2C_TIMINGR_SCLH_Pos)        /*!< 0x0000FF00 */
21502 #define I2C_TIMINGR_SCLH                    I2C_TIMINGR_SCLH_Msk                    /*!< SCL high period (master mode) */
21503 #define I2C_TIMINGR_SDADEL_Pos              (16U)
21504 #define I2C_TIMINGR_SDADEL_Msk              (0xFUL << I2C_TIMINGR_SDADEL_Pos)       /*!< 0x000F0000 */
21505 #define I2C_TIMINGR_SDADEL                  I2C_TIMINGR_SDADEL_Msk                  /*!< Data hold time */
21506 #define I2C_TIMINGR_SCLDEL_Pos              (20U)
21507 #define I2C_TIMINGR_SCLDEL_Msk              (0xFUL << I2C_TIMINGR_SCLDEL_Pos)       /*!< 0x00F00000 */
21508 #define I2C_TIMINGR_SCLDEL                  I2C_TIMINGR_SCLDEL_Msk                  /*!< Data setup time */
21509 #define I2C_TIMINGR_PRESC_Pos               (28U)
21510 #define I2C_TIMINGR_PRESC_Msk               (0xFUL << I2C_TIMINGR_PRESC_Pos)        /*!< 0xF0000000 */
21511 #define I2C_TIMINGR_PRESC                   I2C_TIMINGR_PRESC_Msk                   /*!< Timings prescaler */
21512 
21513 /******************* Bit definition for I2C_TIMEOUTR register *******************/
21514 #define I2C_TIMEOUTR_TIMEOUTA_Pos           (0U)
21515 #define I2C_TIMEOUTR_TIMEOUTA_Msk           (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)  /*!< 0x00000FFF */
21516 #define I2C_TIMEOUTR_TIMEOUTA               I2C_TIMEOUTR_TIMEOUTA_Msk               /*!< Bus timeout A */
21517 #define I2C_TIMEOUTR_TIDLE_Pos              (12U)
21518 #define I2C_TIMEOUTR_TIDLE_Msk              (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)       /*!< 0x00001000 */
21519 #define I2C_TIMEOUTR_TIDLE                  I2C_TIMEOUTR_TIDLE_Msk                  /*!< Idle clock timeout detection */
21520 #define I2C_TIMEOUTR_TIMOUTEN_Pos           (15U)
21521 #define I2C_TIMEOUTR_TIMOUTEN_Msk           (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)    /*!< 0x00008000 */
21522 #define I2C_TIMEOUTR_TIMOUTEN               I2C_TIMEOUTR_TIMOUTEN_Msk               /*!< Clock timeout enable */
21523 #define I2C_TIMEOUTR_TIMEOUTB_Pos           (16U)
21524 #define I2C_TIMEOUTR_TIMEOUTB_Msk           (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)  /*!< 0x0FFF0000 */
21525 #define I2C_TIMEOUTR_TIMEOUTB               I2C_TIMEOUTR_TIMEOUTB_Msk               /*!< Bus timeout B*/
21526 #define I2C_TIMEOUTR_TEXTEN_Pos             (31U)
21527 #define I2C_TIMEOUTR_TEXTEN_Msk             (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)      /*!< 0x80000000 */
21528 #define I2C_TIMEOUTR_TEXTEN                 I2C_TIMEOUTR_TEXTEN_Msk                 /*!< Extended clock timeout enable */
21529 
21530 /******************  Bit definition for I2C_ISR register  *********************/
21531 #define I2C_ISR_TXE_Pos                     (0U)
21532 #define I2C_ISR_TXE_Msk                     (0x1UL << I2C_ISR_TXE_Pos)              /*!< 0x00000001 */
21533 #define I2C_ISR_TXE                         I2C_ISR_TXE_Msk                         /*!< Transmit data register empty */
21534 #define I2C_ISR_TXIS_Pos                    (1U)
21535 #define I2C_ISR_TXIS_Msk                    (0x1UL << I2C_ISR_TXIS_Pos)             /*!< 0x00000002 */
21536 #define I2C_ISR_TXIS                        I2C_ISR_TXIS_Msk                        /*!< Transmit interrupt status */
21537 #define I2C_ISR_RXNE_Pos                    (2U)
21538 #define I2C_ISR_RXNE_Msk                    (0x1UL << I2C_ISR_RXNE_Pos)             /*!< 0x00000004 */
21539 #define I2C_ISR_RXNE                        I2C_ISR_RXNE_Msk                        /*!< Receive data register not empty */
21540 #define I2C_ISR_ADDR_Pos                    (3U)
21541 #define I2C_ISR_ADDR_Msk                    (0x1UL << I2C_ISR_ADDR_Pos)             /*!< 0x00000008 */
21542 #define I2C_ISR_ADDR                        I2C_ISR_ADDR_Msk                        /*!< Address matched (slave mode)*/
21543 #define I2C_ISR_NACKF_Pos                   (4U)
21544 #define I2C_ISR_NACKF_Msk                   (0x1UL << I2C_ISR_NACKF_Pos)            /*!< 0x00000010 */
21545 #define I2C_ISR_NACKF                       I2C_ISR_NACKF_Msk                       /*!< NACK received flag */
21546 #define I2C_ISR_STOPF_Pos                   (5U)
21547 #define I2C_ISR_STOPF_Msk                   (0x1UL << I2C_ISR_STOPF_Pos)            /*!< 0x00000020 */
21548 #define I2C_ISR_STOPF                       I2C_ISR_STOPF_Msk                       /*!< STOP detection flag */
21549 #define I2C_ISR_TC_Pos                      (6U)
21550 #define I2C_ISR_TC_Msk                      (0x1UL << I2C_ISR_TC_Pos)               /*!< 0x00000040 */
21551 #define I2C_ISR_TC                          I2C_ISR_TC_Msk                          /*!< Transfer complete (master mode) */
21552 #define I2C_ISR_TCR_Pos                     (7U)
21553 #define I2C_ISR_TCR_Msk                     (0x1UL << I2C_ISR_TCR_Pos)              /*!< 0x00000080 */
21554 #define I2C_ISR_TCR                         I2C_ISR_TCR_Msk                         /*!< Transfer complete reload */
21555 #define I2C_ISR_BERR_Pos                    (8U)
21556 #define I2C_ISR_BERR_Msk                    (0x1UL << I2C_ISR_BERR_Pos)             /*!< 0x00000100 */
21557 #define I2C_ISR_BERR                        I2C_ISR_BERR_Msk                        /*!< Bus error */
21558 #define I2C_ISR_ARLO_Pos                    (9U)
21559 #define I2C_ISR_ARLO_Msk                    (0x1UL << I2C_ISR_ARLO_Pos)             /*!< 0x00000200 */
21560 #define I2C_ISR_ARLO                        I2C_ISR_ARLO_Msk                        /*!< Arbitration lost */
21561 #define I2C_ISR_OVR_Pos                     (10U)
21562 #define I2C_ISR_OVR_Msk                     (0x1UL << I2C_ISR_OVR_Pos)              /*!< 0x00000400 */
21563 #define I2C_ISR_OVR                         I2C_ISR_OVR_Msk                         /*!< Overrun/Underrun */
21564 #define I2C_ISR_PECERR_Pos                  (11U)
21565 #define I2C_ISR_PECERR_Msk                  (0x1UL << I2C_ISR_PECERR_Pos)           /*!< 0x00000800 */
21566 #define I2C_ISR_PECERR                      I2C_ISR_PECERR_Msk                      /*!< PEC error in reception */
21567 #define I2C_ISR_TIMEOUT_Pos                 (12U)
21568 #define I2C_ISR_TIMEOUT_Msk                 (0x1UL << I2C_ISR_TIMEOUT_Pos)          /*!< 0x00001000 */
21569 #define I2C_ISR_TIMEOUT                     I2C_ISR_TIMEOUT_Msk                     /*!< Timeout or Tlow detection flag */
21570 #define I2C_ISR_ALERT_Pos                   (13U)
21571 #define I2C_ISR_ALERT_Msk                   (0x1UL << I2C_ISR_ALERT_Pos)            /*!< 0x00002000 */
21572 #define I2C_ISR_ALERT                       I2C_ISR_ALERT_Msk                       /*!< SMBus alert */
21573 #define I2C_ISR_BUSY_Pos                    (15U)
21574 #define I2C_ISR_BUSY_Msk                    (0x1UL << I2C_ISR_BUSY_Pos)             /*!< 0x00008000 */
21575 #define I2C_ISR_BUSY                        I2C_ISR_BUSY_Msk                        /*!< Bus busy */
21576 #define I2C_ISR_DIR_Pos                     (16U)
21577 #define I2C_ISR_DIR_Msk                     (0x1UL << I2C_ISR_DIR_Pos)              /*!< 0x00010000 */
21578 #define I2C_ISR_DIR                         I2C_ISR_DIR_Msk                         /*!< Transfer direction (slave mode) */
21579 #define I2C_ISR_ADDCODE_Pos                 (17U)
21580 #define I2C_ISR_ADDCODE_Msk                 (0x7FUL << I2C_ISR_ADDCODE_Pos)         /*!< 0x00FE0000 */
21581 #define I2C_ISR_ADDCODE                     I2C_ISR_ADDCODE_Msk                     /*!< Address match code (slave mode) */
21582 
21583 /******************  Bit definition for I2C_ICR register  *********************/
21584 #define I2C_ICR_ADDRCF_Pos                  (3U)
21585 #define I2C_ICR_ADDRCF_Msk                  (0x1UL << I2C_ICR_ADDRCF_Pos)           /*!< 0x00000008 */
21586 #define I2C_ICR_ADDRCF                      I2C_ICR_ADDRCF_Msk                      /*!< Address matched clear flag */
21587 #define I2C_ICR_NACKCF_Pos                  (4U)
21588 #define I2C_ICR_NACKCF_Msk                  (0x1UL << I2C_ICR_NACKCF_Pos)           /*!< 0x00000010 */
21589 #define I2C_ICR_NACKCF                      I2C_ICR_NACKCF_Msk                      /*!< NACK clear flag */
21590 #define I2C_ICR_STOPCF_Pos                  (5U)
21591 #define I2C_ICR_STOPCF_Msk                  (0x1UL << I2C_ICR_STOPCF_Pos)           /*!< 0x00000020 */
21592 #define I2C_ICR_STOPCF                      I2C_ICR_STOPCF_Msk                      /*!< STOP detection clear flag */
21593 #define I2C_ICR_BERRCF_Pos                  (8U)
21594 #define I2C_ICR_BERRCF_Msk                  (0x1UL << I2C_ICR_BERRCF_Pos)           /*!< 0x00000100 */
21595 #define I2C_ICR_BERRCF                      I2C_ICR_BERRCF_Msk                      /*!< Bus error clear flag */
21596 #define I2C_ICR_ARLOCF_Pos                  (9U)
21597 #define I2C_ICR_ARLOCF_Msk                  (0x1UL << I2C_ICR_ARLOCF_Pos)           /*!< 0x00000200 */
21598 #define I2C_ICR_ARLOCF                      I2C_ICR_ARLOCF_Msk                      /*!< Arbitration lost clear flag */
21599 #define I2C_ICR_OVRCF_Pos                   (10U)
21600 #define I2C_ICR_OVRCF_Msk                   (0x1UL << I2C_ICR_OVRCF_Pos)            /*!< 0x00000400 */
21601 #define I2C_ICR_OVRCF                       I2C_ICR_OVRCF_Msk                       /*!< Overrun/Underrun clear flag */
21602 #define I2C_ICR_PECCF_Pos                   (11U)
21603 #define I2C_ICR_PECCF_Msk                   (0x1UL << I2C_ICR_PECCF_Pos)            /*!< 0x00000800 */
21604 #define I2C_ICR_PECCF                       I2C_ICR_PECCF_Msk                       /*!< PAC error clear flag */
21605 #define I2C_ICR_TIMOUTCF_Pos                (12U)
21606 #define I2C_ICR_TIMOUTCF_Msk                (0x1UL << I2C_ICR_TIMOUTCF_Pos)         /*!< 0x00001000 */
21607 #define I2C_ICR_TIMOUTCF                    I2C_ICR_TIMOUTCF_Msk                    /*!< Timeout clear flag */
21608 #define I2C_ICR_ALERTCF_Pos                 (13U)
21609 #define I2C_ICR_ALERTCF_Msk                 (0x1UL << I2C_ICR_ALERTCF_Pos)          /*!< 0x00002000 */
21610 #define I2C_ICR_ALERTCF                     I2C_ICR_ALERTCF_Msk                     /*!< Alert clear flag */
21611 
21612 /******************  Bit definition for I2C_PECR register  *********************/
21613 #define I2C_PECR_PEC_Pos                    (0U)
21614 #define I2C_PECR_PEC_Msk                    (0xFFUL << I2C_PECR_PEC_Pos)            /*!< 0x000000FF */
21615 #define I2C_PECR_PEC                        I2C_PECR_PEC_Msk                        /*!< PEC register */
21616 
21617 /******************  Bit definition for I2C_RXDR register  *********************/
21618 #define I2C_RXDR_RXDATA_Pos                 (0U)
21619 #define I2C_RXDR_RXDATA_Msk                 (0xFFUL << I2C_RXDR_RXDATA_Pos)         /*!< 0x000000FF */
21620 #define I2C_RXDR_RXDATA                     I2C_RXDR_RXDATA_Msk                     /*!< 8-bit receive data */
21621 
21622 /******************  Bit definition for I2C_TXDR register  *********************/
21623 #define I2C_TXDR_TXDATA_Pos                 (0U)
21624 #define I2C_TXDR_TXDATA_Msk                 (0xFFUL << I2C_TXDR_TXDATA_Pos)         /*!< 0x000000FF */
21625 #define I2C_TXDR_TXDATA                     I2C_TXDR_TXDATA_Msk                     /*!< 8-bit transmit data */
21626 
21627 
21628 /******************************************************************************/
21629 /*                                                                            */
21630 /*             Improved Inter-integrated Circuit Interface (I3C)              */
21631 /*                                                                            */
21632 /******************************************************************************/
21633 /*******************  Bit definition for I3C_CR register  *********************/
21634 #define I3C_CR_DCNT_Pos                     (0U)
21635 #define I3C_CR_DCNT_Msk                     (0xFFFFUL << I3C_CR_DCNT_Pos)           /*!< 0x0000FFFF */
21636 #define I3C_CR_DCNT                         I3C_CR_DCNT_Msk                         /*!< Data Byte Count */
21637 #define I3C_CR_RNW_Pos                      (16U)
21638 #define I3C_CR_RNW_Msk                      (0x1UL << I3C_CR_RNW_Pos)               /*!< 0x00010000 */
21639 #define I3C_CR_RNW                          I3C_CR_RNW_Msk                          /*!< Read Not Write */
21640 #define I3C_CR_CCC_Pos                      (16U)
21641 #define I3C_CR_CCC_Msk                      (0xFFUL << I3C_CR_CCC_Pos)              /*!< 0x00FF0000 */
21642 #define I3C_CR_CCC                          I3C_CR_CCC_Msk                          /*!< 8-Bit CCC code */
21643 #define I3C_CR_ADD_Pos                      (17U)
21644 #define I3C_CR_ADD_Msk                      (0x7FUL << I3C_CR_ADD_Pos)              /*!< 0x00FE0000 */
21645 #define I3C_CR_ADD                          I3C_CR_ADD_Msk                          /*!< Target Address */
21646 #define I3C_CR_MTYPE_Pos                    (27U)
21647 #define I3C_CR_MTYPE_Msk                    (0xFUL << I3C_CR_MTYPE_Pos)             /*!< 0xF8000000 */
21648 #define I3C_CR_MTYPE                        I3C_CR_MTYPE_Msk                        /*!< Message Type */
21649 #define I3C_CR_MTYPE_0                      (0x1UL << I3C_CR_MTYPE_Pos)             /*!< 0x08000000 */
21650 #define I3C_CR_MTYPE_1                      (0x2UL << I3C_CR_MTYPE_Pos)             /*!< 0x10000000 */
21651 #define I3C_CR_MTYPE_2                      (0x4UL << I3C_CR_MTYPE_Pos)             /*!< 0x20000000 */
21652 #define I3C_CR_MTYPE_3                      (0x8UL << I3C_CR_MTYPE_Pos)             /*!< 0x40000000 */
21653 #define I3C_CR_MEND_Pos                     (31U)
21654 #define I3C_CR_MEND_Msk                     (0x1UL << I3C_CR_MEND_Pos)              /*!< 0x80000000 */
21655 #define I3C_CR_MEND                         I3C_CR_MEND_Msk                         /*!< Message End */
21656 
21657 /*******************  Bit definition for I3C_CFGR register  *******************/
21658 #define I3C_CFGR_EN_Pos                     (0U)
21659 #define I3C_CFGR_EN_Msk                     (0x1UL << I3C_CFGR_EN_Pos)              /*!< 0x00000001 */
21660 #define I3C_CFGR_EN                         I3C_CFGR_EN_Msk                         /*!< Peripheral Enable */
21661 #define I3C_CFGR_CRINIT_Pos                 (1U)
21662 #define I3C_CFGR_CRINIT_Msk                 (0x1UL << I3C_CFGR_CRINIT_Pos)          /*!< 0x00000002 */
21663 #define I3C_CFGR_CRINIT                     I3C_CFGR_CRINIT_Msk                     /*!< Peripheral Init mode (Target/Controller) */
21664 #define I3C_CFGR_NOARBH_Pos                 (2U)
21665 #define I3C_CFGR_NOARBH_Msk                 (0x1UL << I3C_CFGR_NOARBH_Pos)          /*!< 0x00000004 */
21666 #define I3C_CFGR_NOARBH                     I3C_CFGR_NOARBH_Msk                     /*!< No Arbitration Header (7'h7E)*/
21667 #define I3C_CFGR_RSTPTRN_Pos                (3U)
21668 #define I3C_CFGR_RSTPTRN_Msk                (0x1UL << I3C_CFGR_RSTPTRN_Pos)         /*!< 0x00000008 */
21669 #define I3C_CFGR_RSTPTRN                    I3C_CFGR_RSTPTRN_Msk                    /*!< Reset Pattern enable */
21670 #define I3C_CFGR_EXITPTRN_Pos               (4U)
21671 #define I3C_CFGR_EXITPTRN_Msk               (0x1UL << I3C_CFGR_EXITPTRN_Pos)        /*!< 0x00000010 */
21672 #define I3C_CFGR_EXITPTRN                   I3C_CFGR_EXITPTRN_Msk                   /*!< Exit Pattern enable */
21673 #define I3C_CFGR_HKSDAEN_Pos                (5U)
21674 #define I3C_CFGR_HKSDAEN_Msk                (0x1UL << I3C_CFGR_HKSDAEN_Pos)         /*!< 0x00000020 */
21675 #define I3C_CFGR_HKSDAEN                    I3C_CFGR_HKSDAEN_Msk                    /*!< High-Keeper on SDA Enable */
21676 #define I3C_CFGR_HJACK_Pos                  (7U)
21677 #define I3C_CFGR_HJACK_Msk                  (0x1UL << I3C_CFGR_HJACK_Pos)           /*!< 0x00000080 */
21678 #define I3C_CFGR_HJACK                      I3C_CFGR_HJACK_Msk                      /*!< Hot Join Acknowledgment */
21679 #define I3C_CFGR_RXDMAEN_Pos                (8U)
21680 #define I3C_CFGR_RXDMAEN_Msk                (0x1UL << I3C_CFGR_RXDMAEN_Pos)         /*!< 0x00000100 */
21681 #define I3C_CFGR_RXDMAEN                    I3C_CFGR_RXDMAEN_Msk                    /*!< RX FIFO DMA mode Enable */
21682 #define I3C_CFGR_RXFLUSH_Pos                (9U)
21683 #define I3C_CFGR_RXFLUSH_Msk                (0x1UL << I3C_CFGR_RXFLUSH_Pos)         /*!< 0x00000200 */
21684 #define I3C_CFGR_RXFLUSH                    I3C_CFGR_RXFLUSH_Msk                    /*!< RX FIFO Flush */
21685 #define I3C_CFGR_RXTHRES_Pos                (10U)
21686 #define I3C_CFGR_RXTHRES_Msk                (0x1UL << I3C_CFGR_RXTHRES_Pos)         /*!< 0x00000400 */
21687 #define I3C_CFGR_RXTHRES                    I3C_CFGR_RXTHRES_Msk                    /*!< RX FIFO Threshold */
21688 #define I3C_CFGR_TXDMAEN_Pos                (12U)
21689 #define I3C_CFGR_TXDMAEN_Msk                (0x1UL << I3C_CFGR_TXDMAEN_Pos)         /*!< 0x00001000 */
21690 #define I3C_CFGR_TXDMAEN                    I3C_CFGR_TXDMAEN_Msk                    /*!< TX FIFO DMA mode Enable */
21691 #define I3C_CFGR_TXFLUSH_Pos                (13U)
21692 #define I3C_CFGR_TXFLUSH_Msk                (0x1UL << I3C_CFGR_TXFLUSH_Pos)         /*!< 0x00002000 */
21693 #define I3C_CFGR_TXFLUSH                    I3C_CFGR_TXFLUSH_Msk                    /*!< TX FIFO Flush */
21694 #define I3C_CFGR_TXTHRES_Pos                (14U)
21695 #define I3C_CFGR_TXTHRES_Msk                (0x1UL << I3C_CFGR_TXTHRES_Pos)         /*!< 0x00004000 */
21696 #define I3C_CFGR_TXTHRES                    I3C_CFGR_TXTHRES_Msk                    /*!< TX FIFO Threshold */
21697 #define I3C_CFGR_SDMAEN_Pos                 (16U)
21698 #define I3C_CFGR_SDMAEN_Msk                 (0x1UL << I3C_CFGR_SDMAEN_Pos)          /*!< 0x00010000 */
21699 #define I3C_CFGR_SDMAEN                     I3C_CFGR_SDMAEN_Msk                     /*!< Status FIFO DMA mode Enable */
21700 #define I3C_CFGR_SFLUSH_Pos                 (17U)
21701 #define I3C_CFGR_SFLUSH_Msk                 (0x1UL << I3C_CFGR_SFLUSH_Pos)          /*!< 0x00020000 */
21702 #define I3C_CFGR_SFLUSH                     I3C_CFGR_SFLUSH_Msk                     /*!< Status FIFO Flush */
21703 #define I3C_CFGR_SMODE_Pos                  (18U)
21704 #define I3C_CFGR_SMODE_Msk                  (0x1UL << I3C_CFGR_SMODE_Pos)           /*!< 0x00040000 */
21705 #define I3C_CFGR_SMODE                      I3C_CFGR_SMODE_Msk                      /*!< Status FIFO mode Enable */
21706 #define I3C_CFGR_TMODE_Pos                  (19U)
21707 #define I3C_CFGR_TMODE_Msk                  (0x1UL << I3C_CFGR_TMODE_Pos)           /*!< 0x00080000 */
21708 #define I3C_CFGR_TMODE                      I3C_CFGR_TMODE_Msk                      /*!< Control FIFO mode Enable */
21709 #define I3C_CFGR_CDMAEN_Pos                 (20U)
21710 #define I3C_CFGR_CDMAEN_Msk                 (0x1UL << I3C_CFGR_CDMAEN_Pos)          /*!< 0x00100000 */
21711 #define I3C_CFGR_CDMAEN                     I3C_CFGR_CDMAEN_Msk                     /*!< Control FIFO DMA mode Enable */
21712 #define I3C_CFGR_CFLUSH_Pos                 (21U)
21713 #define I3C_CFGR_CFLUSH_Msk                 (0x1UL << I3C_CFGR_CFLUSH_Pos)          /*!< 0x00200000 */
21714 #define I3C_CFGR_CFLUSH                     I3C_CFGR_CFLUSH_Msk                     /*!< Control FIFO Flush */
21715 #define I3C_CFGR_TSFSET_Pos                 (30U)
21716 #define I3C_CFGR_TSFSET_Msk                 (0x1UL << I3C_CFGR_TSFSET_Pos)          /*!< 0x40000000 */
21717 #define I3C_CFGR_TSFSET                     I3C_CFGR_TSFSET_Msk                     /*!< Transfer Set */
21718 
21719 /*******************  Bit definition for I3C_RDR register  ********************/
21720 #define I3C_RDR_RDB0_Pos                    (0U)
21721 #define I3C_RDR_RDB0_Msk                    (0xFFUL << I3C_RDR_RDB0_Pos)            /*!< 0x000000FF */
21722 #define I3C_RDR_RDB0                        I3C_RDR_RDB0_Msk                        /*!< Receive Data Byte */
21723 
21724 /******************  Bit definition for I3C_RDWR register  ********************/
21725 #define I3C_RDWR_RDBx_Pos                   (0U)
21726 #define I3C_RDWR_RDBx_Msk                   (0xFFFFFFFFUL << I3C_RDWR_RDBx_Pos)     /*!< 0xFFFFFFFF */
21727 #define I3C_RDWR_RDBx                       I3C_RDWR_RDBx_Msk                       /*!< Receive Data Byte, full double word */
21728 #define I3C_RDWR_RDB0_Pos                   (0U)
21729 #define I3C_RDWR_RDB0_Msk                   (0xFFUL << I3C_RDWR_RDB0_Pos)           /*!< 0x000000FF */
21730 #define I3C_RDWR_RDB0                       I3C_RDWR_RDB0_Msk                       /*!< Receive Data Byte 0 */
21731 #define I3C_RDWR_RDB1_Pos                   (8U)
21732 #define I3C_RDWR_RDB1_Msk                   (0xFFUL << I3C_RDWR_RDB1_Pos)           /*!< 0x0000FF00 */
21733 #define I3C_RDWR_RDB1                       I3C_RDWR_RDB1_Msk                       /*!< Receive Data Byte 1 */
21734 #define I3C_RDWR_RDB2_Pos                   (16U)
21735 #define I3C_RDWR_RDB2_Msk                   (0xFFUL << I3C_RDWR_RDB2_Pos)           /*!< 0x00FF0000 */
21736 #define I3C_RDWR_RDB2                       I3C_RDWR_RDB2_Msk                       /*!< Receive Data Byte 2 */
21737 #define I3C_RDWR_RDB3_Pos                   (24U)
21738 #define I3C_RDWR_RDB3_Msk                   (0xFFUL << I3C_RDWR_RDB3_Pos)           /*!< 0xFF000000 */
21739 #define I3C_RDWR_RDB3                       I3C_RDWR_RDB3_Msk                       /*!< Receive Data Byte 3 */
21740 
21741 /*******************  Bit definition for I3C_TDR register  ********************/
21742 #define I3C_TDR_TDB0_Pos                    (0U)
21743 #define I3C_TDR_TDB0_Msk                    (0xFFUL << I3C_TDR_TDB0_Pos)            /*!< 0x000000FF */
21744 #define I3C_TDR_TDB0                        I3C_TDR_TDB0_Msk                        /*!< Transmit Data Byte */
21745 
21746 /******************  Bit definition for I3C_TDWR register  ********************/
21747 #define I3C_TDWR_TDBx_Pos                   (0U)
21748 #define I3C_TDWR_TDBx_Msk                   (0xFFFFFFFFUL << I3C_TDWR_TDBx_Pos)     /*!< 0xFFFFFFFF */
21749 #define I3C_TDWR_TDBx                       I3C_TDWR_TDBx_Msk                       /*!< Transmit Data Byte, full double word */
21750 #define I3C_TDWR_TDB0_Pos                   (0U)
21751 #define I3C_TDWR_TDB0_Msk                   (0xFFUL << I3C_TDWR_TDB0_Pos)           /*!< 0x000000FF */
21752 #define I3C_TDWR_TDB0                       I3C_TDWR_TDB0_Msk                       /*!< Transmit Data Byte 0 */
21753 #define I3C_TDWR_TDB1_Pos                   (8U)
21754 #define I3C_TDWR_TDB1_Msk                   (0xFFUL << I3C_TDWR_TDB1_Pos)           /*!< 0x0000FF00 */
21755 #define I3C_TDWR_TDB1                       I3C_TDWR_TDB1_Msk                       /*!< Transmit Data Byte 1 */
21756 #define I3C_TDWR_TDB2_Pos                   (16U)
21757 #define I3C_TDWR_TDB2_Msk                   (0xFFUL << I3C_TDWR_TDB2_Pos)           /*!< 0x00FF0000 */
21758 #define I3C_TDWR_TDB2                       I3C_TDWR_TDB2_Msk                       /*!< Transmit Data Byte 2 */
21759 #define I3C_TDWR_TDB3_Pos                   (24U)
21760 #define I3C_TDWR_TDB3_Msk                   (0xFFUL << I3C_TDWR_TDB3_Pos)           /*!< 0xFF000000 */
21761 #define I3C_TDWR_TDB3                       I3C_TDWR_TDB3_Msk                       /*!< Transmit Data Byte 3 */
21762 
21763 /*******************  Bit definition for I3C_IBIDR register  ******************/
21764 #define I3C_IBIDR_IBIDBx_Pos                (0U)
21765 #define I3C_IBIDR_IBIDBx_Msk                (0xFFFFFFFFUL << I3C_IBIDR_IBIDBx_Pos)  /*!< 0xFFFFFFFF */
21766 #define I3C_IBIDR_IBIDBx                    I3C_IBIDR_IBIDBx_Msk                    /*!< IBI Data Byte, full double word */
21767 #define I3C_IBIDR_IBIDB0_Pos                (0U)
21768 #define I3C_IBIDR_IBIDB0_Msk                (0xFFUL << I3C_IBIDR_IBIDB0_Pos)        /*!< 0x000000FF */
21769 #define I3C_IBIDR_IBIDB0                    I3C_IBIDR_IBIDB0_Msk                    /*!< IBI Data Byte 0 */
21770 #define I3C_IBIDR_IBIDB1_Pos                (8U)
21771 #define I3C_IBIDR_IBIDB1_Msk                (0xFFUL << I3C_IBIDR_IBIDB1_Pos)        /*!< 0x0000FF00 */
21772 #define I3C_IBIDR_IBIDB1                    I3C_IBIDR_IBIDB1_Msk                    /*!< IBI Data Byte 1 */
21773 #define I3C_IBIDR_IBIDB2_Pos                (16U)
21774 #define I3C_IBIDR_IBIDB2_Msk                (0xFFUL << I3C_IBIDR_IBIDB2_Pos)        /*!< 0x00FF0000 */
21775 #define I3C_IBIDR_IBIDB2                    I3C_IBIDR_IBIDB2_Msk                    /*!< IBI Data Byte 2 */
21776 #define I3C_IBIDR_IBIDB3_Pos                (24U)
21777 #define I3C_IBIDR_IBIDB3_Msk                (0xFFUL << I3C_IBIDR_IBIDB3_Pos)        /*!< 0xFF000000 */
21778 #define I3C_IBIDR_IBIDB3                    I3C_IBIDR_IBIDB3_Msk                    /*!< IBI Data Byte 3 */
21779 
21780 /******************  Bit definition for I3C_TGTTDR register  ******************/
21781 #define I3C_TGTTDR_TGTTDCNT_Pos             (0U)
21782 #define I3C_TGTTDR_TGTTDCNT_Msk             (0xFFFFUL << I3C_TGTTDR_TGTTDCNT_Pos)   /*!< 0x0000FFFF */
21783 #define I3C_TGTTDR_TGTTDCNT                 I3C_TGTTDR_TGTTDCNT_Msk                 /*!< Target Transmit Data Counter */
21784 #define I3C_TGTTDR_PRELOAD_Pos              (16U)
21785 #define I3C_TGTTDR_PRELOAD_Msk              (0x1UL << I3C_TGTTDR_PRELOAD_Pos)       /*!< 0x00010000 */
21786 #define I3C_TGTTDR_PRELOAD                  I3C_TGTTDR_PRELOAD_Msk                  /*!< Transmit FIFO Preload Enable/Status */
21787 
21788 /*******************  Bit definition for I3C_SR register  *********************/
21789 #define I3C_SR_XDCNT_Pos                    (0U)
21790 #define I3C_SR_XDCNT_Msk                    (0xFFFFUL << I3C_SR_XDCNT_Pos)          /*!< 0x0000FFFF */
21791 #define I3C_SR_XDCNT                        I3C_SR_XDCNT_Msk                        /*!< Transfer Data Byte Count status */
21792 #define I3C_SR_ABT_Pos                      (17U)
21793 #define I3C_SR_ABT_Msk                      (0x1UL << I3C_SR_ABT_Pos)               /*!< 0x00020000 */
21794 #define I3C_SR_ABT                          I3C_SR_ABT_Msk                          /*!< Target Abort Indication */
21795 #define I3C_SR_DIR_Pos                      (18U)
21796 #define I3C_SR_DIR_Msk                      (0x1UL << I3C_SR_DIR_Pos)               /*!< 0x00040000 */
21797 #define I3C_SR_DIR                          I3C_SR_DIR_Msk                          /*!< Message Direction */
21798 #define I3C_SR_MID_Pos                      (24U)
21799 #define I3C_SR_MID_Msk                      (0xFFUL << I3C_SR_MID_Pos)              /*!< 0xFF000000 */
21800 #define I3C_SR_MID                          I3C_SR_MID_Msk                          /*!< Message Identifier */
21801 
21802 /*******************  Bit definition for I3C_SER register  ********************/
21803 #define I3C_SER_CODERR_Pos                  (0U)
21804 #define I3C_SER_CODERR_Msk                  (0xFUL << I3C_SER_CODERR_Pos)           /*!< 0x0000000F */
21805 #define I3C_SER_CODERR                      I3C_SER_CODERR_Msk                      /*!< Protocol Error Code */
21806 #define I3C_SER_CODERR_0                    (0x1UL << I3C_SER_CODERR_Pos)           /*!< 0x00000001 */
21807 #define I3C_SER_CODERR_1                    (0x2UL << I3C_SER_CODERR_Pos)           /*!< 0x00000002 */
21808 #define I3C_SER_CODERR_2                    (0x4UL << I3C_SER_CODERR_Pos)           /*!< 0x00000004 */
21809 #define I3C_SER_CODERR_3                    (0x8UL << I3C_SER_CODERR_Pos)           /*!< 0x00000008 */
21810 #define I3C_SER_PERR_Pos                    (4U)
21811 #define I3C_SER_PERR_Msk                    (0x1UL << I3C_SER_PERR_Pos)             /*!< 0x00000010 */
21812 #define I3C_SER_PERR                        I3C_SER_PERR_Msk                        /*!< Protocol Error */
21813 #define I3C_SER_STALL_Pos                   (5U)
21814 #define I3C_SER_STALL_Msk                   (0x1UL << I3C_SER_STALL_Pos)            /*!< 0x00000020 */
21815 #define I3C_SER_STALL                       I3C_SER_STALL_Msk                       /*!< SCL Stall Error */
21816 #define I3C_SER_DOVR_Pos                    (6U)
21817 #define I3C_SER_DOVR_Msk                    (0x1UL << I3C_SER_DOVR_Pos)             /*!< 0x00000040 */
21818 #define I3C_SER_DOVR                        I3C_SER_DOVR_Msk                        /*!< RX/TX FIFO Overrun */
21819 #define I3C_SER_COVR_Pos                    (7U)
21820 #define I3C_SER_COVR_Msk                    (0x1UL << I3C_SER_COVR_Pos)             /*!< 0x00000080 */
21821 #define I3C_SER_COVR                        I3C_SER_COVR_Msk                        /*!< Status/Control FIFO Overrun */
21822 #define I3C_SER_ANACK_Pos                   (8U)
21823 #define I3C_SER_ANACK_Msk                   (0x1UL << I3C_SER_ANACK_Pos)            /*!< 0x00000100 */
21824 #define I3C_SER_ANACK                       I3C_SER_ANACK_Msk                       /*!< Address Not Acknowledged */
21825 #define I3C_SER_DNACK_Pos                   (9U)
21826 #define I3C_SER_DNACK_Msk                   (0x1UL << I3C_SER_DNACK_Pos)            /*!< 0x00000200 */
21827 #define I3C_SER_DNACK                       I3C_SER_DNACK_Msk                       /*!< Data Not Acknowledged */
21828 #define I3C_SER_DERR_Pos                    (10U)
21829 #define I3C_SER_DERR_Msk                    (0x1UL << I3C_SER_DERR_Pos)             /*!< 0x00000400 */
21830 #define I3C_SER_DERR                        I3C_SER_DERR_Msk                        /*!< Data Error during the controller-role hand-off procedure */
21831 
21832 /*******************  Bit definition for I3C_RMR register  ********************/
21833 #define I3C_RMR_IBIRDCNT_Pos                (0U)
21834 #define I3C_RMR_IBIRDCNT_Msk                (0x7UL << I3C_RMR_IBIRDCNT_Pos)         /*!< 0x00000007 */
21835 #define I3C_RMR_IBIRDCNT                    I3C_RMR_IBIRDCNT_Msk                    /*!< Data Count when reading IBI data */
21836 #define I3C_RMR_RCODE_Pos                   (8U)
21837 #define I3C_RMR_RCODE_Msk                   (0xFFUL << I3C_RMR_RCODE_Pos)           /*!< 0x0000FF00 */
21838 #define I3C_RMR_RCODE                       I3C_RMR_RCODE_Msk                       /*!< CCC code of received command */
21839 #define I3C_RMR_RADD_Pos                    (17U)
21840 #define I3C_RMR_RADD_Msk                    (0x7FUL << I3C_RMR_RADD_Pos)            /*!< 0x00FE0000 */
21841 #define I3C_RMR_RADD                        I3C_RMR_RADD_Msk                        /*!< Target Address Received during accepted IBI or Controller-role request */
21842 
21843 /*******************  Bit definition for I3C_EVR register  ********************/
21844 #define I3C_EVR_CFEF_Pos                    (0U)
21845 #define I3C_EVR_CFEF_Msk                    (0x1UL << I3C_EVR_CFEF_Pos)             /*!< 0x00000001 */
21846 #define I3C_EVR_CFEF                        I3C_EVR_CFEF_Msk                        /*!< Control FIFO Empty Flag */
21847 #define I3C_EVR_TXFEF_Pos                   (1U)
21848 #define I3C_EVR_TXFEF_Msk                   (0x1UL << I3C_EVR_TXFEF_Pos)            /*!< 0x00000002 */
21849 #define I3C_EVR_TXFEF                       I3C_EVR_TXFEF_Msk                       /*!< TX FIFO Empty Flag */
21850 #define I3C_EVR_CFNFF_Pos                   (2U)
21851 #define I3C_EVR_CFNFF_Msk                   (0x1UL << I3C_EVR_CFNFF_Pos)            /*!< 0x00000004 */
21852 #define I3C_EVR_CFNFF                       I3C_EVR_CFNFF_Msk                       /*!< Control FIFO Not Full Flag */
21853 #define I3C_EVR_SFNEF_Pos                   (3U)
21854 #define I3C_EVR_SFNEF_Msk                   (0x1UL << I3C_EVR_SFNEF_Pos)            /*!< 0x00000008 */
21855 #define I3C_EVR_SFNEF                       I3C_EVR_SFNEF_Msk                       /*!< Status FIFO Not Empty Flag */
21856 #define I3C_EVR_TXFNFF_Pos                  (4U)
21857 #define I3C_EVR_TXFNFF_Msk                  (0x1UL << I3C_EVR_TXFNFF_Pos)           /*!< 0x00000010 */
21858 #define I3C_EVR_TXFNFF                      I3C_EVR_TXFNFF_Msk                      /*!< TX FIFO Not Full Flag */
21859 #define I3C_EVR_RXFNEF_Pos                  (5U)
21860 #define I3C_EVR_RXFNEF_Msk                  (0x1UL << I3C_EVR_RXFNEF_Pos)           /*!< 0x00000020 */
21861 #define I3C_EVR_RXFNEF                      I3C_EVR_RXFNEF_Msk                      /*!< RX FIFO Not Empty Flag */
21862 #define I3C_EVR_TXLASTF_Pos                 (6U)
21863 #define I3C_EVR_TXLASTF_Msk                 (0x1UL << I3C_EVR_TXLASTF_Pos)          /*!< 0x00000040 */
21864 #define I3C_EVR_TXLASTF                     I3C_EVR_TXLASTF_Msk                     /*!< Last TX byte available in FIFO */
21865 #define I3C_EVR_RXLASTF_Pos                 (7U)
21866 #define I3C_EVR_RXLASTF_Msk                 (0x1UL << I3C_EVR_RXLASTF_Pos)          /*!< 0x00000080 */
21867 #define I3C_EVR_RXLASTF                     I3C_EVR_RXLASTF_Msk                     /*!< Last RX byte read from FIFO */
21868 #define I3C_EVR_FCF_Pos                     (9U)
21869 #define I3C_EVR_FCF_Msk                     (0x1UL << I3C_EVR_FCF_Pos)              /*!< 0x00000200 */
21870 #define I3C_EVR_FCF                         I3C_EVR_FCF_Msk                         /*!< Frame Complete Flag */
21871 #define I3C_EVR_RXTGTENDF_Pos               (10U)
21872 #define I3C_EVR_RXTGTENDF_Msk               (0x1UL << I3C_EVR_RXTGTENDF_Pos)        /*!< 0x00000400 */
21873 #define I3C_EVR_RXTGTENDF                   I3C_EVR_RXTGTENDF_Msk                   /*!< Reception Target End Flag */
21874 #define I3C_EVR_ERRF_Pos                    (11U)
21875 #define I3C_EVR_ERRF_Msk                    (0x1UL << I3C_EVR_ERRF_Pos)             /*!< 0x00000800 */
21876 #define I3C_EVR_ERRF                        I3C_EVR_ERRF_Msk                        /*!< Error Flag */
21877 #define I3C_EVR_IBIF_Pos                    (15U)
21878 #define I3C_EVR_IBIF_Msk                    (0x1UL << I3C_EVR_IBIF_Pos)             /*!< 0x00008000 */
21879 #define I3C_EVR_IBIF                        I3C_EVR_IBIF_Msk                        /*!< IBI Flag */
21880 #define I3C_EVR_IBIENDF_Pos                 (16U)
21881 #define I3C_EVR_IBIENDF_Msk                 (0x1UL << I3C_EVR_IBIENDF_Pos)          /*!< 0x00010000 */
21882 #define I3C_EVR_IBIENDF                     I3C_EVR_IBIENDF_Msk                     /*!< IBI End Flag */
21883 #define I3C_EVR_CRF_Pos                     (17U)
21884 #define I3C_EVR_CRF_Msk                     (0x1UL << I3C_EVR_CRF_Pos)              /*!< 0x00020000 */
21885 #define I3C_EVR_CRF                         I3C_EVR_CRF_Msk                         /*!< Controller-role Request Flag */
21886 #define I3C_EVR_CRUPDF_Pos                  (18U)
21887 #define I3C_EVR_CRUPDF_Msk                  (0x1UL << I3C_EVR_CRUPDF_Pos)           /*!< 0x00040000 */
21888 #define I3C_EVR_CRUPDF                      I3C_EVR_CRUPDF_Msk                      /*!< Controller-role Update Flag */
21889 #define I3C_EVR_HJF_Pos                     (19U)
21890 #define I3C_EVR_HJF_Msk                     (0x1UL << I3C_EVR_HJF_Pos)              /*!< 0x00080000 */
21891 #define I3C_EVR_HJF                         I3C_EVR_HJF_Msk                         /*!< Hot Join Flag */
21892 #define I3C_EVR_WKPF_Pos                    (21U)
21893 #define I3C_EVR_WKPF_Msk                    (0x1UL << I3C_EVR_WKPF_Pos)             /*!< 0x00200000 */
21894 #define I3C_EVR_WKPF                        I3C_EVR_WKPF_Msk                        /*!< Wake Up Flag */
21895 #define I3C_EVR_GETF_Pos                    (22U)
21896 #define I3C_EVR_GETF_Msk                    (0x1UL << I3C_EVR_GETF_Pos)             /*!< 0x00400000 */
21897 #define I3C_EVR_GETF                        I3C_EVR_GETF_Msk                        /*!< Get type CCC received Flag */
21898 #define I3C_EVR_STAF_Pos                    (23U)
21899 #define I3C_EVR_STAF_Msk                    (0x1UL << I3C_EVR_STAF_Pos)             /*!< 0x00800000 */
21900 #define I3C_EVR_STAF                        I3C_EVR_STAF_Msk                        /*!< Get Status Flag */
21901 #define I3C_EVR_DAUPDF_Pos                  (24U)
21902 #define I3C_EVR_DAUPDF_Msk                  (0x1UL << I3C_EVR_DAUPDF_Pos)           /*!< 0x01000000 */
21903 #define I3C_EVR_DAUPDF                      I3C_EVR_DAUPDF_Msk                      /*!< Dynamic Address Update Flag */
21904 #define I3C_EVR_MWLUPDF_Pos                 (25U)
21905 #define I3C_EVR_MWLUPDF_Msk                 (0x1UL << I3C_EVR_MWLUPDF_Pos)          /*!< 0x02000000 */
21906 #define I3C_EVR_MWLUPDF                     I3C_EVR_MWLUPDF_Msk                     /*!< Max Write Length Update Flag */
21907 #define I3C_EVR_MRLUPDF_Pos                 (26U)
21908 #define I3C_EVR_MRLUPDF_Msk                 (0x1UL << I3C_EVR_MRLUPDF_Pos)          /*!< 0x04000000 */
21909 #define I3C_EVR_MRLUPDF                     I3C_EVR_MRLUPDF_Msk                     /*!< Max Read Length Update Flag */
21910 #define I3C_EVR_RSTF_Pos                    (27U)
21911 #define I3C_EVR_RSTF_Msk                    (0x1UL << I3C_EVR_RSTF_Pos)             /*!< 0x08000000 */
21912 #define I3C_EVR_RSTF                        I3C_EVR_RSTF_Msk                        /*!< Reset Flag, due to Reset pattern received */
21913 #define I3C_EVR_ASUPDF_Pos                  (28U)
21914 #define I3C_EVR_ASUPDF_Msk                  (0x1UL << I3C_EVR_ASUPDF_Pos)           /*!< 0x10000000 */
21915 #define I3C_EVR_ASUPDF                      I3C_EVR_ASUPDF_Msk                      /*!< Activity State Flag */
21916 #define I3C_EVR_INTUPDF_Pos                 (29U)
21917 #define I3C_EVR_INTUPDF_Msk                 (0x1UL << I3C_EVR_INTUPDF_Pos)          /*!< 0x20000000 */
21918 #define I3C_EVR_INTUPDF                     I3C_EVR_INTUPDF_Msk                     /*!< Interrupt Update Flag */
21919 #define I3C_EVR_DEFF_Pos                    (30U)
21920 #define I3C_EVR_DEFF_Msk                    (0x1UL << I3C_EVR_DEFF_Pos)             /*!< 0x40000000 */
21921 #define I3C_EVR_DEFF                        I3C_EVR_DEFF_Msk                        /*!< List of Targets Command Received Flag */
21922 #define I3C_EVR_GRPF_Pos                    (31U)
21923 #define I3C_EVR_GRPF_Msk                    (0x1UL << I3C_EVR_GRPF_Pos)             /*!< 0x80000000 */
21924 #define I3C_EVR_GRPF                        I3C_EVR_GRPF_Msk                        /*!< List of Group Addresses Command Received Flag */
21925 
21926 /*******************  Bit definition for I3C_IER register  ********************/
21927 #define I3C_IER_CFNFIE_Pos                  (2U)
21928 #define I3C_IER_CFNFIE_Msk                  (0x1UL << I3C_IER_CFNFIE_Pos)           /*!< 0x00000004 */
21929 #define I3C_IER_CFNFIE                      I3C_IER_CFNFIE_Msk                      /*!< Control FIFO Not Full Interrupt Enable */
21930 #define I3C_IER_SFNEIE_Pos                  (3U)
21931 #define I3C_IER_SFNEIE_Msk                  (0x1UL << I3C_IER_SFNEIE_Pos)           /*!< 0x00000008 */
21932 #define I3C_IER_SFNEIE                      I3C_IER_SFNEIE_Msk                      /*!< Status FIFO Not Empty Interrupt Enable */
21933 #define I3C_IER_TXFNFIE_Pos                 (4U)
21934 #define I3C_IER_TXFNFIE_Msk                 (0x1UL << I3C_IER_TXFNFIE_Pos)          /*!< 0x00000010 */
21935 #define I3C_IER_TXFNFIE                     I3C_IER_TXFNFIE_Msk                     /*!< TX FIFO Not Full Interrupt Enable */
21936 #define I3C_IER_RXFNEIE_Pos                 (5U)
21937 #define I3C_IER_RXFNEIE_Msk                 (0x1UL << I3C_IER_RXFNEIE_Pos)          /*!< 0x00000020 */
21938 #define I3C_IER_RXFNEIE                     I3C_IER_RXFNEIE_Msk                     /*!< RX FIFO Not Empty Interrupt Enable */
21939 #define I3C_IER_FCIE_Pos                    (9U)
21940 #define I3C_IER_FCIE_Msk                    (0x1UL << I3C_IER_FCIE_Pos)             /*!< 0x00000200 */
21941 #define I3C_IER_FCIE                        I3C_IER_FCIE_Msk                        /*!< Frame Complete Interrupt Enable */
21942 #define I3C_IER_RXTGTENDIE_Pos              (10U)
21943 #define I3C_IER_RXTGTENDIE_Msk              (0x1UL << I3C_IER_RXTGTENDIE_Pos)       /*!< 0x00000400 */
21944 #define I3C_IER_RXTGTENDIE                  I3C_IER_RXTGTENDIE_Msk                  /*!< Reception Target End Interrupt Enable */
21945 #define I3C_IER_ERRIE_Pos                   (11U)
21946 #define I3C_IER_ERRIE_Msk                   (0x1UL << I3C_IER_ERRIE_Pos)            /*!< 0x00000800 */
21947 #define I3C_IER_ERRIE                       I3C_IER_ERRIE_Msk                       /*!< Error Interrupt Enable */
21948 #define I3C_IER_IBIIE_Pos                   (15U)
21949 #define I3C_IER_IBIIE_Msk                   (0x1UL << I3C_IER_IBIIE_Pos)            /*!< 0x00008000 */
21950 #define I3C_IER_IBIIE                       I3C_IER_IBIIE_Msk                       /*!< IBI Interrupt Enable */
21951 #define I3C_IER_IBIENDIE_Pos                (16U)
21952 #define I3C_IER_IBIENDIE_Msk                (0x1UL << I3C_IER_IBIENDIE_Pos)         /*!< 0x00010000 */
21953 #define I3C_IER_IBIENDIE                    I3C_IER_IBIENDIE_Msk                    /*!< IBI End Interrupt Enable */
21954 #define I3C_IER_CRIE_Pos                    (17U)
21955 #define I3C_IER_CRIE_Msk                    (0x1UL << I3C_IER_CRIE_Pos)             /*!< 0x00020000 */
21956 #define I3C_IER_CRIE                        I3C_IER_CRIE_Msk                        /*!< Controller-role Interrupt Enable */
21957 #define I3C_IER_CRUPDIE_Pos                 (18U)
21958 #define I3C_IER_CRUPDIE_Msk                 (0x1UL << I3C_IER_CRUPDIE_Pos)          /*!< 0x00040000 */
21959 #define I3C_IER_CRUPDIE                     I3C_IER_CRUPDIE_Msk                     /*!< Controller-role Update Interrupt Enable */
21960 #define I3C_IER_HJIE_Pos                    (19U)
21961 #define I3C_IER_HJIE_Msk                    (0x1UL << I3C_IER_HJIE_Pos)             /*!< 0x00080000 */
21962 #define I3C_IER_HJIE                        I3C_IER_HJIE_Msk                        /*!< Hot Join Interrupt Enable */
21963 #define I3C_IER_WKPIE_Pos                   (21U)
21964 #define I3C_IER_WKPIE_Msk                   (0x1UL << I3C_IER_WKPIE_Pos)            /*!< 0x00200000 */
21965 #define I3C_IER_WKPIE                       I3C_IER_WKPIE_Msk                       /*!< Wake Up Interrupt Enable */
21966 #define I3C_IER_GETIE_Pos                   (22U)
21967 #define I3C_IER_GETIE_Msk                   (0x1UL << I3C_IER_GETIE_Pos)            /*!< 0x00400000 */
21968 #define I3C_IER_GETIE                       I3C_IER_GETIE_Msk                       /*!< Get type CCC received Interrupt Enable */
21969 #define I3C_IER_STAIE_Pos                   (23U)
21970 #define I3C_IER_STAIE_Msk                   (0x1UL << I3C_IER_STAIE_Pos)            /*!< 0x00800000 */
21971 #define I3C_IER_STAIE                       I3C_IER_STAIE_Msk                       /*!< Get Status Interrupt Enable */
21972 #define I3C_IER_DAUPDIE_Pos                 (24U)
21973 #define I3C_IER_DAUPDIE_Msk                 (0x1UL << I3C_IER_DAUPDIE_Pos)          /*!< 0x01000000 */
21974 #define I3C_IER_DAUPDIE                     I3C_IER_DAUPDIE_Msk                     /*!< Dynamic Address Update Interrupt Enable */
21975 #define I3C_IER_MWLUPDIE_Pos                (25U)
21976 #define I3C_IER_MWLUPDIE_Msk                (0x1UL << I3C_IER_MWLUPDIE_Pos)         /*!< 0x02000000 */
21977 #define I3C_IER_MWLUPDIE                    I3C_IER_MWLUPDIE_Msk                    /*!< Max Write Length Update Interrupt Enable */
21978 #define I3C_IER_MRLUPDIE_Pos                (26U)
21979 #define I3C_IER_MRLUPDIE_Msk                (0x1UL << I3C_IER_MRLUPDIE_Pos)         /*!< 0x04000000 */
21980 #define I3C_IER_MRLUPDIE                    I3C_IER_MRLUPDIE_Msk                    /*!< Max Read Length Update Interrupt Enable */
21981 #define I3C_IER_RSTIE_Pos                   (27U)
21982 #define I3C_IER_RSTIE_Msk                   (0x1UL << I3C_IER_RSTIE_Pos)            /*!< 0x08000000 */
21983 #define I3C_IER_RSTIE                       I3C_IER_RSTIE_Msk                       /*!< Reset Interrupt Enabled, due to Reset pattern received */
21984 #define I3C_IER_ASUPDIE_Pos                 (28U)
21985 #define I3C_IER_ASUPDIE_Msk                 (0x1UL << I3C_IER_ASUPDIE_Pos)          /*!< 0x10000000 */
21986 #define I3C_IER_ASUPDIE                     I3C_IER_ASUPDIE_Msk                     /*!< Activity State Interrupt Enable */
21987 #define I3C_IER_INTUPDIE_Pos                (29U)
21988 #define I3C_IER_INTUPDIE_Msk                (0x1UL << I3C_IER_INTUPDIE_Pos)         /*!< 0x20000000 */
21989 #define I3C_IER_INTUPDIE                    I3C_IER_INTUPDIE_Msk                    /*!< Interrupt Update Interrupt Enable */
21990 #define I3C_IER_DEFIE_Pos                   (30U)
21991 #define I3C_IER_DEFIE_Msk                   (0x1UL << I3C_IER_DEFIE_Pos)            /*!< 0x40000000 */
21992 #define I3C_IER_DEFIE                       I3C_IER_DEFIE_Msk                       /*!< List of Targets Command Received Interrupt Enable */
21993 #define I3C_IER_GRPIE_Pos                   (31U)
21994 #define I3C_IER_GRPIE_Msk                   (0x1UL << I3C_IER_GRPIE_Pos)            /*!< 0x80000000 */
21995 #define I3C_IER_GRPIE                       I3C_IER_GRPIE_Msk                       /*!< List of Group Addresses Command Received Interrupt Enable */
21996 
21997 /*******************  Bit definition for I3C_CEVR register  *******************/
21998 #define I3C_CEVR_CFCF_Pos                   (9U)
21999 #define I3C_CEVR_CFCF_Msk                   (0x1UL << I3C_CEVR_CFCF_Pos)            /*!< 0x00000200 */
22000 #define I3C_CEVR_CFCF                       I3C_CEVR_CFCF_Msk                       /*!< Frame Complete Clear Flag */
22001 #define I3C_CEVR_CRXTGTENDF_Pos             (10U)
22002 #define I3C_CEVR_CRXTGTENDF_Msk             (0x1UL << I3C_CEVR_CRXTGTENDF_Pos)      /*!< 0x00000400 */
22003 #define I3C_CEVR_CRXTGTENDF                 I3C_CEVR_CRXTGTENDF_Msk                 /*!< Reception Target End Clear Flag */
22004 #define I3C_CEVR_CERRF_Pos                  (11U)
22005 #define I3C_CEVR_CERRF_Msk                  (0x1UL << I3C_CEVR_CERRF_Pos)           /*!< 0x00000800 */
22006 #define I3C_CEVR_CERRF                      I3C_CEVR_CERRF_Msk                      /*!< Error Clear Flag */
22007 #define I3C_CEVR_CIBIF_Pos                  (15U)
22008 #define I3C_CEVR_CIBIF_Msk                  (0x1UL << I3C_CEVR_CIBIF_Pos)           /*!< 0x00008000 */
22009 #define I3C_CEVR_CIBIF                      I3C_CEVR_CIBIF_Msk                      /*!< IBI Clear Flag */
22010 #define I3C_CEVR_CIBIENDF_Pos               (16U)
22011 #define I3C_CEVR_CIBIENDF_Msk               (0x1UL << I3C_CEVR_CIBIENDF_Pos)        /*!< 0x00010000 */
22012 #define I3C_CEVR_CIBIENDF                   I3C_CEVR_CIBIENDF_Msk                   /*!< IBI End Clear Flag */
22013 #define I3C_CEVR_CCRF_Pos                   (17U)
22014 #define I3C_CEVR_CCRF_Msk                   (0x1UL << I3C_CEVR_CCRF_Pos)            /*!< 0x00020000 */
22015 #define I3C_CEVR_CCRF                       I3C_CEVR_CCRF_Msk                       /*!< Controller-role Clear Flag */
22016 #define I3C_CEVR_CCRUPDF_Pos                (18U)
22017 #define I3C_CEVR_CCRUPDF_Msk                (0x1UL << I3C_CEVR_CCRUPDF_Pos)         /*!< 0x00040000 */
22018 #define I3C_CEVR_CCRUPDF                    I3C_CEVR_CCRUPDF_Msk                    /*!< Controller-role Update Clear Flag */
22019 #define I3C_CEVR_CHJF_Pos                   (19U)
22020 #define I3C_CEVR_CHJF_Msk                   (0x1UL << I3C_CEVR_CHJF_Pos)            /*!< 0x00080000 */
22021 #define I3C_CEVR_CHJF                       I3C_CEVR_CHJF_Msk                       /*!< Hot Join Clear Flag */
22022 #define I3C_CEVR_CWKPF_Pos                  (21U)
22023 #define I3C_CEVR_CWKPF_Msk                  (0x1UL << I3C_CEVR_CWKPF_Pos)           /*!< 0x00200000 */
22024 #define I3C_CEVR_CWKPF                      I3C_CEVR_CWKPF_Msk                      /*!< Wake Up Clear Flag */
22025 #define I3C_CEVR_CGETF_Pos                  (22U)
22026 #define I3C_CEVR_CGETF_Msk                  (0x1UL << I3C_CEVR_CGETF_Pos)           /*!< 0x00400000 */
22027 #define I3C_CEVR_CGETF                      I3C_CEVR_CGETF_Msk                      /*!< Get type CCC received Clear Flag */
22028 #define I3C_CEVR_CSTAF_Pos                  (23U)
22029 #define I3C_CEVR_CSTAF_Msk                  (0x1UL << I3C_CEVR_CSTAF_Pos)           /*!< 0x00800000 */
22030 #define I3C_CEVR_CSTAF                      I3C_CEVR_CSTAF_Msk                      /*!< Get Status Clear Flag */
22031 #define I3C_CEVR_CDAUPDF_Pos                (24U)
22032 #define I3C_CEVR_CDAUPDF_Msk                (0x1UL << I3C_CEVR_CDAUPDF_Pos)         /*!< 0x01000000 */
22033 #define I3C_CEVR_CDAUPDF                    I3C_CEVR_CDAUPDF_Msk                    /*!< Dynamic Address Update Clear Flag */
22034 #define I3C_CEVR_CMWLUPDF_Pos               (25U)
22035 #define I3C_CEVR_CMWLUPDF_Msk               (0x1UL << I3C_CEVR_CMWLUPDF_Pos)        /*!< 0x02000000 */
22036 #define I3C_CEVR_CMWLUPDF                   I3C_CEVR_CMWLUPDF_Msk                   /*!< Max Write Length Update Clear Flag */
22037 #define I3C_CEVR_CMRLUPDF_Pos               (26U)
22038 #define I3C_CEVR_CMRLUPDF_Msk               (0x1UL << I3C_CEVR_CMRLUPDF_Pos)        /*!< 0x04000000 */
22039 #define I3C_CEVR_CMRLUPDF                   I3C_CEVR_CMRLUPDF_Msk                   /*!< Max Read Length Update Clear Flag */
22040 #define I3C_CEVR_CRSTF_Pos                  (27U)
22041 #define I3C_CEVR_CRSTF_Msk                  (0x1UL << I3C_CEVR_CRSTF_Pos)           /*!< 0x08000000 */
22042 #define I3C_CEVR_CRSTF                      I3C_CEVR_CRSTF_Msk                      /*!< Reset Flag, due to Reset pattern received */
22043 #define I3C_CEVR_CASUPDF_Pos                (28U)
22044 #define I3C_CEVR_CASUPDF_Msk                (0x1UL << I3C_CEVR_CASUPDF_Pos)         /*!< 0x10000000 */
22045 #define I3C_CEVR_CASUPDF                    I3C_CEVR_CASUPDF_Msk                    /*!< Activity State Clear Flag */
22046 #define I3C_CEVR_CINTUPDF_Pos               (29U)
22047 #define I3C_CEVR_CINTUPDF_Msk               (0x1UL << I3C_CEVR_CINTUPDF_Pos)        /*!< 0x20000000 */
22048 #define I3C_CEVR_CINTUPDF                   I3C_CEVR_CINTUPDF_Msk                   /*!< Interrupt Update Clear Flag */
22049 #define I3C_CEVR_CDEFF_Pos                  (30U)
22050 #define I3C_CEVR_CDEFF_Msk                  (0x1UL << I3C_CEVR_CDEFF_Pos)           /*!< 0x40000000 */
22051 #define I3C_CEVR_CDEFF                      I3C_CEVR_CDEFF_Msk                      /*!< List of Targets Command Received Clear Flag */
22052 #define I3C_CEVR_CGRPF_Pos                  (31U)
22053 #define I3C_CEVR_CGRPF_Msk                  (0x1UL << I3C_CEVR_CGRPF_Pos)           /*!< 0x80000000 */
22054 #define I3C_CEVR_CGRPF                      I3C_CEVR_CGRPF_Msk                      /*!< List of Group Addresses Command Received Clear Flag */
22055 
22056 /******************  Bit definition for I3C_DEVR0 register  *******************/
22057 #define I3C_DEVR0_DAVAL_Pos                 (0U)
22058 #define I3C_DEVR0_DAVAL_Msk                 (0x1UL << I3C_DEVR0_DAVAL_Pos)          /*!< 0x00000001 */
22059 #define I3C_DEVR0_DAVAL                     I3C_DEVR0_DAVAL_Msk                     /*!< Dynamic Address Validity */
22060 #define I3C_DEVR0_DA_Pos                    (1U)
22061 #define I3C_DEVR0_DA_Msk                    (0x7FUL << I3C_DEVR0_DA_Pos)            /*!< 0x000000FE */
22062 #define I3C_DEVR0_DA                        I3C_DEVR0_DA_Msk                        /*!< Own Target Device Address */
22063 #define I3C_DEVR0_IBIEN_Pos                 (16U)
22064 #define I3C_DEVR0_IBIEN_Msk                 (0x1UL << I3C_DEVR0_IBIEN_Pos)          /*!< 0x00010000 */
22065 #define I3C_DEVR0_IBIEN                     I3C_DEVR0_IBIEN_Msk                     /*!< IBI Enable */
22066 #define I3C_DEVR0_CREN_Pos                  (17U)
22067 #define I3C_DEVR0_CREN_Msk                  (0x1UL << I3C_DEVR0_CREN_Pos)           /*!< 0x00020000 */
22068 #define I3C_DEVR0_CREN                      I3C_DEVR0_CREN_Msk                      /*!< Controller-role Enable */
22069 #define I3C_DEVR0_HJEN_Pos                  (19U)
22070 #define I3C_DEVR0_HJEN_Msk                  (0x1UL << I3C_DEVR0_HJEN_Pos)           /*!< 0x00080000 */
22071 #define I3C_DEVR0_HJEN                      I3C_DEVR0_HJEN_Msk                      /*!< Hot Join Enable */
22072 #define I3C_DEVR0_AS_Pos                    (20U)
22073 #define I3C_DEVR0_AS_Msk                    (0x3UL << I3C_DEVR0_AS_Pos)             /*!< 0x00300000 */
22074 #define I3C_DEVR0_AS                        I3C_DEVR0_AS_Msk                        /*!< Activity State value update after ENTAx received */
22075 #define I3C_DEVR0_AS_0                      (0x1UL << I3C_DEVR0_AS_Pos)             /*!< 0x00100000 */
22076 #define I3C_DEVR0_AS_1                      (0x2UL << I3C_DEVR0_AS_Pos)             /*!< 0x00200000 */
22077 #define I3C_DEVR0_RSTACT_Pos                (22U)
22078 #define I3C_DEVR0_RSTACT_Msk                (0x3UL << I3C_DEVR0_RSTACT_Pos)         /*!< 0x00C000000 */
22079 #define I3C_DEVR0_RSTACT                    I3C_DEVR0_RSTACT_Msk                    /*!< Reset Action value update after RSTACT received */
22080 #define I3C_DEVR0_RSTACT_0                  (0x1UL << I3C_DEVR0_RSTACT_Pos)         /*!< 0x00400000 */
22081 #define I3C_DEVR0_RSTACT_1                  (0x2UL << I3C_DEVR0_RSTACT_Pos)         /*!< 0x00800000 */
22082 #define I3C_DEVR0_RSTVAL_Pos                (24U)
22083 #define I3C_DEVR0_RSTVAL_Msk                (0x1UL << I3C_DEVR0_RSTVAL_Pos)         /*!< 0x01000000 */
22084 #define I3C_DEVR0_RSTVAL                    I3C_DEVR0_RSTVAL_Msk                    /*!< Reset Action Valid */
22085 
22086 /******************  Bit definition for I3C_DEVRX register  *******************/
22087 #define I3C_DEVRX_DA_Pos                    (1U)
22088 #define I3C_DEVRX_DA_Msk                    (0x7FUL << I3C_DEVRX_DA_Pos)            /*!< 0x000000FE */
22089 #define I3C_DEVRX_DA                        I3C_DEVRX_DA_Msk                        /*!< Dynamic Address Target x */
22090 #define I3C_DEVRX_IBIACK_Pos                (16U)
22091 #define I3C_DEVRX_IBIACK_Msk                (0x1UL << I3C_DEVRX_IBIACK_Pos)         /*!< 0x00010000 */
22092 #define I3C_DEVRX_IBIACK                    I3C_DEVRX_IBIACK_Msk                    /*!< IBI Acknowledge from Target x */
22093 #define I3C_DEVRX_CRACK_Pos                 (17U)
22094 #define I3C_DEVRX_CRACK_Msk                 (0x1UL << I3C_DEVRX_CRACK_Pos)          /*!< 0x00020000 */
22095 #define I3C_DEVRX_CRACK                     I3C_DEVRX_CRACK_Msk                     /*!< Controller-role Acknowledge from Target x */
22096 #define I3C_DEVRX_IBIDEN_Pos                (18U)
22097 #define I3C_DEVRX_IBIDEN_Msk                (0x1UL << I3C_DEVRX_IBIDEN_Pos)         /*!< 0x00040000 */
22098 #define I3C_DEVRX_IBIDEN                    I3C_DEVRX_IBIDEN_Msk                    /*!< IBI Additional Data Enable */
22099 #define I3C_DEVRX_SUSP_Pos                  (19U)
22100 #define I3C_DEVRX_SUSP_Msk                  (0x1UL << I3C_DEVRX_SUSP_Pos)           /*!< 0x00080000 */
22101 #define I3C_DEVRX_SUSP                      I3C_DEVRX_SUSP_Msk                      /*!< Suspended Transfer */
22102 #define I3C_DEVRX_DIS_Pos                   (31U)
22103 #define I3C_DEVRX_DIS_Msk                   (0x1UL << I3C_DEVRX_DIS_Pos)            /*!< 0x80000000 */
22104 #define I3C_DEVRX_DIS                       I3C_DEVRX_DIS_Msk                       /*!< Disable Register access */
22105 
22106 /******************  Bit definition for I3C_MAXRLR register  ******************/
22107 #define I3C_MAXRLR_MRL_Pos                  (0U)
22108 #define I3C_MAXRLR_MRL_Msk                  (0xFFFFUL << I3C_MAXRLR_MRL_Pos)        /*!< 0x0000FFFF */
22109 #define I3C_MAXRLR_MRL                      I3C_MAXRLR_MRL_Msk                      /*!< Maximum Read Length */
22110 #define I3C_MAXRLR_IBIP_Pos                 (16U)
22111 #define I3C_MAXRLR_IBIP_Msk                 (0x7UL << I3C_MAXRLR_IBIP_Pos)          /*!< 0x00070000 */
22112 #define I3C_MAXRLR_IBIP                     I3C_MAXRLR_IBIP_Msk                     /*!< IBI Payload size */
22113 #define I3C_MAXRLR_IBIP_0                   (0x1UL << I3C_MAXRLR_IBIP_Pos)          /*!< 0x00010000 */
22114 #define I3C_MAXRLR_IBIP_1                   (0x2UL << I3C_MAXRLR_IBIP_Pos)          /*!< 0x00020000 */
22115 #define I3C_MAXRLR_IBIP_2                   (0x4UL << I3C_MAXRLR_IBIP_Pos)          /*!< 0x00040000 */
22116 
22117 /******************  Bit definition for I3C_MAXWLR register  ******************/
22118 #define I3C_MAXWLR_MWL_Pos                  (0U)
22119 #define I3C_MAXWLR_MWL_Msk                  (0xFFFFUL << I3C_MAXWLR_MWL_Pos)        /*!< 0x0000FFFF */
22120 #define I3C_MAXWLR_MWL                      I3C_MAXWLR_MWL_Msk                      /*!< Maximum Write Length */
22121 
22122 /****************  Bit definition for I3C_TIMINGR0 register  ******************/
22123 #define I3C_TIMINGR0_SCLL_PP_Pos            (0U)
22124 #define I3C_TIMINGR0_SCLL_PP_Msk            (0xFFUL << I3C_TIMINGR0_SCLL_PP_Pos)    /*!< 0x000000FF */
22125 #define I3C_TIMINGR0_SCLL_PP                I3C_TIMINGR0_SCLL_PP_Msk                /*!< SCL Low duration during I3C Push-Pull phases */
22126 #define I3C_TIMINGR0_SCLH_I3C_Pos           (8U)
22127 #define I3C_TIMINGR0_SCLH_I3C_Msk           (0xFFUL << I3C_TIMINGR0_SCLH_I3C_Pos)   /*!< 0x0000FF00 */
22128 #define I3C_TIMINGR0_SCLH_I3C               I3C_TIMINGR0_SCLH_I3C_Msk               /*!< SCL High duration during I3C Open-drain and Push-Pull phases */
22129 #define I3C_TIMINGR0_SCLL_OD_Pos            (16U)
22130 #define I3C_TIMINGR0_SCLL_OD_Msk            (0xFFUL << I3C_TIMINGR0_SCLL_OD_Pos)    /*!< 0x00FF0000 */
22131 #define I3C_TIMINGR0_SCLL_OD                I3C_TIMINGR0_SCLL_OD_Msk                /*!< SCL Low duration during  I3C Open-drain phases and I2C transfer */
22132 #define I3C_TIMINGR0_SCLH_I2C_Pos           (24U)
22133 #define I3C_TIMINGR0_SCLH_I2C_Msk           (0xFFUL << I3C_TIMINGR0_SCLH_I2C_Pos)   /*!< 0xFF000000 */
22134 #define I3C_TIMINGR0_SCLH_I2C               I3C_TIMINGR0_SCLH_I2C_Msk               /*!< SCL High duration during I2C transfer */
22135 
22136 /****************  Bit definition for I3C_TIMINGR1 register  ******************/
22137 #define I3C_TIMINGR1_AVAL_Pos               (0U)
22138 #define I3C_TIMINGR1_AVAL_Msk               (0xFFUL << I3C_TIMINGR1_AVAL_Pos)       /*!< 0x000000FF */
22139 #define I3C_TIMINGR1_AVAL                   I3C_TIMINGR1_AVAL_Msk                   /*!< Timing for I3C Bus Idle or Available condition */
22140 #define I3C_TIMINGR1_ASNCR_Pos              (8U)
22141 #define I3C_TIMINGR1_ASNCR_Msk              (0x3UL << I3C_TIMINGR1_ASNCR_Pos)       /*!< 0x00000300 */
22142 #define I3C_TIMINGR1_ASNCR                  I3C_TIMINGR1_ASNCR_Msk                  /*!< Activity State of the New Controller */
22143 #define I3C_TIMINGR1_ASNCR_0                (0x1UL << I3C_TIMINGR1_ASNCR_Pos)       /*!< 0x00000100 */
22144 #define I3C_TIMINGR1_ASNCR_1                (0x2UL << I3C_TIMINGR1_ASNCR_Pos)       /*!< 0x00000200 */
22145 #define I3C_TIMINGR1_FREE_Pos               (16U)
22146 #define I3C_TIMINGR1_FREE_Msk               (0x7FUL << I3C_TIMINGR1_FREE_Pos)       /*!< 0x007F0000 */
22147 #define I3C_TIMINGR1_FREE                   I3C_TIMINGR1_FREE_Msk                   /*!< Timing for I3C Bus Free condition */
22148 #define I3C_TIMINGR1_SDA_HD_Pos             (28U)
22149 #define I3C_TIMINGR1_SDA_HD_Msk             (0x1UL << I3C_TIMINGR1_SDA_HD_Pos)      /*!< 0x00010000 */
22150 #define I3C_TIMINGR1_SDA_HD                 I3C_TIMINGR1_SDA_HD_Msk                 /*!< SDA Hold Duration */
22151 
22152 /****************  Bit definition for I3C_TIMINGR2 register  ******************/
22153 #define I3C_TIMINGR2_STALLT_Pos             (0U)
22154 #define I3C_TIMINGR2_STALLT_Msk             (0x1UL << I3C_TIMINGR2_STALLT_Pos)      /*!< 0x0000001 */
22155 #define I3C_TIMINGR2_STALLT                 I3C_TIMINGR2_STALLT_Msk                 /*!< Stall on T bit */
22156 #define I3C_TIMINGR2_STALLD_Pos             (1U)
22157 #define I3C_TIMINGR2_STALLD_Msk             (0x1UL << I3C_TIMINGR2_STALLD_Pos)      /*!< 0x0000002 */
22158 #define I3C_TIMINGR2_STALLD                 I3C_TIMINGR2_STALLD_Msk                 /*!< Stall on PAR bit of data bytes */
22159 #define I3C_TIMINGR2_STALLC_Pos             (2U)
22160 #define I3C_TIMINGR2_STALLC_Msk             (0x1UL << I3C_TIMINGR2_STALLC_Pos)      /*!< 0x0000004 */
22161 #define I3C_TIMINGR2_STALLC                 I3C_TIMINGR2_STALLC_Msk                 /*!< Stall on PAR bit of CCC byte */
22162 #define I3C_TIMINGR2_STALLA_Pos             (3U)
22163 #define I3C_TIMINGR2_STALLA_Msk             (0x1UL << I3C_TIMINGR2_STALLA_Pos)      /*!< 0x0000008 */
22164 #define I3C_TIMINGR2_STALLA                 I3C_TIMINGR2_STALLA_Msk                 /*!< Stall on ACK bit */
22165 #define I3C_TIMINGR2_STALL_Pos              (8U)
22166 #define I3C_TIMINGR2_STALL_Msk              (0xFFUL << I3C_TIMINGR2_STALL_Pos)      /*!< 0x000FF00 */
22167 #define I3C_TIMINGR2_STALL                  I3C_TIMINGR2_STALL_Msk                  /*!< Controller Stall duration */
22168 
22169 /*******************  Bit definition for I3C_BCR register  ********************/
22170 #define I3C_BCR_BCR_Pos                     (0U)
22171 #define I3C_BCR_BCR_Msk                     (0xFFUL << I3C_BCR_BCR_Pos)             /*!< 0x000000FF */
22172 #define I3C_BCR_BCR                         I3C_BCR_BCR_Msk                         /*!< Bus Characteristics */
22173 #define I3C_BCR_BCR0_Pos                    (0U)
22174 #define I3C_BCR_BCR0_Msk                    (0x1UL << I3C_BCR_BCR0_Pos)             /*!< 0x00000001 */
22175 #define I3C_BCR_BCR0                        I3C_BCR_BCR0_Msk                        /*!< Max Data Speed Limitation */
22176 #define I3C_BCR_BCR1_Pos                    (1U)
22177 #define I3C_BCR_BCR1_Msk                    (0x1UL << I3C_BCR_BCR1_Pos)             /*!< 0x00000002 */
22178 #define I3C_BCR_BCR1                        I3C_BCR_BCR1_Msk                        /*!< IBI Request capable */
22179 #define I3C_BCR_BCR2_Pos                    (2U)
22180 #define I3C_BCR_BCR2_Msk                    (0x1UL << I3C_BCR_BCR2_Pos)             /*!< 0x00000004 */
22181 #define I3C_BCR_BCR2                        I3C_BCR_BCR2_Msk                        /*!< IBI Payload additional Mandatory Data Byte */
22182 #define I3C_BCR_BCR3_Pos                    (3U)
22183 #define I3C_BCR_BCR3_Msk                    (0x1UL << I3C_BCR_BCR3_Pos)             /*!< 0x00000008 */
22184 #define I3C_BCR_BCR3                        I3C_BCR_BCR3_Msk                        /*!< Offline capable */
22185 #define I3C_BCR_BCR4_Pos                    (4U)
22186 #define I3C_BCR_BCR4_Msk                    (0x1UL << I3C_BCR_BCR4_Pos)             /*!< 0x00000010 */
22187 #define I3C_BCR_BCR4                        I3C_BCR_BCR4_Msk                        /*!< Virtual target support */
22188 #define I3C_BCR_BCR5_Pos                    (5U)
22189 #define I3C_BCR_BCR5_Msk                    (0x1UL << I3C_BCR_BCR5_Pos)             /*!< 0x00000020 */
22190 #define I3C_BCR_BCR5                        I3C_BCR_BCR5_Msk                        /*!< Advanced capabilities */
22191 #define I3C_BCR_BCR6_Pos                    (6U)
22192 #define I3C_BCR_BCR6_Msk                    (0x1UL << I3C_BCR_BCR6_Pos)             /*!< 0x00000040 */
22193 #define I3C_BCR_BCR6                        I3C_BCR_BCR6_Msk                        /*!< Device Role shared during Dynamic Address Assignment */
22194 
22195 /*******************  Bit definition for I3C_DCR register  ********************/
22196 #define I3C_DCR_DCR_Pos                     (0U)
22197 #define I3C_DCR_DCR_Msk                     (0xFFUL << I3C_DCR_DCR_Pos)             /*!< 0x00000FF */
22198 #define I3C_DCR_DCR                         I3C_DCR_DCR_Msk                         /*!< Devices Characteristics */
22199 
22200 /*****************  Bit definition for I3C_GETCAPR register  ******************/
22201 #define I3C_GETCAPR_CAPPEND_Pos             (14U)
22202 #define I3C_GETCAPR_CAPPEND_Msk             (0x1UL << I3C_GETCAPR_CAPPEND_Pos)      /*!< 0x00004000 */
22203 #define I3C_GETCAPR_CAPPEND                 I3C_GETCAPR_CAPPEND_Msk                 /*!< IBI Request with Mandatory Data Byte */
22204 
22205 /*****************  Bit definition for I3C_CRCAPR register  *******************/
22206 #define I3C_CRCAPR_CAPDHOFF_Pos             (3U)
22207 #define I3C_CRCAPR_CAPDHOFF_Msk             (0x1UL << I3C_CRCAPR_CAPDHOFF_Pos)      /*!< 0x00000008 */
22208 #define I3C_CRCAPR_CAPDHOFF                 I3C_CRCAPR_CAPDHOFF_Msk                 /*!< Controller-role handoff needed */
22209 #define I3C_CRCAPR_CAPGRP_Pos               (9U)
22210 #define I3C_CRCAPR_CAPGRP_Msk               (0x1UL << I3C_CRCAPR_CAPGRP_Pos)        /*!< 0x00000200 */
22211 #define I3C_CRCAPR_CAPGRP                   I3C_CRCAPR_CAPGRP_Msk                   /*!< Group Address handoff supported */
22212 
22213 /****************  Bit definition for I3C_GETMXDSR register  ******************/
22214 #define I3C_GETMXDSR_HOFFAS_Pos             (0U)
22215 #define I3C_GETMXDSR_HOFFAS_Msk             (0x3UL << I3C_GETMXDSR_HOFFAS_Pos)      /*!< 0x00000003 */
22216 #define I3C_GETMXDSR_HOFFAS                 I3C_GETMXDSR_HOFFAS_Msk                 /*!< Handoff Activity State */
22217 #define I3C_GETMXDSR_HOFFAS_0               (0x1UL << I3C_GETMXDSR_HOFFAS_Pos)      /*!< 0x00000001 */
22218 #define I3C_GETMXDSR_HOFFAS_1               (0x2UL << I3C_GETMXDSR_HOFFAS_Pos)      /*!< 0x00000002 */
22219 #define I3C_GETMXDSR_FMT_Pos                (8U)
22220 #define I3C_GETMXDSR_FMT_Msk                (0x3UL << I3C_GETMXDSR_FMT_Pos)         /*!< 0x00000300 */
22221 #define I3C_GETMXDSR_FMT                    I3C_GETMXDSR_FMT_Msk                    /*!< Get Max Data Speed response in format 2 */
22222 #define I3C_GETMXDSR_FMT_0                  (0x1UL << I3C_GETMXDSR_FMT_Pos)         /*!< 0x00000100 */
22223 #define I3C_GETMXDSR_FMT_1                  (0x2UL << I3C_GETMXDSR_FMT_Pos)         /*!< 0x00000200 */
22224 #define I3C_GETMXDSR_RDTURN_Pos             (16U)
22225 #define I3C_GETMXDSR_RDTURN_Msk             (0xFFUL << I3C_GETMXDSR_RDTURN_Pos)     /*!< 0x00FF0000 */
22226 #define I3C_GETMXDSR_RDTURN                 I3C_GETMXDSR_RDTURN_Msk                 /*!< Max Read Turnaround Middle Byte  */
22227 #define I3C_GETMXDSR_TSCO_Pos               (24U)
22228 #define I3C_GETMXDSR_TSCO_Msk               (0x1UL << I3C_GETMXDSR_TSCO_Pos)        /*!< 0x01000000 */
22229 #define I3C_GETMXDSR_TSCO                   I3C_GETMXDSR_TSCO_Msk                   /*!< Clock-to-data Turnaround time */
22230 
22231 /******************  Bit definition for I3C_EPIDR register  *******************/
22232 #define I3C_EPIDR_MIPIID_Pos                (12U)
22233 #define I3C_EPIDR_MIPIID_Msk                (0xFUL << I3C_EPIDR_MIPIID_Pos)         /*!< 0x0000F000 */
22234 #define I3C_EPIDR_MIPIID                    I3C_EPIDR_MIPIID_Msk                    /*!< MIPI Instance ID */
22235 #define I3C_EPIDR_IDTSEL_Pos                (16U)
22236 #define I3C_EPIDR_IDTSEL_Msk                (0x1UL << I3C_EPIDR_IDTSEL_Pos)         /*!< 0x00010000 */
22237 #define I3C_EPIDR_IDTSEL                    I3C_EPIDR_IDTSEL_Msk                    /*!< ID Type Selector */
22238 #define I3C_EPIDR_MIPIMID_Pos               (17U)
22239 #define I3C_EPIDR_MIPIMID_Msk               (0x7FFFUL << I3C_EPIDR_MIPIMID_Pos)     /*!< 0xFFFE0000 */
22240 #define I3C_EPIDR_MIPIMID                   I3C_EPIDR_MIPIMID_Msk                   /*!< MIPI Manufacturer ID */
22241 
22242 
22243 /******************************************************************************/
22244 /*                                                                            */
22245 /*             Illegal Access Controller (IAC)                                */
22246 /*                                                                            */
22247 /******************************************************************************/
22248 /*******************  Bits definition for IAC_IER0 register *******************/
22249 #define IAC_IER0_IAIE0_Pos            (0U)
22250 #define IAC_IER0_IAIE0_Msk            (0x1UL << IAC_IER0_IAIE0_Pos)              /*!< 0x00000001 */
22251 #define IAC_IER0_IAIE0                IAC_IER0_IAIE0_Msk
22252 #define IAC_IER0_IAIE1_Pos            (1U)
22253 #define IAC_IER0_IAIE1_Msk            (0x1UL << IAC_IER0_IAIE1_Pos)              /*!< 0x00000002 */
22254 #define IAC_IER0_IAIE1                IAC_IER0_IAIE1_Msk
22255 #define IAC_IER0_IAIE2_Pos            (2U)
22256 #define IAC_IER0_IAIE2_Msk            (0x1UL << IAC_IER0_IAIE2_Pos)              /*!< 0x00000004 */
22257 #define IAC_IER0_IAIE2                IAC_IER0_IAIE2_Msk
22258 #define IAC_IER0_IAIE3_Pos            (3U)
22259 #define IAC_IER0_IAIE3_Msk            (0x1UL << IAC_IER0_IAIE3_Pos)              /*!< 0x00000008 */
22260 #define IAC_IER0_IAIE3                IAC_IER0_IAIE3_Msk
22261 #define IAC_IER0_IAIE4_Pos            (4U)
22262 #define IAC_IER0_IAIE4_Msk            (0x1UL << IAC_IER0_IAIE4_Pos)              /*!< 0x00000010 */
22263 #define IAC_IER0_IAIE4                IAC_IER0_IAIE4_Msk
22264 #define IAC_IER0_IAIE5_Pos            (5U)
22265 #define IAC_IER0_IAIE5_Msk            (0x1UL << IAC_IER0_IAIE5_Pos)              /*!< 0x00000020 */
22266 #define IAC_IER0_IAIE5                IAC_IER0_IAIE5_Msk
22267 #define IAC_IER0_IAIE6_Pos            (6U)
22268 #define IAC_IER0_IAIE6_Msk            (0x1UL << IAC_IER0_IAIE6_Pos)              /*!< 0x00000040 */
22269 #define IAC_IER0_IAIE6                IAC_IER0_IAIE6_Msk
22270 #define IAC_IER0_IAIE8_Pos            (8U)
22271 #define IAC_IER0_IAIE8_Msk            (0x1UL << IAC_IER0_IAIE8_Pos)              /*!< 0x00000100 */
22272 #define IAC_IER0_IAIE8                IAC_IER0_IAIE8_Msk
22273 #define IAC_IER0_IAIE9_Pos            (9U)
22274 #define IAC_IER0_IAIE9_Msk            (0x1UL << IAC_IER0_IAIE9_Pos)              /*!< 0x00000200 */
22275 #define IAC_IER0_IAIE9                IAC_IER0_IAIE9_Msk
22276 #define IAC_IER0_IAIE10_Pos           (10U)
22277 #define IAC_IER0_IAIE10_Msk           (0x1UL << IAC_IER0_IAIE10_Pos)             /*!< 0x00000400 */
22278 #define IAC_IER0_IAIE10               IAC_IER0_IAIE10_Msk
22279 #define IAC_IER0_IAIE11_Pos           (11U)
22280 #define IAC_IER0_IAIE11_Msk           (0x1UL << IAC_IER0_IAIE11_Pos)             /*!< 0x00000800 */
22281 #define IAC_IER0_IAIE11               IAC_IER0_IAIE11_Msk
22282 #define IAC_IER0_IAIE12_Pos           (12U)
22283 #define IAC_IER0_IAIE12_Msk           (0x1UL << IAC_IER0_IAIE12_Pos)             /*!< 0x00001000 */
22284 #define IAC_IER0_IAIE12               IAC_IER0_IAIE12_Msk
22285 #define IAC_IER0_IAIE13_Pos           (13U)
22286 #define IAC_IER0_IAIE13_Msk           (0x1UL << IAC_IER0_IAIE13_Pos)             /*!< 0x00002000 */
22287 #define IAC_IER0_IAIE13               IAC_IER0_IAIE13_Msk
22288 #define IAC_IER0_IAIE14_Pos           (14U)
22289 #define IAC_IER0_IAIE14_Msk           (0x1UL << IAC_IER0_IAIE14_Pos)             /*!< 0x00004000 */
22290 #define IAC_IER0_IAIE14               IAC_IER0_IAIE14_Msk
22291 #define IAC_IER0_IAIE15_Pos           (15U)
22292 #define IAC_IER0_IAIE15_Msk           (0x1UL << IAC_IER0_IAIE15_Pos)             /*!< 0x00008000 */
22293 #define IAC_IER0_IAIE15               IAC_IER0_IAIE15_Msk
22294 #define IAC_IER0_IAIE16_Pos           (16U)
22295 #define IAC_IER0_IAIE16_Msk           (0x1UL << IAC_IER0_IAIE16_Pos)             /*!< 0x00010000 */
22296 #define IAC_IER0_IAIE16               IAC_IER0_IAIE16_Msk
22297 #define IAC_IER0_IAIE17_Pos           (17U)
22298 #define IAC_IER0_IAIE17_Msk           (0x1UL << IAC_IER0_IAIE17_Pos)             /*!< 0x00020000 */
22299 #define IAC_IER0_IAIE17               IAC_IER0_IAIE17_Msk
22300 #define IAC_IER0_IAIE18_Pos           (18U)
22301 #define IAC_IER0_IAIE18_Msk           (0x1UL << IAC_IER0_IAIE18_Pos)             /*!< 0x00040000 */
22302 #define IAC_IER0_IAIE18               IAC_IER0_IAIE18_Msk
22303 #define IAC_IER0_IAIE19_Pos           (19U)
22304 #define IAC_IER0_IAIE19_Msk           (0x1UL << IAC_IER0_IAIE19_Pos)             /*!< 0x00080000 */
22305 #define IAC_IER0_IAIE19               IAC_IER0_IAIE19_Msk
22306 #define IAC_IER0_IAIE20_Pos           (20U)
22307 #define IAC_IER0_IAIE20_Msk           (0x1UL << IAC_IER0_IAIE20_Pos)             /*!< 0x00100000 */
22308 #define IAC_IER0_IAIE20               IAC_IER0_IAIE20_Msk
22309 #define IAC_IER0_IAIE21_Pos           (21U)
22310 #define IAC_IER0_IAIE21_Msk           (0x1UL << IAC_IER0_IAIE21_Pos)             /*!< 0x00200000 */
22311 #define IAC_IER0_IAIE21               IAC_IER0_IAIE21_Msk
22312 #define IAC_IER0_IAIE22_Pos           (22U)
22313 #define IAC_IER0_IAIE22_Msk           (0x1UL << IAC_IER0_IAIE22_Pos)             /*!< 0x00400000 */
22314 #define IAC_IER0_IAIE22               IAC_IER0_IAIE22_Msk
22315 #define IAC_IER0_IAIE23_Pos           (23U)
22316 #define IAC_IER0_IAIE23_Msk           (0x1UL << IAC_IER0_IAIE23_Pos)             /*!< 0x00800000 */
22317 #define IAC_IER0_IAIE23               IAC_IER0_IAIE23_Msk
22318 #define IAC_IER0_IAIE24_Pos           (24U)
22319 #define IAC_IER0_IAIE24_Msk           (0x1UL << IAC_IER0_IAIE24_Pos)             /*!< 0x01000000 */
22320 #define IAC_IER0_IAIE24               IAC_IER0_IAIE24_Msk
22321 #define IAC_IER0_IAIE25_Pos           (25U)
22322 #define IAC_IER0_IAIE25_Msk           (0x1UL << IAC_IER0_IAIE25_Pos)             /*!< 0x02000000 */
22323 #define IAC_IER0_IAIE25               IAC_IER0_IAIE25_Msk
22324 #define IAC_IER0_IAIE26_Pos           (26U)
22325 #define IAC_IER0_IAIE26_Msk           (0x1UL << IAC_IER0_IAIE26_Pos)             /*!< 0x04000000 */
22326 #define IAC_IER0_IAIE26               IAC_IER0_IAIE26_Msk
22327 #define IAC_IER0_IAIE27_Pos           (27U)
22328 #define IAC_IER0_IAIE27_Msk           (0x1UL << IAC_IER0_IAIE27_Pos)             /*!< 0x08000000 */
22329 #define IAC_IER0_IAIE27               IAC_IER0_IAIE27_Msk
22330 #define IAC_IER0_IAIE28_Pos           (28U)
22331 #define IAC_IER0_IAIE28_Msk           (0x1UL << IAC_IER0_IAIE28_Pos)             /*!< 0x10000000 */
22332 #define IAC_IER0_IAIE28               IAC_IER0_IAIE28_Msk
22333 #define IAC_IER0_IAIE29_Pos           (29U)
22334 #define IAC_IER0_IAIE29_Msk           (0x1UL << IAC_IER0_IAIE29_Pos)             /*!< 0x20000000 */
22335 #define IAC_IER0_IAIE29               IAC_IER0_IAIE29_Msk
22336 #define IAC_IER0_IAIE30_Pos           (30U)
22337 #define IAC_IER0_IAIE30_Msk           (0x1UL << IAC_IER0_IAIE30_Pos)             /*!< 0x40000000 */
22338 #define IAC_IER0_IAIE30               IAC_IER0_IAIE30_Msk
22339 #define IAC_IER0_IAIE31_Pos           (31U)
22340 #define IAC_IER0_IAIE31_Msk           (0x1UL << IAC_IER0_IAIE31_Pos)             /*!< 0x80000000 */
22341 #define IAC_IER0_IAIE31               IAC_IER0_IAIE31_Msk
22342 
22343 /*******************  Bits definition for IAC_IER1 register *******************/
22344 #define IAC_IER1_IAIE32_Pos           (0U)
22345 #define IAC_IER1_IAIE32_Msk           (0x1UL << IAC_IER1_IAIE32_Pos)             /*!< 0x00000001 */
22346 #define IAC_IER1_IAIE32               IAC_IER1_IAIE32_Msk
22347 #define IAC_IER1_IAIE33_Pos           (1U)
22348 #define IAC_IER1_IAIE33_Msk           (0x1UL << IAC_IER1_IAIE33_Pos)             /*!< 0x00000002 */
22349 #define IAC_IER1_IAIE33               IAC_IER1_IAIE33_Msk
22350 #define IAC_IER1_IAIE34_Pos           (2U)
22351 #define IAC_IER1_IAIE34_Msk           (0x1UL << IAC_IER1_IAIE34_Pos)             /*!< 0x00000004 */
22352 #define IAC_IER1_IAIE34               IAC_IER1_IAIE34_Msk
22353 #define IAC_IER1_IAIE35_Pos           (3U)
22354 #define IAC_IER1_IAIE35_Msk           (0x1UL << IAC_IER1_IAIE35_Pos)             /*!< 0x00000008 */
22355 #define IAC_IER1_IAIE35               IAC_IER1_IAIE35_Msk
22356 #define IAC_IER1_IAIE36_Pos           (4U)
22357 #define IAC_IER1_IAIE36_Msk           (0x1UL << IAC_IER1_IAIE36_Pos)             /*!< 0x00000010 */
22358 #define IAC_IER1_IAIE36               IAC_IER1_IAIE36_Msk
22359 #define IAC_IER1_IAIE37_Pos           (5U)
22360 #define IAC_IER1_IAIE37_Msk           (0x1UL << IAC_IER1_IAIE37_Pos)             /*!< 0x00000020 */
22361 #define IAC_IER1_IAIE37               IAC_IER1_IAIE37_Msk
22362 #define IAC_IER1_IAIE38_Pos           (6U)
22363 #define IAC_IER1_IAIE38_Msk           (0x1UL << IAC_IER1_IAIE38_Pos)             /*!< 0x00000040 */
22364 #define IAC_IER1_IAIE38               IAC_IER1_IAIE38_Msk
22365 #define IAC_IER1_IAIE39_Pos           (7U)
22366 #define IAC_IER1_IAIE39_Msk           (0x1UL << IAC_IER1_IAIE39_Pos)             /*!< 0x00000080 */
22367 #define IAC_IER1_IAIE39               IAC_IER1_IAIE39_Msk
22368 #define IAC_IER1_IAIE40_Pos           (8U)
22369 #define IAC_IER1_IAIE40_Msk           (0x1UL << IAC_IER1_IAIE40_Pos)             /*!< 0x00000100 */
22370 #define IAC_IER1_IAIE40               IAC_IER1_IAIE40_Msk
22371 #define IAC_IER1_IAIE41_Pos           (9U)
22372 #define IAC_IER1_IAIE41_Msk           (0x1UL << IAC_IER1_IAIE41_Pos)             /*!< 0x00000200 */
22373 #define IAC_IER1_IAIE41               IAC_IER1_IAIE41_Msk
22374 #define IAC_IER1_IAIE42_Pos           (10U)
22375 #define IAC_IER1_IAIE42_Msk           (0x1UL << IAC_IER1_IAIE42_Pos)             /*!< 0x00000400 */
22376 #define IAC_IER1_IAIE42               IAC_IER1_IAIE42_Msk
22377 #define IAC_IER1_IAIE43_Pos           (11U)
22378 #define IAC_IER1_IAIE43_Msk           (0x1UL << IAC_IER1_IAIE43_Pos)             /*!< 0x00000800 */
22379 #define IAC_IER1_IAIE43               IAC_IER1_IAIE43_Msk
22380 #define IAC_IER1_IAIE44_Pos           (12U)
22381 #define IAC_IER1_IAIE44_Msk           (0x1UL << IAC_IER1_IAIE44_Pos)             /*!< 0x00001000 */
22382 #define IAC_IER1_IAIE44               IAC_IER1_IAIE44_Msk
22383 #define IAC_IER1_IAIE45_Pos           (13U)
22384 #define IAC_IER1_IAIE45_Msk           (0x1UL << IAC_IER1_IAIE45_Pos)             /*!< 0x00002000 */
22385 #define IAC_IER1_IAIE45               IAC_IER1_IAIE45_Msk
22386 #define IAC_IER1_IAIE46_Pos           (14U)
22387 #define IAC_IER1_IAIE46_Msk           (0x1UL << IAC_IER1_IAIE46_Pos)             /*!< 0x00004000 */
22388 #define IAC_IER1_IAIE46               IAC_IER1_IAIE46_Msk
22389 #define IAC_IER1_IAIE47_Pos           (15U)
22390 #define IAC_IER1_IAIE47_Msk           (0x1UL << IAC_IER1_IAIE47_Pos)             /*!< 0x00008000 */
22391 #define IAC_IER1_IAIE47               IAC_IER1_IAIE47_Msk
22392 #define IAC_IER1_IAIE48_Pos           (16U)
22393 #define IAC_IER1_IAIE48_Msk           (0x1UL << IAC_IER1_IAIE48_Pos)             /*!< 0x00010000 */
22394 #define IAC_IER1_IAIE48               IAC_IER1_IAIE48_Msk
22395 #define IAC_IER1_IAIE49_Pos           (17U)
22396 #define IAC_IER1_IAIE49_Msk           (0x1UL << IAC_IER1_IAIE49_Pos)             /*!< 0x00020000 */
22397 #define IAC_IER1_IAIE49               IAC_IER1_IAIE49_Msk
22398 #define IAC_IER1_IAIE50_Pos           (18U)
22399 #define IAC_IER1_IAIE50_Msk           (0x1UL << IAC_IER1_IAIE50_Pos)             /*!< 0x00040000 */
22400 #define IAC_IER1_IAIE50               IAC_IER1_IAIE50_Msk
22401 #define IAC_IER1_IAIE51_Pos           (19U)
22402 #define IAC_IER1_IAIE51_Msk           (0x1UL << IAC_IER1_IAIE51_Pos)             /*!< 0x00080000 */
22403 #define IAC_IER1_IAIE51               IAC_IER1_IAIE51_Msk
22404 #define IAC_IER1_IAIE52_Pos           (20U)
22405 #define IAC_IER1_IAIE52_Msk           (0x1UL << IAC_IER1_IAIE52_Pos)             /*!< 0x00100000 */
22406 #define IAC_IER1_IAIE52               IAC_IER1_IAIE52_Msk
22407 #define IAC_IER1_IAIE53_Pos           (21U)
22408 #define IAC_IER1_IAIE53_Msk           (0x1UL << IAC_IER1_IAIE53_Pos)             /*!< 0x00200000 */
22409 #define IAC_IER1_IAIE53               IAC_IER1_IAIE53_Msk
22410 #define IAC_IER1_IAIE54_Pos           (22U)
22411 #define IAC_IER1_IAIE54_Msk           (0x1UL << IAC_IER1_IAIE54_Pos)             /*!< 0x00400000 */
22412 #define IAC_IER1_IAIE54               IAC_IER1_IAIE54_Msk
22413 #define IAC_IER1_IAIE55_Pos           (23U)
22414 #define IAC_IER1_IAIE55_Msk           (0x1UL << IAC_IER1_IAIE55_Pos)             /*!< 0x00800000 */
22415 #define IAC_IER1_IAIE55               IAC_IER1_IAIE55_Msk
22416 #define IAC_IER1_IAIE56_Pos           (24U)
22417 #define IAC_IER1_IAIE56_Msk           (0x1UL << IAC_IER1_IAIE56_Pos)             /*!< 0x01000000 */
22418 #define IAC_IER1_IAIE56               IAC_IER1_IAIE56_Msk
22419 #define IAC_IER1_IAIE57_Pos           (25U)
22420 #define IAC_IER1_IAIE57_Msk           (0x1UL << IAC_IER1_IAIE57_Pos)             /*!< 0x02000000 */
22421 #define IAC_IER1_IAIE57               IAC_IER1_IAIE57_Msk
22422 #define IAC_IER1_IAIE58_Pos           (26U)
22423 #define IAC_IER1_IAIE58_Msk           (0x1UL << IAC_IER1_IAIE58_Pos)             /*!< 0x04000000 */
22424 #define IAC_IER1_IAIE58               IAC_IER1_IAIE58_Msk
22425 #define IAC_IER1_IAIE60_Pos           (28U)
22426 #define IAC_IER1_IAIE60_Msk           (0x1UL << IAC_IER1_IAIE60_Pos)             /*!< 0x10000000 */
22427 #define IAC_IER1_IAIE60               IAC_IER1_IAIE60_Msk
22428 #define IAC_IER1_IAIE61_Pos           (29U)
22429 #define IAC_IER1_IAIE61_Msk           (0x1UL << IAC_IER1_IAIE61_Pos)             /*!< 0x20000000 */
22430 #define IAC_IER1_IAIE61               IAC_IER1_IAIE61_Msk
22431 #define IAC_IER1_IAIE62_Pos           (30U)
22432 #define IAC_IER1_IAIE62_Msk           (0x1UL << IAC_IER1_IAIE62_Pos)             /*!< 0x40000000 */
22433 #define IAC_IER1_IAIE62               IAC_IER1_IAIE62_Msk
22434 
22435 /*******************  Bits definition for IAC_IER2 register *******************/
22436 #define IAC_IER2_IAIE64_Pos           (0U)
22437 #define IAC_IER2_IAIE64_Msk           (0x1UL << IAC_IER2_IAIE64_Pos)             /*!< 0x00000001 */
22438 #define IAC_IER2_IAIE64               IAC_IER2_IAIE64_Msk
22439 #define IAC_IER2_IAIE65_Pos           (1U)
22440 #define IAC_IER2_IAIE65_Msk           (0x1UL << IAC_IER2_IAIE65_Pos)             /*!< 0x00000002 */
22441 #define IAC_IER2_IAIE65               IAC_IER2_IAIE65_Msk
22442 #define IAC_IER2_IAIE67_Pos           (3U)
22443 #define IAC_IER2_IAIE67_Msk           (0x1UL << IAC_IER2_IAIE67_Pos)             /*!< 0x00000008 */
22444 #define IAC_IER2_IAIE67               IAC_IER2_IAIE67_Msk
22445 #define IAC_IER2_IAIE68_Pos           (4U)
22446 #define IAC_IER2_IAIE68_Msk           (0x1UL << IAC_IER2_IAIE68_Pos)             /*!< 0x00000010 */
22447 #define IAC_IER2_IAIE68               IAC_IER2_IAIE68_Msk
22448 #define IAC_IER2_IAIE69_Pos           (5U)
22449 #define IAC_IER2_IAIE69_Msk           (0x1UL << IAC_IER2_IAIE69_Pos)             /*!< 0x00000020 */
22450 #define IAC_IER2_IAIE69               IAC_IER2_IAIE69_Msk
22451 #define IAC_IER2_IAIE76_Pos           (12U)
22452 #define IAC_IER2_IAIE76_Msk           (0x1UL << IAC_IER2_IAIE76_Pos)             /*!< 0x00001000 */
22453 #define IAC_IER2_IAIE76               IAC_IER2_IAIE76_Msk
22454 #define IAC_IER2_IAIE77_Pos           (13U)
22455 #define IAC_IER2_IAIE77_Msk           (0x1UL << IAC_IER2_IAIE77_Pos)             /*!< 0x00002000 */
22456 #define IAC_IER2_IAIE77               IAC_IER2_IAIE77_Msk
22457 #define IAC_IER2_IAIE78_Pos           (14U)
22458 #define IAC_IER2_IAIE78_Msk           (0x1UL << IAC_IER2_IAIE78_Pos)             /*!< 0x00004000 */
22459 #define IAC_IER2_IAIE78               IAC_IER2_IAIE78_Msk
22460 #define IAC_IER2_IAIE79_Pos           (15U)
22461 #define IAC_IER2_IAIE79_Msk           (0x1UL << IAC_IER2_IAIE79_Pos)             /*!< 0x00008000 */
22462 #define IAC_IER2_IAIE79               IAC_IER2_IAIE79_Msk
22463 #define IAC_IER2_IAIE80_Pos           (16U)
22464 #define IAC_IER2_IAIE80_Msk           (0x1UL << IAC_IER2_IAIE80_Pos)             /*!< 0x00010000 */
22465 #define IAC_IER2_IAIE80               IAC_IER2_IAIE80_Msk
22466 #define IAC_IER2_IAIE81_Pos           (17U)
22467 #define IAC_IER2_IAIE81_Msk           (0x1UL << IAC_IER2_IAIE81_Pos)             /*!< 0x00020000 */
22468 #define IAC_IER2_IAIE81               IAC_IER2_IAIE81_Msk
22469 #define IAC_IER2_IAIE82_Pos           (18U)
22470 #define IAC_IER2_IAIE82_Msk           (0x1UL << IAC_IER2_IAIE82_Pos)             /*!< 0x00040000 */
22471 #define IAC_IER2_IAIE82               IAC_IER2_IAIE82_Msk
22472 #define IAC_IER2_IAIE83_Pos           (19U)
22473 #define IAC_IER2_IAIE83_Msk           (0x1UL << IAC_IER2_IAIE83_Pos)             /*!< 0x00080000 */
22474 #define IAC_IER2_IAIE83               IAC_IER2_IAIE83_Msk
22475 #define IAC_IER2_IAIE84_Pos           (20U)
22476 #define IAC_IER2_IAIE84_Msk           (0x1UL << IAC_IER2_IAIE84_Pos)             /*!< 0x00100000 */
22477 #define IAC_IER2_IAIE84               IAC_IER2_IAIE84_Msk
22478 #define IAC_IER2_IAIE86_Pos           (22U)
22479 #define IAC_IER2_IAIE86_Msk           (0x1UL << IAC_IER2_IAIE86_Pos)             /*!< 0x00400000 */
22480 #define IAC_IER2_IAIE86               IAC_IER2_IAIE86_Msk
22481 #define IAC_IER2_IAIE87_Pos           (23U)
22482 #define IAC_IER2_IAIE87_Msk           (0x1UL << IAC_IER2_IAIE87_Pos)             /*!< 0x00800000 */
22483 #define IAC_IER2_IAIE87               IAC_IER2_IAIE87_Msk
22484 #define IAC_IER2_IAIE88_Pos           (24U)
22485 #define IAC_IER2_IAIE88_Msk           (0x1UL << IAC_IER2_IAIE88_Pos)             /*!< 0x01000000 */
22486 #define IAC_IER2_IAIE88               IAC_IER2_IAIE88_Msk
22487 #define IAC_IER2_IAIE89_Pos           (25U)
22488 #define IAC_IER2_IAIE89_Msk           (0x1UL << IAC_IER2_IAIE89_Pos)             /*!< 0x02000000 */
22489 #define IAC_IER2_IAIE89               IAC_IER2_IAIE89_Msk
22490 #define IAC_IER2_IAIE90_Pos           (26U)
22491 #define IAC_IER2_IAIE90_Msk           (0x1UL << IAC_IER2_IAIE90_Pos)             /*!< 0x04000000 */
22492 #define IAC_IER2_IAIE90               IAC_IER2_IAIE90_Msk
22493 #define IAC_IER2_IAIE92_Pos           (28U)
22494 #define IAC_IER2_IAIE92_Msk           (0x1UL << IAC_IER2_IAIE92_Pos)             /*!< 0x10000000 */
22495 #define IAC_IER2_IAIE92               IAC_IER2_IAIE92_Msk
22496 #define IAC_IER2_IAIE93_Pos           (29U)
22497 #define IAC_IER2_IAIE93_Msk           (0x1UL << IAC_IER2_IAIE93_Pos)             /*!< 0x20000000 */
22498 #define IAC_IER2_IAIE93               IAC_IER2_IAIE93_Msk
22499 #define IAC_IER2_IAIE94_Pos           (30U)
22500 #define IAC_IER2_IAIE94_Msk           (0x1UL << IAC_IER2_IAIE94_Pos)             /*!< 0x40000000 */
22501 #define IAC_IER2_IAIE94               IAC_IER2_IAIE94_Msk
22502 #define IAC_IER2_IAIE95_Pos           (31U)
22503 #define IAC_IER2_IAIE95_Msk           (0x1UL << IAC_IER2_IAIE95_Pos)             /*!< 0x80000000 */
22504 #define IAC_IER2_IAIE95               IAC_IER2_IAIE95_Msk
22505 
22506 /*******************  Bits definition for IAC_IER3 register *******************/
22507 #define IAC_IER3_IAIE96_Pos           (0U)
22508 #define IAC_IER3_IAIE96_Msk           (0x1UL << IAC_IER3_IAIE96_Pos)             /*!< 0x00000001 */
22509 #define IAC_IER3_IAIE96               IAC_IER3_IAIE96_Msk
22510 #define IAC_IER3_IAIE97_Pos           (1U)
22511 #define IAC_IER3_IAIE97_Msk           (0x1UL << IAC_IER3_IAIE97_Pos)             /*!< 0x00000002 */
22512 #define IAC_IER3_IAIE97               IAC_IER3_IAIE97_Msk
22513 #define IAC_IER3_IAIE98_Pos           (2U)
22514 #define IAC_IER3_IAIE98_Msk           (0x1UL << IAC_IER3_IAIE98_Pos)             /*!< 0x00000004 */
22515 #define IAC_IER3_IAIE98               IAC_IER3_IAIE98_Msk
22516 #define IAC_IER3_IAIE99_Pos           (3U)
22517 #define IAC_IER3_IAIE99_Msk           (0x1UL << IAC_IER3_IAIE99_Pos)             /*!< 0x00000008 */
22518 #define IAC_IER3_IAIE99               IAC_IER3_IAIE99_Msk
22519 #define IAC_IER3_IAIE100_Pos          (4U)
22520 #define IAC_IER3_IAIE100_Msk          (0x1UL << IAC_IER3_IAIE100_Pos)            /*!< 0x00000010 */
22521 #define IAC_IER3_IAIE100              IAC_IER3_IAIE100_Msk
22522 #define IAC_IER3_IAIE101_Pos          (5U)
22523 #define IAC_IER3_IAIE101_Msk          (0x1UL << IAC_IER3_IAIE101_Pos)            /*!< 0x00000020 */
22524 #define IAC_IER3_IAIE101              IAC_IER3_IAIE101_Msk
22525 #define IAC_IER3_IAIE102_Pos          (6U)
22526 #define IAC_IER3_IAIE102_Msk          (0x1UL << IAC_IER3_IAIE102_Pos)            /*!< 0x00000040 */
22527 #define IAC_IER3_IAIE102              IAC_IER3_IAIE102_Msk
22528 #define IAC_IER3_IAIE103_Pos          (7U)
22529 #define IAC_IER3_IAIE103_Msk          (0x1UL << IAC_IER3_IAIE103_Pos)            /*!< 0x00000080 */
22530 #define IAC_IER3_IAIE103              IAC_IER3_IAIE103_Msk
22531 #define IAC_IER3_IAIE104_Pos          (8U)
22532 #define IAC_IER3_IAIE104_Msk          (0x1UL << IAC_IER3_IAIE104_Pos)            /*!< 0x00000100 */
22533 #define IAC_IER3_IAIE104              IAC_IER3_IAIE104_Msk
22534 #define IAC_IER3_IAIE106_Pos          (10U)
22535 #define IAC_IER3_IAIE106_Msk          (0x1UL << IAC_IER3_IAIE106_Pos)            /*!< 0x00000400 */
22536 #define IAC_IER3_IAIE106              IAC_IER3_IAIE106_Msk
22537 
22538 /*******************  Bits definition for IAC_IER4 register *******************/
22539 #define IAC_IER4_IAIE128_Pos          (0U)
22540 #define IAC_IER4_IAIE128_Msk          (0x1UL << IAC_IER4_IAIE128_Pos)            /*!< 0x00000001 */
22541 #define IAC_IER4_IAIE128              IAC_IER4_IAIE128_Msk
22542 #define IAC_IER4_IAIE129_Pos          (1U)
22543 #define IAC_IER4_IAIE129_Msk          (0x1UL << IAC_IER4_IAIE129_Pos)            /*!< 0x00000002 */
22544 #define IAC_IER4_IAIE129              IAC_IER4_IAIE129_Msk
22545 #define IAC_IER4_IAIE130_Pos          (2U)
22546 #define IAC_IER4_IAIE130_Msk          (0x1UL << IAC_IER4_IAIE130_Pos)            /*!< 0x00000004 */
22547 #define IAC_IER4_IAIE130              IAC_IER4_IAIE130_Msk
22548 #define IAC_IER4_IAIE131_Pos          (3U)
22549 #define IAC_IER4_IAIE131_Msk          (0x1UL << IAC_IER4_IAIE131_Pos)            /*!< 0x00000008 */
22550 #define IAC_IER4_IAIE131              IAC_IER4_IAIE131_Msk
22551 #define IAC_IER4_IAIE133_Pos          (5U)
22552 #define IAC_IER4_IAIE133_Msk          (0x1UL << IAC_IER4_IAIE133_Pos)            /*!< 0x00000020 */
22553 #define IAC_IER4_IAIE133              IAC_IER4_IAIE133_Msk
22554 #define IAC_IER4_IAIE134_Pos          (6U)
22555 #define IAC_IER4_IAIE134_Msk          (0x1UL << IAC_IER4_IAIE134_Pos)            /*!< 0x00000040 */
22556 #define IAC_IER4_IAIE134              IAC_IER4_IAIE134_Msk
22557 #define IAC_IER4_IAIE135_Pos          (7U)
22558 #define IAC_IER4_IAIE135_Msk          (0x1UL << IAC_IER4_IAIE135_Pos)            /*!< 0x00000080 */
22559 #define IAC_IER4_IAIE135              IAC_IER4_IAIE135_Msk
22560 #define IAC_IER4_IAIE136_Pos          (8U)
22561 #define IAC_IER4_IAIE136_Msk          (0x1UL << IAC_IER4_IAIE136_Pos)            /*!< 0x00000100 */
22562 #define IAC_IER4_IAIE136              IAC_IER4_IAIE136_Msk
22563 #define IAC_IER4_IAIE137_Pos          (9U)
22564 #define IAC_IER4_IAIE137_Msk          (0x1UL << IAC_IER4_IAIE137_Pos)            /*!< 0x00000200 */
22565 #define IAC_IER4_IAIE137              IAC_IER4_IAIE137_Msk
22566 #define IAC_IER4_IAIE138_Pos          (10U)
22567 #define IAC_IER4_IAIE138_Msk          (0x1UL << IAC_IER4_IAIE138_Pos)            /*!< 0x00000400 */
22568 #define IAC_IER4_IAIE138              IAC_IER4_IAIE138_Msk
22569 #define IAC_IER4_IAIE139_Pos          (11U)
22570 #define IAC_IER4_IAIE139_Msk          (0x1UL << IAC_IER4_IAIE139_Pos)            /*!< 0x00000800 */
22571 #define IAC_IER4_IAIE139              IAC_IER4_IAIE139_Msk
22572 #define IAC_IER4_IAIE140_Pos          (12U)
22573 #define IAC_IER4_IAIE140_Msk          (0x1UL << IAC_IER4_IAIE140_Pos)            /*!< 0x00001000 */
22574 #define IAC_IER4_IAIE140              IAC_IER4_IAIE140_Msk
22575 #define IAC_IER4_IAIE141_Pos          (13U)
22576 #define IAC_IER4_IAIE141_Msk          (0x1UL << IAC_IER4_IAIE141_Pos)            /*!< 0x00002000 */
22577 #define IAC_IER4_IAIE141              IAC_IER4_IAIE141_Msk
22578 #define IAC_IER4_IAIE142_Pos          (14U)
22579 #define IAC_IER4_IAIE142_Msk          (0x1UL << IAC_IER4_IAIE142_Pos)            /*!< 0x00004000 */
22580 #define IAC_IER4_IAIE142              IAC_IER4_IAIE142_Msk
22581 #define IAC_IER4_IAIE143_Pos          (15U)
22582 #define IAC_IER4_IAIE143_Msk          (0x1UL << IAC_IER4_IAIE143_Pos)            /*!< 0x00008000 */
22583 #define IAC_IER4_IAIE143              IAC_IER4_IAIE143_Msk
22584 #define IAC_IER4_IAIE144_Pos          (16U)
22585 #define IAC_IER4_IAIE144_Msk          (0x1UL << IAC_IER4_IAIE144_Pos)            /*!< 0x00010000 */
22586 #define IAC_IER4_IAIE144              IAC_IER4_IAIE144_Msk
22587 #define IAC_IER4_IAIE145_Pos          (17U)
22588 #define IAC_IER4_IAIE145_Msk          (0x1UL << IAC_IER4_IAIE145_Pos)            /*!< 0x00020000 */
22589 #define IAC_IER4_IAIE145              IAC_IER4_IAIE145_Msk
22590 #define IAC_IER4_IAIE146_Pos          (18U)
22591 #define IAC_IER4_IAIE146_Msk          (0x1UL << IAC_IER4_IAIE146_Pos)            /*!< 0x00040000 */
22592 #define IAC_IER4_IAIE146              IAC_IER4_IAIE146_Msk
22593 #define IAC_IER4_IAIE147_Pos          (19U)
22594 #define IAC_IER4_IAIE147_Msk          (0x1UL << IAC_IER4_IAIE147_Pos)            /*!< 0x00080000 */
22595 #define IAC_IER4_IAIE147              IAC_IER4_IAIE147_Msk
22596 #define IAC_IER4_IAIE149_Pos          (21U)
22597 #define IAC_IER4_IAIE149_Msk          (0x1UL << IAC_IER4_IAIE149_Pos)            /*!< 0x00200000 */
22598 #define IAC_IER4_IAIE149              IAC_IER4_IAIE149_Msk
22599 #define IAC_IER4_IAIE150_Pos          (22U)
22600 #define IAC_IER4_IAIE150_Msk          (0x1UL << IAC_IER4_IAIE150_Pos)            /*!< 0x00400000 */
22601 #define IAC_IER4_IAIE150              IAC_IER4_IAIE150_Msk
22602 #define IAC_IER4_IAIE151_Pos          (23U)
22603 #define IAC_IER4_IAIE151_Msk          (0x1UL << IAC_IER4_IAIE151_Pos)            /*!< 0x00800000 */
22604 #define IAC_IER4_IAIE151              IAC_IER4_IAIE151_Msk
22605 #define IAC_IER4_IAIE152_Pos          (24U)
22606 #define IAC_IER4_IAIE152_Msk          (0x1UL << IAC_IER4_IAIE152_Pos)            /*!< 0x01000000 */
22607 #define IAC_IER4_IAIE152              IAC_IER4_IAIE152_Msk
22608 #define IAC_IER4_IAIE153_Pos          (25U)
22609 #define IAC_IER4_IAIE153_Msk          (0x1UL << IAC_IER4_IAIE153_Pos)            /*!< 0x02000000 */
22610 #define IAC_IER4_IAIE153              IAC_IER4_IAIE153_Msk
22611 #define IAC_IER4_IAIE155_Pos          (27U)
22612 #define IAC_IER4_IAIE155_Msk          (0x1UL << IAC_IER4_IAIE155_Pos)            /*!< 0x08000000 */
22613 #define IAC_IER4_IAIE155              IAC_IER4_IAIE155_Msk
22614 #define IAC_IER4_IAIE156_Pos          (28U)
22615 #define IAC_IER4_IAIE156_Msk          (0x1UL << IAC_IER4_IAIE156_Pos)            /*!< 0x10000000 */
22616 #define IAC_IER4_IAIE156              IAC_IER4_IAIE156_Msk
22617 #define IAC_IER4_IAIE157_Pos          (29U)
22618 #define IAC_IER4_IAIE157_Msk          (0x1UL << IAC_IER4_IAIE157_Pos)            /*!< 0x20000000 */
22619 #define IAC_IER4_IAIE157              IAC_IER4_IAIE157_Msk
22620 
22621 /*******************  Bits definition for IAC_ISR0 register *******************/
22622 #define IAC_ISR0_IAF0_Pos             (0U)
22623 #define IAC_ISR0_IAF0_Msk             (0x1UL << IAC_ISR0_IAF0_Pos)               /*!< 0x00000001 */
22624 #define IAC_ISR0_IAF0                 IAC_ISR0_IAF0_Msk
22625 #define IAC_ISR0_IAF1_Pos             (1U)
22626 #define IAC_ISR0_IAF1_Msk             (0x1UL << IAC_ISR0_IAF1_Pos)               /*!< 0x00000002 */
22627 #define IAC_ISR0_IAF1                 IAC_ISR0_IAF1_Msk
22628 #define IAC_ISR0_IAF2_Pos             (2U)
22629 #define IAC_ISR0_IAF2_Msk             (0x1UL << IAC_ISR0_IAF2_Pos)               /*!< 0x00000004 */
22630 #define IAC_ISR0_IAF2                 IAC_ISR0_IAF2_Msk
22631 #define IAC_ISR0_IAF3_Pos             (3U)
22632 #define IAC_ISR0_IAF3_Msk             (0x1UL << IAC_ISR0_IAF3_Pos)               /*!< 0x00000008 */
22633 #define IAC_ISR0_IAF3                 IAC_ISR0_IAF3_Msk
22634 #define IAC_ISR0_IAF4_Pos             (4U)
22635 #define IAC_ISR0_IAF4_Msk             (0x1UL << IAC_ISR0_IAF4_Pos)               /*!< 0x00000010 */
22636 #define IAC_ISR0_IAF4                 IAC_ISR0_IAF4_Msk
22637 #define IAC_ISR0_IAF5_Pos             (5U)
22638 #define IAC_ISR0_IAF5_Msk             (0x1UL << IAC_ISR0_IAF5_Pos)               /*!< 0x00000020 */
22639 #define IAC_ISR0_IAF5                 IAC_ISR0_IAF5_Msk
22640 #define IAC_ISR0_IAF6_Pos             (6U)
22641 #define IAC_ISR0_IAF6_Msk             (0x1UL << IAC_ISR0_IAF6_Pos)               /*!< 0x00000040 */
22642 #define IAC_ISR0_IAF6                 IAC_ISR0_IAF6_Msk
22643 #define IAC_ISR0_IAF8_Pos             (8U)
22644 #define IAC_ISR0_IAF8_Msk             (0x1UL << IAC_ISR0_IAF8_Pos)               /*!< 0x00000100 */
22645 #define IAC_ISR0_IAF8                 IAC_ISR0_IAF8_Msk
22646 #define IAC_ISR0_IAF9_Pos             (9U)
22647 #define IAC_ISR0_IAF9_Msk             (0x1UL << IAC_ISR0_IAF9_Pos)               /*!< 0x00000200 */
22648 #define IAC_ISR0_IAF9                 IAC_ISR0_IAF9_Msk
22649 #define IAC_ISR0_IAF10_Pos            (10U)
22650 #define IAC_ISR0_IAF10_Msk            (0x1UL << IAC_ISR0_IAF10_Pos)              /*!< 0x00000400 */
22651 #define IAC_ISR0_IAF10                IAC_ISR0_IAF10_Msk
22652 #define IAC_ISR0_IAF11_Pos            (11U)
22653 #define IAC_ISR0_IAF11_Msk            (0x1UL << IAC_ISR0_IAF11_Pos)              /*!< 0x00000800 */
22654 #define IAC_ISR0_IAF11                IAC_ISR0_IAF11_Msk
22655 #define IAC_ISR0_IAF12_Pos            (12U)
22656 #define IAC_ISR0_IAF12_Msk            (0x1UL << IAC_ISR0_IAF12_Pos)              /*!< 0x00001000 */
22657 #define IAC_ISR0_IAF12                IAC_ISR0_IAF12_Msk
22658 #define IAC_ISR0_IAF13_Pos            (13U)
22659 #define IAC_ISR0_IAF13_Msk            (0x1UL << IAC_ISR0_IAF13_Pos)              /*!< 0x00002000 */
22660 #define IAC_ISR0_IAF13                IAC_ISR0_IAF13_Msk
22661 #define IAC_ISR0_IAF14_Pos            (14U)
22662 #define IAC_ISR0_IAF14_Msk            (0x1UL << IAC_ISR0_IAF14_Pos)              /*!< 0x00004000 */
22663 #define IAC_ISR0_IAF14                IAC_ISR0_IAF14_Msk
22664 #define IAC_ISR0_IAF15_Pos            (15U)
22665 #define IAC_ISR0_IAF15_Msk            (0x1UL << IAC_ISR0_IAF15_Pos)              /*!< 0x00008000 */
22666 #define IAC_ISR0_IAF15                IAC_ISR0_IAF15_Msk
22667 #define IAC_ISR0_IAF16_Pos            (16U)
22668 #define IAC_ISR0_IAF16_Msk            (0x1UL << IAC_ISR0_IAF16_Pos)              /*!< 0x00010000 */
22669 #define IAC_ISR0_IAF16                IAC_ISR0_IAF16_Msk
22670 #define IAC_ISR0_IAF17_Pos            (17U)
22671 #define IAC_ISR0_IAF17_Msk            (0x1UL << IAC_ISR0_IAF17_Pos)              /*!< 0x00020000 */
22672 #define IAC_ISR0_IAF17                IAC_ISR0_IAF17_Msk
22673 #define IAC_ISR0_IAF18_Pos            (18U)
22674 #define IAC_ISR0_IAF18_Msk            (0x1UL << IAC_ISR0_IAF18_Pos)              /*!< 0x00040000 */
22675 #define IAC_ISR0_IAF18                IAC_ISR0_IAF18_Msk
22676 #define IAC_ISR0_IAF19_Pos            (19U)
22677 #define IAC_ISR0_IAF19_Msk            (0x1UL << IAC_ISR0_IAF19_Pos)              /*!< 0x00080000 */
22678 #define IAC_ISR0_IAF19                IAC_ISR0_IAF19_Msk
22679 #define IAC_ISR0_IAF20_Pos            (20U)
22680 #define IAC_ISR0_IAF20_Msk            (0x1UL << IAC_ISR0_IAF20_Pos)              /*!< 0x00100000 */
22681 #define IAC_ISR0_IAF20                IAC_ISR0_IAF20_Msk
22682 #define IAC_ISR0_IAF21_Pos            (21U)
22683 #define IAC_ISR0_IAF21_Msk            (0x1UL << IAC_ISR0_IAF21_Pos)              /*!< 0x00200000 */
22684 #define IAC_ISR0_IAF21                IAC_ISR0_IAF21_Msk
22685 #define IAC_ISR0_IAF22_Pos            (22U)
22686 #define IAC_ISR0_IAF22_Msk            (0x1UL << IAC_ISR0_IAF22_Pos)              /*!< 0x00400000 */
22687 #define IAC_ISR0_IAF22                IAC_ISR0_IAF22_Msk
22688 #define IAC_ISR0_IAF23_Pos            (23U)
22689 #define IAC_ISR0_IAF23_Msk            (0x1UL << IAC_ISR0_IAF23_Pos)              /*!< 0x00800000 */
22690 #define IAC_ISR0_IAF23                IAC_ISR0_IAF23_Msk
22691 #define IAC_ISR0_IAF24_Pos            (24U)
22692 #define IAC_ISR0_IAF24_Msk            (0x1UL << IAC_ISR0_IAF24_Pos)              /*!< 0x01000000 */
22693 #define IAC_ISR0_IAF24                IAC_ISR0_IAF24_Msk
22694 #define IAC_ISR0_IAF25_Pos            (25U)
22695 #define IAC_ISR0_IAF25_Msk            (0x1UL << IAC_ISR0_IAF25_Pos)              /*!< 0x02000000 */
22696 #define IAC_ISR0_IAF25                IAC_ISR0_IAF25_Msk
22697 #define IAC_ISR0_IAF26_Pos            (26U)
22698 #define IAC_ISR0_IAF26_Msk            (0x1UL << IAC_ISR0_IAF26_Pos)              /*!< 0x04000000 */
22699 #define IAC_ISR0_IAF26                IAC_ISR0_IAF26_Msk
22700 #define IAC_ISR0_IAF27_Pos            (27U)
22701 #define IAC_ISR0_IAF27_Msk            (0x1UL << IAC_ISR0_IAF27_Pos)              /*!< 0x08000000 */
22702 #define IAC_ISR0_IAF27                IAC_ISR0_IAF27_Msk
22703 #define IAC_ISR0_IAF28_Pos            (28U)
22704 #define IAC_ISR0_IAF28_Msk            (0x1UL << IAC_ISR0_IAF28_Pos)              /*!< 0x10000000 */
22705 #define IAC_ISR0_IAF28                IAC_ISR0_IAF28_Msk
22706 #define IAC_ISR0_IAF29_Pos            (29U)
22707 #define IAC_ISR0_IAF29_Msk            (0x1UL << IAC_ISR0_IAF29_Pos)              /*!< 0x20000000 */
22708 #define IAC_ISR0_IAF29                IAC_ISR0_IAF29_Msk
22709 #define IAC_ISR0_IAF30_Pos            (30U)
22710 #define IAC_ISR0_IAF30_Msk            (0x1UL << IAC_ISR0_IAF30_Pos)              /*!< 0x40000000 */
22711 #define IAC_ISR0_IAF30                IAC_ISR0_IAF30_Msk
22712 #define IAC_ISR0_IAF31_Pos            (31U)
22713 #define IAC_ISR0_IAF31_Msk            (0x1UL << IAC_ISR0_IAF31_Pos)              /*!< 0x80000000 */
22714 #define IAC_ISR0_IAF31                IAC_ISR0_IAF31_Msk
22715 
22716 /*******************  Bits definition for IAC_ISR1 register *******************/
22717 #define IAC_ISR1_IAF32_Pos            (0U)
22718 #define IAC_ISR1_IAF32_Msk            (0x1UL << IAC_ISR1_IAF32_Pos)              /*!< 0x00000001 */
22719 #define IAC_ISR1_IAF32                IAC_ISR1_IAF32_Msk
22720 #define IAC_ISR1_IAF33_Pos            (1U)
22721 #define IAC_ISR1_IAF33_Msk            (0x1UL << IAC_ISR1_IAF33_Pos)              /*!< 0x00000002 */
22722 #define IAC_ISR1_IAF33                IAC_ISR1_IAF33_Msk
22723 #define IAC_ISR1_IAF34_Pos            (2U)
22724 #define IAC_ISR1_IAF34_Msk            (0x1UL << IAC_ISR1_IAF34_Pos)              /*!< 0x00000004 */
22725 #define IAC_ISR1_IAF34                IAC_ISR1_IAF34_Msk
22726 #define IAC_ISR1_IAF35_Pos            (3U)
22727 #define IAC_ISR1_IAF35_Msk            (0x1UL << IAC_ISR1_IAF35_Pos)              /*!< 0x00000008 */
22728 #define IAC_ISR1_IAF35                IAC_ISR1_IAF35_Msk
22729 #define IAC_ISR1_IAF36_Pos            (4U)
22730 #define IAC_ISR1_IAF36_Msk            (0x1UL << IAC_ISR1_IAF36_Pos)              /*!< 0x00000010 */
22731 #define IAC_ISR1_IAF36                IAC_ISR1_IAF36_Msk
22732 #define IAC_ISR1_IAF37_Pos            (5U)
22733 #define IAC_ISR1_IAF37_Msk            (0x1UL << IAC_ISR1_IAF37_Pos)              /*!< 0x00000020 */
22734 #define IAC_ISR1_IAF37                IAC_ISR1_IAF37_Msk
22735 #define IAC_ISR1_IAF38_Pos            (6U)
22736 #define IAC_ISR1_IAF38_Msk            (0x1UL << IAC_ISR1_IAF38_Pos)              /*!< 0x00000040 */
22737 #define IAC_ISR1_IAF38                IAC_ISR1_IAF38_Msk
22738 #define IAC_ISR1_IAF39_Pos            (7U)
22739 #define IAC_ISR1_IAF39_Msk            (0x1UL << IAC_ISR1_IAF39_Pos)              /*!< 0x00000080 */
22740 #define IAC_ISR1_IAF39                IAC_ISR1_IAF39_Msk
22741 #define IAC_ISR1_IAF40_Pos            (8U)
22742 #define IAC_ISR1_IAF40_Msk            (0x1UL << IAC_ISR1_IAF40_Pos)              /*!< 0x00000100 */
22743 #define IAC_ISR1_IAF40                IAC_ISR1_IAF40_Msk
22744 #define IAC_ISR1_IAF41_Pos            (9U)
22745 #define IAC_ISR1_IAF41_Msk            (0x1UL << IAC_ISR1_IAF41_Pos)              /*!< 0x00000200 */
22746 #define IAC_ISR1_IAF41                IAC_ISR1_IAF41_Msk
22747 #define IAC_ISR1_IAF42_Pos            (10U)
22748 #define IAC_ISR1_IAF42_Msk            (0x1UL << IAC_ISR1_IAF42_Pos)              /*!< 0x00000400 */
22749 #define IAC_ISR1_IAF42                IAC_ISR1_IAF42_Msk
22750 #define IAC_ISR1_IAF43_Pos            (11U)
22751 #define IAC_ISR1_IAF43_Msk            (0x1UL << IAC_ISR1_IAF43_Pos)              /*!< 0x00000800 */
22752 #define IAC_ISR1_IAF43                IAC_ISR1_IAF43_Msk
22753 #define IAC_ISR1_IAF44_Pos            (12U)
22754 #define IAC_ISR1_IAF44_Msk            (0x1UL << IAC_ISR1_IAF44_Pos)              /*!< 0x00001000 */
22755 #define IAC_ISR1_IAF44                IAC_ISR1_IAF44_Msk
22756 #define IAC_ISR1_IAF45_Pos            (13U)
22757 #define IAC_ISR1_IAF45_Msk            (0x1UL << IAC_ISR1_IAF45_Pos)              /*!< 0x00002000 */
22758 #define IAC_ISR1_IAF45                IAC_ISR1_IAF45_Msk
22759 #define IAC_ISR1_IAF46_Pos            (14U)
22760 #define IAC_ISR1_IAF46_Msk            (0x1UL << IAC_ISR1_IAF46_Pos)              /*!< 0x00004000 */
22761 #define IAC_ISR1_IAF46                IAC_ISR1_IAF46_Msk
22762 #define IAC_ISR1_IAF47_Pos            (15U)
22763 #define IAC_ISR1_IAF47_Msk            (0x1UL << IAC_ISR1_IAF47_Pos)              /*!< 0x00008000 */
22764 #define IAC_ISR1_IAF47                IAC_ISR1_IAF47_Msk
22765 #define IAC_ISR1_IAF48_Pos            (16U)
22766 #define IAC_ISR1_IAF48_Msk            (0x1UL << IAC_ISR1_IAF48_Pos)              /*!< 0x00010000 */
22767 #define IAC_ISR1_IAF48                IAC_ISR1_IAF48_Msk
22768 #define IAC_ISR1_IAF49_Pos            (17U)
22769 #define IAC_ISR1_IAF49_Msk            (0x1UL << IAC_ISR1_IAF49_Pos)              /*!< 0x00020000 */
22770 #define IAC_ISR1_IAF49                IAC_ISR1_IAF49_Msk
22771 #define IAC_ISR1_IAF50_Pos            (18U)
22772 #define IAC_ISR1_IAF50_Msk            (0x1UL << IAC_ISR1_IAF50_Pos)              /*!< 0x00040000 */
22773 #define IAC_ISR1_IAF50                IAC_ISR1_IAF50_Msk
22774 #define IAC_ISR1_IAF51_Pos            (19U)
22775 #define IAC_ISR1_IAF51_Msk            (0x1UL << IAC_ISR1_IAF51_Pos)              /*!< 0x00080000 */
22776 #define IAC_ISR1_IAF51                IAC_ISR1_IAF51_Msk
22777 #define IAC_ISR1_IAF52_Pos            (20U)
22778 #define IAC_ISR1_IAF52_Msk            (0x1UL << IAC_ISR1_IAF52_Pos)              /*!< 0x00100000 */
22779 #define IAC_ISR1_IAF52                IAC_ISR1_IAF52_Msk
22780 #define IAC_ISR1_IAF53_Pos            (21U)
22781 #define IAC_ISR1_IAF53_Msk            (0x1UL << IAC_ISR1_IAF53_Pos)              /*!< 0x00200000 */
22782 #define IAC_ISR1_IAF53                IAC_ISR1_IAF53_Msk
22783 #define IAC_ISR1_IAF54_Pos            (22U)
22784 #define IAC_ISR1_IAF54_Msk            (0x1UL << IAC_ISR1_IAF54_Pos)              /*!< 0x00400000 */
22785 #define IAC_ISR1_IAF54                IAC_ISR1_IAF54_Msk
22786 #define IAC_ISR1_IAF55_Pos            (23U)
22787 #define IAC_ISR1_IAF55_Msk            (0x1UL << IAC_ISR1_IAF55_Pos)              /*!< 0x00800000 */
22788 #define IAC_ISR1_IAF55                IAC_ISR1_IAF55_Msk
22789 #define IAC_ISR1_IAF56_Pos            (24U)
22790 #define IAC_ISR1_IAF56_Msk            (0x1UL << IAC_ISR1_IAF56_Pos)              /*!< 0x01000000 */
22791 #define IAC_ISR1_IAF56                IAC_ISR1_IAF56_Msk
22792 #define IAC_ISR1_IAF57_Pos            (25U)
22793 #define IAC_ISR1_IAF57_Msk            (0x1UL << IAC_ISR1_IAF57_Pos)              /*!< 0x02000000 */
22794 #define IAC_ISR1_IAF57                IAC_ISR1_IAF57_Msk
22795 #define IAC_ISR1_IAF58_Pos            (26U)
22796 #define IAC_ISR1_IAF58_Msk            (0x1UL << IAC_ISR1_IAF58_Pos)              /*!< 0x04000000 */
22797 #define IAC_ISR1_IAF58                IAC_ISR1_IAF58_Msk
22798 #define IAC_ISR1_IAF60_Pos            (28U)
22799 #define IAC_ISR1_IAF60_Msk            (0x1UL << IAC_ISR1_IAF60_Pos)              /*!< 0x10000000 */
22800 #define IAC_ISR1_IAF60                IAC_ISR1_IAF60_Msk
22801 #define IAC_ISR1_IAF61_Pos            (29U)
22802 #define IAC_ISR1_IAF61_Msk            (0x1UL << IAC_ISR1_IAF61_Pos)              /*!< 0x20000000 */
22803 #define IAC_ISR1_IAF61                IAC_ISR1_IAF61_Msk
22804 #define IAC_ISR1_IAF62_Pos            (30U)
22805 #define IAC_ISR1_IAF62_Msk            (0x1UL << IAC_ISR1_IAF62_Pos)              /*!< 0x40000000 */
22806 #define IAC_ISR1_IAF62                IAC_ISR1_IAF62_Msk
22807 
22808 /*******************  Bits definition for IAC_ISR2 register *******************/
22809 #define IAC_ISR2_IAF64_Pos            (0U)
22810 #define IAC_ISR2_IAF64_Msk            (0x1UL << IAC_ISR2_IAF64_Pos)              /*!< 0x00000001 */
22811 #define IAC_ISR2_IAF64                IAC_ISR2_IAF64_Msk
22812 #define IAC_ISR2_IAF65_Pos            (1U)
22813 #define IAC_ISR2_IAF65_Msk            (0x1UL << IAC_ISR2_IAF65_Pos)              /*!< 0x00000002 */
22814 #define IAC_ISR2_IAF65                IAC_ISR2_IAF65_Msk
22815 #define IAC_ISR2_IAF67_Pos            (3U)
22816 #define IAC_ISR2_IAF67_Msk            (0x1UL << IAC_ISR2_IAF67_Pos)              /*!< 0x00000008 */
22817 #define IAC_ISR2_IAF67                IAC_ISR2_IAF67_Msk
22818 #define IAC_ISR2_IAF68_Pos            (4U)
22819 #define IAC_ISR2_IAF68_Msk            (0x1UL << IAC_ISR2_IAF68_Pos)              /*!< 0x00000010 */
22820 #define IAC_ISR2_IAF68                IAC_ISR2_IAF68_Msk
22821 #define IAC_ISR2_IAF69_Pos            (5U)
22822 #define IAC_ISR2_IAF69_Msk            (0x1UL << IAC_ISR2_IAF69_Pos)              /*!< 0x00000020 */
22823 #define IAC_ISR2_IAF69                IAC_ISR2_IAF69_Msk
22824 #define IAC_ISR2_IAF76_Pos            (12U)
22825 #define IAC_ISR2_IAF76_Msk            (0x1UL << IAC_ISR2_IAF76_Pos)              /*!< 0x00001000 */
22826 #define IAC_ISR2_IAF76                IAC_ISR2_IAF76_Msk
22827 #define IAC_ISR2_IAF77_Pos            (13U)
22828 #define IAC_ISR2_IAF77_Msk            (0x1UL << IAC_ISR2_IAF77_Pos)              /*!< 0x00002000 */
22829 #define IAC_ISR2_IAF77                IAC_ISR2_IAF77_Msk
22830 #define IAC_ISR2_IAF78_Pos            (14U)
22831 #define IAC_ISR2_IAF78_Msk            (0x1UL << IAC_ISR2_IAF78_Pos)              /*!< 0x00004000 */
22832 #define IAC_ISR2_IAF78                IAC_ISR2_IAF78_Msk
22833 #define IAC_ISR2_IAF79_Pos            (15U)
22834 #define IAC_ISR2_IAF79_Msk            (0x1UL << IAC_ISR2_IAF79_Pos)              /*!< 0x00008000 */
22835 #define IAC_ISR2_IAF79                IAC_ISR2_IAF79_Msk
22836 #define IAC_ISR2_IAF80_Pos            (16U)
22837 #define IAC_ISR2_IAF80_Msk            (0x1UL << IAC_ISR2_IAF80_Pos)              /*!< 0x00010000 */
22838 #define IAC_ISR2_IAF80                IAC_ISR2_IAF80_Msk
22839 #define IAC_ISR2_IAF81_Pos            (17U)
22840 #define IAC_ISR2_IAF81_Msk            (0x1UL << IAC_ISR2_IAF81_Pos)              /*!< 0x00020000 */
22841 #define IAC_ISR2_IAF81                IAC_ISR2_IAF81_Msk
22842 #define IAC_ISR2_IAF82_Pos            (18U)
22843 #define IAC_ISR2_IAF82_Msk            (0x1UL << IAC_ISR2_IAF82_Pos)              /*!< 0x00040000 */
22844 #define IAC_ISR2_IAF82                IAC_ISR2_IAF82_Msk
22845 #define IAC_ISR2_IAF83_Pos            (19U)
22846 #define IAC_ISR2_IAF83_Msk            (0x1UL << IAC_ISR2_IAF83_Pos)              /*!< 0x00080000 */
22847 #define IAC_ISR2_IAF83                IAC_ISR2_IAF83_Msk
22848 #define IAC_ISR2_IAF84_Pos            (20U)
22849 #define IAC_ISR2_IAF84_Msk            (0x1UL << IAC_ISR2_IAF84_Pos)              /*!< 0x00100000 */
22850 #define IAC_ISR2_IAF84                IAC_ISR2_IAF84_Msk
22851 #define IAC_ISR2_IAF86_Pos            (22U)
22852 #define IAC_ISR2_IAF86_Msk            (0x1UL << IAC_ISR2_IAF86_Pos)              /*!< 0x00400000 */
22853 #define IAC_ISR2_IAF86                IAC_ISR2_IAF86_Msk
22854 #define IAC_ISR2_IAF87_Pos            (23U)
22855 #define IAC_ISR2_IAF87_Msk            (0x1UL << IAC_ISR2_IAF87_Pos)              /*!< 0x00800000 */
22856 #define IAC_ISR2_IAF87                IAC_ISR2_IAF87_Msk
22857 #define IAC_ISR2_IAF88_Pos            (24U)
22858 #define IAC_ISR2_IAF88_Msk            (0x1UL << IAC_ISR2_IAF88_Pos)              /*!< 0x01000000 */
22859 #define IAC_ISR2_IAF88                IAC_ISR2_IAF88_Msk
22860 #define IAC_ISR2_IAF89_Pos            (25U)
22861 #define IAC_ISR2_IAF89_Msk            (0x1UL << IAC_ISR2_IAF89_Pos)              /*!< 0x02000000 */
22862 #define IAC_ISR2_IAF89                IAC_ISR2_IAF89_Msk
22863 #define IAC_ISR2_IAF90_Pos            (26U)
22864 #define IAC_ISR2_IAF90_Msk            (0x1UL << IAC_ISR2_IAF90_Pos)              /*!< 0x04000000 */
22865 #define IAC_ISR2_IAF90                IAC_ISR2_IAF90_Msk
22866 #define IAC_ISR2_IAF92_Pos            (28U)
22867 #define IAC_ISR2_IAF92_Msk            (0x1UL << IAC_ISR2_IAF92_Pos)              /*!< 0x10000000 */
22868 #define IAC_ISR2_IAF92                IAC_ISR2_IAF92_Msk
22869 #define IAC_ISR2_IAF93_Pos            (29U)
22870 #define IAC_ISR2_IAF93_Msk            (0x1UL << IAC_ISR2_IAF93_Pos)              /*!< 0x20000000 */
22871 #define IAC_ISR2_IAF93                IAC_ISR2_IAF93_Msk
22872 #define IAC_ISR2_IAF94_Pos            (30U)
22873 #define IAC_ISR2_IAF94_Msk            (0x1UL << IAC_ISR2_IAF94_Pos)              /*!< 0x40000000 */
22874 #define IAC_ISR2_IAF94                IAC_ISR2_IAF94_Msk
22875 #define IAC_ISR2_IAF95_Pos            (31U)
22876 #define IAC_ISR2_IAF95_Msk            (0x1UL << IAC_ISR2_IAF95_Pos)              /*!< 0x80000000 */
22877 #define IAC_ISR2_IAF95                IAC_ISR2_IAF95_Msk
22878 
22879 /*******************  Bits definition for IAC_ISR3 register *******************/
22880 #define IAC_ISR3_IAF96_Pos            (0U)
22881 #define IAC_ISR3_IAF96_Msk            (0x1UL << IAC_ISR3_IAF96_Pos)              /*!< 0x00000001 */
22882 #define IAC_ISR3_IAF96                IAC_ISR3_IAF96_Msk
22883 #define IAC_ISR3_IAF97_Pos            (1U)
22884 #define IAC_ISR3_IAF97_Msk            (0x1UL << IAC_ISR3_IAF97_Pos)              /*!< 0x00000002 */
22885 #define IAC_ISR3_IAF97                IAC_ISR3_IAF97_Msk
22886 #define IAC_ISR3_IAF98_Pos            (2U)
22887 #define IAC_ISR3_IAF98_Msk            (0x1UL << IAC_ISR3_IAF98_Pos)              /*!< 0x00000004 */
22888 #define IAC_ISR3_IAF98                IAC_ISR3_IAF98_Msk
22889 #define IAC_ISR3_IAF99_Pos            (3U)
22890 #define IAC_ISR3_IAF99_Msk            (0x1UL << IAC_ISR3_IAF99_Pos)              /*!< 0x00000008 */
22891 #define IAC_ISR3_IAF99                IAC_ISR3_IAF99_Msk
22892 #define IAC_ISR3_IAF100_Pos           (4U)
22893 #define IAC_ISR3_IAF100_Msk           (0x1UL << IAC_ISR3_IAF100_Pos)             /*!< 0x00000010 */
22894 #define IAC_ISR3_IAF100               IAC_ISR3_IAF100_Msk
22895 #define IAC_ISR3_IAF101_Pos           (5U)
22896 #define IAC_ISR3_IAF101_Msk           (0x1UL << IAC_ISR3_IAF101_Pos)             /*!< 0x00000020 */
22897 #define IAC_ISR3_IAF101               IAC_ISR3_IAF101_Msk
22898 #define IAC_ISR3_IAF102_Pos           (6U)
22899 #define IAC_ISR3_IAF102_Msk           (0x1UL << IAC_ISR3_IAF102_Pos)             /*!< 0x00000040 */
22900 #define IAC_ISR3_IAF102               IAC_ISR3_IAF102_Msk
22901 #define IAC_ISR3_IAF103_Pos           (7U)
22902 #define IAC_ISR3_IAF103_Msk           (0x1UL << IAC_ISR3_IAF103_Pos)             /*!< 0x00000080 */
22903 #define IAC_ISR3_IAF103               IAC_ISR3_IAF103_Msk
22904 #define IAC_ISR3_IAF104_Pos           (8U)
22905 #define IAC_ISR3_IAF104_Msk           (0x1UL << IAC_ISR3_IAF104_Pos)             /*!< 0x00000100 */
22906 #define IAC_ISR3_IAF104               IAC_ISR3_IAF104_Msk
22907 #define IAC_ISR3_IAF106_Pos           (10U)
22908 #define IAC_ISR3_IAF106_Msk           (0x1UL << IAC_ISR3_IAF106_Pos)             /*!< 0x00000400 */
22909 #define IAC_ISR3_IAF106               IAC_ISR3_IAF106_Msk
22910 
22911 /*******************  Bits definition for IAC_ISR4 register *******************/
22912 #define IAC_ISR4_IAF128_Pos           (0U)
22913 #define IAC_ISR4_IAF128_Msk           (0x1UL << IAC_ISR4_IAF128_Pos)             /*!< 0x00000001 */
22914 #define IAC_ISR4_IAF128               IAC_ISR4_IAF128_Msk
22915 #define IAC_ISR4_IAF129_Pos           (1U)
22916 #define IAC_ISR4_IAF129_Msk           (0x1UL << IAC_ISR4_IAF129_Pos)             /*!< 0x00000002 */
22917 #define IAC_ISR4_IAF129               IAC_ISR4_IAF129_Msk
22918 #define IAC_ISR4_IAF130_Pos           (2U)
22919 #define IAC_ISR4_IAF130_Msk           (0x1UL << IAC_ISR4_IAF130_Pos)             /*!< 0x00000004 */
22920 #define IAC_ISR4_IAF130               IAC_ISR4_IAF130_Msk
22921 #define IAC_ISR4_IAF131_Pos           (3U)
22922 #define IAC_ISR4_IAF131_Msk           (0x1UL << IAC_ISR4_IAF131_Pos)             /*!< 0x00000008 */
22923 #define IAC_ISR4_IAF131               IAC_ISR4_IAF131_Msk
22924 #define IAC_ISR4_IAF133_Pos           (5U)
22925 #define IAC_ISR4_IAF133_Msk           (0x1UL << IAC_ISR4_IAF133_Pos)             /*!< 0x00000020 */
22926 #define IAC_ISR4_IAF133               IAC_ISR4_IAF133_Msk
22927 #define IAC_ISR4_IAF134_Pos           (6U)
22928 #define IAC_ISR4_IAF134_Msk           (0x1UL << IAC_ISR4_IAF134_Pos)             /*!< 0x00000040 */
22929 #define IAC_ISR4_IAF134               IAC_ISR4_IAF134_Msk
22930 #define IAC_ISR4_IAF135_Pos           (7U)
22931 #define IAC_ISR4_IAF135_Msk           (0x1UL << IAC_ISR4_IAF135_Pos)             /*!< 0x00000080 */
22932 #define IAC_ISR4_IAF135               IAC_ISR4_IAF135_Msk
22933 #define IAC_ISR4_IAF136_Pos           (8U)
22934 #define IAC_ISR4_IAF136_Msk           (0x1UL << IAC_ISR4_IAF136_Pos)             /*!< 0x00000100 */
22935 #define IAC_ISR4_IAF136               IAC_ISR4_IAF136_Msk
22936 #define IAC_ISR4_IAF137_Pos           (9U)
22937 #define IAC_ISR4_IAF137_Msk           (0x1UL << IAC_ISR4_IAF137_Pos)             /*!< 0x00000200 */
22938 #define IAC_ISR4_IAF137               IAC_ISR4_IAF137_Msk
22939 #define IAC_ISR4_IAF138_Pos           (10U)
22940 #define IAC_ISR4_IAF138_Msk           (0x1UL << IAC_ISR4_IAF138_Pos)             /*!< 0x00000400 */
22941 #define IAC_ISR4_IAF138               IAC_ISR4_IAF138_Msk
22942 #define IAC_ISR4_IAF139_Pos           (11U)
22943 #define IAC_ISR4_IAF139_Msk           (0x1UL << IAC_ISR4_IAF139_Pos)             /*!< 0x00000800 */
22944 #define IAC_ISR4_IAF139               IAC_ISR4_IAF139_Msk
22945 #define IAC_ISR4_IAF140_Pos           (12U)
22946 #define IAC_ISR4_IAF140_Msk           (0x1UL << IAC_ISR4_IAF140_Pos)             /*!< 0x00001000 */
22947 #define IAC_ISR4_IAF140               IAC_ISR4_IAF140_Msk
22948 #define IAC_ISR4_IAF141_Pos           (13U)
22949 #define IAC_ISR4_IAF141_Msk           (0x1UL << IAC_ISR4_IAF141_Pos)             /*!< 0x00002000 */
22950 #define IAC_ISR4_IAF141               IAC_ISR4_IAF141_Msk
22951 #define IAC_ISR4_IAF142_Pos           (14U)
22952 #define IAC_ISR4_IAF142_Msk           (0x1UL << IAC_ISR4_IAF142_Pos)             /*!< 0x00004000 */
22953 #define IAC_ISR4_IAF142               IAC_ISR4_IAF142_Msk
22954 #define IAC_ISR4_IAF143_Pos           (15U)
22955 #define IAC_ISR4_IAF143_Msk           (0x1UL << IAC_ISR4_IAF143_Pos)             /*!< 0x00008000 */
22956 #define IAC_ISR4_IAF143               IAC_ISR4_IAF143_Msk
22957 #define IAC_ISR4_IAF144_Pos           (16U)
22958 #define IAC_ISR4_IAF144_Msk           (0x1UL << IAC_ISR4_IAF144_Pos)             /*!< 0x00010000 */
22959 #define IAC_ISR4_IAF144               IAC_ISR4_IAF144_Msk
22960 #define IAC_ISR4_IAF145_Pos           (17U)
22961 #define IAC_ISR4_IAF145_Msk           (0x1UL << IAC_ISR4_IAF145_Pos)             /*!< 0x00020000 */
22962 #define IAC_ISR4_IAF145               IAC_ISR4_IAF145_Msk
22963 #define IAC_ISR4_IAF146_Pos           (18U)
22964 #define IAC_ISR4_IAF146_Msk           (0x1UL << IAC_ISR4_IAF146_Pos)             /*!< 0x00040000 */
22965 #define IAC_ISR4_IAF146               IAC_ISR4_IAF146_Msk
22966 #define IAC_ISR4_IAF147_Pos           (19U)
22967 #define IAC_ISR4_IAF147_Msk           (0x1UL << IAC_ISR4_IAF147_Pos)             /*!< 0x00080000 */
22968 #define IAC_ISR4_IAF147               IAC_ISR4_IAF147_Msk
22969 #define IAC_ISR4_IAF149_Pos           (21U)
22970 #define IAC_ISR4_IAF149_Msk           (0x1UL << IAC_ISR4_IAF149_Pos)             /*!< 0x00200000 */
22971 #define IAC_ISR4_IAF149               IAC_ISR4_IAF149_Msk
22972 #define IAC_ISR4_IAF150_Pos           (22U)
22973 #define IAC_ISR4_IAF150_Msk           (0x1UL << IAC_ISR4_IAF150_Pos)             /*!< 0x00400000 */
22974 #define IAC_ISR4_IAF150               IAC_ISR4_IAF150_Msk
22975 #define IAC_ISR4_IAF151_Pos           (23U)
22976 #define IAC_ISR4_IAF151_Msk           (0x1UL << IAC_ISR4_IAF151_Pos)             /*!< 0x00800000 */
22977 #define IAC_ISR4_IAF151               IAC_ISR4_IAF151_Msk
22978 #define IAC_ISR4_IAF152_Pos           (24U)
22979 #define IAC_ISR4_IAF152_Msk           (0x1UL << IAC_ISR4_IAF152_Pos)             /*!< 0x01000000 */
22980 #define IAC_ISR4_IAF152               IAC_ISR4_IAF152_Msk
22981 #define IAC_ISR4_IAF153_Pos           (25U)
22982 #define IAC_ISR4_IAF153_Msk           (0x1UL << IAC_ISR4_IAF153_Pos)             /*!< 0x02000000 */
22983 #define IAC_ISR4_IAF153               IAC_ISR4_IAF153_Msk
22984 #define IAC_ISR4_IAF155_Pos           (27U)
22985 #define IAC_ISR4_IAF155_Msk           (0x1UL << IAC_ISR4_IAF155_Pos)             /*!< 0x08000000 */
22986 #define IAC_ISR4_IAF155               IAC_ISR4_IAF155_Msk
22987 #define IAC_ISR4_IAF156_Pos           (28U)
22988 #define IAC_ISR4_IAF156_Msk           (0x1UL << IAC_ISR4_IAF156_Pos)             /*!< 0x10000000 */
22989 #define IAC_ISR4_IAF156               IAC_ISR4_IAF156_Msk
22990 #define IAC_ISR4_IAF157_Pos           (29U)
22991 #define IAC_ISR4_IAF157_Msk           (0x1UL << IAC_ISR4_IAF157_Pos)             /*!< 0x20000000 */
22992 #define IAC_ISR4_IAF157               IAC_ISR4_IAF157_Msk
22993 
22994 /*******************  Bits definition for IAC_ICR0 register *******************/
22995 #define IAC_ICR0_IACF0_Pos            (0U)
22996 #define IAC_ICR0_IACF0_Msk            (0x1UL << IAC_ICR0_IACF0_Pos)               /*!< 0x00000001 */
22997 #define IAC_ICR0_IACF0                IAC_ICR0_IACF0_Msk
22998 #define IAC_ICR0_IACF1_Pos            (1U)
22999 #define IAC_ICR0_IACF1_Msk            (0x1UL << IAC_ICR0_IACF1_Pos)               /*!< 0x00000002 */
23000 #define IAC_ICR0_IACF1                IAC_ICR0_IACF1_Msk
23001 #define IAC_ICR0_IACF2_Pos            (2U)
23002 #define IAC_ICR0_IACF2_Msk            (0x1UL << IAC_ICR0_IACF2_Pos)               /*!< 0x00000004 */
23003 #define IAC_ICR0_IACF2                IAC_ICR0_IACF2_Msk
23004 #define IAC_ICR0_IACF3_Pos            (3U)
23005 #define IAC_ICR0_IACF3_Msk            (0x1UL << IAC_ICR0_IACF3_Pos)               /*!< 0x00000008 */
23006 #define IAC_ICR0_IACF3                IAC_ICR0_IACF3_Msk
23007 #define IAC_ICR0_IACF4_Pos            (4U)
23008 #define IAC_ICR0_IACF4_Msk            (0x1UL << IAC_ICR0_IACF4_Pos)               /*!< 0x00000010 */
23009 #define IAC_ICR0_IACF4                IAC_ICR0_IACF4_Msk
23010 #define IAC_ICR0_IACF5_Pos            (5U)
23011 #define IAC_ICR0_IACF5_Msk            (0x1UL << IAC_ICR0_IACF5_Pos)               /*!< 0x00000020 */
23012 #define IAC_ICR0_IACF5                IAC_ICR0_IACF5_Msk
23013 #define IAC_ICR0_IACF6_Pos            (6U)
23014 #define IAC_ICR0_IACF6_Msk            (0x1UL << IAC_ICR0_IACF6_Pos)               /*!< 0x00000040 */
23015 #define IAC_ICR0_IACF6                IAC_ICR0_IACF6_Msk
23016 #define IAC_ICR0_IACF8_Pos            (8U)
23017 #define IAC_ICR0_IACF8_Msk            (0x1UL << IAC_ICR0_IACF8_Pos)               /*!< 0x00000100 */
23018 #define IAC_ICR0_IACF8                IAC_ICR0_IACF8_Msk
23019 #define IAC_ICR0_IACF9_Pos            (9U)
23020 #define IAC_ICR0_IACF9_Msk            (0x1UL << IAC_ICR0_IACF9_Pos)               /*!< 0x00000200 */
23021 #define IAC_ICR0_IACF9                IAC_ICR0_IACF9_Msk
23022 #define IAC_ICR0_IACF10_Pos           (10U)
23023 #define IAC_ICR0_IACF10_Msk           (0x1UL << IAC_ICR0_IACF10_Pos)              /*!< 0x00000400 */
23024 #define IAC_ICR0_IACF10               IAC_ICR0_IACF10_Msk
23025 #define IAC_ICR0_IACF11_Pos           (11U)
23026 #define IAC_ICR0_IACF11_Msk           (0x1UL << IAC_ICR0_IACF11_Pos)              /*!< 0x00000800 */
23027 #define IAC_ICR0_IACF11               IAC_ICR0_IACF11_Msk
23028 #define IAC_ICR0_IACF12_Pos           (12U)
23029 #define IAC_ICR0_IACF12_Msk           (0x1UL << IAC_ICR0_IACF12_Pos)              /*!< 0x00001000 */
23030 #define IAC_ICR0_IACF12               IAC_ICR0_IACF12_Msk
23031 #define IAC_ICR0_IACF13_Pos           (13U)
23032 #define IAC_ICR0_IACF13_Msk           (0x1UL << IAC_ICR0_IACF13_Pos)              /*!< 0x00002000 */
23033 #define IAC_ICR0_IACF13               IAC_ICR0_IACF13_Msk
23034 #define IAC_ICR0_IACF14_Pos           (14U)
23035 #define IAC_ICR0_IACF14_Msk           (0x1UL << IAC_ICR0_IACF14_Pos)              /*!< 0x00004000 */
23036 #define IAC_ICR0_IACF14               IAC_ICR0_IACF14_Msk
23037 #define IAC_ICR0_IACF15_Pos           (15U)
23038 #define IAC_ICR0_IACF15_Msk           (0x1UL << IAC_ICR0_IACF15_Pos)              /*!< 0x00008000 */
23039 #define IAC_ICR0_IACF15               IAC_ICR0_IACF15_Msk
23040 #define IAC_ICR0_IACF16_Pos           (16U)
23041 #define IAC_ICR0_IACF16_Msk           (0x1UL << IAC_ICR0_IACF16_Pos)              /*!< 0x00010000 */
23042 #define IAC_ICR0_IACF16               IAC_ICR0_IACF16_Msk
23043 #define IAC_ICR0_IACF17_Pos           (17U)
23044 #define IAC_ICR0_IACF17_Msk           (0x1UL << IAC_ICR0_IACF17_Pos)              /*!< 0x00020000 */
23045 #define IAC_ICR0_IACF17               IAC_ICR0_IACF17_Msk
23046 #define IAC_ICR0_IACF18_Pos           (18U)
23047 #define IAC_ICR0_IACF18_Msk           (0x1UL << IAC_ICR0_IACF18_Pos)              /*!< 0x00040000 */
23048 #define IAC_ICR0_IACF18               IAC_ICR0_IACF18_Msk
23049 #define IAC_ICR0_IACF19_Pos           (19U)
23050 #define IAC_ICR0_IACF19_Msk           (0x1UL << IAC_ICR0_IACF19_Pos)              /*!< 0x00080000 */
23051 #define IAC_ICR0_IACF19               IAC_ICR0_IACF19_Msk
23052 #define IAC_ICR0_IACF20_Pos           (20U)
23053 #define IAC_ICR0_IACF20_Msk           (0x1UL << IAC_ICR0_IACF20_Pos)              /*!< 0x00100000 */
23054 #define IAC_ICR0_IACF20               IAC_ICR0_IACF20_Msk
23055 #define IAC_ICR0_IACF21_Pos           (21U)
23056 #define IAC_ICR0_IACF21_Msk           (0x1UL << IAC_ICR0_IACF21_Pos)              /*!< 0x00200000 */
23057 #define IAC_ICR0_IACF21               IAC_ICR0_IACF21_Msk
23058 #define IAC_ICR0_IACF22_Pos           (22U)
23059 #define IAC_ICR0_IACF22_Msk           (0x1UL << IAC_ICR0_IACF22_Pos)              /*!< 0x00400000 */
23060 #define IAC_ICR0_IACF22               IAC_ICR0_IACF22_Msk
23061 #define IAC_ICR0_IACF23_Pos           (23U)
23062 #define IAC_ICR0_IACF23_Msk           (0x1UL << IAC_ICR0_IACF23_Pos)              /*!< 0x00800000 */
23063 #define IAC_ICR0_IACF23               IAC_ICR0_IACF23_Msk
23064 #define IAC_ICR0_IACF24_Pos           (24U)
23065 #define IAC_ICR0_IACF24_Msk           (0x1UL << IAC_ICR0_IACF24_Pos)              /*!< 0x01000000 */
23066 #define IAC_ICR0_IACF24               IAC_ICR0_IACF24_Msk
23067 #define IAC_ICR0_IACF25_Pos           (25U)
23068 #define IAC_ICR0_IACF25_Msk           (0x1UL << IAC_ICR0_IACF25_Pos)              /*!< 0x02000000 */
23069 #define IAC_ICR0_IACF25               IAC_ICR0_IACF25_Msk
23070 #define IAC_ICR0_IACF26_Pos           (26U)
23071 #define IAC_ICR0_IACF26_Msk           (0x1UL << IAC_ICR0_IACF26_Pos)              /*!< 0x04000000 */
23072 #define IAC_ICR0_IACF26               IAC_ICR0_IACF26_Msk
23073 #define IAC_ICR0_IACF27_Pos           (27U)
23074 #define IAC_ICR0_IACF27_Msk           (0x1UL << IAC_ICR0_IACF27_Pos)              /*!< 0x08000000 */
23075 #define IAC_ICR0_IACF27               IAC_ICR0_IACF27_Msk
23076 #define IAC_ICR0_IACF28_Pos           (28U)
23077 #define IAC_ICR0_IACF28_Msk           (0x1UL << IAC_ICR0_IACF28_Pos)              /*!< 0x10000000 */
23078 #define IAC_ICR0_IACF28               IAC_ICR0_IACF28_Msk
23079 #define IAC_ICR0_IACF29_Pos           (29U)
23080 #define IAC_ICR0_IACF29_Msk           (0x1UL << IAC_ICR0_IACF29_Pos)              /*!< 0x20000000 */
23081 #define IAC_ICR0_IACF29               IAC_ICR0_IACF29_Msk
23082 #define IAC_ICR0_IACF30_Pos           (30U)
23083 #define IAC_ICR0_IACF30_Msk           (0x1UL << IAC_ICR0_IACF30_Pos)              /*!< 0x40000000 */
23084 #define IAC_ICR0_IACF30               IAC_ICR0_IACF30_Msk
23085 #define IAC_ICR0_IACF31_Pos           (31U)
23086 #define IAC_ICR0_IACF31_Msk           (0x1UL << IAC_ICR0_IACF31_Pos)              /*!< 0x80000000 */
23087 #define IAC_ICR0_IACF31               IAC_ICR0_IACF31_Msk
23088 
23089 /*******************  Bits definition for IAC_ICR1 register *******************/
23090 #define IAC_ICR1_IACF32_Pos           (0U)
23091 #define IAC_ICR1_IACF32_Msk           (0x1UL << IAC_ICR1_IACF32_Pos)              /*!< 0x00000001 */
23092 #define IAC_ICR1_IACF32               IAC_ICR1_IACF32_Msk
23093 #define IAC_ICR1_IACF33_Pos           (1U)
23094 #define IAC_ICR1_IACF33_Msk           (0x1UL << IAC_ICR1_IACF33_Pos)              /*!< 0x00000002 */
23095 #define IAC_ICR1_IACF33               IAC_ICR1_IACF33_Msk
23096 #define IAC_ICR1_IACF34_Pos           (2U)
23097 #define IAC_ICR1_IACF34_Msk           (0x1UL << IAC_ICR1_IACF34_Pos)              /*!< 0x00000004 */
23098 #define IAC_ICR1_IACF34               IAC_ICR1_IACF34_Msk
23099 #define IAC_ICR1_IACF35_Pos           (3U)
23100 #define IAC_ICR1_IACF35_Msk           (0x1UL << IAC_ICR1_IACF35_Pos)              /*!< 0x00000008 */
23101 #define IAC_ICR1_IACF35               IAC_ICR1_IACF35_Msk
23102 #define IAC_ICR1_IACF36_Pos           (4U)
23103 #define IAC_ICR1_IACF36_Msk           (0x1UL << IAC_ICR1_IACF36_Pos)              /*!< 0x00000010 */
23104 #define IAC_ICR1_IACF36               IAC_ICR1_IACF36_Msk
23105 #define IAC_ICR1_IACF37_Pos           (5U)
23106 #define IAC_ICR1_IACF37_Msk           (0x1UL << IAC_ICR1_IACF37_Pos)              /*!< 0x00000020 */
23107 #define IAC_ICR1_IACF37               IAC_ICR1_IACF37_Msk
23108 #define IAC_ICR1_IACF38_Pos           (6U)
23109 #define IAC_ICR1_IACF38_Msk           (0x1UL << IAC_ICR1_IACF38_Pos)              /*!< 0x00000040 */
23110 #define IAC_ICR1_IACF38               IAC_ICR1_IACF38_Msk
23111 #define IAC_ICR1_IACF39_Pos           (7U)
23112 #define IAC_ICR1_IACF39_Msk           (0x1UL << IAC_ICR1_IACF39_Pos)              /*!< 0x00000080 */
23113 #define IAC_ICR1_IACF39               IAC_ICR1_IACF39_Msk
23114 #define IAC_ICR1_IACF40_Pos           (8U)
23115 #define IAC_ICR1_IACF40_Msk           (0x1UL << IAC_ICR1_IACF40_Pos)              /*!< 0x00000100 */
23116 #define IAC_ICR1_IACF40               IAC_ICR1_IACF40_Msk
23117 #define IAC_ICR1_IACF41_Pos           (9U)
23118 #define IAC_ICR1_IACF41_Msk           (0x1UL << IAC_ICR1_IACF41_Pos)              /*!< 0x00000200 */
23119 #define IAC_ICR1_IACF41               IAC_ICR1_IACF41_Msk
23120 #define IAC_ICR1_IACF42_Pos           (10U)
23121 #define IAC_ICR1_IACF42_Msk           (0x1UL << IAC_ICR1_IACF42_Pos)              /*!< 0x00000400 */
23122 #define IAC_ICR1_IACF42               IAC_ICR1_IACF42_Msk
23123 #define IAC_ICR1_IACF43_Pos           (11U)
23124 #define IAC_ICR1_IACF43_Msk           (0x1UL << IAC_ICR1_IACF43_Pos)              /*!< 0x00000800 */
23125 #define IAC_ICR1_IACF43               IAC_ICR1_IACF43_Msk
23126 #define IAC_ICR1_IACF44_Pos           (12U)
23127 #define IAC_ICR1_IACF44_Msk           (0x1UL << IAC_ICR1_IACF44_Pos)              /*!< 0x00001000 */
23128 #define IAC_ICR1_IACF44               IAC_ICR1_IACF44_Msk
23129 #define IAC_ICR1_IACF45_Pos           (13U)
23130 #define IAC_ICR1_IACF45_Msk           (0x1UL << IAC_ICR1_IACF45_Pos)              /*!< 0x00002000 */
23131 #define IAC_ICR1_IACF45               IAC_ICR1_IACF45_Msk
23132 #define IAC_ICR1_IACF46_Pos           (14U)
23133 #define IAC_ICR1_IACF46_Msk           (0x1UL << IAC_ICR1_IACF46_Pos)              /*!< 0x00004000 */
23134 #define IAC_ICR1_IACF46               IAC_ICR1_IACF46_Msk
23135 #define IAC_ICR1_IACF47_Pos           (15U)
23136 #define IAC_ICR1_IACF47_Msk           (0x1UL << IAC_ICR1_IACF47_Pos)              /*!< 0x00008000 */
23137 #define IAC_ICR1_IACF47               IAC_ICR1_IACF47_Msk
23138 #define IAC_ICR1_IACF48_Pos           (16U)
23139 #define IAC_ICR1_IACF48_Msk           (0x1UL << IAC_ICR1_IACF48_Pos)              /*!< 0x00010000 */
23140 #define IAC_ICR1_IACF48               IAC_ICR1_IACF48_Msk
23141 #define IAC_ICR1_IACF49_Pos           (17U)
23142 #define IAC_ICR1_IACF49_Msk           (0x1UL << IAC_ICR1_IACF49_Pos)              /*!< 0x00020000 */
23143 #define IAC_ICR1_IACF49               IAC_ICR1_IACF49_Msk
23144 #define IAC_ICR1_IACF50_Pos           (18U)
23145 #define IAC_ICR1_IACF50_Msk           (0x1UL << IAC_ICR1_IACF50_Pos)              /*!< 0x00040000 */
23146 #define IAC_ICR1_IACF50               IAC_ICR1_IACF50_Msk
23147 #define IAC_ICR1_IACF51_Pos           (19U)
23148 #define IAC_ICR1_IACF51_Msk           (0x1UL << IAC_ICR1_IACF51_Pos)              /*!< 0x00080000 */
23149 #define IAC_ICR1_IACF51               IAC_ICR1_IACF51_Msk
23150 #define IAC_ICR1_IACF52_Pos           (20U)
23151 #define IAC_ICR1_IACF52_Msk           (0x1UL << IAC_ICR1_IACF52_Pos)              /*!< 0x00100000 */
23152 #define IAC_ICR1_IACF52               IAC_ICR1_IACF52_Msk
23153 #define IAC_ICR1_IACF53_Pos           (21U)
23154 #define IAC_ICR1_IACF53_Msk           (0x1UL << IAC_ICR1_IACF53_Pos)              /*!< 0x00200000 */
23155 #define IAC_ICR1_IACF53               IAC_ICR1_IACF53_Msk
23156 #define IAC_ICR1_IACF54_Pos           (22U)
23157 #define IAC_ICR1_IACF54_Msk           (0x1UL << IAC_ICR1_IACF54_Pos)              /*!< 0x00400000 */
23158 #define IAC_ICR1_IACF54               IAC_ICR1_IACF54_Msk
23159 #define IAC_ICR1_IACF55_Pos           (23U)
23160 #define IAC_ICR1_IACF55_Msk           (0x1UL << IAC_ICR1_IACF55_Pos)              /*!< 0x00800000 */
23161 #define IAC_ICR1_IACF55               IAC_ICR1_IACF55_Msk
23162 #define IAC_ICR1_IACF56_Pos           (24U)
23163 #define IAC_ICR1_IACF56_Msk           (0x1UL << IAC_ICR1_IACF56_Pos)              /*!< 0x01000000 */
23164 #define IAC_ICR1_IACF56               IAC_ICR1_IACF56_Msk
23165 #define IAC_ICR1_IACF57_Pos           (25U)
23166 #define IAC_ICR1_IACF57_Msk           (0x1UL << IAC_ICR1_IACF57_Pos)              /*!< 0x02000000 */
23167 #define IAC_ICR1_IACF57               IAC_ICR1_IACF57_Msk
23168 #define IAC_ICR1_IACF58_Pos           (26U)
23169 #define IAC_ICR1_IACF58_Msk           (0x1UL << IAC_ICR1_IACF58_Pos)              /*!< 0x04000000 */
23170 #define IAC_ICR1_IACF58               IAC_ICR1_IACF58_Msk
23171 #define IAC_ICR1_IACF60_Pos           (28U)
23172 #define IAC_ICR1_IACF60_Msk           (0x1UL << IAC_ICR1_IACF60_Pos)              /*!< 0x10000000 */
23173 #define IAC_ICR1_IACF60               IAC_ICR1_IACF60_Msk
23174 #define IAC_ICR1_IACF61_Pos           (29U)
23175 #define IAC_ICR1_IACF61_Msk           (0x1UL << IAC_ICR1_IACF61_Pos)              /*!< 0x20000000 */
23176 #define IAC_ICR1_IACF61               IAC_ICR1_IACF61_Msk
23177 #define IAC_ICR1_IACF62_Pos           (30U)
23178 #define IAC_ICR1_IACF62_Msk           (0x1UL << IAC_ICR1_IACF62_Pos)              /*!< 0x40000000 */
23179 #define IAC_ICR1_IACF62               IAC_ICR1_IACF62_Msk
23180 
23181 /*******************  Bits definition for IAC_ICR2 register *******************/
23182 #define IAC_ICR2_IACF64_Pos           (0U)
23183 #define IAC_ICR2_IACF64_Msk           (0x1UL << IAC_ICR2_IACF64_Pos)              /*!< 0x00000001 */
23184 #define IAC_ICR2_IACF64               IAC_ICR2_IACF64_Msk
23185 #define IAC_ICR2_IACF65_Pos           (1U)
23186 #define IAC_ICR2_IACF65_Msk           (0x1UL << IAC_ICR2_IACF65_Pos)              /*!< 0x00000002 */
23187 #define IAC_ICR2_IACF65               IAC_ICR2_IACF65_Msk
23188 #define IAC_ICR2_IACF67_Pos           (3U)
23189 #define IAC_ICR2_IACF67_Msk           (0x1UL << IAC_ICR2_IACF67_Pos)              /*!< 0x00000008 */
23190 #define IAC_ICR2_IACF67               IAC_ICR2_IACF67_Msk
23191 #define IAC_ICR2_IACF68_Pos           (4U)
23192 #define IAC_ICR2_IACF68_Msk           (0x1UL << IAC_ICR2_IACF68_Pos)              /*!< 0x00000010 */
23193 #define IAC_ICR2_IACF68               IAC_ICR2_IACF68_Msk
23194 #define IAC_ICR2_IACF69_Pos           (5U)
23195 #define IAC_ICR2_IACF69_Msk           (0x1UL << IAC_ICR2_IACF69_Pos)              /*!< 0x00000020 */
23196 #define IAC_ICR2_IACF69               IAC_ICR2_IACF69_Msk
23197 #define IAC_ICR2_IACF76_Pos           (12U)
23198 #define IAC_ICR2_IACF76_Msk           (0x1UL << IAC_ICR2_IACF76_Pos)              /*!< 0x00001000 */
23199 #define IAC_ICR2_IACF76               IAC_ICR2_IACF76_Msk
23200 #define IAC_ICR2_IACF77_Pos           (13U)
23201 #define IAC_ICR2_IACF77_Msk           (0x1UL << IAC_ICR2_IACF77_Pos)              /*!< 0x00002000 */
23202 #define IAC_ICR2_IACF77               IAC_ICR2_IACF77_Msk
23203 #define IAC_ICR2_IACF78_Pos           (14U)
23204 #define IAC_ICR2_IACF78_Msk           (0x1UL << IAC_ICR2_IACF78_Pos)              /*!< 0x00004000 */
23205 #define IAC_ICR2_IACF78               IAC_ICR2_IACF78_Msk
23206 #define IAC_ICR2_IACF79_Pos           (15U)
23207 #define IAC_ICR2_IACF79_Msk           (0x1UL << IAC_ICR2_IACF79_Pos)              /*!< 0x00008000 */
23208 #define IAC_ICR2_IACF79               IAC_ICR2_IACF79_Msk
23209 #define IAC_ICR2_IACF80_Pos           (16U)
23210 #define IAC_ICR2_IACF80_Msk           (0x1UL << IAC_ICR2_IACF80_Pos)              /*!< 0x00010000 */
23211 #define IAC_ICR2_IACF80               IAC_ICR2_IACF80_Msk
23212 #define IAC_ICR2_IACF81_Pos           (17U)
23213 #define IAC_ICR2_IACF81_Msk           (0x1UL << IAC_ICR2_IACF81_Pos)              /*!< 0x00020000 */
23214 #define IAC_ICR2_IACF81               IAC_ICR2_IACF81_Msk
23215 #define IAC_ICR2_IACF82_Pos           (18U)
23216 #define IAC_ICR2_IACF82_Msk           (0x1UL << IAC_ICR2_IACF82_Pos)              /*!< 0x00040000 */
23217 #define IAC_ICR2_IACF82               IAC_ICR2_IACF82_Msk
23218 #define IAC_ICR2_IACF83_Pos           (19U)
23219 #define IAC_ICR2_IACF83_Msk           (0x1UL << IAC_ICR2_IACF83_Pos)              /*!< 0x00080000 */
23220 #define IAC_ICR2_IACF83               IAC_ICR2_IACF83_Msk
23221 #define IAC_ICR2_IACF84_Pos           (20U)
23222 #define IAC_ICR2_IACF84_Msk           (0x1UL << IAC_ICR2_IACF84_Pos)              /*!< 0x00100000 */
23223 #define IAC_ICR2_IACF84               IAC_ICR2_IACF84_Msk
23224 #define IAC_ICR2_IACF86_Pos           (22U)
23225 #define IAC_ICR2_IACF86_Msk           (0x1UL << IAC_ICR2_IACF86_Pos)              /*!< 0x00400000 */
23226 #define IAC_ICR2_IACF86               IAC_ICR2_IACF86_Msk
23227 #define IAC_ICR2_IACF87_Pos           (23U)
23228 #define IAC_ICR2_IACF87_Msk           (0x1UL << IAC_ICR2_IACF87_Pos)              /*!< 0x00800000 */
23229 #define IAC_ICR2_IACF87               IAC_ICR2_IACF87_Msk
23230 #define IAC_ICR2_IACF88_Pos           (24U)
23231 #define IAC_ICR2_IACF88_Msk           (0x1UL << IAC_ICR2_IACF88_Pos)              /*!< 0x01000000 */
23232 #define IAC_ICR2_IACF88               IAC_ICR2_IACF88_Msk
23233 #define IAC_ICR2_IACF89_Pos           (25U)
23234 #define IAC_ICR2_IACF89_Msk           (0x1UL << IAC_ICR2_IACF89_Pos)              /*!< 0x02000000 */
23235 #define IAC_ICR2_IACF89               IAC_ICR2_IACF89_Msk
23236 #define IAC_ICR2_IACF90_Pos           (26U)
23237 #define IAC_ICR2_IACF90_Msk           (0x1UL << IAC_ICR2_IACF90_Pos)              /*!< 0x04000000 */
23238 #define IAC_ICR2_IACF90               IAC_ICR2_IACF90_Msk
23239 #define IAC_ICR2_IACF92_Pos           (28U)
23240 #define IAC_ICR2_IACF92_Msk           (0x1UL << IAC_ICR2_IACF92_Pos)              /*!< 0x10000000 */
23241 #define IAC_ICR2_IACF92               IAC_ICR2_IACF92_Msk
23242 #define IAC_ICR2_IACF93_Pos           (29U)
23243 #define IAC_ICR2_IACF93_Msk           (0x1UL << IAC_ICR2_IACF93_Pos)              /*!< 0x20000000 */
23244 #define IAC_ICR2_IACF93               IAC_ICR2_IACF93_Msk
23245 #define IAC_ICR2_IACF94_Pos           (30U)
23246 #define IAC_ICR2_IACF94_Msk           (0x1UL << IAC_ICR2_IACF94_Pos)              /*!< 0x40000000 */
23247 #define IAC_ICR2_IACF94               IAC_ICR2_IACF94_Msk
23248 #define IAC_ICR2_IACF95_Pos           (31U)
23249 #define IAC_ICR2_IACF95_Msk           (0x1UL << IAC_ICR2_IACF95_Pos)              /*!< 0x80000000 */
23250 #define IAC_ICR2_IACF95               IAC_ICR2_IACF95_Msk
23251 
23252 /*******************  Bits definition for IAC_ICR3 register *******************/
23253 #define IAC_ICR3_IACF96_Pos           (0U)
23254 #define IAC_ICR3_IACF96_Msk           (0x1UL << IAC_ICR3_IACF96_Pos)              /*!< 0x00000001 */
23255 #define IAC_ICR3_IACF96               IAC_ICR3_IACF96_Msk
23256 #define IAC_ICR3_IACF97_Pos           (1U)
23257 #define IAC_ICR3_IACF97_Msk           (0x1UL << IAC_ICR3_IACF97_Pos)              /*!< 0x00000002 */
23258 #define IAC_ICR3_IACF97               IAC_ICR3_IACF97_Msk
23259 #define IAC_ICR3_IACF98_Pos           (2U)
23260 #define IAC_ICR3_IACF98_Msk           (0x1UL << IAC_ICR3_IACF98_Pos)              /*!< 0x00000004 */
23261 #define IAC_ICR3_IACF98               IAC_ICR3_IACF98_Msk
23262 #define IAC_ICR3_IACF99_Pos           (3U)
23263 #define IAC_ICR3_IACF99_Msk           (0x1UL << IAC_ICR3_IACF99_Pos)              /*!< 0x00000008 */
23264 #define IAC_ICR3_IACF99               IAC_ICR3_IACF99_Msk
23265 #define IAC_ICR3_IACF100_Pos          (4U)
23266 #define IAC_ICR3_IACF100_Msk          (0x1UL << IAC_ICR3_IACF100_Pos)             /*!< 0x00000010 */
23267 #define IAC_ICR3_IACF100              IAC_ICR3_IACF100_Msk
23268 #define IAC_ICR3_IACF101_Pos          (5U)
23269 #define IAC_ICR3_IACF101_Msk          (0x1UL << IAC_ICR3_IACF101_Pos)             /*!< 0x00000020 */
23270 #define IAC_ICR3_IACF101              IAC_ICR3_IACF101_Msk
23271 #define IAC_ICR3_IACF102_Pos          (6U)
23272 #define IAC_ICR3_IACF102_Msk          (0x1UL << IAC_ICR3_IACF102_Pos)             /*!< 0x00000040 */
23273 #define IAC_ICR3_IACF102              IAC_ICR3_IACF102_Msk
23274 #define IAC_ICR3_IACF103_Pos          (7U)
23275 #define IAC_ICR3_IACF103_Msk          (0x1UL << IAC_ICR3_IACF103_Pos)             /*!< 0x00000080 */
23276 #define IAC_ICR3_IACF103              IAC_ICR3_IACF103_Msk
23277 #define IAC_ICR3_IACF104_Pos          (8U)
23278 #define IAC_ICR3_IACF104_Msk          (0x1UL << IAC_ICR3_IACF104_Pos)             /*!< 0x00000100 */
23279 #define IAC_ICR3_IACF104              IAC_ICR3_IACF104_Msk
23280 #define IAC_ICR3_IACF106_Pos          (10U)
23281 #define IAC_ICR3_IACF106_Msk          (0x1UL << IAC_ICR3_IACF106_Pos)             /*!< 0x00000400 */
23282 #define IAC_ICR3_IACF106              IAC_ICR3_IACF106_Msk
23283 
23284 /*******************  Bits definition for IAC_ICR4 register *******************/
23285 #define IAC_ICR4_IACF128_Pos          (0U)
23286 #define IAC_ICR4_IACF128_Msk          (0x1UL << IAC_ICR4_IACF128_Pos)             /*!< 0x00000001 */
23287 #define IAC_ICR4_IACF128              IAC_ICR4_IACF128_Msk
23288 #define IAC_ICR4_IACF129_Pos          (1U)
23289 #define IAC_ICR4_IACF129_Msk          (0x1UL << IAC_ICR4_IACF129_Pos)             /*!< 0x00000002 */
23290 #define IAC_ICR4_IACF129              IAC_ICR4_IACF129_Msk
23291 #define IAC_ICR4_IACF130_Pos          (2U)
23292 #define IAC_ICR4_IACF130_Msk          (0x1UL << IAC_ICR4_IACF130_Pos)             /*!< 0x00000004 */
23293 #define IAC_ICR4_IACF130              IAC_ICR4_IACF130_Msk
23294 #define IAC_ICR4_IACF131_Pos          (3U)
23295 #define IAC_ICR4_IACF131_Msk          (0x1UL << IAC_ICR4_IACF131_Pos)             /*!< 0x00000008 */
23296 #define IAC_ICR4_IACF131              IAC_ICR4_IACF131_Msk
23297 #define IAC_ICR4_IACF133_Pos          (5U)
23298 #define IAC_ICR4_IACF133_Msk          (0x1UL << IAC_ICR4_IACF133_Pos)             /*!< 0x00000020 */
23299 #define IAC_ICR4_IACF133              IAC_ICR4_IACF133_Msk
23300 #define IAC_ICR4_IACF134_Pos          (6U)
23301 #define IAC_ICR4_IACF134_Msk          (0x1UL << IAC_ICR4_IACF134_Pos)             /*!< 0x00000040 */
23302 #define IAC_ICR4_IACF134              IAC_ICR4_IACF134_Msk
23303 #define IAC_ICR4_IACF135_Pos          (7U)
23304 #define IAC_ICR4_IACF135_Msk          (0x1UL << IAC_ICR4_IACF135_Pos)             /*!< 0x00000080 */
23305 #define IAC_ICR4_IACF135              IAC_ICR4_IACF135_Msk
23306 #define IAC_ICR4_IACF136_Pos          (8U)
23307 #define IAC_ICR4_IACF136_Msk          (0x1UL << IAC_ICR4_IACF136_Pos)             /*!< 0x00000100 */
23308 #define IAC_ICR4_IACF136              IAC_ICR4_IACF136_Msk
23309 #define IAC_ICR4_IACF137_Pos          (9U)
23310 #define IAC_ICR4_IACF137_Msk          (0x1UL << IAC_ICR4_IACF137_Pos)             /*!< 0x00000200 */
23311 #define IAC_ICR4_IACF137              IAC_ICR4_IACF137_Msk
23312 #define IAC_ICR4_IACF138_Pos          (10U)
23313 #define IAC_ICR4_IACF138_Msk          (0x1UL << IAC_ICR4_IACF138_Pos)             /*!< 0x00000400 */
23314 #define IAC_ICR4_IACF138              IAC_ICR4_IACF138_Msk
23315 #define IAC_ICR4_IACF139_Pos          (11U)
23316 #define IAC_ICR4_IACF139_Msk          (0x1UL << IAC_ICR4_IACF139_Pos)             /*!< 0x00000800 */
23317 #define IAC_ICR4_IACF139              IAC_ICR4_IACF139_Msk
23318 #define IAC_ICR4_IACF140_Pos          (12U)
23319 #define IAC_ICR4_IACF140_Msk          (0x1UL << IAC_ICR4_IACF140_Pos)             /*!< 0x00001000 */
23320 #define IAC_ICR4_IACF140              IAC_ICR4_IACF140_Msk
23321 #define IAC_ICR4_IACF141_Pos          (13U)
23322 #define IAC_ICR4_IACF141_Msk          (0x1UL << IAC_ICR4_IACF141_Pos)             /*!< 0x00002000 */
23323 #define IAC_ICR4_IACF141              IAC_ICR4_IACF141_Msk
23324 #define IAC_ICR4_IACF142_Pos          (14U)
23325 #define IAC_ICR4_IACF142_Msk          (0x1UL << IAC_ICR4_IACF142_Pos)             /*!< 0x00004000 */
23326 #define IAC_ICR4_IACF142              IAC_ICR4_IACF142_Msk
23327 #define IAC_ICR4_IACF143_Pos          (15U)
23328 #define IAC_ICR4_IACF143_Msk          (0x1UL << IAC_ICR4_IACF143_Pos)             /*!< 0x00008000 */
23329 #define IAC_ICR4_IACF143              IAC_ICR4_IACF143_Msk
23330 #define IAC_ICR4_IACF144_Pos          (16U)
23331 #define IAC_ICR4_IACF144_Msk          (0x1UL << IAC_ICR4_IACF144_Pos)             /*!< 0x00010000 */
23332 #define IAC_ICR4_IACF144              IAC_ICR4_IACF144_Msk
23333 #define IAC_ICR4_IACF145_Pos          (17U)
23334 #define IAC_ICR4_IACF145_Msk          (0x1UL << IAC_ICR4_IACF145_Pos)             /*!< 0x00020000 */
23335 #define IAC_ICR4_IACF145              IAC_ICR4_IACF145_Msk
23336 #define IAC_ICR4_IACF146_Pos          (18U)
23337 #define IAC_ICR4_IACF146_Msk          (0x1UL << IAC_ICR4_IACF146_Pos)             /*!< 0x00040000 */
23338 #define IAC_ICR4_IACF146              IAC_ICR4_IACF146_Msk
23339 #define IAC_ICR4_IACF147_Pos          (19U)
23340 #define IAC_ICR4_IACF147_Msk          (0x1UL << IAC_ICR4_IACF147_Pos)             /*!< 0x00080000 */
23341 #define IAC_ICR4_IACF147              IAC_ICR4_IACF147_Msk
23342 #define IAC_ICR4_IACF149_Pos          (21U)
23343 #define IAC_ICR4_IACF149_Msk          (0x1UL << IAC_ICR4_IACF149_Pos)             /*!< 0x00200000 */
23344 #define IAC_ICR4_IACF149              IAC_ICR4_IACF149_Msk
23345 #define IAC_ICR4_IACF150_Pos          (22U)
23346 #define IAC_ICR4_IACF150_Msk          (0x1UL << IAC_ICR4_IACF150_Pos)             /*!< 0x00400000 */
23347 #define IAC_ICR4_IACF150              IAC_ICR4_IACF150_Msk
23348 #define IAC_ICR4_IACF151_Pos          (23U)
23349 #define IAC_ICR4_IACF151_Msk          (0x1UL << IAC_ICR4_IACF151_Pos)             /*!< 0x00800000 */
23350 #define IAC_ICR4_IACF151              IAC_ICR4_IACF151_Msk
23351 #define IAC_ICR4_IACF152_Pos          (24U)
23352 #define IAC_ICR4_IACF152_Msk          (0x1UL << IAC_ICR4_IACF152_Pos)             /*!< 0x01000000 */
23353 #define IAC_ICR4_IACF152              IAC_ICR4_IACF152_Msk
23354 #define IAC_ICR4_IACF153_Pos          (25U)
23355 #define IAC_ICR4_IACF153_Msk          (0x1UL << IAC_ICR4_IACF153_Pos)             /*!< 0x02000000 */
23356 #define IAC_ICR4_IACF153              IAC_ICR4_IACF153_Msk
23357 #define IAC_ICR4_IACF155_Pos          (27U)
23358 #define IAC_ICR4_IACF155_Msk          (0x1UL << IAC_ICR4_IACF155_Pos)             /*!< 0x08000000 */
23359 #define IAC_ICR4_IACF155              IAC_ICR4_IACF155_Msk
23360 #define IAC_ICR4_IACF156_Pos          (28U)
23361 #define IAC_ICR4_IACF156_Msk          (0x1UL << IAC_ICR4_IACF156_Pos)             /*!< 0x10000000 */
23362 #define IAC_ICR4_IACF156              IAC_ICR4_IACF156_Msk
23363 #define IAC_ICR4_IACF157_Pos          (29U)
23364 #define IAC_ICR4_IACF157_Msk          (0x1UL << IAC_ICR4_IACF157_Pos)             /*!< 0x20000000 */
23365 #define IAC_ICR4_IACF157              IAC_ICR4_IACF157_Msk
23366 
23367 
23368 /******************************************************************************/
23369 /*                                                                            */
23370 /*                                 ICACHE                                     */
23371 /*                                                                            */
23372 /******************************************************************************/
23373 /******************  Bit definition for ICACHE_CR register  *******************/
23374 #define ICACHE_CR_EN_Pos               (0U)
23375 #define ICACHE_CR_EN_Msk               (0x1UL << ICACHE_CR_EN_Pos)             /*!< 0x00000001 */
23376 #define ICACHE_CR_EN                   ICACHE_CR_EN_Msk                        /*!< Enable */
23377 #define ICACHE_CR_CACHEINV_Pos         (1U)
23378 #define ICACHE_CR_CACHEINV_Msk         (0x1UL << ICACHE_CR_CACHEINV_Pos)       /*!< 0x00000002 */
23379 #define ICACHE_CR_CACHEINV             ICACHE_CR_CACHEINV_Msk                  /*!< Cache invalidation */
23380 #define ICACHE_CR_WAYSEL_Pos           (2U)
23381 #define ICACHE_CR_WAYSEL_Msk           (0x1UL << ICACHE_CR_WAYSEL_Pos)         /*!< 0x00000004 */
23382 #define ICACHE_CR_WAYSEL               ICACHE_CR_WAYSEL_Msk                    /*!< Ways selection */
23383 #define ICACHE_CR_HITMEN_Pos           (16U)
23384 #define ICACHE_CR_HITMEN_Msk           (0x1UL << ICACHE_CR_HITMEN_Pos)         /*!< 0x00010000 */
23385 #define ICACHE_CR_HITMEN               ICACHE_CR_HITMEN_Msk                    /*!< Hit monitor enable */
23386 #define ICACHE_CR_MISSMEN_Pos          (17U)
23387 #define ICACHE_CR_MISSMEN_Msk          (0x1UL << ICACHE_CR_MISSMEN_Pos)        /*!< 0x00020000 */
23388 #define ICACHE_CR_MISSMEN              ICACHE_CR_MISSMEN_Msk                   /*!< Miss monitor enable */
23389 #define ICACHE_CR_HITMRST_Pos          (18U)
23390 #define ICACHE_CR_HITMRST_Msk          (0x1UL << ICACHE_CR_HITMRST_Pos)        /*!< 0x00040000 */
23391 #define ICACHE_CR_HITMRST              ICACHE_CR_HITMRST_Msk                   /*!< Hit monitor reset */
23392 #define ICACHE_CR_MISSMRST_Pos         (19U)
23393 #define ICACHE_CR_MISSMRST_Msk         (0x1UL << ICACHE_CR_MISSMRST_Pos)       /*!< 0x00080000 */
23394 #define ICACHE_CR_MISSMRST             ICACHE_CR_MISSMRST_Msk                  /*!< Miss monitor reset */
23395 
23396 /******************  Bit definition for ICACHE_SR register  *******************/
23397 #define ICACHE_SR_BUSYF_Pos            (0U)
23398 #define ICACHE_SR_BUSYF_Msk            (0x1UL << ICACHE_SR_BUSYF_Pos)          /*!< 0x00000001 */
23399 #define ICACHE_SR_BUSYF                ICACHE_SR_BUSYF_Msk                     /*!< Busy flag */
23400 #define ICACHE_SR_BSYENDF_Pos          (1U)
23401 #define ICACHE_SR_BSYENDF_Msk          (0x1UL << ICACHE_SR_BSYENDF_Pos)        /*!< 0x00000002 */
23402 #define ICACHE_SR_BSYENDF              ICACHE_SR_BSYENDF_Msk                   /*!< Busy end flag */
23403 #define ICACHE_SR_ERRF_Pos             (2U)
23404 #define ICACHE_SR_ERRF_Msk             (0x1UL << ICACHE_SR_ERRF_Pos)           /*!< 0x00000004 */
23405 #define ICACHE_SR_ERRF                 ICACHE_SR_ERRF_Msk                      /*!< Cache error flag */
23406 
23407 /******************  Bit definition for ICACHE_IER register  ******************/
23408 #define ICACHE_IER_BSYENDIE_Pos        (1U)
23409 #define ICACHE_IER_BSYENDIE_Msk        (0x1UL << ICACHE_IER_BSYENDIE_Pos)      /*!< 0x00000002 */
23410 #define ICACHE_IER_BSYENDIE            ICACHE_IER_BSYENDIE_Msk                 /*!< Busy end interrupt enable */
23411 #define ICACHE_IER_ERRIE_Pos           (2U)
23412 #define ICACHE_IER_ERRIE_Msk           (0x1UL << ICACHE_IER_ERRIE_Pos)         /*!< 0x00000004 */
23413 #define ICACHE_IER_ERRIE               ICACHE_IER_ERRIE_Msk                    /*!< Cache error interrupt enable */
23414 
23415 /******************  Bit definition for ICACHE_FCR register  ******************/
23416 #define ICACHE_FCR_CBSYENDF_Pos        (1U)
23417 #define ICACHE_FCR_CBSYENDF_Msk        (0x1UL << ICACHE_FCR_CBSYENDF_Pos)      /*!< 0x00000002 */
23418 #define ICACHE_FCR_CBSYENDF            ICACHE_FCR_CBSYENDF_Msk                 /*!< Busy end flag clear */
23419 #define ICACHE_FCR_CERRF_Pos           (2U)
23420 #define ICACHE_FCR_CERRF_Msk           (0x1UL << ICACHE_FCR_CERRF_Pos)         /*!< 0x00000004 */
23421 #define ICACHE_FCR_CERRF               ICACHE_FCR_CERRF_Msk                    /*!< Cache error flag clear */
23422 
23423 /******************  Bit definition for ICACHE_HMONR register  ****************/
23424 #define ICACHE_HMONR_HITMON_Pos         (0U)
23425 #define ICACHE_HMONR_HITMON_Msk         (0xFFFFFFFFUL << ICACHE_HMONR_HITMON_Pos)/*!< 0xFFFFFFFF */
23426 #define ICACHE_HMONR_HITMON             ICACHE_HMONR_HITMON_Msk                /*!< Cache hit monitor register */
23427 
23428 /******************  Bit definition for ICACHE_MMONR register  ****************/
23429 #define ICACHE_MMONR_MISSMON_Pos        (0U)
23430 #define ICACHE_MMONR_MISSMON_Msk        (0xFFFFUL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x0000FFFF */
23431 #define ICACHE_MMONR_MISSMON            ICACHE_MMONR_MISSMON_Msk               /*!< Cache miss monitor register */
23432 
23433 
23434 /******************************************************************************/
23435 /*                                                                            */
23436 /*                        Independent Watchdog (IWDG)                         */
23437 /*                                                                            */
23438 /******************************************************************************/
23439 /*******************  Bit definition for IWDG_KR register  ********************/
23440 #define IWDG_KR_KEY_Pos             (0U)
23441 #define IWDG_KR_KEY_Msk             (0xFFFFUL << IWDG_KR_KEY_Pos)          /*!< 0x0000FFFF */
23442 #define IWDG_KR_KEY                 IWDG_KR_KEY_Msk                       /*!< Key value (write only, read 0x0000) */
23443 
23444 /*******************  Bit definition for IWDG_PR register  ********************/
23445 #define IWDG_PR_PR_Pos              (0U)
23446 #define IWDG_PR_PR_Msk              (0xFUL << IWDG_PR_PR_Pos)              /*!< 0x0000000F */
23447 #define IWDG_PR_PR                  IWDG_PR_PR_Msk                        /*!< Prescaler divider */
23448 #define IWDG_PR_PR_0                (0x1UL << IWDG_PR_PR_Pos)              /*!< 0x00000001 */
23449 #define IWDG_PR_PR_1                (0x2UL << IWDG_PR_PR_Pos)              /*!< 0x00000002 */
23450 #define IWDG_PR_PR_2                (0x4UL << IWDG_PR_PR_Pos)              /*!< 0x00000004 */
23451 #define IWDG_PR_PR_3                (0x8UL << IWDG_PR_PR_Pos)              /*!< 0x00000008 */
23452 
23453 /*******************  Bit definition for IWDG_RLR register  *******************/
23454 #define IWDG_RLR_RL_Pos             (0U)
23455 #define IWDG_RLR_RL_Msk             (0xFFFUL << IWDG_RLR_RL_Pos)           /*!< 0x00000FFF */
23456 #define IWDG_RLR_RL                 IWDG_RLR_RL_Msk                       /*!< Watchdog counter reload value */
23457 
23458 /*******************  Bit definition for IWDG_SR register  ********************/
23459 #define IWDG_SR_PVU_Pos             (0U)
23460 #define IWDG_SR_PVU_Msk             (0x1UL << IWDG_SR_PVU_Pos)             /*!< 0x00000001 */
23461 #define IWDG_SR_PVU                 IWDG_SR_PVU_Msk                       /*!< Watchdog prescaler value update */
23462 #define IWDG_SR_RVU_Pos             (1U)
23463 #define IWDG_SR_RVU_Msk             (0x1UL << IWDG_SR_RVU_Pos)             /*!< 0x00000002 */
23464 #define IWDG_SR_RVU                 IWDG_SR_RVU_Msk                       /*!< Watchdog counter reload value update */
23465 #define IWDG_SR_WVU_Pos             (2U)
23466 #define IWDG_SR_WVU_Msk             (0x1UL << IWDG_SR_WVU_Pos)             /*!< 0x00000004 */
23467 #define IWDG_SR_WVU                 IWDG_SR_WVU_Msk                       /*!< Watchdog counter window value update */
23468 #define IWDG_SR_EWU_Pos             (3U)
23469 #define IWDG_SR_EWU_Msk             (0x1UL << IWDG_SR_EWU_Pos)             /*!< 0x00000008 */
23470 #define IWDG_SR_EWU                 IWDG_SR_EWU_Msk                       /*!< Watchdog interrupt comparator value update */
23471 #define IWDG_SR_ONF_Pos             (8U)
23472 #define IWDG_SR_ONF_Msk             (0x1UL << IWDG_SR_ONF_Pos)             /*!< 0x00000100 */
23473 #define IWDG_SR_ONF                 IWDG_SR_ONF_Msk                       /*!< Watchdog Enable status bit */
23474 #define IWDG_SR_EWIF_Pos            (15U)
23475 #define IWDG_SR_EWIF_Msk            (0x1UL << IWDG_SR_EWIF_Pos)            /*!< 0x00008000 */
23476 #define IWDG_SR_EWIF                IWDG_SR_EWIF_Msk                      /*!< Watchdog Early Interrupt flag */
23477 
23478 /******************  Bit definition for IWDG_WINR register  *******************/
23479 #define IWDG_WINR_WIN_Pos           (0U)
23480 #define IWDG_WINR_WIN_Msk           (0xFFFUL << IWDG_WINR_WIN_Pos)         /*!< 0x00000FFF */
23481 #define IWDG_WINR_WIN               IWDG_WINR_WIN_Msk                     /*!< Watchdog counter window value */
23482 
23483 /******************  Bit definition for IWDG_EWCR register  *******************/
23484 #define IWDG_EWCR_EWIT_Pos          (0U)
23485 #define IWDG_EWCR_EWIT_Msk          (0xFFFUL << IWDG_EWCR_EWIT_Pos)        /*!< 0x00000FFF */
23486 #define IWDG_EWCR_EWIT              IWDG_EWCR_EWIT_Msk                    /*!< Watchdog counter window value */
23487 #define IWDG_EWCR_EWIE_Pos          (15U)
23488 #define IWDG_EWCR_EWIE_Msk          (0x1UL << IWDG_EWCR_EWIE_Pos)          /*!< 0x00008000 */
23489 #define IWDG_EWCR_EWIE              IWDG_EWCR_EWIE_Msk                    /*!< Watchdog early interrupt enable */
23490 
23491 /*******************  Bit definition for IWDG_ICR register  *******************/
23492 #define IWDG_ICR_EWIC_Pos           (15U)
23493 #define IWDG_ICR_EWIC_Msk           (0x1UL << IWDG_ICR_EWIC_Pos)           /*!< 0x00008000 */
23494 #define IWDG_ICR_EWIC               IWDG_ICR_EWIC_Msk                     /*!< Watchdog early interrupt acknowledge */
23495 
23496 
23497 /******************************************************************************/
23498 /*                                                                            */
23499 /*                        JPEG Encoder/Decoder                                */
23500 /*                                                                            */
23501 /******************************************************************************/
23502 /********************  Bit definition for CONFR0 register  ********************/
23503 #define JPEG_CONFR0_START_Pos           (0U)
23504 #define JPEG_CONFR0_START_Msk           (0x1UL << JPEG_CONFR0_START_Pos)         /*!< 0x00000001 */
23505 #define JPEG_CONFR0_START               JPEG_CONFR0_START_Msk                    /*!<Start/Stop bit */
23506 
23507 /********************  Bit definition for CONFR1 register  ********************/
23508 #define JPEG_CONFR1_NF_Pos              (0U)
23509 #define JPEG_CONFR1_NF_Msk              (0x3UL << JPEG_CONFR1_NF_Pos)            /*!< 0x00000003 */
23510 #define JPEG_CONFR1_NF                  JPEG_CONFR1_NF_Msk                       /*!<Number of color components */
23511 #define JPEG_CONFR1_NF_0                (0x1UL << JPEG_CONFR1_NF_Pos)            /*!< 0x00000001 */
23512 #define JPEG_CONFR1_NF_1                (0x2UL << JPEG_CONFR1_NF_Pos)            /*!< 0x00000002 */
23513 #define JPEG_CONFR1_DE_Pos              (3U)
23514 #define JPEG_CONFR1_DE_Msk              (0x1UL << JPEG_CONFR1_DE_Pos)            /*!< 0x00000008 */
23515 #define JPEG_CONFR1_DE                  JPEG_CONFR1_DE_Msk                       /*!<Decoding Enable */
23516 #define JPEG_CONFR1_COLORSPACE_Pos      (4U)
23517 #define JPEG_CONFR1_COLORSPACE_Msk      (0x3UL << JPEG_CONFR1_COLORSPACE_Pos)    /*!< 0x00000030 */
23518 #define JPEG_CONFR1_COLORSPACE          JPEG_CONFR1_COLORSPACE_Msk               /*!<Color Space */
23519 #define JPEG_CONFR1_COLORSPACE_0        (0x1UL << JPEG_CONFR1_COLORSPACE_Pos)    /*!< 0x00000010 */
23520 #define JPEG_CONFR1_COLORSPACE_1        (0x2UL << JPEG_CONFR1_COLORSPACE_Pos)    /*!< 0x00000020 */
23521 #define JPEG_CONFR1_NS_Pos              (6U)
23522 #define JPEG_CONFR1_NS_Msk              (0x3UL << JPEG_CONFR1_NS_Pos)            /*!< 0x000000C0 */
23523 #define JPEG_CONFR1_NS                  JPEG_CONFR1_NS_Msk                       /*!<Number of components for Scan */
23524 #define JPEG_CONFR1_NS_0                (0x1UL << JPEG_CONFR1_NS_Pos)            /*!< 0x00000040 */
23525 #define JPEG_CONFR1_NS_1                (0x2UL << JPEG_CONFR1_NS_Pos)            /*!< 0x00000080 */
23526 #define JPEG_CONFR1_HDR_Pos             (8U)
23527 #define JPEG_CONFR1_HDR_Msk             (0x1UL << JPEG_CONFR1_HDR_Pos)           /*!< 0x00000100 */
23528 #define JPEG_CONFR1_HDR                 JPEG_CONFR1_HDR_Msk                      /*!<Header Processing On/Off */
23529 #define JPEG_CONFR1_YSIZE_Pos           (16U)
23530 #define JPEG_CONFR1_YSIZE_Msk           (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos)      /*!< 0xFFFF0000 */
23531 #define JPEG_CONFR1_YSIZE               JPEG_CONFR1_YSIZE_Msk                    /*!<Number of lines in source image */
23532 
23533 /********************  Bit definition for CONFR2 register  ********************/
23534 #define JPEG_CONFR2_NMCU_Pos            (0U)
23535 #define JPEG_CONFR2_NMCU_Msk            (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos)    /*!< 0x03FFFFFF */
23536 #define JPEG_CONFR2_NMCU                JPEG_CONFR2_NMCU_Msk                     /*!<Number of MCU units minus 1 to encode */
23537 
23538 /********************  Bit definition for CONFR3 register  ********************/
23539 #define JPEG_CONFR3_XSIZE_Pos           (16U)
23540 #define JPEG_CONFR3_XSIZE_Msk           (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos)      /*!< 0xFFFF0000 */
23541 #define JPEG_CONFR3_XSIZE               JPEG_CONFR3_XSIZE_Msk                    /*!<Number of pixels per line */
23542 
23543 /********************  Bit definition for CONFR4 register  ********************/
23544 #define JPEG_CONFR4_HD_Pos              (0U)
23545 #define JPEG_CONFR4_HD_Msk              (0x1UL << JPEG_CONFR4_HD_Pos)            /*!< 0x00000001 */
23546 #define JPEG_CONFR4_HD                  JPEG_CONFR4_HD_Msk                       /*!<Selects the Huffman table for encoding the DC coefficients */
23547 #define JPEG_CONFR4_HA_Pos              (1U)
23548 #define JPEG_CONFR4_HA_Msk              (0x1UL << JPEG_CONFR4_HA_Pos)            /*!< 0x00000002 */
23549 #define JPEG_CONFR4_HA                  JPEG_CONFR4_HA_Msk                       /*!<Selects the Huffman table for encoding the AC coefficients */
23550 #define JPEG_CONFR4_QT_Pos              (2U)
23551 #define JPEG_CONFR4_QT_Msk              (0x3UL << JPEG_CONFR4_QT_Pos)            /*!< 0x0000000C */
23552 #define JPEG_CONFR4_QT                  JPEG_CONFR4_QT_Msk                       /*!<Selects quantization table associated with a color component */
23553 #define JPEG_CONFR4_QT_0                (0x1UL << JPEG_CONFR4_QT_Pos)            /*!< 0x00000004 */
23554 #define JPEG_CONFR4_QT_1                (0x2UL << JPEG_CONFR4_QT_Pos)            /*!< 0x00000008 */
23555 #define JPEG_CONFR4_NB_Pos              (4U)
23556 #define JPEG_CONFR4_NB_Msk              (0xFUL << JPEG_CONFR4_NB_Pos)            /*!< 0x000000F0 */
23557 #define JPEG_CONFR4_NB                  JPEG_CONFR4_NB_Msk                       /*!<Number of data units minus 1 that belong to a particular color in the MCU */
23558 #define JPEG_CONFR4_NB_0                (0x1UL << JPEG_CONFR4_NB_Pos)            /*!< 0x00000010 */
23559 #define JPEG_CONFR4_NB_1                (0x2UL << JPEG_CONFR4_NB_Pos)            /*!< 0x00000020 */
23560 #define JPEG_CONFR4_NB_2                (0x4UL << JPEG_CONFR4_NB_Pos)            /*!< 0x00000040 */
23561 #define JPEG_CONFR4_NB_3                (0x8UL << JPEG_CONFR4_NB_Pos)            /*!< 0x00000080 */
23562 #define JPEG_CONFR4_VSF_Pos             (8U)
23563 #define JPEG_CONFR4_VSF_Msk             (0xFUL << JPEG_CONFR4_VSF_Pos)           /*!< 0x00000F00 */
23564 #define JPEG_CONFR4_VSF                 JPEG_CONFR4_VSF_Msk                      /*!<Vertical sampling factor for component 1 */
23565 #define JPEG_CONFR4_VSF_0               (0x1UL << JPEG_CONFR4_VSF_Pos)           /*!< 0x00000100 */
23566 #define JPEG_CONFR4_VSF_1               (0x2UL << JPEG_CONFR4_VSF_Pos)           /*!< 0x00000200 */
23567 #define JPEG_CONFR4_VSF_2               (0x4UL << JPEG_CONFR4_VSF_Pos)           /*!< 0x00000400 */
23568 #define JPEG_CONFR4_VSF_3               (0x8UL << JPEG_CONFR4_VSF_Pos)           /*!< 0x00000800 */
23569 #define JPEG_CONFR4_HSF_Pos             (12U)
23570 #define JPEG_CONFR4_HSF_Msk             (0xFUL << JPEG_CONFR4_HSF_Pos)           /*!< 0x0000F000 */
23571 #define JPEG_CONFR4_HSF                 JPEG_CONFR4_HSF_Msk                      /*!<Horizontal sampling factor for component 1 */
23572 #define JPEG_CONFR4_HSF_0               (0x1UL << JPEG_CONFR4_HSF_Pos)           /*!< 0x00001000 */
23573 #define JPEG_CONFR4_HSF_1               (0x2UL << JPEG_CONFR4_HSF_Pos)           /*!< 0x00002000 */
23574 #define JPEG_CONFR4_HSF_2               (0x4UL << JPEG_CONFR4_HSF_Pos)           /*!< 0x00004000 */
23575 #define JPEG_CONFR4_HSF_3               (0x8UL << JPEG_CONFR4_HSF_Pos)           /*!< 0x00008000 */
23576 
23577 /********************  Bit definition for CONFR5 register  ********************/
23578 #define JPEG_CONFR5_HD_Pos              (0U)
23579 #define JPEG_CONFR5_HD_Msk              (0x1UL << JPEG_CONFR5_HD_Pos)            /*!< 0x00000001 */
23580 #define JPEG_CONFR5_HD                  JPEG_CONFR5_HD_Msk                       /*!<Selects the Huffman table for encoding the DC coefficients */
23581 #define JPEG_CONFR5_HA_Pos              (1U)
23582 #define JPEG_CONFR5_HA_Msk              (0x1UL << JPEG_CONFR5_HA_Pos)            /*!< 0x00000002 */
23583 #define JPEG_CONFR5_HA                  JPEG_CONFR5_HA_Msk                       /*!<Selects the Huffman table for encoding the AC coefficients */
23584 #define JPEG_CONFR5_QT_Pos              (2U)
23585 #define JPEG_CONFR5_QT_Msk              (0x3UL << JPEG_CONFR5_QT_Pos)            /*!< 0x0000000C */
23586 #define JPEG_CONFR5_QT                  JPEG_CONFR5_QT_Msk                       /*!<Selects quantization table associated with a color component */
23587 #define JPEG_CONFR5_QT_0                (0x1UL << JPEG_CONFR5_QT_Pos)            /*!< 0x00000004 */
23588 #define JPEG_CONFR5_QT_1                (0x2UL << JPEG_CONFR5_QT_Pos)            /*!< 0x00000008 */
23589 #define JPEG_CONFR5_NB_Pos              (4U)
23590 #define JPEG_CONFR5_NB_Msk              (0xFUL << JPEG_CONFR5_NB_Pos)            /*!< 0x000000F0 */
23591 #define JPEG_CONFR5_NB                  JPEG_CONFR5_NB_Msk                       /*!<Number of data units minus 1 that belong to a particular color in the MCU */
23592 #define JPEG_CONFR5_NB_0                (0x1UL << JPEG_CONFR5_NB_Pos)            /*!< 0x00000010 */
23593 #define JPEG_CONFR5_NB_1                (0x2UL << JPEG_CONFR5_NB_Pos)            /*!< 0x00000020 */
23594 #define JPEG_CONFR5_NB_2                (0x4UL << JPEG_CONFR5_NB_Pos)            /*!< 0x00000040 */
23595 #define JPEG_CONFR5_NB_3                (0x8UL << JPEG_CONFR5_NB_Pos)            /*!< 0x00000080 */
23596 #define JPEG_CONFR5_VSF_Pos             (8U)
23597 #define JPEG_CONFR5_VSF_Msk             (0xFUL << JPEG_CONFR5_VSF_Pos)           /*!< 0x00000F00 */
23598 #define JPEG_CONFR5_VSF                 JPEG_CONFR5_VSF_Msk                      /*!<Vertical sampling factor for component 2 */
23599 #define JPEG_CONFR5_VSF_0               (0x1UL << JPEG_CONFR5_VSF_Pos)           /*!< 0x00000100 */
23600 #define JPEG_CONFR5_VSF_1               (0x2UL << JPEG_CONFR5_VSF_Pos)           /*!< 0x00000200 */
23601 #define JPEG_CONFR5_VSF_2               (0x4UL << JPEG_CONFR5_VSF_Pos)           /*!< 0x00000400 */
23602 #define JPEG_CONFR5_VSF_3               (0x8UL << JPEG_CONFR5_VSF_Pos)           /*!< 0x00000800 */
23603 #define JPEG_CONFR5_HSF_Pos             (12U)
23604 #define JPEG_CONFR5_HSF_Msk             (0xFUL << JPEG_CONFR5_HSF_Pos)           /*!< 0x0000F000 */
23605 #define JPEG_CONFR5_HSF                 JPEG_CONFR5_HSF_Msk                      /*!<Horizontal sampling factor for component 2 */
23606 #define JPEG_CONFR5_HSF_0               (0x1UL << JPEG_CONFR5_HSF_Pos)           /*!< 0x00001000 */
23607 #define JPEG_CONFR5_HSF_1               (0x2UL << JPEG_CONFR5_HSF_Pos)           /*!< 0x00002000 */
23608 #define JPEG_CONFR5_HSF_2               (0x4UL << JPEG_CONFR5_HSF_Pos)           /*!< 0x00004000 */
23609 #define JPEG_CONFR5_HSF_3               (0x8UL << JPEG_CONFR5_HSF_Pos)           /*!< 0x00008000 */
23610 
23611 /********************  Bit definition for CONFR6 register  ********************/
23612 #define JPEG_CONFR6_HD_Pos              (0U)
23613 #define JPEG_CONFR6_HD_Msk              (0x1UL << JPEG_CONFR6_HD_Pos)            /*!< 0x00000001 */
23614 #define JPEG_CONFR6_HD                  JPEG_CONFR6_HD_Msk                       /*!<Selects the Huffman table for encoding the DC coefficients */
23615 #define JPEG_CONFR6_HA_Pos              (1U)
23616 #define JPEG_CONFR6_HA_Msk              (0x1UL << JPEG_CONFR6_HA_Pos)            /*!< 0x00000002 */
23617 #define JPEG_CONFR6_HA                  JPEG_CONFR6_HA_Msk                       /*!<Selects the Huffman table for encoding the AC coefficients */
23618 #define JPEG_CONFR6_QT_Pos              (2U)
23619 #define JPEG_CONFR6_QT_Msk              (0x3UL << JPEG_CONFR6_QT_Pos)            /*!< 0x0000000C */
23620 #define JPEG_CONFR6_QT                  JPEG_CONFR6_QT_Msk                       /*!<Selects quantization table associated with a color component */
23621 #define JPEG_CONFR6_QT_0                (0x1UL << JPEG_CONFR6_QT_Pos)            /*!< 0x00000004 */
23622 #define JPEG_CONFR6_QT_1                (0x2UL << JPEG_CONFR6_QT_Pos)            /*!< 0x00000008 */
23623 #define JPEG_CONFR6_NB_Pos              (4U)
23624 #define JPEG_CONFR6_NB_Msk              (0xFUL << JPEG_CONFR6_NB_Pos)            /*!< 0x000000F0 */
23625 #define JPEG_CONFR6_NB                  JPEG_CONFR6_NB_Msk                       /*!<Number of data units minus 1 that belong to a particular color in the MCU */
23626 #define JPEG_CONFR6_NB_0                (0x1UL << JPEG_CONFR6_NB_Pos)            /*!< 0x00000010 */
23627 #define JPEG_CONFR6_NB_1                (0x2UL << JPEG_CONFR6_NB_Pos)            /*!< 0x00000020 */
23628 #define JPEG_CONFR6_NB_2                (0x4UL << JPEG_CONFR6_NB_Pos)            /*!< 0x00000040 */
23629 #define JPEG_CONFR6_NB_3                (0x8UL << JPEG_CONFR6_NB_Pos)            /*!< 0x00000080 */
23630 #define JPEG_CONFR6_VSF_Pos             (8U)
23631 #define JPEG_CONFR6_VSF_Msk             (0xFUL << JPEG_CONFR6_VSF_Pos)           /*!< 0x00000F00 */
23632 #define JPEG_CONFR6_VSF                 JPEG_CONFR6_VSF_Msk                      /*!<Vertical sampling factor for component 2 */
23633 #define JPEG_CONFR6_VSF_0               (0x1UL << JPEG_CONFR6_VSF_Pos)           /*!< 0x00000100 */
23634 #define JPEG_CONFR6_VSF_1               (0x2UL << JPEG_CONFR6_VSF_Pos)           /*!< 0x00000200 */
23635 #define JPEG_CONFR6_VSF_2               (0x4UL << JPEG_CONFR6_VSF_Pos)           /*!< 0x00000400 */
23636 #define JPEG_CONFR6_VSF_3               (0x8UL << JPEG_CONFR6_VSF_Pos)           /*!< 0x00000800 */
23637 #define JPEG_CONFR6_HSF_Pos             (12U)
23638 #define JPEG_CONFR6_HSF_Msk             (0xFUL << JPEG_CONFR6_HSF_Pos)           /*!< 0x0000F000 */
23639 #define JPEG_CONFR6_HSF                 JPEG_CONFR6_HSF_Msk                      /*!<Horizontal sampling factor for component 2 */
23640 #define JPEG_CONFR6_HSF_0               (0x1UL << JPEG_CONFR6_HSF_Pos)           /*!< 0x00001000 */
23641 #define JPEG_CONFR6_HSF_1               (0x2UL << JPEG_CONFR6_HSF_Pos)           /*!< 0x00002000 */
23642 #define JPEG_CONFR6_HSF_2               (0x4UL << JPEG_CONFR6_HSF_Pos)           /*!< 0x00004000 */
23643 #define JPEG_CONFR6_HSF_3               (0x8UL << JPEG_CONFR6_HSF_Pos)           /*!< 0x00008000 */
23644 
23645 /********************  Bit definition for CONFR7 register  ********************/
23646 #define JPEG_CONFR7_HD_Pos              (0U)
23647 #define JPEG_CONFR7_HD_Msk              (0x1UL << JPEG_CONFR7_HD_Pos)            /*!< 0x00000001 */
23648 #define JPEG_CONFR7_HD                  JPEG_CONFR7_HD_Msk                       /*!<Selects the Huffman table for encoding the DC coefficients */
23649 #define JPEG_CONFR7_HA_Pos              (1U)
23650 #define JPEG_CONFR7_HA_Msk              (0x1UL << JPEG_CONFR7_HA_Pos)            /*!< 0x00000002 */
23651 #define JPEG_CONFR7_HA                  JPEG_CONFR7_HA_Msk                       /*!<Selects the Huffman table for encoding the AC coefficients */
23652 #define JPEG_CONFR7_QT_Pos              (2U)
23653 #define JPEG_CONFR7_QT_Msk              (0x3UL << JPEG_CONFR7_QT_Pos)            /*!< 0x0000000C */
23654 #define JPEG_CONFR7_QT                  JPEG_CONFR7_QT_Msk                       /*!<Selects quantization table associated with a color component */
23655 #define JPEG_CONFR7_QT_0                (0x1UL << JPEG_CONFR7_QT_Pos)            /*!< 0x00000004 */
23656 #define JPEG_CONFR7_QT_1                (0x2UL << JPEG_CONFR7_QT_Pos)            /*!< 0x00000008 */
23657 #define JPEG_CONFR7_NB_Pos              (4U)
23658 #define JPEG_CONFR7_NB_Msk              (0xFUL << JPEG_CONFR7_NB_Pos)            /*!< 0x000000F0 */
23659 #define JPEG_CONFR7_NB                  JPEG_CONFR7_NB_Msk                       /*!<Number of data units minus 1 that belong to a particular color in the MCU */
23660 #define JPEG_CONFR7_NB_0                (0x1UL << JPEG_CONFR7_NB_Pos)            /*!< 0x00000010 */
23661 #define JPEG_CONFR7_NB_1                (0x2UL << JPEG_CONFR7_NB_Pos)            /*!< 0x00000020 */
23662 #define JPEG_CONFR7_NB_2                (0x4UL << JPEG_CONFR7_NB_Pos)            /*!< 0x00000040 */
23663 #define JPEG_CONFR7_NB_3                (0x8UL << JPEG_CONFR7_NB_Pos)            /*!< 0x00000080 */
23664 #define JPEG_CONFR7_VSF_Pos             (8U)
23665 #define JPEG_CONFR7_VSF_Msk             (0xFUL << JPEG_CONFR7_VSF_Pos)           /*!< 0x00000F00 */
23666 #define JPEG_CONFR7_VSF                 JPEG_CONFR7_VSF_Msk                      /*!<Vertical sampling factor for component 2 */
23667 #define JPEG_CONFR7_VSF_0               (0x1UL << JPEG_CONFR7_VSF_Pos)           /*!< 0x00000100 */
23668 #define JPEG_CONFR7_VSF_1               (0x2UL << JPEG_CONFR7_VSF_Pos)           /*!< 0x00000200 */
23669 #define JPEG_CONFR7_VSF_2               (0x4UL << JPEG_CONFR7_VSF_Pos)           /*!< 0x00000400 */
23670 #define JPEG_CONFR7_VSF_3               (0x8UL << JPEG_CONFR7_VSF_Pos)           /*!< 0x00000800 */
23671 #define JPEG_CONFR7_HSF_Pos             (12U)
23672 #define JPEG_CONFR7_HSF_Msk             (0xFUL << JPEG_CONFR7_HSF_Pos)           /*!< 0x0000F000 */
23673 #define JPEG_CONFR7_HSF                 JPEG_CONFR7_HSF_Msk                      /*!<Horizontal sampling factor for component 2 */
23674 #define JPEG_CONFR7_HSF_0               (0x1UL << JPEG_CONFR7_HSF_Pos)           /*!< 0x00001000 */
23675 #define JPEG_CONFR7_HSF_1               (0x2UL << JPEG_CONFR7_HSF_Pos)           /*!< 0x00002000 */
23676 #define JPEG_CONFR7_HSF_2               (0x4UL << JPEG_CONFR7_HSF_Pos)           /*!< 0x00004000 */
23677 #define JPEG_CONFR7_HSF_3               (0x8UL << JPEG_CONFR7_HSF_Pos)           /*!< 0x00008000 */
23678 
23679 /********************  Bit definition for CR register  ********************/
23680 #define JPEG_CR_JCEN_Pos                (0U)
23681 #define JPEG_CR_JCEN_Msk                (0x1UL << JPEG_CR_JCEN_Pos)              /*!< 0x00000001 */
23682 #define JPEG_CR_JCEN                    JPEG_CR_JCEN_Msk                         /*!<Enable the JPEG Codec Core */
23683 #define JPEG_CR_IFTIE_Pos               (1U)
23684 #define JPEG_CR_IFTIE_Msk               (0x1UL << JPEG_CR_IFTIE_Pos)             /*!< 0x00000002 */
23685 #define JPEG_CR_IFTIE                   JPEG_CR_IFTIE_Msk                        /*!<Input FIFO Threshold Interrupt Enable */
23686 #define JPEG_CR_IFNFIE_Pos              (2U)
23687 #define JPEG_CR_IFNFIE_Msk              (0x1UL << JPEG_CR_IFNFIE_Pos)            /*!< 0x00000004 */
23688 #define JPEG_CR_IFNFIE                  JPEG_CR_IFNFIE_Msk                       /*!<Input FIFO Not Full Interrupt Enable */
23689 #define JPEG_CR_OFTIE_Pos               (3U)
23690 #define JPEG_CR_OFTIE_Msk               (0x1UL << JPEG_CR_OFTIE_Pos)             /*!< 0x00000008 */
23691 #define JPEG_CR_OFTIE                   JPEG_CR_OFTIE_Msk                        /*!<Output FIFO Threshold Interrupt Enable */
23692 #define JPEG_CR_OFNEIE_Pos              (4U)
23693 #define JPEG_CR_OFNEIE_Msk              (0x1UL << JPEG_CR_OFNEIE_Pos)            /*!< 0x00000010 */
23694 #define JPEG_CR_OFNEIE                  JPEG_CR_OFNEIE_Msk                       /*!<Output FIFO Not Empty Interrupt Enable */
23695 #define JPEG_CR_EOCIE_Pos               (5U)
23696 #define JPEG_CR_EOCIE_Msk               (0x1UL << JPEG_CR_EOCIE_Pos)             /*!< 0x00000020 */
23697 #define JPEG_CR_EOCIE                   JPEG_CR_EOCIE_Msk                        /*!<End of Conversion Interrupt Enable */
23698 #define JPEG_CR_HPDIE_Pos               (6U)
23699 #define JPEG_CR_HPDIE_Msk               (0x1UL << JPEG_CR_HPDIE_Pos)             /*!< 0x00000040 */
23700 #define JPEG_CR_HPDIE                   JPEG_CR_HPDIE_Msk                        /*!<Header Parsing Done Interrupt Enable */
23701 #define JPEG_CR_IDMAEN_Pos              (11U)
23702 #define JPEG_CR_IDMAEN_Msk              (0x1UL << JPEG_CR_IDMAEN_Pos)            /*!< 0x00000800 */
23703 #define JPEG_CR_IDMAEN                  JPEG_CR_IDMAEN_Msk                       /*!<Input DMA enable */
23704 #define JPEG_CR_ODMAEN_Pos              (12U)
23705 #define JPEG_CR_ODMAEN_Msk              (0x1UL << JPEG_CR_ODMAEN_Pos)            /*!< 0x00001000 */
23706 #define JPEG_CR_ODMAEN                  JPEG_CR_ODMAEN_Msk                       /*!<Output DMA enable */
23707 #define JPEG_CR_IFF_Pos                 (13U)
23708 #define JPEG_CR_IFF_Msk                 (0x1UL << JPEG_CR_IFF_Pos)               /*!< 0x00002000 */
23709 #define JPEG_CR_IFF                     JPEG_CR_IFF_Msk                          /*!<Flush the input FIFO */
23710 #define JPEG_CR_OFF_Pos                 (14U)
23711 #define JPEG_CR_OFF_Msk                 (0x1UL << JPEG_CR_OFF_Pos)               /*!< 0x00004000 */
23712 #define JPEG_CR_OFF                     JPEG_CR_OFF_Msk                          /*!<Flush the output FIFO */
23713 
23714 /********************  Bit definition for SR register  ********************/
23715 #define JPEG_SR_IFTF_Pos                (1U)
23716 #define JPEG_SR_IFTF_Msk                (0x1UL << JPEG_SR_IFTF_Pos)              /*!< 0x00000002 */
23717 #define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                         /*!<Input FIFO is not full and is below its threshold flag */
23718 #define JPEG_SR_IFNFF_Pos               (2U)
23719 #define JPEG_SR_IFNFF_Msk               (0x1UL << JPEG_SR_IFNFF_Pos)             /*!< 0x00000004 */
23720 #define JPEG_SR_IFNFF                   JPEG_SR_IFNFF_Msk                        /*!<Input FIFO Not Full Flag, a data can be written */
23721 #define JPEG_SR_OFTF_Pos                (3U)
23722 #define JPEG_SR_OFTF_Msk                (0x1UL << JPEG_SR_OFTF_Pos)              /*!< 0x00000008 */
23723 #define JPEG_SR_OFTF                    JPEG_SR_OFTF_Msk                         /*!<Output FIFO is not empty and has reach its threshold */
23724 #define JPEG_SR_OFNEF_Pos               (4U)
23725 #define JPEG_SR_OFNEF_Msk               (0x1UL << JPEG_SR_OFNEF_Pos)             /*!< 0x00000010 */
23726 #define JPEG_SR_OFNEF                   JPEG_SR_OFNEF_Msk                        /*!<Output FIFO is not empty, a data is available */
23727 #define JPEG_SR_EOCF_Pos                (5U)
23728 #define JPEG_SR_EOCF_Msk                (0x1UL << JPEG_SR_EOCF_Pos)              /*!< 0x00000020 */
23729 #define JPEG_SR_EOCF                    JPEG_SR_EOCF_Msk                         /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */
23730 #define JPEG_SR_HPDF_Pos                (6U)
23731 #define JPEG_SR_HPDF_Msk                (0x1UL << JPEG_SR_HPDF_Pos)              /*!< 0x00000040 */
23732 #define JPEG_SR_HPDF                    JPEG_SR_HPDF_Msk                         /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */
23733 #define JPEG_SR_COF_Pos                 (7U)
23734 #define JPEG_SR_COF_Msk                 (0x1UL << JPEG_SR_COF_Pos)               /*!< 0x00000080 */
23735 #define JPEG_SR_COF                     JPEG_SR_COF_Msk                          /*!<JPEG Codec operation on going flag */
23736 
23737 /********************  Bit definition for CFR register  ********************/
23738 #define JPEG_CFR_CEOCF_Pos              (5U)
23739 #define JPEG_CFR_CEOCF_Msk              (0x1UL << JPEG_CFR_CEOCF_Pos)            /*!< 0x00000020 */
23740 #define JPEG_CFR_CEOCF                  JPEG_CFR_CEOCF_Msk                       /*!<Clear End of Conversion Flag */
23741 #define JPEG_CFR_CHPDF_Pos              (6U)
23742 #define JPEG_CFR_CHPDF_Msk              (0x1UL << JPEG_CFR_CHPDF_Pos)            /*!< 0x00000040 */
23743 #define JPEG_CFR_CHPDF                  JPEG_CFR_CHPDF_Msk                       /*!<Clear Header Parsing Done Flag */
23744 
23745 /********************  Bit definition for DIR register  ********************/
23746 #define JPEG_DIR_DATAIN_Pos             (0U)
23747 #define JPEG_DIR_DATAIN_Msk             (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos)    /*!< 0xFFFFFFFF */
23748 #define JPEG_DIR_DATAIN                 JPEG_DIR_DATAIN_Msk                      /*!<Data Input FIFO */
23749 
23750 /********************  Bit definition for DOR register  ********************/
23751 #define JPEG_DOR_DATAOUT_Pos            (0U)
23752 #define JPEG_DOR_DATAOUT_Msk            (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos)   /*!< 0xFFFFFFFF */
23753 #define JPEG_DOR_DATAOUT                JPEG_DOR_DATAOUT_Msk                     /*!<Data Output FIFO */
23754 
23755 
23756 /******************************************************************************/
23757 /*                                                                            */
23758 /*                         Low Power Timer (LPTIM)                            */
23759 /*                                                                            */
23760 /******************************************************************************/
23761 /******************  Bit definition for LPTIM_ISR register  *******************/
23762 #define LPTIM_ISR_CC1IF_Pos         (0U)
23763 #define LPTIM_ISR_CC1IF_Msk         (0x1UL << LPTIM_ISR_CC1IF_Pos)             /*!< 0x00000001 */
23764 #define LPTIM_ISR_CC1IF             LPTIM_ISR_CC1IF_Msk                        /*!< Capture/Compare 1 interrupt flag */
23765 #define LPTIM_ISR_ARRM_Pos          (1U)
23766 #define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */
23767 #define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
23768 #define LPTIM_ISR_EXTTRIG_Pos       (2U)
23769 #define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */
23770 #define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
23771 #define LPTIM_ISR_CMP1OK_Pos        (3U)
23772 #define LPTIM_ISR_CMP1OK_Msk        (0x1UL << LPTIM_ISR_CMP1OK_Pos)            /*!< 0x00000008 */
23773 #define LPTIM_ISR_CMP1OK            LPTIM_ISR_CMP1OK_Msk                       /*!< Compare register 1 update OK */
23774 #define LPTIM_ISR_ARROK_Pos         (4U)
23775 #define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */
23776 #define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
23777 #define LPTIM_ISR_UP_Pos            (5U)
23778 #define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */
23779 #define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
23780 #define LPTIM_ISR_DOWN_Pos          (6U)
23781 #define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */
23782 #define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
23783 #define LPTIM_ISR_UE_Pos            (7U)
23784 #define LPTIM_ISR_UE_Msk            (0x1UL << LPTIM_ISR_UE_Pos)                /*!< 0x00000080 */
23785 #define LPTIM_ISR_UE                LPTIM_ISR_UE_Msk                           /*!< Update event occurrence */
23786 #define LPTIM_ISR_REPOK_Pos         (8U)
23787 #define LPTIM_ISR_REPOK_Msk         (0x1UL << LPTIM_ISR_REPOK_Pos)             /*!< 0x00000100 */
23788 #define LPTIM_ISR_REPOK             LPTIM_ISR_REPOK_Msk                        /*!< Repetition register update OK */
23789 #define LPTIM_ISR_CC2IF_Pos         (9U)
23790 #define LPTIM_ISR_CC2IF_Msk         (0x1UL << LPTIM_ISR_CC2IF_Pos)             /*!< 0x00000200 */
23791 #define LPTIM_ISR_CC2IF             LPTIM_ISR_CC2IF_Msk                        /*!< Capture/Compare 2 interrupt flag */
23792 #define LPTIM_ISR_CC1OF_Pos         (12U)
23793 #define LPTIM_ISR_CC1OF_Msk         (0x1UL << LPTIM_ISR_CC1OF_Pos)             /*!< 0x00001000 */
23794 #define LPTIM_ISR_CC1OF             LPTIM_ISR_CC1OF_Msk                        /*!< Capture/Compare 1 over-capture flag */
23795 #define LPTIM_ISR_CC2OF_Pos         (13U)
23796 #define LPTIM_ISR_CC2OF_Msk         (0x1UL << LPTIM_ISR_CC2OF_Pos)             /*!< 0x00002000 */
23797 #define LPTIM_ISR_CC2OF             LPTIM_ISR_CC2OF_Msk                        /*!< Capture/Compare 2 over-capture flag */
23798 #define LPTIM_ISR_CMP2OK_Pos        (19U)
23799 #define LPTIM_ISR_CMP2OK_Msk        (0x1UL << LPTIM_ISR_CMP2OK_Pos)            /*!< 0x00080000 */
23800 #define LPTIM_ISR_CMP2OK            LPTIM_ISR_CMP2OK_Msk                       /*!< Compare register 2 update OK */
23801 #define LPTIM_ISR_DIEROK_Pos        (24U)
23802 #define LPTIM_ISR_DIEROK_Msk        (0x1UL << LPTIM_ISR_DIEROK_Pos)            /*!< 0x01000000 */
23803 #define LPTIM_ISR_DIEROK            LPTIM_ISR_DIEROK_Msk                       /*!< Interrupt enable register update OK */
23804 
23805 /******************  Bit definition for LPTIM_ICR register  *******************/
23806 #define LPTIM_ICR_CC1CF_Pos         (0U)
23807 #define LPTIM_ICR_CC1CF_Msk         (0x1UL << LPTIM_ICR_CC1CF_Pos)             /*!< 0x00000001 */
23808 #define LPTIM_ICR_CC1CF              LPTIM_ICR_CC1CF_Msk                       /*!< Capture/Compare 1 clear flag  */
23809 #define LPTIM_ICR_ARRMCF_Pos        (1U)
23810 #define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */
23811 #define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
23812 #define LPTIM_ICR_EXTTRIGCF_Pos     (2U)
23813 #define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */
23814 #define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
23815 #define LPTIM_ICR_CMP1OKCF_Pos      (3U)
23816 #define LPTIM_ICR_CMP1OKCF_Msk      (0x1UL << LPTIM_ICR_CMP1OKCF_Pos)          /*!< 0x00000008 */
23817 #define LPTIM_ICR_CMP1OKCF          LPTIM_ICR_CMP1OKCF_Msk                     /*!< Compare register 1 update OK clear flag */
23818 #define LPTIM_ICR_ARROKCF_Pos       (4U)
23819 #define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */
23820 #define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
23821 #define LPTIM_ICR_UPCF_Pos          (5U)
23822 #define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */
23823 #define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
23824 #define LPTIM_ICR_DOWNCF_Pos        (6U)
23825 #define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */
23826 #define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
23827 #define LPTIM_ICR_UECF_Pos          (7U)
23828 #define LPTIM_ICR_UECF_Msk          (0x1UL << LPTIM_ICR_UECF_Pos)              /*!< 0x00000080 */
23829 #define LPTIM_ICR_UECF              LPTIM_ICR_UECF_Msk                         /*!< Update event Clear Flag */
23830 #define LPTIM_ICR_REPOKCF_Pos       (8U)
23831 #define LPTIM_ICR_REPOKCF_Msk       (0x1UL << LPTIM_ICR_REPOKCF_Pos)           /*!< 0x00000100 */
23832 #define LPTIM_ICR_REPOKCF           LPTIM_ICR_REPOKCF_Msk                      /*!< Repetition register update OK Clear Flag */
23833 #define LPTIM_ICR_CC2CF_Pos         (9U)
23834 #define LPTIM_ICR_CC2CF_Msk         (0x1UL << LPTIM_ICR_CC2CF_Pos)             /*!< 0x00000200 */
23835 #define LPTIM_ICR_CC2CF             LPTIM_ICR_CC2CF_Msk                        /*!< Capture/Compare 2 clear flag  */
23836 #define LPTIM_ICR_CC1OCF_Pos        (12U)
23837 #define LPTIM_ICR_CC1OCF_Msk        (0x1UL << LPTIM_ICR_CC1OCF_Pos)            /*!< 0x00001000 */
23838 #define LPTIM_ICR_CC1OCF            LPTIM_ICR_CC1OCF_Msk                       /*!< Capture/Compare 1 over-capture clear flag */
23839 #define LPTIM_ICR_CC2OCF_Pos        (13U)
23840 #define LPTIM_ICR_CC2OCF_Msk        (0x1UL << LPTIM_ICR_CC2OCF_Pos)            /*!< 0x00002000 */
23841 #define LPTIM_ICR_CC2OCF            LPTIM_ICR_CC2OCF_Msk                       /*!< Capture/Compare 2 over-capture clear flag */
23842 #define LPTIM_ICR_CMP2OKCF_Pos      (19U)
23843 #define LPTIM_ICR_CMP2OKCF_Msk      (0x1UL << LPTIM_ICR_CMP2OKCF_Pos)          /*!< 0x00080000 */
23844 #define LPTIM_ICR_CMP2OKCF          LPTIM_ICR_CMP2OKCF_Msk                     /*!< Compare register 2 update OK clear flag */
23845 #define LPTIM_ICR_DIEROKCF_Pos      (24U)
23846 #define LPTIM_ICR_DIEROKCF_Msk      (0x1UL << LPTIM_ICR_DIEROKCF_Pos)          /*!< 0x01000000 */
23847 #define LPTIM_ICR_DIEROKCF          LPTIM_ICR_DIEROKCF_Msk                     /*!< Interrupt enable register update OK clear flag */
23848 
23849 /******************  Bit definition for LPTIM_DIER register *******************/
23850 #define LPTIM_DIER_CC1IE_Pos        (0U)
23851 #define LPTIM_DIER_CC1IE_Msk        (0x1UL << LPTIM_DIER_CC1IE_Pos)            /*!< 0x00000001 */
23852 #define LPTIM_DIER_CC1IE            LPTIM_DIER_CC1IE_Msk                       /*!< Compare/Compare interrupt enable */
23853 #define LPTIM_DIER_ARRMIE_Pos        (1U)
23854 #define LPTIM_DIER_ARRMIE_Msk       (0x1UL << LPTIM_DIER_ARRMIE_Pos)           /*!< 0x00000002 */
23855 #define LPTIM_DIER_ARRMIE           LPTIM_DIER_ARRMIE_Msk                      /*!< Autoreload match Interrupt Enable */
23856 #define LPTIM_DIER_EXTTRIGIE_Pos    (2U)
23857 #define LPTIM_DIER_EXTTRIGIE_Msk    (0x1UL << LPTIM_DIER_EXTTRIGIE_Pos)        /*!< 0x00000004 */
23858 #define LPTIM_DIER_EXTTRIGIE        LPTIM_DIER_EXTTRIGIE_Msk                   /*!< External trigger edge event Interrupt Enable */
23859 #define LPTIM_DIER_CMP1OKIE_Pos     (3U)
23860 #define LPTIM_DIER_CMP1OKIE_Msk     (0x1UL << LPTIM_DIER_CMP1OKIE_Pos)         /*!< 0x00000008 */
23861 #define LPTIM_DIER_CMP1OKIE         LPTIM_DIER_CMP1OKIE_Msk                    /*!< Compare register 1 update OK interrupt enable */
23862 #define LPTIM_DIER_ARROKIE_Pos      (4U)
23863 #define LPTIM_DIER_ARROKIE_Msk      (0x1UL << LPTIM_DIER_ARROKIE_Pos)          /*!< 0x00000010 */
23864 #define LPTIM_DIER_ARROKIE          LPTIM_DIER_ARROKIE_Msk                     /*!< Autoreload register update OK Interrupt Enable */
23865 #define LPTIM_DIER_UPIE_Pos         (5U)
23866 #define LPTIM_DIER_UPIE_Msk         (0x1UL << LPTIM_DIER_UPIE_Pos)             /*!< 0x00000020 */
23867 #define LPTIM_DIER_UPIE             LPTIM_DIER_UPIE_Msk                        /*!< Counter direction change down to up Interrupt Enable */
23868 #define LPTIM_DIER_DOWNIE_Pos       (6U)
23869 #define LPTIM_DIER_DOWNIE_Msk       (0x1UL << LPTIM_DIER_DOWNIE_Pos)           /*!< 0x00000040 */
23870 #define LPTIM_DIER_DOWNIE           LPTIM_DIER_DOWNIE_Msk                      /*!< Counter direction change up to down Interrupt Enable */
23871 #define LPTIM_DIER_UEIE_Pos         (7U)
23872 #define LPTIM_DIER_UEIE_Msk         (0x1UL << LPTIM_DIER_UEIE_Pos)             /*!< 0x00000080 */
23873 #define LPTIM_DIER_UEIE             LPTIM_DIER_UEIE_Msk                        /*!< Update event Interrupt Enable */
23874 #define LPTIM_DIER_REPOKIE_Pos      (8U)
23875 #define LPTIM_DIER_REPOKIE_Msk      (0x1UL << LPTIM_DIER_REPOKIE_Pos)          /*!< 0x00000100 */
23876 #define LPTIM_DIER_REPOKIE          LPTIM_DIER_REPOKIE_Msk                     /*!< Repetition register update OK Interrupt Enable */
23877 #define LPTIM_DIER_CC2IE_Pos        (9U)
23878 #define LPTIM_DIER_CC2IE_Msk        (0x1UL << LPTIM_DIER_CC2IE_Pos)            /*!< 0x00000200 */
23879 #define LPTIM_DIER_CC2IE            LPTIM_DIER_CC2IE_Msk                       /*!< Capture/Compare 2 interrupt interrupt enable */
23880 #define LPTIM_DIER_CC1OIE_Pos       (12U)
23881 #define LPTIM_DIER_CC1OIE_Msk       (0x1UL << LPTIM_DIER_CC1OIE_Pos)           /*!< 0x00001000 */
23882 #define LPTIM_DIER_CC1OIE           LPTIM_DIER_CC1OIE_Msk                      /*!< Capture/Compare 1 over-capture interrupt enable */
23883 #define LPTIM_DIER_CC2OIE_Pos       (13U)
23884 #define LPTIM_DIER_CC2OIE_Msk       (0x1UL << LPTIM_DIER_CC2OIE_Pos)           /*!< 0x00002000 */
23885 #define LPTIM_DIER_CC2OIE           LPTIM_DIER_CC2OIE_Msk                      /*!< Capture/Compare 2 over-capture interrupt enable */
23886 #define LPTIM_DIER_CC1DE_Pos        (16U)
23887 #define LPTIM_DIER_CC1DE_Msk        (0x1UL << LPTIM_DIER_CC1DE_Pos)            /*!< 0x00010000 */
23888 #define LPTIM_DIER_CC1DE            LPTIM_DIER_CC1DE_Msk                       /*!< Capture/Compare 1 DMA request enable */
23889 #define LPTIM_DIER_CMP2OKIE_Pos     (19U)
23890 #define LPTIM_DIER_CMP2OKIE_Msk     (0x1UL << LPTIM_DIER_CMP2OKIE_Pos)         /*!< 0x00080000 */
23891 #define LPTIM_DIER_CMP2OKIE         LPTIM_DIER_CMP2OKIE_Msk                    /*!< Compare register 2 update OK interrupt enable */
23892 #define LPTIM_DIER_UEDE_Pos         (23U)
23893 #define LPTIM_DIER_UEDE_Msk         (0x1UL << LPTIM_DIER_UEDE_Pos)             /*!< 0x00800000 */
23894 #define LPTIM_DIER_UEDE             LPTIM_DIER_UEDE_Msk                        /*!< Update event DMA request enable */
23895 #define LPTIM_DIER_CC2DE_Pos        (25U)
23896 #define LPTIM_DIER_CC2DE_Msk        (0x1UL << LPTIM_DIER_CC2DE_Pos)            /*!< 0x02000000 */
23897 #define LPTIM_DIER_CC2DE            LPTIM_DIER_CC2DE_Msk                       /*!< Capture/Compare 2 DMA request enable */
23898 
23899 /******************  Bit definition for LPTIM_CFGR register *******************/
23900 #define LPTIM_CFGR_CKSEL_Pos        (0U)
23901 #define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */
23902 #define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
23903 #define LPTIM_CFGR_CKPOL_Pos        (1U)
23904 #define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */
23905 #define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
23906 #define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000002 */
23907 #define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000004 */
23908 #define LPTIM_CFGR_CKFLT_Pos        (3U)
23909 #define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */
23910 #define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
23911 #define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000008 */
23912 #define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000010 */
23913 #define LPTIM_CFGR_TRGFLT_Pos       (6U)
23914 #define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */
23915 #define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
23916 #define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x00000040 */
23917 #define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x00000080 */
23918 #define LPTIM_CFGR_PRESC_Pos        (9U)
23919 #define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */
23920 #define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
23921 #define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000200 */
23922 #define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000400 */
23923 #define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000800 */
23924 #define LPTIM_CFGR_TRIGSEL_Pos      (13U)
23925 #define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x0000E000 */
23926 #define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
23927 #define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00002000 */
23928 #define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00004000 */
23929 #define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00008000 */
23930 #define LPTIM_CFGR_TRIGEN_Pos       (17U)
23931 #define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */
23932 #define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
23933 #define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00020000 */
23934 #define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00040000 */
23935 #define LPTIM_CFGR_TIMOUT_Pos       (19U)
23936 #define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */
23937 #define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
23938 #define LPTIM_CFGR_WAVE_Pos         (20U)
23939 #define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */
23940 #define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
23941 #define LPTIM_CFGR_WAVPOL_Pos       (21U)
23942 #define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */
23943 #define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
23944 #define LPTIM_CFGR_PRELOAD_Pos      (22U)
23945 #define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */
23946 #define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
23947 #define LPTIM_CFGR_COUNTMODE_Pos    (23U)
23948 #define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */
23949 #define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
23950 #define LPTIM_CFGR_ENC_Pos          (24U)
23951 #define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */
23952 #define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
23953 
23954 /******************  Bit definition for LPTIM_CR register  ********************/
23955 #define LPTIM_CR_ENABLE_Pos         (0U)
23956 #define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */
23957 #define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
23958 #define LPTIM_CR_SNGSTRT_Pos        (1U)
23959 #define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)            /*!< 0x00000002 */
23960 #define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
23961 #define LPTIM_CR_CNTSTRT_Pos        (2U)
23962 #define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */
23963 #define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
23964 #define LPTIM_CR_COUNTRST_Pos       (3U)
23965 #define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */
23966 #define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Counter reset */
23967 #define LPTIM_CR_RSTARE_Pos         (4U)
23968 #define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */
23969 #define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Reset after read enable */
23970 
23971 /******************  Bit definition for LPTIM_CMP register  *******************/
23972 #define LPTIM_CCR1_CCR1_Pos           (0U)
23973 #define LPTIM_CCR1_CCR1_Msk           (0xFFFFUL << LPTIM_CCR1_CCR1_Pos)        /*!< 0x0000FFFF */
23974 #define LPTIM_CCR1_CCR1               LPTIM_CCR1_CCR1_Msk                      /*!< Compare register 1 */
23975 
23976 /******************  Bit definition for LPTIM_ARR register  *******************/
23977 #define LPTIM_ARR_ARR_Pos           (0U)
23978 #define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */
23979 #define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
23980 
23981 /******************  Bit definition for LPTIM_CNT register  *******************/
23982 #define LPTIM_CNT_CNT_Pos           (0U)
23983 #define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */
23984 #define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
23985 
23986 /******************  Bit definition for LPTIM_CFGR2 register  *****************/
23987 #define LPTIM_CFGR2_IN1SEL_Pos      (0U)
23988 #define LPTIM_CFGR2_IN1SEL_Msk      (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000003 */
23989 #define LPTIM_CFGR2_IN1SEL          LPTIM_CFGR2_IN1SEL_Msk                     /*!< IN1SEL[1:0] bits (Remap selection) */
23990 #define LPTIM_CFGR2_IN1SEL_0        (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000001 */
23991 #define LPTIM_CFGR2_IN1SEL_1        (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000002 */
23992 #define LPTIM_CFGR2_IN2SEL_Pos      (4U)
23993 #define LPTIM_CFGR2_IN2SEL_Msk      (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000030 */
23994 #define LPTIM_CFGR2_IN2SEL          LPTIM_CFGR2_IN2SEL_Msk                     /*!< IN2SEL[5:4] bits (Remap selection) */
23995 #define LPTIM_CFGR2_IN2SEL_0        (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000010 */
23996 #define LPTIM_CFGR2_IN2SEL_1        (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000020 */
23997 #define LPTIM_CFGR2_IC1SEL_Pos      (16U)
23998 #define LPTIM_CFGR2_IC1SEL_Msk      (0x3UL << LPTIM_CFGR2_IC1SEL_Pos)          /*!< 0x00000003 */
23999 #define LPTIM_CFGR2_IC1SEL          LPTIM_CFGR2_IC1SEL_Msk                     /*!< IC1SEL[17:16] bits */
24000 #define LPTIM_CFGR2_IC1SEL_0        (0x1UL << LPTIM_CFGR2_IC1SEL_Pos)          /*!< 0x00010000 */
24001 #define LPTIM_CFGR2_IC1SEL_1        (0x2UL << LPTIM_CFGR2_IC1SEL_Pos)          /*!< 0x00020000 */
24002 #define LPTIM_CFGR2_IC2SEL_Pos      (20U)
24003 #define LPTIM_CFGR2_IC2SEL_Msk      (0x3UL << LPTIM_CFGR2_IC2SEL_Pos)          /*!< 0x00000030 */
24004 #define LPTIM_CFGR2_IC2SEL          LPTIM_CFGR2_IC2SEL_Msk                     /*!< IC2SEL[21:20] bits */
24005 #define LPTIM_CFGR2_IC2SEL_0        (0x1UL << LPTIM_CFGR2_IC2SEL_Pos)          /*!< 0x00100000 */
24006 #define LPTIM_CFGR2_IC2SEL_1        (0x2UL << LPTIM_CFGR2_IC2SEL_Pos)          /*!< 0x00200000 */
24007 
24008 /******************  Bit definition for LPTIM_RCR register  *******************/
24009 #define LPTIM_RCR_REP_Pos           (0U)
24010 #define LPTIM_RCR_REP_Msk           (0xFFUL << LPTIM_RCR_REP_Pos)              /*!< 0x000000FF */
24011 #define LPTIM_RCR_REP               LPTIM_RCR_REP_Msk                          /*!< Repetition Counter Value */
24012 
24013 /*****************  Bit definition for LPTIM_CCMR1 register  ******************/
24014 #define LPTIM_CCMR1_CC1SEL_Pos      (0U)
24015 #define LPTIM_CCMR1_CC1SEL_Msk      (0x1UL << LPTIM_CCMR1_CC1SEL_Pos)          /*!< 0x00000001 */
24016 #define LPTIM_CCMR1_CC1SEL          LPTIM_CCMR1_CC1SEL_Msk                     /*!< Capture/Compare 1 selection */
24017 #define LPTIM_CCMR1_CC1E_Pos        (1U)
24018 #define LPTIM_CCMR1_CC1E_Msk        (0x1UL << LPTIM_CCMR1_CC1E_Pos)            /*!< 0x00000002 */
24019 #define LPTIM_CCMR1_CC1E            LPTIM_CCMR1_CC1E_Msk                       /*!< Capture/Compare 1 output enable */
24020 #define LPTIM_CCMR1_CC1P_Pos        (2U)
24021 #define LPTIM_CCMR1_CC1P_Msk        (0x3UL << LPTIM_CCMR1_CC1P_Pos)            /*!< 0x0000000C */
24022 #define LPTIM_CCMR1_CC1P            LPTIM_CCMR1_CC1P_Msk                       /*!< Capture/Compare 1 output polarity */
24023 #define LPTIM_CCMR1_CC1P_0          (0x1UL << LPTIM_CCMR1_CC1P_Pos)            /*!< 0x00000004 */
24024 #define LPTIM_CCMR1_CC1P_1          (0x2UL << LPTIM_CCMR1_CC1P_Pos)            /*!< 0x00000008 */
24025 #define LPTIM_CCMR1_IC1PSC_Pos      (8U)
24026 #define LPTIM_CCMR1_IC1PSC_Msk      (0x3UL << LPTIM_CCMR1_IC1PSC_Pos)          /*!< 0x00000300 */
24027 #define LPTIM_CCMR1_IC1PSC          LPTIM_CCMR1_IC1PSC_Msk                     /*!< Input capture 1 prescaler */
24028 #define LPTIM_CCMR1_IC1PSC_0        (0x1UL << LPTIM_CCMR1_IC1PSC_Pos)          /*!< 0x00000100 */
24029 #define LPTIM_CCMR1_IC1PSC_1        (0x2UL << LPTIM_CCMR1_IC1PSC_Pos)          /*!< 0x00000200 */
24030 #define LPTIM_CCMR1_IC1F_Pos        (12U)
24031 #define LPTIM_CCMR1_IC1F_Msk        (0x3UL << LPTIM_CCMR1_IC1F_Pos)            /*!< 0x00003000 */
24032 #define LPTIM_CCMR1_IC1F            LPTIM_CCMR1_IC1F_Msk                       /*!< Input capture 1 filter */
24033 #define LPTIM_CCMR1_IC1F_0          (0x1UL << LPTIM_CCMR1_IC1F_Pos)            /*!< 0x00001000 */
24034 #define LPTIM_CCMR1_IC1F_1          (0x2UL << LPTIM_CCMR1_IC1F_Pos)            /*!< 0x00002000 */
24035 #define LPTIM_CCMR1_CC2SEL_Pos      (16U)
24036 #define LPTIM_CCMR1_CC2SEL_Msk      (0x1UL << LPTIM_CCMR1_CC2SEL_Pos)          /*!< 0x00010000 */
24037 #define LPTIM_CCMR1_CC2SEL          LPTIM_CCMR1_CC2SEL_Msk                     /*!< Capture/Compare 2 selection */
24038 #define LPTIM_CCMR1_CC2E_Pos        (17U)
24039 #define LPTIM_CCMR1_CC2E_Msk        (0x1UL << LPTIM_CCMR1_CC2E_Pos)            /*!< 0x00020000 */
24040 #define LPTIM_CCMR1_CC2E            LPTIM_CCMR1_CC2E_Msk                       /*!< Capture/Compare 2 output enable */
24041 #define LPTIM_CCMR1_CC2P_Pos        (18U)
24042 #define LPTIM_CCMR1_CC2P_Msk        (0x3UL << LPTIM_CCMR1_CC2P_Pos)            /*!< 0x000C0000 */
24043 #define LPTIM_CCMR1_CC2P            LPTIM_CCMR1_CC2P_Msk                       /*!< Capture/Compare 2 output polarity */
24044 #define LPTIM_CCMR1_CC2P_0          (0x1UL << LPTIM_CCMR1_CC2P_Pos)            /*!< 0x00040000 */
24045 #define LPTIM_CCMR1_CC2P_1          (0x2UL << LPTIM_CCMR1_CC2P_Pos)            /*!< 0x00080000 */
24046 #define LPTIM_CCMR1_IC2PSC_Pos      (24U)
24047 #define LPTIM_CCMR1_IC2PSC_Msk      (0x3UL << LPTIM_CCMR1_IC2PSC_Pos)          /*!< 0x03000000 */
24048 #define LPTIM_CCMR1_IC2PSC          LPTIM_CCMR1_IC2PSC_Msk                     /*!< Input capture 2 prescaler */
24049 #define LPTIM_CCMR1_IC2PSC_0        (0x1UL << LPTIM_CCMR1_IC2PSC_Pos)          /*!< 0x01000000 */
24050 #define LPTIM_CCMR1_IC2PSC_1        (0x2UL << LPTIM_CCMR1_IC2PSC_Pos)          /*!< 0x02000000 */
24051 #define LPTIM_CCMR1_IC2F_Pos        (28U)
24052 #define LPTIM_CCMR1_IC2F_Msk        (0x3UL << LPTIM_CCMR1_IC2F_Pos)            /*!< 0x30000000 */
24053 #define LPTIM_CCMR1_IC2F            LPTIM_CCMR1_IC2F_Msk                       /*!< Input capture 2 filter */
24054 #define LPTIM_CCMR1_IC2F_0          (0x1UL << LPTIM_CCMR1_IC2F_Pos)            /*!< 0x10000000 */
24055 #define LPTIM_CCMR1_IC2F_1          (0x2UL << LPTIM_CCMR1_IC2F_Pos)            /*!< 0x20000000 */
24056 
24057 /******************  Bit definition for LPTIM_CCR2 register  ******************/
24058 #define LPTIM_CCR2_CCR2_Pos         (0U)
24059 #define LPTIM_CCR2_CCR2_Msk         (0xFFFFUL << LPTIM_CCR2_CCR2_Pos)           /*!< 0x0000FFFF */
24060 #define LPTIM_CCR2_CCR2             LPTIM_CCR2_CCR2_Msk                         /*!< Compare register 2 */
24061 
24062 
24063 /******************************************************************************/
24064 /*                                                                            */
24065 /*                      LCD-TFT Display Controller (LTDC)                     */
24066 /*                                                                            */
24067 /******************************************************************************/
24068 
24069 /* Bit fields for LTDC_SSCR register */
24070 #define LTDC_SSCR_VSH_Pos                (0U)
24071 #define LTDC_SSCR_VSH_Msk                (0xfffUL << LTDC_SSCR_VSH_Pos)
24072 #define LTDC_SSCR_VSH                    LTDC_SSCR_VSH_Msk  /*!< vertical synchronization height (in units of horizontal scan line)These bits define the vertical Synchronization height minus 1. It represents the number of horizontal synchronization lines. */
24073 #define LTDC_SSCR_HSW_Pos                (16U)
24074 #define LTDC_SSCR_HSW_Msk                (0xfffUL << LTDC_SSCR_HSW_Pos)
24075 #define LTDC_SSCR_HSW                    LTDC_SSCR_HSW_Msk  /*!< horizontal synchronization width (in units of pixel clock period)These bits define the number of Horizontal Synchronization pixel minus 1. */
24076 
24077 /* Bit fields for LTDC_BPCR register */
24078 #define LTDC_BPCR_AVBP_Pos               (0U)
24079 #define LTDC_BPCR_AVBP_Msk               (0xfffUL << LTDC_BPCR_AVBP_Pos)
24080 #define LTDC_BPCR_AVBP                   LTDC_BPCR_AVBP_Msk  /*!< accumulated Vertical back porch (in units of horizontal scan line)These bits define the accumulated vertical back porch width that includes the vertical synchronization and vertical back porch lines minus 1.The vertical back porch is the number of horizontal scan lines at a start of frame to the start of the first active scan line of the next frame. */
24081 #define LTDC_BPCR_AHBP_Pos               (16U)
24082 #define LTDC_BPCR_AHBP_Msk               (0xfffUL << LTDC_BPCR_AHBP_Pos)
24083 #define LTDC_BPCR_AHBP                   LTDC_BPCR_AHBP_Msk  /*!< accumulated horizontal back porch (in units of pixel clock period)These bits define the accumulated horizontal back porch width that includes the horizontal synchronization and horizontal back porch pixels minus 1.The horizontal back porch is the period between horizontal synchronization going inactive and the start of the active display part of the next scan line. */
24084 
24085 /* Bit fields for LTDC_AWCR register */
24086 #define LTDC_AWCR_AAH_Pos                (0U)
24087 #define LTDC_AWCR_AAH_Msk                (0xfffUL << LTDC_AWCR_AAH_Pos)
24088 #define LTDC_AWCR_AAH                    LTDC_AWCR_AAH_Msk  /*!< accumulated active height (in units of horizontal scan line)These bits define the accumulated height which includes the vertical synchronization, vertical back porch and the active height lines minus 1. The active height is the number of active lines in the panel.Refer to device datasheet for maximum active height supported following maximum pixel clock. */
24089 #define LTDC_AWCR_AAW_Pos                (16U)
24090 #define LTDC_AWCR_AAW_Msk                (0xfffUL << LTDC_AWCR_AAW_Pos)
24091 #define LTDC_AWCR_AAW                    LTDC_AWCR_AAW_Msk  /*!< accumulated active width (in units of pixel clock period)These bits define the accumulated active width which includes the horizontal synchronization, horizontal back porch and active pixels minus 1.The active width is the number of pixels in active display area of the panel scan line.Refer to device datasheet for maximum active width supported following maximum pixel clock. */
24092 
24093 /* Bit fields for LTDC_TWCR register */
24094 #define LTDC_TWCR_TOTALH_Pos             (0U)
24095 #define LTDC_TWCR_TOTALH_Msk             (0xfffUL << LTDC_TWCR_TOTALH_Pos)
24096 #define LTDC_TWCR_TOTALH                 LTDC_TWCR_TOTALH_Msk  /*!< total height (in units of horizontal scan line)These bits defines the accumulated height which includes the vertical synchronization, vertical back porch, the active height and vertical front porch height lines minus 1. */
24097 #define LTDC_TWCR_TOTALW_Pos             (16U)
24098 #define LTDC_TWCR_TOTALW_Msk             (0xfffUL << LTDC_TWCR_TOTALW_Pos)
24099 #define LTDC_TWCR_TOTALW                 LTDC_TWCR_TOTALW_Msk  /*!< total width (in units of pixel clock period)These bits defines the accumulated total width which includes the horizontal synchronization, horizontal back porch, active width and horizontal front porch pixels minus 1. */
24100 
24101 /* Bit fields for LTDC_GCR register */
24102 #define LTDC_GCR_LTDCEN_Pos              (0U)
24103 #define LTDC_GCR_LTDCEN_Msk              (0x1UL << LTDC_GCR_LTDCEN_Pos)
24104 #define LTDC_GCR_LTDCEN                  LTDC_GCR_LTDCEN_Msk  /*!< LCD-TFT controller enableThis bit is set and cleared by software.- 0: LTDC disable- 1: LTDC enable */
24105 #define LTDC_GCR_GAMEN_Pos               (1U)
24106 #define LTDC_GCR_GAMEN_Msk               (0x1UL << LTDC_GCR_GAMEN_Pos)
24107 #define LTDC_GCR_GAMEN                   LTDC_GCR_GAMEN_Msk  /*!< LCD-TFT controller enableThis bit is set and cleared by software.- 0: GammaCorrection disable (pixels bypass the gamma operator)- 1: Gamma Correction enable */
24108 #define LTDC_GCR_ROTEN_Pos               (2U)
24109 #define LTDC_GCR_ROTEN_Msk               (0x1UL << LTDC_GCR_ROTEN_Pos)
24110 #define LTDC_GCR_ROTEN                   LTDC_GCR_ROTEN_Msk  /*!< LCD-TFT controller enableThis bit is set and cleared by software.- 0: Rotation disable- 1: Rotation enable (for a pure visual rotation, the mirroring has to be activated) */
24111 #define LTDC_GCR_DBW_Pos                 (4U)
24112 #define LTDC_GCR_DBW_Msk                 (0x7UL << LTDC_GCR_DBW_Pos)
24113 #define LTDC_GCR_DBW                     LTDC_GCR_DBW_Msk  /*!< dither blue widthThese bits return the dither blue bits. */
24114 #define LTDC_GCR_DGW_Pos                 (8U)
24115 #define LTDC_GCR_DGW_Msk                 (0x7UL << LTDC_GCR_DGW_Pos)
24116 #define LTDC_GCR_DGW                     LTDC_GCR_DGW_Msk  /*!< dither green widthThese bits return the dither green bits. */
24117 #define LTDC_GCR_DRW_Pos                 (12U)
24118 #define LTDC_GCR_DRW_Msk                 (0x7UL << LTDC_GCR_DRW_Pos)
24119 #define LTDC_GCR_DRW                     LTDC_GCR_DRW_Msk  /*!< dither red widthThese bits return the Dither Red Bits. */
24120 #define LTDC_GCR_DEN_Pos                 (16U)
24121 #define LTDC_GCR_DEN_Msk                 (0x1UL << LTDC_GCR_DEN_Pos)
24122 #define LTDC_GCR_DEN                     LTDC_GCR_DEN_Msk  /*!< dither enableThis bit is set and cleared by software.- 0: dither disable- 1: dither enable */
24123 #define LTDC_GCR_BCKEN_Pos               (17U)
24124 #define LTDC_GCR_BCKEN_Msk               (0x1UL << LTDC_GCR_BCKEN_Pos)
24125 #define LTDC_GCR_BCKEN                   LTDC_GCR_BCKEN_Msk  /*!< backgroundlayer enableThis bit is set and cleared by software.- 0: backgrounddisable- 1: background enable */
24126 #define LTDC_GCR_CRCEN_Pos               (19U)
24127 #define LTDC_GCR_CRCEN_Msk               (0x1UL << LTDC_GCR_CRCEN_Pos)
24128 #define LTDC_GCR_CRCEN                   LTDC_GCR_CRCEN_Msk  /*!< CRC enableThis bit is set and cleared by software.- 0: CRC disable- 1: CRC enable */
24129 #define LTDC_GCR_SFEN_Pos                (24U)
24130 #define LTDC_GCR_SFEN_Msk                (0x1UL << LTDC_GCR_SFEN_Pos)
24131 #define LTDC_GCR_SFEN                    LTDC_GCR_SFEN_Msk  /*!< single-frame mode: mode enableThis bit is set and cleared by software.- 0: single-frame disable:a trigger (on SFSW or External) will generate a continuous flow.- 1: single-frame enable: a trigger (on SFSW or External) will generate a single frame. */
24132 #define LTDC_GCR_SFSWTR_Pos              (25U)
24133 #define LTDC_GCR_SFSWTR_Msk              (0x1UL << LTDC_GCR_SFSWTR_Pos)
24134 #define LTDC_GCR_SFSWTR                  LTDC_GCR_SFSWTR_Msk  /*!< single-frame mode: software triggerThis bit is set by software and cleared by hardware.- 0: no action- 1: triggers one frame */
24135 #define LTDC_GCR_SFEXEN_Pos              (26U)
24136 #define LTDC_GCR_SFEXEN_Msk              (0x1UL << LTDC_GCR_SFEXEN_Pos)
24137 #define LTDC_GCR_SFEXEN                  LTDC_GCR_SFEXEN_Msk  /*!< single-frame mode: external trigger enableThis bit is set and cleared by software.- 0: external trigger disable- 1: external trigger enable: a trigger on the external trigger will generate one single frame. */
24138 #define LTDC_GCR_PCPOL_Pos               (28U)
24139 #define LTDC_GCR_PCPOL_Msk               (0x1UL << LTDC_GCR_PCPOL_Pos)
24140 #define LTDC_GCR_PCPOL                   LTDC_GCR_PCPOL_Msk  /*!< pixel clock polarityThis bit is set and cleared by software.- 0: pixel clock polarity is active low.- 1: pixel clock is active high. */
24141 #define LTDC_GCR_DEPOL_Pos               (29U)
24142 #define LTDC_GCR_DEPOL_Msk               (0x1UL << LTDC_GCR_DEPOL_Pos)
24143 #define LTDC_GCR_DEPOL                   LTDC_GCR_DEPOL_Msk  /*!< blanking (=no data/pixel) polarityThis bit is set and cleared by software.- 0: blanking (no data/pixel) polarity is active low.- 1: blanking (no data/pixel) polarity is active high. */
24144 #define LTDC_GCR_VSPOL_Pos               (30U)
24145 #define LTDC_GCR_VSPOL_Msk               (0x1UL << LTDC_GCR_VSPOL_Pos)
24146 #define LTDC_GCR_VSPOL                   LTDC_GCR_VSPOL_Msk  /*!< vertical synchronization polarityThis bit is set and cleared by software.- 0: vertical synchronization is active low.- 1: vertical synchronization is active high. */
24147 #define LTDC_GCR_HSPOL_Pos               (31U)
24148 #define LTDC_GCR_HSPOL_Msk               (0x1UL << LTDC_GCR_HSPOL_Pos)
24149 #define LTDC_GCR_HSPOL                   LTDC_GCR_HSPOL_Msk  /*!< horizontal synchronization polarityThis bit is set and cleared by software.- 0: horizontal synchronization polarity is active low.- 1: horizontal synchronization polarity is active high. */
24150 
24151 /* Bit fields for LTDC_SRCR register */
24152 #define LTDC_SRCR_IMR_Pos                (0U)
24153 #define LTDC_SRCR_IMR_Msk                (0x1UL << LTDC_SRCR_IMR_Pos)
24154 #define LTDC_SRCR_IMR                    LTDC_SRCR_IMR_Msk  /*!< immediate reload triggerThis bit is set by software and cleared only by hardware after reload.- 0: no effect- 1: The shadow registers are reloaded immediately. */
24155 #define LTDC_SRCR_VBR_Pos                (1U)
24156 #define LTDC_SRCR_VBR_Msk                (0x1UL << LTDC_SRCR_VBR_Pos)
24157 #define LTDC_SRCR_VBR                    LTDC_SRCR_VBR_Msk  /*!< vertical blanking reload requestThis bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set).- 0: no effect- 1: The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area). */
24158 
24159 /* Bit fields for LTDC_GCCR register */
24160 #define LTDC_GCCR_ADDR_Pos               (0U)
24161 #define LTDC_GCCR_ADDR_Msk               (0xffUL << LTDC_GCCR_ADDR_Pos)
24162 #define LTDC_GCCR_ADDR                   LTDC_GCCR_ADDR_Msk  /*!< address of the R,G,B table where the COMP component is written.When LTDC_GC1R.GCT=2, the gamma is implemented with 8 interpolated segment. In that case, the valid ADDR addresses are: 0, 32, 64, 96, 128, 160, 192, 224, 255.Note that for ADDR=255, the gamma interpolation hardware considers that the address is 256. */
24163 #define LTDC_GCCR_COMP_Pos               (8U)
24164 #define LTDC_GCCR_COMP_Msk               (0xffUL << LTDC_GCCR_COMP_Pos)
24165 #define LTDC_GCCR_COMP                   LTDC_GCCR_COMP_Msk  /*!< color component to be written, in either (or all) the R,G,B tables.. */
24166 #define LTDC_GCCR_BEN_Pos                (16U)
24167 #define LTDC_GCCR_BEN_Msk                (0x1UL << LTDC_GCCR_BEN_Pos)
24168 #define LTDC_GCCR_BEN                    LTDC_GCCR_BEN_Msk  /*!< write trigger to the blue table- 0: no action done- 1: COMP is written at ADDR in the Blue table. */
24169 #define LTDC_GCCR_GEN_Pos                (17U)
24170 #define LTDC_GCCR_GEN_Msk                (0x1UL << LTDC_GCCR_GEN_Pos)
24171 #define LTDC_GCCR_GEN                    LTDC_GCCR_GEN_Msk  /*!< write trigger to the green table- 0: no action done- 1: COMP is written at ADDR in the Green table. */
24172 #define LTDC_GCCR_REN_Pos                (18U)
24173 #define LTDC_GCCR_REN_Msk                (0x1UL << LTDC_GCCR_REN_Pos)
24174 #define LTDC_GCCR_REN                    LTDC_GCCR_REN_Msk  /*!< write trigger to the red table- 0: no action done- 1: COMP is written at ADDR in the Red table. */
24175 
24176 /* Bit fields for LTDC_BCCR register */
24177 #define LTDC_BCCR_BCBLUE_Pos             (0U)
24178 #define LTDC_BCCR_BCBLUE_Msk             (0xffUL << LTDC_BCCR_BCBLUE_Pos)
24179 #define LTDC_BCCR_BCBLUE                 LTDC_BCCR_BCBLUE_Msk  /*!< background color blue valueThese bits configure the background blue value. */
24180 #define LTDC_BCCR_BCGREEN_Pos            (8U)
24181 #define LTDC_BCCR_BCGREEN_Msk            (0xffUL << LTDC_BCCR_BCGREEN_Pos)
24182 #define LTDC_BCCR_BCGREEN                LTDC_BCCR_BCGREEN_Msk  /*!< background color green valueThese bits configure the background green value. */
24183 #define LTDC_BCCR_BCRED_Pos              (16U)
24184 #define LTDC_BCCR_BCRED_Msk              (0xffUL << LTDC_BCCR_BCRED_Pos)
24185 #define LTDC_BCCR_BCRED                  LTDC_BCCR_BCRED_Msk  /*!< background color red valueThese bits configure the background red value. */
24186 
24187 /* Bit fields for LTDC_IER register */
24188 #define LTDC_IER_LIE_Pos                 (0U)
24189 #define LTDC_IER_LIE_Msk                 (0x1UL << LTDC_IER_LIE_Pos)
24190 #define LTDC_IER_LIE                     LTDC_IER_LIE_Msk  /*!< line interrupt enableThis bit is set and cleared by software.- 0: line interrupt disable- 1: line interrupt enable */
24191 #define LTDC_IER_FUWIE_Pos               (1U)
24192 #define LTDC_IER_FUWIE_Msk               (0x1UL << LTDC_IER_FUWIE_Pos)
24193 #define LTDC_IER_FUWIE                   LTDC_IER_FUWIE_Msk  /*!< FIFO underrun warning interrupt enableThis bit is set and cleared by software.- 0: FIFO underrun interrupt disable- 1: FIFO underrun Interrupt enable */
24194 #define LTDC_IER_TERRIE_Pos              (2U)
24195 #define LTDC_IER_TERRIE_Msk              (0x1UL << LTDC_IER_TERRIE_Pos)
24196 #define LTDC_IER_TERRIE                  LTDC_IER_TERRIE_Msk  /*!< transfer error interrupt enableThis bit is set and cleared by software.- 0: transfer error interrupt disable- 1: transfer error interrupt enable */
24197 #define LTDC_IER_RRIE_Pos                (3U)
24198 #define LTDC_IER_RRIE_Msk                (0x1UL << LTDC_IER_RRIE_Pos)
24199 #define LTDC_IER_RRIE                    LTDC_IER_RRIE_Msk  /*!< register reload interrupt enableThis bit is set and cleared by software.- 0: register reload interrupt disable- 1: register reload interrupt enable */
24200 #define LTDC_IER_FUIE_Pos                (6U)
24201 #define LTDC_IER_FUIE_Msk                (0x1UL << LTDC_IER_FUIE_Pos)
24202 #define LTDC_IER_FUIE                    LTDC_IER_FUIE_Msk  /*!< FIFO underrun interrupt enableThis bit is set and cleared by software.- 0: FIFO underrun killing interrupt disable- 1: FIFO underrun killing Interrupt enable */
24203 #define LTDC_IER_CRCIE_Pos               (7U)
24204 #define LTDC_IER_CRCIE_Msk               (0x1UL << LTDC_IER_CRCIE_Pos)
24205 #define LTDC_IER_CRCIE                   LTDC_IER_CRCIE_Msk  /*!< CRC error interrupt enableThis bit is set and cleared by software.- 0: crcerror disable- 1: crc error interrupt enable */
24206 #define LTDC_IER_FURIE_Pos               (8U)
24207 #define LTDC_IER_FURIE_Msk               (0x1UL << LTDC_IER_FURIE_Pos)
24208 #define LTDC_IER_FURIE                   LTDC_IER_FURIE_Msk  /*!< FIFOunderrun at rotation interrupt enableThis bit is set and cleared by software.- 0: FIFOunderrun at rotation interrupt disable- 1: FIFO underrunat rotation interrupt enable */
24209 
24210 /* Bit fields for LTDC_ISR register */
24211 #define LTDC_ISR_LIF_Pos                 (0U)
24212 #define LTDC_ISR_LIF_Msk                 (0x1UL << LTDC_ISR_LIF_Pos)
24213 #define LTDC_ISR_LIF                     LTDC_ISR_LIF_Msk  /*!< line interrupt flag- 0: no line interrupt generated- 1: line interrupt generated when a programmed line is reached */
24214 #define LTDC_ISR_FUWIF_Pos               (1U)
24215 #define LTDC_ISR_FUWIF_Msk               (0x1UL << LTDC_ISR_FUWIF_Pos)
24216 #define LTDC_ISR_FUWIF                   LTDC_ISR_FUWIF_Msk  /*!< FIFO underrun warning interrupt flag- 0: no FIFO underrun warning interrupt generated.- 1: FIFO underrun warning interrupt generated, if one of the layer FIFOs is empty and pixel data is read from the FIFO */
24217 #define LTDC_ISR_TERRIF_Pos              (2U)
24218 #define LTDC_ISR_TERRIF_Msk              (0x1UL << LTDC_ISR_TERRIF_Pos)
24219 #define LTDC_ISR_TERRIF                  LTDC_ISR_TERRIF_Msk  /*!< transfer error interrupt flag- 0: no transfer error interrupt generated- 1: transfer error interrupt generated when a bus error occurs */
24220 #define LTDC_ISR_RRIF_Pos                (3U)
24221 #define LTDC_ISR_RRIF_Msk                (0x1UL << LTDC_ISR_RRIF_Pos)
24222 #define LTDC_ISR_RRIF                    LTDC_ISR_RRIF_Msk  /*!< register reload interrupt flag- 0: no register reload interrupt generated- 1: register reload interrupt generated when a vertical blanking reload occurs (and the first line after the active area is reached) */
24223 #define LTDC_ISR_FUIF_Pos                (6U)
24224 #define LTDC_ISR_FUIF_Msk                (0x1UL << LTDC_ISR_FUIF_Pos)
24225 #define LTDC_ISR_FUIF                    LTDC_ISR_FUIF_Msk  /*!< FIFO underrun interrupt flag- 0: no FIFO underrun killing interrupt generated.- 1: FIFO underrun killing interrupt generated, if one of the layer FIFOs is empty and many pixel data is read from the FIFO */
24226 #define LTDC_ISR_CRCIF_Pos               (7U)
24227 #define LTDC_ISR_CRCIF_Msk               (0x1UL << LTDC_ISR_CRCIF_Pos)
24228 #define LTDC_ISR_CRCIF                   LTDC_ISR_CRCIF_Msk  /*!< transfer error interrupt flag- 0: no CRC error interrupt generated- 1: CRC error interrupt generated when the computed CRC is different from the expected CRC. */
24229 #define LTDC_ISR_FURIF_Pos               (8U)
24230 #define LTDC_ISR_FURIF_Msk               (0x1UL << LTDC_ISR_FURIF_Pos)
24231 #define LTDC_ISR_FURIF                   LTDC_ISR_FURIF_Msk  /*!< FIFO underrun at rotation interrupt flag- 0: no FIFO underrun at rotation interrupt generated- 1: FIFO underrun at rotation interrupt generated */
24232 
24233 /* Bit fields for LTDC_ICR register */
24234 #define LTDC_ICR_CLIF_Pos                (0U)
24235 #define LTDC_ICR_CLIF_Msk                (0x1UL << LTDC_ICR_CLIF_Pos)
24236 #define LTDC_ICR_CLIF                    LTDC_ICR_CLIF_Msk  /*!< clears the line interrupt flag- 0: no effect- 1: clears the LIF flag in the LTDC_ISR register. */
24237 #define LTDC_ICR_CFUWIF_Pos              (1U)
24238 #define LTDC_ICR_CFUWIF_Msk              (0x1UL << LTDC_ICR_CFUWIF_Pos)
24239 #define LTDC_ICR_CFUWIF                  LTDC_ICR_CFUWIF_Msk  /*!< clears the FIFO underrun warning interrupt flag- 0: no effect- 1: clears the FUWIF flag in the LTDC_ISR register. */
24240 #define LTDC_ICR_CTERRIF_Pos             (2U)
24241 #define LTDC_ICR_CTERRIF_Msk             (0x1UL << LTDC_ICR_CTERRIF_Pos)
24242 #define LTDC_ICR_CTERRIF                 LTDC_ICR_CTERRIF_Msk  /*!< clears the transfer error interrupt flag- 0: no effect- 1: clears the TERRIF flag in the LTDC_ISR register. */
24243 #define LTDC_ICR_CRRIF_Pos               (3U)
24244 #define LTDC_ICR_CRRIF_Msk               (0x1UL << LTDC_ICR_CRRIF_Pos)
24245 #define LTDC_ICR_CRRIF                   LTDC_ICR_CRRIF_Msk  /*!< clears register reload interrupt flag- 0: no effect- 1: clears the RRIF flag in the LTDC_ISR register */
24246 #define LTDC_ICR_CFUIF_Pos               (6U)
24247 #define LTDC_ICR_CFUIF_Msk               (0x1UL << LTDC_ICR_CFUIF_Pos)
24248 #define LTDC_ICR_CFUIF                   LTDC_ICR_CFUIF_Msk  /*!< clears the FIFO underrun warning interrupt flag- 0: no effect- 1: clears the FUKIF flag in the LTDC_ISR register. */
24249 #define LTDC_ICR_CCRCIF_Pos              (7U)
24250 #define LTDC_ICR_CCRCIF_Msk              (0x1UL << LTDC_ICR_CCRCIF_Pos)
24251 #define LTDC_ICR_CCRCIF                  LTDC_ICR_CCRCIF_Msk  /*!< clears the transfer error interrupt flag- 0: no effect- 1: clears the CRCIF flag in the LTDC_ISR register. */
24252 #define LTDC_ICR_CFURIF_Pos              (8U)
24253 #define LTDC_ICR_CFURIF_Msk              (0x1UL << LTDC_ICR_CFURIF_Pos)
24254 #define LTDC_ICR_CFURIF                  LTDC_ICR_CFURIF_Msk  /*!< clears register reload interrupt flag- 0: no effect- 1: clears the FURIF flag in the LTDC_ISR register */
24255 
24256 /* Bit fields for LTDC_LIPCR register */
24257 #define LTDC_LIPCR_LIPOS_Pos             (0U)
24258 #define LTDC_LIPCR_LIPOS_Msk             (0xfffUL << LTDC_LIPCR_LIPOS_Pos)
24259 #define LTDC_LIPCR_LIPOS                 LTDC_LIPCR_LIPOS_Msk  /*!< line interrupt positionThese bits configure the line interrupt position. */
24260 
24261 /* Bit fields for LTDC_CPSR register */
24262 #define LTDC_CPSR_CYPOS_Pos              (0U)
24263 #define LTDC_CPSR_CYPOS_Msk              (0xfffUL << LTDC_CPSR_CYPOS_Pos)
24264 #define LTDC_CPSR_CYPOS                  LTDC_CPSR_CYPOS_Msk  /*!< current Y positionThese bits return the current Y position. */
24265 #define LTDC_CPSR_CXPOS_Pos              (16U)
24266 #define LTDC_CPSR_CXPOS_Msk              (0xfffUL << LTDC_CPSR_CXPOS_Pos)
24267 #define LTDC_CPSR_CXPOS                  LTDC_CPSR_CXPOS_Msk  /*!< current X positionThese bits return the current X position. */
24268 
24269 /* Bit fields for LTDC_CDSR register */
24270 #define LTDC_CDSR_VDES_Pos               (0U)
24271 #define LTDC_CDSR_VDES_Msk               (0x1UL << LTDC_CDSR_VDES_Pos)
24272 #define LTDC_CDSR_VDES                   LTDC_CDSR_VDES_Msk  /*!< vertical data enable display status- 0: active low- 1: active high */
24273 #define LTDC_CDSR_HDES_Pos               (1U)
24274 #define LTDC_CDSR_HDES_Msk               (0x1UL << LTDC_CDSR_HDES_Pos)
24275 #define LTDC_CDSR_HDES                   LTDC_CDSR_HDES_Msk  /*!< horizontal data enable display status- 0: active low- 1: active high */
24276 #define LTDC_CDSR_VSYNCS_Pos             (2U)
24277 #define LTDC_CDSR_VSYNCS_Msk             (0x1UL << LTDC_CDSR_VSYNCS_Pos)
24278 #define LTDC_CDSR_VSYNCS                 LTDC_CDSR_VSYNCS_Msk  /*!< vertical synchronization display status- 0: active low- 1: active high */
24279 #define LTDC_CDSR_HSYNCS_Pos             (3U)
24280 #define LTDC_CDSR_HSYNCS_Msk             (0x1UL << LTDC_CDSR_HSYNCS_Pos)
24281 #define LTDC_CDSR_HSYNCS                 LTDC_CDSR_HSYNCS_Msk  /*!< horizontal synchronization display status- 0: active low- 1: active high */
24282 
24283 /* Bit fields for LTDC_EDCR register */
24284 #define LTDC_EDCR_OCYEN_Pos              (25U)
24285 #define LTDC_EDCR_OCYEN_Msk              (0x1UL << LTDC_EDCR_OCYEN_Pos)
24286 #define LTDC_EDCR_OCYEN                  LTDC_EDCR_OCYEN_Msk  /*!< output conversion to YCbCr 422: Enable- 0: conversion is disabled- 1: conversion is enabled */
24287 #define LTDC_EDCR_OCYSEL_Pos             (26U)
24288 #define LTDC_EDCR_OCYSEL_Msk             (0x1UL << LTDC_EDCR_OCYSEL_Pos)
24289 #define LTDC_EDCR_OCYSEL                 LTDC_EDCR_OCYSEL_Msk  /*!< output conversion to YCbCr 422: selection of the CCIR hard-wired coefficients:- 0: use CCIR-BT601 set (for typically SDTV analog-like displays)- 1: use CCIR-BT709 set (for typically HDTV digital-like displays) */
24290 #define LTDC_EDCR_OCYCO_Pos              (27U)
24291 #define LTDC_EDCR_OCYCO_Msk              (0x1UL << LTDC_EDCR_OCYCO_Pos)
24292 #define LTDC_EDCR_OCYCO                  LTDC_EDCR_OCYCO_Msk  /*!< output conversion to YCbCr 422: chrominance order.- 0: Cb is output first (so: Y0Cb, then Y1Cr, Y2Cb, etc .. ).- 1: Cr is output first (so: Y0Cr, then Y1Cb, Y2Cr, etc ..). */
24293 
24294 /* Bit fields for LTDC_IER2 register */
24295 #define LTDC_IER2_LIE_Pos                (0U)
24296 #define LTDC_IER2_LIE_Msk                (0x1UL << LTDC_IER2_LIE_Pos)
24297 #define LTDC_IER2_LIE                    LTDC_IER2_LIE_Msk  /*!< line interrupt enableThis bit is set and cleared by software.- 0: line interrupt disable- 1: line interrupt enable */
24298 #define LTDC_IER2_FUWIE_Pos              (1U)
24299 #define LTDC_IER2_FUWIE_Msk              (0x1UL << LTDC_IER2_FUWIE_Pos)
24300 #define LTDC_IER2_FUWIE                  LTDC_IER2_FUWIE_Msk  /*!< FIFO underrun warning interrupt enableThis bit is set and cleared by software.- 0: FIFO underrun interrupt disable- 1: FIFO underrun Interrupt enable */
24301 #define LTDC_IER2_TERRIE_Pos             (2U)
24302 #define LTDC_IER2_TERRIE_Msk             (0x1UL << LTDC_IER2_TERRIE_Pos)
24303 #define LTDC_IER2_TERRIE                 LTDC_IER2_TERRIE_Msk  /*!< transfer error interrupt enableThis bit is set and cleared by software.- 0: transfer error interrupt disable- 1: transfer error interrupt enable */
24304 #define LTDC_IER2_RRIE_Pos               (3U)
24305 #define LTDC_IER2_RRIE_Msk               (0x1UL << LTDC_IER2_RRIE_Pos)
24306 #define LTDC_IER2_RRIE                   LTDC_IER2_RRIE_Msk  /*!< register reload interrupt enableThis bit is set and cleared by software.- 0: register reload interrupt disable- 1: register reload interrupt enable */
24307 #define LTDC_IER2_FUIE_Pos               (6U)
24308 #define LTDC_IER2_FUIE_Msk               (0x1UL << LTDC_IER2_FUIE_Pos)
24309 #define LTDC_IER2_FUIE                   LTDC_IER2_FUIE_Msk  /*!< FIFO underrun interrupt enableThis bit is set and cleared by software.- 0: FIFO underrun killing interrupt disable- 1: FIFO underrun killing Interrupt enable */
24310 #define LTDC_IER2_CRCIE_Pos              (7U)
24311 #define LTDC_IER2_CRCIE_Msk              (0x1UL << LTDC_IER2_CRCIE_Pos)
24312 #define LTDC_IER2_CRCIE                  LTDC_IER2_CRCIE_Msk  /*!< CRC error interrupt enableThis bit is set and cleared by software.- 0: crcerror disable- 1: crc error interrupt enable */
24313 
24314 /* Bit fields for LTDC_ISR2 register */
24315 #define LTDC_ISR2_LIF_Pos                (0U)
24316 #define LTDC_ISR2_LIF_Msk                (0x1UL << LTDC_ISR2_LIF_Pos)
24317 #define LTDC_ISR2_LIF                    LTDC_ISR2_LIF_Msk  /*!< line interrupt flag- 0: no line interrupt generated- 1: line interrupt generated when a programmed line is reached */
24318 #define LTDC_ISR2_FUWIF_Pos              (1U)
24319 #define LTDC_ISR2_FUWIF_Msk              (0x1UL << LTDC_ISR2_FUWIF_Pos)
24320 #define LTDC_ISR2_FUWIF                  LTDC_ISR2_FUWIF_Msk  /*!< FIFO underrun warning interrupt flag- 0: no FIFO underrun warning interrupt generated.- 1: FIFO underrun warning interrupt generated, if one of the layer FIFOs is empty and pixel data is read from the FIFO */
24321 #define LTDC_ISR2_TERRIF_Pos             (2U)
24322 #define LTDC_ISR2_TERRIF_Msk             (0x1UL << LTDC_ISR2_TERRIF_Pos)
24323 #define LTDC_ISR2_TERRIF                 LTDC_ISR2_TERRIF_Msk  /*!< transfer error interrupt flag- 0: no transfer error interrupt generated- 1: transfer error interrupt generated when a bus error occurs */
24324 #define LTDC_ISR2_RRIF_Pos               (3U)
24325 #define LTDC_ISR2_RRIF_Msk               (0x1UL << LTDC_ISR2_RRIF_Pos)
24326 #define LTDC_ISR2_RRIF                   LTDC_ISR2_RRIF_Msk  /*!< register reload interrupt flag- 0: no register reload interrupt generated- 1: register reload interrupt generated when a vertical blanking reload occurs (and the first line after the active area is reached) */
24327 #define LTDC_ISR2_FUIF_Pos               (6U)
24328 #define LTDC_ISR2_FUIF_Msk               (0x1UL << LTDC_ISR2_FUIF_Pos)
24329 #define LTDC_ISR2_FUIF                   LTDC_ISR2_FUIF_Msk  /*!< FIFO underrun interrupt flag- 0: no FIFO underrun killing interrupt generated.- 1: FIFO underrun killing interrupt generated, if one of the layer FIFOs is empty and many pixel data are read from the FIFO */
24330 #define LTDC_ISR2_CRCIF_Pos              (7U)
24331 #define LTDC_ISR2_CRCIF_Msk              (0x1UL << LTDC_ISR2_CRCIF_Pos)
24332 #define LTDC_ISR2_CRCIF                  LTDC_ISR2_CRCIF_Msk  /*!< transfer error interrupt flag- 0: no CRC error interrupt generated- 1: CRC error interrupt generated when a bus error occurs */
24333 
24334 /* Bit fields for LTDC_ICR2 register */
24335 #define LTDC_ICR2_CLIF_Pos               (0U)
24336 #define LTDC_ICR2_CLIF_Msk               (0x1UL << LTDC_ICR2_CLIF_Pos)
24337 #define LTDC_ICR2_CLIF                   LTDC_ICR2_CLIF_Msk  /*!< clears the line interrupt flag- 0: no effect- 1: clears the LIF flag in the LTDC_ISR register. */
24338 #define LTDC_ICR2_CFUWIF_Pos             (1U)
24339 #define LTDC_ICR2_CFUWIF_Msk             (0x1UL << LTDC_ICR2_CFUWIF_Pos)
24340 #define LTDC_ICR2_CFUWIF                 LTDC_ICR2_CFUWIF_Msk  /*!< clears the FIFO underrun warning interrupt flag- 0: no effect- 1: clears the FUWIF flag in the LTDC_ISR register. */
24341 #define LTDC_ICR2_CTERRIF_Pos            (2U)
24342 #define LTDC_ICR2_CTERRIF_Msk            (0x1UL << LTDC_ICR2_CTERRIF_Pos)
24343 #define LTDC_ICR2_CTERRIF                LTDC_ICR2_CTERRIF_Msk  /*!< clears the transfer error interrupt flag- 0: no effect- 1: clears the TERRIF flag in the LTDC_ISR register. */
24344 #define LTDC_ICR2_CRRIF_Pos              (3U)
24345 #define LTDC_ICR2_CRRIF_Msk              (0x1UL << LTDC_ICR2_CRRIF_Pos)
24346 #define LTDC_ICR2_CRRIF                  LTDC_ICR2_CRRIF_Msk  /*!< clears register reload interrupt flag- 0: no effect- 1: clears the RRIF flag in the LTDC_ISR register */
24347 #define LTDC_ICR2_CFUIF_Pos              (6U)
24348 #define LTDC_ICR2_CFUIF_Msk              (0x1UL << LTDC_ICR2_CFUIF_Pos)
24349 #define LTDC_ICR2_CFUIF                  LTDC_ICR2_CFUIF_Msk  /*!< clears the FIFO underrun warning interrupt flag- 0: no effect- 1: clears the FUKIF flag in the LTDC_ISR register. */
24350 #define LTDC_ICR2_CCRCIF_Pos             (7U)
24351 #define LTDC_ICR2_CCRCIF_Msk             (0x1UL << LTDC_ICR2_CCRCIF_Pos)
24352 #define LTDC_ICR2_CCRCIF                 LTDC_ICR2_CCRCIF_Msk  /*!< clears the transfer error interrupt flag- 0: no effect- 1: clears the CRCIF flag in the LTDC_ISR register. */
24353 
24354 /* Bit fields for LTDC_LIPCR2 register */
24355 #define LTDC_LIPCR2_LIPOS_Pos             (0U)
24356 #define LTDC_LIPCR2_LIPOS_Msk             (0xffffUL << LTDC_LIPCR2_LIPOS_Pos)
24357 #define LTDC_LIPCR2_LIPOS                 LTDC_LIPCR2_LIPOS_Msk  /*!< line interrupt positionThese bits configure the line interrupt position. */
24358 
24359 /* Bit fields for LTDC_CPSR2 register */
24360 #define LTDC_CPSR2_CYPOS_Pos             (0U)
24361 #define LTDC_CPSR2_CYPOS_Msk             (0xffffUL << LTDC_CPSR2_CYPOS_Pos)
24362 #define LTDC_CPSR2_CYPOS                 LTDC_CPSR2_CYPOS_Msk  /*!< current Y positionThese bits return the current Y position. */
24363 #define LTDC_CPSR2_CXPOS_Pos             (16U)
24364 #define LTDC_CPSR2_CXPOS_Msk             (0xffffUL << LTDC_CPSR2_CXPOS_Pos)
24365 #define LTDC_CPSR2_CXPOS                 LTDC_CPSR2_CXPOS_Msk  /*!< current X positionThese bits return the current X position. */
24366 
24367 /* Bit fields for LTDC_ECRCR register */
24368 #define LTDC_ECRCR_ECRC_Pos              (0U)
24369 #define LTDC_ECRCR_ECRC_Msk              (0xffffUL << LTDC_ECRCR_ECRC_Pos)
24370 #define LTDC_ECRCR_ECRC                  LTDC_ECRCR_ECRC_Msk  /*!< expected CRC of frame */
24371 
24372 /* Bit fields for LTDC_CCRCR register */
24373 #define LTDC_CCRCR_CCRC_Pos              (0U)
24374 #define LTDC_CCRCR_CCRC_Msk              (0xffffUL << LTDC_CCRCR_CCRC_Pos)
24375 #define LTDC_CCRCR_CCRC                  LTDC_CCRCR_CCRC_Msk  /*!< expected CRC of frame */
24376 
24377 /* Bit fields for LTDC_FUTR register */
24378 #define LTDC_FUTR_THRE_Pos               (0U)
24379 #define LTDC_FUTR_THRE_Msk               (0xffffUL << LTDC_FUTR_THRE_Pos)
24380 #define LTDC_FUTR_THRE                   LTDC_FUTR_THRE_Msk  /*!< threshold to trigger a FIFO underrun killing interrupt (unit is per fifo word, 64bit) */
24381 
24382 /* Bit fields for LTDC_LxC0R register */
24383 #define LTDC_LxC0R_CKTA_Pos              (0U)
24384 #define LTDC_LxC0R_CKTA_Msk              (0x1UL << LTDC_LxC0R_CKTA_Pos)
24385 #define LTDC_LxC0R_CKTA                  LTDC_LxC0R_CKTA_Msk  /*!< color key transparency Ability */
24386 #define LTDC_LxC0R_CFBDA_Pos             (1U)
24387 #define LTDC_LxC0R_CFBDA_Msk             (0x1UL << LTDC_LxC0R_CFBDA_Pos)
24388 #define LTDC_LxC0R_CFBDA                 LTDC_LxC0R_CFBDA_Msk  /*!< color frame buffer duplication ability */
24389 #define LTDC_LxC0R_CFBPA_Pos             (2U)
24390 #define LTDC_LxC0R_CFBPA_Msk             (0x1UL << LTDC_LxC0R_CFBPA_Pos)
24391 #define LTDC_LxC0R_CFBPA                 LTDC_LxC0R_CFBPA_Msk  /*!< color frame buffer pitch ability */
24392 #define LTDC_LxC0R_APA_Pos               (3U)
24393 #define LTDC_LxC0R_APA_Msk               (0x1UL << LTDC_LxC0R_APA_Pos)
24394 #define LTDC_LxC0R_APA                   LTDC_LxC0R_APA_Msk  /*!< alpha plane ability */
24395 #define LTDC_LxC0R_DCP_Pos               (4U)
24396 #define LTDC_LxC0R_DCP_Msk               (0x1UL << LTDC_LxC0R_DCP_Pos)
24397 #define LTDC_LxC0R_DCP                   LTDC_LxC0R_DCP_Msk  /*!< default color programmability */
24398 #define LTDC_LxC0R_WINA_Pos              (5U)
24399 #define LTDC_LxC0R_WINA_Msk              (0x1UL << LTDC_LxC0R_WINA_Pos)
24400 #define LTDC_LxC0R_WINA                  LTDC_LxC0R_WINA_Msk  /*!< windowing ability */
24401 #define LTDC_LxC0R_CLUTA_Pos             (6U)
24402 #define LTDC_LxC0R_CLUTA_Msk             (0x1UL << LTDC_LxC0R_CLUTA_Pos)
24403 #define LTDC_LxC0R_CLUTA                 LTDC_LxC0R_CLUTA_Msk  /*!< CLUT ability */
24404 #define LTDC_LxC0R_CKRA_Pos              (7U)
24405 #define LTDC_LxC0R_CKRA_Msk              (0x1UL << LTDC_LxC0R_CKRA_Pos)
24406 #define LTDC_LxC0R_CKRA                  LTDC_LxC0R_CKRA_Msk  /*!< color key replace ability */
24407 #define LTDC_LxC0R_F21_Pos               (8U)
24408 #define LTDC_LxC0R_F21_Msk               (0x1UL << LTDC_LxC0R_F21_Pos)
24409 #define LTDC_LxC0R_F21                   LTDC_LxC0R_F21_Msk  /*!< blending factor 2, ability for: 1.0 */
24410 #define LTDC_LxC0R_F20_Pos               (9U)
24411 #define LTDC_LxC0R_F20_Msk               (0x1UL << LTDC_LxC0R_F20_Pos)
24412 #define LTDC_LxC0R_F20                   LTDC_LxC0R_F20_Msk  /*!< blending factor 2, ability for: 0.0 */
24413 #define LTDC_LxC0R_F2P_Pos               (10U)
24414 #define LTDC_LxC0R_F2P_Msk               (0x1UL << LTDC_LxC0R_F2P_Pos)
24415 #define LTDC_LxC0R_F2P                   LTDC_LxC0R_F2P_Msk  /*!< blending factor 2, ability for: pixel_alpha */
24416 #define LTDC_LxC0R_F21P_Pos              (11U)
24417 #define LTDC_LxC0R_F21P_Msk              (0x1UL << LTDC_LxC0R_F21P_Pos)
24418 #define LTDC_LxC0R_F21P                  LTDC_LxC0R_F21P_Msk  /*!< blending factor 2, ability for: 1.0 - pixel_alpha */
24419 #define LTDC_LxC0R_F2C_Pos               (12U)
24420 #define LTDC_LxC0R_F2C_Msk               (0x1UL << LTDC_LxC0R_F2C_Pos)
24421 #define LTDC_LxC0R_F2C                   LTDC_LxC0R_F2C_Msk  /*!< blending factor 2, ability for: constant_alpha */
24422 #define LTDC_LxC0R_F21C_Pos              (13U)
24423 #define LTDC_LxC0R_F21C_Msk              (0x1UL << LTDC_LxC0R_F21C_Pos)
24424 #define LTDC_LxC0R_F21C                  LTDC_LxC0R_F21C_Msk  /*!< blending factor 2, ability for: 1.0 - constant_alpha */
24425 #define LTDC_LxC0R_F2PC_Pos              (14U)
24426 #define LTDC_LxC0R_F2PC_Msk              (0x1UL << LTDC_LxC0R_F2PC_Pos)
24427 #define LTDC_LxC0R_F2PC                  LTDC_LxC0R_F2PC_Msk  /*!< blending factor 2, ability for: pixel_alpha * constant_alpha */
24428 #define LTDC_LxC0R_F21PC_Pos             (15U)
24429 #define LTDC_LxC0R_F21PC_Msk             (0x1UL << LTDC_LxC0R_F21PC_Pos)
24430 #define LTDC_LxC0R_F21PC                 LTDC_LxC0R_F21PC_Msk  /*!< blending factor 2, ability for: 1.0 - (pixel_alpha * constant_alpha) */
24431 #define LTDC_LxC0R_F11_Pos               (16U)
24432 #define LTDC_LxC0R_F11_Msk               (0x1UL << LTDC_LxC0R_F11_Pos)
24433 #define LTDC_LxC0R_F11                   LTDC_LxC0R_F11_Msk  /*!< blending factor 1, ability for: 1.0 */
24434 #define LTDC_LxC0R_F10_Pos               (17U)
24435 #define LTDC_LxC0R_F10_Msk               (0x1UL << LTDC_LxC0R_F10_Pos)
24436 #define LTDC_LxC0R_F10                   LTDC_LxC0R_F10_Msk  /*!< blending factor 1,ability for: 0.0 */
24437 #define LTDC_LxC0R_F1P_Pos               (18U)
24438 #define LTDC_LxC0R_F1P_Msk               (0x1UL << LTDC_LxC0R_F1P_Pos)
24439 #define LTDC_LxC0R_F1P                   LTDC_LxC0R_F1P_Msk  /*!< blending factor 1, ability for: pixel_alpha */
24440 #define LTDC_LxC0R_F11P_Pos              (19U)
24441 #define LTDC_LxC0R_F11P_Msk              (0x1UL << LTDC_LxC0R_F11P_Pos)
24442 #define LTDC_LxC0R_F11P                  LTDC_LxC0R_F11P_Msk  /*!< blending factor 1, ability for: 1.0 - pixel_alpha */
24443 #define LTDC_LxC0R_F1C_Pos               (20U)
24444 #define LTDC_LxC0R_F1C_Msk               (0x1UL << LTDC_LxC0R_F1C_Pos)
24445 #define LTDC_LxC0R_F1C                   LTDC_LxC0R_F1C_Msk  /*!< blending factor 1, ability for: constant_alpha */
24446 #define LTDC_LxC0R_F11C_Pos              (21U)
24447 #define LTDC_LxC0R_F11C_Msk              (0x1UL << LTDC_LxC0R_F11C_Pos)
24448 #define LTDC_LxC0R_F11C                  LTDC_LxC0R_F11C_Msk  /*!< blending factor 1, ability for: 1.0 - constant_alpha */
24449 #define LTDC_LxC0R_F1PC_Pos              (22U)
24450 #define LTDC_LxC0R_F1PC_Msk              (0x1UL << LTDC_LxC0R_F1PC_Pos)
24451 #define LTDC_LxC0R_F1PC                  LTDC_LxC0R_F1PC_Msk  /*!< blending factor 1, ability for: pixel_alpha * constant_alpha */
24452 #define LTDC_LxC0R_F11PC_Pos             (23U)
24453 #define LTDC_LxC0R_F11PC_Msk             (0x1UL << LTDC_LxC0R_F11PC_Pos)
24454 #define LTDC_LxC0R_F11PC                 LTDC_LxC0R_F11PC_Msk  /*!< blending factor 1, ability for: 1.0 - (pixel_alpha * constant_alpha) */
24455 #define LTDC_LxC0R_P88_Pos               (24U)
24456 #define LTDC_LxC0R_P88_Msk               (0x1UL << LTDC_LxC0R_P88_Pos)
24457 #define LTDC_LxC0R_P88                   LTDC_LxC0R_P88_Msk  /*!< pixel format, ability for: AL88. */
24458 #define LTDC_LxC0R_P44_Pos               (25U)
24459 #define LTDC_LxC0R_P44_Msk               (0x1UL << LTDC_LxC0R_P44_Pos)
24460 #define LTDC_LxC0R_P44                   LTDC_LxC0R_P44_Msk  /*!< pixel format, ability for: AL44. */
24461 #define LTDC_LxC0R_P8_Pos                (26U)
24462 #define LTDC_LxC0R_P8_Msk                (0x1UL << LTDC_LxC0R_P8_Pos)
24463 #define LTDC_LxC0R_P8                    LTDC_LxC0R_P8_Msk  /*!< pixel format, ability for: L8. */
24464 #define LTDC_LxC0R_P4444_Pos             (27U)
24465 #define LTDC_LxC0R_P4444_Msk             (0x1UL << LTDC_LxC0R_P4444_Pos)
24466 #define LTDC_LxC0R_P4444                 LTDC_LxC0R_P4444_Msk  /*!< pixel format, ability for: ARGB4444. */
24467 #define LTDC_LxC0R_P1555_Pos             (28U)
24468 #define LTDC_LxC0R_P1555_Msk             (0x1UL << LTDC_LxC0R_P1555_Pos)
24469 #define LTDC_LxC0R_P1555                 LTDC_LxC0R_P1555_Msk  /*!< pixel format, ability for: ARGB1555. */
24470 #define LTDC_LxC0R_P565_Pos              (29U)
24471 #define LTDC_LxC0R_P565_Msk              (0x1UL << LTDC_LxC0R_P565_Pos)
24472 #define LTDC_LxC0R_P565                  LTDC_LxC0R_P565_Msk  /*!< pixel format, ability for: RGB565. */
24473 #define LTDC_LxC0R_P888_Pos              (30U)
24474 #define LTDC_LxC0R_P888_Msk              (0x1UL << LTDC_LxC0R_P888_Pos)
24475 #define LTDC_LxC0R_P888                  LTDC_LxC0R_P888_Msk  /*!< pixel format, ability for: RGB888. */
24476 #define LTDC_LxC0R_P8888_Pos             (31U)
24477 #define LTDC_LxC0R_P8888_Msk             (0x1UL << LTDC_LxC0R_P8888_Pos)
24478 #define LTDC_LxC0R_P8888                 LTDC_LxC0R_P8888_Msk  /*!< pixel format, ability for: ARGB8888. */
24479 
24480 /* Bit fields for LTDC_LxC1R register */
24481 #define LTDC_LxC1R_YIA_Pos               (0U)
24482 #define LTDC_LxC1R_YIA_Msk               (0x1UL << LTDC_LxC1R_YIA_Pos)
24483 #define LTDC_LxC1R_YIA                   LTDC_LxC1R_YIA_Msk  /*!< YCbCr 422 interleaved ability for that layer.- 0: interleaved not available- 1: interleaved available */
24484 #define LTDC_LxC1R_YSPA_Pos              (1U)
24485 #define LTDC_LxC1R_YSPA_Msk              (0x1UL << LTDC_LxC1R_YSPA_Pos)
24486 #define LTDC_LxC1R_YSPA                  LTDC_LxC1R_YSPA_Msk  /*!< YCbCr 420 semi-planar ability for that layer.- 0: semiplanar not available- 1: semi-planar available */
24487 #define LTDC_LxC1R_YFPA_Pos              (2U)
24488 #define LTDC_LxC1R_YFPA_Msk              (0x1UL << LTDC_LxC1R_YFPA_Pos)
24489 #define LTDC_LxC1R_YFPA                  LTDC_LxC1R_YFPA_Msk  /*!< YCbCr 420 full-planar ability for that layer.- 0: full planar not available- 1: full planar available */
24490 #define LTDC_LxC1R_SCA_Pos               (31U)
24491 #define LTDC_LxC1R_SCA_Msk               (0x1UL << LTDC_LxC1R_SCA_Pos)
24492 #define LTDC_LxC1R_SCA                   LTDC_LxC1R_SCA_Msk  /*!< scaling ability for that layer.- 0: scaling not available- 1: scaling available */
24493 
24494 /* Bit fields for LTDC_LxRCR register */
24495 #define LTDC_LxRCR_IMR_Pos               (0U)
24496 #define LTDC_LxRCR_IMR_Msk               (0x1UL << LTDC_LxRCR_IMR_Pos)
24497 #define LTDC_LxRCR_IMR                   LTDC_LxRCR_IMR_Msk  /*!< immediate reload triggerThis bit is set by software and cleared only by hardware after reload.- 0: no effect- 1: The shadow registers are reloaded immediately. */
24498 #define LTDC_LxRCR_VBR_Pos               (1U)
24499 #define LTDC_LxRCR_VBR_Msk               (0x1UL << LTDC_LxRCR_VBR_Pos)
24500 #define LTDC_LxRCR_VBR                   LTDC_LxRCR_VBR_Msk  /*!< vertical blanking reload requestThis bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set).- 0: no effect- 1: The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area). */
24501 #define LTDC_LxRCR_GRMSK_Pos             (2U)
24502 #define LTDC_LxRCR_GRMSK_Msk             (0x1UL << LTDC_LxRCR_GRMSK_Pos)
24503 #define LTDC_LxRCR_GRMSK                 LTDC_LxRCR_GRMSK_Msk  /*!< shadow reload control: global (centralized) reload maskedThis bit is set and cleared by software.- 0: global reload active (the control from the LTDC_SRCR are enabled)- 1: global reload is masked (the control from the LTDC_SRCR are disabled) */
24504 
24505 /* Bit fields for LTDC_LxCR register */
24506 #define LTDC_LxCR_LEN_Pos                (0U)
24507 #define LTDC_LxCR_LEN_Msk                (0x1UL << LTDC_LxCR_LEN_Pos)
24508 #define LTDC_LxCR_LEN                    LTDC_LxCR_LEN_Msk  /*!< layer enable: the bit is used to enable/disable the presence of this whole layer.This bit is set and cleared by software.- 0: layer disabled- 1: layer enabled */
24509 #define LTDC_LxCR_CKEN_Pos               (1U)
24510 #define LTDC_LxCR_CKEN_Msk               (0x1UL << LTDC_LxCR_CKEN_Pos)
24511 #define LTDC_LxCR_CKEN                   LTDC_LxCR_CKEN_Msk  /*!< color keying enableThis bit is set and cleared by software.- 0: color keying disabled- 1: color keying enabled: if RGB matches, then the ARGB are set to 0. */
24512 #define LTDC_LxCR_VPDEN_Pos              (2U)
24513 #define LTDC_LxCR_VPDEN_Msk              (0x1UL << LTDC_LxCR_VPDEN_Pos)
24514 #define LTDC_LxCR_VPDEN                  LTDC_LxCR_VPDEN_Msk  /*!< vertical pixel duplication enableThis bit is set and cleared by software.- 0: duplication disabled- 1: duplication enabled */
24515 #define LTDC_LxCR_CLUTEN_Pos             (4U)
24516 #define LTDC_LxCR_CLUTEN_Msk             (0x1UL << LTDC_LxCR_CLUTEN_Pos)
24517 #define LTDC_LxCR_CLUTEN                 LTDC_LxCR_CLUTEN_Msk  /*!< color look-up table enableThis bit is set and cleared by software.- 0: color look-up table disabled- 1: color look-up table enabledThe CLUT is only meaningful for L8, AL44 and AL88 pixel format. Refer to Color look-up table (CLUT) */
24518 #define LTDC_LxCR_HMEN_Pos               (8U)
24519 #define LTDC_LxCR_HMEN_Msk               (0x1UL << LTDC_LxCR_HMEN_Pos)
24520 #define LTDC_LxCR_HMEN                   LTDC_LxCR_HMEN_Msk  /*!< horizontal mirroring enableThis bit is set and cleared by software.- 0: mirror disabled- 1: mirror enabled (if so, the color frame buffer start address has to be set to the last byte of the first line, so for instannce: if line is 100 pixels, 24bpp, then address is set to 299) */
24521 #define LTDC_LxCR_DCBEN_Pos              (9U)
24522 #define LTDC_LxCR_DCBEN_Msk              (0x1UL << LTDC_LxCR_DCBEN_Pos)
24523 #define LTDC_LxCR_DCBEN                  LTDC_LxCR_DCBEN_Msk  /*!< default color blending enableThis bit is set and cleared by software.- 0: blending disabled- 1: blending enabled */
24524 
24525 /* Bit fields for LTDC_LxWHPCR register */
24526 #define LTDC_LxWHPCR_WHSTPOS_Pos         (0U)
24527 #define LTDC_LxWHPCR_WHSTPOS_Msk         (0xfffUL << LTDC_LxWHPCR_WHSTPOS_Pos)
24528 #define LTDC_LxWHPCR_WHSTPOS             LTDC_LxWHPCR_WHSTPOS_Msk  /*!< window horizontal start positionThese bits configure the first visible pixel of a line of the layer window.WHSTPOS[15:0] must be >= AAW[15:0] bits (programmed in LTDC_AWCR register). */
24529 #define LTDC_LxWHPCR_WHSPPOS_Pos         (16U)
24530 #define LTDC_LxWHPCR_WHSPPOS_Msk         (0xfffUL << LTDC_LxWHPCR_WHSPPOS_Pos)
24531 #define LTDC_LxWHPCR_WHSPPOS             LTDC_LxWHPCR_WHSPPOS_Msk  /*!< window horizontal stop positionThese bits configure the last visible pixel of a line of the layer window.WHSPPOS[15:0] must be <= AHBP[15:0] bits + 1 (programmed in LTDC_BPCR register). */
24532 
24533 /* Bit fields for LTDC_LxWVPCR register */
24534 #define LTDC_LxWVPCR_WVSTPOS_Pos         (0U)
24535 #define LTDC_LxWVPCR_WVSTPOS_Msk         (0xfffUL << LTDC_LxWVPCR_WVSTPOS_Pos)
24536 #define LTDC_LxWVPCR_WVSTPOS             LTDC_LxWVPCR_WVSTPOS_Msk  /*!< window vertical start positionThese bits configure the first visible line of the layer window.WVSTPOS[15:0] must be >= AAH[15:0] bits (programmed in LTDC_AWCR register). */
24537 #define LTDC_LxWVPCR_WVSPPOS_Pos         (16U)
24538 #define LTDC_LxWVPCR_WVSPPOS_Msk         (0xfffUL << LTDC_LxWVPCR_WVSPPOS_Pos)
24539 #define LTDC_LxWVPCR_WVSPPOS             LTDC_LxWVPCR_WVSPPOS_Msk  /*!< window vertical stop positionThese bits configure the last visible line of the layer window.WVSPPOS[11:0] must be <= AVBP[15:0] bits + 1 (programmed in LTDC_BPCR register). */
24540 
24541 /* Bit fields for LTDC_LxCKCR register */
24542 #define LTDC_LxCKCR_CKBLUE_Pos           (0U)
24543 #define LTDC_LxCKCR_CKBLUE_Msk           (0xffUL << LTDC_LxCKCR_CKBLUE_Pos)
24544 #define LTDC_LxCKCR_CKBLUE               LTDC_LxCKCR_CKBLUE_Msk  /*!< color key blue value */
24545 #define LTDC_LxCKCR_CKGREEN_Pos          (8U)
24546 #define LTDC_LxCKCR_CKGREEN_Msk          (0xffUL << LTDC_LxCKCR_CKGREEN_Pos)
24547 #define LTDC_LxCKCR_CKGREEN              LTDC_LxCKCR_CKGREEN_Msk  /*!< color key green value */
24548 #define LTDC_LxCKCR_CKRED_Pos            (16U)
24549 #define LTDC_LxCKCR_CKRED_Msk            (0xffUL << LTDC_LxCKCR_CKRED_Pos)
24550 #define LTDC_LxCKCR_CKRED                LTDC_LxCKCR_CKRED_Msk  /*!< color key red value */
24551 
24552 /* Bit fields for LTDC_LxPFCR register */
24553 #define LTDC_LxPFCR_PF_Pos               (0U)
24554 #define LTDC_LxPFCR_PF_Msk               (0x7UL << LTDC_LxPFCR_PF_Pos)
24555 #define LTDC_LxPFCR_PF                   LTDC_LxPFCR_PF_Msk  /*!< pixel formatThese bits configure the pixel format- 000: ARGB8888- 001: RGB888- 010: RGB565- 011: ARGB1555- 100: ARGB4444- 101: L8 (8-bit luminance)- 110: AL44 (4-bit alpha, 4-bit luminance)- 111: AL88 (8-bit alpha, 8-bit luminance) */
24556 
24557 /* Bit fields for LTDC_LxCACR register */
24558 #define LTDC_LxCACR_CONSTA_Pos           (0U)
24559 #define LTDC_LxCACR_CONSTA_Msk           (0xffUL << LTDC_LxCACR_CONSTA_Pos)
24560 #define LTDC_LxCACR_CONSTA               LTDC_LxCACR_CONSTA_Msk  /*!< constant alphaThese bits configure the constant alpha used for blending. The constant alpha is divided by 255 by hardware.Example: if the programmed constant alpha is 0xFF, the constant alpha value is 255 / 255 = 1. */
24561 
24562 /* Bit fields for LTDC_LxDCCR register */
24563 #define LTDC_LxDCCR_DCBLUE_Pos           (0U)
24564 #define LTDC_LxDCCR_DCBLUE_Msk           (0xffUL << LTDC_LxDCCR_DCBLUE_Pos)
24565 #define LTDC_LxDCCR_DCBLUE               LTDC_LxDCCR_DCBLUE_Msk  /*!< default color blueThese bits configure the default blue value. */
24566 #define LTDC_LxDCCR_DCGREEN_Pos          (8U)
24567 #define LTDC_LxDCCR_DCGREEN_Msk          (0xffUL << LTDC_LxDCCR_DCGREEN_Pos)
24568 #define LTDC_LxDCCR_DCGREEN              LTDC_LxDCCR_DCGREEN_Msk  /*!< default color greenThese bits configure the default green value. */
24569 #define LTDC_LxDCCR_DCRED_Pos            (16U)
24570 #define LTDC_LxDCCR_DCRED_Msk            (0xffUL << LTDC_LxDCCR_DCRED_Pos)
24571 #define LTDC_LxDCCR_DCRED                LTDC_LxDCCR_DCRED_Msk  /*!< default color redThese bits configure the default red value. */
24572 #define LTDC_LxDCCR_DCALPHA_Pos          (24U)
24573 #define LTDC_LxDCCR_DCALPHA_Msk          (0xffUL << LTDC_LxDCCR_DCALPHA_Pos)
24574 #define LTDC_LxDCCR_DCALPHA              LTDC_LxDCCR_DCALPHA_Msk  /*!< default color alphaThese bits configure the default alpha value. */
24575 
24576 /* Bit fields for LTDC_LxBFCR register */
24577 #define LTDC_LxBFCR_BF2_Pos              (0U)
24578 #define LTDC_LxBFCR_BF2_Msk              (0x7UL << LTDC_LxBFCR_BF2_Pos)
24579 #define LTDC_LxBFCR_BF2                  LTDC_LxBFCR_BF2_Msk  /*!< blending factor 2These bits select the blending factor F2- 000: reserved- 001: reserved- 010: reserved- 011: reserved- 100: reserved- 101: 1 - constant alpha- 110: reserved- 111: 1 - (pixel alpha x constant alpha) */
24580 #define LTDC_LxBFCR_BF1_Pos              (8U)
24581 #define LTDC_LxBFCR_BF1_Msk              (0x7UL << LTDC_LxBFCR_BF1_Pos)
24582 #define LTDC_LxBFCR_BF1                  LTDC_LxBFCR_BF1_Msk  /*!< blending factor 1These bits select the blending factor F1.- 000: reserved- 001: reserved- 010: reserved- 011: reserved- 100: constant alpha- 101: reserved- 110: pixel alpha x constant alpha- 111: reserved */
24583 #define LTDC_LxBFCR_BOR_Pos              (16U)
24584 #define LTDC_LxBFCR_BOR_Msk              (0x1UL << LTDC_LxBFCR_BOR_Pos)
24585 #define LTDC_LxBFCR_BOR                  LTDC_LxBFCR_BOR_Msk  /*!< blending orderThese bits select the blending orderBOR.BOR= 0000 is for the most background layer (usually hidden behind others)BOR= 1111 is for the most foreground layer (always visible, never hidden by any other).In case of inconsistency, like two layers at same order, the blending engine reverses to BOR[LayerID] = LayerID-1, so that Layer3 is in foreground and Layer1 is in background.Note: if the Layer3 is set as secure, to guarantee it is on the foreground, it should be configured with BOR(Layer3)=1111. */
24586 
24587 /* Bit fields for LTDC_LxBLCR register */
24588 #define LTDC_LxBLCR_BL_Pos               (0U)
24589 #define LTDC_LxBLCR_BL_Msk               (0x1fUL << LTDC_LxBLCR_BL_Pos)
24590 #define LTDC_LxBLCR_BL                   LTDC_LxBLCR_BL_Msk  /*!< burst length- 0x00: maximum burst length (16 words 64bit, thus 128 Bytes)- 0x01: 1 word (of 64bit) per burst..- 0x10: 16 words (of 64bit) per burst- 0x11: reserved...- 0xFF: reserved. */
24591 
24592 /* Bit fields for LTDC_LxPCR register */
24593 #define LTDC_LxPCR_YCEN_Pos              (3U)
24594 #define LTDC_LxPCR_YCEN_Msk              (0x1UL << LTDC_LxPCR_YCEN_Pos)
24595 #define LTDC_LxPCR_YCEN                  LTDC_LxPCR_YCEN_Msk  /*!< YCbCr-to-RGB Conversion Enable:- 0: conversion disabled.- 1: YCbCr conversion enabled, using the YCM setting above. */
24596 #define LTDC_LxPCR_YCM_Pos               (4U)
24597 #define LTDC_LxPCR_YCM_Msk               (0x3UL << LTDC_LxPCR_YCM_Pos)
24598 #define LTDC_LxPCR_YCM                   LTDC_LxPCR_YCM_Msk  /*!< YCbCr Conversion ModeDefined the type of input that is considered and converted to a YCbCr 444:- 00: interleaved 422 (Cb and Cr component are replicated horizontally for pixels P and P+1)- 01: semi-Planar 420: (Cb and Cr component are replicated horizontally and vertically. The layer main configuration defines the access to the Y buffer, and auxiliary registers define the access to the Cb and Cr buffers).- 10: full-Planar 420: (Cb and Cr component are replicated horizontally and vertically. The layer main configuration defines the access to the Y buffer, and auxiliary registers define the access to the Cb and Cr buffers).- 11: reserved. */
24599 #define LTDC_LxPCR_YF_Pos                (6U)
24600 #define LTDC_LxPCR_YF_Msk                (0x1UL << LTDC_LxPCR_YF_Pos)
24601 #define LTDC_LxPCR_YF                    LTDC_LxPCR_YF_Msk  /*!< Y Component FirstDefines if the byte 0 of a word (in LSB) contains the Y component.- 0: Y component disabled (thus Cr or Cb component is on byte 0)- 1: Y component enabled (thus Y component is on byte 0) */
24602 #define LTDC_LxPCR_CBF_Pos               (7U)
24603 #define LTDC_LxPCR_CBF_Msk               (0x1UL << LTDC_LxPCR_CBF_Pos)
24604 #define LTDC_LxPCR_CBF                   LTDC_LxPCR_CBF_Msk  /*!< Cb Component FirstDefines if the byte 0 and 1 of a word (in LSB) contains the Cb component. The setting impacts only for interleaved and semi-planar modes, as it has no meaning in full-planar mode)- 0: Cb disabled (thus Cr component is on byte 0 and 1)- 1: Cb enabled (thus Cb component is on byte 0 and 1) */
24605 #define LTDC_LxPCR_OF_Pos                (8U)
24606 #define LTDC_LxPCR_OF_Msk                (0x1UL << LTDC_LxPCR_OF_Pos)
24607 #define LTDC_LxPCR_OF                    LTDC_LxPCR_OF_Msk  /*!< Odd Pixel FirstDefines if the byte 0 of a word (in LSB) contains the Odd pixel.- 0: odd pixel disabled (thus even pixel on byte 0)- 1: odd pixel enabled (thus odd pixel on byte 0) */
24608 #define LTDC_LxPCR_YREN_Pos              (9U)
24609 #define LTDC_LxPCR_YREN_Msk              (0x1UL << LTDC_LxPCR_YREN_Pos)
24610 #define LTDC_LxPCR_YREN                  LTDC_LxPCR_YREN_Msk  /*!< Y Rescale EnableWhen enabled, incoming Y values in range 16..235 are re-scaled to range 0..255, - 0: rescaling disabled.- 1: rescaling enabled. */
24611 
24612 /* Bit fields for LTDC_LxCFBAR register */
24613 #define LTDC_LxCFBAR_CFBADD_Pos          (0U)
24614 #define LTDC_LxCFBAR_CFBADD_Msk          (0xffffffffUL << LTDC_LxCFBAR_CFBADD_Pos)
24615 #define LTDC_LxCFBAR_CFBADD              LTDC_LxCFBAR_CFBADD_Msk  /*!< color frame buffer start addressThese bits define the color frame buffer start address. */
24616 
24617 /* Bit fields for LTDC_LxCFBLR register */
24618 #define LTDC_LxCFBLR_CFBLL_Pos           (0U)
24619 #define LTDC_LxCFBLR_CFBLL_Msk           (0x3fffUL << LTDC_LxCFBLR_CFBLL_Pos)
24620 #define LTDC_LxCFBLR_CFBLL               LTDC_LxCFBLR_CFBLL_Msk  /*!< color frame buffer line lengthThese bits define the length of one line of pixels in bytes + 7.The line length is computed as follows:active high width * number of bytes per pixel + 7. */
24621 #define LTDC_LxCFBLR_CFBP_Pos            (16U)
24622 #define LTDC_LxCFBLR_CFBP_Msk            (0x7fffUL << LTDC_LxCFBLR_CFBP_Pos)
24623 #define LTDC_LxCFBLR_CFBP                LTDC_LxCFBLR_CFBP_Msk  /*!< color frame buffer pitch in bytesThese bits define the pitch that is the increment from the start of one line of pixels to the start of the next line in bytes.Negative values (with msb bit = 1) are allowed, to read the buffer from bottom to top, and thus to flip is vertically. When vertically flipped, as the address register must provide the address of the first line to be read, the address register must point to the start of the bottom line of the buffer. */
24624 
24625 /* Bit fields for LTDC_LxCFBLNR register */
24626 #define LTDC_LxCFBLNR_CFBLNBR_Pos        (0U)
24627 #define LTDC_LxCFBLNR_CFBLNBR_Msk        (0xfffUL << LTDC_LxCFBLNR_CFBLNBR_Pos)
24628 #define LTDC_LxCFBLNR_CFBLNBR            LTDC_LxCFBLNR_CFBLNBR_Msk  /*!< frame buffer line numberThese bits define the number of lines in the frame buffer that corresponds to the active high width. */
24629 
24630 /* Bit fields for LTDC_L1AFBA0R register */
24631 #define LTDC_L1AFBA0R_AFBADD0_Pos        (0U)
24632 #define LTDC_L1AFBA0R_AFBADD0_Msk        (0xffffffffUL << LTDC_L1AFBA0R_AFBADD0_Pos)
24633 #define LTDC_L1AFBA0R_AFBADD0            LTDC_L1AFBA0R_AFBADD0_Msk  /*!< color frame buffer start addressThese bits define the color frame buffer start address. */
24634 
24635 /* Bit fields for LTDC_LxAFBA1R register */
24636 #define LTDC_L1AFBA1R_AFBADD1_Pos        (0U)
24637 #define LTDC_L1AFBA1R_AFBADD1_Msk        (0xffffffffUL << LTDC_L1AFBA1R_AFBADD1_Pos)
24638 #define LTDC_L1AFBA1R_AFBADD1            LTDC_L1AFBA1R_AFBADD1_Msk  /*!< color frame buffer start addressThese bits define the color frame buffer start address. */
24639 
24640 /* Bit fields for LTDC_LxAFBLR register */
24641 #define LTDC_L1AFBLR_AFBLL_Pos           (0U)
24642 #define LTDC_L1AFBLR_AFBLL_Msk           (0xffffUL << LTDC_L1AFBLR_AFBLL_Pos)
24643 #define LTDC_L1AFBLR_AFBLL               LTDC_L1AFBLR_AFBLL_Msk  /*!< color frame buffer line lengthThese bits define the length of one line of pixels in bytes + 7.The line length is computed as follows:active high width * number of bytes per pixel + 7. */
24644 #define LTDC_L1AFBLR_AFBP_Pos            (16U)
24645 #define LTDC_L1AFBLR_AFBP_Msk            (0xffffUL << LTDC_L1AFBLR_AFBP_Pos)
24646 #define LTDC_L1AFBLR_AFBP                LTDC_L1AFBLR_AFBP_Msk  /*!< color frame buffer pitch in bytesThese bits define the pitch that is the increment from the start of one line of pixels to the start of the next line in bytes.Negative values (with msb bit = 1) are allowed, to read the buffer from bottom to top, and thus to flip is vertically. When vertically flipped, as the address register must provide the address of the first line to be read, the address register must point to the start of the bottom line of the buffer. */
24647 
24648 /* Bit fields for LTDC_LxAFBLNR register */
24649 #define LTDC_L1AFBLNR_AFBLNBR_Pos        (0U)
24650 #define LTDC_L1AFBLNR_AFBLNBR_Msk        (0xffffUL << LTDC_L1AFBLNR_AFBLNBR_Pos)
24651 #define LTDC_L1AFBLNR_AFBLNBR            LTDC_L1AFBLNR_AFBLNBR_Msk  /*!< frame buffer line numberThese bits define the number of lines in the frame buffer that corresponds to the active high width. */
24652 
24653 /* Bit fields for LTDC_LxCLUTWR register */
24654 #define LTDC_LxCLUTWR_BLUE_Pos           (0U)
24655 #define LTDC_LxCLUTWR_BLUE_Msk           (0xffUL << LTDC_LxCLUTWR_BLUE_Pos)
24656 #define LTDC_LxCLUTWR_BLUE               LTDC_LxCLUTWR_BLUE_Msk  /*!< blue valueThese bits configure the blue value. */
24657 #define LTDC_LxCLUTWR_GREEN_Pos          (8U)
24658 #define LTDC_LxCLUTWR_GREEN_Msk          (0xffUL << LTDC_LxCLUTWR_GREEN_Pos)
24659 #define LTDC_LxCLUTWR_GREEN              LTDC_LxCLUTWR_GREEN_Msk  /*!< green valueThese bits configure the green value. */
24660 #define LTDC_LxCLUTWR_RED_Pos            (16U)
24661 #define LTDC_LxCLUTWR_RED_Msk            (0xffUL << LTDC_LxCLUTWR_RED_Pos)
24662 #define LTDC_LxCLUTWR_RED                LTDC_LxCLUTWR_RED_Msk  /*!< red valueThese bits configure the red value. */
24663 #define LTDC_LxCLUTWR_CLUTADD_Pos        (24U)
24664 #define LTDC_LxCLUTWR_CLUTADD_Msk        (0xffUL << LTDC_LxCLUTWR_CLUTADD_Pos)
24665 #define LTDC_LxCLUTWR_CLUTADD            LTDC_LxCLUTWR_CLUTADD_Msk  /*!< CLUT addressThese bits configure the CLUT address (color position within the CLUT) of each RGB value. */
24666 
24667 /* Bit fields for LTDC_LxCYR0R register */
24668 #define LTDC_LxCYR0R_CR2R_Pos            (0U)
24669 #define LTDC_LxCYR0R_CR2R_Msk            (0x3ffUL << LTDC_LxCYR0R_CR2R_Pos)
24670 #define LTDC_LxCYR0R_CR2R                LTDC_LxCYR0R_CR2R_Msk  /*!< Cr-to-Red coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */
24671 #define LTDC_LxCYR0R_CB2B_Pos            (16U)
24672 #define LTDC_LxCYR0R_CB2B_Msk            (0x3ffUL << LTDC_LxCYR0R_CB2B_Pos)
24673 #define LTDC_LxCYR0R_CB2B                LTDC_LxCYR0R_CB2B_Msk  /*!< Cb-to-Blue coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */
24674 
24675 /* Bit fields for LTDC_LxCYR1R register */
24676 #define LTDC_LxCYR1R_CR2G_Pos            (0U)
24677 #define LTDC_LxCYR1R_CR2G_Msk            (0x3ffUL << LTDC_LxCYR1R_CR2G_Pos)
24678 #define LTDC_LxCYR1R_CR2G                LTDC_LxCYR1R_CR2G_Msk  /*!< Cr-to-Green coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */
24679 #define LTDC_LxCYR1R_CB2G_Pos            (16U)
24680 #define LTDC_LxCYR1R_CB2G_Msk            (0x3ffUL << LTDC_LxCYR1R_CB2G_Pos)
24681 #define LTDC_LxCYR1R_CB2G                LTDC_LxCYR1R_CB2G_Msk  /*!< Cb-to-Green coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */
24682 
24683 /* Bit fields for LTDC_LxFPF0R register */
24684 #define LTDC_LxFPF0R_APOS_Pos            (0U)
24685 #define LTDC_LxFPF0R_APOS_Msk            (0x1fUL << LTDC_LxFPF0R_APOS_Pos)
24686 #define LTDC_LxFPF0R_APOS                LTDC_LxFPF0R_APOS_Msk  /*!< Location of the alpha component inside the pixel memory word (in bits). */
24687 
24688 #define LTDC_LxFPF0R_ALEN_Pos            (5U)
24689 #define LTDC_LxFPF0R_ALEN_Msk            (0xfUL << LTDC_LxFPF0R_ALEN_Pos)
24690 #define LTDC_LxFPF0R_ALEN                LTDC_LxFPF0R_ALEN_Msk  /*!< Width of the alpha component (in bits). */
24691 
24692 #define LTDC_LxFPF0R_RPOS_Pos            (9U)
24693 #define LTDC_LxFPF0R_RPOS_Msk            (0x1fUL << LTDC_LxFPF0R_RPOS_Pos)
24694 #define LTDC_LxFPF0R_RPOS                LTDC_LxFPF0R_RPOS_Msk  /*!< Location of the red component inside the pixel memory word (in bits). */
24695 
24696 #define LTDC_LxFPF0R_RLEN_Pos            (14U)
24697 #define LTDC_LxFPF0R_RLEN_Msk            (0xfUL << LTDC_LxFPF0R_RLEN_Pos)
24698 #define LTDC_LxFPF0R_RLEN                LTDC_LxFPF0R_RLEN_Msk  /*!< Width of the red component (in bits). */
24699 
24700 /* Bit fields for LTDC_LxFPF1R register */
24701 #define LTDC_LxFPF1R_GPOS_Pos            (0U)
24702 #define LTDC_LxFPF1R_GPOS_Msk            (0x1fUL << LTDC_LxFPF1R_GPOS_Pos)
24703 #define LTDC_LxFPF1R_GPOS                LTDC_LxFPF1R_GPOS_Msk  /*!< Location of the alpha component inside the pixel memory word (in bits). */
24704 
24705 #define LTDC_LxFPF1R_GLEN_Pos            (5U)
24706 #define LTDC_LxFPF1R_GLEN_Msk            (0xfUL << LTDC_LxFPF1R_GLEN_Pos)
24707 #define LTDC_LxFPF1R_GLEN                LTDC_LxFPF1R_GLEN_Msk  /*!< Width of the alpha component (in bits). */
24708 
24709 #define LTDC_LxFPF1R_BPOS_Pos            (9U)
24710 #define LTDC_LxFPF1R_BPOS_Msk            (0x1fUL << LTDC_LxFPF1R_BPOS_Pos)
24711 #define LTDC_LxFPF1R_BPOS                LTDC_LxFPF1R_BPOS_Msk  /*!< Location of the red component inside the pixel memory word (in bits). */
24712 
24713 #define LTDC_LxFPF1R_BLEN_Pos            (14U)
24714 #define LTDC_LxFPF1R_BLEN_Msk            (0xfUL << LTDC_LxFPF1R_BLEN_Pos)
24715 #define LTDC_LxFPF1R_BLEN                LTDC_LxFPF1R_BLEN_Msk  /*!< Width of the red component (in bits). */
24716 
24717 #define LTDC_LxFPF1R_PSIZE_Pos            (18U)
24718 #define LTDC_LxFPF1R_PSIZE_Msk            (0x7UL << LTDC_LxFPF1R_PSIZE_Pos)
24719 #define LTDC_LxFPF1R_PSIZE                LTDC_LxFPF1R_PSIZE_Msk  /*!< Width of the red component (in bits). */
24720 
24721 
24722 /******************************************************************************/
24723 /*                                                                            */
24724 /*                       Memory Cipher Engine (MCE)                           */
24725 /*                                                                            */
24726 /******************************************************************************/
24727 /********************  Bit definition for MCE_CR register  ********************/
24728 #define MCE_CR_GLOCK_Pos               (0U)
24729 #define MCE_CR_GLOCK_Msk               (0x1UL << MCE_CR_GLOCK_Pos)             /*!< 0x00000001 */
24730 #define MCE_CR_GLOCK                   MCE_CR_GLOCK_Msk                        /*!< MCE global lock */
24731 #define MCE_CR_MKLOCK_Pos              (1U)
24732 #define MCE_CR_MKLOCK_Msk              (0x1UL << MCE_CR_MKLOCK_Pos)            /*!< 0x00000002 */
24733 #define MCE_CR_MKLOCK                  MCE_CR_MKLOCK_Msk                       /*!< MCE master and fast master keys lock */
24734 #define MCE_CR_CIPHERSEL_Pos           (4U)
24735 #define MCE_CR_CIPHERSEL_Msk           (0x3UL << MCE_CR_CIPHERSEL_Pos)         /*!< 0x00000030 */
24736 #define MCE_CR_CIPHERSEL               MCE_CR_CIPHERSEL_Msk                    /*!< MCE Cipher selection */
24737 #define MCE_CR_CIPHERSEL_0             (0x1UL << MCE_CR_CIPHERSEL_Pos)         /*!< 0x00000010 */
24738 #define MCE_CR_CIPHERSEL_1             (0x2UL << MCE_CR_CIPHERSEL_Pos)         /*!< 0x00000020 */
24739 
24740 /********************  Bit definition for MCE_SR register  ********************/
24741 #define MCE_SR_MKVALID_Pos             (0U)
24742 #define MCE_SR_MKVALID_Msk             (0x1UL << MCE_SR_MKVALID_Pos)           /*!< 0x00000001 */
24743 #define MCE_SR_MKVALID                 MCE_SR_MKVALID_Msk                      /*!< MCE master key valid flag */
24744 #define MCE_SR_FMKVALID_Pos            (2U)
24745 #define MCE_SR_FMKVALID_Msk            (0x1UL << MCE_SR_FMKVALID_Pos)          /*!< 0x00000004 */
24746 #define MCE_SR_FMKVALID                 MCE_SR_FMKVALID_Msk                    /*!< MCE fast master key valid flag */
24747 #define MCE_SR_ENCDIS_Pos              (4U)
24748 #define MCE_SR_ENCDIS_Msk              (0x1UL << MCE_SR_ENCDIS_Pos)            /*!< 0x00000010 */
24749 #define MCE_SR_ENCDIS                  MCE_SR_ENCDIS_Msk                       /*!< MCE encryption disabled flag */
24750 
24751 /********************  Bit definition for MCE_IASR register  ******************/
24752 #define MCE_IASR_IAEF_Pos              (1U)
24753 #define MCE_IASR_IAEF_Msk              (0x1UL << MCE_IASR_IAEF_Pos)             /*!< 0x00000002 */
24754 #define MCE_IASR_IAEF                  MCE_IASR_IAEF_Msk                        /*!< MCE illegal access error flag */
24755 
24756 /********************  Bit definition for MCE_IACR register  ******************/
24757 #define MCE_IACR_IAEF_Pos              (1U)
24758 #define MCE_IACR_IAEF_Msk              (0x1UL << MCE_IACR_IAEF_Pos)             /*!< 0x00000002 */
24759 #define MCE_IACR_IAEF                  MCE_IACR_IAEF_Msk                        /*!< MCE illegal access error clear bit */
24760 
24761 /********************  Bit definition for MCE_IAIER register  *****************/
24762 #define MCE_IAIER_IAEIE_Pos            (1U)
24763 #define MCE_IAIER_IAEIE_Msk            (0x1UL << MCE_IAIER_IAEIE_Pos)           /*!< 0x00000002 */
24764 #define MCE_IAIER_IAEIE                MCE_IAIER_IAEIE_Msk                      /*!< MCE illegal access error interrupt enable */
24765 
24766 /********************  Bit definition for MCE_IADDR register  *****************/
24767 #define MCE_IADDR_IADD_Pos             (0U)
24768 #define MCE_IADDR_IADD_Msk             (0xFFFFFFFFUL << MCE_IADDR_IADD_Pos)    /*!< 0xFFFFFFFF */
24769 #define MCE_IADDR_IADD                 MCE_IADDR_IADD_Msk                      /*!< MCE illegal access */
24770 
24771 /********************  Bit definition for MCE_REGCR register  *****************/
24772 #define MCE_REGCR_BREN_Pos             (0U)
24773 #define MCE_REGCR_BREN_Msk             (0x1UL << MCE_REGCR_BREN_Pos)            /*!< 0x00000001 */
24774 #define MCE_REGCR_BREN                 MCE_REGCR_BREN_Msk                       /*!< MCE base region enable */
24775 #define MCE_REGCR_CTXID_Pos            (9U)
24776 #define MCE_REGCR_CTXID_Msk            (0x3UL << MCE_REGCR_CTXID_Pos)           /*!< 0x00000600 */
24777 #define MCE_REGCR_CTXID                MCE_REGCR_CTXID_Msk                      /*!< MCE context ID */
24778 #define MCE_REGCR_CTXID_0              (0x1UL << MCE_REGCR_CTXID_Pos)           /*!< 0x00000200 */
24779 #define MCE_REGCR_CTXID_1              (0x2UL << MCE_REGCR_CTXID_Pos)           /*!< 0x00000400 */
24780 #define MCE_REGCR_ENC_Pos              (14U)
24781 #define MCE_REGCR_ENC_Msk              (0x3UL << MCE_REGCR_ENC_Pos)             /*!< 0x0000C000 */
24782 #define MCE_REGCR_ENC                  MCE_REGCR_ENC_Msk                        /*!< MCE encrypted region */
24783 #define MCE_REGCR_ENC_0                (0x1UL << MCE_REGCR_ENC_Pos)             /*!< 0x00004000 */
24784 #define MCE_REGCR_ENC_1                (0x2UL << MCE_REGCR_ENC_Pos)             /*!< 0x00008000 */
24785 
24786 /********************  Bit definition for MCE_SADDR register  *****************/
24787 #define MCE_SADDR_BADDSTART_Pos        (12U)
24788 #define MCE_SADDR_BADDSTART_Msk        (0xFFFFFUL << MCE_SADDR_BADDSTART_Pos)   /*!< 0xFFFFF000 */
24789 #define MCE_SADDR_BADDSTART            MCE_SADDR_BADDSTART_Msk                  /*!< MCE region address start */
24790 
24791 /********************  Bit definition for MCE_EADDR register  *****************/
24792 #define MCE_EADDR_BADDEND_Pos          (12U)
24793 #define MCE_EADDR_BADDEND_Msk          (0xFFFFFUL << MCE_EADDR_BADDEND_Pos)     /*!< 0xFFFFF000 */
24794 #define MCE_EADDR_BADDEND              MCE_EADDR_BADDEND_Msk                    /*!< MCE region address end */
24795 
24796 /********************  Bit definition for MCE_MKEYR0 register  ****************/
24797 #define MCE_MKEYR0_MKEY_Pos            (0U)
24798 #define MCE_MKEYR0_MKEY_Msk            (0xFFFFFFFFUL << MCE_MKEYR0_MKEY_Pos)    /*!< 0xFFFFFFFF */
24799 #define MCE_MKEYR0_MKEY                MCE_MKEYR0_MKEY_Msk                      /*!< MCE master key, bits [31:0] */
24800 
24801 /********************  Bit definition for MCE_MKEYR1 register  ****************/
24802 #define MCE_MKEYR1_MKEY_Pos            (0U)
24803 #define MCE_MKEYR1_MKEY_Msk            (0xFFFFFFFFUL << MCE_MKEYR1_MKEY_Pos)    /*!< 0xFFFFFFFF */
24804 #define MCE_MKEYR1_MKEY                MCE_MKEYR1_MKEY_Msk                      /*!< MCE master key, bits [63:32] */
24805 
24806 /********************  Bit definition for MCE_MKEYR2 register  ****************/
24807 #define MCE_MKEYR2_MKEY_Pos            (0U)
24808 #define MCE_MKEYR2_MKEY_Msk            (0xFFFFFFFFUL << MCE_MKEYR2_MKEY_Pos)    /*!< 0xFFFFFFFF */
24809 #define MCE_MKEYR2_MKEY                MCE_MKEYR2_MKEY_Msk                      /*!< MCE master key, bits [95:64] */
24810 
24811 /********************  Bit definition for MCE_MKEYR3 register  ****************/
24812 #define MCE_MKEYR3_MKEY_Pos            (0U)
24813 #define MCE_MKEYR3_MKEY_Msk            (0xFFFFFFFFUL << MCE_MKEYR3_MKEY_Pos)    /*!< 0xFFFFFFFF */
24814 #define MCE_MKEYR3_MKEY                MCE_MKEYR3_MKEY_Msk                      /*!< MCE master key, bits [127:96] */
24815 
24816 /********************  Bit definition for MCE_MKEYR4 register  ****************/
24817 #define MCE_MKEYR4_MKEY_Pos            (0U)
24818 #define MCE_MKEYR4_MKEY_Msk            (0xFFFFFFFFUL << MCE_MKEYR4_MKEY_Pos)    /*!< 0xFFFFFFFF */
24819 #define MCE_MKEYR4_MKEY                MCE_MKEYR4_MKEY_Msk                      /*!< MCE master key, bits [159:128] */
24820 
24821 /********************  Bit definition for MCE_MKEYR5 register  ****************/
24822 #define MCE_MKEYR5_MKEY_Pos            (0U)
24823 #define MCE_MKEYR5_MKEY_Msk            (0xFFFFFFFFUL << MCE_MKEYR5_MKEY_Pos)    /*!< 0xFFFFFFFF */
24824 #define MCE_MKEYR5_MKEY                MCE_MKEYR5_MKEY_Msk                      /*!< MCE master key, bits [191:160] */
24825 
24826 /********************  Bit definition for MCE_MKEYR6 register  ****************/
24827 #define MCE_MKEYR6_MKEY_Pos            (0U)
24828 #define MCE_MKEYR6_MKEY_Msk            (0xFFFFFFFFUL << MCE_MKEYR6_MKEY_Pos)    /*!< 0xFFFFFFFF */
24829 #define MCE_MKEYR6_MKEY                MCE_MKEYR6_MKEY_Msk                      /*!< MCE master key, bits [223:192] */
24830 
24831 /********************  Bit definition for MCE_MKEYR7 register  ****************/
24832 #define MCE_MKEYR7_MKEY_Pos            (0U)
24833 #define MCE_MKEYR7_MKEY_Msk            (0xFFFFFFFFUL << MCE_MKEYR7_MKEY_Pos)    /*!< 0xFFFFFFFF */
24834 #define MCE_MKEYR7_MKEY                MCE_MKEYR7_MKEY_Msk                      /*!< MCE master key, bits [255:224] */
24835 
24836 /********************  Bit definition for MCE_FMKEYR0 register  ***************/
24837 #define MCE_FMKEYR0_FMKEY_Pos          (0U)
24838 #define MCE_FMKEYR0_FMKEY_Msk          (0xFFFFFFFFUL << MCE_FMKEYR0_FMKEY_Pos)  /*!< 0xFFFFFFFF */
24839 #define MCE_FMKEYR0_FMKEY              MCE_FMKEYR0_FMKEY_Msk                    /*!< MCE fast master key, bits [31:0] */
24840 
24841 /********************  Bit definition for MCE_FMKEYR1 register  ***************/
24842 #define MCE_FMKEYR1_FMKEY_Pos          (0U)
24843 #define MCE_FMKEYR1_FMKEY_Msk          (0xFFFFFFFFUL << MCE_FMKEYR1_FMKEY_Pos)  /*!< 0xFFFFFFFF */
24844 #define MCE_FMKEYR1_FMKEY              MCE_FMKEYR1_FMKEY_Msk                    /*!< MCE fast master key, bits [63:32] */
24845 
24846 /********************  Bit definition for MCE_FMKEYR2 register  ***************/
24847 #define MCE_FMKEYR2_FMKEY_Pos          (0U)
24848 #define MCE_FMKEYR2_FMKEY_Msk          (0xFFFFFFFFUL << MCE_FMKEYR2_FMKEY_Pos)  /*!< 0xFFFFFFFF */
24849 #define MCE_FMKEYR2_FMKEY              MCE_FMKEYR2_FMKEY_Msk                    /*!< MCE fast master key, bits [95:64] */
24850 
24851 /********************  Bit definition for MCE_FMKEYR3 register  ***************/
24852 #define MCE_FMKEYR3_FMKEY_Pos          (0U)
24853 #define MCE_FMKEYR3_FMKEY_Msk          (0xFFFFFFFFUL << MCE_FMKEYR3_FMKEY_Pos)  /*!< 0xFFFFFFFF */
24854 #define MCE_FMKEYR3_FMKEY              MCE_FMKEYR3_FMKEY_Msk                    /*!< MCE fast master key, bits [127:96] */
24855 
24856 /********************  Bit definition for MCE_FMKEYR4 register  ****************/
24857 #define MCE_FMKEYR4_FMKEY_Pos          (0U)
24858 #define MCE_FMKEYR4_FMKEY_Msk          (0xFFFFFFFFUL << MCE_FMKEYR4_FMKEY_Pos)  /*!< 0xFFFFFFFF */
24859 #define MCE_FMKEYR4_FMKEY              MCE_FMKEYR4_FMKEY_Msk                    /*!< MCE fast master key, bits [159:128] */
24860 
24861 /********************  Bit definition for MCE_FMKEYR5 register  ****************/
24862 #define MCE_FMKEYR5_FMKEY_Pos          (0U)
24863 #define MCE_FMKEYR5_FMKEY_Msk          (0xFFFFFFFFUL << MCE_FMKEYR5_FMKEY_Pos)  /*!< 0xFFFFFFFF */
24864 #define MCE_FMKEYR5_FMKEY              MCE_FMKEYR5_FMKEY_Msk                    /*!< MCE fast master key, bits [191:160] */
24865 
24866 /********************  Bit definition for MCE_FMKEYR6 register  ****************/
24867 #define MCE_FMKEYR6_FMKEY_Pos          (0U)
24868 #define MCE_FMKEYR6_FMKEY_Msk          (0xFFFFFFFFUL << MCE_FMKEYR6_FMKEY_Pos)  /*!< 0xFFFFFFFF */
24869 #define MCE_FMKEYR6_FMKEY              MCE_FMKEYR6_FMKEY_Msk                    /*!< MCE fast master key, bits [223:192] */
24870 
24871 /********************  Bit definition for MCE_FMKEYR7 register  ****************/
24872 #define MCE_FMKEYR7_FMKEY_Pos          (0U)
24873 #define MCE_FMKEYR7_FMKEY_Msk          (0xFFFFFFFFUL << MCE_FMKEYR7_FMKEY_Pos)  /*!< 0xFFFFFFFF */
24874 #define MCE_FMKEYR7_FMKEY              MCE_FMKEYR7_FMKEY_Msk                    /*!< MCE fast master key, bits [255:224] */
24875 
24876 /********************  Bit definition for MCE_CCCFGR register  ****************/
24877 #define MCE_CCCFGR_CCEN_Pos             (0U)
24878 #define MCE_CCCFGR_CCEN_Msk             (0x1UL << MCE_CCCFGR_CCEN_Pos)          /*!< 0x00000001 */
24879 #define MCE_CCCFGR_CCEN                 MCE_CCCFGR_CCEN_Msk                     /*!< MCE cipher context enable */
24880 #define MCE_CCCFGR_CCLOCK_Pos           (1U)
24881 #define MCE_CCCFGR_CCLOCK_Msk           (0x1UL << MCE_CCCFGR_CCLOCK_Pos)        /*!< 0x00000002 */
24882 #define MCE_CCCFGR_CCLOCK               MCE_CCCFGR_CCLOCK_Msk                   /*!< MCE cipher context lock */
24883 #define MCE_CCCFGR_KEYLOCK_Pos          (2U)
24884 #define MCE_CCCFGR_KEYLOCK_Msk          (0x1UL << MCE_CCCFGR_KEYLOCK_Pos)       /*!< 0x00000004 */
24885 #define MCE_CCCFGR_KEYLOCK              MCE_CCCFGR_KEYLOCK_Msk                  /*!< MCE cipher context key lock */
24886 #define MCE_CCCFGR_MODE_Pos             (4U)
24887 #define MCE_CCCFGR_MODE_Msk             (0x3UL << MCE_CCCFGR_MODE_Pos)          /*!< 0x00000030 */
24888 #define MCE_CCCFGR_MODE                 MCE_CCCFGR_MODE_Msk                     /*!< MCE authorized cipher mode */
24889 #define MCE_CCCFGR_MODE_0               (0x1UL << MCE_CCCFGR_MODE_Pos)          /*!< 0x00000010 */
24890 #define MCE_CCCFGR_MODE_1               (0x2UL << MCE_CCCFGR_MODE_Pos)          /*!< 0x00000020 */
24891 #define MCE_CCCFGR_KEYCRC_Pos           (8U)
24892 #define MCE_CCCFGR_KEYCRC_Msk           (0xFFUL << MCE_CCCFGR_KEYCRC_Pos)       /*!< 0x0000FF00 */
24893 #define MCE_CCCFGR_KEYCRC               MCE_CCCFGR_KEYCRC_Msk                   /*!< MCE cipher context key CRC */
24894 #define MCE_CCCFGR_VERSION_Pos          (16U)
24895 #define MCE_CCCFGR_VERSION_Msk          (0xFFFFUL << MCE_CCCFGR_VERSION_Pos)    /*!< 0xFFFF0000 */
24896 #define MCE_CCCFGR_VERSION              MCE_CCCFGR_VERSION_Msk                  /*!< MCE cipher context version */
24897 
24898 /********************  Bit definition for MCE_CCNR0 register  *****************/
24899 #define MCE_CCNR0_SCNONCE_Pos          (0U)
24900 #define MCE_CCNR0_SCNONCE_Msk          (0xFFFFFFFFUL << MCE_CCNR0_SCNONCE_Pos)  /*!< 0xFFFFFFFF */
24901 #define MCE_CCNR0_SCNONCE              MCE_CCNR0_SCNONCE_Msk                    /*!< MCE cipher context stream cipher nonce, bits [31:0] */
24902 
24903 /********************  Bit definition for MCE_CCNR1 register  ****************/
24904 #define MCE_CCNR1_SCNONCE_Pos          (0U)
24905 #define MCE_CCNR1_SCNONCE_Msk          (0xFFFFFFFFUL << MCE_CCNR1_SCNONCE_Pos)  /*!< 0xFFFFFFFF */
24906 #define MCE_CCNR1_SCNONCE              MCE_CCNR1_SCNONCE_Msk                    /*!< MCE cipher context stream cipher nonce, bits [63:32] */
24907 
24908 /********************  Bit definition for MCE_CCKEYR0 register  ***************/
24909 #define MCE_CCKEYR0_KEY_Pos            (0U)
24910 #define MCE_CCKEYR0_KEY_Msk            (0xFFFFFFFFUL << MCE_CCKEYR0_KEY_Pos)    /*!< 0xFFFFFFFF */
24911 #define MCE_CCKEYR0_KEY                MCE_CCKEYR0_KEY_Msk                      /*!< MCE cipher context key, bits [31:0] */
24912 
24913 /********************  Bit definition for MCE_CCKEYR1 register  ***************/
24914 #define MCE_CCKEYR1_KEY_Pos            (0U)
24915 #define MCE_CCKEYR1_KEY_Msk            (0xFFFFFFFFUL << MCE_CCKEYR1_KEY_Pos)    /*!< 0xFFFFFFFF */
24916 #define MCE_CCKEYR1_KEY                MCE_CCKEYR1_KEY_Msk                      /*!< MCE fast master key, bits [63:32] */
24917 
24918 /********************  Bit definition for MCE_CCKEYR2 register  ***************/
24919 #define MCE_CCKEYR2_KEY_Pos            (0U)
24920 #define MCE_CCKEYR2_KEY_Msk            (0xFFFFFFFFUL << MCE_CCKEYR2_KEY_Pos)    /*!< 0xFFFFFFFF */
24921 #define MCE_CCKEYR2_KEY                MCE_CCKEYR2_KEY_Msk                      /*!< MCE fast master key, bits [95:64] */
24922 
24923 /********************  Bit definition for MCE_CCKEYR3 register  ***************/
24924 #define MCE_CCKEYR3_KEY_Pos            (0U)
24925 #define MCE_CCKEYR3_KEY_Msk            (0xFFFFFFFFUL << MCE_CCKEYR3_KEY_Pos)    /*!< 0xFFFFFFFF */
24926 #define MCE_CCKEYR3_KEY                MCE_CCKEYR3_KEY_Msk                      /*!< MCE fast master key, bits [127:96] */
24927 
24928 
24929 /******************************************************************************/
24930 /*                                                                            */
24931 /*                                 MDF/ADF                                    */
24932 /*                                                                            */
24933 /******************************************************************************/
24934 /*******************  Bit definition for MDF/ADF_GCR register  ****************/
24935 #define MDF_GCR_TRGO_Pos                    (0U)
24936 #define MDF_GCR_TRGO_Msk                    (0x1UL << MDF_GCR_TRGO_Pos)             /*!< 0x00000001 */
24937 #define MDF_GCR_TRGO                        MDF_GCR_TRGO_Msk                        /*!< Trigger output control */
24938 #define MDF_GCR_ILVNB_Pos                   (4U)
24939 #define MDF_GCR_ILVNB_Msk                   (0xFUL << MDF_GCR_ILVNB_Pos)            /*!< 0x000000F0 */
24940 #define MDF_GCR_ILVNB                       MDF_GCR_ILVNB_Msk                       /*!< Interleaved Number */
24941 
24942 /*******************  Bit definition for MDF/ADF_CKGCR register  ********************/
24943 #define MDF_CKGCR_CKDEN_Pos                 (0U)
24944 #define MDF_CKGCR_CKDEN_Msk                 (0x1UL << MDF_CKGCR_CKDEN_Pos)          /*!< 0x00000001 */
24945 #define MDF_CKGCR_CKDEN                     MDF_CKGCR_CKDEN_Msk                     /*!<CKGEN diveders enable */
24946 #define MDF_CKGCR_CCK0EN_Pos                (1U)
24947 #define MDF_CKGCR_CCK0EN_Msk                (0x1UL << MDF_CKGCR_CCK0EN_Pos)         /*!< 0x00000002 */
24948 #define MDF_CKGCR_CCK0EN                    MDF_CKGCR_CCK0EN_Msk                    /*!<CCK0 clock enable */
24949 #define MDF_CKGCR_CCK1EN_Pos                (2U)
24950 #define MDF_CKGCR_CCK1EN_Msk                (0x1UL << MDF_CKGCR_CCK1EN_Pos)         /*!< 0x00000004 */
24951 #define MDF_CKGCR_CCK1EN                    MDF_CKGCR_CCK1EN_Msk                    /*!<CCK1 clock enable */
24952 #define MDF_CKGCR_CKGMOD_Pos                (4U)
24953 #define MDF_CKGCR_CKGMOD_Msk                (0x1UL << MDF_CKGCR_CKGMOD_Pos)         /*!< 0x00000010 */
24954 #define MDF_CKGCR_CKGMOD                    MDF_CKGCR_CKGMOD_Msk                    /*!<Clock genartor mode */
24955 #define MDF_CKGCR_CCK0DIR_Pos               (5U)
24956 #define MDF_CKGCR_CCK0DIR_Msk               (0x1UL << MDF_CKGCR_CCK0DIR_Pos)        /*!< 0x00000020 */
24957 #define MDF_CKGCR_CCK0DIR                   MDF_CKGCR_CCK0DIR_Msk                   /*!<CCK0 clock direction */
24958 #define MDF_CKGCR_CCK1DIR_Pos               (6U)
24959 #define MDF_CKGCR_CCK1DIR_Msk               (0x1UL << MDF_CKGCR_CCK1DIR_Pos)        /*!< 0x00000040 */
24960 #define MDF_CKGCR_CCK1DIR                   MDF_CKGCR_CCK1DIR_Msk                   /*!<CCK1 clock direction */
24961 #define MDF_CKGCR_TRGSENS_Pos               (8U)
24962 #define MDF_CKGCR_TRGSENS_Msk               (0x1UL << MDF_CKGCR_TRGSENS_Pos)        /*!< 0x00000100 */
24963 #define MDF_CKGCR_TRGSENS                   MDF_CKGCR_TRGSENS_Msk                   /*!<CKGEN trigger sensitivity selection */
24964 #define MDF_CKGCR_TRGSRC_Pos                (12U)
24965 #define MDF_CKGCR_TRGSRC_Msk                (0xFUL << MDF_CKGCR_TRGSRC_Pos)         /*!< 0x0000F000 */
24966 #define MDF_CKGCR_TRGSRC                    MDF_CKGCR_TRGSRC_Msk                    /*!<Digital Filter trigger signal selection */
24967 #define MDF_CKGCR_TRGSRC_0                  (0x1UL << MDF_CKGCR_TRGSRC_Pos)         /*!< 0x00001000 */
24968 #define MDF_CKGCR_TRGSRC_1                  (0x2UL << MDF_CKGCR_TRGSRC_Pos)         /*!< 0x00002000 */
24969 #define MDF_CKGCR_TRGSRC_2                  (0x4UL << MDF_CKGCR_TRGSRC_Pos)         /*!< 0x00004000 */
24970 #define MDF_CKGCR_TRGSRC_3                  (0x8UL << MDF_CKGCR_TRGSRC_Pos)         /*!< 0x00008000 */
24971 #define MDF_CKGCR_CCKDIV_Pos                (16U)
24972 #define MDF_CKGCR_CCKDIV_Msk                (0xFUL << MDF_CKGCR_CCKDIV_Pos)         /*!< 0x000F0000 */
24973 #define MDF_CKGCR_CCKDIV                    MDF_CKGCR_CCKDIV_Msk                    /*!<Divider to control the MDF_CCK clock */
24974 #define MDF_CKGCR_PROCDIV_Pos               (24U)
24975 #define MDF_CKGCR_PROCDIV_Msk               (0x7FUL << MDF_CKGCR_PROCDIV_Pos)       /*!< 0x7F000000 */
24976 #define MDF_CKGCR_PROCDIV                   MDF_CKGCR_PROCDIV_Msk                   /*!<Divider to control the serial interface clock */
24977 #define MDF_CKGCR_CCKACTIVE_Pos             (31U)
24978 #define MDF_CKGCR_CCKACTIVE_Msk             (0x1UL << MDF_CKGCR_CCKACTIVE_Pos)      /*!< 0x80000000 */
24979 #define MDF_CKGCR_CCKACTIVE                 MDF_CKGCR_CCKACTIVE_Msk                 /*!<Clock generator active flag */
24980 
24981 /*******************  Bit definition for MDF/ADF_OR register  ********************/
24982 #define MDF_OR_OPTION_Pos                   (0U)
24983 #define MDF_OR_OPTION_Msk                   (0xFFFFFFFFUL << MDF_OR_OPTION_Pos)     /*!< 0xFFFFFFFF */
24984 #define MDF_OR_OPTION                       MDF_OR_OPTION_Msk                       /*!<Option Control Bits */
24985 
24986 /*******************  Bit definition for MDF/ADF_SITFxCR register  ********************/
24987 #define MDF_SITFCR_SITFEN_Pos               (0U)
24988 #define MDF_SITFCR_SITFEN_Msk               (0x1UL << MDF_SITFCR_SITFEN_Pos)        /*!< 0x00000001 */
24989 #define MDF_SITFCR_SITFEN                   MDF_SITFCR_SITFEN_Msk                   /*!<Serial interface enable */
24990 #define MDF_SITFCR_SCKSRC_Pos               (1U)
24991 #define MDF_SITFCR_SCKSRC_Msk               (0x3UL << MDF_SITFCR_SCKSRC_Pos)        /*!< 0x00000006 */
24992 #define MDF_SITFCR_SCKSRC                   MDF_SITFCR_SCKSRC_Msk                   /*!<Serial clock source */
24993 #define MDF_SITFCR_SCKSRC_0                 (0x1UL << MDF_SITFCR_SCKSRC_Pos)
24994 #define MDF_SITFCR_SCKSRC_1                 (0x2UL << MDF_SITFCR_SCKSRC_Pos)
24995 #define MDF_SITFCR_SITFMOD_Pos              (4U)
24996 #define MDF_SITFCR_SITFMOD_Msk              (0x3UL << MDF_SITFCR_SITFMOD_Pos)       /*!< 0x00000030 */
24997 #define MDF_SITFCR_SITFMOD                  MDF_SITFCR_SITFMOD_Msk                  /*!<Serial interface type */
24998 #define MDF_SITFCR_SITFMOD_0                (0x1UL << MDF_SITFCR_SITFMOD_Pos)       /*!< 0x00000010 */
24999 #define MDF_SITFCR_SITFMOD_1                (0x2UL << MDF_SITFCR_SITFMOD_Pos)       /*!< 0x00000020 */
25000 #define MDF_SITFCR_STH_Pos                  (8U)
25001 #define MDF_SITFCR_STH_Msk                  (0x1FUL << MDF_SITFCR_STH_Pos)          /*!< 0x00001F00 */
25002 #define MDF_SITFCR_STH                      MDF_SITFCR_STH_Msk                      /*!<Manchester Symbol threshold / SPI threshold */
25003 #define MDF_SITFCR_SITFACTIVE_Pos           (31U)
25004 #define MDF_SITFCR_SITFACTIVE_Msk           (0x1UL << MDF_SITFCR_SITFACTIVE_Pos)    /*!< 0x80000000 */
25005 #define MDF_SITFCR_SITFACTIVE               MDF_SITFCR_SITFACTIVE_Msk               /*!<Serial interface active flag */
25006 
25007 /*******************  Bit definition for MDF/ADF_BSMXxCR register  ********************/
25008 #define MDF_BSMXCR_BSSEL_Pos                (0U)
25009 #define MDF_BSMXCR_BSSEL_Msk                (0x1FUL << MDF_BSMXCR_BSSEL_Pos)        /*!< 0x0000001F */
25010 #define MDF_BSMXCR_BSSEL                    MDF_BSMXCR_BSSEL_Msk                    /*!<Bit Streal selection */
25011 #define MDF_BSMXCR_BSSEL_0                  (0x1UL  << MDF_BSMXCR_BSSEL_Pos)        /*!< 0x00000001 */
25012 #define MDF_BSMXCR_BSSEL_1                  (0x2UL  << MDF_BSMXCR_BSSEL_Pos)        /*!< 0x00000002 */
25013 #define MDF_BSMXCR_BSSEL_2                  (0x4UL  << MDF_BSMXCR_BSSEL_Pos)        /*!< 0x00000004 */
25014 #define MDF_BSMXCR_BSSEL_3                  (0x8UL  << MDF_BSMXCR_BSSEL_Pos)        /*!< 0x00000008 */
25015 #define MDF_BSMXCR_BSSEL_4                  (0x10UL  << MDF_BSMXCR_BSSEL_Pos)       /*!< 0x00000010 */
25016 #define MDF_BSMXCR_BSMXACTIVATE_Pos         (31U)
25017 #define MDF_BSMXCR_BSMXACTIVATE_Msk         (0x1UL << MDF_BSMXCR_BSMXACTIVATE_Pos)  /*!< 0x80000000 */
25018 #define MDF_BSMXCR_BSMXACTIVATE             MDF_BSMXCR_BSMXACTIVATE_Msk             /*!<Bit Streal activation flag */
25019 
25020 /*******************  Bit definition for MDF/ADF_DFLTxCR register  ********************/
25021 #define MDF_DFLTCR_DFLTEN_Pos               (0U)
25022 #define MDF_DFLTCR_DFLTEN_Msk               (0x1UL << MDF_DFLTCR_DFLTEN_Pos)        /*!< 0x00000001 */
25023 #define MDF_DFLTCR_DFLTEN                   MDF_DFLTCR_DFLTEN_Msk                   /*!<Digital filter enable */
25024 #define MDF_DFLTCR_DMAEN_Pos                (1U)
25025 #define MDF_DFLTCR_DMAEN_Msk                (0x1UL << MDF_DFLTCR_DMAEN_Pos)         /*!< 0x00000002 */
25026 #define MDF_DFLTCR_DMAEN                    MDF_DFLTCR_DMAEN_Msk                    /*!<DMA request enable */
25027 #define MDF_DFLTCR_FTH_Pos                  (2U)
25028 #define MDF_DFLTCR_FTH_Msk                  (0x1UL << MDF_DFLTCR_FTH_Pos)           /*!< 0x00000004 */
25029 #define MDF_DFLTCR_FTH                      MDF_DFLTCR_FTH_Msk                      /*!<RXFIFO Threshold selection */
25030 #define MDF_DFLTCR_ACQMOD_Pos               (4U)
25031 #define MDF_DFLTCR_ACQMOD_Msk               (0x7UL << MDF_DFLTCR_ACQMOD_Pos)        /*!< 0x00000004 */
25032 #define MDF_DFLTCR_ACQMOD                   MDF_DFLTCR_ACQMOD_Msk                   /*!<Digital filter trigger mode */
25033 #define MDF_DFLTCR_ACQMOD_0                 (0x1UL << MDF_DFLTCR_ACQMOD_Pos)        /*!< 0x00000010 */
25034 #define MDF_DFLTCR_ACQMOD_1                 (0x2UL << MDF_DFLTCR_ACQMOD_Pos)        /*!< 0x00000020 */
25035 #define MDF_DFLTCR_ACQMOD_2                 (0x4UL << MDF_DFLTCR_ACQMOD_Pos)        /*!< 0x00000040 */
25036 #define MDF_DFLTCR_TRGSENS_Pos              (8U)
25037 #define MDF_DFLTCR_TRGSENS_Msk              (0x1UL << MDF_DFLTCR_TRGSENS_Pos)       /*!< 0x00000004 */
25038 #define MDF_DFLTCR_TRGSENS                  MDF_DFLTCR_TRGSENS_Msk                  /*!<Digital filter trigger sensitivity selection */
25039 #define MDF_DFLTCR_TRGSRC_Pos               (12U)
25040 #define MDF_DFLTCR_TRGSRC_Msk               (0xFUL << MDF_DFLTCR_TRGSRC_Pos)        /*!< 0x00000004 */
25041 #define MDF_DFLTCR_TRGSRC                   MDF_DFLTCR_TRGSRC_Msk                   /*!<Digital filter trigger signal selection */
25042 #define MDF_DFLTCR_TRGSRC_0                 (0x1UL << MDF_DFLTCR_TRGSRC_Pos)        /*!< 0x00001000 */
25043 #define MDF_DFLTCR_TRGSRC_1                 (0x2UL << MDF_DFLTCR_TRGSRC_Pos)        /*!< 0x00002000 */
25044 #define MDF_DFLTCR_TRGSRC_2                 (0x4UL << MDF_DFLTCR_TRGSRC_Pos)        /*!< 0x00004000 */
25045 #define MDF_DFLTCR_TRGSRC_3                 (0x8UL << MDF_DFLTCR_TRGSRC_Pos)        /*!< 0x00008000 */
25046 #define MDF_DFLTCR_SNPSFMT_Pos              (16U)
25047 #define MDF_DFLTCR_SNPSFMT_Msk              (0x1UL << MDF_DFLTCR_SNPSFMT_Pos)       /*!< 0x00000004 */
25048 #define MDF_DFLTCR_SNPSFMT                  MDF_DFLTCR_SNPSFMT_Msk                  /*!<SnapShot Data format */
25049 #define MDF_DFLTCR_NBDIS_Pos                (20U)
25050 #define MDF_DFLTCR_NBDIS_Msk                (0xFFUL << MDF_DFLTCR_NBDIS_Pos)        /*!< 0x00000004 */
25051 #define MDF_DFLTCR_NBDIS                    MDF_DFLTCR_NBDIS_Msk                    /*!<Number of samples to be discard */
25052 #define MDF_DFLTCR_DFLTRUN_Pos              (30U)
25053 #define MDF_DFLTCR_DFLTRUN_Msk              (0x1UL << MDF_DFLTCR_DFLTRUN_Pos)       /*!< 0x00000004 */
25054 #define MDF_DFLTCR_DFLTRUN                  MDF_DFLTCR_DFLTRUN_Msk                  /*!<Digital filter run status flag */
25055 #define MDF_DFLTCR_DFLTACTIVE_Pos           (31U)
25056 #define MDF_DFLTCR_DFLTACTIVE_Msk           (0x1UL << MDF_DFLTCR_DFLTACTIVE_Pos)    /*!< 0x00000004 */
25057 #define MDF_DFLTCR_DFLTACTIVE               MDF_DFLTCR_DFLTACTIVE_Msk               /*!<Digital filter active flag */
25058 
25059 /*******************  Bit definition for MDF/ADF_DFLTxCICR register  ********************/
25060 #define MDF_DFLTCICR_DATSRC_Pos             (0U)
25061 #define MDF_DFLTCICR_DATSRC_Msk             (0x3UL << MDF_DFLTCICR_DATSRC_Pos)      /*!< 0x00000003 */
25062 #define MDF_DFLTCICR_DATSRC                 MDF_DFLTCICR_DATSRC_Msk                 /*!<Source Data for the digital filter */
25063 #define MDF_DFLTCICR_DATSRC_0               (0x1UL << MDF_DFLTCICR_DATSRC_Pos)      /*!< 0x00000001 */
25064 #define MDF_DFLTCICR_DATSRC_1               (0x2UL << MDF_DFLTCICR_DATSRC_Pos)      /*!< 0x00000002 */
25065 #define MDF_DFLTCICR_CICMOD_Pos             (4U)
25066 #define MDF_DFLTCICR_CICMOD_Msk             (0x7UL << MDF_DFLTCICR_CICMOD_Pos)      /*!< 0x00000070 */
25067 #define MDF_DFLTCICR_CICMOD                 MDF_DFLTCICR_CICMOD_Msk                 /*!<Select the CIC Mode*/
25068 #define MDF_DFLTCICR_CICMOD_0               (0x1UL << MDF_DFLTCICR_CICMOD_Pos)      /*!< 0x00000010 */
25069 #define MDF_DFLTCICR_CICMOD_1               (0x2UL << MDF_DFLTCICR_CICMOD_Pos)      /*!< 0x00000020 */
25070 #define MDF_DFLTCICR_CICMOD_2               (0x4UL << MDF_DFLTCICR_CICMOD_Pos)      /*!< 0x00000030 */
25071 #define MDF_DFLTCICR_MCICD_Pos              (8U)
25072 #define MDF_DFLTCICR_MCICD_Msk              (0x1FFUL << MDF_DFLTCICR_MCICD_Pos)     /*!< 0x0001FF00 */
25073 #define MDF_DFLTCICR_MCICD                  MDF_DFLTCICR_MCICD_Msk                  /*!<CIC decimation ratio selection*/
25074 #define MDF_DFLTCICR_SCALE_Pos              (20U)
25075 #define MDF_DFLTCICR_SCALE_Msk              (0x3FUL << MDF_DFLTCICR_SCALE_Pos)      /*!< 0x03F00000 */
25076 #define MDF_DFLTCICR_SCALE                  MDF_DFLTCICR_SCALE_Msk                  /*!<Scaling factor selection*/
25077 
25078 /*******************  Bit definition for MDF/ADF_DFLTxRSFR register  ********************/
25079 #define MDF_DFLTRSFR_RSFLTBYP_Pos           (0U)
25080 #define MDF_DFLTRSFR_RSFLTBYP_Msk           (0x1UL << MDF_DFLTRSFR_RSFLTBYP_Pos)    /*!< 0x00000001 */
25081 #define MDF_DFLTRSFR_RSFLTBYP               MDF_DFLTRSFR_RSFLTBYP_Msk               /*!<Reshape filter bypass*/
25082 #define MDF_DFLTRSFR_RSFLTD_Pos             (4U)
25083 #define MDF_DFLTRSFR_RSFLTD_Msk             (0x1UL << MDF_DFLTRSFR_RSFLTD_Pos)      /*!< 0x00000010 */
25084 #define MDF_DFLTRSFR_RSFLTD                 MDF_DFLTRSFR_RSFLTD_Msk                 /*!<Reshape filter decimation ratio*/
25085 #define MDF_DFLTRSFR_HPFBYP_Pos             (7U)
25086 #define MDF_DFLTRSFR_HPFBYP_Msk             (0x1UL << MDF_DFLTRSFR_HPFBYP_Pos)      /*!< 0x00000080 */
25087 #define MDF_DFLTRSFR_HPFBYP                 MDF_DFLTRSFR_HPFBYP_Msk                 /*!<High-pass filter bypass*/
25088 #define MDF_DFLTRSFR_HPFC_Pos               (8U)
25089 #define MDF_DFLTRSFR_HPFC_Msk               (0x3UL << MDF_DFLTRSFR_HPFC_Pos)        /*!< 0x00000080 */
25090 #define MDF_DFLTRSFR_HPFC                   MDF_DFLTRSFR_HPFC_Msk                   /*!<High-pass filter cut-off frequency*/
25091 #define MDF_DFLTRSFR_HPFC_0                 (0x1UL << MDF_DFLTRSFR_HPFC_Pos)
25092 #define MDF_DFLTRSFR_HPFC_1                 (0x2UL << MDF_DFLTRSFR_HPFC_Pos)
25093 
25094 /*******************  Bit definition for MDF/ADF_DFLTxINTR register  ********************/
25095 #define MDF_DFLTINTR_INTDIV_Pos             (0U)
25096 #define MDF_DFLTINTR_INTDIV_Msk             (0x3UL << MDF_DFLTINTR_INTDIV_Pos)      /*!< 0x00000003 */
25097 #define MDF_DFLTINTR_INTDIV                 MDF_DFLTINTR_INTDIV_Msk                 /*!<Integrator output dividion*/
25098 #define MDF_DFLTINTR_INTDIV_0               (0x1UL << MDF_DFLTINTR_INTDIV_Pos)      /*!< 0x00000001 */
25099 #define MDF_DFLTINTR_INTDIV_1               (0x2UL << MDF_DFLTINTR_INTDIV_Pos)      /*!< 0x00000002 */
25100 #define MDF_DFLTINTR_INTVAL_Pos             (4U)
25101 #define MDF_DFLTINTR_INTVAL_Msk             (0x7FUL << MDF_DFLTINTR_INTVAL_Pos)     /*!< 0x000007F0 */
25102 #define MDF_DFLTINTR_INTVAL                 MDF_DFLTINTR_INTVAL_Msk                 /*!<Integrator value selection*/
25103 
25104 /*******************  Bit definition for MDF/ADF_OLDxCR register  ********************/
25105 #define MDF_OLDCR_OLDEN_Pos                 (0U)
25106 #define MDF_OLDCR_OLDEN_Msk                 (0x1UL << MDF_OLDCR_OLDEN_Pos)          /*!< 0x00000001 */
25107 #define MDF_OLDCR_OLDEN                     MDF_OLDCR_OLDEN_Msk                     /*!<OLD enable*/
25108 #define MDF_OLDCR_THINB_Pos                 (1U)
25109 #define MDF_OLDCR_THINB_Msk                 (0x1UL << MDF_OLDCR_THINB_Pos)          /*!< 0x00000002 */
25110 #define MDF_OLDCR_THINB                     MDF_OLDCR_THINB_Msk                     /*!<OLD threshold in band*/
25111 #define MDF_OLDCR_BKOLD_Pos                 (4U)
25112 #define MDF_OLDCR_BKOLD_Msk                 (0xFUL << MDF_OLDCR_BKOLD_Pos)          /*!< 0x000000F0 */
25113 #define MDF_OLDCR_BKOLD                     MDF_OLDCR_BKOLD_Msk                     /*!<Bteak signal assignment for OLD*/
25114 #define MDF_OLDCR_BKOLD_0                   (0x1UL << MDF_OLDCR_BKOLD_Pos)          /*!< 0x00000010 */
25115 #define MDF_OLDCR_BKOLD_1                   (0x2UL << MDF_OLDCR_BKOLD_Pos)          /*!< 0x00000020 */
25116 #define MDF_OLDCR_BKOLD_2                   (0x4UL << MDF_OLDCR_BKOLD_Pos)          /*!< 0x00000040 */
25117 #define MDF_OLDCR_BKOLD_3                   (0x8UL << MDF_OLDCR_BKOLD_Pos)          /*!< 0x00000080 */
25118 #define MDF_OLDCR_ACICN_Pos                 (12U)
25119 #define MDF_OLDCR_ACICN_Msk                 (0x3UL << MDF_OLDCR_ACICN_Pos)          /*!< 0x00003000 */
25120 #define MDF_OLDCR_ACICN                     MDF_OLDCR_ACICN_Msk                     /*!<OLD CIC order selection*/
25121 #define MDF_OLDCR_ACICN_0                   (0x1UL << MDF_OLDCR_ACICN_Pos)          /*!< 0x00001000 */
25122 #define MDF_OLDCR_ACICN_1                   (0x2UL << MDF_OLDCR_ACICN_Pos)          /*!< 0x00002000 */
25123 #define MDF_OLDCR_ACICD_Pos                 (17U)
25124 #define MDF_OLDCR_ACICD_Msk                 (0x1FUL << MDF_OLDCR_ACICD_Pos)         /*!< 0x003E0000 */
25125 #define MDF_OLDCR_ACICD                     MDF_OLDCR_ACICD_Msk                     /*!<OLD CIC decimation ratio selection*/
25126 #define MDF_OLDCR_OLDACTIVE_Pos             (31U)
25127 #define MDF_OLDCR_OLDACTIVE_Msk             (0x1UL << MDF_OLDCR_OLDACTIVE_Pos)      /*!< 0x80000000 */
25128 #define MDF_OLDCR_OLDACTIVE                 MDF_OLDCR_OLDACTIVE_Msk                 /*!<OLD active flag*/
25129 
25130 /*******************  Bit definition for MDF/ADF_OLDxTHLR register  ********************/
25131 #define MDF_OLDTHLR_OLDTHL_Pos              (0U)
25132 #define MDF_OLDTHLR_OLDTHL_Msk              (0x3FFFFFFUL << MDF_OLDTHLR_OLDTHL_Pos) /*!< 0x03FFFFFF */
25133 #define MDF_OLDTHLR_OLDTHL                  MDF_OLDTHLR_OLDTHL_Msk                  /*!<OLD Low threshold value*/
25134 
25135 /*******************  Bit definition for MDF/ADF_OLDxTHHR register  ********************/
25136 #define MDF_OLDTHHR_OLDTHH_Pos              (0U)
25137 #define MDF_OLDTHHR_OLDTHH_Msk              (0x3FFFFFFUL << MDF_OLDTHHR_OLDTHH_Pos) /*!< 0x03FFFFFF */
25138 #define MDF_OLDTHHR_OLDTHH                  MDF_OLDTHHR_OLDTHH_Msk                  /*!<OLD High threshold value*/
25139 
25140 /*******************  Bit definition for MDF/ADF_DLYxCR register  ********************/
25141 #define MDF_DLYCR_SKPDLY_Pos                (0U)
25142 #define MDF_DLYCR_SKPDLY_Msk                (0x7FUL << MDF_DLYCR_SKPDLY_Pos)        /*!< 0x0000007F */
25143 #define MDF_DLYCR_SKPDLY                    MDF_DLYCR_SKPDLY_Msk                    /*!<Delay to apply to a bitstream*/
25144 #define MDF_DLYCR_SKPBF_Pos                 (31U)
25145 #define MDF_DLYCR_SKPBF_Msk                 (0x1UL << MDF_DLYCR_SKPBF_Pos)          /*!< 0x80000000 */
25146 #define MDF_DLYCR_SKPBF                     MDF_DLYCR_SKPBF_Msk                     /*!<DSkip Busy Flag*/
25147 
25148 /*******************  Bit definition for MDF/ADF_SCDxCR register  ********************/
25149 #define MDF_SCDCR_SCDEN_Pos                 (0U)
25150 #define MDF_SCDCR_SCDEN_Msk                 (0x1UL << MDF_SCDCR_SCDEN_Pos)          /*!< 0x00000001 */
25151 #define MDF_SCDCR_SCDEN                     MDF_SCDCR_SCDEN_Msk                     /*!<Short circuit detector enable*/
25152 #define MDF_SCDCR_BKSCD_Pos                 (4U)
25153 #define MDF_SCDCR_BKSCD_Msk                 (0xFUL << MDF_SCDCR_BKSCD_Pos)          /*!< 0x000000F0 */
25154 #define MDF_SCDCR_BKSCD                     MDF_SCDCR_BKSCD_Msk                     /*!<Break signal assignment to short circuit detector */
25155 #define MDF_SCDCR_BKSCD_0                   (0x1UL << MDF_SCDCR_BKSCD_Pos)          /*!< 0x00000010 */
25156 #define MDF_SCDCR_BKSCD_1                   (0x2UL << MDF_SCDCR_BKSCD_Pos)          /*!< 0x00000020 */
25157 #define MDF_SCDCR_BKSCD_2                   (0x4UL << MDF_SCDCR_BKSCD_Pos)          /*!< 0x00000040 */
25158 #define MDF_SCDCR_BKSCD_3                   (0x8UL << MDF_SCDCR_BKSCD_Pos)          /*!< 0x00000080 */
25159 #define MDF_SCDCR_SCDT_Pos                  (12U)
25160 #define MDF_SCDCR_SCDT_Msk                  (0xFFUL << MDF_SCDCR_SCDT_Pos)          /*!< 0x00000FF00 */
25161 #define MDF_SCDCR_SCDT                      MDF_SCDCR_SCDT_Msk                      /*!<Short circuit detector threshold*/
25162 #define MDF_SCDCR_SCDACTIVE_Pos             (31U)
25163 #define MDF_SCDCR_SCDACTIVE_Msk             (0x1UL << MDF_SCDCR_SCDACTIVE_Pos)      /*!< 0x80000000 */
25164 #define MDF_SCDCR_SCDACTIVE                 MDF_SCDCR_SCDACTIVE_Msk                 /*!<Short circuit detector active flag*/
25165 
25166 /*******************  Bit definition for MDF/ADF_DFLTIER register  ********************/
25167 #define MDF_DFLTIER_FTHIE_Pos               (0U)
25168 #define MDF_DFLTIER_FTHIE_Msk               (0x1UL << MDF_DFLTIER_FTHIE_Pos)        /*!< 0x00000001 */
25169 #define MDF_DFLTIER_FTHIE                   MDF_DFLTIER_FTHIE_Msk                   /*!<RXFIFO threshold interrupt enable*/
25170 #define MDF_DFLTIER_DOVRIE_Pos              (1U)
25171 #define MDF_DFLTIER_DOVRIE_Msk              (0x1UL << MDF_DFLTIER_DOVRIE_Pos)       /*!< 0x00000002 */
25172 #define MDF_DFLTIER_DOVRIE                  MDF_DFLTIER_DOVRIE_Msk                  /*!<Data overflow interrupt enable*/
25173 #define MDF_DFLTIER_SSDRIE_Pos              (2U)
25174 #define MDF_DFLTIER_SSDRIE_Msk              (0x1UL << MDF_DFLTIER_SSDRIE_Pos)       /*!< 0x00000004 */
25175 #define MDF_DFLTIER_SSDRIE                  MDF_DFLTIER_SSDRIE_Msk                  /*!<Snapshot data ready interrupt enable*/
25176 #define MDF_DFLTIER_OLDIE_Pos               (4U)
25177 #define MDF_DFLTIER_OLDIE_Msk               (0x1UL << MDF_DFLTIER_OLDIE_Pos)        /*!< 0x00000010 */
25178 #define MDF_DFLTIER_OLDIE                   MDF_DFLTIER_OLDIE_Msk                   /*!<OLD interrupt enable*/
25179 #define MDF_DFLTIER_SSOVRIE_Pos             (7U)
25180 #define MDF_DFLTIER_SSOVRIE_Msk             (0x1UL << MDF_DFLTIER_SSOVRIE_Pos)      /*!< 0x00000080 */
25181 #define MDF_DFLTIER_SSOVRIE                 MDF_DFLTIER_SSOVRIE_Msk                 /*!<Snapshot overrun interrupt enable*/
25182 #define MDF_DFLTIER_SCDIE_Pos               (8U)
25183 #define MDF_DFLTIER_SCDIE_Msk               (0x1UL << MDF_DFLTIER_SCDIE_Pos)        /*!< 0x00000100 */
25184 #define MDF_DFLTIER_SCDIE                   MDF_DFLTIER_SCDIE_Msk                   /*!<Short circuit dtector interrupt enable*/
25185 #define MDF_DFLTIER_SATIE_Pos               (9U)
25186 #define MDF_DFLTIER_SATIE_Msk               (0x1UL << MDF_DFLTIER_SATIE_Pos)        /*!< 0x00000200 */
25187 #define MDF_DFLTIER_SATIE                   MDF_DFLTIER_SATIE_Msk                   /*!<Saturation detection interrupt enable*/
25188 #define MDF_DFLTIER_CKABIE_Pos              (10U)
25189 #define MDF_DFLTIER_CKABIE_Msk              (0x1UL << MDF_DFLTIER_CKABIE_Pos)       /*!< 0x00000400 */
25190 #define MDF_DFLTIER_CKABIE                  MDF_DFLTIER_CKABIE_Msk                  /*!<Clock absence detection interrupt enable*/
25191 #define MDF_DFLTIER_RFOVRIE_Pos             (11U)
25192 #define MDF_DFLTIER_RFOVRIE_Msk             (0x1UL << MDF_DFLTIER_RFOVRIE_Pos)      /*!< 0x00000800 */
25193 #define MDF_DFLTIER_RFOVRIE                 MDF_DFLTIER_RFOVRIE_Msk                 /*!<reshape filter overrun interrupt enable*/
25194 #define MDF_DFLTIER_SDDETIE_Pos             (12U)
25195 #define MDF_DFLTIER_SDDETIE_Msk             (0x1UL << MDF_DFLTIER_SDDETIE_Pos)      /*!< 0x00001000 */
25196 #define MDF_DFLTIER_SDDETIE                 MDF_DFLTIER_SDDETIE_Msk                 /*!<SAD interrupt enable*/
25197 #define MDF_DFLTIER_SDLVLIE_Pos             (13U)
25198 #define MDF_DFLTIER_SDLVLIE_Msk             (0x1UL << MDF_DFLTIER_SDLVLIE_Pos)      /*!< 0x00002000 */
25199 #define MDF_DFLTIER_SDLVLIE                 MDF_DFLTIER_SDLVLIE_Msk                 /*!<Sound level value ready interrupt enable*/
25200 
25201 /*******************  Bit definition for MDF/ADF_DFLTISR register  ********************/
25202 #define MDF_DFLTISR_FTHF_Pos                (0U)
25203 #define MDF_DFLTISR_FTHF_Msk                (0x1UL << MDF_DFLTISR_FTHF_Pos)         /*!< 0x00000001 */
25204 #define MDF_DFLTISR_FTHF                    MDF_DFLTISR_FTHF_Msk                    /*!<RXFIFO threshold interrupt flag*/
25205 #define MDF_DFLTISR_DOVRF_Pos               (1U)
25206 #define MDF_DFLTISR_DOVRF_Msk               (0x1UL << MDF_DFLTISR_DOVRF_Pos)        /*!< 0x00000002 */
25207 #define MDF_DFLTISR_DOVRF                   MDF_DFLTISR_DOVRF_Msk                   /*!<Data overflow interrupt flag*/
25208 #define MDF_DFLTISR_SSDRF_Pos               (2U)
25209 #define MDF_DFLTISR_SSDRF_Msk               (0x1UL << MDF_DFLTISR_SSDRF_Pos)        /*!< 0x00000004 */
25210 #define MDF_DFLTISR_SSDRF                   MDF_DFLTISR_SSDRF_Msk                   /*!<Snapshot data ready interrupt flag*/
25211 #define MDF_DFLTISR_RXNEF_Pos               (3U)
25212 #define MDF_DFLTISR_RXNEF_Msk               (0x1UL << MDF_DFLTISR_RXNEF_Pos)        /*!< 0x00000008 */
25213 #define MDF_DFLTISR_RXNEF                   MDF_DFLTISR_RXNEF_Msk                   /*!<Snapshot data ready interrupt flag*/
25214 #define MDF_DFLTISR_OLDF_Pos                (4U)
25215 #define MDF_DFLTISR_OLDF_Msk                (0x1UL << MDF_DFLTISR_OLDF_Pos)         /*!< 0x00000010 */
25216 #define MDF_DFLTISR_OLDF                    MDF_DFLTISR_OLDF_Msk                    /*!<OLD interrupt flag*/
25217 #define MDF_DFLTISR_THLF_Pos                (5U)
25218 #define MDF_DFLTISR_THLF_Msk                (0x1UL << MDF_DFLTISR_THLF_Pos)         /*!< 0x00000010 */
25219 #define MDF_DFLTISR_THLF                    MDF_DFLTISR_THLF_Msk                    /*!<OLD interrupt flag*/
25220 #define MDF_DFLTISR_THHF_Pos                (6U)
25221 #define MDF_DFLTISR_THHF_Msk                (0x1UL << MDF_DFLTISR_THHF_Pos)         /*!< 0x00000010 */
25222 #define MDF_DFLTISR_THHF                    MDF_DFLTISR_THHF_Msk                    /*!<OLD interrupt flag*/
25223 #define MDF_DFLTISR_SSOVRF_Pos              (7U)
25224 #define MDF_DFLTISR_SSOVRF_Msk              (0x1UL << MDF_DFLTISR_SSOVRF_Pos)      /*!< 0x00000080 */
25225 #define MDF_DFLTISR_SSOVRF                  MDF_DFLTISR_SSOVRF_Msk                  /*!<Snapshot overrun interrupt flag*/
25226 #define MDF_DFLTISR_SCDF_Pos                (8U)
25227 #define MDF_DFLTISR_SCDF_Msk                (0x1UL << MDF_DFLTISR_SCDF_Pos)         /*!< 0x00000100 */
25228 #define MDF_DFLTISR_SCDF                    MDF_DFLTISR_SCDF_Msk                    /*!<Short circuit dtector interrupt flag*/
25229 #define MDF_DFLTISR_SATF_Pos                (9U)
25230 #define MDF_DFLTISR_SATF_Msk                (0x1UL << MDF_DFLTISR_SATF_Pos)         /*!< 0x00000200 */
25231 #define MDF_DFLTISR_SATF                    MDF_DFLTISR_SATF_Msk                    /*!<Saturation detection interrupt flag*/
25232 #define MDF_DFLTISR_CKABF_Pos               (10U)
25233 #define MDF_DFLTISR_CKABF_Msk               (0x1UL << MDF_DFLTISR_CKABF_Pos)        /*!< 0x00000400 */
25234 #define MDF_DFLTISR_CKABF                   MDF_DFLTISR_CKABF_Msk                   /*!<Clock absence detection interrupt flag*/
25235 #define MDF_DFLTISR_RFOVRF_Pos              (11U)
25236 #define MDF_DFLTISR_RFOVRF_Msk              (0x1UL << MDF_DFLTISR_RFOVRF_Pos)       /*!< 0x00000800 */
25237 #define MDF_DFLTISR_RFOVRF                  MDF_DFLTISR_RFOVRF_Msk                  /*!<reshape filter overrun interrupt flag*/
25238 #define MDF_DFLTISR_SDDETF_Pos              (12U)
25239 #define MDF_DFLTISR_SDDETF_Msk              (0x1UL << MDF_DFLTISR_SDDETF_Pos)        /*!< 0x00001000 */
25240 #define MDF_DFLTISR_SDDETF                  MDF_DFLTISR_SDDETF_Msk                  /*!<SAD interrupt flag*/
25241 #define MDF_DFLTISR_SDLVLF_Pos              (13U)
25242 #define MDF_DFLTISR_SDLVLF_Msk              (0x1UL << MDF_DFLTISR_SDLVLF_Pos)       /*!< 0x00002000 */
25243 #define MDF_DFLTISR_SDLVLF                  MDF_DFLTISR_SDLVLF_Msk                  /*!<Sound level value ready interrupt flag*/
25244 
25245 /*******************  Bit definition for MDF/ADF_OECCR register  ********************/
25246 #define MDF_OECCR_OFFSET_Pos                (0U)
25247 #define MDF_OECCR_OFFSET_Msk                (0x3FFFFFFUL << MDF_OECCR_OFFSET_Pos)   /*!< 0x03FFFFFF */
25248 #define MDF_OECCR_OFFSET                    MDF_OECCR_OFFSET_Msk                    /*!<Short circuit detector enable*/
25249 
25250 /*******************  Bit definition for MDF/ADF_SADCR register  ********************/
25251 #define MDF_SADCR_SADEN_Pos                 (0U)
25252 #define MDF_SADCR_SADEN_Msk                 (0x1UL << MDF_SADCR_SADEN_Pos)          /*!< 0x00000001 */
25253 #define MDF_SADCR_SADEN                     MDF_SADCR_SADEN_Msk                     /*!<SAD enable*/
25254 #define MDF_SADCR_DATCAP_Pos                (1U)
25255 #define MDF_SADCR_DATCAP_Msk                (0x3UL << MDF_SADCR_DATCAP_Pos)         /*!< 0x00000003 */
25256 #define MDF_SADCR_DATCAP                    MDF_SADCR_DATCAP_Msk                    /*!<SAD data capture mode*/
25257 #define MDF_SADCR_DATCAP_0                  (0x1UL << MDF_SADCR_DATCAP_Pos)         /*!< 0x00000002 */
25258 #define MDF_SADCR_DATCAP_1                  (0x2UL << MDF_SADCR_DATCAP_Pos)         /*!< 0x00000004 */
25259 #define MDF_SADCR_DETCFG_Pos                (3U)
25260 #define MDF_SADCR_DETCFG_Msk                (0x1UL << MDF_SADCR_DETCFG_Pos)         /*!< 0x00000008 */
25261 #define MDF_SADCR_DETCFG                    MDF_SADCR_DETCFG_Msk                    /*!<SAD trigger event configuration*/
25262 #define MDF_SADCR_SADST_Pos                 (4U)
25263 #define MDF_SADCR_SADST_Msk                 (0x3UL << MDF_SADCR_SADST_Pos)          /*!< 0x00000030 */
25264 #define MDF_SADCR_SADST                     MDF_SADCR_SADST_Msk                     /*!<SAD state*/
25265 #define MDF_SADCR_HYSTEN_Pos                (7U)
25266 #define MDF_SADCR_HYSTEN_Msk                (0x1UL << MDF_SADCR_HYSTEN_Pos)         /*!< 0x00000080 */
25267 #define MDF_SADCR_HYSTEN                    MDF_SADCR_HYSTEN_Msk                    /*!<Hysteresis enable*/
25268 #define MDF_SADCR_FRSIZE_Pos                (8U)
25269 #define MDF_SADCR_FRSIZE_Msk                (0x7UL << MDF_SADCR_FRSIZE_Pos)         /*!< 0x00000700 */
25270 #define MDF_SADCR_FRSIZE                    MDF_SADCR_FRSIZE_Msk                    /*!<Frame size*/
25271 #define MDF_SADCR_FRSIZE_0                  (0x1UL << MDF_SADCR_FRSIZE_Pos)         /*!< 0x00000100 */
25272 #define MDF_SADCR_FRSIZE_1                  (0x2UL << MDF_SADCR_FRSIZE_Pos)         /*!< 0x00000200 */
25273 #define MDF_SADCR_FRSIZE_2                  (0x4UL << MDF_SADCR_FRSIZE_Pos)         /*!< 0x00000300 */
25274 #define MDF_SADCR_SADMOD_Pos                (12U)
25275 #define MDF_SADCR_SADMOD_Msk                (0x3UL << MDF_SADCR_SADMOD_Pos)         /*!< 0x00003000 */
25276 #define MDF_SADCR_SADMOD                    MDF_SADCR_SADMOD_Msk                    /*!<SAD working mode*/
25277 #define MDF_SADCR_SADMOD_0                  (0x1UL << MDF_SADCR_SADMOD_Pos)         /*!< 0x00001000 */
25278 #define MDF_SADCR_SADMOD_1                  (0x2UL << MDF_SADCR_SADMOD_Pos)         /*!< 0x00002000 */
25279 #define MDF_SADCR_SADACTIVE_Pos             (31U)
25280 #define MDF_SADCR_SADACTIVE_Msk             (0x1UL << MDF_SADCR_SADACTIVE_Pos)      /*!< 0x80000000 */
25281 #define MDF_SADCR_SADACTIVE                 MDF_SADCR_SADACTIVE_Msk                 /*!<SAD active flag*/
25282 
25283 /*******************  Bit definition for MDF/ADF_SADCFGR register  ********************/
25284 #define MDF_SADCFGR_SNTHR_Pos               (0U)
25285 #define MDF_SADCFGR_SNTHR_Msk               (0xFUL << MDF_SADCFGR_SNTHR_Pos)        /*!< 0x0000000F */
25286 #define MDF_SADCFGR_SNTHR                   MDF_SADCFGR_SNTHR_Msk                   /*!<Signal to noise threshold*/
25287 #define MDF_SADCFGR_SNTHR_0                 (0x1UL << MDF_SADCFGR_SNTHR_Pos)        /*!< 0x00000001 */
25288 #define MDF_SADCFGR_SNTHR_1                 (0x2UL << MDF_SADCFGR_SNTHR_Pos)        /*!< 0x00000002 */
25289 #define MDF_SADCFGR_SNTHR_2                 (0x4UL << MDF_SADCFGR_SNTHR_Pos)        /*!< 0x00000004 */
25290 #define MDF_SADCFGR_SNTHR_3                 (0x8UL << MDF_SADCFGR_SNTHR_Pos)        /*!< 0x00000008 */
25291 #define MDF_SADCFGR_ANSLP_Pos               (4U)
25292 #define MDF_SADCFGR_ANSLP_Msk               (0x7UL << MDF_SADCFGR_ANSLP_Pos)        /*!< 0x00000070 */
25293 #define MDF_SADCFGR_ANSLP                   MDF_SADCFGR_ANSLP_Msk                   /*!<Ambiant noise slope control*/
25294 #define MDF_SADCFGR_LFRNB_Pos               (8U)
25295 #define MDF_SADCFGR_LFRNB_Msk               (0x7UL << MDF_SADCFGR_LFRNB_Pos)        /*!< 0x00000700 */
25296 #define MDF_SADCFGR_LFRNB                   MDF_SADCFGR_LFRNB_Msk                   /*!<Number of learning frames*/
25297 #define MDF_SADCFGR_LFRNB_0                 (0x1UL << MDF_SADCFGR_LFRNB_Pos)        /*!< 0x00000100 */
25298 #define MDF_SADCFGR_LFRNB_1                 (0x2UL << MDF_SADCFGR_LFRNB_Pos)        /*!< 0x00000200 */
25299 #define MDF_SADCFGR_LFRNB_2                 (0x4UL << MDF_SADCFGR_LFRNB_Pos)        /*!< 0x00000400 */
25300 #define MDF_SADCFGR_HGOVR_Pos               (12U)
25301 #define MDF_SADCFGR_HGOVR_Msk               (0x7UL << MDF_SADCFGR_HGOVR_Pos)        /*!< 0x00007000 */
25302 #define MDF_SADCFGR_HGOVR                   MDF_SADCFGR_HGOVR_Msk                   /*!<Hangover time window*/
25303 #define MDF_SADCFGR_HGOVR_0                 (0x1UL << MDF_SADCFGR_HGOVR_Pos)        /*!< 0x00001000 */
25304 #define MDF_SADCFGR_HGOVR_1                 (0x2UL << MDF_SADCFGR_HGOVR_Pos)        /*!< 0x00002000 */
25305 #define MDF_SADCFGR_HGOVR_2                 (0x4UL << MDF_SADCFGR_HGOVR_Pos)        /*!< 0x00004000 */
25306 #define MDF_SADCFGR_ANMIN_Pos               (16U)
25307 #define MDF_SADCFGR_ANMIN_Msk               (0x1FFFUL << MDF_SADCFGR_ANMIN_Pos)     /*!< 0x1FFF0000 */
25308 #define MDF_SADCFGR_ANMIN                   MDF_SADCFGR_ANMIN_Msk                   /*!<Hangover time window*/
25309 
25310 /*******************  Bit definition for MDF/ADF_SADSDLVR register  ********************/
25311 #define MDF_SADSDLVR_SDLVL_Pos              (0U)
25312 #define MDF_SADSDLVR_SDLVL_Msk              (0x7FFFUL << MDF_SADSDLVR_SDLVL_Pos)    /*!< 0x00007FFF */
25313 #define MDF_SADSDLVR_SDLVL                  MDF_SADSDLVR_SDLVL_Msk                  /*!<Short term sound level*/
25314 
25315 /*******************  Bit definition for MDF/ADF_SADANLVR register  ********************/
25316 #define MDF_SADANLVR_ANLVL_Pos              (0U)
25317 #define MDF_SADANLVR_ANLVL_Msk              (0x7FFFUL << MDF_SADANLVR_ANLVL_Pos)    /*!< 0x00007FFF */
25318 #define MDF_SADANLVR_ANLVL                  MDF_SADANLVR_ANLVL_Msk                  /*!<Ambiant noise level estimation*/
25319 
25320 /*******************  Bit definition for MDF/ADF_SNPSDR register  ********************/
25321 #define MDF_SNPSDR_MCICDC_Pos               (0U)
25322 #define MDF_SNPSDR_MCICDC_Msk               (0x1FFUL << MDF_SNPSDR_MCICDC_Pos)      /*!< 0x000001FF */
25323 #define MDF_SNPSDR_MCICDC                   MDF_SNPSDR_MCICDC_Msk                   /*!<MCIC decimation counter*/
25324 #define MDF_SNPSDR_EXTSDR_Pos               (9U)
25325 #define MDF_SNPSDR_EXTSDR_Msk               (0x7FUL << MDF_SNPSDR_EXTSDR_Pos)       /*!< 0x0000FE00 */
25326 #define MDF_SNPSDR_EXTSDR                   MDF_SNPSDR_EXTSDR_Msk                   /*!<Extended data size*/
25327 #define MDF_SNPSDR_SDR_Pos                  (16U)
25328 #define MDF_SNPSDR_SDR_Msk                  (0xFFFFUL << MDF_SNPSDR_SDR_Pos)        /*!< 0xFFFF0000 */
25329 #define MDF_SNPSDR_SDR                      MDF_SNPSDR_SDR_Msk                      /*!<Extended data size*/
25330 
25331 /*******************  Bit definition for MDF/ADF_DFLTDR register  ********************/
25332 #define MDF_DFLTDR_DR_Pos                   (8U)
25333 #define MDF_DFLTDR_DR_Msk                   (0xFFFFFFUL << MDF_DFLTDR_DR_Pos)       /*!< 0xFFFFFF00 */
25334 #define MDF_DFLTDR_DR                       MDF_DFLTDR_DR_Msk                       /*!<MCIC decimation counter*/
25335 
25336 
25337 /******************************************************************************/
25338 /*                                                                            */
25339 /*                                 MDIOS                                      */
25340 /*                                                                            */
25341 /******************************************************************************/
25342 /********************  Bit definition for MDIOS_CR register  *******************/
25343 #define MDIOS_CR_EN_Pos                (0U)
25344 #define MDIOS_CR_EN_Msk                (0x1UL << MDIOS_CR_EN_Pos)              /*!< 0x00000001 */
25345 #define MDIOS_CR_EN                    MDIOS_CR_EN_Msk                         /*!<  MDIOS slave peripheral enable */
25346 #define MDIOS_CR_WRIE_Pos              (1U)
25347 #define MDIOS_CR_WRIE_Msk              (0x1UL << MDIOS_CR_WRIE_Pos)            /*!< 0x00000002 */
25348 #define MDIOS_CR_WRIE                  MDIOS_CR_WRIE_Msk                       /*!<  MDIOS slave register write interrupt enable. */
25349 #define MDIOS_CR_RDIE_Pos              (2U)
25350 #define MDIOS_CR_RDIE_Msk              (0x1UL << MDIOS_CR_RDIE_Pos)            /*!< 0x00000004 */
25351 #define MDIOS_CR_RDIE                  MDIOS_CR_RDIE_Msk                       /*!<  MDIOS slave register read interrupt enable. */
25352 #define MDIOS_CR_EIE_Pos               (3U)
25353 #define MDIOS_CR_EIE_Msk               (0x1UL << MDIOS_CR_EIE_Pos)             /*!< 0x00000008 */
25354 #define MDIOS_CR_EIE                   MDIOS_CR_EIE_Msk                        /*!<  MDIOS slave register error interrupt enable. */
25355 #define MDIOS_CR_DPC_Pos               (7U)
25356 #define MDIOS_CR_DPC_Msk               (0x1UL << MDIOS_CR_DPC_Pos)             /*!< 0x00000080 */
25357 #define MDIOS_CR_DPC                   MDIOS_CR_DPC_Msk                        /*!<  MDIOS slave disable preamble check. */
25358 #define MDIOS_CR_PORT_ADDRESS_Pos      (8U)
25359 #define MDIOS_CR_PORT_ADDRESS_Msk      (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos)   /*!< 0x00001F00 */
25360 #define MDIOS_CR_PORT_ADDRESS          MDIOS_CR_PORT_ADDRESS_Msk               /*!<  MDIOS slave port address mask. */
25361 #define MDIOS_CR_PORT_ADDRESS_0        (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000100 */
25362 #define MDIOS_CR_PORT_ADDRESS_1        (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000200 */
25363 #define MDIOS_CR_PORT_ADDRESS_2        (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000400 */
25364 #define MDIOS_CR_PORT_ADDRESS_3        (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000800 */
25365 #define MDIOS_CR_PORT_ADDRESS_4        (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00001000 */
25366 
25367 /********************  Bit definition for MDIOS_SR register  *******************/
25368 #define MDIOS_SR_PERF_Pos              (0U)
25369 #define MDIOS_SR_PERF_Msk              (0x1UL << MDIOS_SR_PERF_Pos)            /*!< 0x00000001 */
25370 #define MDIOS_SR_PERF                  MDIOS_SR_PERF_Msk                       /*!<  MDIOS slave turnaround error flag*/
25371 #define MDIOS_SR_SERF_Pos              (1U)
25372 #define MDIOS_SR_SERF_Msk              (0x1UL << MDIOS_SR_SERF_Pos)            /*!< 0x00000002 */
25373 #define MDIOS_SR_SERF                  MDIOS_SR_SERF_Msk                       /*!<  MDIOS slave start error flag */
25374 #define MDIOS_SR_TERF_Pos              (2U)
25375 #define MDIOS_SR_TERF_Msk              (0x1UL << MDIOS_SR_TERF_Pos)            /*!< 0x00000004 */
25376 #define MDIOS_SR_TERF                  MDIOS_SR_TERF_Msk                       /*!<  MDIOS slave preamble error flag */
25377 
25378 /********************  Bit definition for MDIOS_CLRFR register  *******************/
25379 #define MDIOS_SR_CPERF_Pos             (0U)
25380 #define MDIOS_SR_CPERF_Msk             (0x1UL << MDIOS_SR_CPERF_Pos)           /*!< 0x00000001 */
25381 #define MDIOS_SR_CPERF                 MDIOS_SR_CPERF_Msk                      /*!<  MDIOS slave Clear the turnaround error flag */
25382 #define MDIOS_SR_CSERF_Pos             (1U)
25383 #define MDIOS_SR_CSERF_Msk             (0x1UL << MDIOS_SR_CSERF_Pos)           /*!< 0x00000002 */
25384 #define MDIOS_SR_CSERF                 MDIOS_SR_CSERF_Msk                      /*!<  MDIOS slave Clear the start error flag */
25385 #define MDIOS_SR_CTERF_Pos             (2U)
25386 #define MDIOS_SR_CTERF_Msk             (0x1UL << MDIOS_SR_CTERF_Pos)           /*!< 0x00000004 */
25387 #define MDIOS_SR_CTERF                 MDIOS_SR_CTERF_Msk                      /*!<  MDIOS slave Clear the preamble error flag */
25388 
25389 
25390 /******************************************************************************/
25391 /*                                                                            */
25392 /*                       Public Key Accelerator (PKA)                         */
25393 /*                                                                            */
25394 /******************************************************************************/
25395 /*******************  Bit definition for PKA_CR register  *********************/
25396 #define PKA_CR_EN_Pos                       (0U)
25397 #define PKA_CR_EN_Msk                       (0x1UL << PKA_CR_EN_Pos)                /*!< 0x00000001 */
25398 #define PKA_CR_EN                           PKA_CR_EN_Msk                           /*!< PKA enable */
25399 #define PKA_CR_START_Pos                    (1U)
25400 #define PKA_CR_START_Msk                    (0x1UL << PKA_CR_START_Pos)             /*!< 0x00000002 */
25401 #define PKA_CR_START                        PKA_CR_START_Msk                        /*!< Start operation */
25402 #define PKA_CR_MODE_Pos                     (8U)
25403 #define PKA_CR_MODE_Msk                     (0x3FUL << PKA_CR_MODE_Pos)             /*!< 0x00003F00 */
25404 #define PKA_CR_MODE                         PKA_CR_MODE_Msk                         /*!< MODE[5:0] PKA operation code */
25405 #define PKA_CR_MODE_0                       (0x01UL << PKA_CR_MODE_Pos)             /*!< 0x00000100 */
25406 #define PKA_CR_MODE_1                       (0x02UL << PKA_CR_MODE_Pos)             /*!< 0x00000200 */
25407 #define PKA_CR_MODE_2                       (0x04UL << PKA_CR_MODE_Pos)             /*!< 0x00000400 */
25408 #define PKA_CR_MODE_3                       (0x08UL << PKA_CR_MODE_Pos)             /*!< 0x00000800 */
25409 #define PKA_CR_MODE_4                       (0x10UL << PKA_CR_MODE_Pos)             /*!< 0x00001000 */
25410 #define PKA_CR_MODE_5                       (0x20UL << PKA_CR_MODE_Pos)             /*!< 0x00002000 */
25411 #define PKA_CR_PROCENDIE_Pos                (17U)
25412 #define PKA_CR_PROCENDIE_Msk                (0x1UL << PKA_CR_PROCENDIE_Pos)         /*!< 0x00020000 */
25413 #define PKA_CR_PROCENDIE                    PKA_CR_PROCENDIE_Msk                    /*!< End of operation interrupt enable */
25414 #define PKA_CR_RAMERRIE_Pos                 (19U)
25415 #define PKA_CR_RAMERRIE_Msk                 (0x1UL << PKA_CR_RAMERRIE_Pos)          /*!< 0x00080000 */
25416 #define PKA_CR_RAMERRIE                     PKA_CR_RAMERRIE_Msk                     /*!< RAM error interrupt enable */
25417 #define PKA_CR_ADDRERRIE_Pos                (20U)
25418 #define PKA_CR_ADDRERRIE_Msk                (0x1UL << PKA_CR_ADDRERRIE_Pos)         /*!< 0x00100000 */
25419 #define PKA_CR_ADDRERRIE                    PKA_CR_ADDRERRIE_Msk                    /*!< Address error interrupt enable */
25420 #define PKA_CR_OPERRIE_Pos                  (21U)
25421 #define PKA_CR_OPERRIE_Msk                  (0x1UL << PKA_CR_OPERRIE_Pos)           /*!< 0x00200000 */
25422 #define PKA_CR_OPERRIE                      PKA_CR_OPERRIE_Msk                      /*!< Operation Error interrupt enable */
25423 
25424 /*******************  Bit definition for PKA_SR register  *********************/
25425 #define PKA_SR_INITOK_Pos                   (0U)
25426 #define PKA_SR_INITOK_Msk                   (0x1UL << PKA_SR_INITOK_Pos)            /*!< 0x00000001 */
25427 #define PKA_SR_INITOK                       PKA_SR_INITOK_Msk                       /*!< PKA initialisation flag */
25428 #define PKA_SR_BUSY_Pos                     (16U)
25429 #define PKA_SR_BUSY_Msk                     (0x1UL << PKA_SR_BUSY_Pos)              /*!< 0x00010000 */
25430 #define PKA_SR_BUSY                         PKA_SR_BUSY_Msk                         /*!< PKA operation is in progress */
25431 #define PKA_SR_PROCENDF_Pos                 (17U)
25432 #define PKA_SR_PROCENDF_Msk                 (0x1UL << PKA_SR_PROCENDF_Pos)          /*!< 0x00020000 */
25433 #define PKA_SR_PROCENDF                     PKA_SR_PROCENDF_Msk                     /*!< PKA end of operation flag */
25434 #define PKA_SR_RAMERRF_Pos                  (19U)
25435 #define PKA_SR_RAMERRF_Msk                  (0x1UL << PKA_SR_RAMERRF_Pos)           /*!< 0x00080000 */
25436 #define PKA_SR_RAMERRF                      PKA_SR_RAMERRF_Msk                      /*!< PKA RAM error flag */
25437 #define PKA_SR_ADDRERRF_Pos                 (20U)
25438 #define PKA_SR_ADDRERRF_Msk                 (0x1UL << PKA_SR_ADDRERRF_Pos)          /*!< 0x00100000 */
25439 #define PKA_SR_ADDRERRF                     PKA_SR_ADDRERRF_Msk                     /*!< Address error flag */
25440 #define PKA_SR_OPERRF_Pos                   (21U)
25441 #define PKA_SR_OPERRF_Msk                   (0x1UL << PKA_SR_OPERRF_Pos)            /*!< 0x00200000 */
25442 #define PKA_SR_OPERRF                       PKA_SR_OPERRF_Msk                       /*!< PKA operation Error flag*/
25443 
25444 /*******************  Bit definition for PKA_CLRFR register  ******************/
25445 #define PKA_CLRFR_PROCENDFC_Pos             (17U)
25446 #define PKA_CLRFR_PROCENDFC_Msk             (0x1UL << PKA_CLRFR_PROCENDFC_Pos)      /*!< 0x00020000 */
25447 #define PKA_CLRFR_PROCENDFC                 PKA_CLRFR_PROCENDFC_Msk                 /*!< Clear PKA end of operation flag */
25448 #define PKA_CLRFR_RAMERRFC_Pos              (19U)
25449 #define PKA_CLRFR_RAMERRFC_Msk              (0x1UL << PKA_CLRFR_RAMERRFC_Pos)       /*!< 0x00080000 */
25450 #define PKA_CLRFR_RAMERRFC                  PKA_CLRFR_RAMERRFC_Msk                  /*!< Clear PKA RAM error flag */
25451 #define PKA_CLRFR_ADDRERRFC_Pos             (20U)
25452 #define PKA_CLRFR_ADDRERRFC_Msk             (0x1UL << PKA_CLRFR_ADDRERRFC_Pos)      /*!< 0x00100000 */
25453 #define PKA_CLRFR_ADDRERRFC                 PKA_CLRFR_ADDRERRFC_Msk                 /*!< Clear address error flag */
25454 #define PKA_CLRFR_OPERRFC_Pos               (21U)
25455 #define PKA_CLRFR_OPERRFC_Msk               (0x1UL << PKA_CLRFR_OPERRFC_Pos)        /*!< 0x00200000 */
25456 #define PKA_CLRFR_OPERRFC                   PKA_CLRFR_OPERRFC_Msk                   /*!< Clear PKA operation Error flag*/
25457 
25458 /*******************  Bits definition for PKA RAM  *************************/
25459 #define PKA_RAM_OFFSET                                 (0x0400UL)                          /*!< PKA RAM address offset */
25460 
25461 /* Compute Montgomery parameter input data */
25462 #define PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS            ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
25463 #define PKA_MONTGOMERY_PARAM_IN_MODULUS                ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus */
25464 
25465 /* Compute Montgomery parameter output data */
25466 #define PKA_MONTGOMERY_PARAM_OUT_PARAMETER             ((0x0620UL - PKA_RAM_OFFSET)>>2)    /*!< Output Montgomery parameter */
25467 
25468 /* Compute modular exponentiation input data */
25469 #define PKA_MODULAR_EXP_IN_EXP_NB_BITS                 ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input exponent number of bits */
25470 #define PKA_MODULAR_EXP_IN_OP_NB_BITS                  ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
25471 #define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM            ((0x0620UL - PKA_RAM_OFFSET)>>2)    /*!< Input storage area for Montgomery parameter */
25472 #define PKA_MODULAR_EXP_IN_EXPONENT_BASE               ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input base of the exponentiation */
25473 #define PKA_MODULAR_EXP_IN_EXPONENT                    ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Input exponent to process */
25474 #define PKA_MODULAR_EXP_IN_MODULUS                     ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus */
25475 #define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE       ((0x16C8UL - PKA_RAM_OFFSET)>>2)    /*!< Input base of the protected exponentiation */
25476 #define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT            ((0x14B8UL - PKA_RAM_OFFSET)>>2)    /*!< Input exponent to process protected exponentiation*/
25477 #define PKA_MODULAR_EXP_PROTECT_IN_MODULUS             ((0x0838UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus to process protected exponentiation */
25478 #define PKA_MODULAR_EXP_PROTECT_IN_PHI                 ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input phi to process protected exponentiation */
25479 
25480 /* Compute modular exponentiation output data */
25481 #define PKA_MODULAR_EXP_OUT_RESULT                     ((0x0838UL - PKA_RAM_OFFSET)>>2)    /*!< Output result of the exponentiation */
25482 #define PKA_MODULAR_EXP_OUT_ERROR                      ((0x1298UL - PKA_RAM_OFFSET)>>2)    /*!< Output error of the exponentiation */
25483 #define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM           ((0x0620UL - PKA_RAM_OFFSET)>>2)    /*!< Output storage area for Montgomery parameter */
25484 #define PKA_MODULAR_EXP_OUT_EXPONENT_BASE              ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Output base of the exponentiation */
25485 
25486 /* Compute ECC scalar multiplication input data */
25487 #define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS              ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input curve prime order n number of bits */
25488 #define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
25489 #define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN             ((0x0410UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
25490 #define PKA_ECC_SCALAR_MUL_IN_A_COEFF                  ((0x0418UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'a' coefficient */
25491 #define PKA_ECC_SCALAR_MUL_IN_B_COEFF                  ((0x0520UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'b' coefficient */
25492 #define PKA_ECC_SCALAR_MUL_IN_MOD_GF                   ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
25493 #define PKA_ECC_SCALAR_MUL_IN_K                        ((0x12A0UL - PKA_RAM_OFFSET)>>2)    /*!< Input 'k' of KP */
25494 #define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X          ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
25495 #define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y          ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
25496 #define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER            ((0x0F88UL - PKA_RAM_OFFSET)>>2)    /*!< Input prime order n */
25497 
25498 /* Compute ECC scalar multiplication output data */
25499 #define PKA_ECC_SCALAR_MUL_OUT_RESULT_X                ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Output result X coordinate */
25500 #define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y                ((0x05D0UL - PKA_RAM_OFFSET)>>2)    /*!< Output result Y coordinate */
25501 #define PKA_ECC_SCALAR_MUL_OUT_ERROR                   ((0x0680UL - PKA_RAM_OFFSET)>>2)    /*!< Output result error */
25502 
25503 /* Point check input data */
25504 #define PKA_POINT_CHECK_IN_MOD_NB_BITS                 ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
25505 #define PKA_POINT_CHECK_IN_A_COEFF_SIGN                ((0x0410UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
25506 #define PKA_POINT_CHECK_IN_A_COEFF                     ((0x0418UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'a' coefficient */
25507 #define PKA_POINT_CHECK_IN_B_COEFF                     ((0x0520UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'b' coefficient */
25508 #define PKA_POINT_CHECK_IN_MOD_GF                      ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
25509 #define PKA_POINT_CHECK_IN_INITIAL_POINT_X             ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
25510 #define PKA_POINT_CHECK_IN_INITIAL_POINT_Y             ((0x05D0UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
25511 #define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM            ((0x04C8UL - PKA_RAM_OFFSET)>>2)    /*!< Input storage area for Montgomery parameter */
25512 
25513 /* Point check output data */
25514 #define PKA_POINT_CHECK_OUT_ERROR                      ((0x0680UL - PKA_RAM_OFFSET)>>2)    /*!< Output error */
25515 
25516 /* ECDSA signature input data */
25517 #define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS                ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input order number of bits */
25518 #define PKA_ECDSA_SIGN_IN_MOD_NB_BITS                  ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
25519 #define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN                 ((0x0410UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
25520 #define PKA_ECDSA_SIGN_IN_A_COEFF                      ((0x0418UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'a' coefficient */
25521 #define PKA_ECDSA_SIGN_IN_B_COEFF                      ((0x0520UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'b' coefficient */
25522 #define PKA_ECDSA_SIGN_IN_MOD_GF                       ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
25523 #define PKA_ECDSA_SIGN_IN_K                            ((0x12A0UL - PKA_RAM_OFFSET)>>2)    /*!< Input k value of the ECDSA */
25524 #define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X              ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
25525 #define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y              ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
25526 #define PKA_ECDSA_SIGN_IN_HASH_E                       ((0x0FE8UL - PKA_RAM_OFFSET)>>2)    /*!< Input e, hash of the message */
25527 #define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D                ((0x0F28UL - PKA_RAM_OFFSET)>>2)    /*!< Input d, private key */
25528 #define PKA_ECDSA_SIGN_IN_ORDER_N                      ((0x0F88UL - PKA_RAM_OFFSET)>>2)    /*!< Input n, order of the curve */
25529 
25530 /* ECDSA signature output data */
25531 #define PKA_ECDSA_SIGN_OUT_ERROR                       ((0x0FE0UL - PKA_RAM_OFFSET)>>2)    /*!< Output error */
25532 #define PKA_ECDSA_SIGN_OUT_SIGNATURE_R                 ((0x0730UL - PKA_RAM_OFFSET)>>2)    /*!< Output signature r */
25533 #define PKA_ECDSA_SIGN_OUT_SIGNATURE_S                 ((0x0788UL - PKA_RAM_OFFSET)>>2)    /*!< Output signature s */
25534 #define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X               ((0x1400UL - PKA_RAM_OFFSET)>>2)    /*!< Extended output result point X coordinate */
25535 #define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y               ((0x1458UL - PKA_RAM_OFFSET)>>2)    /*!< Extended output result point Y coordinate */
25536 
25537 
25538 /* ECDSA verification input data */
25539 #define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input order number of bits */
25540 #define PKA_ECDSA_VERIF_IN_MOD_NB_BITS                 ((0x04C8UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
25541 #define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN                ((0x0468UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
25542 #define PKA_ECDSA_VERIF_IN_A_COEFF                     ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'a' coefficient */
25543 #define PKA_ECDSA_VERIF_IN_MOD_GF                      ((0x04D0UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
25544 #define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X             ((0x0678UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
25545 #define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y             ((0x06D0UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
25546 #define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X          ((0x12F8UL - PKA_RAM_OFFSET)>>2)    /*!< Input public key point X coordinate */
25547 #define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y          ((0x1350UL - PKA_RAM_OFFSET)>>2)    /*!< Input public key point Y coordinate */
25548 #define PKA_ECDSA_VERIF_IN_SIGNATURE_R                 ((0x10E0UL - PKA_RAM_OFFSET)>>2)    /*!< Input r, part of the signature */
25549 #define PKA_ECDSA_VERIF_IN_SIGNATURE_S                 ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input s, part of the signature */
25550 #define PKA_ECDSA_VERIF_IN_HASH_E                      ((0x13A8UL - PKA_RAM_OFFSET)>>2)    /*!< Input e, hash of the message */
25551 #define PKA_ECDSA_VERIF_IN_ORDER_N                     ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input n, order of the curve */
25552 
25553 /* ECDSA verification output data */
25554 #define PKA_ECDSA_VERIF_OUT_RESULT                     ((0x05D0UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
25555 
25556 /* RSA CRT exponentiation input data */
25557 #define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS                 ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operands number of bits */
25558 #define PKA_RSA_CRT_EXP_IN_DP_CRT                      ((0x0730UL - PKA_RAM_OFFSET)>>2)    /*!< Input Dp CRT parameter */
25559 #define PKA_RSA_CRT_EXP_IN_DQ_CRT                      ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Input Dq CRT parameter */
25560 #define PKA_RSA_CRT_EXP_IN_QINV_CRT                    ((0x0948UL - PKA_RAM_OFFSET)>>2)    /*!< Input qInv CRT parameter */
25561 #define PKA_RSA_CRT_EXP_IN_PRIME_P                     ((0x0B60UL - PKA_RAM_OFFSET)>>2)    /*!< Input Prime p */
25562 #define PKA_RSA_CRT_EXP_IN_PRIME_Q                     ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input Prime q */
25563 #define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE               ((0x12A0UL - PKA_RAM_OFFSET)>>2)    /*!< Input base of the exponentiation */
25564 
25565 /* RSA CRT exponentiation output data */
25566 #define PKA_RSA_CRT_EXP_OUT_RESULT                     ((0x0838UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
25567 
25568 /* Modular reduction input data */
25569 #define PKA_MODULAR_REDUC_IN_OP_LENGTH                 ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand length */
25570 #define PKA_MODULAR_REDUC_IN_MOD_LENGTH                ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus length */
25571 #define PKA_MODULAR_REDUC_IN_OPERAND                   ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand */
25572 #define PKA_MODULAR_REDUC_IN_MODULUS                   ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus */
25573 
25574 /* Modular reduction output data */
25575 #define PKA_MODULAR_REDUC_OUT_RESULT                   ((0xE78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
25576 
25577 /* Arithmetic addition input data */
25578 #define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
25579 #define PKA_ARITHMETIC_ADD_IN_OP1                      ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
25580 #define PKA_ARITHMETIC_ADD_IN_OP2                      ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
25581 
25582 /* Arithmetic addition output data */
25583 #define PKA_ARITHMETIC_ADD_OUT_RESULT                  ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
25584 
25585 /* Arithmetic subtraction input data */
25586 #define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
25587 #define PKA_ARITHMETIC_SUB_IN_OP1                      ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
25588 #define PKA_ARITHMETIC_SUB_IN_OP2                      ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
25589 
25590 /* Arithmetic subtraction output data */
25591 #define PKA_ARITHMETIC_SUB_OUT_RESULT                  ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
25592 
25593 /* Arithmetic multiplication input data */
25594 #define PKA_ARITHMETIC_MUL_NB_BITS                     ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
25595 #define PKA_ARITHMETIC_MUL_IN_OP1                      ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
25596 #define PKA_ARITHMETIC_MUL_IN_OP2                      ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
25597 
25598 /* Arithmetic multiplication output data */
25599 #define PKA_ARITHMETIC_MUL_OUT_RESULT                  ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
25600 
25601 /* Comparison input data */
25602 #define PKA_COMPARISON_IN_OP_NB_BITS                   ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
25603 #define PKA_COMPARISON_IN_OP1                          ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
25604 #define PKA_COMPARISON_IN_OP2                          ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
25605 
25606 /* Comparison output data */
25607 #define PKA_COMPARISON_OUT_RESULT                      ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
25608 
25609 /* Modular addition input data */
25610 #define PKA_MODULAR_ADD_NB_BITS                        ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
25611 #define PKA_MODULAR_ADD_IN_OP1                         ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
25612 #define PKA_MODULAR_ADD_IN_OP2                         ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
25613 #define PKA_MODULAR_ADD_IN_OP3_MOD                     ((0x1088UL - PKA_RAM_OFFSET)>>2)   /*!< Input operand op3 (modulus) */
25614 
25615 /* Modular addition output data */
25616 #define PKA_MODULAR_ADD_OUT_RESULT                     ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
25617 
25618 /* Modular inversion input data */
25619 #define PKA_MODULAR_INV_NB_BITS                        ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
25620 #define PKA_MODULAR_INV_IN_OP1                         ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
25621 #define PKA_MODULAR_INV_IN_OP2_MOD                     ((0x0C68UL - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 (modulus) */
25622 
25623 /* Modular inversion output data */
25624 #define PKA_MODULAR_INV_OUT_RESULT                     ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
25625 
25626 /* Modular subtraction input data */
25627 #define PKA_MODULAR_SUB_IN_OP_NB_BITS                  ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
25628 #define PKA_MODULAR_SUB_IN_OP1                         ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
25629 #define PKA_MODULAR_SUB_IN_OP2                         ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
25630 #define PKA_MODULAR_SUB_IN_OP3_MOD                     ((0x1088UL - PKA_RAM_OFFSET)>>2)   /*!< Input operand op3 */
25631 
25632 /* Modular subtraction output data */
25633 #define PKA_MODULAR_SUB_OUT_RESULT                     ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
25634 
25635 /* Montgomery multiplication input data */
25636 #define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
25637 #define PKA_MONTGOMERY_MUL_IN_OP1                      ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
25638 #define PKA_MONTGOMERY_MUL_IN_OP2                      ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
25639 #define PKA_MONTGOMERY_MUL_IN_OP3_MOD                  ((0x1088UL - PKA_RAM_OFFSET)>>2)   /*!< Input modulus */
25640 
25641 /* Montgomery multiplication output data */
25642 #define PKA_MONTGOMERY_MUL_OUT_RESULT                  ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
25643 
25644 /* Generic Arithmetic input data */
25645 #define PKA_ARITHMETIC_ALL_OPS_NB_BITS                 ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
25646 #define PKA_ARITHMETIC_ALL_OPS_IN_OP1                  ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
25647 #define PKA_ARITHMETIC_ALL_OPS_IN_OP2                  ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
25648 #define PKA_ARITHMETIC_ALL_OPS_IN_OP3                  ((0x1088UL - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
25649 
25650 /* Generic Arithmetic output data */
25651 #define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT              ((0x0E78UL - PKA_RAM_OFFSET)>>2)   /*!< Output result for arithmetic operations */
25652 
25653 /* Compute ECC complete addition input data */
25654 #define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS            ((0x0408UL - PKA_RAM_OFFSET)>>2)   /*!< Input Modulus number of bits */
25655 #define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN           ((0x0410UL - PKA_RAM_OFFSET)>>2)   /*!< Input sign of the 'a' coefficient */
25656 #define PKA_ECC_COMPLETE_ADD_IN_A_COEFF                ((0x0418UL - PKA_RAM_OFFSET)>>2)   /*!< Input ECC curve '|a|' coefficient */
25657 #define PKA_ECC_COMPLETE_ADD_IN_MOD_P                  ((0x0470UL - PKA_RAM_OFFSET)>>2)   /*!< Input modulus GF(p) */
25658 #define PKA_ECC_COMPLETE_ADD_IN_POINT1_X               ((0x0628UL - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P X coordinate */
25659 #define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y               ((0x0680UL - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P Y coordinate */
25660 #define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z               ((0x06D8UL - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P Z coordinate */
25661 #define PKA_ECC_COMPLETE_ADD_IN_POINT2_X               ((0x0730UL - PKA_RAM_OFFSET)>>2)   /*!< Input initial point Q X coordinate */
25662 #define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y               ((0x0788UL - PKA_RAM_OFFSET)>>2)   /*!< Input initial point Q Y coordinate */
25663 #define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z               ((0x07E0UL - PKA_RAM_OFFSET)>>2)   /*!< Input initial point Q Z coordinate */
25664 
25665 /* Compute ECC complete addition output data */
25666 #define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X              ((0x0D60UL - PKA_RAM_OFFSET)>>2)   /*!< Output result X coordinate */
25667 #define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y              ((0x0DB8UL - PKA_RAM_OFFSET)>>2)   /*!< Output result Y coordinate */
25668 #define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z              ((0x0E10UL - PKA_RAM_OFFSET)>>2)   /*!< Output result Z coordinate */
25669 
25670 /* Compute ECC double base ladder input data */
25671 #define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS  ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input n, order of the curve */
25672 #define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS          ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input Modulus number of bits */
25673 #define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN         ((0x0410UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
25674 #define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF              ((0x0418UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve '|a|' coefficient */
25675 #define PKA_ECC_DOUBLE_LADDER_IN_MOD_P                ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
25676 #define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER            ((0x0520UL - PKA_RAM_OFFSET)>>2)    /*!< Input 'k' integer coefficient */
25677 #define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER            ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Input 'm' integer coefficient */
25678 #define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X             ((0x0628UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
25679 #define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y             ((0x0680UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
25680 #define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z             ((0x06D8UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Z coordinate */
25681 #define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X             ((0x0730UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point Q X coordinate */
25682 #define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y             ((0x0788UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point Q Y coordinate */
25683 #define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z             ((0x07E0UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point Q Z coordinate */
25684 
25685 /* Compute ECC double base ladder output data */
25686 #define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X          ((0x0578UL - PKA_RAM_OFFSET)>>2)      /*!< Output result X coordinate (affine coordinate) */
25687 #define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y          ((0x05D0UL - PKA_RAM_OFFSET)>>2)      /*!< Output result Y coordinate (affine coordinate) */
25688 #define PKA_ECC_DOUBLE_LADDER_OUT_ERROR             ((0x0520UL - PKA_RAM_OFFSET)>>2)      /*!< Output result error */
25689 
25690 /* Compute ECC projective to affine conversion input data */
25691 #define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS           ((0x0408UL - PKA_RAM_OFFSET)>>2)  /*!< Input Modulus number of bits */
25692 #define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P                 ((0x0470UL - PKA_RAM_OFFSET)>>2)  /*!< Input modulus GF(p) */
25693 #define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X               ((0x0D60UL - PKA_RAM_OFFSET)>>2)  /*!< Input initial projective point P X coordinate */
25694 #define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y               ((0x0DB8UL - PKA_RAM_OFFSET)>>2)  /*!< Input initial projective point P Y coordinate */
25695 #define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z               ((0x0E10UL - PKA_RAM_OFFSET)>>2)  /*!< Input initial projective point P Z coordinate */
25696 #define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2   ((0x04C8UL - PKA_RAM_OFFSET)>>2)  /*!< Input storage area for Montgomery parameter */
25697 
25698 /* Compute ECC projective to affine conversion output data */
25699 #define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X      ((0x0578UL - PKA_RAM_OFFSET)>>2)         /*!< Output result x affine coordinate */
25700 #define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y      ((0x05D0UL - PKA_RAM_OFFSET)>>2)         /*!< Output result y affine coordinate */
25701 #define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR         ((0x0680UL - PKA_RAM_OFFSET)>>2)         /*!< Output result error */
25702 
25703 
25704 /******************************************************************************/
25705 /*                                                                            */
25706 /*                Parallel Synchronous Slave Interface (PSSI )                */
25707 /*                                                                            */
25708 /******************************************************************************/
25709 /********************  Bit definition for PSSI_CR register  *******************/
25710 #define PSSI_CR_CKPOL_Pos                   (5U)
25711 #define PSSI_CR_CKPOL_Msk                   (0x1UL << PSSI_CR_CKPOL_Pos)            /*!< 0x00000020 */
25712 #define PSSI_CR_CKPOL                       PSSI_CR_CKPOL_Msk                       /*!< Parallel data clock polarity */
25713 #define PSSI_CR_DEPOL_Pos                   (6U)
25714 #define PSSI_CR_DEPOL_Msk                   (0x1UL << PSSI_CR_DEPOL_Pos)            /*!< 0x00000040 */
25715 #define PSSI_CR_DEPOL                       PSSI_CR_DEPOL_Msk                       /*!<  Data enable polarity */
25716 #define PSSI_CR_RDYPOL_Pos                  (8U)
25717 #define PSSI_CR_RDYPOL_Msk                  (0x1UL << PSSI_CR_RDYPOL_Pos)           /*!< 0x00000100 */
25718 #define PSSI_CR_RDYPOL                      PSSI_CR_RDYPOL_Msk                      /*!< Ready polarity */
25719 #define PSSI_CR_EDM_Pos                     (10U)
25720 #define PSSI_CR_EDM_Msk                     (0x3UL << PSSI_CR_EDM_Pos)              /*!< 0x00000C00 */
25721 #define PSSI_CR_EDM                         PSSI_CR_EDM_Msk                         /*!< Extended data mode */
25722 #define PSSI_CR_ENABLE_Pos                  (14U)
25723 #define PSSI_CR_ENABLE_Msk                  (0x1UL << PSSI_CR_ENABLE_Pos)           /*!< 0x00004000 */
25724 #define PSSI_CR_ENABLE                      PSSI_CR_ENABLE_Msk                      /*!< PSSI enable */
25725 #define PSSI_CR_DERDYCFG_Pos                (18U)
25726 #define PSSI_CR_DERDYCFG_Msk                (0x7UL << PSSI_CR_DERDYCFG_Pos)         /*!< 0x001C0000 */
25727 #define PSSI_CR_DERDYCFG                    PSSI_CR_DERDYCFG_Msk                    /*!< Data enable and ready configuration */
25728 #define PSSI_CR_CKSRC_Pos                   (29U)
25729 #define PSSI_CR_CKSRC_Msk                   (0x1UL << PSSI_CR_CKSRC_Pos)            /*!< 0x20000000 */
25730 #define PSSI_CR_CKSRC                       PSSI_CR_CKSRC_Msk                       /*!< Clock source */
25731 #define PSSI_CR_DMAEN_Pos                   (30U)
25732 #define PSSI_CR_DMAEN_Msk                   (0x1UL << PSSI_CR_DMAEN_Pos)            /*!< 0x40000000 */
25733 #define PSSI_CR_DMAEN                       PSSI_CR_DMAEN_Msk                       /*!< DMA enable */
25734 #define PSSI_CR_OUTEN_Pos                   (31U)
25735 #define PSSI_CR_OUTEN_Msk                   (0x1UL << PSSI_CR_OUTEN_Pos)            /*!< 0x80000000 */
25736 #define PSSI_CR_OUTEN                       PSSI_CR_OUTEN_Msk                       /*!< Data direction selection */
25737 
25738 /********************  Bit definition for PSSI_SR register  *******************/
25739 #define PSSI_SR_RTT4B_Pos                   (2U)
25740 #define PSSI_SR_RTT4B_Msk                   (0x1UL << PSSI_SR_RTT4B_Pos)            /*!< 0x00000004 */
25741 #define PSSI_SR_RTT4B                       PSSI_SR_RTT4B_Msk                       /*!< Ready to transfer four bytes */
25742 #define PSSI_SR_RTT1B_Pos                   (3U)
25743 #define PSSI_SR_RTT1B_Msk                   (0x1UL << PSSI_SR_RTT1B_Pos)            /*!< 0x00000008 */
25744 #define PSSI_SR_RTT1B                       PSSI_SR_RTT1B_Msk                       /*!< Ready to transfer one byte */
25745 
25746 /********************  Bit definition for PSSI_RIS register  *******************/
25747 #define PSSI_RIS_OVR_RIS_Pos                (1U)
25748 #define PSSI_RIS_OVR_RIS_Msk                (0x1UL << PSSI_RIS_OVR_RIS_Pos)         /*!< 0x00000002 */
25749 #define PSSI_RIS_OVR_RIS                    PSSI_RIS_OVR_RIS_Msk                    /*!< Data buffer overrun/underrun raw interrupt status */
25750 
25751 /********************  Bit definition for PSSI_IER register  *******************/
25752 #define PSSI_IER_OVR_IE_Pos                 (1U)
25753 #define PSSI_IER_OVR_IE_Msk                 (0x1UL << PSSI_IER_OVR_IE_Pos)          /*!< 0x00000002 */
25754 #define PSSI_IER_OVR_IE                     PSSI_IER_OVR_IE_Msk                     /*!< Data buffer overrun/underrun interrupt enable */
25755 
25756 /********************  Bit definition for PSSI_MIS register  *******************/
25757 #define PSSI_MIS_OVR_MIS_Pos                (1U)
25758 #define PSSI_MIS_OVR_MIS_Msk                (0x1UL << PSSI_MIS_OVR_MIS_Pos)         /*!< 0x00000002 */
25759 #define PSSI_MIS_OVR_MIS                    PSSI_MIS_OVR_MIS_Msk                    /*!< Data buffer overrun/underrun masked interrupt status */
25760 
25761 /********************  Bit definition for PSSI_ICR register  *******************/
25762 #define PSSI_ICR_OVR_ISC_Pos                (1U)
25763 #define PSSI_ICR_OVR_ISC_Msk                (0x1UL << PSSI_ICR_OVR_ISC_Pos)         /*!< 0x00000002 */
25764 #define PSSI_ICR_OVR_ISC                    PSSI_ICR_OVR_ISC_Msk                    /*!< Data buffer overrun/underrun interrupt status clear */
25765 
25766 /********************  Bit definition for PSSI_DR register  *******************/
25767 #define PSSI_DR_DR_Pos                      (0U)
25768 #define PSSI_DR_DR_Msk                      (0xFFFFFFFFUL << PSSI_DR_DR_Pos)        /*!< 0xFFFFFFF */
25769 #define PSSI_DR_DR                          PSSI_DR_DR_Msk                          /*!< Data register  */
25770 
25771 
25772 /******************************************************************************/
25773 /*                                                                            */
25774 /*                             Power Control                                  */
25775 /*                                                                            */
25776 /******************************************************************************/
25777 /*******************  Bit definition for PWR_CR1 register  ********************/
25778 #define PWR_CR1_SDEN_Pos                (2U)
25779 #define PWR_CR1_SDEN_Msk                (0x1UL << PWR_CR1_SDEN_Pos)             /*!< 0x00000004 */
25780 #define PWR_CR1_SDEN                    PWR_CR1_SDEN_Msk                        /*!< SMPS step-down converter enable */
25781 #define PWR_CR1_MODE_PDN_Pos            (4U)
25782 #define PWR_CR1_MODE_PDN_Msk            (0x1UL << PWR_CR1_MODE_PDN_Pos)         /*!< 0x00000010 */
25783 #define PWR_CR1_MODE_PDN                PWR_CR1_MODE_PDN_Msk                    /*!< Pull down on output voltage during power down mode */
25784 #define PWR_CR1_LPDS08V_Pos             (5U)
25785 #define PWR_CR1_LPDS08V_Msk             (0x1UL << PWR_CR1_LPDS08V_Pos)          /*!< 0x00000020 */
25786 #define PWR_CR1_LPDS08V                 PWR_CR1_LPDS08V_Msk                     /*!< SMPS Low power mode enable (SVOS high only) */
25787 #define PWR_CR1_VDD18SMPSVMEN_Pos       (8U)
25788 #define PWR_CR1_VDD18SMPSVMEN_Msk       (0x1UL << PWR_CR1_VDD18SMPSVMEN_Pos)    /*!< 0x00000100 */
25789 #define PWR_CR1_VDD18SMPSVMEN           PWR_CR1_VDD18SMPSVMEN_Msk               /*!< VDD18SMPS voltage monitor enable */
25790 #define PWR_CR1_VDD18SMPSRDY_Pos        (15U)
25791 #define PWR_CR1_VDD18SMPSRDY_Msk        (0x1UL << PWR_CR1_VDD18SMPSRDY_Pos)     /*!< 0x00008000 */
25792 #define PWR_CR1_VDD18SMPSRDY            PWR_CR1_VDD18SMPSRDY_Msk                /*!< VDD18SMPS ready */
25793 #define PWR_CR1_POPL_Pos                (16U)
25794 #define PWR_CR1_POPL_Msk                (0x1FUL << PWR_CR1_POPL_Pos)            /*!< 0x001F0000 */
25795 #define PWR_CR1_POPL                    PWR_CR1_POPL_Msk                        /*!< pwr_on pulse low configuration */
25796 #define PWR_CR1_POPL_0                  (0x1UL << PWR_CR1_POPL_Pos)             /*!< 0x00010000 */
25797 #define PWR_CR1_POPL_1                  (0x2UL << PWR_CR1_POPL_Pos)             /*!< 0x00020000 */
25798 #define PWR_CR1_POPL_2                  (0x4UL << PWR_CR1_POPL_Pos)             /*!< 0x00040000 */
25799 #define PWR_CR1_POPL_3                  (0x8UL << PWR_CR1_POPL_Pos)             /*!< 0x00080000 */
25800 #define PWR_CR1_POPL_4                  (0x10UL << PWR_CR1_POPL_Pos)            /*!< 0x00100000 */
25801 
25802 /*******************  Bit definition for PWR_CR2 register  ********************/
25803 #define PWR_CR2_PVDEN_Pos               (0U)
25804 #define PWR_CR2_PVDEN_Msk               (0x1UL << PWR_CR2_PVDEN_Pos)            /*!< 0x00000001 */
25805 #define PWR_CR2_PVDEN                   PWR_CR2_PVDEN_Msk                       /*!< Programmable Voltage detector enable */
25806 #define PWR_CR2_PVDO_Pos                (8U)
25807 #define PWR_CR2_PVDO_Msk                (0x1UL << PWR_CR2_PVDO_Pos)             /*!< 0x00000100 */
25808 #define PWR_CR2_PVDO                    PWR_CR2_PVDO_Msk                        /*!< Programmable Voltage Detect Output */
25809 
25810 /*******************  Bit definition for PWR_CR3 register  ********************/
25811 #define PWR_CR3_VCOREMONEN_Pos          (0U)
25812 #define PWR_CR3_VCOREMONEN_Msk          (0x1UL << PWR_CR3_VCOREMONEN_Pos)       /*!< 0x00000001 */
25813 #define PWR_CR3_VCOREMONEN              PWR_CR3_VCOREMONEN_Msk                  /*!< VDDCORE monitoring enable */
25814 #define PWR_CR3_VCORELLS_Pos            (4U)
25815 #define PWR_CR3_VCORELLS_Msk            (0x1UL << PWR_CR3_VCORELLS_Pos)         /*!< 0x00000010 */
25816 #define PWR_CR3_VCORELLS                PWR_CR3_VCORELLS_Msk                    /*!< VDDCORE Voltage Detector low level selection */
25817 #define PWR_CR3_VCOREL_Pos              (8U)
25818 #define PWR_CR3_VCOREL_Msk              (0x1UL << PWR_CR3_VCOREL_Pos)           /*!< 0x00000100 */
25819 #define PWR_CR3_VCOREL                  PWR_CR3_VCOREL_Msk                      /*!< Monitored VDDCORE level above low threshold */
25820 #define PWR_CR3_VCOREH_Pos              (9U)
25821 #define PWR_CR3_VCOREH_Msk              (0x1UL << PWR_CR3_VCOREH_Pos)           /*!< 0x00000200 */
25822 #define PWR_CR3_VCOREH                  PWR_CR3_VCOREH_Msk                      /*!< Monitored VDDCORE level above high threshold */
25823 
25824 /*******************  Bit definition for PWR_CR4 register  ********************/
25825 #define PWR_CR4_TCMRBSEN_Pos            (0U)
25826 #define PWR_CR4_TCMRBSEN_Msk            (0x1UL << PWR_CR4_TCMRBSEN_Pos)         /*!< 0x00000001 */
25827 #define PWR_CR4_TCMRBSEN                PWR_CR4_TCMRBSEN_Msk                    /*!< I-TCM and D-TCM RAMs backup supply enable (used to maintain TCM RAMs content in Standby mode) */
25828 #define PWR_CR4_TCMFLXRBSEN_Pos         (4U)
25829 #define PWR_CR4_TCMFLXRBSEN_Msk         (0x1UL << PWR_CR4_TCMFLXRBSEN_Pos)      /*!< 0x00000010 */
25830 #define PWR_CR4_TCMFLXRBSEN             PWR_CR4_TCMFLXRBSEN_Msk                 /*!< I-TCM FLEX MEM backup supply enable (used to maintain I-TCM FLEX MEM content in Standby mode) */
25831 
25832 /******************  Bit definition for PWR_VOSCR register  *******************/
25833 #define PWR_VOSCR_VOS_Pos               (0U)
25834 #define PWR_VOSCR_VOS_Msk               (0x1UL << PWR_VOSCR_VOS_Pos)            /*!< 0x00000001 */
25835 #define PWR_VOSCR_VOS                   PWR_VOSCR_VOS_Msk                       /*!< Voltage scaling selection according to performance */
25836 #define PWR_VOSCR_VOSRDY_Pos            (1U)
25837 #define PWR_VOSCR_VOSRDY_Msk            (0x1UL << PWR_VOSCR_VOSRDY_Pos)         /*!< 0x00000002 */
25838 #define PWR_VOSCR_VOSRDY                PWR_VOSCR_VOSRDY_Msk                    /*!< VOS Ready bit for VCORE voltage scaling output selection */
25839 #define PWR_VOSCR_ACTVOS_Pos            (16U)
25840 #define PWR_VOSCR_ACTVOS_Msk            (0x1UL << PWR_VOSCR_ACTVOS_Pos)         /*!< 0x00010000 */
25841 #define PWR_VOSCR_ACTVOS                PWR_VOSCR_ACTVOS_Msk                    /*!< VOS currently applied for VCORE voltage scaling selection */
25842 #define PWR_VOSCR_ACTVOSRDY_Pos         (17U)
25843 #define PWR_VOSCR_ACTVOSRDY_Msk         (0x1UL << PWR_VOSCR_ACTVOSRDY_Pos)      /*!< 0x00020000 */
25844 #define PWR_VOSCR_ACTVOSRDY             PWR_VOSCR_ACTVOSRDY_Msk                 /*!< Voltage levels ready bit for currently used ACTVOS */
25845 
25846 /******************  Bit definition for PWR_BDCR1 register  *******************/
25847 #define PWR_BDCR1_MONEN_Pos             (0U)
25848 #define PWR_BDCR1_MONEN_Msk             (0x1UL << PWR_BDCR1_MONEN_Pos)          /*!< 0x00000001 */
25849 #define PWR_BDCR1_MONEN                 PWR_BDCR1_MONEN_Msk                     /*!< VBAT and temperature monitoring enable */
25850 #define PWR_BDCR1_VBATL_Pos             (16U)
25851 #define PWR_BDCR1_VBATL_Msk             (0x1UL << PWR_BDCR1_VBATL_Pos)          /*!< 0x00010000 */
25852 #define PWR_BDCR1_VBATL                 PWR_BDCR1_VBATL_Msk                     /*!< VBAT level monitoring versus low threshold */
25853 #define PWR_BDCR1_VBATH_Pos             (17U)
25854 #define PWR_BDCR1_VBATH_Msk             (0x1UL << PWR_BDCR1_VBATH_Pos)          /*!< 0x00020000 */
25855 #define PWR_BDCR1_VBATH                 PWR_BDCR1_VBATH_Msk                     /*!< VBAT level monitoring versus high threshold */
25856 #define PWR_BDCR1_TEMPL_Pos             (18U)
25857 #define PWR_BDCR1_TEMPL_Msk             (0x1UL << PWR_BDCR1_TEMPL_Pos)          /*!< 0x00040000 */
25858 #define PWR_BDCR1_TEMPL                 PWR_BDCR1_TEMPL_Msk                     /*!< Temperature level monitoring versus low threshold */
25859 #define PWR_BDCR1_TEMPH_Pos             (19U)
25860 #define PWR_BDCR1_TEMPH_Msk             (0x1UL << PWR_BDCR1_TEMPH_Pos)          /*!< 0x00080000 */
25861 #define PWR_BDCR1_TEMPH                 PWR_BDCR1_TEMPH_Msk                     /*!< Temperature level monitoring versus high threshold */
25862 
25863 /******************  Bit definition for PWR_BDCR2 register  *******************/
25864 #define PWR_BDCR2_BKPRBSEN_Pos          (0U)
25865 #define PWR_BDCR2_BKPRBSEN_Msk          (0x1UL << PWR_BDCR2_BKPRBSEN_Pos)       /*!< 0x00000001 */
25866 #define PWR_BDCR2_BKPRBSEN              PWR_BDCR2_BKPRBSEN_Msk                  /*!< Backup RAM backup supply enable (used to maintain BKP RAM content in Standby and VBAT modes) */
25867 
25868 /******************  Bit definition for PWR_DBPCR register  *******************/
25869 #define PWR_DBPCR_DBP_Pos               (0U)
25870 #define PWR_DBPCR_DBP_Msk               (0x1UL << PWR_DBPCR_DBP_Pos)            /*!< 0x00000001 */
25871 #define PWR_DBPCR_DBP                   PWR_DBPCR_DBP_Msk                       /*!< Disable backup domain write protection */
25872 
25873 /******************  Bit definition for PWR_CPUCR register  *******************/
25874 #define PWR_CPUCR_PDDS_Pos              (0U)
25875 #define PWR_CPUCR_PDDS_Msk              (0x1UL << PWR_CPUCR_PDDS_Pos)           /*!< 0x00000001 */
25876 #define PWR_CPUCR_PDDS                  PWR_CPUCR_PDDS_Msk                      /*!< Power Down Deepsleep selection */
25877 #define PWR_CPUCR_CSSF_Pos              (1U)
25878 #define PWR_CPUCR_CSSF_Msk              (0x1UL << PWR_CPUCR_CSSF_Pos)           /*!< 0x00000002 */
25879 #define PWR_CPUCR_CSSF                  PWR_CPUCR_CSSF_Msk                      /*!< Clear Standby and Stop flags (always read as 0) */
25880 #define PWR_CPUCR_STOPF_Pos             (8U)
25881 #define PWR_CPUCR_STOPF_Msk             (0x1UL << PWR_CPUCR_STOPF_Pos)          /*!< 0x00000100 */
25882 #define PWR_CPUCR_STOPF                 PWR_CPUCR_STOPF_Msk                     /*!< STOP flag */
25883 #define PWR_CPUCR_SBF_Pos               (9U)
25884 #define PWR_CPUCR_SBF_Msk               (0x1UL << PWR_CPUCR_SBF_Pos)            /*!< 0x00000200 */
25885 #define PWR_CPUCR_SBF                   PWR_CPUCR_SBF_Msk                       /*!< System Standby flag */
25886 #define PWR_CPUCR_SVOS_Pos              (16U)
25887 #define PWR_CPUCR_SVOS_Msk              (0x1UL << PWR_CPUCR_SVOS_Pos)           /*!< 0x00010000 */
25888 #define PWR_CPUCR_SVOS                  PWR_CPUCR_SVOS_Msk                      /*!< System Stop mode voltage scaling selection */
25889 
25890 /******************  Bit definition for PWR_SVMCR1 register  ******************/
25891 #define PWR_SVMCR1_VDDIO4VMEN_Pos       (0U)
25892 #define PWR_SVMCR1_VDDIO4VMEN_Msk       (0x1UL << PWR_SVMCR1_VDDIO4VMEN_Pos)    /*!< 0x00000001 */
25893 #define PWR_SVMCR1_VDDIO4VMEN           PWR_SVMCR1_VDDIO4VMEN_Msk               /*!< VDDOI4 Independent I/Os voltage monitor enable */
25894 #define PWR_SVMCR1_VDDIO4SV_Pos         (8U)
25895 #define PWR_SVMCR1_VDDIO4SV_Msk         (0x1UL << PWR_SVMCR1_VDDIO4SV_Pos)      /*!< 0x00000100 */
25896 #define PWR_SVMCR1_VDDIO4SV             PWR_SVMCR1_VDDIO4SV_Msk                 /*!< VDDIO4 Independent I/Os supply valid */
25897 #define PWR_SVMCR1_VDDIO4RDY_Pos        (16U)
25898 #define PWR_SVMCR1_VDDIO4RDY_Msk        (0x1UL << PWR_SVMCR1_VDDIO4RDY_Pos)     /*!< 0x00010000 */
25899 #define PWR_SVMCR1_VDDIO4RDY            PWR_SVMCR1_VDDIO4RDY_Msk                /*!< VDDIO4 ready */
25900 #define PWR_SVMCR1_VDDIO4VRSEL_Pos      (24U)
25901 #define PWR_SVMCR1_VDDIO4VRSEL_Msk      (0x1UL << PWR_SVMCR1_VDDIO4VRSEL_Pos)   /*!< 0x01000000 */
25902 #define PWR_SVMCR1_VDDIO4VRSEL          PWR_SVMCR1_VDDIO4VRSEL_Msk              /*!< VDDIO4 IO voltage range selection */
25903 #define PWR_SVMCR1_VDDIO4VRSTBY_Pos     (25U)
25904 #define PWR_SVMCR1_VDDIO4VRSTBY_Msk     (0x1UL << PWR_SVMCR1_VDDIO4VRSTBY_Pos)  /*!< 0x04000000 */
25905 #define PWR_SVMCR1_VDDIO4VRSTBY         PWR_SVMCR1_VDDIO4VRSTBY_Msk             /*!< VDDIO4 IO voltage range standby mode */
25906 
25907 /******************  Bit definition for PWR_SVMCR2 register  ******************/
25908 #define PWR_SVMCR2_VDDIO5VMEN_Pos       (0U)
25909 #define PWR_SVMCR2_VDDIO5VMEN_Msk       (0x1UL << PWR_SVMCR2_VDDIO5VMEN_Pos)    /*!< 0x00000001 */
25910 #define PWR_SVMCR2_VDDIO5VMEN           PWR_SVMCR2_VDDIO5VMEN_Msk               /*!< VDDIO5 Independent voltage monitor enable */
25911 #define PWR_SVMCR2_VDDIO5SV_Pos         (8U)
25912 #define PWR_SVMCR2_VDDIO5SV_Msk         (0x1UL << PWR_SVMCR2_VDDIO5SV_Pos)      /*!< 0x00000100 */
25913 #define PWR_SVMCR2_VDDIO5SV             PWR_SVMCR2_VDDIO5SV_Msk                 /*!< VDDIO5 Independent supply valid */
25914 #define PWR_SVMCR2_VDDIO5RDY_Pos        (16U)
25915 #define PWR_SVMCR2_VDDIO5RDY_Msk        (0x1UL << PWR_SVMCR2_VDDIO5RDY_Pos)     /*!< 0x00010000 */
25916 #define PWR_SVMCR2_VDDIO5RDY            PWR_SVMCR2_VDDIO5RDY_Msk                /*!< VDDIO5 ready */
25917 #define PWR_SVMCR2_VDDIO5VRSEL_Pos      (24U)
25918 #define PWR_SVMCR2_VDDIO5VRSEL_Msk      (0x1UL << PWR_SVMCR2_VDDIO5VRSEL_Pos)   /*!< 0x01000000 */
25919 #define PWR_SVMCR2_VDDIO5VRSEL          PWR_SVMCR2_VDDIO5VRSEL_Msk              /*!< VDDIO5 IO voltage range selection */
25920 #define PWR_SVMCR2_VDDIO5VRSTBY_Pos     (25U)
25921 #define PWR_SVMCR2_VDDIO5VRSTBY_Msk     (0x1UL << PWR_SVMCR2_VDDIO5VRSTBY_Pos)  /*!< 0x02000000 */
25922 #define PWR_SVMCR2_VDDIO5VRSTBY         PWR_SVMCR2_VDDIO5VRSTBY_Msk             /*!< VDDIO5 IO voltage range standby mode */
25923 
25924 /******************  Bit definition for PWR_SVMCR3 register  ******************/
25925 #define PWR_SVMCR3_VDDIO2VMEN_Pos       (0U)
25926 #define PWR_SVMCR3_VDDIO2VMEN_Msk       (0x1UL << PWR_SVMCR3_VDDIO2VMEN_Pos)    /*!< 0x00000001 */
25927 #define PWR_SVMCR3_VDDIO2VMEN           PWR_SVMCR3_VDDIO2VMEN_Msk               /*!< VDDIO2 Independent voltage monitor enable */
25928 #define PWR_SVMCR3_VDDIO3VMEN_Pos       (1U)
25929 #define PWR_SVMCR3_VDDIO3VMEN_Msk       (0x1UL << PWR_SVMCR3_VDDIO3VMEN_Pos)    /*!< 0x00000002 */
25930 #define PWR_SVMCR3_VDDIO3VMEN           PWR_SVMCR3_VDDIO3VMEN_Msk               /*!< VDDIO3 Independent voltage monitor enable */
25931 #define PWR_SVMCR3_USB33VMEN_Pos        (2U)
25932 #define PWR_SVMCR3_USB33VMEN_Msk        (0x1UL << PWR_SVMCR3_USB33VMEN_Pos)     /*!< 0x00000004 */
25933 #define PWR_SVMCR3_USB33VMEN            PWR_SVMCR3_USB33VMEN_Msk                /*!< VDD33USB Independent USB 33 voltage monitor enable */
25934 #define PWR_SVMCR3_AVMEN_Pos            (4U)
25935 #define PWR_SVMCR3_AVMEN_Msk            (0x1UL << PWR_SVMCR3_AVMEN_Pos)         /*!< 0x00000010 */
25936 #define PWR_SVMCR3_AVMEN                PWR_SVMCR3_AVMEN_Msk                    /*!< VDDA18ADC Independent ADC voltage monitor enable */
25937 #define PWR_SVMCR3_VDDIO2SV_Pos         (8U)
25938 #define PWR_SVMCR3_VDDIO2SV_Msk         (0x1UL << PWR_SVMCR3_VDDIO2SV_Pos)      /*!< 0x00000100 */
25939 #define PWR_SVMCR3_VDDIO2SV             PWR_SVMCR3_VDDIO2SV_Msk                 /*!< VDDIO2 Independent supply valid */
25940 #define PWR_SVMCR3_VDDIO3SV_Pos         (9U)
25941 #define PWR_SVMCR3_VDDIO3SV_Msk         (0x1UL << PWR_SVMCR3_VDDIO3SV_Pos)      /*!< 0x00000200 */
25942 #define PWR_SVMCR3_VDDIO3SV             PWR_SVMCR3_VDDIO3SV_Msk                 /*!< VDDIO3 Independent supply valid */
25943 #define PWR_SVMCR3_USB33SV_Pos          (10U)
25944 #define PWR_SVMCR3_USB33SV_Msk          (0x1UL << PWR_SVMCR3_USB33SV_Pos)       /*!< 0x00000400 */
25945 #define PWR_SVMCR3_USB33SV              PWR_SVMCR3_USB33SV_Msk                  /*!< VDD33USB Independent supply valid */
25946 #define PWR_SVMCR3_ASV_Pos              (12U)
25947 #define PWR_SVMCR3_ASV_Msk              (0x1UL << PWR_SVMCR3_ASV_Pos)           /*!< 0x00001000 */
25948 #define PWR_SVMCR3_ASV                  PWR_SVMCR3_ASV_Msk                      /*!< VDDA18ADC Independent supply valid */
25949 #define PWR_SVMCR3_VDDIO2RDY_Pos        (16U)
25950 #define PWR_SVMCR3_VDDIO2RDY_Msk        (0x1UL << PWR_SVMCR3_VDDIO2RDY_Pos)     /*!< 0x00010000 */
25951 #define PWR_SVMCR3_VDDIO2RDY            PWR_SVMCR3_VDDIO2RDY_Msk                /*!< VDDIO2 ready */
25952 #define PWR_SVMCR3_VDDIO3RDY_Pos        (17U)
25953 #define PWR_SVMCR3_VDDIO3RDY_Msk        (0x1UL << PWR_SVMCR3_VDDIO3RDY_Pos)     /*!< 0x00020000 */
25954 #define PWR_SVMCR3_VDDIO3RDY            PWR_SVMCR3_VDDIO3RDY_Msk                /*!< VDDIO3 ready */
25955 #define PWR_SVMCR3_USB33RDY_Pos         (18U)
25956 #define PWR_SVMCR3_USB33RDY_Msk         (0x1UL << PWR_SVMCR3_USB33RDY_Pos)      /*!< 0x00040000 */
25957 #define PWR_SVMCR3_USB33RDY             PWR_SVMCR3_USB33RDY_Msk                 /*!< VDD33USB ready */
25958 #define PWR_SVMCR3_ARDY_Pos             (20U)
25959 #define PWR_SVMCR3_ARDY_Msk             (0x1UL << PWR_SVMCR3_ARDY_Pos)          /*!< 0x00100000 */
25960 #define PWR_SVMCR3_ARDY                 PWR_SVMCR3_ARDY_Msk                     /*!< VDDA18ADC ready */
25961 #define PWR_SVMCR3_VDDIOVRSEL_Pos       (24U)
25962 #define PWR_SVMCR3_VDDIOVRSEL_Msk       (0x1UL << PWR_SVMCR3_VDDIOVRSEL_Pos)    /*!< 0x01000000 */
25963 #define PWR_SVMCR3_VDDIOVRSEL           PWR_SVMCR3_VDDIOVRSEL_Msk               /*!< VDD IO voltage range selection */
25964 #define PWR_SVMCR3_VDDIO2VRSEL_Pos      (25U)
25965 #define PWR_SVMCR3_VDDIO2VRSEL_Msk      (0x1UL << PWR_SVMCR3_VDDIO2VRSEL_Pos)   /*!< 0x02000000 */
25966 #define PWR_SVMCR3_VDDIO2VRSEL          PWR_SVMCR3_VDDIO2VRSEL_Msk              /*!< VDDIO2 IO voltage range selection */
25967 #define PWR_SVMCR3_VDDIO3VRSEL_Pos      (26U)
25968 #define PWR_SVMCR3_VDDIO3VRSEL_Msk      (0x1UL << PWR_SVMCR3_VDDIO3VRSEL_Pos)   /*!< 0x04000000 */
25969 #define PWR_SVMCR3_VDDIO3VRSEL          PWR_SVMCR3_VDDIO3VRSEL_Msk              /*!< VDDIO3 IO voltage range selection */
25970 
25971 /*****************  Bit definition for PWR_WKUPCR register  *******************/
25972 #define PWR_WKUPCR_WKUPC1_Pos          (0U)
25973 #define PWR_WKUPCR_WKUPC1_Msk          (0x1UL << PWR_WKUPCR_WKUPC1_Pos)         /*!< 0x00000001 */
25974 #define PWR_WKUPCR_WKUPC1              PWR_WKUPCR_WKUPC1_Msk                    /*!< Clear Wakeup Flag for WKUP1 pin */
25975 #define PWR_WKUPCR_WKUPC2_Pos          (1U)
25976 #define PWR_WKUPCR_WKUPC2_Msk          (0x1UL << PWR_WKUPCR_WKUPC2_Pos)         /*!< 0x00000002 */
25977 #define PWR_WKUPCR_WKUPC2              PWR_WKUPCR_WKUPC2_Msk                    /*!< Clear Wakeup Flag for WKUP2 pin */
25978 #define PWR_WKUPCR_WKUPC3_Pos          (2U)
25979 #define PWR_WKUPCR_WKUPC3_Msk          (0x1UL << PWR_WKUPCR_WKUPC3_Pos)         /*!< 0x00000004 */
25980 #define PWR_WKUPCR_WKUPC3              PWR_WKUPCR_WKUPC3_Msk                    /*!< Clear Wakeup Flag for WKUP3 pin */
25981 #define PWR_WKUPCR_WKUPC4_Pos          (3U)
25982 #define PWR_WKUPCR_WKUPC4_Msk          (0x1UL << PWR_WKUPCR_WKUPC4_Pos)         /*!< 0x00000008 */
25983 #define PWR_WKUPCR_WKUPC4              PWR_WKUPCR_WKUPC4_Msk                    /*!< Clear Wakeup Flag for WKUP4 pin */
25984 #define PWR_WKUPCR_WKUPC_Pos           (0U)
25985 #define PWR_WKUPCR_WKUPC_Msk           (0xFUL << PWR_WKUPCR_WKUPC_Pos)         /*!< 0x0000000F */
25986 #define PWR_WKUPCR_WKUPC               PWR_WKUPCR_WKUPC_Msk                    /*!< Clear Wakeup Flag 1 to 4 */
25987 
25988 /*****************  Bit definition for PWR_WKUPSR register  *******************/
25989 #define PWR_WKUPSR_WKUPF1_Pos          (0U)
25990 #define PWR_WKUPSR_WKUPF1_Msk          (0x1UL << PWR_WKUPSR_WKUPF1_Pos)         /*!< 0x00000001 */
25991 #define PWR_WKUPSR_WKUPF1              PWR_WKUPSR_WKUPF1_Msk                    /*!< Wakeup Flag for WKUP1 pin */
25992 #define PWR_WKUPSR_WKUPF2_Pos          (1U)
25993 #define PWR_WKUPSR_WKUPF2_Msk          (0x1UL << PWR_WKUPSR_WKUPF2_Pos)         /*!< 0x00000002 */
25994 #define PWR_WKUPSR_WKUPF2              PWR_WKUPSR_WKUPF2_Msk                    /*!< Wakeup Flag for WKUP2 pin */
25995 #define PWR_WKUPSR_WKUPF3_Pos          (2U)
25996 #define PWR_WKUPSR_WKUPF3_Msk          (0x1UL << PWR_WKUPSR_WKUPF3_Pos)         /*!< 0x00000004 */
25997 #define PWR_WKUPSR_WKUPF3              PWR_WKUPSR_WKUPF3_Msk                    /*!< Wakeup Flag for WKUP3 pin */
25998 #define PWR_WKUPSR_WKUPF4_Pos          (3U)
25999 #define PWR_WKUPSR_WKUPF4_Msk          (0x1UL << PWR_WKUPSR_WKUPF4_Pos)         /*!< 0x00000008 */
26000 #define PWR_WKUPSR_WKUPF4              PWR_WKUPSR_WKUPF4_Msk                    /*!< Wakeup Flag for WKUP4 pin */
26001 
26002 /*****************  Bit definition for PWR_WKUPEPR register  *******************/
26003 #define PWR_WKUPEPR_WKUPEN1_Pos        (0U)
26004 #define PWR_WKUPEPR_WKUPEN1_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos)       /*!< 0x00000001 */
26005 #define PWR_WKUPEPR_WKUPEN1            PWR_WKUPEPR_WKUPEN1_Msk                  /*!< Enable Wakeup pin WKUP1 */
26006 #define PWR_WKUPEPR_WKUPEN2_Pos        (1U)
26007 #define PWR_WKUPEPR_WKUPEN2_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos)       /*!< 0x00000002 */
26008 #define PWR_WKUPEPR_WKUPEN2            PWR_WKUPEPR_WKUPEN2_Msk                  /*!< Enable Wakeup pin WKUP2 */
26009 #define PWR_WKUPEPR_WKUPEN3_Pos        (2U)
26010 #define PWR_WKUPEPR_WKUPEN3_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos)       /*!< 0x00000004 */
26011 #define PWR_WKUPEPR_WKUPEN3            PWR_WKUPEPR_WKUPEN3_Msk                  /*!< Enable Wakeup pin WKUP3 */
26012 #define PWR_WKUPEPR_WKUPEN4_Pos        (3U)
26013 #define PWR_WKUPEPR_WKUPEN4_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos)       /*!< 0x00000008 */
26014 #define PWR_WKUPEPR_WKUPEN4            PWR_WKUPEPR_WKUPEN4_Msk                  /*!< Enable Wakeup pin WKUP4 */
26015 #define PWR_WKUPEPR_WKUPP1_Pos         (8U)
26016 #define PWR_WKUPEPR_WKUPP1_Msk         (0x1UL << PWR_WKUPEPR_WKUPP1_Pos)        /*!< 0x00000100 */
26017 #define PWR_WKUPEPR_WKUPP1             PWR_WKUPEPR_WKUPP1_Msk                   /*!< Wakeup Polarity bit for WKUP1 pin */
26018 #define PWR_WKUPEPR_WKUPP2_Pos         (9U)
26019 #define PWR_WKUPEPR_WKUPP2_Msk         (0x1UL << PWR_WKUPEPR_WKUPP2_Pos)        /*!< 0x00000200 */
26020 #define PWR_WKUPEPR_WKUPP2             PWR_WKUPEPR_WKUPP2_Msk                   /*!< Wakeup Polarity bit for WKUP2 pin */
26021 #define PWR_WKUPEPR_WKUPP3_Pos         (10U)
26022 #define PWR_WKUPEPR_WKUPP3_Msk         (0x1UL << PWR_WKUPEPR_WKUPP3_Pos)        /*!< 0x00000400 */
26023 #define PWR_WKUPEPR_WKUPP3             PWR_WKUPEPR_WKUPP3_Msk                   /*!< Wakeup Polarity bit for WKUP3 pin */
26024 #define PWR_WKUPEPR_WKUPP4_Pos         (11U)
26025 #define PWR_WKUPEPR_WKUPP4_Msk         (0x1UL << PWR_WKUPEPR_WKUPP4_Pos)        /*!< 0x00000800 */
26026 #define PWR_WKUPEPR_WKUPP4             PWR_WKUPEPR_WKUPP4_Msk                   /*!< Wakeup Polarity bit for WKUP4 pin */
26027 #define PWR_WKUPEPR_WKUPP_Pos          (8U)
26028 #define PWR_WKUPEPR_WKUPP_Msk          (0x0FUL << PWR_WKUPEPR_WKUPP_Pos)        /*!< 0x0000300F */
26029 #define PWR_WKUPEPR_WKUPP              PWR_WKUPEPR_WKUPP_Msk                    /*!< Wakeup Pin Polarity for WKUP1 to WKUP4 */
26030 #define PWR_WKUPEPR_WKUPPUPD1_Pos      (16U)
26031 #define PWR_WKUPEPR_WKUPPUPD1_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos)     /*!< 0x00030000 */
26032 #define PWR_WKUPEPR_WKUPPUPD1          PWR_WKUPEPR_WKUPPUPD1_Msk                /*!< Wakeup pull configuration for WKUP1 pin */
26033 #define PWR_WKUPEPR_WKUPPUPD1_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos)     /*!< 0x00010000 */
26034 #define PWR_WKUPEPR_WKUPPUPD1_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos)     /*!< 0x00020000 */
26035 #define PWR_WKUPEPR_WKUPPUPD2_Pos      (18U)
26036 #define PWR_WKUPEPR_WKUPPUPD2_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos)     /*!< 0x000C0000 */
26037 #define PWR_WKUPEPR_WKUPPUPD2          PWR_WKUPEPR_WKUPPUPD2_Msk                /*!< Wakeup pull configuration for WKUP2 pin */
26038 #define PWR_WKUPEPR_WKUPPUPD2_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos)     /*!< 0x00040000 */
26039 #define PWR_WKUPEPR_WKUPPUPD2_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos)     /*!< 0x00080000 */
26040 #define PWR_WKUPEPR_WKUPPUPD3_Pos      (20U)
26041 #define PWR_WKUPEPR_WKUPPUPD3_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos)     /*!< 0x00300000 */
26042 #define PWR_WKUPEPR_WKUPPUPD3          PWR_WKUPEPR_WKUPPUPD3_Msk                /*!< Wakeup pull configuration for WKUP3 pin */
26043 #define PWR_WKUPEPR_WKUPPUPD3_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos)     /*!< 0x00100000 */
26044 #define PWR_WKUPEPR_WKUPPUPD3_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos)     /*!< 0x00200000 */
26045 #define PWR_WKUPEPR_WKUPPUPD4_Pos      (22U)
26046 #define PWR_WKUPEPR_WKUPPUPD4_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos)     /*!< 0x00C00000 */
26047 #define PWR_WKUPEPR_WKUPPUPD4          PWR_WKUPEPR_WKUPPUPD4_Msk                /*!< Wakeup pull configuration for WKUP4 pin */
26048 #define PWR_WKUPEPR_WKUPPUPD4_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos)     /*!< 0x00400000 */
26049 #define PWR_WKUPEPR_WKUPPUPD4_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos)     /*!< 0x00800000 */
26050 #define PWR_WKUPEPR_WKUPEN_Pos         (0U)
26051 #define PWR_WKUPEPR_WKUPEN_Msk         (0x0FUL << PWR_WKUPEPR_WKUPEN_Pos)       /*!< 0x0000003F */
26052 #define PWR_WKUPEPR_WKUPEN             PWR_WKUPEPR_WKUPEN_Msk                   /*!< Enable all Wakeup Pin */
26053 
26054 /*****************  Bit definition for PWR_SECCFGR register  ******************/
26055 #define PWR_SECCFGR_SEC0_Pos            (0U)
26056 #define PWR_SECCFGR_SEC0_Msk            (0x1UL << PWR_SECCFGR_SEC0_Pos)         /*!< 0x00000001 */
26057 #define PWR_SECCFGR_SEC0                PWR_SECCFGR_SEC0_Msk                    /*!< System supply configuration secure protection */
26058 #define PWR_SECCFGR_SEC1_Pos            (1U)
26059 #define PWR_SECCFGR_SEC1_Msk            (0x1UL << PWR_SECCFGR_SEC1_Pos)         /*!< 0x00000002 */
26060 #define PWR_SECCFGR_SEC1                PWR_SECCFGR_SEC1_Msk                    /*!< Programmable voltage detector secure protection */
26061 #define PWR_SECCFGR_SEC2_Pos            (2U)
26062 #define PWR_SECCFGR_SEC2_Msk            (0x1UL << PWR_SECCFGR_SEC2_Pos)         /*!< 0x00000004 */
26063 #define PWR_SECCFGR_SEC2                PWR_SECCFGR_SEC2_Msk                    /*!< VDDCORE monitor secure protection */
26064 #define PWR_SECCFGR_SEC3_Pos            (3U)
26065 #define PWR_SECCFGR_SEC3_Msk            (0x1UL << PWR_SECCFGR_SEC3_Pos)         /*!< 0x00000008 */
26066 #define PWR_SECCFGR_SEC3                PWR_SECCFGR_SEC3_Msk                    /*!< I-TCM/D-TCM and I-TCM FLEX MEM low power control secure protection */
26067 #define PWR_SECCFGR_SEC4_Pos            (4U)
26068 #define PWR_SECCFGR_SEC4_Msk            (0x1UL << PWR_SECCFGR_SEC4_Pos)         /*!< 0x00000010 */
26069 #define PWR_SECCFGR_SEC4                PWR_SECCFGR_SEC4_Msk                    /*!< Voltage scaling selection secure protection */
26070 #define PWR_SECCFGR_SEC5_Pos            (5U)
26071 #define PWR_SECCFGR_SEC5_Msk            (0x1UL << PWR_SECCFGR_SEC5_Pos)         /*!< 0x00000020 */
26072 #define PWR_SECCFGR_SEC5                PWR_SECCFGR_SEC5_Msk                    /*!< Backup domain secure protection */
26073 #define PWR_SECCFGR_SEC6_Pos            (6U)
26074 #define PWR_SECCFGR_SEC6_Msk            (0x1UL << PWR_SECCFGR_SEC6_Pos)         /*!< 0x00000040 */
26075 #define PWR_SECCFGR_SEC6                PWR_SECCFGR_SEC6_Msk                    /*!< CPU power control secure protection */
26076 #define PWR_SECCFGR_SEC7_Pos            (7U)
26077 #define PWR_SECCFGR_SEC7_Msk            (0x1UL << PWR_SECCFGR_SEC7_Pos)         /*!< 0x00000080 */
26078 #define PWR_SECCFGR_SEC7                PWR_SECCFGR_SEC7_Msk                    /*!< Peripheral voltage monitor secure protection */
26079 #define PWR_SECCFGR_WKUPSEC1_Pos        (16U)
26080 #define PWR_SECCFGR_WKUPSEC1_Msk        (0x1UL << PWR_SECCFGR_WKUPSEC1_Pos)     /*!< 0x00010000 */
26081 #define PWR_SECCFGR_WKUPSEC1            PWR_SECCFGR_WKUPSEC1_Msk                /*!< WKUP1 secure protection */
26082 #define PWR_SECCFGR_WKUPSEC2_Pos        (17U)
26083 #define PWR_SECCFGR_WKUPSEC2_Msk        (0x1UL << PWR_SECCFGR_WKUPSEC2_Pos)     /*!< 0x00020000 */
26084 #define PWR_SECCFGR_WKUPSEC2            PWR_SECCFGR_WKUPSEC2_Msk                /*!< WKUP2 secure protection */
26085 #define PWR_SECCFGR_WKUPSEC3_Pos        (18U)
26086 #define PWR_SECCFGR_WKUPSEC3_Msk        (0x1UL << PWR_SECCFGR_WKUPSEC3_Pos)     /*!< 0x00040000 */
26087 #define PWR_SECCFGR_WKUPSEC3            PWR_SECCFGR_WKUPSEC3_Msk                /*!< WKUP3 secure protection */
26088 #define PWR_SECCFGR_WKUPSEC4_Pos        (19U)
26089 #define PWR_SECCFGR_WKUPSEC4_Msk        (0x1UL << PWR_SECCFGR_WKUPSEC4_Pos)     /*!< 0x00080000 */
26090 #define PWR_SECCFGR_WKUPSEC4            PWR_SECCFGR_WKUPSEC4_Msk                /*!< WKUP4 secure protection */
26091 
26092 /*****************  Bit definition for PWR_PRIVCFGR register  *****************/
26093 #define PWR_PRIVCFGR_PRIV0_Pos          (0U)
26094 #define PWR_PRIVCFGR_PRIV0_Msk          (0x1UL << PWR_PRIVCFGR_PRIV0_Pos)       /*!< 0x00000001 */
26095 #define PWR_PRIVCFGR_PRIV0              PWR_PRIVCFGR_PRIV0_Msk                  /*!< System supply configuration privileged protection */
26096 #define PWR_PRIVCFGR_PRIV1_Pos          (1U)
26097 #define PWR_PRIVCFGR_PRIV1_Msk          (0x1UL << PWR_PRIVCFGR_PRIV1_Pos)       /*!< 0x00000002 */
26098 #define PWR_PRIVCFGR_PRIV1              PWR_PRIVCFGR_PRIV1_Msk                  /*!< Programmable voltage detector privileged protection */
26099 #define PWR_PRIVCFGR_PRIV2_Pos          (2U)
26100 #define PWR_PRIVCFGR_PRIV2_Msk          (0x1UL << PWR_PRIVCFGR_PRIV2_Pos)       /*!< 0x00000004 */
26101 #define PWR_PRIVCFGR_PRIV2              PWR_PRIVCFGR_PRIV2_Msk                  /*!< VDDCORE monitor privileged protection */
26102 #define PWR_PRIVCFGR_PRIV3_Pos          (3U)
26103 #define PWR_PRIVCFGR_PRIV3_Msk          (0x1UL << PWR_PRIVCFGR_PRIV3_Pos)       /*!< 0x00000008 */
26104 #define PWR_PRIVCFGR_PRIV3              PWR_PRIVCFGR_PRIV3_Msk                  /*!< I-TCM/D-TCM and I-TCM FLEX MEM low power control privileged protection */
26105 #define PWR_PRIVCFGR_PRIV4_Pos          (4U)
26106 #define PWR_PRIVCFGR_PRIV4_Msk          (0x1UL << PWR_PRIVCFGR_PRIV4_Pos)       /*!< 0x00000010 */
26107 #define PWR_PRIVCFGR_PRIV4              PWR_PRIVCFGR_PRIV4_Msk                  /*!< Voltage scaling selection privileged protection */
26108 #define PWR_PRIVCFGR_PRIV5_Pos          (5U)
26109 #define PWR_PRIVCFGR_PRIV5_Msk          (0x1UL << PWR_PRIVCFGR_PRIV5_Pos)       /*!< 0x00000020 */
26110 #define PWR_PRIVCFGR_PRIV5              PWR_PRIVCFGR_PRIV5_Msk                  /*!< Backup domain privileged protection */
26111 #define PWR_PRIVCFGR_PRIV6_Pos          (6U)
26112 #define PWR_PRIVCFGR_PRIV6_Msk          (0x1UL << PWR_PRIVCFGR_PRIV6_Pos)       /*!< 0x00000040 */
26113 #define PWR_PRIVCFGR_PRIV6              PWR_PRIVCFGR_PRIV6_Msk                  /*!< CPU power control privileged protection */
26114 #define PWR_PRIVCFGR_PRIV7_Pos          (7U)
26115 #define PWR_PRIVCFGR_PRIV7_Msk          (0x1UL << PWR_PRIVCFGR_PRIV7_Pos)       /*!< 0x00000080 */
26116 #define PWR_PRIVCFGR_PRIV7              PWR_PRIVCFGR_PRIV7_Msk                  /*!< Peripheral voltage monitor privileged protection */
26117 #define PWR_PRIVCFGR_WKUPPRIV1_Pos      (16U)
26118 #define PWR_PRIVCFGR_WKUPPRIV1_Msk      (0x1UL << PWR_PRIVCFGR_WKUPPRIV1_Pos)   /*!< 0x00010000 */
26119 #define PWR_PRIVCFGR_WKUPPRIV1          PWR_PRIVCFGR_WKUPPRIV1_Msk              /*!< WKUP1 privileged protection */
26120 #define PWR_PRIVCFGR_WKUPPRIV2_Pos      (17U)
26121 #define PWR_PRIVCFGR_WKUPPRIV2_Msk      (0x1UL << PWR_PRIVCFGR_WKUPPRIV2_Pos)   /*!< 0x00020000 */
26122 #define PWR_PRIVCFGR_WKUPPRIV2          PWR_PRIVCFGR_WKUPPRIV2_Msk              /*!< WKUP2 privileged protection */
26123 #define PWR_PRIVCFGR_WKUPPRIV3_Pos      (18U)
26124 #define PWR_PRIVCFGR_WKUPPRIV3_Msk      (0x1UL << PWR_PRIVCFGR_WKUPPRIV3_Pos)   /*!< 0x00040000 */
26125 #define PWR_PRIVCFGR_WKUPPRIV3          PWR_PRIVCFGR_WKUPPRIV3_Msk              /*!< WKUP3 privileged protection */
26126 #define PWR_PRIVCFGR_WKUPPRIV4_Pos      (19U)
26127 #define PWR_PRIVCFGR_WKUPPRIV4_Msk      (0x1UL << PWR_PRIVCFGR_WKUPPRIV4_Pos)   /*!< 0x00080000 */
26128 #define PWR_PRIVCFGR_WKUPPRIV4          PWR_PRIVCFGR_WKUPPRIV4_Msk              /*!< WKUP4 privileged protection */
26129 
26130 
26131 /******************************************************************************/
26132 /*                                                                            */
26133 /*                       RAMs configuration controller                        */
26134 /*                                                                            */
26135 /******************************************************************************/
26136 /*******************  Bit definition for RAMCFG_CR register  ******************/
26137 #define RAMCFG_CR_ECCE_Pos              (0U)
26138 #define RAMCFG_CR_ECCE_Msk              (0x1UL << RAMCFG_CR_ECCE_Pos)          /*!< 0x00000001 */
26139 #define RAMCFG_CR_ECCE                  RAMCFG_CR_ECCE_Msk                     /*!< ECC Enable */
26140 #define RAMCFG_CR_ALE_Pos               (4U)
26141 #define RAMCFG_CR_ALE_Msk               (0x1UL << RAMCFG_CR_ALE_Pos)           /*!< 0x00000010 */
26142 #define RAMCFG_CR_ALE                   RAMCFG_CR_ALE_Msk                      /*!< Address Latching Enable */
26143 #define RAMCFG_CR_SRAMER_Pos            (8U)
26144 #define RAMCFG_CR_SRAMER_Msk            (0x1UL << RAMCFG_CR_SRAMER_Pos)        /*!< 0x00000100 */
26145 #define RAMCFG_CR_SRAMER                RAMCFG_CR_SRAMER_Msk                   /*!< Start Erase */
26146 #define RAMCFG_CR_SRAMHWERDIS_Pos       (12U)
26147 #define RAMCFG_CR_SRAMHWERDIS_Msk       (0x1UL << RAMCFG_CR_SRAMHWERDIS_Pos)   /*!< 0x00001000 */
26148 #define RAMCFG_CR_SRAMHWERDIS           RAMCFG_CR_SRAMHWERDIS_Msk              /*!< SRAM hardware erase disable */
26149 #define RAMCFG_CR_ITCMCFG_Pos           (16U)
26150 #define RAMCFG_CR_ITCMCFG_Msk           (0x3UL << RAMCFG_CR_ITCMCFG_Pos)       /*!< 0x00030000 */
26151 #define RAMCFG_CR_ITCMCFG               RAMCFG_CR_ITCMCFG_Msk                  /*!< Configuration of the FLEXMEM D-TCM extension */
26152 #define RAMCFG_CR_ITCMCFG_0             (0x1UL << RAMCFG_CR_ITCMCFG_Pos)       /*!< 0x00010000 */
26153 #define RAMCFG_CR_ITCMCFG_1             (0x2UL << RAMCFG_CR_ITCMCFG_Pos)       /*!< 0x00020000 */
26154 #define RAMCFG_CR_SRAMSD_Pos            (20U)
26155 #define RAMCFG_CR_SRAMSD_Msk            (0x1UL << RAMCFG_CR_SRAMSD_Pos)        /*!< 0x00100000 */
26156 #define RAMCFG_CR_SRAMSD                RAMCFG_CR_SRAMSD_Msk                   /*!< Shutdown AXISRAMx */
26157 #define RAMCFG_CR_DTCMCFG_Pos           (24U)
26158 #define RAMCFG_CR_DTCMCFG_Msk           (0x1UL << RAMCFG_CR_DTCMCFG_Pos)       /*!< 0x01000000 */
26159 #define RAMCFG_CR_DTCMCFG               RAMCFG_CR_DTCMCFG_Msk                  /*!< Configuration of the FLEXMEM D-TCM extension */
26160 
26161 /*******************  Bit definition for RAMCFG_IER register  *****************/
26162 #define RAMCFG_IER_SEIE_Pos             (0U)
26163 #define RAMCFG_IER_SEIE_Msk             (0x1UL << RAMCFG_IER_SEIE_Pos)         /*!< 0x00000001 */
26164 #define RAMCFG_IER_SEIE                 RAMCFG_IER_SEIE_Msk                    /*!< Single Error Interrupt Enable */
26165 #define RAMCFG_IER_DEIE_Pos             (1U)
26166 #define RAMCFG_IER_DEIE_Msk             (0x1UL << RAMCFG_IER_DEIE_Pos)         /*!< 0x00000002 */
26167 #define RAMCFG_IER_DEIE                 RAMCFG_IER_DEIE_Msk                    /*!< Double Error Interrupt Enable */
26168 
26169 /*******************  Bit definition for RAMCFG_ISR register  *****************/
26170 #define RAMCFG_ISR_SEDC_Pos             (0U)
26171 #define RAMCFG_ISR_SEDC_Msk             (0x1UL << RAMCFG_ISR_SEDC_Pos)         /*!< 0x00000001 */
26172 #define RAMCFG_ISR_SEDC                 RAMCFG_ISR_SEDC_Msk                    /*!< Single Error Detected and Corrected flag */
26173 #define RAMCFG_ISR_DED_Pos              (1U)
26174 #define RAMCFG_ISR_DED_Msk              (0x1UL << RAMCFG_ISR_DED_Pos)          /*!< 0x00000002 */
26175 #define RAMCFG_ISR_DED                  RAMCFG_ISR_DED_Msk                     /*!< Double Error Detected flag */
26176 #define RAMCFG_ISR_SRAMBUSY_Pos         (8U)
26177 #define RAMCFG_ISR_SRAMBUSY_Msk         (0x1UL << RAMCFG_ISR_SRAMBUSY_Pos)     /*!< 0x00000100 */
26178 #define RAMCFG_ISR_SRAMBUSY             RAMCFG_ISR_SRAMBUSY_Msk                /*!< SRAM busy flag */
26179 
26180 /*******************  Bit definition for RAMCFG_ESEAR register  ****************/
26181 #define RAMCFG_ESEAR_ESEA_Pos           (0U)
26182 #define RAMCFG_ESEAR_ESEA_Msk           (0x7FFUL << RAMCFG_ESEAR_ESEA_Pos)     /*!< 0x000007FF */
26183 #define RAMCFG_ESEAR_ESEA               RAMCFG_ESEAR_ESEA_Msk                  /*!< ECC Single Error Address */
26184 
26185 /*******************  Bit definition for RAMCFG_EDEAR register  ****************/
26186 #define RAMCFG_EDEAR_EDEA_Pos           (0U)
26187 #define RAMCFG_EDEAR_EDEA_Msk           (0x7FFUL << RAMCFG_EDEAR_EDEA_Pos)     /*!< 0x000007FF */
26188 #define RAMCFG_EDEAR_EDEA               RAMCFG_EDEAR_EDEA_Msk                  /*!< ECC Double Error Address */
26189 
26190 /*******************  Bit definition for RAMCFG_ICR register  *****************/
26191 #define RAMCFG_ICR_CSEDC_Pos            (0U)
26192 #define RAMCFG_ICR_CSEDC_Msk            (0x1UL << RAMCFG_ICR_CSEDC_Pos)        /*!< 0x00000001 */
26193 #define RAMCFG_ICR_CSEDC                RAMCFG_ICR_CSEDC_Msk                   /*!< Clear ECC Single Error Detected and Corrected Flag */
26194 #define RAMCFG_ICR_CDED_Pos             (1U)
26195 #define RAMCFG_ICR_CDED_Msk             (0x1UL << RAMCFG_ICR_CDED_Pos)         /*!< 0x00000002 */
26196 #define RAMCFG_ICR_CDED                 RAMCFG_ICR_CDED_Msk                    /*!< Clear ECC Double Error Detected Flag*/
26197 
26198 /*****************  Bit definition for RAMCFG_ECCKEYR register  ***************/
26199 #define RAMCFG_ECCKEYR_ECCKEY_Pos       (0U)
26200 #define RAMCFG_ECCKEYR_ECCKEY_Msk       (0xFFUL << RAMCFG_ECCKEYR_ECCKEY_Pos)  /*!< 0x000000FF */
26201 #define RAMCFG_ECCKEYR_ECCKEY           RAMCFG_ECCKEYR_ECCKEY_Msk              /*!< ECC Write Protection Key */
26202 
26203 /*****************  Bit definition for RAMCFG_ERKEYR register  ****************/
26204 #define RAMCFG_ERKEYR_ERASEKEY_Pos      (0U)
26205 #define RAMCFG_ERKEYR_ERASEKEY_Msk      (0xFFUL << RAMCFG_ERKEYR_ERASEKEY_Pos) /*!< 0x000000FF */
26206 #define RAMCFG_ERKEYR_ERASEKEY          RAMCFG_ERKEYR_ERASEKEY_Msk             /*!< Erase Write Protection Key */
26207 
26208 
26209 /******************************************************************************/
26210 /*                                                                            */
26211 /*                                    (RCC)                                   */
26212 /*                                                                            */
26213 /******************************************************************************/
26214 /********************  Bit definition for RCC_CR register  ********************/
26215 #define RCC_CR_LSION_Pos                        (0U)
26216 #define RCC_CR_LSION_Msk                        (0x1UL << RCC_CR_LSION_Pos)           /*!< 0x00000001 */
26217 #define RCC_CR_LSION                            RCC_CR_LSION_Msk                     /*!< LSI oscillator enable */
26218 #define RCC_CR_LSEON_Pos                        (1U)
26219 #define RCC_CR_LSEON_Msk                        (0x1UL << RCC_CR_LSEON_Pos)           /*!< 0x00000002 */
26220 #define RCC_CR_LSEON                            RCC_CR_LSEON_Msk                     /*!< LSE oscillator enable */
26221 #define RCC_CR_MSION_Pos                        (2U)
26222 #define RCC_CR_MSION_Msk                        (0x1UL << RCC_CR_MSION_Pos)           /*!< 0x00000004 */
26223 #define RCC_CR_MSION                            RCC_CR_MSION_Msk                     /*!< MSI oscillator enable */
26224 #define RCC_CR_HSION_Pos                        (3U)
26225 #define RCC_CR_HSION_Msk                        (0x1UL << RCC_CR_HSION_Pos)           /*!< 0x00000008 */
26226 #define RCC_CR_HSION                            RCC_CR_HSION_Msk                     /*!< HSI oscillator enable */
26227 #define RCC_CR_HSEON_Pos                        (4U)
26228 #define RCC_CR_HSEON_Msk                        (0x1UL << RCC_CR_HSEON_Pos)           /*!< 0x00000010 */
26229 #define RCC_CR_HSEON                            RCC_CR_HSEON_Msk                     /*!< HSE oscillator enable */
26230 #define RCC_CR_PLL1ON_Pos                       (8U)
26231 #define RCC_CR_PLL1ON_Msk                       (0x1UL << RCC_CR_PLL1ON_Pos)          /*!< 0x00000100 */
26232 #define RCC_CR_PLL1ON                           RCC_CR_PLL1ON_Msk                    /*!< PLL1 enable */
26233 #define RCC_CR_PLL2ON_Pos                       (9U)
26234 #define RCC_CR_PLL2ON_Msk                       (0x1UL << RCC_CR_PLL2ON_Pos)          /*!< 0x00000200 */
26235 #define RCC_CR_PLL2ON                           RCC_CR_PLL2ON_Msk                    /*!< PLL2 enable */
26236 #define RCC_CR_PLL3ON_Pos                       (10U)
26237 #define RCC_CR_PLL3ON_Msk                       (0x1UL << RCC_CR_PLL3ON_Pos)          /*!< 0x00000400 */
26238 #define RCC_CR_PLL3ON                           RCC_CR_PLL3ON_Msk                    /*!< PLL3 enable */
26239 #define RCC_CR_PLL4ON_Pos                       (11U)
26240 #define RCC_CR_PLL4ON_Msk                       (0x1UL << RCC_CR_PLL4ON_Pos)          /*!< 0x00000800 */
26241 #define RCC_CR_PLL4ON                           RCC_CR_PLL4ON_Msk                    /*!< PLL4 enable */
26242 
26243 /********************  Bit definition for RCC_SR register  ********************/
26244 #define RCC_SR_LSIRDY_Pos                       (0U)
26245 #define RCC_SR_LSIRDY_Msk                       (0x1UL << RCC_SR_LSIRDY_Pos)          /*!< 0x00000001 */
26246 #define RCC_SR_LSIRDY                           RCC_SR_LSIRDY_Msk                    /*!< LSI clock ready flag */
26247 #define RCC_SR_LSERDY_Pos                       (1U)
26248 #define RCC_SR_LSERDY_Msk                       (0x1UL << RCC_SR_LSERDY_Pos)          /*!< 0x00000002 */
26249 #define RCC_SR_LSERDY                           RCC_SR_LSERDY_Msk                    /*!< LSE clock ready flag */
26250 #define RCC_SR_MSIRDY_Pos                       (2U)
26251 #define RCC_SR_MSIRDY_Msk                       (0x1UL << RCC_SR_MSIRDY_Pos)          /*!< 0x00000004 */
26252 #define RCC_SR_MSIRDY                           RCC_SR_MSIRDY_Msk                    /*!< MSI clock ready flag */
26253 #define RCC_SR_HSIRDY_Pos                       (3U)
26254 #define RCC_SR_HSIRDY_Msk                       (0x1UL << RCC_SR_HSIRDY_Pos)          /*!< 0x00000008 */
26255 #define RCC_SR_HSIRDY                           RCC_SR_HSIRDY_Msk                    /*!< HSI clock ready flag */
26256 #define RCC_SR_HSERDY_Pos                       (4U)
26257 #define RCC_SR_HSERDY_Msk                       (0x1UL << RCC_SR_HSERDY_Pos)          /*!< 0x00000010 */
26258 #define RCC_SR_HSERDY                           RCC_SR_HSERDY_Msk                    /*!< HSE clock ready flag */
26259 #define RCC_SR_PLL1RDY_Pos                      (8U)
26260 #define RCC_SR_PLL1RDY_Msk                      (0x1UL << RCC_SR_PLL1RDY_Pos)         /*!< 0x00000100 */
26261 #define RCC_SR_PLL1RDY                          RCC_SR_PLL1RDY_Msk                   /*!< PLL1 clock ready flag */
26262 #define RCC_SR_PLL2RDY_Pos                      (9U)
26263 #define RCC_SR_PLL2RDY_Msk                      (0x1UL << RCC_SR_PLL2RDY_Pos)         /*!< 0x00000200 */
26264 #define RCC_SR_PLL2RDY                          RCC_SR_PLL2RDY_Msk                   /*!< PLL2 clock ready flag */
26265 #define RCC_SR_PLL3RDY_Pos                      (10U)
26266 #define RCC_SR_PLL3RDY_Msk                      (0x1UL << RCC_SR_PLL3RDY_Pos)         /*!< 0x00000400 */
26267 #define RCC_SR_PLL3RDY                          RCC_SR_PLL3RDY_Msk                   /*!< PLL3 clock ready flag */
26268 #define RCC_SR_PLL4RDY_Pos                      (11U)
26269 #define RCC_SR_PLL4RDY_Msk                      (0x1UL << RCC_SR_PLL4RDY_Pos)         /*!< 0x00000800 */
26270 #define RCC_SR_PLL4RDY                          RCC_SR_PLL4RDY_Msk                   /*!< PLL4 clock ready flag */
26271 
26272 /******************  Bit definition for RCC_STOPCR register  ******************/
26273 #define RCC_STOPCR_MSISTOPEN_Pos                (0U)
26274 #define RCC_STOPCR_MSISTOPEN_Msk                (0x1UL << RCC_STOPCR_MSISTOPEN_Pos)   /*!< 0x00000001 */
26275 #define RCC_STOPCR_MSISTOPEN                    RCC_STOPCR_MSISTOPEN_Msk             /*!< MSI oscillator enable */
26276 #define RCC_STOPCR_HSISTOPEN_Pos                (1U)
26277 #define RCC_STOPCR_HSISTOPEN_Msk                (0x1UL << RCC_STOPCR_HSISTOPEN_Pos)   /*!< 0x00000002 */
26278 #define RCC_STOPCR_HSISTOPEN                    RCC_STOPCR_HSISTOPEN_Msk             /*!< HSI oscillator enable */
26279 
26280 /******************  Bit definition for RCC_CFGR1 register  *******************/
26281 #define RCC_CFGR1_STOPWUCK_Pos                  (0U)
26282 #define RCC_CFGR1_STOPWUCK_Msk                  (0x1UL << RCC_CFGR1_STOPWUCK_Pos)     /*!< 0x00000001 */
26283 #define RCC_CFGR1_STOPWUCK                      RCC_CFGR1_STOPWUCK_Msk               /*!< System clock selection after a wake up from system stop */
26284 #define RCC_CFGR1_CPUSW_Pos                     (16U)
26285 #define RCC_CFGR1_CPUSW_Msk                     (0x3UL << RCC_CFGR1_CPUSW_Pos)        /*!< 0x00030000 */
26286 #define RCC_CFGR1_CPUSW                         RCC_CFGR1_CPUSW_Msk                  /*!< CPU clock switch selection */
26287 #define RCC_CFGR1_CPUSW_0                       (0x1UL << RCC_CFGR1_CPUSW_Pos)       /*!< 0x00010000 */
26288 #define RCC_CFGR1_CPUSW_1                       (0x2UL << RCC_CFGR1_CPUSW_Pos)       /*!< 0x00020000 */
26289 #define RCC_CFGR1_CPUSWS_Pos                    (20U)
26290 #define RCC_CFGR1_CPUSWS_Msk                    (0x3UL << RCC_CFGR1_CPUSWS_Pos)       /*!< 0x00300000 */
26291 #define RCC_CFGR1_CPUSWS                        RCC_CFGR1_CPUSWS_Msk                 /*!< CPU clock switch status */
26292 #define RCC_CFGR1_CPUSWS_0                      (0x1UL << RCC_CFGR1_CPUSWS_Pos)      /*!< 0x00100000 */
26293 #define RCC_CFGR1_CPUSWS_1                      (0x2UL << RCC_CFGR1_CPUSWS_Pos)      /*!< 0x00200000 */
26294 #define RCC_CFGR1_SYSSW_Pos                     (24U)
26295 #define RCC_CFGR1_SYSSW_Msk                     (0x3UL << RCC_CFGR1_SYSSW_Pos)        /*!< 0x03000000 */
26296 #define RCC_CFGR1_SYSSW                         RCC_CFGR1_SYSSW_Msk                  /*!< System clock switch selection */
26297 #define RCC_CFGR1_SYSSW_0                       (0x1UL << RCC_CFGR1_SYSSW_Pos)       /*!< 0x01000000 */
26298 #define RCC_CFGR1_SYSSW_1                       (0x2UL << RCC_CFGR1_SYSSW_Pos)       /*!< 0x02000000 */
26299 #define RCC_CFGR1_SYSSWS_Pos                    (28U)
26300 #define RCC_CFGR1_SYSSWS_Msk                    (0x3UL << RCC_CFGR1_SYSSWS_Pos)       /*!< 0x30000000 */
26301 #define RCC_CFGR1_SYSSWS                        RCC_CFGR1_SYSSWS_Msk                 /*!< System clock switch status */
26302 #define RCC_CFGR1_SYSSWS_0                      (0x1UL << RCC_CFGR1_SYSSWS_Pos)      /*!< 0x10000000 */
26303 #define RCC_CFGR1_SYSSWS_1                      (0x2UL << RCC_CFGR1_SYSSWS_Pos)      /*!< 0x20000000 */
26304 
26305 /******************  Bit definition for RCC_CFGR2 register  *******************/
26306 #define RCC_CFGR2_PPRE1_Pos                     (0U)
26307 #define RCC_CFGR2_PPRE1_Msk                     (0x7UL << RCC_CFGR2_PPRE1_Pos)        /*!< 0x00000007 */
26308 #define RCC_CFGR2_PPRE1                         RCC_CFGR2_PPRE1_Msk                  /*!< CPU domain APB1 prescaler */
26309 #define RCC_CFGR2_PPRE1_0                       (0x1UL << RCC_CFGR2_PPRE1_Pos)       /*!< 0x00000001 */
26310 #define RCC_CFGR2_PPRE1_1                       (0x2UL << RCC_CFGR2_PPRE1_Pos)       /*!< 0x00000002 */
26311 #define RCC_CFGR2_PPRE1_2                       (0x4UL << RCC_CFGR2_PPRE1_Pos)       /*!< 0x00000004 */
26312 #define RCC_CFGR2_PPRE2_Pos                     (4U)
26313 #define RCC_CFGR2_PPRE2_Msk                     (0x7UL << RCC_CFGR2_PPRE2_Pos)        /*!< 0x00000070 */
26314 #define RCC_CFGR2_PPRE2                         RCC_CFGR2_PPRE2_Msk                  /*!< CPU domain APB2 prescaler */
26315 #define RCC_CFGR2_PPRE2_0                       (0x1UL << RCC_CFGR2_PPRE2_Pos)       /*!< 0x00000010 */
26316 #define RCC_CFGR2_PPRE2_1                       (0x2UL << RCC_CFGR2_PPRE2_Pos)       /*!< 0x00000020 */
26317 #define RCC_CFGR2_PPRE2_2                       (0x4UL << RCC_CFGR2_PPRE2_Pos)       /*!< 0x00000040 */
26318 #define RCC_CFGR2_PPRE4_Pos                     (12U)
26319 #define RCC_CFGR2_PPRE4_Msk                     (0x7UL << RCC_CFGR2_PPRE4_Pos)        /*!< 0x00007000 */
26320 #define RCC_CFGR2_PPRE4                         RCC_CFGR2_PPRE4_Msk                  /*!< CPU domain APB4 prescaler */
26321 #define RCC_CFGR2_PPRE4_0                       (0x1UL << RCC_CFGR2_PPRE4_Pos)       /*!< 0x00001000 */
26322 #define RCC_CFGR2_PPRE4_1                       (0x2UL << RCC_CFGR2_PPRE4_Pos)       /*!< 0x00002000 */
26323 #define RCC_CFGR2_PPRE4_2                       (0x4UL << RCC_CFGR2_PPRE4_Pos)       /*!< 0x00004000 */
26324 #define RCC_CFGR2_PPRE5_Pos                     (16U)
26325 #define RCC_CFGR2_PPRE5_Msk                     (0x7UL << RCC_CFGR2_PPRE5_Pos)        /*!< 0x00070000 */
26326 #define RCC_CFGR2_PPRE5                         RCC_CFGR2_PPRE5_Msk                  /*!< CPU domain APB5 prescaler */
26327 #define RCC_CFGR2_PPRE5_0                       (0x1UL << RCC_CFGR2_PPRE5_Pos)       /*!< 0x00010000 */
26328 #define RCC_CFGR2_PPRE5_1                       (0x2UL << RCC_CFGR2_PPRE5_Pos)       /*!< 0x00020000 */
26329 #define RCC_CFGR2_PPRE5_2                       (0x4UL << RCC_CFGR2_PPRE5_Pos)       /*!< 0x00040000 */
26330 #define RCC_CFGR2_HPRE_Pos                      (20U)
26331 #define RCC_CFGR2_HPRE_Msk                      (0x7UL << RCC_CFGR2_HPRE_Pos)         /*!< 0x00700000 */
26332 #define RCC_CFGR2_HPRE                          RCC_CFGR2_HPRE_Msk                   /*!< AHB clock prescaler */
26333 #define RCC_CFGR2_HPRE_0                        (0x1UL << RCC_CFGR2_HPRE_Pos)        /*!< 0x00100000 */
26334 #define RCC_CFGR2_HPRE_1                        (0x2UL << RCC_CFGR2_HPRE_Pos)        /*!< 0x00200000 */
26335 #define RCC_CFGR2_HPRE_2                        (0x4UL << RCC_CFGR2_HPRE_Pos)        /*!< 0x00400000 */
26336 #define RCC_CFGR2_TIMPRE_Pos                    (24U)
26337 #define RCC_CFGR2_TIMPRE_Msk                    (0x3UL << RCC_CFGR2_TIMPRE_Pos)       /*!< 0x03000000 */
26338 #define RCC_CFGR2_TIMPRE                        RCC_CFGR2_TIMPRE_Msk                 /*!< Timer clock prescaler selection */
26339 #define RCC_CFGR2_TIMPRE_0                      (0x1UL << RCC_CFGR2_TIMPRE_Pos)      /*!< 0x01000000 */
26340 #define RCC_CFGR2_TIMPRE_1                      (0x2UL << RCC_CFGR2_TIMPRE_Pos)      /*!< 0x02000000 */
26341 
26342 /*******************  Bit definition for RCC_BDCR register  *******************/
26343 #define RCC_BDCR_VSWRST_Pos                     (31U)
26344 #define RCC_BDCR_VSWRST_Msk                     (0x1UL << RCC_BDCR_VSWRST_Pos)       /*!< 0x80000000 */
26345 #define RCC_BDCR_VSWRST                         RCC_BDCR_VSWRST_Msk                  /*!< Vswitch (VSW) domain software reset */
26346 
26347 /******************  Bit definition for RCC_HWRSR register  *******************/
26348 #define RCC_HWRSR_RMVF_Pos                      (16U)
26349 #define RCC_HWRSR_RMVF_Msk                      (0x1UL << RCC_HWRSR_RMVF_Pos)         /*!< 0x00010000 */
26350 #define RCC_HWRSR_RMVF                          RCC_HWRSR_RMVF_Msk                   /*!< Remove reset flag */
26351 #define RCC_HWRSR_LCKRSTF_Pos                   (17U)
26352 #define RCC_HWRSR_LCKRSTF_Msk                   (0x1UL << RCC_HWRSR_LCKRSTF_Pos)      /*!< 0x00020000 */
26353 #define RCC_HWRSR_LCKRSTF                       RCC_HWRSR_LCKRSTF_Msk                /*!< CPU lockup reset flag */
26354 #define RCC_HWRSR_BORRSTF_Pos                   (21U)
26355 #define RCC_HWRSR_BORRSTF_Msk                   (0x1UL << RCC_HWRSR_BORRSTF_Pos)      /*!< 0x00200000 */
26356 #define RCC_HWRSR_BORRSTF                       RCC_HWRSR_BORRSTF_Msk                /*!< BOR reset flag */
26357 #define RCC_HWRSR_PINRSTF_Pos                   (22U)
26358 #define RCC_HWRSR_PINRSTF_Msk                   (0x1UL << RCC_HWRSR_PINRSTF_Pos)      /*!< 0x00400000 */
26359 #define RCC_HWRSR_PINRSTF                       RCC_HWRSR_PINRSTF_Msk                /*!< Pin reset flag (NRST)  */
26360 #define RCC_HWRSR_PORRSTF_Pos                   (23U)
26361 #define RCC_HWRSR_PORRSTF_Msk                   (0x1UL << RCC_HWRSR_PORRSTF_Pos)      /*!< 0x00800000 */
26362 #define RCC_HWRSR_PORRSTF                       RCC_HWRSR_PORRSTF_Msk                /*!< POR/PDR reset flag */
26363 #define RCC_HWRSR_SFTRSTF_Pos                   (24U)
26364 #define RCC_HWRSR_SFTRSTF_Msk                   (0x1UL << RCC_HWRSR_SFTRSTF_Pos)      /*!< 0x01000000 */
26365 #define RCC_HWRSR_SFTRSTF                       RCC_HWRSR_SFTRSTF_Msk                /*!< Software system reset flag  */
26366 #define RCC_HWRSR_IWDGRSTF_Pos                  (26U)
26367 #define RCC_HWRSR_IWDGRSTF_Msk                  (0x1UL << RCC_HWRSR_IWDGRSTF_Pos)     /*!< 0x04000000 */
26368 #define RCC_HWRSR_IWDGRSTF                      RCC_HWRSR_IWDGRSTF_Msk               /*!< Independent watchdog reset flag */
26369 #define RCC_HWRSR_WWDGRSTF_Pos                  (28U)
26370 #define RCC_HWRSR_WWDGRSTF_Msk                  (0x1UL << RCC_HWRSR_WWDGRSTF_Pos)     /*!< 0x10000000 */
26371 #define RCC_HWRSR_WWDGRSTF                      RCC_HWRSR_WWDGRSTF_Msk               /*!< Window watchdog reset flag */
26372 #define RCC_HWRSR_LPWRRSTF_Pos                  (30U)
26373 #define RCC_HWRSR_LPWRRSTF_Msk                  (0x1UL << RCC_HWRSR_LPWRRSTF_Pos)     /*!< 0x40000000 */
26374 #define RCC_HWRSR_LPWRRSTF                      RCC_HWRSR_LPWRRSTF_Msk               /*!< Illegal Stop or Standby flag */
26375 
26376 /*******************  Bit definition for RCC_RSR register  ********************/
26377 #define RCC_RSR_RMVF_Pos                        (16U)
26378 #define RCC_RSR_RMVF_Msk                        (0x1UL << RCC_RSR_RMVF_Pos)           /*!< 0x00010000 */
26379 #define RCC_RSR_RMVF                            RCC_RSR_RMVF_Msk                     /*!< Remove reset flag */
26380 #define RCC_RSR_LCKRSTF_Pos                     (17U)
26381 #define RCC_RSR_LCKRSTF_Msk                     (0x1UL << RCC_RSR_LCKRSTF_Pos)        /*!< 0x00020000 */
26382 #define RCC_RSR_LCKRSTF                         RCC_RSR_LCKRSTF_Msk                  /*!< CPU lockup reset flag */
26383 #define RCC_RSR_BORRSTF_Pos                     (21U)
26384 #define RCC_RSR_BORRSTF_Msk                     (0x1UL << RCC_RSR_BORRSTF_Pos)        /*!< 0x00200000 */
26385 #define RCC_RSR_BORRSTF                         RCC_RSR_BORRSTF_Msk                  /*!< BOR reset flag */
26386 #define RCC_RSR_PINRSTF_Pos                     (22U)
26387 #define RCC_RSR_PINRSTF_Msk                     (0x1UL << RCC_RSR_PINRSTF_Pos)        /*!< 0x00400000 */
26388 #define RCC_RSR_PINRSTF                         RCC_RSR_PINRSTF_Msk                  /*!< Pin reset flag (NRST)  */
26389 #define RCC_RSR_PORRSTF_Pos                     (23U)
26390 #define RCC_RSR_PORRSTF_Msk                     (0x1UL << RCC_RSR_PORRSTF_Pos)        /*!< 0x00800000 */
26391 #define RCC_RSR_PORRSTF                         RCC_RSR_PORRSTF_Msk                  /*!< POR/PDR reset flag */
26392 #define RCC_RSR_SFTRSTF_Pos                     (24U)
26393 #define RCC_RSR_SFTRSTF_Msk                     (0x1UL << RCC_RSR_SFTRSTF_Pos)        /*!< 0x01000000 */
26394 #define RCC_RSR_SFTRSTF                         RCC_RSR_SFTRSTF_Msk                  /*!< Software system reset flag  */
26395 #define RCC_RSR_IWDGRSTF_Pos                    (26U)
26396 #define RCC_RSR_IWDGRSTF_Msk                    (0x1UL << RCC_RSR_IWDGRSTF_Pos)       /*!< 0x04000000 */
26397 #define RCC_RSR_IWDGRSTF                        RCC_RSR_IWDGRSTF_Msk                 /*!< Independent watchdog reset flag */
26398 #define RCC_RSR_WWDGRSTF_Pos                    (28U)
26399 #define RCC_RSR_WWDGRSTF_Msk                    (0x1UL << RCC_RSR_WWDGRSTF_Pos)       /*!< 0x10000000 */
26400 #define RCC_RSR_WWDGRSTF                        RCC_RSR_WWDGRSTF_Msk                 /*!< Window watchdog reset flag */
26401 #define RCC_RSR_LPWRRSTF_Pos                    (30U)
26402 #define RCC_RSR_LPWRRSTF_Msk                    (0x1UL << RCC_RSR_LPWRRSTF_Pos)       /*!< 0x40000000 */
26403 #define RCC_RSR_LPWRRSTF                        RCC_RSR_LPWRRSTF_Msk                 /*!< Illegal Stop or Standby flag */
26404 
26405 /*****************  Bit definition for RCC_LSECFGR register  ******************/
26406 #define RCC_LSECFGR_LSECSSON_Pos                (7U)
26407 #define RCC_LSECFGR_LSECSSON_Msk                (0x1UL << RCC_LSECFGR_LSECSSON_Pos)   /*!< 0x00000080 */
26408 #define RCC_LSECFGR_LSECSSON                    RCC_LSECFGR_LSECSSON_Msk             /*!< LSE clock security system (CSS) enable */
26409 #define RCC_LSECFGR_LSECSSRA_Pos                (8U)
26410 #define RCC_LSECFGR_LSECSSRA_Msk                (0x1UL << RCC_LSECFGR_LSECSSRA_Pos)   /*!< 0x00000100 */
26411 #define RCC_LSECFGR_LSECSSRA                    RCC_LSECFGR_LSECSSRA_Msk             /*!< LSE clock security system (CSS) rearm function */
26412 #define RCC_LSECFGR_LSECSSD_Pos                 (9U)
26413 #define RCC_LSECFGR_LSECSSD_Msk                 (0x1UL << RCC_LSECFGR_LSECSSD_Pos)    /*!< 0x00000200 */
26414 #define RCC_LSECFGR_LSECSSD                     RCC_LSECFGR_LSECSSD_Msk              /*!< LSE clock security system (CSS) failure detection */
26415 #define RCC_LSECFGR_LSEBYP_Pos                  (15U)
26416 #define RCC_LSECFGR_LSEBYP_Msk                  (0x1UL << RCC_LSECFGR_LSEBYP_Pos)     /*!< 0x00008000 */
26417 #define RCC_LSECFGR_LSEBYP                      RCC_LSECFGR_LSEBYP_Msk               /*!< LSE clock bypass */
26418 #define RCC_LSECFGR_LSEEXT_Pos                  (16U)
26419 #define RCC_LSECFGR_LSEEXT_Msk                  (0x1UL << RCC_LSECFGR_LSEEXT_Pos)     /*!< 0x00010000 */
26420 #define RCC_LSECFGR_LSEEXT                      RCC_LSECFGR_LSEEXT_Msk               /*!< LSE clock type in bypass mode */
26421 #define RCC_LSECFGR_LSEGFON_Pos                 (17U)
26422 #define RCC_LSECFGR_LSEGFON_Msk                 (0x1UL << RCC_LSECFGR_LSEGFON_Pos)    /*!< 0x00020000 */
26423 #define RCC_LSECFGR_LSEGFON                     RCC_LSECFGR_LSEGFON_Msk              /*!< LSE clock glitch filter enable */
26424 #define RCC_LSECFGR_LSEDRV_Pos                  (18U)
26425 #define RCC_LSECFGR_LSEDRV_Msk                  (0x3UL << RCC_LSECFGR_LSEDRV_Pos)     /*!< 0x000C0000 */
26426 #define RCC_LSECFGR_LSEDRV                      RCC_LSECFGR_LSEDRV_Msk               /*!< LSE oscillator driving capability */
26427 #define RCC_LSECFGR_LSEDRV_0                    (0x1UL << RCC_LSECFGR_LSEDRV_Pos)    /*!< 0x00040000 */
26428 #define RCC_LSECFGR_LSEDRV_1                    (0x2UL << RCC_LSECFGR_LSEDRV_Pos)    /*!< 0x00080000 */
26429 
26430 /*****************  Bit definition for RCC_MSICFGR register  ******************/
26431 #define RCC_MSICFGR_MSIFREQSEL_Pos              (9U)
26432 #define RCC_MSICFGR_MSIFREQSEL_Msk              (0x1UL << RCC_MSICFGR_MSIFREQSEL_Pos) /*!< 0x00000200 */
26433 #define RCC_MSICFGR_MSIFREQSEL                  RCC_MSICFGR_MSIFREQSEL_Msk           /*!< MSI oscillator frequency selection */
26434 #define RCC_MSICFGR_MSITRIM_Pos                 (16U)
26435 #define RCC_MSICFGR_MSITRIM_Msk                 (0x1FUL << RCC_MSICFGR_MSITRIM_Pos)   /*!< 0x001F0000 */
26436 #define RCC_MSICFGR_MSITRIM                     RCC_MSICFGR_MSITRIM_Msk              /*!< MSI clock trimming */
26437 #define RCC_MSICFGR_MSICAL_Pos                  (23U)
26438 #define RCC_MSICFGR_MSICAL_Msk                  (0xFFUL << RCC_MSICFGR_MSICAL_Pos)    /*!< 0x7F800000 */
26439 #define RCC_MSICFGR_MSICAL                      RCC_MSICFGR_MSICAL_Msk               /*!< MSI clock calibration */
26440 
26441 /*****************  Bit definition for RCC_HSICFGR register  ******************/
26442 #define RCC_HSICFGR_HSIDIV_Pos                  (7U)
26443 #define RCC_HSICFGR_HSIDIV_Msk                  (0x3UL << RCC_HSICFGR_HSIDIV_Pos)     /*!< 0x00000180 */
26444 #define RCC_HSICFGR_HSIDIV                      RCC_HSICFGR_HSIDIV_Msk               /*!< HSI clock divider */
26445 #define RCC_HSICFGR_HSIDIV_0                    (0x1UL << RCC_HSICFGR_HSIDIV_Pos)    /*!< 0x00000080 */
26446 #define RCC_HSICFGR_HSIDIV_1                    (0x2UL << RCC_HSICFGR_HSIDIV_Pos)    /*!< 0x00000100 */
26447 #define RCC_HSICFGR_HSITRIM_Pos                 (16U)
26448 #define RCC_HSICFGR_HSITRIM_Msk                 (0x7FUL << RCC_HSICFGR_HSITRIM_Pos)   /*!< 0x007F0000 */
26449 #define RCC_HSICFGR_HSITRIM                     RCC_HSICFGR_HSITRIM_Msk              /*!< HSI clock trimming */
26450 #define RCC_HSICFGR_HSICAL_Pos                  (23U)
26451 #define RCC_HSICFGR_HSICAL_Msk                  (0x1FFUL << RCC_HSICFGR_HSICAL_Pos)   /*!< 0xFF800000 */
26452 #define RCC_HSICFGR_HSICAL                      RCC_HSICFGR_HSICAL_Msk               /*!< HSI clock calibration */
26453 
26454 /******************  Bit definition for RCC_HSIMCR register  ******************/
26455 #define RCC_HSIMCR_HSIREF_Pos                   (0U)
26456 #define RCC_HSIMCR_HSIREF_Msk                   (0x7FFUL << RCC_HSIMCR_HSIREF_Pos)    /*!< 0x000007FF */
26457 #define RCC_HSIMCR_HSIREF                       RCC_HSIMCR_HSIREF_Msk                /*!< HSI clock-cycle counter reference value */
26458 #define RCC_HSIMCR_HSIDEV_Pos                   (16U)
26459 #define RCC_HSIMCR_HSIDEV_Msk                   (0x3FUL << RCC_HSIMCR_HSIDEV_Pos)     /*!< 0x003F0000 */
26460 #define RCC_HSIMCR_HSIDEV                       RCC_HSIMCR_HSIDEV_Msk                /*!< HSI clock count deviation value */
26461 #define RCC_HSIMCR_HSIMONEN_Pos                 (31U)
26462 #define RCC_HSIMCR_HSIMONEN_Msk                 (0x1UL << RCC_HSIMCR_HSIMONEN_Pos)    /*!< 0x80000000 */
26463 #define RCC_HSIMCR_HSIMONEN                     RCC_HSIMCR_HSIMONEN_Msk              /*!< HSI clock period monitor enable */
26464 
26465 /******************  Bit definition for RCC_HSIMSR register  ******************/
26466 #define RCC_HSIMSR_HSIVAL_Pos                   (0U)
26467 #define RCC_HSIMSR_HSIVAL_Msk                   (0x7FFUL << RCC_HSIMSR_HSIVAL_Pos)    /*!< 0x000007FF */
26468 #define RCC_HSIMSR_HSIVAL                       RCC_HSIMSR_HSIVAL_Msk                /*!< HSI clock-cycle counter measured value */
26469 
26470 /*****************  Bit definition for RCC_HSECFGR register  ******************/
26471 #define RCC_HSECFGR_HSEDIV2SEL_Pos              (6U)
26472 #define RCC_HSECFGR_HSEDIV2SEL_Msk              (0x1UL << RCC_HSECFGR_HSEDIV2SEL_Pos) /*!< 0x00000040 */
26473 #define RCC_HSECFGR_HSEDIV2SEL                  RCC_HSECFGR_HSEDIV2SEL_Msk           /*!< HSE div2 clock source select */
26474 #define RCC_HSECFGR_HSECSSON_Pos                (7U)
26475 #define RCC_HSECFGR_HSECSSON_Msk                (0x1UL << RCC_HSECFGR_HSECSSON_Pos)   /*!< 0x00000080 */
26476 #define RCC_HSECFGR_HSECSSON                    RCC_HSECFGR_HSECSSON_Msk             /*!< HSE CSS enable */
26477 #define RCC_HSECFGR_HSECSSD_Pos                 (9U)
26478 #define RCC_HSECFGR_HSECSSD_Msk                 (0x1UL << RCC_HSECFGR_HSECSSD_Pos)    /*!< 0x00000200 */
26479 #define RCC_HSECFGR_HSECSSD                     RCC_HSECFGR_HSECSSD_Msk              /*!< HSE CSS failure detection */
26480 #define RCC_HSECFGR_HSECSSBYP_Pos               (10U)
26481 #define RCC_HSECFGR_HSECSSBYP_Msk               (0x1UL << RCC_HSECFGR_HSECSSBYP_Pos)  /*!< 0x00000400 */
26482 #define RCC_HSECFGR_HSECSSBYP                   RCC_HSECFGR_HSECSSBYP_Msk            /*!< HSE CSS bypass enable */
26483 #define RCC_HSECFGR_HSECSSBPRE_Pos              (11U)
26484 #define RCC_HSECFGR_HSECSSBPRE_Msk              (0xFUL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00007800 */
26485 #define RCC_HSECFGR_HSECSSBPRE                  RCC_HSECFGR_HSECSSBPRE_Msk           /*!< HSE CSS bypass divider */
26486 #define RCC_HSECFGR_HSECSSBPRE_0                (0x1UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00000800 */
26487 #define RCC_HSECFGR_HSECSSBPRE_1                (0x2UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00001000 */
26488 #define RCC_HSECFGR_HSECSSBPRE_2                (0x4UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00002000 */
26489 #define RCC_HSECFGR_HSECSSBPRE_3                (0x8UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00004000 */
26490 #define RCC_HSECFGR_HSEBYP_Pos                  (15U)
26491 #define RCC_HSECFGR_HSEBYP_Msk                  (0x1UL << RCC_HSECFGR_HSEBYP_Pos)     /*!< 0x00008000 */
26492 #define RCC_HSECFGR_HSEBYP                      RCC_HSECFGR_HSEBYP_Msk               /*!< HSE clock bypass */
26493 #define RCC_HSECFGR_HSEEXT_Pos                  (16U)
26494 #define RCC_HSECFGR_HSEEXT_Msk                  (0x1UL << RCC_HSECFGR_HSEEXT_Pos)     /*!< 0x00010000 */
26495 #define RCC_HSECFGR_HSEEXT                      RCC_HSECFGR_HSEEXT_Msk               /*!< HSE clock type in bypass mode */
26496 
26497 /****************  Bit definition for RCC_PLL1CFGR1 register  *****************/
26498 #define RCC_PLL1CFGR1_PLL1DIVN_Pos              (8U)
26499 #define RCC_PLL1CFGR1_PLL1DIVN_Msk              (0xFFFUL << RCC_PLL1CFGR1_PLL1DIVN_Pos) /*!< 0x000FFF00 */
26500 #define RCC_PLL1CFGR1_PLL1DIVN                  RCC_PLL1CFGR1_PLL1DIVN_Msk           /*!< PLL1 integer part for the VCO multiplication factor */
26501 #define RCC_PLL1CFGR1_PLL1DIVM_Pos              (20U)
26502 #define RCC_PLL1CFGR1_PLL1DIVM_Msk              (0x3FUL << RCC_PLL1CFGR1_PLL1DIVM_Pos)/*!< 0x03F00000 */
26503 #define RCC_PLL1CFGR1_PLL1DIVM                  RCC_PLL1CFGR1_PLL1DIVM_Msk           /*!< PLL1 reference input clock divide frequency ratio */
26504 #define RCC_PLL1CFGR1_PLL1BYP_Pos               (27U)
26505 #define RCC_PLL1CFGR1_PLL1BYP_Msk               (0x1UL << RCC_PLL1CFGR1_PLL1BYP_Pos)  /*!< 0x08000000 */
26506 #define RCC_PLL1CFGR1_PLL1BYP                   RCC_PLL1CFGR1_PLL1BYP_Msk            /*!< PLL1 bypass */
26507 #define RCC_PLL1CFGR1_PLL1SEL_Pos               (28U)
26508 #define RCC_PLL1CFGR1_PLL1SEL_Msk               (0x7UL << RCC_PLL1CFGR1_PLL1SEL_Pos)  /*!< 0x70000000 */
26509 #define RCC_PLL1CFGR1_PLL1SEL                   RCC_PLL1CFGR1_PLL1SEL_Msk            /*!< PLL1 source selection of the reference clock */
26510 #define RCC_PLL1CFGR1_PLL1SEL_0                 (0x1UL << RCC_PLL1CFGR1_PLL1SEL_Pos) /*!< 0x10000000 */
26511 #define RCC_PLL1CFGR1_PLL1SEL_1                 (0x2UL << RCC_PLL1CFGR1_PLL1SEL_Pos) /*!< 0x20000000 */
26512 #define RCC_PLL1CFGR1_PLL1SEL_2                 (0x4UL << RCC_PLL1CFGR1_PLL1SEL_Pos) /*!< 0x40000000 */
26513 
26514 /****************  Bit definition for RCC_PLL1CFGR2 register  *****************/
26515 #define RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos          (0U)
26516 #define RCC_PLL1CFGR2_PLL1DIVNFRAC_Msk          (0xFFFFFFUL << RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos)        /*!< 0x00FFFFFF */
26517 #define RCC_PLL1CFGR2_PLL1DIVNFRAC              RCC_PLL1CFGR2_PLL1DIVNFRAC_Msk       /*!< PLL1 fractional part of the VCO multiplication factor */
26518 
26519 /****************  Bit definition for RCC_PLL1CFGR3 register  *****************/
26520 #define RCC_PLL1CFGR3_PLL1MODSSRST_Pos          (0U)
26521 #define RCC_PLL1CFGR3_PLL1MODSSRST_Msk          (0x1UL << RCC_PLL1CFGR3_PLL1MODSSRST_Pos)   /*!< 0x00000001 */
26522 #define RCC_PLL1CFGR3_PLL1MODSSRST              RCC_PLL1CFGR3_PLL1MODSSRST_Msk       /*!< PLL1 modulation spread spectrum reset */
26523 #define RCC_PLL1CFGR3_PLL1DACEN_Pos             (1U)
26524 #define RCC_PLL1CFGR3_PLL1DACEN_Msk             (0x1UL << RCC_PLL1CFGR3_PLL1DACEN_Pos)/*!< 0x00000002 */
26525 #define RCC_PLL1CFGR3_PLL1DACEN                 RCC_PLL1CFGR3_PLL1DACEN_Msk          /*!< PLL1 noise canceling DAC enable in fractional mode */
26526 #define RCC_PLL1CFGR3_PLL1MODSSDIS_Pos          (2U)
26527 #define RCC_PLL1CFGR3_PLL1MODSSDIS_Msk          (0x1UL << RCC_PLL1CFGR3_PLL1MODSSDIS_Pos)   /*!< 0x00000004 */
26528 #define RCC_PLL1CFGR3_PLL1MODSSDIS              RCC_PLL1CFGR3_PLL1MODSSDIS_Msk       /*!< PLL1 modulation spread spectrum disable  */
26529 #define RCC_PLL1CFGR3_PLL1MODDSEN_Pos           (3U)
26530 #define RCC_PLL1CFGR3_PLL1MODDSEN_Msk           (0x1UL << RCC_PLL1CFGR3_PLL1MODDSEN_Pos)  /*!< 0x00000008 */
26531 #define RCC_PLL1CFGR3_PLL1MODDSEN               RCC_PLL1CFGR3_PLL1MODDSEN_Msk        /*!< PLL1 modulation spread spectrum (and fractional divide) enable */
26532 #define RCC_PLL1CFGR3_PLL1MODSPRDW_Pos          (4U)
26533 #define RCC_PLL1CFGR3_PLL1MODSPRDW_Msk          (0x1UL << RCC_PLL1CFGR3_PLL1MODSPRDW_Pos)   /*!< 0x00000010 */
26534 #define RCC_PLL1CFGR3_PLL1MODSPRDW              RCC_PLL1CFGR3_PLL1MODSPRDW_Msk       /*!< PLL1 modulation spread spectrum down */
26535 #define RCC_PLL1CFGR3_PLL1MODDIV_Pos            (8U)
26536 #define RCC_PLL1CFGR3_PLL1MODDIV_Msk            (0xFUL << RCC_PLL1CFGR3_PLL1MODDIV_Pos) /*!< 0x00000F00 */
26537 #define RCC_PLL1CFGR3_PLL1MODDIV                RCC_PLL1CFGR3_PLL1MODDIV_Msk         /*!< PLL1 modulation division frequency adjustment  */
26538 #define RCC_PLL1CFGR3_PLL1MODSPR_Pos            (16U)
26539 #define RCC_PLL1CFGR3_PLL1MODSPR_Msk            (0x1FUL << RCC_PLL1CFGR3_PLL1MODSPR_Pos)  /*!< 0x001F0000 */
26540 #define RCC_PLL1CFGR3_PLL1MODSPR                RCC_PLL1CFGR3_PLL1MODSPR_Msk         /*!< PLL1 modulation spread depth adjustment */
26541 #define RCC_PLL1CFGR3_PLL1PDIV2_Pos             (24U)
26542 #define RCC_PLL1CFGR3_PLL1PDIV2_Msk             (0x7UL << RCC_PLL1CFGR3_PLL1PDIV2_Pos)/*!< 0x07000000 */
26543 #define RCC_PLL1CFGR3_PLL1PDIV2                 RCC_PLL1CFGR3_PLL1PDIV2_Msk          /*!< PLL1 VCO frequency divider level 2 */
26544 #define RCC_PLL1CFGR3_PLL1PDIV1_Pos             (27U)
26545 #define RCC_PLL1CFGR3_PLL1PDIV1_Msk             (0x7UL << RCC_PLL1CFGR3_PLL1PDIV1_Pos)/*!< 0x38000000 */
26546 #define RCC_PLL1CFGR3_PLL1PDIV1                 RCC_PLL1CFGR3_PLL1PDIV1_Msk          /*!< PLL1 VCO frequency divider level 1 */
26547 #define RCC_PLL1CFGR3_PLL1PDIVEN_Pos            (30U)
26548 #define RCC_PLL1CFGR3_PLL1PDIVEN_Msk            (0x1UL << RCC_PLL1CFGR3_PLL1PDIVEN_Pos) /*!< 0x40000000 */
26549 #define RCC_PLL1CFGR3_PLL1PDIVEN                RCC_PLL1CFGR3_PLL1PDIVEN_Msk         /*!< PLL1 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */
26550 
26551 /****************  Bit definition for RCC_PLL2CFGR1 register  *****************/
26552 #define RCC_PLL2CFGR1_PLL2DIVN_Pos              (8U)
26553 #define RCC_PLL2CFGR1_PLL2DIVN_Msk              (0xFFFUL << RCC_PLL2CFGR1_PLL2DIVN_Pos) /*!< 0x000FFF00 */
26554 #define RCC_PLL2CFGR1_PLL2DIVN                  RCC_PLL2CFGR1_PLL2DIVN_Msk           /*!< PLL2 integer part for the VCO multiplication factor */
26555 #define RCC_PLL2CFGR1_PLL2DIVM_Pos              (20U)
26556 #define RCC_PLL2CFGR1_PLL2DIVM_Msk              (0x3FUL << RCC_PLL2CFGR1_PLL2DIVM_Pos)/*!< 0x03F00000 */
26557 #define RCC_PLL2CFGR1_PLL2DIVM                  RCC_PLL2CFGR1_PLL2DIVM_Msk           /*!< PLL2 reference input clock divide frequency ratio */
26558 #define RCC_PLL2CFGR1_PLL2BYP_Pos               (27U)
26559 #define RCC_PLL2CFGR1_PLL2BYP_Msk               (0x1UL << RCC_PLL2CFGR1_PLL2BYP_Pos)  /*!< 0x08000000 */
26560 #define RCC_PLL2CFGR1_PLL2BYP                   RCC_PLL2CFGR1_PLL2BYP_Msk            /*!< PLL2 bypass */
26561 #define RCC_PLL2CFGR1_PLL2SEL_Pos               (28U)
26562 #define RCC_PLL2CFGR1_PLL2SEL_Msk               (0x7UL << RCC_PLL2CFGR1_PLL2SEL_Pos)  /*!< 0x70000000 */
26563 #define RCC_PLL2CFGR1_PLL2SEL                   RCC_PLL2CFGR1_PLL2SEL_Msk            /*!< PLL2 source selection of the reference clock */
26564 #define RCC_PLL2CFGR1_PLL2SEL_0                 (0x1UL << RCC_PLL2CFGR1_PLL2SEL_Pos) /*!< 0x10000000 */
26565 #define RCC_PLL2CFGR1_PLL2SEL_1                 (0x2UL << RCC_PLL2CFGR1_PLL2SEL_Pos) /*!< 0x20000000 */
26566 #define RCC_PLL2CFGR1_PLL2SEL_2                 (0x4UL << RCC_PLL2CFGR1_PLL2SEL_Pos) /*!< 0x40000000 */
26567 
26568 /****************  Bit definition for RCC_PLL2CFGR2 register  *****************/
26569 #define RCC_PLL2CFGR2_PLL2DIVNFRAC_Pos          (0U)
26570 #define RCC_PLL2CFGR2_PLL2DIVNFRAC_Msk          (0xFFFFFFUL << RCC_PLL2CFGR2_PLL2DIVNFRAC_Pos)        /*!< 0x00FFFFFF */
26571 #define RCC_PLL2CFGR2_PLL2DIVNFRAC              RCC_PLL2CFGR2_PLL2DIVNFRAC_Msk       /*!< PLL2 fractional part of the VCO multiplication factor */
26572 
26573 /****************  Bit definition for RCC_PLL2CFGR3 register  *****************/
26574 #define RCC_PLL2CFGR3_PLL2MODSSRST_Pos          (0U)
26575 #define RCC_PLL2CFGR3_PLL2MODSSRST_Msk          (0x1UL << RCC_PLL2CFGR3_PLL2MODSSRST_Pos)   /*!< 0x00000001 */
26576 #define RCC_PLL2CFGR3_PLL2MODSSRST              RCC_PLL2CFGR3_PLL2MODSSRST_Msk       /*!< PLL2 modulation spread spectrum reset */
26577 #define RCC_PLL2CFGR3_PLL2DACEN_Pos             (1U)
26578 #define RCC_PLL2CFGR3_PLL2DACEN_Msk             (0x1UL << RCC_PLL2CFGR3_PLL2DACEN_Pos)/*!< 0x00000002 */
26579 #define RCC_PLL2CFGR3_PLL2DACEN                 RCC_PLL2CFGR3_PLL2DACEN_Msk          /*!< PLL2 noise canceling DAC enable in fractional mode */
26580 #define RCC_PLL2CFGR3_PLL2MODSSDIS_Pos          (2U)
26581 #define RCC_PLL2CFGR3_PLL2MODSSDIS_Msk          (0x1UL << RCC_PLL2CFGR3_PLL2MODSSDIS_Pos)   /*!< 0x00000004 */
26582 #define RCC_PLL2CFGR3_PLL2MODSSDIS              RCC_PLL2CFGR3_PLL2MODSSDIS_Msk       /*!< PLL2 modulation spread spectrum disable  */
26583 #define RCC_PLL2CFGR3_PLL2MODDSEN_Pos           (3U)
26584 #define RCC_PLL2CFGR3_PLL2MODDSEN_Msk           (0x1UL << RCC_PLL2CFGR3_PLL2MODDSEN_Pos)  /*!< 0x00000008 */
26585 #define RCC_PLL2CFGR3_PLL2MODDSEN               RCC_PLL2CFGR3_PLL2MODDSEN_Msk        /*!< PLL2 modulation spread spectrum (and fractional divide) enable */
26586 #define RCC_PLL2CFGR3_PLL2MODSPRDW_Pos          (4U)
26587 #define RCC_PLL2CFGR3_PLL2MODSPRDW_Msk          (0x1UL << RCC_PLL2CFGR3_PLL2MODSPRDW_Pos)   /*!< 0x00000010 */
26588 #define RCC_PLL2CFGR3_PLL2MODSPRDW              RCC_PLL2CFGR3_PLL2MODSPRDW_Msk       /*!< PLL2 modulation down spread */
26589 #define RCC_PLL2CFGR3_PLL2MODDIV_Pos            (8U)
26590 #define RCC_PLL2CFGR3_PLL2MODDIV_Msk            (0xFUL << RCC_PLL2CFGR3_PLL2MODDIV_Pos) /*!< 0x00000F00 */
26591 #define RCC_PLL2CFGR3_PLL2MODDIV                RCC_PLL2CFGR3_PLL2MODDIV_Msk         /*!< PLL2 modulation division frequency adjustment  */
26592 #define RCC_PLL2CFGR3_PLL2MODSPR_Pos            (16U)
26593 #define RCC_PLL2CFGR3_PLL2MODSPR_Msk            (0x1FUL << RCC_PLL2CFGR3_PLL2MODSPR_Pos)  /*!< 0x001F0000 */
26594 #define RCC_PLL2CFGR3_PLL2MODSPR                RCC_PLL2CFGR3_PLL2MODSPR_Msk         /*!< PLL2 modulation spread depth adjustment */
26595 #define RCC_PLL2CFGR3_PLL2PDIV2_Pos             (24U)
26596 #define RCC_PLL2CFGR3_PLL2PDIV2_Msk             (0x7UL << RCC_PLL2CFGR3_PLL2PDIV2_Pos)/*!< 0x07000000 */
26597 #define RCC_PLL2CFGR3_PLL2PDIV2                 RCC_PLL2CFGR3_PLL2PDIV2_Msk          /*!< PLL2 VCO frequency divider level 2 */
26598 #define RCC_PLL2CFGR3_PLL2PDIV1_Pos             (27U)
26599 #define RCC_PLL2CFGR3_PLL2PDIV1_Msk             (0x7UL << RCC_PLL2CFGR3_PLL2PDIV1_Pos)/*!< 0x38000000 */
26600 #define RCC_PLL2CFGR3_PLL2PDIV1                 RCC_PLL2CFGR3_PLL2PDIV1_Msk          /*!< PLL2 VCO frequency divider level 1 */
26601 #define RCC_PLL2CFGR3_PLL2PDIVEN_Pos            (30U)
26602 #define RCC_PLL2CFGR3_PLL2PDIVEN_Msk            (0x1UL << RCC_PLL2CFGR3_PLL2PDIVEN_Pos) /*!< 0x40000000 */
26603 #define RCC_PLL2CFGR3_PLL2PDIVEN                RCC_PLL2CFGR3_PLL2PDIVEN_Msk         /*!< PLL2 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */
26604 
26605 /****************  Bit definition for RCC_PLL3CFGR1 register  *****************/
26606 #define RCC_PLL3CFGR1_PLL3DIVN_Pos              (8U)
26607 #define RCC_PLL3CFGR1_PLL3DIVN_Msk              (0xFFFUL << RCC_PLL3CFGR1_PLL3DIVN_Pos) /*!< 0x000FFF00 */
26608 #define RCC_PLL3CFGR1_PLL3DIVN                  RCC_PLL3CFGR1_PLL3DIVN_Msk           /*!< PLL3 Integer part for the VCO multiplication factor */
26609 #define RCC_PLL3CFGR1_PLL3DIVM_Pos              (20U)
26610 #define RCC_PLL3CFGR1_PLL3DIVM_Msk              (0x3FUL << RCC_PLL3CFGR1_PLL3DIVM_Pos)/*!< 0x03F00000 */
26611 #define RCC_PLL3CFGR1_PLL3DIVM                  RCC_PLL3CFGR1_PLL3DIVM_Msk           /*!< PLL3 reference input clock divide frequency ratio */
26612 #define RCC_PLL3CFGR1_PLL3BYP_Pos               (27U)
26613 #define RCC_PLL3CFGR1_PLL3BYP_Msk               (0x1UL << RCC_PLL3CFGR1_PLL3BYP_Pos)  /*!< 0x08000000 */
26614 #define RCC_PLL3CFGR1_PLL3BYP                   RCC_PLL3CFGR1_PLL3BYP_Msk            /*!< PLL3 bypass */
26615 #define RCC_PLL3CFGR1_PLL3SEL_Pos               (28U)
26616 #define RCC_PLL3CFGR1_PLL3SEL_Msk               (0x7UL << RCC_PLL3CFGR1_PLL3SEL_Pos)  /*!< 0x70000000 */
26617 #define RCC_PLL3CFGR1_PLL3SEL                   RCC_PLL3CFGR1_PLL3SEL_Msk            /*!< PLL3 source selection of the reference clock */
26618 #define RCC_PLL3CFGR1_PLL3SEL_0                 (0x1UL << RCC_PLL3CFGR1_PLL3SEL_Pos) /*!< 0x10000000 */
26619 #define RCC_PLL3CFGR1_PLL3SEL_1                 (0x2UL << RCC_PLL3CFGR1_PLL3SEL_Pos) /*!< 0x20000000 */
26620 #define RCC_PLL3CFGR1_PLL3SEL_2                 (0x4UL << RCC_PLL3CFGR1_PLL3SEL_Pos) /*!< 0x40000000 */
26621 
26622 /****************  Bit definition for RCC_PLL3CFGR2 register  *****************/
26623 #define RCC_PLL3CFGR2_PLL3DIVNFRAC_Pos          (0U)
26624 #define RCC_PLL3CFGR2_PLL3DIVNFRAC_Msk          (0xFFFFFFUL << RCC_PLL3CFGR2_PLL3DIVNFRAC_Pos)        /*!< 0x00FFFFFF */
26625 #define RCC_PLL3CFGR2_PLL3DIVNFRAC              RCC_PLL3CFGR2_PLL3DIVNFRAC_Msk       /*!< PLL3 fractional part of the VCO multiplication factor */
26626 
26627 /****************  Bit definition for RCC_PLL3CFGR3 register  *****************/
26628 #define RCC_PLL3CFGR3_PLL3MODSSRST_Pos          (0U)
26629 #define RCC_PLL3CFGR3_PLL3MODSSRST_Msk          (0x1UL << RCC_PLL3CFGR3_PLL3MODSSRST_Pos)   /*!< 0x00000001 */
26630 #define RCC_PLL3CFGR3_PLL3MODSSRST              RCC_PLL3CFGR3_PLL3MODSSRST_Msk       /*!< PLL3 modulation spread spectrum reset */
26631 #define RCC_PLL3CFGR3_PLL3DACEN_Pos             (1U)
26632 #define RCC_PLL3CFGR3_PLL3DACEN_Msk             (0x1UL << RCC_PLL3CFGR3_PLL3DACEN_Pos)/*!< 0x00000002 */
26633 #define RCC_PLL3CFGR3_PLL3DACEN                 RCC_PLL3CFGR3_PLL3DACEN_Msk          /*!< PLL3 noise canceling DAC enable in fractional mode */
26634 #define RCC_PLL3CFGR3_PLL3MODSSDIS_Pos          (2U)
26635 #define RCC_PLL3CFGR3_PLL3MODSSDIS_Msk          (0x1UL << RCC_PLL3CFGR3_PLL3MODSSDIS_Pos)   /*!< 0x00000004 */
26636 #define RCC_PLL3CFGR3_PLL3MODSSDIS              RCC_PLL3CFGR3_PLL3MODSSDIS_Msk       /*!< PLL3 modulation spread spectrum disable  */
26637 #define RCC_PLL3CFGR3_PLL3MODDSEN_Pos           (3U)
26638 #define RCC_PLL3CFGR3_PLL3MODDSEN_Msk           (0x1UL << RCC_PLL3CFGR3_PLL3MODDSEN_Pos)  /*!< 0x00000008 */
26639 #define RCC_PLL3CFGR3_PLL3MODDSEN               RCC_PLL3CFGR3_PLL3MODDSEN_Msk        /*!< PLL3 modulation spread spectrum (and fractional divide) enable */
26640 #define RCC_PLL3CFGR3_PLL3MODSPRDW_Pos          (4U)
26641 #define RCC_PLL3CFGR3_PLL3MODSPRDW_Msk          (0x1UL << RCC_PLL3CFGR3_PLL3MODSPRDW_Pos)   /*!< 0x00000010 */
26642 #define RCC_PLL3CFGR3_PLL3MODSPRDW              RCC_PLL3CFGR3_PLL3MODSPRDW_Msk       /*!< PLL3 modulation down spread */
26643 #define RCC_PLL3CFGR3_PLL3MODDIV_Pos            (8U)
26644 #define RCC_PLL3CFGR3_PLL3MODDIV_Msk            (0xFUL << RCC_PLL3CFGR3_PLL3MODDIV_Pos) /*!< 0x00000F00 */
26645 #define RCC_PLL3CFGR3_PLL3MODDIV                RCC_PLL3CFGR3_PLL3MODDIV_Msk         /*!< PLL3 modulation division frequency adjustment  */
26646 #define RCC_PLL3CFGR3_PLL3MODSPR_Pos            (16U)
26647 #define RCC_PLL3CFGR3_PLL3MODSPR_Msk            (0x1FUL << RCC_PLL3CFGR3_PLL3MODSPR_Pos)  /*!< 0x001F0000 */
26648 #define RCC_PLL3CFGR3_PLL3MODSPR                RCC_PLL3CFGR3_PLL3MODSPR_Msk         /*!< PLL3 modulation spread depth adjustment */
26649 #define RCC_PLL3CFGR3_PLL3PDIV2_Pos             (24U)
26650 #define RCC_PLL3CFGR3_PLL3PDIV2_Msk             (0x7UL << RCC_PLL3CFGR3_PLL3PDIV2_Pos)/*!< 0x07000000 */
26651 #define RCC_PLL3CFGR3_PLL3PDIV2                 RCC_PLL3CFGR3_PLL3PDIV2_Msk          /*!< PLL3 VCO frequency divider level 2 */
26652 #define RCC_PLL3CFGR3_PLL3PDIV1_Pos             (27U)
26653 #define RCC_PLL3CFGR3_PLL3PDIV1_Msk             (0x7UL << RCC_PLL3CFGR3_PLL3PDIV1_Pos)/*!< 0x38000000 */
26654 #define RCC_PLL3CFGR3_PLL3PDIV1                 RCC_PLL3CFGR3_PLL3PDIV1_Msk          /*!< PLL3 VCO frequency divider level 1 */
26655 #define RCC_PLL3CFGR3_PLL3PDIVEN_Pos            (30U)
26656 #define RCC_PLL3CFGR3_PLL3PDIVEN_Msk            (0x1UL << RCC_PLL3CFGR3_PLL3PDIVEN_Pos) /*!< 0x40000000 */
26657 #define RCC_PLL3CFGR3_PLL3PDIVEN                RCC_PLL3CFGR3_PLL3PDIVEN_Msk         /*!< PLL3 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */
26658 
26659 /****************  Bit definition for RCC_PLL4CFGR1 register  *****************/
26660 #define RCC_PLL4CFGR1_PLL4DIVN_Pos              (8U)
26661 #define RCC_PLL4CFGR1_PLL4DIVN_Msk              (0xFFFUL << RCC_PLL4CFGR1_PLL4DIVN_Pos) /*!< 0x000FFF00 */
26662 #define RCC_PLL4CFGR1_PLL4DIVN                  RCC_PLL4CFGR1_PLL4DIVN_Msk           /*!< PLL4 integer part for the VCO multiplication factor */
26663 #define RCC_PLL4CFGR1_PLL4DIVM_Pos              (20U)
26664 #define RCC_PLL4CFGR1_PLL4DIVM_Msk              (0x3FUL << RCC_PLL4CFGR1_PLL4DIVM_Pos)/*!< 0x03F00000 */
26665 #define RCC_PLL4CFGR1_PLL4DIVM                  RCC_PLL4CFGR1_PLL4DIVM_Msk           /*!< PLL4 reference input clock divide frequency ratio */
26666 #define RCC_PLL4CFGR1_PLL4BYP_Pos               (27U)
26667 #define RCC_PLL4CFGR1_PLL4BYP_Msk               (0x1UL << RCC_PLL4CFGR1_PLL4BYP_Pos)  /*!< 0x08000000 */
26668 #define RCC_PLL4CFGR1_PLL4BYP                   RCC_PLL4CFGR1_PLL4BYP_Msk            /*!< PLL4 bypass */
26669 #define RCC_PLL4CFGR1_PLL4SEL_Pos               (28U)
26670 #define RCC_PLL4CFGR1_PLL4SEL_Msk               (0x7UL << RCC_PLL4CFGR1_PLL4SEL_Pos)  /*!< 0x70000000 */
26671 #define RCC_PLL4CFGR1_PLL4SEL                   RCC_PLL4CFGR1_PLL4SEL_Msk            /*!< PLL4 source selection of the reference clock */
26672 #define RCC_PLL4CFGR1_PLL4SEL_0                 (0x1UL << RCC_PLL4CFGR1_PLL4SEL_Pos) /*!< 0x10000000 */
26673 #define RCC_PLL4CFGR1_PLL4SEL_1                 (0x2UL << RCC_PLL4CFGR1_PLL4SEL_Pos) /*!< 0x20000000 */
26674 #define RCC_PLL4CFGR1_PLL4SEL_2                 (0x4UL << RCC_PLL4CFGR1_PLL4SEL_Pos) /*!< 0x40000000 */
26675 
26676 /****************  Bit definition for RCC_PLL4CFGR2 register  *****************/
26677 #define RCC_PLL4CFGR2_PLL4DIVNFRAC_Pos          (0U)
26678 #define RCC_PLL4CFGR2_PLL4DIVNFRAC_Msk          (0xFFFFFFUL << RCC_PLL4CFGR2_PLL4DIVNFRAC_Pos)        /*!< 0x00FFFFFF */
26679 #define RCC_PLL4CFGR2_PLL4DIVNFRAC              RCC_PLL4CFGR2_PLL4DIVNFRAC_Msk       /*!< PLL4 fractional part of the VCO multiplication factor */
26680 
26681 /****************  Bit definition for RCC_PLL4CFGR3 register  *****************/
26682 #define RCC_PLL4CFGR3_PLL4MODSSRST_Pos          (0U)
26683 #define RCC_PLL4CFGR3_PLL4MODSSRST_Msk          (0x1UL << RCC_PLL4CFGR3_PLL4MODSSRST_Pos)   /*!< 0x00000001 */
26684 #define RCC_PLL4CFGR3_PLL4MODSSRST              RCC_PLL4CFGR3_PLL4MODSSRST_Msk       /*!< PLL4 modulation spread spectrum reset */
26685 #define RCC_PLL4CFGR3_PLL4DACEN_Pos             (1U)
26686 #define RCC_PLL4CFGR3_PLL4DACEN_Msk             (0x1UL << RCC_PLL4CFGR3_PLL4DACEN_Pos)/*!< 0x00000002 */
26687 #define RCC_PLL4CFGR3_PLL4DACEN                 RCC_PLL4CFGR3_PLL4DACEN_Msk          /*!< PLL4 noise canceling DAC enable in fractional mode */
26688 #define RCC_PLL4CFGR3_PLL4MODSSDIS_Pos          (2U)
26689 #define RCC_PLL4CFGR3_PLL4MODSSDIS_Msk          (0x1UL << RCC_PLL4CFGR3_PLL4MODSSDIS_Pos)   /*!< 0x00000004 */
26690 #define RCC_PLL4CFGR3_PLL4MODSSDIS              RCC_PLL4CFGR3_PLL4MODSSDIS_Msk       /*!< PLL4 modulation spread spectrum disable  */
26691 #define RCC_PLL4CFGR3_PLL4MODDSEN_Pos           (3U)
26692 #define RCC_PLL4CFGR3_PLL4MODDSEN_Msk           (0x1UL << RCC_PLL4CFGR3_PLL4MODDSEN_Pos)  /*!< 0x00000008 */
26693 #define RCC_PLL4CFGR3_PLL4MODDSEN               RCC_PLL4CFGR3_PLL4MODDSEN_Msk        /*!< PLL4 modulation spread spectrum (and fractional divide) enable */
26694 #define RCC_PLL4CFGR3_PLL4MODSPRDW_Pos          (4U)
26695 #define RCC_PLL4CFGR3_PLL4MODSPRDW_Msk          (0x1UL << RCC_PLL4CFGR3_PLL4MODSPRDW_Pos)   /*!< 0x00000010 */
26696 #define RCC_PLL4CFGR3_PLL4MODSPRDW              RCC_PLL4CFGR3_PLL4MODSPRDW_Msk       /*!< PLL4 modulation down spread */
26697 #define RCC_PLL4CFGR3_PLL4MODDIV_Pos            (8U)
26698 #define RCC_PLL4CFGR3_PLL4MODDIV_Msk            (0xFUL << RCC_PLL4CFGR3_PLL4MODDIV_Pos) /*!< 0x00000F00 */
26699 #define RCC_PLL4CFGR3_PLL4MODDIV                RCC_PLL4CFGR3_PLL4MODDIV_Msk         /*!< PLL4 modulation division frequency adjustment  */
26700 #define RCC_PLL4CFGR3_PLL4MODSPR_Pos            (16U)
26701 #define RCC_PLL4CFGR3_PLL4MODSPR_Msk            (0x1FUL << RCC_PLL4CFGR3_PLL4MODSPR_Pos)  /*!< 0x001F0000 */
26702 #define RCC_PLL4CFGR3_PLL4MODSPR                RCC_PLL4CFGR3_PLL4MODSPR_Msk         /*!< PLL4 modulation spread depth adjustment */
26703 #define RCC_PLL4CFGR3_PLL4PDIV2_Pos             (24U)
26704 #define RCC_PLL4CFGR3_PLL4PDIV2_Msk             (0x7UL << RCC_PLL4CFGR3_PLL4PDIV2_Pos)/*!< 0x07000000 */
26705 #define RCC_PLL4CFGR3_PLL4PDIV2                 RCC_PLL4CFGR3_PLL4PDIV2_Msk          /*!< PLL4 VCO frequency divider level 2 */
26706 #define RCC_PLL4CFGR3_PLL4PDIV1_Pos             (27U)
26707 #define RCC_PLL4CFGR3_PLL4PDIV1_Msk             (0x7UL << RCC_PLL4CFGR3_PLL4PDIV1_Pos)/*!< 0x38000000 */
26708 #define RCC_PLL4CFGR3_PLL4PDIV1                 RCC_PLL4CFGR3_PLL4PDIV1_Msk          /*!< PLL4 VCO frequency divider level 1 */
26709 #define RCC_PLL4CFGR3_PLL4PDIVEN_Pos            (30U)
26710 #define RCC_PLL4CFGR3_PLL4PDIVEN_Msk            (0x1UL << RCC_PLL4CFGR3_PLL4PDIVEN_Pos) /*!< 0x40000000 */
26711 #define RCC_PLL4CFGR3_PLL4PDIVEN                RCC_PLL4CFGR3_PLL4PDIVEN_Msk         /*!< PLL4 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */
26712 
26713 /*****************  Bit definition for RCC_IC1CFGR register  ******************/
26714 #define RCC_IC1CFGR_IC1INT_Pos                  (16U)
26715 #define RCC_IC1CFGR_IC1INT_Msk                  (0xFFUL << RCC_IC1CFGR_IC1INT_Pos)    /*!< 0x00FF0000 */
26716 #define RCC_IC1CFGR_IC1INT                      RCC_IC1CFGR_IC1INT_Msk               /*!< Divider IC1 integer division factor */
26717 #define RCC_IC1CFGR_IC1SEL_Pos                  (28U)
26718 #define RCC_IC1CFGR_IC1SEL_Msk                  (0x3UL << RCC_IC1CFGR_IC1SEL_Pos)     /*!< 0x30000000 */
26719 #define RCC_IC1CFGR_IC1SEL                      RCC_IC1CFGR_IC1SEL_Msk               /*!< Divider IC1 source selection */
26720 #define RCC_IC1CFGR_IC1SEL_0                    (0x1UL << RCC_IC1CFGR_IC1SEL_Pos)    /*!< 0x10000000 */
26721 #define RCC_IC1CFGR_IC1SEL_1                    (0x2UL << RCC_IC1CFGR_IC1SEL_Pos)    /*!< 0x20000000 */
26722 
26723 /*****************  Bit definition for RCC_IC2CFGR register  ******************/
26724 #define RCC_IC2CFGR_IC2INT_Pos                  (16U)
26725 #define RCC_IC2CFGR_IC2INT_Msk                  (0xFFUL << RCC_IC2CFGR_IC2INT_Pos)    /*!< 0x00FF0000 */
26726 #define RCC_IC2CFGR_IC2INT                      RCC_IC2CFGR_IC2INT_Msk               /*!< Divider IC2 integer division factor */
26727 #define RCC_IC2CFGR_IC2SEL_Pos                  (28U)
26728 #define RCC_IC2CFGR_IC2SEL_Msk                  (0x3UL << RCC_IC2CFGR_IC2SEL_Pos)     /*!< 0x30000000 */
26729 #define RCC_IC2CFGR_IC2SEL                      RCC_IC2CFGR_IC2SEL_Msk               /*!< Divider IC2 source selection */
26730 #define RCC_IC2CFGR_IC2SEL_0                    (0x1UL << RCC_IC2CFGR_IC2SEL_Pos)    /*!< 0x10000000 */
26731 #define RCC_IC2CFGR_IC2SEL_1                    (0x2UL << RCC_IC2CFGR_IC2SEL_Pos)    /*!< 0x20000000 */
26732 
26733 /*****************  Bit definition for RCC_IC3CFGR register  ******************/
26734 #define RCC_IC3CFGR_IC3INT_Pos                  (16U)
26735 #define RCC_IC3CFGR_IC3INT_Msk                  (0xFFUL << RCC_IC3CFGR_IC3INT_Pos)    /*!< 0x00FF0000 */
26736 #define RCC_IC3CFGR_IC3INT                      RCC_IC3CFGR_IC3INT_Msk               /*!< Divider IC3 integer division factor */
26737 #define RCC_IC3CFGR_IC3SEL_Pos                  (28U)
26738 #define RCC_IC3CFGR_IC3SEL_Msk                  (0x3UL << RCC_IC3CFGR_IC3SEL_Pos)     /*!< 0x30000000 */
26739 #define RCC_IC3CFGR_IC3SEL                      RCC_IC3CFGR_IC3SEL_Msk               /*!< Divider IC3 source selection */
26740 #define RCC_IC3CFGR_IC3SEL_0                    (0x1UL << RCC_IC3CFGR_IC3SEL_Pos)    /*!< 0x10000000 */
26741 #define RCC_IC3CFGR_IC3SEL_1                    (0x2UL << RCC_IC3CFGR_IC3SEL_Pos)    /*!< 0x20000000 */
26742 
26743 /*****************  Bit definition for RCC_IC4CFGR register  ******************/
26744 #define RCC_IC4CFGR_IC4INT_Pos                  (16U)
26745 #define RCC_IC4CFGR_IC4INT_Msk                  (0xFFUL << RCC_IC4CFGR_IC4INT_Pos)    /*!< 0x00FF0000 */
26746 #define RCC_IC4CFGR_IC4INT                      RCC_IC4CFGR_IC4INT_Msk               /*!< Divider IC4 integer division factor */
26747 #define RCC_IC4CFGR_IC4SEL_Pos                  (28U)
26748 #define RCC_IC4CFGR_IC4SEL_Msk                  (0x3UL << RCC_IC4CFGR_IC4SEL_Pos)     /*!< 0x30000000 */
26749 #define RCC_IC4CFGR_IC4SEL                      RCC_IC4CFGR_IC4SEL_Msk               /*!< Divider IC4 source selection */
26750 #define RCC_IC4CFGR_IC4SEL_0                    (0x1UL << RCC_IC4CFGR_IC4SEL_Pos)    /*!< 0x10000000 */
26751 #define RCC_IC4CFGR_IC4SEL_1                    (0x2UL << RCC_IC4CFGR_IC4SEL_Pos)    /*!< 0x20000000 */
26752 
26753 /*****************  Bit definition for RCC_IC5CFGR register  ******************/
26754 #define RCC_IC5CFGR_IC5INT_Pos                  (16U)
26755 #define RCC_IC5CFGR_IC5INT_Msk                  (0xFFUL << RCC_IC5CFGR_IC5INT_Pos)    /*!< 0x00FF0000 */
26756 #define RCC_IC5CFGR_IC5INT                      RCC_IC5CFGR_IC5INT_Msk               /*!< Divider IC5 integer division factor */
26757 #define RCC_IC5CFGR_IC5SEL_Pos                  (28U)
26758 #define RCC_IC5CFGR_IC5SEL_Msk                  (0x3UL << RCC_IC5CFGR_IC5SEL_Pos)     /*!< 0x30000000 */
26759 #define RCC_IC5CFGR_IC5SEL                      RCC_IC5CFGR_IC5SEL_Msk               /*!< Divider IC5 source selection */
26760 #define RCC_IC5CFGR_IC5SEL_0                    (0x1UL << RCC_IC5CFGR_IC5SEL_Pos)    /*!< 0x10000000 */
26761 #define RCC_IC5CFGR_IC5SEL_1                    (0x2UL << RCC_IC5CFGR_IC5SEL_Pos)    /*!< 0x20000000 */
26762 
26763 /*****************  Bit definition for RCC_IC6CFGR register  ******************/
26764 #define RCC_IC6CFGR_IC6INT_Pos                  (16U)
26765 #define RCC_IC6CFGR_IC6INT_Msk                  (0xFFUL << RCC_IC6CFGR_IC6INT_Pos)    /*!< 0x00FF0000 */
26766 #define RCC_IC6CFGR_IC6INT                      RCC_IC6CFGR_IC6INT_Msk               /*!< Divider IC6 integer division factor */
26767 #define RCC_IC6CFGR_IC6SEL_Pos                  (28U)
26768 #define RCC_IC6CFGR_IC6SEL_Msk                  (0x3UL << RCC_IC6CFGR_IC6SEL_Pos)     /*!< 0x30000000 */
26769 #define RCC_IC6CFGR_IC6SEL                      RCC_IC6CFGR_IC6SEL_Msk               /*!< Divider IC6 source selection */
26770 #define RCC_IC6CFGR_IC6SEL_0                    (0x1UL << RCC_IC6CFGR_IC6SEL_Pos)    /*!< 0x10000000 */
26771 #define RCC_IC6CFGR_IC6SEL_1                    (0x2UL << RCC_IC6CFGR_IC6SEL_Pos)    /*!< 0x20000000 */
26772 
26773 /*****************  Bit definition for RCC_IC7CFGR register  ******************/
26774 #define RCC_IC7CFGR_IC7INT_Pos                  (16U)
26775 #define RCC_IC7CFGR_IC7INT_Msk                  (0xFFUL << RCC_IC7CFGR_IC7INT_Pos)    /*!< 0x00FF0000 */
26776 #define RCC_IC7CFGR_IC7INT                      RCC_IC7CFGR_IC7INT_Msk               /*!< Divider IC7 integer division factor */
26777 #define RCC_IC7CFGR_IC7SEL_Pos                  (28U)
26778 #define RCC_IC7CFGR_IC7SEL_Msk                  (0x3UL << RCC_IC7CFGR_IC7SEL_Pos)     /*!< 0x30000000 */
26779 #define RCC_IC7CFGR_IC7SEL                      RCC_IC7CFGR_IC7SEL_Msk               /*!< Divider IC7 source selection */
26780 #define RCC_IC7CFGR_IC7SEL_0                    (0x1UL << RCC_IC7CFGR_IC7SEL_Pos)    /*!< 0x10000000 */
26781 #define RCC_IC7CFGR_IC7SEL_1                    (0x2UL << RCC_IC7CFGR_IC7SEL_Pos)    /*!< 0x20000000 */
26782 
26783 /*****************  Bit definition for RCC_IC8CFGR register  ******************/
26784 #define RCC_IC8CFGR_IC8INT_Pos                  (16U)
26785 #define RCC_IC8CFGR_IC8INT_Msk                  (0xFFUL << RCC_IC8CFGR_IC8INT_Pos)    /*!< 0x00FF0000 */
26786 #define RCC_IC8CFGR_IC8INT                      RCC_IC8CFGR_IC8INT_Msk               /*!< Divider IC8 integer division factor */
26787 #define RCC_IC8CFGR_IC8SEL_Pos                  (28U)
26788 #define RCC_IC8CFGR_IC8SEL_Msk                  (0x3UL << RCC_IC8CFGR_IC8SEL_Pos)     /*!< 0x30000000 */
26789 #define RCC_IC8CFGR_IC8SEL                      RCC_IC8CFGR_IC8SEL_Msk               /*!< Divider IC8 source selection */
26790 #define RCC_IC8CFGR_IC8SEL_0                    (0x1UL << RCC_IC8CFGR_IC8SEL_Pos)    /*!< 0x10000000 */
26791 #define RCC_IC8CFGR_IC8SEL_1                    (0x2UL << RCC_IC8CFGR_IC8SEL_Pos)    /*!< 0x20000000 */
26792 
26793 /*****************  Bit definition for RCC_IC9CFGR register  ******************/
26794 #define RCC_IC9CFGR_IC9INT_Pos                  (16U)
26795 #define RCC_IC9CFGR_IC9INT_Msk                  (0xFFUL << RCC_IC9CFGR_IC9INT_Pos)    /*!< 0x00FF0000 */
26796 #define RCC_IC9CFGR_IC9INT                      RCC_IC9CFGR_IC9INT_Msk               /*!< Divider IC9 integer division factor */
26797 #define RCC_IC9CFGR_IC9SEL_Pos                  (28U)
26798 #define RCC_IC9CFGR_IC9SEL_Msk                  (0x3UL << RCC_IC9CFGR_IC9SEL_Pos)     /*!< 0x30000000 */
26799 #define RCC_IC9CFGR_IC9SEL                      RCC_IC9CFGR_IC9SEL_Msk               /*!< Divider IC9 source selection */
26800 #define RCC_IC9CFGR_IC9SEL_0                    (0x1UL << RCC_IC9CFGR_IC9SEL_Pos)    /*!< 0x10000000 */
26801 #define RCC_IC9CFGR_IC9SEL_1                    (0x2UL << RCC_IC9CFGR_IC9SEL_Pos)    /*!< 0x20000000 */
26802 
26803 /*****************  Bit definition for RCC_IC10CFGR register  *****************/
26804 #define RCC_IC10CFGR_IC10INT_Pos                (16U)
26805 #define RCC_IC10CFGR_IC10INT_Msk                (0xFFUL << RCC_IC10CFGR_IC10INT_Pos)  /*!< 0x00FF0000 */
26806 #define RCC_IC10CFGR_IC10INT                    RCC_IC10CFGR_IC10INT_Msk             /*!< Divider IC10 integer division factor */
26807 #define RCC_IC10CFGR_IC10SEL_Pos                (28U)
26808 #define RCC_IC10CFGR_IC10SEL_Msk                (0x3UL << RCC_IC10CFGR_IC10SEL_Pos)   /*!< 0x30000000 */
26809 #define RCC_IC10CFGR_IC10SEL                    RCC_IC10CFGR_IC10SEL_Msk             /*!< Divider IC10 source selection */
26810 #define RCC_IC10CFGR_IC10SEL_0                  (0x1UL << RCC_IC10CFGR_IC10SEL_Pos)  /*!< 0x10000000 */
26811 #define RCC_IC10CFGR_IC10SEL_1                  (0x2UL << RCC_IC10CFGR_IC10SEL_Pos)  /*!< 0x20000000 */
26812 
26813 /*****************  Bit definition for RCC_IC11CFGR register  *****************/
26814 #define RCC_IC11CFGR_IC11INT_Pos                (16U)
26815 #define RCC_IC11CFGR_IC11INT_Msk                (0xFFUL << RCC_IC11CFGR_IC11INT_Pos)  /*!< 0x00FF0000 */
26816 #define RCC_IC11CFGR_IC11INT                    RCC_IC11CFGR_IC11INT_Msk             /*!< Divider IC11 integer division factor */
26817 #define RCC_IC11CFGR_IC11SEL_Pos                (28U)
26818 #define RCC_IC11CFGR_IC11SEL_Msk                (0x3UL << RCC_IC11CFGR_IC11SEL_Pos)   /*!< 0x30000000 */
26819 #define RCC_IC11CFGR_IC11SEL                    RCC_IC11CFGR_IC11SEL_Msk             /*!< Divider IC11 source selection */
26820 #define RCC_IC11CFGR_IC11SEL_0                  (0x1UL << RCC_IC11CFGR_IC11SEL_Pos)  /*!< 0x10000000 */
26821 #define RCC_IC11CFGR_IC11SEL_1                  (0x2UL << RCC_IC11CFGR_IC11SEL_Pos)  /*!< 0x20000000 */
26822 
26823 /*****************  Bit definition for RCC_IC12CFGR register  *****************/
26824 #define RCC_IC12CFGR_IC12INT_Pos                (16U)
26825 #define RCC_IC12CFGR_IC12INT_Msk                (0xFFUL << RCC_IC12CFGR_IC12INT_Pos)  /*!< 0x00FF0000 */
26826 #define RCC_IC12CFGR_IC12INT                    RCC_IC12CFGR_IC12INT_Msk             /*!< Divider IC12 integer division factor */
26827 #define RCC_IC12CFGR_IC12SEL_Pos                (28U)
26828 #define RCC_IC12CFGR_IC12SEL_Msk                (0x3UL << RCC_IC12CFGR_IC12SEL_Pos)   /*!< 0x30000000 */
26829 #define RCC_IC12CFGR_IC12SEL                    RCC_IC12CFGR_IC12SEL_Msk             /*!< Divider IC12 source selection */
26830 #define RCC_IC12CFGR_IC12SEL_0                  (0x1UL << RCC_IC12CFGR_IC12SEL_Pos)  /*!< 0x10000000 */
26831 #define RCC_IC12CFGR_IC12SEL_1                  (0x2UL << RCC_IC12CFGR_IC12SEL_Pos)  /*!< 0x20000000 */
26832 
26833 /*****************  Bit definition for RCC_IC13CFGR register  *****************/
26834 #define RCC_IC13CFGR_IC13INT_Pos                (16U)
26835 #define RCC_IC13CFGR_IC13INT_Msk                (0xFFUL << RCC_IC13CFGR_IC13INT_Pos)  /*!< 0x00FF0000 */
26836 #define RCC_IC13CFGR_IC13INT                    RCC_IC13CFGR_IC13INT_Msk             /*!< Divider IC13 integer division factor */
26837 #define RCC_IC13CFGR_IC13SEL_Pos                (28U)
26838 #define RCC_IC13CFGR_IC13SEL_Msk                (0x3UL << RCC_IC13CFGR_IC13SEL_Pos)   /*!< 0x30000000 */
26839 #define RCC_IC13CFGR_IC13SEL                    RCC_IC13CFGR_IC13SEL_Msk             /*!< Divider IC13 source selection */
26840 #define RCC_IC13CFGR_IC13SEL_0                  (0x1UL << RCC_IC13CFGR_IC13SEL_Pos)  /*!< 0x10000000 */
26841 #define RCC_IC13CFGR_IC13SEL_1                  (0x2UL << RCC_IC13CFGR_IC13SEL_Pos)  /*!< 0x20000000 */
26842 
26843 /*****************  Bit definition for RCC_IC14CFGR register  *****************/
26844 #define RCC_IC14CFGR_IC14INT_Pos                (16U)
26845 #define RCC_IC14CFGR_IC14INT_Msk                (0xFFUL << RCC_IC14CFGR_IC14INT_Pos)  /*!< 0x00FF0000 */
26846 #define RCC_IC14CFGR_IC14INT                    RCC_IC14CFGR_IC14INT_Msk             /*!< Divider IC14 integer division factor */
26847 #define RCC_IC14CFGR_IC14SEL_Pos                (28U)
26848 #define RCC_IC14CFGR_IC14SEL_Msk                (0x3UL << RCC_IC14CFGR_IC14SEL_Pos)   /*!< 0x30000000 */
26849 #define RCC_IC14CFGR_IC14SEL                    RCC_IC14CFGR_IC14SEL_Msk             /*!< Divider IC14 source selection */
26850 #define RCC_IC14CFGR_IC14SEL_0                  (0x1UL << RCC_IC14CFGR_IC14SEL_Pos)  /*!< 0x10000000 */
26851 #define RCC_IC14CFGR_IC14SEL_1                  (0x2UL << RCC_IC14CFGR_IC14SEL_Pos)  /*!< 0x20000000 */
26852 
26853 /*****************  Bit definition for RCC_IC15CFGR register  *****************/
26854 #define RCC_IC15CFGR_IC15INT_Pos                (16U)
26855 #define RCC_IC15CFGR_IC15INT_Msk                (0xFFUL << RCC_IC15CFGR_IC15INT_Pos)  /*!< 0x00FF0000 */
26856 #define RCC_IC15CFGR_IC15INT                    RCC_IC15CFGR_IC15INT_Msk             /*!< Divider IC15 integer division factor */
26857 #define RCC_IC15CFGR_IC15SEL_Pos                (28U)
26858 #define RCC_IC15CFGR_IC15SEL_Msk                (0x3UL << RCC_IC15CFGR_IC15SEL_Pos)   /*!< 0x30000000 */
26859 #define RCC_IC15CFGR_IC15SEL                    RCC_IC15CFGR_IC15SEL_Msk             /*!< Divider IC15 source selection */
26860 #define RCC_IC15CFGR_IC15SEL_0                  (0x1UL << RCC_IC15CFGR_IC15SEL_Pos)  /*!< 0x10000000 */
26861 #define RCC_IC15CFGR_IC15SEL_1                  (0x2UL << RCC_IC15CFGR_IC15SEL_Pos)  /*!< 0x20000000 */
26862 
26863 /*****************  Bit definition for RCC_IC16CFGR register  *****************/
26864 #define RCC_IC16CFGR_IC16INT_Pos                (16U)
26865 #define RCC_IC16CFGR_IC16INT_Msk                (0xFFUL << RCC_IC16CFGR_IC16INT_Pos)  /*!< 0x00FF0000 */
26866 #define RCC_IC16CFGR_IC16INT                    RCC_IC16CFGR_IC16INT_Msk             /*!< Divider IC16 integer division factor */
26867 #define RCC_IC16CFGR_IC16SEL_Pos                (28U)
26868 #define RCC_IC16CFGR_IC16SEL_Msk                (0x3UL << RCC_IC16CFGR_IC16SEL_Pos)   /*!< 0x30000000 */
26869 #define RCC_IC16CFGR_IC16SEL                    RCC_IC16CFGR_IC16SEL_Msk             /*!< Divider IC16 source selection */
26870 #define RCC_IC16CFGR_IC16SEL_0                  (0x1UL << RCC_IC16CFGR_IC16SEL_Pos)  /*!< 0x10000000 */
26871 #define RCC_IC16CFGR_IC16SEL_1                  (0x2UL << RCC_IC16CFGR_IC16SEL_Pos)  /*!< 0x20000000 */
26872 
26873 /*****************  Bit definition for RCC_IC17CFGR register  *****************/
26874 #define RCC_IC17CFGR_IC17INT_Pos                (16U)
26875 #define RCC_IC17CFGR_IC17INT_Msk                (0xFFUL << RCC_IC17CFGR_IC17INT_Pos)  /*!< 0x00FF0000 */
26876 #define RCC_IC17CFGR_IC17INT                    RCC_IC17CFGR_IC17INT_Msk             /*!< Divider IC17 integer division factor */
26877 #define RCC_IC17CFGR_IC17SEL_Pos                (28U)
26878 #define RCC_IC17CFGR_IC17SEL_Msk                (0x3UL << RCC_IC17CFGR_IC17SEL_Pos)   /*!< 0x30000000 */
26879 #define RCC_IC17CFGR_IC17SEL                    RCC_IC17CFGR_IC17SEL_Msk             /*!< Divider IC17 source selection */
26880 #define RCC_IC17CFGR_IC17SEL_0                  (0x1UL << RCC_IC17CFGR_IC17SEL_Pos)  /*!< 0x10000000 */
26881 #define RCC_IC17CFGR_IC17SEL_1                  (0x2UL << RCC_IC17CFGR_IC17SEL_Pos)  /*!< 0x20000000 */
26882 
26883 /*****************  Bit definition for RCC_IC18CFGR register  *****************/
26884 #define RCC_IC18CFGR_IC18INT_Pos                (16U)
26885 #define RCC_IC18CFGR_IC18INT_Msk                (0xFFUL << RCC_IC18CFGR_IC18INT_Pos)  /*!< 0x00FF0000 */
26886 #define RCC_IC18CFGR_IC18INT                    RCC_IC18CFGR_IC18INT_Msk             /*!< Divider IC18 integer division factor */
26887 #define RCC_IC18CFGR_IC18SEL_Pos                (28U)
26888 #define RCC_IC18CFGR_IC18SEL_Msk                (0x3UL << RCC_IC18CFGR_IC18SEL_Pos)   /*!< 0x30000000 */
26889 #define RCC_IC18CFGR_IC18SEL                    RCC_IC18CFGR_IC18SEL_Msk             /*!< Divider IC18 source selection */
26890 #define RCC_IC18CFGR_IC18SEL_0                  (0x1UL << RCC_IC18CFGR_IC18SEL_Pos)  /*!< 0x10000000 */
26891 #define RCC_IC18CFGR_IC18SEL_1                  (0x2UL << RCC_IC18CFGR_IC18SEL_Pos)  /*!< 0x20000000 */
26892 
26893 /*****************  Bit definition for RCC_IC19CFGR register  *****************/
26894 #define RCC_IC19CFGR_IC19INT_Pos                (16U)
26895 #define RCC_IC19CFGR_IC19INT_Msk                (0xFFUL << RCC_IC19CFGR_IC19INT_Pos)  /*!< 0x00FF0000 */
26896 #define RCC_IC19CFGR_IC19INT                    RCC_IC19CFGR_IC19INT_Msk             /*!< Divider IC19 integer division factor */
26897 #define RCC_IC19CFGR_IC19SEL_Pos                (28U)
26898 #define RCC_IC19CFGR_IC19SEL_Msk                (0x3UL << RCC_IC19CFGR_IC19SEL_Pos)   /*!< 0x30000000 */
26899 #define RCC_IC19CFGR_IC19SEL                    RCC_IC19CFGR_IC19SEL_Msk             /*!< Divider IC19 source selection */
26900 #define RCC_IC19CFGR_IC19SEL_0                  (0x1UL << RCC_IC19CFGR_IC19SEL_Pos)  /*!< 0x10000000 */
26901 #define RCC_IC19CFGR_IC19SEL_1                  (0x2UL << RCC_IC19CFGR_IC19SEL_Pos)  /*!< 0x20000000 */
26902 
26903 /*****************  Bit definition for RCC_IC20CFGR register  *****************/
26904 #define RCC_IC20CFGR_IC20INT_Pos                (16U)
26905 #define RCC_IC20CFGR_IC20INT_Msk                (0xFFUL << RCC_IC20CFGR_IC20INT_Pos)  /*!< 0x00FF0000 */
26906 #define RCC_IC20CFGR_IC20INT                    RCC_IC20CFGR_IC20INT_Msk             /*!< Divider IC20 integer division factor */
26907 #define RCC_IC20CFGR_IC20SEL_Pos                (28U)
26908 #define RCC_IC20CFGR_IC20SEL_Msk                (0x3UL << RCC_IC20CFGR_IC20SEL_Pos)   /*!< 0x30000000 */
26909 #define RCC_IC20CFGR_IC20SEL                    RCC_IC20CFGR_IC20SEL_Msk             /*!< Divider IC20 source selection */
26910 #define RCC_IC20CFGR_IC20SEL_0                  (0x1UL << RCC_IC20CFGR_IC20SEL_Pos)  /*!< 0x10000000 */
26911 #define RCC_IC20CFGR_IC20SEL_1                  (0x2UL << RCC_IC20CFGR_IC20SEL_Pos)  /*!< 0x20000000 */
26912 
26913 /*******************  Bit definition for RCC_CIER register  *******************/
26914 #define RCC_CIER_LSIRDYIE_Pos                   (0U)
26915 #define RCC_CIER_LSIRDYIE_Msk                   (0x1UL << RCC_CIER_LSIRDYIE_Pos)      /*!< 0x00000001 */
26916 #define RCC_CIER_LSIRDYIE                       RCC_CIER_LSIRDYIE_Msk                /*!< LSI ready interrupt enable */
26917 #define RCC_CIER_LSERDYIE_Pos                   (1U)
26918 #define RCC_CIER_LSERDYIE_Msk                   (0x1UL << RCC_CIER_LSERDYIE_Pos)      /*!< 0x00000002 */
26919 #define RCC_CIER_LSERDYIE                       RCC_CIER_LSERDYIE_Msk                /*!< LSE ready interrupt enable */
26920 #define RCC_CIER_MSIRDYIE_Pos                   (2U)
26921 #define RCC_CIER_MSIRDYIE_Msk                   (0x1UL << RCC_CIER_MSIRDYIE_Pos)      /*!< 0x00000004 */
26922 #define RCC_CIER_MSIRDYIE                       RCC_CIER_MSIRDYIE_Msk                /*!< MSI ready interrupt enable */
26923 #define RCC_CIER_HSIRDYIE_Pos                   (3U)
26924 #define RCC_CIER_HSIRDYIE_Msk                   (0x1UL << RCC_CIER_HSIRDYIE_Pos)      /*!< 0x00000008 */
26925 #define RCC_CIER_HSIRDYIE                       RCC_CIER_HSIRDYIE_Msk                /*!< HSI ready interrupt enable */
26926 #define RCC_CIER_HSERDYIE_Pos                   (4U)
26927 #define RCC_CIER_HSERDYIE_Msk                   (0x1UL << RCC_CIER_HSERDYIE_Pos)      /*!< 0x00000010 */
26928 #define RCC_CIER_HSERDYIE                       RCC_CIER_HSERDYIE_Msk                /*!< HSE ready interrupt enable */
26929 #define RCC_CIER_PLL1RDYIE_Pos                  (8U)
26930 #define RCC_CIER_PLL1RDYIE_Msk                  (0x1UL << RCC_CIER_PLL1RDYIE_Pos)     /*!< 0x00000100 */
26931 #define RCC_CIER_PLL1RDYIE                      RCC_CIER_PLL1RDYIE_Msk               /*!< PLL1 ready interrupt enable */
26932 #define RCC_CIER_PLL2RDYIE_Pos                  (9U)
26933 #define RCC_CIER_PLL2RDYIE_Msk                  (0x1UL << RCC_CIER_PLL2RDYIE_Pos)     /*!< 0x00000200 */
26934 #define RCC_CIER_PLL2RDYIE                      RCC_CIER_PLL2RDYIE_Msk               /*!< PLL2 ready interrupt enable */
26935 #define RCC_CIER_PLL3RDYIE_Pos                  (10U)
26936 #define RCC_CIER_PLL3RDYIE_Msk                  (0x1UL << RCC_CIER_PLL3RDYIE_Pos)     /*!< 0x00000400 */
26937 #define RCC_CIER_PLL3RDYIE                      RCC_CIER_PLL3RDYIE_Msk               /*!< PLL3 ready interrupt enable */
26938 #define RCC_CIER_PLL4RDYIE_Pos                  (11U)
26939 #define RCC_CIER_PLL4RDYIE_Msk                  (0x1UL << RCC_CIER_PLL4RDYIE_Pos)     /*!< 0x00000800 */
26940 #define RCC_CIER_PLL4RDYIE                      RCC_CIER_PLL4RDYIE_Msk               /*!< PLL4 ready interrupt enable */
26941 #define RCC_CIER_LSECSSIE_Pos                   (16U)
26942 #define RCC_CIER_LSECSSIE_Msk                   (0x1UL << RCC_CIER_LSECSSIE_Pos)      /*!< 0x00010000 */
26943 #define RCC_CIER_LSECSSIE                       RCC_CIER_LSECSSIE_Msk                /*!< LSE CSS interrupt enable */
26944 #define RCC_CIER_HSECSSIE_Pos                   (17U)
26945 #define RCC_CIER_HSECSSIE_Msk                   (0x1UL << RCC_CIER_HSECSSIE_Pos)      /*!< 0x00020000 */
26946 #define RCC_CIER_HSECSSIE                       RCC_CIER_HSECSSIE_Msk                /*!< HSE CSS interrupt enable */
26947 #define RCC_CIER_WKUPIE_Pos                     (24U)
26948 #define RCC_CIER_WKUPIE_Msk                     (0x1UL << RCC_CIER_WKUPIE_Pos)        /*!< 0x01000000 */
26949 #define RCC_CIER_WKUPIE                         RCC_CIER_WKUPIE_Msk                  /*!< CPU wake-up from Stop interrupt enable */
26950 
26951 /*******************  Bit definition for RCC_CIFR register  *******************/
26952 #define RCC_CIFR_LSIRDYF_Pos                    (0U)
26953 #define RCC_CIFR_LSIRDYF_Msk                    (0x1UL << RCC_CIFR_LSIRDYF_Pos)       /*!< 0x00000001 */
26954 #define RCC_CIFR_LSIRDYF                        RCC_CIFR_LSIRDYF_Msk                 /*!< LSI ready interrupt flag */
26955 #define RCC_CIFR_LSERDYF_Pos                    (1U)
26956 #define RCC_CIFR_LSERDYF_Msk                    (0x1UL << RCC_CIFR_LSERDYF_Pos)       /*!< 0x00000002 */
26957 #define RCC_CIFR_LSERDYF                        RCC_CIFR_LSERDYF_Msk                 /*!< LSE ready interrupt flag */
26958 #define RCC_CIFR_MSIRDYF_Pos                    (2U)
26959 #define RCC_CIFR_MSIRDYF_Msk                    (0x1UL << RCC_CIFR_MSIRDYF_Pos)       /*!< 0x00000004 */
26960 #define RCC_CIFR_MSIRDYF                        RCC_CIFR_MSIRDYF_Msk                 /*!< MSI ready interrupt flag */
26961 #define RCC_CIFR_HSIRDYF_Pos                    (3U)
26962 #define RCC_CIFR_HSIRDYF_Msk                    (0x1UL << RCC_CIFR_HSIRDYF_Pos)       /*!< 0x00000008 */
26963 #define RCC_CIFR_HSIRDYF                        RCC_CIFR_HSIRDYF_Msk                 /*!< HSI ready interrupt flag */
26964 #define RCC_CIFR_HSERDYF_Pos                    (4U)
26965 #define RCC_CIFR_HSERDYF_Msk                    (0x1UL << RCC_CIFR_HSERDYF_Pos)       /*!< 0x00000010 */
26966 #define RCC_CIFR_HSERDYF                        RCC_CIFR_HSERDYF_Msk                 /*!< HSE ready interrupt flag */
26967 #define RCC_CIFR_PLL1RDYF_Pos                   (8U)
26968 #define RCC_CIFR_PLL1RDYF_Msk                   (0x1UL << RCC_CIFR_PLL1RDYF_Pos)      /*!< 0x00000100 */
26969 #define RCC_CIFR_PLL1RDYF                       RCC_CIFR_PLL1RDYF_Msk                /*!< PLL1 ready interrupt flag */
26970 #define RCC_CIFR_PLL2RDYF_Pos                   (9U)
26971 #define RCC_CIFR_PLL2RDYF_Msk                   (0x1UL << RCC_CIFR_PLL2RDYF_Pos)      /*!< 0x00000200 */
26972 #define RCC_CIFR_PLL2RDYF                       RCC_CIFR_PLL2RDYF_Msk                /*!< PLL2 ready interrupt flag */
26973 #define RCC_CIFR_PLL3RDYF_Pos                   (10U)
26974 #define RCC_CIFR_PLL3RDYF_Msk                   (0x1UL << RCC_CIFR_PLL3RDYF_Pos)      /*!< 0x00000400 */
26975 #define RCC_CIFR_PLL3RDYF                       RCC_CIFR_PLL3RDYF_Msk                /*!< PLL3 ready interrupt flag */
26976 #define RCC_CIFR_PLL4RDYF_Pos                   (11U)
26977 #define RCC_CIFR_PLL4RDYF_Msk                   (0x1UL << RCC_CIFR_PLL4RDYF_Pos)      /*!< 0x00000800 */
26978 #define RCC_CIFR_PLL4RDYF                       RCC_CIFR_PLL4RDYF_Msk                /*!< PLL4 ready interrupt flag */
26979 #define RCC_CIFR_LSECSSF_Pos                    (16U)
26980 #define RCC_CIFR_LSECSSF_Msk                    (0x1UL << RCC_CIFR_LSECSSF_Pos)       /*!< 0x00010000 */
26981 #define RCC_CIFR_LSECSSF                        RCC_CIFR_LSECSSF_Msk                 /*!< LSE ready interrupt flag */
26982 #define RCC_CIFR_HSECSSF_Pos                    (17U)
26983 #define RCC_CIFR_HSECSSF_Msk                    (0x1UL << RCC_CIFR_HSECSSF_Pos)       /*!< 0x00020000 */
26984 #define RCC_CIFR_HSECSSF                        RCC_CIFR_HSECSSF_Msk                 /*!< HSE ready interrupt flag */
26985 #define RCC_CIFR_WKUPF_Pos                      (24U)
26986 #define RCC_CIFR_WKUPF_Msk                      (0x1UL << RCC_CIFR_WKUPF_Pos)         /*!< 0x01000000 */
26987 #define RCC_CIFR_WKUPF                          RCC_CIFR_WKUPF_Msk                   /*!< CPU wake-up from Stop interrupt flag */
26988 
26989 /*******************  Bit definition for RCC_CICR register  *******************/
26990 #define RCC_CICR_LSIRDYC_Pos                    (0U)
26991 #define RCC_CICR_LSIRDYC_Msk                    (0x1UL << RCC_CICR_LSIRDYC_Pos)       /*!< 0x00000001 */
26992 #define RCC_CICR_LSIRDYC                        RCC_CICR_LSIRDYC_Msk                 /*!< LSI ready interrupt clear */
26993 #define RCC_CICR_LSERDYC_Pos                    (1U)
26994 #define RCC_CICR_LSERDYC_Msk                    (0x1UL << RCC_CICR_LSERDYC_Pos)       /*!< 0x00000002 */
26995 #define RCC_CICR_LSERDYC                        RCC_CICR_LSERDYC_Msk                 /*!< LSE ready interrupt clear */
26996 #define RCC_CICR_MSIRDYC_Pos                    (2U)
26997 #define RCC_CICR_MSIRDYC_Msk                    (0x1UL << RCC_CICR_MSIRDYC_Pos)       /*!< 0x00000004 */
26998 #define RCC_CICR_MSIRDYC                        RCC_CICR_MSIRDYC_Msk                 /*!< MSI ready interrupt clear */
26999 #define RCC_CICR_HSIRDYC_Pos                    (3U)
27000 #define RCC_CICR_HSIRDYC_Msk                    (0x1UL << RCC_CICR_HSIRDYC_Pos)       /*!< 0x00000008 */
27001 #define RCC_CICR_HSIRDYC                        RCC_CICR_HSIRDYC_Msk                 /*!< HSI ready interrupt clear */
27002 #define RCC_CICR_HSERDYC_Pos                    (4U)
27003 #define RCC_CICR_HSERDYC_Msk                    (0x1UL << RCC_CICR_HSERDYC_Pos)       /*!< 0x00000010 */
27004 #define RCC_CICR_HSERDYC                        RCC_CICR_HSERDYC_Msk                 /*!< HSE ready interrupt clear */
27005 #define RCC_CICR_PLL1RDYC_Pos                   (8U)
27006 #define RCC_CICR_PLL1RDYC_Msk                   (0x1UL << RCC_CICR_PLL1RDYC_Pos)      /*!< 0x00000100 */
27007 #define RCC_CICR_PLL1RDYC                       RCC_CICR_PLL1RDYC_Msk                /*!< PLL1 ready interrupt clear */
27008 #define RCC_CICR_PLL2RDYC_Pos                   (9U)
27009 #define RCC_CICR_PLL2RDYC_Msk                   (0x1UL << RCC_CICR_PLL2RDYC_Pos)      /*!< 0x00000200 */
27010 #define RCC_CICR_PLL2RDYC                       RCC_CICR_PLL2RDYC_Msk                /*!< PLL2 ready interrupt clear */
27011 #define RCC_CICR_PLL3RDYC_Pos                   (10U)
27012 #define RCC_CICR_PLL3RDYC_Msk                   (0x1UL << RCC_CICR_PLL3RDYC_Pos)      /*!< 0x00000400 */
27013 #define RCC_CICR_PLL3RDYC                       RCC_CICR_PLL3RDYC_Msk                /*!< PLL3 ready interrupt clear */
27014 #define RCC_CICR_PLL4RDYC_Pos                   (11U)
27015 #define RCC_CICR_PLL4RDYC_Msk                   (0x1UL << RCC_CICR_PLL4RDYC_Pos)      /*!< 0x00000800 */
27016 #define RCC_CICR_PLL4RDYC                       RCC_CICR_PLL4RDYC_Msk                /*!< PLL4 ready interrupt clear */
27017 #define RCC_CICR_LSECSSC_Pos                    (16U)
27018 #define RCC_CICR_LSECSSC_Msk                    (0x1UL << RCC_CICR_LSECSSC_Pos)       /*!< 0x00010000 */
27019 #define RCC_CICR_LSECSSC                        RCC_CICR_LSECSSC_Msk                 /*!< LSE ready interrupt clear */
27020 #define RCC_CICR_HSECSSC_Pos                    (17U)
27021 #define RCC_CICR_HSECSSC_Msk                    (0x1UL << RCC_CICR_HSECSSC_Pos)       /*!< 0x00020000 */
27022 #define RCC_CICR_HSECSSC                        RCC_CICR_HSECSSC_Msk                 /*!< HSE ready interrupt clear */
27023 #define RCC_CICR_WKUPFC_Pos                     (24U)
27024 #define RCC_CICR_WKUPFC_Msk                     (0x1UL << RCC_CICR_WKUPFC_Pos)        /*!< 0x01000000 */
27025 #define RCC_CICR_WKUPFC                         RCC_CICR_WKUPFC_Msk                  /*!< CPU wake-up ready interrupt clear */
27026 
27027 /******************  Bit definition for RCC_CCIPR1 register  ******************/
27028 #define RCC_CCIPR1_ADF1SEL_Pos                  (0U)
27029 #define RCC_CCIPR1_ADF1SEL_Msk                  (0x7UL << RCC_CCIPR1_ADF1SEL_Pos)                  /*!< 0x00000007 */
27030 #define RCC_CCIPR1_ADF1SEL                      RCC_CCIPR1_ADF1SEL_Msk                            /*!< Source selection for the ADF1 kernel clock */
27031 #define RCC_CCIPR1_ADF1SEL_0                    (0x1UL << RCC_CCIPR1_ADF1SEL_Pos)                  /*!< 0x00000001 */
27032 #define RCC_CCIPR1_ADF1SEL_1                    (0x2UL << RCC_CCIPR1_ADF1SEL_Pos)                  /*!< 0x00000002 */
27033 #define RCC_CCIPR1_ADF1SEL_2                    (0x4UL << RCC_CCIPR1_ADF1SEL_Pos)                  /*!< 0x00000004 */
27034 #define RCC_CCIPR1_ADC12SEL_Pos                 (4U)
27035 #define RCC_CCIPR1_ADC12SEL_Msk                 (0x7UL << RCC_CCIPR1_ADC12SEL_Pos)                 /*!< 0x00000070 */
27036 #define RCC_CCIPR1_ADC12SEL                     RCC_CCIPR1_ADC12SEL_Msk                           /*!< Source selection for the ADC12 kernel clock */
27037 #define RCC_CCIPR1_ADC12SEL_0                   (0x1UL << RCC_CCIPR1_ADC12SEL_Pos)                /*!< 0x00000010 */
27038 #define RCC_CCIPR1_ADC12SEL_1                   (0x2UL << RCC_CCIPR1_ADC12SEL_Pos)                /*!< 0x00000020 */
27039 #define RCC_CCIPR1_ADC12SEL_2                   (0x4UL << RCC_CCIPR1_ADC12SEL_Pos)                /*!< 0x00000040 */
27040 #define RCC_CCIPR1_ADCPRE_Pos                   (8U)
27041 #define RCC_CCIPR1_ADCPRE_Msk                   (0xFFUL << RCC_CCIPR1_ADCPRE_Pos)                  /*!< 0x0000FF00 */
27042 #define RCC_CCIPR1_ADCPRE                       RCC_CCIPR1_ADCPRE_Msk                             /*!< ADC12 Bus Slave clock divider selection (for clock ck_icn_s_vencram) */
27043 #define RCC_CCIPR1_ADCPRE_0                     (0x1UL << RCC_CCIPR1_ADCPRE_Pos)                 /*!< 0x00000100 */
27044 #define RCC_CCIPR1_ADCPRE_1                     (0x2UL << RCC_CCIPR1_ADCPRE_Pos)                 /*!< 0x00000200 */
27045 #define RCC_CCIPR1_ADCPRE_2                     (0x4UL << RCC_CCIPR1_ADCPRE_Pos)                 /*!< 0x00000400 */
27046 #define RCC_CCIPR1_ADCPRE_3                     (0x8UL << RCC_CCIPR1_ADCPRE_Pos)                 /*!< 0x00000800 */
27047 #define RCC_CCIPR1_ADCPRE_4                     (0x10UL << RCC_CCIPR1_ADCPRE_Pos)                /*!< 0x00001000 */
27048 #define RCC_CCIPR1_ADCPRE_5                     (0x20UL << RCC_CCIPR1_ADCPRE_Pos)                /*!< 0x00002000 */
27049 #define RCC_CCIPR1_ADCPRE_6                     (0x40UL << RCC_CCIPR1_ADCPRE_Pos)                /*!< 0x00004000 */
27050 #define RCC_CCIPR1_ADCPRE_7                     (0x80UL << RCC_CCIPR1_ADCPRE_Pos)                /*!< 0x00008000 */
27051 #define RCC_CCIPR1_DCMIPPSEL_Pos                (20U)
27052 #define RCC_CCIPR1_DCMIPPSEL_Msk                (0x3UL << RCC_CCIPR1_DCMIPPSEL_Pos)                /*!< 0x00300000 */
27053 #define RCC_CCIPR1_DCMIPPSEL                    RCC_CCIPR1_DCMIPPSEL_Msk                          /*!< Source selection for the DCMIPP kernel clock */
27054 #define RCC_CCIPR1_DCMIPPSEL_0                  (0x1UL << RCC_CCIPR1_DCMIPPSEL_Pos)           /*!< 0x00100000 */
27055 #define RCC_CCIPR1_DCMIPPSEL_1                  (0x2UL << RCC_CCIPR1_DCMIPPSEL_Pos)           /*!< 0x00200000 */
27056 
27057 /******************  Bit definition for RCC_CCIPR2 register  ******************/
27058 #define RCC_CCIPR2_ETH1PTPSEL_Pos               (0U)
27059 #define RCC_CCIPR2_ETH1PTPSEL_Msk               (0x3UL << RCC_CCIPR2_ETH1PTPSEL_Pos)               /*!< 0x00000003 */
27060 #define RCC_CCIPR2_ETH1PTPSEL                   RCC_CCIPR2_ETH1PTPSEL_Msk                         /*!< Source selection for the ETH1 kernel clock */
27061 #define RCC_CCIPR2_ETH1PTPSEL_0                 (0x1UL << RCC_CCIPR2_ETH1PTPSEL_Pos)               /*!< 0x00000001 */
27062 #define RCC_CCIPR2_ETH1PTPSEL_1                 (0x2UL << RCC_CCIPR2_ETH1PTPSEL_Pos)               /*!< 0x00000002 */
27063 #define RCC_CCIPR2_ETH1PTPDIV_Pos               (4U)
27064 #define RCC_CCIPR2_ETH1PTPDIV_Msk               (0xFUL << RCC_CCIPR2_ETH1PTPDIV_Pos)               /*!< 0x000000F0 */
27065 #define RCC_CCIPR2_ETH1PTPDIV                   RCC_CCIPR2_ETH1PTPDIV_Msk                         /*!< ETH1 Kernel clock divider selection (for clock ck_ker_eth1ptp) */
27066 #define RCC_CCIPR2_ETH1PTPDIV_0                 (0x1UL << RCC_CCIPR2_ETH1PTPDIV_Pos)              /*!< 0x00000010 */
27067 #define RCC_CCIPR2_ETH1PTPDIV_1                 (0x2UL << RCC_CCIPR2_ETH1PTPDIV_Pos)              /*!< 0x00000020 */
27068 #define RCC_CCIPR2_ETH1PTPDIV_2                 (0x4UL << RCC_CCIPR2_ETH1PTPDIV_Pos)              /*!< 0x00000040 */
27069 #define RCC_CCIPR2_ETH1PTPDIV_3                 (0x8UL << RCC_CCIPR2_ETH1PTPDIV_Pos)              /*!< 0x00000080 */
27070 #define RCC_CCIPR2_ETH1PWRDOWNACK_Pos           (8U)
27071 #define RCC_CCIPR2_ETH1PWRDOWNACK_Msk           (0x1UL << RCC_CCIPR2_ETH1PWRDOWNACK_Pos)           /*!< 0x00000100 */
27072 #define RCC_CCIPR2_ETH1PWRDOWNACK               RCC_CCIPR2_ETH1PWRDOWNACK_Msk                     /*!< Set and reset by software */
27073 #define RCC_CCIPR2_ETH1CLKSEL_Pos               (12U)
27074 #define RCC_CCIPR2_ETH1CLKSEL_Msk               (0x3UL << RCC_CCIPR2_ETH1CLKSEL_Pos)               /*!< 0x00003000 */
27075 #define RCC_CCIPR2_ETH1CLKSEL                   RCC_CCIPR2_ETH1CLKSEL_Msk                         /*!< Source selection for the ETH1 kernel clock */
27076 #define RCC_CCIPR2_ETH1CLKSEL_0                 (0x1UL << RCC_CCIPR2_ETH1CLKSEL_Pos)            /*!< 0x00001000 */
27077 #define RCC_CCIPR2_ETH1CLKSEL_1                 (0x2UL << RCC_CCIPR2_ETH1CLKSEL_Pos)            /*!< 0x00002000 */
27078 #define RCC_CCIPR2_ETH1SEL_Pos                  (16U)
27079 #define RCC_CCIPR2_ETH1SEL_Msk                  (0x7UL << RCC_CCIPR2_ETH1SEL_Pos)                  /*!< 0x00070000 */
27080 #define RCC_CCIPR2_ETH1SEL                      RCC_CCIPR2_ETH1SEL_Msk                            /*!< Set and reset by software */
27081 #define RCC_CCIPR2_ETH1SEL_0                    (0x1UL << RCC_CCIPR2_ETH1SEL_Pos)              /*!< 0x00010000 */
27082 #define RCC_CCIPR2_ETH1SEL_1                    (0x2UL << RCC_CCIPR2_ETH1SEL_Pos)              /*!< 0x00020000 */
27083 #define RCC_CCIPR2_ETH1SEL_2                    (0x4UL << RCC_CCIPR2_ETH1SEL_Pos)              /*!< 0x00040000 */
27084 #define RCC_CCIPR2_ETH1REFCLKSEL_Pos            (20U)
27085 #define RCC_CCIPR2_ETH1REFCLKSEL_Msk            (0x1UL << RCC_CCIPR2_ETH1REFCLKSEL_Pos)            /*!< 0x00100000 */
27086 #define RCC_CCIPR2_ETH1REFCLKSEL                RCC_CCIPR2_ETH1REFCLKSEL_Msk                      /*!< Set and reset by software */
27087 #define RCC_CCIPR2_ETH1GTXCLKSEL_Pos            (24U)
27088 #define RCC_CCIPR2_ETH1GTXCLKSEL_Msk            (0x1UL << RCC_CCIPR2_ETH1GTXCLKSEL_Pos)            /*!< 0x01000000 */
27089 #define RCC_CCIPR2_ETH1GTXCLKSEL                RCC_CCIPR2_ETH1GTXCLKSEL_Msk                      /*!< Set and reset by software */
27090 
27091 /******************  Bit definition for RCC_CCIPR3 register  ******************/
27092 #define RCC_CCIPR3_FDCANSEL_Pos                 (0U)
27093 #define RCC_CCIPR3_FDCANSEL_Msk                 (0x3UL << RCC_CCIPR3_FDCANSEL_Pos)                 /*!< 0x00000003 */
27094 #define RCC_CCIPR3_FDCANSEL                     RCC_CCIPR3_FDCANSEL_Msk                           /*!< Source selection for the FDCAN kernel clock */
27095 #define RCC_CCIPR3_FDCANSEL_0                   (0x1UL << RCC_CCIPR3_FDCANSEL_Pos)                 /*!< 0x00000001 */
27096 #define RCC_CCIPR3_FDCANSEL_1                   (0x2UL << RCC_CCIPR3_FDCANSEL_Pos)                 /*!< 0x00000002 */
27097 #define RCC_CCIPR3_FMCSEL_Pos                   (4U)
27098 #define RCC_CCIPR3_FMCSEL_Msk                   (0x3UL << RCC_CCIPR3_FMCSEL_Pos)                   /*!< 0x00000030 */
27099 #define RCC_CCIPR3_FMCSEL                       RCC_CCIPR3_FMCSEL_Msk                             /*!< Source selection for the FMC kernel clock */
27100 #define RCC_CCIPR3_FMCSEL_0                     (0x1UL << RCC_CCIPR3_FMCSEL_Pos)                  /*!< 0x00000010 */
27101 #define RCC_CCIPR3_FMCSEL_1                     (0x2UL << RCC_CCIPR3_FMCSEL_Pos)                  /*!< 0x00000020 */
27102 #define RCC_CCIPR3_DFTSEL_Pos                   (8U)
27103 #define RCC_CCIPR3_DFTSEL_Msk                   (0x1UL << RCC_CCIPR3_DFTSEL_Pos)                   /*!< 0x00000100 */
27104 #define RCC_CCIPR3_DFTSEL                       RCC_CCIPR3_DFTSEL_Msk                             /*!< Source selection for the DFT kernel clock */
27105 
27106 /******************  Bit definition for RCC_CCIPR4 register  ******************/
27107 #define RCC_CCIPR4_I2C1SEL_Pos                  (0U)
27108 #define RCC_CCIPR4_I2C1SEL_Msk                  (0x7UL << RCC_CCIPR4_I2C1SEL_Pos)                  /*!< 0x00000007 */
27109 #define RCC_CCIPR4_I2C1SEL                      RCC_CCIPR4_I2C1SEL_Msk                            /*!< Source selection for the I2C1 kernel clock */
27110 #define RCC_CCIPR4_I2C1SEL_0                    (0x1UL << RCC_CCIPR4_I2C1SEL_Pos)                  /*!< 0x00000001 */
27111 #define RCC_CCIPR4_I2C1SEL_1                    (0x2UL << RCC_CCIPR4_I2C1SEL_Pos)                  /*!< 0x00000002 */
27112 #define RCC_CCIPR4_I2C1SEL_2                    (0x4UL << RCC_CCIPR4_I2C1SEL_Pos)                  /*!< 0x00000004 */
27113 #define RCC_CCIPR4_I2C2SEL_Pos                  (4U)
27114 #define RCC_CCIPR4_I2C2SEL_Msk                  (0x7UL << RCC_CCIPR4_I2C2SEL_Pos)                  /*!< 0x00000070 */
27115 #define RCC_CCIPR4_I2C2SEL                      RCC_CCIPR4_I2C2SEL_Msk                            /*!< Source selection for the I2C2 kernel clock */
27116 #define RCC_CCIPR4_I2C2SEL_0                    (0x1UL << RCC_CCIPR4_I2C2SEL_Pos)                 /*!< 0x00000010 */
27117 #define RCC_CCIPR4_I2C2SEL_1                    (0x2UL << RCC_CCIPR4_I2C2SEL_Pos)                 /*!< 0x00000020 */
27118 #define RCC_CCIPR4_I2C2SEL_2                    (0x4UL << RCC_CCIPR4_I2C2SEL_Pos)                 /*!< 0x00000040 */
27119 #define RCC_CCIPR4_I2C3SEL_Pos                  (8U)
27120 #define RCC_CCIPR4_I2C3SEL_Msk                  (0x7UL << RCC_CCIPR4_I2C3SEL_Pos)                  /*!< 0x00000700 */
27121 #define RCC_CCIPR4_I2C3SEL                      RCC_CCIPR4_I2C3SEL_Msk                            /*!< Source selection for the I2C3 kernel clock */
27122 #define RCC_CCIPR4_I2C3SEL_0                    (0x1UL << RCC_CCIPR4_I2C3SEL_Pos)                /*!< 0x00000100 */
27123 #define RCC_CCIPR4_I2C3SEL_1                    (0x2UL << RCC_CCIPR4_I2C3SEL_Pos)                /*!< 0x00000200 */
27124 #define RCC_CCIPR4_I2C3SEL_2                    (0x4UL << RCC_CCIPR4_I2C3SEL_Pos)                /*!< 0x00000400 */
27125 #define RCC_CCIPR4_I2C4SEL_Pos                  (12U)
27126 #define RCC_CCIPR4_I2C4SEL_Msk                  (0x7UL << RCC_CCIPR4_I2C4SEL_Pos)                  /*!< 0x00007000 */
27127 #define RCC_CCIPR4_I2C4SEL                      RCC_CCIPR4_I2C4SEL_Msk                            /*!< Source selection for the I2C4 kernel clock */
27128 #define RCC_CCIPR4_I2C4SEL_0                    (0x1UL << RCC_CCIPR4_I2C4SEL_Pos)               /*!< 0x00001000 */
27129 #define RCC_CCIPR4_I2C4SEL_1                    (0x2UL << RCC_CCIPR4_I2C4SEL_Pos)               /*!< 0x00002000 */
27130 #define RCC_CCIPR4_I2C4SEL_2                    (0x4UL << RCC_CCIPR4_I2C4SEL_Pos)               /*!< 0x00004000 */
27131 #define RCC_CCIPR4_I3C1SEL_Pos                  (16U)
27132 #define RCC_CCIPR4_I3C1SEL_Msk                  (0x7UL << RCC_CCIPR4_I3C1SEL_Pos)                  /*!< 0x00070000 */
27133 #define RCC_CCIPR4_I3C1SEL                      RCC_CCIPR4_I3C1SEL_Msk                            /*!< Source selection for the I3C1 kernel clock */
27134 #define RCC_CCIPR4_I3C1SEL_0                    (0x1UL << RCC_CCIPR4_I3C1SEL_Pos)              /*!< 0x00010000 */
27135 #define RCC_CCIPR4_I3C1SEL_1                    (0x2UL << RCC_CCIPR4_I3C1SEL_Pos)              /*!< 0x00020000 */
27136 #define RCC_CCIPR4_I3C1SEL_2                    (0x4UL << RCC_CCIPR4_I3C1SEL_Pos)              /*!< 0x00040000 */
27137 #define RCC_CCIPR4_I3C2SEL_Pos                  (20U)
27138 #define RCC_CCIPR4_I3C2SEL_Msk                  (0x7UL << RCC_CCIPR4_I3C2SEL_Pos)                  /*!< 0x00700000 */
27139 #define RCC_CCIPR4_I3C2SEL                      RCC_CCIPR4_I3C2SEL_Msk                            /*!< Source selection for the I3C2 kernel clock */
27140 #define RCC_CCIPR4_I3C2SEL_0                    (0x1UL << RCC_CCIPR4_I3C2SEL_Pos)             /*!< 0x00100000 */
27141 #define RCC_CCIPR4_I3C2SEL_1                    (0x2UL << RCC_CCIPR4_I3C2SEL_Pos)             /*!< 0x00200000 */
27142 #define RCC_CCIPR4_I3C2SEL_2                    (0x4UL << RCC_CCIPR4_I3C2SEL_Pos)             /*!< 0x00400000 */
27143 #define RCC_CCIPR4_LTDCSEL_Pos                  (24U)
27144 #define RCC_CCIPR4_LTDCSEL_Msk                  (0x3UL << RCC_CCIPR4_LTDCSEL_Pos)                  /*!< 0x03000000 */
27145 #define RCC_CCIPR4_LTDCSEL                      RCC_CCIPR4_LTDCSEL_Msk                            /*!< Source selection for the LTDC kernel clock */
27146 #define RCC_CCIPR4_LTDCSEL_0                    (0x1UL << RCC_CCIPR4_LTDCSEL_Pos)            /*!< 0x01000000 */
27147 #define RCC_CCIPR4_LTDCSEL_1                    (0x2UL << RCC_CCIPR4_LTDCSEL_Pos)            /*!< 0x02000000 */
27148 
27149 /******************  Bit definition for RCC_CCIPR5 register  ******************/
27150 #define RCC_CCIPR5_MCO1SEL_Pos                  (0U)
27151 #define RCC_CCIPR5_MCO1SEL_Msk                  (0x7UL << RCC_CCIPR5_MCO1SEL_Pos)                  /*!< 0x00000007 */
27152 #define RCC_CCIPR5_MCO1SEL                      RCC_CCIPR5_MCO1SEL_Msk                            /*!< Source selection for the MCO1 kernel clock */
27153 #define RCC_CCIPR5_MCO1SEL_0                    (0x1UL << RCC_CCIPR5_MCO1SEL_Pos)                  /*!< 0x00000001 */
27154 #define RCC_CCIPR5_MCO1SEL_1                    (0x2UL << RCC_CCIPR5_MCO1SEL_Pos)                  /*!< 0x00000002 */
27155 #define RCC_CCIPR5_MCO1SEL_2                    (0x4UL << RCC_CCIPR5_MCO1SEL_Pos)                  /*!< 0x00000004 */
27156 #define RCC_CCIPR5_MCO1PRE_Pos                  (4U)
27157 #define RCC_CCIPR5_MCO1PRE_Msk                  (0xFUL << RCC_CCIPR5_MCO1PRE_Pos)                  /*!< 0x000000F0 */
27158 #define RCC_CCIPR5_MCO1PRE                      RCC_CCIPR5_MCO1PRE_Msk                            /*!< MCO1 Kernel clock divider selection (for clock MCO1) */
27159 #define RCC_CCIPR5_MCO1PRE_0                    (0x1UL << RCC_CCIPR5_MCO1PRE_Pos)                 /*!< 0x00000010 */
27160 #define RCC_CCIPR5_MCO1PRE_1                    (0x2UL << RCC_CCIPR5_MCO1PRE_Pos)                 /*!< 0x00000020 */
27161 #define RCC_CCIPR5_MCO1PRE_2                    (0x4UL << RCC_CCIPR5_MCO1PRE_Pos)                 /*!< 0x00000040 */
27162 #define RCC_CCIPR5_MCO1PRE_3                    (0x8UL << RCC_CCIPR5_MCO1PRE_Pos)                 /*!< 0x00000080 */
27163 #define RCC_CCIPR5_MCO2SEL_Pos                  (8U)
27164 #define RCC_CCIPR5_MCO2SEL_Msk                  (0x7UL << RCC_CCIPR5_MCO2SEL_Pos)                  /*!< 0x00000700 */
27165 #define RCC_CCIPR5_MCO2SEL                      RCC_CCIPR5_MCO2SEL_Msk                            /*!< Source selection for the MCO2 kernel clock */
27166 #define RCC_CCIPR5_MCO2SEL_0                    (0x1UL << RCC_CCIPR5_MCO2SEL_Pos)                /*!< 0x00000100 */
27167 #define RCC_CCIPR5_MCO2SEL_1                    (0x2UL << RCC_CCIPR5_MCO2SEL_Pos)                /*!< 0x00000200 */
27168 #define RCC_CCIPR5_MCO2SEL_2                    (0x4UL << RCC_CCIPR5_MCO2SEL_Pos)                /*!< 0x00000400 */
27169 #define RCC_CCIPR5_MCO2PRE_Pos                  (12U)
27170 #define RCC_CCIPR5_MCO2PRE_Msk                  (0xFUL << RCC_CCIPR5_MCO2PRE_Pos)                  /*!< 0x0000F000 */
27171 #define RCC_CCIPR5_MCO2PRE                      RCC_CCIPR5_MCO2PRE_Msk                            /*!< MCO2 Kernel clock divider selection (for clock MCO2) */
27172 #define RCC_CCIPR5_MCO2PRE_0                    (0x1UL << RCC_CCIPR5_MCO2PRE_Pos)               /*!< 0x00001000 */
27173 #define RCC_CCIPR5_MCO2PRE_1                    (0x2UL << RCC_CCIPR5_MCO2PRE_Pos)               /*!< 0x00002000 */
27174 #define RCC_CCIPR5_MCO2PRE_2                    (0x4UL << RCC_CCIPR5_MCO2PRE_Pos)               /*!< 0x00004000 */
27175 #define RCC_CCIPR5_MCO2PRE_3                    (0x8UL << RCC_CCIPR5_MCO2PRE_Pos)               /*!< 0x00008000 */
27176 #define RCC_CCIPR5_MDF1SEL_Pos                  (16U)
27177 #define RCC_CCIPR5_MDF1SEL_Msk                  (0x7UL << RCC_CCIPR5_MDF1SEL_Pos)                  /*!< 0x00070000 */
27178 #define RCC_CCIPR5_MDF1SEL                      RCC_CCIPR5_MDF1SEL_Msk                            /*!< Source selection for the MDF1 kernel clock */
27179 #define RCC_CCIPR5_MDF1SEL_0                    (0x1UL << RCC_CCIPR5_MDF1SEL_Pos)              /*!< 0x00010000 */
27180 #define RCC_CCIPR5_MDF1SEL_1                    (0x2UL << RCC_CCIPR5_MDF1SEL_Pos)              /*!< 0x00020000 */
27181 #define RCC_CCIPR5_MDF1SEL_2                    (0x4UL << RCC_CCIPR5_MDF1SEL_Pos)              /*!< 0x00040000 */
27182 
27183 /******************  Bit definition for RCC_CCIPR6 register  ******************/
27184 #define RCC_CCIPR6_XSPI1SEL_Pos                 (0U)
27185 #define RCC_CCIPR6_XSPI1SEL_Msk                 (0x3UL << RCC_CCIPR6_XSPI1SEL_Pos)                 /*!< 0x00000003 */
27186 #define RCC_CCIPR6_XSPI1SEL                     RCC_CCIPR6_XSPI1SEL_Msk                           /*!< Source selection for the XSPI1 kernel clock */
27187 #define RCC_CCIPR6_XSPI1SEL_0                   (0x1UL << RCC_CCIPR6_XSPI1SEL_Pos)                 /*!< 0x00000001 */
27188 #define RCC_CCIPR6_XSPI1SEL_1                   (0x2UL << RCC_CCIPR6_XSPI1SEL_Pos)                 /*!< 0x00000002 */
27189 #define RCC_CCIPR6_XSPI2SEL_Pos                 (4U)
27190 #define RCC_CCIPR6_XSPI2SEL_Msk                 (0x3UL << RCC_CCIPR6_XSPI2SEL_Pos)                 /*!< 0x00000030 */
27191 #define RCC_CCIPR6_XSPI2SEL                     RCC_CCIPR6_XSPI2SEL_Msk                           /*!< Source selection for the XSPI2 kernel clock */
27192 #define RCC_CCIPR6_XSPI2SEL_0                   (0x1UL << RCC_CCIPR6_XSPI2SEL_Pos)                /*!< 0x00000010 */
27193 #define RCC_CCIPR6_XSPI2SEL_1                   (0x2UL << RCC_CCIPR6_XSPI2SEL_Pos)                /*!< 0x00000020 */
27194 #define RCC_CCIPR6_XSPI3SEL_Pos                 (8U)
27195 #define RCC_CCIPR6_XSPI3SEL_Msk                 (0x3UL << RCC_CCIPR6_XSPI3SEL_Pos)                 /*!< 0x00000300 */
27196 #define RCC_CCIPR6_XSPI3SEL                     RCC_CCIPR6_XSPI3SEL_Msk                           /*!< Source selection for the XSPI3 kernel clock */
27197 #define RCC_CCIPR6_XSPI3SEL_0                   (0x1UL << RCC_CCIPR6_XSPI3SEL_Pos)               /*!< 0x00000100 */
27198 #define RCC_CCIPR6_XSPI3SEL_1                   (0x2UL << RCC_CCIPR6_XSPI3SEL_Pos)               /*!< 0x00000200 */
27199 #define RCC_CCIPR6_OTGPHY1SEL_Pos               (12U)
27200 #define RCC_CCIPR6_OTGPHY1SEL_Msk               (0x3UL << RCC_CCIPR6_OTGPHY1SEL_Pos)               /*!< 0x00003000 */
27201 #define RCC_CCIPR6_OTGPHY1SEL                   RCC_CCIPR6_OTGPHY1SEL_Msk                         /*!< Source selection for the OTGPHY1 kernel clock */
27202 #define RCC_CCIPR6_OTGPHY1SEL_0                 (0x1UL << RCC_CCIPR6_OTGPHY1SEL_Pos)            /*!< 0x00001000 */
27203 #define RCC_CCIPR6_OTGPHY1SEL_1                 (0x2UL << RCC_CCIPR6_OTGPHY1SEL_Pos)            /*!< 0x00002000 */
27204 #define RCC_CCIPR6_OTGPHY1CKREFSEL_Pos          (16U)
27205 #define RCC_CCIPR6_OTGPHY1CKREFSEL_Msk          (0x1UL << RCC_CCIPR6_OTGPHY1CKREFSEL_Pos)          /*!< 0x00010000 */
27206 #define RCC_CCIPR6_OTGPHY1CKREFSEL              RCC_CCIPR6_OTGPHY1CKREFSEL_Msk                    /*!< Set and reset by software */
27207 #define RCC_CCIPR6_OTGPHY2SEL_Pos               (20U)
27208 #define RCC_CCIPR6_OTGPHY2SEL_Msk               (0x3UL << RCC_CCIPR6_OTGPHY2SEL_Pos)               /*!< 0x00300000 */
27209 #define RCC_CCIPR6_OTGPHY2SEL                   RCC_CCIPR6_OTGPHY2SEL_Msk                         /*!< Source selection for the OTGPHY2 kernel clock */
27210 #define RCC_CCIPR6_OTGPHY2SEL_0                 (0x1UL << RCC_CCIPR6_OTGPHY2SEL_Pos)          /*!< 0x00100000 */
27211 #define RCC_CCIPR6_OTGPHY2SEL_1                 (0x2UL << RCC_CCIPR6_OTGPHY2SEL_Pos)          /*!< 0x00200000 */
27212 #define RCC_CCIPR6_OTGPHY2CKREFSEL_Pos          (24U)
27213 #define RCC_CCIPR6_OTGPHY2CKREFSEL_Msk          (0x1UL << RCC_CCIPR6_OTGPHY2CKREFSEL_Pos)          /*!< 0x01000000 */
27214 #define RCC_CCIPR6_OTGPHY2CKREFSEL              RCC_CCIPR6_OTGPHY2CKREFSEL_Msk                    /*!< Set and reset by software */
27215 
27216 /******************  Bit definition for RCC_CCIPR7 register  ******************/
27217 #define RCC_CCIPR7_PERSEL_Pos                   (0U)
27218 #define RCC_CCIPR7_PERSEL_Msk                   (0x7UL << RCC_CCIPR7_PERSEL_Pos)                   /*!< 0x00000007 */
27219 #define RCC_CCIPR7_PERSEL                       RCC_CCIPR7_PERSEL_Msk                             /*!< Source selection for the PER kernel clock */
27220 #define RCC_CCIPR7_PERSEL_0                     (0x1UL << RCC_CCIPR7_PERSEL_Pos)                   /*!< 0x00000001 */
27221 #define RCC_CCIPR7_PERSEL_1                     (0x2UL << RCC_CCIPR7_PERSEL_Pos)                   /*!< 0x00000002 */
27222 #define RCC_CCIPR7_PERSEL_2                     (0x4UL << RCC_CCIPR7_PERSEL_Pos)                   /*!< 0x00000004 */
27223 #define RCC_CCIPR7_PSSISEL_Pos                  (4U)
27224 #define RCC_CCIPR7_PSSISEL_Msk                  (0x3UL << RCC_CCIPR7_PSSISEL_Pos)                  /*!< 0x00000030 */
27225 #define RCC_CCIPR7_PSSISEL                      RCC_CCIPR7_PSSISEL_Msk                            /*!< Source selection for the PSSI kernel clock */
27226 #define RCC_CCIPR7_PSSISEL_0                    (0x1UL << RCC_CCIPR7_PSSISEL_Pos)                 /*!< 0x00000010 */
27227 #define RCC_CCIPR7_PSSISEL_1                    (0x2UL << RCC_CCIPR7_PSSISEL_Pos)                 /*!< 0x00000020 */
27228 #define RCC_CCIPR7_RTCSEL_Pos                   (8U)
27229 #define RCC_CCIPR7_RTCSEL_Msk                   (0x3UL << RCC_CCIPR7_RTCSEL_Pos)                   /*!< 0x00000300 */
27230 #define RCC_CCIPR7_RTCSEL                       RCC_CCIPR7_RTCSEL_Msk                             /*!< Source selection for the RTC kernel clock */
27231 #define RCC_CCIPR7_RTCSEL_0                     (0x1UL << RCC_CCIPR7_RTCSEL_Pos)                 /*!< 0x00000100 */
27232 #define RCC_CCIPR7_RTCSEL_1                     (0x2UL << RCC_CCIPR7_RTCSEL_Pos)                 /*!< 0x00000200 */
27233 #define RCC_CCIPR7_RTCPRE_Pos                   (12U)
27234 #define RCC_CCIPR7_RTCPRE_Msk                   (0x3FUL << RCC_CCIPR7_RTCPRE_Pos)                  /*!< 0x0003F000 */
27235 #define RCC_CCIPR7_RTCPRE                       RCC_CCIPR7_RTCPRE_Msk                             /*!< RTC OSC clock divider selection (for clock hse_ck) */
27236 #define RCC_CCIPR7_RTCPRE_0                     (0x1UL << RCC_CCIPR7_RTCPRE_Pos)                /*!< 0x00001000 */
27237 #define RCC_CCIPR7_RTCPRE_1                     (0x2UL << RCC_CCIPR7_RTCPRE_Pos)                /*!< 0x00002000 */
27238 #define RCC_CCIPR7_RTCPRE_2                     (0x4UL << RCC_CCIPR7_RTCPRE_Pos)                /*!< 0x00004000 */
27239 #define RCC_CCIPR7_RTCPRE_3                     (0x8UL << RCC_CCIPR7_RTCPRE_Pos)                /*!< 0x00008000 */
27240 #define RCC_CCIPR7_RTCPRE_4                     (0x10UL << RCC_CCIPR7_RTCPRE_Pos)               /*!< 0x00010000 */
27241 #define RCC_CCIPR7_RTCPRE_5                     (0x20UL << RCC_CCIPR7_RTCPRE_Pos)               /*!< 0x00020000 */
27242 #define RCC_CCIPR7_SAI1SEL_Pos                  (20U)
27243 #define RCC_CCIPR7_SAI1SEL_Msk                  (0x7UL << RCC_CCIPR7_SAI1SEL_Pos)                  /*!< 0x00700000 */
27244 #define RCC_CCIPR7_SAI1SEL                      RCC_CCIPR7_SAI1SEL_Msk                            /*!< Source selection for the SAI1 kernel clock */
27245 #define RCC_CCIPR7_SAI1SEL_0                    (0x1UL << RCC_CCIPR7_SAI1SEL_Pos)             /*!< 0x00100000 */
27246 #define RCC_CCIPR7_SAI1SEL_1                    (0x2UL << RCC_CCIPR7_SAI1SEL_Pos)             /*!< 0x00200000 */
27247 #define RCC_CCIPR7_SAI1SEL_2                    (0x4UL << RCC_CCIPR7_SAI1SEL_Pos)             /*!< 0x00400000 */
27248 #define RCC_CCIPR7_SAI2SEL_Pos                  (24U)
27249 #define RCC_CCIPR7_SAI2SEL_Msk                  (0x7UL << RCC_CCIPR7_SAI2SEL_Pos)                  /*!< 0x07000000 */
27250 #define RCC_CCIPR7_SAI2SEL                      RCC_CCIPR7_SAI2SEL_Msk                            /*!< Source selection for the SAI2 kernel clock */
27251 #define RCC_CCIPR7_SAI2SEL_0                    (0x1UL << RCC_CCIPR7_SAI2SEL_Pos)            /*!< 0x01000000 */
27252 #define RCC_CCIPR7_SAI2SEL_1                    (0x2UL << RCC_CCIPR7_SAI2SEL_Pos)            /*!< 0x02000000 */
27253 #define RCC_CCIPR7_SAI2SEL_2                    (0x4UL << RCC_CCIPR7_SAI2SEL_Pos)            /*!< 0x04000000 */
27254 
27255 /******************  Bit definition for RCC_CCIPR8 register  ******************/
27256 #define RCC_CCIPR8_SDMMC1SEL_Pos                (0U)
27257 #define RCC_CCIPR8_SDMMC1SEL_Msk                (0x3UL << RCC_CCIPR8_SDMMC1SEL_Pos)                /*!< 0x00000003 */
27258 #define RCC_CCIPR8_SDMMC1SEL                    RCC_CCIPR8_SDMMC1SEL_Msk                          /*!< Source selection for the SDMMC1 kernel clock */
27259 #define RCC_CCIPR8_SDMMC1SEL_0                  (0x1UL << RCC_CCIPR8_SDMMC1SEL_Pos)                /*!< 0x00000001 */
27260 #define RCC_CCIPR8_SDMMC1SEL_1                  (0x2UL << RCC_CCIPR8_SDMMC1SEL_Pos)                /*!< 0x00000002 */
27261 #define RCC_CCIPR8_SDMMC2SEL_Pos                (4U)
27262 #define RCC_CCIPR8_SDMMC2SEL_Msk                (0x3UL << RCC_CCIPR8_SDMMC2SEL_Pos)                /*!< 0x00000030 */
27263 #define RCC_CCIPR8_SDMMC2SEL                    RCC_CCIPR8_SDMMC2SEL_Msk                          /*!< Source selection for the SDMMC2 kernel clock */
27264 #define RCC_CCIPR8_SDMMC2SEL_0                  (0x1UL << RCC_CCIPR8_SDMMC2SEL_Pos)               /*!< 0x00000010 */
27265 #define RCC_CCIPR8_SDMMC2SEL_1                  (0x2UL << RCC_CCIPR8_SDMMC2SEL_Pos)               /*!< 0x00000020 */
27266 
27267 /******************  Bit definition for RCC_CCIPR9 register  ******************/
27268 #define RCC_CCIPR9_SPDIFRX1SEL_Pos              (0U)
27269 #define RCC_CCIPR9_SPDIFRX1SEL_Msk              (0x7UL << RCC_CCIPR9_SPDIFRX1SEL_Pos)              /*!< 0x00000007 */
27270 #define RCC_CCIPR9_SPDIFRX1SEL                  RCC_CCIPR9_SPDIFRX1SEL_Msk                        /*!< Source selection for the SPDIFRX1 kernel clock */
27271 #define RCC_CCIPR9_SPDIFRX1SEL_0                (0x1UL << RCC_CCIPR9_SPDIFRX1SEL_Pos)              /*!< 0x00000001 */
27272 #define RCC_CCIPR9_SPDIFRX1SEL_1                (0x2UL << RCC_CCIPR9_SPDIFRX1SEL_Pos)              /*!< 0x00000002 */
27273 #define RCC_CCIPR9_SPDIFRX1SEL_2                (0x4UL << RCC_CCIPR9_SPDIFRX1SEL_Pos)              /*!< 0x00000004 */
27274 #define RCC_CCIPR9_SPI1SEL_Pos                  (4U)
27275 #define RCC_CCIPR9_SPI1SEL_Msk                  (0x7UL << RCC_CCIPR9_SPI1SEL_Pos)                  /*!< 0x00000070 */
27276 #define RCC_CCIPR9_SPI1SEL                      RCC_CCIPR9_SPI1SEL_Msk                            /*!< Source selection for the SPI1 kernel clock */
27277 #define RCC_CCIPR9_SPI1SEL_0                    (0x1UL << RCC_CCIPR9_SPI1SEL_Pos)                 /*!< 0x00000010 */
27278 #define RCC_CCIPR9_SPI1SEL_1                    (0x2UL << RCC_CCIPR9_SPI1SEL_Pos)                 /*!< 0x00000020 */
27279 #define RCC_CCIPR9_SPI1SEL_2                    (0x4UL << RCC_CCIPR9_SPI1SEL_Pos)                 /*!< 0x00000040 */
27280 #define RCC_CCIPR9_SPI2SEL_Pos                  (8U)
27281 #define RCC_CCIPR9_SPI2SEL_Msk                  (0x7UL << RCC_CCIPR9_SPI2SEL_Pos)                  /*!< 0x00000700 */
27282 #define RCC_CCIPR9_SPI2SEL                      RCC_CCIPR9_SPI2SEL_Msk                            /*!< Source selection for the SPI2 kernel clock */
27283 #define RCC_CCIPR9_SPI2SEL_0                    (0x1UL << RCC_CCIPR9_SPI2SEL_Pos)                /*!< 0x00000100 */
27284 #define RCC_CCIPR9_SPI2SEL_1                    (0x2UL << RCC_CCIPR9_SPI2SEL_Pos)                /*!< 0x00000200 */
27285 #define RCC_CCIPR9_SPI2SEL_2                    (0x4UL << RCC_CCIPR9_SPI2SEL_Pos)                /*!< 0x00000400 */
27286 #define RCC_CCIPR9_SPI3SEL_Pos                  (12U)
27287 #define RCC_CCIPR9_SPI3SEL_Msk                  (0x7UL << RCC_CCIPR9_SPI3SEL_Pos)                  /*!< 0x00007000 */
27288 #define RCC_CCIPR9_SPI3SEL                      RCC_CCIPR9_SPI3SEL_Msk                            /*!< Source selection for the SPI3 kernel clock */
27289 #define RCC_CCIPR9_SPI3SEL_0                    (0x1UL << RCC_CCIPR9_SPI3SEL_Pos)               /*!< 0x00001000 */
27290 #define RCC_CCIPR9_SPI3SEL_1                    (0x2UL << RCC_CCIPR9_SPI3SEL_Pos)               /*!< 0x00002000 */
27291 #define RCC_CCIPR9_SPI3SEL_2                    (0x4UL << RCC_CCIPR9_SPI3SEL_Pos)               /*!< 0x00004000 */
27292 #define RCC_CCIPR9_SPI4SEL_Pos                  (16U)
27293 #define RCC_CCIPR9_SPI4SEL_Msk                  (0x7UL << RCC_CCIPR9_SPI4SEL_Pos)                  /*!< 0x00070000 */
27294 #define RCC_CCIPR9_SPI4SEL                      RCC_CCIPR9_SPI4SEL_Msk                            /*!< Source selection for the SPI4 kernel clock */
27295 #define RCC_CCIPR9_SPI4SEL_0                    (0x1UL << RCC_CCIPR9_SPI4SEL_Pos)              /*!< 0x00010000 */
27296 #define RCC_CCIPR9_SPI4SEL_1                    (0x2UL << RCC_CCIPR9_SPI4SEL_Pos)              /*!< 0x00020000 */
27297 #define RCC_CCIPR9_SPI4SEL_2                    (0x4UL << RCC_CCIPR9_SPI4SEL_Pos)              /*!< 0x00040000 */
27298 #define RCC_CCIPR9_SPI5SEL_Pos                  (20U)
27299 #define RCC_CCIPR9_SPI5SEL_Msk                  (0x7UL << RCC_CCIPR9_SPI5SEL_Pos)                  /*!< 0x00700000 */
27300 #define RCC_CCIPR9_SPI5SEL                      RCC_CCIPR9_SPI5SEL_Msk                            /*!< Source selection for the SPI5 kernel clock */
27301 #define RCC_CCIPR9_SPI5SEL_0                    (0x1UL << RCC_CCIPR9_SPI5SEL_Pos)             /*!< 0x00100000 */
27302 #define RCC_CCIPR9_SPI5SEL_1                    (0x2UL << RCC_CCIPR9_SPI5SEL_Pos)             /*!< 0x00200000 */
27303 #define RCC_CCIPR9_SPI5SEL_2                    (0x4UL << RCC_CCIPR9_SPI5SEL_Pos)             /*!< 0x00400000 */
27304 #define RCC_CCIPR9_SPI6SEL_Pos                  (24U)
27305 #define RCC_CCIPR9_SPI6SEL_Msk                  (0x7UL << RCC_CCIPR9_SPI6SEL_Pos)                  /*!< 0x07000000 */
27306 #define RCC_CCIPR9_SPI6SEL                      RCC_CCIPR9_SPI6SEL_Msk                            /*!< Source selection for the SPI6 kernel clock */
27307 #define RCC_CCIPR9_SPI6SEL_0                    (0x1UL << RCC_CCIPR9_SPI6SEL_Pos)            /*!< 0x01000000 */
27308 #define RCC_CCIPR9_SPI6SEL_1                    (0x2UL << RCC_CCIPR9_SPI6SEL_Pos)            /*!< 0x02000000 */
27309 #define RCC_CCIPR9_SPI6SEL_2                    (0x4UL << RCC_CCIPR9_SPI6SEL_Pos)            /*!< 0x04000000 */
27310 
27311 /*****************  Bit definition for RCC_CCIPR12 register  ******************/
27312 #define RCC_CCIPR12_LPTIM1SEL_Pos               (8U)
27313 #define RCC_CCIPR12_LPTIM1SEL_Msk               (0x7UL << RCC_CCIPR12_LPTIM1SEL_Pos)               /*!< 0x00000700 */
27314 #define RCC_CCIPR12_LPTIM1SEL                   RCC_CCIPR12_LPTIM1SEL_Msk                         /*!< Source selection for the LPTIM1 kernel clock */
27315 #define RCC_CCIPR12_LPTIM1SEL_0                 (0x1UL << RCC_CCIPR12_LPTIM1SEL_Pos)             /*!< 0x00000100 */
27316 #define RCC_CCIPR12_LPTIM1SEL_1                 (0x2UL << RCC_CCIPR12_LPTIM1SEL_Pos)             /*!< 0x00000200 */
27317 #define RCC_CCIPR12_LPTIM1SEL_2                 (0x4UL << RCC_CCIPR12_LPTIM1SEL_Pos)             /*!< 0x00000400 */
27318 #define RCC_CCIPR12_LPTIM2SEL_Pos               (12U)
27319 #define RCC_CCIPR12_LPTIM2SEL_Msk               (0x7UL << RCC_CCIPR12_LPTIM2SEL_Pos)               /*!< 0x00007000 */
27320 #define RCC_CCIPR12_LPTIM2SEL                   RCC_CCIPR12_LPTIM2SEL_Msk                         /*!< Source selection for the LPTIM2 kernel clock */
27321 #define RCC_CCIPR12_LPTIM2SEL_0                 (0x1UL << RCC_CCIPR12_LPTIM2SEL_Pos)            /*!< 0x00001000 */
27322 #define RCC_CCIPR12_LPTIM2SEL_1                 (0x2UL << RCC_CCIPR12_LPTIM2SEL_Pos)            /*!< 0x00002000 */
27323 #define RCC_CCIPR12_LPTIM2SEL_2                 (0x4UL << RCC_CCIPR12_LPTIM2SEL_Pos)            /*!< 0x00004000 */
27324 #define RCC_CCIPR12_LPTIM3SEL_Pos               (16U)
27325 #define RCC_CCIPR12_LPTIM3SEL_Msk               (0x7UL << RCC_CCIPR12_LPTIM3SEL_Pos)               /*!< 0x00070000 */
27326 #define RCC_CCIPR12_LPTIM3SEL                   RCC_CCIPR12_LPTIM3SEL_Msk                         /*!< Source selection for the LPTIM3 kernel clock */
27327 #define RCC_CCIPR12_LPTIM3SEL_0                 (0x1UL << RCC_CCIPR12_LPTIM3SEL_Pos)           /*!< 0x00010000 */
27328 #define RCC_CCIPR12_LPTIM3SEL_1                 (0x2UL << RCC_CCIPR12_LPTIM3SEL_Pos)           /*!< 0x00020000 */
27329 #define RCC_CCIPR12_LPTIM3SEL_2                 (0x4UL << RCC_CCIPR12_LPTIM3SEL_Pos)           /*!< 0x00040000 */
27330 #define RCC_CCIPR12_LPTIM4SEL_Pos               (20U)
27331 #define RCC_CCIPR12_LPTIM4SEL_Msk               (0x7UL << RCC_CCIPR12_LPTIM4SEL_Pos)               /*!< 0x00700000 */
27332 #define RCC_CCIPR12_LPTIM4SEL                   RCC_CCIPR12_LPTIM4SEL_Msk                         /*!< Source selection for the LPTIM4 kernel clock */
27333 #define RCC_CCIPR12_LPTIM4SEL_0                 (0x1UL << RCC_CCIPR12_LPTIM4SEL_Pos)          /*!< 0x00100000 */
27334 #define RCC_CCIPR12_LPTIM4SEL_1                 (0x2UL << RCC_CCIPR12_LPTIM4SEL_Pos)          /*!< 0x00200000 */
27335 #define RCC_CCIPR12_LPTIM4SEL_2                 (0x4UL << RCC_CCIPR12_LPTIM4SEL_Pos)          /*!< 0x00400000 */
27336 #define RCC_CCIPR12_LPTIM5SEL_Pos               (24U)
27337 #define RCC_CCIPR12_LPTIM5SEL_Msk               (0x7UL << RCC_CCIPR12_LPTIM5SEL_Pos)               /*!< 0x07000000 */
27338 #define RCC_CCIPR12_LPTIM5SEL                   RCC_CCIPR12_LPTIM5SEL_Msk                         /*!< Source selection for the LPTIM5 kernel clock */
27339 #define RCC_CCIPR12_LPTIM5SEL_0                 (0x1UL << RCC_CCIPR12_LPTIM5SEL_Pos)         /*!< 0x01000000 */
27340 #define RCC_CCIPR12_LPTIM5SEL_1                 (0x2UL << RCC_CCIPR12_LPTIM5SEL_Pos)         /*!< 0x02000000 */
27341 #define RCC_CCIPR12_LPTIM5SEL_2                 (0x4UL << RCC_CCIPR12_LPTIM5SEL_Pos)         /*!< 0x04000000 */
27342 
27343 /*****************  Bit definition for RCC_CCIPR13 register  ******************/
27344 #define RCC_CCIPR13_USART1SEL_Pos               (0U)
27345 #define RCC_CCIPR13_USART1SEL_Msk               (0x7UL << RCC_CCIPR13_USART1SEL_Pos)               /*!< 0x00000007 */
27346 #define RCC_CCIPR13_USART1SEL                   RCC_CCIPR13_USART1SEL_Msk                         /*!< Source selection for the USART1 kernel clock */
27347 #define RCC_CCIPR13_USART1SEL_0                 (0x1UL << RCC_CCIPR13_USART1SEL_Pos)               /*!< 0x00000001 */
27348 #define RCC_CCIPR13_USART1SEL_1                 (0x2UL << RCC_CCIPR13_USART1SEL_Pos)               /*!< 0x00000002 */
27349 #define RCC_CCIPR13_USART1SEL_2                 (0x4UL << RCC_CCIPR13_USART1SEL_Pos)               /*!< 0x00000004 */
27350 #define RCC_CCIPR13_USART2SEL_Pos               (4U)
27351 #define RCC_CCIPR13_USART2SEL_Msk               (0x7UL << RCC_CCIPR13_USART2SEL_Pos)               /*!< 0x00000070 */
27352 #define RCC_CCIPR13_USART2SEL                   RCC_CCIPR13_USART2SEL_Msk                         /*!< Source selection for the USART2 kernel clock */
27353 #define RCC_CCIPR13_USART2SEL_0                 (0x1UL << RCC_CCIPR13_USART2SEL_Pos)              /*!< 0x00000010 */
27354 #define RCC_CCIPR13_USART2SEL_1                 (0x2UL << RCC_CCIPR13_USART2SEL_Pos)              /*!< 0x00000020 */
27355 #define RCC_CCIPR13_USART2SEL_2                 (0x4UL << RCC_CCIPR13_USART2SEL_Pos)              /*!< 0x00000040 */
27356 #define RCC_CCIPR13_USART3SEL_Pos               (8U)
27357 #define RCC_CCIPR13_USART3SEL_Msk               (0x7UL << RCC_CCIPR13_USART3SEL_Pos)               /*!< 0x00000700 */
27358 #define RCC_CCIPR13_USART3SEL                   RCC_CCIPR13_USART3SEL_Msk                         /*!< Source selection for the USART3 kernel clock */
27359 #define RCC_CCIPR13_USART3SEL_0                 (0x1UL << RCC_CCIPR13_USART3SEL_Pos)             /*!< 0x00000100 */
27360 #define RCC_CCIPR13_USART3SEL_1                 (0x2UL << RCC_CCIPR13_USART3SEL_Pos)             /*!< 0x00000200 */
27361 #define RCC_CCIPR13_USART3SEL_2                 (0x4UL << RCC_CCIPR13_USART3SEL_Pos)             /*!< 0x00000400 */
27362 #define RCC_CCIPR13_UART4SEL_Pos                (12U)
27363 #define RCC_CCIPR13_UART4SEL_Msk                (0x7UL << RCC_CCIPR13_UART4SEL_Pos)                /*!< 0x00007000 */
27364 #define RCC_CCIPR13_UART4SEL                    RCC_CCIPR13_UART4SEL_Msk                          /*!< Source selection for the UART4 kernel clock */
27365 #define RCC_CCIPR13_UART4SEL_0                  (0x1UL << RCC_CCIPR13_UART4SEL_Pos)             /*!< 0x00001000 */
27366 #define RCC_CCIPR13_UART4SEL_1                  (0x2UL << RCC_CCIPR13_UART4SEL_Pos)             /*!< 0x00002000 */
27367 #define RCC_CCIPR13_UART4SEL_2                  (0x4UL << RCC_CCIPR13_UART4SEL_Pos)             /*!< 0x00004000 */
27368 #define RCC_CCIPR13_UART5SEL_Pos                (16U)
27369 #define RCC_CCIPR13_UART5SEL_Msk                (0x7UL << RCC_CCIPR13_UART5SEL_Pos)                /*!< 0x00070000 */
27370 #define RCC_CCIPR13_UART5SEL                    RCC_CCIPR13_UART5SEL_Msk                          /*!< Source selection for the UART5 kernel clock */
27371 #define RCC_CCIPR13_UART5SEL_0                  (0x1UL << RCC_CCIPR13_UART5SEL_Pos)            /*!< 0x00010000 */
27372 #define RCC_CCIPR13_UART5SEL_1                  (0x2UL << RCC_CCIPR13_UART5SEL_Pos)            /*!< 0x00020000 */
27373 #define RCC_CCIPR13_UART5SEL_2                  (0x4UL << RCC_CCIPR13_UART5SEL_Pos)            /*!< 0x00040000 */
27374 #define RCC_CCIPR13_USART6SEL_Pos               (20U)
27375 #define RCC_CCIPR13_USART6SEL_Msk               (0x7UL << RCC_CCIPR13_USART6SEL_Pos)               /*!< 0x00700000 */
27376 #define RCC_CCIPR13_USART6SEL                   RCC_CCIPR13_USART6SEL_Msk                         /*!< Source selection for the USART6 kernel clock */
27377 #define RCC_CCIPR13_USART6SEL_0                 (0x1UL << RCC_CCIPR13_USART6SEL_Pos)          /*!< 0x00100000 */
27378 #define RCC_CCIPR13_USART6SEL_1                 (0x2UL << RCC_CCIPR13_USART6SEL_Pos)          /*!< 0x00200000 */
27379 #define RCC_CCIPR13_USART6SEL_2                 (0x4UL << RCC_CCIPR13_USART6SEL_Pos)          /*!< 0x00400000 */
27380 #define RCC_CCIPR13_UART7SEL_Pos                (24U)
27381 #define RCC_CCIPR13_UART7SEL_Msk                (0x7UL << RCC_CCIPR13_UART7SEL_Pos)                /*!< 0x07000000 */
27382 #define RCC_CCIPR13_UART7SEL                    RCC_CCIPR13_UART7SEL_Msk                          /*!< Source selection for the UART7 kernel clock */
27383 #define RCC_CCIPR13_UART7SEL_0                  (0x1UL << RCC_CCIPR13_UART7SEL_Pos)          /*!< 0x01000000 */
27384 #define RCC_CCIPR13_UART7SEL_1                  (0x2UL << RCC_CCIPR13_UART7SEL_Pos)          /*!< 0x02000000 */
27385 #define RCC_CCIPR13_UART7SEL_2                  (0x4UL << RCC_CCIPR13_UART7SEL_Pos)          /*!< 0x04000000 */
27386 #define RCC_CCIPR13_UART8SEL_Pos                (28U)
27387 #define RCC_CCIPR13_UART8SEL_Msk                (0x7UL << RCC_CCIPR13_UART8SEL_Pos)                /*!< 0x70000000 */
27388 #define RCC_CCIPR13_UART8SEL                    RCC_CCIPR13_UART8SEL_Msk                          /*!< Source selection for the UART8 kernel clock */
27389 #define RCC_CCIPR13_UART8SEL_0                  (0x1UL << RCC_CCIPR13_UART8SEL_Pos)         /*!< 0x10000000 */
27390 #define RCC_CCIPR13_UART8SEL_1                  (0x2UL << RCC_CCIPR13_UART8SEL_Pos)         /*!< 0x20000000 */
27391 #define RCC_CCIPR13_UART8SEL_2                  (0x4UL << RCC_CCIPR13_UART8SEL_Pos)         /*!< 0x40000000 */
27392 
27393 /*****************  Bit definition for RCC_CCIPR14 register  ******************/
27394 #define RCC_CCIPR14_UART9SEL_Pos                (0U)
27395 #define RCC_CCIPR14_UART9SEL_Msk                (0x7UL << RCC_CCIPR14_UART9SEL_Pos)                /*!< 0x00000007 */
27396 #define RCC_CCIPR14_UART9SEL                    RCC_CCIPR14_UART9SEL_Msk                          /*!< Source selection for the UART9 kernel clock */
27397 #define RCC_CCIPR14_UART9SEL_0                  (0x1UL << RCC_CCIPR14_UART9SEL_Pos)                /*!< 0x00000001 */
27398 #define RCC_CCIPR14_UART9SEL_1                  (0x2UL << RCC_CCIPR14_UART9SEL_Pos)                /*!< 0x00000002 */
27399 #define RCC_CCIPR14_UART9SEL_2                  (0x4UL << RCC_CCIPR14_UART9SEL_Pos)                /*!< 0x00000004 */
27400 #define RCC_CCIPR14_USART10SEL_Pos              (4U)
27401 #define RCC_CCIPR14_USART10SEL_Msk              (0x7UL << RCC_CCIPR14_USART10SEL_Pos)              /*!< 0x00000070 */
27402 #define RCC_CCIPR14_USART10SEL                  RCC_CCIPR14_USART10SEL_Msk                        /*!< Source selection for the USART10 kernel clock */
27403 #define RCC_CCIPR14_USART10SEL_0                (0x1UL << RCC_CCIPR14_USART10SEL_Pos)             /*!< 0x00000010 */
27404 #define RCC_CCIPR14_USART10SEL_1                (0x2UL << RCC_CCIPR14_USART10SEL_Pos)             /*!< 0x00000020 */
27405 #define RCC_CCIPR14_USART10SEL_2                (0x4UL << RCC_CCIPR14_USART10SEL_Pos)             /*!< 0x00000040 */
27406 #define RCC_CCIPR14_LPUART1SEL_Pos              (8U)
27407 #define RCC_CCIPR14_LPUART1SEL_Msk              (0x7UL << RCC_CCIPR14_LPUART1SEL_Pos)              /*!< 0x00000700 */
27408 #define RCC_CCIPR14_LPUART1SEL                  RCC_CCIPR14_LPUART1SEL_Msk                        /*!< Source selection for the LPUART1 kernel clock */
27409 #define RCC_CCIPR14_LPUART1SEL_0                (0x1UL << RCC_CCIPR14_LPUART1SEL_Pos)            /*!< 0x00000100 */
27410 #define RCC_CCIPR14_LPUART1SEL_1                (0x2UL << RCC_CCIPR14_LPUART1SEL_Pos)            /*!< 0x00000200 */
27411 #define RCC_CCIPR14_LPUART1SEL_2                (0x4UL << RCC_CCIPR14_LPUART1SEL_Pos)            /*!< 0x00000400 */
27412 
27413 /*****************  Bit definition for RCC_MISCRSTR register  *****************/
27414 #define RCC_MISCRSTR_DBGRST_Pos                 (0U)
27415 #define RCC_MISCRSTR_DBGRST_Msk                 (0x1UL << RCC_MISCRSTR_DBGRST_Pos)    /*!< 0x00000001 */
27416 #define RCC_MISCRSTR_DBGRST                     RCC_MISCRSTR_DBGRST_Msk              /*!< DBG reset */
27417 #define RCC_MISCRSTR_XSPIPHY1RST_Pos            (4U)
27418 #define RCC_MISCRSTR_XSPIPHY1RST_Msk            (0x1UL << RCC_MISCRSTR_XSPIPHY1RST_Pos) /*!< 0x00000010 */
27419 #define RCC_MISCRSTR_XSPIPHY1RST                RCC_MISCRSTR_XSPIPHY1RST_Msk         /*!< XSPIPHY1 reset */
27420 #define RCC_MISCRSTR_XSPIPHY2RST_Pos            (5U)
27421 #define RCC_MISCRSTR_XSPIPHY2RST_Msk            (0x1UL << RCC_MISCRSTR_XSPIPHY2RST_Pos) /*!< 0x00000020 */
27422 #define RCC_MISCRSTR_XSPIPHY2RST                RCC_MISCRSTR_XSPIPHY2RST_Msk         /*!< XSPIPHY2 reset */
27423 #define RCC_MISCRSTR_SDMMC1DLLRST_Pos           (7U)
27424 #define RCC_MISCRSTR_SDMMC1DLLRST_Msk           (0x1UL << RCC_MISCRSTR_SDMMC1DLLRST_Pos)  /*!< 0x00000080 */
27425 #define RCC_MISCRSTR_SDMMC1DLLRST               RCC_MISCRSTR_SDMMC1DLLRST_Msk        /*!< SDMMC1DLL reset */
27426 #define RCC_MISCRSTR_SDMMC2DLLRST_Pos           (8U)
27427 #define RCC_MISCRSTR_SDMMC2DLLRST_Msk           (0x1UL << RCC_MISCRSTR_SDMMC2DLLRST_Pos)  /*!< 0x00000100 */
27428 #define RCC_MISCRSTR_SDMMC2DLLRST               RCC_MISCRSTR_SDMMC2DLLRST_Msk        /*!< SDMMC2DLL reset */
27429 
27430 /*****************  Bit definition for RCC_MEMRSTR register  ******************/
27431 #define RCC_MEMRSTR_AXISRAM3RST_Pos             (0U)
27432 #define RCC_MEMRSTR_AXISRAM3RST_Msk             (0x1UL << RCC_MEMRSTR_AXISRAM3RST_Pos)/*!< 0x00000001 */
27433 #define RCC_MEMRSTR_AXISRAM3RST                 RCC_MEMRSTR_AXISRAM3RST_Msk          /*!< AXISRAM3 reset */
27434 #define RCC_MEMRSTR_AXISRAM4RST_Pos             (1U)
27435 #define RCC_MEMRSTR_AXISRAM4RST_Msk             (0x1UL << RCC_MEMRSTR_AXISRAM4RST_Pos)/*!< 0x00000002 */
27436 #define RCC_MEMRSTR_AXISRAM4RST                 RCC_MEMRSTR_AXISRAM4RST_Msk          /*!< AXISRAM4 reset */
27437 #define RCC_MEMRSTR_AXISRAM5RST_Pos             (2U)
27438 #define RCC_MEMRSTR_AXISRAM5RST_Msk             (0x1UL << RCC_MEMRSTR_AXISRAM5RST_Pos)/*!< 0x00000004 */
27439 #define RCC_MEMRSTR_AXISRAM5RST                 RCC_MEMRSTR_AXISRAM5RST_Msk          /*!< AXISRAM5 reset */
27440 #define RCC_MEMRSTR_AXISRAM6RST_Pos             (3U)
27441 #define RCC_MEMRSTR_AXISRAM6RST_Msk             (0x1UL << RCC_MEMRSTR_AXISRAM6RST_Pos)/*!< 0x00000008 */
27442 #define RCC_MEMRSTR_AXISRAM6RST                 RCC_MEMRSTR_AXISRAM6RST_Msk          /*!< AXISRAM6 reset */
27443 #define RCC_MEMRSTR_AHBSRAM1RST_Pos             (4U)
27444 #define RCC_MEMRSTR_AHBSRAM1RST_Msk             (0x1UL << RCC_MEMRSTR_AHBSRAM1RST_Pos)/*!< 0x00000010 */
27445 #define RCC_MEMRSTR_AHBSRAM1RST                 RCC_MEMRSTR_AHBSRAM1RST_Msk          /*!< AHBSRAM1 reset */
27446 #define RCC_MEMRSTR_AHBSRAM2RST_Pos             (5U)
27447 #define RCC_MEMRSTR_AHBSRAM2RST_Msk             (0x1UL << RCC_MEMRSTR_AHBSRAM2RST_Pos)/*!< 0x00000020 */
27448 #define RCC_MEMRSTR_AHBSRAM2RST                 RCC_MEMRSTR_AHBSRAM2RST_Msk          /*!< AHBSRAM2 reset */
27449 #define RCC_MEMRSTR_AXISRAM1RST_Pos             (7U)
27450 #define RCC_MEMRSTR_AXISRAM1RST_Msk             (0x1UL << RCC_MEMRSTR_AXISRAM1RST_Pos)/*!< 0x00000080 */
27451 #define RCC_MEMRSTR_AXISRAM1RST                 RCC_MEMRSTR_AXISRAM1RST_Msk          /*!< AXISRAM1 reset */
27452 #define RCC_MEMRSTR_AXISRAM2RST_Pos             (8U)
27453 #define RCC_MEMRSTR_AXISRAM2RST_Msk             (0x1UL << RCC_MEMRSTR_AXISRAM2RST_Pos)/*!< 0x00000100 */
27454 #define RCC_MEMRSTR_AXISRAM2RST                 RCC_MEMRSTR_AXISRAM2RST_Msk          /*!< AXISRAM2 reset */
27455 #define RCC_MEMRSTR_FLEXRAMRST_Pos              (9U)
27456 #define RCC_MEMRSTR_FLEXRAMRST_Msk              (0x1UL << RCC_MEMRSTR_FLEXRAMRST_Pos) /*!< 0x00000200 */
27457 #define RCC_MEMRSTR_FLEXRAMRST                  RCC_MEMRSTR_FLEXRAMRST_Msk           /*!< FLEXRAM reset */
27458 #define RCC_MEMRSTR_CACHEAXIRAMRST_Pos          (10U)
27459 #define RCC_MEMRSTR_CACHEAXIRAMRST_Msk          (0x1UL << RCC_MEMRSTR_CACHEAXIRAMRST_Pos)   /*!< 0x00000400 */
27460 #define RCC_MEMRSTR_CACHEAXIRAMRST              RCC_MEMRSTR_CACHEAXIRAMRST_Msk       /*!< CACHEAXIRAM reset */
27461 #define RCC_MEMRSTR_VENCRAMRST_Pos              (11U)
27462 #define RCC_MEMRSTR_VENCRAMRST_Msk              (0x1UL << RCC_MEMRSTR_VENCRAMRST_Pos) /*!< 0x00000800 */
27463 #define RCC_MEMRSTR_VENCRAMRST                  RCC_MEMRSTR_VENCRAMRST_Msk           /*!< VENCRAM reset */
27464 #define RCC_MEMRSTR_BOOTROMRST_Pos              (12U)
27465 #define RCC_MEMRSTR_BOOTROMRST_Msk              (0x1UL << RCC_MEMRSTR_BOOTROMRST_Pos) /*!< 0x00001000 */
27466 #define RCC_MEMRSTR_BOOTROMRST                  RCC_MEMRSTR_BOOTROMRST_Msk           /*!< Boot ROM reset */
27467 
27468 /*****************  Bit definition for RCC_AHB1RSTR register  *****************/
27469 #define RCC_AHB1RSTR_GPDMA1RST_Pos              (4U)
27470 #define RCC_AHB1RSTR_GPDMA1RST_Msk              (0x1UL << RCC_AHB1RSTR_GPDMA1RST_Pos) /*!< 0x00000010 */
27471 #define RCC_AHB1RSTR_GPDMA1RST                  RCC_AHB1RSTR_GPDMA1RST_Msk           /*!< GPDMA1 reset */
27472 #define RCC_AHB1RSTR_ADC12RST_Pos               (5U)
27473 #define RCC_AHB1RSTR_ADC12RST_Msk               (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos)  /*!< 0x00000020 */
27474 #define RCC_AHB1RSTR_ADC12RST                   RCC_AHB1RSTR_ADC12RST_Msk            /*!< ADC12 reset */
27475 
27476 /*****************  Bit definition for RCC_AHB2RSTR register  *****************/
27477 #define RCC_AHB2RSTR_RAMCFGRST_Pos              (12U)
27478 #define RCC_AHB2RSTR_RAMCFGRST_Msk              (0x1UL << RCC_AHB2RSTR_RAMCFGRST_Pos) /*!< 0x00001000 */
27479 #define RCC_AHB2RSTR_RAMCFGRST                  RCC_AHB2RSTR_RAMCFGRST_Msk           /*!< RAMCFG reset */
27480 #define RCC_AHB2RSTR_MDF1RST_Pos                (16U)
27481 #define RCC_AHB2RSTR_MDF1RST_Msk                (0x1UL << RCC_AHB2RSTR_MDF1RST_Pos)   /*!< 0x00010000 */
27482 #define RCC_AHB2RSTR_MDF1RST                    RCC_AHB2RSTR_MDF1RST_Msk             /*!< MDF1 reset */
27483 #define RCC_AHB2RSTR_ADF1RST_Pos                (17U)
27484 #define RCC_AHB2RSTR_ADF1RST_Msk                (0x1UL << RCC_AHB2RSTR_ADF1RST_Pos)   /*!< 0x00020000 */
27485 #define RCC_AHB2RSTR_ADF1RST                    RCC_AHB2RSTR_ADF1RST_Msk             /*!< ADF1 reset */
27486 
27487 /*****************  Bit definition for RCC_AHB3RSTR register  *****************/
27488 #define RCC_AHB3RSTR_RNGRST_Pos                 (0U)
27489 #define RCC_AHB3RSTR_RNGRST_Msk                 (0x1UL << RCC_AHB3RSTR_RNGRST_Pos)    /*!< 0x00000001 */
27490 #define RCC_AHB3RSTR_RNGRST                     RCC_AHB3RSTR_RNGRST_Msk              /*!< RNG reset */
27491 #define RCC_AHB3RSTR_HASHRST_Pos                (1U)
27492 #define RCC_AHB3RSTR_HASHRST_Msk                (0x1UL << RCC_AHB3RSTR_HASHRST_Pos)   /*!< 0x00000002 */
27493 #define RCC_AHB3RSTR_HASHRST                    RCC_AHB3RSTR_HASHRST_Msk             /*!< HASH reset */
27494 #define RCC_AHB3RSTR_CRYPRST_Pos                (2U)
27495 #define RCC_AHB3RSTR_CRYPRST_Msk                (0x1UL << RCC_AHB3RSTR_CRYPRST_Pos)   /*!< 0x00000004 */
27496 #define RCC_AHB3RSTR_CRYPRST                    RCC_AHB3RSTR_CRYPRST_Msk             /*!< CRYP reset */
27497 #define RCC_AHB3RSTR_SAESRST_Pos                (4U)
27498 #define RCC_AHB3RSTR_SAESRST_Msk                (0x1UL << RCC_AHB3RSTR_SAESRST_Pos)   /*!< 0x00000010 */
27499 #define RCC_AHB3RSTR_SAESRST                    RCC_AHB3RSTR_SAESRST_Msk             /*!< SAES reset */
27500 #define RCC_AHB3RSTR_PKARST_Pos                 (8U)
27501 #define RCC_AHB3RSTR_PKARST_Msk                 (0x1UL << RCC_AHB3RSTR_PKARST_Pos)    /*!< 0x00000100 */
27502 #define RCC_AHB3RSTR_PKARST                     RCC_AHB3RSTR_PKARST_Msk              /*!< PKA reset */
27503 #define RCC_AHB3RSTR_IACRST_Pos                 (10U)
27504 #define RCC_AHB3RSTR_IACRST_Msk                 (0x1UL << RCC_AHB3RSTR_IACRST_Pos)    /*!< 0x00000400 */
27505 #define RCC_AHB3RSTR_IACRST                     RCC_AHB3RSTR_IACRST_Msk              /*!< IAC reset */
27506 
27507 /*****************  Bit definition for RCC_AHB4RSTR register  *****************/
27508 #define RCC_AHB4RSTR_GPIOARST_Pos               (0U)
27509 #define RCC_AHB4RSTR_GPIOARST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos)  /*!< 0x00000001 */
27510 #define RCC_AHB4RSTR_GPIOARST                   RCC_AHB4RSTR_GPIOARST_Msk            /*!< GPIO A reset */
27511 #define RCC_AHB4RSTR_GPIOBRST_Pos               (1U)
27512 #define RCC_AHB4RSTR_GPIOBRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos)  /*!< 0x00000002 */
27513 #define RCC_AHB4RSTR_GPIOBRST                   RCC_AHB4RSTR_GPIOBRST_Msk            /*!< GPIO B reset */
27514 #define RCC_AHB4RSTR_GPIOCRST_Pos               (2U)
27515 #define RCC_AHB4RSTR_GPIOCRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos)  /*!< 0x00000004 */
27516 #define RCC_AHB4RSTR_GPIOCRST                   RCC_AHB4RSTR_GPIOCRST_Msk            /*!< GPIO C reset */
27517 #define RCC_AHB4RSTR_GPIODRST_Pos               (3U)
27518 #define RCC_AHB4RSTR_GPIODRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos)  /*!< 0x00000008 */
27519 #define RCC_AHB4RSTR_GPIODRST                   RCC_AHB4RSTR_GPIODRST_Msk            /*!< GPIO D reset */
27520 #define RCC_AHB4RSTR_GPIOERST_Pos               (4U)
27521 #define RCC_AHB4RSTR_GPIOERST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos)  /*!< 0x00000010 */
27522 #define RCC_AHB4RSTR_GPIOERST                   RCC_AHB4RSTR_GPIOERST_Msk            /*!< GPIO E reset */
27523 #define RCC_AHB4RSTR_GPIOFRST_Pos               (5U)
27524 #define RCC_AHB4RSTR_GPIOFRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos)  /*!< 0x00000020 */
27525 #define RCC_AHB4RSTR_GPIOFRST                   RCC_AHB4RSTR_GPIOFRST_Msk            /*!< GPIO F reset */
27526 #define RCC_AHB4RSTR_GPIOGRST_Pos               (6U)
27527 #define RCC_AHB4RSTR_GPIOGRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos)  /*!< 0x00000040 */
27528 #define RCC_AHB4RSTR_GPIOGRST                   RCC_AHB4RSTR_GPIOGRST_Msk            /*!< GPIO G reset */
27529 #define RCC_AHB4RSTR_GPIOHRST_Pos               (7U)
27530 #define RCC_AHB4RSTR_GPIOHRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos)  /*!< 0x00000080 */
27531 #define RCC_AHB4RSTR_GPIOHRST                   RCC_AHB4RSTR_GPIOHRST_Msk            /*!< GPIO H reset */
27532 #define RCC_AHB4RSTR_GPIONRST_Pos               (13U)
27533 #define RCC_AHB4RSTR_GPIONRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIONRST_Pos)  /*!< 0x00002000 */
27534 #define RCC_AHB4RSTR_GPIONRST                   RCC_AHB4RSTR_GPIONRST_Msk            /*!< GPIO N reset */
27535 #define RCC_AHB4RSTR_GPIOORST_Pos               (14U)
27536 #define RCC_AHB4RSTR_GPIOORST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOORST_Pos)  /*!< 0x00004000 */
27537 #define RCC_AHB4RSTR_GPIOORST                   RCC_AHB4RSTR_GPIOORST_Msk            /*!< GPIO O reset */
27538 #define RCC_AHB4RSTR_GPIOPRST_Pos               (15U)
27539 #define RCC_AHB4RSTR_GPIOPRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOPRST_Pos)  /*!< 0x00008000 */
27540 #define RCC_AHB4RSTR_GPIOPRST                   RCC_AHB4RSTR_GPIOPRST_Msk            /*!< GPIO P reset */
27541 #define RCC_AHB4RSTR_GPIOQRST_Pos               (16U)
27542 #define RCC_AHB4RSTR_GPIOQRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOQRST_Pos)  /*!< 0x00010000 */
27543 #define RCC_AHB4RSTR_GPIOQRST                   RCC_AHB4RSTR_GPIOQRST_Msk            /*!< GPIO Q reset */
27544 #define RCC_AHB4RSTR_PWRRST_Pos                 (18U)
27545 #define RCC_AHB4RSTR_PWRRST_Msk                 (0x1UL << RCC_AHB4RSTR_PWRRST_Pos)    /*!< 0x00040000 */
27546 #define RCC_AHB4RSTR_PWRRST                     RCC_AHB4RSTR_PWRRST_Msk              /*!< PWR reset */
27547 #define RCC_AHB4RSTR_CRCRST_Pos                 (19U)
27548 #define RCC_AHB4RSTR_CRCRST_Msk                 (0x1UL << RCC_AHB4RSTR_CRCRST_Pos)    /*!< 0x00080000 */
27549 #define RCC_AHB4RSTR_CRCRST                     RCC_AHB4RSTR_CRCRST_Msk              /*!< CRC reset */
27550 
27551 /*****************  Bit definition for RCC_AHB5RSTR register  *****************/
27552 #define RCC_AHB5RSTR_HPDMA1RST_Pos              (0U)
27553 #define RCC_AHB5RSTR_HPDMA1RST_Msk              (0x1UL << RCC_AHB5RSTR_HPDMA1RST_Pos) /*!< 0x00000001 */
27554 #define RCC_AHB5RSTR_HPDMA1RST                  RCC_AHB5RSTR_HPDMA1RST_Msk           /*!< HPDMA1 reset */
27555 #define RCC_AHB5RSTR_DMA2DRST_Pos               (1U)
27556 #define RCC_AHB5RSTR_DMA2DRST_Msk               (0x1UL << RCC_AHB5RSTR_DMA2DRST_Pos)  /*!< 0x00000002 */
27557 #define RCC_AHB5RSTR_DMA2DRST                   RCC_AHB5RSTR_DMA2DRST_Msk            /*!< DMA2D reset */
27558 #define RCC_AHB5RSTR_JPEGRST_Pos                (3U)
27559 #define RCC_AHB5RSTR_JPEGRST_Msk                (0x1UL << RCC_AHB5RSTR_JPEGRST_Pos)   /*!< 0x00000008 */
27560 #define RCC_AHB5RSTR_JPEGRST                    RCC_AHB5RSTR_JPEGRST_Msk             /*!< JPEG reset */
27561 #define RCC_AHB5RSTR_FMCRST_Pos                 (4U)
27562 #define RCC_AHB5RSTR_FMCRST_Msk                 (0x1UL << RCC_AHB5RSTR_FMCRST_Pos)    /*!< 0x00000010 */
27563 #define RCC_AHB5RSTR_FMCRST                     RCC_AHB5RSTR_FMCRST_Msk              /*!< FMC reset */
27564 #define RCC_AHB5RSTR_XSPI1RST_Pos               (5U)
27565 #define RCC_AHB5RSTR_XSPI1RST_Msk               (0x1UL << RCC_AHB5RSTR_XSPI1RST_Pos)  /*!< 0x00000020 */
27566 #define RCC_AHB5RSTR_XSPI1RST                   RCC_AHB5RSTR_XSPI1RST_Msk            /*!< XSPI1 reset */
27567 #define RCC_AHB5RSTR_PSSIRST_Pos                (6U)
27568 #define RCC_AHB5RSTR_PSSIRST_Msk                (0x1UL << RCC_AHB5RSTR_PSSIRST_Pos)   /*!< 0x00000040 */
27569 #define RCC_AHB5RSTR_PSSIRST                    RCC_AHB5RSTR_PSSIRST_Msk             /*!< PSSI reset */
27570 #define RCC_AHB5RSTR_SDMMC2RST_Pos              (7U)
27571 #define RCC_AHB5RSTR_SDMMC2RST_Msk              (0x1UL << RCC_AHB5RSTR_SDMMC2RST_Pos) /*!< 0x00000080 */
27572 #define RCC_AHB5RSTR_SDMMC2RST                  RCC_AHB5RSTR_SDMMC2RST_Msk           /*!< SDMMC2 reset */
27573 #define RCC_AHB5RSTR_SDMMC1RST_Pos              (8U)
27574 #define RCC_AHB5RSTR_SDMMC1RST_Msk              (0x1UL << RCC_AHB5RSTR_SDMMC1RST_Pos) /*!< 0x00000100 */
27575 #define RCC_AHB5RSTR_SDMMC1RST                  RCC_AHB5RSTR_SDMMC1RST_Msk           /*!< SDMMC1 reset */
27576 #define RCC_AHB5RSTR_XSPI2RST_Pos               (12U)
27577 #define RCC_AHB5RSTR_XSPI2RST_Msk               (0x1UL << RCC_AHB5RSTR_XSPI2RST_Pos)  /*!< 0x00001000 */
27578 #define RCC_AHB5RSTR_XSPI2RST                   RCC_AHB5RSTR_XSPI2RST_Msk            /*!< XSPI2 reset */
27579 #define RCC_AHB5RSTR_XSPIMRST_Pos               (13U)
27580 #define RCC_AHB5RSTR_XSPIMRST_Msk               (0x1UL << RCC_AHB5RSTR_XSPIMRST_Pos)  /*!< 0x00002000 */
27581 #define RCC_AHB5RSTR_XSPIMRST                   RCC_AHB5RSTR_XSPIMRST_Msk            /*!< XSPIM reset */
27582 #define RCC_AHB5RSTR_XSPI3RST_Pos               (17U)
27583 #define RCC_AHB5RSTR_XSPI3RST_Msk               (0x1UL << RCC_AHB5RSTR_XSPI3RST_Pos)  /*!< 0x00020000 */
27584 #define RCC_AHB5RSTR_XSPI3RST                   RCC_AHB5RSTR_XSPI3RST_Msk            /*!< XSPI3 reset */
27585 #define RCC_AHB5RSTR_GFXMMURST_Pos              (19U)
27586 #define RCC_AHB5RSTR_GFXMMURST_Msk              (0x1UL << RCC_AHB5RSTR_GFXMMURST_Pos) /*!< 0x00080000 */
27587 #define RCC_AHB5RSTR_GFXMMURST                  RCC_AHB5RSTR_GFXMMURST_Msk           /*!< GFXMMU reset */
27588 #define RCC_AHB5RSTR_GPU2DRST_Pos               (20U)
27589 #define RCC_AHB5RSTR_GPU2DRST_Msk               (0x1UL << RCC_AHB5RSTR_GPU2DRST_Pos)  /*!< 0x00100000 */
27590 #define RCC_AHB5RSTR_GPU2DRST                   RCC_AHB5RSTR_GPU2DRST_Msk            /*!< GPU2D reset */
27591 #define RCC_AHB5RSTR_OTG1PHYCTLRST_Pos          (23U)
27592 #define RCC_AHB5RSTR_OTG1PHYCTLRST_Msk          (0x1UL << RCC_AHB5RSTR_OTG1PHYCTLRST_Pos)   /*!< 0x00800000 */
27593 #define RCC_AHB5RSTR_OTG1PHYCTLRST              RCC_AHB5RSTR_OTG1PHYCTLRST_Msk       /*!< OTG1PHYCTL reset */
27594 #define RCC_AHB5RSTR_OTG2PHYCTLRST_Pos          (24U)
27595 #define RCC_AHB5RSTR_OTG2PHYCTLRST_Msk          (0x1UL << RCC_AHB5RSTR_OTG2PHYCTLRST_Pos)   /*!< 0x01000000 */
27596 #define RCC_AHB5RSTR_OTG2PHYCTLRST              RCC_AHB5RSTR_OTG2PHYCTLRST_Msk       /*!< OTG2PHYCTL reset */
27597 #define RCC_AHB5RSTR_ETH1RST_Pos                (25U)
27598 #define RCC_AHB5RSTR_ETH1RST_Msk                (0x1UL << RCC_AHB5RSTR_ETH1RST_Pos)   /*!< 0x02000000 */
27599 #define RCC_AHB5RSTR_ETH1RST                    RCC_AHB5RSTR_ETH1RST_Msk             /*!< ETH1 reset */
27600 #define RCC_AHB5RSTR_OTG1RST_Pos                (26U)
27601 #define RCC_AHB5RSTR_OTG1RST_Msk                (0x1UL << RCC_AHB5RSTR_OTG1RST_Pos)   /*!< 0x04000000 */
27602 #define RCC_AHB5RSTR_OTG1RST                    RCC_AHB5RSTR_OTG1RST_Msk             /*!< OTG1 reset */
27603 #define RCC_AHB5RSTR_OTGPHY1RST_Pos             (27U)
27604 #define RCC_AHB5RSTR_OTGPHY1RST_Msk             (0x1UL << RCC_AHB5RSTR_OTGPHY1RST_Pos)/*!< 0x08000000 */
27605 #define RCC_AHB5RSTR_OTGPHY1RST                 RCC_AHB5RSTR_OTGPHY1RST_Msk          /*!< OTGPHY1 reset */
27606 #define RCC_AHB5RSTR_OTGPHY2RST_Pos             (28U)
27607 #define RCC_AHB5RSTR_OTGPHY2RST_Msk             (0x1UL << RCC_AHB5RSTR_OTGPHY2RST_Pos)/*!< 0x10000000 */
27608 #define RCC_AHB5RSTR_OTGPHY2RST                 RCC_AHB5RSTR_OTGPHY2RST_Msk          /*!< OTGPHY2 reset */
27609 #define RCC_AHB5RSTR_OTG2RST_Pos                (29U)
27610 #define RCC_AHB5RSTR_OTG2RST_Msk                (0x1UL << RCC_AHB5RSTR_OTG2RST_Pos)   /*!< 0x20000000 */
27611 #define RCC_AHB5RSTR_OTG2RST                    RCC_AHB5RSTR_OTG2RST_Msk             /*!< OTG2 reset */
27612 #define RCC_AHB5RSTR_CACHEAXIRST_Pos            (30U)
27613 #define RCC_AHB5RSTR_CACHEAXIRST_Msk            (0x1UL << RCC_AHB5RSTR_CACHEAXIRST_Pos) /*!< 0x40000000 */
27614 #define RCC_AHB5RSTR_CACHEAXIRST                RCC_AHB5RSTR_CACHEAXIRST_Msk         /*!< CACHEAXI reset */
27615 #define RCC_AHB5RSTR_NPURST_Pos                 (31U)
27616 #define RCC_AHB5RSTR_NPURST_Msk                 (0x1UL << RCC_AHB5RSTR_NPURST_Pos)    /*!< 0x80000000 */
27617 #define RCC_AHB5RSTR_NPURST                     RCC_AHB5RSTR_NPURST_Msk              /*!< NPU reset */
27618 
27619 /****************  Bit definition for RCC_APB1RSTR1 register  *****************/
27620 #define RCC_APB1RSTR1_TIM2RST_Pos               (0U)
27621 #define RCC_APB1RSTR1_TIM2RST_Msk               (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos)  /*!< 0x00000001 */
27622 #define RCC_APB1RSTR1_TIM2RST                   RCC_APB1RSTR1_TIM2RST_Msk            /*!< TIM2 reset */
27623 #define RCC_APB1RSTR1_TIM3RST_Pos               (1U)
27624 #define RCC_APB1RSTR1_TIM3RST_Msk               (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos)  /*!< 0x00000002 */
27625 #define RCC_APB1RSTR1_TIM3RST                   RCC_APB1RSTR1_TIM3RST_Msk            /*!< TIM3 reset */
27626 #define RCC_APB1RSTR1_TIM4RST_Pos               (2U)
27627 #define RCC_APB1RSTR1_TIM4RST_Msk               (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos)  /*!< 0x00000004 */
27628 #define RCC_APB1RSTR1_TIM4RST                   RCC_APB1RSTR1_TIM4RST_Msk            /*!< TIM4 reset */
27629 #define RCC_APB1RSTR1_TIM5RST_Pos               (3U)
27630 #define RCC_APB1RSTR1_TIM5RST_Msk               (0x1UL << RCC_APB1RSTR1_TIM5RST_Pos)  /*!< 0x00000008 */
27631 #define RCC_APB1RSTR1_TIM5RST                   RCC_APB1RSTR1_TIM5RST_Msk            /*!< TIM5 reset */
27632 #define RCC_APB1RSTR1_TIM6RST_Pos               (4U)
27633 #define RCC_APB1RSTR1_TIM6RST_Msk               (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos)  /*!< 0x00000010 */
27634 #define RCC_APB1RSTR1_TIM6RST                   RCC_APB1RSTR1_TIM6RST_Msk            /*!< TIM6 reset */
27635 #define RCC_APB1RSTR1_TIM7RST_Pos               (5U)
27636 #define RCC_APB1RSTR1_TIM7RST_Msk               (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos)  /*!< 0x00000020 */
27637 #define RCC_APB1RSTR1_TIM7RST                   RCC_APB1RSTR1_TIM7RST_Msk            /*!< TIM7 reset */
27638 #define RCC_APB1RSTR1_TIM12RST_Pos              (6U)
27639 #define RCC_APB1RSTR1_TIM12RST_Msk              (0x1UL << RCC_APB1RSTR1_TIM12RST_Pos) /*!< 0x00000040 */
27640 #define RCC_APB1RSTR1_TIM12RST                  RCC_APB1RSTR1_TIM12RST_Msk           /*!< TIM12 reset */
27641 #define RCC_APB1RSTR1_TIM13RST_Pos              (7U)
27642 #define RCC_APB1RSTR1_TIM13RST_Msk              (0x1UL << RCC_APB1RSTR1_TIM13RST_Pos) /*!< 0x00000080 */
27643 #define RCC_APB1RSTR1_TIM13RST                  RCC_APB1RSTR1_TIM13RST_Msk           /*!< TIM13 reset */
27644 #define RCC_APB1RSTR1_TIM14RST_Pos              (8U)
27645 #define RCC_APB1RSTR1_TIM14RST_Msk              (0x1UL << RCC_APB1RSTR1_TIM14RST_Pos) /*!< 0x00000100 */
27646 #define RCC_APB1RSTR1_TIM14RST                  RCC_APB1RSTR1_TIM14RST_Msk           /*!< TIM14 reset */
27647 #define RCC_APB1RSTR1_LPTIM1RST_Pos             (9U)
27648 #define RCC_APB1RSTR1_LPTIM1RST_Msk             (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)/*!< 0x00000200 */
27649 #define RCC_APB1RSTR1_LPTIM1RST                 RCC_APB1RSTR1_LPTIM1RST_Msk          /*!< LPTIM1 reset */
27650 #define RCC_APB1RSTR1_WWDGRST_Pos               (11U)
27651 #define RCC_APB1RSTR1_WWDGRST_Msk               (0x1UL << RCC_APB1RSTR1_WWDGRST_Pos)  /*!< 0x00000800 */
27652 #define RCC_APB1RSTR1_WWDGRST                   RCC_APB1RSTR1_WWDGRST_Msk            /*!< WWDG reset */
27653 #define RCC_APB1RSTR1_TIM10RST_Pos              (12U)
27654 #define RCC_APB1RSTR1_TIM10RST_Msk              (0x1UL << RCC_APB1RSTR1_TIM10RST_Pos) /*!< 0x00001000 */
27655 #define RCC_APB1RSTR1_TIM10RST                  RCC_APB1RSTR1_TIM10RST_Msk           /*!< TIM10 reset */
27656 #define RCC_APB1RSTR1_TIM11RST_Pos              (13U)
27657 #define RCC_APB1RSTR1_TIM11RST_Msk              (0x1UL << RCC_APB1RSTR1_TIM11RST_Pos) /*!< 0x00002000 */
27658 #define RCC_APB1RSTR1_TIM11RST                  RCC_APB1RSTR1_TIM11RST_Msk           /*!< TIM11 reset */
27659 #define RCC_APB1RSTR1_SPI2RST_Pos               (14U)
27660 #define RCC_APB1RSTR1_SPI2RST_Msk               (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos)  /*!< 0x00004000 */
27661 #define RCC_APB1RSTR1_SPI2RST                   RCC_APB1RSTR1_SPI2RST_Msk            /*!< SPI2 reset */
27662 #define RCC_APB1RSTR1_SPI3RST_Pos               (15U)
27663 #define RCC_APB1RSTR1_SPI3RST_Msk               (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos)  /*!< 0x00008000 */
27664 #define RCC_APB1RSTR1_SPI3RST                   RCC_APB1RSTR1_SPI3RST_Msk            /*!< SPI3 reset */
27665 #define RCC_APB1RSTR1_SPDIFRX1RST_Pos           (16U)
27666 #define RCC_APB1RSTR1_SPDIFRX1RST_Msk           (0x1UL << RCC_APB1RSTR1_SPDIFRX1RST_Pos)  /*!< 0x00010000 */
27667 #define RCC_APB1RSTR1_SPDIFRX1RST               RCC_APB1RSTR1_SPDIFRX1RST_Msk        /*!< SPDIFRX1 reset */
27668 #define RCC_APB1RSTR1_USART2RST_Pos             (17U)
27669 #define RCC_APB1RSTR1_USART2RST_Msk             (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)/*!< 0x00020000 */
27670 #define RCC_APB1RSTR1_USART2RST                 RCC_APB1RSTR1_USART2RST_Msk          /*!< USART2 reset */
27671 #define RCC_APB1RSTR1_USART3RST_Pos             (18U)
27672 #define RCC_APB1RSTR1_USART3RST_Msk             (0x1UL << RCC_APB1RSTR1_USART3RST_Pos)/*!< 0x00040000 */
27673 #define RCC_APB1RSTR1_USART3RST                 RCC_APB1RSTR1_USART3RST_Msk          /*!< USART3 reset */
27674 #define RCC_APB1RSTR1_UART4RST_Pos              (19U)
27675 #define RCC_APB1RSTR1_UART4RST_Msk              (0x1UL << RCC_APB1RSTR1_UART4RST_Pos) /*!< 0x00080000 */
27676 #define RCC_APB1RSTR1_UART4RST                  RCC_APB1RSTR1_UART4RST_Msk           /*!< UART4 reset */
27677 #define RCC_APB1RSTR1_UART5RST_Pos              (20U)
27678 #define RCC_APB1RSTR1_UART5RST_Msk              (0x1UL << RCC_APB1RSTR1_UART5RST_Pos) /*!< 0x00100000 */
27679 #define RCC_APB1RSTR1_UART5RST                  RCC_APB1RSTR1_UART5RST_Msk           /*!< UART5 reset */
27680 #define RCC_APB1RSTR1_I2C1RST_Pos               (21U)
27681 #define RCC_APB1RSTR1_I2C1RST_Msk               (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos)  /*!< 0x00200000 */
27682 #define RCC_APB1RSTR1_I2C1RST                   RCC_APB1RSTR1_I2C1RST_Msk            /*!< I2C1 reset */
27683 #define RCC_APB1RSTR1_I2C2RST_Pos               (22U)
27684 #define RCC_APB1RSTR1_I2C2RST_Msk               (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos)  /*!< 0x00400000 */
27685 #define RCC_APB1RSTR1_I2C2RST                   RCC_APB1RSTR1_I2C2RST_Msk            /*!< I2C2 reset */
27686 #define RCC_APB1RSTR1_I2C3RST_Pos               (23U)
27687 #define RCC_APB1RSTR1_I2C3RST_Msk               (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos)  /*!< 0x00800000 */
27688 #define RCC_APB1RSTR1_I2C3RST                   RCC_APB1RSTR1_I2C3RST_Msk            /*!< I2C3 reset */
27689 #define RCC_APB1RSTR1_I3C1RST_Pos               (24U)
27690 #define RCC_APB1RSTR1_I3C1RST_Msk               (0x1UL << RCC_APB1RSTR1_I3C1RST_Pos)  /*!< 0x01000000 */
27691 #define RCC_APB1RSTR1_I3C1RST                   RCC_APB1RSTR1_I3C1RST_Msk            /*!< I3C1 reset */
27692 #define RCC_APB1RSTR1_I3C2RST_Pos               (25U)
27693 #define RCC_APB1RSTR1_I3C2RST_Msk               (0x1UL << RCC_APB1RSTR1_I3C2RST_Pos)  /*!< 0x02000000 */
27694 #define RCC_APB1RSTR1_I3C2RST                   RCC_APB1RSTR1_I3C2RST_Msk            /*!< I3C2 reset */
27695 #define RCC_APB1RSTR1_UART7RST_Pos              (30U)
27696 #define RCC_APB1RSTR1_UART7RST_Msk              (0x1UL << RCC_APB1RSTR1_UART7RST_Pos) /*!< 0x40000000 */
27697 #define RCC_APB1RSTR1_UART7RST                  RCC_APB1RSTR1_UART7RST_Msk           /*!< UART7 reset */
27698 #define RCC_APB1RSTR1_UART8RST_Pos              (31U)
27699 #define RCC_APB1RSTR1_UART8RST_Msk              (0x1UL << RCC_APB1RSTR1_UART8RST_Pos) /*!< 0x80000000 */
27700 #define RCC_APB1RSTR1_UART8RST                  RCC_APB1RSTR1_UART8RST_Msk           /*!< UART8 reset */
27701 
27702 /****************  Bit definition for RCC_APB1RSTR2 register  *****************/
27703 #define RCC_APB1RSTR2_MDIOSRST_Pos              (5U)
27704 #define RCC_APB1RSTR2_MDIOSRST_Msk              (0x1UL << RCC_APB1RSTR2_MDIOSRST_Pos) /*!< 0x00000020 */
27705 #define RCC_APB1RSTR2_MDIOSRST                  RCC_APB1RSTR2_MDIOSRST_Msk            /*!< MDIOS reset */
27706 #define RCC_APB1RSTR2_FDCANRST_Pos              (8U)
27707 #define RCC_APB1RSTR2_FDCANRST_Msk              (0x1UL << RCC_APB1RSTR2_FDCANRST_Pos) /*!< 0x00000100 */
27708 #define RCC_APB1RSTR2_FDCANRST                  RCC_APB1RSTR2_FDCANRST_Msk            /*!< FDCAN reset */
27709 #define RCC_APB1RSTR2_UCPD1RST_Pos              (18U)
27710 #define RCC_APB1RSTR2_UCPD1RST_Msk              (0x1UL << RCC_APB1RSTR2_UCPD1RST_Pos) /*!< 0x00040000 */
27711 #define RCC_APB1RSTR2_UCPD1RST                  RCC_APB1RSTR2_UCPD1RST_Msk            /*!< UCPD1 reset */
27712 
27713 /*****************  Bit definition for RCC_APB2RSTR register  *****************/
27714 #define RCC_APB2RSTR_TIM1RST_Pos                (0U)
27715 #define RCC_APB2RSTR_TIM1RST_Msk                (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)   /*!< 0x00000001 */
27716 #define RCC_APB2RSTR_TIM1RST                    RCC_APB2RSTR_TIM1RST_Msk             /*!< TIM1 reset */
27717 #define RCC_APB2RSTR_TIM8RST_Pos                (1U)
27718 #define RCC_APB2RSTR_TIM8RST_Msk                (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)   /*!< 0x00000002 */
27719 #define RCC_APB2RSTR_TIM8RST                    RCC_APB2RSTR_TIM8RST_Msk             /*!< TIM8 reset */
27720 #define RCC_APB2RSTR_USART1RST_Pos              (4U)
27721 #define RCC_APB2RSTR_USART1RST_Msk              (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
27722 #define RCC_APB2RSTR_USART1RST                  RCC_APB2RSTR_USART1RST_Msk           /*!< USART1 reset */
27723 #define RCC_APB2RSTR_USART6RST_Pos              (5U)
27724 #define RCC_APB2RSTR_USART6RST_Msk              (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
27725 #define RCC_APB2RSTR_USART6RST                  RCC_APB2RSTR_USART6RST_Msk           /*!< USART6 reset */
27726 #define RCC_APB2RSTR_UART9RST_Pos               (6U)
27727 #define RCC_APB2RSTR_UART9RST_Msk               (0x1UL << RCC_APB2RSTR_UART9RST_Pos)  /*!< 0x00000040 */
27728 #define RCC_APB2RSTR_UART9RST                   RCC_APB2RSTR_UART9RST_Msk            /*!< UART9 reset */
27729 #define RCC_APB2RSTR_USART10RST_Pos             (7U)
27730 #define RCC_APB2RSTR_USART10RST_Msk             (0x1UL << RCC_APB2RSTR_USART10RST_Pos)/*!< 0x00000080 */
27731 #define RCC_APB2RSTR_USART10RST                 RCC_APB2RSTR_USART10RST_Msk          /*!< USART10 reset */
27732 #define RCC_APB2RSTR_SPI1RST_Pos                (12U)
27733 #define RCC_APB2RSTR_SPI1RST_Msk                (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)   /*!< 0x00001000 */
27734 #define RCC_APB2RSTR_SPI1RST                    RCC_APB2RSTR_SPI1RST_Msk             /*!< SPI1 reset */
27735 #define RCC_APB2RSTR_SPI4RST_Pos                (13U)
27736 #define RCC_APB2RSTR_SPI4RST_Msk                (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)   /*!< 0x00002000 */
27737 #define RCC_APB2RSTR_SPI4RST                    RCC_APB2RSTR_SPI4RST_Msk             /*!< SPI4 reset */
27738 #define RCC_APB2RSTR_TIM18RST_Pos               (15U)
27739 #define RCC_APB2RSTR_TIM18RST_Msk               (0x1UL << RCC_APB2RSTR_TIM18RST_Pos)  /*!< 0x00008000 */
27740 #define RCC_APB2RSTR_TIM18RST                   RCC_APB2RSTR_TIM18RST_Msk            /*!< TIM18 reset */
27741 #define RCC_APB2RSTR_TIM15RST_Pos               (16U)
27742 #define RCC_APB2RSTR_TIM15RST_Msk               (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)  /*!< 0x00010000 */
27743 #define RCC_APB2RSTR_TIM15RST                   RCC_APB2RSTR_TIM15RST_Msk            /*!< TIM15 reset */
27744 #define RCC_APB2RSTR_TIM16RST_Pos               (17U)
27745 #define RCC_APB2RSTR_TIM16RST_Msk               (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)  /*!< 0x00020000 */
27746 #define RCC_APB2RSTR_TIM16RST                   RCC_APB2RSTR_TIM16RST_Msk            /*!< TIM16 reset */
27747 #define RCC_APB2RSTR_TIM17RST_Pos               (18U)
27748 #define RCC_APB2RSTR_TIM17RST_Msk               (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)  /*!< 0x00040000 */
27749 #define RCC_APB2RSTR_TIM17RST                   RCC_APB2RSTR_TIM17RST_Msk            /*!< TIM17 reset */
27750 #define RCC_APB2RSTR_TIM9RST_Pos                (19U)
27751 #define RCC_APB2RSTR_TIM9RST_Msk                (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)   /*!< 0x00080000 */
27752 #define RCC_APB2RSTR_TIM9RST                    RCC_APB2RSTR_TIM9RST_Msk             /*!< TIM9 reset */
27753 #define RCC_APB2RSTR_SPI5RST_Pos                (20U)
27754 #define RCC_APB2RSTR_SPI5RST_Msk                (0x1UL << RCC_APB2RSTR_SPI5RST_Pos)   /*!< 0x00100000 */
27755 #define RCC_APB2RSTR_SPI5RST                    RCC_APB2RSTR_SPI5RST_Msk             /*!< SPI5 reset */
27756 #define RCC_APB2RSTR_SAI1RST_Pos                (21U)
27757 #define RCC_APB2RSTR_SAI1RST_Msk                (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)   /*!< 0x00200000 */
27758 #define RCC_APB2RSTR_SAI1RST                    RCC_APB2RSTR_SAI1RST_Msk             /*!< SAI1 reset */
27759 #define RCC_APB2RSTR_SAI2RST_Pos                (22U)
27760 #define RCC_APB2RSTR_SAI2RST_Msk                (0x1UL << RCC_APB2RSTR_SAI2RST_Pos)   /*!< 0x00400000 */
27761 #define RCC_APB2RSTR_SAI2RST                    RCC_APB2RSTR_SAI2RST_Msk             /*!< SAI2 reset */
27762 
27763 /****************  Bit definition for RCC_APB4RSTR1 register  *****************/
27764 #define RCC_APB4RSTR1_HDPRST_Pos                (2U)
27765 #define RCC_APB4RSTR1_HDPRST_Msk                (0x1UL << RCC_APB4RSTR1_HDPRST_Pos)   /*!< 0x00000004 */
27766 #define RCC_APB4RSTR1_HDPRST                    RCC_APB4RSTR1_HDPRST_Msk             /*!< HDP reset */
27767 #define RCC_APB4RSTR1_LPUART1RST_Pos            (3U)
27768 #define RCC_APB4RSTR1_LPUART1RST_Msk            (0x1UL << RCC_APB4RSTR1_LPUART1RST_Pos) /*!< 0x00000008 */
27769 #define RCC_APB4RSTR1_LPUART1RST                RCC_APB4RSTR1_LPUART1RST_Msk         /*!< LPUART1 reset */
27770 #define RCC_APB4RSTR1_SPI6RST_Pos               (5U)
27771 #define RCC_APB4RSTR1_SPI6RST_Msk               (0x1UL << RCC_APB4RSTR1_SPI6RST_Pos)  /*!< 0x00000020 */
27772 #define RCC_APB4RSTR1_SPI6RST                   RCC_APB4RSTR1_SPI6RST_Msk            /*!< SPI6 reset */
27773 #define RCC_APB4RSTR1_I2C4RST_Pos               (7U)
27774 #define RCC_APB4RSTR1_I2C4RST_Msk               (0x1UL << RCC_APB4RSTR1_I2C4RST_Pos)  /*!< 0x00000080 */
27775 #define RCC_APB4RSTR1_I2C4RST                   RCC_APB4RSTR1_I2C4RST_Msk            /*!< I2C4 reset */
27776 #define RCC_APB4RSTR1_LPTIM2RST_Pos             (9U)
27777 #define RCC_APB4RSTR1_LPTIM2RST_Msk             (0x1UL << RCC_APB4RSTR1_LPTIM2RST_Pos)/*!< 0x00000200 */
27778 #define RCC_APB4RSTR1_LPTIM2RST                 RCC_APB4RSTR1_LPTIM2RST_Msk          /*!< LPTIM2 reset */
27779 #define RCC_APB4RSTR1_LPTIM3RST_Pos             (10U)
27780 #define RCC_APB4RSTR1_LPTIM3RST_Msk             (0x1UL << RCC_APB4RSTR1_LPTIM3RST_Pos)/*!< 0x00000400 */
27781 #define RCC_APB4RSTR1_LPTIM3RST                 RCC_APB4RSTR1_LPTIM3RST_Msk          /*!< LPTIM3 reset */
27782 #define RCC_APB4RSTR1_LPTIM4RST_Pos             (11U)
27783 #define RCC_APB4RSTR1_LPTIM4RST_Msk             (0x1UL << RCC_APB4RSTR1_LPTIM4RST_Pos)/*!< 0x00000800 */
27784 #define RCC_APB4RSTR1_LPTIM4RST                 RCC_APB4RSTR1_LPTIM4RST_Msk          /*!< LPTIM4 reset */
27785 #define RCC_APB4RSTR1_LPTIM5RST_Pos             (12U)
27786 #define RCC_APB4RSTR1_LPTIM5RST_Msk             (0x1UL << RCC_APB4RSTR1_LPTIM5RST_Pos)/*!< 0x00001000 */
27787 #define RCC_APB4RSTR1_LPTIM5RST                 RCC_APB4RSTR1_LPTIM5RST_Msk          /*!< LPTIM5 reset */
27788 #define RCC_APB4RSTR1_VREFBUFRST_Pos            (15U)
27789 #define RCC_APB4RSTR1_VREFBUFRST_Msk            (0x1UL << RCC_APB4RSTR1_VREFBUFRST_Pos) /*!< 0x00008000 */
27790 #define RCC_APB4RSTR1_VREFBUFRST                RCC_APB4RSTR1_VREFBUFRST_Msk         /*!< VREFBUF reset */
27791 #define RCC_APB4RSTR1_RTCRST_Pos                (16U)
27792 #define RCC_APB4RSTR1_RTCRST_Msk                (0x1UL << RCC_APB4RSTR1_RTCRST_Pos)   /*!< 0x00010000 */
27793 #define RCC_APB4RSTR1_RTCRST                    RCC_APB4RSTR1_RTCRST_Msk             /*!< RTC reset */
27794 
27795 /****************  Bit definition for RCC_APB4RSTR2 register  *****************/
27796 #define RCC_APB4RSTR2_SYSCFGRST_Pos             (0U)
27797 #define RCC_APB4RSTR2_SYSCFGRST_Msk             (0x1UL << RCC_APB4RSTR2_SYSCFGRST_Pos)/*!< 0x00000001 */
27798 #define RCC_APB4RSTR2_SYSCFGRST                 RCC_APB4RSTR2_SYSCFGRST_Msk          /*!< SYSCFG reset */
27799 #define RCC_APB4RSTR2_DTSRST_Pos                (2U)
27800 #define RCC_APB4RSTR2_DTSRST_Msk                (0x1UL << RCC_APB4RSTR2_DTSRST_Pos)   /*!< 0x00000004 */
27801 #define RCC_APB4RSTR2_DTSRST                    RCC_APB4RSTR2_DTSRST_Msk             /*!< DTS reset */
27802 
27803 /*****************  Bit definition for RCC_APB5RSTR register  *****************/
27804 #define RCC_APB5RSTR_LTDCRST_Pos                (1U)
27805 #define RCC_APB5RSTR_LTDCRST_Msk                (0x1UL << RCC_APB5RSTR_LTDCRST_Pos)   /*!< 0x00000002 */
27806 #define RCC_APB5RSTR_LTDCRST                    RCC_APB5RSTR_LTDCRST_Msk             /*!< LTDC reset */
27807 #define RCC_APB5RSTR_DCMIPPRST_Pos              (2U)
27808 #define RCC_APB5RSTR_DCMIPPRST_Msk              (0x1UL << RCC_APB5RSTR_DCMIPPRST_Pos) /*!< 0x00000004 */
27809 #define RCC_APB5RSTR_DCMIPPRST                  RCC_APB5RSTR_DCMIPPRST_Msk           /*!< DCMIPP reset */
27810 #define RCC_APB5RSTR_GFXTIMRST_Pos              (4U)
27811 #define RCC_APB5RSTR_GFXTIMRST_Msk              (0x1UL << RCC_APB5RSTR_GFXTIMRST_Pos) /*!< 0x00000010 */
27812 #define RCC_APB5RSTR_GFXTIMRST                  RCC_APB5RSTR_GFXTIMRST_Msk           /*!< GFXTIM reset */
27813 #define RCC_APB5RSTR_VENCRST_Pos                (5U)
27814 #define RCC_APB5RSTR_VENCRST_Msk                (0x1UL << RCC_APB5RSTR_VENCRST_Pos)   /*!< 0x00000020 */
27815 #define RCC_APB5RSTR_VENCRST                    RCC_APB5RSTR_VENCRST_Msk             /*!< VENC reset */
27816 #define RCC_APB5RSTR_CSIRST_Pos                 (6U)
27817 #define RCC_APB5RSTR_CSIRST_Msk                 (0x1UL << RCC_APB5RSTR_CSIRST_Pos)    /*!< 0x00000040 */
27818 #define RCC_APB5RSTR_CSIRST                     RCC_APB5RSTR_CSIRST_Msk              /*!< CSI reset */
27819 
27820 /******************  Bit definition for RCC_DIVENR register  ******************/
27821 #define RCC_DIVENR_IC1EN_Pos                    (0U)
27822 #define RCC_DIVENR_IC1EN_Msk                    (0x1UL << RCC_DIVENR_IC1EN_Pos)       /*!< 0x00000001 */
27823 #define RCC_DIVENR_IC1EN                        RCC_DIVENR_IC1EN_Msk                 /*!< IC1 enable */
27824 #define RCC_DIVENR_IC2EN_Pos                    (1U)
27825 #define RCC_DIVENR_IC2EN_Msk                    (0x1UL << RCC_DIVENR_IC2EN_Pos)       /*!< 0x00000002 */
27826 #define RCC_DIVENR_IC2EN                        RCC_DIVENR_IC2EN_Msk                 /*!< IC2 enable */
27827 #define RCC_DIVENR_IC3EN_Pos                    (2U)
27828 #define RCC_DIVENR_IC3EN_Msk                    (0x1UL << RCC_DIVENR_IC3EN_Pos)       /*!< 0x00000004 */
27829 #define RCC_DIVENR_IC3EN                        RCC_DIVENR_IC3EN_Msk                 /*!< IC3 enable */
27830 #define RCC_DIVENR_IC4EN_Pos                    (3U)
27831 #define RCC_DIVENR_IC4EN_Msk                    (0x1UL << RCC_DIVENR_IC4EN_Pos)       /*!< 0x00000008 */
27832 #define RCC_DIVENR_IC4EN                        RCC_DIVENR_IC4EN_Msk                 /*!< IC4 enable */
27833 #define RCC_DIVENR_IC5EN_Pos                    (4U)
27834 #define RCC_DIVENR_IC5EN_Msk                    (0x1UL << RCC_DIVENR_IC5EN_Pos)       /*!< 0x00000010 */
27835 #define RCC_DIVENR_IC5EN                        RCC_DIVENR_IC5EN_Msk                 /*!< IC5 enable */
27836 #define RCC_DIVENR_IC6EN_Pos                    (5U)
27837 #define RCC_DIVENR_IC6EN_Msk                    (0x1UL << RCC_DIVENR_IC6EN_Pos)       /*!< 0x00000020 */
27838 #define RCC_DIVENR_IC6EN                        RCC_DIVENR_IC6EN_Msk                 /*!< IC6 enable */
27839 #define RCC_DIVENR_IC7EN_Pos                    (6U)
27840 #define RCC_DIVENR_IC7EN_Msk                    (0x1UL << RCC_DIVENR_IC7EN_Pos)       /*!< 0x00000040 */
27841 #define RCC_DIVENR_IC7EN                        RCC_DIVENR_IC7EN_Msk                 /*!< IC7 enable */
27842 #define RCC_DIVENR_IC8EN_Pos                    (7U)
27843 #define RCC_DIVENR_IC8EN_Msk                    (0x1UL << RCC_DIVENR_IC8EN_Pos)       /*!< 0x00000080 */
27844 #define RCC_DIVENR_IC8EN                        RCC_DIVENR_IC8EN_Msk                 /*!< IC8 enable */
27845 #define RCC_DIVENR_IC9EN_Pos                    (8U)
27846 #define RCC_DIVENR_IC9EN_Msk                    (0x1UL << RCC_DIVENR_IC9EN_Pos)       /*!< 0x00000100 */
27847 #define RCC_DIVENR_IC9EN                        RCC_DIVENR_IC9EN_Msk                 /*!< IC9 enable */
27848 #define RCC_DIVENR_IC10EN_Pos                   (9U)
27849 #define RCC_DIVENR_IC10EN_Msk                   (0x1UL << RCC_DIVENR_IC10EN_Pos)      /*!< 0x00000200 */
27850 #define RCC_DIVENR_IC10EN                       RCC_DIVENR_IC10EN_Msk                /*!< IC10 enable */
27851 #define RCC_DIVENR_IC11EN_Pos                   (10U)
27852 #define RCC_DIVENR_IC11EN_Msk                   (0x1UL << RCC_DIVENR_IC11EN_Pos)      /*!< 0x00000400 */
27853 #define RCC_DIVENR_IC11EN                       RCC_DIVENR_IC11EN_Msk                /*!< IC11 enable */
27854 #define RCC_DIVENR_IC12EN_Pos                   (11U)
27855 #define RCC_DIVENR_IC12EN_Msk                   (0x1UL << RCC_DIVENR_IC12EN_Pos)      /*!< 0x00000800 */
27856 #define RCC_DIVENR_IC12EN                       RCC_DIVENR_IC12EN_Msk                /*!< IC12 enable */
27857 #define RCC_DIVENR_IC13EN_Pos                   (12U)
27858 #define RCC_DIVENR_IC13EN_Msk                   (0x1UL << RCC_DIVENR_IC13EN_Pos)      /*!< 0x00001000 */
27859 #define RCC_DIVENR_IC13EN                       RCC_DIVENR_IC13EN_Msk                /*!< IC13 enable */
27860 #define RCC_DIVENR_IC14EN_Pos                   (13U)
27861 #define RCC_DIVENR_IC14EN_Msk                   (0x1UL << RCC_DIVENR_IC14EN_Pos)      /*!< 0x00002000 */
27862 #define RCC_DIVENR_IC14EN                       RCC_DIVENR_IC14EN_Msk                /*!< IC14 enable */
27863 #define RCC_DIVENR_IC15EN_Pos                   (14U)
27864 #define RCC_DIVENR_IC15EN_Msk                   (0x1UL << RCC_DIVENR_IC15EN_Pos)      /*!< 0x00004000 */
27865 #define RCC_DIVENR_IC15EN                       RCC_DIVENR_IC15EN_Msk                /*!< IC15 enable */
27866 #define RCC_DIVENR_IC16EN_Pos                   (15U)
27867 #define RCC_DIVENR_IC16EN_Msk                   (0x1UL << RCC_DIVENR_IC16EN_Pos)      /*!< 0x00008000 */
27868 #define RCC_DIVENR_IC16EN                       RCC_DIVENR_IC16EN_Msk                /*!< IC16 enable */
27869 #define RCC_DIVENR_IC17EN_Pos                   (16U)
27870 #define RCC_DIVENR_IC17EN_Msk                   (0x1UL << RCC_DIVENR_IC17EN_Pos)      /*!< 0x00010000 */
27871 #define RCC_DIVENR_IC17EN                       RCC_DIVENR_IC17EN_Msk                /*!< IC17 enable */
27872 #define RCC_DIVENR_IC18EN_Pos                   (17U)
27873 #define RCC_DIVENR_IC18EN_Msk                   (0x1UL << RCC_DIVENR_IC18EN_Pos)      /*!< 0x00020000 */
27874 #define RCC_DIVENR_IC18EN                       RCC_DIVENR_IC18EN_Msk                /*!< IC18 enable */
27875 #define RCC_DIVENR_IC19EN_Pos                   (18U)
27876 #define RCC_DIVENR_IC19EN_Msk                   (0x1UL << RCC_DIVENR_IC19EN_Pos)      /*!< 0x00040000 */
27877 #define RCC_DIVENR_IC19EN                       RCC_DIVENR_IC19EN_Msk                /*!< IC19 enable */
27878 #define RCC_DIVENR_IC20EN_Pos                   (19U)
27879 #define RCC_DIVENR_IC20EN_Msk                   (0x1UL << RCC_DIVENR_IC20EN_Pos)      /*!< 0x00080000 */
27880 #define RCC_DIVENR_IC20EN                       RCC_DIVENR_IC20EN_Msk                /*!< IC20 enable */
27881 
27882 /******************  Bit definition for RCC_BUSENR register  ******************/
27883 #define RCC_BUSENR_ACLKNEN_Pos                  (0U)
27884 #define RCC_BUSENR_ACLKNEN_Msk                  (0x1UL << RCC_BUSENR_ACLKNEN_Pos)     /*!< 0x00000001 */
27885 #define RCC_BUSENR_ACLKNEN                      RCC_BUSENR_ACLKNEN_Msk               /*!< ACLKN enable */
27886 #define RCC_BUSENR_ACLKNCEN_Pos                 (1U)
27887 #define RCC_BUSENR_ACLKNCEN_Msk                 (0x1UL << RCC_BUSENR_ACLKNCEN_Pos)    /*!< 0x00000002 */
27888 #define RCC_BUSENR_ACLKNCEN                     RCC_BUSENR_ACLKNCEN_Msk              /*!< ACLKNC enable */
27889 #define RCC_BUSENR_AHBMEN_Pos                   (2U)
27890 #define RCC_BUSENR_AHBMEN_Msk                   (0x1UL << RCC_BUSENR_AHBMEN_Pos)      /*!< 0x00000004 */
27891 #define RCC_BUSENR_AHBMEN                       RCC_BUSENR_AHBMEN_Msk                /*!< AHBM enable */
27892 #define RCC_BUSENR_AHB1EN_Pos                   (3U)
27893 #define RCC_BUSENR_AHB1EN_Msk                   (0x1UL << RCC_BUSENR_AHB1EN_Pos)      /*!< 0x00000008 */
27894 #define RCC_BUSENR_AHB1EN                       RCC_BUSENR_AHB1EN_Msk                /*!< AHB1 enable */
27895 #define RCC_BUSENR_AHB2EN_Pos                   (4U)
27896 #define RCC_BUSENR_AHB2EN_Msk                   (0x1UL << RCC_BUSENR_AHB2EN_Pos)      /*!< 0x00000010 */
27897 #define RCC_BUSENR_AHB2EN                       RCC_BUSENR_AHB2EN_Msk                /*!< AHB2 enable */
27898 #define RCC_BUSENR_AHB3EN_Pos                   (5U)
27899 #define RCC_BUSENR_AHB3EN_Msk                   (0x1UL << RCC_BUSENR_AHB3EN_Pos)      /*!< 0x00000020 */
27900 #define RCC_BUSENR_AHB3EN                       RCC_BUSENR_AHB3EN_Msk                /*!< AHB3 enable */
27901 #define RCC_BUSENR_AHB4EN_Pos                   (6U)
27902 #define RCC_BUSENR_AHB4EN_Msk                   (0x1UL << RCC_BUSENR_AHB4EN_Pos)      /*!< 0x00000040 */
27903 #define RCC_BUSENR_AHB4EN                       RCC_BUSENR_AHB4EN_Msk                /*!< AHB4 enable */
27904 #define RCC_BUSENR_AHB5EN_Pos                   (7U)
27905 #define RCC_BUSENR_AHB5EN_Msk                   (0x1UL << RCC_BUSENR_AHB5EN_Pos)      /*!< 0x00000080 */
27906 #define RCC_BUSENR_AHB5EN                       RCC_BUSENR_AHB5EN_Msk                /*!< AHB5 enable */
27907 #define RCC_BUSENR_APB1EN_Pos                   (8U)
27908 #define RCC_BUSENR_APB1EN_Msk                   (0x1UL << RCC_BUSENR_APB1EN_Pos)      /*!< 0x00000100 */
27909 #define RCC_BUSENR_APB1EN                       RCC_BUSENR_APB1EN_Msk                /*!< APB1 enable */
27910 #define RCC_BUSENR_APB2EN_Pos                   (9U)
27911 #define RCC_BUSENR_APB2EN_Msk                   (0x1UL << RCC_BUSENR_APB2EN_Pos)      /*!< 0x00000200 */
27912 #define RCC_BUSENR_APB2EN                       RCC_BUSENR_APB2EN_Msk                /*!< APB2 enable */
27913 #define RCC_BUSENR_APB3EN_Pos                   (10U)
27914 #define RCC_BUSENR_APB3EN_Msk                   (0x1UL << RCC_BUSENR_APB3EN_Pos)      /*!< 0x00000400 */
27915 #define RCC_BUSENR_APB3EN                       RCC_BUSENR_APB3EN_Msk                /*!< APB3 enable */
27916 #define RCC_BUSENR_APB4EN_Pos                   (11U)
27917 #define RCC_BUSENR_APB4EN_Msk                   (0x1UL << RCC_BUSENR_APB4EN_Pos)      /*!< 0x00000800 */
27918 #define RCC_BUSENR_APB4EN                       RCC_BUSENR_APB4EN_Msk                /*!< APB4 enable */
27919 #define RCC_BUSENR_APB5EN_Pos                   (12U)
27920 #define RCC_BUSENR_APB5EN_Msk                   (0x1UL << RCC_BUSENR_APB5EN_Pos)      /*!< 0x00001000 */
27921 #define RCC_BUSENR_APB5EN                       RCC_BUSENR_APB5EN_Msk                /*!< APB5 enable */
27922 
27923 /*****************  Bit definition for RCC_MISCENR register  ******************/
27924 #define RCC_MISCENR_DBGEN_Pos                   (0U)
27925 #define RCC_MISCENR_DBGEN_Msk                   (0x1UL << RCC_MISCENR_DBGEN_Pos)      /*!< 0x00000001 */
27926 #define RCC_MISCENR_DBGEN                       RCC_MISCENR_DBGEN_Msk                /*!< DBG enable */
27927 #define RCC_MISCENR_MCO1EN_Pos                  (1U)
27928 #define RCC_MISCENR_MCO1EN_Msk                  (0x1UL << RCC_MISCENR_MCO1EN_Pos)     /*!< 0x00000002 */
27929 #define RCC_MISCENR_MCO1EN                      RCC_MISCENR_MCO1EN_Msk               /*!< MCO1 enable */
27930 #define RCC_MISCENR_MCO2EN_Pos                  (2U)
27931 #define RCC_MISCENR_MCO2EN_Msk                  (0x1UL << RCC_MISCENR_MCO2EN_Pos)     /*!< 0x00000004 */
27932 #define RCC_MISCENR_MCO2EN                      RCC_MISCENR_MCO2EN_Msk               /*!< MCO2 enable */
27933 #define RCC_MISCENR_XSPIPHYCOMPEN_Pos           (3U)
27934 #define RCC_MISCENR_XSPIPHYCOMPEN_Msk           (0x1UL << RCC_MISCENR_XSPIPHYCOMPEN_Pos)  /*!< 0x00000008 */
27935 #define RCC_MISCENR_XSPIPHYCOMPEN               RCC_MISCENR_XSPIPHYCOMPEN_Msk        /*!< XSPIPHYCOMP enable */
27936 #define RCC_MISCENR_PEREN_Pos                   (6U)
27937 #define RCC_MISCENR_PEREN_Msk                   (0x1UL << RCC_MISCENR_PEREN_Pos)      /*!< 0x00000040 */
27938 #define RCC_MISCENR_PEREN                       RCC_MISCENR_PEREN_Msk                /*!< PER enable */
27939 
27940 /******************  Bit definition for RCC_MEMENR register  ******************/
27941 #define RCC_MEMENR_AXISRAM3EN_Pos               (0U)
27942 #define RCC_MEMENR_AXISRAM3EN_Msk               (0x1UL << RCC_MEMENR_AXISRAM3EN_Pos)  /*!< 0x00000001 */
27943 #define RCC_MEMENR_AXISRAM3EN                   RCC_MEMENR_AXISRAM3EN_Msk            /*!< AXISRAM3 enable */
27944 #define RCC_MEMENR_AXISRAM4EN_Pos               (1U)
27945 #define RCC_MEMENR_AXISRAM4EN_Msk               (0x1UL << RCC_MEMENR_AXISRAM4EN_Pos)  /*!< 0x00000002 */
27946 #define RCC_MEMENR_AXISRAM4EN                   RCC_MEMENR_AXISRAM4EN_Msk            /*!< AXISRAM4 enable */
27947 #define RCC_MEMENR_AXISRAM5EN_Pos               (2U)
27948 #define RCC_MEMENR_AXISRAM5EN_Msk               (0x1UL << RCC_MEMENR_AXISRAM5EN_Pos)  /*!< 0x00000004 */
27949 #define RCC_MEMENR_AXISRAM5EN                   RCC_MEMENR_AXISRAM5EN_Msk            /*!< AXISRAM5 enable */
27950 #define RCC_MEMENR_AXISRAM6EN_Pos               (3U)
27951 #define RCC_MEMENR_AXISRAM6EN_Msk               (0x1UL << RCC_MEMENR_AXISRAM6EN_Pos)  /*!< 0x00000008 */
27952 #define RCC_MEMENR_AXISRAM6EN                   RCC_MEMENR_AXISRAM6EN_Msk            /*!< AXISRAM6 enable */
27953 #define RCC_MEMENR_AHBSRAM1EN_Pos               (4U)
27954 #define RCC_MEMENR_AHBSRAM1EN_Msk               (0x1UL << RCC_MEMENR_AHBSRAM1EN_Pos)  /*!< 0x00000010 */
27955 #define RCC_MEMENR_AHBSRAM1EN                   RCC_MEMENR_AHBSRAM1EN_Msk            /*!< AHBSRAM1 enable */
27956 #define RCC_MEMENR_AHBSRAM2EN_Pos               (5U)
27957 #define RCC_MEMENR_AHBSRAM2EN_Msk               (0x1UL << RCC_MEMENR_AHBSRAM2EN_Pos)  /*!< 0x00000020 */
27958 #define RCC_MEMENR_AHBSRAM2EN                   RCC_MEMENR_AHBSRAM2EN_Msk            /*!< AHBSRAM2 enable */
27959 #define RCC_MEMENR_BKPSRAMEN_Pos                (6U)
27960 #define RCC_MEMENR_BKPSRAMEN_Msk                (0x1UL << RCC_MEMENR_BKPSRAMEN_Pos)   /*!< 0x00000040 */
27961 #define RCC_MEMENR_BKPSRAMEN                    RCC_MEMENR_BKPSRAMEN_Msk             /*!< BKPSRAM enable */
27962 #define RCC_MEMENR_AXISRAM1EN_Pos               (7U)
27963 #define RCC_MEMENR_AXISRAM1EN_Msk               (0x1UL << RCC_MEMENR_AXISRAM1EN_Pos)  /*!< 0x00000080 */
27964 #define RCC_MEMENR_AXISRAM1EN                   RCC_MEMENR_AXISRAM1EN_Msk            /*!< AXISRAM1 enable */
27965 #define RCC_MEMENR_AXISRAM2EN_Pos               (8U)
27966 #define RCC_MEMENR_AXISRAM2EN_Msk               (0x1UL << RCC_MEMENR_AXISRAM2EN_Pos)  /*!< 0x00000100 */
27967 #define RCC_MEMENR_AXISRAM2EN                   RCC_MEMENR_AXISRAM2EN_Msk            /*!< AXISRAM2 enable */
27968 #define RCC_MEMENR_FLEXRAMEN_Pos                (9U)
27969 #define RCC_MEMENR_FLEXRAMEN_Msk                (0x1UL << RCC_MEMENR_FLEXRAMEN_Pos)   /*!< 0x00000200 */
27970 #define RCC_MEMENR_FLEXRAMEN                    RCC_MEMENR_FLEXRAMEN_Msk             /*!< FLEXRAM enable */
27971 #define RCC_MEMENR_CACHEAXIRAMEN_Pos            (10U)
27972 #define RCC_MEMENR_CACHEAXIRAMEN_Msk            (0x1UL << RCC_MEMENR_CACHEAXIRAMEN_Pos) /*!< 0x00000400 */
27973 #define RCC_MEMENR_CACHEAXIRAMEN                RCC_MEMENR_CACHEAXIRAMEN_Msk         /*!< CACHEAXIRAM enable */
27974 #define RCC_MEMENR_VENCRAMEN_Pos                (11U)
27975 #define RCC_MEMENR_VENCRAMEN_Msk                (0x1UL << RCC_MEMENR_VENCRAMEN_Pos)   /*!< 0x00000800 */
27976 #define RCC_MEMENR_VENCRAMEN                    RCC_MEMENR_VENCRAMEN_Msk             /*!< VENCRAM enable */
27977 #define RCC_MEMENR_BOOTROMEN_Pos                (12U)
27978 #define RCC_MEMENR_BOOTROMEN_Msk                (0x1UL << RCC_MEMENR_BOOTROMEN_Pos)   /*!< 0x00001000 */
27979 #define RCC_MEMENR_BOOTROMEN                    RCC_MEMENR_BOOTROMEN_Msk             /*!< Boot ROM enable */
27980 
27981 /*****************  Bit definition for RCC_AHB1ENR register  ******************/
27982 #define RCC_AHB1ENR_GPDMA1EN_Pos                (4U)
27983 #define RCC_AHB1ENR_GPDMA1EN_Msk                (0x1UL << RCC_AHB1ENR_GPDMA1EN_Pos)   /*!< 0x00000010 */
27984 #define RCC_AHB1ENR_GPDMA1EN                    RCC_AHB1ENR_GPDMA1EN_Msk             /*!< GPDMA1 enable */
27985 #define RCC_AHB1ENR_ADC12EN_Pos                 (5U)
27986 #define RCC_AHB1ENR_ADC12EN_Msk                 (0x1UL << RCC_AHB1ENR_ADC12EN_Pos)    /*!< 0x00000020 */
27987 #define RCC_AHB1ENR_ADC12EN                     RCC_AHB1ENR_ADC12EN_Msk              /*!< ADC12 enable */
27988 
27989 /*****************  Bit definition for RCC_AHB2ENR register  ******************/
27990 #define RCC_AHB2ENR_RAMCFGEN_Pos                (12U)
27991 #define RCC_AHB2ENR_RAMCFGEN_Msk                (0x1UL << RCC_AHB2ENR_RAMCFGEN_Pos)   /*!< 0x00001000 */
27992 #define RCC_AHB2ENR_RAMCFGEN                    RCC_AHB2ENR_RAMCFGEN_Msk             /*!< RAMCFG enable */
27993 #define RCC_AHB2ENR_MDF1EN_Pos                  (16U)
27994 #define RCC_AHB2ENR_MDF1EN_Msk                  (0x1UL << RCC_AHB2ENR_MDF1EN_Pos)     /*!< 0x00010000 */
27995 #define RCC_AHB2ENR_MDF1EN                      RCC_AHB2ENR_MDF1EN_Msk               /*!< MDF1 enable */
27996 #define RCC_AHB2ENR_ADF1EN_Pos                  (17U)
27997 #define RCC_AHB2ENR_ADF1EN_Msk                  (0x1UL << RCC_AHB2ENR_ADF1EN_Pos)     /*!< 0x00020000 */
27998 #define RCC_AHB2ENR_ADF1EN                      RCC_AHB2ENR_ADF1EN_Msk               /*!< ADF1 enable */
27999 
28000 /*****************  Bit definition for RCC_AHB3ENR register  ******************/
28001 #define RCC_AHB3ENR_RNGEN_Pos                   (0U)
28002 #define RCC_AHB3ENR_RNGEN_Msk                   (0x1UL << RCC_AHB3ENR_RNGEN_Pos)      /*!< 0x00000001 */
28003 #define RCC_AHB3ENR_RNGEN                       RCC_AHB3ENR_RNGEN_Msk                /*!< RNG enable */
28004 #define RCC_AHB3ENR_HASHEN_Pos                  (1U)
28005 #define RCC_AHB3ENR_HASHEN_Msk                  (0x1UL << RCC_AHB3ENR_HASHEN_Pos)     /*!< 0x00000002 */
28006 #define RCC_AHB3ENR_HASHEN                      RCC_AHB3ENR_HASHEN_Msk               /*!< HASH enable */
28007 #define RCC_AHB3ENR_CRYPEN_Pos                  (2U)
28008 #define RCC_AHB3ENR_CRYPEN_Msk                  (0x1UL << RCC_AHB3ENR_CRYPEN_Pos)     /*!< 0x00000004 */
28009 #define RCC_AHB3ENR_CRYPEN                      RCC_AHB3ENR_CRYPEN_Msk               /*!< CRYP enable */
28010 #define RCC_AHB3ENR_SAESEN_Pos                  (4U)
28011 #define RCC_AHB3ENR_SAESEN_Msk                  (0x1UL << RCC_AHB3ENR_SAESEN_Pos)     /*!< 0x00000010 */
28012 #define RCC_AHB3ENR_SAESEN                      RCC_AHB3ENR_SAESEN_Msk               /*!< SAES enable */
28013 #define RCC_AHB3ENR_PKAEN_Pos                   (8U)
28014 #define RCC_AHB3ENR_PKAEN_Msk                   (0x1UL << RCC_AHB3ENR_PKAEN_Pos)      /*!< 0x00000100 */
28015 #define RCC_AHB3ENR_PKAEN                       RCC_AHB3ENR_PKAEN_Msk                /*!< PKA enable */
28016 #define RCC_AHB3ENR_RIFSCEN_Pos                 (9U)
28017 #define RCC_AHB3ENR_RIFSCEN_Msk                 (0x1UL << RCC_AHB3ENR_RIFSCEN_Pos)    /*!< 0x00000200 */
28018 #define RCC_AHB3ENR_RIFSCEN                     RCC_AHB3ENR_RIFSCEN_Msk              /*!< RIFSC enable */
28019 #define RCC_AHB3ENR_IACEN_Pos                   (10U)
28020 #define RCC_AHB3ENR_IACEN_Msk                   (0x1UL << RCC_AHB3ENR_IACEN_Pos)      /*!< 0x00000400 */
28021 #define RCC_AHB3ENR_IACEN                       RCC_AHB3ENR_IACEN_Msk                /*!< IAC enable */
28022 #define RCC_AHB3ENR_RISAFEN_Pos                 (14U)
28023 #define RCC_AHB3ENR_RISAFEN_Msk                 (0x1UL << RCC_AHB3ENR_RISAFEN_Pos)    /*!< 0x00004000 */
28024 #define RCC_AHB3ENR_RISAFEN                     RCC_AHB3ENR_RISAFEN_Msk              /*!< RISAF enable */
28025 
28026 /*****************  Bit definition for RCC_AHB4ENR register  ******************/
28027 #define RCC_AHB4ENR_GPIOAEN_Pos                 (0U)
28028 #define RCC_AHB4ENR_GPIOAEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos)    /*!< 0x00000001 */
28029 #define RCC_AHB4ENR_GPIOAEN                     RCC_AHB4ENR_GPIOAEN_Msk              /*!< GPIO A enable */
28030 #define RCC_AHB4ENR_GPIOBEN_Pos                 (1U)
28031 #define RCC_AHB4ENR_GPIOBEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos)    /*!< 0x00000002 */
28032 #define RCC_AHB4ENR_GPIOBEN                     RCC_AHB4ENR_GPIOBEN_Msk              /*!< GPIO B enable */
28033 #define RCC_AHB4ENR_GPIOCEN_Pos                 (2U)
28034 #define RCC_AHB4ENR_GPIOCEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos)    /*!< 0x00000004 */
28035 #define RCC_AHB4ENR_GPIOCEN                     RCC_AHB4ENR_GPIOCEN_Msk              /*!< GPIO C enable */
28036 #define RCC_AHB4ENR_GPIODEN_Pos                 (3U)
28037 #define RCC_AHB4ENR_GPIODEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIODEN_Pos)    /*!< 0x00000008 */
28038 #define RCC_AHB4ENR_GPIODEN                     RCC_AHB4ENR_GPIODEN_Msk              /*!< GPIO D enable */
28039 #define RCC_AHB4ENR_GPIOEEN_Pos                 (4U)
28040 #define RCC_AHB4ENR_GPIOEEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos)    /*!< 0x00000010 */
28041 #define RCC_AHB4ENR_GPIOEEN                     RCC_AHB4ENR_GPIOEEN_Msk              /*!< GPIO E enable */
28042 #define RCC_AHB4ENR_GPIOFEN_Pos                 (5U)
28043 #define RCC_AHB4ENR_GPIOFEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos)    /*!< 0x00000020 */
28044 #define RCC_AHB4ENR_GPIOFEN                     RCC_AHB4ENR_GPIOFEN_Msk              /*!< GPIO F enable */
28045 #define RCC_AHB4ENR_GPIOGEN_Pos                 (6U)
28046 #define RCC_AHB4ENR_GPIOGEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos)    /*!< 0x00000040 */
28047 #define RCC_AHB4ENR_GPIOGEN                     RCC_AHB4ENR_GPIOGEN_Msk              /*!< GPIO G enable */
28048 #define RCC_AHB4ENR_GPIOHEN_Pos                 (7U)
28049 #define RCC_AHB4ENR_GPIOHEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos)    /*!< 0x00000080 */
28050 #define RCC_AHB4ENR_GPIOHEN                     RCC_AHB4ENR_GPIOHEN_Msk              /*!< GPIO H enable */
28051 #define RCC_AHB4ENR_GPIONEN_Pos                 (13U)
28052 #define RCC_AHB4ENR_GPIONEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIONEN_Pos)    /*!< 0x00002000 */
28053 #define RCC_AHB4ENR_GPIONEN                     RCC_AHB4ENR_GPIONEN_Msk              /*!< GPIO N enable */
28054 #define RCC_AHB4ENR_GPIOOEN_Pos                 (14U)
28055 #define RCC_AHB4ENR_GPIOOEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOOEN_Pos)    /*!< 0x00004000 */
28056 #define RCC_AHB4ENR_GPIOOEN                     RCC_AHB4ENR_GPIOOEN_Msk              /*!< GPIO O enable */
28057 #define RCC_AHB4ENR_GPIOPEN_Pos                 (15U)
28058 #define RCC_AHB4ENR_GPIOPEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOPEN_Pos)    /*!< 0x00008000 */
28059 #define RCC_AHB4ENR_GPIOPEN                     RCC_AHB4ENR_GPIOPEN_Msk              /*!< GPIO P enable */
28060 #define RCC_AHB4ENR_GPIOQEN_Pos                 (16U)
28061 #define RCC_AHB4ENR_GPIOQEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOQEN_Pos)    /*!< 0x00010000 */
28062 #define RCC_AHB4ENR_GPIOQEN                     RCC_AHB4ENR_GPIOQEN_Msk              /*!< GPIO Q enable */
28063 #define RCC_AHB4ENR_PWREN_Pos                   (18U)
28064 #define RCC_AHB4ENR_PWREN_Msk                   (0x1UL << RCC_AHB4ENR_PWREN_Pos)      /*!< 0x00040000 */
28065 #define RCC_AHB4ENR_PWREN                       RCC_AHB4ENR_PWREN_Msk                /*!< PWR enable */
28066 #define RCC_AHB4ENR_CRCEN_Pos                   (19U)
28067 #define RCC_AHB4ENR_CRCEN_Msk                   (0x1UL << RCC_AHB4ENR_CRCEN_Pos)      /*!< 0x00080000 */
28068 #define RCC_AHB4ENR_CRCEN                       RCC_AHB4ENR_CRCEN_Msk                /*!< CRC enable */
28069 
28070 /*****************  Bit definition for RCC_AHB5ENR register  ******************/
28071 #define RCC_AHB5ENR_HPDMA1EN_Pos                (0U)
28072 #define RCC_AHB5ENR_HPDMA1EN_Msk                (0x1UL << RCC_AHB5ENR_HPDMA1EN_Pos)   /*!< 0x00000001 */
28073 #define RCC_AHB5ENR_HPDMA1EN                    RCC_AHB5ENR_HPDMA1EN_Msk             /*!< HPDMA1 enable */
28074 #define RCC_AHB5ENR_DMA2DEN_Pos                 (1U)
28075 #define RCC_AHB5ENR_DMA2DEN_Msk                 (0x1UL << RCC_AHB5ENR_DMA2DEN_Pos)    /*!< 0x00000002 */
28076 #define RCC_AHB5ENR_DMA2DEN                     RCC_AHB5ENR_DMA2DEN_Msk              /*!< DMA2D enable */
28077 #define RCC_AHB5ENR_JPEGEN_Pos                  (3U)
28078 #define RCC_AHB5ENR_JPEGEN_Msk                  (0x1UL << RCC_AHB5ENR_JPEGEN_Pos)     /*!< 0x00000008 */
28079 #define RCC_AHB5ENR_JPEGEN                      RCC_AHB5ENR_JPEGEN_Msk               /*!< JPEG enable */
28080 #define RCC_AHB5ENR_FMCEN_Pos                   (4U)
28081 #define RCC_AHB5ENR_FMCEN_Msk                   (0x1UL << RCC_AHB5ENR_FMCEN_Pos)      /*!< 0x00000010 */
28082 #define RCC_AHB5ENR_FMCEN                       RCC_AHB5ENR_FMCEN_Msk                /*!< FMC enable */
28083 #define RCC_AHB5ENR_XSPI1EN_Pos                 (5U)
28084 #define RCC_AHB5ENR_XSPI1EN_Msk                 (0x1UL << RCC_AHB5ENR_XSPI1EN_Pos)    /*!< 0x00000020 */
28085 #define RCC_AHB5ENR_XSPI1EN                     RCC_AHB5ENR_XSPI1EN_Msk              /*!< XSPI1 enable */
28086 #define RCC_AHB5ENR_PSSIEN_Pos                  (6U)
28087 #define RCC_AHB5ENR_PSSIEN_Msk                  (0x1UL << RCC_AHB5ENR_PSSIEN_Pos)     /*!< 0x00000040 */
28088 #define RCC_AHB5ENR_PSSIEN                      RCC_AHB5ENR_PSSIEN_Msk               /*!< PSSI enable */
28089 #define RCC_AHB5ENR_SDMMC2EN_Pos                (7U)
28090 #define RCC_AHB5ENR_SDMMC2EN_Msk                (0x1UL << RCC_AHB5ENR_SDMMC2EN_Pos)   /*!< 0x00000080 */
28091 #define RCC_AHB5ENR_SDMMC2EN                    RCC_AHB5ENR_SDMMC2EN_Msk             /*!< SDMMC2 enable */
28092 #define RCC_AHB5ENR_SDMMC1EN_Pos                (8U)
28093 #define RCC_AHB5ENR_SDMMC1EN_Msk                (0x1UL << RCC_AHB5ENR_SDMMC1EN_Pos)   /*!< 0x00000100 */
28094 #define RCC_AHB5ENR_SDMMC1EN                    RCC_AHB5ENR_SDMMC1EN_Msk             /*!< SDMMC1 enable */
28095 #define RCC_AHB5ENR_XSPI2EN_Pos                 (12U)
28096 #define RCC_AHB5ENR_XSPI2EN_Msk                 (0x1UL << RCC_AHB5ENR_XSPI2EN_Pos)    /*!< 0x00001000 */
28097 #define RCC_AHB5ENR_XSPI2EN                     RCC_AHB5ENR_XSPI2EN_Msk              /*!< XSPI2 enable */
28098 #define RCC_AHB5ENR_XSPIMEN_Pos                 (13U)
28099 #define RCC_AHB5ENR_XSPIMEN_Msk                 (0x1UL << RCC_AHB5ENR_XSPIMEN_Pos)    /*!< 0x00002000 */
28100 #define RCC_AHB5ENR_XSPIMEN                     RCC_AHB5ENR_XSPIMEN_Msk              /*!< XSPIM enable */
28101 #define RCC_AHB5ENR_MCE1EN_Pos                  (14U)
28102 #define RCC_AHB5ENR_MCE1EN_Msk                  (0x1UL << RCC_AHB5ENR_MCE1EN_Pos)     /*!< 0x00004000 */
28103 #define RCC_AHB5ENR_MCE1EN                      RCC_AHB5ENR_MCE1EN_Msk               /*!< MCE1 enable */
28104 #define RCC_AHB5ENR_MCE2EN_Pos                  (15U)
28105 #define RCC_AHB5ENR_MCE2EN_Msk                  (0x1UL << RCC_AHB5ENR_MCE2EN_Pos)     /*!< 0x00008000 */
28106 #define RCC_AHB5ENR_MCE2EN                      RCC_AHB5ENR_MCE2EN_Msk               /*!< MCE2 enable */
28107 #define RCC_AHB5ENR_MCE3EN_Pos                  (16U)
28108 #define RCC_AHB5ENR_MCE3EN_Msk                  (0x1UL << RCC_AHB5ENR_MCE3EN_Pos)     /*!< 0x00010000 */
28109 #define RCC_AHB5ENR_MCE3EN                      RCC_AHB5ENR_MCE3EN_Msk               /*!< MCE3 enable */
28110 #define RCC_AHB5ENR_XSPI3EN_Pos                 (17U)
28111 #define RCC_AHB5ENR_XSPI3EN_Msk                 (0x1UL << RCC_AHB5ENR_XSPI3EN_Pos)    /*!< 0x00020000 */
28112 #define RCC_AHB5ENR_XSPI3EN                     RCC_AHB5ENR_XSPI3EN_Msk              /*!< XSPI3 enable */
28113 #define RCC_AHB5ENR_MCE4EN_Pos                  (18U)
28114 #define RCC_AHB5ENR_MCE4EN_Msk                  (0x1UL << RCC_AHB5ENR_MCE4EN_Pos)     /*!< 0x00040000 */
28115 #define RCC_AHB5ENR_MCE4EN                      RCC_AHB5ENR_MCE4EN_Msk               /*!< MCE4 enable */
28116 #define RCC_AHB5ENR_GFXMMUEN_Pos                (19U)
28117 #define RCC_AHB5ENR_GFXMMUEN_Msk                (0x1UL << RCC_AHB5ENR_GFXMMUEN_Pos)   /*!< 0x00080000 */
28118 #define RCC_AHB5ENR_GFXMMUEN                    RCC_AHB5ENR_GFXMMUEN_Msk             /*!< GFXMMU enable */
28119 #define RCC_AHB5ENR_GPU2DEN_Pos                 (20U)
28120 #define RCC_AHB5ENR_GPU2DEN_Msk                 (0x1UL << RCC_AHB5ENR_GPU2DEN_Pos)    /*!< 0x00100000 */
28121 #define RCC_AHB5ENR_GPU2DEN                     RCC_AHB5ENR_GPU2DEN_Msk              /*!< GPU2D enable */
28122 #define RCC_AHB5ENR_ETH1MACEN_Pos               (22U)
28123 #define RCC_AHB5ENR_ETH1MACEN_Msk               (0x1UL << RCC_AHB5ENR_ETH1MACEN_Pos)  /*!< 0x00400000 */
28124 #define RCC_AHB5ENR_ETH1MACEN                   RCC_AHB5ENR_ETH1MACEN_Msk            /*!< ETH1MAC enable */
28125 #define RCC_AHB5ENR_ETH1TXEN_Pos                (23U)
28126 #define RCC_AHB5ENR_ETH1TXEN_Msk                (0x1UL << RCC_AHB5ENR_ETH1TXEN_Pos)   /*!< 0x00800000 */
28127 #define RCC_AHB5ENR_ETH1TXEN                    RCC_AHB5ENR_ETH1TXEN_Msk             /*!< ETH1TX enable */
28128 #define RCC_AHB5ENR_ETH1RXEN_Pos                (24U)
28129 #define RCC_AHB5ENR_ETH1RXEN_Msk                (0x1UL << RCC_AHB5ENR_ETH1RXEN_Pos)   /*!< 0x01000000 */
28130 #define RCC_AHB5ENR_ETH1RXEN                    RCC_AHB5ENR_ETH1RXEN_Msk             /*!< ETH1RX enable */
28131 #define RCC_AHB5ENR_ETH1EN_Pos                  (25U)
28132 #define RCC_AHB5ENR_ETH1EN_Msk                  (0x1UL << RCC_AHB5ENR_ETH1EN_Pos)     /*!< 0x02000000 */
28133 #define RCC_AHB5ENR_ETH1EN                      RCC_AHB5ENR_ETH1EN_Msk               /*!< ETH1 enable */
28134 #define RCC_AHB5ENR_OTG1EN_Pos                  (26U)
28135 #define RCC_AHB5ENR_OTG1EN_Msk                  (0x1UL << RCC_AHB5ENR_OTG1EN_Pos)     /*!< 0x04000000 */
28136 #define RCC_AHB5ENR_OTG1EN                      RCC_AHB5ENR_OTG1EN_Msk               /*!< OTG1 enable */
28137 #define RCC_AHB5ENR_OTGPHY1EN_Pos               (27U)
28138 #define RCC_AHB5ENR_OTGPHY1EN_Msk               (0x1UL << RCC_AHB5ENR_OTGPHY1EN_Pos)  /*!< 0x08000000 */
28139 #define RCC_AHB5ENR_OTGPHY1EN                   RCC_AHB5ENR_OTGPHY1EN_Msk            /*!< OTGPHY1 enable */
28140 #define RCC_AHB5ENR_OTGPHY2EN_Pos               (28U)
28141 #define RCC_AHB5ENR_OTGPHY2EN_Msk               (0x1UL << RCC_AHB5ENR_OTGPHY2EN_Pos)  /*!< 0x10000000 */
28142 #define RCC_AHB5ENR_OTGPHY2EN                   RCC_AHB5ENR_OTGPHY2EN_Msk            /*!< OTGPHY2 enable */
28143 #define RCC_AHB5ENR_OTG2EN_Pos                  (29U)
28144 #define RCC_AHB5ENR_OTG2EN_Msk                  (0x1UL << RCC_AHB5ENR_OTG2EN_Pos)     /*!< 0x20000000 */
28145 #define RCC_AHB5ENR_OTG2EN                      RCC_AHB5ENR_OTG2EN_Msk               /*!< OTG2 enable */
28146 #define RCC_AHB5ENR_CACHEAXIEN_Pos              (30U)
28147 #define RCC_AHB5ENR_CACHEAXIEN_Msk              (0x1UL << RCC_AHB5ENR_CACHEAXIEN_Pos) /*!< 0x40000000 */
28148 #define RCC_AHB5ENR_CACHEAXIEN                  RCC_AHB5ENR_CACHEAXIEN_Msk           /*!< CACHEAXI enable */
28149 #define RCC_AHB5ENR_NPUEN_Pos                   (31U)
28150 #define RCC_AHB5ENR_NPUEN_Msk                   (0x1UL << RCC_AHB5ENR_NPUEN_Pos)      /*!< 0x80000000 */
28151 #define RCC_AHB5ENR_NPUEN                       RCC_AHB5ENR_NPUEN_Msk                /*!< NPU enable */
28152 
28153 /*****************  Bit definition for RCC_APB1ENR1 register  *****************/
28154 #define RCC_APB1ENR1_TIM2EN_Pos                 (0U)
28155 #define RCC_APB1ENR1_TIM2EN_Msk                 (0x1UL << RCC_APB1ENR1_TIM2EN_Pos)    /*!< 0x00000001 */
28156 #define RCC_APB1ENR1_TIM2EN                     RCC_APB1ENR1_TIM2EN_Msk              /*!< TIM2 enable */
28157 #define RCC_APB1ENR1_TIM3EN_Pos                 (1U)
28158 #define RCC_APB1ENR1_TIM3EN_Msk                 (0x1UL << RCC_APB1ENR1_TIM3EN_Pos)    /*!< 0x00000002 */
28159 #define RCC_APB1ENR1_TIM3EN                     RCC_APB1ENR1_TIM3EN_Msk              /*!< TIM3 enable */
28160 #define RCC_APB1ENR1_TIM4EN_Pos                 (2U)
28161 #define RCC_APB1ENR1_TIM4EN_Msk                 (0x1UL << RCC_APB1ENR1_TIM4EN_Pos)    /*!< 0x00000004 */
28162 #define RCC_APB1ENR1_TIM4EN                     RCC_APB1ENR1_TIM4EN_Msk              /*!< TIM4 enable */
28163 #define RCC_APB1ENR1_TIM5EN_Pos                 (3U)
28164 #define RCC_APB1ENR1_TIM5EN_Msk                 (0x1UL << RCC_APB1ENR1_TIM5EN_Pos)    /*!< 0x00000008 */
28165 #define RCC_APB1ENR1_TIM5EN                     RCC_APB1ENR1_TIM5EN_Msk              /*!< TIM5 enable */
28166 #define RCC_APB1ENR1_TIM6EN_Pos                 (4U)
28167 #define RCC_APB1ENR1_TIM6EN_Msk                 (0x1UL << RCC_APB1ENR1_TIM6EN_Pos)    /*!< 0x00000010 */
28168 #define RCC_APB1ENR1_TIM6EN                     RCC_APB1ENR1_TIM6EN_Msk              /*!< TIM6 enable */
28169 #define RCC_APB1ENR1_TIM7EN_Pos                 (5U)
28170 #define RCC_APB1ENR1_TIM7EN_Msk                 (0x1UL << RCC_APB1ENR1_TIM7EN_Pos)    /*!< 0x00000020 */
28171 #define RCC_APB1ENR1_TIM7EN                     RCC_APB1ENR1_TIM7EN_Msk              /*!< TIM7 enable */
28172 #define RCC_APB1ENR1_TIM12EN_Pos                (6U)
28173 #define RCC_APB1ENR1_TIM12EN_Msk                (0x1UL << RCC_APB1ENR1_TIM12EN_Pos)   /*!< 0x00000040 */
28174 #define RCC_APB1ENR1_TIM12EN                    RCC_APB1ENR1_TIM12EN_Msk             /*!< TIM12 enable */
28175 #define RCC_APB1ENR1_TIM13EN_Pos                (7U)
28176 #define RCC_APB1ENR1_TIM13EN_Msk                (0x1UL << RCC_APB1ENR1_TIM13EN_Pos)   /*!< 0x00000080 */
28177 #define RCC_APB1ENR1_TIM13EN                    RCC_APB1ENR1_TIM13EN_Msk             /*!< TIM13 enable */
28178 #define RCC_APB1ENR1_TIM14EN_Pos                (8U)
28179 #define RCC_APB1ENR1_TIM14EN_Msk                (0x1UL << RCC_APB1ENR1_TIM14EN_Pos)   /*!< 0x00000100 */
28180 #define RCC_APB1ENR1_TIM14EN                    RCC_APB1ENR1_TIM14EN_Msk             /*!< TIM14 enable */
28181 #define RCC_APB1ENR1_LPTIM1EN_Pos               (9U)
28182 #define RCC_APB1ENR1_LPTIM1EN_Msk               (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos)  /*!< 0x00000200 */
28183 #define RCC_APB1ENR1_LPTIM1EN                   RCC_APB1ENR1_LPTIM1EN_Msk            /*!< LPTIM1 enable */
28184 #define RCC_APB1ENR1_WWDGEN_Pos                 (11U)
28185 #define RCC_APB1ENR1_WWDGEN_Msk                 (0x1UL << RCC_APB1ENR1_WWDGEN_Pos)    /*!< 0x00000800 */
28186 #define RCC_APB1ENR1_WWDGEN                     RCC_APB1ENR1_WWDGEN_Msk              /*!< WWDG enable */
28187 #define RCC_APB1ENR1_TIM10EN_Pos                (12U)
28188 #define RCC_APB1ENR1_TIM10EN_Msk                (0x1UL << RCC_APB1ENR1_TIM10EN_Pos)   /*!< 0x00001000 */
28189 #define RCC_APB1ENR1_TIM10EN                    RCC_APB1ENR1_TIM10EN_Msk             /*!< TIM10 enable */
28190 #define RCC_APB1ENR1_TIM11EN_Pos                (13U)
28191 #define RCC_APB1ENR1_TIM11EN_Msk                (0x1UL << RCC_APB1ENR1_TIM11EN_Pos)   /*!< 0x00002000 */
28192 #define RCC_APB1ENR1_TIM11EN                    RCC_APB1ENR1_TIM11EN_Msk             /*!< TIM11 enable */
28193 #define RCC_APB1ENR1_SPI2EN_Pos                 (14U)
28194 #define RCC_APB1ENR1_SPI2EN_Msk                 (0x1UL << RCC_APB1ENR1_SPI2EN_Pos)    /*!< 0x00004000 */
28195 #define RCC_APB1ENR1_SPI2EN                     RCC_APB1ENR1_SPI2EN_Msk              /*!< SPI2 enable */
28196 #define RCC_APB1ENR1_SPI3EN_Pos                 (15U)
28197 #define RCC_APB1ENR1_SPI3EN_Msk                 (0x1UL << RCC_APB1ENR1_SPI3EN_Pos)    /*!< 0x00008000 */
28198 #define RCC_APB1ENR1_SPI3EN                     RCC_APB1ENR1_SPI3EN_Msk              /*!< SPI3 enable */
28199 #define RCC_APB1ENR1_SPDIFRX1EN_Pos             (16U)
28200 #define RCC_APB1ENR1_SPDIFRX1EN_Msk             (0x1UL << RCC_APB1ENR1_SPDIFRX1EN_Pos)/*!< 0x00010000 */
28201 #define RCC_APB1ENR1_SPDIFRX1EN                 RCC_APB1ENR1_SPDIFRX1EN_Msk          /*!< SPDIFRX1 enable */
28202 #define RCC_APB1ENR1_USART2EN_Pos               (17U)
28203 #define RCC_APB1ENR1_USART2EN_Msk               (0x1UL << RCC_APB1ENR1_USART2EN_Pos)  /*!< 0x00020000 */
28204 #define RCC_APB1ENR1_USART2EN                   RCC_APB1ENR1_USART2EN_Msk            /*!< USART2 enable */
28205 #define RCC_APB1ENR1_USART3EN_Pos               (18U)
28206 #define RCC_APB1ENR1_USART3EN_Msk               (0x1UL << RCC_APB1ENR1_USART3EN_Pos)  /*!< 0x00040000 */
28207 #define RCC_APB1ENR1_USART3EN                   RCC_APB1ENR1_USART3EN_Msk            /*!< USART3 enable */
28208 #define RCC_APB1ENR1_UART4EN_Pos                (19U)
28209 #define RCC_APB1ENR1_UART4EN_Msk                (0x1UL << RCC_APB1ENR1_UART4EN_Pos)   /*!< 0x00080000 */
28210 #define RCC_APB1ENR1_UART4EN                    RCC_APB1ENR1_UART4EN_Msk             /*!< UART4 enable */
28211 #define RCC_APB1ENR1_UART5EN_Pos                (20U)
28212 #define RCC_APB1ENR1_UART5EN_Msk                (0x1UL << RCC_APB1ENR1_UART5EN_Pos)   /*!< 0x00100000 */
28213 #define RCC_APB1ENR1_UART5EN                    RCC_APB1ENR1_UART5EN_Msk             /*!< UART5 enable */
28214 #define RCC_APB1ENR1_I2C1EN_Pos                 (21U)
28215 #define RCC_APB1ENR1_I2C1EN_Msk                 (0x1UL << RCC_APB1ENR1_I2C1EN_Pos)    /*!< 0x00200000 */
28216 #define RCC_APB1ENR1_I2C1EN                     RCC_APB1ENR1_I2C1EN_Msk              /*!< I2C1 enable */
28217 #define RCC_APB1ENR1_I2C2EN_Pos                 (22U)
28218 #define RCC_APB1ENR1_I2C2EN_Msk                 (0x1UL << RCC_APB1ENR1_I2C2EN_Pos)    /*!< 0x00400000 */
28219 #define RCC_APB1ENR1_I2C2EN                     RCC_APB1ENR1_I2C2EN_Msk              /*!< I2C2 enable */
28220 #define RCC_APB1ENR1_I2C3EN_Pos                 (23U)
28221 #define RCC_APB1ENR1_I2C3EN_Msk                 (0x1UL << RCC_APB1ENR1_I2C3EN_Pos)    /*!< 0x00800000 */
28222 #define RCC_APB1ENR1_I2C3EN                     RCC_APB1ENR1_I2C3EN_Msk              /*!< I2C3 enable */
28223 #define RCC_APB1ENR1_I3C1EN_Pos                 (24U)
28224 #define RCC_APB1ENR1_I3C1EN_Msk                 (0x1UL << RCC_APB1ENR1_I3C1EN_Pos)    /*!< 0x01000000 */
28225 #define RCC_APB1ENR1_I3C1EN                     RCC_APB1ENR1_I3C1EN_Msk              /*!< I3C1 enable */
28226 #define RCC_APB1ENR1_I3C2EN_Pos                 (25U)
28227 #define RCC_APB1ENR1_I3C2EN_Msk                 (0x1UL << RCC_APB1ENR1_I3C2EN_Pos)    /*!< 0x02000000 */
28228 #define RCC_APB1ENR1_I3C2EN                     RCC_APB1ENR1_I3C2EN_Msk              /*!< I3C2 enable */
28229 #define RCC_APB1ENR1_UART7EN_Pos                (30U)
28230 #define RCC_APB1ENR1_UART7EN_Msk                (0x1UL << RCC_APB1ENR1_UART7EN_Pos)   /*!< 0x40000000 */
28231 #define RCC_APB1ENR1_UART7EN                    RCC_APB1ENR1_UART7EN_Msk             /*!< UART7 enable */
28232 #define RCC_APB1ENR1_UART8EN_Pos                (31U)
28233 #define RCC_APB1ENR1_UART8EN_Msk                (0x1UL << RCC_APB1ENR1_UART8EN_Pos)   /*!< 0x80000000 */
28234 #define RCC_APB1ENR1_UART8EN                    RCC_APB1ENR1_UART8EN_Msk             /*!< UART8 enable */
28235 
28236 /*****************  Bit definition for RCC_APB1ENR2 register  *****************/
28237 #define RCC_APB1ENR2_MDIOSEN_Pos                (5U)
28238 #define RCC_APB1ENR2_MDIOSEN_Msk                (0x1UL << RCC_APB1ENR2_MDIOSEN_Pos)   /*!< 0x00000020 */
28239 #define RCC_APB1ENR2_MDIOSEN                    RCC_APB1ENR2_MDIOSEN_Msk             /*!< MDIOS enable */
28240 #define RCC_APB1ENR2_FDCANEN_Pos                (8U)
28241 #define RCC_APB1ENR2_FDCANEN_Msk                (0x1UL << RCC_APB1ENR2_FDCANEN_Pos)   /*!< 0x00000100 */
28242 #define RCC_APB1ENR2_FDCANEN                    RCC_APB1ENR2_FDCANEN_Msk             /*!< FDCAN enable */
28243 #define RCC_APB1ENR2_UCPD1EN_Pos                (18U)
28244 #define RCC_APB1ENR2_UCPD1EN_Msk                (0x1UL << RCC_APB1ENR2_UCPD1EN_Pos)   /*!< 0x00040000 */
28245 #define RCC_APB1ENR2_UCPD1EN                    RCC_APB1ENR2_UCPD1EN_Msk             /*!< UCPD1 enable */
28246 
28247 /*****************  Bit definition for RCC_APB2ENR register  ******************/
28248 #define RCC_APB2ENR_TIM1EN_Pos                  (0U)
28249 #define RCC_APB2ENR_TIM1EN_Msk                  (0x1UL << RCC_APB2ENR_TIM1EN_Pos)     /*!< 0x00000001 */
28250 #define RCC_APB2ENR_TIM1EN                      RCC_APB2ENR_TIM1EN_Msk               /*!< TIM1 enable */
28251 #define RCC_APB2ENR_TIM8EN_Pos                  (1U)
28252 #define RCC_APB2ENR_TIM8EN_Msk                  (0x1UL << RCC_APB2ENR_TIM8EN_Pos)     /*!< 0x00000002 */
28253 #define RCC_APB2ENR_TIM8EN                      RCC_APB2ENR_TIM8EN_Msk               /*!< TIM8 enable */
28254 #define RCC_APB2ENR_USART1EN_Pos                (4U)
28255 #define RCC_APB2ENR_USART1EN_Msk                (0x1UL << RCC_APB2ENR_USART1EN_Pos)   /*!< 0x00000010 */
28256 #define RCC_APB2ENR_USART1EN                    RCC_APB2ENR_USART1EN_Msk             /*!< USART1 enable */
28257 #define RCC_APB2ENR_USART6EN_Pos                (5U)
28258 #define RCC_APB2ENR_USART6EN_Msk                (0x1UL << RCC_APB2ENR_USART6EN_Pos)   /*!< 0x00000020 */
28259 #define RCC_APB2ENR_USART6EN                    RCC_APB2ENR_USART6EN_Msk             /*!< USART6 enable */
28260 #define RCC_APB2ENR_UART9EN_Pos                 (6U)
28261 #define RCC_APB2ENR_UART9EN_Msk                 (0x1UL << RCC_APB2ENR_UART9EN_Pos)    /*!< 0x00000040 */
28262 #define RCC_APB2ENR_UART9EN                     RCC_APB2ENR_UART9EN_Msk              /*!< UART9 enable */
28263 #define RCC_APB2ENR_USART10EN_Pos               (7U)
28264 #define RCC_APB2ENR_USART10EN_Msk               (0x1UL << RCC_APB2ENR_USART10EN_Pos)  /*!< 0x00000080 */
28265 #define RCC_APB2ENR_USART10EN                   RCC_APB2ENR_USART10EN_Msk            /*!< USART10 enable */
28266 #define RCC_APB2ENR_SPI1EN_Pos                  (12U)
28267 #define RCC_APB2ENR_SPI1EN_Msk                  (0x1UL << RCC_APB2ENR_SPI1EN_Pos)     /*!< 0x00001000 */
28268 #define RCC_APB2ENR_SPI1EN                      RCC_APB2ENR_SPI1EN_Msk               /*!< SPI1 enable */
28269 #define RCC_APB2ENR_SPI4EN_Pos                  (13U)
28270 #define RCC_APB2ENR_SPI4EN_Msk                  (0x1UL << RCC_APB2ENR_SPI4EN_Pos)     /*!< 0x00002000 */
28271 #define RCC_APB2ENR_SPI4EN                      RCC_APB2ENR_SPI4EN_Msk               /*!< SPI4 enable */
28272 #define RCC_APB2ENR_TIM18EN_Pos                 (15U)
28273 #define RCC_APB2ENR_TIM18EN_Msk                 (0x1UL << RCC_APB2ENR_TIM18EN_Pos)    /*!< 0x00008000 */
28274 #define RCC_APB2ENR_TIM18EN                     RCC_APB2ENR_TIM18EN_Msk              /*!< TIM18 enable */
28275 #define RCC_APB2ENR_TIM15EN_Pos                 (16U)
28276 #define RCC_APB2ENR_TIM15EN_Msk                 (0x1UL << RCC_APB2ENR_TIM15EN_Pos)    /*!< 0x00010000 */
28277 #define RCC_APB2ENR_TIM15EN                     RCC_APB2ENR_TIM15EN_Msk              /*!< TIM15 enable */
28278 #define RCC_APB2ENR_TIM16EN_Pos                 (17U)
28279 #define RCC_APB2ENR_TIM16EN_Msk                 (0x1UL << RCC_APB2ENR_TIM16EN_Pos)    /*!< 0x00020000 */
28280 #define RCC_APB2ENR_TIM16EN                     RCC_APB2ENR_TIM16EN_Msk              /*!< TIM16 enable */
28281 #define RCC_APB2ENR_TIM17EN_Pos                 (18U)
28282 #define RCC_APB2ENR_TIM17EN_Msk                 (0x1UL << RCC_APB2ENR_TIM17EN_Pos)    /*!< 0x00040000 */
28283 #define RCC_APB2ENR_TIM17EN                     RCC_APB2ENR_TIM17EN_Msk              /*!< TIM17 enable */
28284 #define RCC_APB2ENR_TIM9EN_Pos                  (19U)
28285 #define RCC_APB2ENR_TIM9EN_Msk                  (0x1UL << RCC_APB2ENR_TIM9EN_Pos)     /*!< 0x00080000 */
28286 #define RCC_APB2ENR_TIM9EN                      RCC_APB2ENR_TIM9EN_Msk               /*!< TIM9 enable */
28287 #define RCC_APB2ENR_SPI5EN_Pos                  (20U)
28288 #define RCC_APB2ENR_SPI5EN_Msk                  (0x1UL << RCC_APB2ENR_SPI5EN_Pos)     /*!< 0x00100000 */
28289 #define RCC_APB2ENR_SPI5EN                      RCC_APB2ENR_SPI5EN_Msk               /*!< SPI5 enable */
28290 #define RCC_APB2ENR_SAI1EN_Pos                  (21U)
28291 #define RCC_APB2ENR_SAI1EN_Msk                  (0x1UL << RCC_APB2ENR_SAI1EN_Pos)     /*!< 0x00200000 */
28292 #define RCC_APB2ENR_SAI1EN                      RCC_APB2ENR_SAI1EN_Msk               /*!< SAI1 enable */
28293 #define RCC_APB2ENR_SAI2EN_Pos                  (22U)
28294 #define RCC_APB2ENR_SAI2EN_Msk                  (0x1UL << RCC_APB2ENR_SAI2EN_Pos)     /*!< 0x00400000 */
28295 #define RCC_APB2ENR_SAI2EN                      RCC_APB2ENR_SAI2EN_Msk               /*!< SAI2 enable */
28296 
28297 /*****************  Bit definition for RCC_APB3ENR register  ******************/
28298 #define RCC_APB3ENR_DFTEN_Pos                   (2U)
28299 #define RCC_APB3ENR_DFTEN_Msk                   (0x1UL << RCC_APB3ENR_DFTEN_Pos)      /*!< 0x00000004 */
28300 #define RCC_APB3ENR_DFTEN                       RCC_APB3ENR_DFTEN_Msk                /*!< DFT enable */
28301 
28302 /*****************  Bit definition for RCC_APB4ENR1 register  *****************/
28303 #define RCC_APB4ENR1_HDPEN_Pos                  (2U)
28304 #define RCC_APB4ENR1_HDPEN_Msk                  (0x1UL << RCC_APB4ENR1_HDPEN_Pos)     /*!< 0x00000004 */
28305 #define RCC_APB4ENR1_HDPEN                      RCC_APB4ENR1_HDPEN_Msk               /*!< HDP enable */
28306 #define RCC_APB4ENR1_LPUART1EN_Pos              (3U)
28307 #define RCC_APB4ENR1_LPUART1EN_Msk              (0x1UL << RCC_APB4ENR1_LPUART1EN_Pos) /*!< 0x00000008 */
28308 #define RCC_APB4ENR1_LPUART1EN                  RCC_APB4ENR1_LPUART1EN_Msk           /*!< LPUART1 enable */
28309 #define RCC_APB4ENR1_SPI6EN_Pos                 (5U)
28310 #define RCC_APB4ENR1_SPI6EN_Msk                 (0x1UL << RCC_APB4ENR1_SPI6EN_Pos)    /*!< 0x00000020 */
28311 #define RCC_APB4ENR1_SPI6EN                     RCC_APB4ENR1_SPI6EN_Msk              /*!< SPI6 enable */
28312 #define RCC_APB4ENR1_I2C4EN_Pos                 (7U)
28313 #define RCC_APB4ENR1_I2C4EN_Msk                 (0x1UL << RCC_APB4ENR1_I2C4EN_Pos)    /*!< 0x00000080 */
28314 #define RCC_APB4ENR1_I2C4EN                     RCC_APB4ENR1_I2C4EN_Msk              /*!< I2C4 enable */
28315 #define RCC_APB4ENR1_LPTIM2EN_Pos               (9U)
28316 #define RCC_APB4ENR1_LPTIM2EN_Msk               (0x1UL << RCC_APB4ENR1_LPTIM2EN_Pos)  /*!< 0x00000200 */
28317 #define RCC_APB4ENR1_LPTIM2EN                   RCC_APB4ENR1_LPTIM2EN_Msk            /*!< LPTIM2 enable */
28318 #define RCC_APB4ENR1_LPTIM3EN_Pos               (10U)
28319 #define RCC_APB4ENR1_LPTIM3EN_Msk               (0x1UL << RCC_APB4ENR1_LPTIM3EN_Pos)  /*!< 0x00000400 */
28320 #define RCC_APB4ENR1_LPTIM3EN                   RCC_APB4ENR1_LPTIM3EN_Msk            /*!< LPTIM3 enable */
28321 #define RCC_APB4ENR1_LPTIM4EN_Pos               (11U)
28322 #define RCC_APB4ENR1_LPTIM4EN_Msk               (0x1UL << RCC_APB4ENR1_LPTIM4EN_Pos)  /*!< 0x00000800 */
28323 #define RCC_APB4ENR1_LPTIM4EN                   RCC_APB4ENR1_LPTIM4EN_Msk            /*!< LPTIM4 enable */
28324 #define RCC_APB4ENR1_LPTIM5EN_Pos               (12U)
28325 #define RCC_APB4ENR1_LPTIM5EN_Msk               (0x1UL << RCC_APB4ENR1_LPTIM5EN_Pos)  /*!< 0x00001000 */
28326 #define RCC_APB4ENR1_LPTIM5EN                   RCC_APB4ENR1_LPTIM5EN_Msk            /*!< LPTIM5 enable */
28327 #define RCC_APB4ENR1_VREFBUFEN_Pos              (15U)
28328 #define RCC_APB4ENR1_VREFBUFEN_Msk              (0x1UL << RCC_APB4ENR1_VREFBUFEN_Pos) /*!< 0x00008000 */
28329 #define RCC_APB4ENR1_VREFBUFEN                  RCC_APB4ENR1_VREFBUFEN_Msk           /*!< VREFBUF enable */
28330 #define RCC_APB4ENR1_RTCEN_Pos                  (16U)
28331 #define RCC_APB4ENR1_RTCEN_Msk                  (0x1UL << RCC_APB4ENR1_RTCEN_Pos)     /*!< 0x00010000 */
28332 #define RCC_APB4ENR1_RTCEN                      RCC_APB4ENR1_RTCEN_Msk               /*!< RTC enable */
28333 #define RCC_APB4ENR1_RTCAPBEN_Pos               (17U)
28334 #define RCC_APB4ENR1_RTCAPBEN_Msk               (0x1UL << RCC_APB4ENR1_RTCAPBEN_Pos)  /*!< 0x00020000 */
28335 #define RCC_APB4ENR1_RTCAPBEN                   RCC_APB4ENR1_RTCAPBEN_Msk            /*!< RTCAPB enable */
28336 
28337 /*****************  Bit definition for RCC_APB4ENR2 register  *****************/
28338 #define RCC_APB4ENR2_SYSCFGEN_Pos               (0U)
28339 #define RCC_APB4ENR2_SYSCFGEN_Msk               (0x1UL << RCC_APB4ENR2_SYSCFGEN_Pos)  /*!< 0x00000001 */
28340 #define RCC_APB4ENR2_SYSCFGEN                   RCC_APB4ENR2_SYSCFGEN_Msk            /*!< SYSCFG enable */
28341 #define RCC_APB4ENR2_BSECEN_Pos                 (1U)
28342 #define RCC_APB4ENR2_BSECEN_Msk                 (0x1UL << RCC_APB4ENR2_BSECEN_Pos)    /*!< 0x00000002 */
28343 #define RCC_APB4ENR2_BSECEN                     RCC_APB4ENR2_BSECEN_Msk              /*!< BSEC enable */
28344 #define RCC_APB4ENR2_DTSEN_Pos                  (2U)
28345 #define RCC_APB4ENR2_DTSEN_Msk                  (0x1UL << RCC_APB4ENR2_DTSEN_Pos)     /*!< 0x00000004 */
28346 #define RCC_APB4ENR2_DTSEN                      RCC_APB4ENR2_DTSEN_Msk               /*!< DTS enable */
28347 
28348 /*****************  Bit definition for RCC_APB5ENR register  ******************/
28349 #define RCC_APB5ENR_LTDCEN_Pos                  (1U)
28350 #define RCC_APB5ENR_LTDCEN_Msk                  (0x1UL << RCC_APB5ENR_LTDCEN_Pos)     /*!< 0x00000002 */
28351 #define RCC_APB5ENR_LTDCEN                      RCC_APB5ENR_LTDCEN_Msk               /*!< LTDC enable */
28352 #define RCC_APB5ENR_DCMIPPEN_Pos                (2U)
28353 #define RCC_APB5ENR_DCMIPPEN_Msk                (0x1UL << RCC_APB5ENR_DCMIPPEN_Pos)   /*!< 0x00000004 */
28354 #define RCC_APB5ENR_DCMIPPEN                    RCC_APB5ENR_DCMIPPEN_Msk             /*!< DCMIPP enable */
28355 #define RCC_APB5ENR_GFXTIMEN_Pos                (4U)
28356 #define RCC_APB5ENR_GFXTIMEN_Msk                (0x1UL << RCC_APB5ENR_GFXTIMEN_Pos)   /*!< 0x00000010 */
28357 #define RCC_APB5ENR_GFXTIMEN                    RCC_APB5ENR_GFXTIMEN_Msk             /*!< GFXTIM enable */
28358 #define RCC_APB5ENR_VENCEN_Pos                  (5U)
28359 #define RCC_APB5ENR_VENCEN_Msk                  (0x1UL << RCC_APB5ENR_VENCEN_Pos)     /*!< 0x00000020 */
28360 #define RCC_APB5ENR_VENCEN                      RCC_APB5ENR_VENCEN_Msk               /*!< VENC enable */
28361 #define RCC_APB5ENR_CSIEN_Pos                   (6U)
28362 #define RCC_APB5ENR_CSIEN_Msk                   (0x1UL << RCC_APB5ENR_CSIEN_Pos)      /*!< 0x00000040 */
28363 #define RCC_APB5ENR_CSIEN                       RCC_APB5ENR_CSIEN_Msk                /*!< CSI enable */
28364 
28365 /*****************  Bit definition for RCC_BUSLPENR register  *****************/
28366 #define RCC_BUSLPENR_ACLKNLPEN_Pos              (0U)
28367 #define RCC_BUSLPENR_ACLKNLPEN_Msk              (0x1UL << RCC_BUSLPENR_ACLKNLPEN_Pos) /*!< 0x00000001 */
28368 #define RCC_BUSLPENR_ACLKNLPEN                  RCC_BUSLPENR_ACLKNLPEN_Msk           /*!< ACLKN enable  */
28369 #define RCC_BUSLPENR_ACLKNCLPEN_Pos             (1U)
28370 #define RCC_BUSLPENR_ACLKNCLPEN_Msk             (0x1UL << RCC_BUSLPENR_ACLKNCLPEN_Pos)/*!< 0x00000002 */
28371 #define RCC_BUSLPENR_ACLKNCLPEN                 RCC_BUSLPENR_ACLKNCLPEN_Msk          /*!< ACLKNC enable */
28372 
28373 /****************  Bit definition for RCC_MISCLPENR register  *****************/
28374 #define RCC_MISCLPENR_DBGLPEN_Pos               (0U)
28375 #define RCC_MISCLPENR_DBGLPEN_Msk               (0x1UL << RCC_MISCLPENR_DBGLPEN_Pos)  /*!< 0x00000001 */
28376 #define RCC_MISCLPENR_DBGLPEN                   RCC_MISCLPENR_DBGLPEN_Msk            /*!< DBG enable  */
28377 #define RCC_MISCLPENR_XSPIPHYCOMPLPEN_Pos       (3U)
28378 #define RCC_MISCLPENR_XSPIPHYCOMPLPEN_Msk       (0x1UL << RCC_MISCLPENR_XSPIPHYCOMPLPEN_Pos)      /*!< 0x00000008 */
28379 #define RCC_MISCLPENR_XSPIPHYCOMPLPEN           RCC_MISCLPENR_XSPIPHYCOMPLPEN_Msk    /*!< XSPIPHYCOMP enable  */
28380 #define RCC_MISCLPENR_PERLPEN_Pos               (6U)
28381 #define RCC_MISCLPENR_PERLPEN_Msk               (0x1UL << RCC_MISCLPENR_PERLPEN_Pos)  /*!< 0x00000040 */
28382 #define RCC_MISCLPENR_PERLPEN                   RCC_MISCLPENR_PERLPEN_Msk            /*!< PER enable  */
28383 
28384 /*****************  Bit definition for RCC_MEMLPENR register  *****************/
28385 #define RCC_MEMLPENR_AXISRAM3LPEN_Pos           (0U)
28386 #define RCC_MEMLPENR_AXISRAM3LPEN_Msk           (0x1UL << RCC_MEMLPENR_AXISRAM3LPEN_Pos)  /*!< 0x00000001 */
28387 #define RCC_MEMLPENR_AXISRAM3LPEN               RCC_MEMLPENR_AXISRAM3LPEN_Msk        /*!< AXISRAM3 enable */
28388 #define RCC_MEMLPENR_AXISRAM4LPEN_Pos           (1U)
28389 #define RCC_MEMLPENR_AXISRAM4LPEN_Msk           (0x1UL << RCC_MEMLPENR_AXISRAM4LPEN_Pos)  /*!< 0x00000002 */
28390 #define RCC_MEMLPENR_AXISRAM4LPEN               RCC_MEMLPENR_AXISRAM4LPEN_Msk        /*!< AXISRAM4 enable */
28391 #define RCC_MEMLPENR_AXISRAM5LPEN_Pos           (2U)
28392 #define RCC_MEMLPENR_AXISRAM5LPEN_Msk           (0x1UL << RCC_MEMLPENR_AXISRAM5LPEN_Pos)  /*!< 0x00000004 */
28393 #define RCC_MEMLPENR_AXISRAM5LPEN               RCC_MEMLPENR_AXISRAM5LPEN_Msk        /*!< AXISRAM5 enable */
28394 #define RCC_MEMLPENR_AXISRAM6LPEN_Pos           (3U)
28395 #define RCC_MEMLPENR_AXISRAM6LPEN_Msk           (0x1UL << RCC_MEMLPENR_AXISRAM6LPEN_Pos)  /*!< 0x00000008 */
28396 #define RCC_MEMLPENR_AXISRAM6LPEN               RCC_MEMLPENR_AXISRAM6LPEN_Msk        /*!< AXISRAM6 enable */
28397 #define RCC_MEMLPENR_AHBSRAM1LPEN_Pos           (4U)
28398 #define RCC_MEMLPENR_AHBSRAM1LPEN_Msk           (0x1UL << RCC_MEMLPENR_AHBSRAM1LPEN_Pos)  /*!< 0x00000010 */
28399 #define RCC_MEMLPENR_AHBSRAM1LPEN               RCC_MEMLPENR_AHBSRAM1LPEN_Msk        /*!< AHBSRAM1 enable */
28400 #define RCC_MEMLPENR_AHBSRAM2LPEN_Pos           (5U)
28401 #define RCC_MEMLPENR_AHBSRAM2LPEN_Msk           (0x1UL << RCC_MEMLPENR_AHBSRAM2LPEN_Pos)  /*!< 0x00000020 */
28402 #define RCC_MEMLPENR_AHBSRAM2LPEN               RCC_MEMLPENR_AHBSRAM2LPEN_Msk        /*!< AHBSRAM2 enable */
28403 #define RCC_MEMLPENR_BKPSRAMLPEN_Pos            (6U)
28404 #define RCC_MEMLPENR_BKPSRAMLPEN_Msk            (0x1UL << RCC_MEMLPENR_BKPSRAMLPEN_Pos) /*!< 0x00000040 */
28405 #define RCC_MEMLPENR_BKPSRAMLPEN                RCC_MEMLPENR_BKPSRAMLPEN_Msk         /*!< BKPSRAM enable */
28406 #define RCC_MEMLPENR_AXISRAM1LPEN_Pos           (7U)
28407 #define RCC_MEMLPENR_AXISRAM1LPEN_Msk           (0x1UL << RCC_MEMLPENR_AXISRAM1LPEN_Pos)  /*!< 0x00000080 */
28408 #define RCC_MEMLPENR_AXISRAM1LPEN               RCC_MEMLPENR_AXISRAM1LPEN_Msk        /*!< AXISRAM1 enable */
28409 #define RCC_MEMLPENR_AXISRAM2LPEN_Pos           (8U)
28410 #define RCC_MEMLPENR_AXISRAM2LPEN_Msk           (0x1UL << RCC_MEMLPENR_AXISRAM2LPEN_Pos)  /*!< 0x00000100 */
28411 #define RCC_MEMLPENR_AXISRAM2LPEN               RCC_MEMLPENR_AXISRAM2LPEN_Msk        /*!< AXISRAM2 enable */
28412 #define RCC_MEMLPENR_FLEXRAMLPEN_Pos            (9U)
28413 #define RCC_MEMLPENR_FLEXRAMLPEN_Msk            (0x1UL << RCC_MEMLPENR_FLEXRAMLPEN_Pos) /*!< 0x00000200 */
28414 #define RCC_MEMLPENR_FLEXRAMLPEN                RCC_MEMLPENR_FLEXRAMLPEN_Msk         /*!< FLEXRAM enable */
28415 #define RCC_MEMLPENR_CACHEAXIRAMLPEN_Pos        (10U)
28416 #define RCC_MEMLPENR_CACHEAXIRAMLPEN_Msk        (0x1UL << RCC_MEMLPENR_CACHEAXIRAMLPEN_Pos)     /*!< 0x00000400 */
28417 #define RCC_MEMLPENR_CACHEAXIRAMLPEN            RCC_MEMLPENR_CACHEAXIRAMLPEN_Msk     /*!< CACHEAXIRAM enable */
28418 #define RCC_MEMLPENR_VENCRAMLPEN_Pos            (11U)
28419 #define RCC_MEMLPENR_VENCRAMLPEN_Msk            (0x1UL << RCC_MEMLPENR_VENCRAMLPEN_Pos) /*!< 0x00000800 */
28420 #define RCC_MEMLPENR_VENCRAMLPEN                RCC_MEMLPENR_VENCRAMLPEN_Msk         /*!< VENCRAM enable */
28421 #define RCC_MEMLPENR_BOOTROMLPEN_Pos            (12U)
28422 #define RCC_MEMLPENR_BOOTROMLPEN_Msk            (0x1UL << RCC_MEMLPENR_BOOTROMLPEN_Pos) /*!< 0x00001000 */
28423 #define RCC_MEMLPENR_BOOTROMLPEN                RCC_MEMLPENR_BOOTROMLPEN_Msk         /*!< Boot ROM enable */
28424 
28425 /****************  Bit definition for RCC_AHB1LPENR register  *****************/
28426 #define RCC_AHB1LPENR_GPDMA1LPEN_Pos            (4U)
28427 #define RCC_AHB1LPENR_GPDMA1LPEN_Msk            (0x1UL << RCC_AHB1LPENR_GPDMA1LPEN_Pos) /*!< 0x00000010 */
28428 #define RCC_AHB1LPENR_GPDMA1LPEN                RCC_AHB1LPENR_GPDMA1LPEN_Msk         /*!< GPDMA1 enable */
28429 #define RCC_AHB1LPENR_ADC12LPEN_Pos             (5U)
28430 #define RCC_AHB1LPENR_ADC12LPEN_Msk             (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos)/*!< 0x00000020 */
28431 #define RCC_AHB1LPENR_ADC12LPEN                 RCC_AHB1LPENR_ADC12LPEN_Msk          /*!< ADC12 enable */
28432 
28433 /****************  Bit definition for RCC_AHB2LPENR register  *****************/
28434 #define RCC_AHB2LPENR_RAMCFGLPEN_Pos            (12U)
28435 #define RCC_AHB2LPENR_RAMCFGLPEN_Msk            (0x1UL << RCC_AHB2LPENR_RAMCFGLPEN_Pos) /*!< 0x00001000 */
28436 #define RCC_AHB2LPENR_RAMCFGLPEN                RCC_AHB2LPENR_RAMCFGLPEN_Msk         /*!< RAMCFG enable */
28437 #define RCC_AHB2LPENR_MDF1LPEN_Pos              (16U)
28438 #define RCC_AHB2LPENR_MDF1LPEN_Msk              (0x1UL << RCC_AHB2LPENR_MDF1LPEN_Pos) /*!< 0x00010000 */
28439 #define RCC_AHB2LPENR_MDF1LPEN                  RCC_AHB2LPENR_MDF1LPEN_Msk           /*!< MDF1 enable */
28440 #define RCC_AHB2LPENR_ADF1LPEN_Pos              (17U)
28441 #define RCC_AHB2LPENR_ADF1LPEN_Msk              (0x1UL << RCC_AHB2LPENR_ADF1LPEN_Pos) /*!< 0x00020000 */
28442 #define RCC_AHB2LPENR_ADF1LPEN                  RCC_AHB2LPENR_ADF1LPEN_Msk           /*!< ADF1 enable */
28443 
28444 /****************  Bit definition for RCC_AHB3LPENR register  *****************/
28445 #define RCC_AHB3LPENR_RNGLPEN_Pos               (0U)
28446 #define RCC_AHB3LPENR_RNGLPEN_Msk               (0x1UL << RCC_AHB3LPENR_RNGLPEN_Pos)  /*!< 0x00000001 */
28447 #define RCC_AHB3LPENR_RNGLPEN                   RCC_AHB3LPENR_RNGLPEN_Msk            /*!< RNG enable */
28448 #define RCC_AHB3LPENR_HASHLPEN_Pos              (1U)
28449 #define RCC_AHB3LPENR_HASHLPEN_Msk              (0x1UL << RCC_AHB3LPENR_HASHLPEN_Pos) /*!< 0x00000002 */
28450 #define RCC_AHB3LPENR_HASHLPEN                  RCC_AHB3LPENR_HASHLPEN_Msk           /*!< HASH enable */
28451 #define RCC_AHB3LPENR_CRYPLPEN_Pos              (2U)
28452 #define RCC_AHB3LPENR_CRYPLPEN_Msk              (0x1UL << RCC_AHB3LPENR_CRYPLPEN_Pos) /*!< 0x00000004 */
28453 #define RCC_AHB3LPENR_CRYPLPEN                  RCC_AHB3LPENR_CRYPLPEN_Msk           /*!< CRYP enable */
28454 #define RCC_AHB3LPENR_SAESLPEN_Pos              (4U)
28455 #define RCC_AHB3LPENR_SAESLPEN_Msk              (0x1UL << RCC_AHB3LPENR_SAESLPEN_Pos) /*!< 0x00000010 */
28456 #define RCC_AHB3LPENR_SAESLPEN                  RCC_AHB3LPENR_SAESLPEN_Msk           /*!< SAES enable */
28457 #define RCC_AHB3LPENR_PKALPEN_Pos               (8U)
28458 #define RCC_AHB3LPENR_PKALPEN_Msk               (0x1UL << RCC_AHB3LPENR_PKALPEN_Pos)  /*!< 0x00000100 */
28459 #define RCC_AHB3LPENR_PKALPEN                   RCC_AHB3LPENR_PKALPEN_Msk            /*!< PKA enable */
28460 #define RCC_AHB3LPENR_RIFSCLPEN_Pos             (9U)
28461 #define RCC_AHB3LPENR_RIFSCLPEN_Msk             (0x1UL << RCC_AHB3LPENR_RIFSCLPEN_Pos)/*!< 0x00000200 */
28462 #define RCC_AHB3LPENR_RIFSCLPEN                 RCC_AHB3LPENR_RIFSCLPEN_Msk          /*!< RIFSC enable */
28463 #define RCC_AHB3LPENR_IACLPEN_Pos               (10U)
28464 #define RCC_AHB3LPENR_IACLPEN_Msk               (0x1UL << RCC_AHB3LPENR_IACLPEN_Pos)  /*!< 0x00000400 */
28465 #define RCC_AHB3LPENR_IACLPEN                   RCC_AHB3LPENR_IACLPEN_Msk            /*!< IAC enable */
28466 #define RCC_AHB3LPENR_RISAFLPEN_Pos             (14U)
28467 #define RCC_AHB3LPENR_RISAFLPEN_Msk             (0x1UL << RCC_AHB3LPENR_RISAFLPEN_Pos)/*!< 0x00004000 */
28468 #define RCC_AHB3LPENR_RISAFLPEN                 RCC_AHB3LPENR_RISAFLPEN_Msk          /*!< RISAF enable */
28469 
28470 /****************  Bit definition for RCC_AHB4LPENR register  *****************/
28471 #define RCC_AHB4LPENR_GPIOALPEN_Pos             (0U)
28472 #define RCC_AHB4LPENR_GPIOALPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos)/*!< 0x00000001 */
28473 #define RCC_AHB4LPENR_GPIOALPEN                 RCC_AHB4LPENR_GPIOALPEN_Msk          /*!< GPIO A enable */
28474 #define RCC_AHB4LPENR_GPIOBLPEN_Pos             (1U)
28475 #define RCC_AHB4LPENR_GPIOBLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos)/*!< 0x00000002 */
28476 #define RCC_AHB4LPENR_GPIOBLPEN                 RCC_AHB4LPENR_GPIOBLPEN_Msk          /*!< GPIO B enable */
28477 #define RCC_AHB4LPENR_GPIOCLPEN_Pos             (2U)
28478 #define RCC_AHB4LPENR_GPIOCLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos)/*!< 0x00000004 */
28479 #define RCC_AHB4LPENR_GPIOCLPEN                 RCC_AHB4LPENR_GPIOCLPEN_Msk          /*!< GPIO C enable */
28480 #define RCC_AHB4LPENR_GPIODLPEN_Pos             (3U)
28481 #define RCC_AHB4LPENR_GPIODLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos)/*!< 0x00000008 */
28482 #define RCC_AHB4LPENR_GPIODLPEN                 RCC_AHB4LPENR_GPIODLPEN_Msk          /*!< GPIO D enable */
28483 #define RCC_AHB4LPENR_GPIOELPEN_Pos             (4U)
28484 #define RCC_AHB4LPENR_GPIOELPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos)/*!< 0x00000010 */
28485 #define RCC_AHB4LPENR_GPIOELPEN                 RCC_AHB4LPENR_GPIOELPEN_Msk          /*!< GPIO E enable */
28486 #define RCC_AHB4LPENR_GPIOFLPEN_Pos             (5U)
28487 #define RCC_AHB4LPENR_GPIOFLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos)/*!< 0x00000020 */
28488 #define RCC_AHB4LPENR_GPIOFLPEN                 RCC_AHB4LPENR_GPIOFLPEN_Msk          /*!< GPIO F enable */
28489 #define RCC_AHB4LPENR_GPIOGLPEN_Pos             (6U)
28490 #define RCC_AHB4LPENR_GPIOGLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos)/*!< 0x00000040 */
28491 #define RCC_AHB4LPENR_GPIOGLPEN                 RCC_AHB4LPENR_GPIOGLPEN_Msk          /*!< GPIO G enable */
28492 #define RCC_AHB4LPENR_GPIOHLPEN_Pos             (7U)
28493 #define RCC_AHB4LPENR_GPIOHLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos)/*!< 0x00000080 */
28494 #define RCC_AHB4LPENR_GPIOHLPEN                 RCC_AHB4LPENR_GPIOHLPEN_Msk          /*!< GPIO H enable */
28495 #define RCC_AHB4LPENR_GPIONLPEN_Pos             (13U)
28496 #define RCC_AHB4LPENR_GPIONLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIONLPEN_Pos)/*!< 0x00002000 */
28497 #define RCC_AHB4LPENR_GPIONLPEN                 RCC_AHB4LPENR_GPIONLPEN_Msk          /*!< GPIO N enable */
28498 #define RCC_AHB4LPENR_GPIOOLPEN_Pos             (14U)
28499 #define RCC_AHB4LPENR_GPIOOLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOOLPEN_Pos)/*!< 0x00004000 */
28500 #define RCC_AHB4LPENR_GPIOOLPEN                 RCC_AHB4LPENR_GPIOOLPEN_Msk          /*!< GPIO O enable */
28501 #define RCC_AHB4LPENR_GPIOPLPEN_Pos             (15U)
28502 #define RCC_AHB4LPENR_GPIOPLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOPLPEN_Pos)/*!< 0x00008000 */
28503 #define RCC_AHB4LPENR_GPIOPLPEN                 RCC_AHB4LPENR_GPIOPLPEN_Msk          /*!< GPIO P enable */
28504 #define RCC_AHB4LPENR_GPIOQLPEN_Pos             (16U)
28505 #define RCC_AHB4LPENR_GPIOQLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOQLPEN_Pos)/*!< 0x00010000 */
28506 #define RCC_AHB4LPENR_GPIOQLPEN                 RCC_AHB4LPENR_GPIOQLPEN_Msk          /*!< GPIO Q enable */
28507 #define RCC_AHB4LPENR_PWRLPEN_Pos               (18U)
28508 #define RCC_AHB4LPENR_PWRLPEN_Msk               (0x1UL << RCC_AHB4LPENR_PWRLPEN_Pos)  /*!< 0x00040000 */
28509 #define RCC_AHB4LPENR_PWRLPEN                   RCC_AHB4LPENR_PWRLPEN_Msk            /*!< PWR enable */
28510 #define RCC_AHB4LPENR_CRCLPEN_Pos               (19U)
28511 #define RCC_AHB4LPENR_CRCLPEN_Msk               (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos)  /*!< 0x00080000 */
28512 #define RCC_AHB4LPENR_CRCLPEN                   RCC_AHB4LPENR_CRCLPEN_Msk            /*!< CRC enable */
28513 
28514 /****************  Bit definition for RCC_AHB5LPENR register  *****************/
28515 #define RCC_AHB5LPENR_HPDMA1LPEN_Pos            (0U)
28516 #define RCC_AHB5LPENR_HPDMA1LPEN_Msk            (0x1UL << RCC_AHB5LPENR_HPDMA1LPEN_Pos) /*!< 0x00000001 */
28517 #define RCC_AHB5LPENR_HPDMA1LPEN                RCC_AHB5LPENR_HPDMA1LPEN_Msk         /*!< HPDMA1 enable */
28518 #define RCC_AHB5LPENR_DMA2DLPEN_Pos             (1U)
28519 #define RCC_AHB5LPENR_DMA2DLPEN_Msk             (0x1UL << RCC_AHB5LPENR_DMA2DLPEN_Pos)/*!< 0x00000002 */
28520 #define RCC_AHB5LPENR_DMA2DLPEN                 RCC_AHB5LPENR_DMA2DLPEN_Msk          /*!< DMA2D enable */
28521 #define RCC_AHB5LPENR_JPEGLPEN_Pos              (3U)
28522 #define RCC_AHB5LPENR_JPEGLPEN_Msk              (0x1UL << RCC_AHB5LPENR_JPEGLPEN_Pos) /*!< 0x00000008 */
28523 #define RCC_AHB5LPENR_JPEGLPEN                  RCC_AHB5LPENR_JPEGLPEN_Msk           /*!< JPEG enable */
28524 #define RCC_AHB5LPENR_FMCLPEN_Pos               (4U)
28525 #define RCC_AHB5LPENR_FMCLPEN_Msk               (0x1UL << RCC_AHB5LPENR_FMCLPEN_Pos)  /*!< 0x00000010 */
28526 #define RCC_AHB5LPENR_FMCLPEN                   RCC_AHB5LPENR_FMCLPEN_Msk            /*!< FMC enable */
28527 #define RCC_AHB5LPENR_XSPI1LPEN_Pos             (5U)
28528 #define RCC_AHB5LPENR_XSPI1LPEN_Msk             (0x1UL << RCC_AHB5LPENR_XSPI1LPEN_Pos)/*!< 0x00000020 */
28529 #define RCC_AHB5LPENR_XSPI1LPEN                 RCC_AHB5LPENR_XSPI1LPEN_Msk          /*!< XSPI1 enable */
28530 #define RCC_AHB5LPENR_PSSILPEN_Pos              (6U)
28531 #define RCC_AHB5LPENR_PSSILPEN_Msk              (0x1UL << RCC_AHB5LPENR_PSSILPEN_Pos) /*!< 0x00000040 */
28532 #define RCC_AHB5LPENR_PSSILPEN                  RCC_AHB5LPENR_PSSILPEN_Msk           /*!< PSSI enable */
28533 #define RCC_AHB5LPENR_SDMMC2LPEN_Pos            (7U)
28534 #define RCC_AHB5LPENR_SDMMC2LPEN_Msk            (0x1UL << RCC_AHB5LPENR_SDMMC2LPEN_Pos) /*!< 0x00000080 */
28535 #define RCC_AHB5LPENR_SDMMC2LPEN                RCC_AHB5LPENR_SDMMC2LPEN_Msk         /*!< SDMMC2 enable */
28536 #define RCC_AHB5LPENR_SDMMC1LPEN_Pos            (8U)
28537 #define RCC_AHB5LPENR_SDMMC1LPEN_Msk            (0x1UL << RCC_AHB5LPENR_SDMMC1LPEN_Pos) /*!< 0x00000100 */
28538 #define RCC_AHB5LPENR_SDMMC1LPEN                RCC_AHB5LPENR_SDMMC1LPEN_Msk         /*!< SDMMC1 enable */
28539 #define RCC_AHB5LPENR_XSPI2LPEN_Pos             (12U)
28540 #define RCC_AHB5LPENR_XSPI2LPEN_Msk             (0x1UL << RCC_AHB5LPENR_XSPI2LPEN_Pos)/*!< 0x00001000 */
28541 #define RCC_AHB5LPENR_XSPI2LPEN                 RCC_AHB5LPENR_XSPI2LPEN_Msk          /*!< XSPI2 enable */
28542 #define RCC_AHB5LPENR_XSPIMLPEN_Pos             (13U)
28543 #define RCC_AHB5LPENR_XSPIMLPEN_Msk             (0x1UL << RCC_AHB5LPENR_XSPIMLPEN_Pos)/*!< 0x00002000 */
28544 #define RCC_AHB5LPENR_XSPIMLPEN                 RCC_AHB5LPENR_XSPIMLPEN_Msk          /*!< XSPIM enable */
28545 #define RCC_AHB5LPENR_MCE1LPEN_Pos              (14U)
28546 #define RCC_AHB5LPENR_MCE1LPEN_Msk              (0x1UL << RCC_AHB5LPENR_MCE1LPEN_Pos) /*!< 0x00004000 */
28547 #define RCC_AHB5LPENR_MCE1LPEN                  RCC_AHB5LPENR_MCE1LPEN_Msk           /*!< MCE1 enable */
28548 #define RCC_AHB5LPENR_MCE2LPEN_Pos              (15U)
28549 #define RCC_AHB5LPENR_MCE2LPEN_Msk              (0x1UL << RCC_AHB5LPENR_MCE2LPEN_Pos) /*!< 0x00008000 */
28550 #define RCC_AHB5LPENR_MCE2LPEN                  RCC_AHB5LPENR_MCE2LPEN_Msk           /*!< MCE2 enable */
28551 #define RCC_AHB5LPENR_MCE3LPEN_Pos              (16U)
28552 #define RCC_AHB5LPENR_MCE3LPEN_Msk              (0x1UL << RCC_AHB5LPENR_MCE3LPEN_Pos) /*!< 0x00010000 */
28553 #define RCC_AHB5LPENR_MCE3LPEN                  RCC_AHB5LPENR_MCE3LPEN_Msk           /*!< MCE3 enable */
28554 #define RCC_AHB5LPENR_XSPI3LPEN_Pos             (17U)
28555 #define RCC_AHB5LPENR_XSPI3LPEN_Msk             (0x1UL << RCC_AHB5LPENR_XSPI3LPEN_Pos)/*!< 0x00020000 */
28556 #define RCC_AHB5LPENR_XSPI3LPEN                 RCC_AHB5LPENR_XSPI3LPEN_Msk          /*!< XSPI3 enable */
28557 #define RCC_AHB5LPENR_MCE4LPEN_Pos              (18U)
28558 #define RCC_AHB5LPENR_MCE4LPEN_Msk              (0x1UL << RCC_AHB5LPENR_MCE4LPEN_Pos) /*!< 0x00040000 */
28559 #define RCC_AHB5LPENR_MCE4LPEN                  RCC_AHB5LPENR_MCE4LPEN_Msk           /*!< MCE4 enable */
28560 #define RCC_AHB5LPENR_GFXMMULPEN_Pos            (19U)
28561 #define RCC_AHB5LPENR_GFXMMULPEN_Msk            (0x1UL << RCC_AHB5LPENR_GFXMMULPEN_Pos) /*!< 0x00080000 */
28562 #define RCC_AHB5LPENR_GFXMMULPEN                RCC_AHB5LPENR_GFXMMULPEN_Msk         /*!< GFXMMU enable */
28563 #define RCC_AHB5LPENR_GPU2DLPEN_Pos             (20U)
28564 #define RCC_AHB5LPENR_GPU2DLPEN_Msk             (0x1UL << RCC_AHB5LPENR_GPU2DLPEN_Pos)/*!< 0x00100000 */
28565 #define RCC_AHB5LPENR_GPU2DLPEN                 RCC_AHB5LPENR_GPU2DLPEN_Msk          /*!< GPU2D enable */
28566 #define RCC_AHB5LPENR_ETH1MACLPEN_Pos           (22U)
28567 #define RCC_AHB5LPENR_ETH1MACLPEN_Msk           (0x1UL << RCC_AHB5LPENR_ETH1MACLPEN_Pos)  /*!< 0x00400000 */
28568 #define RCC_AHB5LPENR_ETH1MACLPEN               RCC_AHB5LPENR_ETH1MACLPEN_Msk        /*!< ETH1MAC enable */
28569 #define RCC_AHB5LPENR_ETH1TXLPEN_Pos            (23U)
28570 #define RCC_AHB5LPENR_ETH1TXLPEN_Msk            (0x1UL << RCC_AHB5LPENR_ETH1TXLPEN_Pos) /*!< 0x00800000 */
28571 #define RCC_AHB5LPENR_ETH1TXLPEN                RCC_AHB5LPENR_ETH1TXLPEN_Msk         /*!< ETH1TX enable */
28572 #define RCC_AHB5LPENR_ETH1RXLPEN_Pos            (24U)
28573 #define RCC_AHB5LPENR_ETH1RXLPEN_Msk            (0x1UL << RCC_AHB5LPENR_ETH1RXLPEN_Pos) /*!< 0x01000000 */
28574 #define RCC_AHB5LPENR_ETH1RXLPEN                RCC_AHB5LPENR_ETH1RXLPEN_Msk         /*!< ETH1RX enable */
28575 #define RCC_AHB5LPENR_ETH1LPEN_Pos              (25U)
28576 #define RCC_AHB5LPENR_ETH1LPEN_Msk              (0x1UL << RCC_AHB5LPENR_ETH1LPEN_Pos) /*!< 0x02000000 */
28577 #define RCC_AHB5LPENR_ETH1LPEN                  RCC_AHB5LPENR_ETH1LPEN_Msk           /*!< ETH1 enable */
28578 #define RCC_AHB5LPENR_OTG1LPEN_Pos              (26U)
28579 #define RCC_AHB5LPENR_OTG1LPEN_Msk              (0x1UL << RCC_AHB5LPENR_OTG1LPEN_Pos) /*!< 0x04000000 */
28580 #define RCC_AHB5LPENR_OTG1LPEN                  RCC_AHB5LPENR_OTG1LPEN_Msk           /*!< OTG1 enable */
28581 #define RCC_AHB5LPENR_OTGPHY1LPEN_Pos           (27U)
28582 #define RCC_AHB5LPENR_OTGPHY1LPEN_Msk           (0x1UL << RCC_AHB5LPENR_OTGPHY1LPEN_Pos)  /*!< 0x08000000 */
28583 #define RCC_AHB5LPENR_OTGPHY1LPEN               RCC_AHB5LPENR_OTGPHY1LPEN_Msk        /*!< OTGPHY1 enable */
28584 #define RCC_AHB5LPENR_OTGPHY2LPEN_Pos           (28U)
28585 #define RCC_AHB5LPENR_OTGPHY2LPEN_Msk           (0x1UL << RCC_AHB5LPENR_OTGPHY2LPEN_Pos)  /*!< 0x10000000 */
28586 #define RCC_AHB5LPENR_OTGPHY2LPEN               RCC_AHB5LPENR_OTGPHY2LPEN_Msk        /*!< OTGPHY2 enable */
28587 #define RCC_AHB5LPENR_OTG2LPEN_Pos              (29U)
28588 #define RCC_AHB5LPENR_OTG2LPEN_Msk              (0x1UL << RCC_AHB5LPENR_OTG2LPEN_Pos) /*!< 0x20000000 */
28589 #define RCC_AHB5LPENR_OTG2LPEN                  RCC_AHB5LPENR_OTG2LPEN_Msk           /*!< OTG2 enable */
28590 #define RCC_AHB5LPENR_CACHEAXILPEN_Pos          (30U)
28591 #define RCC_AHB5LPENR_CACHEAXILPEN_Msk          (0x1UL << RCC_AHB5LPENR_CACHEAXILPEN_Pos)   /*!< 0x40000000 */
28592 #define RCC_AHB5LPENR_CACHEAXILPEN              RCC_AHB5LPENR_CACHEAXILPEN_Msk       /*!< CACHEAXI enable */
28593 #define RCC_AHB5LPENR_NPULPEN_Pos               (31U)
28594 #define RCC_AHB5LPENR_NPULPEN_Msk               (0x1UL << RCC_AHB5LPENR_NPULPEN_Pos)  /*!< 0x80000000 */
28595 #define RCC_AHB5LPENR_NPULPEN                   RCC_AHB5LPENR_NPULPEN_Msk            /*!< NPU enable */
28596 
28597 /****************  Bit definition for RCC_APB1LPENR1 register  ****************/
28598 #define RCC_APB1LPENR1_TIM2LPEN_Pos             (0U)
28599 #define RCC_APB1LPENR1_TIM2LPEN_Msk             (0x1UL << RCC_APB1LPENR1_TIM2LPEN_Pos)/*!< 0x00000001 */
28600 #define RCC_APB1LPENR1_TIM2LPEN                 RCC_APB1LPENR1_TIM2LPEN_Msk          /*!< TIM2 enable */
28601 #define RCC_APB1LPENR1_TIM3LPEN_Pos             (1U)
28602 #define RCC_APB1LPENR1_TIM3LPEN_Msk             (0x1UL << RCC_APB1LPENR1_TIM3LPEN_Pos)/*!< 0x00000002 */
28603 #define RCC_APB1LPENR1_TIM3LPEN                 RCC_APB1LPENR1_TIM3LPEN_Msk          /*!< TIM3 enable */
28604 #define RCC_APB1LPENR1_TIM4LPEN_Pos             (2U)
28605 #define RCC_APB1LPENR1_TIM4LPEN_Msk             (0x1UL << RCC_APB1LPENR1_TIM4LPEN_Pos)/*!< 0x00000004 */
28606 #define RCC_APB1LPENR1_TIM4LPEN                 RCC_APB1LPENR1_TIM4LPEN_Msk          /*!< TIM4 enable */
28607 #define RCC_APB1LPENR1_TIM5LPEN_Pos             (3U)
28608 #define RCC_APB1LPENR1_TIM5LPEN_Msk             (0x1UL << RCC_APB1LPENR1_TIM5LPEN_Pos)/*!< 0x00000008 */
28609 #define RCC_APB1LPENR1_TIM5LPEN                 RCC_APB1LPENR1_TIM5LPEN_Msk          /*!< TIM5 enable */
28610 #define RCC_APB1LPENR1_TIM6LPEN_Pos             (4U)
28611 #define RCC_APB1LPENR1_TIM6LPEN_Msk             (0x1UL << RCC_APB1LPENR1_TIM6LPEN_Pos)/*!< 0x00000010 */
28612 #define RCC_APB1LPENR1_TIM6LPEN                 RCC_APB1LPENR1_TIM6LPEN_Msk          /*!< TIM6 enable */
28613 #define RCC_APB1LPENR1_TIM7LPEN_Pos             (5U)
28614 #define RCC_APB1LPENR1_TIM7LPEN_Msk             (0x1UL << RCC_APB1LPENR1_TIM7LPEN_Pos)/*!< 0x00000020 */
28615 #define RCC_APB1LPENR1_TIM7LPEN                 RCC_APB1LPENR1_TIM7LPEN_Msk          /*!< TIM7 enable */
28616 #define RCC_APB1LPENR1_TIM12LPEN_Pos            (6U)
28617 #define RCC_APB1LPENR1_TIM12LPEN_Msk            (0x1UL << RCC_APB1LPENR1_TIM12LPEN_Pos) /*!< 0x00000040 */
28618 #define RCC_APB1LPENR1_TIM12LPEN                RCC_APB1LPENR1_TIM12LPEN_Msk         /*!< TIM12 enable */
28619 #define RCC_APB1LPENR1_TIM13LPEN_Pos            (7U)
28620 #define RCC_APB1LPENR1_TIM13LPEN_Msk            (0x1UL << RCC_APB1LPENR1_TIM13LPEN_Pos) /*!< 0x00000080 */
28621 #define RCC_APB1LPENR1_TIM13LPEN                RCC_APB1LPENR1_TIM13LPEN_Msk         /*!< TIM13 enable */
28622 #define RCC_APB1LPENR1_TIM14LPEN_Pos            (8U)
28623 #define RCC_APB1LPENR1_TIM14LPEN_Msk            (0x1UL << RCC_APB1LPENR1_TIM14LPEN_Pos) /*!< 0x00000100 */
28624 #define RCC_APB1LPENR1_TIM14LPEN                RCC_APB1LPENR1_TIM14LPEN_Msk         /*!< TIM14 enable */
28625 #define RCC_APB1LPENR1_LPTIM1LPEN_Pos           (9U)
28626 #define RCC_APB1LPENR1_LPTIM1LPEN_Msk           (0x1UL << RCC_APB1LPENR1_LPTIM1LPEN_Pos)  /*!< 0x00000200 */
28627 #define RCC_APB1LPENR1_LPTIM1LPEN               RCC_APB1LPENR1_LPTIM1LPEN_Msk        /*!< LPTIM1 enable */
28628 #define RCC_APB1LPENR1_WWDGLPEN_Pos             (11U)
28629 #define RCC_APB1LPENR1_WWDGLPEN_Msk             (0x1UL << RCC_APB1LPENR1_WWDGLPEN_Pos)/*!< 0x00000800 */
28630 #define RCC_APB1LPENR1_WWDGLPEN                 RCC_APB1LPENR1_WWDGLPEN_Msk          /*!< WWDG enable */
28631 #define RCC_APB1LPENR1_TIM10LPEN_Pos            (12U)
28632 #define RCC_APB1LPENR1_TIM10LPEN_Msk            (0x1UL << RCC_APB1LPENR1_TIM10LPEN_Pos) /*!< 0x00001000 */
28633 #define RCC_APB1LPENR1_TIM10LPEN                RCC_APB1LPENR1_TIM10LPEN_Msk         /*!< TIM10 enable */
28634 #define RCC_APB1LPENR1_TIM11LPEN_Pos            (13U)
28635 #define RCC_APB1LPENR1_TIM11LPEN_Msk            (0x1UL << RCC_APB1LPENR1_TIM11LPEN_Pos) /*!< 0x00002000 */
28636 #define RCC_APB1LPENR1_TIM11LPEN                RCC_APB1LPENR1_TIM11LPEN_Msk         /*!< TIM11 enable */
28637 #define RCC_APB1LPENR1_SPI2LPEN_Pos             (14U)
28638 #define RCC_APB1LPENR1_SPI2LPEN_Msk             (0x1UL << RCC_APB1LPENR1_SPI2LPEN_Pos)/*!< 0x00004000 */
28639 #define RCC_APB1LPENR1_SPI2LPEN                 RCC_APB1LPENR1_SPI2LPEN_Msk          /*!< SPI2 enable */
28640 #define RCC_APB1LPENR1_SPI3LPEN_Pos             (15U)
28641 #define RCC_APB1LPENR1_SPI3LPEN_Msk             (0x1UL << RCC_APB1LPENR1_SPI3LPEN_Pos)/*!< 0x00008000 */
28642 #define RCC_APB1LPENR1_SPI3LPEN                 RCC_APB1LPENR1_SPI3LPEN_Msk          /*!< SPI3 enable */
28643 #define RCC_APB1LPENR1_SPDIFRX1LPEN_Pos         (16U)
28644 #define RCC_APB1LPENR1_SPDIFRX1LPEN_Msk         (0x1UL << RCC_APB1LPENR1_SPDIFRX1LPEN_Pos)    /*!< 0x00010000 */
28645 #define RCC_APB1LPENR1_SPDIFRX1LPEN             RCC_APB1LPENR1_SPDIFRX1LPEN_Msk      /*!< SPDIFRX1 enable */
28646 #define RCC_APB1LPENR1_USART2LPEN_Pos           (17U)
28647 #define RCC_APB1LPENR1_USART2LPEN_Msk           (0x1UL << RCC_APB1LPENR1_USART2LPEN_Pos)  /*!< 0x00020000 */
28648 #define RCC_APB1LPENR1_USART2LPEN               RCC_APB1LPENR1_USART2LPEN_Msk        /*!< USART2 enable */
28649 #define RCC_APB1LPENR1_USART3LPEN_Pos           (18U)
28650 #define RCC_APB1LPENR1_USART3LPEN_Msk           (0x1UL << RCC_APB1LPENR1_USART3LPEN_Pos)  /*!< 0x00040000 */
28651 #define RCC_APB1LPENR1_USART3LPEN               RCC_APB1LPENR1_USART3LPEN_Msk        /*!< USART3 enable */
28652 #define RCC_APB1LPENR1_UART4LPEN_Pos            (19U)
28653 #define RCC_APB1LPENR1_UART4LPEN_Msk            (0x1UL << RCC_APB1LPENR1_UART4LPEN_Pos) /*!< 0x00080000 */
28654 #define RCC_APB1LPENR1_UART4LPEN                RCC_APB1LPENR1_UART4LPEN_Msk         /*!< UART4 enable */
28655 #define RCC_APB1LPENR1_UART5LPEN_Pos            (20U)
28656 #define RCC_APB1LPENR1_UART5LPEN_Msk            (0x1UL << RCC_APB1LPENR1_UART5LPEN_Pos) /*!< 0x00100000 */
28657 #define RCC_APB1LPENR1_UART5LPEN                RCC_APB1LPENR1_UART5LPEN_Msk         /*!< UART5 enable */
28658 #define RCC_APB1LPENR1_I2C1LPEN_Pos             (21U)
28659 #define RCC_APB1LPENR1_I2C1LPEN_Msk             (0x1UL << RCC_APB1LPENR1_I2C1LPEN_Pos)/*!< 0x00200000 */
28660 #define RCC_APB1LPENR1_I2C1LPEN                 RCC_APB1LPENR1_I2C1LPEN_Msk          /*!< I2C1 enable */
28661 #define RCC_APB1LPENR1_I2C2LPEN_Pos             (22U)
28662 #define RCC_APB1LPENR1_I2C2LPEN_Msk             (0x1UL << RCC_APB1LPENR1_I2C2LPEN_Pos)/*!< 0x00400000 */
28663 #define RCC_APB1LPENR1_I2C2LPEN                 RCC_APB1LPENR1_I2C2LPEN_Msk          /*!< I2C2 enable */
28664 #define RCC_APB1LPENR1_I2C3LPEN_Pos             (23U)
28665 #define RCC_APB1LPENR1_I2C3LPEN_Msk             (0x1UL << RCC_APB1LPENR1_I2C3LPEN_Pos)/*!< 0x00800000 */
28666 #define RCC_APB1LPENR1_I2C3LPEN                 RCC_APB1LPENR1_I2C3LPEN_Msk          /*!< I2C3 enable */
28667 #define RCC_APB1LPENR1_I3C1LPEN_Pos             (24U)
28668 #define RCC_APB1LPENR1_I3C1LPEN_Msk             (0x1UL << RCC_APB1LPENR1_I3C1LPEN_Pos)/*!< 0x01000000 */
28669 #define RCC_APB1LPENR1_I3C1LPEN                 RCC_APB1LPENR1_I3C1LPEN_Msk          /*!< I3C1 enable */
28670 #define RCC_APB1LPENR1_I3C2LPEN_Pos             (25U)
28671 #define RCC_APB1LPENR1_I3C2LPEN_Msk             (0x1UL << RCC_APB1LPENR1_I3C2LPEN_Pos)/*!< 0x02000000 */
28672 #define RCC_APB1LPENR1_I3C2LPEN                 RCC_APB1LPENR1_I3C2LPEN_Msk          /*!< I3C2 enable */
28673 #define RCC_APB1LPENR1_UART7LPEN_Pos            (30U)
28674 #define RCC_APB1LPENR1_UART7LPEN_Msk            (0x1UL << RCC_APB1LPENR1_UART7LPEN_Pos) /*!< 0x40000000 */
28675 #define RCC_APB1LPENR1_UART7LPEN                RCC_APB1LPENR1_UART7LPEN_Msk         /*!< UART7 enable */
28676 #define RCC_APB1LPENR1_UART8LPEN_Pos            (31U)
28677 #define RCC_APB1LPENR1_UART8LPEN_Msk            (0x1UL << RCC_APB1LPENR1_UART8LPEN_Pos) /*!< 0x80000000 */
28678 #define RCC_APB1LPENR1_UART8LPEN                RCC_APB1LPENR1_UART8LPEN_Msk         /*!< UART8 enable */
28679 
28680 /****************  Bit definition for RCC_APB1LPENR2 register  ****************/
28681 #define RCC_APB1LPENR2_MDIOSLPEN_Pos            (5U)
28682 #define RCC_APB1LPENR2_MDIOSLPEN_Msk            (0x1UL << RCC_APB1LPENR2_MDIOSLPEN_Pos) /*!< 0x00000020 */
28683 #define RCC_APB1LPENR2_MDIOSLPEN                RCC_APB1LPENR2_MDIOSLPEN_Msk         /*!< MDIOS enable in Sleep mode */
28684 #define RCC_APB1LPENR2_FDCANLPEN_Pos            (8U)
28685 #define RCC_APB1LPENR2_FDCANLPEN_Msk            (0x1UL << RCC_APB1LPENR2_FDCANLPEN_Pos) /*!< 0x00000100 */
28686 #define RCC_APB1LPENR2_FDCANLPEN                RCC_APB1LPENR2_FDCANLPEN_Msk         /*!< FDCAN enablein Sleep mode */
28687 #define RCC_APB1LPENR2_UCPD1LPEN_Pos            (18U)
28688 #define RCC_APB1LPENR2_UCPD1LPEN_Msk            (0x1UL << RCC_APB1LPENR2_UCPD1LPEN_Pos) /*!< 0x00040000 */
28689 #define RCC_APB1LPENR2_UCPD1LPEN                RCC_APB1LPENR2_UCPD1LPEN_Msk         /*!< UCPD1 enable in Sleep mode */
28690 
28691 /****************  Bit definition for RCC_APB2LPENR register  *****************/
28692 #define RCC_APB2LPENR_TIM1LPEN_Pos              (0U)
28693 #define RCC_APB2LPENR_TIM1LPEN_Msk              (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
28694 #define RCC_APB2LPENR_TIM1LPEN                  RCC_APB2LPENR_TIM1LPEN_Msk           /*!< TIM1 enable */
28695 #define RCC_APB2LPENR_TIM8LPEN_Pos              (1U)
28696 #define RCC_APB2LPENR_TIM8LPEN_Msk              (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
28697 #define RCC_APB2LPENR_TIM8LPEN                  RCC_APB2LPENR_TIM8LPEN_Msk           /*!< TIM8 enable */
28698 #define RCC_APB2LPENR_USART1LPEN_Pos            (4U)
28699 #define RCC_APB2LPENR_USART1LPEN_Msk            (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
28700 #define RCC_APB2LPENR_USART1LPEN                RCC_APB2LPENR_USART1LPEN_Msk         /*!< USART1 enable */
28701 #define RCC_APB2LPENR_USART6LPEN_Pos            (5U)
28702 #define RCC_APB2LPENR_USART6LPEN_Msk            (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
28703 #define RCC_APB2LPENR_USART6LPEN                RCC_APB2LPENR_USART6LPEN_Msk         /*!< USART6 enable */
28704 #define RCC_APB2LPENR_UART9LPEN_Pos             (6U)
28705 #define RCC_APB2LPENR_UART9LPEN_Msk             (0x1UL << RCC_APB2LPENR_UART9LPEN_Pos)/*!< 0x00000040 */
28706 #define RCC_APB2LPENR_UART9LPEN                 RCC_APB2LPENR_UART9LPEN_Msk          /*!< UART9 enable */
28707 #define RCC_APB2LPENR_USART10LPEN_Pos           (7U)
28708 #define RCC_APB2LPENR_USART10LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART10LPEN_Pos)  /*!< 0x00000080 */
28709 #define RCC_APB2LPENR_USART10LPEN               RCC_APB2LPENR_USART10LPEN_Msk        /*!< USART10 enable */
28710 #define RCC_APB2LPENR_SPI1LPEN_Pos              (12U)
28711 #define RCC_APB2LPENR_SPI1LPEN_Msk              (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
28712 #define RCC_APB2LPENR_SPI1LPEN                  RCC_APB2LPENR_SPI1LPEN_Msk           /*!< SPI1 enable */
28713 #define RCC_APB2LPENR_SPI4LPEN_Pos              (13U)
28714 #define RCC_APB2LPENR_SPI4LPEN_Msk              (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
28715 #define RCC_APB2LPENR_SPI4LPEN                  RCC_APB2LPENR_SPI4LPEN_Msk           /*!< SPI4 enable */
28716 #define RCC_APB2LPENR_TIM18LPEN_Pos             (15U)
28717 #define RCC_APB2LPENR_TIM18LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM18LPEN_Pos)/*!< 0x00008000 */
28718 #define RCC_APB2LPENR_TIM18LPEN                 RCC_APB2LPENR_TIM18LPEN_Msk          /*!< TIM18 enable */
28719 #define RCC_APB2LPENR_TIM15LPEN_Pos             (16U)
28720 #define RCC_APB2LPENR_TIM15LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos)/*!< 0x00010000 */
28721 #define RCC_APB2LPENR_TIM15LPEN                 RCC_APB2LPENR_TIM15LPEN_Msk          /*!< TIM15 enable */
28722 #define RCC_APB2LPENR_TIM16LPEN_Pos             (17U)
28723 #define RCC_APB2LPENR_TIM16LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos)/*!< 0x00020000 */
28724 #define RCC_APB2LPENR_TIM16LPEN                 RCC_APB2LPENR_TIM16LPEN_Msk          /*!< TIM16 enable */
28725 #define RCC_APB2LPENR_TIM17LPEN_Pos             (18U)
28726 #define RCC_APB2LPENR_TIM17LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos)/*!< 0x00040000 */
28727 #define RCC_APB2LPENR_TIM17LPEN                 RCC_APB2LPENR_TIM17LPEN_Msk          /*!< TIM17 enable */
28728 #define RCC_APB2LPENR_TIM9LPEN_Pos              (19U)
28729 #define RCC_APB2LPENR_TIM9LPEN_Msk              (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00080000 */
28730 #define RCC_APB2LPENR_TIM9LPEN                  RCC_APB2LPENR_TIM9LPEN_Msk           /*!< TIM9 enable */
28731 #define RCC_APB2LPENR_SPI5LPEN_Pos              (20U)
28732 #define RCC_APB2LPENR_SPI5LPEN_Msk              (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
28733 #define RCC_APB2LPENR_SPI5LPEN                  RCC_APB2LPENR_SPI5LPEN_Msk           /*!< SPI5 enable */
28734 #define RCC_APB2LPENR_SAI1LPEN_Pos              (21U)
28735 #define RCC_APB2LPENR_SAI1LPEN_Msk              (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00200000 */
28736 #define RCC_APB2LPENR_SAI1LPEN                  RCC_APB2LPENR_SAI1LPEN_Msk           /*!< SAI1 enable */
28737 #define RCC_APB2LPENR_SAI2LPEN_Pos              (22U)
28738 #define RCC_APB2LPENR_SAI2LPEN_Msk              (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00400000 */
28739 #define RCC_APB2LPENR_SAI2LPEN                  RCC_APB2LPENR_SAI2LPEN_Msk           /*!< SAI2 enable */
28740 
28741 /****************  Bit definition for RCC_APB3LPENR register  *****************/
28742 #define RCC_APB3LPENR_DFTLPEN_Pos               (2U)
28743 #define RCC_APB3LPENR_DFTLPEN_Msk               (0x1UL << RCC_APB3LPENR_DFTLPEN_Pos)  /*!< 0x00000004 */
28744 #define RCC_APB3LPENR_DFTLPEN                   RCC_APB3LPENR_DFTLPEN_Msk            /*!< DFT enable */
28745 
28746 /****************  Bit definition for RCC_APB4LPENR1 register  ****************/
28747 #define RCC_APB4LPENR1_HDPLPEN_Pos              (2U)
28748 #define RCC_APB4LPENR1_HDPLPEN_Msk              (0x1UL << RCC_APB4LPENR1_HDPLPEN_Pos) /*!< 0x00000004 */
28749 #define RCC_APB4LPENR1_HDPLPEN                  RCC_APB4LPENR1_HDPLPEN_Msk           /*!< HDP enable */
28750 #define RCC_APB4LPENR1_LPUART1LPEN_Pos          (3U)
28751 #define RCC_APB4LPENR1_LPUART1LPEN_Msk          (0x1UL << RCC_APB4LPENR1_LPUART1LPEN_Pos)   /*!< 0x00000008 */
28752 #define RCC_APB4LPENR1_LPUART1LPEN              RCC_APB4LPENR1_LPUART1LPEN_Msk       /*!< LPUART1 enable */
28753 #define RCC_APB4LPENR1_SPI6LPEN_Pos             (5U)
28754 #define RCC_APB4LPENR1_SPI6LPEN_Msk             (0x1UL << RCC_APB4LPENR1_SPI6LPEN_Pos)/*!< 0x00000020 */
28755 #define RCC_APB4LPENR1_SPI6LPEN                 RCC_APB4LPENR1_SPI6LPEN_Msk          /*!< SPI6 enable */
28756 #define RCC_APB4LPENR1_I2C4LPEN_Pos             (7U)
28757 #define RCC_APB4LPENR1_I2C4LPEN_Msk             (0x1UL << RCC_APB4LPENR1_I2C4LPEN_Pos)/*!< 0x00000080 */
28758 #define RCC_APB4LPENR1_I2C4LPEN                 RCC_APB4LPENR1_I2C4LPEN_Msk          /*!< I2C4 enable */
28759 #define RCC_APB4LPENR1_LPTIM2LPEN_Pos           (9U)
28760 #define RCC_APB4LPENR1_LPTIM2LPEN_Msk           (0x1UL << RCC_APB4LPENR1_LPTIM2LPEN_Pos)  /*!< 0x00000200 */
28761 #define RCC_APB4LPENR1_LPTIM2LPEN               RCC_APB4LPENR1_LPTIM2LPEN_Msk        /*!< LPTIM2 enable */
28762 #define RCC_APB4LPENR1_LPTIM3LPEN_Pos           (10U)
28763 #define RCC_APB4LPENR1_LPTIM3LPEN_Msk           (0x1UL << RCC_APB4LPENR1_LPTIM3LPEN_Pos)  /*!< 0x00000400 */
28764 #define RCC_APB4LPENR1_LPTIM3LPEN               RCC_APB4LPENR1_LPTIM3LPEN_Msk        /*!< LPTIM3 enable */
28765 #define RCC_APB4LPENR1_LPTIM4LPEN_Pos           (11U)
28766 #define RCC_APB4LPENR1_LPTIM4LPEN_Msk           (0x1UL << RCC_APB4LPENR1_LPTIM4LPEN_Pos)  /*!< 0x00000800 */
28767 #define RCC_APB4LPENR1_LPTIM4LPEN               RCC_APB4LPENR1_LPTIM4LPEN_Msk        /*!< LPTIM4 enable */
28768 #define RCC_APB4LPENR1_LPTIM5LPEN_Pos           (12U)
28769 #define RCC_APB4LPENR1_LPTIM5LPEN_Msk           (0x1UL << RCC_APB4LPENR1_LPTIM5LPEN_Pos)  /*!< 0x00001000 */
28770 #define RCC_APB4LPENR1_LPTIM5LPEN               RCC_APB4LPENR1_LPTIM5LPEN_Msk        /*!< LPTIM5 enable */
28771 #define RCC_APB4LPENR1_VREFBUFLPEN_Pos          (15U)
28772 #define RCC_APB4LPENR1_VREFBUFLPEN_Msk          (0x1UL << RCC_APB4LPENR1_VREFBUFLPEN_Pos)   /*!< 0x00008000 */
28773 #define RCC_APB4LPENR1_VREFBUFLPEN              RCC_APB4LPENR1_VREFBUFLPEN_Msk       /*!< VREFBUF enable */
28774 #define RCC_APB4LPENR1_RTCLPEN_Pos              (16U)
28775 #define RCC_APB4LPENR1_RTCLPEN_Msk              (0x1UL << RCC_APB4LPENR1_RTCLPEN_Pos) /*!< 0x00010000 */
28776 #define RCC_APB4LPENR1_RTCLPEN                  RCC_APB4LPENR1_RTCLPEN_Msk           /*!< RTC enable */
28777 #define RCC_APB4LPENR1_RTCAPBLPEN_Pos           (17U)
28778 #define RCC_APB4LPENR1_RTCAPBLPEN_Msk           (0x1UL << RCC_APB4LPENR1_RTCAPBLPEN_Pos)  /*!< 0x00020000 */
28779 #define RCC_APB4LPENR1_RTCAPBLPEN               RCC_APB4LPENR1_RTCAPBLPEN_Msk        /*!< RTCAPB enable */
28780 
28781 /****************  Bit definition for RCC_APB4LPENR2 register  ****************/
28782 #define RCC_APB4LPENR2_SYSCFGLPEN_Pos           (0U)
28783 #define RCC_APB4LPENR2_SYSCFGLPEN_Msk           (0x1UL << RCC_APB4LPENR2_SYSCFGLPEN_Pos)  /*!< 0x00000001 */
28784 #define RCC_APB4LPENR2_SYSCFGLPEN               RCC_APB4LPENR2_SYSCFGLPEN_Msk        /*!< SYSCFG enable */
28785 #define RCC_APB4LPENR2_BSECLPEN_Pos             (1U)
28786 #define RCC_APB4LPENR2_BSECLPEN_Msk             (0x1UL << RCC_APB4LPENR2_BSECLPEN_Pos)/*!< 0x00000002 */
28787 #define RCC_APB4LPENR2_BSECLPEN                 RCC_APB4LPENR2_BSECLPEN_Msk          /*!< BSEC enable */
28788 #define RCC_APB4LPENR2_DTSLPEN_Pos              (2U)
28789 #define RCC_APB4LPENR2_DTSLPEN_Msk              (0x1UL << RCC_APB4LPENR2_DTSLPEN_Pos) /*!< 0x00000004 */
28790 #define RCC_APB4LPENR2_DTSLPEN                  RCC_APB4LPENR2_DTSLPEN_Msk           /*!< DTS enable */
28791 
28792 /****************  Bit definition for RCC_APB5LPENR register  *****************/
28793 #define RCC_APB5LPENR_LTDCLPEN_Pos              (1U)
28794 #define RCC_APB5LPENR_LTDCLPEN_Msk              (0x1UL << RCC_APB5LPENR_LTDCLPEN_Pos) /*!< 0x00000002 */
28795 #define RCC_APB5LPENR_LTDCLPEN                  RCC_APB5LPENR_LTDCLPEN_Msk           /*!< LTDC enable */
28796 #define RCC_APB5LPENR_DCMIPPLPEN_Pos            (2U)
28797 #define RCC_APB5LPENR_DCMIPPLPEN_Msk            (0x1UL << RCC_APB5LPENR_DCMIPPLPEN_Pos) /*!< 0x00000004 */
28798 #define RCC_APB5LPENR_DCMIPPLPEN                RCC_APB5LPENR_DCMIPPLPEN_Msk         /*!< DCMIPP enable */
28799 #define RCC_APB5LPENR_GFXTIMLPEN_Pos            (4U)
28800 #define RCC_APB5LPENR_GFXTIMLPEN_Msk            (0x1UL << RCC_APB5LPENR_GFXTIMLPEN_Pos) /*!< 0x00000010 */
28801 #define RCC_APB5LPENR_GFXTIMLPEN                RCC_APB5LPENR_GFXTIMLPEN_Msk         /*!< GFXTIM enable */
28802 #define RCC_APB5LPENR_VENCLPEN_Pos              (5U)
28803 #define RCC_APB5LPENR_VENCLPEN_Msk              (0x1UL << RCC_APB5LPENR_VENCLPEN_Pos) /*!< 0x00000020 */
28804 #define RCC_APB5LPENR_VENCLPEN                  RCC_APB5LPENR_VENCLPEN_Msk           /*!< VENC enable */
28805 #define RCC_APB5LPENR_CSILPEN_Pos               (6U)
28806 #define RCC_APB5LPENR_CSILPEN_Msk               (0x1UL << RCC_APB5LPENR_CSILPEN_Pos)  /*!< 0x00000040 */
28807 #define RCC_APB5LPENR_CSILPEN                   RCC_APB5LPENR_CSILPEN_Msk            /*!< CSI enable */
28808 
28809 /*******************  Bit definition for RCC_RDCR register  *******************/
28810 #define RCC_RDCR_MRD_Pos                        (16U)
28811 #define RCC_RDCR_MRD_Msk                        (0x1FUL << RCC_RDCR_MRD_Pos)          /*!< 0x001F0000 */
28812 #define RCC_RDCR_MRD                            RCC_RDCR_MRD_Msk                     /*!< Minimum reset duration */
28813 
28814 /*****************  Bit definition for RCC_SECCFGR0 register  *****************/
28815 #define RCC_SECCFGR0_LSISEC_Pos                 (0U)
28816 #define RCC_SECCFGR0_LSISEC_Msk                 (0x1UL << RCC_SECCFGR0_LSISEC_Pos)    /*!< 0x00000001 */
28817 #define RCC_SECCFGR0_LSISEC                     RCC_SECCFGR0_LSISEC_Msk              /*!< Secure protection of LSI oscillator configuration bits */
28818 #define RCC_SECCFGR0_LSESEC_Pos                 (1U)
28819 #define RCC_SECCFGR0_LSESEC_Msk                 (0x1UL << RCC_SECCFGR0_LSESEC_Pos)    /*!< 0x00000002 */
28820 #define RCC_SECCFGR0_LSESEC                     RCC_SECCFGR0_LSESEC_Msk              /*!< Secure protection of LSE oscillator configuration bits */
28821 #define RCC_SECCFGR0_MSISEC_Pos                 (2U)
28822 #define RCC_SECCFGR0_MSISEC_Msk                 (0x1UL << RCC_SECCFGR0_MSISEC_Pos)    /*!< 0x00000004 */
28823 #define RCC_SECCFGR0_MSISEC                     RCC_SECCFGR0_MSISEC_Msk              /*!< Secure protection of MSI oscillator configuration bits */
28824 #define RCC_SECCFGR0_HSISEC_Pos                 (3U)
28825 #define RCC_SECCFGR0_HSISEC_Msk                 (0x1UL << RCC_SECCFGR0_HSISEC_Pos)    /*!< 0x00000008 */
28826 #define RCC_SECCFGR0_HSISEC                     RCC_SECCFGR0_HSISEC_Msk              /*!< Secure protection of HSI oscillator configuration bits */
28827 #define RCC_SECCFGR0_HSESEC_Pos                 (4U)
28828 #define RCC_SECCFGR0_HSESEC_Msk                 (0x1UL << RCC_SECCFGR0_HSESEC_Pos)    /*!< 0x00000010 */
28829 #define RCC_SECCFGR0_HSESEC                     RCC_SECCFGR0_HSESEC_Msk              /*!< Secure protection of HSE oscillator configuration bits */
28830 
28831 /****************  Bit definition for RCC_PRIVCFGR0 register  *****************/
28832 #define RCC_PRIVCFGR0_LSIPRIV_Pos               (0U)
28833 #define RCC_PRIVCFGR0_LSIPRIV_Msk               (0x1UL << RCC_PRIVCFGR0_LSIPRIV_Pos)  /*!< 0x00000001 */
28834 #define RCC_PRIVCFGR0_LSIPRIV                   RCC_PRIVCFGR0_LSIPRIV_Msk            /*!< Privileged protection of LSI oscillator configuration bits */
28835 #define RCC_PRIVCFGR0_LSEPRIV_Pos               (1U)
28836 #define RCC_PRIVCFGR0_LSEPRIV_Msk               (0x1UL << RCC_PRIVCFGR0_LSEPRIV_Pos)  /*!< 0x00000002 */
28837 #define RCC_PRIVCFGR0_LSEPRIV                   RCC_PRIVCFGR0_LSEPRIV_Msk            /*!< Privileged protection of LSE oscillator configuration bits */
28838 #define RCC_PRIVCFGR0_MSIPRIV_Pos               (2U)
28839 #define RCC_PRIVCFGR0_MSIPRIV_Msk               (0x1UL << RCC_PRIVCFGR0_MSIPRIV_Pos)  /*!< 0x00000004 */
28840 #define RCC_PRIVCFGR0_MSIPRIV                   RCC_PRIVCFGR0_MSIPRIV_Msk            /*!< Privileged protection of MSI oscillator configuration bits */
28841 #define RCC_PRIVCFGR0_HSIPRIV_Pos               (3U)
28842 #define RCC_PRIVCFGR0_HSIPRIV_Msk               (0x1UL << RCC_PRIVCFGR0_HSIPRIV_Pos)  /*!< 0x00000008 */
28843 #define RCC_PRIVCFGR0_HSIPRIV                   RCC_PRIVCFGR0_HSIPRIV_Msk            /*!< Privileged protection of HSI oscillator configuration bits */
28844 #define RCC_PRIVCFGR0_HSEPRIV_Pos               (4U)
28845 #define RCC_PRIVCFGR0_HSEPRIV_Msk               (0x1UL << RCC_PRIVCFGR0_HSEPRIV_Pos)  /*!< 0x00000010 */
28846 #define RCC_PRIVCFGR0_HSEPRIV                   RCC_PRIVCFGR0_HSEPRIV_Msk            /*!< Privileged protection of HSE oscillator configuration bits */
28847 
28848 /****************  Bit definition for RCC_LOCKCFGR0 register  *****************/
28849 #define RCC_LOCKCFGR0_LSILOCK_Pos               (0U)
28850 #define RCC_LOCKCFGR0_LSILOCK_Msk               (0x1UL << RCC_LOCKCFGR0_LSILOCK_Pos)  /*!< 0x00000001 */
28851 #define RCC_LOCKCFGR0_LSILOCK                   RCC_LOCKCFGR0_LSILOCK_Msk            /*!< Locked protection of LSI oscillator configuration bits */
28852 #define RCC_LOCKCFGR0_LSELOCK_Pos               (1U)
28853 #define RCC_LOCKCFGR0_LSELOCK_Msk               (0x1UL << RCC_LOCKCFGR0_LSELOCK_Pos)  /*!< 0x00000002 */
28854 #define RCC_LOCKCFGR0_LSELOCK                   RCC_LOCKCFGR0_LSELOCK_Msk            /*!< Locked protection of LSE oscillator configuration bits */
28855 #define RCC_LOCKCFGR0_MSILOCK_Pos               (2U)
28856 #define RCC_LOCKCFGR0_MSILOCK_Msk               (0x1UL << RCC_LOCKCFGR0_MSILOCK_Pos)  /*!< 0x00000004 */
28857 #define RCC_LOCKCFGR0_MSILOCK                   RCC_LOCKCFGR0_MSILOCK_Msk            /*!< Locked protection of MSI oscillator configuration bits */
28858 #define RCC_LOCKCFGR0_HSILOCK_Pos               (3U)
28859 #define RCC_LOCKCFGR0_HSILOCK_Msk               (0x1UL << RCC_LOCKCFGR0_HSILOCK_Pos)  /*!< 0x00000008 */
28860 #define RCC_LOCKCFGR0_HSILOCK                   RCC_LOCKCFGR0_HSILOCK_Msk            /*!< Locked protection of HSI oscillator configuration bits */
28861 #define RCC_LOCKCFGR0_HSELOCK_Pos               (4U)
28862 #define RCC_LOCKCFGR0_HSELOCK_Msk               (0x1UL << RCC_LOCKCFGR0_HSELOCK_Pos)  /*!< 0x00000010 */
28863 #define RCC_LOCKCFGR0_HSELOCK                   RCC_LOCKCFGR0_HSELOCK_Msk            /*!< Locked protection of HSE oscillator configuration bits */
28864 
28865 /*****************  Bit definition for RCC_PUBCFGR0 register  *****************/
28866 #define RCC_PUBCFGR0_LSIPUB_Pos                 (0U)
28867 #define RCC_PUBCFGR0_LSIPUB_Msk                 (0x1UL << RCC_PUBCFGR0_LSIPUB_Pos)    /*!< 0x00000001 */
28868 #define RCC_PUBCFGR0_LSIPUB                     RCC_PUBCFGR0_LSIPUB_Msk              /*!< Public protection of LSI oscillator configuration bits */
28869 #define RCC_PUBCFGR0_LSEPUB_Pos                 (1U)
28870 #define RCC_PUBCFGR0_LSEPUB_Msk                 (0x1UL << RCC_PUBCFGR0_LSEPUB_Pos)    /*!< 0x00000002 */
28871 #define RCC_PUBCFGR0_LSEPUB                     RCC_PUBCFGR0_LSEPUB_Msk              /*!< Public protection of LSE oscillator configuration bits */
28872 #define RCC_PUBCFGR0_MSIPUB_Pos                 (2U)
28873 #define RCC_PUBCFGR0_MSIPUB_Msk                 (0x1UL << RCC_PUBCFGR0_MSIPUB_Pos)    /*!< 0x00000004 */
28874 #define RCC_PUBCFGR0_MSIPUB                     RCC_PUBCFGR0_MSIPUB_Msk              /*!< Public protection of MSI oscillator configuration bits */
28875 #define RCC_PUBCFGR0_HSIPUB_Pos                 (3U)
28876 #define RCC_PUBCFGR0_HSIPUB_Msk                 (0x1UL << RCC_PUBCFGR0_HSIPUB_Pos)    /*!< 0x00000008 */
28877 #define RCC_PUBCFGR0_HSIPUB                     RCC_PUBCFGR0_HSIPUB_Msk              /*!< Public protection of HSI oscillator configuration bits */
28878 #define RCC_PUBCFGR0_HSEPUB_Pos                 (4U)
28879 #define RCC_PUBCFGR0_HSEPUB_Msk                 (0x1UL << RCC_PUBCFGR0_HSEPUB_Pos)    /*!< 0x00000010 */
28880 #define RCC_PUBCFGR0_HSEPUB                     RCC_PUBCFGR0_HSEPUB_Msk              /*!< Public protection of HSE oscillator configuration bits */
28881 
28882 /*****************  Bit definition for RCC_SECCFGR1 register  *****************/
28883 #define RCC_SECCFGR1_PLL1SEC_Pos                (0U)
28884 #define RCC_SECCFGR1_PLL1SEC_Msk                (0x1UL << RCC_SECCFGR1_PLL1SEC_Pos)   /*!< 0x00000001 */
28885 #define RCC_SECCFGR1_PLL1SEC                    RCC_SECCFGR1_PLL1SEC_Msk             /*!< Secure protection of PLL1 configuration bits */
28886 #define RCC_SECCFGR1_PLL2SEC_Pos                (1U)
28887 #define RCC_SECCFGR1_PLL2SEC_Msk                (0x1UL << RCC_SECCFGR1_PLL2SEC_Pos)   /*!< 0x00000002 */
28888 #define RCC_SECCFGR1_PLL2SEC                    RCC_SECCFGR1_PLL2SEC_Msk             /*!< Secure protection of PLL2 configuration bits */
28889 #define RCC_SECCFGR1_PLL3SEC_Pos                (2U)
28890 #define RCC_SECCFGR1_PLL3SEC_Msk                (0x1UL << RCC_SECCFGR1_PLL3SEC_Pos)   /*!< 0x00000004 */
28891 #define RCC_SECCFGR1_PLL3SEC                    RCC_SECCFGR1_PLL3SEC_Msk             /*!< Secure protection of PLL3 configuration bits */
28892 #define RCC_SECCFGR1_PLL4SEC_Pos                (3U)
28893 #define RCC_SECCFGR1_PLL4SEC_Msk                (0x1UL << RCC_SECCFGR1_PLL4SEC_Pos)   /*!< 0x00000008 */
28894 #define RCC_SECCFGR1_PLL4SEC                    RCC_SECCFGR1_PLL4SEC_Msk             /*!< Secure protection of PLL4 configuration bits */
28895 
28896 /****************  Bit definition for RCC_PRIVCFGR1 register  *****************/
28897 #define RCC_PRIVCFGR1_PLL1PRIV_Pos              (0U)
28898 #define RCC_PRIVCFGR1_PLL1PRIV_Msk              (0x1UL << RCC_PRIVCFGR1_PLL1PRIV_Pos) /*!< 0x00000001 */
28899 #define RCC_PRIVCFGR1_PLL1PRIV                  RCC_PRIVCFGR1_PLL1PRIV_Msk           /*!< Privileged protection of PLL1 configuration bits */
28900 #define RCC_PRIVCFGR1_PLL2PRIV_Pos              (1U)
28901 #define RCC_PRIVCFGR1_PLL2PRIV_Msk              (0x1UL << RCC_PRIVCFGR1_PLL2PRIV_Pos) /*!< 0x00000002 */
28902 #define RCC_PRIVCFGR1_PLL2PRIV                  RCC_PRIVCFGR1_PLL2PRIV_Msk           /*!< Privileged protection of PLL2 configuration bits */
28903 #define RCC_PRIVCFGR1_PLL3PRIV_Pos              (2U)
28904 #define RCC_PRIVCFGR1_PLL3PRIV_Msk              (0x1UL << RCC_PRIVCFGR1_PLL3PRIV_Pos) /*!< 0x00000004 */
28905 #define RCC_PRIVCFGR1_PLL3PRIV                  RCC_PRIVCFGR1_PLL3PRIV_Msk           /*!< Privileged protection of PLL3 configuration bits */
28906 #define RCC_PRIVCFGR1_PLL4PRIV_Pos              (3U)
28907 #define RCC_PRIVCFGR1_PLL4PRIV_Msk              (0x1UL << RCC_PRIVCFGR1_PLL4PRIV_Pos) /*!< 0x00000008 */
28908 #define RCC_PRIVCFGR1_PLL4PRIV                  RCC_PRIVCFGR1_PLL4PRIV_Msk           /*!< Privileged protection of PLL4 configuration bits */
28909 
28910 /****************  Bit definition for RCC_LOCKCFGR1 register  *****************/
28911 #define RCC_LOCKCFGR1_PLL1LOCK_Pos              (0U)
28912 #define RCC_LOCKCFGR1_PLL1LOCK_Msk              (0x1UL << RCC_LOCKCFGR1_PLL1LOCK_Pos) /*!< 0x00000001 */
28913 #define RCC_LOCKCFGR1_PLL1LOCK                  RCC_LOCKCFGR1_PLL1LOCK_Msk           /*!< Locked protection of PLL1 configuration bits */
28914 #define RCC_LOCKCFGR1_PLL2LOCK_Pos              (1U)
28915 #define RCC_LOCKCFGR1_PLL2LOCK_Msk              (0x1UL << RCC_LOCKCFGR1_PLL2LOCK_Pos) /*!< 0x00000002 */
28916 #define RCC_LOCKCFGR1_PLL2LOCK                  RCC_LOCKCFGR1_PLL2LOCK_Msk           /*!< Locked protection of PLL2 configuration bits */
28917 #define RCC_LOCKCFGR1_PLL3LOCK_Pos              (2U)
28918 #define RCC_LOCKCFGR1_PLL3LOCK_Msk              (0x1UL << RCC_LOCKCFGR1_PLL3LOCK_Pos) /*!< 0x00000004 */
28919 #define RCC_LOCKCFGR1_PLL3LOCK                  RCC_LOCKCFGR1_PLL3LOCK_Msk           /*!< Locked protection of PLL3 configuration bits */
28920 #define RCC_LOCKCFGR1_PLL4LOCK_Pos              (3U)
28921 #define RCC_LOCKCFGR1_PLL4LOCK_Msk              (0x1UL << RCC_LOCKCFGR1_PLL4LOCK_Pos) /*!< 0x00000008 */
28922 #define RCC_LOCKCFGR1_PLL4LOCK                  RCC_LOCKCFGR1_PLL4LOCK_Msk           /*!< Locked protection of PLL4 configuration bits */
28923 
28924 /*****************  Bit definition for RCC_PUBCFGR1 register  *****************/
28925 #define RCC_PUBCFGR1_PLL1PUB_Pos                (0U)
28926 #define RCC_PUBCFGR1_PLL1PUB_Msk                (0x1UL << RCC_PUBCFGR1_PLL1PUB_Pos)   /*!< 0x00000001 */
28927 #define RCC_PUBCFGR1_PLL1PUB                    RCC_PUBCFGR1_PLL1PUB_Msk             /*!< Public protection of PLL1 configuration bits */
28928 #define RCC_PUBCFGR1_PLL2PUB_Pos                (1U)
28929 #define RCC_PUBCFGR1_PLL2PUB_Msk                (0x1UL << RCC_PUBCFGR1_PLL2PUB_Pos)   /*!< 0x00000002 */
28930 #define RCC_PUBCFGR1_PLL2PUB                    RCC_PUBCFGR1_PLL2PUB_Msk             /*!< Public protection of PLL2 configuration bits */
28931 #define RCC_PUBCFGR1_PLL3PUB_Pos                (2U)
28932 #define RCC_PUBCFGR1_PLL3PUB_Msk                (0x1UL << RCC_PUBCFGR1_PLL3PUB_Pos)   /*!< 0x00000004 */
28933 #define RCC_PUBCFGR1_PLL3PUB                    RCC_PUBCFGR1_PLL3PUB_Msk             /*!< Public protection of PLL3 configuration bits */
28934 #define RCC_PUBCFGR1_PLL4PUB_Pos                (3U)
28935 #define RCC_PUBCFGR1_PLL4PUB_Msk                (0x1UL << RCC_PUBCFGR1_PLL4PUB_Pos)   /*!< 0x00000008 */
28936 #define RCC_PUBCFGR1_PLL4PUB                    RCC_PUBCFGR1_PLL4PUB_Msk             /*!< Public protection of PLL4 configuration bits */
28937 
28938 /*****************  Bit definition for RCC_SECCFGR2 register  *****************/
28939 #define RCC_SECCFGR2_IC1SEC_Pos                 (0U)
28940 #define RCC_SECCFGR2_IC1SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC1SEC_Pos)    /*!< 0x00000001 */
28941 #define RCC_SECCFGR2_IC1SEC                     RCC_SECCFGR2_IC1SEC_Msk              /*!< Secure protection of IC1 divider configuration bits */
28942 #define RCC_SECCFGR2_IC2SEC_Pos                 (1U)
28943 #define RCC_SECCFGR2_IC2SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC2SEC_Pos)    /*!< 0x00000002 */
28944 #define RCC_SECCFGR2_IC2SEC                     RCC_SECCFGR2_IC2SEC_Msk              /*!< Secure protection of IC2 divider configuration bits */
28945 #define RCC_SECCFGR2_IC3SEC_Pos                 (2U)
28946 #define RCC_SECCFGR2_IC3SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC3SEC_Pos)    /*!< 0x00000004 */
28947 #define RCC_SECCFGR2_IC3SEC                     RCC_SECCFGR2_IC3SEC_Msk              /*!< Secure protection of IC3 divider configuration bits */
28948 #define RCC_SECCFGR2_IC4SEC_Pos                 (3U)
28949 #define RCC_SECCFGR2_IC4SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC4SEC_Pos)    /*!< 0x00000008 */
28950 #define RCC_SECCFGR2_IC4SEC                     RCC_SECCFGR2_IC4SEC_Msk              /*!< Secure protection of IC4 divider configuration bits */
28951 #define RCC_SECCFGR2_IC5SEC_Pos                 (4U)
28952 #define RCC_SECCFGR2_IC5SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC5SEC_Pos)    /*!< 0x00000010 */
28953 #define RCC_SECCFGR2_IC5SEC                     RCC_SECCFGR2_IC5SEC_Msk              /*!< Secure protection of IC5 divider configuration bits */
28954 #define RCC_SECCFGR2_IC6SEC_Pos                 (5U)
28955 #define RCC_SECCFGR2_IC6SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC6SEC_Pos)    /*!< 0x00000020 */
28956 #define RCC_SECCFGR2_IC6SEC                     RCC_SECCFGR2_IC6SEC_Msk              /*!< Secure protection of IC6 divider configuration bits */
28957 #define RCC_SECCFGR2_IC7SEC_Pos                 (6U)
28958 #define RCC_SECCFGR2_IC7SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC7SEC_Pos)    /*!< 0x00000040 */
28959 #define RCC_SECCFGR2_IC7SEC                     RCC_SECCFGR2_IC7SEC_Msk              /*!< Secure protection of IC7 divider configuration bits */
28960 #define RCC_SECCFGR2_IC8SEC_Pos                 (7U)
28961 #define RCC_SECCFGR2_IC8SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC8SEC_Pos)    /*!< 0x00000080 */
28962 #define RCC_SECCFGR2_IC8SEC                     RCC_SECCFGR2_IC8SEC_Msk              /*!< Secure protection of IC8 divider configuration bits */
28963 #define RCC_SECCFGR2_IC9SEC_Pos                 (8U)
28964 #define RCC_SECCFGR2_IC9SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC9SEC_Pos)    /*!< 0x00000100 */
28965 #define RCC_SECCFGR2_IC9SEC                     RCC_SECCFGR2_IC9SEC_Msk              /*!< Secure protection of IC9 divider configuration bits */
28966 #define RCC_SECCFGR2_IC10SEC_Pos                (9U)
28967 #define RCC_SECCFGR2_IC10SEC_Msk                (0x1UL << RCC_SECCFGR2_IC10SEC_Pos)   /*!< 0x00000200 */
28968 #define RCC_SECCFGR2_IC10SEC                    RCC_SECCFGR2_IC10SEC_Msk             /*!< Secure protection of IC10 divider configuration bits */
28969 #define RCC_SECCFGR2_IC11SEC_Pos                (10U)
28970 #define RCC_SECCFGR2_IC11SEC_Msk                (0x1UL << RCC_SECCFGR2_IC11SEC_Pos)   /*!< 0x00000400 */
28971 #define RCC_SECCFGR2_IC11SEC                    RCC_SECCFGR2_IC11SEC_Msk             /*!< Secure protection of IC11 divider configuration bits */
28972 #define RCC_SECCFGR2_IC12SEC_Pos                (11U)
28973 #define RCC_SECCFGR2_IC12SEC_Msk                (0x1UL << RCC_SECCFGR2_IC12SEC_Pos)   /*!< 0x00000800 */
28974 #define RCC_SECCFGR2_IC12SEC                    RCC_SECCFGR2_IC12SEC_Msk             /*!< Secure protection of IC12 divider configuration bits */
28975 #define RCC_SECCFGR2_IC13SEC_Pos                (12U)
28976 #define RCC_SECCFGR2_IC13SEC_Msk                (0x1UL << RCC_SECCFGR2_IC13SEC_Pos)   /*!< 0x00001000 */
28977 #define RCC_SECCFGR2_IC13SEC                    RCC_SECCFGR2_IC13SEC_Msk             /*!< Secure protection of IC13 divider configuration bits */
28978 #define RCC_SECCFGR2_IC14SEC_Pos                (13U)
28979 #define RCC_SECCFGR2_IC14SEC_Msk                (0x1UL << RCC_SECCFGR2_IC14SEC_Pos)   /*!< 0x00002000 */
28980 #define RCC_SECCFGR2_IC14SEC                    RCC_SECCFGR2_IC14SEC_Msk             /*!< Secure protection of IC14 divider configuration bits */
28981 #define RCC_SECCFGR2_IC15SEC_Pos                (14U)
28982 #define RCC_SECCFGR2_IC15SEC_Msk                (0x1UL << RCC_SECCFGR2_IC15SEC_Pos)   /*!< 0x00004000 */
28983 #define RCC_SECCFGR2_IC15SEC                    RCC_SECCFGR2_IC15SEC_Msk             /*!< Secure protection of IC15 divider configuration bits */
28984 #define RCC_SECCFGR2_IC16SEC_Pos                (15U)
28985 #define RCC_SECCFGR2_IC16SEC_Msk                (0x1UL << RCC_SECCFGR2_IC16SEC_Pos)   /*!< 0x00008000 */
28986 #define RCC_SECCFGR2_IC16SEC                    RCC_SECCFGR2_IC16SEC_Msk             /*!< Secure protection of IC16 divider configuration bits */
28987 #define RCC_SECCFGR2_IC17SEC_Pos                (16U)
28988 #define RCC_SECCFGR2_IC17SEC_Msk                (0x1UL << RCC_SECCFGR2_IC17SEC_Pos)   /*!< 0x00010000 */
28989 #define RCC_SECCFGR2_IC17SEC                    RCC_SECCFGR2_IC17SEC_Msk             /*!< Secure protection of IC17 divider configuration bits */
28990 #define RCC_SECCFGR2_IC18SEC_Pos                (17U)
28991 #define RCC_SECCFGR2_IC18SEC_Msk                (0x1UL << RCC_SECCFGR2_IC18SEC_Pos)   /*!< 0x00020000 */
28992 #define RCC_SECCFGR2_IC18SEC                    RCC_SECCFGR2_IC18SEC_Msk             /*!< Secure protection of IC18 divider configuration bits */
28993 #define RCC_SECCFGR2_IC19SEC_Pos                (18U)
28994 #define RCC_SECCFGR2_IC19SEC_Msk                (0x1UL << RCC_SECCFGR2_IC19SEC_Pos)   /*!< 0x00040000 */
28995 #define RCC_SECCFGR2_IC19SEC                    RCC_SECCFGR2_IC19SEC_Msk             /*!< Secure protection of IC19 divider configuration bits */
28996 #define RCC_SECCFGR2_IC20SEC_Pos                (19U)
28997 #define RCC_SECCFGR2_IC20SEC_Msk                (0x1UL << RCC_SECCFGR2_IC20SEC_Pos)   /*!< 0x00080000 */
28998 #define RCC_SECCFGR2_IC20SEC                    RCC_SECCFGR2_IC20SEC_Msk             /*!< Secure protection of IC20 divider configuration bits */
28999 
29000 /****************  Bit definition for RCC_PRIVCFGR2 register  *****************/
29001 #define RCC_PRIVCFGR2_IC1PRIV_Pos               (0U)
29002 #define RCC_PRIVCFGR2_IC1PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC1PRIV_Pos)  /*!< 0x00000001 */
29003 #define RCC_PRIVCFGR2_IC1PRIV                   RCC_PRIVCFGR2_IC1PRIV_Msk            /*!< Privileged protection of IC1 divider configuration bits */
29004 #define RCC_PRIVCFGR2_IC2PRIV_Pos               (1U)
29005 #define RCC_PRIVCFGR2_IC2PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC2PRIV_Pos)  /*!< 0x00000002 */
29006 #define RCC_PRIVCFGR2_IC2PRIV                   RCC_PRIVCFGR2_IC2PRIV_Msk            /*!< Privileged protection of IC2 divider configuration bits */
29007 #define RCC_PRIVCFGR2_IC3PRIV_Pos               (2U)
29008 #define RCC_PRIVCFGR2_IC3PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC3PRIV_Pos)  /*!< 0x00000004 */
29009 #define RCC_PRIVCFGR2_IC3PRIV                   RCC_PRIVCFGR2_IC3PRIV_Msk            /*!< Privileged protection of IC3 divider configuration bits */
29010 #define RCC_PRIVCFGR2_IC4PRIV_Pos               (3U)
29011 #define RCC_PRIVCFGR2_IC4PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC4PRIV_Pos)  /*!< 0x00000008 */
29012 #define RCC_PRIVCFGR2_IC4PRIV                   RCC_PRIVCFGR2_IC4PRIV_Msk            /*!< Privileged protection of IC4 divider configuration bits */
29013 #define RCC_PRIVCFGR2_IC5PRIV_Pos               (4U)
29014 #define RCC_PRIVCFGR2_IC5PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC5PRIV_Pos)  /*!< 0x00000010 */
29015 #define RCC_PRIVCFGR2_IC5PRIV                   RCC_PRIVCFGR2_IC5PRIV_Msk            /*!< Privileged protection of IC5 divider configuration bits */
29016 #define RCC_PRIVCFGR2_IC6PRIV_Pos               (5U)
29017 #define RCC_PRIVCFGR2_IC6PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC6PRIV_Pos)  /*!< 0x00000020 */
29018 #define RCC_PRIVCFGR2_IC6PRIV                   RCC_PRIVCFGR2_IC6PRIV_Msk            /*!< Privileged protection of IC6 divider configuration bits */
29019 #define RCC_PRIVCFGR2_IC7PRIV_Pos               (6U)
29020 #define RCC_PRIVCFGR2_IC7PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC7PRIV_Pos)  /*!< 0x00000040 */
29021 #define RCC_PRIVCFGR2_IC7PRIV                   RCC_PRIVCFGR2_IC7PRIV_Msk            /*!< Privileged protection of IC7 divider configuration bits */
29022 #define RCC_PRIVCFGR2_IC8PRIV_Pos               (7U)
29023 #define RCC_PRIVCFGR2_IC8PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC8PRIV_Pos)  /*!< 0x00000080 */
29024 #define RCC_PRIVCFGR2_IC8PRIV                   RCC_PRIVCFGR2_IC8PRIV_Msk            /*!< Privileged protection of IC8 divider configuration bits */
29025 #define RCC_PRIVCFGR2_IC9PRIV_Pos               (8U)
29026 #define RCC_PRIVCFGR2_IC9PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC9PRIV_Pos)  /*!< 0x00000100 */
29027 #define RCC_PRIVCFGR2_IC9PRIV                   RCC_PRIVCFGR2_IC9PRIV_Msk            /*!< Privileged protection of IC9 divider configuration bits */
29028 #define RCC_PRIVCFGR2_IC10PRIV_Pos              (9U)
29029 #define RCC_PRIVCFGR2_IC10PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC10PRIV_Pos) /*!< 0x00000200 */
29030 #define RCC_PRIVCFGR2_IC10PRIV                  RCC_PRIVCFGR2_IC10PRIV_Msk           /*!< Privileged protection of IC10 divider configuration bits */
29031 #define RCC_PRIVCFGR2_IC11PRIV_Pos              (10U)
29032 #define RCC_PRIVCFGR2_IC11PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC11PRIV_Pos) /*!< 0x00000400 */
29033 #define RCC_PRIVCFGR2_IC11PRIV                  RCC_PRIVCFGR2_IC11PRIV_Msk           /*!< Privileged protection of IC11 divider configuration bits */
29034 #define RCC_PRIVCFGR2_IC12PRIV_Pos              (11U)
29035 #define RCC_PRIVCFGR2_IC12PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC12PRIV_Pos) /*!< 0x00000800 */
29036 #define RCC_PRIVCFGR2_IC12PRIV                  RCC_PRIVCFGR2_IC12PRIV_Msk           /*!< Privileged protection of IC12 divider configuration bits */
29037 #define RCC_PRIVCFGR2_IC13PRIV_Pos              (12U)
29038 #define RCC_PRIVCFGR2_IC13PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC13PRIV_Pos) /*!< 0x00001000 */
29039 #define RCC_PRIVCFGR2_IC13PRIV                  RCC_PRIVCFGR2_IC13PRIV_Msk           /*!< Privileged protection of IC13 divider configuration bits */
29040 #define RCC_PRIVCFGR2_IC14PRIV_Pos              (13U)
29041 #define RCC_PRIVCFGR2_IC14PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC14PRIV_Pos) /*!< 0x00002000 */
29042 #define RCC_PRIVCFGR2_IC14PRIV                  RCC_PRIVCFGR2_IC14PRIV_Msk           /*!< Privileged protection of IC14 divider configuration bits */
29043 #define RCC_PRIVCFGR2_IC15PRIV_Pos              (14U)
29044 #define RCC_PRIVCFGR2_IC15PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC15PRIV_Pos) /*!< 0x00004000 */
29045 #define RCC_PRIVCFGR2_IC15PRIV                  RCC_PRIVCFGR2_IC15PRIV_Msk           /*!< Privileged protection of IC15 divider configuration bits */
29046 #define RCC_PRIVCFGR2_IC16PRIV_Pos              (15U)
29047 #define RCC_PRIVCFGR2_IC16PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC16PRIV_Pos) /*!< 0x00008000 */
29048 #define RCC_PRIVCFGR2_IC16PRIV                  RCC_PRIVCFGR2_IC16PRIV_Msk           /*!< Privileged protection of IC16 divider configuration bits */
29049 #define RCC_PRIVCFGR2_IC17PRIV_Pos              (16U)
29050 #define RCC_PRIVCFGR2_IC17PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC17PRIV_Pos) /*!< 0x00010000 */
29051 #define RCC_PRIVCFGR2_IC17PRIV                  RCC_PRIVCFGR2_IC17PRIV_Msk           /*!< Privileges protection of IC17 divider configuration bits */
29052 #define RCC_PRIVCFGR2_IC18PRIV_Pos              (17U)
29053 #define RCC_PRIVCFGR2_IC18PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC18PRIV_Pos) /*!< 0x00020000 */
29054 #define RCC_PRIVCFGR2_IC18PRIV                  RCC_PRIVCFGR2_IC18PRIV_Msk           /*!< Privilege protection of IC18 divider configuration bits */
29055 #define RCC_PRIVCFGR2_IC19PRIV_Pos              (18U)
29056 #define RCC_PRIVCFGR2_IC19PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC19PRIV_Pos) /*!< 0x00040000 */
29057 #define RCC_PRIVCFGR2_IC19PRIV                  RCC_PRIVCFGR2_IC19PRIV_Msk           /*!< Privileged protection of IC19 divider configuration bits */
29058 #define RCC_PRIVCFGR2_IC20PRIV_Pos              (19U)
29059 #define RCC_PRIVCFGR2_IC20PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC20PRIV_Pos) /*!< 0x00080000 */
29060 #define RCC_PRIVCFGR2_IC20PRIV                  RCC_PRIVCFGR2_IC20PRIV_Msk           /*!< Privileged protection of IC20 divider configuration bits */
29061 
29062 /****************  Bit definition for RCC_LOCKCFGR2 register  *****************/
29063 #define RCC_LOCKCFGR2_IC1LOCK_Pos               (0U)
29064 #define RCC_LOCKCFGR2_IC1LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC1LOCK_Pos)  /*!< 0x00000001 */
29065 #define RCC_LOCKCFGR2_IC1LOCK                   RCC_LOCKCFGR2_IC1LOCK_Msk            /*!< Locked protection of IC1 divider configuration bits */
29066 #define RCC_LOCKCFGR2_IC2LOCK_Pos               (1U)
29067 #define RCC_LOCKCFGR2_IC2LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC2LOCK_Pos)  /*!< 0x00000002 */
29068 #define RCC_LOCKCFGR2_IC2LOCK                   RCC_LOCKCFGR2_IC2LOCK_Msk            /*!< Locked protection of IC2 divider configuration bits */
29069 #define RCC_LOCKCFGR2_IC3LOCK_Pos               (2U)
29070 #define RCC_LOCKCFGR2_IC3LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC3LOCK_Pos)  /*!< 0x00000004 */
29071 #define RCC_LOCKCFGR2_IC3LOCK                   RCC_LOCKCFGR2_IC3LOCK_Msk            /*!< Locked protection of IC3 divider configuration bits */
29072 #define RCC_LOCKCFGR2_IC4LOCK_Pos               (3U)
29073 #define RCC_LOCKCFGR2_IC4LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC4LOCK_Pos)  /*!< 0x00000008 */
29074 #define RCC_LOCKCFGR2_IC4LOCK                   RCC_LOCKCFGR2_IC4LOCK_Msk            /*!< Locked protection of IC4 divider configuration bits */
29075 #define RCC_LOCKCFGR2_IC5LOCK_Pos               (4U)
29076 #define RCC_LOCKCFGR2_IC5LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC5LOCK_Pos)  /*!< 0x00000010 */
29077 #define RCC_LOCKCFGR2_IC5LOCK                   RCC_LOCKCFGR2_IC5LOCK_Msk            /*!< Locked protection of IC5 divider configuration bits */
29078 #define RCC_LOCKCFGR2_IC6LOCK_Pos               (5U)
29079 #define RCC_LOCKCFGR2_IC6LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC6LOCK_Pos)  /*!< 0x00000020 */
29080 #define RCC_LOCKCFGR2_IC6LOCK                   RCC_LOCKCFGR2_IC6LOCK_Msk            /*!< Locked protection of IC6 divider configuration bits */
29081 #define RCC_LOCKCFGR2_IC7LOCK_Pos               (6U)
29082 #define RCC_LOCKCFGR2_IC7LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC7LOCK_Pos)  /*!< 0x00000040 */
29083 #define RCC_LOCKCFGR2_IC7LOCK                   RCC_LOCKCFGR2_IC7LOCK_Msk            /*!< Locked protection of IC7 divider configuration bits */
29084 #define RCC_LOCKCFGR2_IC8LOCK_Pos               (7U)
29085 #define RCC_LOCKCFGR2_IC8LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC8LOCK_Pos)  /*!< 0x00000080 */
29086 #define RCC_LOCKCFGR2_IC8LOCK                   RCC_LOCKCFGR2_IC8LOCK_Msk            /*!< Locked protection of IC8 divider configuration bits */
29087 #define RCC_LOCKCFGR2_IC9LOCK_Pos               (8U)
29088 #define RCC_LOCKCFGR2_IC9LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC9LOCK_Pos)  /*!< 0x00000100 */
29089 #define RCC_LOCKCFGR2_IC9LOCK                   RCC_LOCKCFGR2_IC9LOCK_Msk            /*!< Locked protection of IC9 divider configuration bits */
29090 #define RCC_LOCKCFGR2_IC10LOCK_Pos              (9U)
29091 #define RCC_LOCKCFGR2_IC10LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC10LOCK_Pos) /*!< 0x00000200 */
29092 #define RCC_LOCKCFGR2_IC10LOCK                  RCC_LOCKCFGR2_IC10LOCK_Msk           /*!< Locked protection of IC10 divider configuration bits */
29093 #define RCC_LOCKCFGR2_IC11LOCK_Pos              (10U)
29094 #define RCC_LOCKCFGR2_IC11LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC11LOCK_Pos) /*!< 0x00000400 */
29095 #define RCC_LOCKCFGR2_IC11LOCK                  RCC_LOCKCFGR2_IC11LOCK_Msk           /*!< Locked protection of IC11 divider configuration bits */
29096 #define RCC_LOCKCFGR2_IC12LOCK_Pos              (11U)
29097 #define RCC_LOCKCFGR2_IC12LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC12LOCK_Pos) /*!< 0x00000800 */
29098 #define RCC_LOCKCFGR2_IC12LOCK                  RCC_LOCKCFGR2_IC12LOCK_Msk           /*!< Locked protection of IC12 divider configuration bits */
29099 #define RCC_LOCKCFGR2_IC13LOCK_Pos              (12U)
29100 #define RCC_LOCKCFGR2_IC13LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC13LOCK_Pos) /*!< 0x00001000 */
29101 #define RCC_LOCKCFGR2_IC13LOCK                  RCC_LOCKCFGR2_IC13LOCK_Msk           /*!< Locked protection of IC13 divider configuration bits */
29102 #define RCC_LOCKCFGR2_IC14LOCK_Pos              (13U)
29103 #define RCC_LOCKCFGR2_IC14LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC14LOCK_Pos) /*!< 0x00002000 */
29104 #define RCC_LOCKCFGR2_IC14LOCK                  RCC_LOCKCFGR2_IC14LOCK_Msk           /*!< Locked protection of IC14 divider configuration bits */
29105 #define RCC_LOCKCFGR2_IC15LOCK_Pos              (14U)
29106 #define RCC_LOCKCFGR2_IC15LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC15LOCK_Pos) /*!< 0x00004000 */
29107 #define RCC_LOCKCFGR2_IC15LOCK                  RCC_LOCKCFGR2_IC15LOCK_Msk           /*!< Locked protection of IC15 divider configuration bits */
29108 #define RCC_LOCKCFGR2_IC16LOCK_Pos              (15U)
29109 #define RCC_LOCKCFGR2_IC16LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC16LOCK_Pos) /*!< 0x00008000 */
29110 #define RCC_LOCKCFGR2_IC16LOCK                  RCC_LOCKCFGR2_IC16LOCK_Msk           /*!< Locked protection of IC16 divider configuration bits */
29111 #define RCC_LOCKCFGR2_IC17LOCK_Pos              (16U)
29112 #define RCC_LOCKCFGR2_IC17LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC17LOCK_Pos) /*!< 0x00010000 */
29113 #define RCC_LOCKCFGR2_IC17LOCK                  RCC_LOCKCFGR2_IC17LOCK_Msk           /*!< Locked protection of IC17 divider configuration bits */
29114 #define RCC_LOCKCFGR2_IC18LOCK_Pos              (17U)
29115 #define RCC_LOCKCFGR2_IC18LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC18LOCK_Pos) /*!< 0x00020000 */
29116 #define RCC_LOCKCFGR2_IC18LOCK                  RCC_LOCKCFGR2_IC18LOCK_Msk           /*!< Locked protection of IC18 divider configuration bits */
29117 #define RCC_LOCKCFGR2_IC19LOCK_Pos              (18U)
29118 #define RCC_LOCKCFGR2_IC19LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC19LOCK_Pos) /*!< 0x00040000 */
29119 #define RCC_LOCKCFGR2_IC19LOCK                  RCC_LOCKCFGR2_IC19LOCK_Msk           /*!< Locked protection of IC19 divider configuration bits */
29120 #define RCC_LOCKCFGR2_IC20LOCK_Pos              (19U)
29121 #define RCC_LOCKCFGR2_IC20LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC20LOCK_Pos) /*!< 0x00080000 */
29122 #define RCC_LOCKCFGR2_IC20LOCK                  RCC_LOCKCFGR2_IC20LOCK_Msk           /*!< Locked protection of IC20 divider configuration bits */
29123 
29124 /*****************  Bit definition for RCC_PUBCFGR2 register  *****************/
29125 #define RCC_PUBCFGR2_IC1PUB_Pos                 (0U)
29126 #define RCC_PUBCFGR2_IC1PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC1PUB_Pos)    /*!< 0x00000001 */
29127 #define RCC_PUBCFGR2_IC1PUB                     RCC_PUBCFGR2_IC1PUB_Msk              /*!< Public protection of IC1 divider configuration bits */
29128 #define RCC_PUBCFGR2_IC2PUB_Pos                 (1U)
29129 #define RCC_PUBCFGR2_IC2PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC2PUB_Pos)    /*!< 0x00000002 */
29130 #define RCC_PUBCFGR2_IC2PUB                     RCC_PUBCFGR2_IC2PUB_Msk              /*!< Public protection of IC2 divider configuration bits */
29131 #define RCC_PUBCFGR2_IC3PUB_Pos                 (2U)
29132 #define RCC_PUBCFGR2_IC3PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC3PUB_Pos)    /*!< 0x00000004 */
29133 #define RCC_PUBCFGR2_IC3PUB                     RCC_PUBCFGR2_IC3PUB_Msk              /*!< Public protection of IC3 divider configuration bits */
29134 #define RCC_PUBCFGR2_IC4PUB_Pos                 (3U)
29135 #define RCC_PUBCFGR2_IC4PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC4PUB_Pos)    /*!< 0x00000008 */
29136 #define RCC_PUBCFGR2_IC4PUB                     RCC_PUBCFGR2_IC4PUB_Msk              /*!< Public protection of IC4 divider configuration bits */
29137 #define RCC_PUBCFGR2_IC5PUB_Pos                 (4U)
29138 #define RCC_PUBCFGR2_IC5PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC5PUB_Pos)    /*!< 0x00000010 */
29139 #define RCC_PUBCFGR2_IC5PUB                     RCC_PUBCFGR2_IC5PUB_Msk              /*!< Public protection of IC5 divider configuration bits */
29140 #define RCC_PUBCFGR2_IC6PUB_Pos                 (5U)
29141 #define RCC_PUBCFGR2_IC6PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC6PUB_Pos)    /*!< 0x00000020 */
29142 #define RCC_PUBCFGR2_IC6PUB                     RCC_PUBCFGR2_IC6PUB_Msk              /*!< Public protection of IC6 divider configuration bits */
29143 #define RCC_PUBCFGR2_IC7PUB_Pos                 (6U)
29144 #define RCC_PUBCFGR2_IC7PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC7PUB_Pos)    /*!< 0x00000040 */
29145 #define RCC_PUBCFGR2_IC7PUB                     RCC_PUBCFGR2_IC7PUB_Msk              /*!< Public protection of IC7 divider configuration bits */
29146 #define RCC_PUBCFGR2_IC8PUB_Pos                 (7U)
29147 #define RCC_PUBCFGR2_IC8PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC8PUB_Pos)    /*!< 0x00000080 */
29148 #define RCC_PUBCFGR2_IC8PUB                     RCC_PUBCFGR2_IC8PUB_Msk              /*!< Public protection of IC8 divider configuration bits */
29149 #define RCC_PUBCFGR2_IC9PUB_Pos                 (8U)
29150 #define RCC_PUBCFGR2_IC9PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC9PUB_Pos)    /*!< 0x00000100 */
29151 #define RCC_PUBCFGR2_IC9PUB                     RCC_PUBCFGR2_IC9PUB_Msk              /*!< Public protection of IC9 divider configuration bits */
29152 #define RCC_PUBCFGR2_IC10PUB_Pos                (9U)
29153 #define RCC_PUBCFGR2_IC10PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC10PUB_Pos)   /*!< 0x00000200 */
29154 #define RCC_PUBCFGR2_IC10PUB                    RCC_PUBCFGR2_IC10PUB_Msk             /*!< Public protection of IC10 divider configuration bits */
29155 #define RCC_PUBCFGR2_IC11PUB_Pos                (10U)
29156 #define RCC_PUBCFGR2_IC11PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC11PUB_Pos)   /*!< 0x00000400 */
29157 #define RCC_PUBCFGR2_IC11PUB                    RCC_PUBCFGR2_IC11PUB_Msk             /*!< Public protection of IC11 divider configuration bits */
29158 #define RCC_PUBCFGR2_IC12PUB_Pos                (11U)
29159 #define RCC_PUBCFGR2_IC12PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC12PUB_Pos)   /*!< 0x00000800 */
29160 #define RCC_PUBCFGR2_IC12PUB                    RCC_PUBCFGR2_IC12PUB_Msk             /*!< Public protection of IC12 divider configuration bits */
29161 #define RCC_PUBCFGR2_IC13PUB_Pos                (12U)
29162 #define RCC_PUBCFGR2_IC13PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC13PUB_Pos)   /*!< 0x00001000 */
29163 #define RCC_PUBCFGR2_IC13PUB                    RCC_PUBCFGR2_IC13PUB_Msk             /*!< Public protection of IC13 divider configuration bits */
29164 #define RCC_PUBCFGR2_IC14PUB_Pos                (13U)
29165 #define RCC_PUBCFGR2_IC14PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC14PUB_Pos)   /*!< 0x00002000 */
29166 #define RCC_PUBCFGR2_IC14PUB                    RCC_PUBCFGR2_IC14PUB_Msk             /*!< Public protection of IC14 divider configuration bits */
29167 #define RCC_PUBCFGR2_IC15PUB_Pos                (14U)
29168 #define RCC_PUBCFGR2_IC15PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC15PUB_Pos)   /*!< 0x00004000 */
29169 #define RCC_PUBCFGR2_IC15PUB                    RCC_PUBCFGR2_IC15PUB_Msk             /*!< Public protection of IC15 divider configuration bits */
29170 #define RCC_PUBCFGR2_IC16PUB_Pos                (15U)
29171 #define RCC_PUBCFGR2_IC16PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC16PUB_Pos)   /*!< 0x00008000 */
29172 #define RCC_PUBCFGR2_IC16PUB                    RCC_PUBCFGR2_IC16PUB_Msk             /*!< Public protection of IC16 divider configuration bits */
29173 #define RCC_PUBCFGR2_IC17PUB_Pos                (16U)
29174 #define RCC_PUBCFGR2_IC17PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC17PUB_Pos)   /*!< 0x00010000 */
29175 #define RCC_PUBCFGR2_IC17PUB                    RCC_PUBCFGR2_IC17PUB_Msk             /*!< Public protection of IC17 divider configuration bits */
29176 #define RCC_PUBCFGR2_IC18PUB_Pos                (17U)
29177 #define RCC_PUBCFGR2_IC18PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC18PUB_Pos)   /*!< 0x00020000 */
29178 #define RCC_PUBCFGR2_IC18PUB                    RCC_PUBCFGR2_IC18PUB_Msk             /*!< Public protection of IC18 divider configuration bits */
29179 #define RCC_PUBCFGR2_IC19PUB_Pos                (18U)
29180 #define RCC_PUBCFGR2_IC19PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC19PUB_Pos)   /*!< 0x00040000 */
29181 #define RCC_PUBCFGR2_IC19PUB                    RCC_PUBCFGR2_IC19PUB_Msk             /*!< Public protection of IC19 divider configuration bits */
29182 #define RCC_PUBCFGR2_IC20PUB_Pos                (19U)
29183 #define RCC_PUBCFGR2_IC20PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC20PUB_Pos)   /*!< 0x00080000 */
29184 #define RCC_PUBCFGR2_IC20PUB                    RCC_PUBCFGR2_IC20PUB_Msk             /*!< Public protection of IC20 divider configuration bits */
29185 
29186 /*****************  Bit definition for RCC_SECCFGR3 register  *****************/
29187 #define RCC_SECCFGR3_MODSEC_Pos                 (0U)
29188 #define RCC_SECCFGR3_MODSEC_Msk                 (0x1UL << RCC_SECCFGR3_MODSEC_Pos)    /*!< 0x00000001 */
29189 #define RCC_SECCFGR3_MODSEC                     RCC_SECCFGR3_MODSEC_Msk              /*!< Secure protection of MOD system configuration bits */
29190 #define RCC_SECCFGR3_SYSSEC_Pos                 (1U)
29191 #define RCC_SECCFGR3_SYSSEC_Msk                 (0x1UL << RCC_SECCFGR3_SYSSEC_Pos)    /*!< 0x00000002 */
29192 #define RCC_SECCFGR3_SYSSEC                     RCC_SECCFGR3_SYSSEC_Msk              /*!< Secure protection of SYS system configuration bit */
29193 #define RCC_SECCFGR3_BUSSEC_Pos                 (2U)
29194 #define RCC_SECCFGR3_BUSSEC_Msk                 (0x1UL << RCC_SECCFGR3_BUSSEC_Pos)    /*!< 0x00000004 */
29195 #define RCC_SECCFGR3_BUSSEC                     RCC_SECCFGR3_BUSSEC_Msk              /*!< Secure protection of BUS system configuration bits */
29196 #define RCC_SECCFGR3_PERSEC_Pos                 (3U)
29197 #define RCC_SECCFGR3_PERSEC_Msk                 (0x1UL << RCC_SECCFGR3_PERSEC_Pos)    /*!< 0x00000008 */
29198 #define RCC_SECCFGR3_PERSEC                     RCC_SECCFGR3_PERSEC_Msk              /*!< Secure protection of PER system configuration bits */
29199 #define RCC_SECCFGR3_INTSEC_Pos                 (4U)
29200 #define RCC_SECCFGR3_INTSEC_Msk                 (0x1UL << RCC_SECCFGR3_INTSEC_Pos)    /*!< 0x00000010 */
29201 #define RCC_SECCFGR3_INTSEC                     RCC_SECCFGR3_INTSEC_Msk              /*!< Secure protection of INT system configuration bits */
29202 #define RCC_SECCFGR3_RSTSEC_Pos                 (5U)
29203 #define RCC_SECCFGR3_RSTSEC_Msk                 (0x1UL << RCC_SECCFGR3_RSTSEC_Pos)    /*!< 0x00000020 */
29204 #define RCC_SECCFGR3_RSTSEC                     RCC_SECCFGR3_RSTSEC_Msk              /*!< Secure protection of RST system configuration bits */
29205 
29206 /****************  Bit definition for RCC_PRIVCFGR3 register  *****************/
29207 #define RCC_PRIVCFGR3_MODPRIV_Pos               (0U)
29208 #define RCC_PRIVCFGR3_MODPRIV_Msk               (0x1UL << RCC_PRIVCFGR3_MODPRIV_Pos)  /*!< 0x00000001 */
29209 #define RCC_PRIVCFGR3_MODPRIV                   RCC_PRIVCFGR3_MODPRIV_Msk            /*!< Privileged protection of MOD system configuration bits */
29210 #define RCC_PRIVCFGR3_SYSPRIV_Pos               (1U)
29211 #define RCC_PRIVCFGR3_SYSPRIV_Msk               (0x1UL << RCC_PRIVCFGR3_SYSPRIV_Pos)  /*!< 0x00000002 */
29212 #define RCC_PRIVCFGR3_SYSPRIV                   RCC_PRIVCFGR3_SYSPRIV_Msk            /*!< Privileged protection of SYS system configuration bits */
29213 #define RCC_PRIVCFGR3_BUSPRIV_Pos               (2U)
29214 #define RCC_PRIVCFGR3_BUSPRIV_Msk               (0x1UL << RCC_PRIVCFGR3_BUSPRIV_Pos)  /*!< 0x00000004 */
29215 #define RCC_PRIVCFGR3_BUSPRIV                   RCC_PRIVCFGR3_BUSPRIV_Msk            /*!< Privileged protection of BUS system configuration bits */
29216 #define RCC_PRIVCFGR3_PERPRIV_Pos               (3U)
29217 #define RCC_PRIVCFGR3_PERPRIV_Msk               (0x1UL << RCC_PRIVCFGR3_PERPRIV_Pos)  /*!< 0x00000008 */
29218 #define RCC_PRIVCFGR3_PERPRIV                   RCC_PRIVCFGR3_PERPRIV_Msk            /*!< Privileged protection of PER system configuration bits */
29219 #define RCC_PRIVCFGR3_INTPRIV_Pos               (4U)
29220 #define RCC_PRIVCFGR3_INTPRIV_Msk               (0x1UL << RCC_PRIVCFGR3_INTPRIV_Pos)  /*!< 0x00000010 */
29221 #define RCC_PRIVCFGR3_INTPRIV                   RCC_PRIVCFGR3_INTPRIV_Msk            /*!< Privileged protection of INT system configuration bits */
29222 #define RCC_PRIVCFGR3_RSTPRIV_Pos               (5U)
29223 #define RCC_PRIVCFGR3_RSTPRIV_Msk               (0x1UL << RCC_PRIVCFGR3_RSTPRIV_Pos)  /*!< 0x00000020 */
29224 #define RCC_PRIVCFGR3_RSTPRIV                   RCC_PRIVCFGR3_RSTPRIV_Msk            /*!< Privileged protection of RST system configuration bits */
29225 
29226 /****************  Bit definition for RCC_LOCKCFGR3 register  *****************/
29227 #define RCC_LOCKCFGR3_MODLOCK_Pos               (0U)
29228 #define RCC_LOCKCFGR3_MODLOCK_Msk               (0x1UL << RCC_LOCKCFGR3_MODLOCK_Pos)  /*!< 0x00000001 */
29229 #define RCC_LOCKCFGR3_MODLOCK                   RCC_LOCKCFGR3_MODLOCK_Msk            /*!< Locked protection of MOD system configuration bits */
29230 #define RCC_LOCKCFGR3_SYSLOCK_Pos               (1U)
29231 #define RCC_LOCKCFGR3_SYSLOCK_Msk               (0x1UL << RCC_LOCKCFGR3_SYSLOCK_Pos)  /*!< 0x00000002 */
29232 #define RCC_LOCKCFGR3_SYSLOCK                   RCC_LOCKCFGR3_SYSLOCK_Msk            /*!< Locked protection of SYS system configuration bits */
29233 #define RCC_LOCKCFGR3_BUSLOCK_Pos               (2U)
29234 #define RCC_LOCKCFGR3_BUSLOCK_Msk               (0x1UL << RCC_LOCKCFGR3_BUSLOCK_Pos)  /*!< 0x00000004 */
29235 #define RCC_LOCKCFGR3_BUSLOCK                   RCC_LOCKCFGR3_BUSLOCK_Msk            /*!< Locked protection of BUS system configuration bits */
29236 #define RCC_LOCKCFGR3_PERLOCK_Pos               (3U)
29237 #define RCC_LOCKCFGR3_PERLOCK_Msk               (0x1UL << RCC_LOCKCFGR3_PERLOCK_Pos)  /*!< 0x00000008 */
29238 #define RCC_LOCKCFGR3_PERLOCK                   RCC_LOCKCFGR3_PERLOCK_Msk            /*!< Locked protection of PER system configuration bits */
29239 #define RCC_LOCKCFGR3_INTLOCK_Pos               (4U)
29240 #define RCC_LOCKCFGR3_INTLOCK_Msk               (0x1UL << RCC_LOCKCFGR3_INTLOCK_Pos)  /*!< 0x00000010 */
29241 #define RCC_LOCKCFGR3_INTLOCK                   RCC_LOCKCFGR3_INTLOCK_Msk            /*!< Locked protection of INT system configuration bits */
29242 #define RCC_LOCKCFGR3_RSTLOCK_Pos               (5U)
29243 #define RCC_LOCKCFGR3_RSTLOCK_Msk               (0x1UL << RCC_LOCKCFGR3_RSTLOCK_Pos)  /*!< 0x00000020 */
29244 #define RCC_LOCKCFGR3_RSTLOCK                   RCC_LOCKCFGR3_RSTLOCK_Msk            /*!< Locked protection of RST system configuration bits */
29245 
29246 /*****************  Bit definition for RCC_PUBCFGR3 register  *****************/
29247 #define RCC_PUBCFGR3_MODPUB_Pos                 (0U)
29248 #define RCC_PUBCFGR3_MODPUB_Msk                 (0x1UL << RCC_PUBCFGR3_MODPUB_Pos)    /*!< 0x00000001 */
29249 #define RCC_PUBCFGR3_MODPUB                     RCC_PUBCFGR3_MODPUB_Msk              /*!< Public protection of MOD system configuration bits */
29250 #define RCC_PUBCFGR3_SYSPUB_Pos                 (1U)
29251 #define RCC_PUBCFGR3_SYSPUB_Msk                 (0x1UL << RCC_PUBCFGR3_SYSPUB_Pos)    /*!< 0x00000002 */
29252 #define RCC_PUBCFGR3_SYSPUB                     RCC_PUBCFGR3_SYSPUB_Msk              /*!< Public protection of SYS system configuration bits */
29253 #define RCC_PUBCFGR3_BUSPUB_Pos                 (2U)
29254 #define RCC_PUBCFGR3_BUSPUB_Msk                 (0x1UL << RCC_PUBCFGR3_BUSPUB_Pos)    /*!< 0x00000004 */
29255 #define RCC_PUBCFGR3_BUSPUB                     RCC_PUBCFGR3_BUSPUB_Msk              /*!< Public protection of BUS system configuration bits */
29256 #define RCC_PUBCFGR3_PERPUB_Pos                 (3U)
29257 #define RCC_PUBCFGR3_PERPUB_Msk                 (0x1UL << RCC_PUBCFGR3_PERPUB_Pos)    /*!< 0x00000008 */
29258 #define RCC_PUBCFGR3_PERPUB                     RCC_PUBCFGR3_PERPUB_Msk              /*!< Public protection of PER system configuration bits */
29259 #define RCC_PUBCFGR3_INTPUB_Pos                 (4U)
29260 #define RCC_PUBCFGR3_INTPUB_Msk                 (0x1UL << RCC_PUBCFGR3_INTPUB_Pos)    /*!< 0x00000010 */
29261 #define RCC_PUBCFGR3_INTPUB                     RCC_PUBCFGR3_INTPUB_Msk              /*!< Public protection of INT system configuration bits */
29262 #define RCC_PUBCFGR3_RSTPUB_Pos                 (5U)
29263 #define RCC_PUBCFGR3_RSTPUB_Msk                 (0x1UL << RCC_PUBCFGR3_RSTPUB_Pos)    /*!< 0x00000020 */
29264 #define RCC_PUBCFGR3_RSTPUB                     RCC_PUBCFGR3_RSTPUB_Msk              /*!< Public protection of RST system configuration bits */
29265 
29266 /*****************  Bit definition for RCC_SECCFGR4 register  *****************/
29267 #define RCC_SECCFGR4_ACLKNSEC_Pos               (0U)
29268 #define RCC_SECCFGR4_ACLKNSEC_Msk               (0x1UL << RCC_SECCFGR4_ACLKNSEC_Pos)  /*!< 0x00000001 */
29269 #define RCC_SECCFGR4_ACLKNSEC                   RCC_SECCFGR4_ACLKNSEC_Msk            /*!< Secure protection of ACLKN bus configuration bits */
29270 #define RCC_SECCFGR4_ACLKNCSEC_Pos              (1U)
29271 #define RCC_SECCFGR4_ACLKNCSEC_Msk              (0x1UL << RCC_SECCFGR4_ACLKNCSEC_Pos) /*!< 0x00000002 */
29272 #define RCC_SECCFGR4_ACLKNCSEC                  RCC_SECCFGR4_ACLKNCSEC_Msk           /*!< Secure protection of ACLKNC bus configuration bits */
29273 #define RCC_SECCFGR4_AHBMSEC_Pos                (2U)
29274 #define RCC_SECCFGR4_AHBMSEC_Msk                (0x1UL << RCC_SECCFGR4_AHBMSEC_Pos)   /*!< 0x00000004 */
29275 #define RCC_SECCFGR4_AHBMSEC                    RCC_SECCFGR4_AHBMSEC_Msk             /*!< Secure protection of AHBM bus configuration bits */
29276 #define RCC_SECCFGR4_AHB1SEC_Pos                (3U)
29277 #define RCC_SECCFGR4_AHB1SEC_Msk                (0x1UL << RCC_SECCFGR4_AHB1SEC_Pos)   /*!< 0x00000008 */
29278 #define RCC_SECCFGR4_AHB1SEC                    RCC_SECCFGR4_AHB1SEC_Msk             /*!< Secure protection of AHB1 bus configuration bits */
29279 #define RCC_SECCFGR4_AHB2SEC_Pos                (4U)
29280 #define RCC_SECCFGR4_AHB2SEC_Msk                (0x1UL << RCC_SECCFGR4_AHB2SEC_Pos)   /*!< 0x00000010 */
29281 #define RCC_SECCFGR4_AHB2SEC                    RCC_SECCFGR4_AHB2SEC_Msk             /*!< Secure protection of AHB2 bus configuration bits */
29282 #define RCC_SECCFGR4_AHB3SEC_Pos                (5U)
29283 #define RCC_SECCFGR4_AHB3SEC_Msk                (0x1UL << RCC_SECCFGR4_AHB3SEC_Pos)   /*!< 0x00000020 */
29284 #define RCC_SECCFGR4_AHB3SEC                    RCC_SECCFGR4_AHB3SEC_Msk             /*!< Secure protection of AHB3 bus configuration bits */
29285 #define RCC_SECCFGR4_AHB4SEC_Pos                (6U)
29286 #define RCC_SECCFGR4_AHB4SEC_Msk                (0x1UL << RCC_SECCFGR4_AHB4SEC_Pos)   /*!< 0x00000040 */
29287 #define RCC_SECCFGR4_AHB4SEC                    RCC_SECCFGR4_AHB4SEC_Msk             /*!< Secure protection of AHB4 bus configuration bits */
29288 #define RCC_SECCFGR4_AHB5SEC_Pos                (7U)
29289 #define RCC_SECCFGR4_AHB5SEC_Msk                (0x1UL << RCC_SECCFGR4_AHB5SEC_Pos)   /*!< 0x00000080 */
29290 #define RCC_SECCFGR4_AHB5SEC                    RCC_SECCFGR4_AHB5SEC_Msk             /*!< Secure protection of AHB5 bus configuration bits */
29291 #define RCC_SECCFGR4_APB1SEC_Pos                (8U)
29292 #define RCC_SECCFGR4_APB1SEC_Msk                (0x1UL << RCC_SECCFGR4_APB1SEC_Pos)   /*!< 0x00000100 */
29293 #define RCC_SECCFGR4_APB1SEC                    RCC_SECCFGR4_APB1SEC_Msk             /*!< Secure protection of APB1 bus configuration bits */
29294 #define RCC_SECCFGR4_APB2SEC_Pos                (9U)
29295 #define RCC_SECCFGR4_APB2SEC_Msk                (0x1UL << RCC_SECCFGR4_APB2SEC_Pos)   /*!< 0x00000200 */
29296 #define RCC_SECCFGR4_APB2SEC                    RCC_SECCFGR4_APB2SEC_Msk             /*!< Secure protection of APB2 bus configuration bits */
29297 #define RCC_SECCFGR4_APB3SEC_Pos                (10U)
29298 #define RCC_SECCFGR4_APB3SEC_Msk                (0x1UL << RCC_SECCFGR4_APB3SEC_Pos)   /*!< 0x00000400 */
29299 #define RCC_SECCFGR4_APB3SEC                    RCC_SECCFGR4_APB3SEC_Msk             /*!< Secure protection of APB3 bus configuration bits */
29300 #define RCC_SECCFGR4_APB4SEC_Pos                (11U)
29301 #define RCC_SECCFGR4_APB4SEC_Msk                (0x1UL << RCC_SECCFGR4_APB4SEC_Pos)   /*!< 0x00000800 */
29302 #define RCC_SECCFGR4_APB4SEC                    RCC_SECCFGR4_APB4SEC_Msk             /*!< Secure protection of APB4 bus configuration bits */
29303 #define RCC_SECCFGR4_APB5SEC_Pos                (12U)
29304 #define RCC_SECCFGR4_APB5SEC_Msk                (0x1UL << RCC_SECCFGR4_APB5SEC_Pos)   /*!< 0x00001000 */
29305 #define RCC_SECCFGR4_APB5SEC                    RCC_SECCFGR4_APB5SEC_Msk             /*!< Secure protection of APB5 bus configuration bits */
29306 #define RCC_SECCFGR4_NOCSEC_Pos                 (13U)
29307 #define RCC_SECCFGR4_NOCSEC_Msk                 (0x1UL << RCC_SECCFGR4_NOCSEC_Pos)    /*!< 0x00002000 */
29308 #define RCC_SECCFGR4_NOCSEC                     RCC_SECCFGR4_NOCSEC_Msk              /*!< Secure protection of NOC bus configuration bits */
29309 
29310 /****************  Bit definition for RCC_PRIVCFGR4 register  *****************/
29311 #define RCC_PRIVCFGR4_ACLKNPRIV_Pos             (0U)
29312 #define RCC_PRIVCFGR4_ACLKNPRIV_Msk             (0x1UL << RCC_PRIVCFGR4_ACLKNPRIV_Pos)/*!< 0x00000001 */
29313 #define RCC_PRIVCFGR4_ACLKNPRIV                 RCC_PRIVCFGR4_ACLKNPRIV_Msk          /*!< Privileged protection of ACLKN bus configuration bits */
29314 #define RCC_PRIVCFGR4_ACLKNCPRIV_Pos            (1U)
29315 #define RCC_PRIVCFGR4_ACLKNCPRIV_Msk            (0x1UL << RCC_PRIVCFGR4_ACLKNCPRIV_Pos) /*!< 0x00000002 */
29316 #define RCC_PRIVCFGR4_ACLKNCPRIV                RCC_PRIVCFGR4_ACLKNCPRIV_Msk         /*!< Privileged protection of ACLKNC bus configuration bits */
29317 #define RCC_PRIVCFGR4_AHBMPRIV_Pos              (2U)
29318 #define RCC_PRIVCFGR4_AHBMPRIV_Msk              (0x1UL << RCC_PRIVCFGR4_AHBMPRIV_Pos) /*!< 0x00000004 */
29319 #define RCC_PRIVCFGR4_AHBMPRIV                  RCC_PRIVCFGR4_AHBMPRIV_Msk           /*!< Privileged protection of AHBM bus configuration bits */
29320 #define RCC_PRIVCFGR4_AHB1PRIV_Pos              (3U)
29321 #define RCC_PRIVCFGR4_AHB1PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_AHB1PRIV_Pos) /*!< 0x00000008 */
29322 #define RCC_PRIVCFGR4_AHB1PRIV                  RCC_PRIVCFGR4_AHB1PRIV_Msk           /*!< Privileged protection of AHB1 bus configuration bits */
29323 #define RCC_PRIVCFGR4_AHB2PRIV_Pos              (4U)
29324 #define RCC_PRIVCFGR4_AHB2PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_AHB2PRIV_Pos) /*!< 0x00000010 */
29325 #define RCC_PRIVCFGR4_AHB2PRIV                  RCC_PRIVCFGR4_AHB2PRIV_Msk           /*!< Privileged protection of AHB2 bus configuration bits */
29326 #define RCC_PRIVCFGR4_AHB3PRIV_Pos              (5U)
29327 #define RCC_PRIVCFGR4_AHB3PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_AHB3PRIV_Pos) /*!< 0x00000020 */
29328 #define RCC_PRIVCFGR4_AHB3PRIV                  RCC_PRIVCFGR4_AHB3PRIV_Msk           /*!< Privileged protection of AHB3 bus configuration bits */
29329 #define RCC_PRIVCFGR4_AHB4PRIV_Pos              (6U)
29330 #define RCC_PRIVCFGR4_AHB4PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_AHB4PRIV_Pos) /*!< 0x00000040 */
29331 #define RCC_PRIVCFGR4_AHB4PRIV                  RCC_PRIVCFGR4_AHB4PRIV_Msk           /*!< Privileged protection of AHB4 bus configuration bits */
29332 #define RCC_PRIVCFGR4_AHB5PRIV_Pos              (7U)
29333 #define RCC_PRIVCFGR4_AHB5PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_AHB5PRIV_Pos) /*!< 0x00000080 */
29334 #define RCC_PRIVCFGR4_AHB5PRIV                  RCC_PRIVCFGR4_AHB5PRIV_Msk           /*!< Privileged protection of AHB5 bus configuration bits */
29335 #define RCC_PRIVCFGR4_APB1PRIV_Pos              (8U)
29336 #define RCC_PRIVCFGR4_APB1PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_APB1PRIV_Pos) /*!< 0x00000100 */
29337 #define RCC_PRIVCFGR4_APB1PRIV                  RCC_PRIVCFGR4_APB1PRIV_Msk           /*!< Privileged protection of APB1 bus configuration bits */
29338 #define RCC_PRIVCFGR4_APB2PRIV_Pos              (9U)
29339 #define RCC_PRIVCFGR4_APB2PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_APB2PRIV_Pos) /*!< 0x00000200 */
29340 #define RCC_PRIVCFGR4_APB2PRIV                  RCC_PRIVCFGR4_APB2PRIV_Msk           /*!< Privileged protection of APB2 bus configuration bits */
29341 #define RCC_PRIVCFGR4_APB3PRIV_Pos              (10U)
29342 #define RCC_PRIVCFGR4_APB3PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_APB3PRIV_Pos) /*!< 0x00000400 */
29343 #define RCC_PRIVCFGR4_APB3PRIV                  RCC_PRIVCFGR4_APB3PRIV_Msk           /*!< Privileged protection of APB3 bus configuration bits */
29344 #define RCC_PRIVCFGR4_APB4PRIV_Pos              (11U)
29345 #define RCC_PRIVCFGR4_APB4PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_APB4PRIV_Pos) /*!< 0x00000800 */
29346 #define RCC_PRIVCFGR4_APB4PRIV                  RCC_PRIVCFGR4_APB4PRIV_Msk           /*!< Privileged protection of APB4 bus configuration bits */
29347 #define RCC_PRIVCFGR4_APB5PRIV_Pos              (12U)
29348 #define RCC_PRIVCFGR4_APB5PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_APB5PRIV_Pos) /*!< 0x00001000 */
29349 #define RCC_PRIVCFGR4_APB5PRIV                  RCC_PRIVCFGR4_APB5PRIV_Msk           /*!< Privileged protection of APB5 bus configuration bits */
29350 #define RCC_PRIVCFGR4_NOCPRIV_Pos               (13U)
29351 #define RCC_PRIVCFGR4_NOCPRIV_Msk               (0x1UL << RCC_PRIVCFGR4_NOCPRIV_Pos)  /*!< 0x00002000 */
29352 #define RCC_PRIVCFGR4_NOCPRIV                   RCC_PRIVCFGR4_NOCPRIV_Msk            /*!< Privileged protection of NOC bus configuration bits */
29353 
29354 /****************  Bit definition for RCC_LOCKCFGR4 register  *****************/
29355 #define RCC_LOCKCFGR4_ACLKNLOCK_Pos             (0U)
29356 #define RCC_LOCKCFGR4_ACLKNLOCK_Msk             (0x1UL << RCC_LOCKCFGR4_ACLKNLOCK_Pos)/*!< 0x00000001 */
29357 #define RCC_LOCKCFGR4_ACLKNLOCK                 RCC_LOCKCFGR4_ACLKNLOCK_Msk          /*!< Locked protection of ACLKN bus configuration bits */
29358 #define RCC_LOCKCFGR4_ACLKNCLOCK_Pos            (1U)
29359 #define RCC_LOCKCFGR4_ACLKNCLOCK_Msk            (0x1UL << RCC_LOCKCFGR4_ACLKNCLOCK_Pos) /*!< 0x00000002 */
29360 #define RCC_LOCKCFGR4_ACLKNCLOCK                RCC_LOCKCFGR4_ACLKNCLOCK_Msk         /*!< Locked protection of ACLKNC bus configuration bits */
29361 #define RCC_LOCKCFGR4_AHBMLOCK_Pos              (2U)
29362 #define RCC_LOCKCFGR4_AHBMLOCK_Msk              (0x1UL << RCC_LOCKCFGR4_AHBMLOCK_Pos) /*!< 0x00000004 */
29363 #define RCC_LOCKCFGR4_AHBMLOCK                  RCC_LOCKCFGR4_AHBMLOCK_Msk           /*!< Locked protection of AHBM bus configuration bits */
29364 #define RCC_LOCKCFGR4_AHB1LOCK_Pos              (3U)
29365 #define RCC_LOCKCFGR4_AHB1LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_AHB1LOCK_Pos) /*!< 0x00000008 */
29366 #define RCC_LOCKCFGR4_AHB1LOCK                  RCC_LOCKCFGR4_AHB1LOCK_Msk           /*!< Locked protection of AHB1 bus configuration bits */
29367 #define RCC_LOCKCFGR4_AHB2LOCK_Pos              (4U)
29368 #define RCC_LOCKCFGR4_AHB2LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_AHB2LOCK_Pos) /*!< 0x00000010 */
29369 #define RCC_LOCKCFGR4_AHB2LOCK                  RCC_LOCKCFGR4_AHB2LOCK_Msk           /*!< Locked protection of AHB2 bus configuration bits */
29370 #define RCC_LOCKCFGR4_AHB3LOCK_Pos              (5U)
29371 #define RCC_LOCKCFGR4_AHB3LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_AHB3LOCK_Pos) /*!< 0x00000020 */
29372 #define RCC_LOCKCFGR4_AHB3LOCK                  RCC_LOCKCFGR4_AHB3LOCK_Msk           /*!< Locked protection of AHB3 bus configuration bits */
29373 #define RCC_LOCKCFGR4_AHB4LOCK_Pos              (6U)
29374 #define RCC_LOCKCFGR4_AHB4LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_AHB4LOCK_Pos) /*!< 0x00000040 */
29375 #define RCC_LOCKCFGR4_AHB4LOCK                  RCC_LOCKCFGR4_AHB4LOCK_Msk           /*!< Locked protection of AHB4 bus configuration bits */
29376 #define RCC_LOCKCFGR4_AHB5LOCK_Pos              (7U)
29377 #define RCC_LOCKCFGR4_AHB5LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_AHB5LOCK_Pos) /*!< 0x00000080 */
29378 #define RCC_LOCKCFGR4_AHB5LOCK                  RCC_LOCKCFGR4_AHB5LOCK_Msk           /*!< Locked protection of AHB5 bus configuration bits */
29379 #define RCC_LOCKCFGR4_APB1LOCK_Pos              (8U)
29380 #define RCC_LOCKCFGR4_APB1LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_APB1LOCK_Pos) /*!< 0x00000100 */
29381 #define RCC_LOCKCFGR4_APB1LOCK                  RCC_LOCKCFGR4_APB1LOCK_Msk           /*!< Locked protection of APB1 bus configuration bits */
29382 #define RCC_LOCKCFGR4_APB2LOCK_Pos              (9U)
29383 #define RCC_LOCKCFGR4_APB2LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_APB2LOCK_Pos) /*!< 0x00000200 */
29384 #define RCC_LOCKCFGR4_APB2LOCK                  RCC_LOCKCFGR4_APB2LOCK_Msk           /*!< Locked protection of APB2 bus configuration bits */
29385 #define RCC_LOCKCFGR4_APB3LOCK_Pos              (10U)
29386 #define RCC_LOCKCFGR4_APB3LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_APB3LOCK_Pos) /*!< 0x00000400 */
29387 #define RCC_LOCKCFGR4_APB3LOCK                  RCC_LOCKCFGR4_APB3LOCK_Msk           /*!< Locked protection of APB3 bus configuration bits */
29388 #define RCC_LOCKCFGR4_APB4LOCK_Pos              (11U)
29389 #define RCC_LOCKCFGR4_APB4LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_APB4LOCK_Pos) /*!< 0x00000800 */
29390 #define RCC_LOCKCFGR4_APB4LOCK                  RCC_LOCKCFGR4_APB4LOCK_Msk           /*!< Locked protection of APB4 bus configuration bits */
29391 #define RCC_LOCKCFGR4_APB5LOCK_Pos              (12U)
29392 #define RCC_LOCKCFGR4_APB5LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_APB5LOCK_Pos) /*!< 0x00001000 */
29393 #define RCC_LOCKCFGR4_APB5LOCK                  RCC_LOCKCFGR4_APB5LOCK_Msk           /*!< Locked protection of APB5 bus configuration bits */
29394 #define RCC_LOCKCFGR4_NOCLOCK_Pos               (13U)
29395 #define RCC_LOCKCFGR4_NOCLOCK_Msk               (0x1UL << RCC_LOCKCFGR4_NOCLOCK_Pos)  /*!< 0x00002000 */
29396 #define RCC_LOCKCFGR4_NOCLOCK                   RCC_LOCKCFGR4_NOCLOCK_Msk            /*!< Locked protection of NOC bus configuration bits */
29397 
29398 /*****************  Bit definition for RCC_PUBCFGR4 register  *****************/
29399 #define RCC_PUBCFGR4_ACLKNPUB_Pos               (0U)
29400 #define RCC_PUBCFGR4_ACLKNPUB_Msk               (0x1UL << RCC_PUBCFGR4_ACLKNPUB_Pos)  /*!< 0x00000001 */
29401 #define RCC_PUBCFGR4_ACLKNPUB                   RCC_PUBCFGR4_ACLKNPUB_Msk            /*!< Public protection of the ACLKN bus configuration bits */
29402 #define RCC_PUBCFGR4_ACLKNCPUB_Pos              (1U)
29403 #define RCC_PUBCFGR4_ACLKNCPUB_Msk              (0x1UL << RCC_PUBCFGR4_ACLKNCPUB_Pos) /*!< 0x00000002 */
29404 #define RCC_PUBCFGR4_ACLKNCPUB                  RCC_PUBCFGR4_ACLKNCPUB_Msk           /*!< Public protection of ACLKNC bus configuration bits */
29405 #define RCC_PUBCFGR4_AHBMPUB_Pos                (2U)
29406 #define RCC_PUBCFGR4_AHBMPUB_Msk                (0x1UL << RCC_PUBCFGR4_AHBMPUB_Pos)   /*!< 0x00000004 */
29407 #define RCC_PUBCFGR4_AHBMPUB                    RCC_PUBCFGR4_AHBMPUB_Msk             /*!< Public protection of AHBM bus configuration bits */
29408 #define RCC_PUBCFGR4_AHB1PUB_Pos                (3U)
29409 #define RCC_PUBCFGR4_AHB1PUB_Msk                (0x1UL << RCC_PUBCFGR4_AHB1PUB_Pos)   /*!< 0x00000008 */
29410 #define RCC_PUBCFGR4_AHB1PUB                    RCC_PUBCFGR4_AHB1PUB_Msk             /*!< Public protection of AHB1 bus configuration bits */
29411 #define RCC_PUBCFGR4_AHB2PUB_Pos                (4U)
29412 #define RCC_PUBCFGR4_AHB2PUB_Msk                (0x1UL << RCC_PUBCFGR4_AHB2PUB_Pos)   /*!< 0x00000010 */
29413 #define RCC_PUBCFGR4_AHB2PUB                    RCC_PUBCFGR4_AHB2PUB_Msk             /*!< Public protection of AHB2 bus configuration bits */
29414 #define RCC_PUBCFGR4_AHB3PUB_Pos                (5U)
29415 #define RCC_PUBCFGR4_AHB3PUB_Msk                (0x1UL << RCC_PUBCFGR4_AHB3PUB_Pos)   /*!< 0x00000020 */
29416 #define RCC_PUBCFGR4_AHB3PUB                    RCC_PUBCFGR4_AHB3PUB_Msk             /*!< Public protection of AHB3 bus configuration bits */
29417 #define RCC_PUBCFGR4_AHB4PUB_Pos                (6U)
29418 #define RCC_PUBCFGR4_AHB4PUB_Msk                (0x1UL << RCC_PUBCFGR4_AHB4PUB_Pos)   /*!< 0x00000040 */
29419 #define RCC_PUBCFGR4_AHB4PUB                    RCC_PUBCFGR4_AHB4PUB_Msk             /*!< Public protection of AHB4 bus configuration bits */
29420 #define RCC_PUBCFGR4_AHB5PUB_Pos                (7U)
29421 #define RCC_PUBCFGR4_AHB5PUB_Msk                (0x1UL << RCC_PUBCFGR4_AHB5PUB_Pos)   /*!< 0x00000080 */
29422 #define RCC_PUBCFGR4_AHB5PUB                    RCC_PUBCFGR4_AHB5PUB_Msk             /*!< Public protection of AHB5 bus configuration bits */
29423 #define RCC_PUBCFGR4_APB1PUB_Pos                (8U)
29424 #define RCC_PUBCFGR4_APB1PUB_Msk                (0x1UL << RCC_PUBCFGR4_APB1PUB_Pos)   /*!< 0x00000100 */
29425 #define RCC_PUBCFGR4_APB1PUB                    RCC_PUBCFGR4_APB1PUB_Msk             /*!< Public protection of APB1 bus configuration bits */
29426 #define RCC_PUBCFGR4_APB2PUB_Pos                (9U)
29427 #define RCC_PUBCFGR4_APB2PUB_Msk                (0x1UL << RCC_PUBCFGR4_APB2PUB_Pos)   /*!< 0x00000200 */
29428 #define RCC_PUBCFGR4_APB2PUB                    RCC_PUBCFGR4_APB2PUB_Msk             /*!< Public protection of APB2 bus configuration bits */
29429 #define RCC_PUBCFGR4_APB3PUB_Pos                (10U)
29430 #define RCC_PUBCFGR4_APB3PUB_Msk                (0x1UL << RCC_PUBCFGR4_APB3PUB_Pos)   /*!< 0x00000400 */
29431 #define RCC_PUBCFGR4_APB3PUB                    RCC_PUBCFGR4_APB3PUB_Msk             /*!< Public protection of APB3 bus configuration bits */
29432 #define RCC_PUBCFGR4_APB4PUB_Pos                (11U)
29433 #define RCC_PUBCFGR4_APB4PUB_Msk                (0x1UL << RCC_PUBCFGR4_APB4PUB_Pos)   /*!< 0x00000800 */
29434 #define RCC_PUBCFGR4_APB4PUB                    RCC_PUBCFGR4_APB4PUB_Msk             /*!< Public protection of APB4 bus configuration bits */
29435 #define RCC_PUBCFGR4_APB5PUB_Pos                (12U)
29436 #define RCC_PUBCFGR4_APB5PUB_Msk                (0x1UL << RCC_PUBCFGR4_APB5PUB_Pos)   /*!< 0x00001000 */
29437 #define RCC_PUBCFGR4_APB5PUB                    RCC_PUBCFGR4_APB5PUB_Msk             /*!< Public protection of APB5 bus configuration bits */
29438 #define RCC_PUBCFGR4_NOCPUB_Pos                 (13U)
29439 #define RCC_PUBCFGR4_NOCPUB_Msk                 (0x1UL << RCC_PUBCFGR4_NOCPUB_Pos)    /*!< 0x00002000 */
29440 #define RCC_PUBCFGR4_NOCPUB                     RCC_PUBCFGR4_NOCPUB_Msk              /*!< Public protection of NOC bus configuration bits */
29441 
29442 /*****************  Bit definition for RCC_PUBCFGR5 register  *****************/
29443 #define RCC_PUBCFGR5_AXISRAM3PUB_Pos            (0U)
29444 #define RCC_PUBCFGR5_AXISRAM3PUB_Msk            (0x1UL << RCC_PUBCFGR5_AXISRAM3PUB_Pos) /*!< 0x00000001 */
29445 #define RCC_PUBCFGR5_AXISRAM3PUB                RCC_PUBCFGR5_AXISRAM3PUB_Msk         /*!< Public protection of AXISRAM3 bus configuration bits */
29446 #define RCC_PUBCFGR5_AXISRAM4PUB_Pos            (1U)
29447 #define RCC_PUBCFGR5_AXISRAM4PUB_Msk            (0x1UL << RCC_PUBCFGR5_AXISRAM4PUB_Pos) /*!< 0x00000002 */
29448 #define RCC_PUBCFGR5_AXISRAM4PUB                RCC_PUBCFGR5_AXISRAM4PUB_Msk         /*!< Public protection of AXISRAM4 bus configuration bits */
29449 #define RCC_PUBCFGR5_AXISRAM5PUB_Pos            (2U)
29450 #define RCC_PUBCFGR5_AXISRAM5PUB_Msk            (0x1UL << RCC_PUBCFGR5_AXISRAM5PUB_Pos) /*!< 0x00000004 */
29451 #define RCC_PUBCFGR5_AXISRAM5PUB                RCC_PUBCFGR5_AXISRAM5PUB_Msk         /*!< Public protection of AXISRAM5 bus configuration bits */
29452 #define RCC_PUBCFGR5_AXISRAM6PUB_Pos            (3U)
29453 #define RCC_PUBCFGR5_AXISRAM6PUB_Msk            (0x1UL << RCC_PUBCFGR5_AXISRAM6PUB_Pos) /*!< 0x00000008 */
29454 #define RCC_PUBCFGR5_AXISRAM6PUB                RCC_PUBCFGR5_AXISRAM6PUB_Msk         /*!< Public protection of AXISRAM6 bus configuration bits */
29455 #define RCC_PUBCFGR5_AHBSRAM1PUB_Pos            (4U)
29456 #define RCC_PUBCFGR5_AHBSRAM1PUB_Msk            (0x1UL << RCC_PUBCFGR5_AHBSRAM1PUB_Pos) /*!< 0x00000010 */
29457 #define RCC_PUBCFGR5_AHBSRAM1PUB                RCC_PUBCFGR5_AHBSRAM1PUB_Msk         /*!< Public protection of AHBSRAM1 bus configuration bits */
29458 #define RCC_PUBCFGR5_AHBSRAM2PUB_Pos            (5U)
29459 #define RCC_PUBCFGR5_AHBSRAM2PUB_Msk            (0x1UL << RCC_PUBCFGR5_AHBSRAM2PUB_Pos) /*!< 0x00000020 */
29460 #define RCC_PUBCFGR5_AHBSRAM2PUB                RCC_PUBCFGR5_AHBSRAM2PUB_Msk         /*!< Public protection of AHBSRAM2 bus configuration bits */
29461 #define RCC_PUBCFGR5_BKPSRAMPUB_Pos             (6U)
29462 #define RCC_PUBCFGR5_BKPSRAMPUB_Msk             (0x1UL << RCC_PUBCFGR5_BKPSRAMPUB_Pos)/*!< 0x00000040 */
29463 #define RCC_PUBCFGR5_BKPSRAMPUB                 RCC_PUBCFGR5_BKPSRAMPUB_Msk          /*!< Public protection of BKPSRAM bus configuration bits */
29464 #define RCC_PUBCFGR5_AXISRAM1PUB_Pos            (7U)
29465 #define RCC_PUBCFGR5_AXISRAM1PUB_Msk            (0x1UL << RCC_PUBCFGR5_AXISRAM1PUB_Pos) /*!< 0x00000080 */
29466 #define RCC_PUBCFGR5_AXISRAM1PUB                RCC_PUBCFGR5_AXISRAM1PUB_Msk         /*!< Public protection of AXISRAM1 bus configuration bits */
29467 #define RCC_PUBCFGR5_AXISRAM2PUB_Pos            (8U)
29468 #define RCC_PUBCFGR5_AXISRAM2PUB_Msk            (0x1UL << RCC_PUBCFGR5_AXISRAM2PUB_Pos) /*!< 0x00000100 */
29469 #define RCC_PUBCFGR5_AXISRAM2PUB                RCC_PUBCFGR5_AXISRAM2PUB_Msk         /*!< Public protection of AXISRAM2 bus configuration bits */
29470 #define RCC_PUBCFGR5_FLEXRAMPUB_Pos             (9U)
29471 #define RCC_PUBCFGR5_FLEXRAMPUB_Msk             (0x1UL << RCC_PUBCFGR5_FLEXRAMPUB_Pos)/*!< 0x00000200 */
29472 #define RCC_PUBCFGR5_FLEXRAMPUB                 RCC_PUBCFGR5_FLEXRAMPUB_Msk          /*!< Public protection of FLEXRAM bus configuration bits */
29473 #define RCC_PUBCFGR5_CACHEAXIRAMPUB_Pos         (10U)
29474 #define RCC_PUBCFGR5_CACHEAXIRAMPUB_Msk         (0x1UL << RCC_PUBCFGR5_CACHEAXIRAMPUB_Pos)    /*!< 0x00000400 */
29475 #define RCC_PUBCFGR5_CACHEAXIRAMPUB             RCC_PUBCFGR5_CACHEAXIRAMPUB_Msk      /*!< Public protection of CACHEAXIRAM bus configuration bits */
29476 #define RCC_PUBCFGR5_VENCRAMPUB_Pos             (11U)
29477 #define RCC_PUBCFGR5_VENCRAMPUB_Msk             (0x1UL << RCC_PUBCFGR5_VENCRAMPUB_Pos)/*!< 0x00000800 */
29478 #define RCC_PUBCFGR5_VENCRAMPUB                 RCC_PUBCFGR5_VENCRAMPUB_Msk          /*!< Public protection of VENCRAM bus configuration bits */
29479 
29480 /*******************  Bit definition for RCC_CSR register  ********************/
29481 #define RCC_CSR_LSIONS_Pos                      (0U)
29482 #define RCC_CSR_LSIONS_Msk                      (0x1UL << RCC_CSR_LSIONS_Pos)         /*!< 0x00000001 */
29483 #define RCC_CSR_LSIONS                          RCC_CSR_LSIONS_Msk                   /*!< LSI oscillator enable */
29484 #define RCC_CSR_LSEONS_Pos                      (1U)
29485 #define RCC_CSR_LSEONS_Msk                      (0x1UL << RCC_CSR_LSEONS_Pos)         /*!< 0x00000002 */
29486 #define RCC_CSR_LSEONS                          RCC_CSR_LSEONS_Msk                   /*!< LSE oscillator enable */
29487 #define RCC_CSR_MSIONS_Pos                      (2U)
29488 #define RCC_CSR_MSIONS_Msk                      (0x1UL << RCC_CSR_MSIONS_Pos)         /*!< 0x00000004 */
29489 #define RCC_CSR_MSIONS                          RCC_CSR_MSIONS_Msk                   /*!< MSI oscillator enable */
29490 #define RCC_CSR_HSIONS_Pos                      (3U)
29491 #define RCC_CSR_HSIONS_Msk                      (0x1UL << RCC_CSR_HSIONS_Pos)         /*!< 0x00000008 */
29492 #define RCC_CSR_HSIONS                          RCC_CSR_HSIONS_Msk                   /*!< HSI oscillator enable */
29493 #define RCC_CSR_HSEONS_Pos                      (4U)
29494 #define RCC_CSR_HSEONS_Msk                      (0x1UL << RCC_CSR_HSEONS_Pos)         /*!< 0x00000010 */
29495 #define RCC_CSR_HSEONS                          RCC_CSR_HSEONS_Msk                   /*!< HSE oscillator enable */
29496 #define RCC_CSR_PLL1ONS_Pos                     (8U)
29497 #define RCC_CSR_PLL1ONS_Msk                     (0x1UL << RCC_CSR_PLL1ONS_Pos)        /*!< 0x00000100 */
29498 #define RCC_CSR_PLL1ONS                         RCC_CSR_PLL1ONS_Msk                  /*!< PLL1 oscillator enable */
29499 #define RCC_CSR_PLL2ONS_Pos                     (9U)
29500 #define RCC_CSR_PLL2ONS_Msk                     (0x1UL << RCC_CSR_PLL2ONS_Pos)        /*!< 0x00000200 */
29501 #define RCC_CSR_PLL2ONS                         RCC_CSR_PLL2ONS_Msk                  /*!< PLL2 oscillator enable */
29502 #define RCC_CSR_PLL3ONS_Pos                     (10U)
29503 #define RCC_CSR_PLL3ONS_Msk                     (0x1UL << RCC_CSR_PLL3ONS_Pos)        /*!< 0x00000400 */
29504 #define RCC_CSR_PLL3ONS                         RCC_CSR_PLL3ONS_Msk                  /*!< PLL3 oscillator enable */
29505 #define RCC_CSR_PLL4ONS_Pos                     (11U)
29506 #define RCC_CSR_PLL4ONS_Msk                     (0x1UL << RCC_CSR_PLL4ONS_Pos)        /*!< 0x00000800 */
29507 #define RCC_CSR_PLL4ONS                         RCC_CSR_PLL4ONS_Msk                  /*!< PLL4 oscillator enable */
29508 
29509 /*****************  Bit definition for RCC_STOPCSR register  ******************/
29510 #define RCC_STOPCSR_MSISTOPENS_Pos              (0U)
29511 #define RCC_STOPCSR_MSISTOPENS_Msk              (0x1UL << RCC_STOPCSR_MSISTOPENS_Pos) /*!< 0x00000001 */
29512 #define RCC_STOPCSR_MSISTOPENS                  RCC_STOPCSR_MSISTOPENS_Msk           /*!< MSI oscillator enable */
29513 #define RCC_STOPCSR_HSISTOPENS_Pos              (1U)
29514 #define RCC_STOPCSR_HSISTOPENS_Msk              (0x1UL << RCC_STOPCSR_HSISTOPENS_Pos) /*!< 0x00000002 */
29515 #define RCC_STOPCSR_HSISTOPENS                  RCC_STOPCSR_HSISTOPENS_Msk           /*!< HSI oscillator enable */
29516 
29517 /****************  Bit definition for RCC_MISCRSTSR register  *****************/
29518 #define RCC_MISCRSTSR_DBGRSTS_Pos               (0U)
29519 #define RCC_MISCRSTSR_DBGRSTS_Msk               (0x1UL << RCC_MISCRSTSR_DBGRSTS_Pos)  /*!< 0x00000001 */
29520 #define RCC_MISCRSTSR_DBGRSTS                   RCC_MISCRSTSR_DBGRSTS_Msk            /*!< DBG reset */
29521 #define RCC_MISCRSTSR_XSPIPHY1RSTS_Pos          (4U)
29522 #define RCC_MISCRSTSR_XSPIPHY1RSTS_Msk          (0x1UL << RCC_MISCRSTSR_XSPIPHY1RSTS_Pos)   /*!< 0x00000010 */
29523 #define RCC_MISCRSTSR_XSPIPHY1RSTS              RCC_MISCRSTSR_XSPIPHY1RSTS_Msk       /*!< XSPIPHY1 reset */
29524 #define RCC_MISCRSTSR_XSPIPHY2RSTS_Pos          (5U)
29525 #define RCC_MISCRSTSR_XSPIPHY2RSTS_Msk          (0x1UL << RCC_MISCRSTSR_XSPIPHY2RSTS_Pos)   /*!< 0x00000020 */
29526 #define RCC_MISCRSTSR_XSPIPHY2RSTS              RCC_MISCRSTSR_XSPIPHY2RSTS_Msk       /*!< XSPIPHY2 reset */
29527 #define RCC_MISCRSTSR_SDMMC1DLLRSTS_Pos         (7U)
29528 #define RCC_MISCRSTSR_SDMMC1DLLRSTS_Msk         (0x1UL << RCC_MISCRSTSR_SDMMC1DLLRSTS_Pos)    /*!< 0x00000080 */
29529 #define RCC_MISCRSTSR_SDMMC1DLLRSTS             RCC_MISCRSTSR_SDMMC1DLLRSTS_Msk      /*!< SDMMC1DLL reset */
29530 #define RCC_MISCRSTSR_SDMMC2DLLRSTS_Pos         (8U)
29531 #define RCC_MISCRSTSR_SDMMC2DLLRSTS_Msk         (0x1UL << RCC_MISCRSTSR_SDMMC2DLLRSTS_Pos)    /*!< 0x00000100 */
29532 #define RCC_MISCRSTSR_SDMMC2DLLRSTS             RCC_MISCRSTSR_SDMMC2DLLRSTS_Msk      /*!< SDMMC2DLL reset */
29533 
29534 /*****************  Bit definition for RCC_MEMRSTSR register  *****************/
29535 #define RCC_MEMRSTSR_AXISRAM3RSTS_Pos           (0U)
29536 #define RCC_MEMRSTSR_AXISRAM3RSTS_Msk           (0x1UL << RCC_MEMRSTSR_AXISRAM3RSTS_Pos)  /*!< 0x00000001 */
29537 #define RCC_MEMRSTSR_AXISRAM3RSTS               RCC_MEMRSTSR_AXISRAM3RSTS_Msk        /*!< AXISRAM3 reset */
29538 #define RCC_MEMRSTSR_AXISRAM4RSTS_Pos           (1U)
29539 #define RCC_MEMRSTSR_AXISRAM4RSTS_Msk           (0x1UL << RCC_MEMRSTSR_AXISRAM4RSTS_Pos)  /*!< 0x00000002 */
29540 #define RCC_MEMRSTSR_AXISRAM4RSTS               RCC_MEMRSTSR_AXISRAM4RSTS_Msk        /*!< AXISRAM4 reset */
29541 #define RCC_MEMRSTSR_AXISRAM5RSTS_Pos           (2U)
29542 #define RCC_MEMRSTSR_AXISRAM5RSTS_Msk           (0x1UL << RCC_MEMRSTSR_AXISRAM5RSTS_Pos)  /*!< 0x00000004 */
29543 #define RCC_MEMRSTSR_AXISRAM5RSTS               RCC_MEMRSTSR_AXISRAM5RSTS_Msk        /*!< AXISRAM5 reset */
29544 #define RCC_MEMRSTSR_AXISRAM6RSTS_Pos           (3U)
29545 #define RCC_MEMRSTSR_AXISRAM6RSTS_Msk           (0x1UL << RCC_MEMRSTSR_AXISRAM6RSTS_Pos)  /*!< 0x00000008 */
29546 #define RCC_MEMRSTSR_AXISRAM6RSTS               RCC_MEMRSTSR_AXISRAM6RSTS_Msk        /*!< AXISRAM6 reset */
29547 #define RCC_MEMRSTSR_AHBSRAM1RSTS_Pos           (4U)
29548 #define RCC_MEMRSTSR_AHBSRAM1RSTS_Msk           (0x1UL << RCC_MEMRSTSR_AHBSRAM1RSTS_Pos)  /*!< 0x00000010 */
29549 #define RCC_MEMRSTSR_AHBSRAM1RSTS               RCC_MEMRSTSR_AHBSRAM1RSTS_Msk        /*!< AHBSRAM1 reset */
29550 #define RCC_MEMRSTSR_AHBSRAM2RSTS_Pos           (5U)
29551 #define RCC_MEMRSTSR_AHBSRAM2RSTS_Msk           (0x1UL << RCC_MEMRSTSR_AHBSRAM2RSTS_Pos)  /*!< 0x00000020 */
29552 #define RCC_MEMRSTSR_AHBSRAM2RSTS               RCC_MEMRSTSR_AHBSRAM2RSTS_Msk        /*!< AHBSRAM2 reset */
29553 #define RCC_MEMRSTSR_AXISRAM1RSTS_Pos           (7U)
29554 #define RCC_MEMRSTSR_AXISRAM1RSTS_Msk           (0x1UL << RCC_MEMRSTSR_AXISRAM1RSTS_Pos)  /*!< 0x00000080 */
29555 #define RCC_MEMRSTSR_AXISRAM1RSTS               RCC_MEMRSTSR_AXISRAM1RSTS_Msk        /*!< AXISRAM1 reset */
29556 #define RCC_MEMRSTSR_AXISRAM2RSTS_Pos           (8U)
29557 #define RCC_MEMRSTSR_AXISRAM2RSTS_Msk           (0x1UL << RCC_MEMRSTSR_AXISRAM2RSTS_Pos)  /*!< 0x00000100 */
29558 #define RCC_MEMRSTSR_AXISRAM2RSTS               RCC_MEMRSTSR_AXISRAM2RSTS_Msk        /*!< AXISRAM2 reset */
29559 #define RCC_MEMRSTSR_FLEXRAMRSTS_Pos            (9U)
29560 #define RCC_MEMRSTSR_FLEXRAMRSTS_Msk            (0x1UL << RCC_MEMRSTSR_FLEXRAMRSTS_Pos) /*!< 0x00000200 */
29561 #define RCC_MEMRSTSR_FLEXRAMRSTS                RCC_MEMRSTSR_FLEXRAMRSTS_Msk         /*!< FLEXRAM reset */
29562 #define RCC_MEMRSTSR_CACHEAXIRAMRSTS_Pos        (10U)
29563 #define RCC_MEMRSTSR_CACHEAXIRAMRSTS_Msk        (0x1UL << RCC_MEMRSTSR_CACHEAXIRAMRSTS_Pos)     /*!< 0x00000400 */
29564 #define RCC_MEMRSTSR_CACHEAXIRAMRSTS            RCC_MEMRSTSR_CACHEAXIRAMRSTS_Msk     /*!< CACHEAXIRAM reset */
29565 #define RCC_MEMRSTSR_VENCRAMRSTS_Pos            (11U)
29566 #define RCC_MEMRSTSR_VENCRAMRSTS_Msk            (0x1UL << RCC_MEMRSTSR_VENCRAMRSTS_Pos) /*!< 0x00000800 */
29567 #define RCC_MEMRSTSR_VENCRAMRSTS                RCC_MEMRSTSR_VENCRAMRSTS_Msk         /*!< VENCRAM reset */
29568 #define RCC_MEMRSTSR_BOOTROMRSTS_Pos            (12U)
29569 #define RCC_MEMRSTSR_BOOTROMRSTS_Msk            (0x1UL << RCC_MEMRSTSR_BOOTROMRSTS_Pos) /*!< 0x00001000 */
29570 #define RCC_MEMRSTSR_BOOTROMRSTS                RCC_MEMRSTSR_BOOTROMRSTS_Msk         /*!< Boot ROM reset */
29571 
29572 /****************  Bit definition for RCC_AHB1RSTSR register  *****************/
29573 #define RCC_AHB1RSTSR_GPDMA1RSTS_Pos            (4U)
29574 #define RCC_AHB1RSTSR_GPDMA1RSTS_Msk            (0x1UL << RCC_AHB1RSTSR_GPDMA1RSTS_Pos) /*!< 0x00000010 */
29575 #define RCC_AHB1RSTSR_GPDMA1RSTS                RCC_AHB1RSTSR_GPDMA1RSTS_Msk         /*!< GPDMA1 reset */
29576 #define RCC_AHB1RSTSR_ADC12RSTS_Pos             (5U)
29577 #define RCC_AHB1RSTSR_ADC12RSTS_Msk             (0x1UL << RCC_AHB1RSTSR_ADC12RSTS_Pos)/*!< 0x00000020 */
29578 #define RCC_AHB1RSTSR_ADC12RSTS                 RCC_AHB1RSTSR_ADC12RSTS_Msk          /*!< ADC12 reset */
29579 
29580 /****************  Bit definition for RCC_AHB2RSTSR register  *****************/
29581 #define RCC_AHB2RSTSR_RAMCFGRSTS_Pos            (12U)
29582 #define RCC_AHB2RSTSR_RAMCFGRSTS_Msk            (0x1UL << RCC_AHB2RSTSR_RAMCFGRSTS_Pos) /*!< 0x00001000 */
29583 #define RCC_AHB2RSTSR_RAMCFGRSTS                RCC_AHB2RSTSR_RAMCFGRSTS_Msk         /*!< RAMCFG reset */
29584 #define RCC_AHB2RSTSR_MDF1RSTS_Pos              (16U)
29585 #define RCC_AHB2RSTSR_MDF1RSTS_Msk              (0x1UL << RCC_AHB2RSTSR_MDF1RSTS_Pos) /*!< 0x00010000 */
29586 #define RCC_AHB2RSTSR_MDF1RSTS                  RCC_AHB2RSTSR_MDF1RSTS_Msk           /*!< MDF1 reset */
29587 #define RCC_AHB2RSTSR_ADF1RSTS_Pos              (17U)
29588 #define RCC_AHB2RSTSR_ADF1RSTS_Msk              (0x1UL << RCC_AHB2RSTSR_ADF1RSTS_Pos) /*!< 0x00020000 */
29589 #define RCC_AHB2RSTSR_ADF1RSTS                  RCC_AHB2RSTSR_ADF1RSTS_Msk           /*!< ADF1 reset */
29590 
29591 /****************  Bit definition for RCC_AHB3RSTSR register  *****************/
29592 #define RCC_AHB3RSTSR_RNGRSTS_Pos               (0U)
29593 #define RCC_AHB3RSTSR_RNGRSTS_Msk               (0x1UL << RCC_AHB3RSTSR_RNGRSTS_Pos)  /*!< 0x00000001 */
29594 #define RCC_AHB3RSTSR_RNGRSTS                   RCC_AHB3RSTSR_RNGRSTS_Msk            /*!< RNG reset */
29595 #define RCC_AHB3RSTSR_HASHRSTS_Pos              (1U)
29596 #define RCC_AHB3RSTSR_HASHRSTS_Msk              (0x1UL << RCC_AHB3RSTSR_HASHRSTS_Pos) /*!< 0x00000002 */
29597 #define RCC_AHB3RSTSR_HASHRSTS                  RCC_AHB3RSTSR_HASHRSTS_Msk           /*!< HASH reset */
29598 #define RCC_AHB3RSTSR_CRYPRSTS_Pos              (2U)
29599 #define RCC_AHB3RSTSR_CRYPRSTS_Msk              (0x1UL << RCC_AHB3RSTSR_CRYPRSTS_Pos) /*!< 0x00000004 */
29600 #define RCC_AHB3RSTSR_CRYPRSTS                  RCC_AHB3RSTSR_CRYPRSTS_Msk           /*!< CRYP reset */
29601 #define RCC_AHB3RSTSR_SAESRSTS_Pos              (4U)
29602 #define RCC_AHB3RSTSR_SAESRSTS_Msk              (0x1UL << RCC_AHB3RSTSR_SAESRSTS_Pos) /*!< 0x00000010 */
29603 #define RCC_AHB3RSTSR_SAESRSTS                  RCC_AHB3RSTSR_SAESRSTS_Msk           /*!< SAES reset */
29604 #define RCC_AHB3RSTSR_PKARSTS_Pos               (8U)
29605 #define RCC_AHB3RSTSR_PKARSTS_Msk               (0x1UL << RCC_AHB3RSTSR_PKARSTS_Pos)  /*!< 0x00000100 */
29606 #define RCC_AHB3RSTSR_PKARSTS                   RCC_AHB3RSTSR_PKARSTS_Msk            /*!< PKA reset */
29607 #define RCC_AHB3RSTSR_IACRSTS_Pos               (10U)
29608 #define RCC_AHB3RSTSR_IACRSTS_Msk               (0x1UL << RCC_AHB3RSTSR_IACRSTS_Pos)  /*!< 0x00000400 */
29609 #define RCC_AHB3RSTSR_IACRSTS                   RCC_AHB3RSTSR_IACRSTS_Msk            /*!< IAC reset */
29610 
29611 /****************  Bit definition for RCC_AHB4RSTSR register  *****************/
29612 #define RCC_AHB4RSTSR_GPIOARSTS_Pos             (0U)
29613 #define RCC_AHB4RSTSR_GPIOARSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOARSTS_Pos)/*!< 0x00000001 */
29614 #define RCC_AHB4RSTSR_GPIOARSTS                 RCC_AHB4RSTSR_GPIOARSTS_Msk          /*!< GPIO A reset */
29615 #define RCC_AHB4RSTSR_GPIOBRSTS_Pos             (1U)
29616 #define RCC_AHB4RSTSR_GPIOBRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOBRSTS_Pos)/*!< 0x00000002 */
29617 #define RCC_AHB4RSTSR_GPIOBRSTS                 RCC_AHB4RSTSR_GPIOBRSTS_Msk          /*!< GPIO B reset */
29618 #define RCC_AHB4RSTSR_GPIOCRSTS_Pos             (2U)
29619 #define RCC_AHB4RSTSR_GPIOCRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOCRSTS_Pos)/*!< 0x00000004 */
29620 #define RCC_AHB4RSTSR_GPIOCRSTS                 RCC_AHB4RSTSR_GPIOCRSTS_Msk          /*!< GPIO C reset */
29621 #define RCC_AHB4RSTSR_GPIODRSTS_Pos             (3U)
29622 #define RCC_AHB4RSTSR_GPIODRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIODRSTS_Pos)/*!< 0x00000008 */
29623 #define RCC_AHB4RSTSR_GPIODRSTS                 RCC_AHB4RSTSR_GPIODRSTS_Msk          /*!< GPIO D reset */
29624 #define RCC_AHB4RSTSR_GPIOERSTS_Pos             (4U)
29625 #define RCC_AHB4RSTSR_GPIOERSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOERSTS_Pos)/*!< 0x00000010 */
29626 #define RCC_AHB4RSTSR_GPIOERSTS                 RCC_AHB4RSTSR_GPIOERSTS_Msk          /*!< GPIO E reset */
29627 #define RCC_AHB4RSTSR_GPIOFRSTS_Pos             (5U)
29628 #define RCC_AHB4RSTSR_GPIOFRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOFRSTS_Pos)/*!< 0x00000020 */
29629 #define RCC_AHB4RSTSR_GPIOFRSTS                 RCC_AHB4RSTSR_GPIOFRSTS_Msk          /*!< GPIO F reset */
29630 #define RCC_AHB4RSTSR_GPIOGRSTS_Pos             (6U)
29631 #define RCC_AHB4RSTSR_GPIOGRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOGRSTS_Pos)/*!< 0x00000040 */
29632 #define RCC_AHB4RSTSR_GPIOGRSTS                 RCC_AHB4RSTSR_GPIOGRSTS_Msk          /*!< GPIO G reset */
29633 #define RCC_AHB4RSTSR_GPIOHRSTS_Pos             (7U)
29634 #define RCC_AHB4RSTSR_GPIOHRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOHRSTS_Pos)/*!< 0x00000080 */
29635 #define RCC_AHB4RSTSR_GPIOHRSTS                 RCC_AHB4RSTSR_GPIOHRSTS_Msk          /*!< GPIO H reset */
29636 #define RCC_AHB4RSTSR_GPIONRSTS_Pos             (13U)
29637 #define RCC_AHB4RSTSR_GPIONRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIONRSTS_Pos)/*!< 0x00002000 */
29638 #define RCC_AHB4RSTSR_GPIONRSTS                 RCC_AHB4RSTSR_GPIONRSTS_Msk          /*!< GPIO N reset */
29639 #define RCC_AHB4RSTSR_GPIOORSTS_Pos             (14U)
29640 #define RCC_AHB4RSTSR_GPIOORSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOORSTS_Pos)/*!< 0x00004000 */
29641 #define RCC_AHB4RSTSR_GPIOORSTS                 RCC_AHB4RSTSR_GPIOORSTS_Msk          /*!< GPIO O reset */
29642 #define RCC_AHB4RSTSR_GPIOPRSTS_Pos             (15U)
29643 #define RCC_AHB4RSTSR_GPIOPRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOPRSTS_Pos)/*!< 0x00008000 */
29644 #define RCC_AHB4RSTSR_GPIOPRSTS                 RCC_AHB4RSTSR_GPIOPRSTS_Msk          /*!< GPIO P reset */
29645 #define RCC_AHB4RSTSR_GPIOQRSTS_Pos             (16U)
29646 #define RCC_AHB4RSTSR_GPIOQRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOQRSTS_Pos)/*!< 0x00010000 */
29647 #define RCC_AHB4RSTSR_GPIOQRSTS                 RCC_AHB4RSTSR_GPIOQRSTS_Msk          /*!< GPIO Q reset */
29648 #define RCC_AHB4RSTSR_PWRRSTS_Pos               (18U)
29649 #define RCC_AHB4RSTSR_PWRRSTS_Msk               (0x1UL << RCC_AHB4RSTSR_PWRRSTS_Pos)  /*!< 0x00040000 */
29650 #define RCC_AHB4RSTSR_PWRRSTS                   RCC_AHB4RSTSR_PWRRSTS_Msk            /*!< PWR reset */
29651 #define RCC_AHB4RSTSR_CRCRSTS_Pos               (19U)
29652 #define RCC_AHB4RSTSR_CRCRSTS_Msk               (0x1UL << RCC_AHB4RSTSR_CRCRSTS_Pos)  /*!< 0x00080000 */
29653 #define RCC_AHB4RSTSR_CRCRSTS                   RCC_AHB4RSTSR_CRCRSTS_Msk            /*!< CRC reset */
29654 
29655 /****************  Bit definition for RCC_AHB5RSTSR register  *****************/
29656 #define RCC_AHB5RSTSR_HPDMA1RSTS_Pos            (0U)
29657 #define RCC_AHB5RSTSR_HPDMA1RSTS_Msk            (0x1UL << RCC_AHB5RSTSR_HPDMA1RSTS_Pos) /*!< 0x00000001 */
29658 #define RCC_AHB5RSTSR_HPDMA1RSTS                RCC_AHB5RSTSR_HPDMA1RSTS_Msk         /*!< HPDMA1 reset */
29659 #define RCC_AHB5RSTSR_DMA2DRSTS_Pos             (1U)
29660 #define RCC_AHB5RSTSR_DMA2DRSTS_Msk             (0x1UL << RCC_AHB5RSTSR_DMA2DRSTS_Pos)/*!< 0x00000002 */
29661 #define RCC_AHB5RSTSR_DMA2DRSTS                 RCC_AHB5RSTSR_DMA2DRSTS_Msk          /*!< DMA2D reset */
29662 #define RCC_AHB5RSTSR_JPEGRSTS_Pos              (3U)
29663 #define RCC_AHB5RSTSR_JPEGRSTS_Msk              (0x1UL << RCC_AHB5RSTSR_JPEGRSTS_Pos) /*!< 0x00000008 */
29664 #define RCC_AHB5RSTSR_JPEGRSTS                  RCC_AHB5RSTSR_JPEGRSTS_Msk           /*!< JPEG reset */
29665 #define RCC_AHB5RSTSR_FMCRSTS_Pos               (4U)
29666 #define RCC_AHB5RSTSR_FMCRSTS_Msk               (0x1UL << RCC_AHB5RSTSR_FMCRSTS_Pos)  /*!< 0x00000010 */
29667 #define RCC_AHB5RSTSR_FMCRSTS                   RCC_AHB5RSTSR_FMCRSTS_Msk            /*!< FMC reset */
29668 #define RCC_AHB5RSTSR_XSPI1RSTS_Pos             (5U)
29669 #define RCC_AHB5RSTSR_XSPI1RSTS_Msk             (0x1UL << RCC_AHB5RSTSR_XSPI1RSTS_Pos)/*!< 0x00000020 */
29670 #define RCC_AHB5RSTSR_XSPI1RSTS                 RCC_AHB5RSTSR_XSPI1RSTS_Msk          /*!< XSPI1 reset */
29671 #define RCC_AHB5RSTSR_PSSIRSTS_Pos              (6U)
29672 #define RCC_AHB5RSTSR_PSSIRSTS_Msk              (0x1UL << RCC_AHB5RSTSR_PSSIRSTS_Pos) /*!< 0x00000040 */
29673 #define RCC_AHB5RSTSR_PSSIRSTS                  RCC_AHB5RSTSR_PSSIRSTS_Msk           /*!< PSSI reset */
29674 #define RCC_AHB5RSTSR_SDMMC2RSTS_Pos            (7U)
29675 #define RCC_AHB5RSTSR_SDMMC2RSTS_Msk            (0x1UL << RCC_AHB5RSTSR_SDMMC2RSTS_Pos) /*!< 0x00000080 */
29676 #define RCC_AHB5RSTSR_SDMMC2RSTS                RCC_AHB5RSTSR_SDMMC2RSTS_Msk         /*!< SDMMC2 reset */
29677 #define RCC_AHB5RSTSR_SDMMC1RSTS_Pos            (8U)
29678 #define RCC_AHB5RSTSR_SDMMC1RSTS_Msk            (0x1UL << RCC_AHB5RSTSR_SDMMC1RSTS_Pos) /*!< 0x00000100 */
29679 #define RCC_AHB5RSTSR_SDMMC1RSTS                RCC_AHB5RSTSR_SDMMC1RSTS_Msk         /*!< SDMMC1 reset */
29680 #define RCC_AHB5RSTSR_XSPI2RSTS_Pos             (12U)
29681 #define RCC_AHB5RSTSR_XSPI2RSTS_Msk             (0x1UL << RCC_AHB5RSTSR_XSPI2RSTS_Pos)/*!< 0x00001000 */
29682 #define RCC_AHB5RSTSR_XSPI2RSTS                 RCC_AHB5RSTSR_XSPI2RSTS_Msk          /*!< XSPI2 reset */
29683 #define RCC_AHB5RSTSR_XSPIMRSTS_Pos             (13U)
29684 #define RCC_AHB5RSTSR_XSPIMRSTS_Msk             (0x1UL << RCC_AHB5RSTSR_XSPIMRSTS_Pos)/*!< 0x00002000 */
29685 #define RCC_AHB5RSTSR_XSPIMRSTS                 RCC_AHB5RSTSR_XSPIMRSTS_Msk          /*!< XSPIM reset */
29686 #define RCC_AHB5RSTSR_XSPI3RSTS_Pos             (17U)
29687 #define RCC_AHB5RSTSR_XSPI3RSTS_Msk             (0x1UL << RCC_AHB5RSTSR_XSPI3RSTS_Pos)/*!< 0x00020000 */
29688 #define RCC_AHB5RSTSR_XSPI3RSTS                 RCC_AHB5RSTSR_XSPI3RSTS_Msk          /*!< XSPI3 reset */
29689 #define RCC_AHB5RSTSR_GFXMMURSTS_Pos            (19U)
29690 #define RCC_AHB5RSTSR_GFXMMURSTS_Msk            (0x1UL << RCC_AHB5RSTSR_GFXMMURSTS_Pos) /*!< 0x00080000 */
29691 #define RCC_AHB5RSTSR_GFXMMURSTS                RCC_AHB5RSTSR_GFXMMURSTS_Msk         /*!< GFXMMU reset */
29692 #define RCC_AHB5RSTSR_GPU2DRSTS_Pos             (20U)
29693 #define RCC_AHB5RSTSR_GPU2DRSTS_Msk             (0x1UL << RCC_AHB5RSTSR_GPU2DRSTS_Pos)/*!< 0x00100000 */
29694 #define RCC_AHB5RSTSR_GPU2DRSTS                 RCC_AHB5RSTSR_GPU2DRSTS_Msk          /*!< GPU2D reset */
29695 #define RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Pos        (23U)
29696 #define RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Msk        (0x1UL << RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Pos)     /*!< 0x00800000 */
29697 #define RCC_AHB5RSTSR_OTG1PHYCTLRSTS            RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Msk     /*!< OTG1PHYCTL reset */
29698 #define RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Pos        (24U)
29699 #define RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Msk        (0x1UL << RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Pos)     /*!< 0x01000000 */
29700 #define RCC_AHB5RSTSR_OTG2PHYCTLRSTS            RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Msk     /*!< OTG2PHYCTL reset */
29701 #define RCC_AHB5RSTSR_ETH1RSTS_Pos              (25U)
29702 #define RCC_AHB5RSTSR_ETH1RSTS_Msk              (0x1UL << RCC_AHB5RSTSR_ETH1RSTS_Pos) /*!< 0x02000000 */
29703 #define RCC_AHB5RSTSR_ETH1RSTS                  RCC_AHB5RSTSR_ETH1RSTS_Msk           /*!< ETH1 reset */
29704 #define RCC_AHB5RSTSR_OTG1RSTS_Pos              (26U)
29705 #define RCC_AHB5RSTSR_OTG1RSTS_Msk              (0x1UL << RCC_AHB5RSTSR_OTG1RSTS_Pos) /*!< 0x04000000 */
29706 #define RCC_AHB5RSTSR_OTG1RSTS                  RCC_AHB5RSTSR_OTG1RSTS_Msk           /*!< OTG1 reset */
29707 #define RCC_AHB5RSTSR_OTGPHY1RSTS_Pos           (27U)
29708 #define RCC_AHB5RSTSR_OTGPHY1RSTS_Msk           (0x1UL << RCC_AHB5RSTSR_OTGPHY1RSTS_Pos)  /*!< 0x08000000 */
29709 #define RCC_AHB5RSTSR_OTGPHY1RSTS               RCC_AHB5RSTSR_OTGPHY1RSTS_Msk        /*!< OTGPHY1 reset */
29710 #define RCC_AHB5RSTSR_OTGPHY2RSTS_Pos           (28U)
29711 #define RCC_AHB5RSTSR_OTGPHY2RSTS_Msk           (0x1UL << RCC_AHB5RSTSR_OTGPHY2RSTS_Pos)  /*!< 0x10000000 */
29712 #define RCC_AHB5RSTSR_OTGPHY2RSTS               RCC_AHB5RSTSR_OTGPHY2RSTS_Msk        /*!< OTGPHY2 reset */
29713 #define RCC_AHB5RSTSR_OTG2RSTS_Pos              (29U)
29714 #define RCC_AHB5RSTSR_OTG2RSTS_Msk              (0x1UL << RCC_AHB5RSTSR_OTG2RSTS_Pos) /*!< 0x20000000 */
29715 #define RCC_AHB5RSTSR_OTG2RSTS                  RCC_AHB5RSTSR_OTG2RSTS_Msk           /*!< OTG2 reset */
29716 #define RCC_AHB5RSTSR_CACHEAXIRSTS_Pos          (30U)
29717 #define RCC_AHB5RSTSR_CACHEAXIRSTS_Msk          (0x1UL << RCC_AHB5RSTSR_CACHEAXIRSTS_Pos)   /*!< 0x40000000 */
29718 #define RCC_AHB5RSTSR_CACHEAXIRSTS              RCC_AHB5RSTSR_CACHEAXIRSTS_Msk       /*!< CACHEAXI reset */
29719 #define RCC_AHB5RSTSR_NPURSTS_Pos               (31U)
29720 #define RCC_AHB5RSTSR_NPURSTS_Msk               (0x1UL << RCC_AHB5RSTSR_NPURSTS_Pos)  /*!< 0x80000000 */
29721 #define RCC_AHB5RSTSR_NPURSTS                   RCC_AHB5RSTSR_NPURSTS_Msk            /*!< NPU reset */
29722 
29723 /****************  Bit definition for RCC_APB1RSTSR1 register  ****************/
29724 #define RCC_APB1RSTSR1_TIM2RSTS_Pos             (0U)
29725 #define RCC_APB1RSTSR1_TIM2RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_TIM2RSTS_Pos)/*!< 0x00000001 */
29726 #define RCC_APB1RSTSR1_TIM2RSTS                 RCC_APB1RSTSR1_TIM2RSTS_Msk          /*!< TIM2 reset */
29727 #define RCC_APB1RSTSR1_TIM3RSTS_Pos             (1U)
29728 #define RCC_APB1RSTSR1_TIM3RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_TIM3RSTS_Pos)/*!< 0x00000002 */
29729 #define RCC_APB1RSTSR1_TIM3RSTS                 RCC_APB1RSTSR1_TIM3RSTS_Msk          /*!< TIM3 reset */
29730 #define RCC_APB1RSTSR1_TIM4RSTS_Pos             (2U)
29731 #define RCC_APB1RSTSR1_TIM4RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_TIM4RSTS_Pos)/*!< 0x00000004 */
29732 #define RCC_APB1RSTSR1_TIM4RSTS                 RCC_APB1RSTSR1_TIM4RSTS_Msk          /*!< TIM4 reset */
29733 #define RCC_APB1RSTSR1_TIM5RSTS_Pos             (3U)
29734 #define RCC_APB1RSTSR1_TIM5RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_TIM5RSTS_Pos)/*!< 0x00000008 */
29735 #define RCC_APB1RSTSR1_TIM5RSTS                 RCC_APB1RSTSR1_TIM5RSTS_Msk          /*!< TIM5 reset */
29736 #define RCC_APB1RSTSR1_TIM6RSTS_Pos             (4U)
29737 #define RCC_APB1RSTSR1_TIM6RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_TIM6RSTS_Pos)/*!< 0x00000010 */
29738 #define RCC_APB1RSTSR1_TIM6RSTS                 RCC_APB1RSTSR1_TIM6RSTS_Msk          /*!< TIM6 reset */
29739 #define RCC_APB1RSTSR1_TIM7RSTS_Pos             (5U)
29740 #define RCC_APB1RSTSR1_TIM7RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_TIM7RSTS_Pos)/*!< 0x00000020 */
29741 #define RCC_APB1RSTSR1_TIM7RSTS                 RCC_APB1RSTSR1_TIM7RSTS_Msk          /*!< TIM7 reset */
29742 #define RCC_APB1RSTSR1_TIM12RSTS_Pos            (6U)
29743 #define RCC_APB1RSTSR1_TIM12RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_TIM12RSTS_Pos) /*!< 0x00000040 */
29744 #define RCC_APB1RSTSR1_TIM12RSTS                RCC_APB1RSTSR1_TIM12RSTS_Msk         /*!< TIM12 reset */
29745 #define RCC_APB1RSTSR1_TIM13RSTS_Pos            (7U)
29746 #define RCC_APB1RSTSR1_TIM13RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_TIM13RSTS_Pos) /*!< 0x00000080 */
29747 #define RCC_APB1RSTSR1_TIM13RSTS                RCC_APB1RSTSR1_TIM13RSTS_Msk         /*!< TIM13 reset */
29748 #define RCC_APB1RSTSR1_TIM14RSTS_Pos            (8U)
29749 #define RCC_APB1RSTSR1_TIM14RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_TIM14RSTS_Pos) /*!< 0x00000100 */
29750 #define RCC_APB1RSTSR1_TIM14RSTS                RCC_APB1RSTSR1_TIM14RSTS_Msk         /*!< TIM14 reset */
29751 #define RCC_APB1RSTSR1_LPTIM1RSTS_Pos           (9U)
29752 #define RCC_APB1RSTSR1_LPTIM1RSTS_Msk           (0x1UL << RCC_APB1RSTSR1_LPTIM1RSTS_Pos)  /*!< 0x00000200 */
29753 #define RCC_APB1RSTSR1_LPTIM1RSTS               RCC_APB1RSTSR1_LPTIM1RSTS_Msk        /*!< LPTIM1 reset */
29754 #define RCC_APB1RSTSR1_WWDGRSTS_Pos             (11U)
29755 #define RCC_APB1RSTSR1_WWDGRSTS_Msk             (0x1UL << RCC_APB1RSTSR1_WWDGRSTS_Pos)/*!< 0x00000800 */
29756 #define RCC_APB1RSTSR1_WWDGRSTS                 RCC_APB1RSTSR1_WWDGRSTS_Msk          /*!< WWDG reset */
29757 #define RCC_APB1RSTSR1_TIM10RSTS_Pos            (12U)
29758 #define RCC_APB1RSTSR1_TIM10RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_TIM10RSTS_Pos) /*!< 0x00001000 */
29759 #define RCC_APB1RSTSR1_TIM10RSTS                RCC_APB1RSTSR1_TIM10RSTS_Msk         /*!< TIM10 reset */
29760 #define RCC_APB1RSTSR1_TIM11RSTS_Pos            (13U)
29761 #define RCC_APB1RSTSR1_TIM11RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_TIM11RSTS_Pos) /*!< 0x00002000 */
29762 #define RCC_APB1RSTSR1_TIM11RSTS                RCC_APB1RSTSR1_TIM11RSTS_Msk         /*!< TIM11 reset */
29763 #define RCC_APB1RSTSR1_SPI2RSTS_Pos             (14U)
29764 #define RCC_APB1RSTSR1_SPI2RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_SPI2RSTS_Pos)/*!< 0x00004000 */
29765 #define RCC_APB1RSTSR1_SPI2RSTS                 RCC_APB1RSTSR1_SPI2RSTS_Msk          /*!< SPI2 reset */
29766 #define RCC_APB1RSTSR1_SPI3RSTS_Pos             (15U)
29767 #define RCC_APB1RSTSR1_SPI3RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_SPI3RSTS_Pos)/*!< 0x00008000 */
29768 #define RCC_APB1RSTSR1_SPI3RSTS                 RCC_APB1RSTSR1_SPI3RSTS_Msk          /*!< SPI3 reset */
29769 #define RCC_APB1RSTSR1_SPDIFRX1RSTS_Pos         (16U)
29770 #define RCC_APB1RSTSR1_SPDIFRX1RSTS_Msk         (0x1UL << RCC_APB1RSTSR1_SPDIFRX1RSTS_Pos)    /*!< 0x00010000 */
29771 #define RCC_APB1RSTSR1_SPDIFRX1RSTS             RCC_APB1RSTSR1_SPDIFRX1RSTS_Msk      /*!< SPDIFRX1 reset */
29772 #define RCC_APB1RSTSR1_USART2RSTS_Pos           (17U)
29773 #define RCC_APB1RSTSR1_USART2RSTS_Msk           (0x1UL << RCC_APB1RSTSR1_USART2RSTS_Pos)  /*!< 0x00020000 */
29774 #define RCC_APB1RSTSR1_USART2RSTS               RCC_APB1RSTSR1_USART2RSTS_Msk        /*!< USART2 reset */
29775 #define RCC_APB1RSTSR1_USART3RSTS_Pos           (18U)
29776 #define RCC_APB1RSTSR1_USART3RSTS_Msk           (0x1UL << RCC_APB1RSTSR1_USART3RSTS_Pos)  /*!< 0x00040000 */
29777 #define RCC_APB1RSTSR1_USART3RSTS               RCC_APB1RSTSR1_USART3RSTS_Msk        /*!< USART3 reset */
29778 #define RCC_APB1RSTSR1_UART4RSTS_Pos            (19U)
29779 #define RCC_APB1RSTSR1_UART4RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_UART4RSTS_Pos) /*!< 0x00080000 */
29780 #define RCC_APB1RSTSR1_UART4RSTS                RCC_APB1RSTSR1_UART4RSTS_Msk         /*!< UART4 reset */
29781 #define RCC_APB1RSTSR1_UART5RSTS_Pos            (20U)
29782 #define RCC_APB1RSTSR1_UART5RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_UART5RSTS_Pos) /*!< 0x00100000 */
29783 #define RCC_APB1RSTSR1_UART5RSTS                RCC_APB1RSTSR1_UART5RSTS_Msk         /*!< UART5 reset */
29784 #define RCC_APB1RSTSR1_I2C1RSTS_Pos             (21U)
29785 #define RCC_APB1RSTSR1_I2C1RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_I2C1RSTS_Pos)/*!< 0x00200000 */
29786 #define RCC_APB1RSTSR1_I2C1RSTS                 RCC_APB1RSTSR1_I2C1RSTS_Msk          /*!< I2C1 reset */
29787 #define RCC_APB1RSTSR1_I2C2RSTS_Pos             (22U)
29788 #define RCC_APB1RSTSR1_I2C2RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_I2C2RSTS_Pos)/*!< 0x00400000 */
29789 #define RCC_APB1RSTSR1_I2C2RSTS                 RCC_APB1RSTSR1_I2C2RSTS_Msk          /*!< I2C2 reset */
29790 #define RCC_APB1RSTSR1_I2C3RSTS_Pos             (23U)
29791 #define RCC_APB1RSTSR1_I2C3RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_I2C3RSTS_Pos)/*!< 0x00800000 */
29792 #define RCC_APB1RSTSR1_I2C3RSTS                 RCC_APB1RSTSR1_I2C3RSTS_Msk          /*!< I2C3 reset */
29793 #define RCC_APB1RSTSR1_I3C1RSTS_Pos             (24U)
29794 #define RCC_APB1RSTSR1_I3C1RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_I3C1RSTS_Pos)/*!< 0x01000000 */
29795 #define RCC_APB1RSTSR1_I3C1RSTS                 RCC_APB1RSTSR1_I3C1RSTS_Msk          /*!< I3C1 reset */
29796 #define RCC_APB1RSTSR1_I3C2RSTS_Pos             (25U)
29797 #define RCC_APB1RSTSR1_I3C2RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_I3C2RSTS_Pos)/*!< 0x02000000 */
29798 #define RCC_APB1RSTSR1_I3C2RSTS                 RCC_APB1RSTSR1_I3C2RSTS_Msk          /*!< I3C2 reset */
29799 #define RCC_APB1RSTSR1_UART7RSTS_Pos            (30U)
29800 #define RCC_APB1RSTSR1_UART7RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_UART7RSTS_Pos) /*!< 0x40000000 */
29801 #define RCC_APB1RSTSR1_UART7RSTS                RCC_APB1RSTSR1_UART7RSTS_Msk         /*!< UART7 reset */
29802 #define RCC_APB1RSTSR1_UART8RSTS_Pos            (31U)
29803 #define RCC_APB1RSTSR1_UART8RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_UART8RSTS_Pos) /*!< 0x80000000 */
29804 #define RCC_APB1RSTSR1_UART8RSTS                RCC_APB1RSTSR1_UART8RSTS_Msk         /*!< UART8 reset */
29805 
29806 /****************  Bit definition for RCC_APB1RSTSR2 register  ****************/
29807 #define RCC_APB1RSTSR2_MDIOSRSTS_Pos            (5U)
29808 #define RCC_APB1RSTSR2_MDIOSRSTS_Msk            (0x1UL << RCC_APB1RSTSR2_MDIOSRSTS_Pos) /*!< 0x00000020 */
29809 #define RCC_APB1RSTSR2_MDIOSRSTS                RCC_APB1RSTSR2_MDIOSRSTS_Msk         /*!< MDIOS reset */
29810 #define RCC_APB1RSTSR2_FDCANRSTS_Pos            (8U)
29811 #define RCC_APB1RSTSR2_FDCANRSTS_Msk            (0x1UL << RCC_APB1RSTSR2_FDCANRSTS_Pos) /*!< 0x00000100 */
29812 #define RCC_APB1RSTSR2_FDCANRSTS                RCC_APB1RSTSR2_FDCANRSTS_Msk         /*!< FDCAN reset */
29813 #define RCC_APB1RSTSR2_UCPD1RSTS_Pos            (18U)
29814 #define RCC_APB1RSTSR2_UCPD1RSTS_Msk            (0x1UL << RCC_APB1RSTSR2_UCPD1RSTS_Pos) /*!< 0x00040000 */
29815 #define RCC_APB1RSTSR2_UCPD1RSTS                RCC_APB1RSTSR2_UCPD1RSTS_Msk         /*!< UCPD1 reset */
29816 
29817 /****************  Bit definition for RCC_APB2RSTSR register  *****************/
29818 #define RCC_APB2RSTSR_TIM1RSTS_Pos              (0U)
29819 #define RCC_APB2RSTSR_TIM1RSTS_Msk              (0x1UL << RCC_APB2RSTSR_TIM1RSTS_Pos) /*!< 0x00000001 */
29820 #define RCC_APB2RSTSR_TIM1RSTS                  RCC_APB2RSTSR_TIM1RSTS_Msk           /*!< TIM1 reset */
29821 #define RCC_APB2RSTSR_TIM8RSTS_Pos              (1U)
29822 #define RCC_APB2RSTSR_TIM8RSTS_Msk              (0x1UL << RCC_APB2RSTSR_TIM8RSTS_Pos) /*!< 0x00000002 */
29823 #define RCC_APB2RSTSR_TIM8RSTS                  RCC_APB2RSTSR_TIM8RSTS_Msk           /*!< TIM8 reset */
29824 #define RCC_APB2RSTSR_USART1RSTS_Pos            (4U)
29825 #define RCC_APB2RSTSR_USART1RSTS_Msk            (0x1UL << RCC_APB2RSTSR_USART1RSTS_Pos) /*!< 0x00000010 */
29826 #define RCC_APB2RSTSR_USART1RSTS                RCC_APB2RSTSR_USART1RSTS_Msk         /*!< USART1 reset */
29827 #define RCC_APB2RSTSR_USART6RSTS_Pos            (5U)
29828 #define RCC_APB2RSTSR_USART6RSTS_Msk            (0x1UL << RCC_APB2RSTSR_USART6RSTS_Pos) /*!< 0x00000020 */
29829 #define RCC_APB2RSTSR_USART6RSTS                RCC_APB2RSTSR_USART6RSTS_Msk         /*!< USART6 reset */
29830 #define RCC_APB2RSTSR_UART9RSTS_Pos             (6U)
29831 #define RCC_APB2RSTSR_UART9RSTS_Msk             (0x1UL << RCC_APB2RSTSR_UART9RSTS_Pos)/*!< 0x00000040 */
29832 #define RCC_APB2RSTSR_UART9RSTS                 RCC_APB2RSTSR_UART9RSTS_Msk          /*!< UART9 reset */
29833 #define RCC_APB2RSTSR_USART10RSTS_Pos           (7U)
29834 #define RCC_APB2RSTSR_USART10RSTS_Msk           (0x1UL << RCC_APB2RSTSR_USART10RSTS_Pos)  /*!< 0x00000080 */
29835 #define RCC_APB2RSTSR_USART10RSTS               RCC_APB2RSTSR_USART10RSTS_Msk        /*!< USART10 reset */
29836 #define RCC_APB2RSTSR_SPI1RSTS_Pos              (12U)
29837 #define RCC_APB2RSTSR_SPI1RSTS_Msk              (0x1UL << RCC_APB2RSTSR_SPI1RSTS_Pos) /*!< 0x00001000 */
29838 #define RCC_APB2RSTSR_SPI1RSTS                  RCC_APB2RSTSR_SPI1RSTS_Msk           /*!< SPI1 reset */
29839 #define RCC_APB2RSTSR_SPI4RSTS_Pos              (13U)
29840 #define RCC_APB2RSTSR_SPI4RSTS_Msk              (0x1UL << RCC_APB2RSTSR_SPI4RSTS_Pos) /*!< 0x00002000 */
29841 #define RCC_APB2RSTSR_SPI4RSTS                  RCC_APB2RSTSR_SPI4RSTS_Msk           /*!< SPI4 reset */
29842 #define RCC_APB2RSTSR_TIM18RSTS_Pos             (15U)
29843 #define RCC_APB2RSTSR_TIM18RSTS_Msk             (0x1UL << RCC_APB2RSTSR_TIM18RSTS_Pos)/*!< 0x00008000 */
29844 #define RCC_APB2RSTSR_TIM18RSTS                 RCC_APB2RSTSR_TIM18RSTS_Msk          /*!< TIM18 reset */
29845 #define RCC_APB2RSTSR_TIM15RSTS_Pos             (16U)
29846 #define RCC_APB2RSTSR_TIM15RSTS_Msk             (0x1UL << RCC_APB2RSTSR_TIM15RSTS_Pos)/*!< 0x00010000 */
29847 #define RCC_APB2RSTSR_TIM15RSTS                 RCC_APB2RSTSR_TIM15RSTS_Msk          /*!< TIM15 reset */
29848 #define RCC_APB2RSTSR_TIM16RSTS_Pos             (17U)
29849 #define RCC_APB2RSTSR_TIM16RSTS_Msk             (0x1UL << RCC_APB2RSTSR_TIM16RSTS_Pos)/*!< 0x00020000 */
29850 #define RCC_APB2RSTSR_TIM16RSTS                 RCC_APB2RSTSR_TIM16RSTS_Msk          /*!< TIM16 reset */
29851 #define RCC_APB2RSTSR_TIM17RSTS_Pos             (18U)
29852 #define RCC_APB2RSTSR_TIM17RSTS_Msk             (0x1UL << RCC_APB2RSTSR_TIM17RSTS_Pos)/*!< 0x00040000 */
29853 #define RCC_APB2RSTSR_TIM17RSTS                 RCC_APB2RSTSR_TIM17RSTS_Msk          /*!< TIM17 reset */
29854 #define RCC_APB2RSTSR_TIM9RSTS_Pos              (19U)
29855 #define RCC_APB2RSTSR_TIM9RSTS_Msk              (0x1UL << RCC_APB2RSTSR_TIM9RSTS_Pos) /*!< 0x00080000 */
29856 #define RCC_APB2RSTSR_TIM9RSTS                  RCC_APB2RSTSR_TIM9RSTS_Msk           /*!< TIM9 reset */
29857 #define RCC_APB2RSTSR_SPI5RSTS_Pos              (20U)
29858 #define RCC_APB2RSTSR_SPI5RSTS_Msk              (0x1UL << RCC_APB2RSTSR_SPI5RSTS_Pos) /*!< 0x00100000 */
29859 #define RCC_APB2RSTSR_SPI5RSTS                  RCC_APB2RSTSR_SPI5RSTS_Msk           /*!< SPI5 reset */
29860 #define RCC_APB2RSTSR_SAI1RSTS_Pos              (21U)
29861 #define RCC_APB2RSTSR_SAI1RSTS_Msk              (0x1UL << RCC_APB2RSTSR_SAI1RSTS_Pos) /*!< 0x00200000 */
29862 #define RCC_APB2RSTSR_SAI1RSTS                  RCC_APB2RSTSR_SAI1RSTS_Msk           /*!< SAI1 reset */
29863 #define RCC_APB2RSTSR_SAI2RSTS_Pos              (22U)
29864 #define RCC_APB2RSTSR_SAI2RSTS_Msk              (0x1UL << RCC_APB2RSTSR_SAI2RSTS_Pos) /*!< 0x00400000 */
29865 #define RCC_APB2RSTSR_SAI2RSTS                  RCC_APB2RSTSR_SAI2RSTS_Msk           /*!< SAI2 reset */
29866 
29867 /****************  Bit definition for RCC_APB4RSTSR1 register  ****************/
29868 #define RCC_APB4RSTSR1_HDPRSTS_Pos              (2U)
29869 #define RCC_APB4RSTSR1_HDPRSTS_Msk              (0x1UL << RCC_APB4RSTSR1_HDPRSTS_Pos) /*!< 0x00000004 */
29870 #define RCC_APB4RSTSR1_HDPRSTS                  RCC_APB4RSTSR1_HDPRSTS_Msk           /*!< HDP reset */
29871 #define RCC_APB4RSTSR1_LPUART1RSTS_Pos          (3U)
29872 #define RCC_APB4RSTSR1_LPUART1RSTS_Msk          (0x1UL << RCC_APB4RSTSR1_LPUART1RSTS_Pos)   /*!< 0x00000008 */
29873 #define RCC_APB4RSTSR1_LPUART1RSTS              RCC_APB4RSTSR1_LPUART1RSTS_Msk       /*!< LPUART1 reset */
29874 #define RCC_APB4RSTSR1_SPI6RSTS_Pos             (5U)
29875 #define RCC_APB4RSTSR1_SPI6RSTS_Msk             (0x1UL << RCC_APB4RSTSR1_SPI6RSTS_Pos)/*!< 0x00000020 */
29876 #define RCC_APB4RSTSR1_SPI6RSTS                 RCC_APB4RSTSR1_SPI6RSTS_Msk          /*!< SPI6 reset */
29877 #define RCC_APB4RSTSR1_I2C4RSTS_Pos             (7U)
29878 #define RCC_APB4RSTSR1_I2C4RSTS_Msk             (0x1UL << RCC_APB4RSTSR1_I2C4RSTS_Pos)/*!< 0x00000080 */
29879 #define RCC_APB4RSTSR1_I2C4RSTS                 RCC_APB4RSTSR1_I2C4RSTS_Msk          /*!< I2C4 reset */
29880 #define RCC_APB4RSTSR1_LPTIM2RSTS_Pos           (9U)
29881 #define RCC_APB4RSTSR1_LPTIM2RSTS_Msk           (0x1UL << RCC_APB4RSTSR1_LPTIM2RSTS_Pos)  /*!< 0x00000200 */
29882 #define RCC_APB4RSTSR1_LPTIM2RSTS               RCC_APB4RSTSR1_LPTIM2RSTS_Msk        /*!< LPTIM2 reset */
29883 #define RCC_APB4RSTSR1_LPTIM3RSTS_Pos           (10U)
29884 #define RCC_APB4RSTSR1_LPTIM3RSTS_Msk           (0x1UL << RCC_APB4RSTSR1_LPTIM3RSTS_Pos)  /*!< 0x00000400 */
29885 #define RCC_APB4RSTSR1_LPTIM3RSTS               RCC_APB4RSTSR1_LPTIM3RSTS_Msk        /*!< LPTIM3 reset */
29886 #define RCC_APB4RSTSR1_LPTIM4RSTS_Pos           (11U)
29887 #define RCC_APB4RSTSR1_LPTIM4RSTS_Msk           (0x1UL << RCC_APB4RSTSR1_LPTIM4RSTS_Pos)  /*!< 0x00000800 */
29888 #define RCC_APB4RSTSR1_LPTIM4RSTS               RCC_APB4RSTSR1_LPTIM4RSTS_Msk        /*!< LPTIM4 reset */
29889 #define RCC_APB4RSTSR1_LPTIM5RSTS_Pos           (12U)
29890 #define RCC_APB4RSTSR1_LPTIM5RSTS_Msk           (0x1UL << RCC_APB4RSTSR1_LPTIM5RSTS_Pos)  /*!< 0x00001000 */
29891 #define RCC_APB4RSTSR1_LPTIM5RSTS               RCC_APB4RSTSR1_LPTIM5RSTS_Msk        /*!< LPTIM5 reset */
29892 #define RCC_APB4RSTSR1_VREFBUFRSTS_Pos          (15U)
29893 #define RCC_APB4RSTSR1_VREFBUFRSTS_Msk          (0x1UL << RCC_APB4RSTSR1_VREFBUFRSTS_Pos)   /*!< 0x00008000 */
29894 #define RCC_APB4RSTSR1_VREFBUFRSTS              RCC_APB4RSTSR1_VREFBUFRSTS_Msk       /*!< VREFBUF reset */
29895 #define RCC_APB4RSTSR1_RTCRSTS_Pos              (16U)
29896 #define RCC_APB4RSTSR1_RTCRSTS_Msk              (0x1UL << RCC_APB4RSTSR1_RTCRSTS_Pos) /*!< 0x00010000 */
29897 #define RCC_APB4RSTSR1_RTCRSTS                  RCC_APB4RSTSR1_RTCRSTS_Msk           /*!< RTC reset */
29898 
29899 /****************  Bit definition for RCC_APB4RSTSR2 register  ****************/
29900 #define RCC_APB4RSTSR2_SYSCFGRSTS_Pos           (0U)
29901 #define RCC_APB4RSTSR2_SYSCFGRSTS_Msk           (0x1UL << RCC_APB4RSTSR2_SYSCFGRSTS_Pos)  /*!< 0x00000001 */
29902 #define RCC_APB4RSTSR2_SYSCFGRSTS               RCC_APB4RSTSR2_SYSCFGRSTS_Msk        /*!< SYSCFG reset */
29903 #define RCC_APB4RSTSR2_DTSRSTS_Pos              (2U)
29904 #define RCC_APB4RSTSR2_DTSRSTS_Msk              (0x1UL << RCC_APB4RSTSR2_DTSRSTS_Pos) /*!< 0x00000004 */
29905 #define RCC_APB4RSTSR2_DTSRSTS                  RCC_APB4RSTSR2_DTSRSTS_Msk           /*!< DTS reset */
29906 
29907 /****************  Bit definition for RCC_APB5RSTSR register  *****************/
29908 #define RCC_APB5RSTSR_LTDCRSTS_Pos              (1U)
29909 #define RCC_APB5RSTSR_LTDCRSTS_Msk              (0x1UL << RCC_APB5RSTSR_LTDCRSTS_Pos) /*!< 0x00000002 */
29910 #define RCC_APB5RSTSR_LTDCRSTS                  RCC_APB5RSTSR_LTDCRSTS_Msk           /*!< LTDC reset */
29911 #define RCC_APB5RSTSR_DCMIPPRSTS_Pos            (2U)
29912 #define RCC_APB5RSTSR_DCMIPPRSTS_Msk            (0x1UL << RCC_APB5RSTSR_DCMIPPRSTS_Pos) /*!< 0x00000004 */
29913 #define RCC_APB5RSTSR_DCMIPPRSTS                RCC_APB5RSTSR_DCMIPPRSTS_Msk         /*!< DCMIPP reset */
29914 #define RCC_APB5RSTSR_GFXTIMRSTS_Pos            (4U)
29915 #define RCC_APB5RSTSR_GFXTIMRSTS_Msk            (0x1UL << RCC_APB5RSTSR_GFXTIMRSTS_Pos) /*!< 0x00000010 */
29916 #define RCC_APB5RSTSR_GFXTIMRSTS                RCC_APB5RSTSR_GFXTIMRSTS_Msk         /*!< GFXTIM reset */
29917 #define RCC_APB5RSTSR_VENCRSTS_Pos              (5U)
29918 #define RCC_APB5RSTSR_VENCRSTS_Msk              (0x1UL << RCC_APB5RSTSR_VENCRSTS_Pos) /*!< 0x00000020 */
29919 #define RCC_APB5RSTSR_VENCRSTS                  RCC_APB5RSTSR_VENCRSTS_Msk           /*!< VENC reset */
29920 #define RCC_APB5RSTSR_CSIRSTS_Pos               (6U)
29921 #define RCC_APB5RSTSR_CSIRSTS_Msk               (0x1UL << RCC_APB5RSTSR_CSIRSTS_Pos)  /*!< 0x00000040 */
29922 #define RCC_APB5RSTSR_CSIRSTS                   RCC_APB5RSTSR_CSIRSTS_Msk            /*!< CSI reset */
29923 
29924 /*****************  Bit definition for RCC_DIVENSR register  ******************/
29925 #define RCC_DIVENSR_IC1ENS_Pos                  (0U)
29926 #define RCC_DIVENSR_IC1ENS_Msk                  (0x1UL << RCC_DIVENSR_IC1ENS_Pos)     /*!< 0x00000001 */
29927 #define RCC_DIVENSR_IC1ENS                      RCC_DIVENSR_IC1ENS_Msk               /*!< IC1 enable */
29928 #define RCC_DIVENSR_IC2ENS_Pos                  (1U)
29929 #define RCC_DIVENSR_IC2ENS_Msk                  (0x1UL << RCC_DIVENSR_IC2ENS_Pos)     /*!< 0x00000002 */
29930 #define RCC_DIVENSR_IC2ENS                      RCC_DIVENSR_IC2ENS_Msk               /*!< IC2 enable */
29931 #define RCC_DIVENSR_IC3ENS_Pos                  (2U)
29932 #define RCC_DIVENSR_IC3ENS_Msk                  (0x1UL << RCC_DIVENSR_IC3ENS_Pos)     /*!< 0x00000004 */
29933 #define RCC_DIVENSR_IC3ENS                      RCC_DIVENSR_IC3ENS_Msk               /*!< IC3 enable */
29934 #define RCC_DIVENSR_IC4ENS_Pos                  (3U)
29935 #define RCC_DIVENSR_IC4ENS_Msk                  (0x1UL << RCC_DIVENSR_IC4ENS_Pos)     /*!< 0x00000008 */
29936 #define RCC_DIVENSR_IC4ENS                      RCC_DIVENSR_IC4ENS_Msk               /*!< IC4 enable */
29937 #define RCC_DIVENSR_IC5ENS_Pos                  (4U)
29938 #define RCC_DIVENSR_IC5ENS_Msk                  (0x1UL << RCC_DIVENSR_IC5ENS_Pos)     /*!< 0x00000010 */
29939 #define RCC_DIVENSR_IC5ENS                      RCC_DIVENSR_IC5ENS_Msk               /*!< IC5 enable */
29940 #define RCC_DIVENSR_IC6ENS_Pos                  (5U)
29941 #define RCC_DIVENSR_IC6ENS_Msk                  (0x1UL << RCC_DIVENSR_IC6ENS_Pos)     /*!< 0x00000020 */
29942 #define RCC_DIVENSR_IC6ENS                      RCC_DIVENSR_IC6ENS_Msk               /*!< IC6 enable */
29943 #define RCC_DIVENSR_IC7ENS_Pos                  (6U)
29944 #define RCC_DIVENSR_IC7ENS_Msk                  (0x1UL << RCC_DIVENSR_IC7ENS_Pos)     /*!< 0x00000040 */
29945 #define RCC_DIVENSR_IC7ENS                      RCC_DIVENSR_IC7ENS_Msk               /*!< IC7 enable */
29946 #define RCC_DIVENSR_IC8ENS_Pos                  (7U)
29947 #define RCC_DIVENSR_IC8ENS_Msk                  (0x1UL << RCC_DIVENSR_IC8ENS_Pos)     /*!< 0x00000080 */
29948 #define RCC_DIVENSR_IC8ENS                      RCC_DIVENSR_IC8ENS_Msk               /*!< IC8 enable */
29949 #define RCC_DIVENSR_IC9ENS_Pos                  (8U)
29950 #define RCC_DIVENSR_IC9ENS_Msk                  (0x1UL << RCC_DIVENSR_IC9ENS_Pos)     /*!< 0x00000100 */
29951 #define RCC_DIVENSR_IC9ENS                      RCC_DIVENSR_IC9ENS_Msk               /*!< IC9 enable */
29952 #define RCC_DIVENSR_IC10ENS_Pos                 (9U)
29953 #define RCC_DIVENSR_IC10ENS_Msk                 (0x1UL << RCC_DIVENSR_IC10ENS_Pos)    /*!< 0x00000200 */
29954 #define RCC_DIVENSR_IC10ENS                     RCC_DIVENSR_IC10ENS_Msk              /*!< IC10 enable */
29955 #define RCC_DIVENSR_IC11ENS_Pos                 (10U)
29956 #define RCC_DIVENSR_IC11ENS_Msk                 (0x1UL << RCC_DIVENSR_IC11ENS_Pos)    /*!< 0x00000400 */
29957 #define RCC_DIVENSR_IC11ENS                     RCC_DIVENSR_IC11ENS_Msk              /*!< IC11 enable */
29958 #define RCC_DIVENSR_IC12ENS_Pos                 (11U)
29959 #define RCC_DIVENSR_IC12ENS_Msk                 (0x1UL << RCC_DIVENSR_IC12ENS_Pos)    /*!< 0x00000800 */
29960 #define RCC_DIVENSR_IC12ENS                     RCC_DIVENSR_IC12ENS_Msk              /*!< IC12 enable */
29961 #define RCC_DIVENSR_IC13ENS_Pos                 (12U)
29962 #define RCC_DIVENSR_IC13ENS_Msk                 (0x1UL << RCC_DIVENSR_IC13ENS_Pos)    /*!< 0x00001000 */
29963 #define RCC_DIVENSR_IC13ENS                     RCC_DIVENSR_IC13ENS_Msk              /*!< IC13 enable */
29964 #define RCC_DIVENSR_IC14ENS_Pos                 (13U)
29965 #define RCC_DIVENSR_IC14ENS_Msk                 (0x1UL << RCC_DIVENSR_IC14ENS_Pos)    /*!< 0x00002000 */
29966 #define RCC_DIVENSR_IC14ENS                     RCC_DIVENSR_IC14ENS_Msk              /*!< IC14 enable */
29967 #define RCC_DIVENSR_IC15ENS_Pos                 (14U)
29968 #define RCC_DIVENSR_IC15ENS_Msk                 (0x1UL << RCC_DIVENSR_IC15ENS_Pos)    /*!< 0x00004000 */
29969 #define RCC_DIVENSR_IC15ENS                     RCC_DIVENSR_IC15ENS_Msk              /*!< IC15 enable */
29970 #define RCC_DIVENSR_IC16ENS_Pos                 (15U)
29971 #define RCC_DIVENSR_IC16ENS_Msk                 (0x1UL << RCC_DIVENSR_IC16ENS_Pos)    /*!< 0x00008000 */
29972 #define RCC_DIVENSR_IC16ENS                     RCC_DIVENSR_IC16ENS_Msk              /*!< IC16 enable */
29973 #define RCC_DIVENSR_IC17ENS_Pos                 (16U)
29974 #define RCC_DIVENSR_IC17ENS_Msk                 (0x1UL << RCC_DIVENSR_IC17ENS_Pos)    /*!< 0x00010000 */
29975 #define RCC_DIVENSR_IC17ENS                     RCC_DIVENSR_IC17ENS_Msk              /*!< IC17 enable */
29976 #define RCC_DIVENSR_IC18ENS_Pos                 (17U)
29977 #define RCC_DIVENSR_IC18ENS_Msk                 (0x1UL << RCC_DIVENSR_IC18ENS_Pos)    /*!< 0x00020000 */
29978 #define RCC_DIVENSR_IC18ENS                     RCC_DIVENSR_IC18ENS_Msk              /*!< IC18 enable */
29979 #define RCC_DIVENSR_IC19ENS_Pos                 (18U)
29980 #define RCC_DIVENSR_IC19ENS_Msk                 (0x1UL << RCC_DIVENSR_IC19ENS_Pos)    /*!< 0x00040000 */
29981 #define RCC_DIVENSR_IC19ENS                     RCC_DIVENSR_IC19ENS_Msk              /*!< IC19 enable */
29982 #define RCC_DIVENSR_IC20ENS_Pos                 (19U)
29983 #define RCC_DIVENSR_IC20ENS_Msk                 (0x1UL << RCC_DIVENSR_IC20ENS_Pos)    /*!< 0x00080000 */
29984 #define RCC_DIVENSR_IC20ENS                     RCC_DIVENSR_IC20ENS_Msk              /*!< IC20 enable */
29985 
29986 /*****************  Bit definition for RCC_BUSENSR register  ******************/
29987 #define RCC_BUSENSR_ACLKNENS_Pos                (0U)
29988 #define RCC_BUSENSR_ACLKNENS_Msk                (0x1UL << RCC_BUSENSR_ACLKNENS_Pos)   /*!< 0x00000001 */
29989 #define RCC_BUSENSR_ACLKNENS                    RCC_BUSENSR_ACLKNENS_Msk             /*!< ACLKN enable */
29990 #define RCC_BUSENSR_ACLKNCENS_Pos               (1U)
29991 #define RCC_BUSENSR_ACLKNCENS_Msk               (0x1UL << RCC_BUSENSR_ACLKNCENS_Pos)  /*!< 0x00000002 */
29992 #define RCC_BUSENSR_ACLKNCENS                   RCC_BUSENSR_ACLKNCENS_Msk            /*!< ACLKNC enable */
29993 #define RCC_BUSENSR_AHBMENS_Pos                 (2U)
29994 #define RCC_BUSENSR_AHBMENS_Msk                 (0x1UL << RCC_BUSENSR_AHBMENS_Pos)    /*!< 0x00000004 */
29995 #define RCC_BUSENSR_AHBMENS                     RCC_BUSENSR_AHBMENS_Msk              /*!< AHBM enable */
29996 #define RCC_BUSENSR_AHB1ENS_Pos                 (3U)
29997 #define RCC_BUSENSR_AHB1ENS_Msk                 (0x1UL << RCC_BUSENSR_AHB1ENS_Pos)    /*!< 0x00000008 */
29998 #define RCC_BUSENSR_AHB1ENS                     RCC_BUSENSR_AHB1ENS_Msk              /*!< AHB1 enable */
29999 #define RCC_BUSENSR_AHB2ENS_Pos                 (4U)
30000 #define RCC_BUSENSR_AHB2ENS_Msk                 (0x1UL << RCC_BUSENSR_AHB2ENS_Pos)    /*!< 0x00000010 */
30001 #define RCC_BUSENSR_AHB2ENS                     RCC_BUSENSR_AHB2ENS_Msk              /*!< AHB2 enable */
30002 #define RCC_BUSENSR_AHB3ENS_Pos                 (5U)
30003 #define RCC_BUSENSR_AHB3ENS_Msk                 (0x1UL << RCC_BUSENSR_AHB3ENS_Pos)    /*!< 0x00000020 */
30004 #define RCC_BUSENSR_AHB3ENS                     RCC_BUSENSR_AHB3ENS_Msk              /*!< AHB3 enable */
30005 #define RCC_BUSENSR_AHB4ENS_Pos                 (6U)
30006 #define RCC_BUSENSR_AHB4ENS_Msk                 (0x1UL << RCC_BUSENSR_AHB4ENS_Pos)    /*!< 0x00000040 */
30007 #define RCC_BUSENSR_AHB4ENS                     RCC_BUSENSR_AHB4ENS_Msk              /*!< AHB4 enable */
30008 #define RCC_BUSENSR_AHB5ENS_Pos                 (7U)
30009 #define RCC_BUSENSR_AHB5ENS_Msk                 (0x1UL << RCC_BUSENSR_AHB5ENS_Pos)    /*!< 0x00000080 */
30010 #define RCC_BUSENSR_AHB5ENS                     RCC_BUSENSR_AHB5ENS_Msk              /*!< AHB5 enable */
30011 #define RCC_BUSENSR_APB1ENS_Pos                 (8U)
30012 #define RCC_BUSENSR_APB1ENS_Msk                 (0x1UL << RCC_BUSENSR_APB1ENS_Pos)    /*!< 0x00000100 */
30013 #define RCC_BUSENSR_APB1ENS                     RCC_BUSENSR_APB1ENS_Msk              /*!< APB1 enable */
30014 #define RCC_BUSENSR_APB2ENS_Pos                 (9U)
30015 #define RCC_BUSENSR_APB2ENS_Msk                 (0x1UL << RCC_BUSENSR_APB2ENS_Pos)    /*!< 0x00000200 */
30016 #define RCC_BUSENSR_APB2ENS                     RCC_BUSENSR_APB2ENS_Msk              /*!< APB2 enable */
30017 #define RCC_BUSENSR_APB3ENS_Pos                 (10U)
30018 #define RCC_BUSENSR_APB3ENS_Msk                 (0x1UL << RCC_BUSENSR_APB3ENS_Pos)    /*!< 0x00000400 */
30019 #define RCC_BUSENSR_APB3ENS                     RCC_BUSENSR_APB3ENS_Msk              /*!< APB3 enable */
30020 #define RCC_BUSENSR_APB4ENS_Pos                 (11U)
30021 #define RCC_BUSENSR_APB4ENS_Msk                 (0x1UL << RCC_BUSENSR_APB4ENS_Pos)    /*!< 0x00000800 */
30022 #define RCC_BUSENSR_APB4ENS                     RCC_BUSENSR_APB4ENS_Msk              /*!< APB4 enable */
30023 #define RCC_BUSENSR_APB5ENS_Pos                 (12U)
30024 #define RCC_BUSENSR_APB5ENS_Msk                 (0x1UL << RCC_BUSENSR_APB5ENS_Pos)    /*!< 0x00001000 */
30025 #define RCC_BUSENSR_APB5ENS                     RCC_BUSENSR_APB5ENS_Msk              /*!< APB5 enable */
30026 
30027 /*****************  Bit definition for RCC_MISCENSR register  *****************/
30028 #define RCC_MISCENSR_DBGENS_Pos                 (0U)
30029 #define RCC_MISCENSR_DBGENS_Msk                 (0x1UL << RCC_MISCENSR_DBGENS_Pos)    /*!< 0x00000001 */
30030 #define RCC_MISCENSR_DBGENS                     RCC_MISCENSR_DBGENS_Msk              /*!< DBG enable */
30031 #define RCC_MISCENSR_MCO1ENS_Pos                (1U)
30032 #define RCC_MISCENSR_MCO1ENS_Msk                (0x1UL << RCC_MISCENSR_MCO1ENS_Pos)   /*!< 0x00000002 */
30033 #define RCC_MISCENSR_MCO1ENS                    RCC_MISCENSR_MCO1ENS_Msk             /*!< MCO1 enable */
30034 #define RCC_MISCENSR_MCO2ENS_Pos                (2U)
30035 #define RCC_MISCENSR_MCO2ENS_Msk                (0x1UL << RCC_MISCENSR_MCO2ENS_Pos)   /*!< 0x00000004 */
30036 #define RCC_MISCENSR_MCO2ENS                    RCC_MISCENSR_MCO2ENS_Msk             /*!< MCO2 enable */
30037 #define RCC_MISCENSR_XSPIPHYCOMPENS_Pos         (3U)
30038 #define RCC_MISCENSR_XSPIPHYCOMPENS_Msk         (0x1UL << RCC_MISCENSR_XSPIPHYCOMPENS_Pos)    /*!< 0x00000008 */
30039 #define RCC_MISCENSR_XSPIPHYCOMPENS             RCC_MISCENSR_XSPIPHYCOMPENS_Msk      /*!< XSPIPHYCOMP enable */
30040 #define RCC_MISCENSR_PERENS_Pos                 (6U)
30041 #define RCC_MISCENSR_PERENS_Msk                 (0x1UL << RCC_MISCENSR_PERENS_Pos)    /*!< 0x00000040 */
30042 #define RCC_MISCENSR_PERENS                     RCC_MISCENSR_PERENS_Msk              /*!< PER enable */
30043 
30044 /*****************  Bit definition for RCC_MEMENSR register  ******************/
30045 #define RCC_MEMENSR_AXISRAM3ENS_Pos             (0U)
30046 #define RCC_MEMENSR_AXISRAM3ENS_Msk             (0x1UL << RCC_MEMENSR_AXISRAM3ENS_Pos)/*!< 0x00000001 */
30047 #define RCC_MEMENSR_AXISRAM3ENS                 RCC_MEMENSR_AXISRAM3ENS_Msk          /*!< AXISRAM3 enable */
30048 #define RCC_MEMENSR_AXISRAM4ENS_Pos             (1U)
30049 #define RCC_MEMENSR_AXISRAM4ENS_Msk             (0x1UL << RCC_MEMENSR_AXISRAM4ENS_Pos)/*!< 0x00000002 */
30050 #define RCC_MEMENSR_AXISRAM4ENS                 RCC_MEMENSR_AXISRAM4ENS_Msk          /*!< AXISRAM4 enable */
30051 #define RCC_MEMENSR_AXISRAM5ENS_Pos             (2U)
30052 #define RCC_MEMENSR_AXISRAM5ENS_Msk             (0x1UL << RCC_MEMENSR_AXISRAM5ENS_Pos)/*!< 0x00000004 */
30053 #define RCC_MEMENSR_AXISRAM5ENS                 RCC_MEMENSR_AXISRAM5ENS_Msk          /*!< AXISRAM5 enable */
30054 #define RCC_MEMENSR_AXISRAM6ENS_Pos             (3U)
30055 #define RCC_MEMENSR_AXISRAM6ENS_Msk             (0x1UL << RCC_MEMENSR_AXISRAM6ENS_Pos)/*!< 0x00000008 */
30056 #define RCC_MEMENSR_AXISRAM6ENS                 RCC_MEMENSR_AXISRAM6ENS_Msk          /*!< AXISRAM6 enable */
30057 #define RCC_MEMENSR_AHBSRAM1ENS_Pos             (4U)
30058 #define RCC_MEMENSR_AHBSRAM1ENS_Msk             (0x1UL << RCC_MEMENSR_AHBSRAM1ENS_Pos)/*!< 0x00000010 */
30059 #define RCC_MEMENSR_AHBSRAM1ENS                 RCC_MEMENSR_AHBSRAM1ENS_Msk          /*!< AHBSRAM1 enable */
30060 #define RCC_MEMENSR_AHBSRAM2ENS_Pos             (5U)
30061 #define RCC_MEMENSR_AHBSRAM2ENS_Msk             (0x1UL << RCC_MEMENSR_AHBSRAM2ENS_Pos)/*!< 0x00000020 */
30062 #define RCC_MEMENSR_AHBSRAM2ENS                 RCC_MEMENSR_AHBSRAM2ENS_Msk          /*!< AHBSRAM2 enable */
30063 #define RCC_MEMENSR_BKPSRAMENS_Pos              (6U)
30064 #define RCC_MEMENSR_BKPSRAMENS_Msk              (0x1UL << RCC_MEMENSR_BKPSRAMENS_Pos) /*!< 0x00000040 */
30065 #define RCC_MEMENSR_BKPSRAMENS                  RCC_MEMENSR_BKPSRAMENS_Msk           /*!< BKPSRAM enable */
30066 #define RCC_MEMENSR_AXISRAM1ENS_Pos             (7U)
30067 #define RCC_MEMENSR_AXISRAM1ENS_Msk             (0x1UL << RCC_MEMENSR_AXISRAM1ENS_Pos)/*!< 0x00000080 */
30068 #define RCC_MEMENSR_AXISRAM1ENS                 RCC_MEMENSR_AXISRAM1ENS_Msk          /*!< AXISRAM1 enable */
30069 #define RCC_MEMENSR_AXISRAM2ENS_Pos             (8U)
30070 #define RCC_MEMENSR_AXISRAM2ENS_Msk             (0x1UL << RCC_MEMENSR_AXISRAM2ENS_Pos)/*!< 0x00000100 */
30071 #define RCC_MEMENSR_AXISRAM2ENS                 RCC_MEMENSR_AXISRAM2ENS_Msk          /*!< AXISRAM2 enable */
30072 #define RCC_MEMENSR_FLEXRAMENS_Pos              (9U)
30073 #define RCC_MEMENSR_FLEXRAMENS_Msk              (0x1UL << RCC_MEMENSR_FLEXRAMENS_Pos) /*!< 0x00000200 */
30074 #define RCC_MEMENSR_FLEXRAMENS                  RCC_MEMENSR_FLEXRAMENS_Msk           /*!< FLEXRAM enable */
30075 #define RCC_MEMENSR_CACHEAXIRAMENS_Pos          (10U)
30076 #define RCC_MEMENSR_CACHEAXIRAMENS_Msk          (0x1UL << RCC_MEMENSR_CACHEAXIRAMENS_Pos)   /*!< 0x00000400 */
30077 #define RCC_MEMENSR_CACHEAXIRAMENS              RCC_MEMENSR_CACHEAXIRAMENS_Msk       /*!< CACHEAXIRAM enable */
30078 #define RCC_MEMENSR_VENCRAMENS_Pos              (11U)
30079 #define RCC_MEMENSR_VENCRAMENS_Msk              (0x1UL << RCC_MEMENSR_VENCRAMENS_Pos) /*!< 0x00000800 */
30080 #define RCC_MEMENSR_VENCRAMENS                  RCC_MEMENSR_VENCRAMENS_Msk           /*!< VENCRAM enable */
30081 #define RCC_MEMENSR_BOOTROMENS_Pos              (12U)
30082 #define RCC_MEMENSR_BOOTROMENS_Msk              (0x1UL << RCC_MEMENSR_BOOTROMENS_Pos) /*!< 0x00001000 */
30083 #define RCC_MEMENSR_BOOTROMENS                  RCC_MEMENSR_BOOTROMENS_Msk           /*!< Boot ROM enable */
30084 
30085 /*****************  Bit definition for RCC_AHB1ENSR register  *****************/
30086 #define RCC_AHB1ENSR_GPDMA1ENS_Pos              (4U)
30087 #define RCC_AHB1ENSR_GPDMA1ENS_Msk              (0x1UL << RCC_AHB1ENSR_GPDMA1ENS_Pos) /*!< 0x00000010 */
30088 #define RCC_AHB1ENSR_GPDMA1ENS                  RCC_AHB1ENSR_GPDMA1ENS_Msk           /*!< GPDMA1 enable */
30089 #define RCC_AHB1ENSR_ADC12ENS_Pos               (5U)
30090 #define RCC_AHB1ENSR_ADC12ENS_Msk               (0x1UL << RCC_AHB1ENSR_ADC12ENS_Pos)  /*!< 0x00000020 */
30091 #define RCC_AHB1ENSR_ADC12ENS                   RCC_AHB1ENSR_ADC12ENS_Msk            /*!< ADC12 enable */
30092 
30093 /*****************  Bit definition for RCC_AHB2ENSR register  *****************/
30094 #define RCC_AHB2ENSR_RAMCFGENS_Pos              (12U)
30095 #define RCC_AHB2ENSR_RAMCFGENS_Msk              (0x1UL << RCC_AHB2ENSR_RAMCFGENS_Pos) /*!< 0x00001000 */
30096 #define RCC_AHB2ENSR_RAMCFGENS                  RCC_AHB2ENSR_RAMCFGENS_Msk           /*!< RAMCFG enable */
30097 #define RCC_AHB2ENSR_MDF1ENS_Pos                (16U)
30098 #define RCC_AHB2ENSR_MDF1ENS_Msk                (0x1UL << RCC_AHB2ENSR_MDF1ENS_Pos)   /*!< 0x00010000 */
30099 #define RCC_AHB2ENSR_MDF1ENS                    RCC_AHB2ENSR_MDF1ENS_Msk             /*!< MDF1 enable */
30100 #define RCC_AHB2ENSR_ADF1ENS_Pos                (17U)
30101 #define RCC_AHB2ENSR_ADF1ENS_Msk                (0x1UL << RCC_AHB2ENSR_ADF1ENS_Pos)   /*!< 0x00020000 */
30102 #define RCC_AHB2ENSR_ADF1ENS                    RCC_AHB2ENSR_ADF1ENS_Msk             /*!< ADF1 enable */
30103 
30104 /*****************  Bit definition for RCC_AHB3ENSR register  *****************/
30105 #define RCC_AHB3ENSR_RNGENS_Pos                 (0U)
30106 #define RCC_AHB3ENSR_RNGENS_Msk                 (0x1UL << RCC_AHB3ENSR_RNGENS_Pos)    /*!< 0x00000001 */
30107 #define RCC_AHB3ENSR_RNGENS                     RCC_AHB3ENSR_RNGENS_Msk              /*!< RNG enable */
30108 #define RCC_AHB3ENSR_HASHENS_Pos                (1U)
30109 #define RCC_AHB3ENSR_HASHENS_Msk                (0x1UL << RCC_AHB3ENSR_HASHENS_Pos)   /*!< 0x00000002 */
30110 #define RCC_AHB3ENSR_HASHENS                    RCC_AHB3ENSR_HASHENS_Msk             /*!< HASH enable */
30111 #define RCC_AHB3ENSR_CRYPENS_Pos                (2U)
30112 #define RCC_AHB3ENSR_CRYPENS_Msk                (0x1UL << RCC_AHB3ENSR_CRYPENS_Pos)   /*!< 0x00000004 */
30113 #define RCC_AHB3ENSR_CRYPENS                    RCC_AHB3ENSR_CRYPENS_Msk             /*!< CRYP enable */
30114 #define RCC_AHB3ENSR_SAESENS_Pos                (4U)
30115 #define RCC_AHB3ENSR_SAESENS_Msk                (0x1UL << RCC_AHB3ENSR_SAESENS_Pos)   /*!< 0x00000010 */
30116 #define RCC_AHB3ENSR_SAESENS                    RCC_AHB3ENSR_SAESENS_Msk             /*!< SAES enable */
30117 #define RCC_AHB3ENSR_PKAENS_Pos                 (8U)
30118 #define RCC_AHB3ENSR_PKAENS_Msk                 (0x1UL << RCC_AHB3ENSR_PKAENS_Pos)    /*!< 0x00000100 */
30119 #define RCC_AHB3ENSR_PKAENS                     RCC_AHB3ENSR_PKAENS_Msk              /*!< PKA enable */
30120 #define RCC_AHB3ENSR_RIFSCENS_Pos               (9U)
30121 #define RCC_AHB3ENSR_RIFSCENS_Msk               (0x1UL << RCC_AHB3ENSR_RIFSCENS_Pos)  /*!< 0x00000200 */
30122 #define RCC_AHB3ENSR_RIFSCENS                   RCC_AHB3ENSR_RIFSCENS_Msk            /*!< RIFSC enable */
30123 #define RCC_AHB3ENSR_IACENS_Pos                 (10U)
30124 #define RCC_AHB3ENSR_IACENS_Msk                 (0x1UL << RCC_AHB3ENSR_IACENS_Pos)    /*!< 0x00000400 */
30125 #define RCC_AHB3ENSR_IACENS                     RCC_AHB3ENSR_IACENS_Msk              /*!< IAC enable */
30126 #define RCC_AHB3ENSR_RISAFENS_Pos               (14U)
30127 #define RCC_AHB3ENSR_RISAFENS_Msk               (0x1UL << RCC_AHB3ENSR_RISAFENS_Pos)  /*!< 0x00004000 */
30128 #define RCC_AHB3ENSR_RISAFENS                   RCC_AHB3ENSR_RISAFENS_Msk            /*!< RISAF enable */
30129 
30130 /*****************  Bit definition for RCC_AHB4ENSR register  *****************/
30131 #define RCC_AHB4ENSR_GPIOAENS_Pos               (0U)
30132 #define RCC_AHB4ENSR_GPIOAENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOAENS_Pos)  /*!< 0x00000001 */
30133 #define RCC_AHB4ENSR_GPIOAENS                   RCC_AHB4ENSR_GPIOAENS_Msk            /*!< GPIO A enable */
30134 #define RCC_AHB4ENSR_GPIOBENS_Pos               (1U)
30135 #define RCC_AHB4ENSR_GPIOBENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOBENS_Pos)  /*!< 0x00000002 */
30136 #define RCC_AHB4ENSR_GPIOBENS                   RCC_AHB4ENSR_GPIOBENS_Msk            /*!< GPIO B enable */
30137 #define RCC_AHB4ENSR_GPIOCENS_Pos               (2U)
30138 #define RCC_AHB4ENSR_GPIOCENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOCENS_Pos)  /*!< 0x00000004 */
30139 #define RCC_AHB4ENSR_GPIOCENS                   RCC_AHB4ENSR_GPIOCENS_Msk            /*!< GPIO C enable */
30140 #define RCC_AHB4ENSR_GPIODENS_Pos               (3U)
30141 #define RCC_AHB4ENSR_GPIODENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIODENS_Pos)  /*!< 0x00000008 */
30142 #define RCC_AHB4ENSR_GPIODENS                   RCC_AHB4ENSR_GPIODENS_Msk            /*!< GPIO D enable */
30143 #define RCC_AHB4ENSR_GPIOEENS_Pos               (4U)
30144 #define RCC_AHB4ENSR_GPIOEENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOEENS_Pos)  /*!< 0x00000010 */
30145 #define RCC_AHB4ENSR_GPIOEENS                   RCC_AHB4ENSR_GPIOEENS_Msk            /*!< GPIO E enable */
30146 #define RCC_AHB4ENSR_GPIOFENS_Pos               (5U)
30147 #define RCC_AHB4ENSR_GPIOFENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOFENS_Pos)  /*!< 0x00000020 */
30148 #define RCC_AHB4ENSR_GPIOFENS                   RCC_AHB4ENSR_GPIOFENS_Msk            /*!< GPIO F enable */
30149 #define RCC_AHB4ENSR_GPIOGENS_Pos               (6U)
30150 #define RCC_AHB4ENSR_GPIOGENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOGENS_Pos)  /*!< 0x00000040 */
30151 #define RCC_AHB4ENSR_GPIOGENS                   RCC_AHB4ENSR_GPIOGENS_Msk            /*!< GPIO G enable */
30152 #define RCC_AHB4ENSR_GPIOHENS_Pos               (7U)
30153 #define RCC_AHB4ENSR_GPIOHENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOHENS_Pos)  /*!< 0x00000080 */
30154 #define RCC_AHB4ENSR_GPIOHENS                   RCC_AHB4ENSR_GPIOHENS_Msk            /*!< GPIO H enable */
30155 #define RCC_AHB4ENSR_GPIONENS_Pos               (13U)
30156 #define RCC_AHB4ENSR_GPIONENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIONENS_Pos)  /*!< 0x00002000 */
30157 #define RCC_AHB4ENSR_GPIONENS                   RCC_AHB4ENSR_GPIONENS_Msk            /*!< GPIO N enable */
30158 #define RCC_AHB4ENSR_GPIOOENS_Pos               (14U)
30159 #define RCC_AHB4ENSR_GPIOOENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOOENS_Pos)  /*!< 0x00004000 */
30160 #define RCC_AHB4ENSR_GPIOOENS                   RCC_AHB4ENSR_GPIOOENS_Msk            /*!< GPIO O enable */
30161 #define RCC_AHB4ENSR_GPIOPENS_Pos               (15U)
30162 #define RCC_AHB4ENSR_GPIOPENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOPENS_Pos)  /*!< 0x00008000 */
30163 #define RCC_AHB4ENSR_GPIOPENS                   RCC_AHB4ENSR_GPIOPENS_Msk            /*!< GPIO P enable */
30164 #define RCC_AHB4ENSR_GPIOQENS_Pos               (16U)
30165 #define RCC_AHB4ENSR_GPIOQENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOQENS_Pos)  /*!< 0x00010000 */
30166 #define RCC_AHB4ENSR_GPIOQENS                   RCC_AHB4ENSR_GPIOQENS_Msk            /*!< GPIO Q enable */
30167 #define RCC_AHB4ENSR_PWRENS_Pos                 (18U)
30168 #define RCC_AHB4ENSR_PWRENS_Msk                 (0x1UL << RCC_AHB4ENSR_PWRENS_Pos)    /*!< 0x00040000 */
30169 #define RCC_AHB4ENSR_PWRENS                     RCC_AHB4ENSR_PWRENS_Msk              /*!< PWR enable */
30170 #define RCC_AHB4ENSR_CRCENS_Pos                 (19U)
30171 #define RCC_AHB4ENSR_CRCENS_Msk                 (0x1UL << RCC_AHB4ENSR_CRCENS_Pos)    /*!< 0x00080000 */
30172 #define RCC_AHB4ENSR_CRCENS                     RCC_AHB4ENSR_CRCENS_Msk              /*!< CRC enable */
30173 
30174 /*****************  Bit definition for RCC_AHB5ENSR register  *****************/
30175 #define RCC_AHB5ENSR_HPDMA1ENS_Pos              (0U)
30176 #define RCC_AHB5ENSR_HPDMA1ENS_Msk              (0x1UL << RCC_AHB5ENSR_HPDMA1ENS_Pos) /*!< 0x00000001 */
30177 #define RCC_AHB5ENSR_HPDMA1ENS                  RCC_AHB5ENSR_HPDMA1ENS_Msk           /*!< HPDMA1 enable */
30178 #define RCC_AHB5ENSR_DMA2DENS_Pos               (1U)
30179 #define RCC_AHB5ENSR_DMA2DENS_Msk               (0x1UL << RCC_AHB5ENSR_DMA2DENS_Pos)  /*!< 0x00000002 */
30180 #define RCC_AHB5ENSR_DMA2DENS                   RCC_AHB5ENSR_DMA2DENS_Msk            /*!< DMA2D enable */
30181 #define RCC_AHB5ENSR_JPEGENS_Pos                (3U)
30182 #define RCC_AHB5ENSR_JPEGENS_Msk                (0x1UL << RCC_AHB5ENSR_JPEGENS_Pos)   /*!< 0x00000008 */
30183 #define RCC_AHB5ENSR_JPEGENS                    RCC_AHB5ENSR_JPEGENS_Msk             /*!< JPEG enable */
30184 #define RCC_AHB5ENSR_FMCENS_Pos                 (4U)
30185 #define RCC_AHB5ENSR_FMCENS_Msk                 (0x1UL << RCC_AHB5ENSR_FMCENS_Pos)    /*!< 0x00000010 */
30186 #define RCC_AHB5ENSR_FMCENS                     RCC_AHB5ENSR_FMCENS_Msk              /*!< FMC enable */
30187 #define RCC_AHB5ENSR_XSPI1ENS_Pos               (5U)
30188 #define RCC_AHB5ENSR_XSPI1ENS_Msk               (0x1UL << RCC_AHB5ENSR_XSPI1ENS_Pos)  /*!< 0x00000020 */
30189 #define RCC_AHB5ENSR_XSPI1ENS                   RCC_AHB5ENSR_XSPI1ENS_Msk            /*!< XSPI1 enable */
30190 #define RCC_AHB5ENSR_PSSIENS_Pos                (6U)
30191 #define RCC_AHB5ENSR_PSSIENS_Msk                (0x1UL << RCC_AHB5ENSR_PSSIENS_Pos)   /*!< 0x00000040 */
30192 #define RCC_AHB5ENSR_PSSIENS                    RCC_AHB5ENSR_PSSIENS_Msk             /*!< PSSI enable */
30193 #define RCC_AHB5ENSR_SDMMC2ENS_Pos              (7U)
30194 #define RCC_AHB5ENSR_SDMMC2ENS_Msk              (0x1UL << RCC_AHB5ENSR_SDMMC2ENS_Pos) /*!< 0x00000080 */
30195 #define RCC_AHB5ENSR_SDMMC2ENS                  RCC_AHB5ENSR_SDMMC2ENS_Msk           /*!< SDMMC2 enable */
30196 #define RCC_AHB5ENSR_SDMMC1ENS_Pos              (8U)
30197 #define RCC_AHB5ENSR_SDMMC1ENS_Msk              (0x1UL << RCC_AHB5ENSR_SDMMC1ENS_Pos) /*!< 0x00000100 */
30198 #define RCC_AHB5ENSR_SDMMC1ENS                  RCC_AHB5ENSR_SDMMC1ENS_Msk           /*!< SDMMC1 enable */
30199 #define RCC_AHB5ENSR_XSPI2ENS_Pos               (12U)
30200 #define RCC_AHB5ENSR_XSPI2ENS_Msk               (0x1UL << RCC_AHB5ENSR_XSPI2ENS_Pos)  /*!< 0x00001000 */
30201 #define RCC_AHB5ENSR_XSPI2ENS                   RCC_AHB5ENSR_XSPI2ENS_Msk            /*!< XSPI2 enable */
30202 #define RCC_AHB5ENSR_XSPIMENS_Pos               (13U)
30203 #define RCC_AHB5ENSR_XSPIMENS_Msk               (0x1UL << RCC_AHB5ENSR_XSPIMENS_Pos)  /*!< 0x00002000 */
30204 #define RCC_AHB5ENSR_XSPIMENS                   RCC_AHB5ENSR_XSPIMENS_Msk            /*!< XSPIM enable */
30205 #define RCC_AHB5ENSR_MCE1ENS_Pos                (14U)
30206 #define RCC_AHB5ENSR_MCE1ENS_Msk                (0x1UL << RCC_AHB5ENSR_MCE1ENS_Pos)   /*!< 0x00004000 */
30207 #define RCC_AHB5ENSR_MCE1ENS                    RCC_AHB5ENSR_MCE1ENS_Msk             /*!< MCE1 enable */
30208 #define RCC_AHB5ENSR_MCE2ENS_Pos                (15U)
30209 #define RCC_AHB5ENSR_MCE2ENS_Msk                (0x1UL << RCC_AHB5ENSR_MCE2ENS_Pos)   /*!< 0x00008000 */
30210 #define RCC_AHB5ENSR_MCE2ENS                    RCC_AHB5ENSR_MCE2ENS_Msk             /*!< MCE2 enable */
30211 #define RCC_AHB5ENSR_MCE3ENS_Pos                (16U)
30212 #define RCC_AHB5ENSR_MCE3ENS_Msk                (0x1UL << RCC_AHB5ENSR_MCE3ENS_Pos)   /*!< 0x00010000 */
30213 #define RCC_AHB5ENSR_MCE3ENS                    RCC_AHB5ENSR_MCE3ENS_Msk             /*!< MCE3 enable */
30214 #define RCC_AHB5ENSR_XSPI3ENS_Pos               (17U)
30215 #define RCC_AHB5ENSR_XSPI3ENS_Msk               (0x1UL << RCC_AHB5ENSR_XSPI3ENS_Pos)  /*!< 0x00020000 */
30216 #define RCC_AHB5ENSR_XSPI3ENS                   RCC_AHB5ENSR_XSPI3ENS_Msk            /*!< XSPI3 enable */
30217 #define RCC_AHB5ENSR_MCE4ENS_Pos                (18U)
30218 #define RCC_AHB5ENSR_MCE4ENS_Msk                (0x1UL << RCC_AHB5ENSR_MCE4ENS_Pos)   /*!< 0x00040000 */
30219 #define RCC_AHB5ENSR_MCE4ENS                    RCC_AHB5ENSR_MCE4ENS_Msk             /*!< MCE4 enable */
30220 #define RCC_AHB5ENSR_GFXMMUENS_Pos              (19U)
30221 #define RCC_AHB5ENSR_GFXMMUENS_Msk              (0x1UL << RCC_AHB5ENSR_GFXMMUENS_Pos) /*!< 0x00080000 */
30222 #define RCC_AHB5ENSR_GFXMMUENS                  RCC_AHB5ENSR_GFXMMUENS_Msk           /*!< GFXMMU enable */
30223 #define RCC_AHB5ENSR_GPU2DENS_Pos               (20U)
30224 #define RCC_AHB5ENSR_GPU2DENS_Msk               (0x1UL << RCC_AHB5ENSR_GPU2DENS_Pos)  /*!< 0x00100000 */
30225 #define RCC_AHB5ENSR_GPU2DENS                   RCC_AHB5ENSR_GPU2DENS_Msk            /*!< GPU2D enable */
30226 #define RCC_AHB5ENSR_ETH1MACENS_Pos             (22U)
30227 #define RCC_AHB5ENSR_ETH1MACENS_Msk             (0x1UL << RCC_AHB5ENSR_ETH1MACENS_Pos)/*!< 0x00400000 */
30228 #define RCC_AHB5ENSR_ETH1MACENS                 RCC_AHB5ENSR_ETH1MACENS_Msk          /*!< ETH1MAC enable */
30229 #define RCC_AHB5ENSR_ETH1TXENS_Pos              (23U)
30230 #define RCC_AHB5ENSR_ETH1TXENS_Msk              (0x1UL << RCC_AHB5ENSR_ETH1TXENS_Pos) /*!< 0x00800000 */
30231 #define RCC_AHB5ENSR_ETH1TXENS                  RCC_AHB5ENSR_ETH1TXENS_Msk           /*!< ETH1TX enable */
30232 #define RCC_AHB5ENSR_ETH1RXENS_Pos              (24U)
30233 #define RCC_AHB5ENSR_ETH1RXENS_Msk              (0x1UL << RCC_AHB5ENSR_ETH1RXENS_Pos) /*!< 0x01000000 */
30234 #define RCC_AHB5ENSR_ETH1RXENS                  RCC_AHB5ENSR_ETH1RXENS_Msk           /*!< ETH1RX enable */
30235 #define RCC_AHB5ENSR_ETH1ENS_Pos                (25U)
30236 #define RCC_AHB5ENSR_ETH1ENS_Msk                (0x1UL << RCC_AHB5ENSR_ETH1ENS_Pos)   /*!< 0x02000000 */
30237 #define RCC_AHB5ENSR_ETH1ENS                    RCC_AHB5ENSR_ETH1ENS_Msk             /*!< ETH1 enable */
30238 #define RCC_AHB5ENSR_OTG1ENS_Pos                (26U)
30239 #define RCC_AHB5ENSR_OTG1ENS_Msk                (0x1UL << RCC_AHB5ENSR_OTG1ENS_Pos)   /*!< 0x04000000 */
30240 #define RCC_AHB5ENSR_OTG1ENS                    RCC_AHB5ENSR_OTG1ENS_Msk             /*!< OTG1 enable */
30241 #define RCC_AHB5ENSR_OTGPHY1ENS_Pos             (27U)
30242 #define RCC_AHB5ENSR_OTGPHY1ENS_Msk             (0x1UL << RCC_AHB5ENSR_OTGPHY1ENS_Pos)/*!< 0x08000000 */
30243 #define RCC_AHB5ENSR_OTGPHY1ENS                 RCC_AHB5ENSR_OTGPHY1ENS_Msk          /*!< OTGPHY1 enable */
30244 #define RCC_AHB5ENSR_OTGPHY2ENS_Pos             (28U)
30245 #define RCC_AHB5ENSR_OTGPHY2ENS_Msk             (0x1UL << RCC_AHB5ENSR_OTGPHY2ENS_Pos)/*!< 0x10000000 */
30246 #define RCC_AHB5ENSR_OTGPHY2ENS                 RCC_AHB5ENSR_OTGPHY2ENS_Msk          /*!< OTGPHY2 enable */
30247 #define RCC_AHB5ENSR_OTG2ENS_Pos                (29U)
30248 #define RCC_AHB5ENSR_OTG2ENS_Msk                (0x1UL << RCC_AHB5ENSR_OTG2ENS_Pos)   /*!< 0x20000000 */
30249 #define RCC_AHB5ENSR_OTG2ENS                    RCC_AHB5ENSR_OTG2ENS_Msk             /*!< OTG2 enable */
30250 #define RCC_AHB5ENSR_CACHEAXIENS_Pos            (30U)
30251 #define RCC_AHB5ENSR_CACHEAXIENS_Msk            (0x1UL << RCC_AHB5ENSR_CACHEAXIENS_Pos) /*!< 0x40000000 */
30252 #define RCC_AHB5ENSR_CACHEAXIENS                RCC_AHB5ENSR_CACHEAXIENS_Msk         /*!< CACHEAXI enable */
30253 #define RCC_AHB5ENSR_NPUENS_Pos                 (31U)
30254 #define RCC_AHB5ENSR_NPUENS_Msk                 (0x1UL << RCC_AHB5ENSR_NPUENS_Pos)    /*!< 0x80000000 */
30255 #define RCC_AHB5ENSR_NPUENS                     RCC_AHB5ENSR_NPUENS_Msk              /*!< NPU enable */
30256 
30257 /****************  Bit definition for RCC_APB1ENSR1 register  *****************/
30258 #define RCC_APB1ENSR1_TIM2ENS_Pos               (0U)
30259 #define RCC_APB1ENSR1_TIM2ENS_Msk               (0x1UL << RCC_APB1ENSR1_TIM2ENS_Pos)  /*!< 0x00000001 */
30260 #define RCC_APB1ENSR1_TIM2ENS                   RCC_APB1ENSR1_TIM2ENS_Msk            /*!< TIM2 enable */
30261 #define RCC_APB1ENSR1_TIM3ENS_Pos               (1U)
30262 #define RCC_APB1ENSR1_TIM3ENS_Msk               (0x1UL << RCC_APB1ENSR1_TIM3ENS_Pos)  /*!< 0x00000002 */
30263 #define RCC_APB1ENSR1_TIM3ENS                   RCC_APB1ENSR1_TIM3ENS_Msk            /*!< TIM3 enable */
30264 #define RCC_APB1ENSR1_TIM4ENS_Pos               (2U)
30265 #define RCC_APB1ENSR1_TIM4ENS_Msk               (0x1UL << RCC_APB1ENSR1_TIM4ENS_Pos)  /*!< 0x00000004 */
30266 #define RCC_APB1ENSR1_TIM4ENS                   RCC_APB1ENSR1_TIM4ENS_Msk            /*!< TIM4 enable */
30267 #define RCC_APB1ENSR1_TIM5ENS_Pos               (3U)
30268 #define RCC_APB1ENSR1_TIM5ENS_Msk               (0x1UL << RCC_APB1ENSR1_TIM5ENS_Pos)  /*!< 0x00000008 */
30269 #define RCC_APB1ENSR1_TIM5ENS                   RCC_APB1ENSR1_TIM5ENS_Msk            /*!< TIM5 enable */
30270 #define RCC_APB1ENSR1_TIM6ENS_Pos               (4U)
30271 #define RCC_APB1ENSR1_TIM6ENS_Msk               (0x1UL << RCC_APB1ENSR1_TIM6ENS_Pos)  /*!< 0x00000010 */
30272 #define RCC_APB1ENSR1_TIM6ENS                   RCC_APB1ENSR1_TIM6ENS_Msk            /*!< TIM6 enable */
30273 #define RCC_APB1ENSR1_TIM7ENS_Pos               (5U)
30274 #define RCC_APB1ENSR1_TIM7ENS_Msk               (0x1UL << RCC_APB1ENSR1_TIM7ENS_Pos)  /*!< 0x00000020 */
30275 #define RCC_APB1ENSR1_TIM7ENS                   RCC_APB1ENSR1_TIM7ENS_Msk            /*!< TIM7 enable */
30276 #define RCC_APB1ENSR1_TIM12ENS_Pos              (6U)
30277 #define RCC_APB1ENSR1_TIM12ENS_Msk              (0x1UL << RCC_APB1ENSR1_TIM12ENS_Pos) /*!< 0x00000040 */
30278 #define RCC_APB1ENSR1_TIM12ENS                  RCC_APB1ENSR1_TIM12ENS_Msk           /*!< TIM12 enable */
30279 #define RCC_APB1ENSR1_TIM13ENS_Pos              (7U)
30280 #define RCC_APB1ENSR1_TIM13ENS_Msk              (0x1UL << RCC_APB1ENSR1_TIM13ENS_Pos) /*!< 0x00000080 */
30281 #define RCC_APB1ENSR1_TIM13ENS                  RCC_APB1ENSR1_TIM13ENS_Msk           /*!< TIM13 enable */
30282 #define RCC_APB1ENSR1_TIM14ENS_Pos              (8U)
30283 #define RCC_APB1ENSR1_TIM14ENS_Msk              (0x1UL << RCC_APB1ENSR1_TIM14ENS_Pos) /*!< 0x00000100 */
30284 #define RCC_APB1ENSR1_TIM14ENS                  RCC_APB1ENSR1_TIM14ENS_Msk           /*!< TIM14 enable */
30285 #define RCC_APB1ENSR1_LPTIM1ENS_Pos             (9U)
30286 #define RCC_APB1ENSR1_LPTIM1ENS_Msk             (0x1UL << RCC_APB1ENSR1_LPTIM1ENS_Pos)/*!< 0x00000200 */
30287 #define RCC_APB1ENSR1_LPTIM1ENS                 RCC_APB1ENSR1_LPTIM1ENS_Msk          /*!< LPTIM1 enable */
30288 #define RCC_APB1ENSR1_WWDGENS_Pos               (11U)
30289 #define RCC_APB1ENSR1_WWDGENS_Msk               (0x1UL << RCC_APB1ENSR1_WWDGENS_Pos)  /*!< 0x00000800 */
30290 #define RCC_APB1ENSR1_WWDGENS                   RCC_APB1ENSR1_WWDGENS_Msk            /*!< WWDG enable */
30291 #define RCC_APB1ENSR1_TIM10ENS_Pos              (12U)
30292 #define RCC_APB1ENSR1_TIM10ENS_Msk              (0x1UL << RCC_APB1ENSR1_TIM10ENS_Pos) /*!< 0x00001000 */
30293 #define RCC_APB1ENSR1_TIM10ENS                  RCC_APB1ENSR1_TIM10ENS_Msk           /*!< TIM10 enable */
30294 #define RCC_APB1ENSR1_TIM11ENS_Pos              (13U)
30295 #define RCC_APB1ENSR1_TIM11ENS_Msk              (0x1UL << RCC_APB1ENSR1_TIM11ENS_Pos) /*!< 0x00002000 */
30296 #define RCC_APB1ENSR1_TIM11ENS                  RCC_APB1ENSR1_TIM11ENS_Msk           /*!< TIM11 enable */
30297 #define RCC_APB1ENSR1_SPI2ENS_Pos               (14U)
30298 #define RCC_APB1ENSR1_SPI2ENS_Msk               (0x1UL << RCC_APB1ENSR1_SPI2ENS_Pos)  /*!< 0x00004000 */
30299 #define RCC_APB1ENSR1_SPI2ENS                   RCC_APB1ENSR1_SPI2ENS_Msk            /*!< SPI2 enable */
30300 #define RCC_APB1ENSR1_SPI3ENS_Pos               (15U)
30301 #define RCC_APB1ENSR1_SPI3ENS_Msk               (0x1UL << RCC_APB1ENSR1_SPI3ENS_Pos)  /*!< 0x00008000 */
30302 #define RCC_APB1ENSR1_SPI3ENS                   RCC_APB1ENSR1_SPI3ENS_Msk            /*!< SPI3 enable */
30303 #define RCC_APB1ENSR1_SPDIFRX1ENS_Pos           (16U)
30304 #define RCC_APB1ENSR1_SPDIFRX1ENS_Msk           (0x1UL << RCC_APB1ENSR1_SPDIFRX1ENS_Pos)  /*!< 0x00010000 */
30305 #define RCC_APB1ENSR1_SPDIFRX1ENS               RCC_APB1ENSR1_SPDIFRX1ENS_Msk        /*!< SPDIFRX1 enable */
30306 #define RCC_APB1ENSR1_USART2ENS_Pos             (17U)
30307 #define RCC_APB1ENSR1_USART2ENS_Msk             (0x1UL << RCC_APB1ENSR1_USART2ENS_Pos)/*!< 0x00020000 */
30308 #define RCC_APB1ENSR1_USART2ENS                 RCC_APB1ENSR1_USART2ENS_Msk          /*!< USART2 enable */
30309 #define RCC_APB1ENSR1_USART3ENS_Pos             (18U)
30310 #define RCC_APB1ENSR1_USART3ENS_Msk             (0x1UL << RCC_APB1ENSR1_USART3ENS_Pos)/*!< 0x00040000 */
30311 #define RCC_APB1ENSR1_USART3ENS                 RCC_APB1ENSR1_USART3ENS_Msk          /*!< USART3 enable */
30312 #define RCC_APB1ENSR1_UART4ENS_Pos              (19U)
30313 #define RCC_APB1ENSR1_UART4ENS_Msk              (0x1UL << RCC_APB1ENSR1_UART4ENS_Pos) /*!< 0x00080000 */
30314 #define RCC_APB1ENSR1_UART4ENS                  RCC_APB1ENSR1_UART4ENS_Msk           /*!< UART4 enable */
30315 #define RCC_APB1ENSR1_UART5ENS_Pos              (20U)
30316 #define RCC_APB1ENSR1_UART5ENS_Msk              (0x1UL << RCC_APB1ENSR1_UART5ENS_Pos) /*!< 0x00100000 */
30317 #define RCC_APB1ENSR1_UART5ENS                  RCC_APB1ENSR1_UART5ENS_Msk           /*!< UART5 enable */
30318 #define RCC_APB1ENSR1_I2C1ENS_Pos               (21U)
30319 #define RCC_APB1ENSR1_I2C1ENS_Msk               (0x1UL << RCC_APB1ENSR1_I2C1ENS_Pos)  /*!< 0x00200000 */
30320 #define RCC_APB1ENSR1_I2C1ENS                   RCC_APB1ENSR1_I2C1ENS_Msk            /*!< I2C1 enable */
30321 #define RCC_APB1ENSR1_I2C2ENS_Pos               (22U)
30322 #define RCC_APB1ENSR1_I2C2ENS_Msk               (0x1UL << RCC_APB1ENSR1_I2C2ENS_Pos)  /*!< 0x00400000 */
30323 #define RCC_APB1ENSR1_I2C2ENS                   RCC_APB1ENSR1_I2C2ENS_Msk            /*!< I2C2 enable */
30324 #define RCC_APB1ENSR1_I2C3ENS_Pos               (23U)
30325 #define RCC_APB1ENSR1_I2C3ENS_Msk               (0x1UL << RCC_APB1ENSR1_I2C3ENS_Pos)  /*!< 0x00800000 */
30326 #define RCC_APB1ENSR1_I2C3ENS                   RCC_APB1ENSR1_I2C3ENS_Msk            /*!< I2C3 enable */
30327 #define RCC_APB1ENSR1_I3C1ENS_Pos               (24U)
30328 #define RCC_APB1ENSR1_I3C1ENS_Msk               (0x1UL << RCC_APB1ENSR1_I3C1ENS_Pos)  /*!< 0x01000000 */
30329 #define RCC_APB1ENSR1_I3C1ENS                   RCC_APB1ENSR1_I3C1ENS_Msk            /*!< I3C1 enable */
30330 #define RCC_APB1ENSR1_I3C2ENS_Pos               (25U)
30331 #define RCC_APB1ENSR1_I3C2ENS_Msk               (0x1UL << RCC_APB1ENSR1_I3C2ENS_Pos)  /*!< 0x02000000 */
30332 #define RCC_APB1ENSR1_I3C2ENS                   RCC_APB1ENSR1_I3C2ENS_Msk            /*!< I3C2 enable */
30333 #define RCC_APB1ENSR1_UART7ENS_Pos              (30U)
30334 #define RCC_APB1ENSR1_UART7ENS_Msk              (0x1UL << RCC_APB1ENSR1_UART7ENS_Pos) /*!< 0x40000000 */
30335 #define RCC_APB1ENSR1_UART7ENS                  RCC_APB1ENSR1_UART7ENS_Msk           /*!< UART7 enable */
30336 #define RCC_APB1ENSR1_UART8ENS_Pos              (31U)
30337 #define RCC_APB1ENSR1_UART8ENS_Msk              (0x1UL << RCC_APB1ENSR1_UART8ENS_Pos) /*!< 0x80000000 */
30338 #define RCC_APB1ENSR1_UART8ENS                  RCC_APB1ENSR1_UART8ENS_Msk           /*!< UART8 enable */
30339 
30340 /****************  Bit definition for RCC_APB1ENSR2 register  *****************/
30341 #define RCC_APB1ENSR2_MDIOSENS_Pos              (5U)
30342 #define RCC_APB1ENSR2_MDIOSENS_Msk              (0x1UL << RCC_APB1ENSR2_MDIOSENS_Pos) /*!< 0x00000020 */
30343 #define RCC_APB1ENSR2_MDIOSENS                  RCC_APB1ENSR2_MDIOSENS_Msk           /*!< MDIOS enable */
30344 #define RCC_APB1ENSR2_FDCANENS_Pos              (8U)
30345 #define RCC_APB1ENSR2_FDCANENS_Msk              (0x1UL << RCC_APB1ENSR2_FDCANENS_Pos) /*!< 0x00000100 */
30346 #define RCC_APB1ENSR2_FDCANENS                  RCC_APB1ENSR2_FDCANENS_Msk           /*!< FDCAN enable */
30347 #define RCC_APB1ENSR2_UCPD1ENS_Pos              (18U)
30348 #define RCC_APB1ENSR2_UCPD1ENS_Msk              (0x1UL << RCC_APB1ENSR2_UCPD1ENS_Pos) /*!< 0x00040000 */
30349 #define RCC_APB1ENSR2_UCPD1ENS                  RCC_APB1ENSR2_UCPD1ENS_Msk           /*!< UCPD1 enable */
30350 
30351 /*****************  Bit definition for RCC_APB2ENSR register  *****************/
30352 #define RCC_APB2ENSR_TIM1ENS_Pos                (0U)
30353 #define RCC_APB2ENSR_TIM1ENS_Msk                (0x1UL << RCC_APB2ENSR_TIM1ENS_Pos)   /*!< 0x00000001 */
30354 #define RCC_APB2ENSR_TIM1ENS                    RCC_APB2ENSR_TIM1ENS_Msk             /*!< TIM1 enable */
30355 #define RCC_APB2ENSR_TIM8ENS_Pos                (1U)
30356 #define RCC_APB2ENSR_TIM8ENS_Msk                (0x1UL << RCC_APB2ENSR_TIM8ENS_Pos)   /*!< 0x00000002 */
30357 #define RCC_APB2ENSR_TIM8ENS                    RCC_APB2ENSR_TIM8ENS_Msk             /*!< TIM8 enable */
30358 #define RCC_APB2ENSR_USART1ENS_Pos              (4U)
30359 #define RCC_APB2ENSR_USART1ENS_Msk              (0x1UL << RCC_APB2ENSR_USART1ENS_Pos) /*!< 0x00000010 */
30360 #define RCC_APB2ENSR_USART1ENS                  RCC_APB2ENSR_USART1ENS_Msk           /*!< USART1 enable */
30361 #define RCC_APB2ENSR_USART6ENS_Pos              (5U)
30362 #define RCC_APB2ENSR_USART6ENS_Msk              (0x1UL << RCC_APB2ENSR_USART6ENS_Pos) /*!< 0x00000020 */
30363 #define RCC_APB2ENSR_USART6ENS                  RCC_APB2ENSR_USART6ENS_Msk           /*!< USART6 enable */
30364 #define RCC_APB2ENSR_UART9ENS_Pos               (6U)
30365 #define RCC_APB2ENSR_UART9ENS_Msk               (0x1UL << RCC_APB2ENSR_UART9ENS_Pos)  /*!< 0x00000040 */
30366 #define RCC_APB2ENSR_UART9ENS                   RCC_APB2ENSR_UART9ENS_Msk            /*!< UART9 enable */
30367 #define RCC_APB2ENSR_USART10ENS_Pos             (7U)
30368 #define RCC_APB2ENSR_USART10ENS_Msk             (0x1UL << RCC_APB2ENSR_USART10ENS_Pos)/*!< 0x00000080 */
30369 #define RCC_APB2ENSR_USART10ENS                 RCC_APB2ENSR_USART10ENS_Msk          /*!< USART10 enable */
30370 #define RCC_APB2ENSR_SPI1ENS_Pos                (12U)
30371 #define RCC_APB2ENSR_SPI1ENS_Msk                (0x1UL << RCC_APB2ENSR_SPI1ENS_Pos)   /*!< 0x00001000 */
30372 #define RCC_APB2ENSR_SPI1ENS                    RCC_APB2ENSR_SPI1ENS_Msk             /*!< SPI1 enable */
30373 #define RCC_APB2ENSR_SPI4ENS_Pos                (13U)
30374 #define RCC_APB2ENSR_SPI4ENS_Msk                (0x1UL << RCC_APB2ENSR_SPI4ENS_Pos)   /*!< 0x00002000 */
30375 #define RCC_APB2ENSR_SPI4ENS                    RCC_APB2ENSR_SPI4ENS_Msk             /*!< SPI4 enable */
30376 #define RCC_APB2ENSR_TIM18ENS_Pos               (15U)
30377 #define RCC_APB2ENSR_TIM18ENS_Msk               (0x1UL << RCC_APB2ENSR_TIM18ENS_Pos)  /*!< 0x00008000 */
30378 #define RCC_APB2ENSR_TIM18ENS                   RCC_APB2ENSR_TIM18ENS_Msk            /*!< TIM18 enable */
30379 #define RCC_APB2ENSR_TIM15ENS_Pos               (16U)
30380 #define RCC_APB2ENSR_TIM15ENS_Msk               (0x1UL << RCC_APB2ENSR_TIM15ENS_Pos)  /*!< 0x00010000 */
30381 #define RCC_APB2ENSR_TIM15ENS                   RCC_APB2ENSR_TIM15ENS_Msk            /*!< TIM15 enable */
30382 #define RCC_APB2ENSR_TIM16ENS_Pos               (17U)
30383 #define RCC_APB2ENSR_TIM16ENS_Msk               (0x1UL << RCC_APB2ENSR_TIM16ENS_Pos)  /*!< 0x00020000 */
30384 #define RCC_APB2ENSR_TIM16ENS                   RCC_APB2ENSR_TIM16ENS_Msk            /*!< TIM16 enable */
30385 #define RCC_APB2ENSR_TIM17ENS_Pos               (18U)
30386 #define RCC_APB2ENSR_TIM17ENS_Msk               (0x1UL << RCC_APB2ENSR_TIM17ENS_Pos)  /*!< 0x00040000 */
30387 #define RCC_APB2ENSR_TIM17ENS                   RCC_APB2ENSR_TIM17ENS_Msk            /*!< TIM17 enable */
30388 #define RCC_APB2ENSR_TIM9ENS_Pos                (19U)
30389 #define RCC_APB2ENSR_TIM9ENS_Msk                (0x1UL << RCC_APB2ENSR_TIM9ENS_Pos)   /*!< 0x00080000 */
30390 #define RCC_APB2ENSR_TIM9ENS                    RCC_APB2ENSR_TIM9ENS_Msk             /*!< TIM9 enable */
30391 #define RCC_APB2ENSR_SPI5ENS_Pos                (20U)
30392 #define RCC_APB2ENSR_SPI5ENS_Msk                (0x1UL << RCC_APB2ENSR_SPI5ENS_Pos)   /*!< 0x00100000 */
30393 #define RCC_APB2ENSR_SPI5ENS                    RCC_APB2ENSR_SPI5ENS_Msk             /*!< SPI5 enable */
30394 #define RCC_APB2ENSR_SAI1ENS_Pos                (21U)
30395 #define RCC_APB2ENSR_SAI1ENS_Msk                (0x1UL << RCC_APB2ENSR_SAI1ENS_Pos)   /*!< 0x00200000 */
30396 #define RCC_APB2ENSR_SAI1ENS                    RCC_APB2ENSR_SAI1ENS_Msk             /*!< SAI1 enable */
30397 #define RCC_APB2ENSR_SAI2ENS_Pos                (22U)
30398 #define RCC_APB2ENSR_SAI2ENS_Msk                (0x1UL << RCC_APB2ENSR_SAI2ENS_Pos)   /*!< 0x00400000 */
30399 #define RCC_APB2ENSR_SAI2ENS                    RCC_APB2ENSR_SAI2ENS_Msk             /*!< SAI2 enable */
30400 
30401 /*****************  Bit definition for RCC_APB3ENSR register  *****************/
30402 #define RCC_APB3ENSR_DFTENS_Pos                 (2U)
30403 #define RCC_APB3ENSR_DFTENS_Msk                 (0x1UL << RCC_APB3ENSR_DFTENS_Pos)    /*!< 0x00000004 */
30404 #define RCC_APB3ENSR_DFTENS                     RCC_APB3ENSR_DFTENS_Msk              /*!< DFT enable */
30405 
30406 /****************  Bit definition for RCC_APB4ENSR1 register  *****************/
30407 #define RCC_APB4ENSR1_HDPENS_Pos                (2U)
30408 #define RCC_APB4ENSR1_HDPENS_Msk                (0x1UL << RCC_APB4ENSR1_HDPENS_Pos)   /*!< 0x00000004 */
30409 #define RCC_APB4ENSR1_HDPENS                    RCC_APB4ENSR1_HDPENS_Msk             /*!< HDP enable */
30410 #define RCC_APB4ENSR1_LPUART1ENS_Pos            (3U)
30411 #define RCC_APB4ENSR1_LPUART1ENS_Msk            (0x1UL << RCC_APB4ENSR1_LPUART1ENS_Pos) /*!< 0x00000008 */
30412 #define RCC_APB4ENSR1_LPUART1ENS                RCC_APB4ENSR1_LPUART1ENS_Msk         /*!< LPUART1 enable */
30413 #define RCC_APB4ENSR1_SPI6ENS_Pos               (5U)
30414 #define RCC_APB4ENSR1_SPI6ENS_Msk               (0x1UL << RCC_APB4ENSR1_SPI6ENS_Pos)  /*!< 0x00000020 */
30415 #define RCC_APB4ENSR1_SPI6ENS                   RCC_APB4ENSR1_SPI6ENS_Msk            /*!< SPI6 enable */
30416 #define RCC_APB4ENSR1_I2C4ENS_Pos               (7U)
30417 #define RCC_APB4ENSR1_I2C4ENS_Msk               (0x1UL << RCC_APB4ENSR1_I2C4ENS_Pos)  /*!< 0x00000080 */
30418 #define RCC_APB4ENSR1_I2C4ENS                   RCC_APB4ENSR1_I2C4ENS_Msk            /*!< I2C4 enable */
30419 #define RCC_APB4ENSR1_LPTIM2ENS_Pos             (9U)
30420 #define RCC_APB4ENSR1_LPTIM2ENS_Msk             (0x1UL << RCC_APB4ENSR1_LPTIM2ENS_Pos)/*!< 0x00000200 */
30421 #define RCC_APB4ENSR1_LPTIM2ENS                 RCC_APB4ENSR1_LPTIM2ENS_Msk          /*!< LPTIM2 enable */
30422 #define RCC_APB4ENSR1_LPTIM3ENS_Pos             (10U)
30423 #define RCC_APB4ENSR1_LPTIM3ENS_Msk             (0x1UL << RCC_APB4ENSR1_LPTIM3ENS_Pos)/*!< 0x00000400 */
30424 #define RCC_APB4ENSR1_LPTIM3ENS                 RCC_APB4ENSR1_LPTIM3ENS_Msk          /*!< LPTIM3 enable */
30425 #define RCC_APB4ENSR1_LPTIM4ENS_Pos             (11U)
30426 #define RCC_APB4ENSR1_LPTIM4ENS_Msk             (0x1UL << RCC_APB4ENSR1_LPTIM4ENS_Pos)/*!< 0x00000800 */
30427 #define RCC_APB4ENSR1_LPTIM4ENS                 RCC_APB4ENSR1_LPTIM4ENS_Msk          /*!< LPTIM4 enable */
30428 #define RCC_APB4ENSR1_LPTIM5ENS_Pos             (12U)
30429 #define RCC_APB4ENSR1_LPTIM5ENS_Msk             (0x1UL << RCC_APB4ENSR1_LPTIM5ENS_Pos)/*!< 0x00001000 */
30430 #define RCC_APB4ENSR1_LPTIM5ENS                 RCC_APB4ENSR1_LPTIM5ENS_Msk          /*!< LPTIM5 enable */
30431 #define RCC_APB4ENSR1_VREFBUFENS_Pos            (15U)
30432 #define RCC_APB4ENSR1_VREFBUFENS_Msk            (0x1UL << RCC_APB4ENSR1_VREFBUFENS_Pos) /*!< 0x00008000 */
30433 #define RCC_APB4ENSR1_VREFBUFENS                RCC_APB4ENSR1_VREFBUFENS_Msk         /*!< VREFBUF enable */
30434 #define RCC_APB4ENSR1_RTCENS_Pos                (16U)
30435 #define RCC_APB4ENSR1_RTCENS_Msk                (0x1UL << RCC_APB4ENSR1_RTCENS_Pos)   /*!< 0x00010000 */
30436 #define RCC_APB4ENSR1_RTCENS                    RCC_APB4ENSR1_RTCENS_Msk             /*!< RTC enable */
30437 #define RCC_APB4ENSR1_RTCAPBENS_Pos             (17U)
30438 #define RCC_APB4ENSR1_RTCAPBENS_Msk             (0x1UL << RCC_APB4ENSR1_RTCAPBENS_Pos)/*!< 0x00020000 */
30439 #define RCC_APB4ENSR1_RTCAPBENS                 RCC_APB4ENSR1_RTCAPBENS_Msk          /*!< RTCAPB enable */
30440 
30441 /****************  Bit definition for RCC_APB4ENSR2 register  *****************/
30442 #define RCC_APB4ENSR2_SYSCFGENS_Pos             (0U)
30443 #define RCC_APB4ENSR2_SYSCFGENS_Msk             (0x1UL << RCC_APB4ENSR2_SYSCFGENS_Pos)/*!< 0x00000001 */
30444 #define RCC_APB4ENSR2_SYSCFGENS                 RCC_APB4ENSR2_SYSCFGENS_Msk          /*!< SYSCFG enable */
30445 #define RCC_APB4ENSR2_BSECENS_Pos               (1U)
30446 #define RCC_APB4ENSR2_BSECENS_Msk               (0x1UL << RCC_APB4ENSR2_BSECENS_Pos)  /*!< 0x00000002 */
30447 #define RCC_APB4ENSR2_BSECENS                   RCC_APB4ENSR2_BSECENS_Msk            /*!< BSEC enable */
30448 #define RCC_APB4ENSR2_DTSENS_Pos                (2U)
30449 #define RCC_APB4ENSR2_DTSENS_Msk                (0x1UL << RCC_APB4ENSR2_DTSENS_Pos)   /*!< 0x00000004 */
30450 #define RCC_APB4ENSR2_DTSENS                    RCC_APB4ENSR2_DTSENS_Msk             /*!< DTS enable */
30451 
30452 /*****************  Bit definition for RCC_APB5ENSR register  *****************/
30453 #define RCC_APB5ENSR_LTDCENS_Pos                (1U)
30454 #define RCC_APB5ENSR_LTDCENS_Msk                (0x1UL << RCC_APB5ENSR_LTDCENS_Pos)   /*!< 0x00000002 */
30455 #define RCC_APB5ENSR_LTDCENS                    RCC_APB5ENSR_LTDCENS_Msk             /*!< LTDC enable */
30456 #define RCC_APB5ENSR_DCMIPPENS_Pos              (2U)
30457 #define RCC_APB5ENSR_DCMIPPENS_Msk              (0x1UL << RCC_APB5ENSR_DCMIPPENS_Pos) /*!< 0x00000004 */
30458 #define RCC_APB5ENSR_DCMIPPENS                  RCC_APB5ENSR_DCMIPPENS_Msk           /*!< DCMIPP enable */
30459 #define RCC_APB5ENSR_GFXTIMENS_Pos              (4U)
30460 #define RCC_APB5ENSR_GFXTIMENS_Msk              (0x1UL << RCC_APB5ENSR_GFXTIMENS_Pos) /*!< 0x00000010 */
30461 #define RCC_APB5ENSR_GFXTIMENS                  RCC_APB5ENSR_GFXTIMENS_Msk           /*!< GFXTIM enable */
30462 #define RCC_APB5ENSR_VENCENS_Pos                (5U)
30463 #define RCC_APB5ENSR_VENCENS_Msk                (0x1UL << RCC_APB5ENSR_VENCENS_Pos)   /*!< 0x00000020 */
30464 #define RCC_APB5ENSR_VENCENS                    RCC_APB5ENSR_VENCENS_Msk             /*!< VENC enable */
30465 #define RCC_APB5ENSR_CSIENS_Pos                 (6U)
30466 #define RCC_APB5ENSR_CSIENS_Msk                 (0x1UL << RCC_APB5ENSR_CSIENS_Pos)    /*!< 0x00000040 */
30467 #define RCC_APB5ENSR_CSIENS                     RCC_APB5ENSR_CSIENS_Msk              /*!< CSI enable */
30468 
30469 /****************  Bit definition for RCC_BUSLPENSR register  *****************/
30470 #define RCC_BUSLPENSR_ACLKNLPENS_Pos            (0U)
30471 #define RCC_BUSLPENSR_ACLKNLPENS_Msk            (0x1UL << RCC_BUSLPENSR_ACLKNLPENS_Pos) /*!< 0x00000001 */
30472 #define RCC_BUSLPENSR_ACLKNLPENS                RCC_BUSLPENSR_ACLKNLPENS_Msk         /*!< ACLKN enable  */
30473 #define RCC_BUSLPENSR_ACLKNCLPENS_Pos           (1U)
30474 #define RCC_BUSLPENSR_ACLKNCLPENS_Msk           (0x1UL << RCC_BUSLPENSR_ACLKNCLPENS_Pos)  /*!< 0x00000002 */
30475 #define RCC_BUSLPENSR_ACLKNCLPENS               RCC_BUSLPENSR_ACLKNCLPENS_Msk        /*!< ACLKNC enable  */
30476 
30477 /****************  Bit definition for RCC_MISCLPENSR register  ****************/
30478 #define RCC_MISCLPENSR_DBGLPENS_Pos             (0U)
30479 #define RCC_MISCLPENSR_DBGLPENS_Msk             (0x1UL << RCC_MISCLPENSR_DBGLPENS_Pos)/*!< 0x00000001 */
30480 #define RCC_MISCLPENSR_DBGLPENS                 RCC_MISCLPENSR_DBGLPENS_Msk          /*!< DBG enable  */
30481 #define RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Pos     (3U)
30482 #define RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Msk     (0x1UL << RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Pos)        /*!< 0x00000008 */
30483 #define RCC_MISCLPENSR_XSPIPHYCOMPLPENS         RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Msk  /*!< XSPIPHYCOMP enable  */
30484 #define RCC_MISCLPENSR_PERLPENS_Pos             (6U)
30485 #define RCC_MISCLPENSR_PERLPENS_Msk             (0x1UL << RCC_MISCLPENSR_PERLPENS_Pos)/*!< 0x00000040 */
30486 #define RCC_MISCLPENSR_PERLPENS                 RCC_MISCLPENSR_PERLPENS_Msk          /*!< PER enable  */
30487 
30488 /****************  Bit definition for RCC_MEMLPENSR register  *****************/
30489 #define RCC_MEMLPENSR_AXISRAM3LPENS_Pos         (0U)
30490 #define RCC_MEMLPENSR_AXISRAM3LPENS_Msk         (0x1UL << RCC_MEMLPENSR_AXISRAM3LPENS_Pos)    /*!< 0x00000001 */
30491 #define RCC_MEMLPENSR_AXISRAM3LPENS             RCC_MEMLPENSR_AXISRAM3LPENS_Msk      /*!< AXISRAM3 enable  */
30492 #define RCC_MEMLPENSR_AXISRAM4LPENS_Pos         (1U)
30493 #define RCC_MEMLPENSR_AXISRAM4LPENS_Msk         (0x1UL << RCC_MEMLPENSR_AXISRAM4LPENS_Pos)    /*!< 0x00000002 */
30494 #define RCC_MEMLPENSR_AXISRAM4LPENS             RCC_MEMLPENSR_AXISRAM4LPENS_Msk      /*!< AXISRAM4 enable  */
30495 #define RCC_MEMLPENSR_AXISRAM5LPENS_Pos         (2U)
30496 #define RCC_MEMLPENSR_AXISRAM5LPENS_Msk         (0x1UL << RCC_MEMLPENSR_AXISRAM5LPENS_Pos)    /*!< 0x00000004 */
30497 #define RCC_MEMLPENSR_AXISRAM5LPENS             RCC_MEMLPENSR_AXISRAM5LPENS_Msk      /*!< AXISRAM5 enable  */
30498 #define RCC_MEMLPENSR_AXISRAM6LPENS_Pos         (3U)
30499 #define RCC_MEMLPENSR_AXISRAM6LPENS_Msk         (0x1UL << RCC_MEMLPENSR_AXISRAM6LPENS_Pos)    /*!< 0x00000008 */
30500 #define RCC_MEMLPENSR_AXISRAM6LPENS             RCC_MEMLPENSR_AXISRAM6LPENS_Msk      /*!< AXISRAM6 enable  */
30501 #define RCC_MEMLPENSR_AHBSRAM1LPENS_Pos         (4U)
30502 #define RCC_MEMLPENSR_AHBSRAM1LPENS_Msk         (0x1UL << RCC_MEMLPENSR_AHBSRAM1LPENS_Pos)    /*!< 0x00000010 */
30503 #define RCC_MEMLPENSR_AHBSRAM1LPENS             RCC_MEMLPENSR_AHBSRAM1LPENS_Msk      /*!< AHBSRAM1 enable  */
30504 #define RCC_MEMLPENSR_AHBSRAM2LPENS_Pos         (5U)
30505 #define RCC_MEMLPENSR_AHBSRAM2LPENS_Msk         (0x1UL << RCC_MEMLPENSR_AHBSRAM2LPENS_Pos)    /*!< 0x00000020 */
30506 #define RCC_MEMLPENSR_AHBSRAM2LPENS             RCC_MEMLPENSR_AHBSRAM2LPENS_Msk      /*!< AHBSRAM2 enable  */
30507 #define RCC_MEMLPENSR_BKPSRAMLPENS_Pos          (6U)
30508 #define RCC_MEMLPENSR_BKPSRAMLPENS_Msk          (0x1UL << RCC_MEMLPENSR_BKPSRAMLPENS_Pos)   /*!< 0x00000040 */
30509 #define RCC_MEMLPENSR_BKPSRAMLPENS              RCC_MEMLPENSR_BKPSRAMLPENS_Msk       /*!< BKPSRAM enable  */
30510 #define RCC_MEMLPENSR_AXISRAM1LPENS_Pos         (7U)
30511 #define RCC_MEMLPENSR_AXISRAM1LPENS_Msk         (0x1UL << RCC_MEMLPENSR_AXISRAM1LPENS_Pos)    /*!< 0x00000080 */
30512 #define RCC_MEMLPENSR_AXISRAM1LPENS             RCC_MEMLPENSR_AXISRAM1LPENS_Msk      /*!< AXISRAM1 enable  */
30513 #define RCC_MEMLPENSR_AXISRAM2LPENS_Pos         (8U)
30514 #define RCC_MEMLPENSR_AXISRAM2LPENS_Msk         (0x1UL << RCC_MEMLPENSR_AXISRAM2LPENS_Pos)    /*!< 0x00000100 */
30515 #define RCC_MEMLPENSR_AXISRAM2LPENS             RCC_MEMLPENSR_AXISRAM2LPENS_Msk      /*!< AXISRAM2 enable  */
30516 #define RCC_MEMLPENSR_FLEXRAMLPENS_Pos          (9U)
30517 #define RCC_MEMLPENSR_FLEXRAMLPENS_Msk          (0x1UL << RCC_MEMLPENSR_FLEXRAMLPENS_Pos)   /*!< 0x00000200 */
30518 #define RCC_MEMLPENSR_FLEXRAMLPENS              RCC_MEMLPENSR_FLEXRAMLPENS_Msk       /*!< FLEXRAM enable  */
30519 #define RCC_MEMLPENSR_CACHEAXIRAMLPENS_Pos      (10U)
30520 #define RCC_MEMLPENSR_CACHEAXIRAMLPENS_Msk      (0x1UL << RCC_MEMLPENSR_CACHEAXIRAMLPENS_Pos)       /*!< 0x00000400 */
30521 #define RCC_MEMLPENSR_CACHEAXIRAMLPENS          RCC_MEMLPENSR_CACHEAXIRAMLPENS_Msk   /*!< CACHEAXIRAM enable  */
30522 #define RCC_MEMLPENSR_VENCRAMLPENS_Pos          (11U)
30523 #define RCC_MEMLPENSR_VENCRAMLPENS_Msk          (0x1UL << RCC_MEMLPENSR_VENCRAMLPENS_Pos)   /*!< 0x00000800 */
30524 #define RCC_MEMLPENSR_VENCRAMLPENS              RCC_MEMLPENSR_VENCRAMLPENS_Msk       /*!< VENCRAM enable  */
30525 #define RCC_MEMLPENSR_BOOTROMLPENS_Pos          (12U)
30526 #define RCC_MEMLPENSR_BOOTROMLPENS_Msk          (0x1UL << RCC_MEMLPENSR_BOOTROMLPENS_Pos)   /*!< 0x00001000 */
30527 #define RCC_MEMLPENSR_BOOTROMLPENS              RCC_MEMLPENSR_BOOTROMLPENS_Msk       /*!< Boot ROM enable  */
30528 
30529 /****************  Bit definition for RCC_AHB1LPENSR register  ****************/
30530 #define RCC_AHB1LPENSR_GPDMA1LPENS_Pos          (4U)
30531 #define RCC_AHB1LPENSR_GPDMA1LPENS_Msk          (0x1UL << RCC_AHB1LPENSR_GPDMA1LPENS_Pos)   /*!< 0x00000010 */
30532 #define RCC_AHB1LPENSR_GPDMA1LPENS              RCC_AHB1LPENSR_GPDMA1LPENS_Msk       /*!< GPDMA1 enable  */
30533 #define RCC_AHB1LPENSR_ADC12LPENS_Pos           (5U)
30534 #define RCC_AHB1LPENSR_ADC12LPENS_Msk           (0x1UL << RCC_AHB1LPENSR_ADC12LPENS_Pos)  /*!< 0x00000020 */
30535 #define RCC_AHB1LPENSR_ADC12LPENS               RCC_AHB1LPENSR_ADC12LPENS_Msk        /*!< ADC12 enable  */
30536 
30537 /****************  Bit definition for RCC_AHB2LPENSR register  ****************/
30538 #define RCC_AHB2LPENSR_RAMCFGLPENS_Pos          (12U)
30539 #define RCC_AHB2LPENSR_RAMCFGLPENS_Msk          (0x1UL << RCC_AHB2LPENSR_RAMCFGLPENS_Pos)   /*!< 0x00001000 */
30540 #define RCC_AHB2LPENSR_RAMCFGLPENS              RCC_AHB2LPENSR_RAMCFGLPENS_Msk       /*!< RAMCFG enable  */
30541 #define RCC_AHB2LPENSR_MDF1LPENS_Pos            (16U)
30542 #define RCC_AHB2LPENSR_MDF1LPENS_Msk            (0x1UL << RCC_AHB2LPENSR_MDF1LPENS_Pos) /*!< 0x00010000 */
30543 #define RCC_AHB2LPENSR_MDF1LPENS                RCC_AHB2LPENSR_MDF1LPENS_Msk         /*!< MDF1 enable  */
30544 #define RCC_AHB2LPENSR_ADF1LPENS_Pos            (17U)
30545 #define RCC_AHB2LPENSR_ADF1LPENS_Msk            (0x1UL << RCC_AHB2LPENSR_ADF1LPENS_Pos) /*!< 0x00020000 */
30546 #define RCC_AHB2LPENSR_ADF1LPENS                RCC_AHB2LPENSR_ADF1LPENS_Msk         /*!< ADF1 enable  */
30547 
30548 /****************  Bit definition for RCC_AHB3LPENSR register  ****************/
30549 #define RCC_AHB3LPENSR_RNGLPENS_Pos             (0U)
30550 #define RCC_AHB3LPENSR_RNGLPENS_Msk             (0x1UL << RCC_AHB3LPENSR_RNGLPENS_Pos)/*!< 0x00000001 */
30551 #define RCC_AHB3LPENSR_RNGLPENS                 RCC_AHB3LPENSR_RNGLPENS_Msk          /*!< RNG enable  */
30552 #define RCC_AHB3LPENSR_HASHLPENS_Pos            (1U)
30553 #define RCC_AHB3LPENSR_HASHLPENS_Msk            (0x1UL << RCC_AHB3LPENSR_HASHLPENS_Pos) /*!< 0x00000002 */
30554 #define RCC_AHB3LPENSR_HASHLPENS                RCC_AHB3LPENSR_HASHLPENS_Msk         /*!< HASH enable  */
30555 #define RCC_AHB3LPENSR_CRYPLPENS_Pos            (2U)
30556 #define RCC_AHB3LPENSR_CRYPLPENS_Msk            (0x1UL << RCC_AHB3LPENSR_CRYPLPENS_Pos) /*!< 0x00000004 */
30557 #define RCC_AHB3LPENSR_CRYPLPENS                RCC_AHB3LPENSR_CRYPLPENS_Msk         /*!< CRYP enable  */
30558 #define RCC_AHB3LPENSR_SAESLPENS_Pos            (4U)
30559 #define RCC_AHB3LPENSR_SAESLPENS_Msk            (0x1UL << RCC_AHB3LPENSR_SAESLPENS_Pos) /*!< 0x00000010 */
30560 #define RCC_AHB3LPENSR_SAESLPENS                RCC_AHB3LPENSR_SAESLPENS_Msk         /*!< SAES enable  */
30561 #define RCC_AHB3LPENSR_PKALPENS_Pos             (8U)
30562 #define RCC_AHB3LPENSR_PKALPENS_Msk             (0x1UL << RCC_AHB3LPENSR_PKALPENS_Pos)/*!< 0x00000100 */
30563 #define RCC_AHB3LPENSR_PKALPENS                 RCC_AHB3LPENSR_PKALPENS_Msk          /*!< PKA enable  */
30564 #define RCC_AHB3LPENSR_RIFSCLPENS_Pos           (9U)
30565 #define RCC_AHB3LPENSR_RIFSCLPENS_Msk           (0x1UL << RCC_AHB3LPENSR_RIFSCLPENS_Pos)  /*!< 0x00000200 */
30566 #define RCC_AHB3LPENSR_RIFSCLPENS               RCC_AHB3LPENSR_RIFSCLPENS_Msk        /*!< RIFSC enable  */
30567 #define RCC_AHB3LPENSR_IACLPENS_Pos             (10U)
30568 #define RCC_AHB3LPENSR_IACLPENS_Msk             (0x1UL << RCC_AHB3LPENSR_IACLPENS_Pos)/*!< 0x00000400 */
30569 #define RCC_AHB3LPENSR_IACLPENS                 RCC_AHB3LPENSR_IACLPENS_Msk          /*!< IAC enable in Sleep mode */
30570 #define RCC_AHB3LPENSR_RISAFLPENS_Pos           (14U)
30571 #define RCC_AHB3LPENSR_RISAFLPENS_Msk           (0x1UL << RCC_AHB3LPENSR_RISAFLPENS_Pos)  /*!< 0x00004000 */
30572 #define RCC_AHB3LPENSR_RISAFLPENS               RCC_AHB3LPENSR_RISAFLPENS_Msk        /*!< RISAF enable  */
30573 
30574 /****************  Bit definition for RCC_AHB4LPENSR register  ****************/
30575 #define RCC_AHB4LPENSR_GPIOALPENS_Pos           (0U)
30576 #define RCC_AHB4LPENSR_GPIOALPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOALPENS_Pos)  /*!< 0x00000001 */
30577 #define RCC_AHB4LPENSR_GPIOALPENS               RCC_AHB4LPENSR_GPIOALPENS_Msk        /*!< GPIO A enable  */
30578 #define RCC_AHB4LPENSR_GPIOBLPENS_Pos           (1U)
30579 #define RCC_AHB4LPENSR_GPIOBLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOBLPENS_Pos)  /*!< 0x00000002 */
30580 #define RCC_AHB4LPENSR_GPIOBLPENS               RCC_AHB4LPENSR_GPIOBLPENS_Msk        /*!< GPIO B enable  */
30581 #define RCC_AHB4LPENSR_GPIOCLPENS_Pos           (2U)
30582 #define RCC_AHB4LPENSR_GPIOCLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOCLPENS_Pos)  /*!< 0x00000004 */
30583 #define RCC_AHB4LPENSR_GPIOCLPENS               RCC_AHB4LPENSR_GPIOCLPENS_Msk        /*!< GPIO C enable  */
30584 #define RCC_AHB4LPENSR_GPIODLPENS_Pos           (3U)
30585 #define RCC_AHB4LPENSR_GPIODLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIODLPENS_Pos)  /*!< 0x00000008 */
30586 #define RCC_AHB4LPENSR_GPIODLPENS               RCC_AHB4LPENSR_GPIODLPENS_Msk        /*!< GPIO D enable  */
30587 #define RCC_AHB4LPENSR_GPIOELPENS_Pos           (4U)
30588 #define RCC_AHB4LPENSR_GPIOELPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOELPENS_Pos)  /*!< 0x00000010 */
30589 #define RCC_AHB4LPENSR_GPIOELPENS               RCC_AHB4LPENSR_GPIOELPENS_Msk        /*!< GPIO E enable  */
30590 #define RCC_AHB4LPENSR_GPIOFLPENS_Pos           (5U)
30591 #define RCC_AHB4LPENSR_GPIOFLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOFLPENS_Pos)  /*!< 0x00000020 */
30592 #define RCC_AHB4LPENSR_GPIOFLPENS               RCC_AHB4LPENSR_GPIOFLPENS_Msk        /*!< GPIO F enable  */
30593 #define RCC_AHB4LPENSR_GPIOGLPENS_Pos           (6U)
30594 #define RCC_AHB4LPENSR_GPIOGLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOGLPENS_Pos)  /*!< 0x00000040 */
30595 #define RCC_AHB4LPENSR_GPIOGLPENS               RCC_AHB4LPENSR_GPIOGLPENS_Msk        /*!< GPIO G enable  */
30596 #define RCC_AHB4LPENSR_GPIOHLPENS_Pos           (7U)
30597 #define RCC_AHB4LPENSR_GPIOHLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOHLPENS_Pos)  /*!< 0x00000080 */
30598 #define RCC_AHB4LPENSR_GPIOHLPENS               RCC_AHB4LPENSR_GPIOHLPENS_Msk        /*!< GPIO H enable  */
30599 #define RCC_AHB4LPENSR_GPIONLPENS_Pos           (13U)
30600 #define RCC_AHB4LPENSR_GPIONLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIONLPENS_Pos)  /*!< 0x00002000 */
30601 #define RCC_AHB4LPENSR_GPIONLPENS               RCC_AHB4LPENSR_GPIONLPENS_Msk        /*!< GPIO N enable  */
30602 #define RCC_AHB4LPENSR_GPIOOLPENS_Pos           (14U)
30603 #define RCC_AHB4LPENSR_GPIOOLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOOLPENS_Pos)  /*!< 0x00004000 */
30604 #define RCC_AHB4LPENSR_GPIOOLPENS               RCC_AHB4LPENSR_GPIOOLPENS_Msk        /*!< GPIO O enable  */
30605 #define RCC_AHB4LPENSR_GPIOPLPENS_Pos           (15U)
30606 #define RCC_AHB4LPENSR_GPIOPLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOPLPENS_Pos)  /*!< 0x00008000 */
30607 #define RCC_AHB4LPENSR_GPIOPLPENS               RCC_AHB4LPENSR_GPIOPLPENS_Msk        /*!< GPIO P enable  */
30608 #define RCC_AHB4LPENSR_GPIOQLPENS_Pos           (16U)
30609 #define RCC_AHB4LPENSR_GPIOQLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOQLPENS_Pos)  /*!< 0x00010000 */
30610 #define RCC_AHB4LPENSR_GPIOQLPENS               RCC_AHB4LPENSR_GPIOQLPENS_Msk        /*!< GPIO Q enable  */
30611 #define RCC_AHB4LPENSR_PWRLPENS_Pos             (18U)
30612 #define RCC_AHB4LPENSR_PWRLPENS_Msk             (0x1UL << RCC_AHB4LPENSR_PWRLPENS_Pos)/*!< 0x00040000 */
30613 #define RCC_AHB4LPENSR_PWRLPENS                 RCC_AHB4LPENSR_PWRLPENS_Msk          /*!< PWR enable  */
30614 #define RCC_AHB4LPENSR_CRCLPENS_Pos             (19U)
30615 #define RCC_AHB4LPENSR_CRCLPENS_Msk             (0x1UL << RCC_AHB4LPENSR_CRCLPENS_Pos)/*!< 0x00080000 */
30616 #define RCC_AHB4LPENSR_CRCLPENS                 RCC_AHB4LPENSR_CRCLPENS_Msk          /*!< CRC enable  */
30617 
30618 /****************  Bit definition for RCC_AHB5LPENSR register  ****************/
30619 #define RCC_AHB5LPENSR_HPDMA1LPENS_Pos          (0U)
30620 #define RCC_AHB5LPENSR_HPDMA1LPENS_Msk          (0x1UL << RCC_AHB5LPENSR_HPDMA1LPENS_Pos)   /*!< 0x00000001 */
30621 #define RCC_AHB5LPENSR_HPDMA1LPENS              RCC_AHB5LPENSR_HPDMA1LPENS_Msk       /*!< HPDMA1 enable  */
30622 #define RCC_AHB5LPENSR_DMA2DLPENS_Pos           (1U)
30623 #define RCC_AHB5LPENSR_DMA2DLPENS_Msk           (0x1UL << RCC_AHB5LPENSR_DMA2DLPENS_Pos)  /*!< 0x00000002 */
30624 #define RCC_AHB5LPENSR_DMA2DLPENS               RCC_AHB5LPENSR_DMA2DLPENS_Msk        /*!< DMA2D enable  */
30625 #define RCC_AHB5LPENSR_JPEGLPENS_Pos            (3U)
30626 #define RCC_AHB5LPENSR_JPEGLPENS_Msk            (0x1UL << RCC_AHB5LPENSR_JPEGLPENS_Pos) /*!< 0x00000008 */
30627 #define RCC_AHB5LPENSR_JPEGLPENS                RCC_AHB5LPENSR_JPEGLPENS_Msk         /*!< JPEG enable  */
30628 #define RCC_AHB5LPENSR_FMCLPENS_Pos             (4U)
30629 #define RCC_AHB5LPENSR_FMCLPENS_Msk             (0x1UL << RCC_AHB5LPENSR_FMCLPENS_Pos)/*!< 0x00000010 */
30630 #define RCC_AHB5LPENSR_FMCLPENS                 RCC_AHB5LPENSR_FMCLPENS_Msk          /*!< FMC enable  */
30631 #define RCC_AHB5LPENSR_XSPI1LPENS_Pos           (5U)
30632 #define RCC_AHB5LPENSR_XSPI1LPENS_Msk           (0x1UL << RCC_AHB5LPENSR_XSPI1LPENS_Pos)  /*!< 0x00000020 */
30633 #define RCC_AHB5LPENSR_XSPI1LPENS               RCC_AHB5LPENSR_XSPI1LPENS_Msk        /*!< XSPI1 enable  */
30634 #define RCC_AHB5LPENSR_PSSILPENS_Pos            (6U)
30635 #define RCC_AHB5LPENSR_PSSILPENS_Msk            (0x1UL << RCC_AHB5LPENSR_PSSILPENS_Pos) /*!< 0x00000040 */
30636 #define RCC_AHB5LPENSR_PSSILPENS                RCC_AHB5LPENSR_PSSILPENS_Msk         /*!< PSSI enable  */
30637 #define RCC_AHB5LPENSR_SDMMC2LPENS_Pos          (7U)
30638 #define RCC_AHB5LPENSR_SDMMC2LPENS_Msk          (0x1UL << RCC_AHB5LPENSR_SDMMC2LPENS_Pos)   /*!< 0x00000080 */
30639 #define RCC_AHB5LPENSR_SDMMC2LPENS              RCC_AHB5LPENSR_SDMMC2LPENS_Msk       /*!< SDMMC2 enable  */
30640 #define RCC_AHB5LPENSR_SDMMC1LPENS_Pos          (8U)
30641 #define RCC_AHB5LPENSR_SDMMC1LPENS_Msk          (0x1UL << RCC_AHB5LPENSR_SDMMC1LPENS_Pos)   /*!< 0x00000100 */
30642 #define RCC_AHB5LPENSR_SDMMC1LPENS              RCC_AHB5LPENSR_SDMMC1LPENS_Msk       /*!< SDMMC1 enable  */
30643 #define RCC_AHB5LPENSR_XSPI2LPENS_Pos           (12U)
30644 #define RCC_AHB5LPENSR_XSPI2LPENS_Msk           (0x1UL << RCC_AHB5LPENSR_XSPI2LPENS_Pos)  /*!< 0x00001000 */
30645 #define RCC_AHB5LPENSR_XSPI2LPENS               RCC_AHB5LPENSR_XSPI2LPENS_Msk        /*!< XSPI2 enable  */
30646 #define RCC_AHB5LPENSR_XSPIMLPENS_Pos           (13U)
30647 #define RCC_AHB5LPENSR_XSPIMLPENS_Msk           (0x1UL << RCC_AHB5LPENSR_XSPIMLPENS_Pos)  /*!< 0x00002000 */
30648 #define RCC_AHB5LPENSR_XSPIMLPENS               RCC_AHB5LPENSR_XSPIMLPENS_Msk        /*!< XSPIM enable  */
30649 #define RCC_AHB5LPENSR_MCE1LPENS_Pos            (14U)
30650 #define RCC_AHB5LPENSR_MCE1LPENS_Msk            (0x1UL << RCC_AHB5LPENSR_MCE1LPENS_Pos) /*!< 0x00004000 */
30651 #define RCC_AHB5LPENSR_MCE1LPENS                RCC_AHB5LPENSR_MCE1LPENS_Msk         /*!< MCE1 enable  */
30652 #define RCC_AHB5LPENSR_MCE2LPENS_Pos            (15U)
30653 #define RCC_AHB5LPENSR_MCE2LPENS_Msk            (0x1UL << RCC_AHB5LPENSR_MCE2LPENS_Pos) /*!< 0x00008000 */
30654 #define RCC_AHB5LPENSR_MCE2LPENS                RCC_AHB5LPENSR_MCE2LPENS_Msk         /*!< MCE2 enable  */
30655 #define RCC_AHB5LPENSR_MCE3LPENS_Pos            (16U)
30656 #define RCC_AHB5LPENSR_MCE3LPENS_Msk            (0x1UL << RCC_AHB5LPENSR_MCE3LPENS_Pos) /*!< 0x00010000 */
30657 #define RCC_AHB5LPENSR_MCE3LPENS                RCC_AHB5LPENSR_MCE3LPENS_Msk         /*!< MCE3 enable  */
30658 #define RCC_AHB5LPENSR_XSPI3LPENS_Pos           (17U)
30659 #define RCC_AHB5LPENSR_XSPI3LPENS_Msk           (0x1UL << RCC_AHB5LPENSR_XSPI3LPENS_Pos)  /*!< 0x00020000 */
30660 #define RCC_AHB5LPENSR_XSPI3LPENS               RCC_AHB5LPENSR_XSPI3LPENS_Msk        /*!< XSPI3 enable  */
30661 #define RCC_AHB5LPENSR_MCE4LPENS_Pos            (18U)
30662 #define RCC_AHB5LPENSR_MCE4LPENS_Msk            (0x1UL << RCC_AHB5LPENSR_MCE4LPENS_Pos) /*!< 0x00040000 */
30663 #define RCC_AHB5LPENSR_MCE4LPENS                RCC_AHB5LPENSR_MCE4LPENS_Msk         /*!< MCE4 enable  */
30664 #define RCC_AHB5LPENSR_GFXMMULPENS_Pos          (19U)
30665 #define RCC_AHB5LPENSR_GFXMMULPENS_Msk          (0x1UL << RCC_AHB5LPENSR_GFXMMULPENS_Pos)   /*!< 0x00080000 */
30666 #define RCC_AHB5LPENSR_GFXMMULPENS              RCC_AHB5LPENSR_GFXMMULPENS_Msk       /*!< GFXMMU enable  */
30667 #define RCC_AHB5LPENSR_GPU2DLPENS_Pos           (20U)
30668 #define RCC_AHB5LPENSR_GPU2DLPENS_Msk           (0x1UL << RCC_AHB5LPENSR_GPU2DLPENS_Pos)  /*!< 0x00100000 */
30669 #define RCC_AHB5LPENSR_GPU2DLPENS               RCC_AHB5LPENSR_GPU2DLPENS_Msk        /*!< GPU2D enable */
30670 #define RCC_AHB5LPENSR_ETH1MACLPENS_Pos         (22U)
30671 #define RCC_AHB5LPENSR_ETH1MACLPENS_Msk         (0x1UL << RCC_AHB5LPENSR_ETH1MACLPENS_Pos)    /*!< 0x00400000 */
30672 #define RCC_AHB5LPENSR_ETH1MACLPENS             RCC_AHB5LPENSR_ETH1MACLPENS_Msk      /*!< ETH1MAC enable  */
30673 #define RCC_AHB5LPENSR_ETH1TXLPENS_Pos          (23U)
30674 #define RCC_AHB5LPENSR_ETH1TXLPENS_Msk          (0x1UL << RCC_AHB5LPENSR_ETH1TXLPENS_Pos)   /*!< 0x00800000 */
30675 #define RCC_AHB5LPENSR_ETH1TXLPENS              RCC_AHB5LPENSR_ETH1TXLPENS_Msk       /*!< ETH1TX enable  */
30676 #define RCC_AHB5LPENSR_ETH1RXLPENS_Pos          (24U)
30677 #define RCC_AHB5LPENSR_ETH1RXLPENS_Msk          (0x1UL << RCC_AHB5LPENSR_ETH1RXLPENS_Pos)   /*!< 0x01000000 */
30678 #define RCC_AHB5LPENSR_ETH1RXLPENS              RCC_AHB5LPENSR_ETH1RXLPENS_Msk       /*!< ETH1RX enable  */
30679 #define RCC_AHB5LPENSR_ETH1LPENS_Pos            (25U)
30680 #define RCC_AHB5LPENSR_ETH1LPENS_Msk            (0x1UL << RCC_AHB5LPENSR_ETH1LPENS_Pos) /*!< 0x02000000 */
30681 #define RCC_AHB5LPENSR_ETH1LPENS                RCC_AHB5LPENSR_ETH1LPENS_Msk         /*!< ETH1 enable  */
30682 #define RCC_AHB5LPENSR_OTG1LPENS_Pos            (26U)
30683 #define RCC_AHB5LPENSR_OTG1LPENS_Msk            (0x1UL << RCC_AHB5LPENSR_OTG1LPENS_Pos) /*!< 0x04000000 */
30684 #define RCC_AHB5LPENSR_OTG1LPENS                RCC_AHB5LPENSR_OTG1LPENS_Msk         /*!< OTG1 enable  */
30685 #define RCC_AHB5LPENSR_OTGPHY1LPENS_Pos         (27U)
30686 #define RCC_AHB5LPENSR_OTGPHY1LPENS_Msk         (0x1UL << RCC_AHB5LPENSR_OTGPHY1LPENS_Pos)    /*!< 0x08000000 */
30687 #define RCC_AHB5LPENSR_OTGPHY1LPENS             RCC_AHB5LPENSR_OTGPHY1LPENS_Msk      /*!< OTGPHY1 enable  */
30688 #define RCC_AHB5LPENSR_OTGPHY2LPENS_Pos         (28U)
30689 #define RCC_AHB5LPENSR_OTGPHY2LPENS_Msk         (0x1UL << RCC_AHB5LPENSR_OTGPHY2LPENS_Pos)    /*!< 0x10000000 */
30690 #define RCC_AHB5LPENSR_OTGPHY2LPENS             RCC_AHB5LPENSR_OTGPHY2LPENS_Msk      /*!< OTGPHY2 enable  */
30691 #define RCC_AHB5LPENSR_OTG2LPENS_Pos            (29U)
30692 #define RCC_AHB5LPENSR_OTG2LPENS_Msk            (0x1UL << RCC_AHB5LPENSR_OTG2LPENS_Pos) /*!< 0x20000000 */
30693 #define RCC_AHB5LPENSR_OTG2LPENS                RCC_AHB5LPENSR_OTG2LPENS_Msk         /*!< OTG2 enable  */
30694 #define RCC_AHB5LPENSR_CACHEAXILPENS_Pos        (30U)
30695 #define RCC_AHB5LPENSR_CACHEAXILPENS_Msk        (0x1UL << RCC_AHB5LPENSR_CACHEAXILPENS_Pos)     /*!< 0x40000000 */
30696 #define RCC_AHB5LPENSR_CACHEAXILPENS            RCC_AHB5LPENSR_CACHEAXILPENS_Msk     /*!< CACHEAXI enable  */
30697 #define RCC_AHB5LPENSR_NPULPENS_Pos             (31U)
30698 #define RCC_AHB5LPENSR_NPULPENS_Msk             (0x1UL << RCC_AHB5LPENSR_NPULPENS_Pos)/*!< 0x80000000 */
30699 #define RCC_AHB5LPENSR_NPULPENS                 RCC_AHB5LPENSR_NPULPENS_Msk          /*!< NPU enable  */
30700 
30701 /***************  Bit definition for RCC_APB1LPENSR1 register  ****************/
30702 #define RCC_APB1LPENSR1_TIM2LPENS_Pos           (0U)
30703 #define RCC_APB1LPENSR1_TIM2LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_TIM2LPENS_Pos)  /*!< 0x00000001 */
30704 #define RCC_APB1LPENSR1_TIM2LPENS               RCC_APB1LPENSR1_TIM2LPENS_Msk        /*!< TIM2 enable  */
30705 #define RCC_APB1LPENSR1_TIM3LPENS_Pos           (1U)
30706 #define RCC_APB1LPENSR1_TIM3LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_TIM3LPENS_Pos)  /*!< 0x00000002 */
30707 #define RCC_APB1LPENSR1_TIM3LPENS               RCC_APB1LPENSR1_TIM3LPENS_Msk        /*!< TIM3 enable  */
30708 #define RCC_APB1LPENSR1_TIM4LPENS_Pos           (2U)
30709 #define RCC_APB1LPENSR1_TIM4LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_TIM4LPENS_Pos)  /*!< 0x00000004 */
30710 #define RCC_APB1LPENSR1_TIM4LPENS               RCC_APB1LPENSR1_TIM4LPENS_Msk        /*!< TIM4 enable  */
30711 #define RCC_APB1LPENSR1_TIM5LPENS_Pos           (3U)
30712 #define RCC_APB1LPENSR1_TIM5LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_TIM5LPENS_Pos)  /*!< 0x00000008 */
30713 #define RCC_APB1LPENSR1_TIM5LPENS               RCC_APB1LPENSR1_TIM5LPENS_Msk        /*!< TIM5 enable  */
30714 #define RCC_APB1LPENSR1_TIM6LPENS_Pos           (4U)
30715 #define RCC_APB1LPENSR1_TIM6LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_TIM6LPENS_Pos)  /*!< 0x00000010 */
30716 #define RCC_APB1LPENSR1_TIM6LPENS               RCC_APB1LPENSR1_TIM6LPENS_Msk        /*!< TIM6 enable  */
30717 #define RCC_APB1LPENSR1_TIM7LPENS_Pos           (5U)
30718 #define RCC_APB1LPENSR1_TIM7LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_TIM7LPENS_Pos)  /*!< 0x00000020 */
30719 #define RCC_APB1LPENSR1_TIM7LPENS               RCC_APB1LPENSR1_TIM7LPENS_Msk        /*!< TIM7 enable  */
30720 #define RCC_APB1LPENSR1_TIM12LPENS_Pos          (6U)
30721 #define RCC_APB1LPENSR1_TIM12LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_TIM12LPENS_Pos)   /*!< 0x00000040 */
30722 #define RCC_APB1LPENSR1_TIM12LPENS              RCC_APB1LPENSR1_TIM12LPENS_Msk       /*!< TIM12 enable  */
30723 #define RCC_APB1LPENSR1_TIM13LPENS_Pos          (7U)
30724 #define RCC_APB1LPENSR1_TIM13LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_TIM13LPENS_Pos)   /*!< 0x00000080 */
30725 #define RCC_APB1LPENSR1_TIM13LPENS              RCC_APB1LPENSR1_TIM13LPENS_Msk       /*!< TIM13 enable  */
30726 #define RCC_APB1LPENSR1_TIM14LPENS_Pos          (8U)
30727 #define RCC_APB1LPENSR1_TIM14LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_TIM14LPENS_Pos)   /*!< 0x00000100 */
30728 #define RCC_APB1LPENSR1_TIM14LPENS              RCC_APB1LPENSR1_TIM14LPENS_Msk       /*!< TIM14 enable  */
30729 #define RCC_APB1LPENSR1_LPTIM1LPENS_Pos         (9U)
30730 #define RCC_APB1LPENSR1_LPTIM1LPENS_Msk         (0x1UL << RCC_APB1LPENSR1_LPTIM1LPENS_Pos)    /*!< 0x00000200 */
30731 #define RCC_APB1LPENSR1_LPTIM1LPENS             RCC_APB1LPENSR1_LPTIM1LPENS_Msk      /*!< LPTIM1 enable  */
30732 #define RCC_APB1LPENSR1_WWDGLPENS_Pos           (11U)
30733 #define RCC_APB1LPENSR1_WWDGLPENS_Msk           (0x1UL << RCC_APB1LPENSR1_WWDGLPENS_Pos)  /*!< 0x00000800 */
30734 #define RCC_APB1LPENSR1_WWDGLPENS               RCC_APB1LPENSR1_WWDGLPENS_Msk        /*!< WWDG enable  */
30735 #define RCC_APB1LPENSR1_TIM10LPENS_Pos          (12U)
30736 #define RCC_APB1LPENSR1_TIM10LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_TIM10LPENS_Pos)   /*!< 0x00001000 */
30737 #define RCC_APB1LPENSR1_TIM10LPENS              RCC_APB1LPENSR1_TIM10LPENS_Msk       /*!< TIM10 enable  */
30738 #define RCC_APB1LPENSR1_TIM11LPENS_Pos          (13U)
30739 #define RCC_APB1LPENSR1_TIM11LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_TIM11LPENS_Pos)   /*!< 0x00002000 */
30740 #define RCC_APB1LPENSR1_TIM11LPENS              RCC_APB1LPENSR1_TIM11LPENS_Msk       /*!< TIM11 enable  */
30741 #define RCC_APB1LPENSR1_SPI2LPENS_Pos           (14U)
30742 #define RCC_APB1LPENSR1_SPI2LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_SPI2LPENS_Pos)  /*!< 0x00004000 */
30743 #define RCC_APB1LPENSR1_SPI2LPENS               RCC_APB1LPENSR1_SPI2LPENS_Msk        /*!< SPI2 enable  */
30744 #define RCC_APB1LPENSR1_SPI3LPENS_Pos           (15U)
30745 #define RCC_APB1LPENSR1_SPI3LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_SPI3LPENS_Pos)  /*!< 0x00008000 */
30746 #define RCC_APB1LPENSR1_SPI3LPENS               RCC_APB1LPENSR1_SPI3LPENS_Msk        /*!< SPI3 enable  */
30747 #define RCC_APB1LPENSR1_SPDIFRX1LPENS_Pos       (16U)
30748 #define RCC_APB1LPENSR1_SPDIFRX1LPENS_Msk       (0x1UL << RCC_APB1LPENSR1_SPDIFRX1LPENS_Pos)      /*!< 0x00010000 */
30749 #define RCC_APB1LPENSR1_SPDIFRX1LPENS           RCC_APB1LPENSR1_SPDIFRX1LPENS_Msk    /*!< SPDIFRX1 enable  */
30750 #define RCC_APB1LPENSR1_USART2LPENS_Pos         (17U)
30751 #define RCC_APB1LPENSR1_USART2LPENS_Msk         (0x1UL << RCC_APB1LPENSR1_USART2LPENS_Pos)    /*!< 0x00020000 */
30752 #define RCC_APB1LPENSR1_USART2LPENS             RCC_APB1LPENSR1_USART2LPENS_Msk      /*!< USART2 enable  */
30753 #define RCC_APB1LPENSR1_USART3LPENS_Pos         (18U)
30754 #define RCC_APB1LPENSR1_USART3LPENS_Msk         (0x1UL << RCC_APB1LPENSR1_USART3LPENS_Pos)    /*!< 0x00040000 */
30755 #define RCC_APB1LPENSR1_USART3LPENS             RCC_APB1LPENSR1_USART3LPENS_Msk      /*!< USART3 enable  */
30756 #define RCC_APB1LPENSR1_UART4LPENS_Pos          (19U)
30757 #define RCC_APB1LPENSR1_UART4LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_UART4LPENS_Pos)   /*!< 0x00080000 */
30758 #define RCC_APB1LPENSR1_UART4LPENS              RCC_APB1LPENSR1_UART4LPENS_Msk       /*!< UART4 enable  */
30759 #define RCC_APB1LPENSR1_UART5LPENS_Pos          (20U)
30760 #define RCC_APB1LPENSR1_UART5LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_UART5LPENS_Pos)   /*!< 0x00100000 */
30761 #define RCC_APB1LPENSR1_UART5LPENS              RCC_APB1LPENSR1_UART5LPENS_Msk       /*!< UART5 enable  */
30762 #define RCC_APB1LPENSR1_I2C1LPENS_Pos           (21U)
30763 #define RCC_APB1LPENSR1_I2C1LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_I2C1LPENS_Pos)  /*!< 0x00200000 */
30764 #define RCC_APB1LPENSR1_I2C1LPENS               RCC_APB1LPENSR1_I2C1LPENS_Msk        /*!< I2C1 enable  */
30765 #define RCC_APB1LPENSR1_I2C2LPENS_Pos           (22U)
30766 #define RCC_APB1LPENSR1_I2C2LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_I2C2LPENS_Pos)  /*!< 0x00400000 */
30767 #define RCC_APB1LPENSR1_I2C2LPENS               RCC_APB1LPENSR1_I2C2LPENS_Msk        /*!< I2C2 enable  */
30768 #define RCC_APB1LPENSR1_I2C3LPENS_Pos           (23U)
30769 #define RCC_APB1LPENSR1_I2C3LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_I2C3LPENS_Pos)  /*!< 0x00800000 */
30770 #define RCC_APB1LPENSR1_I2C3LPENS               RCC_APB1LPENSR1_I2C3LPENS_Msk        /*!< I2C3 enable  */
30771 #define RCC_APB1LPENSR1_I3C1LPENS_Pos           (24U)
30772 #define RCC_APB1LPENSR1_I3C1LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_I3C1LPENS_Pos)  /*!< 0x01000000 */
30773 #define RCC_APB1LPENSR1_I3C1LPENS               RCC_APB1LPENSR1_I3C1LPENS_Msk        /*!< I3C1 enable  */
30774 #define RCC_APB1LPENSR1_I3C2LPENS_Pos           (25U)
30775 #define RCC_APB1LPENSR1_I3C2LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_I3C2LPENS_Pos)  /*!< 0x02000000 */
30776 #define RCC_APB1LPENSR1_I3C2LPENS               RCC_APB1LPENSR1_I3C2LPENS_Msk        /*!< I3C2 enable  */
30777 #define RCC_APB1LPENSR1_UART7LPENS_Pos          (30U)
30778 #define RCC_APB1LPENSR1_UART7LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_UART7LPENS_Pos)   /*!< 0x40000000 */
30779 #define RCC_APB1LPENSR1_UART7LPENS              RCC_APB1LPENSR1_UART7LPENS_Msk       /*!< UART7 enable  */
30780 #define RCC_APB1LPENSR1_UART8LPENS_Pos          (31U)
30781 #define RCC_APB1LPENSR1_UART8LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_UART8LPENS_Pos)   /*!< 0x80000000 */
30782 #define RCC_APB1LPENSR1_UART8LPENS              RCC_APB1LPENSR1_UART8LPENS_Msk       /*!< UART8 enable  */
30783 
30784 /***************  Bit definition for RCC_APB1LPENSR2 register  ****************/
30785 #define RCC_APB1LPENSR2_MDIOSLPENS_Pos          (5U)
30786 #define RCC_APB1LPENSR2_MDIOSLPENS_Msk          (0x1UL << RCC_APB1LPENSR2_MDIOSLPENS_Pos)   /*!< 0x00000020 */
30787 #define RCC_APB1LPENSR2_MDIOSLPENS              RCC_APB1LPENSR2_MDIOSLPENS_Msk       /*!< MDIOS enable  */
30788 #define RCC_APB1LPENSR2_FDCANLPENS_Pos          (8U)
30789 #define RCC_APB1LPENSR2_FDCANLPENS_Msk          (0x1UL << RCC_APB1LPENSR2_FDCANLPENS_Pos)   /*!< 0x00000100 */
30790 #define RCC_APB1LPENSR2_FDCANLPENS              RCC_APB1LPENSR2_FDCANLPENS_Msk       /*!< FDCAN enable  */
30791 #define RCC_APB1LPENSR2_UCPD1LPENS_Pos          (18U)
30792 #define RCC_APB1LPENSR2_UCPD1LPENS_Msk          (0x1UL << RCC_APB1LPENSR2_UCPD1LPENS_Pos)   /*!< 0x00040000 */
30793 #define RCC_APB1LPENSR2_UCPD1LPENS              RCC_APB1LPENSR2_UCPD1LPENS_Msk       /*!< UCPD1 enable  */
30794 
30795 /****************  Bit definition for RCC_APB2LPENSR register  ****************/
30796 #define RCC_APB2LPENSR_TIM1LPENS_Pos            (0U)
30797 #define RCC_APB2LPENSR_TIM1LPENS_Msk            (0x1UL << RCC_APB2LPENSR_TIM1LPENS_Pos) /*!< 0x00000001 */
30798 #define RCC_APB2LPENSR_TIM1LPENS                RCC_APB2LPENSR_TIM1LPENS_Msk         /*!< TIM1 enable  */
30799 #define RCC_APB2LPENSR_TIM8LPENS_Pos            (1U)
30800 #define RCC_APB2LPENSR_TIM8LPENS_Msk            (0x1UL << RCC_APB2LPENSR_TIM8LPENS_Pos) /*!< 0x00000002 */
30801 #define RCC_APB2LPENSR_TIM8LPENS                RCC_APB2LPENSR_TIM8LPENS_Msk         /*!< TIM8 enable  */
30802 #define RCC_APB2LPENSR_USART1LPENS_Pos          (4U)
30803 #define RCC_APB2LPENSR_USART1LPENS_Msk          (0x1UL << RCC_APB2LPENSR_USART1LPENS_Pos)   /*!< 0x00000010 */
30804 #define RCC_APB2LPENSR_USART1LPENS              RCC_APB2LPENSR_USART1LPENS_Msk       /*!< USART1 enable  */
30805 #define RCC_APB2LPENSR_USART6LPENS_Pos          (5U)
30806 #define RCC_APB2LPENSR_USART6LPENS_Msk          (0x1UL << RCC_APB2LPENSR_USART6LPENS_Pos)   /*!< 0x00000020 */
30807 #define RCC_APB2LPENSR_USART6LPENS              RCC_APB2LPENSR_USART6LPENS_Msk       /*!< USART6 enable  */
30808 #define RCC_APB2LPENSR_UART9LPENS_Pos           (6U)
30809 #define RCC_APB2LPENSR_UART9LPENS_Msk           (0x1UL << RCC_APB2LPENSR_UART9LPENS_Pos)  /*!< 0x00000040 */
30810 #define RCC_APB2LPENSR_UART9LPENS               RCC_APB2LPENSR_UART9LPENS_Msk        /*!< UART9 enable  */
30811 #define RCC_APB2LPENSR_USART10LPENS_Pos         (7U)
30812 #define RCC_APB2LPENSR_USART10LPENS_Msk         (0x1UL << RCC_APB2LPENSR_USART10LPENS_Pos)    /*!< 0x00000080 */
30813 #define RCC_APB2LPENSR_USART10LPENS             RCC_APB2LPENSR_USART10LPENS_Msk      /*!< USART10 enable  */
30814 #define RCC_APB2LPENSR_SPI1LPENS_Pos            (12U)
30815 #define RCC_APB2LPENSR_SPI1LPENS_Msk            (0x1UL << RCC_APB2LPENSR_SPI1LPENS_Pos) /*!< 0x00001000 */
30816 #define RCC_APB2LPENSR_SPI1LPENS                RCC_APB2LPENSR_SPI1LPENS_Msk         /*!< SPI1 enable  */
30817 #define RCC_APB2LPENSR_SPI4LPENS_Pos            (13U)
30818 #define RCC_APB2LPENSR_SPI4LPENS_Msk            (0x1UL << RCC_APB2LPENSR_SPI4LPENS_Pos) /*!< 0x00002000 */
30819 #define RCC_APB2LPENSR_SPI4LPENS                RCC_APB2LPENSR_SPI4LPENS_Msk         /*!< SPI4 enable  */
30820 #define RCC_APB2LPENSR_TIM18LPENS_Pos           (15U)
30821 #define RCC_APB2LPENSR_TIM18LPENS_Msk           (0x1UL << RCC_APB2LPENSR_TIM18LPENS_Pos)  /*!< 0x00008000 */
30822 #define RCC_APB2LPENSR_TIM18LPENS               RCC_APB2LPENSR_TIM18LPENS_Msk        /*!< TIM18 enable  */
30823 #define RCC_APB2LPENSR_TIM15LPENS_Pos           (16U)
30824 #define RCC_APB2LPENSR_TIM15LPENS_Msk           (0x1UL << RCC_APB2LPENSR_TIM15LPENS_Pos)  /*!< 0x00010000 */
30825 #define RCC_APB2LPENSR_TIM15LPENS               RCC_APB2LPENSR_TIM15LPENS_Msk        /*!< TIM15 enable  */
30826 #define RCC_APB2LPENSR_TIM16LPENS_Pos           (17U)
30827 #define RCC_APB2LPENSR_TIM16LPENS_Msk           (0x1UL << RCC_APB2LPENSR_TIM16LPENS_Pos)  /*!< 0x00020000 */
30828 #define RCC_APB2LPENSR_TIM16LPENS               RCC_APB2LPENSR_TIM16LPENS_Msk        /*!< TIM16 enable  */
30829 #define RCC_APB2LPENSR_TIM17LPENS_Pos           (18U)
30830 #define RCC_APB2LPENSR_TIM17LPENS_Msk           (0x1UL << RCC_APB2LPENSR_TIM17LPENS_Pos)  /*!< 0x00040000 */
30831 #define RCC_APB2LPENSR_TIM17LPENS               RCC_APB2LPENSR_TIM17LPENS_Msk        /*!< TIM17 enable  */
30832 #define RCC_APB2LPENSR_TIM9LPENS_Pos            (19U)
30833 #define RCC_APB2LPENSR_TIM9LPENS_Msk            (0x1UL << RCC_APB2LPENSR_TIM9LPENS_Pos) /*!< 0x00080000 */
30834 #define RCC_APB2LPENSR_TIM9LPENS                RCC_APB2LPENSR_TIM9LPENS_Msk         /*!< TIM9 enable  */
30835 #define RCC_APB2LPENSR_SPI5LPENS_Pos            (20U)
30836 #define RCC_APB2LPENSR_SPI5LPENS_Msk            (0x1UL << RCC_APB2LPENSR_SPI5LPENS_Pos) /*!< 0x00100000 */
30837 #define RCC_APB2LPENSR_SPI5LPENS                RCC_APB2LPENSR_SPI5LPENS_Msk         /*!< SPI5 enable  */
30838 #define RCC_APB2LPENSR_SAI1LPENS_Pos            (21U)
30839 #define RCC_APB2LPENSR_SAI1LPENS_Msk            (0x1UL << RCC_APB2LPENSR_SAI1LPENS_Pos) /*!< 0x00200000 */
30840 #define RCC_APB2LPENSR_SAI1LPENS                RCC_APB2LPENSR_SAI1LPENS_Msk         /*!< SAI1 enable  */
30841 #define RCC_APB2LPENSR_SAI2LPENS_Pos            (22U)
30842 #define RCC_APB2LPENSR_SAI2LPENS_Msk            (0x1UL << RCC_APB2LPENSR_SAI2LPENS_Pos) /*!< 0x00400000 */
30843 #define RCC_APB2LPENSR_SAI2LPENS                RCC_APB2LPENSR_SAI2LPENS_Msk         /*!< SAI2 enable  */
30844 
30845 /****************  Bit definition for RCC_APB3LPENSR register  ****************/
30846 #define RCC_APB3LPENSR_DFTLPENS_Pos             (2U)
30847 #define RCC_APB3LPENSR_DFTLPENS_Msk             (0x1UL << RCC_APB3LPENSR_DFTLPENS_Pos)/*!< 0x00000004 */
30848 #define RCC_APB3LPENSR_DFTLPENS                 RCC_APB3LPENSR_DFTLPENS_Msk          /*!< DFT enable  */
30849 
30850 /***************  Bit definition for RCC_APB4LPENSR1 register  ****************/
30851 #define RCC_APB4LPENSR1_HDPLPENS_Pos            (2U)
30852 #define RCC_APB4LPENSR1_HDPLPENS_Msk            (0x1UL << RCC_APB4LPENSR1_HDPLPENS_Pos) /*!< 0x00000004 */
30853 #define RCC_APB4LPENSR1_HDPLPENS                RCC_APB4LPENSR1_HDPLPENS_Msk         /*!< HDP enable  */
30854 #define RCC_APB4LPENSR1_LPUART1LPENS_Pos        (3U)
30855 #define RCC_APB4LPENSR1_LPUART1LPENS_Msk        (0x1UL << RCC_APB4LPENSR1_LPUART1LPENS_Pos)     /*!< 0x00000008 */
30856 #define RCC_APB4LPENSR1_LPUART1LPENS            RCC_APB4LPENSR1_LPUART1LPENS_Msk     /*!< LPUART1 enable  */
30857 #define RCC_APB4LPENSR1_SPI6LPENS_Pos           (5U)
30858 #define RCC_APB4LPENSR1_SPI6LPENS_Msk           (0x1UL << RCC_APB4LPENSR1_SPI6LPENS_Pos)  /*!< 0x00000020 */
30859 #define RCC_APB4LPENSR1_SPI6LPENS               RCC_APB4LPENSR1_SPI6LPENS_Msk        /*!< SPI6 enable  */
30860 #define RCC_APB4LPENSR1_I2C4LPENS_Pos           (7U)
30861 #define RCC_APB4LPENSR1_I2C4LPENS_Msk           (0x1UL << RCC_APB4LPENSR1_I2C4LPENS_Pos)  /*!< 0x00000080 */
30862 #define RCC_APB4LPENSR1_I2C4LPENS               RCC_APB4LPENSR1_I2C4LPENS_Msk        /*!< I2C4 enable  */
30863 #define RCC_APB4LPENSR1_LPTIM2LPENS_Pos         (9U)
30864 #define RCC_APB4LPENSR1_LPTIM2LPENS_Msk         (0x1UL << RCC_APB4LPENSR1_LPTIM2LPENS_Pos)    /*!< 0x00000200 */
30865 #define RCC_APB4LPENSR1_LPTIM2LPENS             RCC_APB4LPENSR1_LPTIM2LPENS_Msk      /*!< LPTIM2 enable  */
30866 #define RCC_APB4LPENSR1_LPTIM3LPENS_Pos         (10U)
30867 #define RCC_APB4LPENSR1_LPTIM3LPENS_Msk         (0x1UL << RCC_APB4LPENSR1_LPTIM3LPENS_Pos)    /*!< 0x00000400 */
30868 #define RCC_APB4LPENSR1_LPTIM3LPENS             RCC_APB4LPENSR1_LPTIM3LPENS_Msk      /*!< LPTIM3 enable  */
30869 #define RCC_APB4LPENSR1_LPTIM4LPENS_Pos         (11U)
30870 #define RCC_APB4LPENSR1_LPTIM4LPENS_Msk         (0x1UL << RCC_APB4LPENSR1_LPTIM4LPENS_Pos)    /*!< 0x00000800 */
30871 #define RCC_APB4LPENSR1_LPTIM4LPENS             RCC_APB4LPENSR1_LPTIM4LPENS_Msk      /*!< LPTIM4 enable  */
30872 #define RCC_APB4LPENSR1_LPTIM5LPENS_Pos         (12U)
30873 #define RCC_APB4LPENSR1_LPTIM5LPENS_Msk         (0x1UL << RCC_APB4LPENSR1_LPTIM5LPENS_Pos)    /*!< 0x00001000 */
30874 #define RCC_APB4LPENSR1_LPTIM5LPENS             RCC_APB4LPENSR1_LPTIM5LPENS_Msk      /*!< LPTIM5 enable  */
30875 #define RCC_APB4LPENSR1_VREFBUFLPENS_Pos        (15U)
30876 #define RCC_APB4LPENSR1_VREFBUFLPENS_Msk        (0x1UL << RCC_APB4LPENSR1_VREFBUFLPENS_Pos)     /*!< 0x00008000 */
30877 #define RCC_APB4LPENSR1_VREFBUFLPENS            RCC_APB4LPENSR1_VREFBUFLPENS_Msk     /*!< VREFBUF enable  */
30878 #define RCC_APB4LPENSR1_RTCLPENS_Pos            (16U)
30879 #define RCC_APB4LPENSR1_RTCLPENS_Msk            (0x1UL << RCC_APB4LPENSR1_RTCLPENS_Pos) /*!< 0x00010000 */
30880 #define RCC_APB4LPENSR1_RTCLPENS                RCC_APB4LPENSR1_RTCLPENS_Msk         /*!< RTC enable  */
30881 #define RCC_APB4LPENSR1_RTCAPBLPENS_Pos         (17U)
30882 #define RCC_APB4LPENSR1_RTCAPBLPENS_Msk         (0x1UL << RCC_APB4LPENSR1_RTCAPBLPENS_Pos)    /*!< 0x00020000 */
30883 #define RCC_APB4LPENSR1_RTCAPBLPENS             RCC_APB4LPENSR1_RTCAPBLPENS_Msk      /*!< RTCAPB enable  */
30884 
30885 /***************  Bit definition for RCC_APB4LPENSR2 register  ****************/
30886 #define RCC_APB4LPENSR2_SYSCFGLPENS_Pos         (0U)
30887 #define RCC_APB4LPENSR2_SYSCFGLPENS_Msk         (0x1UL << RCC_APB4LPENSR2_SYSCFGLPENS_Pos)    /*!< 0x00000001 */
30888 #define RCC_APB4LPENSR2_SYSCFGLPENS             RCC_APB4LPENSR2_SYSCFGLPENS_Msk      /*!< SYSCFG enable  */
30889 #define RCC_APB4LPENSR2_BSECLPENS_Pos           (1U)
30890 #define RCC_APB4LPENSR2_BSECLPENS_Msk           (0x1UL << RCC_APB4LPENSR2_BSECLPENS_Pos)  /*!< 0x00000002 */
30891 #define RCC_APB4LPENSR2_BSECLPENS               RCC_APB4LPENSR2_BSECLPENS_Msk        /*!< BSEC enable  */
30892 #define RCC_APB4LPENSR2_DTSLPENS_Pos            (2U)
30893 #define RCC_APB4LPENSR2_DTSLPENS_Msk            (0x1UL << RCC_APB4LPENSR2_DTSLPENS_Pos) /*!< 0x00000004 */
30894 #define RCC_APB4LPENSR2_DTSLPENS                RCC_APB4LPENSR2_DTSLPENS_Msk         /*!< DTS enable  */
30895 
30896 /****************  Bit definition for RCC_APB5LPENSR register  ****************/
30897 #define RCC_APB5LPENSR_LTDCLPENS_Pos            (1U)
30898 #define RCC_APB5LPENSR_LTDCLPENS_Msk            (0x1UL << RCC_APB5LPENSR_LTDCLPENS_Pos) /*!< 0x00000002 */
30899 #define RCC_APB5LPENSR_LTDCLPENS                RCC_APB5LPENSR_LTDCLPENS_Msk         /*!< LTDC enable */
30900 #define RCC_APB5LPENSR_DCMIPPLPENS_Pos          (2U)
30901 #define RCC_APB5LPENSR_DCMIPPLPENS_Msk          (0x1UL << RCC_APB5LPENSR_DCMIPPLPENS_Pos)   /*!< 0x00000004 */
30902 #define RCC_APB5LPENSR_DCMIPPLPENS              RCC_APB5LPENSR_DCMIPPLPENS_Msk       /*!< DCMIPP enable */
30903 #define RCC_APB5LPENSR_GFXTIMLPENS_Pos          (4U)
30904 #define RCC_APB5LPENSR_GFXTIMLPENS_Msk          (0x1UL << RCC_APB5LPENSR_GFXTIMLPENS_Pos)   /*!< 0x00000010 */
30905 #define RCC_APB5LPENSR_GFXTIMLPENS              RCC_APB5LPENSR_GFXTIMLPENS_Msk       /*!< GFXTIM enable */
30906 #define RCC_APB5LPENSR_VENCLPENS_Pos            (5U)
30907 #define RCC_APB5LPENSR_VENCLPENS_Msk            (0x1UL << RCC_APB5LPENSR_VENCLPENS_Pos) /*!< 0x00000020 */
30908 #define RCC_APB5LPENSR_VENCLPENS                RCC_APB5LPENSR_VENCLPENS_Msk         /*!< VENC enable */
30909 #define RCC_APB5LPENSR_CSILPENS_Pos             (6U)
30910 #define RCC_APB5LPENSR_CSILPENS_Msk             (0x1UL << RCC_APB5LPENSR_CSILPENS_Pos)/*!< 0x00000040 */
30911 #define RCC_APB5LPENSR_CSILPENS                 RCC_APB5LPENSR_CSILPENS_Msk          /*!< CSI enable */
30912 
30913 /****************  Bit definition for RCC_PRIVCFGSR0 register  ****************/
30914 #define RCC_PRIVCFGSR0_LSIPRIVS_Pos             (0U)
30915 #define RCC_PRIVCFGSR0_LSIPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR0_LSIPRIVS_Pos)/*!< 0x00000001 */
30916 #define RCC_PRIVCFGSR0_LSIPRIVS                 RCC_PRIVCFGSR0_LSIPRIVS_Msk          /*!< Privileged protection of the LSI configuration bits (enable, ready, divider) */
30917 #define RCC_PRIVCFGSR0_LSEPRIVS_Pos             (1U)
30918 #define RCC_PRIVCFGSR0_LSEPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR0_LSEPRIVS_Pos)/*!< 0x00000002 */
30919 #define RCC_PRIVCFGSR0_LSEPRIVS                 RCC_PRIVCFGSR0_LSEPRIVS_Msk          /*!< Privileged protection of LSE configuration bits (enable, ready, divider) */
30920 #define RCC_PRIVCFGSR0_MSIPRIVS_Pos             (2U)
30921 #define RCC_PRIVCFGSR0_MSIPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR0_MSIPRIVS_Pos)/*!< 0x00000004 */
30922 #define RCC_PRIVCFGSR0_MSIPRIVS                 RCC_PRIVCFGSR0_MSIPRIVS_Msk          /*!< Privileged protection of MSI configuration bits (enable, ready, divider) */
30923 #define RCC_PRIVCFGSR0_HSIPRIVS_Pos             (3U)
30924 #define RCC_PRIVCFGSR0_HSIPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR0_HSIPRIVS_Pos)/*!< 0x00000008 */
30925 #define RCC_PRIVCFGSR0_HSIPRIVS                 RCC_PRIVCFGSR0_HSIPRIVS_Msk          /*!< Privileged protection of HSI configuration bits (enable, ready, divider) */
30926 #define RCC_PRIVCFGSR0_HSEPRIVS_Pos             (4U)
30927 #define RCC_PRIVCFGSR0_HSEPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR0_HSEPRIVS_Pos)/*!< 0x00000010 */
30928 #define RCC_PRIVCFGSR0_HSEPRIVS                 RCC_PRIVCFGSR0_HSEPRIVS_Msk          /*!< Privileged protection of HSE configuration bits (enable, ready, divider) */
30929 
30930 /****************  Bit definition for RCC_PUBCFGSR0 register  *****************/
30931 #define RCC_PUBCFGSR0_LSIPUBS_Pos               (0U)
30932 #define RCC_PUBCFGSR0_LSIPUBS_Msk               (0x1UL << RCC_PUBCFGSR0_LSIPUBS_Pos)  /*!< 0x00000001 */
30933 #define RCC_PUBCFGSR0_LSIPUBS                   RCC_PUBCFGSR0_LSIPUBS_Msk            /*!< Public protection of LSI configuration bits (enable, ready, divider) */
30934 #define RCC_PUBCFGSR0_LSEPUBS_Pos               (1U)
30935 #define RCC_PUBCFGSR0_LSEPUBS_Msk               (0x1UL << RCC_PUBCFGSR0_LSEPUBS_Pos)  /*!< 0x00000002 */
30936 #define RCC_PUBCFGSR0_LSEPUBS                   RCC_PUBCFGSR0_LSEPUBS_Msk            /*!< Public protection of LSE configuration bits (enable, ready, divider) */
30937 #define RCC_PUBCFGSR0_MSIPUBS_Pos               (2U)
30938 #define RCC_PUBCFGSR0_MSIPUBS_Msk               (0x1UL << RCC_PUBCFGSR0_MSIPUBS_Pos)  /*!< 0x00000004 */
30939 #define RCC_PUBCFGSR0_MSIPUBS                   RCC_PUBCFGSR0_MSIPUBS_Msk            /*!< Public protection of MSI configuration bits (enable, ready, divider) */
30940 #define RCC_PUBCFGSR0_HSIPUBS_Pos               (3U)
30941 #define RCC_PUBCFGSR0_HSIPUBS_Msk               (0x1UL << RCC_PUBCFGSR0_HSIPUBS_Pos)  /*!< 0x00000008 */
30942 #define RCC_PUBCFGSR0_HSIPUBS                   RCC_PUBCFGSR0_HSIPUBS_Msk            /*!< Public protection of HSI configuration bits (enable, ready, divider) */
30943 #define RCC_PUBCFGSR0_HSEPUBS_Pos               (4U)
30944 #define RCC_PUBCFGSR0_HSEPUBS_Msk               (0x1UL << RCC_PUBCFGSR0_HSEPUBS_Pos)  /*!< 0x00000010 */
30945 #define RCC_PUBCFGSR0_HSEPUBS                   RCC_PUBCFGSR0_HSEPUBS_Msk            /*!< Public protection of he HSE configuration bits (enable, ready, divider) */
30946 
30947 /****************  Bit definition for RCC_PRIVCFGSR1 register  ****************/
30948 #define RCC_PRIVCFGSR1_PLL1PRIVS_Pos            (0U)
30949 #define RCC_PRIVCFGSR1_PLL1PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR1_PLL1PRIVS_Pos) /*!< 0x00000001 */
30950 #define RCC_PRIVCFGSR1_PLL1PRIVS                RCC_PRIVCFGSR1_PLL1PRIVS_Msk         /*!< Privileged protection of PLL1 configuration bits (enable, ready, divider) */
30951 #define RCC_PRIVCFGSR1_PLL2PRIVS_Pos            (1U)
30952 #define RCC_PRIVCFGSR1_PLL2PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR1_PLL2PRIVS_Pos) /*!< 0x00000002 */
30953 #define RCC_PRIVCFGSR1_PLL2PRIVS                RCC_PRIVCFGSR1_PLL2PRIVS_Msk         /*!< Privileged protection of PLL2 configuration bits (enable, ready, divider) */
30954 #define RCC_PRIVCFGSR1_PLL3PRIVS_Pos            (2U)
30955 #define RCC_PRIVCFGSR1_PLL3PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR1_PLL3PRIVS_Pos) /*!< 0x00000004 */
30956 #define RCC_PRIVCFGSR1_PLL3PRIVS                RCC_PRIVCFGSR1_PLL3PRIVS_Msk         /*!< Privileged protection of PLL3 configuration bits (enable, ready, divider) */
30957 #define RCC_PRIVCFGSR1_PLL4PRIVS_Pos            (3U)
30958 #define RCC_PRIVCFGSR1_PLL4PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR1_PLL4PRIVS_Pos) /*!< 0x00000008 */
30959 #define RCC_PRIVCFGSR1_PLL4PRIVS                RCC_PRIVCFGSR1_PLL4PRIVS_Msk         /*!< Privileged protection of PLL4 configuration bits (enable, ready, divider) */
30960 
30961 /****************  Bit definition for RCC_PUBCFGSR1 register  *****************/
30962 #define RCC_PUBCFGSR1_PLL1PUBS_Pos              (0U)
30963 #define RCC_PUBCFGSR1_PLL1PUBS_Msk              (0x1UL << RCC_PUBCFGSR1_PLL1PUBS_Pos) /*!< 0x00000001 */
30964 #define RCC_PUBCFGSR1_PLL1PUBS                  RCC_PUBCFGSR1_PLL1PUBS_Msk           /*!< Public protection of PLL1 configuration bits (enable, ready, divider) */
30965 #define RCC_PUBCFGSR1_PLL2PUBS_Pos              (1U)
30966 #define RCC_PUBCFGSR1_PLL2PUBS_Msk              (0x1UL << RCC_PUBCFGSR1_PLL2PUBS_Pos) /*!< 0x00000002 */
30967 #define RCC_PUBCFGSR1_PLL2PUBS                  RCC_PUBCFGSR1_PLL2PUBS_Msk           /*!< Public protection of PLL2 configuration bits (enable, ready, divider) */
30968 #define RCC_PUBCFGSR1_PLL3PUBS_Pos              (2U)
30969 #define RCC_PUBCFGSR1_PLL3PUBS_Msk              (0x1UL << RCC_PUBCFGSR1_PLL3PUBS_Pos) /*!< 0x00000004 */
30970 #define RCC_PUBCFGSR1_PLL3PUBS                  RCC_PUBCFGSR1_PLL3PUBS_Msk           /*!< Public protection of PLL3 configuration bits (enable, ready, divider) */
30971 #define RCC_PUBCFGSR1_PLL4PUBS_Pos              (3U)
30972 #define RCC_PUBCFGSR1_PLL4PUBS_Msk              (0x1UL << RCC_PUBCFGSR1_PLL4PUBS_Pos) /*!< 0x00000008 */
30973 #define RCC_PUBCFGSR1_PLL4PUBS                  RCC_PUBCFGSR1_PLL4PUBS_Msk           /*!< Public protection of PLL4 configuration bits (enable, ready, divider) */
30974 
30975 /****************  Bit definition for RCC_PRIVCFGSR2 register  ****************/
30976 #define RCC_PRIVCFGSR2_IC1PRIVS_Pos             (0U)
30977 #define RCC_PRIVCFGSR2_IC1PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC1PRIVS_Pos)/*!< 0x00000001 */
30978 #define RCC_PRIVCFGSR2_IC1PRIVS                 RCC_PRIVCFGSR2_IC1PRIVS_Msk          /*!< Privileged protection of IC1 configuration bits (enable, ready, divider) */
30979 #define RCC_PRIVCFGSR2_IC2PRIVS_Pos             (1U)
30980 #define RCC_PRIVCFGSR2_IC2PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC2PRIVS_Pos)/*!< 0x00000002 */
30981 #define RCC_PRIVCFGSR2_IC2PRIVS                 RCC_PRIVCFGSR2_IC2PRIVS_Msk          /*!< Privileged protection of IC2 configuration bits (enable, ready, divider) */
30982 #define RCC_PRIVCFGSR2_IC3PRIVS_Pos             (2U)
30983 #define RCC_PRIVCFGSR2_IC3PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC3PRIVS_Pos)/*!< 0x00000004 */
30984 #define RCC_PRIVCFGSR2_IC3PRIVS                 RCC_PRIVCFGSR2_IC3PRIVS_Msk          /*!< Privileged protection of IC3 configuration bits (enable, ready, divider) */
30985 #define RCC_PRIVCFGSR2_IC4PRIVS_Pos             (3U)
30986 #define RCC_PRIVCFGSR2_IC4PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC4PRIVS_Pos)/*!< 0x00000008 */
30987 #define RCC_PRIVCFGSR2_IC4PRIVS                 RCC_PRIVCFGSR2_IC4PRIVS_Msk          /*!< Privileged protection of IC4 configuration bits (enable, ready, divider) */
30988 #define RCC_PRIVCFGSR2_IC5PRIVS_Pos             (4U)
30989 #define RCC_PRIVCFGSR2_IC5PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC5PRIVS_Pos)/*!< 0x00000010 */
30990 #define RCC_PRIVCFGSR2_IC5PRIVS                 RCC_PRIVCFGSR2_IC5PRIVS_Msk          /*!< Privileged protection of IC5 configuration bits (enable, ready, divider) */
30991 #define RCC_PRIVCFGSR2_IC6PRIVS_Pos             (5U)
30992 #define RCC_PRIVCFGSR2_IC6PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC6PRIVS_Pos)/*!< 0x00000020 */
30993 #define RCC_PRIVCFGSR2_IC6PRIVS                 RCC_PRIVCFGSR2_IC6PRIVS_Msk          /*!< Privileged protection of IC6 configuration bits (enable, ready, divider) */
30994 #define RCC_PRIVCFGSR2_IC7PRIVS_Pos             (6U)
30995 #define RCC_PRIVCFGSR2_IC7PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC7PRIVS_Pos)/*!< 0x00000040 */
30996 #define RCC_PRIVCFGSR2_IC7PRIVS                 RCC_PRIVCFGSR2_IC7PRIVS_Msk          /*!< Privileged protection of IC7 configuration bits (enable, ready, divider) */
30997 #define RCC_PRIVCFGSR2_IC8PRIVS_Pos             (7U)
30998 #define RCC_PRIVCFGSR2_IC8PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC8PRIVS_Pos)/*!< 0x00000080 */
30999 #define RCC_PRIVCFGSR2_IC8PRIVS                 RCC_PRIVCFGSR2_IC8PRIVS_Msk          /*!< Privileged protection of IC8 configuration bits (enable, ready, divider) */
31000 #define RCC_PRIVCFGSR2_IC9PRIVS_Pos             (8U)
31001 #define RCC_PRIVCFGSR2_IC9PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC9PRIVS_Pos)/*!< 0x00000100 */
31002 #define RCC_PRIVCFGSR2_IC9PRIVS                 RCC_PRIVCFGSR2_IC9PRIVS_Msk          /*!< Privileged protection of IC9 configuration bits (enable, ready, divider) */
31003 #define RCC_PRIVCFGSR2_IC10PRIVS_Pos            (9U)
31004 #define RCC_PRIVCFGSR2_IC10PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC10PRIVS_Pos) /*!< 0x00000200 */
31005 #define RCC_PRIVCFGSR2_IC10PRIVS                RCC_PRIVCFGSR2_IC10PRIVS_Msk         /*!< Privileged protection of IC10 configuration bits (enable, ready, divider) */
31006 #define RCC_PRIVCFGSR2_IC11PRIVS_Pos            (10U)
31007 #define RCC_PRIVCFGSR2_IC11PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC11PRIVS_Pos) /*!< 0x00000400 */
31008 #define RCC_PRIVCFGSR2_IC11PRIVS                RCC_PRIVCFGSR2_IC11PRIVS_Msk         /*!< Privileged protection of IC11 configuration bits (enable, ready, divider) */
31009 #define RCC_PRIVCFGSR2_IC12PRIVS_Pos            (11U)
31010 #define RCC_PRIVCFGSR2_IC12PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC12PRIVS_Pos) /*!< 0x00000800 */
31011 #define RCC_PRIVCFGSR2_IC12PRIVS                RCC_PRIVCFGSR2_IC12PRIVS_Msk         /*!< Privileged protection of IC12 configuration bits (enable, ready, divider) */
31012 #define RCC_PRIVCFGSR2_IC13PRIVS_Pos            (12U)
31013 #define RCC_PRIVCFGSR2_IC13PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC13PRIVS_Pos) /*!< 0x00001000 */
31014 #define RCC_PRIVCFGSR2_IC13PRIVS                RCC_PRIVCFGSR2_IC13PRIVS_Msk         /*!< Privileged protection of IC13 configuration bits (enable, ready, divider) */
31015 #define RCC_PRIVCFGSR2_IC14PRIVS_Pos            (13U)
31016 #define RCC_PRIVCFGSR2_IC14PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC14PRIVS_Pos) /*!< 0x00002000 */
31017 #define RCC_PRIVCFGSR2_IC14PRIVS                RCC_PRIVCFGSR2_IC14PRIVS_Msk         /*!< Privileged protection of IC14 configuration bits (enable, ready, divider) */
31018 #define RCC_PRIVCFGSR2_IC15PRIVS_Pos            (14U)
31019 #define RCC_PRIVCFGSR2_IC15PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC15PRIVS_Pos) /*!< 0x00004000 */
31020 #define RCC_PRIVCFGSR2_IC15PRIVS                RCC_PRIVCFGSR2_IC15PRIVS_Msk         /*!< Privileged protection of IC15 configuration bits (enable, ready, divider) */
31021 #define RCC_PRIVCFGSR2_IC16PRIVS_Pos            (15U)
31022 #define RCC_PRIVCFGSR2_IC16PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC16PRIVS_Pos) /*!< 0x00008000 */
31023 #define RCC_PRIVCFGSR2_IC16PRIVS                RCC_PRIVCFGSR2_IC16PRIVS_Msk         /*!< Privileged protection of IC16 configuration bits (enable, ready, divider) */
31024 #define RCC_PRIVCFGSR2_IC17PRIVS_Pos            (16U)
31025 #define RCC_PRIVCFGSR2_IC17PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC17PRIVS_Pos) /*!< 0x00010000 */
31026 #define RCC_PRIVCFGSR2_IC17PRIVS                RCC_PRIVCFGSR2_IC17PRIVS_Msk         /*!< Privileged protection of IC17 configuration bits (enable, ready, divider) */
31027 #define RCC_PRIVCFGSR2_IC18PRIVS_Pos            (17U)
31028 #define RCC_PRIVCFGSR2_IC18PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC18PRIVS_Pos) /*!< 0x00020000 */
31029 #define RCC_PRIVCFGSR2_IC18PRIVS                RCC_PRIVCFGSR2_IC18PRIVS_Msk         /*!< Privileged protection of IC18 configuration bits (enable, ready, divider) */
31030 #define RCC_PRIVCFGSR2_IC19PRIVS_Pos            (18U)
31031 #define RCC_PRIVCFGSR2_IC19PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC19PRIVS_Pos) /*!< 0x00040000 */
31032 #define RCC_PRIVCFGSR2_IC19PRIVS                RCC_PRIVCFGSR2_IC19PRIVS_Msk         /*!< Privileged protection of IC19 configuration bits (enable, ready, divider) */
31033 #define RCC_PRIVCFGSR2_IC20PRIVS_Pos            (19U)
31034 #define RCC_PRIVCFGSR2_IC20PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC20PRIVS_Pos) /*!< 0x00080000 */
31035 #define RCC_PRIVCFGSR2_IC20PRIVS                RCC_PRIVCFGSR2_IC20PRIVS_Msk         /*!< Privileged protection of IC20 configuration bits (enable, ready, divider) */
31036 
31037 /****************  Bit definition for RCC_PUBCFGSR2 register  *****************/
31038 #define RCC_PUBCFGSR2_IC1PUBS_Pos               (0U)
31039 #define RCC_PUBCFGSR2_IC1PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC1PUBS_Pos)  /*!< 0x00000001 */
31040 #define RCC_PUBCFGSR2_IC1PUBS                   RCC_PUBCFGSR2_IC1PUBS_Msk            /*!< Public protection of IC1 configuration bits (enable, ready, divider) */
31041 #define RCC_PUBCFGSR2_IC2PUBS_Pos               (1U)
31042 #define RCC_PUBCFGSR2_IC2PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC2PUBS_Pos)  /*!< 0x00000002 */
31043 #define RCC_PUBCFGSR2_IC2PUBS                   RCC_PUBCFGSR2_IC2PUBS_Msk            /*!< Public protection of IC2 configuration bits (enable, ready, divider) */
31044 #define RCC_PUBCFGSR2_IC3PUBS_Pos               (2U)
31045 #define RCC_PUBCFGSR2_IC3PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC3PUBS_Pos)  /*!< 0x00000004 */
31046 #define RCC_PUBCFGSR2_IC3PUBS                   RCC_PUBCFGSR2_IC3PUBS_Msk            /*!< Public protection of IC3 configuration bits (enable, ready, divider) */
31047 #define RCC_PUBCFGSR2_IC4PUBS_Pos               (3U)
31048 #define RCC_PUBCFGSR2_IC4PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC4PUBS_Pos)  /*!< 0x00000008 */
31049 #define RCC_PUBCFGSR2_IC4PUBS                   RCC_PUBCFGSR2_IC4PUBS_Msk            /*!< Public protection of IC4 configuration bits (enable, ready, divider) */
31050 #define RCC_PUBCFGSR2_IC5PUBS_Pos               (4U)
31051 #define RCC_PUBCFGSR2_IC5PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC5PUBS_Pos)  /*!< 0x00000010 */
31052 #define RCC_PUBCFGSR2_IC5PUBS                   RCC_PUBCFGSR2_IC5PUBS_Msk            /*!< Public protection of IC5 configuration bits (enable, ready, divider) */
31053 #define RCC_PUBCFGSR2_IC6PUBS_Pos               (5U)
31054 #define RCC_PUBCFGSR2_IC6PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC6PUBS_Pos)  /*!< 0x00000020 */
31055 #define RCC_PUBCFGSR2_IC6PUBS                   RCC_PUBCFGSR2_IC6PUBS_Msk            /*!< Public protection of IC6 configuration bits (enable, ready, divider) */
31056 #define RCC_PUBCFGSR2_IC7PUBS_Pos               (6U)
31057 #define RCC_PUBCFGSR2_IC7PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC7PUBS_Pos)  /*!< 0x00000040 */
31058 #define RCC_PUBCFGSR2_IC7PUBS                   RCC_PUBCFGSR2_IC7PUBS_Msk            /*!< Public protection of IC7 configuration bits (enable, ready, divider) */
31059 #define RCC_PUBCFGSR2_IC8PUBS_Pos               (7U)
31060 #define RCC_PUBCFGSR2_IC8PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC8PUBS_Pos)  /*!< 0x00000080 */
31061 #define RCC_PUBCFGSR2_IC8PUBS                   RCC_PUBCFGSR2_IC8PUBS_Msk            /*!< Public protection of IC8 configuration bits (enable, ready, divider) */
31062 #define RCC_PUBCFGSR2_IC9PUBS_Pos               (8U)
31063 #define RCC_PUBCFGSR2_IC9PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC9PUBS_Pos)  /*!< 0x00000100 */
31064 #define RCC_PUBCFGSR2_IC9PUBS                   RCC_PUBCFGSR2_IC9PUBS_Msk            /*!< Public protection of IC9 configuration bits (enable, ready, divider) */
31065 #define RCC_PUBCFGSR2_IC10PUBS_Pos              (9U)
31066 #define RCC_PUBCFGSR2_IC10PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC10PUBS_Pos) /*!< 0x00000200 */
31067 #define RCC_PUBCFGSR2_IC10PUBS                  RCC_PUBCFGSR2_IC10PUBS_Msk           /*!< Public protection of IC10 configuration bits (enable, ready, divider) */
31068 #define RCC_PUBCFGSR2_IC11PUBS_Pos              (10U)
31069 #define RCC_PUBCFGSR2_IC11PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC11PUBS_Pos) /*!< 0x00000400 */
31070 #define RCC_PUBCFGSR2_IC11PUBS                  RCC_PUBCFGSR2_IC11PUBS_Msk           /*!< Public protection of IC11 configuration bits (enable, ready, divider) */
31071 #define RCC_PUBCFGSR2_IC12PUBS_Pos              (11U)
31072 #define RCC_PUBCFGSR2_IC12PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC12PUBS_Pos) /*!< 0x00000800 */
31073 #define RCC_PUBCFGSR2_IC12PUBS                  RCC_PUBCFGSR2_IC12PUBS_Msk           /*!< Public protection of IC12 configuration bits (enable, ready, divider) */
31074 #define RCC_PUBCFGSR2_IC13PUBS_Pos              (12U)
31075 #define RCC_PUBCFGSR2_IC13PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC13PUBS_Pos) /*!< 0x00001000 */
31076 #define RCC_PUBCFGSR2_IC13PUBS                  RCC_PUBCFGSR2_IC13PUBS_Msk           /*!< Public protection of IC13 configuration bits (enable, ready, divider) */
31077 #define RCC_PUBCFGSR2_IC14PUBS_Pos              (13U)
31078 #define RCC_PUBCFGSR2_IC14PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC14PUBS_Pos) /*!< 0x00002000 */
31079 #define RCC_PUBCFGSR2_IC14PUBS                  RCC_PUBCFGSR2_IC14PUBS_Msk           /*!< Public protection of IC14 configuration bits (enable, ready, divider) */
31080 #define RCC_PUBCFGSR2_IC15PUBS_Pos              (14U)
31081 #define RCC_PUBCFGSR2_IC15PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC15PUBS_Pos) /*!< 0x00004000 */
31082 #define RCC_PUBCFGSR2_IC15PUBS                  RCC_PUBCFGSR2_IC15PUBS_Msk           /*!< Public protection of IC15 configuration bits (enable, ready, divider) */
31083 #define RCC_PUBCFGSR2_IC16PUBS_Pos              (15U)
31084 #define RCC_PUBCFGSR2_IC16PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC16PUBS_Pos) /*!< 0x00008000 */
31085 #define RCC_PUBCFGSR2_IC16PUBS                  RCC_PUBCFGSR2_IC16PUBS_Msk           /*!< Public protection of th IC16 configuration bits (enable, ready, divider */
31086 #define RCC_PUBCFGSR2_IC17PUBS_Pos              (16U)
31087 #define RCC_PUBCFGSR2_IC17PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC17PUBS_Pos) /*!< 0x00010000 */
31088 #define RCC_PUBCFGSR2_IC17PUBS                  RCC_PUBCFGSR2_IC17PUBS_Msk           /*!< Public protection of IC17 configuration bits (enable, ready, divider) */
31089 #define RCC_PUBCFGSR2_IC18PUBS_Pos              (17U)
31090 #define RCC_PUBCFGSR2_IC18PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC18PUBS_Pos) /*!< 0x00020000 */
31091 #define RCC_PUBCFGSR2_IC18PUBS                  RCC_PUBCFGSR2_IC18PUBS_Msk           /*!< Public protection of IC18 configuration bits (enable, ready, divider) */
31092 #define RCC_PUBCFGSR2_IC19PUBS_Pos              (18U)
31093 #define RCC_PUBCFGSR2_IC19PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC19PUBS_Pos) /*!< 0x00040000 */
31094 #define RCC_PUBCFGSR2_IC19PUBS                  RCC_PUBCFGSR2_IC19PUBS_Msk           /*!< Public protection of IC19 configuration bits (enable, ready, divider) */
31095 #define RCC_PUBCFGSR2_IC20PUBS_Pos              (19U)
31096 #define RCC_PUBCFGSR2_IC20PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC20PUBS_Pos) /*!< 0x00080000 */
31097 #define RCC_PUBCFGSR2_IC20PUBS                  RCC_PUBCFGSR2_IC20PUBS_Msk           /*!< Public protection of IC20 configuration bits (enable, ready, divider) */
31098 
31099 /****************  Bit definition for RCC_PRIVCFGSR3 register  ****************/
31100 #define RCC_PRIVCFGSR3_MODPRIVS_Pos             (0U)
31101 #define RCC_PRIVCFGSR3_MODPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR3_MODPRIVS_Pos)/*!< 0x00000001 */
31102 #define RCC_PRIVCFGSR3_MODPRIVS                 RCC_PRIVCFGSR3_MODPRIVS_Msk          /*!< Privileged protection of MOD configuration bits (enable, ready, divider) */
31103 #define RCC_PRIVCFGSR3_SYSPRIVS_Pos             (1U)
31104 #define RCC_PRIVCFGSR3_SYSPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR3_SYSPRIVS_Pos)/*!< 0x00000002 */
31105 #define RCC_PRIVCFGSR3_SYSPRIVS                 RCC_PRIVCFGSR3_SYSPRIVS_Msk          /*!< Privileged protection of SYS configuration bits (enable, ready, divider) */
31106 #define RCC_PRIVCFGSR3_BUSPRIVS_Pos             (2U)
31107 #define RCC_PRIVCFGSR3_BUSPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR3_BUSPRIVS_Pos)/*!< 0x00000004 */
31108 #define RCC_PRIVCFGSR3_BUSPRIVS                 RCC_PRIVCFGSR3_BUSPRIVS_Msk          /*!< Privileged protection of BUS configuration bits (enable, ready, divider) */
31109 #define RCC_PRIVCFGSR3_PERPRIVS_Pos             (3U)
31110 #define RCC_PRIVCFGSR3_PERPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR3_PERPRIVS_Pos)/*!< 0x00000008 */
31111 #define RCC_PRIVCFGSR3_PERPRIVS                 RCC_PRIVCFGSR3_PERPRIVS_Msk          /*!< Privileged protection of PER configuration bits (enable, ready, divider) */
31112 #define RCC_PRIVCFGSR3_INTPRIVS_Pos             (4U)
31113 #define RCC_PRIVCFGSR3_INTPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR3_INTPRIVS_Pos)/*!< 0x00000010 */
31114 #define RCC_PRIVCFGSR3_INTPRIVS                 RCC_PRIVCFGSR3_INTPRIVS_Msk          /*!< Privileged protection of INT configuration bits (enable, ready, divider) */
31115 #define RCC_PRIVCFGSR3_RSTPRIVS_Pos             (5U)
31116 #define RCC_PRIVCFGSR3_RSTPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR3_RSTPRIVS_Pos)/*!< 0x00000020 */
31117 #define RCC_PRIVCFGSR3_RSTPRIVS                 RCC_PRIVCFGSR3_RSTPRIVS_Msk          /*!< Privileged protection of RST configuration bits (enable, ready, divider) */
31118 
31119 /****************  Bit definition for RCC_PUBCFGSR3 register  *****************/
31120 #define RCC_PUBCFGSR3_MODPUBS_Pos               (0U)
31121 #define RCC_PUBCFGSR3_MODPUBS_Msk               (0x1UL << RCC_PUBCFGSR3_MODPUBS_Pos)  /*!< 0x00000001 */
31122 #define RCC_PUBCFGSR3_MODPUBS                   RCC_PUBCFGSR3_MODPUBS_Msk            /*!< Public protection of MOD configuration bits (enable, ready, divider) */
31123 #define RCC_PUBCFGSR3_SYSPUBS_Pos               (1U)
31124 #define RCC_PUBCFGSR3_SYSPUBS_Msk               (0x1UL << RCC_PUBCFGSR3_SYSPUBS_Pos)  /*!< 0x00000002 */
31125 #define RCC_PUBCFGSR3_SYSPUBS                   RCC_PUBCFGSR3_SYSPUBS_Msk            /*!< Public protection of SYS configuration bits (enable, ready, divider) */
31126 #define RCC_PUBCFGSR3_BUSPUBS_Pos               (2U)
31127 #define RCC_PUBCFGSR3_BUSPUBS_Msk               (0x1UL << RCC_PUBCFGSR3_BUSPUBS_Pos)  /*!< 0x00000004 */
31128 #define RCC_PUBCFGSR3_BUSPUBS                   RCC_PUBCFGSR3_BUSPUBS_Msk            /*!< Public protection of BUS configuration bits (enable, ready, divider) */
31129 #define RCC_PUBCFGSR3_PERPUBS_Pos               (3U)
31130 #define RCC_PUBCFGSR3_PERPUBS_Msk               (0x1UL << RCC_PUBCFGSR3_PERPUBS_Pos)  /*!< 0x00000008 */
31131 #define RCC_PUBCFGSR3_PERPUBS                   RCC_PUBCFGSR3_PERPUBS_Msk            /*!< Public protection of PER configuration bits (enable, ready, divider) */
31132 #define RCC_PUBCFGSR3_INTPUBS_Pos               (4U)
31133 #define RCC_PUBCFGSR3_INTPUBS_Msk               (0x1UL << RCC_PUBCFGSR3_INTPUBS_Pos)  /*!< 0x00000010 */
31134 #define RCC_PUBCFGSR3_INTPUBS                   RCC_PUBCFGSR3_INTPUBS_Msk            /*!< Public protection of INT configuration bits (enable, ready, divider) */
31135 #define RCC_PUBCFGSR3_RSTPUBS_Pos               (5U)
31136 #define RCC_PUBCFGSR3_RSTPUBS_Msk               (0x1UL << RCC_PUBCFGSR3_RSTPUBS_Pos)  /*!< 0x00000020 */
31137 #define RCC_PUBCFGSR3_RSTPUBS                   RCC_PUBCFGSR3_RSTPUBS_Msk            /*!< Public protection of RST configuration bits (enable, ready, divider) */
31138 
31139 /****************  Bit definition for RCC_PRIVCFGSR4 register  ****************/
31140 #define RCC_PRIVCFGSR4_ACLKNPRIVS_Pos           (0U)
31141 #define RCC_PRIVCFGSR4_ACLKNPRIVS_Msk           (0x1UL << RCC_PRIVCFGSR4_ACLKNPRIVS_Pos)  /*!< 0x00000001 */
31142 #define RCC_PRIVCFGSR4_ACLKNPRIVS               RCC_PRIVCFGSR4_ACLKNPRIVS_Msk        /*!< Privileged protection of ACLKN configuration bits (enable, ready, divider) */
31143 #define RCC_PRIVCFGSR4_ACLKNCPRIVS_Pos          (1U)
31144 #define RCC_PRIVCFGSR4_ACLKNCPRIVS_Msk          (0x1UL << RCC_PRIVCFGSR4_ACLKNCPRIVS_Pos)   /*!< 0x00000002 */
31145 #define RCC_PRIVCFGSR4_ACLKNCPRIVS              RCC_PRIVCFGSR4_ACLKNCPRIVS_Msk       /*!< Privileged protection of th ACLKNC configuration bits (enable, ready, divider) */
31146 #define RCC_PRIVCFGSR4_AHBMPRIVS_Pos            (2U)
31147 #define RCC_PRIVCFGSR4_AHBMPRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_AHBMPRIVS_Pos) /*!< 0x00000004 */
31148 #define RCC_PRIVCFGSR4_AHBMPRIVS                RCC_PRIVCFGSR4_AHBMPRIVS_Msk         /*!< Privileged protection of AHBM configuration bits (enable, ready, divider) */
31149 #define RCC_PRIVCFGSR4_AHB1PRIVS_Pos            (3U)
31150 #define RCC_PRIVCFGSR4_AHB1PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_AHB1PRIVS_Pos) /*!< 0x00000008 */
31151 #define RCC_PRIVCFGSR4_AHB1PRIVS                RCC_PRIVCFGSR4_AHB1PRIVS_Msk         /*!< Privileged protection of AHB1 configuration bits (enable, ready, divider) */
31152 #define RCC_PRIVCFGSR4_AHB2PRIVS_Pos            (4U)
31153 #define RCC_PRIVCFGSR4_AHB2PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_AHB2PRIVS_Pos) /*!< 0x00000010 */
31154 #define RCC_PRIVCFGSR4_AHB2PRIVS                RCC_PRIVCFGSR4_AHB2PRIVS_Msk         /*!< Privileged protection of AHB2 configuration bits (enable, ready, divider) */
31155 #define RCC_PRIVCFGSR4_AHB3PRIVS_Pos            (5U)
31156 #define RCC_PRIVCFGSR4_AHB3PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_AHB3PRIVS_Pos) /*!< 0x00000020 */
31157 #define RCC_PRIVCFGSR4_AHB3PRIVS                RCC_PRIVCFGSR4_AHB3PRIVS_Msk         /*!< Privileged protection of AHB3 configuration bits (enable, ready, divider) */
31158 #define RCC_PRIVCFGSR4_AHB4PRIVS_Pos            (6U)
31159 #define RCC_PRIVCFGSR4_AHB4PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_AHB4PRIVS_Pos) /*!< 0x00000040 */
31160 #define RCC_PRIVCFGSR4_AHB4PRIVS                RCC_PRIVCFGSR4_AHB4PRIVS_Msk         /*!< Privileged protection of AHB4 configuration bits (enable, ready, divider) */
31161 #define RCC_PRIVCFGSR4_AHB5PRIVS_Pos            (7U)
31162 #define RCC_PRIVCFGSR4_AHB5PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_AHB5PRIVS_Pos) /*!< 0x00000080 */
31163 #define RCC_PRIVCFGSR4_AHB5PRIVS                RCC_PRIVCFGSR4_AHB5PRIVS_Msk         /*!< Privileged protection of AHB5 configuration bits (enable, ready, divider) */
31164 #define RCC_PRIVCFGSR4_APB1PRIVS_Pos            (8U)
31165 #define RCC_PRIVCFGSR4_APB1PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_APB1PRIVS_Pos) /*!< 0x00000100 */
31166 #define RCC_PRIVCFGSR4_APB1PRIVS                RCC_PRIVCFGSR4_APB1PRIVS_Msk         /*!< Privileged protection of APB1 configuration bits (enable, ready, divider) */
31167 #define RCC_PRIVCFGSR4_APB2PRIVS_Pos            (9U)
31168 #define RCC_PRIVCFGSR4_APB2PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_APB2PRIVS_Pos) /*!< 0x00000200 */
31169 #define RCC_PRIVCFGSR4_APB2PRIVS                RCC_PRIVCFGSR4_APB2PRIVS_Msk         /*!< Privileged protection of APB2 configuration bits (enable, ready, divider) */
31170 #define RCC_PRIVCFGSR4_APB3PRIVS_Pos            (10U)
31171 #define RCC_PRIVCFGSR4_APB3PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_APB3PRIVS_Pos) /*!< 0x00000400 */
31172 #define RCC_PRIVCFGSR4_APB3PRIVS                RCC_PRIVCFGSR4_APB3PRIVS_Msk         /*!< Privileged protection of APB3 configuration bits (enable, ready, divider) */
31173 #define RCC_PRIVCFGSR4_APB4PRIVS_Pos            (11U)
31174 #define RCC_PRIVCFGSR4_APB4PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_APB4PRIVS_Pos) /*!< 0x00000800 */
31175 #define RCC_PRIVCFGSR4_APB4PRIVS                RCC_PRIVCFGSR4_APB4PRIVS_Msk         /*!< Privileged protection of APB4 configuration bits (enable, ready, divider) */
31176 #define RCC_PRIVCFGSR4_APB5PRIVS_Pos            (12U)
31177 #define RCC_PRIVCFGSR4_APB5PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_APB5PRIVS_Pos) /*!< 0x00001000 */
31178 #define RCC_PRIVCFGSR4_APB5PRIVS                RCC_PRIVCFGSR4_APB5PRIVS_Msk         /*!< Privileged protection of APB5 configuration bits (enable, ready, divider) */
31179 #define RCC_PRIVCFGSR4_NOCPRIVS_Pos             (13U)
31180 #define RCC_PRIVCFGSR4_NOCPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR4_NOCPRIVS_Pos)/*!< 0x00002000 */
31181 #define RCC_PRIVCFGSR4_NOCPRIVS                 RCC_PRIVCFGSR4_NOCPRIVS_Msk          /*!< Privileged protection of NOC configuration bits (enable, ready, divider) */
31182 
31183 /****************  Bit definition for RCC_PUBCFGSR4 register  *****************/
31184 #define RCC_PUBCFGSR4_ACLKNPUBS_Pos             (0U)
31185 #define RCC_PUBCFGSR4_ACLKNPUBS_Msk             (0x1UL << RCC_PUBCFGSR4_ACLKNPUBS_Pos)/*!< 0x00000001 */
31186 #define RCC_PUBCFGSR4_ACLKNPUBS                 RCC_PUBCFGSR4_ACLKNPUBS_Msk          /*!< Public protection of ACLKN configuration bits (enable, ready, divider) */
31187 #define RCC_PUBCFGSR4_ACLKNCPUBS_Pos            (1U)
31188 #define RCC_PUBCFGSR4_ACLKNCPUBS_Msk            (0x1UL << RCC_PUBCFGSR4_ACLKNCPUBS_Pos) /*!< 0x00000002 */
31189 #define RCC_PUBCFGSR4_ACLKNCPUBS                RCC_PUBCFGSR4_ACLKNCPUBS_Msk         /*!< Public protection of ACLKNC configuration bits (enable, ready, divider) */
31190 #define RCC_PUBCFGSR4_AHBMPUBS_Pos              (2U)
31191 #define RCC_PUBCFGSR4_AHBMPUBS_Msk              (0x1UL << RCC_PUBCFGSR4_AHBMPUBS_Pos) /*!< 0x00000004 */
31192 #define RCC_PUBCFGSR4_AHBMPUBS                  RCC_PUBCFGSR4_AHBMPUBS_Msk           /*!< Public protection of AHBM configuration bits (enable, ready, divider) */
31193 #define RCC_PUBCFGSR4_AHB1PUBS_Pos              (3U)
31194 #define RCC_PUBCFGSR4_AHB1PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_AHB1PUBS_Pos) /*!< 0x00000008 */
31195 #define RCC_PUBCFGSR4_AHB1PUBS                  RCC_PUBCFGSR4_AHB1PUBS_Msk           /*!< Public protection of AHB1 configuration bits (enable, ready, divider) */
31196 #define RCC_PUBCFGSR4_AHB2PUBS_Pos              (4U)
31197 #define RCC_PUBCFGSR4_AHB2PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_AHB2PUBS_Pos) /*!< 0x00000010 */
31198 #define RCC_PUBCFGSR4_AHB2PUBS                  RCC_PUBCFGSR4_AHB2PUBS_Msk           /*!< Public protection of AHB2 configuration bits (enable, ready, divider) */
31199 #define RCC_PUBCFGSR4_AHB3PUBS_Pos              (5U)
31200 #define RCC_PUBCFGSR4_AHB3PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_AHB3PUBS_Pos) /*!< 0x00000020 */
31201 #define RCC_PUBCFGSR4_AHB3PUBS                  RCC_PUBCFGSR4_AHB3PUBS_Msk           /*!< Public protection of AHB3 configuration bits (enable, ready, divider) */
31202 #define RCC_PUBCFGSR4_AHB4PUBS_Pos              (6U)
31203 #define RCC_PUBCFGSR4_AHB4PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_AHB4PUBS_Pos) /*!< 0x00000040 */
31204 #define RCC_PUBCFGSR4_AHB4PUBS                  RCC_PUBCFGSR4_AHB4PUBS_Msk           /*!< Public protection of AHB4 configuration bits (enable, ready, divider) */
31205 #define RCC_PUBCFGSR4_AHB5PUBS_Pos              (7U)
31206 #define RCC_PUBCFGSR4_AHB5PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_AHB5PUBS_Pos) /*!< 0x00000080 */
31207 #define RCC_PUBCFGSR4_AHB5PUBS                  RCC_PUBCFGSR4_AHB5PUBS_Msk           /*!< Public protection of AHB5 configuration bits (enable, ready, divider) */
31208 #define RCC_PUBCFGSR4_APB1PUBS_Pos              (8U)
31209 #define RCC_PUBCFGSR4_APB1PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_APB1PUBS_Pos) /*!< 0x00000100 */
31210 #define RCC_PUBCFGSR4_APB1PUBS                  RCC_PUBCFGSR4_APB1PUBS_Msk           /*!< Public protection of APB1 configuration bits (enable, ready, divider) */
31211 #define RCC_PUBCFGSR4_APB2PUBS_Pos              (9U)
31212 #define RCC_PUBCFGSR4_APB2PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_APB2PUBS_Pos) /*!< 0x00000200 */
31213 #define RCC_PUBCFGSR4_APB2PUBS                  RCC_PUBCFGSR4_APB2PUBS_Msk           /*!< Public protection of APB2 configuration bits (enable, ready, divider) */
31214 #define RCC_PUBCFGSR4_APB3PUBS_Pos              (10U)
31215 #define RCC_PUBCFGSR4_APB3PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_APB3PUBS_Pos) /*!< 0x00000400 */
31216 #define RCC_PUBCFGSR4_APB3PUBS                  RCC_PUBCFGSR4_APB3PUBS_Msk           /*!< Public protection of APB3 configuration bits (enable, ready, divider) */
31217 #define RCC_PUBCFGSR4_APB4PUBS_Pos              (11U)
31218 #define RCC_PUBCFGSR4_APB4PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_APB4PUBS_Pos) /*!< 0x00000800 */
31219 #define RCC_PUBCFGSR4_APB4PUBS                  RCC_PUBCFGSR4_APB4PUBS_Msk           /*!< Public protection of APB4 configuration bits (enable, ready, divider) */
31220 #define RCC_PUBCFGSR4_APB5PUBS_Pos              (12U)
31221 #define RCC_PUBCFGSR4_APB5PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_APB5PUBS_Pos) /*!< 0x00001000 */
31222 #define RCC_PUBCFGSR4_APB5PUBS                  RCC_PUBCFGSR4_APB5PUBS_Msk           /*!< Public protection of APB5 configuration bits (enable, ready, divider) */
31223 #define RCC_PUBCFGSR4_NOCPUBS_Pos               (13U)
31224 #define RCC_PUBCFGSR4_NOCPUBS_Msk               (0x1UL << RCC_PUBCFGSR4_NOCPUBS_Pos)  /*!< 0x00002000 */
31225 #define RCC_PUBCFGSR4_NOCPUBS                   RCC_PUBCFGSR4_NOCPUBS_Msk            /*!< Public protection of NOC configuration bits (enable, ready, divider) */
31226 
31227 /****************  Bit definition for RCC_PUBCFGSR5 register  *****************/
31228 #define RCC_PUBCFGSR5_AXISRAM3PUBS_Pos          (0U)
31229 #define RCC_PUBCFGSR5_AXISRAM3PUBS_Msk          (0x1UL << RCC_PUBCFGSR5_AXISRAM3PUBS_Pos)   /*!< 0x00000001 */
31230 #define RCC_PUBCFGSR5_AXISRAM3PUBS              RCC_PUBCFGSR5_AXISRAM3PUBS_Msk       /*!< Public protection of AXISRAM3 configuration bits (enable, ready, divider) */
31231 #define RCC_PUBCFGSR5_AXISRAM4PUBS_Pos          (1U)
31232 #define RCC_PUBCFGSR5_AXISRAM4PUBS_Msk          (0x1UL << RCC_PUBCFGSR5_AXISRAM4PUBS_Pos)   /*!< 0x00000002 */
31233 #define RCC_PUBCFGSR5_AXISRAM4PUBS              RCC_PUBCFGSR5_AXISRAM4PUBS_Msk       /*!< Public protection of AXISRAM4 configuration bits (enable, ready, divider) */
31234 #define RCC_PUBCFGSR5_AXISRAM5PUBS_Pos          (2U)
31235 #define RCC_PUBCFGSR5_AXISRAM5PUBS_Msk          (0x1UL << RCC_PUBCFGSR5_AXISRAM5PUBS_Pos)   /*!< 0x00000004 */
31236 #define RCC_PUBCFGSR5_AXISRAM5PUBS              RCC_PUBCFGSR5_AXISRAM5PUBS_Msk       /*!< Public protection of AXISRAM5 configuration bits (enable, ready, divider) */
31237 #define RCC_PUBCFGSR5_AXISRAM6PUBS_Pos          (3U)
31238 #define RCC_PUBCFGSR5_AXISRAM6PUBS_Msk          (0x1UL << RCC_PUBCFGSR5_AXISRAM6PUBS_Pos)   /*!< 0x00000008 */
31239 #define RCC_PUBCFGSR5_AXISRAM6PUBS              RCC_PUBCFGSR5_AXISRAM6PUBS_Msk       /*!< Public protection of AXISRAM6 configuration bits (enable, ready, divider) */
31240 #define RCC_PUBCFGSR5_AHBSRAM1PUBS_Pos          (4U)
31241 #define RCC_PUBCFGSR5_AHBSRAM1PUBS_Msk          (0x1UL << RCC_PUBCFGSR5_AHBSRAM1PUBS_Pos)   /*!< 0x00000010 */
31242 #define RCC_PUBCFGSR5_AHBSRAM1PUBS              RCC_PUBCFGSR5_AHBSRAM1PUBS_Msk       /*!< Public protection of AHBSRAM1 configuration bits (enable, ready, divider) */
31243 #define RCC_PUBCFGSR5_AHBSRAM2PUBS_Pos          (5U)
31244 #define RCC_PUBCFGSR5_AHBSRAM2PUBS_Msk          (0x1UL << RCC_PUBCFGSR5_AHBSRAM2PUBS_Pos)   /*!< 0x00000020 */
31245 #define RCC_PUBCFGSR5_AHBSRAM2PUBS              RCC_PUBCFGSR5_AHBSRAM2PUBS_Msk       /*!< Public protection of AHBSRAM2 configuration bits (enable, ready, divider) */
31246 #define RCC_PUBCFGSR5_BKPSRAMPUBS_Pos           (6U)
31247 #define RCC_PUBCFGSR5_BKPSRAMPUBS_Msk           (0x1UL << RCC_PUBCFGSR5_BKPSRAMPUBS_Pos)  /*!< 0x00000040 */
31248 #define RCC_PUBCFGSR5_BKPSRAMPUBS               RCC_PUBCFGSR5_BKPSRAMPUBS_Msk        /*!< Public protection of BKPSRAM configuration bits (enable, ready, divider) */
31249 #define RCC_PUBCFGSR5_AXISRAM1PUBS_Pos          (7U)
31250 #define RCC_PUBCFGSR5_AXISRAM1PUBS_Msk          (0x1UL << RCC_PUBCFGSR5_AXISRAM1PUBS_Pos)   /*!< 0x00000080 */
31251 #define RCC_PUBCFGSR5_AXISRAM1PUBS              RCC_PUBCFGSR5_AXISRAM1PUBS_Msk       /*!< Public protection of AXISRAM1 configuration bits (enable, ready, divider) */
31252 #define RCC_PUBCFGSR5_AXISRAM2PUBS_Pos          (8U)
31253 #define RCC_PUBCFGSR5_AXISRAM2PUBS_Msk          (0x1UL << RCC_PUBCFGSR5_AXISRAM2PUBS_Pos)   /*!< 0x00000100 */
31254 #define RCC_PUBCFGSR5_AXISRAM2PUBS              RCC_PUBCFGSR5_AXISRAM2PUBS_Msk       /*!< Public protection of AXISRAM2 configuration bits (enable, ready, divider) */
31255 #define RCC_PUBCFGSR5_FLEXRAMPUBS_Pos           (9U)
31256 #define RCC_PUBCFGSR5_FLEXRAMPUBS_Msk           (0x1UL << RCC_PUBCFGSR5_FLEXRAMPUBS_Pos)  /*!< 0x00000200 */
31257 #define RCC_PUBCFGSR5_FLEXRAMPUBS               RCC_PUBCFGSR5_FLEXRAMPUBS_Msk        /*!< Public protection of FLEXRAM configuration bits (enable, ready, divider) */
31258 #define RCC_PUBCFGSR5_CACHEAXIRAMPUBS_Pos       (10U)
31259 #define RCC_PUBCFGSR5_CACHEAXIRAMPUBS_Msk       (0x1UL << RCC_PUBCFGSR5_CACHEAXIRAMPUBS_Pos)      /*!< 0x00000400 */
31260 #define RCC_PUBCFGSR5_CACHEAXIRAMPUBS           RCC_PUBCFGSR5_CACHEAXIRAMPUBS_Msk    /*!< Public protection of CACHEAXIRAM configuration bits (enable, ready, divider) */
31261 #define RCC_PUBCFGSR5_VENCRAMPUBS_Pos           (11U)
31262 #define RCC_PUBCFGSR5_VENCRAMPUBS_Msk           (0x1UL << RCC_PUBCFGSR5_VENCRAMPUBS_Pos)  /*!< 0x00000800 */
31263 #define RCC_PUBCFGSR5_VENCRAMPUBS               RCC_PUBCFGSR5_VENCRAMPUBS_Msk        /*!< Public protection of VENCRAM configuration bits (enable, ready, divider) */
31264 
31265 /*******************  Bit definition for RCC_CCR register  ********************/
31266 #define RCC_CCR_LSIONC_Pos                      (0U)
31267 #define RCC_CCR_LSIONC_Msk                      (0x1UL << RCC_CCR_LSIONC_Pos)         /*!< 0x00000001 */
31268 #define RCC_CCR_LSIONC                          RCC_CCR_LSIONC_Msk                   /*!< LSI oscillator enable */
31269 #define RCC_CCR_LSEONC_Pos                      (1U)
31270 #define RCC_CCR_LSEONC_Msk                      (0x1UL << RCC_CCR_LSEONC_Pos)         /*!< 0x00000002 */
31271 #define RCC_CCR_LSEONC                          RCC_CCR_LSEONC_Msk                   /*!< LSE oscillator enable */
31272 #define RCC_CCR_MSIONC_Pos                      (2U)
31273 #define RCC_CCR_MSIONC_Msk                      (0x1UL << RCC_CCR_MSIONC_Pos)         /*!< 0x00000004 */
31274 #define RCC_CCR_MSIONC                          RCC_CCR_MSIONC_Msk                   /*!< MSI oscillator enable */
31275 #define RCC_CCR_HSIONC_Pos                      (3U)
31276 #define RCC_CCR_HSIONC_Msk                      (0x1UL << RCC_CCR_HSIONC_Pos)         /*!< 0x00000008 */
31277 #define RCC_CCR_HSIONC                          RCC_CCR_HSIONC_Msk                   /*!< HSI oscillator enable */
31278 #define RCC_CCR_HSEONC_Pos                      (4U)
31279 #define RCC_CCR_HSEONC_Msk                      (0x1UL << RCC_CCR_HSEONC_Pos)         /*!< 0x00000010 */
31280 #define RCC_CCR_HSEONC                          RCC_CCR_HSEONC_Msk                   /*!< HSE oscillator enable */
31281 #define RCC_CCR_PLL1ONC_Pos                     (8U)
31282 #define RCC_CCR_PLL1ONC_Msk                     (0x1UL << RCC_CCR_PLL1ONC_Pos)        /*!< 0x00000100 */
31283 #define RCC_CCR_PLL1ONC                         RCC_CCR_PLL1ONC_Msk                  /*!< PLL1 oscillator enable */
31284 #define RCC_CCR_PLL2ONC_Pos                     (9U)
31285 #define RCC_CCR_PLL2ONC_Msk                     (0x1UL << RCC_CCR_PLL2ONC_Pos)        /*!< 0x00000200 */
31286 #define RCC_CCR_PLL2ONC                         RCC_CCR_PLL2ONC_Msk                  /*!< PLL2 oscillator enable */
31287 #define RCC_CCR_PLL3ONC_Pos                     (10U)
31288 #define RCC_CCR_PLL3ONC_Msk                     (0x1UL << RCC_CCR_PLL3ONC_Pos)        /*!< 0x00000400 */
31289 #define RCC_CCR_PLL3ONC                         RCC_CCR_PLL3ONC_Msk                  /*!< PLL3 oscillator enable */
31290 #define RCC_CCR_PLL4ONC_Pos                     (11U)
31291 #define RCC_CCR_PLL4ONC_Msk                     (0x1UL << RCC_CCR_PLL4ONC_Pos)        /*!< 0x00000800 */
31292 #define RCC_CCR_PLL4ONC                         RCC_CCR_PLL4ONC_Msk                  /*!< PLL4 oscillator enable */
31293 
31294 /*****************  Bit definition for RCC_STOPCCR register  ******************/
31295 #define RCC_STOPCCR_MSISTOPENC_Pos              (0U)
31296 #define RCC_STOPCCR_MSISTOPENC_Msk              (0x1UL << RCC_STOPCCR_MSISTOPENC_Pos) /*!< 0x00000001 */
31297 #define RCC_STOPCCR_MSISTOPENC                  RCC_STOPCCR_MSISTOPENC_Msk           /*!< MSI oscillator enable */
31298 #define RCC_STOPCCR_HSISTOPENC_Pos              (1U)
31299 #define RCC_STOPCCR_HSISTOPENC_Msk              (0x1UL << RCC_STOPCCR_HSISTOPENC_Pos) /*!< 0x00000002 */
31300 #define RCC_STOPCCR_HSISTOPENC                  RCC_STOPCCR_HSISTOPENC_Msk           /*!< HSI oscillator enable */
31301 
31302 /****************  Bit definition for RCC_MISCRSTCR register  *****************/
31303 #define RCC_MISCRSTCR_DBGRSTC_Pos               (0U)
31304 #define RCC_MISCRSTCR_DBGRSTC_Msk               (0x1UL << RCC_MISCRSTCR_DBGRSTC_Pos)  /*!< 0x00000001 */
31305 #define RCC_MISCRSTCR_DBGRSTC                   RCC_MISCRSTCR_DBGRSTC_Msk            /*!< DBG reset */
31306 #define RCC_MISCRSTCR_XSPIPHY1RSTC_Pos          (4U)
31307 #define RCC_MISCRSTCR_XSPIPHY1RSTC_Msk          (0x1UL << RCC_MISCRSTCR_XSPIPHY1RSTC_Pos)   /*!< 0x00000010 */
31308 #define RCC_MISCRSTCR_XSPIPHY1RSTC              RCC_MISCRSTCR_XSPIPHY1RSTC_Msk       /*!< XSPIPHY1 reset */
31309 #define RCC_MISCRSTCR_XSPIPHY2RSTC_Pos          (5U)
31310 #define RCC_MISCRSTCR_XSPIPHY2RSTC_Msk          (0x1UL << RCC_MISCRSTCR_XSPIPHY2RSTC_Pos)   /*!< 0x00000020 */
31311 #define RCC_MISCRSTCR_XSPIPHY2RSTC              RCC_MISCRSTCR_XSPIPHY2RSTC_Msk       /*!< XSPIPHY2 reset */
31312 #define RCC_MISCRSTCR_SDMMC1DLLRSTC_Pos         (7U)
31313 #define RCC_MISCRSTCR_SDMMC1DLLRSTC_Msk         (0x1UL << RCC_MISCRSTCR_SDMMC1DLLRSTC_Pos)    /*!< 0x00000080 */
31314 #define RCC_MISCRSTCR_SDMMC1DLLRSTC             RCC_MISCRSTCR_SDMMC1DLLRSTC_Msk      /*!< SDMMC1DLL reset */
31315 #define RCC_MISCRSTCR_SDMMC2DLLRSTC_Pos         (8U)
31316 #define RCC_MISCRSTCR_SDMMC2DLLRSTC_Msk         (0x1UL << RCC_MISCRSTCR_SDMMC2DLLRSTC_Pos)    /*!< 0x00000100 */
31317 #define RCC_MISCRSTCR_SDMMC2DLLRSTC             RCC_MISCRSTCR_SDMMC2DLLRSTC_Msk      /*!< SDMMC2DLL reset */
31318 
31319 /*****************  Bit definition for RCC_MEMRSTCR register  *****************/
31320 #define RCC_MEMRSTCR_AXISRAM3RSTC_Pos           (0U)
31321 #define RCC_MEMRSTCR_AXISRAM3RSTC_Msk           (0x1UL << RCC_MEMRSTCR_AXISRAM3RSTC_Pos)  /*!< 0x00000001 */
31322 #define RCC_MEMRSTCR_AXISRAM3RSTC               RCC_MEMRSTCR_AXISRAM3RSTC_Msk        /*!< AXISRAM3 reset */
31323 #define RCC_MEMRSTCR_AXISRAM4RSTC_Pos           (1U)
31324 #define RCC_MEMRSTCR_AXISRAM4RSTC_Msk           (0x1UL << RCC_MEMRSTCR_AXISRAM4RSTC_Pos)  /*!< 0x00000002 */
31325 #define RCC_MEMRSTCR_AXISRAM4RSTC               RCC_MEMRSTCR_AXISRAM4RSTC_Msk        /*!< AXISRAM4 reset */
31326 #define RCC_MEMRSTCR_AXISRAM5RSTC_Pos           (2U)
31327 #define RCC_MEMRSTCR_AXISRAM5RSTC_Msk           (0x1UL << RCC_MEMRSTCR_AXISRAM5RSTC_Pos)  /*!< 0x00000004 */
31328 #define RCC_MEMRSTCR_AXISRAM5RSTC               RCC_MEMRSTCR_AXISRAM5RSTC_Msk        /*!< AXISRAM5 reset */
31329 #define RCC_MEMRSTCR_AXISRAM6RSTC_Pos           (3U)
31330 #define RCC_MEMRSTCR_AXISRAM6RSTC_Msk           (0x1UL << RCC_MEMRSTCR_AXISRAM6RSTC_Pos)  /*!< 0x00000008 */
31331 #define RCC_MEMRSTCR_AXISRAM6RSTC               RCC_MEMRSTCR_AXISRAM6RSTC_Msk        /*!< AXISRAM6 reset */
31332 #define RCC_MEMRSTCR_AHBSRAM1RSTC_Pos           (4U)
31333 #define RCC_MEMRSTCR_AHBSRAM1RSTC_Msk           (0x1UL << RCC_MEMRSTCR_AHBSRAM1RSTC_Pos)  /*!< 0x00000010 */
31334 #define RCC_MEMRSTCR_AHBSRAM1RSTC               RCC_MEMRSTCR_AHBSRAM1RSTC_Msk        /*!< AHBSRAM1 reset */
31335 #define RCC_MEMRSTCR_AHBSRAM2RSTC_Pos           (5U)
31336 #define RCC_MEMRSTCR_AHBSRAM2RSTC_Msk           (0x1UL << RCC_MEMRSTCR_AHBSRAM2RSTC_Pos)  /*!< 0x00000020 */
31337 #define RCC_MEMRSTCR_AHBSRAM2RSTC               RCC_MEMRSTCR_AHBSRAM2RSTC_Msk        /*!< AHBSRAM2 reset */
31338 #define RCC_MEMRSTCR_AXISRAM1RSTC_Pos           (7U)
31339 #define RCC_MEMRSTCR_AXISRAM1RSTC_Msk           (0x1UL << RCC_MEMRSTCR_AXISRAM1RSTC_Pos)  /*!< 0x00000080 */
31340 #define RCC_MEMRSTCR_AXISRAM1RSTC               RCC_MEMRSTCR_AXISRAM1RSTC_Msk        /*!< AXISRAM1 reset */
31341 #define RCC_MEMRSTCR_AXISRAM2RSTC_Pos           (8U)
31342 #define RCC_MEMRSTCR_AXISRAM2RSTC_Msk           (0x1UL << RCC_MEMRSTCR_AXISRAM2RSTC_Pos)  /*!< 0x00000100 */
31343 #define RCC_MEMRSTCR_AXISRAM2RSTC               RCC_MEMRSTCR_AXISRAM2RSTC_Msk        /*!< AXISRAM2 reset */
31344 #define RCC_MEMRSTCR_FLEXRAMRSTC_Pos            (9U)
31345 #define RCC_MEMRSTCR_FLEXRAMRSTC_Msk            (0x1UL << RCC_MEMRSTCR_FLEXRAMRSTC_Pos) /*!< 0x00000200 */
31346 #define RCC_MEMRSTCR_FLEXRAMRSTC                RCC_MEMRSTCR_FLEXRAMRSTC_Msk         /*!< FLEXRAM reset */
31347 #define RCC_MEMRSTCR_CACHEAXIRAMRSTC_Pos        (10U)
31348 #define RCC_MEMRSTCR_CACHEAXIRAMRSTC_Msk        (0x1UL << RCC_MEMRSTCR_CACHEAXIRAMRSTC_Pos)     /*!< 0x00000400 */
31349 #define RCC_MEMRSTCR_CACHEAXIRAMRSTC            RCC_MEMRSTCR_CACHEAXIRAMRSTC_Msk     /*!< CACHEAXIRAM reset */
31350 #define RCC_MEMRSTCR_VENCRAMRSTC_Pos            (11U)
31351 #define RCC_MEMRSTCR_VENCRAMRSTC_Msk            (0x1UL << RCC_MEMRSTCR_VENCRAMRSTC_Pos) /*!< 0x00000800 */
31352 #define RCC_MEMRSTCR_VENCRAMRSTC                RCC_MEMRSTCR_VENCRAMRSTC_Msk         /*!< VENCRAM reset */
31353 #define RCC_MEMRSTCR_BOOTROMRSTC_Pos            (12U)
31354 #define RCC_MEMRSTCR_BOOTROMRSTC_Msk            (0x1UL << RCC_MEMRSTCR_BOOTROMRSTC_Pos) /*!< 0x00001000 */
31355 #define RCC_MEMRSTCR_BOOTROMRSTC                RCC_MEMRSTCR_BOOTROMRSTC_Msk         /*!< Boot ROM reset */
31356 
31357 /****************  Bit definition for RCC_AHB1RSTCR register  *****************/
31358 #define RCC_AHB1RSTCR_GPDMA1RSTC_Pos            (4U)
31359 #define RCC_AHB1RSTCR_GPDMA1RSTC_Msk            (0x1UL << RCC_AHB1RSTCR_GPDMA1RSTC_Pos) /*!< 0x00000010 */
31360 #define RCC_AHB1RSTCR_GPDMA1RSTC                RCC_AHB1RSTCR_GPDMA1RSTC_Msk         /*!< GPDMA1 reset */
31361 #define RCC_AHB1RSTCR_ADC12RSTC_Pos             (5U)
31362 #define RCC_AHB1RSTCR_ADC12RSTC_Msk             (0x1UL << RCC_AHB1RSTCR_ADC12RSTC_Pos)/*!< 0x00000020 */
31363 #define RCC_AHB1RSTCR_ADC12RSTC                 RCC_AHB1RSTCR_ADC12RSTC_Msk          /*!< ADC12 reset */
31364 
31365 /****************  Bit definition for RCC_AHB2RSTCR register  *****************/
31366 #define RCC_AHB2RSTCR_RAMCFGRSTC_Pos            (12U)
31367 #define RCC_AHB2RSTCR_RAMCFGRSTC_Msk            (0x1UL << RCC_AHB2RSTCR_RAMCFGRSTC_Pos) /*!< 0x00001000 */
31368 #define RCC_AHB2RSTCR_RAMCFGRSTC                RCC_AHB2RSTCR_RAMCFGRSTC_Msk         /*!< RAMCFG reset */
31369 #define RCC_AHB2RSTCR_MDF1RSTC_Pos              (16U)
31370 #define RCC_AHB2RSTCR_MDF1RSTC_Msk              (0x1UL << RCC_AHB2RSTCR_MDF1RSTC_Pos) /*!< 0x00010000 */
31371 #define RCC_AHB2RSTCR_MDF1RSTC                  RCC_AHB2RSTCR_MDF1RSTC_Msk           /*!< MDF1 reset */
31372 #define RCC_AHB2RSTCR_ADF1RSTC_Pos              (17U)
31373 #define RCC_AHB2RSTCR_ADF1RSTC_Msk              (0x1UL << RCC_AHB2RSTCR_ADF1RSTC_Pos) /*!< 0x00020000 */
31374 #define RCC_AHB2RSTCR_ADF1RSTC                  RCC_AHB2RSTCR_ADF1RSTC_Msk           /*!< ADF1 reset */
31375 
31376 /****************  Bit definition for RCC_AHB3RSTCR register  *****************/
31377 #define RCC_AHB3RSTCR_RNGRSTC_Pos               (0U)
31378 #define RCC_AHB3RSTCR_RNGRSTC_Msk               (0x1UL << RCC_AHB3RSTCR_RNGRSTC_Pos)  /*!< 0x00000001 */
31379 #define RCC_AHB3RSTCR_RNGRSTC                   RCC_AHB3RSTCR_RNGRSTC_Msk            /*!< RNG reset */
31380 #define RCC_AHB3RSTCR_HASHRSTC_Pos              (1U)
31381 #define RCC_AHB3RSTCR_HASHRSTC_Msk              (0x1UL << RCC_AHB3RSTCR_HASHRSTC_Pos) /*!< 0x00000002 */
31382 #define RCC_AHB3RSTCR_HASHRSTC                  RCC_AHB3RSTCR_HASHRSTC_Msk           /*!< HASH reset */
31383 #define RCC_AHB3RSTCR_CRYPRSTC_Pos              (2U)
31384 #define RCC_AHB3RSTCR_CRYPRSTC_Msk              (0x1UL << RCC_AHB3RSTCR_CRYPRSTC_Pos) /*!< 0x00000004 */
31385 #define RCC_AHB3RSTCR_CRYPRSTC                  RCC_AHB3RSTCR_CRYPRSTC_Msk           /*!< CRYP reset */
31386 #define RCC_AHB3RSTCR_SAESRSTC_Pos              (4U)
31387 #define RCC_AHB3RSTCR_SAESRSTC_Msk              (0x1UL << RCC_AHB3RSTCR_SAESRSTC_Pos) /*!< 0x00000010 */
31388 #define RCC_AHB3RSTCR_SAESRSTC                  RCC_AHB3RSTCR_SAESRSTC_Msk           /*!< SAES reset */
31389 #define RCC_AHB3RSTCR_PKARSTC_Pos               (8U)
31390 #define RCC_AHB3RSTCR_PKARSTC_Msk               (0x1UL << RCC_AHB3RSTCR_PKARSTC_Pos)  /*!< 0x00000100 */
31391 #define RCC_AHB3RSTCR_PKARSTC                   RCC_AHB3RSTCR_PKARSTC_Msk            /*!< PKA reset */
31392 #define RCC_AHB3RSTCR_IACRSTC_Pos               (10U)
31393 #define RCC_AHB3RSTCR_IACRSTC_Msk               (0x1UL << RCC_AHB3RSTCR_IACRSTC_Pos)  /*!< 0x00000400 */
31394 #define RCC_AHB3RSTCR_IACRSTC                   RCC_AHB3RSTCR_IACRSTC_Msk            /*!< IAC reset */
31395 
31396 /****************  Bit definition for RCC_AHB4RSTCR register  *****************/
31397 #define RCC_AHB4RSTCR_GPIOARSTC_Pos             (0U)
31398 #define RCC_AHB4RSTCR_GPIOARSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOARSTC_Pos)/*!< 0x00000001 */
31399 #define RCC_AHB4RSTCR_GPIOARSTC                 RCC_AHB4RSTCR_GPIOARSTC_Msk          /*!< GPIO A reset */
31400 #define RCC_AHB4RSTCR_GPIOBRSTC_Pos             (1U)
31401 #define RCC_AHB4RSTCR_GPIOBRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOBRSTC_Pos)/*!< 0x00000002 */
31402 #define RCC_AHB4RSTCR_GPIOBRSTC                 RCC_AHB4RSTCR_GPIOBRSTC_Msk          /*!< GPIO B reset */
31403 #define RCC_AHB4RSTCR_GPIOCRSTC_Pos             (2U)
31404 #define RCC_AHB4RSTCR_GPIOCRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOCRSTC_Pos)/*!< 0x00000004 */
31405 #define RCC_AHB4RSTCR_GPIOCRSTC                 RCC_AHB4RSTCR_GPIOCRSTC_Msk          /*!< GPIO C reset */
31406 #define RCC_AHB4RSTCR_GPIODRSTC_Pos             (3U)
31407 #define RCC_AHB4RSTCR_GPIODRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIODRSTC_Pos)/*!< 0x00000008 */
31408 #define RCC_AHB4RSTCR_GPIODRSTC                 RCC_AHB4RSTCR_GPIODRSTC_Msk          /*!< GPIO D reset */
31409 #define RCC_AHB4RSTCR_GPIOERSTC_Pos             (4U)
31410 #define RCC_AHB4RSTCR_GPIOERSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOERSTC_Pos)/*!< 0x00000010 */
31411 #define RCC_AHB4RSTCR_GPIOERSTC                 RCC_AHB4RSTCR_GPIOERSTC_Msk          /*!< GPIO E reset */
31412 #define RCC_AHB4RSTCR_GPIOFRSTC_Pos             (5U)
31413 #define RCC_AHB4RSTCR_GPIOFRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOFRSTC_Pos)/*!< 0x00000020 */
31414 #define RCC_AHB4RSTCR_GPIOFRSTC                 RCC_AHB4RSTCR_GPIOFRSTC_Msk          /*!< GPIO F reset */
31415 #define RCC_AHB4RSTCR_GPIOGRSTC_Pos             (6U)
31416 #define RCC_AHB4RSTCR_GPIOGRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOGRSTC_Pos)/*!< 0x00000040 */
31417 #define RCC_AHB4RSTCR_GPIOGRSTC                 RCC_AHB4RSTCR_GPIOGRSTC_Msk          /*!< GPIO G reset */
31418 #define RCC_AHB4RSTCR_GPIOHRSTC_Pos             (7U)
31419 #define RCC_AHB4RSTCR_GPIOHRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOHRSTC_Pos)/*!< 0x00000080 */
31420 #define RCC_AHB4RSTCR_GPIOHRSTC                 RCC_AHB4RSTCR_GPIOHRSTC_Msk          /*!< GPIO H reset */
31421 #define RCC_AHB4RSTCR_GPIONRSTC_Pos             (13U)
31422 #define RCC_AHB4RSTCR_GPIONRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIONRSTC_Pos)/*!< 0x00002000 */
31423 #define RCC_AHB4RSTCR_GPIONRSTC                 RCC_AHB4RSTCR_GPIONRSTC_Msk          /*!< GPIO N reset */
31424 #define RCC_AHB4RSTCR_GPIOORSTC_Pos             (14U)
31425 #define RCC_AHB4RSTCR_GPIOORSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOORSTC_Pos)/*!< 0x00004000 */
31426 #define RCC_AHB4RSTCR_GPIOORSTC                 RCC_AHB4RSTCR_GPIOORSTC_Msk          /*!< GPIO O reset */
31427 #define RCC_AHB4RSTCR_GPIOPRSTC_Pos             (15U)
31428 #define RCC_AHB4RSTCR_GPIOPRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOPRSTC_Pos)/*!< 0x00008000 */
31429 #define RCC_AHB4RSTCR_GPIOPRSTC                 RCC_AHB4RSTCR_GPIOPRSTC_Msk          /*!< GPIO P reset */
31430 #define RCC_AHB4RSTCR_GPIOQRSTC_Pos             (16U)
31431 #define RCC_AHB4RSTCR_GPIOQRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOQRSTC_Pos)/*!< 0x00010000 */
31432 #define RCC_AHB4RSTCR_GPIOQRSTC                 RCC_AHB4RSTCR_GPIOQRSTC_Msk          /*!< GPIO Q reset */
31433 #define RCC_AHB4RSTCR_PWRRSTC_Pos               (18U)
31434 #define RCC_AHB4RSTCR_PWRRSTC_Msk               (0x1UL << RCC_AHB4RSTCR_PWRRSTC_Pos)  /*!< 0x00040000 */
31435 #define RCC_AHB4RSTCR_PWRRSTC                   RCC_AHB4RSTCR_PWRRSTC_Msk            /*!< PWR reset */
31436 #define RCC_AHB4RSTCR_CRCRSTC_Pos               (19U)
31437 #define RCC_AHB4RSTCR_CRCRSTC_Msk               (0x1UL << RCC_AHB4RSTCR_CRCRSTC_Pos)  /*!< 0x00080000 */
31438 #define RCC_AHB4RSTCR_CRCRSTC                   RCC_AHB4RSTCR_CRCRSTC_Msk            /*!< CRC reset */
31439 
31440 /****************  Bit definition for RCC_AHB5RSTCR register  *****************/
31441 #define RCC_AHB5RSTCR_HPDMA1RSTC_Pos            (0U)
31442 #define RCC_AHB5RSTCR_HPDMA1RSTC_Msk            (0x1UL << RCC_AHB5RSTCR_HPDMA1RSTC_Pos) /*!< 0x00000001 */
31443 #define RCC_AHB5RSTCR_HPDMA1RSTC                RCC_AHB5RSTCR_HPDMA1RSTC_Msk         /*!< HPDMA1 reset */
31444 #define RCC_AHB5RSTCR_DMA2DRSTC_Pos             (1U)
31445 #define RCC_AHB5RSTCR_DMA2DRSTC_Msk             (0x1UL << RCC_AHB5RSTCR_DMA2DRSTC_Pos)/*!< 0x00000002 */
31446 #define RCC_AHB5RSTCR_DMA2DRSTC                 RCC_AHB5RSTCR_DMA2DRSTC_Msk          /*!< DMA2D reset */
31447 #define RCC_AHB5RSTCR_JPEGRSTC_Pos              (3U)
31448 #define RCC_AHB5RSTCR_JPEGRSTC_Msk              (0x1UL << RCC_AHB5RSTCR_JPEGRSTC_Pos) /*!< 0x00000008 */
31449 #define RCC_AHB5RSTCR_JPEGRSTC                  RCC_AHB5RSTCR_JPEGRSTC_Msk           /*!< JPEG reset */
31450 #define RCC_AHB5RSTCR_FMCRSTC_Pos               (4U)
31451 #define RCC_AHB5RSTCR_FMCRSTC_Msk               (0x1UL << RCC_AHB5RSTCR_FMCRSTC_Pos)  /*!< 0x00000010 */
31452 #define RCC_AHB5RSTCR_FMCRSTC                   RCC_AHB5RSTCR_FMCRSTC_Msk            /*!< FMC reset */
31453 #define RCC_AHB5RSTCR_XSPI1RSTC_Pos             (5U)
31454 #define RCC_AHB5RSTCR_XSPI1RSTC_Msk             (0x1UL << RCC_AHB5RSTCR_XSPI1RSTC_Pos)/*!< 0x00000020 */
31455 #define RCC_AHB5RSTCR_XSPI1RSTC                 RCC_AHB5RSTCR_XSPI1RSTC_Msk          /*!< XSPI1 reset */
31456 #define RCC_AHB5RSTCR_PSSIRSTC_Pos              (6U)
31457 #define RCC_AHB5RSTCR_PSSIRSTC_Msk              (0x1UL << RCC_AHB5RSTCR_PSSIRSTC_Pos) /*!< 0x00000040 */
31458 #define RCC_AHB5RSTCR_PSSIRSTC                  RCC_AHB5RSTCR_PSSIRSTC_Msk           /*!< PSSI reset */
31459 #define RCC_AHB5RSTCR_SDMMC2RSTC_Pos            (7U)
31460 #define RCC_AHB5RSTCR_SDMMC2RSTC_Msk            (0x1UL << RCC_AHB5RSTCR_SDMMC2RSTC_Pos) /*!< 0x00000080 */
31461 #define RCC_AHB5RSTCR_SDMMC2RSTC                RCC_AHB5RSTCR_SDMMC2RSTC_Msk         /*!< SDMMC2 reset */
31462 #define RCC_AHB5RSTCR_SDMMC1RSTC_Pos            (8U)
31463 #define RCC_AHB5RSTCR_SDMMC1RSTC_Msk            (0x1UL << RCC_AHB5RSTCR_SDMMC1RSTC_Pos) /*!< 0x00000100 */
31464 #define RCC_AHB5RSTCR_SDMMC1RSTC                RCC_AHB5RSTCR_SDMMC1RSTC_Msk         /*!< SDMMC1 reset */
31465 #define RCC_AHB5RSTCR_XSPI2RSTC_Pos             (12U)
31466 #define RCC_AHB5RSTCR_XSPI2RSTC_Msk             (0x1UL << RCC_AHB5RSTCR_XSPI2RSTC_Pos)/*!< 0x00001000 */
31467 #define RCC_AHB5RSTCR_XSPI2RSTC                 RCC_AHB5RSTCR_XSPI2RSTC_Msk          /*!< XSPI2 reset */
31468 #define RCC_AHB5RSTCR_XSPIMRSTC_Pos             (13U)
31469 #define RCC_AHB5RSTCR_XSPIMRSTC_Msk             (0x1UL << RCC_AHB5RSTCR_XSPIMRSTC_Pos)/*!< 0x00002000 */
31470 #define RCC_AHB5RSTCR_XSPIMRSTC                 RCC_AHB5RSTCR_XSPIMRSTC_Msk          /*!< XSPIM reset */
31471 #define RCC_AHB5RSTCR_XSPI3RSTC_Pos             (17U)
31472 #define RCC_AHB5RSTCR_XSPI3RSTC_Msk             (0x1UL << RCC_AHB5RSTCR_XSPI3RSTC_Pos)/*!< 0x00020000 */
31473 #define RCC_AHB5RSTCR_XSPI3RSTC                 RCC_AHB5RSTCR_XSPI3RSTC_Msk          /*!< XSPI3 reset */
31474 #define RCC_AHB5RSTCR_GFXMMURSTC_Pos            (19U)
31475 #define RCC_AHB5RSTCR_GFXMMURSTC_Msk            (0x1UL << RCC_AHB5RSTCR_GFXMMURSTC_Pos) /*!< 0x00080000 */
31476 #define RCC_AHB5RSTCR_GFXMMURSTC                RCC_AHB5RSTCR_GFXMMURSTC_Msk         /*!< GFXMMU reset */
31477 #define RCC_AHB5RSTCR_GPU2DRSTC_Pos             (20U)
31478 #define RCC_AHB5RSTCR_GPU2DRSTC_Msk             (0x1UL << RCC_AHB5RSTCR_GPU2DRSTC_Pos)/*!< 0x00100000 */
31479 #define RCC_AHB5RSTCR_GPU2DRSTC                 RCC_AHB5RSTCR_GPU2DRSTC_Msk          /*!< GPU2D reset */
31480 #define RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Pos        (23U)
31481 #define RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Msk        (0x1UL << RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Pos)     /*!< 0x00800000 */
31482 #define RCC_AHB5RSTCR_OTG1PHYCTLRSTC            RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Msk     /*!< OTG1PHYCTL reset */
31483 #define RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Pos        (24U)
31484 #define RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Msk        (0x1UL << RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Pos)     /*!< 0x01000000 */
31485 #define RCC_AHB5RSTCR_OTG2PHYCTLRSTC            RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Msk     /*!< OTG2PHYCTL reset */
31486 #define RCC_AHB5RSTCR_ETH1RSTC_Pos              (25U)
31487 #define RCC_AHB5RSTCR_ETH1RSTC_Msk              (0x1UL << RCC_AHB5RSTCR_ETH1RSTC_Pos) /*!< 0x02000000 */
31488 #define RCC_AHB5RSTCR_ETH1RSTC                  RCC_AHB5RSTCR_ETH1RSTC_Msk           /*!< ETH1 reset */
31489 #define RCC_AHB5RSTCR_OTG1RSTC_Pos              (26U)
31490 #define RCC_AHB5RSTCR_OTG1RSTC_Msk              (0x1UL << RCC_AHB5RSTCR_OTG1RSTC_Pos) /*!< 0x04000000 */
31491 #define RCC_AHB5RSTCR_OTG1RSTC                  RCC_AHB5RSTCR_OTG1RSTC_Msk           /*!< OTG1 reset */
31492 #define RCC_AHB5RSTCR_OTGPHY1RSTC_Pos           (27U)
31493 #define RCC_AHB5RSTCR_OTGPHY1RSTC_Msk           (0x1UL << RCC_AHB5RSTCR_OTGPHY1RSTC_Pos)  /*!< 0x08000000 */
31494 #define RCC_AHB5RSTCR_OTGPHY1RSTC               RCC_AHB5RSTCR_OTGPHY1RSTC_Msk        /*!< OTGPHY1 reset */
31495 #define RCC_AHB5RSTCR_OTGPHY2RSTC_Pos           (28U)
31496 #define RCC_AHB5RSTCR_OTGPHY2RSTC_Msk           (0x1UL << RCC_AHB5RSTCR_OTGPHY2RSTC_Pos)  /*!< 0x10000000 */
31497 #define RCC_AHB5RSTCR_OTGPHY2RSTC               RCC_AHB5RSTCR_OTGPHY2RSTC_Msk        /*!< OTGPHY2 reset */
31498 #define RCC_AHB5RSTCR_OTG2RSTC_Pos              (29U)
31499 #define RCC_AHB5RSTCR_OTG2RSTC_Msk              (0x1UL << RCC_AHB5RSTCR_OTG2RSTC_Pos) /*!< 0x20000000 */
31500 #define RCC_AHB5RSTCR_OTG2RSTC                  RCC_AHB5RSTCR_OTG2RSTC_Msk           /*!< OTG2 reset */
31501 #define RCC_AHB5RSTCR_CACHEAXIRSTC_Pos          (30U)
31502 #define RCC_AHB5RSTCR_CACHEAXIRSTC_Msk          (0x1UL << RCC_AHB5RSTCR_CACHEAXIRSTC_Pos)   /*!< 0x40000000 */
31503 #define RCC_AHB5RSTCR_CACHEAXIRSTC              RCC_AHB5RSTCR_CACHEAXIRSTC_Msk       /*!< CACHEAXI reset */
31504 #define RCC_AHB5RSTCR_NPURSTC_Pos               (31U)
31505 #define RCC_AHB5RSTCR_NPURSTC_Msk               (0x1UL << RCC_AHB5RSTCR_NPURSTC_Pos)  /*!< 0x80000000 */
31506 #define RCC_AHB5RSTCR_NPURSTC                   RCC_AHB5RSTCR_NPURSTC_Msk            /*!< NPU reset */
31507 
31508 /****************  Bit definition for RCC_APB1RSTCR1 register  ****************/
31509 #define RCC_APB1RSTCR1_TIM2RSTC_Pos             (0U)
31510 #define RCC_APB1RSTCR1_TIM2RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_TIM2RSTC_Pos)/*!< 0x00000001 */
31511 #define RCC_APB1RSTCR1_TIM2RSTC                 RCC_APB1RSTCR1_TIM2RSTC_Msk          /*!< TIM2 reset */
31512 #define RCC_APB1RSTCR1_TIM3RSTC_Pos             (1U)
31513 #define RCC_APB1RSTCR1_TIM3RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_TIM3RSTC_Pos)/*!< 0x00000002 */
31514 #define RCC_APB1RSTCR1_TIM3RSTC                 RCC_APB1RSTCR1_TIM3RSTC_Msk          /*!< TIM3 reset */
31515 #define RCC_APB1RSTCR1_TIM4RSTC_Pos             (2U)
31516 #define RCC_APB1RSTCR1_TIM4RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_TIM4RSTC_Pos)/*!< 0x00000004 */
31517 #define RCC_APB1RSTCR1_TIM4RSTC                 RCC_APB1RSTCR1_TIM4RSTC_Msk          /*!< TIM4 reset */
31518 #define RCC_APB1RSTCR1_TIM5RSTC_Pos             (3U)
31519 #define RCC_APB1RSTCR1_TIM5RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_TIM5RSTC_Pos)/*!< 0x00000008 */
31520 #define RCC_APB1RSTCR1_TIM5RSTC                 RCC_APB1RSTCR1_TIM5RSTC_Msk          /*!< TIM5 reset */
31521 #define RCC_APB1RSTCR1_TIM6RSTC_Pos             (4U)
31522 #define RCC_APB1RSTCR1_TIM6RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_TIM6RSTC_Pos)/*!< 0x00000010 */
31523 #define RCC_APB1RSTCR1_TIM6RSTC                 RCC_APB1RSTCR1_TIM6RSTC_Msk          /*!< TIM6 reset */
31524 #define RCC_APB1RSTCR1_TIM7RSTC_Pos             (5U)
31525 #define RCC_APB1RSTCR1_TIM7RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_TIM7RSTC_Pos)/*!< 0x00000020 */
31526 #define RCC_APB1RSTCR1_TIM7RSTC                 RCC_APB1RSTCR1_TIM7RSTC_Msk          /*!< TIM7 reset */
31527 #define RCC_APB1RSTCR1_TIM12RSTC_Pos            (6U)
31528 #define RCC_APB1RSTCR1_TIM12RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_TIM12RSTC_Pos) /*!< 0x00000040 */
31529 #define RCC_APB1RSTCR1_TIM12RSTC                RCC_APB1RSTCR1_TIM12RSTC_Msk         /*!< TIM12 reset */
31530 #define RCC_APB1RSTCR1_TIM13RSTC_Pos            (7U)
31531 #define RCC_APB1RSTCR1_TIM13RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_TIM13RSTC_Pos) /*!< 0x00000080 */
31532 #define RCC_APB1RSTCR1_TIM13RSTC                RCC_APB1RSTCR1_TIM13RSTC_Msk         /*!< TIM13 reset */
31533 #define RCC_APB1RSTCR1_TIM14RSTC_Pos            (8U)
31534 #define RCC_APB1RSTCR1_TIM14RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_TIM14RSTC_Pos) /*!< 0x00000100 */
31535 #define RCC_APB1RSTCR1_TIM14RSTC                RCC_APB1RSTCR1_TIM14RSTC_Msk         /*!< TIM14 reset */
31536 #define RCC_APB1RSTCR1_LPTIM1RSTC_Pos           (9U)
31537 #define RCC_APB1RSTCR1_LPTIM1RSTC_Msk           (0x1UL << RCC_APB1RSTCR1_LPTIM1RSTC_Pos)  /*!< 0x00000200 */
31538 #define RCC_APB1RSTCR1_LPTIM1RSTC               RCC_APB1RSTCR1_LPTIM1RSTC_Msk        /*!< LPTIM1 reset */
31539 #define RCC_APB1RSTCR1_WWDGRSTC_Pos             (11U)
31540 #define RCC_APB1RSTCR1_WWDGRSTC_Msk             (0x1UL << RCC_APB1RSTCR1_WWDGRSTC_Pos)/*!< 0x00000800 */
31541 #define RCC_APB1RSTCR1_WWDGRSTC                 RCC_APB1RSTCR1_WWDGRSTC_Msk          /*!< WWDG reset */
31542 #define RCC_APB1RSTCR1_TIM10RSTC_Pos            (12U)
31543 #define RCC_APB1RSTCR1_TIM10RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_TIM10RSTC_Pos) /*!< 0x00001000 */
31544 #define RCC_APB1RSTCR1_TIM10RSTC                RCC_APB1RSTCR1_TIM10RSTC_Msk         /*!< TIM10 reset */
31545 #define RCC_APB1RSTCR1_TIM11RSTC_Pos            (13U)
31546 #define RCC_APB1RSTCR1_TIM11RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_TIM11RSTC_Pos) /*!< 0x00002000 */
31547 #define RCC_APB1RSTCR1_TIM11RSTC                RCC_APB1RSTCR1_TIM11RSTC_Msk         /*!< TIM11 reset */
31548 #define RCC_APB1RSTCR1_SPI2RSTC_Pos             (14U)
31549 #define RCC_APB1RSTCR1_SPI2RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_SPI2RSTC_Pos)/*!< 0x00004000 */
31550 #define RCC_APB1RSTCR1_SPI2RSTC                 RCC_APB1RSTCR1_SPI2RSTC_Msk          /*!< SPI2 reset */
31551 #define RCC_APB1RSTCR1_SPI3RSTC_Pos             (15U)
31552 #define RCC_APB1RSTCR1_SPI3RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_SPI3RSTC_Pos)/*!< 0x00008000 */
31553 #define RCC_APB1RSTCR1_SPI3RSTC                 RCC_APB1RSTCR1_SPI3RSTC_Msk          /*!< SPI3 reset */
31554 #define RCC_APB1RSTCR1_SPDIFRX1RSTC_Pos         (16U)
31555 #define RCC_APB1RSTCR1_SPDIFRX1RSTC_Msk         (0x1UL << RCC_APB1RSTCR1_SPDIFRX1RSTC_Pos)    /*!< 0x00010000 */
31556 #define RCC_APB1RSTCR1_SPDIFRX1RSTC             RCC_APB1RSTCR1_SPDIFRX1RSTC_Msk      /*!< SPDIFRX1 reset */
31557 #define RCC_APB1RSTCR1_USART2RSTC_Pos           (17U)
31558 #define RCC_APB1RSTCR1_USART2RSTC_Msk           (0x1UL << RCC_APB1RSTCR1_USART2RSTC_Pos)  /*!< 0x00020000 */
31559 #define RCC_APB1RSTCR1_USART2RSTC               RCC_APB1RSTCR1_USART2RSTC_Msk        /*!< USART2 reset */
31560 #define RCC_APB1RSTCR1_USART3RSTC_Pos           (18U)
31561 #define RCC_APB1RSTCR1_USART3RSTC_Msk           (0x1UL << RCC_APB1RSTCR1_USART3RSTC_Pos)  /*!< 0x00040000 */
31562 #define RCC_APB1RSTCR1_USART3RSTC               RCC_APB1RSTCR1_USART3RSTC_Msk        /*!< USART3 reset */
31563 #define RCC_APB1RSTCR1_UART4RSTC_Pos            (19U)
31564 #define RCC_APB1RSTCR1_UART4RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_UART4RSTC_Pos) /*!< 0x00080000 */
31565 #define RCC_APB1RSTCR1_UART4RSTC                RCC_APB1RSTCR1_UART4RSTC_Msk         /*!< UART4 reset */
31566 #define RCC_APB1RSTCR1_UART5RSTC_Pos            (20U)
31567 #define RCC_APB1RSTCR1_UART5RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_UART5RSTC_Pos) /*!< 0x00100000 */
31568 #define RCC_APB1RSTCR1_UART5RSTC                RCC_APB1RSTCR1_UART5RSTC_Msk         /*!< UART5 reset */
31569 #define RCC_APB1RSTCR1_I2C1RSTC_Pos             (21U)
31570 #define RCC_APB1RSTCR1_I2C1RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_I2C1RSTC_Pos)/*!< 0x00200000 */
31571 #define RCC_APB1RSTCR1_I2C1RSTC                 RCC_APB1RSTCR1_I2C1RSTC_Msk          /*!< I2C1 reset */
31572 #define RCC_APB1RSTCR1_I2C2RSTC_Pos             (22U)
31573 #define RCC_APB1RSTCR1_I2C2RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_I2C2RSTC_Pos)/*!< 0x00400000 */
31574 #define RCC_APB1RSTCR1_I2C2RSTC                 RCC_APB1RSTCR1_I2C2RSTC_Msk          /*!< I2C2 reset */
31575 #define RCC_APB1RSTCR1_I2C3RSTC_Pos             (23U)
31576 #define RCC_APB1RSTCR1_I2C3RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_I2C3RSTC_Pos)/*!< 0x00800000 */
31577 #define RCC_APB1RSTCR1_I2C3RSTC                 RCC_APB1RSTCR1_I2C3RSTC_Msk          /*!< I2C3 reset */
31578 #define RCC_APB1RSTCR1_I3C1RSTC_Pos             (24U)
31579 #define RCC_APB1RSTCR1_I3C1RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_I3C1RSTC_Pos)/*!< 0x01000000 */
31580 #define RCC_APB1RSTCR1_I3C1RSTC                 RCC_APB1RSTCR1_I3C1RSTC_Msk          /*!< I3C1 reset */
31581 #define RCC_APB1RSTCR1_I3C2RSTC_Pos             (25U)
31582 #define RCC_APB1RSTCR1_I3C2RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_I3C2RSTC_Pos)/*!< 0x02000000 */
31583 #define RCC_APB1RSTCR1_I3C2RSTC                 RCC_APB1RSTCR1_I3C2RSTC_Msk          /*!< I3C2 reset */
31584 #define RCC_APB1RSTCR1_UART7RSTC_Pos            (30U)
31585 #define RCC_APB1RSTCR1_UART7RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_UART7RSTC_Pos) /*!< 0x40000000 */
31586 #define RCC_APB1RSTCR1_UART7RSTC                RCC_APB1RSTCR1_UART7RSTC_Msk         /*!< UART7 reset */
31587 #define RCC_APB1RSTCR1_UART8RSTC_Pos            (31U)
31588 #define RCC_APB1RSTCR1_UART8RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_UART8RSTC_Pos) /*!< 0x80000000 */
31589 #define RCC_APB1RSTCR1_UART8RSTC                RCC_APB1RSTCR1_UART8RSTC_Msk         /*!< UART8 reset */
31590 
31591 /****************  Bit definition for RCC_APB1RSTCR2 register  ****************/
31592 #define RCC_APB1RSTCR2_MDIOSRSTC_Pos            (5U)
31593 #define RCC_APB1RSTCR2_MDIOSRSTC_Msk            (0x1UL << RCC_APB1RSTCR2_MDIOSRSTC_Pos) /*!< 0x00000020 */
31594 #define RCC_APB1RSTCR2_MDIOSRSTC                RCC_APB1RSTCR2_MDIOSRSTC_Msk         /*!< MDIOS reset */
31595 #define RCC_APB1RSTCR2_FDCANRSTC_Pos            (8U)
31596 #define RCC_APB1RSTCR2_FDCANRSTC_Msk            (0x1UL << RCC_APB1RSTCR2_FDCANRSTC_Pos) /*!< 0x00000100 */
31597 #define RCC_APB1RSTCR2_FDCANRSTC                RCC_APB1RSTCR2_FDCANRSTC_Msk         /*!< FDCAN reset */
31598 #define RCC_APB1RSTCR2_UCPD1RSTC_Pos            (18U)
31599 #define RCC_APB1RSTCR2_UCPD1RSTC_Msk            (0x1UL << RCC_APB1RSTCR2_UCPD1RSTC_Pos) /*!< 0x00040000 */
31600 #define RCC_APB1RSTCR2_UCPD1RSTC                RCC_APB1RSTCR2_UCPD1RSTC_Msk         /*!< UCPD1 reset */
31601 
31602 /****************  Bit definition for RCC_APB2RSTCR register  *****************/
31603 #define RCC_APB2RSTCR_TIM1RSTC_Pos              (0U)
31604 #define RCC_APB2RSTCR_TIM1RSTC_Msk              (0x1UL << RCC_APB2RSTCR_TIM1RSTC_Pos) /*!< 0x00000001 */
31605 #define RCC_APB2RSTCR_TIM1RSTC                  RCC_APB2RSTCR_TIM1RSTC_Msk           /*!< TIM1 reset */
31606 #define RCC_APB2RSTCR_TIM8RSTC_Pos              (1U)
31607 #define RCC_APB2RSTCR_TIM8RSTC_Msk              (0x1UL << RCC_APB2RSTCR_TIM8RSTC_Pos) /*!< 0x00000002 */
31608 #define RCC_APB2RSTCR_TIM8RSTC                  RCC_APB2RSTCR_TIM8RSTC_Msk           /*!< TIM8 reset */
31609 #define RCC_APB2RSTCR_USART1RSTC_Pos            (4U)
31610 #define RCC_APB2RSTCR_USART1RSTC_Msk            (0x1UL << RCC_APB2RSTCR_USART1RSTC_Pos) /*!< 0x00000010 */
31611 #define RCC_APB2RSTCR_USART1RSTC                RCC_APB2RSTCR_USART1RSTC_Msk         /*!< USART1 reset */
31612 #define RCC_APB2RSTCR_USART6RSTC_Pos            (5U)
31613 #define RCC_APB2RSTCR_USART6RSTC_Msk            (0x1UL << RCC_APB2RSTCR_USART6RSTC_Pos) /*!< 0x00000020 */
31614 #define RCC_APB2RSTCR_USART6RSTC                RCC_APB2RSTCR_USART6RSTC_Msk         /*!< USART6 reset */
31615 #define RCC_APB2RSTCR_UART9RSTC_Pos             (6U)
31616 #define RCC_APB2RSTCR_UART9RSTC_Msk             (0x1UL << RCC_APB2RSTCR_UART9RSTC_Pos)/*!< 0x00000040 */
31617 #define RCC_APB2RSTCR_UART9RSTC                 RCC_APB2RSTCR_UART9RSTC_Msk          /*!< UART9 reset */
31618 #define RCC_APB2RSTCR_USART10RSTC_Pos           (7U)
31619 #define RCC_APB2RSTCR_USART10RSTC_Msk           (0x1UL << RCC_APB2RSTCR_USART10RSTC_Pos)  /*!< 0x00000080 */
31620 #define RCC_APB2RSTCR_USART10RSTC               RCC_APB2RSTCR_USART10RSTC_Msk        /*!< USART10 reset */
31621 #define RCC_APB2RSTCR_SPI1RSTC_Pos              (12U)
31622 #define RCC_APB2RSTCR_SPI1RSTC_Msk              (0x1UL << RCC_APB2RSTCR_SPI1RSTC_Pos) /*!< 0x00001000 */
31623 #define RCC_APB2RSTCR_SPI1RSTC                  RCC_APB2RSTCR_SPI1RSTC_Msk           /*!< SPI1 reset */
31624 #define RCC_APB2RSTCR_SPI4RSTC_Pos              (13U)
31625 #define RCC_APB2RSTCR_SPI4RSTC_Msk              (0x1UL << RCC_APB2RSTCR_SPI4RSTC_Pos) /*!< 0x00002000 */
31626 #define RCC_APB2RSTCR_SPI4RSTC                  RCC_APB2RSTCR_SPI4RSTC_Msk           /*!< SPI4 reset */
31627 #define RCC_APB2RSTCR_TIM18RSTC_Pos             (15U)
31628 #define RCC_APB2RSTCR_TIM18RSTC_Msk             (0x1UL << RCC_APB2RSTCR_TIM18RSTC_Pos)/*!< 0x00008000 */
31629 #define RCC_APB2RSTCR_TIM18RSTC                 RCC_APB2RSTCR_TIM18RSTC_Msk          /*!< TIM18 reset */
31630 #define RCC_APB2RSTCR_TIM15RSTC_Pos             (16U)
31631 #define RCC_APB2RSTCR_TIM15RSTC_Msk             (0x1UL << RCC_APB2RSTCR_TIM15RSTC_Pos)/*!< 0x00010000 */
31632 #define RCC_APB2RSTCR_TIM15RSTC                 RCC_APB2RSTCR_TIM15RSTC_Msk          /*!< TIM15 reset */
31633 #define RCC_APB2RSTCR_TIM16RSTC_Pos             (17U)
31634 #define RCC_APB2RSTCR_TIM16RSTC_Msk             (0x1UL << RCC_APB2RSTCR_TIM16RSTC_Pos)/*!< 0x00020000 */
31635 #define RCC_APB2RSTCR_TIM16RSTC                 RCC_APB2RSTCR_TIM16RSTC_Msk          /*!< TIM16 reset */
31636 #define RCC_APB2RSTCR_TIM17RSTC_Pos             (18U)
31637 #define RCC_APB2RSTCR_TIM17RSTC_Msk             (0x1UL << RCC_APB2RSTCR_TIM17RSTC_Pos)/*!< 0x00040000 */
31638 #define RCC_APB2RSTCR_TIM17RSTC                 RCC_APB2RSTCR_TIM17RSTC_Msk          /*!< TIM17 reset */
31639 #define RCC_APB2RSTCR_TIM9RSTC_Pos              (19U)
31640 #define RCC_APB2RSTCR_TIM9RSTC_Msk              (0x1UL << RCC_APB2RSTCR_TIM9RSTC_Pos) /*!< 0x00080000 */
31641 #define RCC_APB2RSTCR_TIM9RSTC                  RCC_APB2RSTCR_TIM9RSTC_Msk           /*!< TIM9 reset */
31642 #define RCC_APB2RSTCR_SPI5RSTC_Pos              (20U)
31643 #define RCC_APB2RSTCR_SPI5RSTC_Msk              (0x1UL << RCC_APB2RSTCR_SPI5RSTC_Pos) /*!< 0x00100000 */
31644 #define RCC_APB2RSTCR_SPI5RSTC                  RCC_APB2RSTCR_SPI5RSTC_Msk           /*!< SPI5 reset */
31645 #define RCC_APB2RSTCR_SAI1RSTC_Pos              (21U)
31646 #define RCC_APB2RSTCR_SAI1RSTC_Msk              (0x1UL << RCC_APB2RSTCR_SAI1RSTC_Pos) /*!< 0x00200000 */
31647 #define RCC_APB2RSTCR_SAI1RSTC                  RCC_APB2RSTCR_SAI1RSTC_Msk           /*!< SAI1 reset */
31648 #define RCC_APB2RSTCR_SAI2RSTC_Pos              (22U)
31649 #define RCC_APB2RSTCR_SAI2RSTC_Msk              (0x1UL << RCC_APB2RSTCR_SAI2RSTC_Pos) /*!< 0x00400000 */
31650 #define RCC_APB2RSTCR_SAI2RSTC                  RCC_APB2RSTCR_SAI2RSTC_Msk           /*!< SAI2 reset */
31651 
31652 /****************  Bit definition for RCC_APB4RSTCR1 register  ****************/
31653 #define RCC_APB4RSTCR1_HDPRSTC_Pos              (2U)
31654 #define RCC_APB4RSTCR1_HDPRSTC_Msk              (0x1UL << RCC_APB4RSTCR1_HDPRSTC_Pos) /*!< 0x00000004 */
31655 #define RCC_APB4RSTCR1_HDPRSTC                  RCC_APB4RSTCR1_HDPRSTC_Msk           /*!< HDP reset */
31656 #define RCC_APB4RSTCR1_LPUART1RSTC_Pos          (3U)
31657 #define RCC_APB4RSTCR1_LPUART1RSTC_Msk          (0x1UL << RCC_APB4RSTCR1_LPUART1RSTC_Pos)   /*!< 0x00000008 */
31658 #define RCC_APB4RSTCR1_LPUART1RSTC              RCC_APB4RSTCR1_LPUART1RSTC_Msk       /*!< LPUART1 reset */
31659 #define RCC_APB4RSTCR1_SPI6RSTC_Pos             (5U)
31660 #define RCC_APB4RSTCR1_SPI6RSTC_Msk             (0x1UL << RCC_APB4RSTCR1_SPI6RSTC_Pos)/*!< 0x00000020 */
31661 #define RCC_APB4RSTCR1_SPI6RSTC                 RCC_APB4RSTCR1_SPI6RSTC_Msk          /*!< SPI6 reset */
31662 #define RCC_APB4RSTCR1_I2C4RSTC_Pos             (7U)
31663 #define RCC_APB4RSTCR1_I2C4RSTC_Msk             (0x1UL << RCC_APB4RSTCR1_I2C4RSTC_Pos)/*!< 0x00000080 */
31664 #define RCC_APB4RSTCR1_I2C4RSTC                 RCC_APB4RSTCR1_I2C4RSTC_Msk          /*!< I2C4 reset */
31665 #define RCC_APB4RSTCR1_LPTIM2RSTC_Pos           (9U)
31666 #define RCC_APB4RSTCR1_LPTIM2RSTC_Msk           (0x1UL << RCC_APB4RSTCR1_LPTIM2RSTC_Pos)  /*!< 0x00000200 */
31667 #define RCC_APB4RSTCR1_LPTIM2RSTC               RCC_APB4RSTCR1_LPTIM2RSTC_Msk        /*!< LPTIM2 reset */
31668 #define RCC_APB4RSTCR1_LPTIM3RSTC_Pos           (10U)
31669 #define RCC_APB4RSTCR1_LPTIM3RSTC_Msk           (0x1UL << RCC_APB4RSTCR1_LPTIM3RSTC_Pos)  /*!< 0x00000400 */
31670 #define RCC_APB4RSTCR1_LPTIM3RSTC               RCC_APB4RSTCR1_LPTIM3RSTC_Msk        /*!< LPTIM3 reset */
31671 #define RCC_APB4RSTCR1_LPTIM4RSTC_Pos           (11U)
31672 #define RCC_APB4RSTCR1_LPTIM4RSTC_Msk           (0x1UL << RCC_APB4RSTCR1_LPTIM4RSTC_Pos)  /*!< 0x00000800 */
31673 #define RCC_APB4RSTCR1_LPTIM4RSTC               RCC_APB4RSTCR1_LPTIM4RSTC_Msk        /*!< LPTIM4 reset */
31674 #define RCC_APB4RSTCR1_LPTIM5RSTC_Pos           (12U)
31675 #define RCC_APB4RSTCR1_LPTIM5RSTC_Msk           (0x1UL << RCC_APB4RSTCR1_LPTIM5RSTC_Pos)  /*!< 0x00001000 */
31676 #define RCC_APB4RSTCR1_LPTIM5RSTC               RCC_APB4RSTCR1_LPTIM5RSTC_Msk        /*!< LPTIM5 reset */
31677 #define RCC_APB4RSTCR1_VREFBUFRSTC_Pos          (15U)
31678 #define RCC_APB4RSTCR1_VREFBUFRSTC_Msk          (0x1UL << RCC_APB4RSTCR1_VREFBUFRSTC_Pos)   /*!< 0x00008000 */
31679 #define RCC_APB4RSTCR1_VREFBUFRSTC              RCC_APB4RSTCR1_VREFBUFRSTC_Msk       /*!< VREFBUF reset */
31680 #define RCC_APB4RSTCR1_RTCRSTC_Pos              (16U)
31681 #define RCC_APB4RSTCR1_RTCRSTC_Msk              (0x1UL << RCC_APB4RSTCR1_RTCRSTC_Pos) /*!< 0x00010000 */
31682 #define RCC_APB4RSTCR1_RTCRSTC                  RCC_APB4RSTCR1_RTCRSTC_Msk           /*!< RTC reset */
31683 
31684 /****************  Bit definition for RCC_APB4RSTCR2 register  ****************/
31685 #define RCC_APB4RSTCR2_SYSCFGRSTC_Pos           (0U)
31686 #define RCC_APB4RSTCR2_SYSCFGRSTC_Msk           (0x1UL << RCC_APB4RSTCR2_SYSCFGRSTC_Pos)  /*!< 0x00000001 */
31687 #define RCC_APB4RSTCR2_SYSCFGRSTC               RCC_APB4RSTCR2_SYSCFGRSTC_Msk        /*!< SYSCFG reset */
31688 #define RCC_APB4RSTCR2_DTSRSTC_Pos              (2U)
31689 #define RCC_APB4RSTCR2_DTSRSTC_Msk              (0x1UL << RCC_APB4RSTCR2_DTSRSTC_Pos) /*!< 0x00000004 */
31690 #define RCC_APB4RSTCR2_DTSRSTC                  RCC_APB4RSTCR2_DTSRSTC_Msk           /*!< DTS reset */
31691 
31692 /****************  Bit definition for RCC_APB5RSTCR register  *****************/
31693 #define RCC_APB5RSTCR_LTDCRSTC_Pos              (1U)
31694 #define RCC_APB5RSTCR_LTDCRSTC_Msk              (0x1UL << RCC_APB5RSTCR_LTDCRSTC_Pos) /*!< 0x00000002 */
31695 #define RCC_APB5RSTCR_LTDCRSTC                  RCC_APB5RSTCR_LTDCRSTC_Msk           /*!< LTDC reset */
31696 #define RCC_APB5RSTCR_DCMIPPRSTC_Pos            (2U)
31697 #define RCC_APB5RSTCR_DCMIPPRSTC_Msk            (0x1UL << RCC_APB5RSTCR_DCMIPPRSTC_Pos) /*!< 0x00000004 */
31698 #define RCC_APB5RSTCR_DCMIPPRSTC                RCC_APB5RSTCR_DCMIPPRSTC_Msk         /*!< DCMIPP reset */
31699 #define RCC_APB5RSTCR_GFXTIMRSTC_Pos            (4U)
31700 #define RCC_APB5RSTCR_GFXTIMRSTC_Msk            (0x1UL << RCC_APB5RSTCR_GFXTIMRSTC_Pos) /*!< 0x00000010 */
31701 #define RCC_APB5RSTCR_GFXTIMRSTC                RCC_APB5RSTCR_GFXTIMRSTC_Msk         /*!< GFXTIM reset */
31702 #define RCC_APB5RSTCR_VENCRSTC_Pos              (5U)
31703 #define RCC_APB5RSTCR_VENCRSTC_Msk              (0x1UL << RCC_APB5RSTCR_VENCRSTC_Pos) /*!< 0x00000020 */
31704 #define RCC_APB5RSTCR_VENCRSTC                  RCC_APB5RSTCR_VENCRSTC_Msk           /*!< VENC reset */
31705 #define RCC_APB5RSTCR_CSIRSTC_Pos               (6U)
31706 #define RCC_APB5RSTCR_CSIRSTC_Msk               (0x1UL << RCC_APB5RSTCR_CSIRSTC_Pos)  /*!< 0x00000040 */
31707 #define RCC_APB5RSTCR_CSIRSTC                   RCC_APB5RSTCR_CSIRSTC_Msk            /*!< CSI reset */
31708 
31709 /*****************  Bit definition for RCC_DIVENCR register  ******************/
31710 #define RCC_DIVENCR_IC1ENC_Pos                  (0U)
31711 #define RCC_DIVENCR_IC1ENC_Msk                  (0x1UL << RCC_DIVENCR_IC1ENC_Pos)     /*!< 0x00000001 */
31712 #define RCC_DIVENCR_IC1ENC                      RCC_DIVENCR_IC1ENC_Msk               /*!< IC1 enable */
31713 #define RCC_DIVENCR_IC2ENC_Pos                  (1U)
31714 #define RCC_DIVENCR_IC2ENC_Msk                  (0x1UL << RCC_DIVENCR_IC2ENC_Pos)     /*!< 0x00000002 */
31715 #define RCC_DIVENCR_IC2ENC                      RCC_DIVENCR_IC2ENC_Msk               /*!< IC2 enable */
31716 #define RCC_DIVENCR_IC3ENC_Pos                  (2U)
31717 #define RCC_DIVENCR_IC3ENC_Msk                  (0x1UL << RCC_DIVENCR_IC3ENC_Pos)     /*!< 0x00000004 */
31718 #define RCC_DIVENCR_IC3ENC                      RCC_DIVENCR_IC3ENC_Msk               /*!< IC3 enable */
31719 #define RCC_DIVENCR_IC4ENC_Pos                  (3U)
31720 #define RCC_DIVENCR_IC4ENC_Msk                  (0x1UL << RCC_DIVENCR_IC4ENC_Pos)     /*!< 0x00000008 */
31721 #define RCC_DIVENCR_IC4ENC                      RCC_DIVENCR_IC4ENC_Msk               /*!< IC4 enable */
31722 #define RCC_DIVENCR_IC5ENC_Pos                  (4U)
31723 #define RCC_DIVENCR_IC5ENC_Msk                  (0x1UL << RCC_DIVENCR_IC5ENC_Pos)     /*!< 0x00000010 */
31724 #define RCC_DIVENCR_IC5ENC                      RCC_DIVENCR_IC5ENC_Msk               /*!< IC5 enable */
31725 #define RCC_DIVENCR_IC6ENC_Pos                  (5U)
31726 #define RCC_DIVENCR_IC6ENC_Msk                  (0x1UL << RCC_DIVENCR_IC6ENC_Pos)     /*!< 0x00000020 */
31727 #define RCC_DIVENCR_IC6ENC                      RCC_DIVENCR_IC6ENC_Msk               /*!< IC6 enable */
31728 #define RCC_DIVENCR_IC7ENC_Pos                  (6U)
31729 #define RCC_DIVENCR_IC7ENC_Msk                  (0x1UL << RCC_DIVENCR_IC7ENC_Pos)     /*!< 0x00000040 */
31730 #define RCC_DIVENCR_IC7ENC                      RCC_DIVENCR_IC7ENC_Msk               /*!< IC7 enable */
31731 #define RCC_DIVENCR_IC8ENC_Pos                  (7U)
31732 #define RCC_DIVENCR_IC8ENC_Msk                  (0x1UL << RCC_DIVENCR_IC8ENC_Pos)     /*!< 0x00000080 */
31733 #define RCC_DIVENCR_IC8ENC                      RCC_DIVENCR_IC8ENC_Msk               /*!< IC8 enable */
31734 #define RCC_DIVENCR_IC9ENC_Pos                  (8U)
31735 #define RCC_DIVENCR_IC9ENC_Msk                  (0x1UL << RCC_DIVENCR_IC9ENC_Pos)     /*!< 0x00000100 */
31736 #define RCC_DIVENCR_IC9ENC                      RCC_DIVENCR_IC9ENC_Msk               /*!< IC9 enable */
31737 #define RCC_DIVENCR_IC10ENC_Pos                 (9U)
31738 #define RCC_DIVENCR_IC10ENC_Msk                 (0x1UL << RCC_DIVENCR_IC10ENC_Pos)    /*!< 0x00000200 */
31739 #define RCC_DIVENCR_IC10ENC                     RCC_DIVENCR_IC10ENC_Msk              /*!< IC10 enable */
31740 #define RCC_DIVENCR_IC11ENC_Pos                 (10U)
31741 #define RCC_DIVENCR_IC11ENC_Msk                 (0x1UL << RCC_DIVENCR_IC11ENC_Pos)    /*!< 0x00000400 */
31742 #define RCC_DIVENCR_IC11ENC                     RCC_DIVENCR_IC11ENC_Msk              /*!< IC11 enable */
31743 #define RCC_DIVENCR_IC12ENC_Pos                 (11U)
31744 #define RCC_DIVENCR_IC12ENC_Msk                 (0x1UL << RCC_DIVENCR_IC12ENC_Pos)    /*!< 0x00000800 */
31745 #define RCC_DIVENCR_IC12ENC                     RCC_DIVENCR_IC12ENC_Msk              /*!< IC12 enable */
31746 #define RCC_DIVENCR_IC13ENC_Pos                 (12U)
31747 #define RCC_DIVENCR_IC13ENC_Msk                 (0x1UL << RCC_DIVENCR_IC13ENC_Pos)    /*!< 0x00001000 */
31748 #define RCC_DIVENCR_IC13ENC                     RCC_DIVENCR_IC13ENC_Msk              /*!< IC13 enable */
31749 #define RCC_DIVENCR_IC14ENC_Pos                 (13U)
31750 #define RCC_DIVENCR_IC14ENC_Msk                 (0x1UL << RCC_DIVENCR_IC14ENC_Pos)    /*!< 0x00002000 */
31751 #define RCC_DIVENCR_IC14ENC                     RCC_DIVENCR_IC14ENC_Msk              /*!< IC14 enable */
31752 #define RCC_DIVENCR_IC15ENC_Pos                 (14U)
31753 #define RCC_DIVENCR_IC15ENC_Msk                 (0x1UL << RCC_DIVENCR_IC15ENC_Pos)    /*!< 0x00004000 */
31754 #define RCC_DIVENCR_IC15ENC                     RCC_DIVENCR_IC15ENC_Msk              /*!< IC15 enable */
31755 #define RCC_DIVENCR_IC16ENC_Pos                 (15U)
31756 #define RCC_DIVENCR_IC16ENC_Msk                 (0x1UL << RCC_DIVENCR_IC16ENC_Pos)    /*!< 0x00008000 */
31757 #define RCC_DIVENCR_IC16ENC                     RCC_DIVENCR_IC16ENC_Msk              /*!< IC16 enable */
31758 #define RCC_DIVENCR_IC17ENC_Pos                 (16U)
31759 #define RCC_DIVENCR_IC17ENC_Msk                 (0x1UL << RCC_DIVENCR_IC17ENC_Pos)    /*!< 0x00010000 */
31760 #define RCC_DIVENCR_IC17ENC                     RCC_DIVENCR_IC17ENC_Msk              /*!< IC17 enable */
31761 #define RCC_DIVENCR_IC18ENC_Pos                 (17U)
31762 #define RCC_DIVENCR_IC18ENC_Msk                 (0x1UL << RCC_DIVENCR_IC18ENC_Pos)    /*!< 0x00020000 */
31763 #define RCC_DIVENCR_IC18ENC                     RCC_DIVENCR_IC18ENC_Msk              /*!< IC18 enable */
31764 #define RCC_DIVENCR_IC19ENC_Pos                 (18U)
31765 #define RCC_DIVENCR_IC19ENC_Msk                 (0x1UL << RCC_DIVENCR_IC19ENC_Pos)    /*!< 0x00040000 */
31766 #define RCC_DIVENCR_IC19ENC                     RCC_DIVENCR_IC19ENC_Msk              /*!< IC19 enable */
31767 #define RCC_DIVENCR_IC20ENC_Pos                 (19U)
31768 #define RCC_DIVENCR_IC20ENC_Msk                 (0x1UL << RCC_DIVENCR_IC20ENC_Pos)    /*!< 0x00080000 */
31769 #define RCC_DIVENCR_IC20ENC                     RCC_DIVENCR_IC20ENC_Msk              /*!< IC20 enable */
31770 
31771 /*****************  Bit definition for RCC_BUSENCR register  ******************/
31772 #define RCC_BUSENCR_ACLKNENC_Pos                (0U)
31773 #define RCC_BUSENCR_ACLKNENC_Msk                (0x1UL << RCC_BUSENCR_ACLKNENC_Pos)   /*!< 0x00000001 */
31774 #define RCC_BUSENCR_ACLKNENC                    RCC_BUSENCR_ACLKNENC_Msk             /*!< ACLKN enable */
31775 #define RCC_BUSENCR_ACLKNCENC_Pos               (1U)
31776 #define RCC_BUSENCR_ACLKNCENC_Msk               (0x1UL << RCC_BUSENCR_ACLKNCENC_Pos)  /*!< 0x00000002 */
31777 #define RCC_BUSENCR_ACLKNCENC                   RCC_BUSENCR_ACLKNCENC_Msk            /*!< ACLKNC enable */
31778 #define RCC_BUSENCR_AHBMENC_Pos                 (2U)
31779 #define RCC_BUSENCR_AHBMENC_Msk                 (0x1UL << RCC_BUSENCR_AHBMENC_Pos)    /*!< 0x00000004 */
31780 #define RCC_BUSENCR_AHBMENC                     RCC_BUSENCR_AHBMENC_Msk              /*!< AHBM enable */
31781 #define RCC_BUSENCR_AHB1ENC_Pos                 (3U)
31782 #define RCC_BUSENCR_AHB1ENC_Msk                 (0x1UL << RCC_BUSENCR_AHB1ENC_Pos)    /*!< 0x00000008 */
31783 #define RCC_BUSENCR_AHB1ENC                     RCC_BUSENCR_AHB1ENC_Msk              /*!< AHB1 enable */
31784 #define RCC_BUSENCR_AHB2ENC_Pos                 (4U)
31785 #define RCC_BUSENCR_AHB2ENC_Msk                 (0x1UL << RCC_BUSENCR_AHB2ENC_Pos)    /*!< 0x00000010 */
31786 #define RCC_BUSENCR_AHB2ENC                     RCC_BUSENCR_AHB2ENC_Msk              /*!< AHB2 enable */
31787 #define RCC_BUSENCR_AHB3ENC_Pos                 (5U)
31788 #define RCC_BUSENCR_AHB3ENC_Msk                 (0x1UL << RCC_BUSENCR_AHB3ENC_Pos)    /*!< 0x00000020 */
31789 #define RCC_BUSENCR_AHB3ENC                     RCC_BUSENCR_AHB3ENC_Msk              /*!< AHB3 enable */
31790 #define RCC_BUSENCR_AHB4ENC_Pos                 (6U)
31791 #define RCC_BUSENCR_AHB4ENC_Msk                 (0x1UL << RCC_BUSENCR_AHB4ENC_Pos)    /*!< 0x00000040 */
31792 #define RCC_BUSENCR_AHB4ENC                     RCC_BUSENCR_AHB4ENC_Msk              /*!< AHB4 enable */
31793 #define RCC_BUSENCR_AHB5ENC_Pos                 (7U)
31794 #define RCC_BUSENCR_AHB5ENC_Msk                 (0x1UL << RCC_BUSENCR_AHB5ENC_Pos)    /*!< 0x00000080 */
31795 #define RCC_BUSENCR_AHB5ENC                     RCC_BUSENCR_AHB5ENC_Msk              /*!< AHB5 enable */
31796 #define RCC_BUSENCR_APB1ENC_Pos                 (8U)
31797 #define RCC_BUSENCR_APB1ENC_Msk                 (0x1UL << RCC_BUSENCR_APB1ENC_Pos)    /*!< 0x00000100 */
31798 #define RCC_BUSENCR_APB1ENC                     RCC_BUSENCR_APB1ENC_Msk              /*!< APB1 enable */
31799 #define RCC_BUSENCR_APB2ENC_Pos                 (9U)
31800 #define RCC_BUSENCR_APB2ENC_Msk                 (0x1UL << RCC_BUSENCR_APB2ENC_Pos)    /*!< 0x00000200 */
31801 #define RCC_BUSENCR_APB2ENC                     RCC_BUSENCR_APB2ENC_Msk              /*!< APB2 enable */
31802 #define RCC_BUSENCR_APB3ENC_Pos                 (10U)
31803 #define RCC_BUSENCR_APB3ENC_Msk                 (0x1UL << RCC_BUSENCR_APB3ENC_Pos)    /*!< 0x00000400 */
31804 #define RCC_BUSENCR_APB3ENC                     RCC_BUSENCR_APB3ENC_Msk              /*!< APB3 enable */
31805 #define RCC_BUSENCR_APB4ENC_Pos                 (11U)
31806 #define RCC_BUSENCR_APB4ENC_Msk                 (0x1UL << RCC_BUSENCR_APB4ENC_Pos)    /*!< 0x00000800 */
31807 #define RCC_BUSENCR_APB4ENC                     RCC_BUSENCR_APB4ENC_Msk              /*!< APB4 enable */
31808 #define RCC_BUSENCR_APB5ENC_Pos                 (12U)
31809 #define RCC_BUSENCR_APB5ENC_Msk                 (0x1UL << RCC_BUSENCR_APB5ENC_Pos)    /*!< 0x00001000 */
31810 #define RCC_BUSENCR_APB5ENC                     RCC_BUSENCR_APB5ENC_Msk              /*!< APB5 enable */
31811 
31812 /*****************  Bit definition for RCC_MISCENCR register  *****************/
31813 #define RCC_MISCENCR_DBGENC_Pos                 (0U)
31814 #define RCC_MISCENCR_DBGENC_Msk                 (0x1UL << RCC_MISCENCR_DBGENC_Pos)    /*!< 0x00000001 */
31815 #define RCC_MISCENCR_DBGENC                     RCC_MISCENCR_DBGENC_Msk              /*!< DBG enable */
31816 #define RCC_MISCENCR_MCO1ENC_Pos                (1U)
31817 #define RCC_MISCENCR_MCO1ENC_Msk                (0x1UL << RCC_MISCENCR_MCO1ENC_Pos)   /*!< 0x00000002 */
31818 #define RCC_MISCENCR_MCO1ENC                    RCC_MISCENCR_MCO1ENC_Msk             /*!< MCO1 enable */
31819 #define RCC_MISCENCR_MCO2ENC_Pos                (2U)
31820 #define RCC_MISCENCR_MCO2ENC_Msk                (0x1UL << RCC_MISCENCR_MCO2ENC_Pos)   /*!< 0x00000004 */
31821 #define RCC_MISCENCR_MCO2ENC                    RCC_MISCENCR_MCO2ENC_Msk             /*!< MCO2 enable */
31822 #define RCC_MISCENCR_XSPIPHYCOMPENC_Pos         (3U)
31823 #define RCC_MISCENCR_XSPIPHYCOMPENC_Msk         (0x1UL << RCC_MISCENCR_XSPIPHYCOMPENC_Pos)    /*!< 0x00000008 */
31824 #define RCC_MISCENCR_XSPIPHYCOMPENC             RCC_MISCENCR_XSPIPHYCOMPENC_Msk      /*!< XSPIPHYCOMP enable */
31825 #define RCC_MISCENCR_PERENC_Pos                 (6U)
31826 #define RCC_MISCENCR_PERENC_Msk                 (0x1UL << RCC_MISCENCR_PERENC_Pos)    /*!< 0x00000040 */
31827 #define RCC_MISCENCR_PERENC                     RCC_MISCENCR_PERENC_Msk              /*!< PER enable */
31828 
31829 /*****************  Bit definition for RCC_MEMENCR register  ******************/
31830 #define RCC_MEMENCR_AXISRAM3ENC_Pos             (0U)
31831 #define RCC_MEMENCR_AXISRAM3ENC_Msk             (0x1UL << RCC_MEMENCR_AXISRAM3ENC_Pos)/*!< 0x00000001 */
31832 #define RCC_MEMENCR_AXISRAM3ENC                 RCC_MEMENCR_AXISRAM3ENC_Msk          /*!< AXISRAM3 enable */
31833 #define RCC_MEMENCR_AXISRAM4ENC_Pos             (1U)
31834 #define RCC_MEMENCR_AXISRAM4ENC_Msk             (0x1UL << RCC_MEMENCR_AXISRAM4ENC_Pos)/*!< 0x00000002 */
31835 #define RCC_MEMENCR_AXISRAM4ENC                 RCC_MEMENCR_AXISRAM4ENC_Msk          /*!< AXISRAM4 enable */
31836 #define RCC_MEMENCR_AXISRAM5ENC_Pos             (2U)
31837 #define RCC_MEMENCR_AXISRAM5ENC_Msk             (0x1UL << RCC_MEMENCR_AXISRAM5ENC_Pos)/*!< 0x00000004 */
31838 #define RCC_MEMENCR_AXISRAM5ENC                 RCC_MEMENCR_AXISRAM5ENC_Msk          /*!< AXISRAM5 enable */
31839 #define RCC_MEMENCR_AXISRAM6ENC_Pos             (3U)
31840 #define RCC_MEMENCR_AXISRAM6ENC_Msk             (0x1UL << RCC_MEMENCR_AXISRAM6ENC_Pos)/*!< 0x00000008 */
31841 #define RCC_MEMENCR_AXISRAM6ENC                 RCC_MEMENCR_AXISRAM6ENC_Msk          /*!< AXISRAM6 enable */
31842 #define RCC_MEMENCR_AHBSRAM1ENC_Pos             (4U)
31843 #define RCC_MEMENCR_AHBSRAM1ENC_Msk             (0x1UL << RCC_MEMENCR_AHBSRAM1ENC_Pos)/*!< 0x00000010 */
31844 #define RCC_MEMENCR_AHBSRAM1ENC                 RCC_MEMENCR_AHBSRAM1ENC_Msk          /*!< AHBSRAM1 enable */
31845 #define RCC_MEMENCR_AHBSRAM2ENC_Pos             (5U)
31846 #define RCC_MEMENCR_AHBSRAM2ENC_Msk             (0x1UL << RCC_MEMENCR_AHBSRAM2ENC_Pos)/*!< 0x00000020 */
31847 #define RCC_MEMENCR_AHBSRAM2ENC                 RCC_MEMENCR_AHBSRAM2ENC_Msk          /*!< AHBSRAM2 enable */
31848 #define RCC_MEMENCR_BKPSRAMENC_Pos              (6U)
31849 #define RCC_MEMENCR_BKPSRAMENC_Msk              (0x1UL << RCC_MEMENCR_BKPSRAMENC_Pos) /*!< 0x00000040 */
31850 #define RCC_MEMENCR_BKPSRAMENC                  RCC_MEMENCR_BKPSRAMENC_Msk           /*!< BKPSRAM enable */
31851 #define RCC_MEMENCR_AXISRAM1ENC_Pos             (7U)
31852 #define RCC_MEMENCR_AXISRAM1ENC_Msk             (0x1UL << RCC_MEMENCR_AXISRAM1ENC_Pos)/*!< 0x00000080 */
31853 #define RCC_MEMENCR_AXISRAM1ENC                 RCC_MEMENCR_AXISRAM1ENC_Msk          /*!< AXISRAM1 enable */
31854 #define RCC_MEMENCR_AXISRAM2ENC_Pos             (8U)
31855 #define RCC_MEMENCR_AXISRAM2ENC_Msk             (0x1UL << RCC_MEMENCR_AXISRAM2ENC_Pos)/*!< 0x00000100 */
31856 #define RCC_MEMENCR_AXISRAM2ENC                 RCC_MEMENCR_AXISRAM2ENC_Msk          /*!< AXISRAM2 enable */
31857 #define RCC_MEMENCR_FLEXRAMENC_Pos              (9U)
31858 #define RCC_MEMENCR_FLEXRAMENC_Msk              (0x1UL << RCC_MEMENCR_FLEXRAMENC_Pos) /*!< 0x00000200 */
31859 #define RCC_MEMENCR_FLEXRAMENC                  RCC_MEMENCR_FLEXRAMENC_Msk           /*!< FLEXRAM enable */
31860 #define RCC_MEMENCR_CACHEAXIRAMENC_Pos          (10U)
31861 #define RCC_MEMENCR_CACHEAXIRAMENC_Msk          (0x1UL << RCC_MEMENCR_CACHEAXIRAMENC_Pos)   /*!< 0x00000400 */
31862 #define RCC_MEMENCR_CACHEAXIRAMENC              RCC_MEMENCR_CACHEAXIRAMENC_Msk       /*!< CACHEAXIRAM enable */
31863 #define RCC_MEMENCR_VENCRAMENC_Pos              (11U)
31864 #define RCC_MEMENCR_VENCRAMENC_Msk              (0x1UL << RCC_MEMENCR_VENCRAMENC_Pos) /*!< 0x00000800 */
31865 #define RCC_MEMENCR_VENCRAMENC                  RCC_MEMENCR_VENCRAMENC_Msk           /*!< VENCRAM enable */
31866 #define RCC_MEMENCR_BOOTROMENC_Pos              (12U)
31867 #define RCC_MEMENCR_BOOTROMENC_Msk              (0x1UL << RCC_MEMENCR_BOOTROMENC_Pos) /*!< 0x00001000 */
31868 #define RCC_MEMENCR_BOOTROMENC                  RCC_MEMENCR_BOOTROMENC_Msk           /*!< Boot ROM enable */
31869 
31870 /*****************  Bit definition for RCC_AHB1ENCR register  *****************/
31871 #define RCC_AHB1ENCR_GPDMA1ENC_Pos              (4U)
31872 #define RCC_AHB1ENCR_GPDMA1ENC_Msk              (0x1UL << RCC_AHB1ENCR_GPDMA1ENC_Pos) /*!< 0x00000010 */
31873 #define RCC_AHB1ENCR_GPDMA1ENC                  RCC_AHB1ENCR_GPDMA1ENC_Msk           /*!< GPDMA1 enable */
31874 #define RCC_AHB1ENCR_ADC12ENC_Pos               (5U)
31875 #define RCC_AHB1ENCR_ADC12ENC_Msk               (0x1UL << RCC_AHB1ENCR_ADC12ENC_Pos)  /*!< 0x00000020 */
31876 #define RCC_AHB1ENCR_ADC12ENC                   RCC_AHB1ENCR_ADC12ENC_Msk            /*!< ADC12 enable */
31877 
31878 /*****************  Bit definition for RCC_AHB2ENCR register  *****************/
31879 #define RCC_AHB2ENCR_RAMCFGENC_Pos              (12U)
31880 #define RCC_AHB2ENCR_RAMCFGENC_Msk              (0x1UL << RCC_AHB2ENCR_RAMCFGENC_Pos) /*!< 0x00001000 */
31881 #define RCC_AHB2ENCR_RAMCFGENC                  RCC_AHB2ENCR_RAMCFGENC_Msk           /*!< RAMCFG enable */
31882 #define RCC_AHB2ENCR_MDF1ENC_Pos                (16U)
31883 #define RCC_AHB2ENCR_MDF1ENC_Msk                (0x1UL << RCC_AHB2ENCR_MDF1ENC_Pos)   /*!< 0x00010000 */
31884 #define RCC_AHB2ENCR_MDF1ENC                    RCC_AHB2ENCR_MDF1ENC_Msk             /*!< MDF1 enable */
31885 #define RCC_AHB2ENCR_ADF1ENC_Pos                (17U)
31886 #define RCC_AHB2ENCR_ADF1ENC_Msk                (0x1UL << RCC_AHB2ENCR_ADF1ENC_Pos)   /*!< 0x00020000 */
31887 #define RCC_AHB2ENCR_ADF1ENC                    RCC_AHB2ENCR_ADF1ENC_Msk             /*!< ADF1 enable */
31888 
31889 /*****************  Bit definition for RCC_AHB3ENCR register  *****************/
31890 #define RCC_AHB3ENCR_RNGENC_Pos                 (0U)
31891 #define RCC_AHB3ENCR_RNGENC_Msk                 (0x1UL << RCC_AHB3ENCR_RNGENC_Pos)    /*!< 0x00000001 */
31892 #define RCC_AHB3ENCR_RNGENC                     RCC_AHB3ENCR_RNGENC_Msk              /*!< RNG enable */
31893 #define RCC_AHB3ENCR_HASHENC_Pos                (1U)
31894 #define RCC_AHB3ENCR_HASHENC_Msk                (0x1UL << RCC_AHB3ENCR_HASHENC_Pos)   /*!< 0x00000002 */
31895 #define RCC_AHB3ENCR_HASHENC                    RCC_AHB3ENCR_HASHENC_Msk             /*!< HASH enable */
31896 #define RCC_AHB3ENCR_CRYPENC_Pos                (2U)
31897 #define RCC_AHB3ENCR_CRYPENC_Msk                (0x1UL << RCC_AHB3ENCR_CRYPENC_Pos)   /*!< 0x00000004 */
31898 #define RCC_AHB3ENCR_CRYPENC                    RCC_AHB3ENCR_CRYPENC_Msk             /*!< CRYP enable */
31899 #define RCC_AHB3ENCR_SAESENC_Pos                (4U)
31900 #define RCC_AHB3ENCR_SAESENC_Msk                (0x1UL << RCC_AHB3ENCR_SAESENC_Pos)   /*!< 0x00000010 */
31901 #define RCC_AHB3ENCR_SAESENC                    RCC_AHB3ENCR_SAESENC_Msk             /*!< SAES enable */
31902 #define RCC_AHB3ENCR_PKAENC_Pos                 (8U)
31903 #define RCC_AHB3ENCR_PKAENC_Msk                 (0x1UL << RCC_AHB3ENCR_PKAENC_Pos)    /*!< 0x00000100 */
31904 #define RCC_AHB3ENCR_PKAENC                     RCC_AHB3ENCR_PKAENC_Msk              /*!< PKA enable */
31905 #define RCC_AHB3ENCR_RIFSCENC_Pos               (9U)
31906 #define RCC_AHB3ENCR_RIFSCENC_Msk               (0x1UL << RCC_AHB3ENCR_RIFSCENC_Pos)  /*!< 0x00000200 */
31907 #define RCC_AHB3ENCR_RIFSCENC                   RCC_AHB3ENCR_RIFSCENC_Msk            /*!< RIFSC enable */
31908 #define RCC_AHB3ENCR_IACENC_Pos                 (10U)
31909 #define RCC_AHB3ENCR_IACENC_Msk                 (0x1UL << RCC_AHB3ENCR_IACENC_Pos)    /*!< 0x00000400 */
31910 #define RCC_AHB3ENCR_IACENC                     RCC_AHB3ENCR_IACENC_Msk              /*!< IAC enable */
31911 #define RCC_AHB3ENCR_RISAFENC_Pos               (14U)
31912 #define RCC_AHB3ENCR_RISAFENC_Msk               (0x1UL << RCC_AHB3ENCR_RISAFENC_Pos)  /*!< 0x00004000 */
31913 #define RCC_AHB3ENCR_RISAFENC                   RCC_AHB3ENCR_RISAFENC_Msk            /*!< RISAF enable */
31914 
31915 /*****************  Bit definition for RCC_AHB4ENCR register  *****************/
31916 #define RCC_AHB4ENCR_GPIOAENC_Pos               (0U)
31917 #define RCC_AHB4ENCR_GPIOAENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOAENC_Pos)  /*!< 0x00000001 */
31918 #define RCC_AHB4ENCR_GPIOAENC                   RCC_AHB4ENCR_GPIOAENC_Msk            /*!< GPIO A enable */
31919 #define RCC_AHB4ENCR_GPIOBENC_Pos               (1U)
31920 #define RCC_AHB4ENCR_GPIOBENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOBENC_Pos)  /*!< 0x00000002 */
31921 #define RCC_AHB4ENCR_GPIOBENC                   RCC_AHB4ENCR_GPIOBENC_Msk            /*!< GPIO B enable */
31922 #define RCC_AHB4ENCR_GPIOCENC_Pos               (2U)
31923 #define RCC_AHB4ENCR_GPIOCENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOCENC_Pos)  /*!< 0x00000004 */
31924 #define RCC_AHB4ENCR_GPIOCENC                   RCC_AHB4ENCR_GPIOCENC_Msk            /*!< GPIO C enable */
31925 #define RCC_AHB4ENCR_GPIODENC_Pos               (3U)
31926 #define RCC_AHB4ENCR_GPIODENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIODENC_Pos)  /*!< 0x00000008 */
31927 #define RCC_AHB4ENCR_GPIODENC                   RCC_AHB4ENCR_GPIODENC_Msk            /*!< GPIO D enable */
31928 #define RCC_AHB4ENCR_GPIOEENC_Pos               (4U)
31929 #define RCC_AHB4ENCR_GPIOEENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOEENC_Pos)  /*!< 0x00000010 */
31930 #define RCC_AHB4ENCR_GPIOEENC                   RCC_AHB4ENCR_GPIOEENC_Msk            /*!< GPIO E enable */
31931 #define RCC_AHB4ENCR_GPIOFENC_Pos               (5U)
31932 #define RCC_AHB4ENCR_GPIOFENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOFENC_Pos)  /*!< 0x00000020 */
31933 #define RCC_AHB4ENCR_GPIOFENC                   RCC_AHB4ENCR_GPIOFENC_Msk            /*!< GPIO F enable */
31934 #define RCC_AHB4ENCR_GPIOGENC_Pos               (6U)
31935 #define RCC_AHB4ENCR_GPIOGENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOGENC_Pos)  /*!< 0x00000040 */
31936 #define RCC_AHB4ENCR_GPIOGENC                   RCC_AHB4ENCR_GPIOGENC_Msk            /*!< GPIO G enable */
31937 #define RCC_AHB4ENCR_GPIOHENC_Pos               (7U)
31938 #define RCC_AHB4ENCR_GPIOHENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOHENC_Pos)  /*!< 0x00000080 */
31939 #define RCC_AHB4ENCR_GPIOHENC                   RCC_AHB4ENCR_GPIOHENC_Msk            /*!< GPIO H enable */
31940 #define RCC_AHB4ENCR_GPIONENC_Pos               (13U)
31941 #define RCC_AHB4ENCR_GPIONENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIONENC_Pos)  /*!< 0x00002000 */
31942 #define RCC_AHB4ENCR_GPIONENC                   RCC_AHB4ENCR_GPIONENC_Msk            /*!< GPIO N enable */
31943 #define RCC_AHB4ENCR_GPIOOENC_Pos               (14U)
31944 #define RCC_AHB4ENCR_GPIOOENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOOENC_Pos)  /*!< 0x00004000 */
31945 #define RCC_AHB4ENCR_GPIOOENC                   RCC_AHB4ENCR_GPIOOENC_Msk            /*!< GPIO O enable */
31946 #define RCC_AHB4ENCR_GPIOPENC_Pos               (15U)
31947 #define RCC_AHB4ENCR_GPIOPENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOPENC_Pos)  /*!< 0x00008000 */
31948 #define RCC_AHB4ENCR_GPIOPENC                   RCC_AHB4ENCR_GPIOPENC_Msk            /*!< GPIO P enable */
31949 #define RCC_AHB4ENCR_GPIOQENC_Pos               (16U)
31950 #define RCC_AHB4ENCR_GPIOQENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOQENC_Pos)  /*!< 0x00010000 */
31951 #define RCC_AHB4ENCR_GPIOQENC                   RCC_AHB4ENCR_GPIOQENC_Msk            /*!< GPIO Q enable */
31952 #define RCC_AHB4ENCR_PWRENC_Pos                 (18U)
31953 #define RCC_AHB4ENCR_PWRENC_Msk                 (0x1UL << RCC_AHB4ENCR_PWRENC_Pos)    /*!< 0x00040000 */
31954 #define RCC_AHB4ENCR_PWRENC                     RCC_AHB4ENCR_PWRENC_Msk              /*!< PWR enable */
31955 #define RCC_AHB4ENCR_CRCENC_Pos                 (19U)
31956 #define RCC_AHB4ENCR_CRCENC_Msk                 (0x1UL << RCC_AHB4ENCR_CRCENC_Pos)    /*!< 0x00080000 */
31957 #define RCC_AHB4ENCR_CRCENC                     RCC_AHB4ENCR_CRCENC_Msk              /*!< CRC enable */
31958 
31959 /*****************  Bit definition for RCC_AHB5ENCR register  *****************/
31960 #define RCC_AHB5ENCR_HPDMA1ENC_Pos              (0U)
31961 #define RCC_AHB5ENCR_HPDMA1ENC_Msk              (0x1UL << RCC_AHB5ENCR_HPDMA1ENC_Pos) /*!< 0x00000001 */
31962 #define RCC_AHB5ENCR_HPDMA1ENC                  RCC_AHB5ENCR_HPDMA1ENC_Msk           /*!< HPDMA1 enable */
31963 #define RCC_AHB5ENCR_DMA2DENC_Pos               (1U)
31964 #define RCC_AHB5ENCR_DMA2DENC_Msk               (0x1UL << RCC_AHB5ENCR_DMA2DENC_Pos)  /*!< 0x00000002 */
31965 #define RCC_AHB5ENCR_DMA2DENC                   RCC_AHB5ENCR_DMA2DENC_Msk            /*!< DMA2D enable */
31966 #define RCC_AHB5ENCR_JPEGENC_Pos                (3U)
31967 #define RCC_AHB5ENCR_JPEGENC_Msk                (0x1UL << RCC_AHB5ENCR_JPEGENC_Pos)   /*!< 0x00000008 */
31968 #define RCC_AHB5ENCR_JPEGENC                    RCC_AHB5ENCR_JPEGENC_Msk             /*!< JPEG enable */
31969 #define RCC_AHB5ENCR_FMCENC_Pos                 (4U)
31970 #define RCC_AHB5ENCR_FMCENC_Msk                 (0x1UL << RCC_AHB5ENCR_FMCENC_Pos)    /*!< 0x00000010 */
31971 #define RCC_AHB5ENCR_FMCENC                     RCC_AHB5ENCR_FMCENC_Msk              /*!< FMC enable */
31972 #define RCC_AHB5ENCR_XSPI1ENC_Pos               (5U)
31973 #define RCC_AHB5ENCR_XSPI1ENC_Msk               (0x1UL << RCC_AHB5ENCR_XSPI1ENC_Pos)  /*!< 0x00000020 */
31974 #define RCC_AHB5ENCR_XSPI1ENC                   RCC_AHB5ENCR_XSPI1ENC_Msk            /*!< XSPI1 enable */
31975 #define RCC_AHB5ENCR_PSSIENC_Pos                (6U)
31976 #define RCC_AHB5ENCR_PSSIENC_Msk                (0x1UL << RCC_AHB5ENCR_PSSIENC_Pos)   /*!< 0x00000040 */
31977 #define RCC_AHB5ENCR_PSSIENC                    RCC_AHB5ENCR_PSSIENC_Msk             /*!< PSSI enable */
31978 #define RCC_AHB5ENCR_SDMMC2ENC_Pos              (7U)
31979 #define RCC_AHB5ENCR_SDMMC2ENC_Msk              (0x1UL << RCC_AHB5ENCR_SDMMC2ENC_Pos) /*!< 0x00000080 */
31980 #define RCC_AHB5ENCR_SDMMC2ENC                  RCC_AHB5ENCR_SDMMC2ENC_Msk           /*!< SDMMC2 enable */
31981 #define RCC_AHB5ENCR_SDMMC1ENC_Pos              (8U)
31982 #define RCC_AHB5ENCR_SDMMC1ENC_Msk              (0x1UL << RCC_AHB5ENCR_SDMMC1ENC_Pos) /*!< 0x00000100 */
31983 #define RCC_AHB5ENCR_SDMMC1ENC                  RCC_AHB5ENCR_SDMMC1ENC_Msk           /*!< SDMMC1 enable */
31984 #define RCC_AHB5ENCR_XSPI2ENC_Pos               (12U)
31985 #define RCC_AHB5ENCR_XSPI2ENC_Msk               (0x1UL << RCC_AHB5ENCR_XSPI2ENC_Pos)  /*!< 0x00001000 */
31986 #define RCC_AHB5ENCR_XSPI2ENC                   RCC_AHB5ENCR_XSPI2ENC_Msk            /*!< XSPI2 enable */
31987 #define RCC_AHB5ENCR_XSPIMENC_Pos               (13U)
31988 #define RCC_AHB5ENCR_XSPIMENC_Msk               (0x1UL << RCC_AHB5ENCR_XSPIMENC_Pos)  /*!< 0x00002000 */
31989 #define RCC_AHB5ENCR_XSPIMENC                   RCC_AHB5ENCR_XSPIMENC_Msk            /*!< XSPIM enable */
31990 #define RCC_AHB5ENCR_MCE1ENC_Pos                (14U)
31991 #define RCC_AHB5ENCR_MCE1ENC_Msk                (0x1UL << RCC_AHB5ENCR_MCE1ENC_Pos)   /*!< 0x00004000 */
31992 #define RCC_AHB5ENCR_MCE1ENC                    RCC_AHB5ENCR_MCE1ENC_Msk             /*!< MCE1 enable */
31993 #define RCC_AHB5ENCR_MCE2ENC_Pos                (15U)
31994 #define RCC_AHB5ENCR_MCE2ENC_Msk                (0x1UL << RCC_AHB5ENCR_MCE2ENC_Pos)   /*!< 0x00008000 */
31995 #define RCC_AHB5ENCR_MCE2ENC                    RCC_AHB5ENCR_MCE2ENC_Msk             /*!< MCE2 enable */
31996 #define RCC_AHB5ENCR_MCE3ENC_Pos                (16U)
31997 #define RCC_AHB5ENCR_MCE3ENC_Msk                (0x1UL << RCC_AHB5ENCR_MCE3ENC_Pos)   /*!< 0x00010000 */
31998 #define RCC_AHB5ENCR_MCE3ENC                    RCC_AHB5ENCR_MCE3ENC_Msk             /*!< MCE3 enable */
31999 #define RCC_AHB5ENCR_XSPI3ENC_Pos               (17U)
32000 #define RCC_AHB5ENCR_XSPI3ENC_Msk               (0x1UL << RCC_AHB5ENCR_XSPI3ENC_Pos)  /*!< 0x00020000 */
32001 #define RCC_AHB5ENCR_XSPI3ENC                   RCC_AHB5ENCR_XSPI3ENC_Msk            /*!< XSPI3 enable */
32002 #define RCC_AHB5ENCR_MCE4ENC_Pos                (18U)
32003 #define RCC_AHB5ENCR_MCE4ENC_Msk                (0x1UL << RCC_AHB5ENCR_MCE4ENC_Pos)   /*!< 0x00040000 */
32004 #define RCC_AHB5ENCR_MCE4ENC                    RCC_AHB5ENCR_MCE4ENC_Msk             /*!< MCE4 enable */
32005 #define RCC_AHB5ENCR_GFXMMUENC_Pos              (19U)
32006 #define RCC_AHB5ENCR_GFXMMUENC_Msk              (0x1UL << RCC_AHB5ENCR_GFXMMUENC_Pos) /*!< 0x00080000 */
32007 #define RCC_AHB5ENCR_GFXMMUENC                  RCC_AHB5ENCR_GFXMMUENC_Msk           /*!< GFXMMU enable */
32008 #define RCC_AHB5ENCR_GPU2DENC_Pos               (20U)
32009 #define RCC_AHB5ENCR_GPU2DENC_Msk               (0x1UL << RCC_AHB5ENCR_GPU2DENC_Pos)  /*!< 0x00100000 */
32010 #define RCC_AHB5ENCR_GPU2DENC                   RCC_AHB5ENCR_GPU2DENC_Msk            /*!< GPU2D enable */
32011 #define RCC_AHB5ENCR_ETH1MACENC_Pos             (22U)
32012 #define RCC_AHB5ENCR_ETH1MACENC_Msk             (0x1UL << RCC_AHB5ENCR_ETH1MACENC_Pos)/*!< 0x00400000 */
32013 #define RCC_AHB5ENCR_ETH1MACENC                 RCC_AHB5ENCR_ETH1MACENC_Msk          /*!< ETH1MAC enable */
32014 #define RCC_AHB5ENCR_ETH1TXENC_Pos              (23U)
32015 #define RCC_AHB5ENCR_ETH1TXENC_Msk              (0x1UL << RCC_AHB5ENCR_ETH1TXENC_Pos) /*!< 0x00800000 */
32016 #define RCC_AHB5ENCR_ETH1TXENC                  RCC_AHB5ENCR_ETH1TXENC_Msk           /*!< ETH1TX enable */
32017 #define RCC_AHB5ENCR_ETH1RXENC_Pos              (24U)
32018 #define RCC_AHB5ENCR_ETH1RXENC_Msk              (0x1UL << RCC_AHB5ENCR_ETH1RXENC_Pos) /*!< 0x01000000 */
32019 #define RCC_AHB5ENCR_ETH1RXENC                  RCC_AHB5ENCR_ETH1RXENC_Msk           /*!< ETH1RX enable */
32020 #define RCC_AHB5ENCR_ETH1ENC_Pos                (25U)
32021 #define RCC_AHB5ENCR_ETH1ENC_Msk                (0x1UL << RCC_AHB5ENCR_ETH1ENC_Pos)   /*!< 0x02000000 */
32022 #define RCC_AHB5ENCR_ETH1ENC                    RCC_AHB5ENCR_ETH1ENC_Msk             /*!< ETH1 enable */
32023 #define RCC_AHB5ENCR_OTG1ENC_Pos                (26U)
32024 #define RCC_AHB5ENCR_OTG1ENC_Msk                (0x1UL << RCC_AHB5ENCR_OTG1ENC_Pos)   /*!< 0x04000000 */
32025 #define RCC_AHB5ENCR_OTG1ENC                    RCC_AHB5ENCR_OTG1ENC_Msk             /*!< OTG1 enable */
32026 #define RCC_AHB5ENCR_OTGPHY1ENC_Pos             (27U)
32027 #define RCC_AHB5ENCR_OTGPHY1ENC_Msk             (0x1UL << RCC_AHB5ENCR_OTGPHY1ENC_Pos)/*!< 0x08000000 */
32028 #define RCC_AHB5ENCR_OTGPHY1ENC                 RCC_AHB5ENCR_OTGPHY1ENC_Msk          /*!< OTGPHY1 enable */
32029 #define RCC_AHB5ENCR_OTGPHY2ENC_Pos             (28U)
32030 #define RCC_AHB5ENCR_OTGPHY2ENC_Msk             (0x1UL << RCC_AHB5ENCR_OTGPHY2ENC_Pos)/*!< 0x10000000 */
32031 #define RCC_AHB5ENCR_OTGPHY2ENC                 RCC_AHB5ENCR_OTGPHY2ENC_Msk          /*!< OTGPHY2 enable */
32032 #define RCC_AHB5ENCR_OTG2ENC_Pos                (29U)
32033 #define RCC_AHB5ENCR_OTG2ENC_Msk                (0x1UL << RCC_AHB5ENCR_OTG2ENC_Pos)   /*!< 0x20000000 */
32034 #define RCC_AHB5ENCR_OTG2ENC                    RCC_AHB5ENCR_OTG2ENC_Msk             /*!< OTG2 enable */
32035 #define RCC_AHB5ENCR_CACHEAXIENC_Pos            (30U)
32036 #define RCC_AHB5ENCR_CACHEAXIENC_Msk            (0x1UL << RCC_AHB5ENCR_CACHEAXIENC_Pos) /*!< 0x40000000 */
32037 #define RCC_AHB5ENCR_CACHEAXIENC                RCC_AHB5ENCR_CACHEAXIENC_Msk         /*!< CACHEAXI enable */
32038 #define RCC_AHB5ENCR_NPUENC_Pos                 (31U)
32039 #define RCC_AHB5ENCR_NPUENC_Msk                 (0x1UL << RCC_AHB5ENCR_NPUENC_Pos)    /*!< 0x80000000 */
32040 #define RCC_AHB5ENCR_NPUENC                     RCC_AHB5ENCR_NPUENC_Msk              /*!< NPU enable */
32041 
32042 /****************  Bit definition for RCC_APB1ENCR1 register  *****************/
32043 #define RCC_APB1ENCR1_TIM2ENC_Pos               (0U)
32044 #define RCC_APB1ENCR1_TIM2ENC_Msk               (0x1UL << RCC_APB1ENCR1_TIM2ENC_Pos)  /*!< 0x00000001 */
32045 #define RCC_APB1ENCR1_TIM2ENC                   RCC_APB1ENCR1_TIM2ENC_Msk            /*!< TIM2 enable */
32046 #define RCC_APB1ENCR1_TIM3ENC_Pos               (1U)
32047 #define RCC_APB1ENCR1_TIM3ENC_Msk               (0x1UL << RCC_APB1ENCR1_TIM3ENC_Pos)  /*!< 0x00000002 */
32048 #define RCC_APB1ENCR1_TIM3ENC                   RCC_APB1ENCR1_TIM3ENC_Msk            /*!< TIM3 enable */
32049 #define RCC_APB1ENCR1_TIM4ENC_Pos               (2U)
32050 #define RCC_APB1ENCR1_TIM4ENC_Msk               (0x1UL << RCC_APB1ENCR1_TIM4ENC_Pos)  /*!< 0x00000004 */
32051 #define RCC_APB1ENCR1_TIM4ENC                   RCC_APB1ENCR1_TIM4ENC_Msk            /*!< TIM4 enable */
32052 #define RCC_APB1ENCR1_TIM5ENC_Pos               (3U)
32053 #define RCC_APB1ENCR1_TIM5ENC_Msk               (0x1UL << RCC_APB1ENCR1_TIM5ENC_Pos)  /*!< 0x00000008 */
32054 #define RCC_APB1ENCR1_TIM5ENC                   RCC_APB1ENCR1_TIM5ENC_Msk            /*!< TIM5 enable */
32055 #define RCC_APB1ENCR1_TIM6ENC_Pos               (4U)
32056 #define RCC_APB1ENCR1_TIM6ENC_Msk               (0x1UL << RCC_APB1ENCR1_TIM6ENC_Pos)  /*!< 0x00000010 */
32057 #define RCC_APB1ENCR1_TIM6ENC                   RCC_APB1ENCR1_TIM6ENC_Msk            /*!< TIM6 enable */
32058 #define RCC_APB1ENCR1_TIM7ENC_Pos               (5U)
32059 #define RCC_APB1ENCR1_TIM7ENC_Msk               (0x1UL << RCC_APB1ENCR1_TIM7ENC_Pos)  /*!< 0x00000020 */
32060 #define RCC_APB1ENCR1_TIM7ENC                   RCC_APB1ENCR1_TIM7ENC_Msk            /*!< TIM7 enable */
32061 #define RCC_APB1ENCR1_TIM12ENC_Pos              (6U)
32062 #define RCC_APB1ENCR1_TIM12ENC_Msk              (0x1UL << RCC_APB1ENCR1_TIM12ENC_Pos) /*!< 0x00000040 */
32063 #define RCC_APB1ENCR1_TIM12ENC                  RCC_APB1ENCR1_TIM12ENC_Msk           /*!< TIM12 enable */
32064 #define RCC_APB1ENCR1_TIM13ENC_Pos              (7U)
32065 #define RCC_APB1ENCR1_TIM13ENC_Msk              (0x1UL << RCC_APB1ENCR1_TIM13ENC_Pos) /*!< 0x00000080 */
32066 #define RCC_APB1ENCR1_TIM13ENC                  RCC_APB1ENCR1_TIM13ENC_Msk           /*!< TIM13 enable */
32067 #define RCC_APB1ENCR1_TIM14ENC_Pos              (8U)
32068 #define RCC_APB1ENCR1_TIM14ENC_Msk              (0x1UL << RCC_APB1ENCR1_TIM14ENC_Pos) /*!< 0x00000100 */
32069 #define RCC_APB1ENCR1_TIM14ENC                  RCC_APB1ENCR1_TIM14ENC_Msk           /*!< TIM14 enable */
32070 #define RCC_APB1ENCR1_LPTIM1ENC_Pos             (9U)
32071 #define RCC_APB1ENCR1_LPTIM1ENC_Msk             (0x1UL << RCC_APB1ENCR1_LPTIM1ENC_Pos)/*!< 0x00000200 */
32072 #define RCC_APB1ENCR1_LPTIM1ENC                 RCC_APB1ENCR1_LPTIM1ENC_Msk          /*!< LPTIM1 enable */
32073 #define RCC_APB1ENCR1_TIM10ENC_Pos              (12U)
32074 #define RCC_APB1ENCR1_TIM10ENC_Msk              (0x1UL << RCC_APB1ENCR1_TIM10ENC_Pos) /*!< 0x00001000 */
32075 #define RCC_APB1ENCR1_TIM10ENC                  RCC_APB1ENCR1_TIM10ENC_Msk           /*!< TIM10 enable */
32076 #define RCC_APB1ENCR1_TIM11ENC_Pos              (13U)
32077 #define RCC_APB1ENCR1_TIM11ENC_Msk              (0x1UL << RCC_APB1ENCR1_TIM11ENC_Pos) /*!< 0x00002000 */
32078 #define RCC_APB1ENCR1_TIM11ENC                  RCC_APB1ENCR1_TIM11ENC_Msk           /*!< TIM11 enable */
32079 #define RCC_APB1ENCR1_SPI2ENC_Pos               (14U)
32080 #define RCC_APB1ENCR1_SPI2ENC_Msk               (0x1UL << RCC_APB1ENCR1_SPI2ENC_Pos)  /*!< 0x00004000 */
32081 #define RCC_APB1ENCR1_SPI2ENC                   RCC_APB1ENCR1_SPI2ENC_Msk            /*!< SPI2 enable */
32082 #define RCC_APB1ENCR1_SPI3ENC_Pos               (15U)
32083 #define RCC_APB1ENCR1_SPI3ENC_Msk               (0x1UL << RCC_APB1ENCR1_SPI3ENC_Pos)  /*!< 0x00008000 */
32084 #define RCC_APB1ENCR1_SPI3ENC                   RCC_APB1ENCR1_SPI3ENC_Msk            /*!< SPI3 enable */
32085 #define RCC_APB1ENCR1_SPDIFRX1ENC_Pos           (16U)
32086 #define RCC_APB1ENCR1_SPDIFRX1ENC_Msk           (0x1UL << RCC_APB1ENCR1_SPDIFRX1ENC_Pos)  /*!< 0x00010000 */
32087 #define RCC_APB1ENCR1_SPDIFRX1ENC               RCC_APB1ENCR1_SPDIFRX1ENC_Msk        /*!< SPDIFRX1 enable */
32088 #define RCC_APB1ENCR1_USART2ENC_Pos             (17U)
32089 #define RCC_APB1ENCR1_USART2ENC_Msk             (0x1UL << RCC_APB1ENCR1_USART2ENC_Pos)/*!< 0x00020000 */
32090 #define RCC_APB1ENCR1_USART2ENC                 RCC_APB1ENCR1_USART2ENC_Msk          /*!< USART2 enable */
32091 #define RCC_APB1ENCR1_USART3ENC_Pos             (18U)
32092 #define RCC_APB1ENCR1_USART3ENC_Msk             (0x1UL << RCC_APB1ENCR1_USART3ENC_Pos)/*!< 0x00040000 */
32093 #define RCC_APB1ENCR1_USART3ENC                 RCC_APB1ENCR1_USART3ENC_Msk          /*!< USART3 enable */
32094 #define RCC_APB1ENCR1_UART4ENC_Pos              (19U)
32095 #define RCC_APB1ENCR1_UART4ENC_Msk              (0x1UL << RCC_APB1ENCR1_UART4ENC_Pos) /*!< 0x00080000 */
32096 #define RCC_APB1ENCR1_UART4ENC                  RCC_APB1ENCR1_UART4ENC_Msk           /*!< UART4 enable */
32097 #define RCC_APB1ENCR1_UART5ENC_Pos              (20U)
32098 #define RCC_APB1ENCR1_UART5ENC_Msk              (0x1UL << RCC_APB1ENCR1_UART5ENC_Pos) /*!< 0x00100000 */
32099 #define RCC_APB1ENCR1_UART5ENC                  RCC_APB1ENCR1_UART5ENC_Msk           /*!< UART5 enable */
32100 #define RCC_APB1ENCR1_I2C1ENC_Pos               (21U)
32101 #define RCC_APB1ENCR1_I2C1ENC_Msk               (0x1UL << RCC_APB1ENCR1_I2C1ENC_Pos)  /*!< 0x00200000 */
32102 #define RCC_APB1ENCR1_I2C1ENC                   RCC_APB1ENCR1_I2C1ENC_Msk            /*!< I2C1 enable */
32103 #define RCC_APB1ENCR1_I2C2ENC_Pos               (22U)
32104 #define RCC_APB1ENCR1_I2C2ENC_Msk               (0x1UL << RCC_APB1ENCR1_I2C2ENC_Pos)  /*!< 0x00400000 */
32105 #define RCC_APB1ENCR1_I2C2ENC                   RCC_APB1ENCR1_I2C2ENC_Msk            /*!< I2C2 enable */
32106 #define RCC_APB1ENCR1_I2C3ENC_Pos               (23U)
32107 #define RCC_APB1ENCR1_I2C3ENC_Msk               (0x1UL << RCC_APB1ENCR1_I2C3ENC_Pos)  /*!< 0x00800000 */
32108 #define RCC_APB1ENCR1_I2C3ENC                   RCC_APB1ENCR1_I2C3ENC_Msk            /*!< I2C3 enable */
32109 #define RCC_APB1ENCR1_I3C1ENC_Pos               (24U)
32110 #define RCC_APB1ENCR1_I3C1ENC_Msk               (0x1UL << RCC_APB1ENCR1_I3C1ENC_Pos)  /*!< 0x01000000 */
32111 #define RCC_APB1ENCR1_I3C1ENC                   RCC_APB1ENCR1_I3C1ENC_Msk            /*!< I3C1 enable */
32112 #define RCC_APB1ENCR1_I3C2ENC_Pos               (25U)
32113 #define RCC_APB1ENCR1_I3C2ENC_Msk               (0x1UL << RCC_APB1ENCR1_I3C2ENC_Pos)  /*!< 0x02000000 */
32114 #define RCC_APB1ENCR1_I3C2ENC                   RCC_APB1ENCR1_I3C2ENC_Msk            /*!< I3C2 enable */
32115 #define RCC_APB1ENCR1_UART7ENC_Pos              (30U)
32116 #define RCC_APB1ENCR1_UART7ENC_Msk              (0x1UL << RCC_APB1ENCR1_UART7ENC_Pos) /*!< 0x40000000 */
32117 #define RCC_APB1ENCR1_UART7ENC                  RCC_APB1ENCR1_UART7ENC_Msk           /*!< UART7 enable */
32118 #define RCC_APB1ENCR1_UART8ENC_Pos              (31U)
32119 #define RCC_APB1ENCR1_UART8ENC_Msk              (0x1UL << RCC_APB1ENCR1_UART8ENC_Pos) /*!< 0x80000000 */
32120 #define RCC_APB1ENCR1_UART8ENC                  RCC_APB1ENCR1_UART8ENC_Msk           /*!< UART8 enable */
32121 
32122 /****************  Bit definition for RCC_APB1ENCR2 register  *****************/
32123 #define RCC_APB1ENCR2_MDIOSENC_Pos              (5U)
32124 #define RCC_APB1ENCR2_MDIOSENC_Msk              (0x1UL << RCC_APB1ENCR2_MDIOSENC_Pos) /*!< 0x00000020 */
32125 #define RCC_APB1ENCR2_MDIOSENC                  RCC_APB1ENCR2_MDIOSENC_Msk           /*!< MDIOS enable */
32126 #define RCC_APB1ENCR2_FDCANENC_Pos              (8U)
32127 #define RCC_APB1ENCR2_FDCANENC_Msk              (0x1UL << RCC_APB1ENCR2_FDCANENC_Pos) /*!< 0x00000100 */
32128 #define RCC_APB1ENCR2_FDCANENC                  RCC_APB1ENCR2_FDCANENC_Msk           /*!< FDCAN enable */
32129 #define RCC_APB1ENCR2_UCPD1ENC_Pos              (18U)
32130 #define RCC_APB1ENCR2_UCPD1ENC_Msk              (0x1UL << RCC_APB1ENCR2_UCPD1ENC_Pos) /*!< 0x00040000 */
32131 #define RCC_APB1ENCR2_UCPD1ENC                  RCC_APB1ENCR2_UCPD1ENC_Msk           /*!< UCPD1 enable */
32132 
32133 /*****************  Bit definition for RCC_APB2ENCR register  *****************/
32134 #define RCC_APB2ENCR_TIM1ENC_Pos                (0U)
32135 #define RCC_APB2ENCR_TIM1ENC_Msk                (0x1UL << RCC_APB2ENCR_TIM1ENC_Pos)   /*!< 0x00000001 */
32136 #define RCC_APB2ENCR_TIM1ENC                    RCC_APB2ENCR_TIM1ENC_Msk             /*!< TIM1 enable */
32137 #define RCC_APB2ENCR_TIM8ENC_Pos                (1U)
32138 #define RCC_APB2ENCR_TIM8ENC_Msk                (0x1UL << RCC_APB2ENCR_TIM8ENC_Pos)   /*!< 0x00000002 */
32139 #define RCC_APB2ENCR_TIM8ENC                    RCC_APB2ENCR_TIM8ENC_Msk             /*!< TIM8 enable */
32140 #define RCC_APB2ENCR_USART1ENC_Pos              (4U)
32141 #define RCC_APB2ENCR_USART1ENC_Msk              (0x1UL << RCC_APB2ENCR_USART1ENC_Pos) /*!< 0x00000010 */
32142 #define RCC_APB2ENCR_USART1ENC                  RCC_APB2ENCR_USART1ENC_Msk           /*!< USART1 enable */
32143 #define RCC_APB2ENCR_USART6ENC_Pos              (5U)
32144 #define RCC_APB2ENCR_USART6ENC_Msk              (0x1UL << RCC_APB2ENCR_USART6ENC_Pos) /*!< 0x00000020 */
32145 #define RCC_APB2ENCR_USART6ENC                  RCC_APB2ENCR_USART6ENC_Msk           /*!< USART6 enable */
32146 #define RCC_APB2ENCR_UART9ENC_Pos               (6U)
32147 #define RCC_APB2ENCR_UART9ENC_Msk               (0x1UL << RCC_APB2ENCR_UART9ENC_Pos)  /*!< 0x00000040 */
32148 #define RCC_APB2ENCR_UART9ENC                   RCC_APB2ENCR_UART9ENC_Msk            /*!< UART9 enable */
32149 #define RCC_APB2ENCR_USART10ENC_Pos             (7U)
32150 #define RCC_APB2ENCR_USART10ENC_Msk             (0x1UL << RCC_APB2ENCR_USART10ENC_Pos)/*!< 0x00000080 */
32151 #define RCC_APB2ENCR_USART10ENC                 RCC_APB2ENCR_USART10ENC_Msk          /*!< USART10 enable */
32152 #define RCC_APB2ENCR_SPI1ENC_Pos                (12U)
32153 #define RCC_APB2ENCR_SPI1ENC_Msk                (0x1UL << RCC_APB2ENCR_SPI1ENC_Pos)   /*!< 0x00001000 */
32154 #define RCC_APB2ENCR_SPI1ENC                    RCC_APB2ENCR_SPI1ENC_Msk             /*!< SPI1 enable */
32155 #define RCC_APB2ENCR_SPI4ENC_Pos                (13U)
32156 #define RCC_APB2ENCR_SPI4ENC_Msk                (0x1UL << RCC_APB2ENCR_SPI4ENC_Pos)   /*!< 0x00002000 */
32157 #define RCC_APB2ENCR_SPI4ENC                    RCC_APB2ENCR_SPI4ENC_Msk             /*!< SPI4 enable */
32158 #define RCC_APB2ENCR_TIM18ENC_Pos               (15U)
32159 #define RCC_APB2ENCR_TIM18ENC_Msk               (0x1UL << RCC_APB2ENCR_TIM18ENC_Pos)  /*!< 0x00008000 */
32160 #define RCC_APB2ENCR_TIM18ENC                   RCC_APB2ENCR_TIM18ENC_Msk            /*!< TIM18 enable */
32161 #define RCC_APB2ENCR_TIM15ENC_Pos               (16U)
32162 #define RCC_APB2ENCR_TIM15ENC_Msk               (0x1UL << RCC_APB2ENCR_TIM15ENC_Pos)  /*!< 0x00010000 */
32163 #define RCC_APB2ENCR_TIM15ENC                   RCC_APB2ENCR_TIM15ENC_Msk            /*!< TIM15 enable */
32164 #define RCC_APB2ENCR_TIM16ENC_Pos               (17U)
32165 #define RCC_APB2ENCR_TIM16ENC_Msk               (0x1UL << RCC_APB2ENCR_TIM16ENC_Pos)  /*!< 0x00020000 */
32166 #define RCC_APB2ENCR_TIM16ENC                   RCC_APB2ENCR_TIM16ENC_Msk            /*!< TIM16 enable */
32167 #define RCC_APB2ENCR_TIM17ENC_Pos               (18U)
32168 #define RCC_APB2ENCR_TIM17ENC_Msk               (0x1UL << RCC_APB2ENCR_TIM17ENC_Pos)  /*!< 0x00040000 */
32169 #define RCC_APB2ENCR_TIM17ENC                   RCC_APB2ENCR_TIM17ENC_Msk            /*!< TIM17 enable */
32170 #define RCC_APB2ENCR_TIM9ENC_Pos                (19U)
32171 #define RCC_APB2ENCR_TIM9ENC_Msk                (0x1UL << RCC_APB2ENCR_TIM9ENC_Pos)   /*!< 0x00080000 */
32172 #define RCC_APB2ENCR_TIM9ENC                    RCC_APB2ENCR_TIM9ENC_Msk             /*!< TIM9 enable */
32173 #define RCC_APB2ENCR_SPI5ENC_Pos                (20U)
32174 #define RCC_APB2ENCR_SPI5ENC_Msk                (0x1UL << RCC_APB2ENCR_SPI5ENC_Pos)   /*!< 0x00100000 */
32175 #define RCC_APB2ENCR_SPI5ENC                    RCC_APB2ENCR_SPI5ENC_Msk             /*!< SPI5 enable */
32176 #define RCC_APB2ENCR_SAI1ENC_Pos                (21U)
32177 #define RCC_APB2ENCR_SAI1ENC_Msk                (0x1UL << RCC_APB2ENCR_SAI1ENC_Pos)   /*!< 0x00200000 */
32178 #define RCC_APB2ENCR_SAI1ENC                    RCC_APB2ENCR_SAI1ENC_Msk             /*!< SAI1 enable */
32179 #define RCC_APB2ENCR_SAI2ENC_Pos                (22U)
32180 #define RCC_APB2ENCR_SAI2ENC_Msk                (0x1UL << RCC_APB2ENCR_SAI2ENC_Pos)   /*!< 0x00400000 */
32181 #define RCC_APB2ENCR_SAI2ENC                    RCC_APB2ENCR_SAI2ENC_Msk             /*!< SAI2 enable */
32182 
32183 /*****************  Bit definition for RCC_APB3ENCR register  *****************/
32184 #define RCC_APB3ENCR_DFTENC_Pos                 (2U)
32185 #define RCC_APB3ENCR_DFTENC_Msk                 (0x1UL << RCC_APB3ENCR_DFTENC_Pos)    /*!< 0x00000004 */
32186 #define RCC_APB3ENCR_DFTENC                     RCC_APB3ENCR_DFTENC_Msk              /*!< DFT enable */
32187 
32188 /****************  Bit definition for RCC_APB4ENCR1 register  *****************/
32189 #define RCC_APB4ENCR1_HDPENC_Pos                (2U)
32190 #define RCC_APB4ENCR1_HDPENC_Msk                (0x1UL << RCC_APB4ENCR1_HDPENC_Pos)   /*!< 0x00000004 */
32191 #define RCC_APB4ENCR1_HDPENC                    RCC_APB4ENCR1_HDPENC_Msk             /*!< HDP enable */
32192 #define RCC_APB4ENCR1_LPUART1ENC_Pos            (3U)
32193 #define RCC_APB4ENCR1_LPUART1ENC_Msk            (0x1UL << RCC_APB4ENCR1_LPUART1ENC_Pos) /*!< 0x00000008 */
32194 #define RCC_APB4ENCR1_LPUART1ENC                RCC_APB4ENCR1_LPUART1ENC_Msk         /*!< LPUART1 enable */
32195 #define RCC_APB4ENCR1_SPI6ENC_Pos               (5U)
32196 #define RCC_APB4ENCR1_SPI6ENC_Msk               (0x1UL << RCC_APB4ENCR1_SPI6ENC_Pos)  /*!< 0x00000020 */
32197 #define RCC_APB4ENCR1_SPI6ENC                   RCC_APB4ENCR1_SPI6ENC_Msk            /*!< SPI6 enable */
32198 #define RCC_APB4ENCR1_I2C4ENC_Pos               (7U)
32199 #define RCC_APB4ENCR1_I2C4ENC_Msk               (0x1UL << RCC_APB4ENCR1_I2C4ENC_Pos)  /*!< 0x00000080 */
32200 #define RCC_APB4ENCR1_I2C4ENC                   RCC_APB4ENCR1_I2C4ENC_Msk            /*!< I2C4 enable */
32201 #define RCC_APB4ENCR1_LPTIM2ENC_Pos             (9U)
32202 #define RCC_APB4ENCR1_LPTIM2ENC_Msk             (0x1UL << RCC_APB4ENCR1_LPTIM2ENC_Pos)/*!< 0x00000200 */
32203 #define RCC_APB4ENCR1_LPTIM2ENC                 RCC_APB4ENCR1_LPTIM2ENC_Msk          /*!< LPTIM2 enable */
32204 #define RCC_APB4ENCR1_LPTIM3ENC_Pos             (10U)
32205 #define RCC_APB4ENCR1_LPTIM3ENC_Msk             (0x1UL << RCC_APB4ENCR1_LPTIM3ENC_Pos)/*!< 0x00000400 */
32206 #define RCC_APB4ENCR1_LPTIM3ENC                 RCC_APB4ENCR1_LPTIM3ENC_Msk          /*!< LPTIM3 enable */
32207 #define RCC_APB4ENCR1_LPTIM4ENC_Pos             (11U)
32208 #define RCC_APB4ENCR1_LPTIM4ENC_Msk             (0x1UL << RCC_APB4ENCR1_LPTIM4ENC_Pos)/*!< 0x00000800 */
32209 #define RCC_APB4ENCR1_LPTIM4ENC                 RCC_APB4ENCR1_LPTIM4ENC_Msk          /*!< LPTIM4 enable */
32210 #define RCC_APB4ENCR1_LPTIM5ENC_Pos             (12U)
32211 #define RCC_APB4ENCR1_LPTIM5ENC_Msk             (0x1UL << RCC_APB4ENCR1_LPTIM5ENC_Pos)/*!< 0x00001000 */
32212 #define RCC_APB4ENCR1_LPTIM5ENC                 RCC_APB4ENCR1_LPTIM5ENC_Msk          /*!< LPTIM5 enable */
32213 #define RCC_APB4ENCR1_VREFBUFENC_Pos            (15U)
32214 #define RCC_APB4ENCR1_VREFBUFENC_Msk            (0x1UL << RCC_APB4ENCR1_VREFBUFENC_Pos) /*!< 0x00008000 */
32215 #define RCC_APB4ENCR1_VREFBUFENC                RCC_APB4ENCR1_VREFBUFENC_Msk         /*!< VREFBUF enable */
32216 #define RCC_APB4ENCR1_RTCENC_Pos                (16U)
32217 #define RCC_APB4ENCR1_RTCENC_Msk                (0x1UL << RCC_APB4ENCR1_RTCENC_Pos)   /*!< 0x00010000 */
32218 #define RCC_APB4ENCR1_RTCENC                    RCC_APB4ENCR1_RTCENC_Msk             /*!< RTC enable */
32219 #define RCC_APB4ENCR1_RTCAPBENC_Pos             (17U)
32220 #define RCC_APB4ENCR1_RTCAPBENC_Msk             (0x1UL << RCC_APB4ENCR1_RTCAPBENC_Pos)/*!< 0x00020000 */
32221 #define RCC_APB4ENCR1_RTCAPBENC                 RCC_APB4ENCR1_RTCAPBENC_Msk          /*!< RTCAPB enable */
32222 
32223 /****************  Bit definition for RCC_APB4ENCR2 register  *****************/
32224 #define RCC_APB4ENCR2_SYSCFGENC_Pos             (0U)
32225 #define RCC_APB4ENCR2_SYSCFGENC_Msk             (0x1UL << RCC_APB4ENCR2_SYSCFGENC_Pos)/*!< 0x00000001 */
32226 #define RCC_APB4ENCR2_SYSCFGENC                 RCC_APB4ENCR2_SYSCFGENC_Msk          /*!< SYSCFG enable */
32227 #define RCC_APB4ENCR2_BSECENC_Pos               (1U)
32228 #define RCC_APB4ENCR2_BSECENC_Msk               (0x1UL << RCC_APB4ENCR2_BSECENC_Pos)  /*!< 0x00000002 */
32229 #define RCC_APB4ENCR2_BSECENC                   RCC_APB4ENCR2_BSECENC_Msk            /*!< BSEC enable */
32230 #define RCC_APB4ENCR2_DTSENC_Pos                (2U)
32231 #define RCC_APB4ENCR2_DTSENC_Msk                (0x1UL << RCC_APB4ENCR2_DTSENC_Pos)   /*!< 0x00000004 */
32232 #define RCC_APB4ENCR2_DTSENC                    RCC_APB4ENCR2_DTSENC_Msk             /*!< DTS enable */
32233 
32234 /*****************  Bit definition for RCC_APB5ENCR register  *****************/
32235 #define RCC_APB5ENCR_LTDCENC_Pos                (1U)
32236 #define RCC_APB5ENCR_LTDCENC_Msk                (0x1UL << RCC_APB5ENCR_LTDCENC_Pos)   /*!< 0x00000002 */
32237 #define RCC_APB5ENCR_LTDCENC                    RCC_APB5ENCR_LTDCENC_Msk             /*!< LTDC enable */
32238 #define RCC_APB5ENCR_DCMIPPENC_Pos              (2U)
32239 #define RCC_APB5ENCR_DCMIPPENC_Msk              (0x1UL << RCC_APB5ENCR_DCMIPPENC_Pos) /*!< 0x00000004 */
32240 #define RCC_APB5ENCR_DCMIPPENC                  RCC_APB5ENCR_DCMIPPENC_Msk           /*!< DCMIPP enable */
32241 #define RCC_APB5ENCR_GFXTIMENC_Pos              (4U)
32242 #define RCC_APB5ENCR_GFXTIMENC_Msk              (0x1UL << RCC_APB5ENCR_GFXTIMENC_Pos) /*!< 0x00000010 */
32243 #define RCC_APB5ENCR_GFXTIMENC                  RCC_APB5ENCR_GFXTIMENC_Msk           /*!< GFXTIM enable */
32244 #define RCC_APB5ENCR_VENCENC_Pos                (5U)
32245 #define RCC_APB5ENCR_VENCENC_Msk                (0x1UL << RCC_APB5ENCR_VENCENC_Pos)   /*!< 0x00000020 */
32246 #define RCC_APB5ENCR_VENCENC                    RCC_APB5ENCR_VENCENC_Msk             /*!< VENC enable */
32247 #define RCC_APB5ENCR_CSIENC_Pos                 (6U)
32248 #define RCC_APB5ENCR_CSIENC_Msk                 (0x1UL << RCC_APB5ENCR_CSIENC_Pos)    /*!< 0x00000040 */
32249 #define RCC_APB5ENCR_CSIENC                     RCC_APB5ENCR_CSIENC_Msk              /*!< CSI enable */
32250 
32251 /****************  Bit definition for RCC_BUSLPENCR register  *****************/
32252 #define RCC_BUSLPENCR_ACLKNLPENC_Pos            (0U)
32253 #define RCC_BUSLPENCR_ACLKNLPENC_Msk            (0x1UL << RCC_BUSLPENCR_ACLKNLPENC_Pos) /*!< 0x00000001 */
32254 #define RCC_BUSLPENCR_ACLKNLPENC                RCC_BUSLPENCR_ACLKNLPENC_Msk         /*!< ACLKN enable in Sleep mode */
32255 #define RCC_BUSLPENCR_ACLKNCLPENC_Pos           (1U)
32256 #define RCC_BUSLPENCR_ACLKNCLPENC_Msk           (0x1UL << RCC_BUSLPENCR_ACLKNCLPENC_Pos)  /*!< 0x00000002 */
32257 #define RCC_BUSLPENCR_ACLKNCLPENC               RCC_BUSLPENCR_ACLKNCLPENC_Msk        /*!< ACLKNC enable in Sleep mode */
32258 
32259 /****************  Bit definition for RCC_MISCLPENCR register  ****************/
32260 #define RCC_MISCLPENCR_DBGLPENC_Pos             (0U)
32261 #define RCC_MISCLPENCR_DBGLPENC_Msk             (0x1UL << RCC_MISCLPENCR_DBGLPENC_Pos)/*!< 0x00000001 */
32262 #define RCC_MISCLPENCR_DBGLPENC                 RCC_MISCLPENCR_DBGLPENC_Msk          /*!< DBG enable in Sleep mode */
32263 #define RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Pos     (3U)
32264 #define RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Msk     (0x1UL << RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Pos)        /*!< 0x00000008 */
32265 #define RCC_MISCLPENCR_XSPIPHYCOMPLPENC         RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Msk  /*!< XSPIPHYCOMP enable in Sleep mode */
32266 #define RCC_MISCLPENCR_PERLPENC_Pos             (6U)
32267 #define RCC_MISCLPENCR_PERLPENC_Msk             (0x1UL << RCC_MISCLPENCR_PERLPENC_Pos)/*!< 0x00000040 */
32268 #define RCC_MISCLPENCR_PERLPENC                 RCC_MISCLPENCR_PERLPENC_Msk          /*!< PER enable in Sleep mode */
32269 
32270 /****************  Bit definition for RCC_MEMLPENCR register  *****************/
32271 #define RCC_MEMLPENCR_AXISRAM3LPENC_Pos         (0U)
32272 #define RCC_MEMLPENCR_AXISRAM3LPENC_Msk         (0x1UL << RCC_MEMLPENCR_AXISRAM3LPENC_Pos)    /*!< 0x00000001 */
32273 #define RCC_MEMLPENCR_AXISRAM3LPENC             RCC_MEMLPENCR_AXISRAM3LPENC_Msk      /*!< AXISRAM3 enable in Sleep mode */
32274 #define RCC_MEMLPENCR_AXISRAM4LPENC_Pos         (1U)
32275 #define RCC_MEMLPENCR_AXISRAM4LPENC_Msk         (0x1UL << RCC_MEMLPENCR_AXISRAM4LPENC_Pos)    /*!< 0x00000002 */
32276 #define RCC_MEMLPENCR_AXISRAM4LPENC             RCC_MEMLPENCR_AXISRAM4LPENC_Msk      /*!< AXISRAM4 enable in Sleep mode */
32277 #define RCC_MEMLPENCR_AXISRAM5LPENC_Pos         (2U)
32278 #define RCC_MEMLPENCR_AXISRAM5LPENC_Msk         (0x1UL << RCC_MEMLPENCR_AXISRAM5LPENC_Pos)    /*!< 0x00000004 */
32279 #define RCC_MEMLPENCR_AXISRAM5LPENC             RCC_MEMLPENCR_AXISRAM5LPENC_Msk      /*!< AXISRAM5 enable in Sleep mode */
32280 #define RCC_MEMLPENCR_AXISRAM6LPENC_Pos         (3U)
32281 #define RCC_MEMLPENCR_AXISRAM6LPENC_Msk         (0x1UL << RCC_MEMLPENCR_AXISRAM6LPENC_Pos)    /*!< 0x00000008 */
32282 #define RCC_MEMLPENCR_AXISRAM6LPENC             RCC_MEMLPENCR_AXISRAM6LPENC_Msk      /*!< AXISRAM6 enable in Sleep mode */
32283 #define RCC_MEMLPENCR_AHBSRAM1LPENC_Pos         (4U)
32284 #define RCC_MEMLPENCR_AHBSRAM1LPENC_Msk         (0x1UL << RCC_MEMLPENCR_AHBSRAM1LPENC_Pos)    /*!< 0x00000010 */
32285 #define RCC_MEMLPENCR_AHBSRAM1LPENC             RCC_MEMLPENCR_AHBSRAM1LPENC_Msk      /*!< AHBSRAM1 enable in Sleep mode */
32286 #define RCC_MEMLPENCR_AHBSRAM2LPENC_Pos         (5U)
32287 #define RCC_MEMLPENCR_AHBSRAM2LPENC_Msk         (0x1UL << RCC_MEMLPENCR_AHBSRAM2LPENC_Pos)    /*!< 0x00000020 */
32288 #define RCC_MEMLPENCR_AHBSRAM2LPENC             RCC_MEMLPENCR_AHBSRAM2LPENC_Msk      /*!< AHBSRAM2 enable in Sleep mode */
32289 #define RCC_MEMLPENCR_BKPSRAMLPENC_Pos          (6U)
32290 #define RCC_MEMLPENCR_BKPSRAMLPENC_Msk          (0x1UL << RCC_MEMLPENCR_BKPSRAMLPENC_Pos)   /*!< 0x00000040 */
32291 #define RCC_MEMLPENCR_BKPSRAMLPENC              RCC_MEMLPENCR_BKPSRAMLPENC_Msk       /*!< BKPSRAM enable in Sleep mode */
32292 #define RCC_MEMLPENCR_AXISRAM1LPENC_Pos         (7U)
32293 #define RCC_MEMLPENCR_AXISRAM1LPENC_Msk         (0x1UL << RCC_MEMLPENCR_AXISRAM1LPENC_Pos)    /*!< 0x00000080 */
32294 #define RCC_MEMLPENCR_AXISRAM1LPENC             RCC_MEMLPENCR_AXISRAM1LPENC_Msk      /*!< AXISRAM1 enable in Sleep mode */
32295 #define RCC_MEMLPENCR_AXISRAM2LPENC_Pos         (8U)
32296 #define RCC_MEMLPENCR_AXISRAM2LPENC_Msk         (0x1UL << RCC_MEMLPENCR_AXISRAM2LPENC_Pos)    /*!< 0x00000100 */
32297 #define RCC_MEMLPENCR_AXISRAM2LPENC             RCC_MEMLPENCR_AXISRAM2LPENC_Msk      /*!< AXISRAM2 enable in Sleep mode */
32298 #define RCC_MEMLPENCR_FLEXRAMLPENC_Pos          (9U)
32299 #define RCC_MEMLPENCR_FLEXRAMLPENC_Msk          (0x1UL << RCC_MEMLPENCR_FLEXRAMLPENC_Pos)   /*!< 0x00000200 */
32300 #define RCC_MEMLPENCR_FLEXRAMLPENC              RCC_MEMLPENCR_FLEXRAMLPENC_Msk       /*!< FLEXRAM enable in Sleep mode */
32301 #define RCC_MEMLPENCR_CACHEAXIRAMLPENC_Pos      (10U)
32302 #define RCC_MEMLPENCR_CACHEAXIRAMLPENC_Msk      (0x1UL << RCC_MEMLPENCR_CACHEAXIRAMLPENC_Pos)       /*!< 0x00000400 */
32303 #define RCC_MEMLPENCR_CACHEAXIRAMLPENC          RCC_MEMLPENCR_CACHEAXIRAMLPENC_Msk   /*!< CACHEAXIRAM enable in Sleep mode */
32304 #define RCC_MEMLPENCR_VENCRAMLPENC_Pos          (11U)
32305 #define RCC_MEMLPENCR_VENCRAMLPENC_Msk          (0x1UL << RCC_MEMLPENCR_VENCRAMLPENC_Pos)   /*!< 0x00000800 */
32306 #define RCC_MEMLPENCR_VENCRAMLPENC              RCC_MEMLPENCR_VENCRAMLPENC_Msk       /*!< VENCRAM enable in Sleep mode */
32307 #define RCC_MEMLPENCR_BOOTROMLPENC_Pos          (12U)
32308 #define RCC_MEMLPENCR_BOOTROMLPENC_Msk          (0x1UL << RCC_MEMLPENCR_BOOTROMLPENC_Pos)   /*!< 0x00001000 */
32309 #define RCC_MEMLPENCR_BOOTROMLPENC              RCC_MEMLPENCR_BOOTROMLPENC_Msk       /*!< Boot ROM enable in Sleep mode */
32310 
32311 /****************  Bit definition for RCC_AHB1LPENCR register  ****************/
32312 #define RCC_AHB1LPENCR_GPDMA1LPENC_Pos          (4U)
32313 #define RCC_AHB1LPENCR_GPDMA1LPENC_Msk          (0x1UL << RCC_AHB1LPENCR_GPDMA1LPENC_Pos)   /*!< 0x00000010 */
32314 #define RCC_AHB1LPENCR_GPDMA1LPENC              RCC_AHB1LPENCR_GPDMA1LPENC_Msk       /*!< GPDMA1 enable in Sleep mode */
32315 #define RCC_AHB1LPENCR_ADC12LPENC_Pos           (5U)
32316 #define RCC_AHB1LPENCR_ADC12LPENC_Msk           (0x1UL << RCC_AHB1LPENCR_ADC12LPENC_Pos)  /*!< 0x00000020 */
32317 #define RCC_AHB1LPENCR_ADC12LPENC               RCC_AHB1LPENCR_ADC12LPENC_Msk        /*!< ADC12 enable in Sleep mode */
32318 
32319 /****************  Bit definition for RCC_AHB2LPENCR register  ****************/
32320 #define RCC_AHB2LPENCR_RAMCFGLPENC_Pos          (12U)
32321 #define RCC_AHB2LPENCR_RAMCFGLPENC_Msk          (0x1UL << RCC_AHB2LPENCR_RAMCFGLPENC_Pos)   /*!< 0x00001000 */
32322 #define RCC_AHB2LPENCR_RAMCFGLPENC              RCC_AHB2LPENCR_RAMCFGLPENC_Msk       /*!< RAMCFG enable in Sleep mode */
32323 #define RCC_AHB2LPENCR_MDF1LPENC_Pos            (16U)
32324 #define RCC_AHB2LPENCR_MDF1LPENC_Msk            (0x1UL << RCC_AHB2LPENCR_MDF1LPENC_Pos) /*!< 0x00010000 */
32325 #define RCC_AHB2LPENCR_MDF1LPENC                RCC_AHB2LPENCR_MDF1LPENC_Msk         /*!< MDF1 enable in Sleep mode */
32326 #define RCC_AHB2LPENCR_ADF1LPENC_Pos            (17U)
32327 #define RCC_AHB2LPENCR_ADF1LPENC_Msk            (0x1UL << RCC_AHB2LPENCR_ADF1LPENC_Pos) /*!< 0x00020000 */
32328 #define RCC_AHB2LPENCR_ADF1LPENC                RCC_AHB2LPENCR_ADF1LPENC_Msk         /*!< ADF1 enable in Sleep mode */
32329 
32330 /****************  Bit definition for RCC_AHB3LPENCR register  ****************/
32331 #define RCC_AHB3LPENCR_RNGLPENC_Pos             (0U)
32332 #define RCC_AHB3LPENCR_RNGLPENC_Msk             (0x1UL << RCC_AHB3LPENCR_RNGLPENC_Pos)/*!< 0x00000001 */
32333 #define RCC_AHB3LPENCR_RNGLPENC                 RCC_AHB3LPENCR_RNGLPENC_Msk          /*!< RNG enable in Sleep mode */
32334 #define RCC_AHB3LPENCR_HASHLPENC_Pos            (1U)
32335 #define RCC_AHB3LPENCR_HASHLPENC_Msk            (0x1UL << RCC_AHB3LPENCR_HASHLPENC_Pos) /*!< 0x00000002 */
32336 #define RCC_AHB3LPENCR_HASHLPENC                RCC_AHB3LPENCR_HASHLPENC_Msk         /*!< HASH enable in Sleep mode */
32337 #define RCC_AHB3LPENCR_CRYPLPENC_Pos            (2U)
32338 #define RCC_AHB3LPENCR_CRYPLPENC_Msk            (0x1UL << RCC_AHB3LPENCR_CRYPLPENC_Pos) /*!< 0x00000004 */
32339 #define RCC_AHB3LPENCR_CRYPLPENC                RCC_AHB3LPENCR_CRYPLPENC_Msk         /*!< CRYP enable in Sleep mode */
32340 #define RCC_AHB3LPENCR_SAESLPENC_Pos            (4U)
32341 #define RCC_AHB3LPENCR_SAESLPENC_Msk            (0x1UL << RCC_AHB3LPENCR_SAESLPENC_Pos) /*!< 0x00000010 */
32342 #define RCC_AHB3LPENCR_SAESLPENC                RCC_AHB3LPENCR_SAESLPENC_Msk         /*!< SAES enable in Sleep mode */
32343 #define RCC_AHB3LPENCR_PKALPENC_Pos             (8U)
32344 #define RCC_AHB3LPENCR_PKALPENC_Msk             (0x1UL << RCC_AHB3LPENCR_PKALPENC_Pos)/*!< 0x00000100 */
32345 #define RCC_AHB3LPENCR_PKALPENC                 RCC_AHB3LPENCR_PKALPENC_Msk          /*!< PKA enable in Sleep mode */
32346 #define RCC_AHB3LPENCR_RIFSCLPENC_Pos           (9U)
32347 #define RCC_AHB3LPENCR_RIFSCLPENC_Msk           (0x1UL << RCC_AHB3LPENCR_RIFSCLPENC_Pos)  /*!< 0x00000200 */
32348 #define RCC_AHB3LPENCR_RIFSCLPENC               RCC_AHB3LPENCR_RIFSCLPENC_Msk        /*!< RIFSC enable in Sleep mode */
32349 #define RCC_AHB3LPENCR_IACLPENC_Pos             (10U)
32350 #define RCC_AHB3LPENCR_IACLPENC_Msk             (0x1UL << RCC_AHB3LPENCR_IACLPENC_Pos)/*!< 0x00000400 */
32351 #define RCC_AHB3LPENCR_IACLPENC                 RCC_AHB3LPENCR_IACLPENC_Msk          /*!< IAC enable in Sleep mode */
32352 #define RCC_AHB3LPENCR_RISAFLPENC_Pos           (14U)
32353 #define RCC_AHB3LPENCR_RISAFLPENC_Msk           (0x1UL << RCC_AHB3LPENCR_RISAFLPENC_Pos)  /*!< 0x00004000 */
32354 #define RCC_AHB3LPENCR_RISAFLPENC               RCC_AHB3LPENCR_RISAFLPENC_Msk        /*!< RISAF enable in Sleep mode */
32355 
32356 /****************  Bit definition for RCC_AHB4LPENCR register  ****************/
32357 #define RCC_AHB4LPENCR_GPIOALPENC_Pos           (0U)
32358 #define RCC_AHB4LPENCR_GPIOALPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOALPENC_Pos)  /*!< 0x00000001 */
32359 #define RCC_AHB4LPENCR_GPIOALPENC               RCC_AHB4LPENCR_GPIOALPENC_Msk        /*!< GPIO A enable in Sleep mode */
32360 #define RCC_AHB4LPENCR_GPIOBLPENC_Pos           (1U)
32361 #define RCC_AHB4LPENCR_GPIOBLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOBLPENC_Pos)  /*!< 0x00000002 */
32362 #define RCC_AHB4LPENCR_GPIOBLPENC               RCC_AHB4LPENCR_GPIOBLPENC_Msk        /*!< GPIO B enable in Sleep mode */
32363 #define RCC_AHB4LPENCR_GPIOCLPENC_Pos           (2U)
32364 #define RCC_AHB4LPENCR_GPIOCLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOCLPENC_Pos)  /*!< 0x00000004 */
32365 #define RCC_AHB4LPENCR_GPIOCLPENC               RCC_AHB4LPENCR_GPIOCLPENC_Msk        /*!< GPIO C enable in Sleep mode */
32366 #define RCC_AHB4LPENCR_GPIODLPENC_Pos           (3U)
32367 #define RCC_AHB4LPENCR_GPIODLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIODLPENC_Pos)  /*!< 0x00000008 */
32368 #define RCC_AHB4LPENCR_GPIODLPENC               RCC_AHB4LPENCR_GPIODLPENC_Msk        /*!< GPIO D enable in Sleep mode */
32369 #define RCC_AHB4LPENCR_GPIOELPENC_Pos           (4U)
32370 #define RCC_AHB4LPENCR_GPIOELPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOELPENC_Pos)  /*!< 0x00000010 */
32371 #define RCC_AHB4LPENCR_GPIOELPENC               RCC_AHB4LPENCR_GPIOELPENC_Msk        /*!< GPIO E enable in Sleep mode */
32372 #define RCC_AHB4LPENCR_GPIOFLPENC_Pos           (5U)
32373 #define RCC_AHB4LPENCR_GPIOFLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOFLPENC_Pos)  /*!< 0x00000020 */
32374 #define RCC_AHB4LPENCR_GPIOFLPENC               RCC_AHB4LPENCR_GPIOFLPENC_Msk        /*!< GPIO F enable in Sleep mode */
32375 #define RCC_AHB4LPENCR_GPIOGLPENC_Pos           (6U)
32376 #define RCC_AHB4LPENCR_GPIOGLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOGLPENC_Pos)  /*!< 0x00000040 */
32377 #define RCC_AHB4LPENCR_GPIOGLPENC               RCC_AHB4LPENCR_GPIOGLPENC_Msk        /*!< GPIO G enable in Sleep mode */
32378 #define RCC_AHB4LPENCR_GPIOHLPENC_Pos           (7U)
32379 #define RCC_AHB4LPENCR_GPIOHLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOHLPENC_Pos)  /*!< 0x00000080 */
32380 #define RCC_AHB4LPENCR_GPIOHLPENC               RCC_AHB4LPENCR_GPIOHLPENC_Msk        /*!< GPIO H enable in Sleep mode */
32381 #define RCC_AHB4LPENCR_GPIONLPENC_Pos           (13U)
32382 #define RCC_AHB4LPENCR_GPIONLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIONLPENC_Pos)  /*!< 0x00002000 */
32383 #define RCC_AHB4LPENCR_GPIONLPENC               RCC_AHB4LPENCR_GPIONLPENC_Msk        /*!< GPIO N enable in Sleep mode */
32384 #define RCC_AHB4LPENCR_GPIOOLPENC_Pos           (14U)
32385 #define RCC_AHB4LPENCR_GPIOOLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOOLPENC_Pos)  /*!< 0x00004000 */
32386 #define RCC_AHB4LPENCR_GPIOOLPENC               RCC_AHB4LPENCR_GPIOOLPENC_Msk        /*!< GPIO O enable in Sleep mode */
32387 #define RCC_AHB4LPENCR_GPIOPLPENC_Pos           (15U)
32388 #define RCC_AHB4LPENCR_GPIOPLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOPLPENC_Pos)  /*!< 0x00008000 */
32389 #define RCC_AHB4LPENCR_GPIOPLPENC               RCC_AHB4LPENCR_GPIOPLPENC_Msk        /*!< GPIO P enable in Sleep mode */
32390 #define RCC_AHB4LPENCR_GPIOQLPENC_Pos           (16U)
32391 #define RCC_AHB4LPENCR_GPIOQLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOQLPENC_Pos)  /*!< 0x00010000 */
32392 #define RCC_AHB4LPENCR_GPIOQLPENC               RCC_AHB4LPENCR_GPIOQLPENC_Msk        /*!< GPIO Q enable in Sleep mode */
32393 #define RCC_AHB4LPENCR_PWRLPENC_Pos             (18U)
32394 #define RCC_AHB4LPENCR_PWRLPENC_Msk             (0x1UL << RCC_AHB4LPENCR_PWRLPENC_Pos)/*!< 0x00040000 */
32395 #define RCC_AHB4LPENCR_PWRLPENC                 RCC_AHB4LPENCR_PWRLPENC_Msk          /*!< PWR enable in Sleep mode */
32396 #define RCC_AHB4LPENCR_CRCLPENC_Pos             (19U)
32397 #define RCC_AHB4LPENCR_CRCLPENC_Msk             (0x1UL << RCC_AHB4LPENCR_CRCLPENC_Pos)/*!< 0x00080000 */
32398 #define RCC_AHB4LPENCR_CRCLPENC                 RCC_AHB4LPENCR_CRCLPENC_Msk          /*!< CRC enable in Sleep mode */
32399 
32400 /****************  Bit definition for RCC_AHB5LPENCR register  ****************/
32401 #define RCC_AHB5LPENCR_HPDMA1LPENC_Pos          (0U)
32402 #define RCC_AHB5LPENCR_HPDMA1LPENC_Msk          (0x1UL << RCC_AHB5LPENCR_HPDMA1LPENC_Pos)   /*!< 0x00000001 */
32403 #define RCC_AHB5LPENCR_HPDMA1LPENC              RCC_AHB5LPENCR_HPDMA1LPENC_Msk       /*!< HPDMA1 enable in Sleep mode */
32404 #define RCC_AHB5LPENCR_DMA2DLPENC_Pos           (1U)
32405 #define RCC_AHB5LPENCR_DMA2DLPENC_Msk           (0x1UL << RCC_AHB5LPENCR_DMA2DLPENC_Pos)  /*!< 0x00000002 */
32406 #define RCC_AHB5LPENCR_DMA2DLPENC               RCC_AHB5LPENCR_DMA2DLPENC_Msk        /*!< DMA2D enable in Sleep mode */
32407 #define RCC_AHB5LPENCR_JPEGLPENC_Pos            (3U)
32408 #define RCC_AHB5LPENCR_JPEGLPENC_Msk            (0x1UL << RCC_AHB5LPENCR_JPEGLPENC_Pos) /*!< 0x00000008 */
32409 #define RCC_AHB5LPENCR_JPEGLPENC                RCC_AHB5LPENCR_JPEGLPENC_Msk         /*!< JPEG enable in Sleep mode */
32410 #define RCC_AHB5LPENCR_FMCLPENC_Pos             (4U)
32411 #define RCC_AHB5LPENCR_FMCLPENC_Msk             (0x1UL << RCC_AHB5LPENCR_FMCLPENC_Pos)/*!< 0x00000010 */
32412 #define RCC_AHB5LPENCR_FMCLPENC                 RCC_AHB5LPENCR_FMCLPENC_Msk          /*!< FMC enable in Sleep mode */
32413 #define RCC_AHB5LPENCR_XSPI1LPENC_Pos           (5U)
32414 #define RCC_AHB5LPENCR_XSPI1LPENC_Msk           (0x1UL << RCC_AHB5LPENCR_XSPI1LPENC_Pos)  /*!< 0x00000020 */
32415 #define RCC_AHB5LPENCR_XSPI1LPENC               RCC_AHB5LPENCR_XSPI1LPENC_Msk        /*!< XSPI1 enable in Sleep mode */
32416 #define RCC_AHB5LPENCR_PSSILPENC_Pos            (6U)
32417 #define RCC_AHB5LPENCR_PSSILPENC_Msk            (0x1UL << RCC_AHB5LPENCR_PSSILPENC_Pos) /*!< 0x00000040 */
32418 #define RCC_AHB5LPENCR_PSSILPENC                RCC_AHB5LPENCR_PSSILPENC_Msk         /*!< PSSI enable in Sleep mode */
32419 #define RCC_AHB5LPENCR_SDMMC2LPENC_Pos          (7U)
32420 #define RCC_AHB5LPENCR_SDMMC2LPENC_Msk          (0x1UL << RCC_AHB5LPENCR_SDMMC2LPENC_Pos)   /*!< 0x00000080 */
32421 #define RCC_AHB5LPENCR_SDMMC2LPENC              RCC_AHB5LPENCR_SDMMC2LPENC_Msk       /*!< SDMMC2 enable in Sleep mode */
32422 #define RCC_AHB5LPENCR_SDMMC1LPENC_Pos          (8U)
32423 #define RCC_AHB5LPENCR_SDMMC1LPENC_Msk          (0x1UL << RCC_AHB5LPENCR_SDMMC1LPENC_Pos)   /*!< 0x00000100 */
32424 #define RCC_AHB5LPENCR_SDMMC1LPENC              RCC_AHB5LPENCR_SDMMC1LPENC_Msk       /*!< SDMMC1 enable in Sleep mode */
32425 #define RCC_AHB5LPENCR_XSPI2LPENC_Pos           (12U)
32426 #define RCC_AHB5LPENCR_XSPI2LPENC_Msk           (0x1UL << RCC_AHB5LPENCR_XSPI2LPENC_Pos)  /*!< 0x00001000 */
32427 #define RCC_AHB5LPENCR_XSPI2LPENC               RCC_AHB5LPENCR_XSPI2LPENC_Msk        /*!< XSPI2 enable in Sleep mode */
32428 #define RCC_AHB5LPENCR_XSPIMLPENC_Pos           (13U)
32429 #define RCC_AHB5LPENCR_XSPIMLPENC_Msk           (0x1UL << RCC_AHB5LPENCR_XSPIMLPENC_Pos)  /*!< 0x00002000 */
32430 #define RCC_AHB5LPENCR_XSPIMLPENC               RCC_AHB5LPENCR_XSPIMLPENC_Msk        /*!< XSPIM enable in Sleep mode */
32431 #define RCC_AHB5LPENCR_MCE1LPENC_Pos            (14U)
32432 #define RCC_AHB5LPENCR_MCE1LPENC_Msk            (0x1UL << RCC_AHB5LPENCR_MCE1LPENC_Pos) /*!< 0x00004000 */
32433 #define RCC_AHB5LPENCR_MCE1LPENC                RCC_AHB5LPENCR_MCE1LPENC_Msk         /*!< MCE1 enable in Sleep mode */
32434 #define RCC_AHB5LPENCR_MCE2LPENC_Pos            (15U)
32435 #define RCC_AHB5LPENCR_MCE2LPENC_Msk            (0x1UL << RCC_AHB5LPENCR_MCE2LPENC_Pos) /*!< 0x00008000 */
32436 #define RCC_AHB5LPENCR_MCE2LPENC                RCC_AHB5LPENCR_MCE2LPENC_Msk         /*!< MCE2 enable in Sleep mode */
32437 #define RCC_AHB5LPENCR_MCE3LPENC_Pos            (16U)
32438 #define RCC_AHB5LPENCR_MCE3LPENC_Msk            (0x1UL << RCC_AHB5LPENCR_MCE3LPENC_Pos) /*!< 0x00010000 */
32439 #define RCC_AHB5LPENCR_MCE3LPENC                RCC_AHB5LPENCR_MCE3LPENC_Msk         /*!< MCE3 enable in Sleep mode */
32440 #define RCC_AHB5LPENCR_XSPI3LPENC_Pos           (17U)
32441 #define RCC_AHB5LPENCR_XSPI3LPENC_Msk           (0x1UL << RCC_AHB5LPENCR_XSPI3LPENC_Pos)  /*!< 0x00020000 */
32442 #define RCC_AHB5LPENCR_XSPI3LPENC               RCC_AHB5LPENCR_XSPI3LPENC_Msk        /*!< XSPI3 enable in Sleep mode */
32443 #define RCC_AHB5LPENCR_MCE4LPENC_Pos            (18U)
32444 #define RCC_AHB5LPENCR_MCE4LPENC_Msk            (0x1UL << RCC_AHB5LPENCR_MCE4LPENC_Pos) /*!< 0x00040000 */
32445 #define RCC_AHB5LPENCR_MCE4LPENC                RCC_AHB5LPENCR_MCE4LPENC_Msk         /*!< MCE4 enable in Sleep mode */
32446 #define RCC_AHB5LPENCR_GFXMMULPENC_Pos          (19U)
32447 #define RCC_AHB5LPENCR_GFXMMULPENC_Msk          (0x1UL << RCC_AHB5LPENCR_GFXMMULPENC_Pos)   /*!< 0x00080000 */
32448 #define RCC_AHB5LPENCR_GFXMMULPENC              RCC_AHB5LPENCR_GFXMMULPENC_Msk       /*!< GFXMMU enable in Sleep mode */
32449 #define RCC_AHB5LPENCR_GPU2DLPENC_Pos           (20U)
32450 #define RCC_AHB5LPENCR_GPU2DLPENC_Msk           (0x1UL << RCC_AHB5LPENCR_GPU2DLPENC_Pos)  /*!< 0x00100000 */
32451 #define RCC_AHB5LPENCR_GPU2DLPENC               RCC_AHB5LPENCR_GPU2DLPENC_Msk        /*!< GPU2D enable in Sleep mode */
32452 #define RCC_AHB5LPENCR_ETH1MACLPENC_Pos         (22U)
32453 #define RCC_AHB5LPENCR_ETH1MACLPENC_Msk         (0x1UL << RCC_AHB5LPENCR_ETH1MACLPENC_Pos)    /*!< 0x00400000 */
32454 #define RCC_AHB5LPENCR_ETH1MACLPENC             RCC_AHB5LPENCR_ETH1MACLPENC_Msk      /*!< ETH1MAC enable in Sleep mode */
32455 #define RCC_AHB5LPENCR_ETH1TXLPENC_Pos          (23U)
32456 #define RCC_AHB5LPENCR_ETH1TXLPENC_Msk          (0x1UL << RCC_AHB5LPENCR_ETH1TXLPENC_Pos)   /*!< 0x00800000 */
32457 #define RCC_AHB5LPENCR_ETH1TXLPENC              RCC_AHB5LPENCR_ETH1TXLPENC_Msk       /*!< ETH1TX enable in Sleep mode */
32458 #define RCC_AHB5LPENCR_ETH1RXLPENC_Pos          (24U)
32459 #define RCC_AHB5LPENCR_ETH1RXLPENC_Msk          (0x1UL << RCC_AHB5LPENCR_ETH1RXLPENC_Pos)   /*!< 0x01000000 */
32460 #define RCC_AHB5LPENCR_ETH1RXLPENC              RCC_AHB5LPENCR_ETH1RXLPENC_Msk       /*!< ETH1RX enable in Sleep mode */
32461 #define RCC_AHB5LPENCR_ETH1LPENC_Pos            (25U)
32462 #define RCC_AHB5LPENCR_ETH1LPENC_Msk            (0x1UL << RCC_AHB5LPENCR_ETH1LPENC_Pos) /*!< 0x02000000 */
32463 #define RCC_AHB5LPENCR_ETH1LPENC                RCC_AHB5LPENCR_ETH1LPENC_Msk         /*!< ETH1 enable in Sleep mode */
32464 #define RCC_AHB5LPENCR_OTG1LPENC_Pos            (26U)
32465 #define RCC_AHB5LPENCR_OTG1LPENC_Msk            (0x1UL << RCC_AHB5LPENCR_OTG1LPENC_Pos) /*!< 0x04000000 */
32466 #define RCC_AHB5LPENCR_OTG1LPENC                RCC_AHB5LPENCR_OTG1LPENC_Msk         /*!< OTG1 enable in Sleep mode */
32467 #define RCC_AHB5LPENCR_OTGPHY1LPENC_Pos         (27U)
32468 #define RCC_AHB5LPENCR_OTGPHY1LPENC_Msk         (0x1UL << RCC_AHB5LPENCR_OTGPHY1LPENC_Pos)    /*!< 0x08000000 */
32469 #define RCC_AHB5LPENCR_OTGPHY1LPENC             RCC_AHB5LPENCR_OTGPHY1LPENC_Msk      /*!< OTGPHY1 enable in Sleep mode */
32470 #define RCC_AHB5LPENCR_OTGPHY2LPENC_Pos         (28U)
32471 #define RCC_AHB5LPENCR_OTGPHY2LPENC_Msk         (0x1UL << RCC_AHB5LPENCR_OTGPHY2LPENC_Pos)    /*!< 0x10000000 */
32472 #define RCC_AHB5LPENCR_OTGPHY2LPENC             RCC_AHB5LPENCR_OTGPHY2LPENC_Msk      /*!< OTGPHY2 enable in Sleep mode */
32473 #define RCC_AHB5LPENCR_OTG2LPENC_Pos            (29U)
32474 #define RCC_AHB5LPENCR_OTG2LPENC_Msk            (0x1UL << RCC_AHB5LPENCR_OTG2LPENC_Pos) /*!< 0x20000000 */
32475 #define RCC_AHB5LPENCR_OTG2LPENC                RCC_AHB5LPENCR_OTG2LPENC_Msk         /*!< OTG2 enable in Sleep mode */
32476 #define RCC_AHB5LPENCR_CACHEAXILPENC_Pos        (30U)
32477 #define RCC_AHB5LPENCR_CACHEAXILPENC_Msk        (0x1UL << RCC_AHB5LPENCR_CACHEAXILPENC_Pos)     /*!< 0x40000000 */
32478 #define RCC_AHB5LPENCR_CACHEAXILPENC            RCC_AHB5LPENCR_CACHEAXILPENC_Msk     /*!< CACHEAXI enable in Sleep mode */
32479 #define RCC_AHB5LPENCR_NPULPENC_Pos             (31U)
32480 #define RCC_AHB5LPENCR_NPULPENC_Msk             (0x1UL << RCC_AHB5LPENCR_NPULPENC_Pos)/*!< 0x80000000 */
32481 #define RCC_AHB5LPENCR_NPULPENC                 RCC_AHB5LPENCR_NPULPENC_Msk          /*!< NPU enable in Sleep mode */
32482 
32483 /***************  Bit definition for RCC_APB1LPENCR1 register  ****************/
32484 #define RCC_APB1LPENCR1_TIM2LPENC_Pos           (0U)
32485 #define RCC_APB1LPENCR1_TIM2LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_TIM2LPENC_Pos)  /*!< 0x00000001 */
32486 #define RCC_APB1LPENCR1_TIM2LPENC               RCC_APB1LPENCR1_TIM2LPENC_Msk        /*!< TIM2 enable */
32487 #define RCC_APB1LPENCR1_TIM3LPENC_Pos           (1U)
32488 #define RCC_APB1LPENCR1_TIM3LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_TIM3LPENC_Pos)  /*!< 0x00000002 */
32489 #define RCC_APB1LPENCR1_TIM3LPENC               RCC_APB1LPENCR1_TIM3LPENC_Msk        /*!< TIM3 enable */
32490 #define RCC_APB1LPENCR1_TIM4LPENC_Pos           (2U)
32491 #define RCC_APB1LPENCR1_TIM4LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_TIM4LPENC_Pos)  /*!< 0x00000004 */
32492 #define RCC_APB1LPENCR1_TIM4LPENC               RCC_APB1LPENCR1_TIM4LPENC_Msk        /*!< TIM4 enable */
32493 #define RCC_APB1LPENCR1_TIM5LPENC_Pos           (3U)
32494 #define RCC_APB1LPENCR1_TIM5LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_TIM5LPENC_Pos)  /*!< 0x00000008 */
32495 #define RCC_APB1LPENCR1_TIM5LPENC               RCC_APB1LPENCR1_TIM5LPENC_Msk        /*!< TIM5 enable */
32496 #define RCC_APB1LPENCR1_TIM6LPENC_Pos           (4U)
32497 #define RCC_APB1LPENCR1_TIM6LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_TIM6LPENC_Pos)  /*!< 0x00000010 */
32498 #define RCC_APB1LPENCR1_TIM6LPENC               RCC_APB1LPENCR1_TIM6LPENC_Msk        /*!< TIM6 enable */
32499 #define RCC_APB1LPENCR1_TIM7LPENC_Pos           (5U)
32500 #define RCC_APB1LPENCR1_TIM7LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_TIM7LPENC_Pos)  /*!< 0x00000020 */
32501 #define RCC_APB1LPENCR1_TIM7LPENC               RCC_APB1LPENCR1_TIM7LPENC_Msk        /*!< TIM7 enable */
32502 #define RCC_APB1LPENCR1_TIM12LPENC_Pos          (6U)
32503 #define RCC_APB1LPENCR1_TIM12LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_TIM12LPENC_Pos)   /*!< 0x00000040 */
32504 #define RCC_APB1LPENCR1_TIM12LPENC              RCC_APB1LPENCR1_TIM12LPENC_Msk       /*!< TIM12 enable */
32505 #define RCC_APB1LPENCR1_TIM13LPENC_Pos          (7U)
32506 #define RCC_APB1LPENCR1_TIM13LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_TIM13LPENC_Pos)   /*!< 0x00000080 */
32507 #define RCC_APB1LPENCR1_TIM13LPENC              RCC_APB1LPENCR1_TIM13LPENC_Msk       /*!< TIM13 enable */
32508 #define RCC_APB1LPENCR1_TIM14LPENC_Pos          (8U)
32509 #define RCC_APB1LPENCR1_TIM14LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_TIM14LPENC_Pos)   /*!< 0x00000100 */
32510 #define RCC_APB1LPENCR1_TIM14LPENC              RCC_APB1LPENCR1_TIM14LPENC_Msk       /*!< TIM14 enable */
32511 #define RCC_APB1LPENCR1_LPTIM1LPENC_Pos         (9U)
32512 #define RCC_APB1LPENCR1_LPTIM1LPENC_Msk         (0x1UL << RCC_APB1LPENCR1_LPTIM1LPENC_Pos)    /*!< 0x00000200 */
32513 #define RCC_APB1LPENCR1_LPTIM1LPENC             RCC_APB1LPENCR1_LPTIM1LPENC_Msk      /*!< LPTIM1 enable */
32514 #define RCC_APB1LPENCR1_WWDGLPENC_Pos           (11U)
32515 #define RCC_APB1LPENCR1_WWDGLPENC_Msk           (0x1UL << RCC_APB1LPENCR1_WWDGLPENC_Pos)  /*!< 0x00000800 */
32516 #define RCC_APB1LPENCR1_WWDGLPENC               RCC_APB1LPENCR1_WWDGLPENC_Msk        /*!< WWDG enable */
32517 #define RCC_APB1LPENCR1_TIM10LPENC_Pos          (12U)
32518 #define RCC_APB1LPENCR1_TIM10LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_TIM10LPENC_Pos)   /*!< 0x00001000 */
32519 #define RCC_APB1LPENCR1_TIM10LPENC              RCC_APB1LPENCR1_TIM10LPENC_Msk       /*!< TIM10 enable */
32520 #define RCC_APB1LPENCR1_TIM11LPENC_Pos          (13U)
32521 #define RCC_APB1LPENCR1_TIM11LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_TIM11LPENC_Pos)   /*!< 0x00002000 */
32522 #define RCC_APB1LPENCR1_TIM11LPENC              RCC_APB1LPENCR1_TIM11LPENC_Msk       /*!< TIM11 enable */
32523 #define RCC_APB1LPENCR1_SPI2LPENC_Pos           (14U)
32524 #define RCC_APB1LPENCR1_SPI2LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_SPI2LPENC_Pos)  /*!< 0x00004000 */
32525 #define RCC_APB1LPENCR1_SPI2LPENC               RCC_APB1LPENCR1_SPI2LPENC_Msk        /*!< SPI2 enable */
32526 #define RCC_APB1LPENCR1_SPI3LPENC_Pos           (15U)
32527 #define RCC_APB1LPENCR1_SPI3LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_SPI3LPENC_Pos)  /*!< 0x00008000 */
32528 #define RCC_APB1LPENCR1_SPI3LPENC               RCC_APB1LPENCR1_SPI3LPENC_Msk        /*!< SPI3 enable */
32529 #define RCC_APB1LPENCR1_SPDIFRX1LPENC_Pos       (16U)
32530 #define RCC_APB1LPENCR1_SPDIFRX1LPENC_Msk       (0x1UL << RCC_APB1LPENCR1_SPDIFRX1LPENC_Pos)      /*!< 0x00010000 */
32531 #define RCC_APB1LPENCR1_SPDIFRX1LPENC           RCC_APB1LPENCR1_SPDIFRX1LPENC_Msk    /*!< SPDIFRX1 enable */
32532 #define RCC_APB1LPENCR1_USART2LPENC_Pos         (17U)
32533 #define RCC_APB1LPENCR1_USART2LPENC_Msk         (0x1UL << RCC_APB1LPENCR1_USART2LPENC_Pos)    /*!< 0x00020000 */
32534 #define RCC_APB1LPENCR1_USART2LPENC             RCC_APB1LPENCR1_USART2LPENC_Msk      /*!< USART2 enable */
32535 #define RCC_APB1LPENCR1_USART3LPENC_Pos         (18U)
32536 #define RCC_APB1LPENCR1_USART3LPENC_Msk         (0x1UL << RCC_APB1LPENCR1_USART3LPENC_Pos)    /*!< 0x00040000 */
32537 #define RCC_APB1LPENCR1_USART3LPENC             RCC_APB1LPENCR1_USART3LPENC_Msk      /*!< USART3 enable */
32538 #define RCC_APB1LPENCR1_UART4LPENC_Pos          (19U)
32539 #define RCC_APB1LPENCR1_UART4LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_UART4LPENC_Pos)   /*!< 0x00080000 */
32540 #define RCC_APB1LPENCR1_UART4LPENC              RCC_APB1LPENCR1_UART4LPENC_Msk       /*!< UART4 enable */
32541 #define RCC_APB1LPENCR1_UART5LPENC_Pos          (20U)
32542 #define RCC_APB1LPENCR1_UART5LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_UART5LPENC_Pos)   /*!< 0x00100000 */
32543 #define RCC_APB1LPENCR1_UART5LPENC              RCC_APB1LPENCR1_UART5LPENC_Msk       /*!< UART5 enable */
32544 #define RCC_APB1LPENCR1_I2C1LPENC_Pos           (21U)
32545 #define RCC_APB1LPENCR1_I2C1LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_I2C1LPENC_Pos)  /*!< 0x00200000 */
32546 #define RCC_APB1LPENCR1_I2C1LPENC               RCC_APB1LPENCR1_I2C1LPENC_Msk        /*!< I2C1 enable */
32547 #define RCC_APB1LPENCR1_I2C2LPENC_Pos           (22U)
32548 #define RCC_APB1LPENCR1_I2C2LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_I2C2LPENC_Pos)  /*!< 0x00400000 */
32549 #define RCC_APB1LPENCR1_I2C2LPENC               RCC_APB1LPENCR1_I2C2LPENC_Msk        /*!< I2C2 enable */
32550 #define RCC_APB1LPENCR1_I2C3LPENC_Pos           (23U)
32551 #define RCC_APB1LPENCR1_I2C3LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_I2C3LPENC_Pos)  /*!< 0x00800000 */
32552 #define RCC_APB1LPENCR1_I2C3LPENC               RCC_APB1LPENCR1_I2C3LPENC_Msk        /*!< I2C3 enable */
32553 #define RCC_APB1LPENCR1_I3C1LPENC_Pos           (24U)
32554 #define RCC_APB1LPENCR1_I3C1LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_I3C1LPENC_Pos)  /*!< 0x01000000 */
32555 #define RCC_APB1LPENCR1_I3C1LPENC               RCC_APB1LPENCR1_I3C1LPENC_Msk        /*!< I3C1 enable */
32556 #define RCC_APB1LPENCR1_I3C2LPENC_Pos           (25U)
32557 #define RCC_APB1LPENCR1_I3C2LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_I3C2LPENC_Pos)  /*!< 0x02000000 */
32558 #define RCC_APB1LPENCR1_I3C2LPENC               RCC_APB1LPENCR1_I3C2LPENC_Msk        /*!< I3C2 enable */
32559 #define RCC_APB1LPENCR1_UART7LPENC_Pos          (30U)
32560 #define RCC_APB1LPENCR1_UART7LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_UART7LPENC_Pos)   /*!< 0x40000000 */
32561 #define RCC_APB1LPENCR1_UART7LPENC              RCC_APB1LPENCR1_UART7LPENC_Msk       /*!< UART7 enable */
32562 #define RCC_APB1LPENCR1_UART8LPENC_Pos          (31U)
32563 #define RCC_APB1LPENCR1_UART8LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_UART8LPENC_Pos)   /*!< 0x80000000 */
32564 #define RCC_APB1LPENCR1_UART8LPENC              RCC_APB1LPENCR1_UART8LPENC_Msk       /*!< UART8 enable */
32565 
32566 /***************  Bit definition for RCC_APB1LPENCR2 register  ****************/
32567 #define RCC_APB1LPENCR2_MDIOSLPENC_Pos          (5U)
32568 #define RCC_APB1LPENCR2_MDIOSLPENC_Msk          (0x1UL << RCC_APB1LPENCR2_MDIOSLPENC_Pos)   /*!< 0x00000020 */
32569 #define RCC_APB1LPENCR2_MDIOSLPENC              RCC_APB1LPENCR2_MDIOSLPENC_Msk       /*!< MDIOS enable */
32570 #define RCC_APB1LPENCR2_FDCANLPENC_Pos          (8U)
32571 #define RCC_APB1LPENCR2_FDCANLPENC_Msk          (0x1UL << RCC_APB1LPENCR2_FDCANLPENC_Pos)   /*!< 0x00000100 */
32572 #define RCC_APB1LPENCR2_FDCANLPENC              RCC_APB1LPENCR2_FDCANLPENC_Msk       /*!< FDCAN enable */
32573 #define RCC_APB1LPENCR2_UCPD1LPENC_Pos          (18U)
32574 #define RCC_APB1LPENCR2_UCPD1LPENC_Msk          (0x1UL << RCC_APB1LPENCR2_UCPD1LPENC_Pos)   /*!< 0x00040000 */
32575 #define RCC_APB1LPENCR2_UCPD1LPENC              RCC_APB1LPENCR2_UCPD1LPENC_Msk       /*!< UCPD1 enable */
32576 
32577 /****************  Bit definition for RCC_APB2LPENCR register  ****************/
32578 #define RCC_APB2LPENCR_TIM1LPENC_Pos            (0U)
32579 #define RCC_APB2LPENCR_TIM1LPENC_Msk            (0x1UL << RCC_APB2LPENCR_TIM1LPENC_Pos) /*!< 0x00000001 */
32580 #define RCC_APB2LPENCR_TIM1LPENC                RCC_APB2LPENCR_TIM1LPENC_Msk         /*!< TIM1 enable */
32581 #define RCC_APB2LPENCR_TIM8LPENC_Pos            (1U)
32582 #define RCC_APB2LPENCR_TIM8LPENC_Msk            (0x1UL << RCC_APB2LPENCR_TIM8LPENC_Pos) /*!< 0x00000002 */
32583 #define RCC_APB2LPENCR_TIM8LPENC                RCC_APB2LPENCR_TIM8LPENC_Msk         /*!< TIM8 enable */
32584 #define RCC_APB2LPENCR_USART1LPENC_Pos          (4U)
32585 #define RCC_APB2LPENCR_USART1LPENC_Msk          (0x1UL << RCC_APB2LPENCR_USART1LPENC_Pos)   /*!< 0x00000010 */
32586 #define RCC_APB2LPENCR_USART1LPENC              RCC_APB2LPENCR_USART1LPENC_Msk       /*!< USART1 enable */
32587 #define RCC_APB2LPENCR_USART6LPENC_Pos          (5U)
32588 #define RCC_APB2LPENCR_USART6LPENC_Msk          (0x1UL << RCC_APB2LPENCR_USART6LPENC_Pos)   /*!< 0x00000020 */
32589 #define RCC_APB2LPENCR_USART6LPENC              RCC_APB2LPENCR_USART6LPENC_Msk       /*!< USART6 enable */
32590 #define RCC_APB2LPENCR_UART9LPENC_Pos           (6U)
32591 #define RCC_APB2LPENCR_UART9LPENC_Msk           (0x1UL << RCC_APB2LPENCR_UART9LPENC_Pos)  /*!< 0x00000040 */
32592 #define RCC_APB2LPENCR_UART9LPENC               RCC_APB2LPENCR_UART9LPENC_Msk        /*!< UART9 enable */
32593 #define RCC_APB2LPENCR_USART10LPENC_Pos         (7U)
32594 #define RCC_APB2LPENCR_USART10LPENC_Msk         (0x1UL << RCC_APB2LPENCR_USART10LPENC_Pos)    /*!< 0x00000080 */
32595 #define RCC_APB2LPENCR_USART10LPENC             RCC_APB2LPENCR_USART10LPENC_Msk      /*!< USART10 enable */
32596 #define RCC_APB2LPENCR_SPI1LPENC_Pos            (12U)
32597 #define RCC_APB2LPENCR_SPI1LPENC_Msk            (0x1UL << RCC_APB2LPENCR_SPI1LPENC_Pos) /*!< 0x00001000 */
32598 #define RCC_APB2LPENCR_SPI1LPENC                RCC_APB2LPENCR_SPI1LPENC_Msk         /*!< SPI1 enable */
32599 #define RCC_APB2LPENCR_SPI4LPENC_Pos            (13U)
32600 #define RCC_APB2LPENCR_SPI4LPENC_Msk            (0x1UL << RCC_APB2LPENCR_SPI4LPENC_Pos) /*!< 0x00002000 */
32601 #define RCC_APB2LPENCR_SPI4LPENC                RCC_APB2LPENCR_SPI4LPENC_Msk         /*!< SPI4 enable */
32602 #define RCC_APB2LPENCR_TIM18LPENC_Pos           (15U)
32603 #define RCC_APB2LPENCR_TIM18LPENC_Msk           (0x1UL << RCC_APB2LPENCR_TIM18LPENC_Pos)  /*!< 0x00008000 */
32604 #define RCC_APB2LPENCR_TIM18LPENC               RCC_APB2LPENCR_TIM18LPENC_Msk        /*!< TIM18 enable */
32605 #define RCC_APB2LPENCR_TIM15LPENC_Pos           (16U)
32606 #define RCC_APB2LPENCR_TIM15LPENC_Msk           (0x1UL << RCC_APB2LPENCR_TIM15LPENC_Pos)  /*!< 0x00010000 */
32607 #define RCC_APB2LPENCR_TIM15LPENC               RCC_APB2LPENCR_TIM15LPENC_Msk        /*!< TIM15 enable */
32608 #define RCC_APB2LPENCR_TIM16LPENC_Pos           (17U)
32609 #define RCC_APB2LPENCR_TIM16LPENC_Msk           (0x1UL << RCC_APB2LPENCR_TIM16LPENC_Pos)  /*!< 0x00020000 */
32610 #define RCC_APB2LPENCR_TIM16LPENC               RCC_APB2LPENCR_TIM16LPENC_Msk        /*!< TIM16 enable */
32611 #define RCC_APB2LPENCR_TIM17LPENC_Pos           (18U)
32612 #define RCC_APB2LPENCR_TIM17LPENC_Msk           (0x1UL << RCC_APB2LPENCR_TIM17LPENC_Pos)  /*!< 0x00040000 */
32613 #define RCC_APB2LPENCR_TIM17LPENC               RCC_APB2LPENCR_TIM17LPENC_Msk        /*!< TIM17 enable */
32614 #define RCC_APB2LPENCR_TIM9LPENC_Pos            (19U)
32615 #define RCC_APB2LPENCR_TIM9LPENC_Msk            (0x1UL << RCC_APB2LPENCR_TIM9LPENC_Pos) /*!< 0x00080000 */
32616 #define RCC_APB2LPENCR_TIM9LPENC                RCC_APB2LPENCR_TIM9LPENC_Msk         /*!< TIM9 enable */
32617 #define RCC_APB2LPENCR_SPI5LPENC_Pos            (20U)
32618 #define RCC_APB2LPENCR_SPI5LPENC_Msk            (0x1UL << RCC_APB2LPENCR_SPI5LPENC_Pos) /*!< 0x00100000 */
32619 #define RCC_APB2LPENCR_SPI5LPENC                RCC_APB2LPENCR_SPI5LPENC_Msk         /*!< SPI5 enable */
32620 #define RCC_APB2LPENCR_SAI1LPENC_Pos            (21U)
32621 #define RCC_APB2LPENCR_SAI1LPENC_Msk            (0x1UL << RCC_APB2LPENCR_SAI1LPENC_Pos) /*!< 0x00200000 */
32622 #define RCC_APB2LPENCR_SAI1LPENC                RCC_APB2LPENCR_SAI1LPENC_Msk         /*!< SAI1 enable */
32623 #define RCC_APB2LPENCR_SAI2LPENC_Pos            (22U)
32624 #define RCC_APB2LPENCR_SAI2LPENC_Msk            (0x1UL << RCC_APB2LPENCR_SAI2LPENC_Pos) /*!< 0x00400000 */
32625 #define RCC_APB2LPENCR_SAI2LPENC                RCC_APB2LPENCR_SAI2LPENC_Msk         /*!< SAI2 enable */
32626 
32627 /****************  Bit definition for RCC_APB3LPENCR register  ****************/
32628 #define RCC_APB3LPENCR_DFTLPENC_Pos             (2U)
32629 #define RCC_APB3LPENCR_DFTLPENC_Msk             (0x1UL << RCC_APB3LPENCR_DFTLPENC_Pos)/*!< 0x00000004 */
32630 #define RCC_APB3LPENCR_DFTLPENC                 RCC_APB3LPENCR_DFTLPENC_Msk          /*!< DFT enable */
32631 
32632 /***************  Bit definition for RCC_APB4LPENCR1 register  ****************/
32633 #define RCC_APB4LPENCR1_HDPLPENC_Pos            (2U)
32634 #define RCC_APB4LPENCR1_HDPLPENC_Msk            (0x1UL << RCC_APB4LPENCR1_HDPLPENC_Pos) /*!< 0x00000004 */
32635 #define RCC_APB4LPENCR1_HDPLPENC                RCC_APB4LPENCR1_HDPLPENC_Msk         /*!< HDP enable */
32636 #define RCC_APB4LPENCR1_LPUART1LPENC_Pos        (3U)
32637 #define RCC_APB4LPENCR1_LPUART1LPENC_Msk        (0x1UL << RCC_APB4LPENCR1_LPUART1LPENC_Pos)     /*!< 0x00000008 */
32638 #define RCC_APB4LPENCR1_LPUART1LPENC            RCC_APB4LPENCR1_LPUART1LPENC_Msk     /*!< LPUART1 enable */
32639 #define RCC_APB4LPENCR1_SPI6LPENC_Pos           (5U)
32640 #define RCC_APB4LPENCR1_SPI6LPENC_Msk           (0x1UL << RCC_APB4LPENCR1_SPI6LPENC_Pos)  /*!< 0x00000020 */
32641 #define RCC_APB4LPENCR1_SPI6LPENC               RCC_APB4LPENCR1_SPI6LPENC_Msk        /*!< SPI6 enable */
32642 #define RCC_APB4LPENCR1_I2C4LPENC_Pos           (7U)
32643 #define RCC_APB4LPENCR1_I2C4LPENC_Msk           (0x1UL << RCC_APB4LPENCR1_I2C4LPENC_Pos)  /*!< 0x00000080 */
32644 #define RCC_APB4LPENCR1_I2C4LPENC               RCC_APB4LPENCR1_I2C4LPENC_Msk        /*!< I2C4 enable */
32645 #define RCC_APB4LPENCR1_LPTIM2LPENC_Pos         (9U)
32646 #define RCC_APB4LPENCR1_LPTIM2LPENC_Msk         (0x1UL << RCC_APB4LPENCR1_LPTIM2LPENC_Pos)    /*!< 0x00000200 */
32647 #define RCC_APB4LPENCR1_LPTIM2LPENC             RCC_APB4LPENCR1_LPTIM2LPENC_Msk      /*!< LPTIM2 enable */
32648 #define RCC_APB4LPENCR1_LPTIM3LPENC_Pos         (10U)
32649 #define RCC_APB4LPENCR1_LPTIM3LPENC_Msk         (0x1UL << RCC_APB4LPENCR1_LPTIM3LPENC_Pos)    /*!< 0x00000400 */
32650 #define RCC_APB4LPENCR1_LPTIM3LPENC             RCC_APB4LPENCR1_LPTIM3LPENC_Msk      /*!< LPTIM3 enable */
32651 #define RCC_APB4LPENCR1_LPTIM4LPENC_Pos         (11U)
32652 #define RCC_APB4LPENCR1_LPTIM4LPENC_Msk         (0x1UL << RCC_APB4LPENCR1_LPTIM4LPENC_Pos)    /*!< 0x00000800 */
32653 #define RCC_APB4LPENCR1_LPTIM4LPENC             RCC_APB4LPENCR1_LPTIM4LPENC_Msk      /*!< LPTIM4 enable */
32654 #define RCC_APB4LPENCR1_LPTIM5LPENC_Pos         (12U)
32655 #define RCC_APB4LPENCR1_LPTIM5LPENC_Msk         (0x1UL << RCC_APB4LPENCR1_LPTIM5LPENC_Pos)    /*!< 0x00001000 */
32656 #define RCC_APB4LPENCR1_LPTIM5LPENC             RCC_APB4LPENCR1_LPTIM5LPENC_Msk      /*!< LPTIM5 enable */
32657 #define RCC_APB4LPENCR1_VREFBUFLPENC_Pos        (15U)
32658 #define RCC_APB4LPENCR1_VREFBUFLPENC_Msk        (0x1UL << RCC_APB4LPENCR1_VREFBUFLPENC_Pos)     /*!< 0x00008000 */
32659 #define RCC_APB4LPENCR1_VREFBUFLPENC            RCC_APB4LPENCR1_VREFBUFLPENC_Msk     /*!< VREFBUF enable */
32660 #define RCC_APB4LPENCR1_RTCLPENC_Pos            (16U)
32661 #define RCC_APB4LPENCR1_RTCLPENC_Msk            (0x1UL << RCC_APB4LPENCR1_RTCLPENC_Pos) /*!< 0x00010000 */
32662 #define RCC_APB4LPENCR1_RTCLPENC                RCC_APB4LPENCR1_RTCLPENC_Msk         /*!< RTC enable */
32663 #define RCC_APB4LPENCR1_RTCAPBLPENC_Pos         (17U)
32664 #define RCC_APB4LPENCR1_RTCAPBLPENC_Msk         (0x1UL << RCC_APB4LPENCR1_RTCAPBLPENC_Pos)    /*!< 0x00020000 */
32665 #define RCC_APB4LPENCR1_RTCAPBLPENC             RCC_APB4LPENCR1_RTCAPBLPENC_Msk      /*!< RTCAPB enable */
32666 
32667 /***************  Bit definition for RCC_APB4LPENCR2 register  ****************/
32668 #define RCC_APB4LPENCR2_SYSCFGLPENC_Pos         (0U)
32669 #define RCC_APB4LPENCR2_SYSCFGLPENC_Msk         (0x1UL << RCC_APB4LPENCR2_SYSCFGLPENC_Pos)    /*!< 0x00000001 */
32670 #define RCC_APB4LPENCR2_SYSCFGLPENC             RCC_APB4LPENCR2_SYSCFGLPENC_Msk      /*!< SYSCFG enable */
32671 #define RCC_APB4LPENCR2_BSECLPENC_Pos           (1U)
32672 #define RCC_APB4LPENCR2_BSECLPENC_Msk           (0x1UL << RCC_APB4LPENCR2_BSECLPENC_Pos)  /*!< 0x00000002 */
32673 #define RCC_APB4LPENCR2_BSECLPENC               RCC_APB4LPENCR2_BSECLPENC_Msk        /*!< BSEC enable */
32674 #define RCC_APB4LPENCR2_DTSLPENC_Pos            (2U)
32675 #define RCC_APB4LPENCR2_DTSLPENC_Msk            (0x1UL << RCC_APB4LPENCR2_DTSLPENC_Pos) /*!< 0x00000004 */
32676 #define RCC_APB4LPENCR2_DTSLPENC                RCC_APB4LPENCR2_DTSLPENC_Msk         /*!< DTS enable */
32677 
32678 /****************  Bit definition for RCC_APB5LPENCR register  ****************/
32679 #define RCC_APB5LPENCR_LTDCLPENC_Pos            (1U)
32680 #define RCC_APB5LPENCR_LTDCLPENC_Msk            (0x1UL << RCC_APB5LPENCR_LTDCLPENC_Pos) /*!< 0x00000002 */
32681 #define RCC_APB5LPENCR_LTDCLPENC                RCC_APB5LPENCR_LTDCLPENC_Msk         /*!< LTDC sleep enable */
32682 #define RCC_APB5LPENCR_DCMIPPLPENC_Pos          (2U)
32683 #define RCC_APB5LPENCR_DCMIPPLPENC_Msk          (0x1UL << RCC_APB5LPENCR_DCMIPPLPENC_Pos)   /*!< 0x00000004 */
32684 #define RCC_APB5LPENCR_DCMIPPLPENC              RCC_APB5LPENCR_DCMIPPLPENC_Msk       /*!< DCMIPP sleep enable */
32685 #define RCC_APB5LPENCR_GFXTIMLPENC_Pos          (4U)
32686 #define RCC_APB5LPENCR_GFXTIMLPENC_Msk          (0x1UL << RCC_APB5LPENCR_GFXTIMLPENC_Pos)   /*!< 0x00000010 */
32687 #define RCC_APB5LPENCR_GFXTIMLPENC              RCC_APB5LPENCR_GFXTIMLPENC_Msk       /*!< GFXTIM sleep enable */
32688 #define RCC_APB5LPENCR_VENCLPENC_Pos            (5U)
32689 #define RCC_APB5LPENCR_VENCLPENC_Msk            (0x1UL << RCC_APB5LPENCR_VENCLPENC_Pos) /*!< 0x00000020 */
32690 #define RCC_APB5LPENCR_VENCLPENC                RCC_APB5LPENCR_VENCLPENC_Msk         /*!< VENC sleep enable */
32691 #define RCC_APB5LPENCR_CSILPENC_Pos             (6U)
32692 #define RCC_APB5LPENCR_CSILPENC_Msk             (0x1UL << RCC_APB5LPENCR_CSILPENC_Pos)/*!< 0x00000040 */
32693 #define RCC_APB5LPENCR_CSILPENC                 RCC_APB5LPENCR_CSILPENC_Msk          /*!< CSI sleep enable */
32694 
32695 /****************  Bit definition for RCC_PRIVCFGCR0 register  ****************/
32696 #define RCC_PRIVCFGCR0_LSIPRIVC_Pos             (0U)
32697 #define RCC_PRIVCFGCR0_LSIPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR0_LSIPRIVC_Pos)/*!< 0x00000001 */
32698 #define RCC_PRIVCFGCR0_LSIPRIVC                 RCC_PRIVCFGCR0_LSIPRIVC_Msk          /*!< Privileged protection of LSI configuration bits (enable, ready, divider) */
32699 #define RCC_PRIVCFGCR0_LSEPRIVC_Pos             (1U)
32700 #define RCC_PRIVCFGCR0_LSEPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR0_LSEPRIVC_Pos)/*!< 0x00000002 */
32701 #define RCC_PRIVCFGCR0_LSEPRIVC                 RCC_PRIVCFGCR0_LSEPRIVC_Msk          /*!< Privileged protection of LSE configuration bits (enable, ready, divider) */
32702 #define RCC_PRIVCFGCR0_MSIPRIVC_Pos             (2U)
32703 #define RCC_PRIVCFGCR0_MSIPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR0_MSIPRIVC_Pos)/*!< 0x00000004 */
32704 #define RCC_PRIVCFGCR0_MSIPRIVC                 RCC_PRIVCFGCR0_MSIPRIVC_Msk          /*!< Privileged protection of MSI configuration bits (enable, ready, divider) */
32705 #define RCC_PRIVCFGCR0_HSIPRIVC_Pos             (3U)
32706 #define RCC_PRIVCFGCR0_HSIPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR0_HSIPRIVC_Pos)/*!< 0x00000008 */
32707 #define RCC_PRIVCFGCR0_HSIPRIVC                 RCC_PRIVCFGCR0_HSIPRIVC_Msk          /*!< Privileged protection of HSI configuration bits (enable, ready, divider) */
32708 #define RCC_PRIVCFGCR0_HSEPRIVC_Pos             (4U)
32709 #define RCC_PRIVCFGCR0_HSEPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR0_HSEPRIVC_Pos)/*!< 0x00000010 */
32710 #define RCC_PRIVCFGCR0_HSEPRIVC                 RCC_PRIVCFGCR0_HSEPRIVC_Msk          /*!< Privileged protection of HSE configuration bits (enable, ready, divider) */
32711 
32712 /****************  Bit definition for RCC_PUBCFGCR0 register  *****************/
32713 #define RCC_PUBCFGCR0_LSIPUBC_Pos               (0U)
32714 #define RCC_PUBCFGCR0_LSIPUBC_Msk               (0x1UL << RCC_PUBCFGCR0_LSIPUBC_Pos)  /*!< 0x00000001 */
32715 #define RCC_PUBCFGCR0_LSIPUBC                   RCC_PUBCFGCR0_LSIPUBC_Msk            /*!< Public protection of LSI configuration bits (enable, ready, divider) */
32716 #define RCC_PUBCFGCR0_LSEPUBC_Pos               (1U)
32717 #define RCC_PUBCFGCR0_LSEPUBC_Msk               (0x1UL << RCC_PUBCFGCR0_LSEPUBC_Pos)  /*!< 0x00000002 */
32718 #define RCC_PUBCFGCR0_LSEPUBC                   RCC_PUBCFGCR0_LSEPUBC_Msk            /*!< Public protection of LSE configuration bits (enable, ready, divider) */
32719 #define RCC_PUBCFGCR0_MSIPUBC_Pos               (2U)
32720 #define RCC_PUBCFGCR0_MSIPUBC_Msk               (0x1UL << RCC_PUBCFGCR0_MSIPUBC_Pos)  /*!< 0x00000004 */
32721 #define RCC_PUBCFGCR0_MSIPUBC                   RCC_PUBCFGCR0_MSIPUBC_Msk            /*!< Public protection of MSI configuration bits (enable, ready, divider) */
32722 #define RCC_PUBCFGCR0_HSIPUBC_Pos               (3U)
32723 #define RCC_PUBCFGCR0_HSIPUBC_Msk               (0x1UL << RCC_PUBCFGCR0_HSIPUBC_Pos)  /*!< 0x00000008 */
32724 #define RCC_PUBCFGCR0_HSIPUBC                   RCC_PUBCFGCR0_HSIPUBC_Msk            /*!< Public protection of HSI configuration bits (enable, ready, divider) */
32725 #define RCC_PUBCFGCR0_HSEPUBC_Pos               (4U)
32726 #define RCC_PUBCFGCR0_HSEPUBC_Msk               (0x1UL << RCC_PUBCFGCR0_HSEPUBC_Pos)  /*!< 0x00000010 */
32727 #define RCC_PUBCFGCR0_HSEPUBC                   RCC_PUBCFGCR0_HSEPUBC_Msk            /*!< Public protection of HSE configuration bits (enable, ready, divider) */
32728 
32729 /****************  Bit definition for RCC_PRIVCFGCR1 register  ****************/
32730 #define RCC_PRIVCFGCR1_PLL1PRIVC_Pos            (0U)
32731 #define RCC_PRIVCFGCR1_PLL1PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR1_PLL1PRIVC_Pos) /*!< 0x00000001 */
32732 #define RCC_PRIVCFGCR1_PLL1PRIVC                RCC_PRIVCFGCR1_PLL1PRIVC_Msk         /*!< Privileged protection of PLL1 configuration bits (enable, ready, divider) */
32733 #define RCC_PRIVCFGCR1_PLL2PRIVC_Pos            (1U)
32734 #define RCC_PRIVCFGCR1_PLL2PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR1_PLL2PRIVC_Pos) /*!< 0x00000002 */
32735 #define RCC_PRIVCFGCR1_PLL2PRIVC                RCC_PRIVCFGCR1_PLL2PRIVC_Msk         /*!< Privileged protection of PLL2 configuration bits (enable, ready, divider) */
32736 #define RCC_PRIVCFGCR1_PLL3PRIVC_Pos            (2U)
32737 #define RCC_PRIVCFGCR1_PLL3PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR1_PLL3PRIVC_Pos) /*!< 0x00000004 */
32738 #define RCC_PRIVCFGCR1_PLL3PRIVC                RCC_PRIVCFGCR1_PLL3PRIVC_Msk         /*!< Privileged protection of PLL3 configuration bits (enable, ready, divider) */
32739 #define RCC_PRIVCFGCR1_PLL4PRIVC_Pos            (3U)
32740 #define RCC_PRIVCFGCR1_PLL4PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR1_PLL4PRIVC_Pos) /*!< 0x00000008 */
32741 #define RCC_PRIVCFGCR1_PLL4PRIVC                RCC_PRIVCFGCR1_PLL4PRIVC_Msk         /*!< Privileged protection of PLL4 configuration bits (enable, ready, divider) */
32742 
32743 /****************  Bit definition for RCC_PUBCFGCR1 register  *****************/
32744 #define RCC_PUBCFGCR1_PLL1PUBC_Pos              (0U)
32745 #define RCC_PUBCFGCR1_PLL1PUBC_Msk              (0x1UL << RCC_PUBCFGCR1_PLL1PUBC_Pos) /*!< 0x00000001 */
32746 #define RCC_PUBCFGCR1_PLL1PUBC                  RCC_PUBCFGCR1_PLL1PUBC_Msk           /*!< Public protection of th PLL1 configuration bits (enable, ready, divider) */
32747 #define RCC_PUBCFGCR1_PLL2PUBC_Pos              (1U)
32748 #define RCC_PUBCFGCR1_PLL2PUBC_Msk              (0x1UL << RCC_PUBCFGCR1_PLL2PUBC_Pos) /*!< 0x00000002 */
32749 #define RCC_PUBCFGCR1_PLL2PUBC                  RCC_PUBCFGCR1_PLL2PUBC_Msk           /*!< Public protection of te PLL2 configuration bits (enable, ready, divider) */
32750 #define RCC_PUBCFGCR1_PLL3PUBC_Pos              (2U)
32751 #define RCC_PUBCFGCR1_PLL3PUBC_Msk              (0x1UL << RCC_PUBCFGCR1_PLL3PUBC_Pos) /*!< 0x00000004 */
32752 #define RCC_PUBCFGCR1_PLL3PUBC                  RCC_PUBCFGCR1_PLL3PUBC_Msk           /*!< Public protection of PLL3 configuration bits (enable, ready, divider) */
32753 #define RCC_PUBCFGCR1_PLL4PUBC_Pos              (3U)
32754 #define RCC_PUBCFGCR1_PLL4PUBC_Msk              (0x1UL << RCC_PUBCFGCR1_PLL4PUBC_Pos) /*!< 0x00000008 */
32755 #define RCC_PUBCFGCR1_PLL4PUBC                  RCC_PUBCFGCR1_PLL4PUBC_Msk           /*!< Public protection of PLL4 configuration bits (enable, ready, divider) */
32756 
32757 /****************  Bit definition for RCC_PRIVCFGCR2 register  ****************/
32758 #define RCC_PRIVCFGCR2_IC1PRIVC_Pos             (0U)
32759 #define RCC_PRIVCFGCR2_IC1PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC1PRIVC_Pos)/*!< 0x00000001 */
32760 #define RCC_PRIVCFGCR2_IC1PRIVC                 RCC_PRIVCFGCR2_IC1PRIVC_Msk          /*!< Privileged protection of the IC1 configuration bits (enable, ready, divider) */
32761 #define RCC_PRIVCFGCR2_IC2PRIVC_Pos             (1U)
32762 #define RCC_PRIVCFGCR2_IC2PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC2PRIVC_Pos)/*!< 0x00000002 */
32763 #define RCC_PRIVCFGCR2_IC2PRIVC                 RCC_PRIVCFGCR2_IC2PRIVC_Msk          /*!< Privileged protection of the IC2 configuration bits (enable, ready, divider) */
32764 #define RCC_PRIVCFGCR2_IC3PRIVC_Pos             (2U)
32765 #define RCC_PRIVCFGCR2_IC3PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC3PRIVC_Pos)/*!< 0x00000004 */
32766 #define RCC_PRIVCFGCR2_IC3PRIVC                 RCC_PRIVCFGCR2_IC3PRIVC_Msk          /*!< Privileged protection of the IC3 configuration bits (enable, ready, divider) */
32767 #define RCC_PRIVCFGCR2_IC4PRIVC_Pos             (3U)
32768 #define RCC_PRIVCFGCR2_IC4PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC4PRIVC_Pos)/*!< 0x00000008 */
32769 #define RCC_PRIVCFGCR2_IC4PRIVC                 RCC_PRIVCFGCR2_IC4PRIVC_Msk          /*!< Privileged protection of the IC4 configuration bits (enable, ready, divider) */
32770 #define RCC_PRIVCFGCR2_IC5PRIVC_Pos             (4U)
32771 #define RCC_PRIVCFGCR2_IC5PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC5PRIVC_Pos)/*!< 0x00000010 */
32772 #define RCC_PRIVCFGCR2_IC5PRIVC                 RCC_PRIVCFGCR2_IC5PRIVC_Msk          /*!< Privileged protection of the IC5 configuration bits (enable, ready, divider) */
32773 #define RCC_PRIVCFGCR2_IC6PRIVC_Pos             (5U)
32774 #define RCC_PRIVCFGCR2_IC6PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC6PRIVC_Pos)/*!< 0x00000020 */
32775 #define RCC_PRIVCFGCR2_IC6PRIVC                 RCC_PRIVCFGCR2_IC6PRIVC_Msk          /*!< Privileged protection of IC6 configuration bits (enable, ready, divider) */
32776 #define RCC_PRIVCFGCR2_IC7PRIVC_Pos             (6U)
32777 #define RCC_PRIVCFGCR2_IC7PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC7PRIVC_Pos)/*!< 0x00000040 */
32778 #define RCC_PRIVCFGCR2_IC7PRIVC                 RCC_PRIVCFGCR2_IC7PRIVC_Msk          /*!< Privileged protection of IC7 configuration bits (enable, ready, divider) */
32779 #define RCC_PRIVCFGCR2_IC8PRIVC_Pos             (7U)
32780 #define RCC_PRIVCFGCR2_IC8PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC8PRIVC_Pos)/*!< 0x00000080 */
32781 #define RCC_PRIVCFGCR2_IC8PRIVC                 RCC_PRIVCFGCR2_IC8PRIVC_Msk          /*!< Privileged protection of IC8 configuration bits (enable, ready, divider) */
32782 #define RCC_PRIVCFGCR2_IC9PRIVC_Pos             (8U)
32783 #define RCC_PRIVCFGCR2_IC9PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC9PRIVC_Pos)/*!< 0x00000100 */
32784 #define RCC_PRIVCFGCR2_IC9PRIVC                 RCC_PRIVCFGCR2_IC9PRIVC_Msk          /*!< Privileged protection of IC9 configuration bits (enable, ready, divider) */
32785 #define RCC_PRIVCFGCR2_IC10PRIVC_Pos            (9U)
32786 #define RCC_PRIVCFGCR2_IC10PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC10PRIVC_Pos) /*!< 0x00000200 */
32787 #define RCC_PRIVCFGCR2_IC10PRIVC                RCC_PRIVCFGCR2_IC10PRIVC_Msk         /*!< Privileged protection of IC10 configuration bits (enable, ready, divider) */
32788 #define RCC_PRIVCFGCR2_IC11PRIVC_Pos            (10U)
32789 #define RCC_PRIVCFGCR2_IC11PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC11PRIVC_Pos) /*!< 0x00000400 */
32790 #define RCC_PRIVCFGCR2_IC11PRIVC                RCC_PRIVCFGCR2_IC11PRIVC_Msk         /*!< Privileged protection of IC11 configuration bits (enable, ready, divider) */
32791 #define RCC_PRIVCFGCR2_IC12PRIVC_Pos            (11U)
32792 #define RCC_PRIVCFGCR2_IC12PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC12PRIVC_Pos) /*!< 0x00000800 */
32793 #define RCC_PRIVCFGCR2_IC12PRIVC                RCC_PRIVCFGCR2_IC12PRIVC_Msk         /*!< Privileged protection of IC12 configuration bits (enable, ready, divider) */
32794 #define RCC_PRIVCFGCR2_IC13PRIVC_Pos            (12U)
32795 #define RCC_PRIVCFGCR2_IC13PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC13PRIVC_Pos) /*!< 0x00001000 */
32796 #define RCC_PRIVCFGCR2_IC13PRIVC                RCC_PRIVCFGCR2_IC13PRIVC_Msk         /*!< Privileged protection of IC13 configuration bits (enable, ready, divider) */
32797 #define RCC_PRIVCFGCR2_IC14PRIVC_Pos            (13U)
32798 #define RCC_PRIVCFGCR2_IC14PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC14PRIVC_Pos) /*!< 0x00002000 */
32799 #define RCC_PRIVCFGCR2_IC14PRIVC                RCC_PRIVCFGCR2_IC14PRIVC_Msk         /*!< Privileged protection of IC14 configuration bits (enable, ready, divider) */
32800 #define RCC_PRIVCFGCR2_IC15PRIVC_Pos            (14U)
32801 #define RCC_PRIVCFGCR2_IC15PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC15PRIVC_Pos) /*!< 0x00004000 */
32802 #define RCC_PRIVCFGCR2_IC15PRIVC                RCC_PRIVCFGCR2_IC15PRIVC_Msk         /*!< Privileged protection of IC15 configuration bits (enable, ready, divider) */
32803 #define RCC_PRIVCFGCR2_IC16PRIVC_Pos            (15U)
32804 #define RCC_PRIVCFGCR2_IC16PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC16PRIVC_Pos) /*!< 0x00008000 */
32805 #define RCC_PRIVCFGCR2_IC16PRIVC                RCC_PRIVCFGCR2_IC16PRIVC_Msk         /*!< Privileged protection of IC16 configuration bits (enable, ready, divider) */
32806 #define RCC_PRIVCFGCR2_IC17PRIVC_Pos            (16U)
32807 #define RCC_PRIVCFGCR2_IC17PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC17PRIVC_Pos) /*!< 0x00010000 */
32808 #define RCC_PRIVCFGCR2_IC17PRIVC                RCC_PRIVCFGCR2_IC17PRIVC_Msk         /*!< Privileged protection of IC17 configuration bits (enable, ready, divider) */
32809 #define RCC_PRIVCFGCR2_IC18PRIVC_Pos            (17U)
32810 #define RCC_PRIVCFGCR2_IC18PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC18PRIVC_Pos) /*!< 0x00020000 */
32811 #define RCC_PRIVCFGCR2_IC18PRIVC                RCC_PRIVCFGCR2_IC18PRIVC_Msk         /*!< Privileged protection of IC18 configuration bits (enable, ready, divider) */
32812 #define RCC_PRIVCFGCR2_IC19PRIVC_Pos            (18U)
32813 #define RCC_PRIVCFGCR2_IC19PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC19PRIVC_Pos) /*!< 0x00040000 */
32814 #define RCC_PRIVCFGCR2_IC19PRIVC                RCC_PRIVCFGCR2_IC19PRIVC_Msk         /*!< Privileged protection of IC19 configuration bits (enable, ready, divider) */
32815 #define RCC_PRIVCFGCR2_IC20PRIVC_Pos            (19U)
32816 #define RCC_PRIVCFGCR2_IC20PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC20PRIVC_Pos) /*!< 0x00080000 */
32817 #define RCC_PRIVCFGCR2_IC20PRIVC                RCC_PRIVCFGCR2_IC20PRIVC_Msk         /*!< Privileged protection of IC20 configuration bits (enable, ready, divider) */
32818 
32819 /****************  Bit definition for RCC_PUBCFGCR2 register  *****************/
32820 #define RCC_PUBCFGCR2_IC1PUBC_Pos               (0U)
32821 #define RCC_PUBCFGCR2_IC1PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC1PUBC_Pos)  /*!< 0x00000001 */
32822 #define RCC_PUBCFGCR2_IC1PUBC                   RCC_PUBCFGCR2_IC1PUBC_Msk            /*!< Public protection of IC1 configuration bits (enable, ready, divider) */
32823 #define RCC_PUBCFGCR2_IC2PUBC_Pos               (1U)
32824 #define RCC_PUBCFGCR2_IC2PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC2PUBC_Pos)  /*!< 0x00000002 */
32825 #define RCC_PUBCFGCR2_IC2PUBC                   RCC_PUBCFGCR2_IC2PUBC_Msk            /*!< Public protection of IC2 configuration bits (enable, ready, divider) */
32826 #define RCC_PUBCFGCR2_IC3PUBC_Pos               (2U)
32827 #define RCC_PUBCFGCR2_IC3PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC3PUBC_Pos)  /*!< 0x00000004 */
32828 #define RCC_PUBCFGCR2_IC3PUBC                   RCC_PUBCFGCR2_IC3PUBC_Msk            /*!< Public protection of IC3 configuration bits (enable, ready, divider) */
32829 #define RCC_PUBCFGCR2_IC4PUBC_Pos               (3U)
32830 #define RCC_PUBCFGCR2_IC4PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC4PUBC_Pos)  /*!< 0x00000008 */
32831 #define RCC_PUBCFGCR2_IC4PUBC                   RCC_PUBCFGCR2_IC4PUBC_Msk            /*!< Public protection of IC4 configuration bits (enable, ready, divider) */
32832 #define RCC_PUBCFGCR2_IC5PUBC_Pos               (4U)
32833 #define RCC_PUBCFGCR2_IC5PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC5PUBC_Pos)  /*!< 0x00000010 */
32834 #define RCC_PUBCFGCR2_IC5PUBC                   RCC_PUBCFGCR2_IC5PUBC_Msk            /*!< Public protection of IC5 configuration bits (enable, ready, divider) */
32835 #define RCC_PUBCFGCR2_IC6PUBC_Pos               (5U)
32836 #define RCC_PUBCFGCR2_IC6PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC6PUBC_Pos)  /*!< 0x00000020 */
32837 #define RCC_PUBCFGCR2_IC6PUBC                   RCC_PUBCFGCR2_IC6PUBC_Msk            /*!< Public protection of IC6 configuration bits (enable, ready, divider) */
32838 #define RCC_PUBCFGCR2_IC7PUBC_Pos               (6U)
32839 #define RCC_PUBCFGCR2_IC7PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC7PUBC_Pos)  /*!< 0x00000040 */
32840 #define RCC_PUBCFGCR2_IC7PUBC                   RCC_PUBCFGCR2_IC7PUBC_Msk            /*!< Public protection of IC7 configuration bits (enable, ready, divider) */
32841 #define RCC_PUBCFGCR2_IC8PUBC_Pos               (7U)
32842 #define RCC_PUBCFGCR2_IC8PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC8PUBC_Pos)  /*!< 0x00000080 */
32843 #define RCC_PUBCFGCR2_IC8PUBC                   RCC_PUBCFGCR2_IC8PUBC_Msk            /*!< Public protection of IC8 configuration bits (enable, ready, divider) */
32844 #define RCC_PUBCFGCR2_IC9PUBC_Pos               (8U)
32845 #define RCC_PUBCFGCR2_IC9PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC9PUBC_Pos)  /*!< 0x00000100 */
32846 #define RCC_PUBCFGCR2_IC9PUBC                   RCC_PUBCFGCR2_IC9PUBC_Msk            /*!< Public protection of IC9 configuration bits (enable, ready, divider) */
32847 #define RCC_PUBCFGCR2_IC10PUBC_Pos              (9U)
32848 #define RCC_PUBCFGCR2_IC10PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC10PUBC_Pos) /*!< 0x00000200 */
32849 #define RCC_PUBCFGCR2_IC10PUBC                  RCC_PUBCFGCR2_IC10PUBC_Msk           /*!< Public protection of IC10 configuration bits (enable, ready, divider) */
32850 #define RCC_PUBCFGCR2_IC11PUBC_Pos              (10U)
32851 #define RCC_PUBCFGCR2_IC11PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC11PUBC_Pos) /*!< 0x00000400 */
32852 #define RCC_PUBCFGCR2_IC11PUBC                  RCC_PUBCFGCR2_IC11PUBC_Msk           /*!< Public protection of IC11 configuration bits (enable, ready, divider) */
32853 #define RCC_PUBCFGCR2_IC12PUBC_Pos              (11U)
32854 #define RCC_PUBCFGCR2_IC12PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC12PUBC_Pos) /*!< 0x00000800 */
32855 #define RCC_PUBCFGCR2_IC12PUBC                  RCC_PUBCFGCR2_IC12PUBC_Msk           /*!< Public protection of IC12 configuration bits (enable, ready, divider) */
32856 #define RCC_PUBCFGCR2_IC13PUBC_Pos              (12U)
32857 #define RCC_PUBCFGCR2_IC13PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC13PUBC_Pos) /*!< 0x00001000 */
32858 #define RCC_PUBCFGCR2_IC13PUBC                  RCC_PUBCFGCR2_IC13PUBC_Msk           /*!< Public protection of IC13 configuration bits (enable, ready, divider) */
32859 #define RCC_PUBCFGCR2_IC14PUBC_Pos              (13U)
32860 #define RCC_PUBCFGCR2_IC14PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC14PUBC_Pos) /*!< 0x00002000 */
32861 #define RCC_PUBCFGCR2_IC14PUBC                  RCC_PUBCFGCR2_IC14PUBC_Msk           /*!< Public protection of IC14 configuration bits (enable, ready, divider) */
32862 #define RCC_PUBCFGCR2_IC15PUBC_Pos              (14U)
32863 #define RCC_PUBCFGCR2_IC15PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC15PUBC_Pos) /*!< 0x00004000 */
32864 #define RCC_PUBCFGCR2_IC15PUBC                  RCC_PUBCFGCR2_IC15PUBC_Msk           /*!< Public protection of IC15 configuration bits (enable, ready, divider) */
32865 #define RCC_PUBCFGCR2_IC16PUBC_Pos              (15U)
32866 #define RCC_PUBCFGCR2_IC16PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC16PUBC_Pos) /*!< 0x00008000 */
32867 #define RCC_PUBCFGCR2_IC16PUBC                  RCC_PUBCFGCR2_IC16PUBC_Msk           /*!< Public protection of IC16 configuration bits (enable, ready, divider) */
32868 #define RCC_PUBCFGCR2_IC17PUBC_Pos              (16U)
32869 #define RCC_PUBCFGCR2_IC17PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC17PUBC_Pos) /*!< 0x00010000 */
32870 #define RCC_PUBCFGCR2_IC17PUBC                  RCC_PUBCFGCR2_IC17PUBC_Msk           /*!< Public protection of IC17 configuration bits (enable, ready, divider) */
32871 #define RCC_PUBCFGCR2_IC18PUBC_Pos              (17U)
32872 #define RCC_PUBCFGCR2_IC18PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC18PUBC_Pos) /*!< 0x00020000 */
32873 #define RCC_PUBCFGCR2_IC18PUBC                  RCC_PUBCFGCR2_IC18PUBC_Msk           /*!< Public protection of IC18 configuration bits (enable, ready, divider) */
32874 #define RCC_PUBCFGCR2_IC19PUBC_Pos              (18U)
32875 #define RCC_PUBCFGCR2_IC19PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC19PUBC_Pos) /*!< 0x00040000 */
32876 #define RCC_PUBCFGCR2_IC19PUBC                  RCC_PUBCFGCR2_IC19PUBC_Msk           /*!< Public protection of IC19 configuration bits (enable, ready, divider) */
32877 #define RCC_PUBCFGCR2_IC20PUBC_Pos              (19U)
32878 #define RCC_PUBCFGCR2_IC20PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC20PUBC_Pos) /*!< 0x00080000 */
32879 #define RCC_PUBCFGCR2_IC20PUBC                  RCC_PUBCFGCR2_IC20PUBC_Msk           /*!< Public protection of IC20 configuration bits (enable, ready, divider) */
32880 
32881 /****************  Bit definition for RCC_PRIVCFGCR3 register  ****************/
32882 #define RCC_PRIVCFGCR3_MODPRIVC_Pos             (0U)
32883 #define RCC_PRIVCFGCR3_MODPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR3_MODPRIVC_Pos)/*!< 0x00000001 */
32884 #define RCC_PRIVCFGCR3_MODPRIVC                 RCC_PRIVCFGCR3_MODPRIVC_Msk          /*!< Privileged protection of MOD configuration bits (enable, ready, divider) */
32885 #define RCC_PRIVCFGCR3_SYSPRIVC_Pos             (1U)
32886 #define RCC_PRIVCFGCR3_SYSPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR3_SYSPRIVC_Pos)/*!< 0x00000002 */
32887 #define RCC_PRIVCFGCR3_SYSPRIVC                 RCC_PRIVCFGCR3_SYSPRIVC_Msk          /*!< Privileged protection of SYS configuration bits (enable, ready, divider) */
32888 #define RCC_PRIVCFGCR3_BUSPRIVC_Pos             (2U)
32889 #define RCC_PRIVCFGCR3_BUSPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR3_BUSPRIVC_Pos)/*!< 0x00000004 */
32890 #define RCC_PRIVCFGCR3_BUSPRIVC                 RCC_PRIVCFGCR3_BUSPRIVC_Msk          /*!< Privileged protection of BUS configuration bits (enable, ready, divider) */
32891 #define RCC_PRIVCFGCR3_PERPRIVC_Pos             (3U)
32892 #define RCC_PRIVCFGCR3_PERPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR3_PERPRIVC_Pos)/*!< 0x00000008 */
32893 #define RCC_PRIVCFGCR3_PERPRIVC                 RCC_PRIVCFGCR3_PERPRIVC_Msk          /*!< Privileged protection of PER configuration bits (enable, ready, divider) */
32894 #define RCC_PRIVCFGCR3_INTPRIVC_Pos             (4U)
32895 #define RCC_PRIVCFGCR3_INTPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR3_INTPRIVC_Pos)/*!< 0x00000010 */
32896 #define RCC_PRIVCFGCR3_INTPRIVC                 RCC_PRIVCFGCR3_INTPRIVC_Msk          /*!< Privileged protection of INT configuration bits (enable, ready, divider) */
32897 #define RCC_PRIVCFGCR3_RSTPRIVC_Pos             (5U)
32898 #define RCC_PRIVCFGCR3_RSTPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR3_RSTPRIVC_Pos)/*!< 0x00000020 */
32899 #define RCC_PRIVCFGCR3_RSTPRIVC                 RCC_PRIVCFGCR3_RSTPRIVC_Msk          /*!< Privileged protection of RST configuration bits (enable, ready, divider) */
32900 
32901 /****************  Bit definition for RCC_PUBCFGCR3 register  *****************/
32902 #define RCC_PUBCFGCR3_MODPUBC_Pos               (0U)
32903 #define RCC_PUBCFGCR3_MODPUBC_Msk               (0x1UL << RCC_PUBCFGCR3_MODPUBC_Pos)  /*!< 0x00000001 */
32904 #define RCC_PUBCFGCR3_MODPUBC                   RCC_PUBCFGCR3_MODPUBC_Msk            /*!< Public protection of MOD configuration bits (enable, ready, divider) */
32905 #define RCC_PUBCFGCR3_SYSPUBC_Pos               (1U)
32906 #define RCC_PUBCFGCR3_SYSPUBC_Msk               (0x1UL << RCC_PUBCFGCR3_SYSPUBC_Pos)  /*!< 0x00000002 */
32907 #define RCC_PUBCFGCR3_SYSPUBC                   RCC_PUBCFGCR3_SYSPUBC_Msk            /*!< Public protection of SYS configuration bits (enable, ready, divider) */
32908 #define RCC_PUBCFGCR3_BUSPUBC_Pos               (2U)
32909 #define RCC_PUBCFGCR3_BUSPUBC_Msk               (0x1UL << RCC_PUBCFGCR3_BUSPUBC_Pos)  /*!< 0x00000004 */
32910 #define RCC_PUBCFGCR3_BUSPUBC                   RCC_PUBCFGCR3_BUSPUBC_Msk            /*!< Public protection of BUS configuration bits (enable, ready, divider) */
32911 #define RCC_PUBCFGCR3_PERPUBC_Pos               (3U)
32912 #define RCC_PUBCFGCR3_PERPUBC_Msk               (0x1UL << RCC_PUBCFGCR3_PERPUBC_Pos)  /*!< 0x00000008 */
32913 #define RCC_PUBCFGCR3_PERPUBC                   RCC_PUBCFGCR3_PERPUBC_Msk            /*!< Public protection of PER configuration bits (enable, ready, divider) */
32914 #define RCC_PUBCFGCR3_INTPUBC_Pos               (4U)
32915 #define RCC_PUBCFGCR3_INTPUBC_Msk               (0x1UL << RCC_PUBCFGCR3_INTPUBC_Pos)  /*!< 0x00000010 */
32916 #define RCC_PUBCFGCR3_INTPUBC                   RCC_PUBCFGCR3_INTPUBC_Msk            /*!< Public protection of INT configuration bits (enable, ready, divider) */
32917 #define RCC_PUBCFGCR3_RSTPUBC_Pos               (5U)
32918 #define RCC_PUBCFGCR3_RSTPUBC_Msk               (0x1UL << RCC_PUBCFGCR3_RSTPUBC_Pos)  /*!< 0x00000020 */
32919 #define RCC_PUBCFGCR3_RSTPUBC                   RCC_PUBCFGCR3_RSTPUBC_Msk            /*!< Public protection of RST configuration bits (enable, ready, divider) */
32920 
32921 /****************  Bit definition for RCC_PRIVCFGCR4 register  ****************/
32922 #define RCC_PRIVCFGCR4_ACLKNPRIVC_Pos           (0U)
32923 #define RCC_PRIVCFGCR4_ACLKNPRIVC_Msk           (0x1UL << RCC_PRIVCFGCR4_ACLKNPRIVC_Pos)  /*!< 0x00000001 */
32924 #define RCC_PRIVCFGCR4_ACLKNPRIVC               RCC_PRIVCFGCR4_ACLKNPRIVC_Msk        /*!< Privileged protection of ACLKN configuration bits (enable, ready, divider) */
32925 #define RCC_PRIVCFGCR4_ACLKNCPRIVC_Pos          (1U)
32926 #define RCC_PRIVCFGCR4_ACLKNCPRIVC_Msk          (0x1UL << RCC_PRIVCFGCR4_ACLKNCPRIVC_Pos)   /*!< 0x00000002 */
32927 #define RCC_PRIVCFGCR4_ACLKNCPRIVC              RCC_PRIVCFGCR4_ACLKNCPRIVC_Msk       /*!< Privileged protection of ACLKNC configuration bits (enable, ready, divider) */
32928 #define RCC_PRIVCFGCR4_AHBMPRIVC_Pos            (2U)
32929 #define RCC_PRIVCFGCR4_AHBMPRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_AHBMPRIVC_Pos) /*!< 0x00000004 */
32930 #define RCC_PRIVCFGCR4_AHBMPRIVC                RCC_PRIVCFGCR4_AHBMPRIVC_Msk         /*!< Privileged protection of AHBM configuration bits (enable, ready, divider) */
32931 #define RCC_PRIVCFGCR4_AHB1PRIVC_Pos            (3U)
32932 #define RCC_PRIVCFGCR4_AHB1PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_AHB1PRIVC_Pos) /*!< 0x00000008 */
32933 #define RCC_PRIVCFGCR4_AHB1PRIVC                RCC_PRIVCFGCR4_AHB1PRIVC_Msk         /*!< Privileged protection of AHB1 configuration bits (enable, ready, divider) */
32934 #define RCC_PRIVCFGCR4_AHB2PRIVC_Pos            (4U)
32935 #define RCC_PRIVCFGCR4_AHB2PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_AHB2PRIVC_Pos) /*!< 0x00000010 */
32936 #define RCC_PRIVCFGCR4_AHB2PRIVC                RCC_PRIVCFGCR4_AHB2PRIVC_Msk         /*!< Privileged protection of AHB2 configuration bits (enable, ready, divider) */
32937 #define RCC_PRIVCFGCR4_AHB3PRIVC_Pos            (5U)
32938 #define RCC_PRIVCFGCR4_AHB3PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_AHB3PRIVC_Pos) /*!< 0x00000020 */
32939 #define RCC_PRIVCFGCR4_AHB3PRIVC                RCC_PRIVCFGCR4_AHB3PRIVC_Msk         /*!< Privileged protection of AHB3 configuration bits (enable, ready, divider) */
32940 #define RCC_PRIVCFGCR4_AHB4PRIVC_Pos            (6U)
32941 #define RCC_PRIVCFGCR4_AHB4PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_AHB4PRIVC_Pos) /*!< 0x00000040 */
32942 #define RCC_PRIVCFGCR4_AHB4PRIVC                RCC_PRIVCFGCR4_AHB4PRIVC_Msk         /*!< Privileged protection of AHB4 configuration bits (enable, ready, divider) */
32943 #define RCC_PRIVCFGCR4_AHB5PRIVC_Pos            (7U)
32944 #define RCC_PRIVCFGCR4_AHB5PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_AHB5PRIVC_Pos) /*!< 0x00000080 */
32945 #define RCC_PRIVCFGCR4_AHB5PRIVC                RCC_PRIVCFGCR4_AHB5PRIVC_Msk         /*!< Privileged protection of AHB5 configuration bits (enable, ready, divider) */
32946 #define RCC_PRIVCFGCR4_APB1PRIVC_Pos            (8U)
32947 #define RCC_PRIVCFGCR4_APB1PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_APB1PRIVC_Pos) /*!< 0x00000100 */
32948 #define RCC_PRIVCFGCR4_APB1PRIVC                RCC_PRIVCFGCR4_APB1PRIVC_Msk         /*!< Privileged protection of APB1 configuration bits (enable, ready, divider) */
32949 #define RCC_PRIVCFGCR4_APB2PRIVC_Pos            (9U)
32950 #define RCC_PRIVCFGCR4_APB2PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_APB2PRIVC_Pos) /*!< 0x00000200 */
32951 #define RCC_PRIVCFGCR4_APB2PRIVC                RCC_PRIVCFGCR4_APB2PRIVC_Msk         /*!< Privileged protection of APB2 configuration bits (enable, ready, divider) */
32952 #define RCC_PRIVCFGCR4_APB3PRIVC_Pos            (10U)
32953 #define RCC_PRIVCFGCR4_APB3PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_APB3PRIVC_Pos) /*!< 0x00000400 */
32954 #define RCC_PRIVCFGCR4_APB3PRIVC                RCC_PRIVCFGCR4_APB3PRIVC_Msk         /*!< Privileged protection of APB3 configuration bits (enable, ready, divider) */
32955 #define RCC_PRIVCFGCR4_APB4PRIVC_Pos            (11U)
32956 #define RCC_PRIVCFGCR4_APB4PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_APB4PRIVC_Pos) /*!< 0x00000800 */
32957 #define RCC_PRIVCFGCR4_APB4PRIVC                RCC_PRIVCFGCR4_APB4PRIVC_Msk         /*!< Privileged protection of APB4 configuration bits (enable, ready, divider) */
32958 #define RCC_PRIVCFGCR4_APB5PRIVC_Pos            (12U)
32959 #define RCC_PRIVCFGCR4_APB5PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_APB5PRIVC_Pos) /*!< 0x00001000 */
32960 #define RCC_PRIVCFGCR4_APB5PRIVC                RCC_PRIVCFGCR4_APB5PRIVC_Msk         /*!< Privileged protection of APB5 configuration bits (enable, ready, divider) */
32961 #define RCC_PRIVCFGCR4_NOCPRIVC_Pos             (13U)
32962 #define RCC_PRIVCFGCR4_NOCPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR4_NOCPRIVC_Pos)/*!< 0x00002000 */
32963 #define RCC_PRIVCFGCR4_NOCPRIVC                 RCC_PRIVCFGCR4_NOCPRIVC_Msk          /*!< Privileged protection of NOC configuration bits (enable, ready, divider) */
32964 
32965 /****************  Bit definition for RCC_PUBCFGCR4 register  *****************/
32966 #define RCC_PUBCFGCR4_ACLKNPUBC_Pos             (0U)
32967 #define RCC_PUBCFGCR4_ACLKNPUBC_Msk             (0x1UL << RCC_PUBCFGCR4_ACLKNPUBC_Pos)/*!< 0x00000001 */
32968 #define RCC_PUBCFGCR4_ACLKNPUBC                 RCC_PUBCFGCR4_ACLKNPUBC_Msk          /*!< Public protection of ACLKN configuration bits (enable, ready, divider) */
32969 #define RCC_PUBCFGCR4_ACLKNCPUBC_Pos            (1U)
32970 #define RCC_PUBCFGCR4_ACLKNCPUBC_Msk            (0x1UL << RCC_PUBCFGCR4_ACLKNCPUBC_Pos) /*!< 0x00000002 */
32971 #define RCC_PUBCFGCR4_ACLKNCPUBC                RCC_PUBCFGCR4_ACLKNCPUBC_Msk         /*!< Public protection of ACLKNC configuration bits (enable, ready, divider) */
32972 #define RCC_PUBCFGCR4_AHBMPUBC_Pos              (2U)
32973 #define RCC_PUBCFGCR4_AHBMPUBC_Msk              (0x1UL << RCC_PUBCFGCR4_AHBMPUBC_Pos) /*!< 0x00000004 */
32974 #define RCC_PUBCFGCR4_AHBMPUBC                  RCC_PUBCFGCR4_AHBMPUBC_Msk           /*!< Public protection of AHBM configuration bits (enable, ready, divider) */
32975 #define RCC_PUBCFGCR4_AHB1PUBC_Pos              (3U)
32976 #define RCC_PUBCFGCR4_AHB1PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_AHB1PUBC_Pos) /*!< 0x00000008 */
32977 #define RCC_PUBCFGCR4_AHB1PUBC                  RCC_PUBCFGCR4_AHB1PUBC_Msk           /*!< Public protection of AHB1 configuration bits (enable, ready, divider) */
32978 #define RCC_PUBCFGCR4_AHB2PUBC_Pos              (4U)
32979 #define RCC_PUBCFGCR4_AHB2PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_AHB2PUBC_Pos) /*!< 0x00000010 */
32980 #define RCC_PUBCFGCR4_AHB2PUBC                  RCC_PUBCFGCR4_AHB2PUBC_Msk           /*!< Public protection of AHB2 configuration bits (enable, ready, divider) */
32981 #define RCC_PUBCFGCR4_AHB3PUBC_Pos              (5U)
32982 #define RCC_PUBCFGCR4_AHB3PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_AHB3PUBC_Pos) /*!< 0x00000020 */
32983 #define RCC_PUBCFGCR4_AHB3PUBC                  RCC_PUBCFGCR4_AHB3PUBC_Msk           /*!< Public protection of AHB3 configuration bits (enable, ready, divider) */
32984 #define RCC_PUBCFGCR4_AHB4PUBC_Pos              (6U)
32985 #define RCC_PUBCFGCR4_AHB4PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_AHB4PUBC_Pos) /*!< 0x00000040 */
32986 #define RCC_PUBCFGCR4_AHB4PUBC                  RCC_PUBCFGCR4_AHB4PUBC_Msk           /*!< Public protection of AHB4 configuration bits (enable, ready, divider) */
32987 #define RCC_PUBCFGCR4_AHB5PUBC_Pos              (7U)
32988 #define RCC_PUBCFGCR4_AHB5PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_AHB5PUBC_Pos) /*!< 0x00000080 */
32989 #define RCC_PUBCFGCR4_AHB5PUBC                  RCC_PUBCFGCR4_AHB5PUBC_Msk           /*!< Public protection of AHB5 configuration bits (enable, ready, divider) */
32990 #define RCC_PUBCFGCR4_APB1PUBC_Pos              (8U)
32991 #define RCC_PUBCFGCR4_APB1PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_APB1PUBC_Pos) /*!< 0x00000100 */
32992 #define RCC_PUBCFGCR4_APB1PUBC                  RCC_PUBCFGCR4_APB1PUBC_Msk           /*!< Public protection of APB1 configuration bits (enable, ready, divider) */
32993 #define RCC_PUBCFGCR4_APB2PUBC_Pos              (9U)
32994 #define RCC_PUBCFGCR4_APB2PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_APB2PUBC_Pos) /*!< 0x00000200 */
32995 #define RCC_PUBCFGCR4_APB2PUBC                  RCC_PUBCFGCR4_APB2PUBC_Msk           /*!< Public protection of APB2 configuration bits (enable, ready, divider) */
32996 #define RCC_PUBCFGCR4_APB3PUBC_Pos              (10U)
32997 #define RCC_PUBCFGCR4_APB3PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_APB3PUBC_Pos) /*!< 0x00000400 */
32998 #define RCC_PUBCFGCR4_APB3PUBC                  RCC_PUBCFGCR4_APB3PUBC_Msk           /*!< Public protection of APB3 configuration bits (enable, ready, divider) */
32999 #define RCC_PUBCFGCR4_APB4PUBC_Pos              (11U)
33000 #define RCC_PUBCFGCR4_APB4PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_APB4PUBC_Pos) /*!< 0x00000800 */
33001 #define RCC_PUBCFGCR4_APB4PUBC                  RCC_PUBCFGCR4_APB4PUBC_Msk           /*!< Public protection of APB4 configuration bits (enable, ready, divider) */
33002 #define RCC_PUBCFGCR4_APB5PUBC_Pos              (12U)
33003 #define RCC_PUBCFGCR4_APB5PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_APB5PUBC_Pos) /*!< 0x00001000 */
33004 #define RCC_PUBCFGCR4_APB5PUBC                  RCC_PUBCFGCR4_APB5PUBC_Msk           /*!< Public protection of APB5 configuration bits (enable, ready, divider) */
33005 #define RCC_PUBCFGCR4_NOCPUBC_Pos               (13U)
33006 #define RCC_PUBCFGCR4_NOCPUBC_Msk               (0x1UL << RCC_PUBCFGCR4_NOCPUBC_Pos)  /*!< 0x00002000 */
33007 #define RCC_PUBCFGCR4_NOCPUBC                   RCC_PUBCFGCR4_NOCPUBC_Msk            /*!< Public protection of NOC configuration bits (enable, ready, divider) */
33008 
33009 /****************  Bit definition for RCC_PUBCFGCR5 register  *****************/
33010 #define RCC_PUBCFGCR5_AXISRAM3PUBC_Pos          (0U)
33011 #define RCC_PUBCFGCR5_AXISRAM3PUBC_Msk          (0x1UL << RCC_PUBCFGCR5_AXISRAM3PUBC_Pos)   /*!< 0x00000001 */
33012 #define RCC_PUBCFGCR5_AXISRAM3PUBC              RCC_PUBCFGCR5_AXISRAM3PUBC_Msk       /*!< Public protection of AXISRAM3 configuration bits (enable, ready, divider) */
33013 #define RCC_PUBCFGCR5_AXISRAM4PUBC_Pos          (1U)
33014 #define RCC_PUBCFGCR5_AXISRAM4PUBC_Msk          (0x1UL << RCC_PUBCFGCR5_AXISRAM4PUBC_Pos)   /*!< 0x00000002 */
33015 #define RCC_PUBCFGCR5_AXISRAM4PUBC              RCC_PUBCFGCR5_AXISRAM4PUBC_Msk       /*!< Public protection of AXISRAM4 configuration bits (enable, ready, divider) */
33016 #define RCC_PUBCFGCR5_AXISRAM5PUBC_Pos          (2U)
33017 #define RCC_PUBCFGCR5_AXISRAM5PUBC_Msk          (0x1UL << RCC_PUBCFGCR5_AXISRAM5PUBC_Pos)   /*!< 0x00000004 */
33018 #define RCC_PUBCFGCR5_AXISRAM5PUBC              RCC_PUBCFGCR5_AXISRAM5PUBC_Msk       /*!< Public protection of AXISRAM5 configuration bits (enable, ready, divider) */
33019 #define RCC_PUBCFGCR5_AXISRAM6PUBC_Pos          (3U)
33020 #define RCC_PUBCFGCR5_AXISRAM6PUBC_Msk          (0x1UL << RCC_PUBCFGCR5_AXISRAM6PUBC_Pos)   /*!< 0x00000008 */
33021 #define RCC_PUBCFGCR5_AXISRAM6PUBC              RCC_PUBCFGCR5_AXISRAM6PUBC_Msk       /*!< Public protection of AXISRAM6 configuration bits (enable, ready, divider) */
33022 #define RCC_PUBCFGCR5_AHBSRAM1PUBC_Pos          (4U)
33023 #define RCC_PUBCFGCR5_AHBSRAM1PUBC_Msk          (0x1UL << RCC_PUBCFGCR5_AHBSRAM1PUBC_Pos)   /*!< 0x00000010 */
33024 #define RCC_PUBCFGCR5_AHBSRAM1PUBC              RCC_PUBCFGCR5_AHBSRAM1PUBC_Msk       /*!< Public protection of AHBSRAM1 configuration bits (enable, ready, divider) */
33025 #define RCC_PUBCFGCR5_AHBSRAM2PUBC_Pos          (5U)
33026 #define RCC_PUBCFGCR5_AHBSRAM2PUBC_Msk          (0x1UL << RCC_PUBCFGCR5_AHBSRAM2PUBC_Pos)   /*!< 0x00000020 */
33027 #define RCC_PUBCFGCR5_AHBSRAM2PUBC              RCC_PUBCFGCR5_AHBSRAM2PUBC_Msk       /*!< Public protection of AHBSRAM2 configuration bits (enable, ready, divider) */
33028 #define RCC_PUBCFGCR5_BKPSRAMPUBC_Pos           (6U)
33029 #define RCC_PUBCFGCR5_BKPSRAMPUBC_Msk           (0x1UL << RCC_PUBCFGCR5_BKPSRAMPUBC_Pos)  /*!< 0x00000040 */
33030 #define RCC_PUBCFGCR5_BKPSRAMPUBC               RCC_PUBCFGCR5_BKPSRAMPUBC_Msk        /*!< Public protection of BKPSRAM configuration bits (enable, ready, divider) */
33031 #define RCC_PUBCFGCR5_AXISRAM1PUBC_Pos          (7U)
33032 #define RCC_PUBCFGCR5_AXISRAM1PUBC_Msk          (0x1UL << RCC_PUBCFGCR5_AXISRAM1PUBC_Pos)   /*!< 0x00000080 */
33033 #define RCC_PUBCFGCR5_AXISRAM1PUBC              RCC_PUBCFGCR5_AXISRAM1PUBC_Msk       /*!< Public protection of AXISRAM1 configuration bits (enable, ready, divider) */
33034 #define RCC_PUBCFGCR5_AXISRAM2PUBC_Pos          (8U)
33035 #define RCC_PUBCFGCR5_AXISRAM2PUBC_Msk          (0x1UL << RCC_PUBCFGCR5_AXISRAM2PUBC_Pos)   /*!< 0x00000100 */
33036 #define RCC_PUBCFGCR5_AXISRAM2PUBC              RCC_PUBCFGCR5_AXISRAM2PUBC_Msk       /*!< Public protection of AXISRAM2 configuration bits (enable, ready, divider) */
33037 #define RCC_PUBCFGCR5_FLEXRAMPUBC_Pos           (9U)
33038 #define RCC_PUBCFGCR5_FLEXRAMPUBC_Msk           (0x1UL << RCC_PUBCFGCR5_FLEXRAMPUBC_Pos)  /*!< 0x00000200 */
33039 #define RCC_PUBCFGCR5_FLEXRAMPUBC               RCC_PUBCFGCR5_FLEXRAMPUBC_Msk        /*!< Public protection of FLEXRAM configuration bits (enable, ready, divider) */
33040 #define RCC_PUBCFGCR5_CACHEAXIRAMPUBC_Pos       (10U)
33041 #define RCC_PUBCFGCR5_CACHEAXIRAMPUBC_Msk       (0x1UL << RCC_PUBCFGCR5_CACHEAXIRAMPUBC_Pos)      /*!< 0x00000400 */
33042 #define RCC_PUBCFGCR5_CACHEAXIRAMPUBC           RCC_PUBCFGCR5_CACHEAXIRAMPUBC_Msk    /*!< Public protection of CACHEAXIRAM configuration bits  */
33043 #define RCC_PUBCFGCR5_VENCRAMPUBC_Pos           (11U)
33044 #define RCC_PUBCFGCR5_VENCRAMPUBC_Msk           (0x1UL << RCC_PUBCFGCR5_VENCRAMPUBC_Pos)  /*!< 0x00000800 */
33045 #define RCC_PUBCFGCR5_VENCRAMPUBC               RCC_PUBCFGCR5_VENCRAMPUBC_Msk        /*!< Public protection of VENCRAM configuration bits (enable, ready, divider) */
33046 
33047 
33048 /******************************************************************************/
33049 /*                                                                            */
33050 /*          Resource Isolation Framework Security Controller (RIFSC)          */
33051 /*                                                                            */
33052 /******************************************************************************/
33053 /****************  Bit definition for RIFSC_RISC_CR register  *****************/
33054 #define RIFSC_RISC_CR_GLOCK_Pos             (0UL)
33055 #define RIFSC_RISC_CR_GLOCK_Msk             (0x1UL << RIFSC_RISC_CR_GLOCK_Pos)             /*!< 0x00000001 */
33056 #define RIFSC_RISC_CR_GLOCK                 RIFSC_RISC_CR_GLOCK_Msk                        /*!< Global lock */
33057 
33058 /*************  Bit definition for RIFSC_RISC_SECCFGRx register  **************/
33059 #define RIFSC_RISC_SECCFGRx_SEC0_Pos        (0U)
33060 #define RIFSC_RISC_SECCFGRx_SEC0_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC0_Pos)         /*!< 0x00000001 */
33061 #define RIFSC_RISC_SECCFGRx_SEC0            RIFSC_RISC_SECCFGRx_SEC0_Msk                   /*!< Security configuration for peripheral 0 */
33062 #define RIFSC_RISC_SECCFGRx_SEC1_Pos        (1U)
33063 #define RIFSC_RISC_SECCFGRx_SEC1_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC1_Pos)         /*!< 0x00000002 */
33064 #define RIFSC_RISC_SECCFGRx_SEC1            RIFSC_RISC_SECCFGRx_SEC1_Msk                   /*!< Security configuration for peripheral 1 */
33065 #define RIFSC_RISC_SECCFGRx_SEC2_Pos        (2U)
33066 #define RIFSC_RISC_SECCFGRx_SEC2_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC2_Pos)         /*!< 0x00000004 */
33067 #define RIFSC_RISC_SECCFGRx_SEC2            RIFSC_RISC_SECCFGRx_SEC2_Msk                   /*!< Security configuration for peripheral 2 */
33068 #define RIFSC_RISC_SECCFGRx_SEC3_Pos        (3U)
33069 #define RIFSC_RISC_SECCFGRx_SEC3_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC3_Pos)         /*!< 0x00000008 */
33070 #define RIFSC_RISC_SECCFGRx_SEC3            RIFSC_RISC_SECCFGRx_SEC3_Msk                   /*!< Security configuration for peripheral 3 */
33071 #define RIFSC_RISC_SECCFGRx_SEC4_Pos        (4U)
33072 #define RIFSC_RISC_SECCFGRx_SEC4_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC4_Pos)         /*!< 0x00000010 */
33073 #define RIFSC_RISC_SECCFGRx_SEC4            RIFSC_RISC_SECCFGRx_SEC4_Msk                   /*!< Security configuration for peripheral 4 */
33074 #define RIFSC_RISC_SECCFGRx_SEC5_Pos        (5U)
33075 #define RIFSC_RISC_SECCFGRx_SEC5_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC5_Pos)         /*!< 0x00000020 */
33076 #define RIFSC_RISC_SECCFGRx_SEC5            RIFSC_RISC_SECCFGRx_SEC5_Msk                   /*!< Security configuration for peripheral 5 */
33077 #define RIFSC_RISC_SECCFGRx_SEC6_Pos        (6U)
33078 #define RIFSC_RISC_SECCFGRx_SEC6_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC6_Pos)         /*!< 0x00000040 */
33079 #define RIFSC_RISC_SECCFGRx_SEC6            RIFSC_RISC_SECCFGRx_SEC6_Msk                   /*!< Security configuration for peripheral 6 */
33080 #define RIFSC_RISC_SECCFGRx_SEC7_Pos        (7U)
33081 #define RIFSC_RISC_SECCFGRx_SEC7_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC7_Pos)         /*!< 0x00000080 */
33082 #define RIFSC_RISC_SECCFGRx_SEC7            RIFSC_RISC_SECCFGRx_SEC7_Msk                   /*!< Security configuration for peripheral 7 */
33083 #define RIFSC_RISC_SECCFGRx_SEC8_Pos        (8U)
33084 #define RIFSC_RISC_SECCFGRx_SEC8_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC8_Pos)         /*!< 0x00000100 */
33085 #define RIFSC_RISC_SECCFGRx_SEC8            RIFSC_RISC_SECCFGRx_SEC8_Msk                   /*!< Security configuration for peripheral 8 */
33086 #define RIFSC_RISC_SECCFGRx_SEC9_Pos        (9U)
33087 #define RIFSC_RISC_SECCFGRx_SEC9_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC9_Pos)         /*!< 0x00000200 */
33088 #define RIFSC_RISC_SECCFGRx_SEC9            RIFSC_RISC_SECCFGRx_SEC9_Msk                   /*!< Security configuration for peripheral 9 */
33089 #define RIFSC_RISC_SECCFGRx_SEC10_Pos       (10U)
33090 #define RIFSC_RISC_SECCFGRx_SEC10_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC10_Pos)        /*!< 0x00000400 */
33091 #define RIFSC_RISC_SECCFGRx_SEC10           RIFSC_RISC_SECCFGRx_SEC10_Msk                  /*!< Security configuration for peripheral 10 */
33092 #define RIFSC_RISC_SECCFGRx_SEC11_Pos       (11U)
33093 #define RIFSC_RISC_SECCFGRx_SEC11_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC11_Pos)        /*!< 0x00000800 */
33094 #define RIFSC_RISC_SECCFGRx_SEC11           RIFSC_RISC_SECCFGRx_SEC11_Msk                  /*!< Security configuration for peripheral 11 */
33095 #define RIFSC_RISC_SECCFGRx_SEC12_Pos       (12U)
33096 #define RIFSC_RISC_SECCFGRx_SEC12_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC12_Pos)        /*!< 0x00001000 */
33097 #define RIFSC_RISC_SECCFGRx_SEC12           RIFSC_RISC_SECCFGRx_SEC12_Msk                  /*!< Security configuration for peripheral 12 */
33098 #define RIFSC_RISC_SECCFGRx_SEC13_Pos       (13U)
33099 #define RIFSC_RISC_SECCFGRx_SEC13_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC13_Pos)        /*!< 0x00002000 */
33100 #define RIFSC_RISC_SECCFGRx_SEC13           RIFSC_RISC_SECCFGRx_SEC13_Msk                  /*!< Security configuration for peripheral 13 */
33101 #define RIFSC_RISC_SECCFGRx_SEC14_Pos       (14U)
33102 #define RIFSC_RISC_SECCFGRx_SEC14_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC14_Pos)        /*!< 0x00004000 */
33103 #define RIFSC_RISC_SECCFGRx_SEC14           RIFSC_RISC_SECCFGRx_SEC14_Msk                  /*!< Security configuration for peripheral 14 */
33104 #define RIFSC_RISC_SECCFGRx_SEC15_Pos       (15U)
33105 #define RIFSC_RISC_SECCFGRx_SEC15_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC15_Pos)        /*!< 0x00008000 */
33106 #define RIFSC_RISC_SECCFGRx_SEC15           RIFSC_RISC_SECCFGRx_SEC15_Msk                  /*!< Security configuration for peripheral 15 */
33107 #define RIFSC_RISC_SECCFGRx_SEC16_Pos       (16U)
33108 #define RIFSC_RISC_SECCFGRx_SEC16_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC16_Pos)        /*!< 0x00010000 */
33109 #define RIFSC_RISC_SECCFGRx_SEC16           RIFSC_RISC_SECCFGRx_SEC16_Msk                  /*!< Security configuration for peripheral 16 */
33110 #define RIFSC_RISC_SECCFGRx_SEC17_Pos       (17U)
33111 #define RIFSC_RISC_SECCFGRx_SEC17_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC17_Pos)        /*!< 0x00020000 */
33112 #define RIFSC_RISC_SECCFGRx_SEC17           RIFSC_RISC_SECCFGRx_SEC17_Msk                  /*!< Security configuration for peripheral 17 */
33113 #define RIFSC_RISC_SECCFGRx_SEC18_Pos       (18U)
33114 #define RIFSC_RISC_SECCFGRx_SEC18_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC18_Pos)        /*!< 0x00040000 */
33115 #define RIFSC_RISC_SECCFGRx_SEC18           RIFSC_RISC_SECCFGRx_SEC18_Msk                  /*!< Security configuration for peripheral 18 */
33116 #define RIFSC_RISC_SECCFGRx_SEC19_Pos       (19U)
33117 #define RIFSC_RISC_SECCFGRx_SEC19_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC19_Pos)        /*!< 0x00080000 */
33118 #define RIFSC_RISC_SECCFGRx_SEC19           RIFSC_RISC_SECCFGRx_SEC19_Msk                  /*!< Security configuration for peripheral 19 */
33119 #define RIFSC_RISC_SECCFGRx_SEC20_Pos       (20U)
33120 #define RIFSC_RISC_SECCFGRx_SEC20_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC20_Pos)        /*!< 0x00100000 */
33121 #define RIFSC_RISC_SECCFGRx_SEC20           RIFSC_RISC_SECCFGRx_SEC20_Msk                  /*!< Security configuration for peripheral 20 */
33122 #define RIFSC_RISC_SECCFGRx_SEC21_Pos       (21U)
33123 #define RIFSC_RISC_SECCFGRx_SEC21_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC21_Pos)        /*!< 0x00200000 */
33124 #define RIFSC_RISC_SECCFGRx_SEC21           RIFSC_RISC_SECCFGRx_SEC21_Msk                  /*!< Security configuration for peripheral 21 */
33125 #define RIFSC_RISC_SECCFGRx_SEC22_Pos       (22U)
33126 #define RIFSC_RISC_SECCFGRx_SEC22_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC22_Pos)        /*!< 0x00400000 */
33127 #define RIFSC_RISC_SECCFGRx_SEC22           RIFSC_RISC_SECCFGRx_SEC22_Msk                  /*!< Security configuration for peripheral 22 */
33128 #define RIFSC_RISC_SECCFGRx_SEC23_Pos       (23U)
33129 #define RIFSC_RISC_SECCFGRx_SEC23_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC23_Pos)        /*!< 0x00800000 */
33130 #define RIFSC_RISC_SECCFGRx_SEC23           RIFSC_RISC_SECCFGRx_SEC23_Msk                  /*!< Security configuration for peripheral 23 */
33131 #define RIFSC_RISC_SECCFGRx_SEC24_Pos       (24U)
33132 #define RIFSC_RISC_SECCFGRx_SEC24_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC24_Pos)        /*!< 0x01000000 */
33133 #define RIFSC_RISC_SECCFGRx_SEC24           RIFSC_RISC_SECCFGRx_SEC24_Msk                  /*!< Security configuration for peripheral 24 */
33134 #define RIFSC_RISC_SECCFGRx_SEC25_Pos       (25U)
33135 #define RIFSC_RISC_SECCFGRx_SEC25_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC25_Pos)        /*!< 0x02000000 */
33136 #define RIFSC_RISC_SECCFGRx_SEC25           RIFSC_RISC_SECCFGRx_SEC25_Msk                  /*!< Security configuration for peripheral 25 */
33137 #define RIFSC_RISC_SECCFGRx_SEC26_Pos       (26U)
33138 #define RIFSC_RISC_SECCFGRx_SEC26_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC26_Pos)        /*!< 0x04000000 */
33139 #define RIFSC_RISC_SECCFGRx_SEC26           RIFSC_RISC_SECCFGRx_SEC26_Msk                  /*!< Security configuration for peripheral 26 */
33140 #define RIFSC_RISC_SECCFGRx_SEC27_Pos       (27U)
33141 #define RIFSC_RISC_SECCFGRx_SEC27_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC27_Pos)        /*!< 0x08000000 */
33142 #define RIFSC_RISC_SECCFGRx_SEC27           RIFSC_RISC_SECCFGRx_SEC27_Msk                  /*!< Security configuration for peripheral 27 */
33143 #define RIFSC_RISC_SECCFGRx_SEC28_Pos       (28U)
33144 #define RIFSC_RISC_SECCFGRx_SEC28_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC28_Pos)        /*!< 0x10000000 */
33145 #define RIFSC_RISC_SECCFGRx_SEC28           RIFSC_RISC_SECCFGRx_SEC28_Msk                  /*!< Security configuration for peripheral 28 */
33146 #define RIFSC_RISC_SECCFGRx_SEC29_Pos       (29U)
33147 #define RIFSC_RISC_SECCFGRx_SEC29_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC29_Pos)        /*!< 0x20000000 */
33148 #define RIFSC_RISC_SECCFGRx_SEC29           RIFSC_RISC_SECCFGRx_SEC29_Msk                  /*!< Security configuration for peripheral 29 */
33149 #define RIFSC_RISC_SECCFGRx_SEC30_Pos       (30U)
33150 #define RIFSC_RISC_SECCFGRx_SEC30_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC30_Pos)        /*!< 0x40000000 */
33151 #define RIFSC_RISC_SECCFGRx_SEC30           RIFSC_RISC_SECCFGRx_SEC30_Msk                  /*!< Security configuration for peripheral 30 */
33152 #define RIFSC_RISC_SECCFGRx_SEC31_Pos       (31U)
33153 #define RIFSC_RISC_SECCFGRx_SEC31_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC31_Pos)        /*!< 0x80000000 */
33154 #define RIFSC_RISC_SECCFGRx_SEC31           RIFSC_RISC_SECCFGRx_SEC31_Msk                  /*!< Security configuration for peripheral 31 */
33155 
33156 /*************  Bit definition for RIFSC_RISC_PRIVCFGRx register  *************/
33157 #define RIFSC_RISC_PRIVCFGRx_PRIV0_Pos      (0U)
33158 #define RIFSC_RISC_PRIVCFGRx_PRIV0_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV0_Pos)       /*!< 0x00000001 */
33159 #define RIFSC_RISC_PRIVCFGRx_PRIV0          RIFSC_RISC_PRIVCFGRx_PRIV0_Msk                 /*!< privileged-only access permission for peripheral 0 */
33160 #define RIFSC_RISC_PRIVCFGRx_PRIV1_Pos      (1U)
33161 #define RIFSC_RISC_PRIVCFGRx_PRIV1_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV1_Pos)       /*!< 0x00000002 */
33162 #define RIFSC_RISC_PRIVCFGRx_PRIV1          RIFSC_RISC_PRIVCFGRx_PRIV1_Msk                 /*!< privileged-only access permission for peripheral 1 */
33163 #define RIFSC_RISC_PRIVCFGRx_PRIV2_Pos      (2U)
33164 #define RIFSC_RISC_PRIVCFGRx_PRIV2_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV2_Pos)       /*!< 0x00000004 */
33165 #define RIFSC_RISC_PRIVCFGRx_PRIV2          RIFSC_RISC_PRIVCFGRx_PRIV2_Msk                 /*!< privileged-only access permission for peripheral 2 */
33166 #define RIFSC_RISC_PRIVCFGRx_PRIV3_Pos      (3U)
33167 #define RIFSC_RISC_PRIVCFGRx_PRIV3_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV3_Pos)       /*!< 0x00000008 */
33168 #define RIFSC_RISC_PRIVCFGRx_PRIV3          RIFSC_RISC_PRIVCFGRx_PRIV3_Msk                 /*!< privileged-only access permission for peripheral 3 */
33169 #define RIFSC_RISC_PRIVCFGRx_PRIV4_Pos      (4U)
33170 #define RIFSC_RISC_PRIVCFGRx_PRIV4_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV4_Pos)       /*!< 0x00000010 */
33171 #define RIFSC_RISC_PRIVCFGRx_PRIV4          RIFSC_RISC_PRIVCFGRx_PRIV4_Msk                 /*!< privileged-only access permission for peripheral 4 */
33172 #define RIFSC_RISC_PRIVCFGRx_PRIV5_Pos      (5U)
33173 #define RIFSC_RISC_PRIVCFGRx_PRIV5_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV5_Pos)       /*!< 0x00000020 */
33174 #define RIFSC_RISC_PRIVCFGRx_PRIV5          RIFSC_RISC_PRIVCFGRx_PRIV5_Msk                 /*!< privileged-only access permission for peripheral 5 */
33175 #define RIFSC_RISC_PRIVCFGRx_PRIV6_Pos      (6U)
33176 #define RIFSC_RISC_PRIVCFGRx_PRIV6_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV6_Pos)       /*!< 0x00000040 */
33177 #define RIFSC_RISC_PRIVCFGRx_PRIV6          RIFSC_RISC_PRIVCFGRx_PRIV6_Msk                 /*!< privileged-only access permission for peripheral 6 */
33178 #define RIFSC_RISC_PRIVCFGRx_PRIV7_Pos      (7U)
33179 #define RIFSC_RISC_PRIVCFGRx_PRIV7_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV7_Pos)       /*!< 0x00000080 */
33180 #define RIFSC_RISC_PRIVCFGRx_PRIV7          RIFSC_RISC_PRIVCFGRx_PRIV7_Msk                 /*!< privileged-only access permission for peripheral 7 */
33181 #define RIFSC_RISC_PRIVCFGRx_PRIV8_Pos      (8U)
33182 #define RIFSC_RISC_PRIVCFGRx_PRIV8_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV8_Pos)       /*!< 0x00000100 */
33183 #define RIFSC_RISC_PRIVCFGRx_PRIV8          RIFSC_RISC_PRIVCFGRx_PRIV8_Msk                 /*!< privileged-only access permission for peripheral 8 */
33184 #define RIFSC_RISC_PRIVCFGRx_PRIV9_Pos      (9U)
33185 #define RIFSC_RISC_PRIVCFGRx_PRIV9_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV9_Pos)       /*!< 0x00000200 */
33186 #define RIFSC_RISC_PRIVCFGRx_PRIV9          RIFSC_RISC_PRIVCFGRx_PRIV9_Msk                 /*!< privileged-only access permission for peripheral 9 */
33187 #define RIFSC_RISC_PRIVCFGRx_PRIV10_Pos     (10U)
33188 #define RIFSC_RISC_PRIVCFGRx_PRIV10_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV10_Pos)      /*!< 0x00000400 */
33189 #define RIFSC_RISC_PRIVCFGRx_PRIV10         RIFSC_RISC_PRIVCFGRx_PRIV10_Msk                /*!< privileged-only access permission for peripheral 10 */
33190 #define RIFSC_RISC_PRIVCFGRx_PRIV11_Pos     (11U)
33191 #define RIFSC_RISC_PRIVCFGRx_PRIV11_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV11_Pos)      /*!< 0x00000800 */
33192 #define RIFSC_RISC_PRIVCFGRx_PRIV11         RIFSC_RISC_PRIVCFGRx_PRIV11_Msk                /*!< privileged-only access permission for peripheral 11 */
33193 #define RIFSC_RISC_PRIVCFGRx_PRIV12_Pos     (12U)
33194 #define RIFSC_RISC_PRIVCFGRx_PRIV12_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV12_Pos)      /*!< 0x00001000 */
33195 #define RIFSC_RISC_PRIVCFGRx_PRIV12         RIFSC_RISC_PRIVCFGRx_PRIV12_Msk                /*!< privileged-only access permission for peripheral 12 */
33196 #define RIFSC_RISC_PRIVCFGRx_PRIV13_Pos     (13U)
33197 #define RIFSC_RISC_PRIVCFGRx_PRIV13_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV13_Pos)      /*!< 0x00002000 */
33198 #define RIFSC_RISC_PRIVCFGRx_PRIV13         RIFSC_RISC_PRIVCFGRx_PRIV13_Msk                /*!< privileged-only access permission for peripheral 13 */
33199 #define RIFSC_RISC_PRIVCFGRx_PRIV14_Pos     (14U)
33200 #define RIFSC_RISC_PRIVCFGRx_PRIV14_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV14_Pos)      /*!< 0x00004000 */
33201 #define RIFSC_RISC_PRIVCFGRx_PRIV14         RIFSC_RISC_PRIVCFGRx_PRIV14_Msk                /*!< privileged-only access permission for peripheral 14 */
33202 #define RIFSC_RISC_PRIVCFGRx_PRIV15_Pos     (15U)
33203 #define RIFSC_RISC_PRIVCFGRx_PRIV15_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV15_Pos)      /*!< 0x00008000 */
33204 #define RIFSC_RISC_PRIVCFGRx_PRIV15         RIFSC_RISC_PRIVCFGRx_PRIV15_Msk                /*!< privileged-only access permission for peripheral 15 */
33205 #define RIFSC_RISC_PRIVCFGRx_PRIV16_Pos     (16U)
33206 #define RIFSC_RISC_PRIVCFGRx_PRIV16_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV16_Pos)      /*!< 0x00010000 */
33207 #define RIFSC_RISC_PRIVCFGRx_PRIV16         RIFSC_RISC_PRIVCFGRx_PRIV16_Msk                /*!< privileged-only access permission for peripheral 16 */
33208 #define RIFSC_RISC_PRIVCFGRx_PRIV17_Pos     (17U)
33209 #define RIFSC_RISC_PRIVCFGRx_PRIV17_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV17_Pos)      /*!< 0x00020000 */
33210 #define RIFSC_RISC_PRIVCFGRx_PRIV17         RIFSC_RISC_PRIVCFGRx_PRIV17_Msk                /*!< privileged-only access permission for peripheral 17 */
33211 #define RIFSC_RISC_PRIVCFGRx_PRIV18_Pos     (18U)
33212 #define RIFSC_RISC_PRIVCFGRx_PRIV18_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV18_Pos)      /*!< 0x00040000 */
33213 #define RIFSC_RISC_PRIVCFGRx_PRIV18         RIFSC_RISC_PRIVCFGRx_PRIV18_Msk                /*!< privileged-only access permission for peripheral 18 */
33214 #define RIFSC_RISC_PRIVCFGRx_PRIV19_Pos     (19U)
33215 #define RIFSC_RISC_PRIVCFGRx_PRIV19_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV19_Pos)      /*!< 0x00080000 */
33216 #define RIFSC_RISC_PRIVCFGRx_PRIV19         RIFSC_RISC_PRIVCFGRx_PRIV19_Msk                /*!< privileged-only access permission for peripheral 19 */
33217 #define RIFSC_RISC_PRIVCFGRx_PRIV20_Pos     (20U)
33218 #define RIFSC_RISC_PRIVCFGRx_PRIV20_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV20_Pos)      /*!< 0x00100000 */
33219 #define RIFSC_RISC_PRIVCFGRx_PRIV20         RIFSC_RISC_PRIVCFGRx_PRIV20_Msk                /*!< privileged-only access permission for peripheral 20 */
33220 #define RIFSC_RISC_PRIVCFGRx_PRIV21_Pos     (21U)
33221 #define RIFSC_RISC_PRIVCFGRx_PRIV21_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV21_Pos)      /*!< 0x00200000 */
33222 #define RIFSC_RISC_PRIVCFGRx_PRIV21         RIFSC_RISC_PRIVCFGRx_PRIV21_Msk                /*!< privileged-only access permission for peripheral 21 */
33223 #define RIFSC_RISC_PRIVCFGRx_PRIV22_Pos     (22U)
33224 #define RIFSC_RISC_PRIVCFGRx_PRIV22_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV22_Pos)      /*!< 0x00400000 */
33225 #define RIFSC_RISC_PRIVCFGRx_PRIV22         RIFSC_RISC_PRIVCFGRx_PRIV22_Msk                /*!< privileged-only access permission for peripheral 22 */
33226 #define RIFSC_RISC_PRIVCFGRx_PRIV23_Pos     (23U)
33227 #define RIFSC_RISC_PRIVCFGRx_PRIV23_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV23_Pos)      /*!< 0x00800000 */
33228 #define RIFSC_RISC_PRIVCFGRx_PRIV23         RIFSC_RISC_PRIVCFGRx_PRIV23_Msk                /*!< privileged-only access permission for peripheral 23 */
33229 #define RIFSC_RISC_PRIVCFGRx_PRIV24_Pos     (24U)
33230 #define RIFSC_RISC_PRIVCFGRx_PRIV24_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV24_Pos)      /*!< 0x01000000 */
33231 #define RIFSC_RISC_PRIVCFGRx_PRIV24         RIFSC_RISC_PRIVCFGRx_PRIV24_Msk                /*!< privileged-only access permission for peripheral 24 */
33232 #define RIFSC_RISC_PRIVCFGRx_PRIV25_Pos     (25U)
33233 #define RIFSC_RISC_PRIVCFGRx_PRIV25_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV25_Pos)      /*!< 0x02000000 */
33234 #define RIFSC_RISC_PRIVCFGRx_PRIV25         RIFSC_RISC_PRIVCFGRx_PRIV25_Msk                /*!< privileged-only access permission for peripheral 25 */
33235 #define RIFSC_RISC_PRIVCFGRx_PRIV26_Pos     (26U)
33236 #define RIFSC_RISC_PRIVCFGRx_PRIV26_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV26_Pos)      /*!< 0x04000000 */
33237 #define RIFSC_RISC_PRIVCFGRx_PRIV26         RIFSC_RISC_PRIVCFGRx_PRIV26_Msk                /*!< privileged-only access permission for peripheral 26 */
33238 #define RIFSC_RISC_PRIVCFGRx_PRIV27_Pos     (27U)
33239 #define RIFSC_RISC_PRIVCFGRx_PRIV27_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV27_Pos)      /*!< 0x08000000 */
33240 #define RIFSC_RISC_PRIVCFGRx_PRIV27         RIFSC_RISC_PRIVCFGRx_PRIV27_Msk                /*!< privileged-only access permission for peripheral 27 */
33241 #define RIFSC_RISC_PRIVCFGRx_PRIV28_Pos     (28U)
33242 #define RIFSC_RISC_PRIVCFGRx_PRIV28_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV28_Pos)      /*!< 0x10000000 */
33243 #define RIFSC_RISC_PRIVCFGRx_PRIV28         RIFSC_RISC_PRIVCFGRx_PRIV28_Msk                /*!< privileged-only access permission for peripheral 28 */
33244 #define RIFSC_RISC_PRIVCFGRx_PRIV29_Pos     (29U)
33245 #define RIFSC_RISC_PRIVCFGRx_PRIV29_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV29_Pos)      /*!< 0x20000000 */
33246 #define RIFSC_RISC_PRIVCFGRx_PRIV29         RIFSC_RISC_PRIVCFGRx_PRIV29_Msk                /*!< privileged-only access permission for peripheral 29 */
33247 #define RIFSC_RISC_PRIVCFGRx_PRIV30_Pos     (30U)
33248 #define RIFSC_RISC_PRIVCFGRx_PRIV30_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV30_Pos)      /*!< 0x40000000 */
33249 #define RIFSC_RISC_PRIVCFGRx_PRIV30         RIFSC_RISC_PRIVCFGRx_PRIV30_Msk                /*!< privileged-only access permission for peripheral 30 */
33250 #define RIFSC_RISC_PRIVCFGRx_PRIV31_Pos     (31U)
33251 #define RIFSC_RISC_PRIVCFGRx_PRIV31_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV31_Pos)      /*!< 0x80000000 */
33252 #define RIFSC_RISC_PRIVCFGRx_PRIV31         RIFSC_RISC_PRIVCFGRx_PRIV31_Msk                /*!< privileged-only access permission for peripheral 31 */
33253 
33254 /*************  Bit definition for RIFSC_RISC_RCFGLOCKRx register  *************/
33255 #define RIFSC_RISC_RCFGLOCKRx_RLOCK0_Pos    (0U)
33256 #define RIFSC_RISC_RCFGLOCKRx_RLOCK0_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK0_Pos)     /*!< 0x00000001 */
33257 #define RIFSC_RISC_RCFGLOCKRx_RLOCK0        RIFSC_RISC_RCFGLOCKRx_RLOCK0_Msk               /*!< Resource lock for peripheral 0 */
33258 #define RIFSC_RISC_RCFGLOCKRx_RLOCK1_Pos    (1U)
33259 #define RIFSC_RISC_RCFGLOCKRx_RLOCK1_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK1_Pos)     /*!< 0x00000002 */
33260 #define RIFSC_RISC_RCFGLOCKRx_RLOCK1        RIFSC_RISC_RCFGLOCKRx_RLOCK1_Msk               /*!< Resource lock for peripheral 1 */
33261 #define RIFSC_RISC_RCFGLOCKRx_RLOCK2_Pos    (2U)
33262 #define RIFSC_RISC_RCFGLOCKRx_RLOCK2_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK2_Pos)     /*!< 0x00000004 */
33263 #define RIFSC_RISC_RCFGLOCKRx_RLOCK2        RIFSC_RISC_RCFGLOCKRx_RLOCK2_Msk               /*!< Resource lock for peripheral 2 */
33264 #define RIFSC_RISC_RCFGLOCKRx_RLOCK3_Pos    (3U)
33265 #define RIFSC_RISC_RCFGLOCKRx_RLOCK3_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK3_Pos)     /*!< 0x00000008 */
33266 #define RIFSC_RISC_RCFGLOCKRx_RLOCK3        RIFSC_RISC_RCFGLOCKRx_RLOCK3_Msk               /*!< Resource lock for peripheral 3 */
33267 #define RIFSC_RISC_RCFGLOCKRx_RLOCK4_Pos    (4U)
33268 #define RIFSC_RISC_RCFGLOCKRx_RLOCK4_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK4_Pos)     /*!< 0x00000010 */
33269 #define RIFSC_RISC_RCFGLOCKRx_RLOCK4        RIFSC_RISC_RCFGLOCKRx_RLOCK4_Msk               /*!< Resource lock for peripheral 4 */
33270 #define RIFSC_RISC_RCFGLOCKRx_RLOCK5_Pos    (5U)
33271 #define RIFSC_RISC_RCFGLOCKRx_RLOCK5_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK5_Pos)     /*!< 0x00000020 */
33272 #define RIFSC_RISC_RCFGLOCKRx_RLOCK5        RIFSC_RISC_RCFGLOCKRx_RLOCK5_Msk               /*!< Resource lock for peripheral 5 */
33273 #define RIFSC_RISC_RCFGLOCKRx_RLOCK6_Pos    (6U)
33274 #define RIFSC_RISC_RCFGLOCKRx_RLOCK6_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK6_Pos)     /*!< 0x00000040 */
33275 #define RIFSC_RISC_RCFGLOCKRx_RLOCK6        RIFSC_RISC_RCFGLOCKRx_RLOCK6_Msk               /*!< Resource lock for peripheral 6 */
33276 #define RIFSC_RISC_RCFGLOCKRx_RLOCK7_Pos    (7U)
33277 #define RIFSC_RISC_RCFGLOCKRx_RLOCK7_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK7_Pos)     /*!< 0x00000080 */
33278 #define RIFSC_RISC_RCFGLOCKRx_RLOCK7        RIFSC_RISC_RCFGLOCKRx_RLOCK7_Msk               /*!< Resource lock for peripheral 7 */
33279 #define RIFSC_RISC_RCFGLOCKRx_RLOCK8_Pos    (8U)
33280 #define RIFSC_RISC_RCFGLOCKRx_RLOCK8_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK8_Pos)     /*!< 0x00000100 */
33281 #define RIFSC_RISC_RCFGLOCKRx_RLOCK8        RIFSC_RISC_RCFGLOCKRx_RLOCK8_Msk               /*!< Resource lock for peripheral 8 */
33282 #define RIFSC_RISC_RCFGLOCKRx_RLOCK9_Pos    (9U)
33283 #define RIFSC_RISC_RCFGLOCKRx_RLOCK9_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK9_Pos)     /*!< 0x00000200 */
33284 #define RIFSC_RISC_RCFGLOCKRx_RLOCK9        RIFSC_RISC_RCFGLOCKRx_RLOCK9_Msk               /*!< Resource lock for peripheral 9 */
33285 #define RIFSC_RISC_RCFGLOCKRx_RLOCK10_Pos   (10U)
33286 #define RIFSC_RISC_RCFGLOCKRx_RLOCK10_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK10_Pos)    /*!< 0x00000400 */
33287 #define RIFSC_RISC_RCFGLOCKRx_RLOCK10       RIFSC_RISC_RCFGLOCKRx_RLOCK10_Msk              /*!< Resource lock for peripheral 10 */
33288 #define RIFSC_RISC_RCFGLOCKRx_RLOCK11_Pos   (11U)
33289 #define RIFSC_RISC_RCFGLOCKRx_RLOCK11_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK11_Pos)    /*!< 0x00000800 */
33290 #define RIFSC_RISC_RCFGLOCKRx_RLOCK11       RIFSC_RISC_RCFGLOCKRx_RLOCK11_Msk              /*!< Resource lock for peripheral 11 */
33291 #define RIFSC_RISC_RCFGLOCKRx_RLOCK12_Pos   (12U)
33292 #define RIFSC_RISC_RCFGLOCKRx_RLOCK12_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK12_Pos)    /*!< 0x00001000 */
33293 #define RIFSC_RISC_RCFGLOCKRx_RLOCK12       RIFSC_RISC_RCFGLOCKRx_RLOCK12_Msk              /*!< Resource lock for peripheral 12 */
33294 #define RIFSC_RISC_RCFGLOCKRx_RLOCK13_Pos   (13U)
33295 #define RIFSC_RISC_RCFGLOCKRx_RLOCK13_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK13_Pos)    /*!< 0x00002000 */
33296 #define RIFSC_RISC_RCFGLOCKRx_RLOCK13       RIFSC_RISC_RCFGLOCKRx_RLOCK13_Msk              /*!< Resource lock for peripheral 13 */
33297 #define RIFSC_RISC_RCFGLOCKRx_RLOCK14_Pos   (14U)
33298 #define RIFSC_RISC_RCFGLOCKRx_RLOCK14_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK14_Pos)    /*!< 0x00004000 */
33299 #define RIFSC_RISC_RCFGLOCKRx_RLOCK14       RIFSC_RISC_RCFGLOCKRx_RLOCK14_Msk              /*!< Resource lock for peripheral 14 */
33300 #define RIFSC_RISC_RCFGLOCKRx_RLOCK15_Pos   (15U)
33301 #define RIFSC_RISC_RCFGLOCKRx_RLOCK15_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK15_Pos)    /*!< 0x00008000 */
33302 #define RIFSC_RISC_RCFGLOCKRx_RLOCK15       RIFSC_RISC_RCFGLOCKRx_RLOCK15_Msk              /*!< Resource lock for peripheral 15 */
33303 #define RIFSC_RISC_RCFGLOCKRx_RLOCK16_Pos   (16U)
33304 #define RIFSC_RISC_RCFGLOCKRx_RLOCK16_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK16_Pos)    /*!< 0x00010000 */
33305 #define RIFSC_RISC_RCFGLOCKRx_RLOCK16       RIFSC_RISC_RCFGLOCKRx_RLOCK16_Msk              /*!< Resource lock for peripheral 16 */
33306 #define RIFSC_RISC_RCFGLOCKRx_RLOCK17_Pos   (17U)
33307 #define RIFSC_RISC_RCFGLOCKRx_RLOCK17_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK17_Pos)    /*!< 0x00020000 */
33308 #define RIFSC_RISC_RCFGLOCKRx_RLOCK17       RIFSC_RISC_RCFGLOCKRx_RLOCK17_Msk              /*!< Resource lock for peripheral 17 */
33309 #define RIFSC_RISC_RCFGLOCKRx_RLOCK18_Pos   (18U)
33310 #define RIFSC_RISC_RCFGLOCKRx_RLOCK18_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK18_Pos)    /*!< 0x00040000 */
33311 #define RIFSC_RISC_RCFGLOCKRx_RLOCK18       RIFSC_RISC_RCFGLOCKRx_RLOCK18_Msk              /*!< Resource lock for peripheral 18 */
33312 #define RIFSC_RISC_RCFGLOCKRx_RLOCK19_Pos   (19U)
33313 #define RIFSC_RISC_RCFGLOCKRx_RLOCK19_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK19_Pos)    /*!< 0x00080000 */
33314 #define RIFSC_RISC_RCFGLOCKRx_RLOCK19       RIFSC_RISC_RCFGLOCKRx_RLOCK19_Msk              /*!< Resource lock for peripheral 19 */
33315 #define RIFSC_RISC_RCFGLOCKRx_RLOCK20_Pos   (20U)
33316 #define RIFSC_RISC_RCFGLOCKRx_RLOCK20_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK20_Pos)    /*!< 0x00100000 */
33317 #define RIFSC_RISC_RCFGLOCKRx_RLOCK20       RIFSC_RISC_RCFGLOCKRx_RLOCK20_Msk              /*!< Resource lock for peripheral 20 */
33318 #define RIFSC_RISC_RCFGLOCKRx_RLOCK21_Pos   (21U)
33319 #define RIFSC_RISC_RCFGLOCKRx_RLOCK21_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK21_Pos)    /*!< 0x00200000 */
33320 #define RIFSC_RISC_RCFGLOCKRx_RLOCK21       RIFSC_RISC_RCFGLOCKRx_RLOCK21_Msk              /*!< Resource lock for peripheral 21 */
33321 #define RIFSC_RISC_RCFGLOCKRx_RLOCK22_Pos   (22U)
33322 #define RIFSC_RISC_RCFGLOCKRx_RLOCK22_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK22_Pos)    /*!< 0x00400000 */
33323 #define RIFSC_RISC_RCFGLOCKRx_RLOCK22       RIFSC_RISC_RCFGLOCKRx_RLOCK22_Msk              /*!< Resource lock for peripheral 22 */
33324 #define RIFSC_RISC_RCFGLOCKRx_RLOCK23_Pos   (23U)
33325 #define RIFSC_RISC_RCFGLOCKRx_RLOCK23_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK23_Pos)    /*!< 0x00800000 */
33326 #define RIFSC_RISC_RCFGLOCKRx_RLOCK23       RIFSC_RISC_RCFGLOCKRx_RLOCK23_Msk              /*!< Resource lock for peripheral 23 */
33327 #define RIFSC_RISC_RCFGLOCKRx_RLOCK24_Pos   (24U)
33328 #define RIFSC_RISC_RCFGLOCKRx_RLOCK24_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK24_Pos)    /*!< 0x01000000 */
33329 #define RIFSC_RISC_RCFGLOCKRx_RLOCK24       RIFSC_RISC_RCFGLOCKRx_RLOCK24_Msk              /*!< Resource lock for peripheral 24 */
33330 #define RIFSC_RISC_RCFGLOCKRx_RLOCK25_Pos   (25U)
33331 #define RIFSC_RISC_RCFGLOCKRx_RLOCK25_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK25_Pos)    /*!< 0x02000000 */
33332 #define RIFSC_RISC_RCFGLOCKRx_RLOCK25       RIFSC_RISC_RCFGLOCKRx_RLOCK25_Msk              /*!< Resource lock for peripheral 25 */
33333 #define RIFSC_RISC_RCFGLOCKRx_RLOCK26_Pos   (26U)
33334 #define RIFSC_RISC_RCFGLOCKRx_RLOCK26_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK26_Pos)    /*!< 0x04000000 */
33335 #define RIFSC_RISC_RCFGLOCKRx_RLOCK26       RIFSC_RISC_RCFGLOCKRx_RLOCK26_Msk              /*!< Resource lock for peripheral 26 */
33336 #define RIFSC_RISC_RCFGLOCKRx_RLOCK27_Pos   (27U)
33337 #define RIFSC_RISC_RCFGLOCKRx_RLOCK27_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK27_Pos)    /*!< 0x08000000 */
33338 #define RIFSC_RISC_RCFGLOCKRx_RLOCK27       RIFSC_RISC_RCFGLOCKRx_RLOCK27_Msk              /*!< Resource lock for peripheral 27 */
33339 #define RIFSC_RISC_RCFGLOCKRx_RLOCK28_Pos   (28U)
33340 #define RIFSC_RISC_RCFGLOCKRx_RLOCK28_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK28_Pos)    /*!< 0x10000000 */
33341 #define RIFSC_RISC_RCFGLOCKRx_RLOCK28       RIFSC_RISC_RCFGLOCKRx_RLOCK28_Msk              /*!< Resource lock for peripheral 28 */
33342 #define RIFSC_RISC_RCFGLOCKRx_RLOCK29_Pos   (29U)
33343 #define RIFSC_RISC_RCFGLOCKRx_RLOCK29_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK29_Pos)    /*!< 0x20000000 */
33344 #define RIFSC_RISC_RCFGLOCKRx_RLOCK29       RIFSC_RISC_RCFGLOCKRx_RLOCK29_Msk              /*!< Resource lock for peripheral 29 */
33345 #define RIFSC_RISC_RCFGLOCKRx_RLOCK30_Pos   (30U)
33346 #define RIFSC_RISC_RCFGLOCKRx_RLOCK30_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK30_Pos)    /*!< 0x40000000 */
33347 #define RIFSC_RISC_RCFGLOCKRx_RLOCK30       RIFSC_RISC_RCFGLOCKRx_RLOCK30_Msk              /*!< Resource lock for peripheral 30 */
33348 #define RIFSC_RISC_RCFGLOCKRx_RLOCK31_Pos   (31U)
33349 #define RIFSC_RISC_RCFGLOCKRx_RLOCK31_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK31_Pos)    /*!< 0x80000000 */
33350 #define RIFSC_RISC_RCFGLOCKRx_RLOCK31       RIFSC_RISC_RCFGLOCKRx_RLOCK31_Msk              /*!< Resource lock for peripheral 31 */
33351 
33352 /****************  Bit definition for RIFSC_RIMC_CR register  *****************/
33353 #define RIFSC_RIMC_CR_GLOCK_Pos             (0U)
33354 #define RIFSC_RIMC_CR_GLOCK_Msk             (0x1UL << RIFSC_RIMC_CR_GLOCK_Pos)              /*!< 0x00000001 */
33355 #define RIFSC_RIMC_CR_GLOCK                 RIFSC_RIMC_CR_GLOCK_Msk                        /*!< Global lock */
33356 #define RIFSC_RIMC_CR_DAPCID_Pos            (8U)
33357 #define RIFSC_RIMC_CR_DAPCID_Msk            (0x7UL << RIFSC_RIMC_CR_DAPCID_Pos)             /*!< 0x00000700 */
33358 #define RIFSC_RIMC_CR_DAPCID                RIFSC_RIMC_CR_DAPCID_Msk                       /*!< Debug access port compartment ID */
33359 #define RIFSC_RIMC_CR_DAPCID_0              (0x1UL << RIFSC_RIMC_CR_DAPCID_Pos)             /*!< 0x00000100 */
33360 #define RIFSC_RIMC_CR_DAPCID_1              (0x2UL << RIFSC_RIMC_CR_DAPCID_Pos)             /*!< 0x00000200 */
33361 #define RIFSC_RIMC_CR_DAPCID_2              (0x4UL << RIFSC_RIMC_CR_DAPCID_Pos)             /*!< 0x00000400 */
33362 
33363 /***************  Bit definition for RIFSC_RIMC_ATTRx register  ***************/
33364 #define RIFSC_RIMC_ATTRx_MCID_Pos           (4U)
33365 #define RIFSC_RIMC_ATTRx_MCID_Msk           (0x7UL << RIFSC_RIMC_ATTRx_MCID_Pos)            /*!< 0x00000070 */
33366 #define RIFSC_RIMC_ATTRx_MCID               RIFSC_RIMC_ATTRx_MCID_Msk                      /*!< Master CID */
33367 #define RIFSC_RIMC_ATTRx_MCID_0             (0x1UL << RIFSC_RIMC_ATTRx_MCID_Pos)            /*!< 0x00000010 */
33368 #define RIFSC_RIMC_ATTRx_MCID_1             (0x2UL << RIFSC_RIMC_ATTRx_MCID_Pos)            /*!< 0x00000020 */
33369 #define RIFSC_RIMC_ATTRx_MCID_2             (0x4UL << RIFSC_RIMC_ATTRx_MCID_Pos)            /*!< 0x00000040 */
33370 #define RIFSC_RIMC_ATTRx_MSEC_Pos           (8U)
33371 #define RIFSC_RIMC_ATTRx_MSEC_Msk           (0x1UL << RIFSC_RIMC_ATTRx_MSEC_Pos)            /*!< 0x00000100 */
33372 #define RIFSC_RIMC_ATTRx_MSEC               RIFSC_RIMC_ATTRx_MSEC_Msk                      /*!< Master secure */
33373 #define RIFSC_RIMC_ATTRx_MPRIV_Pos          (9U)
33374 #define RIFSC_RIMC_ATTRx_MPRIV_Msk          (0x1UL << RIFSC_RIMC_ATTRx_MPRIV_Pos)           /*!< 0x00000200 */
33375 #define RIFSC_RIMC_ATTRx_MPRIV              RIFSC_RIMC_ATTRx_MPRIV_Msk                     /*!< Master privileged */
33376 
33377 /******************************************************************************/
33378 /*                                                                            */
33379 /*     Resource Isolation Slave unit for Address space protection (RISAF)     */
33380 /*                                                                            */
33381 /******************************************************************************/
33382 /*******************  Bit definition for RISAF_CR register  *******************/
33383 #define RISAF_CR_GLOCK_Pos                 (0U)
33384 #define RISAF_CR_GLOCK_Msk                 (0x1UL << RISAF_CR_GLOCK_Pos)                      /*!< 0x00000001 */
33385 #define RISAF_CR_GLOCK                     RISAF_CR_GLOCK_Msk                                /*!< Global lock */
33386 
33387 /******************  Bit definition for RISAF_IASR register  ******************/
33388 #define RISAF_IASR_CAEF_Pos                (0U)
33389 #define RISAF_IASR_CAEF_Msk                (0x1UL << RISAF_IASR_CAEF_Pos)                     /*!< 0x00000001 */
33390 #define RISAF_IASR_CAEF                    RISAF_IASR_CAEF_Msk                               /*!< Configuration access error flag */
33391 #define RISAF_IASR_IAEF_Pos                (1U)
33392 #define RISAF_IASR_IAEF_Msk                (0x1UL << RISAF_IASR_IAEF_Pos)                     /*!< 0x00000002 */
33393 #define RISAF_IASR_IAEF                    RISAF_IASR_IAEF_Msk                               /*!< Illegal access error flag */
33394 
33395 /******************  Bit definition for RISAF_IACR register  ******************/
33396 #define RISAF_IACR_CAEF_Pos                (0U)
33397 #define RISAF_IACR_CAEF_Msk                (0x1UL << RISAF_IACR_CAEF_Pos)                     /*!< 0x00000001 */
33398 #define RISAF_IACR_CAEF                    RISAF_IACR_CAEF_Msk                               /*!< Configuration access error flag */
33399 #define RISAF_IACR_IAEF_Pos                (1U)
33400 #define RISAF_IACR_IAEF_Msk                (0x1UL << RISAF_IACR_IAEF_Pos)                     /*!< 0x00000002 */
33401 #define RISAF_IACR_IAEF                    RISAF_IACR_IAEF_Msk                               /*!< Illegal access error flag */
33402 
33403 /*****************  Bit definition for RISAF_IAESR register  *****************/
33404 #define RISAF_IAESR_IACID_Pos              (0U)
33405 #define RISAF_IAESR_IACID_Msk              (0x7UL << RISAF_IAESR_IACID_Pos)                  /*!< 0x00000007 */
33406 #define RISAF_IAESR_IACID                  RISAF_IAESR_IACID_Msk                            /*!< Illegal access compartment ID */
33407 #define RISAF_IAESR_IACID_0                (0x1UL << RISAF_IAESR_IACID_Pos)                  /*!< 0x00000001 */
33408 #define RISAF_IAESR_IACID_1                (0x2UL << RISAF_IAESR_IACID_Pos)                  /*!< 0x00000002 */
33409 #define RISAF_IAESR_IACID_2                (0x4UL << RISAF_IAESR_IACID_Pos)                  /*!< 0x00000004 */
33410 #define RISAF_IAESR_IAPRIV_Pos             (4U)
33411 #define RISAF_IAESR_IAPRIV_Msk             (0x1UL << RISAF_IAESR_IAPRIV_Pos)                 /*!< 0x00000010 */
33412 #define RISAF_IAESR_IAPRIV                 RISAF_IAESR_IAPRIV_Msk                           /*!< Illegal access privileged */
33413 #define RISAF_IAESR_IASEC_Pos              (5U)
33414 #define RISAF_IAESR_IASEC_Msk              (0x1UL << RISAF_IAESR_IASEC_Pos)                  /*!< 0x00000020 */
33415 #define RISAF_IAESR_IASEC                  RISAF_IAESR_IASEC_Msk                            /*!< Illegal access security */
33416 #define RISAF_IAESR_IANRW_Pos              (7U)
33417 #define RISAF_IAESR_IANRW_Msk              (0x1UL << RISAF_IAESR_IANRW_Pos)                  /*!< 0x00000080 */
33418 #define RISAF_IAESR_IANRW                  RISAF_IAESR_IANRW_Msk                            /*!< Illegal access read/write */
33419 
33420 /*****************  Bit definition for RISAF_IADDR register  *****************/
33421 #define RISAF_IADDR_IADD_Pos                (0U)
33422 #define RISAF_IADDR_IADD_Msk                (0xFFFFFFFFUL << RISAF_IADDR_IADD_Pos)            /*!< 0xFFFFFFFF */
33423 #define RISAF_IADDR_IADD                    RISAF_IADDR_IADD_Msk                             /*!< Illegal address */
33424 #define RISAF_IADDR_IADD_0                  (0x1UL << RISAF_IADDR_IADD_Pos)                   /*!< 0x00000001 */
33425 #define RISAF_IADDR_IADD_1                  (0x2UL << RISAF_IADDR_IADD_Pos)                   /*!< 0x00000002 */
33426 #define RISAF_IADDR_IADD_2                  (0x4UL << RISAF_IADDR_IADD_Pos)                   /*!< 0x00000004 */
33427 #define RISAF_IADDR_IADD_3                  (0x8UL << RISAF_IADDR_IADD_Pos)                   /*!< 0x00000008 */
33428 #define RISAF_IADDR_IADD_4                  (0x10UL << RISAF_IADDR_IADD_Pos)                  /*!< 0x00000010 */
33429 #define RISAF_IADDR_IADD_5                  (0x20UL << RISAF_IADDR_IADD_Pos)                  /*!< 0x00000020 */
33430 #define RISAF_IADDR_IADD_6                  (0x40UL << RISAF_IADDR_IADD_Pos)                  /*!< 0x00000040 */
33431 #define RISAF_IADDR_IADD_7                  (0x80UL << RISAF_IADDR_IADD_Pos)                  /*!< 0x00000080 */
33432 #define RISAF_IADDR_IADD_8                  (0x100UL << RISAF_IADDR_IADD_Pos)                 /*!< 0x00000100 */
33433 #define RISAF_IADDR_IADD_9                  (0x200UL << RISAF_IADDR_IADD_Pos)                 /*!< 0x00000200 */
33434 #define RISAF_IADDR_IADD_10                 (0x400UL << RISAF_IADDR_IADD_Pos)                 /*!< 0x00000400 */
33435 #define RISAF_IADDR_IADD_11                 (0x800UL << RISAF_IADDR_IADD_Pos)                 /*!< 0x00000800 */
33436 #define RISAF_IADDR_IADD_12                 (0x1000UL << RISAF_IADDR_IADD_Pos)                /*!< 0x00001000 */
33437 #define RISAF_IADDR_IADD_13                 (0x2000UL << RISAF_IADDR_IADD_Pos)                /*!< 0x00002000 */
33438 #define RISAF_IADDR_IADD_14                 (0x4000UL << RISAF_IADDR_IADD_Pos)                /*!< 0x00004000 */
33439 #define RISAF_IADDR_IADD_15                 (0x8000UL << RISAF_IADDR_IADD_Pos)                /*!< 0x00008000 */
33440 #define RISAF_IADDR_IADD_16                 (0x10000UL << RISAF_IADDR_IADD_Pos)               /*!< 0x00010000 */
33441 #define RISAF_IADDR_IADD_17                 (0x20000UL << RISAF_IADDR_IADD_Pos)               /*!< 0x00020000 */
33442 #define RISAF_IADDR_IADD_18                 (0x40000UL << RISAF_IADDR_IADD_Pos)               /*!< 0x00040000 */
33443 #define RISAF_IADDR_IADD_19                 (0x80000UL << RISAF_IADDR_IADD_Pos)               /*!< 0x00080000 */
33444 #define RISAF_IADDR_IADD_20                 (0x100000UL << RISAF_IADDR_IADD_Pos)              /*!< 0x00100000 */
33445 #define RISAF_IADDR_IADD_21                 (0x200000UL << RISAF_IADDR_IADD_Pos)              /*!< 0x00200000 */
33446 #define RISAF_IADDR_IADD_22                 (0x400000UL << RISAF_IADDR_IADD_Pos)              /*!< 0x00400000 */
33447 #define RISAF_IADDR_IADD_23                 (0x800000UL << RISAF_IADDR_IADD_Pos)              /*!< 0x00800000 */
33448 #define RISAF_IADDR_IADD_24                 (0x1000000UL << RISAF_IADDR_IADD_Pos)             /*!< 0x01000000 */
33449 #define RISAF_IADDR_IADD_25                 (0x2000000UL << RISAF_IADDR_IADD_Pos)             /*!< 0x02000000 */
33450 #define RISAF_IADDR_IADD_26                 (0x4000000UL << RISAF_IADDR_IADD_Pos)             /*!< 0x04000000 */
33451 #define RISAF_IADDR_IADD_27                 (0x8000000UL << RISAF_IADDR_IADD_Pos)             /*!< 0x08000000 */
33452 #define RISAF_IADDR_IADD_28                 (0x10000000UL << RISAF_IADDR_IADD_Pos)            /*!< 0x10000000 */
33453 #define RISAF_IADDR_IADD_29                 (0x20000000UL << RISAF_IADDR_IADD_Pos)            /*!< 0x20000000 */
33454 #define RISAF_IADDR_IADD_30                 (0x40000000UL << RISAF_IADDR_IADD_Pos)            /*!< 0x40000000 */
33455 #define RISAF_IADDR_IADD_31                 (0x80000000UL << RISAF_IADDR_IADD_Pos)            /*!< 0x80000000 */
33456 
33457 /***************  Bit definition for RISAF_REGx_CFGR register  ****************/
33458 #define RISAF_REGx_CFGR_BREN_Pos           (0U)
33459 #define RISAF_REGx_CFGR_BREN_Msk           (0x1UL << RISAF_REGx_CFGR_BREN_Pos)                /*!< 0x00000001 */
33460 #define RISAF_REGx_CFGR_BREN               RISAF_REGx_CFGR_BREN_Msk                          /*!< Base region enable */
33461 #define RISAF_REGx_CFGR_SEC_Pos            (8U)
33462 #define RISAF_REGx_CFGR_SEC_Msk            (0x1UL << RISAF_REGx_CFGR_SEC_Pos)                 /*!< 0x00000100 */
33463 #define RISAF_REGx_CFGR_SEC                RISAF_REGx_CFGR_SEC_Msk                           /*!< Secure region */
33464 #define RISAF_REGx_CFGR_PRIVC0_Pos         (16U)
33465 #define RISAF_REGx_CFGR_PRIVC0_Msk         (0x1UL << RISAF_REGx_CFGR_PRIVC0_Pos)              /*!< 0x00010000 */
33466 #define RISAF_REGx_CFGR_PRIVC0             RISAF_REGx_CFGR_PRIVC0_Msk                        /*!< Privileged access for compartment 0 */
33467 #define RISAF_REGx_CFGR_PRIVC1_Pos         (17U)
33468 #define RISAF_REGx_CFGR_PRIVC1_Msk         (0x1UL << RISAF_REGx_CFGR_PRIVC1_Pos)              /*!< 0x00020000 */
33469 #define RISAF_REGx_CFGR_PRIVC1             RISAF_REGx_CFGR_PRIVC1_Msk                        /*!< Privileged access for compartment 1 */
33470 #define RISAF_REGx_CFGR_PRIVC2_Pos         (18U)
33471 #define RISAF_REGx_CFGR_PRIVC2_Msk         (0x1UL << RISAF_REGx_CFGR_PRIVC2_Pos)              /*!< 0x00040000 */
33472 #define RISAF_REGx_CFGR_PRIVC2             RISAF_REGx_CFGR_PRIVC2_Msk                        /*!< Privileged access for compartment 2 */
33473 #define RISAF_REGx_CFGR_PRIVC3_Pos         (19U)
33474 #define RISAF_REGx_CFGR_PRIVC3_Msk         (0x1UL << RISAF_REGx_CFGR_PRIVC3_Pos)              /*!< 0x00080000 */
33475 #define RISAF_REGx_CFGR_PRIVC3             RISAF_REGx_CFGR_PRIVC3_Msk                        /*!< Privileged access for compartment 3 */
33476 #define RISAF_REGx_CFGR_PRIVC4_Pos         (20U)
33477 #define RISAF_REGx_CFGR_PRIVC4_Msk         (0x1UL << RISAF_REGx_CFGR_PRIVC4_Pos)              /*!< 0x00100000 */
33478 #define RISAF_REGx_CFGR_PRIVC4             RISAF_REGx_CFGR_PRIVC4_Msk                        /*!< Privileged access for compartment 4 */
33479 #define RISAF_REGx_CFGR_PRIVC5_Pos         (21U)
33480 #define RISAF_REGx_CFGR_PRIVC5_Msk         (0x1UL << RISAF_REGx_CFGR_PRIVC5_Pos)              /*!< 0x00200000 */
33481 #define RISAF_REGx_CFGR_PRIVC5             RISAF_REGx_CFGR_PRIVC5_Msk                        /*!< Privileged access for compartment 5 */
33482 #define RISAF_REGx_CFGR_PRIVC6_Pos         (22U)
33483 #define RISAF_REGx_CFGR_PRIVC6_Msk         (0x1UL << RISAF_REGx_CFGR_PRIVC6_Pos)              /*!< 0x00400000 */
33484 #define RISAF_REGx_CFGR_PRIVC6             RISAF_REGx_CFGR_PRIVC6_Msk                        /*!< Privileged access for compartment 6 */
33485 #define RISAF_REGx_CFGR_PRIVC7_Pos         (23U)
33486 #define RISAF_REGx_CFGR_PRIVC7_Msk         (0x1UL << RISAF_REGx_CFGR_PRIVC7_Pos)              /*!< 0x00800000 */
33487 #define RISAF_REGx_CFGR_PRIVC7             RISAF_REGx_CFGR_PRIVC7_Msk                        /*!< Privileged access for compartment 7 */
33488 
33489 /**************  Bit definition for RISAF_REGx_STARTR register  ***************/
33490 #define RISAF_REGx_STARTR_BADDSTART_Pos    (0U)
33491 #define RISAF_REGx_STARTR_BADDSTART_Msk    (0xFFFFFFFFUL << RISAF_REGx_STARTR_BADDSTART_Pos)  /*!< 0xFFFFFFFF */
33492 #define RISAF_REGx_STARTR_BADDSTART        RISAF_REGx_STARTR_BADDSTART_Msk                   /*!< Base region address start */
33493 #define RISAF_REGx_STARTR_BADDSTART_0      (0x1UL << RISAF_REGx_STARTR_BADDSTART_Pos)         /*!< 0x00000001 */
33494 #define RISAF_REGx_STARTR_BADDSTART_1      (0x2UL << RISAF_REGx_STARTR_BADDSTART_Pos)         /*!< 0x00000002 */
33495 #define RISAF_REGx_STARTR_BADDSTART_2      (0x4UL << RISAF_REGx_STARTR_BADDSTART_Pos)         /*!< 0x00000004 */
33496 #define RISAF_REGx_STARTR_BADDSTART_3      (0x8UL << RISAF_REGx_STARTR_BADDSTART_Pos)         /*!< 0x00000008 */
33497 #define RISAF_REGx_STARTR_BADDSTART_4      (0x10UL << RISAF_REGx_STARTR_BADDSTART_Pos)        /*!< 0x00000010 */
33498 #define RISAF_REGx_STARTR_BADDSTART_5      (0x20UL << RISAF_REGx_STARTR_BADDSTART_Pos)        /*!< 0x00000020 */
33499 #define RISAF_REGx_STARTR_BADDSTART_6      (0x40UL << RISAF_REGx_STARTR_BADDSTART_Pos)        /*!< 0x00000040 */
33500 #define RISAF_REGx_STARTR_BADDSTART_7      (0x80UL << RISAF_REGx_STARTR_BADDSTART_Pos)        /*!< 0x00000080 */
33501 #define RISAF_REGx_STARTR_BADDSTART_8      (0x100UL << RISAF_REGx_STARTR_BADDSTART_Pos)       /*!< 0x00000100 */
33502 #define RISAF_REGx_STARTR_BADDSTART_9      (0x200UL << RISAF_REGx_STARTR_BADDSTART_Pos)       /*!< 0x00000200 */
33503 #define RISAF_REGx_STARTR_BADDSTART_10     (0x400UL << RISAF_REGx_STARTR_BADDSTART_Pos)       /*!< 0x00000400 */
33504 #define RISAF_REGx_STARTR_BADDSTART_11     (0x800UL << RISAF_REGx_STARTR_BADDSTART_Pos)       /*!< 0x00000800 */
33505 #define RISAF_REGx_STARTR_BADDSTART_12     (0x1000UL << RISAF_REGx_STARTR_BADDSTART_Pos)      /*!< 0x00001000 */
33506 #define RISAF_REGx_STARTR_BADDSTART_13     (0x2000UL << RISAF_REGx_STARTR_BADDSTART_Pos)      /*!< 0x00002000 */
33507 #define RISAF_REGx_STARTR_BADDSTART_14     (0x4000UL << RISAF_REGx_STARTR_BADDSTART_Pos)      /*!< 0x00004000 */
33508 #define RISAF_REGx_STARTR_BADDSTART_15     (0x8000UL << RISAF_REGx_STARTR_BADDSTART_Pos)      /*!< 0x00008000 */
33509 #define RISAF_REGx_STARTR_BADDSTART_16     (0x10000UL << RISAF_REGx_STARTR_BADDSTART_Pos)     /*!< 0x00010000 */
33510 #define RISAF_REGx_STARTR_BADDSTART_17     (0x20000UL << RISAF_REGx_STARTR_BADDSTART_Pos)     /*!< 0x00020000 */
33511 #define RISAF_REGx_STARTR_BADDSTART_18     (0x40000UL << RISAF_REGx_STARTR_BADDSTART_Pos)     /*!< 0x00040000 */
33512 #define RISAF_REGx_STARTR_BADDSTART_19     (0x80000UL << RISAF_REGx_STARTR_BADDSTART_Pos)     /*!< 0x00080000 */
33513 #define RISAF_REGx_STARTR_BADDSTART_20     (0x100000UL << RISAF_REGx_STARTR_BADDSTART_Pos)    /*!< 0x00100000 */
33514 #define RISAF_REGx_STARTR_BADDSTART_21     (0x200000UL << RISAF_REGx_STARTR_BADDSTART_Pos)    /*!< 0x00200000 */
33515 #define RISAF_REGx_STARTR_BADDSTART_22     (0x400000UL << RISAF_REGx_STARTR_BADDSTART_Pos)    /*!< 0x00400000 */
33516 #define RISAF_REGx_STARTR_BADDSTART_23     (0x800000UL << RISAF_REGx_STARTR_BADDSTART_Pos)    /*!< 0x00800000 */
33517 #define RISAF_REGx_STARTR_BADDSTART_24     (0x1000000UL << RISAF_REGx_STARTR_BADDSTART_Pos)   /*!< 0x01000000 */
33518 #define RISAF_REGx_STARTR_BADDSTART_25     (0x2000000UL << RISAF_REGx_STARTR_BADDSTART_Pos)   /*!< 0x02000000 */
33519 #define RISAF_REGx_STARTR_BADDSTART_26     (0x4000000UL << RISAF_REGx_STARTR_BADDSTART_Pos)   /*!< 0x04000000 */
33520 #define RISAF_REGx_STARTR_BADDSTART_27     (0x8000000UL << RISAF_REGx_STARTR_BADDSTART_Pos)   /*!< 0x08000000 */
33521 #define RISAF_REGx_STARTR_BADDSTART_28     (0x10000000UL << RISAF_REGx_STARTR_BADDSTART_Pos)  /*!< 0x10000000 */
33522 #define RISAF_REGx_STARTR_BADDSTART_29     (0x20000000UL << RISAF_REGx_STARTR_BADDSTART_Pos)  /*!< 0x20000000 */
33523 #define RISAF_REGx_STARTR_BADDSTART_30     (0x40000000UL << RISAF_REGx_STARTR_BADDSTART_Pos)  /*!< 0x40000000 */
33524 #define RISAF_REGx_STARTR_BADDSTART_31     (0x80000000UL << RISAF_REGx_STARTR_BADDSTART_Pos)  /*!< 0x80000000 */
33525 
33526 /***************  Bit definition for RISAF_REGx_ENDR register  ****************/
33527 #define RISAF_REGx_ENDR_BADDEND_Pos        (0U)
33528 #define RISAF_REGx_ENDR_BADDEND_Msk        (0xFFFFFFFFUL << RISAF_REGx_ENDR_BADDEND_Pos)      /*!< 0xFFFFFFFF */
33529 #define RISAF_REGx_ENDR_BADDEND            RISAF_REGx_ENDR_BADDEND_Msk                       /*!< Base region address end */
33530 #define RISAF_REGx_ENDR_BADDEND_0          (0x1UL << RISAF_REGx_ENDR_BADDEND_Pos)             /*!< 0x00000001 */
33531 #define RISAF_REGx_ENDR_BADDEND_1          (0x2UL << RISAF_REGx_ENDR_BADDEND_Pos)             /*!< 0x00000002 */
33532 #define RISAF_REGx_ENDR_BADDEND_2          (0x4UL << RISAF_REGx_ENDR_BADDEND_Pos)             /*!< 0x00000004 */
33533 #define RISAF_REGx_ENDR_BADDEND_3          (0x8UL << RISAF_REGx_ENDR_BADDEND_Pos)             /*!< 0x00000008 */
33534 #define RISAF_REGx_ENDR_BADDEND_4          (0x10UL << RISAF_REGx_ENDR_BADDEND_Pos)            /*!< 0x00000010 */
33535 #define RISAF_REGx_ENDR_BADDEND_5          (0x20UL << RISAF_REGx_ENDR_BADDEND_Pos)            /*!< 0x00000020 */
33536 #define RISAF_REGx_ENDR_BADDEND_6          (0x40UL << RISAF_REGx_ENDR_BADDEND_Pos)            /*!< 0x00000040 */
33537 #define RISAF_REGx_ENDR_BADDEND_7          (0x80UL << RISAF_REGx_ENDR_BADDEND_Pos)            /*!< 0x00000080 */
33538 #define RISAF_REGx_ENDR_BADDEND_8          (0x100UL << RISAF_REGx_ENDR_BADDEND_Pos)           /*!< 0x00000100 */
33539 #define RISAF_REGx_ENDR_BADDEND_9          (0x200UL << RISAF_REGx_ENDR_BADDEND_Pos)           /*!< 0x00000200 */
33540 #define RISAF_REGx_ENDR_BADDEND_10         (0x400UL << RISAF_REGx_ENDR_BADDEND_Pos)           /*!< 0x00000400 */
33541 #define RISAF_REGx_ENDR_BADDEND_11         (0x800UL << RISAF_REGx_ENDR_BADDEND_Pos)           /*!< 0x00000800 */
33542 #define RISAF_REGx_ENDR_BADDEND_12         (0x1000UL << RISAF_REGx_ENDR_BADDEND_Pos)          /*!< 0x00001000 */
33543 #define RISAF_REGx_ENDR_BADDEND_13         (0x2000UL << RISAF_REGx_ENDR_BADDEND_Pos)          /*!< 0x00002000 */
33544 #define RISAF_REGx_ENDR_BADDEND_14         (0x4000UL << RISAF_REGx_ENDR_BADDEND_Pos)          /*!< 0x00004000 */
33545 #define RISAF_REGx_ENDR_BADDEND_15         (0x8000UL << RISAF_REGx_ENDR_BADDEND_Pos)          /*!< 0x00008000 */
33546 #define RISAF_REGx_ENDR_BADDEND_16         (0x10000UL << RISAF_REGx_ENDR_BADDEND_Pos)         /*!< 0x00010000 */
33547 #define RISAF_REGx_ENDR_BADDEND_17         (0x20000UL << RISAF_REGx_ENDR_BADDEND_Pos)         /*!< 0x00020000 */
33548 #define RISAF_REGx_ENDR_BADDEND_18         (0x40000UL << RISAF_REGx_ENDR_BADDEND_Pos)         /*!< 0x00040000 */
33549 #define RISAF_REGx_ENDR_BADDEND_19         (0x80000UL << RISAF_REGx_ENDR_BADDEND_Pos)         /*!< 0x00080000 */
33550 #define RISAF_REGx_ENDR_BADDEND_20         (0x100000UL << RISAF_REGx_ENDR_BADDEND_Pos)        /*!< 0x00100000 */
33551 #define RISAF_REGx_ENDR_BADDEND_21         (0x200000UL << RISAF_REGx_ENDR_BADDEND_Pos)        /*!< 0x00200000 */
33552 #define RISAF_REGx_ENDR_BADDEND_22         (0x400000UL << RISAF_REGx_ENDR_BADDEND_Pos)        /*!< 0x00400000 */
33553 #define RISAF_REGx_ENDR_BADDEND_23         (0x800000UL << RISAF_REGx_ENDR_BADDEND_Pos)        /*!< 0x00800000 */
33554 #define RISAF_REGx_ENDR_BADDEND_24         (0x1000000UL << RISAF_REGx_ENDR_BADDEND_Pos)       /*!< 0x01000000 */
33555 #define RISAF_REGx_ENDR_BADDEND_25         (0x2000000UL << RISAF_REGx_ENDR_BADDEND_Pos)       /*!< 0x02000000 */
33556 #define RISAF_REGx_ENDR_BADDEND_26         (0x4000000UL << RISAF_REGx_ENDR_BADDEND_Pos)       /*!< 0x04000000 */
33557 #define RISAF_REGx_ENDR_BADDEND_27         (0x8000000UL << RISAF_REGx_ENDR_BADDEND_Pos)       /*!< 0x08000000 */
33558 #define RISAF_REGx_ENDR_BADDEND_28         (0x10000000UL << RISAF_REGx_ENDR_BADDEND_Pos)      /*!< 0x10000000 */
33559 #define RISAF_REGx_ENDR_BADDEND_29         (0x20000000UL << RISAF_REGx_ENDR_BADDEND_Pos)      /*!< 0x20000000 */
33560 #define RISAF_REGx_ENDR_BADDEND_30         (0x40000000UL << RISAF_REGx_ENDR_BADDEND_Pos)      /*!< 0x40000000 */
33561 #define RISAF_REGx_ENDR_BADDEND_31         (0x80000000UL << RISAF_REGx_ENDR_BADDEND_Pos)      /*!< 0x80000000 */
33562 
33563 /**************  Bit definition for RISAF_REGx_CIDCFGR register  **************/
33564 #define RISAF_REGx_CIDCFGR_RDENC0_Pos      (0U)
33565 #define RISAF_REGx_CIDCFGR_RDENC0_Msk      (0x1UL << RISAF_REGx_CIDCFGR_RDENC0_Pos)           /*!< 0x00000001 */
33566 #define RISAF_REGx_CIDCFGR_RDENC0          RISAF_REGx_CIDCFGR_RDENC0_Msk                     /*!< Read enable for compartment 0 */
33567 #define RISAF_REGx_CIDCFGR_RDENC1_Pos      (1U)
33568 #define RISAF_REGx_CIDCFGR_RDENC1_Msk      (0x1UL << RISAF_REGx_CIDCFGR_RDENC1_Pos)           /*!< 0x00000002 */
33569 #define RISAF_REGx_CIDCFGR_RDENC1          RISAF_REGx_CIDCFGR_RDENC1_Msk                     /*!< Read enable for compartment 1 */
33570 #define RISAF_REGx_CIDCFGR_RDENC2_Pos      (2U)
33571 #define RISAF_REGx_CIDCFGR_RDENC2_Msk      (0x1UL << RISAF_REGx_CIDCFGR_RDENC2_Pos)           /*!< 0x00000004 */
33572 #define RISAF_REGx_CIDCFGR_RDENC2          RISAF_REGx_CIDCFGR_RDENC2_Msk                     /*!< Read enable for compartment 2 */
33573 #define RISAF_REGx_CIDCFGR_RDENC3_Pos      (3U)
33574 #define RISAF_REGx_CIDCFGR_RDENC3_Msk      (0x1UL << RISAF_REGx_CIDCFGR_RDENC3_Pos)           /*!< 0x00000008 */
33575 #define RISAF_REGx_CIDCFGR_RDENC3          RISAF_REGx_CIDCFGR_RDENC3_Msk                     /*!< Read enable for compartment 3 */
33576 #define RISAF_REGx_CIDCFGR_RDENC4_Pos      (4U)
33577 #define RISAF_REGx_CIDCFGR_RDENC4_Msk      (0x1UL << RISAF_REGx_CIDCFGR_RDENC4_Pos)           /*!< 0x00000010 */
33578 #define RISAF_REGx_CIDCFGR_RDENC4          RISAF_REGx_CIDCFGR_RDENC4_Msk                     /*!< Read enable for compartment 4 */
33579 #define RISAF_REGx_CIDCFGR_RDENC5_Pos      (5U)
33580 #define RISAF_REGx_CIDCFGR_RDENC5_Msk      (0x1UL << RISAF_REGx_CIDCFGR_RDENC5_Pos)           /*!< 0x00000020 */
33581 #define RISAF_REGx_CIDCFGR_RDENC5          RISAF_REGx_CIDCFGR_RDENC5_Msk                     /*!< Read enable for compartment 5 */
33582 #define RISAF_REGx_CIDCFGR_RDENC6_Pos      (6U)
33583 #define RISAF_REGx_CIDCFGR_RDENC6_Msk      (0x1UL << RISAF_REGx_CIDCFGR_RDENC6_Pos)           /*!< 0x00000040 */
33584 #define RISAF_REGx_CIDCFGR_RDENC6          RISAF_REGx_CIDCFGR_RDENC6_Msk                     /*!< Read enable for compartment 6 */
33585 #define RISAF_REGx_CIDCFGR_RDENC7_Pos      (7U)
33586 #define RISAF_REGx_CIDCFGR_RDENC7_Msk      (0x1UL << RISAF_REGx_CIDCFGR_RDENC7_Pos)           /*!< 0x00000080 */
33587 #define RISAF_REGx_CIDCFGR_RDENC7          RISAF_REGx_CIDCFGR_RDENC7_Msk                     /*!< Read enable for compartment 7 */
33588 #define RISAF_REGx_CIDCFGR_WRENC0_Pos      (16U)
33589 #define RISAF_REGx_CIDCFGR_WRENC0_Msk      (0x1UL << RISAF_REGx_CIDCFGR_WRENC0_Pos)           /*!< 0x00010000 */
33590 #define RISAF_REGx_CIDCFGR_WRENC0          RISAF_REGx_CIDCFGR_WRENC0_Msk                     /*!< Write enable for compartment 0 */
33591 #define RISAF_REGx_CIDCFGR_WRENC1_Pos      (17U)
33592 #define RISAF_REGx_CIDCFGR_WRENC1_Msk      (0x1UL << RISAF_REGx_CIDCFGR_WRENC1_Pos)           /*!< 0x00020000 */
33593 #define RISAF_REGx_CIDCFGR_WRENC1          RISAF_REGx_CIDCFGR_WRENC1_Msk                     /*!< Write enable for compartment 1 */
33594 #define RISAF_REGx_CIDCFGR_WRENC2_Pos      (18U)
33595 #define RISAF_REGx_CIDCFGR_WRENC2_Msk      (0x1UL << RISAF_REGx_CIDCFGR_WRENC2_Pos)           /*!< 0x00040000 */
33596 #define RISAF_REGx_CIDCFGR_WRENC2          RISAF_REGx_CIDCFGR_WRENC2_Msk                     /*!< Write enable for compartment 2 */
33597 #define RISAF_REGx_CIDCFGR_WRENC3_Pos      (19U)
33598 #define RISAF_REGx_CIDCFGR_WRENC3_Msk      (0x1UL << RISAF_REGx_CIDCFGR_WRENC3_Pos)           /*!< 0x00080000 */
33599 #define RISAF_REGx_CIDCFGR_WRENC3          RISAF_REGx_CIDCFGR_WRENC3_Msk                     /*!< Write enable for compartment 3 */
33600 #define RISAF_REGx_CIDCFGR_WRENC4_Pos      (20U)
33601 #define RISAF_REGx_CIDCFGR_WRENC4_Msk      (0x1UL << RISAF_REGx_CIDCFGR_WRENC4_Pos)           /*!< 0x00100000 */
33602 #define RISAF_REGx_CIDCFGR_WRENC4          RISAF_REGx_CIDCFGR_WRENC4_Msk                     /*!< Write enable for compartment 4 */
33603 #define RISAF_REGx_CIDCFGR_WRENC5_Pos      (21U)
33604 #define RISAF_REGx_CIDCFGR_WRENC5_Msk      (0x1UL << RISAF_REGx_CIDCFGR_WRENC5_Pos)           /*!< 0x00200000 */
33605 #define RISAF_REGx_CIDCFGR_WRENC5          RISAF_REGx_CIDCFGR_WRENC5_Msk                     /*!< Write enable for compartment 5 */
33606 #define RISAF_REGx_CIDCFGR_WRENC6_Pos      (22U)
33607 #define RISAF_REGx_CIDCFGR_WRENC6_Msk      (0x1UL << RISAF_REGx_CIDCFGR_WRENC6_Pos)           /*!< 0x00400000 */
33608 #define RISAF_REGx_CIDCFGR_WRENC6          RISAF_REGx_CIDCFGR_WRENC6_Msk                     /*!< Write enable for compartment 6 */
33609 #define RISAF_REGx_CIDCFGR_WRENC7_Pos      (23U)
33610 #define RISAF_REGx_CIDCFGR_WRENC7_Msk      (0x1UL << RISAF_REGx_CIDCFGR_WRENC7_Pos)           /*!< 0x00800000 */
33611 #define RISAF_REGx_CIDCFGR_WRENC7          RISAF_REGx_CIDCFGR_WRENC7_Msk                     /*!< Write enable for compartment 7 */
33612 
33613 /***************  Bit definition for RISAF_REGx_zCFGR register  ***************/
33614 #define RISAF_REGx_zCFGR_SREN_Pos          (0U)
33615 #define RISAF_REGx_zCFGR_SREN_Msk          (0x1UL << RISAF_REGx_zCFGR_SREN_Pos)               /*!< 0x00000001 */
33616 #define RISAF_REGx_zCFGR_SREN              RISAF_REGx_zCFGR_SREN_Msk                         /*!< Subregion enable */
33617 #define RISAF_REGx_zCFGR_RLOCK_Pos         (1U)
33618 #define RISAF_REGx_zCFGR_RLOCK_Msk         (0x1UL << RISAF_REGx_zCFGR_RLOCK_Pos)              /*!< 0x00000002 */
33619 #define RISAF_REGx_zCFGR_RLOCK             RISAF_REGx_zCFGR_RLOCK_Msk                        /*!< Resource lock */
33620 #define RISAF_REGx_zCFGR_SRCID_Pos         (4U)
33621 #define RISAF_REGx_zCFGR_SRCID_Msk         (0x7UL << RISAF_REGx_zCFGR_SRCID_Pos)              /*!< 0x00000070 */
33622 #define RISAF_REGx_zCFGR_SRCID             RISAF_REGx_zCFGR_SRCID_Msk                        /*!< Subregion CID */
33623 #define RISAF_REGx_zCFGR_SRCID_0           (0x1UL << RISAF_REGx_zCFGR_SRCID_Pos)              /*!< 0x00000010 */
33624 #define RISAF_REGx_zCFGR_SRCID_1           (0x2UL << RISAF_REGx_zCFGR_SRCID_Pos)              /*!< 0x00000020 */
33625 #define RISAF_REGx_zCFGR_SRCID_2           (0x4UL << RISAF_REGx_zCFGR_SRCID_Pos)              /*!< 0x00000040 */
33626 #define RISAF_REGx_zCFGR_SEC_Pos           (8U)
33627 #define RISAF_REGx_zCFGR_SEC_Msk           (0x1UL << RISAF_REGx_zCFGR_SEC_Pos)                /*!< 0x00000100 */
33628 #define RISAF_REGx_zCFGR_SEC               RISAF_REGx_zCFGR_SEC_Msk                          /*!< Secure subregion */
33629 #define RISAF_REGx_zCFGR_PRIV_Pos          (9U)
33630 #define RISAF_REGx_zCFGR_PRIV_Msk          (0x1UL << RISAF_REGx_zCFGR_PRIV_Pos)               /*!< 0x00000200 */
33631 #define RISAF_REGx_zCFGR_PRIV              RISAF_REGx_zCFGR_PRIV_Msk                         /*!< Privileged subregion */
33632 #define RISAF_REGx_zCFGR_RDEN_Pos          (12U)
33633 #define RISAF_REGx_zCFGR_RDEN_Msk          (0x1UL << RISAF_REGx_zCFGR_RDEN_Pos)               /*!< 0x00001000 */
33634 #define RISAF_REGx_zCFGR_RDEN              RISAF_REGx_zCFGR_RDEN_Msk                         /*!< Read enable */
33635 #define RISAF_REGx_zCFGR_WREN_Pos          (13U)
33636 #define RISAF_REGx_zCFGR_WREN_Msk          (0x1UL << RISAF_REGx_zCFGR_WREN_Pos)               /*!< 0x00002000 */
33637 #define RISAF_REGx_zCFGR_WREN              RISAF_REGx_zCFGR_WREN_Msk                         /*!< Write enable */
33638 
33639 /**************  Bit definition for RISAF_REGx_zSTARTR register  **************/
33640 #define RISAF_REGx_zSTARTR_SADDSTART_Pos   (0U)
33641 #define RISAF_REGx_zSTARTR_SADDSTART_Msk   (0xFFFFFFFFUL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0xFFFFFFFF */
33642 #define RISAF_REGx_zSTARTR_SADDSTART       RISAF_REGx_zSTARTR_SADDSTART_Msk                  /*!< Subregion address start */
33643 #define RISAF_REGx_zSTARTR_SADDSTART_0     (0x1UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)        /*!< 0x00000001 */
33644 #define RISAF_REGx_zSTARTR_SADDSTART_1     (0x2UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)        /*!< 0x00000002 */
33645 #define RISAF_REGx_zSTARTR_SADDSTART_2     (0x4UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)        /*!< 0x00000004 */
33646 #define RISAF_REGx_zSTARTR_SADDSTART_3     (0x8UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)        /*!< 0x00000008 */
33647 #define RISAF_REGx_zSTARTR_SADDSTART_4     (0x10UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)       /*!< 0x00000010 */
33648 #define RISAF_REGx_zSTARTR_SADDSTART_5     (0x20UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)       /*!< 0x00000020 */
33649 #define RISAF_REGx_zSTARTR_SADDSTART_6     (0x40UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)       /*!< 0x00000040 */
33650 #define RISAF_REGx_zSTARTR_SADDSTART_7     (0x80UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)       /*!< 0x00000080 */
33651 #define RISAF_REGx_zSTARTR_SADDSTART_8     (0x100UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)      /*!< 0x00000100 */
33652 #define RISAF_REGx_zSTARTR_SADDSTART_9     (0x200UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)      /*!< 0x00000200 */
33653 #define RISAF_REGx_zSTARTR_SADDSTART_10    (0x400UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)      /*!< 0x00000400 */
33654 #define RISAF_REGx_zSTARTR_SADDSTART_11    (0x800UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)      /*!< 0x00000800 */
33655 #define RISAF_REGx_zSTARTR_SADDSTART_12    (0x1000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)     /*!< 0x00001000 */
33656 #define RISAF_REGx_zSTARTR_SADDSTART_13    (0x2000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)     /*!< 0x00002000 */
33657 #define RISAF_REGx_zSTARTR_SADDSTART_14    (0x4000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)     /*!< 0x00004000 */
33658 #define RISAF_REGx_zSTARTR_SADDSTART_15    (0x8000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)     /*!< 0x00008000 */
33659 #define RISAF_REGx_zSTARTR_SADDSTART_16    (0x10000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)    /*!< 0x00010000 */
33660 #define RISAF_REGx_zSTARTR_SADDSTART_17    (0x20000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)    /*!< 0x00020000 */
33661 #define RISAF_REGx_zSTARTR_SADDSTART_18    (0x40000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)    /*!< 0x00040000 */
33662 #define RISAF_REGx_zSTARTR_SADDSTART_19    (0x80000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)    /*!< 0x00080000 */
33663 #define RISAF_REGx_zSTARTR_SADDSTART_20    (0x100000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)   /*!< 0x00100000 */
33664 #define RISAF_REGx_zSTARTR_SADDSTART_21    (0x200000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)   /*!< 0x00200000 */
33665 #define RISAF_REGx_zSTARTR_SADDSTART_22    (0x400000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)   /*!< 0x00400000 */
33666 #define RISAF_REGx_zSTARTR_SADDSTART_23    (0x800000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)   /*!< 0x00800000 */
33667 #define RISAF_REGx_zSTARTR_SADDSTART_24    (0x1000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)  /*!< 0x01000000 */
33668 #define RISAF_REGx_zSTARTR_SADDSTART_25    (0x2000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)  /*!< 0x02000000 */
33669 #define RISAF_REGx_zSTARTR_SADDSTART_26    (0x4000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)  /*!< 0x04000000 */
33670 #define RISAF_REGx_zSTARTR_SADDSTART_27    (0x8000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)  /*!< 0x08000000 */
33671 #define RISAF_REGx_zSTARTR_SADDSTART_28    (0x10000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x10000000 */
33672 #define RISAF_REGx_zSTARTR_SADDSTART_29    (0x20000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x20000000 */
33673 #define RISAF_REGx_zSTARTR_SADDSTART_30    (0x40000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x40000000 */
33674 #define RISAF_REGx_zSTARTR_SADDSTART_31    (0x80000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x80000000 */
33675 
33676 /***************  Bit definition for RISAF_REGx_zENDR register  ***************/
33677 #define RISAF_REGx_zENDR_SADDEND_Pos       (0U)
33678 #define RISAF_REGx_zENDR_SADDEND_Msk       (0xFFFFFFFFUL << RISAF_REGx_zENDR_SADDEND_Pos)     /*!< 0xFFFFFFFF */
33679 #define RISAF_REGx_zENDR_SADDEND           RISAF_REGx_zENDR_SADDEND_Msk                      /*!< Subregion address end */
33680 #define RISAF_REGx_zENDR_SADDEND_0         (0x1UL << RISAF_REGx_zENDR_SADDEND_Pos)            /*!< 0x00000001 */
33681 #define RISAF_REGx_zENDR_SADDEND_1         (0x2UL << RISAF_REGx_zENDR_SADDEND_Pos)            /*!< 0x00000002 */
33682 #define RISAF_REGx_zENDR_SADDEND_2         (0x4UL << RISAF_REGx_zENDR_SADDEND_Pos)            /*!< 0x00000004 */
33683 #define RISAF_REGx_zENDR_SADDEND_3         (0x8UL << RISAF_REGx_zENDR_SADDEND_Pos)            /*!< 0x00000008 */
33684 #define RISAF_REGx_zENDR_SADDEND_4         (0x10UL << RISAF_REGx_zENDR_SADDEND_Pos)           /*!< 0x00000010 */
33685 #define RISAF_REGx_zENDR_SADDEND_5         (0x20UL << RISAF_REGx_zENDR_SADDEND_Pos)           /*!< 0x00000020 */
33686 #define RISAF_REGx_zENDR_SADDEND_6         (0x40UL << RISAF_REGx_zENDR_SADDEND_Pos)           /*!< 0x00000040 */
33687 #define RISAF_REGx_zENDR_SADDEND_7         (0x80UL << RISAF_REGx_zENDR_SADDEND_Pos)           /*!< 0x00000080 */
33688 #define RISAF_REGx_zENDR_SADDEND_8         (0x100UL << RISAF_REGx_zENDR_SADDEND_Pos)          /*!< 0x00000100 */
33689 #define RISAF_REGx_zENDR_SADDEND_9         (0x200UL << RISAF_REGx_zENDR_SADDEND_Pos)          /*!< 0x00000200 */
33690 #define RISAF_REGx_zENDR_SADDEND_10        (0x400UL << RISAF_REGx_zENDR_SADDEND_Pos)          /*!< 0x00000400 */
33691 #define RISAF_REGx_zENDR_SADDEND_11        (0x800UL << RISAF_REGx_zENDR_SADDEND_Pos)          /*!< 0x00000800 */
33692 #define RISAF_REGx_zENDR_SADDEND_12        (0x1000UL << RISAF_REGx_zENDR_SADDEND_Pos)         /*!< 0x00001000 */
33693 #define RISAF_REGx_zENDR_SADDEND_13        (0x2000UL << RISAF_REGx_zENDR_SADDEND_Pos)         /*!< 0x00002000 */
33694 #define RISAF_REGx_zENDR_SADDEND_14        (0x4000UL << RISAF_REGx_zENDR_SADDEND_Pos)         /*!< 0x00004000 */
33695 #define RISAF_REGx_zENDR_SADDEND_15        (0x8000UL << RISAF_REGx_zENDR_SADDEND_Pos)         /*!< 0x00008000 */
33696 #define RISAF_REGx_zENDR_SADDEND_16        (0x10000UL << RISAF_REGx_zENDR_SADDEND_Pos)        /*!< 0x00010000 */
33697 #define RISAF_REGx_zENDR_SADDEND_17        (0x20000UL << RISAF_REGx_zENDR_SADDEND_Pos)        /*!< 0x00020000 */
33698 #define RISAF_REGx_zENDR_SADDEND_18        (0x40000UL << RISAF_REGx_zENDR_SADDEND_Pos)        /*!< 0x00040000 */
33699 #define RISAF_REGx_zENDR_SADDEND_19        (0x80000UL << RISAF_REGx_zENDR_SADDEND_Pos)        /*!< 0x00080000 */
33700 #define RISAF_REGx_zENDR_SADDEND_20        (0x100000UL << RISAF_REGx_zENDR_SADDEND_Pos)       /*!< 0x00100000 */
33701 #define RISAF_REGx_zENDR_SADDEND_21        (0x200000UL << RISAF_REGx_zENDR_SADDEND_Pos)       /*!< 0x00200000 */
33702 #define RISAF_REGx_zENDR_SADDEND_22        (0x400000UL << RISAF_REGx_zENDR_SADDEND_Pos)       /*!< 0x00400000 */
33703 #define RISAF_REGx_zENDR_SADDEND_23        (0x800000UL << RISAF_REGx_zENDR_SADDEND_Pos)       /*!< 0x00800000 */
33704 #define RISAF_REGx_zENDR_SADDEND_24        (0x1000000UL << RISAF_REGx_zENDR_SADDEND_Pos)      /*!< 0x01000000 */
33705 #define RISAF_REGx_zENDR_SADDEND_25        (0x2000000UL << RISAF_REGx_zENDR_SADDEND_Pos)      /*!< 0x02000000 */
33706 #define RISAF_REGx_zENDR_SADDEND_26        (0x4000000UL << RISAF_REGx_zENDR_SADDEND_Pos)      /*!< 0x04000000 */
33707 #define RISAF_REGx_zENDR_SADDEND_27        (0x8000000UL << RISAF_REGx_zENDR_SADDEND_Pos)      /*!< 0x08000000 */
33708 #define RISAF_REGx_zENDR_SADDEND_28        (0x10000000UL << RISAF_REGx_zENDR_SADDEND_Pos)     /*!< 0x10000000 */
33709 #define RISAF_REGx_zENDR_SADDEND_29        (0x20000000UL << RISAF_REGx_zENDR_SADDEND_Pos)     /*!< 0x20000000 */
33710 #define RISAF_REGx_zENDR_SADDEND_30        (0x40000000UL << RISAF_REGx_zENDR_SADDEND_Pos)     /*!< 0x40000000 */
33711 #define RISAF_REGx_zENDR_SADDEND_31        (0x80000000UL << RISAF_REGx_zENDR_SADDEND_Pos)     /*!< 0x80000000 */
33712 
33713 /**************  Bit definition for RISAF_REGx_zNESTR register  ***************/
33714 #define RISAF_REGx_zNESTR_DCEN_Pos         (2U)
33715 #define RISAF_REGx_zNESTR_DCEN_Msk         (0x1UL << RISAF_REGx_zNESTR_DCEN_Pos)              /*!< 0x00000004 */
33716 #define RISAF_REGx_zNESTR_DCEN             RISAF_REGx_zNESTR_DCEN_Msk                        /*!< Delegated configuration enable */
33717 #define RISAF_REGx_zNESTR_DCCID_Pos        (4U)
33718 #define RISAF_REGx_zNESTR_DCCID_Msk        (0x7UL << RISAF_REGx_zNESTR_DCCID_Pos)             /*!< 0x00000070 */
33719 #define RISAF_REGx_zNESTR_DCCID            RISAF_REGx_zNESTR_DCCID_Msk                       /*!< Delegated configuration CID */
33720 #define RISAF_REGx_zNESTR_DCCID_0          (0x1UL << RISAF_REGx_zNESTR_DCCID_Pos)             /*!< 0x00000010 */
33721 #define RISAF_REGx_zNESTR_DCCID_1          (0x2UL << RISAF_REGx_zNESTR_DCCID_Pos)             /*!< 0x00000020 */
33722 #define RISAF_REGx_zNESTR_DCCID_2          (0x4UL << RISAF_REGx_zNESTR_DCCID_Pos)             /*!< 0x00000040 */
33723 
33724 /******************************************************************************/
33725 /*                                                                            */
33726 /*                                    (IAC)                                   */
33727 /*                                                                            */
33728 /******************************************************************************/
33729 /*******************  Bit definition for IAC_IER0 register  *******************/
33730 #define IAC_IERx_IAIE0_Pos         (0U)
33731 #define IAC_IERx_IAIE0_Msk         (0x1UL << IAC_IERx_IAIE0_Pos)        /*!< 0x00000001 */
33732 #define IAC_IERx_IAIE0             IAC_IERx_IAIE0_Msk                  /*!< illegal access interrupt enable for peripheral 0 (i = 0 to 31) */
33733 #define IAC_IERx_IAIE1_Pos         (1U)
33734 #define IAC_IERx_IAIE1_Msk         (0x1UL << IAC_IERx_IAIE1_Pos)        /*!< 0x00000002 */
33735 #define IAC_IERx_IAIE1             IAC_IERx_IAIE1_Msk                  /*!< illegal access interrupt enable for peripheral 1 (i = 0 to 31) */
33736 #define IAC_IERx_IAIE2_Pos         (2U)
33737 #define IAC_IERx_IAIE2_Msk         (0x1UL << IAC_IERx_IAIE2_Pos)        /*!< 0x00000004 */
33738 #define IAC_IERx_IAIE2             IAC_IERx_IAIE2_Msk                  /*!< illegal access interrupt enable for peripheral 2 (i = 0 to 31) */
33739 #define IAC_IERx_IAIE3_Pos         (3U)
33740 #define IAC_IERx_IAIE3_Msk         (0x1UL << IAC_IERx_IAIE3_Pos)        /*!< 0x00000008 */
33741 #define IAC_IERx_IAIE3             IAC_IERx_IAIE3_Msk                  /*!< illegal access interrupt enable for peripheral 3 (i = 0 to 31) */
33742 #define IAC_IERx_IAIE4_Pos         (4U)
33743 #define IAC_IERx_IAIE4_Msk         (0x1UL << IAC_IERx_IAIE4_Pos)        /*!< 0x00000010 */
33744 #define IAC_IERx_IAIE4             IAC_IERx_IAIE4_Msk                  /*!< illegal access interrupt enable for peripheral 4 (i = 0 to 31) */
33745 #define IAC_IERx_IAIE5_Pos         (5U)
33746 #define IAC_IERx_IAIE5_Msk         (0x1UL << IAC_IERx_IAIE5_Pos)        /*!< 0x00000020 */
33747 #define IAC_IERx_IAIE5             IAC_IERx_IAIE5_Msk                  /*!< illegal access interrupt enable for peripheral 5 (i = 0 to 31) */
33748 #define IAC_IERx_IAIE6_Pos         (6U)
33749 #define IAC_IERx_IAIE6_Msk         (0x1UL << IAC_IERx_IAIE6_Pos)        /*!< 0x00000040 */
33750 #define IAC_IERx_IAIE6             IAC_IERx_IAIE6_Msk                  /*!< illegal access interrupt enable for peripheral 6 (i = 0 to 31) */
33751 #define IAC_IERx_IAIE7_Pos         (7U)
33752 #define IAC_IERx_IAIE7_Msk         (0x1UL << IAC_IERx_IAIE7_Pos)        /*!< 0x00000080 */
33753 #define IAC_IERx_IAIE7             IAC_IERx_IAIE7_Msk                  /*!< illegal access interrupt enable for peripheral 7 (i = 0 to 31) */
33754 #define IAC_IERx_IAIE8_Pos         (8U)
33755 #define IAC_IERx_IAIE8_Msk         (0x1UL << IAC_IERx_IAIE8_Pos)        /*!< 0x00000100 */
33756 #define IAC_IERx_IAIE8             IAC_IERx_IAIE8_Msk                  /*!< illegal access interrupt enable for peripheral 8 (i = 0 to 31) */
33757 #define IAC_IERx_IAIE9_Pos         (9U)
33758 #define IAC_IERx_IAIE9_Msk         (0x1UL << IAC_IERx_IAIE9_Pos)        /*!< 0x00000200 */
33759 #define IAC_IERx_IAIE9             IAC_IERx_IAIE9_Msk                  /*!< illegal access interrupt enable for peripheral 9 (i = 0 to 31) */
33760 #define IAC_IERx_IAIE10_Pos        (10U)
33761 #define IAC_IERx_IAIE10_Msk        (0x1UL << IAC_IERx_IAIE10_Pos)       /*!< 0x00000400 */
33762 #define IAC_IERx_IAIE10            IAC_IERx_IAIE10_Msk                 /*!< illegal access interrupt enable for peripheral 10 (i = 0 to 31) */
33763 #define IAC_IERx_IAIE11_Pos        (11U)
33764 #define IAC_IERx_IAIE11_Msk        (0x1UL << IAC_IERx_IAIE11_Pos)       /*!< 0x00000800 */
33765 #define IAC_IERx_IAIE11            IAC_IERx_IAIE11_Msk                 /*!< illegal access interrupt enable for peripheral 11 (i = 0 to 31) */
33766 #define IAC_IERx_IAIE12_Pos        (12U)
33767 #define IAC_IERx_IAIE12_Msk        (0x1UL << IAC_IERx_IAIE12_Pos)       /*!< 0x00001000 */
33768 #define IAC_IERx_IAIE12            IAC_IERx_IAIE12_Msk                 /*!< illegal access interrupt enable for peripheral 12 (i = 0 to 31) */
33769 #define IAC_IERx_IAIE13_Pos        (13U)
33770 #define IAC_IERx_IAIE13_Msk        (0x1UL << IAC_IERx_IAIE13_Pos)       /*!< 0x00002000 */
33771 #define IAC_IERx_IAIE13            IAC_IERx_IAIE13_Msk                 /*!< illegal access interrupt enable for peripheral 13 (i = 0 to 31) */
33772 #define IAC_IERx_IAIE14_Pos        (14U)
33773 #define IAC_IERx_IAIE14_Msk        (0x1UL << IAC_IERx_IAIE14_Pos)       /*!< 0x00004000 */
33774 #define IAC_IERx_IAIE14            IAC_IERx_IAIE14_Msk                 /*!< illegal access interrupt enable for peripheral 14 (i = 0 to 31) */
33775 #define IAC_IERx_IAIE15_Pos        (15U)
33776 #define IAC_IERx_IAIE15_Msk        (0x1UL << IAC_IERx_IAIE15_Pos)       /*!< 0x00008000 */
33777 #define IAC_IERx_IAIE15            IAC_IERx_IAIE15_Msk                 /*!< illegal access interrupt enable for peripheral 15 (i = 0 to 31) */
33778 #define IAC_IERx_IAIE16_Pos        (16U)
33779 #define IAC_IERx_IAIE16_Msk        (0x1UL << IAC_IERx_IAIE16_Pos)       /*!< 0x00010000 */
33780 #define IAC_IERx_IAIE16            IAC_IERx_IAIE16_Msk                 /*!< illegal access interrupt enable for peripheral 16 (i = 0 to 31) */
33781 #define IAC_IERx_IAIE17_Pos        (17U)
33782 #define IAC_IERx_IAIE17_Msk        (0x1UL << IAC_IERx_IAIE17_Pos)       /*!< 0x00020000 */
33783 #define IAC_IERx_IAIE17            IAC_IERx_IAIE17_Msk                 /*!< illegal access interrupt enable for peripheral 17 (i = 0 to 31) */
33784 #define IAC_IERx_IAIE18_Pos        (18U)
33785 #define IAC_IERx_IAIE18_Msk        (0x1UL << IAC_IERx_IAIE18_Pos)       /*!< 0x00040000 */
33786 #define IAC_IERx_IAIE18            IAC_IERx_IAIE18_Msk                 /*!< illegal access interrupt enable for peripheral 18 (i = 0 to 31) */
33787 #define IAC_IERx_IAIE19_Pos        (19U)
33788 #define IAC_IERx_IAIE19_Msk        (0x1UL << IAC_IERx_IAIE19_Pos)       /*!< 0x00080000 */
33789 #define IAC_IERx_IAIE19            IAC_IERx_IAIE19_Msk                 /*!< illegal access interrupt enable for peripheral 19 (i = 0 to 31) */
33790 #define IAC_IERx_IAIE20_Pos        (20U)
33791 #define IAC_IERx_IAIE20_Msk        (0x1UL << IAC_IERx_IAIE20_Pos)       /*!< 0x00100000 */
33792 #define IAC_IERx_IAIE20            IAC_IERx_IAIE20_Msk                 /*!< illegal access interrupt enable for peripheral 20 (i = 0 to 31) */
33793 #define IAC_IERx_IAIE21_Pos        (21U)
33794 #define IAC_IERx_IAIE21_Msk        (0x1UL << IAC_IERx_IAIE21_Pos)       /*!< 0x00200000 */
33795 #define IAC_IERx_IAIE21            IAC_IERx_IAIE21_Msk                 /*!< illegal access interrupt enable for peripheral 21 (i = 0 to 31) */
33796 #define IAC_IERx_IAIE22_Pos        (22U)
33797 #define IAC_IERx_IAIE22_Msk        (0x1UL << IAC_IERx_IAIE22_Pos)       /*!< 0x00400000 */
33798 #define IAC_IERx_IAIE22            IAC_IERx_IAIE22_Msk                 /*!< illegal access interrupt enable for peripheral 22 (i = 0 to 31) */
33799 #define IAC_IERx_IAIE23_Pos        (23U)
33800 #define IAC_IERx_IAIE23_Msk        (0x1UL << IAC_IERx_IAIE23_Pos)       /*!< 0x00800000 */
33801 #define IAC_IERx_IAIE23            IAC_IERx_IAIE23_Msk                 /*!< illegal access interrupt enable for peripheral 23 (i = 0 to 31) */
33802 #define IAC_IERx_IAIE24_Pos        (24U)
33803 #define IAC_IERx_IAIE24_Msk        (0x1UL << IAC_IERx_IAIE24_Pos)       /*!< 0x01000000 */
33804 #define IAC_IERx_IAIE24            IAC_IERx_IAIE24_Msk                 /*!< illegal access interrupt enable for peripheral 24 (i = 0 to 31) */
33805 #define IAC_IERx_IAIE25_Pos        (25U)
33806 #define IAC_IERx_IAIE25_Msk        (0x1UL << IAC_IERx_IAIE25_Pos)       /*!< 0x02000000 */
33807 #define IAC_IERx_IAIE25            IAC_IERx_IAIE25_Msk                 /*!< illegal access interrupt enable for peripheral 25 (i = 0 to 31) */
33808 #define IAC_IERx_IAIE26_Pos        (26U)
33809 #define IAC_IERx_IAIE26_Msk        (0x1UL << IAC_IERx_IAIE26_Pos)       /*!< 0x04000000 */
33810 #define IAC_IERx_IAIE26            IAC_IERx_IAIE26_Msk                 /*!< illegal access interrupt enable for peripheral 26 (i = 0 to 31) */
33811 #define IAC_IERx_IAIE27_Pos        (27U)
33812 #define IAC_IERx_IAIE27_Msk        (0x1UL << IAC_IERx_IAIE27_Pos)       /*!< 0x08000000 */
33813 #define IAC_IERx_IAIE27            IAC_IERx_IAIE27_Msk                 /*!< illegal access interrupt enable for peripheral 27 (i = 0 to 31) */
33814 #define IAC_IERx_IAIE28_Pos        (28U)
33815 #define IAC_IERx_IAIE28_Msk        (0x1UL << IAC_IERx_IAIE28_Pos)       /*!< 0x10000000 */
33816 #define IAC_IERx_IAIE28            IAC_IERx_IAIE28_Msk                 /*!< illegal access interrupt enable for peripheral 28 (i = 0 to 31) */
33817 #define IAC_IERx_IAIE29_Pos        (29U)
33818 #define IAC_IERx_IAIE29_Msk        (0x1UL << IAC_IERx_IAIE29_Pos)       /*!< 0x20000000 */
33819 #define IAC_IERx_IAIE29            IAC_IERx_IAIE29_Msk                 /*!< illegal access interrupt enable for peripheral 29 (i = 0 to 31) */
33820 #define IAC_IERx_IAIE30_Pos        (30U)
33821 #define IAC_IERx_IAIE30_Msk        (0x1UL << IAC_IERx_IAIE30_Pos)       /*!< 0x40000000 */
33822 #define IAC_IERx_IAIE30            IAC_IERx_IAIE30_Msk                 /*!< illegal access interrupt enable for peripheral 30 (i = 0 to 31) */
33823 #define IAC_IERx_IAIE31_Pos        (31U)
33824 #define IAC_IERx_IAIE31_Msk        (0x1UL << IAC_IERx_IAIE31_Pos)       /*!< 0x80000000 */
33825 #define IAC_IERx_IAIE31            IAC_IERx_IAIE31_Msk                 /*!< illegal access interrupt enable for peripheral 31 (i = 0 to 31) */
33826 
33827 /*******************  Bit definition for IAC_ISRx register  *******************/
33828 #define IAC_ISRx_IAF0_Pos          (0U)
33829 #define IAC_ISRx_IAF0_Msk          (0x1UL << IAC_ISRx_IAF0_Pos)         /*!< 0x00000001 */
33830 #define IAC_ISRx_IAF0              IAC_ISRx_IAF0_Msk                   /*!< illegal access interrupt enable for peripheral 0 (i = 0 to 31) */
33831 #define IAC_ISRx_IAF1_Pos          (1U)
33832 #define IAC_ISRx_IAF1_Msk          (0x1UL << IAC_ISRx_IAF1_Pos)         /*!< 0x00000002 */
33833 #define IAC_ISRx_IAF1              IAC_ISRx_IAF1_Msk                   /*!< illegal access interrupt enable for peripheral 1 (i = 0 to 31) */
33834 #define IAC_ISRx_IAF2_Pos          (2U)
33835 #define IAC_ISRx_IAF2_Msk          (0x1UL << IAC_ISRx_IAF2_Pos)         /*!< 0x00000004 */
33836 #define IAC_ISRx_IAF2              IAC_ISRx_IAF2_Msk                   /*!< illegal access interrupt enable for peripheral 2 (i = 0 to 31) */
33837 #define IAC_ISRx_IAF3_Pos          (3U)
33838 #define IAC_ISRx_IAF3_Msk          (0x1UL << IAC_ISRx_IAF3_Pos)         /*!< 0x00000008 */
33839 #define IAC_ISRx_IAF3              IAC_ISRx_IAF3_Msk                   /*!< illegal access interrupt enable for peripheral 3 (i = 0 to 31) */
33840 #define IAC_ISRx_IAF4_Pos          (4U)
33841 #define IAC_ISRx_IAF4_Msk          (0x1UL << IAC_ISRx_IAF4_Pos)         /*!< 0x00000010 */
33842 #define IAC_ISRx_IAF4              IAC_ISRx_IAF4_Msk                   /*!< illegal access interrupt enable for peripheral 4 (i = 0 to 31) */
33843 #define IAC_ISRx_IAF5_Pos          (5U)
33844 #define IAC_ISRx_IAF5_Msk          (0x1UL << IAC_ISRx_IAF5_Pos)         /*!< 0x00000020 */
33845 #define IAC_ISRx_IAF5              IAC_ISRx_IAF5_Msk                   /*!< illegal access interrupt enable for peripheral 5 (i = 0 to 31) */
33846 #define IAC_ISRx_IAF6_Pos          (6U)
33847 #define IAC_ISRx_IAF6_Msk          (0x1UL << IAC_ISRx_IAF6_Pos)         /*!< 0x00000040 */
33848 #define IAC_ISRx_IAF6              IAC_ISRx_IAF6_Msk                   /*!< illegal access interrupt enable for peripheral 6 (i = 0 to 31) */
33849 #define IAC_ISRx_IAF7_Pos          (7U)
33850 #define IAC_ISRx_IAF7_Msk          (0x1UL << IAC_ISRx_IAF7_Pos)         /*!< 0x00000080 */
33851 #define IAC_ISRx_IAF7              IAC_ISRx_IAF7_Msk                   /*!< illegal access interrupt enable for peripheral 7 (i = 0 to 31) */
33852 #define IAC_ISRx_IAF8_Pos          (8U)
33853 #define IAC_ISRx_IAF8_Msk          (0x1UL << IAC_ISRx_IAF8_Pos)         /*!< 0x00000100 */
33854 #define IAC_ISRx_IAF8              IAC_ISRx_IAF8_Msk                   /*!< illegal access interrupt enable for peripheral 8 (i = 0 to 31) */
33855 #define IAC_ISRx_IAF9_Pos          (9U)
33856 #define IAC_ISRx_IAF9_Msk          (0x1UL << IAC_ISRx_IAF9_Pos)         /*!< 0x00000200 */
33857 #define IAC_ISRx_IAF9              IAC_ISRx_IAF9_Msk                   /*!< illegal access interrupt enable for peripheral 9 (i = 0 to 31) */
33858 #define IAC_ISRx_IAF10_Pos         (10U)
33859 #define IAC_ISRx_IAF10_Msk         (0x1UL << IAC_ISRx_IAF10_Pos)        /*!< 0x00000400 */
33860 #define IAC_ISRx_IAF10             IAC_ISRx_IAF10_Msk                  /*!< illegal access interrupt enable for peripheral 10 (i = 0 to 31) */
33861 #define IAC_ISRx_IAF11_Pos         (11U)
33862 #define IAC_ISRx_IAF11_Msk         (0x1UL << IAC_ISRx_IAF11_Pos)        /*!< 0x00000800 */
33863 #define IAC_ISRx_IAF11             IAC_ISRx_IAF11_Msk                  /*!< illegal access interrupt enable for peripheral 11 (i = 0 to 31) */
33864 #define IAC_ISRx_IAF12_Pos         (12U)
33865 #define IAC_ISRx_IAF12_Msk         (0x1UL << IAC_ISRx_IAF12_Pos)        /*!< 0x00001000 */
33866 #define IAC_ISRx_IAF12             IAC_ISRx_IAF12_Msk                  /*!< illegal access interrupt enable for peripheral 12 (i = 0 to 31) */
33867 #define IAC_ISRx_IAF13_Pos         (13U)
33868 #define IAC_ISRx_IAF13_Msk         (0x1UL << IAC_ISRx_IAF13_Pos)        /*!< 0x00002000 */
33869 #define IAC_ISRx_IAF13             IAC_ISRx_IAF13_Msk                  /*!< illegal access interrupt enable for peripheral 13 (i = 0 to 31) */
33870 #define IAC_ISRx_IAF14_Pos         (14U)
33871 #define IAC_ISRx_IAF14_Msk         (0x1UL << IAC_ISRx_IAF14_Pos)        /*!< 0x00004000 */
33872 #define IAC_ISRx_IAF14             IAC_ISRx_IAF14_Msk                  /*!< illegal access interrupt enable for peripheral 14 (i = 0 to 31) */
33873 #define IAC_ISRx_IAF15_Pos         (15U)
33874 #define IAC_ISRx_IAF15_Msk         (0x1UL << IAC_ISRx_IAF15_Pos)        /*!< 0x00008000 */
33875 #define IAC_ISRx_IAF15             IAC_ISRx_IAF15_Msk                  /*!< illegal access interrupt enable for peripheral 15 (i = 0 to 31) */
33876 #define IAC_ISRx_IAF16_Pos         (16U)
33877 #define IAC_ISRx_IAF16_Msk         (0x1UL << IAC_ISRx_IAF16_Pos)        /*!< 0x00010000 */
33878 #define IAC_ISRx_IAF16             IAC_ISRx_IAF16_Msk                  /*!< illegal access interrupt enable for peripheral 16 (i = 0 to 31) */
33879 #define IAC_ISRx_IAF17_Pos         (17U)
33880 #define IAC_ISRx_IAF17_Msk         (0x1UL << IAC_ISRx_IAF17_Pos)        /*!< 0x00020000 */
33881 #define IAC_ISRx_IAF17             IAC_ISRx_IAF17_Msk                  /*!< illegal access interrupt enable for peripheral 17 (i = 0 to 31) */
33882 #define IAC_ISRx_IAF18_Pos         (18U)
33883 #define IAC_ISRx_IAF18_Msk         (0x1UL << IAC_ISRx_IAF18_Pos)        /*!< 0x00040000 */
33884 #define IAC_ISRx_IAF18             IAC_ISRx_IAF18_Msk                  /*!< illegal access interrupt enable for peripheral 18 (i = 0 to 31) */
33885 #define IAC_ISRx_IAF19_Pos         (19U)
33886 #define IAC_ISRx_IAF19_Msk         (0x1UL << IAC_ISRx_IAF19_Pos)        /*!< 0x00080000 */
33887 #define IAC_ISRx_IAF19             IAC_ISRx_IAF19_Msk                  /*!< illegal access interrupt enable for peripheral 19 (i = 0 to 31) */
33888 #define IAC_ISRx_IAF20_Pos         (20U)
33889 #define IAC_ISRx_IAF20_Msk         (0x1UL << IAC_ISRx_IAF20_Pos)        /*!< 0x00100000 */
33890 #define IAC_ISRx_IAF20             IAC_ISRx_IAF20_Msk                  /*!< illegal access interrupt enable for peripheral 20 (i = 0 to 31) */
33891 #define IAC_ISRx_IAF21_Pos         (21U)
33892 #define IAC_ISRx_IAF21_Msk         (0x1UL << IAC_ISRx_IAF21_Pos)        /*!< 0x00200000 */
33893 #define IAC_ISRx_IAF21             IAC_ISRx_IAF21_Msk                  /*!< illegal access interrupt enable for peripheral 21 (i = 0 to 31) */
33894 #define IAC_ISRx_IAF22_Pos         (22U)
33895 #define IAC_ISRx_IAF22_Msk         (0x1UL << IAC_ISRx_IAF22_Pos)        /*!< 0x00400000 */
33896 #define IAC_ISRx_IAF22             IAC_ISRx_IAF22_Msk                  /*!< illegal access interrupt enable for peripheral 22 (i = 0 to 31) */
33897 #define IAC_ISRx_IAF23_Pos         (23U)
33898 #define IAC_ISRx_IAF23_Msk         (0x1UL << IAC_ISRx_IAF23_Pos)        /*!< 0x00800000 */
33899 #define IAC_ISRx_IAF23             IAC_ISRx_IAF23_Msk                  /*!< illegal access interrupt enable for peripheral 23 (i = 0 to 31) */
33900 #define IAC_ISRx_IAF24_Pos         (24U)
33901 #define IAC_ISRx_IAF24_Msk         (0x1UL << IAC_ISRx_IAF24_Pos)        /*!< 0x01000000 */
33902 #define IAC_ISRx_IAF24             IAC_ISRx_IAF24_Msk                  /*!< illegal access interrupt enable for peripheral 24 (i = 0 to 31) */
33903 #define IAC_ISRx_IAF25_Pos         (25U)
33904 #define IAC_ISRx_IAF25_Msk         (0x1UL << IAC_ISRx_IAF25_Pos)        /*!< 0x02000000 */
33905 #define IAC_ISRx_IAF25             IAC_ISRx_IAF25_Msk                  /*!< illegal access interrupt enable for peripheral 25 (i = 0 to 31) */
33906 #define IAC_ISRx_IAF26_Pos         (26U)
33907 #define IAC_ISRx_IAF26_Msk         (0x1UL << IAC_ISRx_IAF26_Pos)        /*!< 0x04000000 */
33908 #define IAC_ISRx_IAF26             IAC_ISRx_IAF26_Msk                  /*!< illegal access interrupt enable for peripheral 26 (i = 0 to 31) */
33909 #define IAC_ISRx_IAF27_Pos         (27U)
33910 #define IAC_ISRx_IAF27_Msk         (0x1UL << IAC_ISRx_IAF27_Pos)        /*!< 0x08000000 */
33911 #define IAC_ISRx_IAF27             IAC_ISRx_IAF27_Msk                  /*!< illegal access interrupt enable for peripheral 27 (i = 0 to 31) */
33912 #define IAC_ISRx_IAF28_Pos         (28U)
33913 #define IAC_ISRx_IAF28_Msk         (0x1UL << IAC_ISRx_IAF28_Pos)        /*!< 0x10000000 */
33914 #define IAC_ISRx_IAF28             IAC_ISRx_IAF28_Msk                  /*!< illegal access interrupt enable for peripheral 28 (i = 0 to 31) */
33915 #define IAC_ISRx_IAF29_Pos         (29U)
33916 #define IAC_ISRx_IAF29_Msk         (0x1UL << IAC_ISRx_IAF29_Pos)        /*!< 0x20000000 */
33917 #define IAC_ISRx_IAF29             IAC_ISRx_IAF29_Msk                  /*!< illegal access interrupt enable for peripheral 29 (i = 0 to 31) */
33918 #define IAC_ISRx_IAF30_Pos         (30U)
33919 #define IAC_ISRx_IAF30_Msk         (0x1UL << IAC_ISRx_IAF30_Pos)        /*!< 0x40000000 */
33920 #define IAC_ISRx_IAF30             IAC_ISRx_IAF30_Msk                  /*!< illegal access interrupt enable for peripheral 30 (i = 0 to 31) */
33921 #define IAC_ISRx_IAF31_Pos         (31U)
33922 #define IAC_ISRx_IAF31_Msk         (0x1UL << IAC_ISRx_IAF31_Pos)        /*!< 0x80000000 */
33923 #define IAC_ISRx_IAF31             IAC_ISRx_IAF31_Msk                  /*!< illegal access interrupt enable for peripheral 31 (i = 0 to 31) */
33924 
33925 /*******************  Bit definition for IAC_ICRx register  *******************/
33926 #define IAC_ICRx_IAF0_Pos          (0U)
33927 #define IAC_ICRx_IAF0_Msk          (0x1UL << IAC_ICRx_IAF0_Pos)         /*!< 0x00000001 */
33928 #define IAC_ICRx_IAF0              IAC_ICRx_IAF0_Msk                   /*!< illegal access flag clear for peripheral 0 (i = 0 to 31) */
33929 #define IAC_ICRx_IAF1_Pos          (1U)
33930 #define IAC_ICRx_IAF1_Msk          (0x1UL << IAC_ICRx_IAF1_Pos)         /*!< 0x00000002 */
33931 #define IAC_ICRx_IAF1              IAC_ICRx_IAF1_Msk                   /*!< illegal access flag clear for peripheral 1 (i = 0 to 31) */
33932 #define IAC_ICRx_IAF2_Pos          (2U)
33933 #define IAC_ICRx_IAF2_Msk          (0x1UL << IAC_ICRx_IAF2_Pos)         /*!< 0x00000004 */
33934 #define IAC_ICRx_IAF2              IAC_ICRx_IAF2_Msk                   /*!< illegal access flag clear for peripheral 2 (i = 0 to 31) */
33935 #define IAC_ICRx_IAF3_Pos          (3U)
33936 #define IAC_ICRx_IAF3_Msk          (0x1UL << IAC_ICRx_IAF3_Pos)         /*!< 0x00000008 */
33937 #define IAC_ICRx_IAF3              IAC_ICRx_IAF3_Msk                   /*!< illegal access flag clear for peripheral 3 (i = 0 to 31) */
33938 #define IAC_ICRx_IAF4_Pos          (4U)
33939 #define IAC_ICRx_IAF4_Msk          (0x1UL << IAC_ICRx_IAF4_Pos)         /*!< 0x00000010 */
33940 #define IAC_ICRx_IAF4              IAC_ICRx_IAF4_Msk                   /*!< illegal access flag clear for peripheral 4 (i = 0 to 31) */
33941 #define IAC_ICRx_IAF5_Pos          (5U)
33942 #define IAC_ICRx_IAF5_Msk          (0x1UL << IAC_ICRx_IAF5_Pos)         /*!< 0x00000020 */
33943 #define IAC_ICRx_IAF5              IAC_ICRx_IAF5_Msk                   /*!< illegal access flag clear for peripheral 5 (i = 0 to 31) */
33944 #define IAC_ICRx_IAF6_Pos          (6U)
33945 #define IAC_ICRx_IAF6_Msk          (0x1UL << IAC_ICRx_IAF6_Pos)         /*!< 0x00000040 */
33946 #define IAC_ICRx_IAF6              IAC_ICRx_IAF6_Msk                   /*!< illegal access flag clear for peripheral 6 (i = 0 to 31) */
33947 #define IAC_ICRx_IAF7_Pos          (7U)
33948 #define IAC_ICRx_IAF7_Msk          (0x1UL << IAC_ICRx_IAF7_Pos)         /*!< 0x00000080 */
33949 #define IAC_ICRx_IAF7              IAC_ICRx_IAF7_Msk                   /*!< illegal access flag clear for peripheral 7 (i = 0 to 31) */
33950 #define IAC_ICRx_IAF8_Pos          (8U)
33951 #define IAC_ICRx_IAF8_Msk          (0x1UL << IAC_ICRx_IAF8_Pos)         /*!< 0x00000100 */
33952 #define IAC_ICRx_IAF8              IAC_ICRx_IAF8_Msk                   /*!< illegal access flag clear for peripheral 8 (i = 0 to 31) */
33953 #define IAC_ICRx_IAF9_Pos          (9U)
33954 #define IAC_ICRx_IAF9_Msk          (0x1UL << IAC_ICRx_IAF9_Pos)         /*!< 0x00000200 */
33955 #define IAC_ICRx_IAF9              IAC_ICRx_IAF9_Msk                   /*!< illegal access flag clear for peripheral 9 (i = 0 to 31) */
33956 #define IAC_ICRx_IAF10_Pos         (10U)
33957 #define IAC_ICRx_IAF10_Msk         (0x1UL << IAC_ICRx_IAF10_Pos)        /*!< 0x00000400 */
33958 #define IAC_ICRx_IAF10             IAC_ICRx_IAF10_Msk                  /*!< illegal access flag clear for peripheral 10 (i = 0 to 31) */
33959 #define IAC_ICRx_IAF11_Pos         (11U)
33960 #define IAC_ICRx_IAF11_Msk         (0x1UL << IAC_ICRx_IAF11_Pos)        /*!< 0x00000800 */
33961 #define IAC_ICRx_IAF11             IAC_ICRx_IAF11_Msk                  /*!< illegal access flag clear for peripheral 11 (i = 0 to 31) */
33962 #define IAC_ICRx_IAF12_Pos         (12U)
33963 #define IAC_ICRx_IAF12_Msk         (0x1UL << IAC_ICRx_IAF12_Pos)        /*!< 0x00001000 */
33964 #define IAC_ICRx_IAF12             IAC_ICRx_IAF12_Msk                  /*!< illegal access flag clear for peripheral 12 (i = 0 to 31) */
33965 #define IAC_ICRx_IAF13_Pos         (13U)
33966 #define IAC_ICRx_IAF13_Msk         (0x1UL << IAC_ICRx_IAF13_Pos)        /*!< 0x00002000 */
33967 #define IAC_ICRx_IAF13             IAC_ICRx_IAF13_Msk                  /*!< illegal access flag clear for peripheral 13 (i = 0 to 31) */
33968 #define IAC_ICRx_IAF14_Pos         (14U)
33969 #define IAC_ICRx_IAF14_Msk         (0x1UL << IAC_ICRx_IAF14_Pos)        /*!< 0x00004000 */
33970 #define IAC_ICRx_IAF14             IAC_ICRx_IAF14_Msk                  /*!< illegal access flag clear for peripheral 14 (i = 0 to 31) */
33971 #define IAC_ICRx_IAF15_Pos         (15U)
33972 #define IAC_ICRx_IAF15_Msk         (0x1UL << IAC_ICRx_IAF15_Pos)        /*!< 0x00008000 */
33973 #define IAC_ICRx_IAF15             IAC_ICRx_IAF15_Msk                  /*!< illegal access flag clear for peripheral 15 (i = 0 to 31) */
33974 #define IAC_ICRx_IAF16_Pos         (16U)
33975 #define IAC_ICRx_IAF16_Msk         (0x1UL << IAC_ICRx_IAF16_Pos)        /*!< 0x00010000 */
33976 #define IAC_ICRx_IAF16             IAC_ICRx_IAF16_Msk                  /*!< illegal access flag clear for peripheral 16 (i = 0 to 31) */
33977 #define IAC_ICRx_IAF17_Pos         (17U)
33978 #define IAC_ICRx_IAF17_Msk         (0x1UL << IAC_ICRx_IAF17_Pos)        /*!< 0x00020000 */
33979 #define IAC_ICRx_IAF17             IAC_ICRx_IAF17_Msk                  /*!< illegal access flag clear for peripheral 17 (i = 0 to 31) */
33980 #define IAC_ICRx_IAF18_Pos         (18U)
33981 #define IAC_ICRx_IAF18_Msk         (0x1UL << IAC_ICRx_IAF18_Pos)        /*!< 0x00040000 */
33982 #define IAC_ICRx_IAF18             IAC_ICRx_IAF18_Msk                  /*!< illegal access flag clear for peripheral 18 (i = 0 to 31) */
33983 #define IAC_ICRx_IAF19_Pos         (19U)
33984 #define IAC_ICRx_IAF19_Msk         (0x1UL << IAC_ICRx_IAF19_Pos)        /*!< 0x00080000 */
33985 #define IAC_ICRx_IAF19             IAC_ICRx_IAF19_Msk                  /*!< illegal access flag clear for peripheral 19 (i = 0 to 31) */
33986 #define IAC_ICRx_IAF20_Pos         (20U)
33987 #define IAC_ICRx_IAF20_Msk         (0x1UL << IAC_ICRx_IAF20_Pos)        /*!< 0x00100000 */
33988 #define IAC_ICRx_IAF20             IAC_ICRx_IAF20_Msk                  /*!< illegal access flag clear for peripheral 20 (i = 0 to 31) */
33989 #define IAC_ICRx_IAF21_Pos         (21U)
33990 #define IAC_ICRx_IAF21_Msk         (0x1UL << IAC_ICRx_IAF21_Pos)        /*!< 0x00200000 */
33991 #define IAC_ICRx_IAF21             IAC_ICRx_IAF21_Msk                  /*!< illegal access flag clear for peripheral 21 (i = 0 to 31) */
33992 #define IAC_ICRx_IAF22_Pos         (22U)
33993 #define IAC_ICRx_IAF22_Msk         (0x1UL << IAC_ICRx_IAF22_Pos)        /*!< 0x00400000 */
33994 #define IAC_ICRx_IAF22             IAC_ICRx_IAF22_Msk                  /*!< illegal access flag clear for peripheral 22 (i = 0 to 31) */
33995 #define IAC_ICRx_IAF23_Pos         (23U)
33996 #define IAC_ICRx_IAF23_Msk         (0x1UL << IAC_ICRx_IAF23_Pos)        /*!< 0x00800000 */
33997 #define IAC_ICRx_IAF23             IAC_ICRx_IAF23_Msk                  /*!< illegal access flag clear for peripheral 23 (i = 0 to 31) */
33998 #define IAC_ICRx_IAF24_Pos         (24U)
33999 #define IAC_ICRx_IAF24_Msk         (0x1UL << IAC_ICRx_IAF24_Pos)        /*!< 0x01000000 */
34000 #define IAC_ICRx_IAF24             IAC_ICRx_IAF24_Msk                  /*!< illegal access flag clear for peripheral 24 (i = 0 to 31) */
34001 #define IAC_ICRx_IAF25_Pos         (25U)
34002 #define IAC_ICRx_IAF25_Msk         (0x1UL << IAC_ICRx_IAF25_Pos)        /*!< 0x02000000 */
34003 #define IAC_ICRx_IAF25             IAC_ICRx_IAF25_Msk                  /*!< illegal access flag clear for peripheral 25 (i = 0 to 31) */
34004 #define IAC_ICRx_IAF26_Pos         (26U)
34005 #define IAC_ICRx_IAF26_Msk         (0x1UL << IAC_ICRx_IAF26_Pos)        /*!< 0x04000000 */
34006 #define IAC_ICRx_IAF26             IAC_ICRx_IAF26_Msk                  /*!< illegal access flag clear for peripheral 26 (i = 0 to 31) */
34007 #define IAC_ICRx_IAF27_Pos         (27U)
34008 #define IAC_ICRx_IAF27_Msk         (0x1UL << IAC_ICRx_IAF27_Pos)        /*!< 0x08000000 */
34009 #define IAC_ICRx_IAF27             IAC_ICRx_IAF27_Msk                  /*!< illegal access flag clear for peripheral 27 (i = 0 to 31) */
34010 #define IAC_ICRx_IAF28_Pos         (28U)
34011 #define IAC_ICRx_IAF28_Msk         (0x1UL << IAC_ICRx_IAF28_Pos)        /*!< 0x10000000 */
34012 #define IAC_ICRx_IAF28             IAC_ICRx_IAF28_Msk                  /*!< illegal access flag clear for peripheral 28 (i = 0 to 31) */
34013 #define IAC_ICRx_IAF29_Pos         (29U)
34014 #define IAC_ICRx_IAF29_Msk         (0x1UL << IAC_ICRx_IAF29_Pos)        /*!< 0x20000000 */
34015 #define IAC_ICRx_IAF29             IAC_ICRx_IAF29_Msk                  /*!< illegal access flag clear for peripheral 29 (i = 0 to 31) */
34016 #define IAC_ICRx_IAF30_Pos         (30U)
34017 #define IAC_ICRx_IAF30_Msk         (0x1UL << IAC_ICRx_IAF30_Pos)        /*!< 0x40000000 */
34018 #define IAC_ICRx_IAF30             IAC_ICRx_IAF30_Msk                  /*!< illegal access flag clear for peripheral 30 (i = 0 to 31) */
34019 #define IAC_ICRx_IAF31_Pos         (31U)
34020 #define IAC_ICRx_IAF31_Msk         (0x1UL << IAC_ICRx_IAF31_Pos)        /*!< 0x80000000 */
34021 #define IAC_ICRx_IAF31             IAC_ICRx_IAF31_Msk                  /*!< illegal access flag clear for peripheral 31 (i = 0 to 31) */
34022 
34023 /******************  Bit definition for IAC_IISRx register  *******************/
34024 #define IAC_IISRx_ILACIN0_Pos      (0U)
34025 #define IAC_IISRx_ILACIN0_Msk      (0x1UL << IAC_IISRx_ILACIN0_Pos)     /*!< 0x00000001 */
34026 #define IAC_IISRx_ILACIN0          IAC_IISRx_ILACIN0_Msk               /*!< illegal access input 0 (i = 0 to 31) */
34027 #define IAC_IISRx_ILACIN1_Pos      (1U)
34028 #define IAC_IISRx_ILACIN1_Msk      (0x1UL << IAC_IISRx_ILACIN1_Pos)     /*!< 0x00000002 */
34029 #define IAC_IISRx_ILACIN1          IAC_IISRx_ILACIN1_Msk               /*!< illegal access input 1 (i = 0 to 31) */
34030 #define IAC_IISRx_ILACIN2_Pos      (2U)
34031 #define IAC_IISRx_ILACIN2_Msk      (0x1UL << IAC_IISRx_ILACIN2_Pos)     /*!< 0x00000004 */
34032 #define IAC_IISRx_ILACIN2          IAC_IISRx_ILACIN2_Msk               /*!< illegal access input 2 (i = 0 to 31) */
34033 #define IAC_IISRx_ILACIN3_Pos      (3U)
34034 #define IAC_IISRx_ILACIN3_Msk      (0x1UL << IAC_IISRx_ILACIN3_Pos)     /*!< 0x00000008 */
34035 #define IAC_IISRx_ILACIN3          IAC_IISRx_ILACIN3_Msk               /*!< illegal access input 3 (i = 0 to 31) */
34036 #define IAC_IISRx_ILACIN4_Pos      (4U)
34037 #define IAC_IISRx_ILACIN4_Msk      (0x1UL << IAC_IISRx_ILACIN4_Pos)     /*!< 0x00000010 */
34038 #define IAC_IISRx_ILACIN4          IAC_IISRx_ILACIN4_Msk               /*!< illegal access input 4 (i = 0 to 31) */
34039 #define IAC_IISRx_ILACIN5_Pos      (5U)
34040 #define IAC_IISRx_ILACIN5_Msk      (0x1UL << IAC_IISRx_ILACIN5_Pos)     /*!< 0x00000020 */
34041 #define IAC_IISRx_ILACIN5          IAC_IISRx_ILACIN5_Msk               /*!< illegal access input 5 (i = 0 to 31) */
34042 #define IAC_IISRx_ILACIN6_Pos      (6U)
34043 #define IAC_IISRx_ILACIN6_Msk      (0x1UL << IAC_IISRx_ILACIN6_Pos)     /*!< 0x00000040 */
34044 #define IAC_IISRx_ILACIN6          IAC_IISRx_ILACIN6_Msk               /*!< illegal access input 6 (i = 0 to 31) */
34045 #define IAC_IISRx_ILACIN7_Pos      (7U)
34046 #define IAC_IISRx_ILACIN7_Msk      (0x1UL << IAC_IISRx_ILACIN7_Pos)     /*!< 0x00000080 */
34047 #define IAC_IISRx_ILACIN7          IAC_IISRx_ILACIN7_Msk               /*!< illegal access input 7 (i = 0 to 31) */
34048 #define IAC_IISRx_ILACIN8_Pos      (8U)
34049 #define IAC_IISRx_ILACIN8_Msk      (0x1UL << IAC_IISRx_ILACIN8_Pos)     /*!< 0x00000100 */
34050 #define IAC_IISRx_ILACIN8          IAC_IISRx_ILACIN8_Msk               /*!< illegal access input 8 (i = 0 to 31) */
34051 #define IAC_IISRx_ILACIN9_Pos      (9U)
34052 #define IAC_IISRx_ILACIN9_Msk      (0x1UL << IAC_IISRx_ILACIN9_Pos)     /*!< 0x00000200 */
34053 #define IAC_IISRx_ILACIN9          IAC_IISRx_ILACIN9_Msk               /*!< illegal access input 9 (i = 0 to 31) */
34054 #define IAC_IISRx_ILACIN10_Pos     (10U)
34055 #define IAC_IISRx_ILACIN10_Msk     (0x1UL << IAC_IISRx_ILACIN10_Pos)    /*!< 0x00000400 */
34056 #define IAC_IISRx_ILACIN10         IAC_IISRx_ILACIN10_Msk              /*!< illegal access input 10 (i = 0 to 31) */
34057 #define IAC_IISRx_ILACIN11_Pos     (11U)
34058 #define IAC_IISRx_ILACIN11_Msk     (0x1UL << IAC_IISRx_ILACIN11_Pos)    /*!< 0x00000800 */
34059 #define IAC_IISRx_ILACIN11         IAC_IISRx_ILACIN11_Msk              /*!< illegal access input 11 (i = 0 to 31) */
34060 #define IAC_IISRx_ILACIN12_Pos     (12U)
34061 #define IAC_IISRx_ILACIN12_Msk     (0x1UL << IAC_IISRx_ILACIN12_Pos)    /*!< 0x00001000 */
34062 #define IAC_IISRx_ILACIN12         IAC_IISRx_ILACIN12_Msk              /*!< illegal access input 12 (i = 0 to 31) */
34063 #define IAC_IISRx_ILACIN13_Pos     (13U)
34064 #define IAC_IISRx_ILACIN13_Msk     (0x1UL << IAC_IISRx_ILACIN13_Pos)    /*!< 0x00002000 */
34065 #define IAC_IISRx_ILACIN13         IAC_IISRx_ILACIN13_Msk              /*!< illegal access input 13 (i = 0 to 31) */
34066 #define IAC_IISRx_ILACIN14_Pos     (14U)
34067 #define IAC_IISRx_ILACIN14_Msk     (0x1UL << IAC_IISRx_ILACIN14_Pos)    /*!< 0x00004000 */
34068 #define IAC_IISRx_ILACIN14         IAC_IISRx_ILACIN14_Msk              /*!< illegal access input 14 (i = 0 to 31) */
34069 #define IAC_IISRx_ILACIN15_Pos     (15U)
34070 #define IAC_IISRx_ILACIN15_Msk     (0x1UL << IAC_IISRx_ILACIN15_Pos)    /*!< 0x00008000 */
34071 #define IAC_IISRx_ILACIN15         IAC_IISRx_ILACIN15_Msk              /*!< illegal access input 15 (i = 0 to 31) */
34072 #define IAC_IISRx_ILACIN16_Pos     (16U)
34073 #define IAC_IISRx_ILACIN16_Msk     (0x1UL << IAC_IISRx_ILACIN16_Pos)    /*!< 0x00010000 */
34074 #define IAC_IISRx_ILACIN16         IAC_IISRx_ILACIN16_Msk              /*!< illegal access input 16 (i = 0 to 31) */
34075 #define IAC_IISRx_ILACIN17_Pos     (17U)
34076 #define IAC_IISRx_ILACIN17_Msk     (0x1UL << IAC_IISRx_ILACIN17_Pos)    /*!< 0x00020000 */
34077 #define IAC_IISRx_ILACIN17         IAC_IISRx_ILACIN17_Msk              /*!< illegal access input 17 (i = 0 to 31) */
34078 #define IAC_IISRx_ILACIN18_Pos     (18U)
34079 #define IAC_IISRx_ILACIN18_Msk     (0x1UL << IAC_IISRx_ILACIN18_Pos)    /*!< 0x00040000 */
34080 #define IAC_IISRx_ILACIN18         IAC_IISRx_ILACIN18_Msk              /*!< illegal access input 18 (i = 0 to 31) */
34081 #define IAC_IISRx_ILACIN19_Pos     (19U)
34082 #define IAC_IISRx_ILACIN19_Msk     (0x1UL << IAC_IISRx_ILACIN19_Pos)    /*!< 0x00080000 */
34083 #define IAC_IISRx_ILACIN19         IAC_IISRx_ILACIN19_Msk              /*!< illegal access input 19 (i = 0 to 31) */
34084 #define IAC_IISRx_ILACIN20_Pos     (20U)
34085 #define IAC_IISRx_ILACIN20_Msk     (0x1UL << IAC_IISRx_ILACIN20_Pos)    /*!< 0x00100000 */
34086 #define IAC_IISRx_ILACIN20         IAC_IISRx_ILACIN20_Msk              /*!< illegal access input 20 (i = 0 to 31) */
34087 #define IAC_IISRx_ILACIN21_Pos     (21U)
34088 #define IAC_IISRx_ILACIN21_Msk     (0x1UL << IAC_IISRx_ILACIN21_Pos)    /*!< 0x00200000 */
34089 #define IAC_IISRx_ILACIN21         IAC_IISRx_ILACIN21_Msk              /*!< illegal access input 21 (i = 0 to 31) */
34090 #define IAC_IISRx_ILACIN22_Pos     (22U)
34091 #define IAC_IISRx_ILACIN22_Msk     (0x1UL << IAC_IISRx_ILACIN22_Pos)    /*!< 0x00400000 */
34092 #define IAC_IISRx_ILACIN22         IAC_IISRx_ILACIN22_Msk              /*!< illegal access input 22 (i = 0 to 31) */
34093 #define IAC_IISRx_ILACIN23_Pos     (23U)
34094 #define IAC_IISRx_ILACIN23_Msk     (0x1UL << IAC_IISRx_ILACIN23_Pos)    /*!< 0x00800000 */
34095 #define IAC_IISRx_ILACIN23         IAC_IISRx_ILACIN23_Msk              /*!< illegal access input 23 (i = 0 to 31) */
34096 #define IAC_IISRx_ILACIN24_Pos     (24U)
34097 #define IAC_IISRx_ILACIN24_Msk     (0x1UL << IAC_IISRx_ILACIN24_Pos)    /*!< 0x01000000 */
34098 #define IAC_IISRx_ILACIN24         IAC_IISRx_ILACIN24_Msk              /*!< illegal access input 24 (i = 0 to 31) */
34099 #define IAC_IISRx_ILACIN25_Pos     (25U)
34100 #define IAC_IISRx_ILACIN25_Msk     (0x1UL << IAC_IISRx_ILACIN25_Pos)    /*!< 0x02000000 */
34101 #define IAC_IISRx_ILACIN25         IAC_IISRx_ILACIN25_Msk              /*!< illegal access input 25 (i = 0 to 31) */
34102 #define IAC_IISRx_ILACIN26_Pos     (26U)
34103 #define IAC_IISRx_ILACIN26_Msk     (0x1UL << IAC_IISRx_ILACIN26_Pos)    /*!< 0x04000000 */
34104 #define IAC_IISRx_ILACIN26         IAC_IISRx_ILACIN26_Msk              /*!< illegal access input 26 (i = 0 to 31) */
34105 #define IAC_IISRx_ILACIN27_Pos     (27U)
34106 #define IAC_IISRx_ILACIN27_Msk     (0x1UL << IAC_IISRx_ILACIN27_Pos)    /*!< 0x08000000 */
34107 #define IAC_IISRx_ILACIN27         IAC_IISRx_ILACIN27_Msk              /*!< illegal access input 27 (i = 0 to 31) */
34108 #define IAC_IISRx_ILACIN28_Pos     (28U)
34109 #define IAC_IISRx_ILACIN28_Msk     (0x1UL << IAC_IISRx_ILACIN28_Pos)    /*!< 0x10000000 */
34110 #define IAC_IISRx_ILACIN28         IAC_IISRx_ILACIN28_Msk              /*!< illegal access input 28 (i = 0 to 31) */
34111 #define IAC_IISRx_ILACIN29_Pos     (29U)
34112 #define IAC_IISRx_ILACIN29_Msk     (0x1UL << IAC_IISRx_ILACIN29_Pos)    /*!< 0x20000000 */
34113 #define IAC_IISRx_ILACIN29         IAC_IISRx_ILACIN29_Msk              /*!< illegal access input 29 (i = 0 to 31) */
34114 #define IAC_IISRx_ILACIN30_Pos     (30U)
34115 #define IAC_IISRx_ILACIN30_Msk     (0x1UL << IAC_IISRx_ILACIN30_Pos)    /*!< 0x40000000 */
34116 #define IAC_IISRx_ILACIN30         IAC_IISRx_ILACIN30_Msk              /*!< illegal access input 30 (i = 0 to 31) */
34117 #define IAC_IISRx_ILACIN31_Pos     (31U)
34118 #define IAC_IISRx_ILACIN31_Msk     (0x1UL << IAC_IISRx_ILACIN31_Pos)    /*!< 0x80000000 */
34119 #define IAC_IISRx_ILACIN31         IAC_IISRx_ILACIN31_Msk              /*!< illegal access input 31 (i = 0 to 31) */
34120 
34121 
34122 /******************************************************************************/
34123 /*                                                                            */
34124 /*                                    RNG                                     */
34125 /*                                                                            */
34126 /******************************************************************************/
34127 /********************  Bits definition for RNG_CR register  *******************/
34128 #define RNG_CR_RNGEN_Pos                    (2U)
34129 #define RNG_CR_RNGEN_Msk                    (0x1UL << RNG_CR_RNGEN_Pos)             /*!< 0x00000004 */
34130 #define RNG_CR_RNGEN                        RNG_CR_RNGEN_Msk
34131 #define RNG_CR_IE_Pos                       (3U)
34132 #define RNG_CR_IE_Msk                       (0x1UL << RNG_CR_IE_Pos)                /*!< 0x00000008 */
34133 #define RNG_CR_IE                           RNG_CR_IE_Msk
34134 #define RNG_CR_CED_Pos                      (5U)
34135 #define RNG_CR_CED_Msk                      (0x1UL << RNG_CR_CED_Pos)               /*!< 0x00000020 */
34136 #define RNG_CR_CED                          RNG_CR_CED_Msk
34137 #define RNG_CR_ARDIS_Pos                    (7U)
34138 #define RNG_CR_ARDIS_Msk                    (0x1UL << RNG_CR_ARDIS_Pos)
34139 #define RNG_CR_ARDIS                        RNG_CR_ARDIS_Msk
34140 #define RNG_CR_RNG_CONFIG3_Pos              (8U)
34141 #define RNG_CR_RNG_CONFIG3_Msk              (0xFUL << RNG_CR_RNG_CONFIG3_Pos)
34142 #define RNG_CR_RNG_CONFIG3                  RNG_CR_RNG_CONFIG3_Msk
34143 #define RNG_CR_NISTC_Pos                    (12U)
34144 #define RNG_CR_NISTC_Msk                    (0x1UL << RNG_CR_NISTC_Pos)
34145 #define RNG_CR_NISTC                        RNG_CR_NISTC_Msk
34146 #define RNG_CR_RNG_CONFIG2_Pos              (13U)
34147 #define RNG_CR_RNG_CONFIG2_Msk              (0x7UL << RNG_CR_RNG_CONFIG2_Pos)
34148 #define RNG_CR_RNG_CONFIG2                  RNG_CR_RNG_CONFIG2_Msk
34149 #define RNG_CR_CLKDIV_Pos                   (16U)
34150 #define RNG_CR_CLKDIV_Msk                   (0xFUL << RNG_CR_CLKDIV_Pos)
34151 #define RNG_CR_CLKDIV                       RNG_CR_CLKDIV_Msk
34152 #define RNG_CR_CLKDIV_0                     (0x1UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00010000 */
34153 #define RNG_CR_CLKDIV_1                     (0x2UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00020000 */
34154 #define RNG_CR_CLKDIV_2                     (0x4UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00040000 */
34155 #define RNG_CR_CLKDIV_3                     (0x8UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00080000 */
34156 #define RNG_CR_RNG_CONFIG1_Pos              (20U)
34157 #define RNG_CR_RNG_CONFIG1_Msk              (0x3FUL << RNG_CR_RNG_CONFIG1_Pos)
34158 #define RNG_CR_RNG_CONFIG1                  RNG_CR_RNG_CONFIG1_Msk
34159 #define RNG_CR_CONDRST_Pos                  (30U)
34160 #define RNG_CR_CONDRST_Msk                  (0x1UL << RNG_CR_CONDRST_Pos)
34161 #define RNG_CR_CONDRST                      RNG_CR_CONDRST_Msk
34162 #define RNG_CR_CONFIGLOCK_Pos               (31U)
34163 #define RNG_CR_CONFIGLOCK_Msk               (0x1UL << RNG_CR_CONFIGLOCK_Pos)
34164 #define RNG_CR_CONFIGLOCK                   RNG_CR_CONFIGLOCK_Msk
34165 
34166 /********************  Bits definition for RNG_SR register  *******************/
34167 #define RNG_SR_DRDY_Pos                     (0U)
34168 #define RNG_SR_DRDY_Msk                     (0x1UL << RNG_SR_DRDY_Pos)              /*!< 0x00000001 */
34169 #define RNG_SR_DRDY                         RNG_SR_DRDY_Msk
34170 #define RNG_SR_CECS_Pos                     (1U)
34171 #define RNG_SR_CECS_Msk                     (0x1UL << RNG_SR_CECS_Pos)              /*!< 0x00000002 */
34172 #define RNG_SR_CECS                         RNG_SR_CECS_Msk
34173 #define RNG_SR_SECS_Pos                     (2U)
34174 #define RNG_SR_SECS_Msk                     (0x1UL << RNG_SR_SECS_Pos)              /*!< 0x00000004 */
34175 #define RNG_SR_SECS                         RNG_SR_SECS_Msk
34176 #define RNG_SR_CEIS_Pos                     (5U)
34177 #define RNG_SR_CEIS_Msk                     (0x1UL << RNG_SR_CEIS_Pos)              /*!< 0x00000020 */
34178 #define RNG_SR_CEIS                         RNG_SR_CEIS_Msk
34179 #define RNG_SR_SEIS_Pos                     (6U)
34180 #define RNG_SR_SEIS_Msk                     (0x1UL << RNG_SR_SEIS_Pos)              /*!< 0x00000040 */
34181 #define RNG_SR_SEIS                         RNG_SR_SEIS_Msk
34182 
34183 /********************  Bits definition for RNG_HTCR register  *******************/
34184 #define RNG_HTCR_HTCFG_Pos                  (0U)
34185 #define RNG_HTCR_HTCFG_Msk                  (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos)    /*!< 0xFFFFFFFF */
34186 #define RNG_HTCR_HTCFG                      RNG_HTCR_HTCFG_Msk
34187 
34188 
34189 /******************************************************************************/
34190 /*                                                                            */
34191 /*                           Real-Time Clock (RTC)                            */
34192 /*                                                                            */
34193 /******************************************************************************/
34194 /********************  Bits definition for RTC_TR register  *******************/
34195 #define RTC_TR_SU_Pos                       (0U)
34196 #define RTC_TR_SU_Msk                       (0xFUL << RTC_TR_SU_Pos)                /*!< 0x0000000F */
34197 #define RTC_TR_SU                           RTC_TR_SU_Msk
34198 #define RTC_TR_SU_0                         (0x1UL << RTC_TR_SU_Pos)                /*!< 0x00000001 */
34199 #define RTC_TR_SU_1                         (0x2UL << RTC_TR_SU_Pos)                /*!< 0x00000002 */
34200 #define RTC_TR_SU_2                         (0x4UL << RTC_TR_SU_Pos)                /*!< 0x00000004 */
34201 #define RTC_TR_SU_3                         (0x8UL << RTC_TR_SU_Pos)                /*!< 0x00000008 */
34202 #define RTC_TR_ST_Pos                       (4U)
34203 #define RTC_TR_ST_Msk                       (0x7UL << RTC_TR_ST_Pos)                /*!< 0x00000070 */
34204 #define RTC_TR_ST                           RTC_TR_ST_Msk
34205 #define RTC_TR_ST_0                         (0x1UL << RTC_TR_ST_Pos)                /*!< 0x00000010 */
34206 #define RTC_TR_ST_1                         (0x2UL << RTC_TR_ST_Pos)                /*!< 0x00000020 */
34207 #define RTC_TR_ST_2                         (0x4UL << RTC_TR_ST_Pos)                /*!< 0x00000040 */
34208 #define RTC_TR_MNU_Pos                      (8U)
34209 #define RTC_TR_MNU_Msk                      (0xFUL << RTC_TR_MNU_Pos)               /*!< 0x00000F00 */
34210 #define RTC_TR_MNU                          RTC_TR_MNU_Msk
34211 #define RTC_TR_MNU_0                        (0x1UL << RTC_TR_MNU_Pos)               /*!< 0x00000100 */
34212 #define RTC_TR_MNU_1                        (0x2UL << RTC_TR_MNU_Pos)               /*!< 0x00000200 */
34213 #define RTC_TR_MNU_2                        (0x4UL << RTC_TR_MNU_Pos)               /*!< 0x00000400 */
34214 #define RTC_TR_MNU_3                        (0x8UL << RTC_TR_MNU_Pos)               /*!< 0x00000800 */
34215 #define RTC_TR_MNT_Pos                      (12U)
34216 #define RTC_TR_MNT_Msk                      (0x7UL << RTC_TR_MNT_Pos)               /*!< 0x00007000 */
34217 #define RTC_TR_MNT                          RTC_TR_MNT_Msk
34218 #define RTC_TR_MNT_0                        (0x1UL << RTC_TR_MNT_Pos)               /*!< 0x00001000 */
34219 #define RTC_TR_MNT_1                        (0x2UL << RTC_TR_MNT_Pos)               /*!< 0x00002000 */
34220 #define RTC_TR_MNT_2                        (0x4UL << RTC_TR_MNT_Pos)               /*!< 0x00004000 */
34221 #define RTC_TR_HU_Pos                       (16U)
34222 #define RTC_TR_HU_Msk                       (0xFUL << RTC_TR_HU_Pos)                /*!< 0x000F0000 */
34223 #define RTC_TR_HU                           RTC_TR_HU_Msk
34224 #define RTC_TR_HU_0                         (0x1UL << RTC_TR_HU_Pos)                /*!< 0x00010000 */
34225 #define RTC_TR_HU_1                         (0x2UL << RTC_TR_HU_Pos)                /*!< 0x00020000 */
34226 #define RTC_TR_HU_2                         (0x4UL << RTC_TR_HU_Pos)                /*!< 0x00040000 */
34227 #define RTC_TR_HU_3                         (0x8UL << RTC_TR_HU_Pos)                /*!< 0x00080000 */
34228 #define RTC_TR_HT_Pos                       (20U)
34229 #define RTC_TR_HT_Msk                       (0x3UL << RTC_TR_HT_Pos)                /*!< 0x00300000 */
34230 #define RTC_TR_HT                           RTC_TR_HT_Msk
34231 #define RTC_TR_HT_0                         (0x1UL << RTC_TR_HT_Pos)                /*!< 0x00100000 */
34232 #define RTC_TR_HT_1                         (0x2UL << RTC_TR_HT_Pos)                /*!< 0x00200000 */
34233 #define RTC_TR_PM_Pos                       (22U)
34234 #define RTC_TR_PM_Msk                       (0x1UL << RTC_TR_PM_Pos)                /*!< 0x00400000 */
34235 #define RTC_TR_PM                           RTC_TR_PM_Msk
34236 
34237 /********************  Bits definition for RTC_DR register  *******************/
34238 #define RTC_DR_DU_Pos                       (0U)
34239 #define RTC_DR_DU_Msk                       (0xFUL << RTC_DR_DU_Pos)                /*!< 0x0000000F */
34240 #define RTC_DR_DU                           RTC_DR_DU_Msk
34241 #define RTC_DR_DU_0                         (0x1UL << RTC_DR_DU_Pos)                /*!< 0x00000001 */
34242 #define RTC_DR_DU_1                         (0x2UL << RTC_DR_DU_Pos)                /*!< 0x00000002 */
34243 #define RTC_DR_DU_2                         (0x4UL << RTC_DR_DU_Pos)                /*!< 0x00000004 */
34244 #define RTC_DR_DU_3                         (0x8UL << RTC_DR_DU_Pos)                /*!< 0x00000008 */
34245 #define RTC_DR_DT_Pos                       (4U)
34246 #define RTC_DR_DT_Msk                       (0x3UL << RTC_DR_DT_Pos)                /*!< 0x00000030 */
34247 #define RTC_DR_DT                           RTC_DR_DT_Msk
34248 #define RTC_DR_DT_0                         (0x1UL << RTC_DR_DT_Pos)                /*!< 0x00000010 */
34249 #define RTC_DR_DT_1                         (0x2UL << RTC_DR_DT_Pos)                /*!< 0x00000020 */
34250 #define RTC_DR_MU_Pos                       (8U)
34251 #define RTC_DR_MU_Msk                       (0xFUL << RTC_DR_MU_Pos)                /*!< 0x00000F00 */
34252 #define RTC_DR_MU                           RTC_DR_MU_Msk
34253 #define RTC_DR_MU_0                         (0x1UL << RTC_DR_MU_Pos)                /*!< 0x00000100 */
34254 #define RTC_DR_MU_1                         (0x2UL << RTC_DR_MU_Pos)                /*!< 0x00000200 */
34255 #define RTC_DR_MU_2                         (0x4UL << RTC_DR_MU_Pos)                /*!< 0x00000400 */
34256 #define RTC_DR_MU_3                         (0x8UL << RTC_DR_MU_Pos)                /*!< 0x00000800 */
34257 #define RTC_DR_MT_Pos                       (12U)
34258 #define RTC_DR_MT_Msk                       (0x1UL << RTC_DR_MT_Pos)                /*!< 0x00001000 */
34259 #define RTC_DR_MT                           RTC_DR_MT_Msk
34260 #define RTC_DR_WDU_Pos                      (13U)
34261 #define RTC_DR_WDU_Msk                      (0x7UL << RTC_DR_WDU_Pos)               /*!< 0x0000E000 */
34262 #define RTC_DR_WDU                          RTC_DR_WDU_Msk
34263 #define RTC_DR_WDU_0                        (0x1UL << RTC_DR_WDU_Pos)               /*!< 0x00002000 */
34264 #define RTC_DR_WDU_1                        (0x2UL << RTC_DR_WDU_Pos)               /*!< 0x00004000 */
34265 #define RTC_DR_WDU_2                        (0x4UL << RTC_DR_WDU_Pos)               /*!< 0x00008000 */
34266 #define RTC_DR_YU_Pos                       (16U)
34267 #define RTC_DR_YU_Msk                       (0xFUL << RTC_DR_YU_Pos)                /*!< 0x000F0000 */
34268 #define RTC_DR_YU                           RTC_DR_YU_Msk
34269 #define RTC_DR_YU_0                         (0x1UL << RTC_DR_YU_Pos)                /*!< 0x00010000 */
34270 #define RTC_DR_YU_1                         (0x2UL << RTC_DR_YU_Pos)                /*!< 0x00020000 */
34271 #define RTC_DR_YU_2                         (0x4UL << RTC_DR_YU_Pos)                /*!< 0x00040000 */
34272 #define RTC_DR_YU_3                         (0x8UL << RTC_DR_YU_Pos)                /*!< 0x00080000 */
34273 #define RTC_DR_YT_Pos                       (20U)
34274 #define RTC_DR_YT_Msk                       (0xFUL << RTC_DR_YT_Pos)                /*!< 0x00F00000 */
34275 #define RTC_DR_YT                           RTC_DR_YT_Msk
34276 #define RTC_DR_YT_0                         (0x1UL << RTC_DR_YT_Pos)                /*!< 0x00100000 */
34277 #define RTC_DR_YT_1                         (0x2UL << RTC_DR_YT_Pos)                /*!< 0x00200000 */
34278 #define RTC_DR_YT_2                         (0x4UL << RTC_DR_YT_Pos)                /*!< 0x00400000 */
34279 #define RTC_DR_YT_3                         (0x8UL << RTC_DR_YT_Pos)                /*!< 0x00800000 */
34280 
34281 /********************  Bits definition for RTC_SSR register  ******************/
34282 #define RTC_SSR_SS_Pos                      (0U)
34283 #define RTC_SSR_SS_Msk                      (0xFFFFFFFFUL << RTC_SSR_SS_Pos)        /*!< 0xFFFFFFFF */
34284 #define RTC_SSR_SS                          RTC_SSR_SS_Msk
34285 
34286 /********************  Bits definition for RTC_ICSR register  ******************/
34287 #define RTC_ICSR_WUTWF_Pos                  (2U)
34288 #define RTC_ICSR_WUTWF_Msk                  (0x1UL << RTC_ICSR_WUTWF_Pos)           /*!< 0x00000004 */
34289 #define RTC_ICSR_WUTWF                      RTC_ICSR_WUTWF_Msk
34290 #define RTC_ICSR_SHPF_Pos                   (3U)
34291 #define RTC_ICSR_SHPF_Msk                   (0x1UL << RTC_ICSR_SHPF_Pos)            /*!< 0x00000008 */
34292 #define RTC_ICSR_SHPF                       RTC_ICSR_SHPF_Msk
34293 #define RTC_ICSR_INITS_Pos                  (4U)
34294 #define RTC_ICSR_INITS_Msk                  (0x1UL << RTC_ICSR_INITS_Pos)           /*!< 0x00000010 */
34295 #define RTC_ICSR_INITS                      RTC_ICSR_INITS_Msk
34296 #define RTC_ICSR_RSF_Pos                    (5U)
34297 #define RTC_ICSR_RSF_Msk                    (0x1UL << RTC_ICSR_RSF_Pos)             /*!< 0x00000020 */
34298 #define RTC_ICSR_RSF                        RTC_ICSR_RSF_Msk
34299 #define RTC_ICSR_INITF_Pos                  (6U)
34300 #define RTC_ICSR_INITF_Msk                  (0x1UL << RTC_ICSR_INITF_Pos)           /*!< 0x00000040 */
34301 #define RTC_ICSR_INITF                      RTC_ICSR_INITF_Msk
34302 #define RTC_ICSR_INIT_Pos                   (7U)
34303 #define RTC_ICSR_INIT_Msk                   (0x1UL << RTC_ICSR_INIT_Pos)            /*!< 0x00000080 */
34304 #define RTC_ICSR_INIT                       RTC_ICSR_INIT_Msk
34305 #define RTC_ICSR_BIN_Pos                    (8U)
34306 #define RTC_ICSR_BIN_Msk                    (0x3UL << RTC_ICSR_BIN_Pos)             /*!< 0x00000300 */
34307 #define RTC_ICSR_BIN                        RTC_ICSR_BIN_Msk
34308 #define RTC_ICSR_BIN_0                      (0x1UL << RTC_ICSR_BIN_Pos)             /*!< 0x00000100 */
34309 #define RTC_ICSR_BIN_1                      (0x2UL << RTC_ICSR_BIN_Pos)             /*!< 0x00000200 */
34310 #define RTC_ICSR_BCDU_Pos                   (10U)
34311 #define RTC_ICSR_BCDU_Msk                   (0x7UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00001C00 */
34312 #define RTC_ICSR_BCDU                       RTC_ICSR_BCDU_Msk
34313 #define RTC_ICSR_BCDU_0                     (0x1UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00000400 */
34314 #define RTC_ICSR_BCDU_1                     (0x2UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00000800 */
34315 #define RTC_ICSR_BCDU_2                     (0x4UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00001000 */
34316 #define RTC_ICSR_RECALPF_Pos                (16U)
34317 #define RTC_ICSR_RECALPF_Msk                (0x1UL << RTC_ICSR_RECALPF_Pos)         /*!< 0x00010000 */
34318 #define RTC_ICSR_RECALPF                    RTC_ICSR_RECALPF_Msk
34319 
34320 /********************  Bits definition for RTC_PRER register  *****************/
34321 #define RTC_PRER_PREDIV_S_Pos               (0U)
34322 #define RTC_PRER_PREDIV_S_Msk               (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)     /*!< 0x00007FFF */
34323 #define RTC_PRER_PREDIV_S                   RTC_PRER_PREDIV_S_Msk
34324 #define RTC_PRER_PREDIV_A_Pos               (16U)
34325 #define RTC_PRER_PREDIV_A_Msk               (0x7FUL << RTC_PRER_PREDIV_A_Pos)       /*!< 0x007F0000 */
34326 #define RTC_PRER_PREDIV_A                   RTC_PRER_PREDIV_A_Msk
34327 
34328 /********************  Bits definition for RTC_WUTR register  *****************/
34329 #define RTC_WUTR_WUT_Pos                    (0U)
34330 #define RTC_WUTR_WUT_Msk                    (0xFFFFUL << RTC_WUTR_WUT_Pos)          /*!< 0x0000FFFF */
34331 #define RTC_WUTR_WUT                        RTC_WUTR_WUT_Msk
34332 #define RTC_WUTR_WUTOCLR_Pos                (16U)
34333 #define RTC_WUTR_WUTOCLR_Msk                (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos)      /*!< 0x0000FFFF */
34334 #define RTC_WUTR_WUTOCLR                    RTC_WUTR_WUTOCLR_Msk
34335 
34336 /********************  Bits definition for RTC_CR register  *******************/
34337 #define RTC_CR_WUCKSEL_Pos                  (0U)
34338 #define RTC_CR_WUCKSEL_Msk                  (0x7UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000007 */
34339 #define RTC_CR_WUCKSEL                      RTC_CR_WUCKSEL_Msk
34340 #define RTC_CR_WUCKSEL_0                    (0x1UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000001 */
34341 #define RTC_CR_WUCKSEL_1                    (0x2UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000002 */
34342 #define RTC_CR_WUCKSEL_2                    (0x4UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000004 */
34343 #define RTC_CR_TSEDGE_Pos                   (3U)
34344 #define RTC_CR_TSEDGE_Msk                   (0x1UL << RTC_CR_TSEDGE_Pos)            /*!< 0x00000008 */
34345 #define RTC_CR_TSEDGE                       RTC_CR_TSEDGE_Msk
34346 #define RTC_CR_REFCKON_Pos                  (4U)
34347 #define RTC_CR_REFCKON_Msk                  (0x1UL << RTC_CR_REFCKON_Pos)           /*!< 0x00000010 */
34348 #define RTC_CR_REFCKON                      RTC_CR_REFCKON_Msk
34349 #define RTC_CR_BYPSHAD_Pos                  (5U)
34350 #define RTC_CR_BYPSHAD_Msk                  (0x1UL << RTC_CR_BYPSHAD_Pos)           /*!< 0x00000020 */
34351 #define RTC_CR_BYPSHAD                      RTC_CR_BYPSHAD_Msk
34352 #define RTC_CR_FMT_Pos                      (6U)
34353 #define RTC_CR_FMT_Msk                      (0x1UL << RTC_CR_FMT_Pos)               /*!< 0x00000040 */
34354 #define RTC_CR_FMT                          RTC_CR_FMT_Msk
34355 #define RTC_CR_SSRUIE_Pos                   (7U)
34356 #define RTC_CR_SSRUIE_Msk                   (0x1UL << RTC_CR_SSRUIE_Pos)            /*!< 0x00000080 */
34357 #define RTC_CR_SSRUIE                       RTC_CR_SSRUIE_Msk
34358 #define RTC_CR_ALRAE_Pos                    (8U)
34359 #define RTC_CR_ALRAE_Msk                    (0x1UL << RTC_CR_ALRAE_Pos)             /*!< 0x00000100 */
34360 #define RTC_CR_ALRAE                        RTC_CR_ALRAE_Msk
34361 #define RTC_CR_ALRBE_Pos                    (9U)
34362 #define RTC_CR_ALRBE_Msk                    (0x1UL << RTC_CR_ALRBE_Pos)             /*!< 0x00000200 */
34363 #define RTC_CR_ALRBE                        RTC_CR_ALRBE_Msk
34364 #define RTC_CR_WUTE_Pos                     (10U)
34365 #define RTC_CR_WUTE_Msk                     (0x1UL << RTC_CR_WUTE_Pos)              /*!< 0x00000400 */
34366 #define RTC_CR_WUTE                         RTC_CR_WUTE_Msk
34367 #define RTC_CR_TSE_Pos                      (11U)
34368 #define RTC_CR_TSE_Msk                      (0x1UL << RTC_CR_TSE_Pos)               /*!< 0x00000800 */
34369 #define RTC_CR_TSE                          RTC_CR_TSE_Msk
34370 #define RTC_CR_ALRAIE_Pos                   (12U)
34371 #define RTC_CR_ALRAIE_Msk                   (0x1UL << RTC_CR_ALRAIE_Pos)            /*!< 0x00001000 */
34372 #define RTC_CR_ALRAIE                       RTC_CR_ALRAIE_Msk
34373 #define RTC_CR_ALRBIE_Pos                   (13U)
34374 #define RTC_CR_ALRBIE_Msk                   (0x1UL << RTC_CR_ALRBIE_Pos)            /*!< 0x00002000 */
34375 #define RTC_CR_ALRBIE                       RTC_CR_ALRBIE_Msk
34376 #define RTC_CR_WUTIE_Pos                    (14U)
34377 #define RTC_CR_WUTIE_Msk                    (0x1UL << RTC_CR_WUTIE_Pos)             /*!< 0x00004000 */
34378 #define RTC_CR_WUTIE                        RTC_CR_WUTIE_Msk
34379 #define RTC_CR_TSIE_Pos                     (15U)
34380 #define RTC_CR_TSIE_Msk                     (0x1UL << RTC_CR_TSIE_Pos)              /*!< 0x00008000 */
34381 #define RTC_CR_TSIE                         RTC_CR_TSIE_Msk
34382 #define RTC_CR_ADD1H_Pos                    (16U)
34383 #define RTC_CR_ADD1H_Msk                    (0x1UL << RTC_CR_ADD1H_Pos)             /*!< 0x00010000 */
34384 #define RTC_CR_ADD1H                        RTC_CR_ADD1H_Msk
34385 #define RTC_CR_SUB1H_Pos                    (17U)
34386 #define RTC_CR_SUB1H_Msk                    (0x1UL << RTC_CR_SUB1H_Pos)             /*!< 0x00020000 */
34387 #define RTC_CR_SUB1H                        RTC_CR_SUB1H_Msk
34388 #define RTC_CR_BKP_Pos                      (18U)
34389 #define RTC_CR_BKP_Msk                      (0x1UL << RTC_CR_BKP_Pos)               /*!< 0x00040000 */
34390 #define RTC_CR_BKP                          RTC_CR_BKP_Msk
34391 #define RTC_CR_COSEL_Pos                    (19U)
34392 #define RTC_CR_COSEL_Msk                    (0x1UL << RTC_CR_COSEL_Pos)             /*!< 0x00080000 */
34393 #define RTC_CR_COSEL                        RTC_CR_COSEL_Msk
34394 #define RTC_CR_POL_Pos                      (20U)
34395 #define RTC_CR_POL_Msk                      (0x1UL << RTC_CR_POL_Pos)               /*!< 0x00100000 */
34396 #define RTC_CR_POL                          RTC_CR_POL_Msk
34397 #define RTC_CR_OSEL_Pos                     (21U)
34398 #define RTC_CR_OSEL_Msk                     (0x3UL << RTC_CR_OSEL_Pos)              /*!< 0x00600000 */
34399 #define RTC_CR_OSEL                         RTC_CR_OSEL_Msk
34400 #define RTC_CR_OSEL_0                       (0x1UL << RTC_CR_OSEL_Pos)              /*!< 0x00200000 */
34401 #define RTC_CR_OSEL_1                       (0x2UL << RTC_CR_OSEL_Pos)              /*!< 0x00400000 */
34402 #define RTC_CR_COE_Pos                      (23U)
34403 #define RTC_CR_COE_Msk                      (0x1UL << RTC_CR_COE_Pos)               /*!< 0x00800000 */
34404 #define RTC_CR_COE                          RTC_CR_COE_Msk
34405 #define RTC_CR_ITSE_Pos                     (24U)
34406 #define RTC_CR_ITSE_Msk                     (0x1UL << RTC_CR_ITSE_Pos)              /*!< 0x01000000 */
34407 #define RTC_CR_ITSE                         RTC_CR_ITSE_Msk                         /*!<Timestamp on internal event enable  */
34408 #define RTC_CR_TAMPTS_Pos                   (25U)
34409 #define RTC_CR_TAMPTS_Msk                   (0x1UL << RTC_CR_TAMPTS_Pos)            /*!< 0x02000000 */
34410 #define RTC_CR_TAMPTS                       RTC_CR_TAMPTS_Msk                       /*!<Activate timestamp on tamper detection event  */
34411 #define RTC_CR_TAMPOE_Pos                   (26U)
34412 #define RTC_CR_TAMPOE_Msk                   (0x1UL << RTC_CR_TAMPOE_Pos)            /*!< 0x04000000 */
34413 #define RTC_CR_TAMPOE                       RTC_CR_TAMPOE_Msk                       /*!<Tamper detection output enable on TAMPALARM  */
34414 #define RTC_CR_ALRAFCLR_Pos                 (27U)
34415 #define RTC_CR_ALRAFCLR_Msk                 (0x1UL << RTC_CR_ALRAFCLR_Pos)          /*!< 0x8000000 */
34416 #define RTC_CR_ALRAFCLR                     RTC_CR_ALRAFCLR_Msk                     /*!<Alarm A mask */
34417 #define RTC_CR_ALRBFCLR_Pos                 (28U)
34418 #define RTC_CR_ALRBFCLR_Msk                 (0x1UL << RTC_CR_ALRBFCLR_Pos)          /*!< 0x10000000 */
34419 #define RTC_CR_ALRBFCLR                     RTC_CR_ALRBFCLR_Msk                     /*!<Alarm B mask */
34420 #define RTC_CR_TAMPALRM_PU_Pos              (29U)
34421 #define RTC_CR_TAMPALRM_PU_Msk              (0x1UL << RTC_CR_TAMPALRM_PU_Pos)       /*!< 0x20000000 */
34422 #define RTC_CR_TAMPALRM_PU                  RTC_CR_TAMPALRM_PU_Msk                  /*!<TAMPALARM output pull-up config */
34423 #define RTC_CR_TAMPALRM_TYPE_Pos            (30U)
34424 #define RTC_CR_TAMPALRM_TYPE_Msk            (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos)     /*!< 0x40000000 */
34425 #define RTC_CR_TAMPALRM_TYPE                RTC_CR_TAMPALRM_TYPE_Msk                /*!<TAMPALARM output type  */
34426 #define RTC_CR_OUT2EN_Pos                   (31U)
34427 #define RTC_CR_OUT2EN_Msk                   (0x1UL << RTC_CR_OUT2EN_Pos)            /*!< 0x80000000 */
34428 #define RTC_CR_OUT2EN                       RTC_CR_OUT2EN_Msk                       /*!<RTC_OUT2 output enable */
34429 
34430 /********************  Bits definition for RTC_PRIVCFGR register  *****************/
34431 #define RTC_PRIVCFGR_ALRAPRIV_Pos           (0U)
34432 #define RTC_PRIVCFGR_ALRAPRIV_Msk           (0x1UL << RTC_PRIVCFGR_ALRAPRIV_Pos)    /*!< 0x00000001 */
34433 #define RTC_PRIVCFGR_ALRAPRIV               RTC_PRIVCFGR_ALRAPRIV_Msk
34434 #define RTC_PRIVCFGR_ALRBPRIV_Pos           (1U)
34435 #define RTC_PRIVCFGR_ALRBPRIV_Msk           (0x1UL << RTC_PRIVCFGR_ALRBPRIV_Pos)    /*!< 0x00000002 */
34436 #define RTC_PRIVCFGR_ALRBPRIV               RTC_PRIVCFGR_ALRBPRIV_Msk
34437 #define RTC_PRIVCFGR_WUTPRIV_Pos            (2U)
34438 #define RTC_PRIVCFGR_WUTPRIV_Msk            (0x1UL << RTC_PRIVCFGR_WUTPRIV_Pos)     /*!< 0x00000004 */
34439 #define RTC_PRIVCFGR_WUTPRIV                RTC_PRIVCFGR_WUTPRIV_Msk
34440 #define RTC_PRIVCFGR_TSPRIV_Pos             (3U)
34441 #define RTC_PRIVCFGR_TSPRIV_Msk             (0x1UL << RTC_PRIVCFGR_TSPRIV_Pos)      /*!< 0x00000008 */
34442 #define RTC_PRIVCFGR_TSPRIV                 RTC_PRIVCFGR_TSPRIV_Msk
34443 #define RTC_PRIVCFGR_CALPRIV_Pos            (13U)
34444 #define RTC_PRIVCFGR_CALPRIV_Msk            (0x1UL << RTC_PRIVCFGR_CALPRIV_Pos)     /*!< 0x00002000 */
34445 #define RTC_PRIVCFGR_CALPRIV                RTC_PRIVCFGR_CALPRIV_Msk
34446 #define RTC_PRIVCFGR_INITPRIV_Pos           (14U)
34447 #define RTC_PRIVCFGR_INITPRIV_Msk           (0x1UL << RTC_PRIVCFGR_INITPRIV_Pos)    /*!< 0x00004000 */
34448 #define RTC_PRIVCFGR_INITPRIV               RTC_PRIVCFGR_INITPRIV_Msk
34449 #define RTC_PRIVCFGR_PRIV_Pos               (15U)
34450 #define RTC_PRIVCFGR_PRIV_Msk               (0x1UL << RTC_PRIVCFGR_PRIV_Pos)        /*!< 0x00008000 */
34451 #define RTC_PRIVCFGR_PRIV                   RTC_PRIVCFGR_PRIV_Msk
34452 
34453 /********************  Bits definition for RTC_SECCFGR register  ******************/
34454 #define RTC_SECCFGR_ALRASEC_Pos             (0U)
34455 #define RTC_SECCFGR_ALRASEC_Msk             (0x1UL << RTC_SECCFGR_ALRASEC_Pos)      /*!< 0x00000001 */
34456 #define RTC_SECCFGR_ALRASEC                 RTC_SECCFGR_ALRASEC_Msk
34457 #define RTC_SECCFGR_ALRBSEC_Pos             (1U)
34458 #define RTC_SECCFGR_ALRBSEC_Msk             (0x1UL << RTC_SECCFGR_ALRBSEC_Pos)      /*!< 0x00000002 */
34459 #define RTC_SECCFGR_ALRBSEC                 RTC_SECCFGR_ALRBSEC_Msk
34460 #define RTC_SECCFGR_WUTSEC_Pos              (2U)
34461 #define RTC_SECCFGR_WUTSEC_Msk              (0x1UL << RTC_SECCFGR_WUTSEC_Pos)       /*!< 0x00000004 */
34462 #define RTC_SECCFGR_WUTSEC                  RTC_SECCFGR_WUTSEC_Msk
34463 #define RTC_SECCFGR_TSSEC_Pos               (3U)
34464 #define RTC_SECCFGR_TSSEC_Msk               (0x1UL << RTC_SECCFGR_TSSEC_Pos)        /*!< 0x00000008 */
34465 #define RTC_SECCFGR_TSSEC                   RTC_SECCFGR_TSSEC_Msk
34466 #define RTC_SECCFGR_CALSEC_Pos              (13U)
34467 #define RTC_SECCFGR_CALSEC_Msk              (0x1UL << RTC_SECCFGR_CALSEC_Pos)       /*!< 0x00002000 */
34468 #define RTC_SECCFGR_CALSEC                  RTC_SECCFGR_CALSEC_Msk
34469 #define RTC_SECCFGR_INITSEC_Pos             (14U)
34470 #define RTC_SECCFGR_INITSEC_Msk             (0x1UL << RTC_SECCFGR_INITSEC_Pos)      /*!< 0x00004000 */
34471 #define RTC_SECCFGR_INITSEC                 RTC_SECCFGR_INITSEC_Msk
34472 #define RTC_SECCFGR_SEC_Pos                 (15U)
34473 #define RTC_SECCFGR_SEC_Msk                 (0x1UL << RTC_SECCFGR_SEC_Pos)          /*!< 0x00008000 */
34474 #define RTC_SECCFGR_SEC                     RTC_SECCFGR_SEC_Msk
34475 
34476 /********************  Bits definition for RTC_WPR register  ******************/
34477 #define RTC_WPR_KEY_Pos                     (0U)
34478 #define RTC_WPR_KEY_Msk                     (0xFFUL << RTC_WPR_KEY_Pos)             /*!< 0x000000FF */
34479 #define RTC_WPR_KEY                         RTC_WPR_KEY_Msk
34480 
34481 /********************  Bits definition for RTC_CALR register  *****************/
34482 #define RTC_CALR_CALM_Pos                   (0U)
34483 #define RTC_CALR_CALM_Msk                   (0x1FFUL << RTC_CALR_CALM_Pos)          /*!< 0x000001FF */
34484 #define RTC_CALR_CALM                       RTC_CALR_CALM_Msk
34485 #define RTC_CALR_CALM_0                     (0x001UL << RTC_CALR_CALM_Pos)          /*!< 0x00000001 */
34486 #define RTC_CALR_CALM_1                     (0x002UL << RTC_CALR_CALM_Pos)          /*!< 0x00000002 */
34487 #define RTC_CALR_CALM_2                     (0x004UL << RTC_CALR_CALM_Pos)          /*!< 0x00000004 */
34488 #define RTC_CALR_CALM_3                     (0x008UL << RTC_CALR_CALM_Pos)          /*!< 0x00000008 */
34489 #define RTC_CALR_CALM_4                     (0x010UL << RTC_CALR_CALM_Pos)          /*!< 0x00000010 */
34490 #define RTC_CALR_CALM_5                     (0x020UL << RTC_CALR_CALM_Pos)          /*!< 0x00000020 */
34491 #define RTC_CALR_CALM_6                     (0x040UL << RTC_CALR_CALM_Pos)          /*!< 0x00000040 */
34492 #define RTC_CALR_CALM_7                     (0x080UL << RTC_CALR_CALM_Pos)          /*!< 0x00000080 */
34493 #define RTC_CALR_CALM_8                     (0x100UL << RTC_CALR_CALM_Pos)          /*!< 0x00000100 */
34494 #define RTC_CALR_LPCAL_Pos                  (12U)
34495 #define RTC_CALR_LPCAL_Msk                  (0x1UL << RTC_CALR_LPCAL_Pos)           /*!< 0x00001000 */
34496 #define RTC_CALR_CALW16                     RTC_CALR_CALW16_Msk
34497 #define RTC_CALR_CALW16_Pos                 (13U)
34498 #define RTC_CALR_CALW16_Msk                 (0x1UL << RTC_CALR_CALW16_Pos)          /*!< 0x00002000 */
34499 #define RTC_CALR_LPCAL                      RTC_CALR_LPCAL_Msk
34500 #define RTC_CALR_CALW8_Pos                  (14U)
34501 #define RTC_CALR_CALW8_Msk                  (0x1UL << RTC_CALR_CALW8_Pos)           /*!< 0x00004000 */
34502 #define RTC_CALR_CALW8                      RTC_CALR_CALW8_Msk
34503 #define RTC_CALR_CALP_Pos                   (15U)
34504 #define RTC_CALR_CALP_Msk                   (0x1UL << RTC_CALR_CALP_Pos)            /*!< 0x00008000 */
34505 #define RTC_CALR_CALP                       RTC_CALR_CALP_Msk
34506 
34507 /********************  Bits definition for RTC_SHIFTR register  ***************/
34508 #define RTC_SHIFTR_SUBFS_Pos                (0U)
34509 #define RTC_SHIFTR_SUBFS_Msk                (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)      /*!< 0x00007FFF */
34510 #define RTC_SHIFTR_SUBFS                    RTC_SHIFTR_SUBFS_Msk
34511 #define RTC_SHIFTR_ADD1S_Pos                (31U)
34512 #define RTC_SHIFTR_ADD1S_Msk                (0x1UL << RTC_SHIFTR_ADD1S_Pos)         /*!< 0x80000000 */
34513 #define RTC_SHIFTR_ADD1S                    RTC_SHIFTR_ADD1S_Msk
34514 
34515 /********************  Bits definition for RTC_TSTR register  *****************/
34516 #define RTC_TSTR_SU_Pos                     (0U)
34517 #define RTC_TSTR_SU_Msk                     (0xFUL << RTC_TSTR_SU_Pos)              /*!< 0x0000000F */
34518 #define RTC_TSTR_SU                         RTC_TSTR_SU_Msk
34519 #define RTC_TSTR_SU_0                       (0x1UL << RTC_TSTR_SU_Pos)              /*!< 0x00000001 */
34520 #define RTC_TSTR_SU_1                       (0x2UL << RTC_TSTR_SU_Pos)              /*!< 0x00000002 */
34521 #define RTC_TSTR_SU_2                       (0x4UL << RTC_TSTR_SU_Pos)              /*!< 0x00000004 */
34522 #define RTC_TSTR_SU_3                       (0x8UL << RTC_TSTR_SU_Pos)              /*!< 0x00000008 */
34523 #define RTC_TSTR_ST_Pos                     (4U)
34524 #define RTC_TSTR_ST_Msk                     (0x7UL << RTC_TSTR_ST_Pos)              /*!< 0x00000070 */
34525 #define RTC_TSTR_ST                         RTC_TSTR_ST_Msk
34526 #define RTC_TSTR_ST_0                       (0x1UL << RTC_TSTR_ST_Pos)              /*!< 0x00000010 */
34527 #define RTC_TSTR_ST_1                       (0x2UL << RTC_TSTR_ST_Pos)              /*!< 0x00000020 */
34528 #define RTC_TSTR_ST_2                       (0x4UL << RTC_TSTR_ST_Pos)              /*!< 0x00000040 */
34529 #define RTC_TSTR_MNU_Pos                    (8U)
34530 #define RTC_TSTR_MNU_Msk                    (0xFUL << RTC_TSTR_MNU_Pos)             /*!< 0x00000F00 */
34531 #define RTC_TSTR_MNU                        RTC_TSTR_MNU_Msk
34532 #define RTC_TSTR_MNU_0                      (0x1UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000100 */
34533 #define RTC_TSTR_MNU_1                      (0x2UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000200 */
34534 #define RTC_TSTR_MNU_2                      (0x4UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000400 */
34535 #define RTC_TSTR_MNU_3                      (0x8UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000800 */
34536 #define RTC_TSTR_MNT_Pos                    (12U)
34537 #define RTC_TSTR_MNT_Msk                    (0x7UL << RTC_TSTR_MNT_Pos)             /*!< 0x00007000 */
34538 #define RTC_TSTR_MNT                        RTC_TSTR_MNT_Msk
34539 #define RTC_TSTR_MNT_0                      (0x1UL << RTC_TSTR_MNT_Pos)             /*!< 0x00001000 */
34540 #define RTC_TSTR_MNT_1                      (0x2UL << RTC_TSTR_MNT_Pos)             /*!< 0x00002000 */
34541 #define RTC_TSTR_MNT_2                      (0x4UL << RTC_TSTR_MNT_Pos)             /*!< 0x00004000 */
34542 #define RTC_TSTR_HU_Pos                     (16U)
34543 #define RTC_TSTR_HU_Msk                     (0xFUL << RTC_TSTR_HU_Pos)              /*!< 0x000F0000 */
34544 #define RTC_TSTR_HU                         RTC_TSTR_HU_Msk
34545 #define RTC_TSTR_HU_0                       (0x1UL << RTC_TSTR_HU_Pos)              /*!< 0x00010000 */
34546 #define RTC_TSTR_HU_1                       (0x2UL << RTC_TSTR_HU_Pos)              /*!< 0x00020000 */
34547 #define RTC_TSTR_HU_2                       (0x4UL << RTC_TSTR_HU_Pos)              /*!< 0x00040000 */
34548 #define RTC_TSTR_HU_3                       (0x8UL << RTC_TSTR_HU_Pos)              /*!< 0x00080000 */
34549 #define RTC_TSTR_HT_Pos                     (20U)
34550 #define RTC_TSTR_HT_Msk                     (0x3UL << RTC_TSTR_HT_Pos)              /*!< 0x00300000 */
34551 #define RTC_TSTR_HT                         RTC_TSTR_HT_Msk
34552 #define RTC_TSTR_HT_0                       (0x1UL << RTC_TSTR_HT_Pos)              /*!< 0x00100000 */
34553 #define RTC_TSTR_HT_1                       (0x2UL << RTC_TSTR_HT_Pos)              /*!< 0x00200000 */
34554 #define RTC_TSTR_PM_Pos                     (22U)
34555 #define RTC_TSTR_PM_Msk                     (0x1UL << RTC_TSTR_PM_Pos)              /*!< 0x00400000 */
34556 #define RTC_TSTR_PM                         RTC_TSTR_PM_Msk
34557 
34558 /********************  Bits definition for RTC_TSDR register  *****************/
34559 #define RTC_TSDR_DU_Pos                     (0U)
34560 #define RTC_TSDR_DU_Msk                     (0xFUL << RTC_TSDR_DU_Pos)              /*!< 0x0000000F */
34561 #define RTC_TSDR_DU                         RTC_TSDR_DU_Msk
34562 #define RTC_TSDR_DU_0                       (0x1UL << RTC_TSDR_DU_Pos)              /*!< 0x00000001 */
34563 #define RTC_TSDR_DU_1                       (0x2UL << RTC_TSDR_DU_Pos)              /*!< 0x00000002 */
34564 #define RTC_TSDR_DU_2                       (0x4UL << RTC_TSDR_DU_Pos)              /*!< 0x00000004 */
34565 #define RTC_TSDR_DU_3                       (0x8UL << RTC_TSDR_DU_Pos)              /*!< 0x00000008 */
34566 #define RTC_TSDR_DT_Pos                     (4U)
34567 #define RTC_TSDR_DT_Msk                     (0x3UL << RTC_TSDR_DT_Pos)              /*!< 0x00000030 */
34568 #define RTC_TSDR_DT                         RTC_TSDR_DT_Msk
34569 #define RTC_TSDR_DT_0                       (0x1UL << RTC_TSDR_DT_Pos)              /*!< 0x00000010 */
34570 #define RTC_TSDR_DT_1                       (0x2UL << RTC_TSDR_DT_Pos)              /*!< 0x00000020 */
34571 #define RTC_TSDR_MU_Pos                     (8U)
34572 #define RTC_TSDR_MU_Msk                     (0xFUL << RTC_TSDR_MU_Pos)              /*!< 0x00000F00 */
34573 #define RTC_TSDR_MU                         RTC_TSDR_MU_Msk
34574 #define RTC_TSDR_MU_0                       (0x1UL << RTC_TSDR_MU_Pos)              /*!< 0x00000100 */
34575 #define RTC_TSDR_MU_1                       (0x2UL << RTC_TSDR_MU_Pos)              /*!< 0x00000200 */
34576 #define RTC_TSDR_MU_2                       (0x4UL << RTC_TSDR_MU_Pos)              /*!< 0x00000400 */
34577 #define RTC_TSDR_MU_3                       (0x8UL << RTC_TSDR_MU_Pos)              /*!< 0x00000800 */
34578 #define RTC_TSDR_MT_Pos                     (12U)
34579 #define RTC_TSDR_MT_Msk                     (0x1UL << RTC_TSDR_MT_Pos)              /*!< 0x00001000 */
34580 #define RTC_TSDR_MT                         RTC_TSDR_MT_Msk
34581 #define RTC_TSDR_WDU_Pos                    (13U)
34582 #define RTC_TSDR_WDU_Msk                    (0x7UL << RTC_TSDR_WDU_Pos)             /*!< 0x0000E000 */
34583 #define RTC_TSDR_WDU                        RTC_TSDR_WDU_Msk
34584 #define RTC_TSDR_WDU_0                      (0x1UL << RTC_TSDR_WDU_Pos)             /*!< 0x00002000 */
34585 #define RTC_TSDR_WDU_1                      (0x2UL << RTC_TSDR_WDU_Pos)             /*!< 0x00004000 */
34586 #define RTC_TSDR_WDU_2                      (0x4UL << RTC_TSDR_WDU_Pos)             /*!< 0x00008000 */
34587 
34588 /********************  Bits definition for RTC_TSSSR register  ****************/
34589 #define RTC_TSSSR_SS_Pos                    (0U)
34590 #define RTC_TSSSR_SS_Msk                    (0xFFFFFFFFUL << RTC_TSSSR_SS_Pos)      /*!< 0xFFFFFFFF */
34591 #define RTC_TSSSR_SS                        RTC_TSSSR_SS_Msk                        /*!< rtc timestamp sub second > */
34592 
34593 /********************  Bits definition for RTC_ALRMAR register  ***************/
34594 #define RTC_ALRMAR_SU_Pos                   (0U)
34595 #define RTC_ALRMAR_SU_Msk                   (0xFUL << RTC_ALRMAR_SU_Pos)            /*!< 0x0000000F */
34596 #define RTC_ALRMAR_SU                       RTC_ALRMAR_SU_Msk
34597 #define RTC_ALRMAR_SU_0                     (0x1UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000001 */
34598 #define RTC_ALRMAR_SU_1                     (0x2UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000002 */
34599 #define RTC_ALRMAR_SU_2                     (0x4UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000004 */
34600 #define RTC_ALRMAR_SU_3                     (0x8UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000008 */
34601 #define RTC_ALRMAR_ST_Pos                   (4U)
34602 #define RTC_ALRMAR_ST_Msk                   (0x7UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000070 */
34603 #define RTC_ALRMAR_ST                       RTC_ALRMAR_ST_Msk
34604 #define RTC_ALRMAR_ST_0                     (0x1UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000010 */
34605 #define RTC_ALRMAR_ST_1                     (0x2UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000020 */
34606 #define RTC_ALRMAR_ST_2                     (0x4UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000040 */
34607 #define RTC_ALRMAR_MSK1_Pos                 (7U)
34608 #define RTC_ALRMAR_MSK1_Msk                 (0x1UL << RTC_ALRMAR_MSK1_Pos)          /*!< 0x00000080 */
34609 #define RTC_ALRMAR_MSK1                     RTC_ALRMAR_MSK1_Msk
34610 #define RTC_ALRMAR_MNU_Pos                  (8U)
34611 #define RTC_ALRMAR_MNU_Msk                  (0xFUL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000F00 */
34612 #define RTC_ALRMAR_MNU                      RTC_ALRMAR_MNU_Msk
34613 #define RTC_ALRMAR_MNU_0                    (0x1UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000100 */
34614 #define RTC_ALRMAR_MNU_1                    (0x2UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000200 */
34615 #define RTC_ALRMAR_MNU_2                    (0x4UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000400 */
34616 #define RTC_ALRMAR_MNU_3                    (0x8UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000800 */
34617 #define RTC_ALRMAR_MNT_Pos                  (12U)
34618 #define RTC_ALRMAR_MNT_Msk                  (0x7UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00007000 */
34619 #define RTC_ALRMAR_MNT                      RTC_ALRMAR_MNT_Msk
34620 #define RTC_ALRMAR_MNT_0                    (0x1UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00001000 */
34621 #define RTC_ALRMAR_MNT_1                    (0x2UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00002000 */
34622 #define RTC_ALRMAR_MNT_2                    (0x4UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00004000 */
34623 #define RTC_ALRMAR_MSK2_Pos                 (15U)
34624 #define RTC_ALRMAR_MSK2_Msk                 (0x1UL << RTC_ALRMAR_MSK2_Pos)          /*!< 0x00008000 */
34625 #define RTC_ALRMAR_MSK2                     RTC_ALRMAR_MSK2_Msk
34626 #define RTC_ALRMAR_HU_Pos                   (16U)
34627 #define RTC_ALRMAR_HU_Msk                   (0xFUL << RTC_ALRMAR_HU_Pos)            /*!< 0x000F0000 */
34628 #define RTC_ALRMAR_HU                       RTC_ALRMAR_HU_Msk
34629 #define RTC_ALRMAR_HU_0                     (0x1UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00010000 */
34630 #define RTC_ALRMAR_HU_1                     (0x2UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00020000 */
34631 #define RTC_ALRMAR_HU_2                     (0x4UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00040000 */
34632 #define RTC_ALRMAR_HU_3                     (0x8UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00080000 */
34633 #define RTC_ALRMAR_HT_Pos                   (20U)
34634 #define RTC_ALRMAR_HT_Msk                   (0x3UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00300000 */
34635 #define RTC_ALRMAR_HT                       RTC_ALRMAR_HT_Msk
34636 #define RTC_ALRMAR_HT_0                     (0x1UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00100000 */
34637 #define RTC_ALRMAR_HT_1                     (0x2UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00200000 */
34638 #define RTC_ALRMAR_PM_Pos                   (22U)
34639 #define RTC_ALRMAR_PM_Msk                   (0x1UL << RTC_ALRMAR_PM_Pos)            /*!< 0x00400000 */
34640 #define RTC_ALRMAR_PM                       RTC_ALRMAR_PM_Msk
34641 #define RTC_ALRMAR_MSK3_Pos                 (23U)
34642 #define RTC_ALRMAR_MSK3_Msk                 (0x1UL << RTC_ALRMAR_MSK3_Pos)          /*!< 0x00800000 */
34643 #define RTC_ALRMAR_MSK3                     RTC_ALRMAR_MSK3_Msk
34644 #define RTC_ALRMAR_DU_Pos                   (24U)
34645 #define RTC_ALRMAR_DU_Msk                   (0xFUL << RTC_ALRMAR_DU_Pos)            /*!< 0x0F000000 */
34646 #define RTC_ALRMAR_DU                       RTC_ALRMAR_DU_Msk
34647 #define RTC_ALRMAR_DU_0                     (0x1UL << RTC_ALRMAR_DU_Pos)            /*!< 0x01000000 */
34648 #define RTC_ALRMAR_DU_1                     (0x2UL << RTC_ALRMAR_DU_Pos)            /*!< 0x02000000 */
34649 #define RTC_ALRMAR_DU_2                     (0x4UL << RTC_ALRMAR_DU_Pos)            /*!< 0x04000000 */
34650 #define RTC_ALRMAR_DU_3                     (0x8UL << RTC_ALRMAR_DU_Pos)            /*!< 0x08000000 */
34651 #define RTC_ALRMAR_DT_Pos                   (28U)
34652 #define RTC_ALRMAR_DT_Msk                   (0x3UL << RTC_ALRMAR_DT_Pos)            /*!< 0x30000000 */
34653 #define RTC_ALRMAR_DT                       RTC_ALRMAR_DT_Msk
34654 #define RTC_ALRMAR_DT_0                     (0x1UL << RTC_ALRMAR_DT_Pos)            /*!< 0x10000000 */
34655 #define RTC_ALRMAR_DT_1                     (0x2UL << RTC_ALRMAR_DT_Pos)            /*!< 0x20000000 */
34656 #define RTC_ALRMAR_WDSEL_Pos                (30U)
34657 #define RTC_ALRMAR_WDSEL_Msk                (0x1UL << RTC_ALRMAR_WDSEL_Pos)         /*!< 0x40000000 */
34658 #define RTC_ALRMAR_WDSEL                    RTC_ALRMAR_WDSEL_Msk
34659 #define RTC_ALRMAR_MSK4_Pos                 (31U)
34660 #define RTC_ALRMAR_MSK4_Msk                 (0x1UL << RTC_ALRMAR_MSK4_Pos)          /*!< 0x80000000 */
34661 #define RTC_ALRMAR_MSK4                     RTC_ALRMAR_MSK4_Msk
34662 
34663 /********************  Bits definition for RTC_ALRMASSR register  *************/
34664 #define RTC_ALRMASSR_SS_Pos                 (0U)
34665 #define RTC_ALRMASSR_SS_Msk                 (0x7FFFUL << RTC_ALRMASSR_SS_Pos)       /*!< 0x00007FFF */
34666 #define RTC_ALRMASSR_SS                     RTC_ALRMASSR_SS_Msk
34667 #define RTC_ALRMASSR_MASKSS_Pos             (24U)
34668 #define RTC_ALRMASSR_MASKSS_Msk             (0x3FUL << RTC_ALRMASSR_MASKSS_Pos)     /*!< 0x3F000000 */
34669 #define RTC_ALRMASSR_MASKSS                 RTC_ALRMASSR_MASKSS_Msk
34670 #define RTC_ALRMASSR_MASKSS_0               (0x1UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x01000000 */
34671 #define RTC_ALRMASSR_MASKSS_1               (0x2UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x02000000 */
34672 #define RTC_ALRMASSR_MASKSS_2               (0x4UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x04000000 */
34673 #define RTC_ALRMASSR_MASKSS_3               (0x8UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x08000000 */
34674 #define RTC_ALRMASSR_MASKSS_4               (0x10UL << RTC_ALRMASSR_MASKSS_Pos)     /*!< 0x10000000 */
34675 #define RTC_ALRMASSR_MASKSS_5               (0x20UL << RTC_ALRMASSR_MASKSS_Pos)     /*!< 0x20000000 */
34676 #define RTC_ALRMASSR_SSCLR_Pos              (31U)
34677 #define RTC_ALRMASSR_SSCLR_Msk              (0x1UL << RTC_ALRMASSR_SSCLR_Pos)       /*!< 0x80000000 */
34678 #define RTC_ALRMASSR_SSCLR                  RTC_ALRMASSR_SSCLR_Msk
34679 
34680 /********************  Bits definition for RTC_ALRMBR register  ***************/
34681 #define RTC_ALRMBR_SU_Pos                   (0U)
34682 #define RTC_ALRMBR_SU_Msk                   (0xFUL << RTC_ALRMBR_SU_Pos)            /*!< 0x0000000F */
34683 #define RTC_ALRMBR_SU                       RTC_ALRMBR_SU_Msk
34684 #define RTC_ALRMBR_SU_0                     (0x1UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000001 */
34685 #define RTC_ALRMBR_SU_1                     (0x2UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000002 */
34686 #define RTC_ALRMBR_SU_2                     (0x4UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000004 */
34687 #define RTC_ALRMBR_SU_3                     (0x8UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000008 */
34688 #define RTC_ALRMBR_ST_Pos                   (4U)
34689 #define RTC_ALRMBR_ST_Msk                   (0x7UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000070 */
34690 #define RTC_ALRMBR_ST                       RTC_ALRMBR_ST_Msk
34691 #define RTC_ALRMBR_ST_0                     (0x1UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000010 */
34692 #define RTC_ALRMBR_ST_1                     (0x2UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000020 */
34693 #define RTC_ALRMBR_ST_2                     (0x4UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000040 */
34694 #define RTC_ALRMBR_MSK1_Pos                 (7U)
34695 #define RTC_ALRMBR_MSK1_Msk                 (0x1UL << RTC_ALRMBR_MSK1_Pos)          /*!< 0x00000080 */
34696 #define RTC_ALRMBR_MSK1                     RTC_ALRMBR_MSK1_Msk
34697 #define RTC_ALRMBR_MNU_Pos                  (8U)
34698 #define RTC_ALRMBR_MNU_Msk                  (0xFUL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000F00 */
34699 #define RTC_ALRMBR_MNU                      RTC_ALRMBR_MNU_Msk
34700 #define RTC_ALRMBR_MNU_0                    (0x1UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000100 */
34701 #define RTC_ALRMBR_MNU_1                    (0x2UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000200 */
34702 #define RTC_ALRMBR_MNU_2                    (0x4UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000400 */
34703 #define RTC_ALRMBR_MNU_3                    (0x8UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000800 */
34704 #define RTC_ALRMBR_MNT_Pos                  (12U)
34705 #define RTC_ALRMBR_MNT_Msk                  (0x7UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00007000 */
34706 #define RTC_ALRMBR_MNT                      RTC_ALRMBR_MNT_Msk
34707 #define RTC_ALRMBR_MNT_0                    (0x1UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00001000 */
34708 #define RTC_ALRMBR_MNT_1                    (0x2UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00002000 */
34709 #define RTC_ALRMBR_MNT_2                    (0x4UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00004000 */
34710 #define RTC_ALRMBR_MSK2_Pos                 (15U)
34711 #define RTC_ALRMBR_MSK2_Msk                 (0x1UL << RTC_ALRMBR_MSK2_Pos)          /*!< 0x00008000 */
34712 #define RTC_ALRMBR_MSK2                     RTC_ALRMBR_MSK2_Msk
34713 #define RTC_ALRMBR_HU_Pos                   (16U)
34714 #define RTC_ALRMBR_HU_Msk                   (0xFUL << RTC_ALRMBR_HU_Pos)            /*!< 0x000F0000 */
34715 #define RTC_ALRMBR_HU                       RTC_ALRMBR_HU_Msk
34716 #define RTC_ALRMBR_HU_0                     (0x1UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00010000 */
34717 #define RTC_ALRMBR_HU_1                     (0x2UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00020000 */
34718 #define RTC_ALRMBR_HU_2                     (0x4UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00040000 */
34719 #define RTC_ALRMBR_HU_3                     (0x8UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00080000 */
34720 #define RTC_ALRMBR_HT_Pos                   (20U)
34721 #define RTC_ALRMBR_HT_Msk                   (0x3UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00300000 */
34722 #define RTC_ALRMBR_HT                       RTC_ALRMBR_HT_Msk
34723 #define RTC_ALRMBR_HT_0                     (0x1UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00100000 */
34724 #define RTC_ALRMBR_HT_1                     (0x2UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00200000 */
34725 #define RTC_ALRMBR_PM_Pos                   (22U)
34726 #define RTC_ALRMBR_PM_Msk                   (0x1UL << RTC_ALRMBR_PM_Pos)            /*!< 0x00400000 */
34727 #define RTC_ALRMBR_PM                       RTC_ALRMBR_PM_Msk
34728 #define RTC_ALRMBR_MSK3_Pos                 (23U)
34729 #define RTC_ALRMBR_MSK3_Msk                 (0x1UL << RTC_ALRMBR_MSK3_Pos)          /*!< 0x00800000 */
34730 #define RTC_ALRMBR_MSK3                     RTC_ALRMBR_MSK3_Msk
34731 #define RTC_ALRMBR_DU_Pos                   (24U)
34732 #define RTC_ALRMBR_DU_Msk                   (0xFUL << RTC_ALRMBR_DU_Pos)            /*!< 0x0F000000 */
34733 #define RTC_ALRMBR_DU                       RTC_ALRMBR_DU_Msk
34734 #define RTC_ALRMBR_DU_0                     (0x1UL << RTC_ALRMBR_DU_Pos)            /*!< 0x01000000 */
34735 #define RTC_ALRMBR_DU_1                     (0x2UL << RTC_ALRMBR_DU_Pos)            /*!< 0x02000000 */
34736 #define RTC_ALRMBR_DU_2                     (0x4UL << RTC_ALRMBR_DU_Pos)            /*!< 0x04000000 */
34737 #define RTC_ALRMBR_DU_3                     (0x8UL << RTC_ALRMBR_DU_Pos)            /*!< 0x08000000 */
34738 #define RTC_ALRMBR_DT_Pos                   (28U)
34739 #define RTC_ALRMBR_DT_Msk                   (0x3UL << RTC_ALRMBR_DT_Pos)            /*!< 0x30000000 */
34740 #define RTC_ALRMBR_DT                       RTC_ALRMBR_DT_Msk
34741 #define RTC_ALRMBR_DT_0                     (0x1UL << RTC_ALRMBR_DT_Pos)            /*!< 0x10000000 */
34742 #define RTC_ALRMBR_DT_1                     (0x2UL << RTC_ALRMBR_DT_Pos)            /*!< 0x20000000 */
34743 #define RTC_ALRMBR_WDSEL_Pos                (30U)
34744 #define RTC_ALRMBR_WDSEL_Msk                (0x1UL << RTC_ALRMBR_WDSEL_Pos)         /*!< 0x40000000 */
34745 #define RTC_ALRMBR_WDSEL                    RTC_ALRMBR_WDSEL_Msk
34746 #define RTC_ALRMBR_MSK4_Pos                 (31U)
34747 #define RTC_ALRMBR_MSK4_Msk                 (0x1UL << RTC_ALRMBR_MSK4_Pos)          /*!< 0x80000000 */
34748 #define RTC_ALRMBR_MSK4                     RTC_ALRMBR_MSK4_Msk
34749 
34750 /********************  Bits definition for RTC_ALRMBSSR register  *************/
34751 #define RTC_ALRMBSSR_SS_Pos                 (0U)
34752 #define RTC_ALRMBSSR_SS_Msk                 (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)       /*!< 0x00007FFF */
34753 #define RTC_ALRMBSSR_SS                     RTC_ALRMBSSR_SS_Msk
34754 #define RTC_ALRMBSSR_MASKSS_Pos             (24U)
34755 #define RTC_ALRMBSSR_MASKSS_Msk             (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos)     /*!< 0x3F000000 */
34756 #define RTC_ALRMBSSR_MASKSS                 RTC_ALRMBSSR_MASKSS_Msk
34757 #define RTC_ALRMBSSR_MASKSS_0               (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x01000000 */
34758 #define RTC_ALRMBSSR_MASKSS_1               (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x02000000 */
34759 #define RTC_ALRMBSSR_MASKSS_2               (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x04000000 */
34760 #define RTC_ALRMBSSR_MASKSS_3               (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x08000000 */
34761 #define RTC_ALRMBSSR_MASKSS_4               (0x10UL << RTC_ALRMBSSR_MASKSS_Pos)     /*!< 0x10000000 */
34762 #define RTC_ALRMBSSR_MASKSS_5               (0x20UL << RTC_ALRMBSSR_MASKSS_Pos)     /*!< 0x20000000 */
34763 #define RTC_ALRMBSSR_SSCLR_Pos              (31U)
34764 #define RTC_ALRMBSSR_SSCLR_Msk              (0x1UL << RTC_ALRMBSSR_SSCLR_Pos)       /*!< 0x80000000 */
34765 #define RTC_ALRMBSSR_SSCLR                  RTC_ALRMBSSR_SSCLR_Msk
34766 
34767 /********************  Bits definition for RTC_SR register  *******************/
34768 #define RTC_SR_ALRAF_Pos                    (0U)
34769 #define RTC_SR_ALRAF_Msk                    (0x1UL << RTC_SR_ALRAF_Pos)             /*!< 0x00000001 */
34770 #define RTC_SR_ALRAF                        RTC_SR_ALRAF_Msk
34771 #define RTC_SR_ALRBF_Pos                    (1U)
34772 #define RTC_SR_ALRBF_Msk                    (0x1UL << RTC_SR_ALRBF_Pos)             /*!< 0x00000002 */
34773 #define RTC_SR_ALRBF                        RTC_SR_ALRBF_Msk
34774 #define RTC_SR_WUTF_Pos                     (2U)
34775 #define RTC_SR_WUTF_Msk                     (0x1UL << RTC_SR_WUTF_Pos)              /*!< 0x00000004 */
34776 #define RTC_SR_WUTF                         RTC_SR_WUTF_Msk
34777 #define RTC_SR_TSF_Pos                      (3U)
34778 #define RTC_SR_TSF_Msk                      (0x1UL << RTC_SR_TSF_Pos)               /*!< 0x00000008 */
34779 #define RTC_SR_TSF                          RTC_SR_TSF_Msk
34780 #define RTC_SR_TSOVF_Pos                    (4U)
34781 #define RTC_SR_TSOVF_Msk                    (0x1UL << RTC_SR_TSOVF_Pos)             /*!< 0x00000010 */
34782 #define RTC_SR_TSOVF                        RTC_SR_TSOVF_Msk
34783 #define RTC_SR_ITSF_Pos                     (5U)
34784 #define RTC_SR_ITSF_Msk                     (0x1UL << RTC_SR_ITSF_Pos)              /*!< 0x00000020 */
34785 #define RTC_SR_ITSF                         RTC_SR_ITSF_Msk
34786 #define RTC_SR_SSRUF_Pos                    (6U)
34787 #define RTC_SR_SSRUF_Msk                    (0x1UL << RTC_SR_SSRUF_Pos)             /*!< 0x00000040 */
34788 #define RTC_SR_SSRUF                        RTC_SR_SSRUF_Msk
34789 
34790 /********************  Bits definition for RTC_MISR register  *****************/
34791 #define RTC_MISR_ALRAMF_Pos                 (0U)
34792 #define RTC_MISR_ALRAMF_Msk                 (0x1UL << RTC_MISR_ALRAMF_Pos)          /*!< 0x00000001 */
34793 #define RTC_MISR_ALRAMF                     RTC_MISR_ALRAMF_Msk
34794 #define RTC_MISR_ALRBMF_Pos                 (1U)
34795 #define RTC_MISR_ALRBMF_Msk                 (0x1UL << RTC_MISR_ALRBMF_Pos)          /*!< 0x00000002 */
34796 #define RTC_MISR_ALRBMF                     RTC_MISR_ALRBMF_Msk
34797 #define RTC_MISR_WUTMF_Pos                  (2U)
34798 #define RTC_MISR_WUTMF_Msk                  (0x1UL << RTC_MISR_WUTMF_Pos)           /*!< 0x00000004 */
34799 #define RTC_MISR_WUTMF                      RTC_MISR_WUTMF_Msk
34800 #define RTC_MISR_TSMF_Pos                   (3U)
34801 #define RTC_MISR_TSMF_Msk                   (0x1UL << RTC_MISR_TSMF_Pos)            /*!< 0x00000008 */
34802 #define RTC_MISR_TSMF                       RTC_MISR_TSMF_Msk
34803 #define RTC_MISR_TSOVMF_Pos                 (4U)
34804 #define RTC_MISR_TSOVMF_Msk                 (0x1UL << RTC_MISR_TSOVMF_Pos)          /*!< 0x00000010 */
34805 #define RTC_MISR_TSOVMF                     RTC_MISR_TSOVMF_Msk
34806 #define RTC_MISR_ITSMF_Pos                  (5U)
34807 #define RTC_MISR_ITSMF_Msk                  (0x1UL << RTC_MISR_ITSMF_Pos)           /*!< 0x00000020 */
34808 #define RTC_MISR_ITSMF                      RTC_MISR_ITSMF_Msk
34809 #define RTC_MISR_SSRUMF_Pos                 (6U)
34810 #define RTC_MISR_SSRUMF_Msk                 (0x1UL << RTC_MISR_SSRUMF_Pos)          /*!< 0x00000040 */
34811 #define RTC_MISR_SSRUMF                     RTC_MISR_SSRUMF_Msk
34812 
34813 /********************  Bits definition for RTC_SMISR register  *****************/
34814 #define RTC_SMISR_ALRAMF_Pos                (0U)
34815 #define RTC_SMISR_ALRAMF_Msk                (0x1UL << RTC_SMISR_ALRAMF_Pos)         /*!< 0x00000001 */
34816 #define RTC_SMISR_ALRAMF                    RTC_SMISR_ALRAMF_Msk
34817 #define RTC_SMISR_ALRBMF_Pos                (1U)
34818 #define RTC_SMISR_ALRBMF_Msk                (0x1UL << RTC_SMISR_ALRBMF_Pos)         /*!< 0x00000002 */
34819 #define RTC_SMISR_ALRBMF                    RTC_SMISR_ALRBMF_Msk
34820 #define RTC_SMISR_WUTMF_Pos                 (2U)
34821 #define RTC_SMISR_WUTMF_Msk                 (0x1UL << RTC_SMISR_WUTMF_Pos)          /*!< 0x00000004 */
34822 #define RTC_SMISR_WUTMF                     RTC_SMISR_WUTMF_Msk
34823 #define RTC_SMISR_TSMF_Pos                  (3U)
34824 #define RTC_SMISR_TSMF_Msk                  (0x1UL << RTC_SMISR_TSMF_Pos)           /*!< 0x00000008 */
34825 #define RTC_SMISR_TSMF                      RTC_SMISR_TSMF_Msk
34826 #define RTC_SMISR_TSOVMF_Pos                (4U)
34827 #define RTC_SMISR_TSOVMF_Msk                (0x1UL << RTC_SMISR_TSOVMF_Pos)         /*!< 0x00000010 */
34828 #define RTC_SMISR_TSOVMF                    RTC_SMISR_TSOVMF_Msk
34829 #define RTC_SMISR_ITSMF_Pos                 (5U)
34830 #define RTC_SMISR_ITSMF_Msk                 (0x1UL << RTC_SMISR_ITSMF_Pos)          /*!< 0x00000020 */
34831 #define RTC_SMISR_ITSMF                     RTC_SMISR_ITSMF_Msk
34832 #define RTC_SMISR_SSRUMF_Pos                (6U)
34833 #define RTC_SMISR_SSRUMF_Msk                (0x1UL << RTC_SMISR_SSRUMF_Pos)         /*!< 0x00000040 */
34834 #define RTC_SMISR_SSRUMF                    RTC_SMISR_SSRUMF_Msk
34835 
34836 /********************  Bits definition for RTC_SCR register  ******************/
34837 #define RTC_SCR_CALRAF_Pos                  (0U)
34838 #define RTC_SCR_CALRAF_Msk                  (0x1UL << RTC_SCR_CALRAF_Pos)           /*!< 0x00000001 */
34839 #define RTC_SCR_CALRAF                      RTC_SCR_CALRAF_Msk
34840 #define RTC_SCR_CALRBF_Pos                  (1U)
34841 #define RTC_SCR_CALRBF_Msk                  (0x1UL << RTC_SCR_CALRBF_Pos)           /*!< 0x00000002 */
34842 #define RTC_SCR_CALRBF                      RTC_SCR_CALRBF_Msk
34843 #define RTC_SCR_CWUTF_Pos                   (2U)
34844 #define RTC_SCR_CWUTF_Msk                   (0x1UL << RTC_SCR_CWUTF_Pos)            /*!< 0x00000004 */
34845 #define RTC_SCR_CWUTF                       RTC_SCR_CWUTF_Msk
34846 #define RTC_SCR_CTSF_Pos                    (3U)
34847 #define RTC_SCR_CTSF_Msk                    (0x1UL << RTC_SCR_CTSF_Pos)             /*!< 0x00000008 */
34848 #define RTC_SCR_CTSF                        RTC_SCR_CTSF_Msk
34849 #define RTC_SCR_CTSOVF_Pos                  (4U)
34850 #define RTC_SCR_CTSOVF_Msk                  (0x1UL << RTC_SCR_CTSOVF_Pos)           /*!< 0x00000010 */
34851 #define RTC_SCR_CTSOVF                      RTC_SCR_CTSOVF_Msk
34852 #define RTC_SCR_CITSF_Pos                   (5U)
34853 #define RTC_SCR_CITSF_Msk                   (0x1UL << RTC_SCR_CITSF_Pos)            /*!< 0x00000020 */
34854 #define RTC_SCR_CITSF                       RTC_SCR_CITSF_Msk
34855 #define RTC_SCR_CSSRUF_Pos                  (6U)
34856 #define RTC_SCR_CSSRUF_Msk                  (0x1UL << RTC_SCR_CSSRUF_Pos)           /*!< 0x00000040 */
34857 #define RTC_SCR_CSSRUF                      RTC_SCR_CSSRUF_Msk
34858 
34859 /********************  Bits definition for RTC_ALRABINR register  ******************/
34860 #define RTC_ALRABINR_SS_Pos                 (0U)
34861 #define RTC_ALRABINR_SS_Msk                 (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos)   /*!< 0xFFFFFFFF */
34862 #define RTC_ALRABINR_SS                     RTC_ALRABINR_SS_Msk
34863 
34864 /********************  Bits definition for RTC_ALRBBINR register  ******************/
34865 #define RTC_ALRBBINR_SS_Pos                 (0U)
34866 #define RTC_ALRBBINR_SS_Msk                 (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos)   /*!< 0xFFFFFFFF */
34867 #define RTC_ALRBBINR_SS                     RTC_ALRBBINR_SS_Msk
34868 
34869 
34870 /******************************************************************************/
34871 /*                                                                            */
34872 /*               Secure Advanced Encryption Standard (SAES)                   */
34873 /*                                                                            */
34874 /******************************************************************************/
34875 /*******************  Bits definition for SAES_CR register  *********************/
34876 #define SAES_CR_EN_Pos                       (0U)
34877 #define SAES_CR_EN_Msk                       (0x1UL << SAES_CR_EN_Pos)                /*!< 0x00000001 */
34878 #define SAES_CR_EN                           SAES_CR_EN_Msk                           /*!< SAES Enable */
34879 #define SAES_CR_DATATYPE_Pos                 (1U)
34880 #define SAES_CR_DATATYPE_Msk                 (0x3UL << SAES_CR_DATATYPE_Pos)          /*!< 0x00000006 */
34881 #define SAES_CR_DATATYPE                     SAES_CR_DATATYPE_Msk                     /*!< Data type selection */
34882 #define SAES_CR_DATATYPE_0                   (0x1UL << SAES_CR_DATATYPE_Pos)          /*!< 0x00000002 */
34883 #define SAES_CR_DATATYPE_1                   (0x2UL << SAES_CR_DATATYPE_Pos)          /*!< 0x00000004 */
34884 #define SAES_CR_MODE_Pos                     (3U)
34885 #define SAES_CR_MODE_Msk                     (0x3UL << SAES_CR_MODE_Pos)              /*!< 0x00000018 */
34886 #define SAES_CR_MODE                         SAES_CR_MODE_Msk                         /*!< SAES Mode Of Operation */
34887 #define SAES_CR_MODE_0                       (0x1UL << SAES_CR_MODE_Pos)              /*!< 0x00000008 */
34888 #define SAES_CR_MODE_1                       (0x2UL << SAES_CR_MODE_Pos)              /*!< 0x00000010 */
34889 #define SAES_CR_CHMOD_Pos                    (5U)
34890 #define SAES_CR_CHMOD_Msk                    (0x803UL << SAES_CR_CHMOD_Pos)           /*!< 0x00010060 */
34891 #define SAES_CR_CHMOD                        SAES_CR_CHMOD_Msk                        /*!< SAES Chaining Mode */
34892 #define SAES_CR_CHMOD_0                      (0x1UL << SAES_CR_CHMOD_Pos)             /*!< 0x00000020*/
34893 #define SAES_CR_CHMOD_1                      (0x2UL << SAES_CR_CHMOD_Pos)             /*!< 0x00000040 */
34894 #define SAES_CR_CHMOD_2                      (0x800UL << SAES_CR_CHMOD_Pos)           /*!< 0x00010000 */
34895 #define SAES_CR_DMAINEN_Pos                  (11U)
34896 #define SAES_CR_DMAINEN_Msk                  (0x1UL << SAES_CR_DMAINEN_Pos)           /*!< 0x00000800 */
34897 #define SAES_CR_DMAINEN                      SAES_CR_DMAINEN_Msk                      /*!< Enable data input phase DMA management  */
34898 #define SAES_CR_DMAOUTEN_Pos                 (12U)
34899 #define SAES_CR_DMAOUTEN_Msk                 (0x1UL << SAES_CR_DMAOUTEN_Pos)          /*!< 0x00001000 */
34900 #define SAES_CR_DMAOUTEN                     SAES_CR_DMAOUTEN_Msk                     /*!< Enable data output phase DMA management */
34901 #define SAES_CR_GCMPH_Pos                    (13U)
34902 #define SAES_CR_GCMPH_Msk                    (0x3UL << SAES_CR_GCMPH_Pos)             /*!< 0x0006000 */
34903 #define SAES_CR_GCMPH                        SAES_CR_GCMPH_Msk                        /*!< GCM or CCM phase selection */
34904 #define SAES_CR_GCMPH_0                      (0x1UL << SAES_CR_GCMPH_Pos)             /*!< 0x00020000 */
34905 #define SAES_CR_GCMPH_1                      (0x2UL << SAES_CR_GCMPH_Pos)             /*!< 0x00040000 */
34906 #define SAES_CR_KEYSIZE_Pos                  (18U)
34907 #define SAES_CR_KEYSIZE_Msk                  (0x1UL << SAES_CR_KEYSIZE_Pos)           /*!< 0x00040000 */
34908 #define SAES_CR_KEYSIZE                      SAES_CR_KEYSIZE_Msk                      /*!< Key size selection */
34909 #define SAES_CR_KEYPROT_Pos                  (19U)
34910 #define SAES_CR_KEYPROT_Msk                  (0x1UL << SAES_CR_KEYPROT_Pos)           /*!< 0x00080000 */
34911 #define SAES_CR_KEYPROT                      SAES_CR_KEYPROT_Msk                      /*!<  Key protection */
34912 #define SAES_CR_NPBLB_Pos                    (20U)
34913 #define SAES_CR_NPBLB_Msk                    (0xFUL << SAES_CR_NPBLB_Pos)             /*!< 0x00F00000 */
34914 #define SAES_CR_NPBLB                        SAES_CR_NPBLB_Msk                        /*!< Number of padding bytes in last block */
34915 #define SAES_CR_NPBLB_0                      (0x1UL << SAES_CR_NPBLB_Pos)             /*!< 0x00100000 */
34916 #define SAES_CR_NPBLB_1                      (0x2UL << SAES_CR_NPBLB_Pos)             /*!< 0x00200000 */
34917 #define SAES_CR_NPBLB_2                      (0x4UL << SAES_CR_NPBLB_Pos)             /*!< 0x00400000 */
34918 #define SAES_CR_NPBLB_3                      (0x8UL << SAES_CR_NPBLB_Pos)             /*!< 0x00800000 */
34919 #define SAES_CR_KMOD_Pos                     (24U)
34920 #define SAES_CR_KMOD_Msk                     (0x3UL << SAES_CR_KMOD_Pos)              /*!< 0x03000000 */
34921 #define SAES_CR_KMOD                         SAES_CR_KMOD_Msk                         /*!< Key mode selection */
34922 #define SAES_CR_KMOD_0                       (0x1UL << SAES_CR_KMOD_Pos)              /*!< 0x01000000 */
34923 #define SAES_CR_KMOD_1                       (0x2UL << SAES_CR_KMOD_Pos)              /*!< 0x02000000 */
34924 #define SAES_CR_KSHAREID_Pos                 (26U)
34925 #define SAES_CR_KSHAREID_Msk                 (0x3UL << SAES_CR_KSHAREID_Pos)          /*!< 0x0C000000 */
34926 #define SAES_CR_KSHAREID                     SAES_CR_KSHAREID_Msk                     /*!< Key Shared ID */
34927 #define SAES_CR_KSHAREID_0                   (0x1UL << SAES_CR_KSHAREID_Pos)          /*!< 0x04000000 */
34928 #define SAES_CR_KSHAREID_1                   (0x2UL << SAES_CR_KSHAREID_Pos)          /*!< 0x08000000 */
34929 #define SAES_CR_KEYSEL_Pos                   (28U)
34930 #define SAES_CR_KEYSEL_Msk                   (0x7UL << SAES_CR_KEYSEL_Pos)            /*!< 0x70000000 */
34931 #define SAES_CR_KEYSEL                       SAES_CR_KEYSEL_Msk                       /*!< Key Selection */
34932 #define SAES_CR_KEYSEL_0                     (0x1UL << SAES_CR_KEYSEL_Pos)            /*!< 0x10000000 */
34933 #define SAES_CR_KEYSEL_1                     (0x2UL << SAES_CR_KEYSEL_Pos)            /*!< 0x20000000 */
34934 #define SAES_CR_KEYSEL_2                     (0x4UL << SAES_CR_KEYSEL_Pos)            /*!< 0x40000000 */
34935 #define SAES_CR_IPRST_Pos                    (31U)
34936 #define SAES_CR_IPRST_Msk                    (0x1UL << SAES_CR_IPRST_Pos)             /*!< 0x80000000 */
34937 #define SAES_CR_IPRST                        SAES_CR_IPRST_Msk                        /*!< SAES IP software reset */
34938 
34939 /*******************  Bits definition for SAES_SR register  *********************/
34940 #define SAES_SR_CCF_Pos                      (0U)
34941 #define SAES_SR_CCF_Msk                      (0x1UL << SAES_SR_CCF_Pos)               /*!< 0x00000001 */
34942 #define SAES_SR_CCF                          SAES_SR_CCF_Msk                          /*!< Computation Complete Flag */
34943 #define SAES_SR_RDERR_Pos                    (1U)
34944 #define SAES_SR_RDERR_Msk                    (0x1UL << SAES_SR_RDERR_Pos)             /*!< 0x00000002 */
34945 #define SAES_SR_RDERR                        SAES_SR_RDERR_Msk                        /*!< Read Error Flag */
34946 #define SAES_SR_WRERR_Pos                    (2U)
34947 #define SAES_SR_WRERR_Msk                    (0x1UL << SAES_SR_WRERR_Pos)             /*!< 0x00000004 */
34948 #define SAES_SR_WRERR                        SAES_SR_WRERR_Msk                        /*!< Write Error Flag */
34949 #define SAES_SR_BUSY_Pos                     (3U)
34950 #define SAES_SR_BUSY_Msk                     (0x1UL << SAES_SR_BUSY_Pos)              /*!< 0x00000008 */
34951 #define SAES_SR_BUSY                         SAES_SR_BUSY_Msk                         /*!< Busy Flag */
34952 #define SAES_SR_KEYVALID_Pos                 (7U)
34953 #define SAES_SR_KEYVALID_Msk                 (0x1UL << SAES_SR_KEYVALID_Pos)          /*!< 0x00000080 */
34954 #define SAES_SR_KEYVALID                     SAES_SR_KEYVALID_Msk                     /*!< Key valid Flag */
34955 
34956 /*******************  Bits definition for SAES_DINR register  *******************/
34957 #define SAES_DINR_Pos                        (0U)
34958 #define SAES_DINR_Msk                        (0xFFFFFFFFUL << SAES_DINR_Pos)          /*!< 0xFFFFFFFF */
34959 #define SAES_DINR                            SAES_DINR_Msk                            /*!< SAES Data Input Register */
34960 
34961 /*******************  Bits definition for SAES_DOUTR register  ******************/
34962 #define SAES_DOUTR_Pos                       (0U)
34963 #define SAES_DOUTR_Msk                       (0xFFFFFFFFUL << SAES_DOUTR_Pos)         /*!< 0xFFFFFFFF */
34964 #define SAES_DOUTR                           SAES_DOUTR_Msk                           /*!< SAES Data Output Register */
34965 
34966 /*******************  Bits definition for SAES_KEYR0 register  ******************/
34967 #define SAES_KEYR0_Pos                       (0U)
34968 #define SAES_KEYR0_Msk                       (0xFFFFFFFFUL << SAES_KEYR0_Pos)         /*!< 0xFFFFFFFF */
34969 #define SAES_KEYR0                           SAES_KEYR0_Msk                           /*!< SAES cryptographic key, bits [31:0] */
34970 
34971 /*******************  Bits definition for SAES_KEYR1 register  ******************/
34972 #define SAES_KEYR1_Pos                       (0U)
34973 #define SAES_KEYR1_Msk                       (0xFFFFFFFFUL << SAES_KEYR1_Pos)         /*!< 0xFFFFFFFF */
34974 #define SAES_KEYR1                           SAES_KEYR1_Msk                           /*!< SAES cryptographic key, bits [63:32] */
34975 
34976 /*******************  Bits definition for SAES_KEYR2 register  ******************/
34977 #define SAES_KEYR2_Pos                       (0U)
34978 #define SAES_KEYR2_Msk                       (0xFFFFFFFFUL << SAES_KEYR2_Pos)         /*!< 0xFFFFFFFF */
34979 #define SAES_KEYR2                           SAES_KEYR2_Msk                           /*!< SAES cryptographic key, bits [95:64] */
34980 
34981 /*******************  Bits definition for SAES_KEYR3 register  ******************/
34982 #define SAES_KEYR3_Pos                       (0U)
34983 #define SAES_KEYR3_Msk                       (0xFFFFFFFFUL << SAES_KEYR3_Pos)         /*!< 0xFFFFFFFF */
34984 #define SAES_KEYR3                           SAES_KEYR3_Msk                           /*!< SAES cryptographic key, bits [127:96] */
34985 
34986 /*******************  Bits definition for SAES_KEYR4 register  ******************/
34987 #define SAES_KEYR4_Pos                       (0U)
34988 #define SAES_KEYR4_Msk                       (0xFFFFFFFFUL << SAES_KEYR4_Pos)         /*!< 0xFFFFFFFF */
34989 #define SAES_KEYR4                           SAES_KEYR4_Msk                           /*!< SAES cryptographic key, bits [127:96] */
34990 
34991 /*******************  Bits definition for SAES_KEYR5 register  ******************/
34992 #define SAES_KEYR5_Pos                       (0U)
34993 #define SAES_KEYR5_Msk                       (0xFFFFFFFFUL << SAES_KEYR5_Pos)         /*!< 0xFFFFFFFF */
34994 #define SAES_KEYR5                           SAES_KEYR5_Msk                           /*!< SAES cryptographic key, bits [127:96] */
34995 
34996 /*******************  Bits definition for SAES_KEYR6 register  ******************/
34997 #define SAES_KEYR6_Pos                       (0U)
34998 #define SAES_KEYR6_Msk                       (0xFFFFFFFFUL << SAES_KEYR6_Pos)         /*!< 0xFFFFFFFF */
34999 #define SAES_KEYR6                           SAES_KEYR6_Msk                           /*!< SAES cryptographic key, bits [127:96] */
35000 
35001 /*******************  Bits definition for SAES_KEYR7 register  ******************/
35002 #define SAES_KEYR7_Pos                       (0U)
35003 #define SAES_KEYR7_Msk                       (0xFFFFFFFFUL << SAES_KEYR7_Pos)         /*!< 0xFFFFFFFF */
35004 #define SAES_KEYR7                           SAES_KEYR7_Msk                           /*!< SAES cryptographic key, bits [127:96] */
35005 
35006 /*******************  Bits definition for SAES_IVR0 register   ******************/
35007 #define SAES_IVR0_Pos                        (0U)
35008 #define SAES_IVR0_Msk                        (0xFFFFFFFFUL << SAES_IVR0_Pos)          /*!< 0xFFFFFFFF */
35009 #define SAES_IVR0                            SAES_IVR0_Msk                            /*!< SAES initialization vector input, bits [31:0] */
35010 
35011 /*******************  Bits definition for SAES_IVR1 register   ******************/
35012 #define SAES_IVR1_Pos                        (0U)
35013 #define SAES_IVR1_Msk                        (0xFFFFFFFFUL << SAES_IVR1_Pos)          /*!< 0xFFFFFFFF */
35014 #define SAES_IVR1                            SAES_IVR1_Msk                            /*!< SAES initialization vector input, bits [63:32] */
35015 
35016 /*******************  Bits definition for SAES_IVR2 register   ******************/
35017 #define SAES_IVR2_Pos                        (0U)
35018 #define SAES_IVR2_Msk                        (0xFFFFFFFFUL << SAES_IVR2_Pos)          /*!< 0xFFFFFFFF */
35019 #define SAES_IVR2                            SAES_IVR2_Msk                            /*!< SAES initialization vector input, bits [95:64] */
35020 
35021 /*******************  Bits definition for SAES_IVR3 register   ******************/
35022 #define SAES_IVR3_Pos                        (0U)
35023 #define SAES_IVR3_Msk                        (0xFFFFFFFFUL << SAES_IVR3_Pos)          /*!< 0xFFFFFFFF */
35024 #define SAES_IVR3                            SAES_IVR3_Msk                            /*!< SAES initialization vector input, bits [127:96] */
35025 
35026 /*******************  Bits definition for SAES_DPACFGR register     ******************/
35027 #define SAES_DPACFGR_REDCFG_Pos              (0U)
35028 #define SAES_DPACFGR_REDCFG_Msk              (0x3UL << SAES_DPACFGR_REDCFG_Pos)       /*!< 0x00000003 */
35029 #define SAES_DPACFGR_REDCFG                  SAES_DPACFGR_REDCFG_Msk                  /*!< Redundancy configuration*/
35030 #define SAES_DPACFGR_REDCFG_0                (0x1UL << SAES_DPACFGR_REDCFG_Pos)       /*!< 0x00000001 */
35031 #define SAES_DPACFGR_REDCFG_1                (0x2UL << SAES_DPACFGR_REDCFG_Pos)       /*!< 0x00000002 */
35032 #define SAES_DPACFGR_RESEED_Pos              (2U)
35033 #define SAES_DPACFGR_RESEED_Msk              (0x1UL << SAES_DPACFGR_RESEED_Pos)       /*!< 0x00000004 */
35034 #define SAES_DPACFGR_RESEED                  SAES_DPACFGR_RESEED_Msk                  /*!< Automatic reseed enable */
35035 #define SAES_DPACFGR_TRIMCFG_Pos             (3U)
35036 #define SAES_DPACFGR_TRIMCFG_Msk             (0x3UL << SAES_DPACFGR_TRIMCFG_Pos)      /*!< 0x00000018 */
35037 #define SAES_DPACFGR_TRIMCFG                 SAES_DPACFGR_TRIMCFG_Msk                 /*!< Clock trimming */
35038 #define SAES_DPACFGR_TRIMCFG_0               (0x1UL << SAES_DPACFGR_TRIMCFG_Pos)      /*!< 0x00000008 */
35039 #define SAES_DPACFGR_TRIMCFG_1               (0x2UL << SAES_DPACFGR_TRIMCFG_Pos)      /*!< 0x00000010 */
35040 #define SAES_DPACFGR_CONFIGLOCK_Pos          (31U)
35041 #define SAES_DPACFGR_CONFIGLOCK_Msk          (0x1UL << SAES_DPACFGR_CONFIGLOCK_Pos)   /*!< 0x80000000 */
35042 #define SAES_DPACFGR_CONFIGLOCK               SAES_DPACFGR_CONFIGLOCK_Msk             /*!< DPA configuration lock */
35043 
35044 /*******************  Bits definition for SAES_IER register     ******************/
35045 #define SAES_IER_CCFIE_Pos                   (0U)
35046 #define SAES_IER_CCFIE_Msk                   (0x1UL << SAES_IER_CCFIE_Pos)            /*!< 0x00000001 */
35047 #define SAES_IER_CCFIE                       SAES_IER_CCFIE_Msk                       /*!< Computation complete flag interrupt enable */
35048 #define SAES_IER_RWEIE_Pos                   (1U)
35049 #define SAES_IER_RWEIE_Msk                   (0x1UL << SAES_IER_RWEIE_Pos)            /*!< 0x00000002 */
35050 #define SAES_IER_RWEIE                       SAES_IER_RWEIE_Msk                       /*!< Read or write error Interrupt Enable */
35051 #define SAES_IER_KEIE_Pos                    (2U)
35052 #define SAES_IER_KEIE_Msk                    (0x1UL << SAES_IER_KEIE_Pos)             /*!< 0x00000004 */
35053 #define SAES_IER_KEIE                        SAES_IER_KEIE_Msk                        /*!< Key error interrupt enable */
35054 #define SAES_IER_RNGEIE_Pos                  (3U)
35055 #define SAES_IER_RNGEIE_Msk                  (0x1UL << SAES_IER_RNGEIE_Pos)           /*!< 0x00000008 */
35056 #define SAES_IER_RNGEIE                      SAES_IER_RNGEIE_Msk                      /*!< RNG error interrupt enable */
35057 
35058 /*******************  Bits definition for SAES_ISR register     ******************/
35059 #define SAES_ISR_CCF_Pos                     (0U)
35060 #define SAES_ISR_CCF_Msk                     (0x1UL << SAES_ISR_CCF_Pos)              /*!< 0x00000001 */
35061 #define SAES_ISR_CCF                         SAES_ISR_CCF_Msk                         /*!< Computation complete flag */
35062 #define SAES_ISR_RWEIF_Pos                   (1U)
35063 #define SAES_ISR_RWEIF_Msk                   (0x1UL << SAES_ISR_RWEIF_Pos)            /*!< 0x00000002 */
35064 #define SAES_ISR_RWEIF                       SAES_ISR_RWEIF_Msk                       /*!< Read or write error Interrupt flag */
35065 #define SAES_ISR_KEIF_Pos                    (2U)
35066 #define SAES_ISR_KEIF_Msk                    (0x1UL << SAES_ISR_KEIF_Pos)             /*!< 0x00000004 */
35067 #define SAES_ISR_KEIF                        SAES_ISR_KEIF_Msk                        /*!< Key error interrupt flag */
35068 #define SAES_ISR_RNGEIF_Pos                  (3U)
35069 #define SAES_ISR_RNGEIF_Msk                  (0x1UL << SAES_ISR_RNGEIF_Pos)           /*!< 0x00000008 */
35070 #define SAES_ISR_RNGEIF                      SAES_ISR_RNGEIF_Msk                      /*!< RNG error interrupt flag */
35071 
35072 /*******************  Bits definition for SAES_ICR register     ******************/
35073 #define SAES_ICR_CCF_Pos                     (0U)
35074 #define SAES_ICR_CCF_Msk                     (0x1UL << SAES_ICR_CCF_Pos)              /*!< 0x00000001 */
35075 #define SAES_ICR_CCF                         SAES_ICR_CCF_Msk                         /*!< Computation complete flag clear */
35076 #define SAES_ICR_RWEIF_Pos                   (1U)
35077 #define SAES_ICR_RWEIF_Msk                   (0x1UL << SAES_ICR_RWEIF_Pos)            /*!< 0x00000002 */
35078 #define SAES_ICR_RWEIF                       SAES_ICR_RWEIF_Msk                       /*!< Read or write error Interrupt flag clear */
35079 #define SAES_ICR_KEIF_Pos                    (2U)
35080 #define SAES_ICR_KEIF_Msk                    (0x1UL << SAES_ICR_KEIF_Pos)             /*!< 0x00000004 */
35081 #define SAES_ICR_KEIF                        SAES_ICR_KEIF_Msk                        /*!< Key error interrupt flag clear */
35082 #define SAES_ICR_RNGEIF_Pos                  (3U)
35083 #define SAES_ICR_RNGEIF_Msk                  (0x1UL << SAES_ICR_RNGEIF_Pos)           /*!< 0x00000008 */
35084 #define SAES_ICR_RNGEIF                      SAES_ICR_RNGEIF_Msk                      /*!< RNG error interrupt flag clear */
35085 
35086 
35087 /******************************************************************************/
35088 /*                                                                            */
35089 /*                          Serial Audio Interface                            */
35090 /*                                                                            */
35091 /******************************************************************************/
35092 /********************  Bit definition for SAI_GCR register  *******************/
35093 #define SAI_GCR_SYNCIN_Pos                  (0U)
35094 #define SAI_GCR_SYNCIN_Msk                  (0x3UL << SAI_GCR_SYNCIN_Pos)           /*!< 0x00000003 */
35095 #define SAI_GCR_SYNCIN                      SAI_GCR_SYNCIN_Msk                      /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
35096 #define SAI_GCR_SYNCIN_0                    (0x1UL << SAI_GCR_SYNCIN_Pos)           /*!< 0x00000001 */
35097 #define SAI_GCR_SYNCIN_1                    (0x2UL << SAI_GCR_SYNCIN_Pos)           /*!< 0x00000002 */
35098 #define SAI_GCR_SYNCOUT_Pos                 (4U)
35099 #define SAI_GCR_SYNCOUT_Msk                 (0x3UL << SAI_GCR_SYNCOUT_Pos)          /*!< 0x00000030 */
35100 #define SAI_GCR_SYNCOUT                     SAI_GCR_SYNCOUT_Msk                     /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
35101 #define SAI_GCR_SYNCOUT_0                   (0x1UL << SAI_GCR_SYNCOUT_Pos)          /*!< 0x00000010 */
35102 #define SAI_GCR_SYNCOUT_1                   (0x2UL << SAI_GCR_SYNCOUT_Pos)          /*!< 0x00000020 */
35103 
35104 /*******************  Bit definition for SAI_xCR1 register  *******************/
35105 #define SAI_xCR1_MODE_Pos                   (0U)
35106 #define SAI_xCR1_MODE_Msk                   (0x3UL << SAI_xCR1_MODE_Pos)            /*!< 0x00000003 */
35107 #define SAI_xCR1_MODE                       SAI_xCR1_MODE_Msk                       /*!<MODE[1:0] bits (Audio Block Mode)           */
35108 #define SAI_xCR1_MODE_0                     (0x1UL << SAI_xCR1_MODE_Pos)            /*!< 0x00000001 */
35109 #define SAI_xCR1_MODE_1                     (0x2UL << SAI_xCR1_MODE_Pos)            /*!< 0x00000002 */
35110 #define SAI_xCR1_PRTCFG_Pos                 (2U)
35111 #define SAI_xCR1_PRTCFG_Msk                 (0x3UL << SAI_xCR1_PRTCFG_Pos)          /*!< 0x0000000C */
35112 #define SAI_xCR1_PRTCFG                     SAI_xCR1_PRTCFG_Msk                     /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
35113 #define SAI_xCR1_PRTCFG_0                   (0x1UL << SAI_xCR1_PRTCFG_Pos)          /*!< 0x00000004 */
35114 #define SAI_xCR1_PRTCFG_1                   (0x2UL << SAI_xCR1_PRTCFG_Pos)          /*!< 0x00000008 */
35115 #define SAI_xCR1_DS_Pos                     (5U)
35116 #define SAI_xCR1_DS_Msk                     (0x7UL << SAI_xCR1_DS_Pos)              /*!< 0x000000E0 */
35117 #define SAI_xCR1_DS                         SAI_xCR1_DS_Msk                         /*!<DS[1:0] bits (Data Size) */
35118 #define SAI_xCR1_DS_0                       (0x1UL << SAI_xCR1_DS_Pos)              /*!< 0x00000020 */
35119 #define SAI_xCR1_DS_1                       (0x2UL << SAI_xCR1_DS_Pos)              /*!< 0x00000040 */
35120 #define SAI_xCR1_DS_2                       (0x4UL << SAI_xCR1_DS_Pos)              /*!< 0x00000080 */
35121 #define SAI_xCR1_LSBFIRST_Pos               (8U)
35122 #define SAI_xCR1_LSBFIRST_Msk               (0x1UL << SAI_xCR1_LSBFIRST_Pos)        /*!< 0x00000100 */
35123 #define SAI_xCR1_LSBFIRST                   SAI_xCR1_LSBFIRST_Msk                   /*!<LSB First Configuration  */
35124 #define SAI_xCR1_CKSTR_Pos                  (9U)
35125 #define SAI_xCR1_CKSTR_Msk                  (0x1UL << SAI_xCR1_CKSTR_Pos)           /*!< 0x00000200 */
35126 #define SAI_xCR1_CKSTR                      SAI_xCR1_CKSTR_Msk                      /*!<ClocK STRobing edge      */
35127 #define SAI_xCR1_SYNCEN_Pos                 (10U)
35128 #define SAI_xCR1_SYNCEN_Msk                 (0x3UL << SAI_xCR1_SYNCEN_Pos)          /*!< 0x00000C00 */
35129 #define SAI_xCR1_SYNCEN                     SAI_xCR1_SYNCEN_Msk                     /*!<SYNCEN[1:0](SYNChronization ENable) */
35130 #define SAI_xCR1_SYNCEN_0                   (0x1UL << SAI_xCR1_SYNCEN_Pos)          /*!< 0x00000400 */
35131 #define SAI_xCR1_SYNCEN_1                   (0x2UL << SAI_xCR1_SYNCEN_Pos)          /*!< 0x00000800 */
35132 #define SAI_xCR1_MONO_Pos                   (12U)
35133 #define SAI_xCR1_MONO_Msk                   (0x1UL << SAI_xCR1_MONO_Pos)            /*!< 0x00001000 */
35134 #define SAI_xCR1_MONO                       SAI_xCR1_MONO_Msk                       /*!<Mono mode                  */
35135 #define SAI_xCR1_OUTDRIV_Pos                (13U)
35136 #define SAI_xCR1_OUTDRIV_Msk                (0x1UL << SAI_xCR1_OUTDRIV_Pos)         /*!< 0x00002000 */
35137 #define SAI_xCR1_OUTDRIV                    SAI_xCR1_OUTDRIV_Msk                    /*!<Output Drive               */
35138 #define SAI_xCR1_SAIEN_Pos                  (16U)
35139 #define SAI_xCR1_SAIEN_Msk                  (0x1UL << SAI_xCR1_SAIEN_Pos)           /*!< 0x00010000 */
35140 #define SAI_xCR1_SAIEN                      SAI_xCR1_SAIEN_Msk                      /*!<Audio Block enable         */
35141 #define SAI_xCR1_DMAEN_Pos                  (17U)
35142 #define SAI_xCR1_DMAEN_Msk                  (0x1UL << SAI_xCR1_DMAEN_Pos)           /*!< 0x00020000 */
35143 #define SAI_xCR1_DMAEN                      SAI_xCR1_DMAEN_Msk                      /*!<DMA enable                 */
35144 #define SAI_xCR1_NODIV_Pos                  (19U)
35145 #define SAI_xCR1_NODIV_Msk                  (0x1UL << SAI_xCR1_NODIV_Pos)           /*!< 0x00080000 */
35146 #define SAI_xCR1_NODIV                      SAI_xCR1_NODIV_Msk                      /*!<No Divider Configuration   */
35147 #define SAI_xCR1_MCKDIV_Pos                 (20U)
35148 #define SAI_xCR1_MCKDIV_Msk                 (0x3FUL << SAI_xCR1_MCKDIV_Pos)         /*!< 0x03F00000 */
35149 #define SAI_xCR1_MCKDIV                     SAI_xCR1_MCKDIV_Msk                     /*!<MCKDIV[5:0] (Master ClocK Divider)  */
35150 #define SAI_xCR1_MCKDIV_0                   (0x00100000UL)                          /*!<Bit 0  */
35151 #define SAI_xCR1_MCKDIV_1                   (0x00200000UL)                          /*!<Bit 1  */
35152 #define SAI_xCR1_MCKDIV_2                   (0x00400000UL)                          /*!<Bit 2  */
35153 #define SAI_xCR1_MCKDIV_3                   (0x00800000UL)                          /*!<Bit 3  */
35154 #define SAI_xCR1_MCKDIV_4                   (0x01000000UL)                          /*!<Bit 4  */
35155 #define SAI_xCR1_MCKDIV_5                   (0x02000000UL)                          /*!<Bit 5  */
35156 #define SAI_xCR1_OSR_Pos                    (26U)
35157 #define SAI_xCR1_OSR_Msk                    (0x1UL << SAI_xCR1_OSR_Pos)             /*!< 0x04000000 */
35158 #define SAI_xCR1_OSR                        SAI_xCR1_OSR_Msk                        /*!<Oversampling ratio for master clock */
35159 #define SAI_xCR1_MCKEN_Pos                  (27U)
35160 #define SAI_xCR1_MCKEN_Msk                  (0x1UL << SAI_xCR1_MCKEN_Pos)           /*!< 0x08000000 */
35161 #define SAI_xCR1_MCKEN                      SAI_xCR1_MCKEN_Msk                      /*!<Master clock generation enable */
35162 
35163 /*******************  Bit definition for SAI_xCR2 register  *******************/
35164 #define SAI_xCR2_FTH_Pos                    (0U)
35165 #define SAI_xCR2_FTH_Msk                    (0x7UL << SAI_xCR2_FTH_Pos)             /*!< 0x00000007 */
35166 #define SAI_xCR2_FTH                        SAI_xCR2_FTH_Msk                        /*!<FTH[2:0](Fifo THreshold)  */
35167 #define SAI_xCR2_FTH_0                      (0x1UL << SAI_xCR2_FTH_Pos)             /*!< 0x00000001 */
35168 #define SAI_xCR2_FTH_1                      (0x2UL << SAI_xCR2_FTH_Pos)             /*!< 0x00000002 */
35169 #define SAI_xCR2_FTH_2                      (0x4UL << SAI_xCR2_FTH_Pos)             /*!< 0x00000004 */
35170 #define SAI_xCR2_FFLUSH_Pos                 (3U)
35171 #define SAI_xCR2_FFLUSH_Msk                 (0x1UL << SAI_xCR2_FFLUSH_Pos)          /*!< 0x00000008 */
35172 #define SAI_xCR2_FFLUSH                     SAI_xCR2_FFLUSH_Msk                     /*!<Fifo FLUSH                       */
35173 #define SAI_xCR2_TRIS_Pos                   (4U)
35174 #define SAI_xCR2_TRIS_Msk                   (0x1UL << SAI_xCR2_TRIS_Pos)            /*!< 0x00000010 */
35175 #define SAI_xCR2_TRIS                       SAI_xCR2_TRIS_Msk                       /*!<TRIState Management on data line */
35176 #define SAI_xCR2_MUTE_Pos                   (5U)
35177 #define SAI_xCR2_MUTE_Msk                   (0x1UL << SAI_xCR2_MUTE_Pos)            /*!< 0x00000020 */
35178 #define SAI_xCR2_MUTE                       SAI_xCR2_MUTE_Msk                       /*!<Mute mode                        */
35179 #define SAI_xCR2_MUTEVAL_Pos                (6U)
35180 #define SAI_xCR2_MUTEVAL_Msk                (0x1UL << SAI_xCR2_MUTEVAL_Pos)         /*!< 0x00000040 */
35181 #define SAI_xCR2_MUTEVAL                    SAI_xCR2_MUTEVAL_Msk                    /*!<Muate value                      */
35182 #define SAI_xCR2_MUTECNT_Pos                (7U)
35183 #define SAI_xCR2_MUTECNT_Msk                (0x3FUL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00001F80 */
35184 #define SAI_xCR2_MUTECNT                    SAI_xCR2_MUTECNT_Msk                    /*!<MUTECNT[5:0] (MUTE counter) */
35185 #define SAI_xCR2_MUTECNT_0                  (0x01UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000080 */
35186 #define SAI_xCR2_MUTECNT_1                  (0x02UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000100 */
35187 #define SAI_xCR2_MUTECNT_2                  (0x04UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000200 */
35188 #define SAI_xCR2_MUTECNT_3                  (0x08UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000400 */
35189 #define SAI_xCR2_MUTECNT_4                  (0x10UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000800 */
35190 #define SAI_xCR2_MUTECNT_5                  (0x20UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00001000 */
35191 #define SAI_xCR2_CPL_Pos                    (13U)
35192 #define SAI_xCR2_CPL_Msk                    (0x1UL << SAI_xCR2_CPL_Pos)             /*!< 0x00002000 */
35193 #define SAI_xCR2_CPL                        SAI_xCR2_CPL_Msk                        /*!<CPL mode                    */
35194 #define SAI_xCR2_COMP_Pos                   (14U)
35195 #define SAI_xCR2_COMP_Msk                   (0x3UL << SAI_xCR2_COMP_Pos)            /*!< 0x0000C000 */
35196 #define SAI_xCR2_COMP                       SAI_xCR2_COMP_Msk                       /*!<COMP[1:0] (Companding mode) */
35197 #define SAI_xCR2_COMP_0                     (0x1UL << SAI_xCR2_COMP_Pos)            /*!< 0x00004000 */
35198 #define SAI_xCR2_COMP_1                     (0x2UL << SAI_xCR2_COMP_Pos)            /*!< 0x00008000 */
35199 
35200 /******************  Bit definition for SAI_xFRCR register  *******************/
35201 #define SAI_xFRCR_FRL_Pos                   (0U)
35202 #define SAI_xFRCR_FRL_Msk                   (0xFFUL << SAI_xFRCR_FRL_Pos)           /*!< 0x000000FF */
35203 #define SAI_xFRCR_FRL                       SAI_xFRCR_FRL_Msk                       /*!<FRL[7:0](Frame length)  */
35204 #define SAI_xFRCR_FRL_0                     (0x01UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000001 */
35205 #define SAI_xFRCR_FRL_1                     (0x02UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000002 */
35206 #define SAI_xFRCR_FRL_2                     (0x04UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000004 */
35207 #define SAI_xFRCR_FRL_3                     (0x08UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000008 */
35208 #define SAI_xFRCR_FRL_4                     (0x10UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000010 */
35209 #define SAI_xFRCR_FRL_5                     (0x20UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000020 */
35210 #define SAI_xFRCR_FRL_6                     (0x40UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000040 */
35211 #define SAI_xFRCR_FRL_7                     (0x80UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000080 */
35212 #define SAI_xFRCR_FSALL_Pos                 (8U)
35213 #define SAI_xFRCR_FSALL_Msk                 (0x7FUL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00007F00 */
35214 #define SAI_xFRCR_FSALL                     SAI_xFRCR_FSALL_Msk                     /*!<FRL[6:0] (Frame synchronization active level length)  */
35215 #define SAI_xFRCR_FSALL_0                   (0x01UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00000100 */
35216 #define SAI_xFRCR_FSALL_1                   (0x02UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00000200 */
35217 #define SAI_xFRCR_FSALL_2                   (0x04UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00000400 */
35218 #define SAI_xFRCR_FSALL_3                   (0x08UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00000800 */
35219 #define SAI_xFRCR_FSALL_4                   (0x10UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00001000 */
35220 #define SAI_xFRCR_FSALL_5                   (0x20UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00002000 */
35221 #define SAI_xFRCR_FSALL_6                   (0x40UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00004000 */
35222 #define SAI_xFRCR_FSDEF_Pos                 (16U)
35223 #define SAI_xFRCR_FSDEF_Msk                 (0x1UL << SAI_xFRCR_FSDEF_Pos)          /*!< 0x00010000 */
35224 #define SAI_xFRCR_FSDEF                     SAI_xFRCR_FSDEF_Msk                     /*!< Frame Synchronization Definition */
35225 #define SAI_xFRCR_FSPOL_Pos                 (17U)
35226 #define SAI_xFRCR_FSPOL_Msk                 (0x1UL << SAI_xFRCR_FSPOL_Pos)          /*!< 0x00020000 */
35227 #define SAI_xFRCR_FSPOL                     SAI_xFRCR_FSPOL_Msk                     /*!<Frame Synchronization POLarity    */
35228 #define SAI_xFRCR_FSOFF_Pos                 (18U)
35229 #define SAI_xFRCR_FSOFF_Msk                 (0x1UL << SAI_xFRCR_FSOFF_Pos)          /*!< 0x00040000 */
35230 #define SAI_xFRCR_FSOFF                     SAI_xFRCR_FSOFF_Msk                     /*!<Frame Synchronization OFFset      */
35231 
35232 /******************  Bit definition for SAI_xSLOTR register  *******************/
35233 #define SAI_xSLOTR_FBOFF_Pos                (0U)
35234 #define SAI_xSLOTR_FBOFF_Msk                (0x1FUL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x0000001F */
35235 #define SAI_xSLOTR_FBOFF                    SAI_xSLOTR_FBOFF_Msk                    /*!<FRL[4:0](First Bit Offset)  */
35236 #define SAI_xSLOTR_FBOFF_0                  (0x01UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000001 */
35237 #define SAI_xSLOTR_FBOFF_1                  (0x02UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000002 */
35238 #define SAI_xSLOTR_FBOFF_2                  (0x04UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000004 */
35239 #define SAI_xSLOTR_FBOFF_3                  (0x08UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000008 */
35240 #define SAI_xSLOTR_FBOFF_4                  (0x10UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000010 */
35241 #define SAI_xSLOTR_SLOTSZ_Pos               (6U)
35242 #define SAI_xSLOTR_SLOTSZ_Msk               (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)        /*!< 0x000000C0 */
35243 #define SAI_xSLOTR_SLOTSZ                   SAI_xSLOTR_SLOTSZ_Msk                   /*!<SLOTSZ[1:0] (Slot size)  */
35244 #define SAI_xSLOTR_SLOTSZ_0                 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)        /*!< 0x00000040 */
35245 #define SAI_xSLOTR_SLOTSZ_1                 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)        /*!< 0x00000080 */
35246 #define SAI_xSLOTR_NBSLOT_Pos               (8U)
35247 #define SAI_xSLOTR_NBSLOT_Msk               (0xFUL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000F00 */
35248 #define SAI_xSLOTR_NBSLOT                   SAI_xSLOTR_NBSLOT_Msk                   /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
35249 #define SAI_xSLOTR_NBSLOT_0                 (0x1UL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000100 */
35250 #define SAI_xSLOTR_NBSLOT_1                 (0x2UL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000200 */
35251 #define SAI_xSLOTR_NBSLOT_2                 (0x4UL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000400 */
35252 #define SAI_xSLOTR_NBSLOT_3                 (0x8UL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000800 */
35253 #define SAI_xSLOTR_SLOTEN_Pos               (16U)
35254 #define SAI_xSLOTR_SLOTEN_Msk               (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)     /*!< 0xFFFF0000 */
35255 #define SAI_xSLOTR_SLOTEN                   SAI_xSLOTR_SLOTEN_Msk                   /*!<SLOTEN[15:0] (Slot Enable)  */
35256 
35257 /*******************  Bit definition for SAI_xIMR register  *******************/
35258 #define SAI_xIMR_OVRUDRIE_Pos               (0U)
35259 #define SAI_xIMR_OVRUDRIE_Msk               (0x1UL << SAI_xIMR_OVRUDRIE_Pos)        /*!< 0x00000001 */
35260 #define SAI_xIMR_OVRUDRIE                   SAI_xIMR_OVRUDRIE_Msk                   /*!<Overrun underrun interrupt enable                              */
35261 #define SAI_xIMR_MUTEDETIE_Pos              (1U)
35262 #define SAI_xIMR_MUTEDETIE_Msk              (0x1UL << SAI_xIMR_MUTEDETIE_Pos)       /*!< 0x00000002 */
35263 #define SAI_xIMR_MUTEDETIE                  SAI_xIMR_MUTEDETIE_Msk                  /*!<Mute detection interrupt enable                                */
35264 #define SAI_xIMR_WCKCFGIE_Pos               (2U)
35265 #define SAI_xIMR_WCKCFGIE_Msk               (0x1UL << SAI_xIMR_WCKCFGIE_Pos)        /*!< 0x00000004 */
35266 #define SAI_xIMR_WCKCFGIE                   SAI_xIMR_WCKCFGIE_Msk                   /*!<Wrong Clock Configuration interrupt enable                     */
35267 #define SAI_xIMR_FREQIE_Pos                 (3U)
35268 #define SAI_xIMR_FREQIE_Msk                 (0x1UL << SAI_xIMR_FREQIE_Pos)          /*!< 0x00000008 */
35269 #define SAI_xIMR_FREQIE                     SAI_xIMR_FREQIE_Msk                     /*!<FIFO request interrupt enable                                  */
35270 #define SAI_xIMR_CNRDYIE_Pos                (4U)
35271 #define SAI_xIMR_CNRDYIE_Msk                (0x1UL << SAI_xIMR_CNRDYIE_Pos)         /*!< 0x00000010 */
35272 #define SAI_xIMR_CNRDYIE                    SAI_xIMR_CNRDYIE_Msk                    /*!<Codec not ready interrupt enable                               */
35273 #define SAI_xIMR_AFSDETIE_Pos               (5U)
35274 #define SAI_xIMR_AFSDETIE_Msk               (0x1UL << SAI_xIMR_AFSDETIE_Pos)        /*!< 0x00000020 */
35275 #define SAI_xIMR_AFSDETIE                   SAI_xIMR_AFSDETIE_Msk                   /*!<Anticipated frame synchronization detection interrupt enable   */
35276 #define SAI_xIMR_LFSDETIE_Pos               (6U)
35277 #define SAI_xIMR_LFSDETIE_Msk               (0x1UL << SAI_xIMR_LFSDETIE_Pos)        /*!< 0x00000040 */
35278 #define SAI_xIMR_LFSDETIE                   SAI_xIMR_LFSDETIE_Msk                   /*!<Late frame synchronization detection interrupt enable          */
35279 
35280 /********************  Bit definition for SAI_xSR register  *******************/
35281 #define SAI_xSR_OVRUDR_Pos                  (0U)
35282 #define SAI_xSR_OVRUDR_Msk                  (0x1UL << SAI_xSR_OVRUDR_Pos)           /*!< 0x00000001 */
35283 #define SAI_xSR_OVRUDR                      SAI_xSR_OVRUDR_Msk                      /*!<Overrun underrun                               */
35284 #define SAI_xSR_MUTEDET_Pos                 (1U)
35285 #define SAI_xSR_MUTEDET_Msk                 (0x1UL << SAI_xSR_MUTEDET_Pos)          /*!< 0x00000002 */
35286 #define SAI_xSR_MUTEDET                     SAI_xSR_MUTEDET_Msk                     /*!<Mute detection                                 */
35287 #define SAI_xSR_WCKCFG_Pos                  (2U)
35288 #define SAI_xSR_WCKCFG_Msk                  (0x1UL << SAI_xSR_WCKCFG_Pos)           /*!< 0x00000004 */
35289 #define SAI_xSR_WCKCFG                      SAI_xSR_WCKCFG_Msk                      /*!<Wrong Clock Configuration                      */
35290 #define SAI_xSR_FREQ_Pos                    (3U)
35291 #define SAI_xSR_FREQ_Msk                    (0x1UL << SAI_xSR_FREQ_Pos)             /*!< 0x00000008 */
35292 #define SAI_xSR_FREQ                        SAI_xSR_FREQ_Msk                        /*!<FIFO request                                   */
35293 #define SAI_xSR_CNRDY_Pos                   (4U)
35294 #define SAI_xSR_CNRDY_Msk                   (0x1UL << SAI_xSR_CNRDY_Pos)            /*!< 0x00000010 */
35295 #define SAI_xSR_CNRDY                       SAI_xSR_CNRDY_Msk                       /*!<Codec not ready                                */
35296 #define SAI_xSR_AFSDET_Pos                  (5U)
35297 #define SAI_xSR_AFSDET_Msk                  (0x1UL << SAI_xSR_AFSDET_Pos)           /*!< 0x00000020 */
35298 #define SAI_xSR_AFSDET                      SAI_xSR_AFSDET_Msk                      /*!<Anticipated frame synchronization detection    */
35299 #define SAI_xSR_LFSDET_Pos                  (6U)
35300 #define SAI_xSR_LFSDET_Msk                  (0x1UL << SAI_xSR_LFSDET_Pos)           /*!< 0x00000040 */
35301 #define SAI_xSR_LFSDET                      SAI_xSR_LFSDET_Msk                      /*!<Late frame synchronization detection           */
35302 #define SAI_xSR_FLVL_Pos                    (16U)
35303 #define SAI_xSR_FLVL_Msk                    (0x7UL << SAI_xSR_FLVL_Pos)             /*!< 0x00070000 */
35304 #define SAI_xSR_FLVL                        SAI_xSR_FLVL_Msk                        /*!<FLVL[2:0] (FIFO Level Threshold)               */
35305 #define SAI_xSR_FLVL_0                      (0x1UL << SAI_xSR_FLVL_Pos)             /*!< 0x00010000 */
35306 #define SAI_xSR_FLVL_1                      (0x2UL << SAI_xSR_FLVL_Pos)             /*!< 0x00020000 */
35307 #define SAI_xSR_FLVL_2                      (0x4UL << SAI_xSR_FLVL_Pos)             /*!< 0x00040000 */
35308 
35309 /******************  Bit definition for SAI_xCLRFR register  ******************/
35310 #define SAI_xCLRFR_COVRUDR_Pos              (0U)
35311 #define SAI_xCLRFR_COVRUDR_Msk              (0x1UL << SAI_xCLRFR_COVRUDR_Pos)       /*!< 0x00000001 */
35312 #define SAI_xCLRFR_COVRUDR                  SAI_xCLRFR_COVRUDR_Msk                  /*!<Clear Overrun underrun                               */
35313 #define SAI_xCLRFR_CMUTEDET_Pos             (1U)
35314 #define SAI_xCLRFR_CMUTEDET_Msk             (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)      /*!< 0x00000002 */
35315 #define SAI_xCLRFR_CMUTEDET                 SAI_xCLRFR_CMUTEDET_Msk                 /*!<Clear Mute detection                                 */
35316 #define SAI_xCLRFR_CWCKCFG_Pos              (2U)
35317 #define SAI_xCLRFR_CWCKCFG_Msk              (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)       /*!< 0x00000004 */
35318 #define SAI_xCLRFR_CWCKCFG                  SAI_xCLRFR_CWCKCFG_Msk                  /*!<Clear Wrong Clock Configuration                      */
35319 #define SAI_xCLRFR_CFREQ_Pos                (3U)
35320 #define SAI_xCLRFR_CFREQ_Msk                (0x1UL << SAI_xCLRFR_CFREQ_Pos)         /*!< 0x00000008 */
35321 #define SAI_xCLRFR_CFREQ                    SAI_xCLRFR_CFREQ_Msk                    /*!<Clear FIFO request                                   */
35322 #define SAI_xCLRFR_CCNRDY_Pos               (4U)
35323 #define SAI_xCLRFR_CCNRDY_Msk               (0x1UL << SAI_xCLRFR_CCNRDY_Pos)        /*!< 0x00000010 */
35324 #define SAI_xCLRFR_CCNRDY                   SAI_xCLRFR_CCNRDY_Msk                   /*!<Clear Codec not ready                                */
35325 #define SAI_xCLRFR_CAFSDET_Pos              (5U)
35326 #define SAI_xCLRFR_CAFSDET_Msk              (0x1UL << SAI_xCLRFR_CAFSDET_Pos)       /*!< 0x00000020 */
35327 #define SAI_xCLRFR_CAFSDET                  SAI_xCLRFR_CAFSDET_Msk                  /*!<Clear Anticipated frame synchronization detection    */
35328 #define SAI_xCLRFR_CLFSDET_Pos              (6U)
35329 #define SAI_xCLRFR_CLFSDET_Msk              (0x1UL << SAI_xCLRFR_CLFSDET_Pos)       /*!< 0x00000040 */
35330 #define SAI_xCLRFR_CLFSDET                  SAI_xCLRFR_CLFSDET_Msk                  /*!<Clear Late frame synchronization detection           */
35331 
35332 /******************  Bit definition for SAI_xDR register  ******************/
35333 #define SAI_xDR_DATA_Pos                    (0U)
35334 #define SAI_xDR_DATA_Msk                    (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)      /*!< 0xFFFFFFFF */
35335 #define SAI_xDR_DATA                        SAI_xDR_DATA_Msk
35336 
35337 /******************  Bit definition for SAI_PDMCR register  *******************/
35338 #define SAI_PDMCR_PDMEN_Pos                 (0U)
35339 #define SAI_PDMCR_PDMEN_Msk                 (0x1UL << SAI_PDMCR_PDMEN_Pos)          /*!< 0x00000001 */
35340 #define SAI_PDMCR_PDMEN                     SAI_PDMCR_PDMEN_Msk                     /*!<PDM enable */
35341 #define SAI_PDMCR_MICNBR_Pos                (4U)
35342 #define SAI_PDMCR_MICNBR_Msk                (0x3UL << SAI_PDMCR_MICNBR_Pos)         /*!< 0x00000030 */
35343 #define SAI_PDMCR_MICNBR                    SAI_PDMCR_MICNBR_Msk                    /*!<MICNBR[1:0] (Number of microphones) */
35344 #define SAI_PDMCR_MICNBR_0                  (0x1UL << SAI_PDMCR_MICNBR_Pos)         /*!< 0x00000010 */
35345 #define SAI_PDMCR_MICNBR_1                  (0x2UL << SAI_PDMCR_MICNBR_Pos)         /*!< 0x00000020 */
35346 #define SAI_PDMCR_CKEN1_Pos                 (8U)
35347 #define SAI_PDMCR_CKEN1_Msk                 (0x1UL << SAI_PDMCR_CKEN1_Pos)          /*!< 0x00000100 */
35348 #define SAI_PDMCR_CKEN1                     SAI_PDMCR_CKEN1_Msk                     /*!<Clock 1 enable */
35349 #define SAI_PDMCR_CKEN2_Pos                 (9U)
35350 #define SAI_PDMCR_CKEN2_Msk                 (0x1UL << SAI_PDMCR_CKEN2_Pos)          /*!< 0x00000200 */
35351 #define SAI_PDMCR_CKEN2                     SAI_PDMCR_CKEN2_Msk                     /*!<Clock 2 enable */
35352 #define SAI_PDMCR_CKEN3_Pos                 (10U)
35353 #define SAI_PDMCR_CKEN3_Msk                 (0x1UL << SAI_PDMCR_CKEN3_Pos)          /*!< 0x00000400 */
35354 #define SAI_PDMCR_CKEN3                     SAI_PDMCR_CKEN3_Msk                     /*!<Clock 3 enable */
35355 #define SAI_PDMCR_CKEN4_Pos                 (11U)
35356 #define SAI_PDMCR_CKEN4_Msk                 (0x1UL << SAI_PDMCR_CKEN4_Pos)          /*!< 0x00000800 */
35357 #define SAI_PDMCR_CKEN4                     SAI_PDMCR_CKEN4_Msk                     /*!<Clock 4 enable */
35358 
35359 /******************  Bit definition for SAI_PDMDLY register  ******************/
35360 #define SAI_PDMDLY_DLYM1L_Pos               (0U)
35361 #define SAI_PDMDLY_DLYM1L_Msk               (0x7UL << SAI_PDMDLY_DLYM1L_Pos)        /*!< 0x00000007 */
35362 #define SAI_PDMDLY_DLYM1L                   SAI_PDMDLY_DLYM1L_Msk                   /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */
35363 #define SAI_PDMDLY_DLYM1L_0                 (0x1UL << SAI_PDMDLY_DLYM1L_Pos)        /*!< 0x00000001 */
35364 #define SAI_PDMDLY_DLYM1L_1                 (0x2UL << SAI_PDMDLY_DLYM1L_Pos)        /*!< 0x00000002 */
35365 #define SAI_PDMDLY_DLYM1L_2                 (0x4UL << SAI_PDMDLY_DLYM1L_Pos)        /*!< 0x00000004 */
35366 #define SAI_PDMDLY_DLYM1R_Pos               (4U)
35367 #define SAI_PDMDLY_DLYM1R_Msk               (0x7UL << SAI_PDMDLY_DLYM1R_Pos)        /*!< 0x00000070 */
35368 #define SAI_PDMDLY_DLYM1R                   SAI_PDMDLY_DLYM1R_Msk                   /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */
35369 #define SAI_PDMDLY_DLYM1R_0                 (0x1UL << SAI_PDMDLY_DLYM1R_Pos)        /*!< 0x00000010 */
35370 #define SAI_PDMDLY_DLYM1R_1                 (0x2UL << SAI_PDMDLY_DLYM1R_Pos)        /*!< 0x00000020 */
35371 #define SAI_PDMDLY_DLYM1R_2                 (0x4UL << SAI_PDMDLY_DLYM1R_Pos)        /*!< 0x00000040 */
35372 #define SAI_PDMDLY_DLYM2L_Pos               (8U)
35373 #define SAI_PDMDLY_DLYM2L_Msk               (0x7UL << SAI_PDMDLY_DLYM2L_Pos)        /*!< 0x00000700 */
35374 #define SAI_PDMDLY_DLYM2L                   SAI_PDMDLY_DLYM2L_Msk                   /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */
35375 #define SAI_PDMDLY_DLYM2L_0                 (0x1UL << SAI_PDMDLY_DLYM2L_Pos)        /*!< 0x00000100 */
35376 #define SAI_PDMDLY_DLYM2L_1                 (0x2UL << SAI_PDMDLY_DLYM2L_Pos)        /*!< 0x00000200 */
35377 #define SAI_PDMDLY_DLYM2L_2                 (0x4UL << SAI_PDMDLY_DLYM2L_Pos)        /*!< 0x00000400 */
35378 #define SAI_PDMDLY_DLYM2R_Pos               (12U)
35379 #define SAI_PDMDLY_DLYM2R_Msk               (0x7UL << SAI_PDMDLY_DLYM2R_Pos)        /*!< 0x00007000 */
35380 #define SAI_PDMDLY_DLYM2R                   SAI_PDMDLY_DLYM2R_Msk                   /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2) */
35381 #define SAI_PDMDLY_DLYM2R_0                 (0x1UL << SAI_PDMDLY_DLYM2R_Pos)        /*!< 0x00001000 */
35382 #define SAI_PDMDLY_DLYM2R_1                 (0x2UL << SAI_PDMDLY_DLYM2R_Pos)        /*!< 0x00002000 */
35383 #define SAI_PDMDLY_DLYM2R_2                 (0x4UL << SAI_PDMDLY_DLYM2R_Pos)        /*!< 0x00004000 */
35384 #define SAI_PDMDLY_DLYM3L_Pos               (16U)
35385 #define SAI_PDMDLY_DLYM3L_Msk               (0x7UL << SAI_PDMDLY_DLYM3L_Pos)        /*!< 0x00070000 */
35386 #define SAI_PDMDLY_DLYM3L                   SAI_PDMDLY_DLYM3L_Msk                   /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3) */
35387 #define SAI_PDMDLY_DLYM3L_0                 (0x1UL << SAI_PDMDLY_DLYM3L_Pos)        /*!< 0x00010000 */
35388 #define SAI_PDMDLY_DLYM3L_1                 (0x2UL << SAI_PDMDLY_DLYM3L_Pos)        /*!< 0x00020000 */
35389 #define SAI_PDMDLY_DLYM3L_2                 (0x4UL << SAI_PDMDLY_DLYM3L_Pos)        /*!< 0x00040000 */
35390 #define SAI_PDMDLY_DLYM3R_Pos               (20U)
35391 #define SAI_PDMDLY_DLYM3R_Msk               (0x7UL << SAI_PDMDLY_DLYM3R_Pos)        /*!< 0x00700000 */
35392 #define SAI_PDMDLY_DLYM3R                   SAI_PDMDLY_DLYM3R_Msk                   /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3) */
35393 #define SAI_PDMDLY_DLYM3R_0                 (0x1UL << SAI_PDMDLY_DLYM3R_Pos)        /*!< 0x00100000 */
35394 #define SAI_PDMDLY_DLYM3R_1                 (0x2UL << SAI_PDMDLY_DLYM3R_Pos)        /*!< 0x00200000 */
35395 #define SAI_PDMDLY_DLYM3R_2                 (0x4UL << SAI_PDMDLY_DLYM3R_Pos)        /*!< 0x00400000 */
35396 #define SAI_PDMDLY_DLYM4L_Pos               (24U)
35397 #define SAI_PDMDLY_DLYM4L_Msk               (0x7UL << SAI_PDMDLY_DLYM4L_Pos)        /*!< 0x07000000 */
35398 #define SAI_PDMDLY_DLYM4L                   SAI_PDMDLY_DLYM4L_Msk                   /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4) */
35399 #define SAI_PDMDLY_DLYM4L_0                 (0x1UL << SAI_PDMDLY_DLYM4L_Pos)        /*!< 0x01000000 */
35400 #define SAI_PDMDLY_DLYM4L_1                 (0x2UL << SAI_PDMDLY_DLYM4L_Pos)        /*!< 0x02000000 */
35401 #define SAI_PDMDLY_DLYM4L_2                 (0x4UL << SAI_PDMDLY_DLYM4L_Pos)        /*!< 0x04000000 */
35402 #define SAI_PDMDLY_DLYM4R_Pos               (28U)
35403 #define SAI_PDMDLY_DLYM4R_Msk               (0x7UL << SAI_PDMDLY_DLYM4R_Pos)        /*!< 0x70000000 */
35404 #define SAI_PDMDLY_DLYM4R                   SAI_PDMDLY_DLYM4R_Msk                   /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4) */
35405 #define SAI_PDMDLY_DLYM4R_0                 (0x1UL << SAI_PDMDLY_DLYM4R_Pos)        /*!< 0x10000000 */
35406 #define SAI_PDMDLY_DLYM4R_1                 (0x2UL << SAI_PDMDLY_DLYM4R_Pos)        /*!< 0x20000000 */
35407 #define SAI_PDMDLY_DLYM4R_2                 (0x4UL << SAI_PDMDLY_DLYM4R_Pos)        /*!< 0x40000000 */
35408 
35409 
35410 /******************************************************************************/
35411 /*                                                                            */
35412 /*                           SDMMC Interface                                  */
35413 /*                                                                            */
35414 /******************************************************************************/
35415 /******************  Bit definition for SDMMC_POWER register  ******************/
35416 #define SDMMC_POWER_PWRCTRL_Pos             (0U)
35417 #define SDMMC_POWER_PWRCTRL_Msk             (0x3UL << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000003 */
35418 #define SDMMC_POWER_PWRCTRL                 SDMMC_POWER_PWRCTRL_Msk                 /*!<PWRCTRL[1:0] bits (Power supply control bits) */
35419 #define SDMMC_POWER_PWRCTRL_0               (0x1UL << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000001 */
35420 #define SDMMC_POWER_PWRCTRL_1               (0x2UL << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000002 */
35421 #define SDMMC_POWER_VSWITCH_Pos             (2U)
35422 #define SDMMC_POWER_VSWITCH_Msk             (0x1UL << SDMMC_POWER_VSWITCH_Pos)      /*!< 0x00000004 */
35423 #define SDMMC_POWER_VSWITCH                 SDMMC_POWER_VSWITCH_Msk                 /*!<Voltage switch sequence start */
35424 #define SDMMC_POWER_VSWITCHEN_Pos           (3U)
35425 #define SDMMC_POWER_VSWITCHEN_Msk           (0x1UL << SDMMC_POWER_VSWITCHEN_Pos)    /*!< 0x00000008 */
35426 #define SDMMC_POWER_VSWITCHEN               SDMMC_POWER_VSWITCHEN_Msk               /*!<Voltage switch procedure enable */
35427 #define SDMMC_POWER_DIRPOL_Pos              (4U)
35428 #define SDMMC_POWER_DIRPOL_Msk              (0x1UL << SDMMC_POWER_DIRPOL_Pos)       /*!< 0x00000010 */
35429 #define SDMMC_POWER_DIRPOL                  SDMMC_POWER_DIRPOL_Msk                  /*!<Data and Command direction signals polarity selection */
35430 
35431 /******************  Bit definition for SDMMC_CLKCR register  ******************/
35432 #define SDMMC_CLKCR_CLKDIV_Pos              (0U)
35433 #define SDMMC_CLKCR_CLKDIV_Msk              (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos)     /*!< 0x000003FF */
35434 #define SDMMC_CLKCR_CLKDIV                  SDMMC_CLKCR_CLKDIV_Msk                  /*!<Clock divide factor             */
35435 #define SDMMC_CLKCR_PWRSAV_Pos              (12U)
35436 #define SDMMC_CLKCR_PWRSAV_Msk              (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)       /*!< 0x00001000 */
35437 #define SDMMC_CLKCR_PWRSAV                  SDMMC_CLKCR_PWRSAV_Msk                  /*!<Power saving configuration bit  */
35438 #define SDMMC_CLKCR_WIDBUS_Pos              (14U)
35439 #define SDMMC_CLKCR_WIDBUS_Msk              (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x0000C000 */
35440 #define SDMMC_CLKCR_WIDBUS                  SDMMC_CLKCR_WIDBUS_Msk                  /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
35441 #define SDMMC_CLKCR_WIDBUS_0                (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x00004000 */
35442 #define SDMMC_CLKCR_WIDBUS_1                (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x00008000 */
35443 #define SDMMC_CLKCR_NEGEDGE_Pos             (16U)
35444 #define SDMMC_CLKCR_NEGEDGE_Msk             (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)      /*!< 0x00010000 */
35445 #define SDMMC_CLKCR_NEGEDGE                 SDMMC_CLKCR_NEGEDGE_Msk                 /*!<SDMMC_CK dephasing selection bit */
35446 #define SDMMC_CLKCR_HWFC_EN_Pos             (17U)
35447 #define SDMMC_CLKCR_HWFC_EN_Msk             (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)      /*!< 0x00020000 */
35448 #define SDMMC_CLKCR_HWFC_EN                 SDMMC_CLKCR_HWFC_EN_Msk                 /*!<HW Flow Control enable           */
35449 #define SDMMC_CLKCR_DDR_Pos                 (18U)
35450 #define SDMMC_CLKCR_DDR_Msk                 (0x1UL << SDMMC_CLKCR_DDR_Pos)          /*!< 0x00040000 */
35451 #define SDMMC_CLKCR_DDR                     SDMMC_CLKCR_DDR_Msk                     /*!<Data rate signaling selection    */
35452 #define SDMMC_CLKCR_BUSSPEED_Pos            (19U)
35453 #define SDMMC_CLKCR_BUSSPEED_Msk            (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos)     /*!< 0x00080000 */
35454 #define SDMMC_CLKCR_BUSSPEED                SDMMC_CLKCR_BUSSPEED_Msk                /*!<Bus speed mode selection         */
35455 #define SDMMC_CLKCR_SELCLKRX_Pos            (20U)
35456 #define SDMMC_CLKCR_SELCLKRX_Msk            (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos)     /*!< 0x00300000 */
35457 #define SDMMC_CLKCR_SELCLKRX                SDMMC_CLKCR_SELCLKRX_Msk                /*!<SELCLKRX[1:0] bits (Receive clock selection) */
35458 #define SDMMC_CLKCR_SELCLKRX_0              (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos)     /*!< 0x00100000 */
35459 #define SDMMC_CLKCR_SELCLKRX_1              (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos)     /*!< 0x00200000 */
35460 
35461 /*******************  Bit definition for SDMMC_ARG register  *******************/
35462 #define SDMMC_ARG_CMDARG_Pos                (0U)
35463 #define SDMMC_ARG_CMDARG_Msk                (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos)  /*!< 0xFFFFFFFF */
35464 #define SDMMC_ARG_CMDARG                    SDMMC_ARG_CMDARG_Msk                    /*!<Command argument */
35465 
35466 /*******************  Bit definition for SDMMC_CMD register  *******************/
35467 #define SDMMC_CMD_CMDINDEX_Pos              (0U)
35468 #define SDMMC_CMD_CMDINDEX_Msk              (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)      /*!< 0x0000003F */
35469 #define SDMMC_CMD_CMDINDEX                  SDMMC_CMD_CMDINDEX_Msk                  /*!<Command Index                               */
35470 #define SDMMC_CMD_CMDTRANS_Pos              (6U)
35471 #define SDMMC_CMD_CMDTRANS_Msk              (0x1UL << SDMMC_CMD_CMDTRANS_Pos)       /*!< 0x00000040 */
35472 #define SDMMC_CMD_CMDTRANS                  SDMMC_CMD_CMDTRANS_Msk                  /*!<CPSM Treats command as a Data Transfer      */
35473 #define SDMMC_CMD_CMDSTOP_Pos               (7U)
35474 #define SDMMC_CMD_CMDSTOP_Msk               (0x1UL << SDMMC_CMD_CMDSTOP_Pos)        /*!< 0x00000080 */
35475 #define SDMMC_CMD_CMDSTOP                   SDMMC_CMD_CMDSTOP_Msk                   /*!<CPSM Treats command as a Stop               */
35476 #define SDMMC_CMD_WAITRESP_Pos              (8U)
35477 #define SDMMC_CMD_WAITRESP_Msk              (0x3UL << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x00000300 */
35478 #define SDMMC_CMD_WAITRESP                  SDMMC_CMD_WAITRESP_Msk                  /*!<WAITRESP[1:0] bits (Wait for response bits) */
35479 #define SDMMC_CMD_WAITRESP_0                (0x1UL << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x00000100 */
35480 #define SDMMC_CMD_WAITRESP_1                (0x2UL << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x00000200 */
35481 #define SDMMC_CMD_WAITINT_Pos               (10U)
35482 #define SDMMC_CMD_WAITINT_Msk               (0x1UL << SDMMC_CMD_WAITINT_Pos)        /*!< 0x00000400 */
35483 #define SDMMC_CMD_WAITINT                   SDMMC_CMD_WAITINT_Msk                   /*!<CPSM Waits for Interrupt Request                               */
35484 #define SDMMC_CMD_WAITPEND_Pos              (11U)
35485 #define SDMMC_CMD_WAITPEND_Msk              (0x1UL << SDMMC_CMD_WAITPEND_Pos)       /*!< 0x00000800 */
35486 #define SDMMC_CMD_WAITPEND                  SDMMC_CMD_WAITPEND_Msk                  /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
35487 #define SDMMC_CMD_CPSMEN_Pos                (12U)
35488 #define SDMMC_CMD_CPSMEN_Msk                (0x1UL << SDMMC_CMD_CPSMEN_Pos)         /*!< 0x00001000 */
35489 #define SDMMC_CMD_CPSMEN                    SDMMC_CMD_CPSMEN_Msk                    /*!<Command path state machine (CPSM) Enable bit                   */
35490 #define SDMMC_CMD_DTHOLD_Pos                (13U)
35491 #define SDMMC_CMD_DTHOLD_Msk                (0x1UL << SDMMC_CMD_DTHOLD_Pos)         /*!< 0x00002000 */
35492 #define SDMMC_CMD_DTHOLD                    SDMMC_CMD_DTHOLD_Msk                    /*!<Hold new data block transmission and reception in the DPSM     */
35493 #define SDMMC_CMD_BOOTMODE_Pos              (14U)
35494 #define SDMMC_CMD_BOOTMODE_Msk              (0x1UL << SDMMC_CMD_BOOTMODE_Pos)       /*!< 0x00004000 */
35495 #define SDMMC_CMD_BOOTMODE                  SDMMC_CMD_BOOTMODE_Msk                  /*!<Boot mode                                                      */
35496 #define SDMMC_CMD_BOOTEN_Pos                (15U)
35497 #define SDMMC_CMD_BOOTEN_Msk                (0x1UL << SDMMC_CMD_BOOTEN_Pos)         /*!< 0x00008000 */
35498 #define SDMMC_CMD_BOOTEN                    SDMMC_CMD_BOOTEN_Msk                    /*!<Enable Boot mode procedure                                     */
35499 #define SDMMC_CMD_CMDSUSPEND_Pos            (16U)
35500 #define SDMMC_CMD_CMDSUSPEND_Msk            (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos)     /*!< 0x00010000 */
35501 #define SDMMC_CMD_CMDSUSPEND                SDMMC_CMD_CMDSUSPEND_Msk                /*!<CPSM Treats command as a Suspend or Resume command             */
35502 
35503 /*****************  Bit definition for SDMMC_RESPCMD register  *****************/
35504 #define SDMMC_RESPCMD_RESPCMD_Pos           (0U)
35505 #define SDMMC_RESPCMD_RESPCMD_Msk           (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos)   /*!< 0x0000003F */
35506 #define SDMMC_RESPCMD_RESPCMD               SDMMC_RESPCMD_RESPCMD_Msk               /*!<Response command index */
35507 
35508 /******************  Bit definition for SDMMC_RESP1 register  ******************/
35509 #define SDMMC_RESP1_CARDSTATUS1_Pos         (0U)
35510 #define SDMMC_RESP1_CARDSTATUS1_Msk         (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
35511 #define SDMMC_RESP1_CARDSTATUS1             SDMMC_RESP1_CARDSTATUS1_Msk             /*!<Card Status */
35512 
35513 /******************  Bit definition for SDMMC_RESP2 register  ******************/
35514 #define SDMMC_RESP2_CARDSTATUS2_Pos         (0U)
35515 #define SDMMC_RESP2_CARDSTATUS2_Msk         (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
35516 #define SDMMC_RESP2_CARDSTATUS2             SDMMC_RESP2_CARDSTATUS2_Msk             /*!<Card Status */
35517 
35518 /******************  Bit definition for SDMMC_RESP3 register  ******************/
35519 #define SDMMC_RESP3_CARDSTATUS3_Pos         (0U)
35520 #define SDMMC_RESP3_CARDSTATUS3_Msk         (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
35521 #define SDMMC_RESP3_CARDSTATUS3             SDMMC_RESP3_CARDSTATUS3_Msk             /*!<Card Status */
35522 
35523 /******************  Bit definition for SDMMC_RESP4 register  ******************/
35524 #define SDMMC_RESP4_CARDSTATUS4_Pos         (0U)
35525 #define SDMMC_RESP4_CARDSTATUS4_Msk         (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
35526 #define SDMMC_RESP4_CARDSTATUS4             SDMMC_RESP4_CARDSTATUS4_Msk             /*!<Card Status */
35527 
35528 /******************  Bit definition for SDMMC_DTIMER register  *****************/
35529 #define SDMMC_DTIMER_DATATIME_Pos           (0U)
35530 #define SDMMC_DTIMER_DATATIME_Msk           (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
35531 #define SDMMC_DTIMER_DATATIME               SDMMC_DTIMER_DATATIME_Msk               /*!<Data timeout period. */
35532 
35533 /******************  Bit definition for SDMMC_DLEN register  *******************/
35534 #define SDMMC_DLEN_DATALENGTH_Pos           (0U)
35535 #define SDMMC_DLEN_DATALENGTH_Msk           (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
35536 #define SDMMC_DLEN_DATALENGTH               SDMMC_DLEN_DATALENGTH_Msk               /*!<Data length value    */
35537 
35538 /******************  Bit definition for SDMMC_DCTRL register  ******************/
35539 #define SDMMC_DCTRL_DTEN_Pos                (0U)
35540 #define SDMMC_DCTRL_DTEN_Msk                (0x1UL << SDMMC_DCTRL_DTEN_Pos)         /*!< 0x00000001 */
35541 #define SDMMC_DCTRL_DTEN                    SDMMC_DCTRL_DTEN_Msk                    /*!<Data transfer enabled bit                */
35542 #define SDMMC_DCTRL_DTDIR_Pos               (1U)
35543 #define SDMMC_DCTRL_DTDIR_Msk               (0x1UL << SDMMC_DCTRL_DTDIR_Pos)        /*!< 0x00000002 */
35544 #define SDMMC_DCTRL_DTDIR                   SDMMC_DCTRL_DTDIR_Msk                   /*!<Data transfer direction selection        */
35545 #define SDMMC_DCTRL_DTMODE_Pos              (2U)
35546 #define SDMMC_DCTRL_DTMODE_Msk              (0x3UL << SDMMC_DCTRL_DTMODE_Pos)       /*!< 0x0000000C */
35547 #define SDMMC_DCTRL_DTMODE                  SDMMC_DCTRL_DTMODE_Msk                  /*!<DTMODE[1:0] Data transfer mode selection */
35548 #define SDMMC_DCTRL_DTMODE_0                (0x1UL << SDMMC_DCTRL_DTMODE_Pos)       /*!< 0x00000004 */
35549 #define SDMMC_DCTRL_DTMODE_1                (0x2UL << SDMMC_DCTRL_DTMODE_Pos)       /*!< 0x00000008 */
35550 #define SDMMC_DCTRL_DBLOCKSIZE_Pos          (4U)
35551 #define SDMMC_DCTRL_DBLOCKSIZE_Msk          (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x000000F0 */
35552 #define SDMMC_DCTRL_DBLOCKSIZE              SDMMC_DCTRL_DBLOCKSIZE_Msk              /*!<DBLOCKSIZE[3:0] bits (Data block size) */
35553 #define SDMMC_DCTRL_DBLOCKSIZE_0            (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000010 */
35554 #define SDMMC_DCTRL_DBLOCKSIZE_1            (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000020 */
35555 #define SDMMC_DCTRL_DBLOCKSIZE_2            (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000040 */
35556 #define SDMMC_DCTRL_DBLOCKSIZE_3            (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000080 */
35557 #define SDMMC_DCTRL_RWSTART_Pos             (8U)
35558 #define SDMMC_DCTRL_RWSTART_Msk             (0x1UL << SDMMC_DCTRL_RWSTART_Pos)      /*!< 0x00000100 */
35559 #define SDMMC_DCTRL_RWSTART                 SDMMC_DCTRL_RWSTART_Msk                 /*!<Read wait start                                 */
35560 #define SDMMC_DCTRL_RWSTOP_Pos              (9U)
35561 #define SDMMC_DCTRL_RWSTOP_Msk              (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)       /*!< 0x00000200 */
35562 #define SDMMC_DCTRL_RWSTOP                  SDMMC_DCTRL_RWSTOP_Msk                  /*!<Read wait stop                                  */
35563 #define SDMMC_DCTRL_RWMOD_Pos               (10U)
35564 #define SDMMC_DCTRL_RWMOD_Msk               (0x1UL << SDMMC_DCTRL_RWMOD_Pos)        /*!< 0x00000400 */
35565 #define SDMMC_DCTRL_RWMOD                   SDMMC_DCTRL_RWMOD_Msk                   /*!<Read wait mode                                  */
35566 #define SDMMC_DCTRL_SDIOEN_Pos              (11U)
35567 #define SDMMC_DCTRL_SDIOEN_Msk              (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)       /*!< 0x00000800 */
35568 #define SDMMC_DCTRL_SDIOEN                  SDMMC_DCTRL_SDIOEN_Msk                  /*!<SD I/O enable functions                         */
35569 #define SDMMC_DCTRL_BOOTACKEN_Pos           (12U)
35570 #define SDMMC_DCTRL_BOOTACKEN_Msk           (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos)    /*!< 0x00001000 */
35571 #define SDMMC_DCTRL_BOOTACKEN               SDMMC_DCTRL_BOOTACKEN_Msk               /*!<Enable the reception of the Boot Acknowledgment */
35572 #define SDMMC_DCTRL_FIFORST_Pos             (13U)
35573 #define SDMMC_DCTRL_FIFORST_Msk             (0x1UL << SDMMC_DCTRL_FIFORST_Pos)      /*!< 0x00002000 */
35574 #define SDMMC_DCTRL_FIFORST                 SDMMC_DCTRL_FIFORST_Msk                 /*!<FIFO reset                                      */
35575 
35576 /******************  Bit definition for SDMMC_DCOUNT register  *****************/
35577 #define SDMMC_DCOUNT_DATACOUNT_Pos          (0U)
35578 #define SDMMC_DCOUNT_DATACOUNT_Msk          (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
35579 #define SDMMC_DCOUNT_DATACOUNT              SDMMC_DCOUNT_DATACOUNT_Msk              /*!<Data count value */
35580 
35581 /******************  Bit definition for SDMMC_STA register  ********************/
35582 #define SDMMC_STA_CCRCFAIL_Pos              (0U)
35583 #define SDMMC_STA_CCRCFAIL_Msk              (0x1UL << SDMMC_STA_CCRCFAIL_Pos)       /*!< 0x00000001 */
35584 #define SDMMC_STA_CCRCFAIL                  SDMMC_STA_CCRCFAIL_Msk                  /*!<Command response received (CRC check failed)  */
35585 #define SDMMC_STA_DCRCFAIL_Pos              (1U)
35586 #define SDMMC_STA_DCRCFAIL_Msk              (0x1UL << SDMMC_STA_DCRCFAIL_Pos)       /*!< 0x00000002 */
35587 #define SDMMC_STA_DCRCFAIL                  SDMMC_STA_DCRCFAIL_Msk                  /*!<Data block sent/received (CRC check failed)   */
35588 #define SDMMC_STA_CTIMEOUT_Pos              (2U)
35589 #define SDMMC_STA_CTIMEOUT_Msk              (0x1UL << SDMMC_STA_CTIMEOUT_Pos)       /*!< 0x00000004 */
35590 #define SDMMC_STA_CTIMEOUT                  SDMMC_STA_CTIMEOUT_Msk                  /*!<Command response timeout                      */
35591 #define SDMMC_STA_DTIMEOUT_Pos              (3U)
35592 #define SDMMC_STA_DTIMEOUT_Msk              (0x1UL << SDMMC_STA_DTIMEOUT_Pos)       /*!< 0x00000008 */
35593 #define SDMMC_STA_DTIMEOUT                  SDMMC_STA_DTIMEOUT_Msk                  /*!<Data timeout                                  */
35594 #define SDMMC_STA_TXUNDERR_Pos              (4U)
35595 #define SDMMC_STA_TXUNDERR_Msk              (0x1UL << SDMMC_STA_TXUNDERR_Pos)       /*!< 0x00000010 */
35596 #define SDMMC_STA_TXUNDERR                  SDMMC_STA_TXUNDERR_Msk                  /*!<Transmit FIFO underrun error                  */
35597 #define SDMMC_STA_RXOVERR_Pos               (5U)
35598 #define SDMMC_STA_RXOVERR_Msk               (0x1UL << SDMMC_STA_RXOVERR_Pos)        /*!< 0x00000020 */
35599 #define SDMMC_STA_RXOVERR                   SDMMC_STA_RXOVERR_Msk                   /*!<Received FIFO overrun error                   */
35600 #define SDMMC_STA_CMDREND_Pos               (6U)
35601 #define SDMMC_STA_CMDREND_Msk               (0x1UL << SDMMC_STA_CMDREND_Pos)        /*!< 0x00000040 */
35602 #define SDMMC_STA_CMDREND                   SDMMC_STA_CMDREND_Msk                   /*!<Command response received (CRC check passed)  */
35603 #define SDMMC_STA_CMDSENT_Pos               (7U)
35604 #define SDMMC_STA_CMDSENT_Msk               (0x1UL << SDMMC_STA_CMDSENT_Pos)        /*!< 0x00000080 */
35605 #define SDMMC_STA_CMDSENT                   SDMMC_STA_CMDSENT_Msk                   /*!<Command sent (no response required)           */
35606 #define SDMMC_STA_DATAEND_Pos               (8U)
35607 #define SDMMC_STA_DATAEND_Msk               (0x1UL << SDMMC_STA_DATAEND_Pos)        /*!< 0x00000100 */
35608 #define SDMMC_STA_DATAEND                   SDMMC_STA_DATAEND_Msk                   /*!<Data end (data counter, SDIDCOUNT, is zero)   */
35609 #define SDMMC_STA_DHOLD_Pos                 (9U)
35610 #define SDMMC_STA_DHOLD_Msk                 (0x1UL << SDMMC_STA_DHOLD_Pos)          /*!< 0x00000200 */
35611 #define SDMMC_STA_DHOLD                     SDMMC_STA_DHOLD_Msk                     /*!<Data transfer Hold                                                      */
35612 #define SDMMC_STA_DBCKEND_Pos               (10U)
35613 #define SDMMC_STA_DBCKEND_Msk               (0x1UL << SDMMC_STA_DBCKEND_Pos)        /*!< 0x00000400 */
35614 #define SDMMC_STA_DBCKEND                   SDMMC_STA_DBCKEND_Msk                   /*!<Data block sent/received (CRC check passed)   */
35615 #define SDMMC_STA_DABORT_Pos                (11U)
35616 #define SDMMC_STA_DABORT_Msk                (0x1UL << SDMMC_STA_DABORT_Pos)         /*!< 0x00000800 */
35617 #define SDMMC_STA_DABORT                    SDMMC_STA_DABORT_Msk                    /*!<Data transfer aborted by CMD12                                          */
35618 #define SDMMC_STA_DPSMACT_Pos               (12U)
35619 #define SDMMC_STA_DPSMACT_Msk               (0x1UL << SDMMC_STA_DPSMACT_Pos)        /*!< 0x00001000 */
35620 #define SDMMC_STA_DPSMACT                   SDMMC_STA_DPSMACT_Msk                   /*!<Data path state machine active                                       */
35621 #define SDMMC_STA_CPSMACT_Pos               (13U)
35622 #define SDMMC_STA_CPSMACT_Msk               (0x1UL << SDMMC_STA_CPSMACT_Pos)        /*!< 0x00002000 */
35623 #define SDMMC_STA_CPSMACT                   SDMMC_STA_CPSMACT_Msk                   /*!<Command path state machine active                                          */
35624 #define SDMMC_STA_TXFIFOHE_Pos              (14U)
35625 #define SDMMC_STA_TXFIFOHE_Msk              (0x1UL << SDMMC_STA_TXFIFOHE_Pos)       /*!< 0x00004000 */
35626 #define SDMMC_STA_TXFIFOHE                  SDMMC_STA_TXFIFOHE_Msk                  /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
35627 #define SDMMC_STA_RXFIFOHF_Pos              (15U)
35628 #define SDMMC_STA_RXFIFOHF_Msk              (0x1UL << SDMMC_STA_RXFIFOHF_Pos)       /*!< 0x00008000 */
35629 #define SDMMC_STA_RXFIFOHF                  SDMMC_STA_RXFIFOHF_Msk                  /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
35630 #define SDMMC_STA_TXFIFOF_Pos               (16U)
35631 #define SDMMC_STA_TXFIFOF_Msk               (0x1UL << SDMMC_STA_TXFIFOF_Pos)        /*!< 0x00010000 */
35632 #define SDMMC_STA_TXFIFOF                   SDMMC_STA_TXFIFOF_Msk                   /*!<Transmit FIFO full                            */
35633 #define SDMMC_STA_RXFIFOF_Pos               (17U)
35634 #define SDMMC_STA_RXFIFOF_Msk               (0x1UL << SDMMC_STA_RXFIFOF_Pos)        /*!< 0x00020000 */
35635 #define SDMMC_STA_RXFIFOF                   SDMMC_STA_RXFIFOF_Msk                   /*!<Receive FIFO full                             */
35636 #define SDMMC_STA_TXFIFOE_Pos               (18U)
35637 #define SDMMC_STA_TXFIFOE_Msk               (0x1UL << SDMMC_STA_TXFIFOE_Pos)        /*!< 0x00040000 */
35638 #define SDMMC_STA_TXFIFOE                   SDMMC_STA_TXFIFOE_Msk                   /*!<Transmit FIFO empty                           */
35639 #define SDMMC_STA_RXFIFOE_Pos               (19U)
35640 #define SDMMC_STA_RXFIFOE_Msk               (0x1UL << SDMMC_STA_RXFIFOE_Pos)        /*!< 0x00080000 */
35641 #define SDMMC_STA_RXFIFOE                   SDMMC_STA_RXFIFOE_Msk                   /*!<Receive FIFO empty                            */
35642 #define SDMMC_STA_BUSYD0_Pos                (20U)
35643 #define SDMMC_STA_BUSYD0_Msk                (0x1UL << SDMMC_STA_BUSYD0_Pos)         /*!< 0x00100000 */
35644 #define SDMMC_STA_BUSYD0                    SDMMC_STA_BUSYD0_Msk                    /*!<Inverted value of SDMMC_D0 line (Busy)                                  */
35645 #define SDMMC_STA_BUSYD0END_Pos             (21U)
35646 #define SDMMC_STA_BUSYD0END_Msk             (0x1UL << SDMMC_STA_BUSYD0END_Pos)      /*!< 0x00200000 */
35647 #define SDMMC_STA_BUSYD0END                 SDMMC_STA_BUSYD0END_Msk                 /*!<End of SDMMC_D0 Busy following a CMD response detected                  */
35648 #define SDMMC_STA_SDIOIT_Pos                (22U)
35649 #define SDMMC_STA_SDIOIT_Msk                (0x1UL << SDMMC_STA_SDIOIT_Pos)         /*!< 0x00400000 */
35650 #define SDMMC_STA_SDIOIT                    SDMMC_STA_SDIOIT_Msk                    /*!<SDIO interrupt received                                                 */
35651 #define SDMMC_STA_ACKFAIL_Pos               (23U)
35652 #define SDMMC_STA_ACKFAIL_Msk               (0x1UL << SDMMC_STA_ACKFAIL_Pos)        /*!< 0x00800000 */
35653 #define SDMMC_STA_ACKFAIL                   SDMMC_STA_ACKFAIL_Msk                   /*!<Boot Acknowledgment received (BootAck check fail)                       */
35654 #define SDMMC_STA_ACKTIMEOUT_Pos            (24U)
35655 #define SDMMC_STA_ACKTIMEOUT_Msk            (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos)     /*!< 0x01000000 */
35656 #define SDMMC_STA_ACKTIMEOUT                SDMMC_STA_ACKTIMEOUT_Msk                /*!<Boot Acknowledgment timeout                                             */
35657 #define SDMMC_STA_VSWEND_Pos                (25U)
35658 #define SDMMC_STA_VSWEND_Msk                (0x1UL << SDMMC_STA_VSWEND_Pos)         /*!< 0x02000000 */
35659 #define SDMMC_STA_VSWEND                    SDMMC_STA_VSWEND_Msk                    /*!<Voltage switch critical timing section completion                       */
35660 #define SDMMC_STA_CKSTOP_Pos                (26U)
35661 #define SDMMC_STA_CKSTOP_Msk                (0x1UL << SDMMC_STA_CKSTOP_Pos)         /*!< 0x04000000 */
35662 #define SDMMC_STA_CKSTOP                    SDMMC_STA_CKSTOP_Msk                    /*!<SDMMC_CK stopped in Voltage switch procedure                            */
35663 #define SDMMC_STA_IDMATE_Pos                (27U)
35664 #define SDMMC_STA_IDMATE_Msk                (0x1UL << SDMMC_STA_IDMATE_Pos)         /*!< 0x08000000 */
35665 #define SDMMC_STA_IDMATE                    SDMMC_STA_IDMATE_Msk                    /*!<IDMA transfer error                                                     */
35666 #define SDMMC_STA_IDMABTC_Pos               (28U)
35667 #define SDMMC_STA_IDMABTC_Msk               (0x1UL << SDMMC_STA_IDMABTC_Pos)        /*!< 0x10000000 */
35668 #define SDMMC_STA_IDMABTC                   SDMMC_STA_IDMABTC_Msk                   /*!<IDMA buffer transfer complete                                           */
35669 
35670 /*******************  Bit definition for SDMMC_ICR register  *******************/
35671 #define SDMMC_ICR_CCRCFAILC_Pos             (0U)
35672 #define SDMMC_ICR_CCRCFAILC_Msk             (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)      /*!< 0x00000001 */
35673 #define SDMMC_ICR_CCRCFAILC                 SDMMC_ICR_CCRCFAILC_Msk                 /*!<CCRCFAIL flag clear bit */
35674 #define SDMMC_ICR_DCRCFAILC_Pos             (1U)
35675 #define SDMMC_ICR_DCRCFAILC_Msk             (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)      /*!< 0x00000002 */
35676 #define SDMMC_ICR_DCRCFAILC                 SDMMC_ICR_DCRCFAILC_Msk                 /*!<DCRCFAIL flag clear bit */
35677 #define SDMMC_ICR_CTIMEOUTC_Pos             (2U)
35678 #define SDMMC_ICR_CTIMEOUTC_Msk             (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)      /*!< 0x00000004 */
35679 #define SDMMC_ICR_CTIMEOUTC                 SDMMC_ICR_CTIMEOUTC_Msk                 /*!<CTIMEOUT flag clear bit */
35680 #define SDMMC_ICR_DTIMEOUTC_Pos             (3U)
35681 #define SDMMC_ICR_DTIMEOUTC_Msk             (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)      /*!< 0x00000008 */
35682 #define SDMMC_ICR_DTIMEOUTC                 SDMMC_ICR_DTIMEOUTC_Msk                 /*!<DTIMEOUT flag clear bit */
35683 #define SDMMC_ICR_TXUNDERRC_Pos             (4U)
35684 #define SDMMC_ICR_TXUNDERRC_Msk             (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)      /*!< 0x00000010 */
35685 #define SDMMC_ICR_TXUNDERRC                 SDMMC_ICR_TXUNDERRC_Msk                 /*!<TXUNDERR flag clear bit */
35686 #define SDMMC_ICR_RXOVERRC_Pos              (5U)
35687 #define SDMMC_ICR_RXOVERRC_Msk              (0x1UL << SDMMC_ICR_RXOVERRC_Pos)       /*!< 0x00000020 */
35688 #define SDMMC_ICR_RXOVERRC                  SDMMC_ICR_RXOVERRC_Msk                  /*!<RXOVERR flag clear bit  */
35689 #define SDMMC_ICR_CMDRENDC_Pos              (6U)
35690 #define SDMMC_ICR_CMDRENDC_Msk              (0x1UL << SDMMC_ICR_CMDRENDC_Pos)       /*!< 0x00000040 */
35691 #define SDMMC_ICR_CMDRENDC                  SDMMC_ICR_CMDRENDC_Msk                  /*!<CMDREND flag clear bit  */
35692 #define SDMMC_ICR_CMDSENTC_Pos              (7U)
35693 #define SDMMC_ICR_CMDSENTC_Msk              (0x1UL << SDMMC_ICR_CMDSENTC_Pos)       /*!< 0x00000080 */
35694 #define SDMMC_ICR_CMDSENTC                  SDMMC_ICR_CMDSENTC_Msk                  /*!<CMDSENT flag clear bit  */
35695 #define SDMMC_ICR_DATAENDC_Pos              (8U)
35696 #define SDMMC_ICR_DATAENDC_Msk              (0x1UL << SDMMC_ICR_DATAENDC_Pos)       /*!< 0x00000100 */
35697 #define SDMMC_ICR_DATAENDC                  SDMMC_ICR_DATAENDC_Msk                  /*!<DATAEND flag clear bit  */
35698 #define SDMMC_ICR_DHOLDC_Pos                (9U)
35699 #define SDMMC_ICR_DHOLDC_Msk                (0x1UL << SDMMC_ICR_DHOLDC_Pos)         /*!< 0x00000200 */
35700 #define SDMMC_ICR_DHOLDC                    SDMMC_ICR_DHOLDC_Msk                    /*!<DHOLD flag clear bit       */
35701 #define SDMMC_ICR_DBCKENDC_Pos              (10U)
35702 #define SDMMC_ICR_DBCKENDC_Msk              (0x1UL << SDMMC_ICR_DBCKENDC_Pos)       /*!< 0x00000400 */
35703 #define SDMMC_ICR_DBCKENDC                  SDMMC_ICR_DBCKENDC_Msk                  /*!<DBCKEND flag clear bit  */
35704 #define SDMMC_ICR_DABORTC_Pos               (11U)
35705 #define SDMMC_ICR_DABORTC_Msk               (0x1UL << SDMMC_ICR_DABORTC_Pos)        /*!< 0x00000800 */
35706 #define SDMMC_ICR_DABORTC                   SDMMC_ICR_DABORTC_Msk                   /*!<DABORTC flag clear bit     */
35707 #define SDMMC_ICR_BUSYD0ENDC_Pos            (21U)
35708 #define SDMMC_ICR_BUSYD0ENDC_Msk            (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos)     /*!< 0x00200000 */
35709 #define SDMMC_ICR_BUSYD0ENDC                SDMMC_ICR_BUSYD0ENDC_Msk                /*!<BUSYD0ENDC flag clear bit  */
35710 #define SDMMC_ICR_SDIOITC_Pos               (22U)
35711 #define SDMMC_ICR_SDIOITC_Msk               (0x1UL << SDMMC_ICR_SDIOITC_Pos)        /*!< 0x00400000 */
35712 #define SDMMC_ICR_SDIOITC                   SDMMC_ICR_SDIOITC_Msk                   /*!<SDIOIT flag clear bit      */
35713 #define SDMMC_ICR_ACKFAILC_Pos              (23U)
35714 #define SDMMC_ICR_ACKFAILC_Msk              (0x1UL << SDMMC_ICR_ACKFAILC_Pos)       /*!< 0x00800000 */
35715 #define SDMMC_ICR_ACKFAILC                  SDMMC_ICR_ACKFAILC_Msk                  /*!<ACKFAILC flag clear bit    */
35716 #define SDMMC_ICR_ACKTIMEOUTC_Pos           (24U)
35717 #define SDMMC_ICR_ACKTIMEOUTC_Msk           (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos)    /*!< 0x01000000 */
35718 #define SDMMC_ICR_ACKTIMEOUTC               SDMMC_ICR_ACKTIMEOUTC_Msk               /*!<ACKTIMEOUTC flag clear bit */
35719 #define SDMMC_ICR_VSWENDC_Pos               (25U)
35720 #define SDMMC_ICR_VSWENDC_Msk               (0x1UL << SDMMC_ICR_VSWENDC_Pos)        /*!< 0x02000000 */
35721 #define SDMMC_ICR_VSWENDC                   SDMMC_ICR_VSWENDC_Msk                   /*!<VSWENDC flag clear bit     */
35722 #define SDMMC_ICR_CKSTOPC_Pos               (26U)
35723 #define SDMMC_ICR_CKSTOPC_Msk               (0x1UL << SDMMC_ICR_CKSTOPC_Pos)        /*!< 0x04000000 */
35724 #define SDMMC_ICR_CKSTOPC                   SDMMC_ICR_CKSTOPC_Msk                   /*!<CKSTOPC flag clear bit     */
35725 #define SDMMC_ICR_IDMATEC_Pos               (27U)
35726 #define SDMMC_ICR_IDMATEC_Msk               (0x1UL << SDMMC_ICR_IDMATEC_Pos)        /*!< 0x08000000 */
35727 #define SDMMC_ICR_IDMATEC                   SDMMC_ICR_IDMATEC_Msk                   /*!<IDMATEC flag clear bit     */
35728 #define SDMMC_ICR_IDMABTCC_Pos              (28U)
35729 #define SDMMC_ICR_IDMABTCC_Msk              (0x1UL << SDMMC_ICR_IDMABTCC_Pos)       /*!< 0x10000000 */
35730 #define SDMMC_ICR_IDMABTCC                  SDMMC_ICR_IDMABTCC_Msk                  /*!<IDMABTCC flag clear bit    */
35731 
35732 /******************  Bit definition for SDMMC_MASK register  *******************/
35733 #define SDMMC_MASK_CCRCFAILIE_Pos           (0U)
35734 #define SDMMC_MASK_CCRCFAILIE_Msk           (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)    /*!< 0x00000001 */
35735 #define SDMMC_MASK_CCRCFAILIE               SDMMC_MASK_CCRCFAILIE_Msk               /*!<Command CRC Fail Interrupt Enable          */
35736 #define SDMMC_MASK_DCRCFAILIE_Pos           (1U)
35737 #define SDMMC_MASK_DCRCFAILIE_Msk           (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)    /*!< 0x00000002 */
35738 #define SDMMC_MASK_DCRCFAILIE               SDMMC_MASK_DCRCFAILIE_Msk               /*!<Data CRC Fail Interrupt Enable             */
35739 #define SDMMC_MASK_CTIMEOUTIE_Pos           (2U)
35740 #define SDMMC_MASK_CTIMEOUTIE_Msk           (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)    /*!< 0x00000004 */
35741 #define SDMMC_MASK_CTIMEOUTIE               SDMMC_MASK_CTIMEOUTIE_Msk               /*!<Command TimeOut Interrupt Enable           */
35742 #define SDMMC_MASK_DTIMEOUTIE_Pos           (3U)
35743 #define SDMMC_MASK_DTIMEOUTIE_Msk           (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)    /*!< 0x00000008 */
35744 #define SDMMC_MASK_DTIMEOUTIE               SDMMC_MASK_DTIMEOUTIE_Msk               /*!<Data TimeOut Interrupt Enable              */
35745 #define SDMMC_MASK_TXUNDERRIE_Pos           (4U)
35746 #define SDMMC_MASK_TXUNDERRIE_Msk           (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)    /*!< 0x00000010 */
35747 #define SDMMC_MASK_TXUNDERRIE               SDMMC_MASK_TXUNDERRIE_Msk               /*!<Tx FIFO UnderRun Error Interrupt Enable    */
35748 #define SDMMC_MASK_RXOVERRIE_Pos            (5U)
35749 #define SDMMC_MASK_RXOVERRIE_Msk            (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)     /*!< 0x00000020 */
35750 #define SDMMC_MASK_RXOVERRIE                SDMMC_MASK_RXOVERRIE_Msk                /*!<Rx FIFO OverRun Error Interrupt Enable     */
35751 #define SDMMC_MASK_CMDRENDIE_Pos            (6U)
35752 #define SDMMC_MASK_CMDRENDIE_Msk            (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)     /*!< 0x00000040 */
35753 #define SDMMC_MASK_CMDRENDIE                SDMMC_MASK_CMDRENDIE_Msk                /*!<Command Response Received Interrupt Enable */
35754 #define SDMMC_MASK_CMDSENTIE_Pos            (7U)
35755 #define SDMMC_MASK_CMDSENTIE_Msk            (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)     /*!< 0x00000080 */
35756 #define SDMMC_MASK_CMDSENTIE                SDMMC_MASK_CMDSENTIE_Msk                /*!<Command Sent Interrupt Enable              */
35757 #define SDMMC_MASK_DATAENDIE_Pos            (8U)
35758 #define SDMMC_MASK_DATAENDIE_Msk            (0x1UL << SDMMC_MASK_DATAENDIE_Pos)     /*!< 0x00000100 */
35759 #define SDMMC_MASK_DATAENDIE                SDMMC_MASK_DATAENDIE_Msk                /*!<Data End Interrupt Enable                  */
35760 #define SDMMC_MASK_DHOLDIE_Pos              (9U)
35761 #define SDMMC_MASK_DHOLDIE_Msk              (0x1UL << SDMMC_MASK_DHOLDIE_Pos)       /*!< 0x00000200 */
35762 #define SDMMC_MASK_DHOLDIE                  SDMMC_MASK_DHOLDIE_Msk                  /*!<Data Hold Interrupt Enable                 */
35763 #define SDMMC_MASK_DBCKENDIE_Pos            (10U)
35764 #define SDMMC_MASK_DBCKENDIE_Msk            (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)     /*!< 0x00000400 */
35765 #define SDMMC_MASK_DBCKENDIE                SDMMC_MASK_DBCKENDIE_Msk                /*!<Data Block End Interrupt Enable            */
35766 #define SDMMC_MASK_DABORTIE_Pos             (11U)
35767 #define SDMMC_MASK_DABORTIE_Msk             (0x1UL << SDMMC_MASK_DABORTIE_Pos)      /*!< 0x00000800 */
35768 #define SDMMC_MASK_DABORTIE                 SDMMC_MASK_DABORTIE_Msk                 /*!<Data transfer aborted interrupt enable     */
35769 #define SDMMC_MASK_TXFIFOHEIE_Pos           (14U)
35770 #define SDMMC_MASK_TXFIFOHEIE_Msk           (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)    /*!< 0x00004000 */
35771 #define SDMMC_MASK_TXFIFOHEIE               SDMMC_MASK_TXFIFOHEIE_Msk               /*!<Tx FIFO Half Empty interrupt Enable        */
35772 #define SDMMC_MASK_RXFIFOHFIE_Pos           (15U)
35773 #define SDMMC_MASK_RXFIFOHFIE_Msk           (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)    /*!< 0x00008000 */
35774 #define SDMMC_MASK_RXFIFOHFIE               SDMMC_MASK_RXFIFOHFIE_Msk               /*!<Rx FIFO Half Full interrupt Enable         */
35775 #define SDMMC_MASK_RXFIFOFIE_Pos            (17U)
35776 #define SDMMC_MASK_RXFIFOFIE_Msk            (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)     /*!< 0x00020000 */
35777 #define SDMMC_MASK_RXFIFOFIE                SDMMC_MASK_RXFIFOFIE_Msk                /*!<Rx FIFO Full interrupt Enable              */
35778 #define SDMMC_MASK_TXFIFOEIE_Pos            (18U)
35779 #define SDMMC_MASK_TXFIFOEIE_Msk            (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)     /*!< 0x00040000 */
35780 #define SDMMC_MASK_TXFIFOEIE                SDMMC_MASK_TXFIFOEIE_Msk                /*!<Tx FIFO Empty interrupt Enable             */
35781 #define SDMMC_MASK_BUSYD0ENDIE_Pos          (21U)
35782 #define SDMMC_MASK_BUSYD0ENDIE_Msk          (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos)   /*!< 0x00200000 */
35783 #define SDMMC_MASK_BUSYD0ENDIE              SDMMC_MASK_BUSYD0ENDIE_Msk              /*!<BUSYD0ENDIE interrupt Enable */
35784 #define SDMMC_MASK_SDIOITIE_Pos             (22U)
35785 #define SDMMC_MASK_SDIOITIE_Msk             (0x1UL << SDMMC_MASK_SDIOITIE_Pos)      /*!< 0x00400000 */
35786 #define SDMMC_MASK_SDIOITIE                 SDMMC_MASK_SDIOITIE_Msk                 /*!<SDMMC Mode Interrupt Received interrupt Enable */
35787 #define SDMMC_MASK_ACKFAILIE_Pos            (23U)
35788 #define SDMMC_MASK_ACKFAILIE_Msk            (0x1UL << SDMMC_MASK_ACKFAILIE_Pos)     /*!< 0x00800000 */
35789 #define SDMMC_MASK_ACKFAILIE                SDMMC_MASK_ACKFAILIE_Msk                /*!<Acknowledgment Fail Interrupt Enable */
35790 #define SDMMC_MASK_ACKTIMEOUTIE_Pos         (24U)
35791 #define SDMMC_MASK_ACKTIMEOUTIE_Msk         (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos)  /*!< 0x01000000 */
35792 #define SDMMC_MASK_ACKTIMEOUTIE             SDMMC_MASK_ACKTIMEOUTIE_Msk             /*!<Acknowledgment timeout Interrupt Enable */
35793 #define SDMMC_MASK_VSWENDIE_Pos             (25U)
35794 #define SDMMC_MASK_VSWENDIE_Msk             (0x1UL << SDMMC_MASK_VSWENDIE_Pos)      /*!< 0x02000000 */
35795 #define SDMMC_MASK_VSWENDIE                 SDMMC_MASK_VSWENDIE_Msk                 /*!<Voltage switch critical timing section completion Interrupt Enable */
35796 #define SDMMC_MASK_CKSTOPIE_Pos             (26U)
35797 #define SDMMC_MASK_CKSTOPIE_Msk             (0x1UL << SDMMC_MASK_CKSTOPIE_Pos)      /*!< 0x04000000 */
35798 #define SDMMC_MASK_CKSTOPIE                 SDMMC_MASK_CKSTOPIE_Msk                 /*!<Voltage Switch clock stopped Interrupt Enable */
35799 #define SDMMC_MASK_IDMABTCIE_Pos            (28U)
35800 #define SDMMC_MASK_IDMABTCIE_Msk            (0x1UL << SDMMC_MASK_IDMABTCIE_Pos)     /*!< 0x10000000 */
35801 #define SDMMC_MASK_IDMABTCIE                SDMMC_MASK_IDMABTCIE_Msk                /*!<IDMA buffer transfer complete Interrupt Enable */
35802 
35803 /*****************  Bit definition for SDMMC_ACKTIME register  *****************/
35804 #define SDMMC_ACKTIME_ACKTIME_Pos           (0U)
35805 #define SDMMC_ACKTIME_ACKTIME_Msk           (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos) /*!< 0x01FFFFFF */
35806 #define SDMMC_ACKTIME_ACKTIME               SDMMC_ACKTIME_ACKTIME_Msk               /*!<Boot acknowledgment timeout period */
35807 
35808 /******************  Bit definition for SDMMC_FIFOTHR register  *******************/
35809 #define SDMMC_FIFOTHR_THR_Pos               (0U)
35810 #define SDMMC_FIFOTHR_THR_Msk               (0xFUL << SDMMC_FIFOTHR_THR_Pos)        /*!< 0x0000000F */
35811 #define SDMMC_FIFOTHR_THR                   SDMMC_FIFOTHR_THR_Msk                   /*!<FIFO threshold */
35812 
35813 /******************  Bit definition for SDMMC_FIFO register  *******************/
35814 #define SDMMC_FIFO_FIFODATA_Pos             (0U)
35815 #define SDMMC_FIFO_FIFODATA_Msk             (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
35816 #define SDMMC_FIFO_FIFODATA                 SDMMC_FIFO_FIFODATA_Msk                 /*!<Receive and transmit FIFO data */
35817 
35818 /******************  Bit definition for SDMMC_IDMACTRL register ****************/
35819 #define SDMMC_IDMA_IDMAEN_Pos               (0U)
35820 #define SDMMC_IDMA_IDMAEN_Msk               (0x1UL << SDMMC_IDMA_IDMAEN_Pos)        /*!< 0x00000001 */
35821 #define SDMMC_IDMA_IDMAEN                   SDMMC_IDMA_IDMAEN_Msk                   /*!< Enable the internal DMA of the SDMMC peripheral */
35822 #define SDMMC_IDMA_IDMABMODE_Pos            (1U)
35823 #define SDMMC_IDMA_IDMABMODE_Msk            (0x1UL << SDMMC_IDMA_IDMABMODE_Pos)     /*!< 0x00000002 */
35824 #define SDMMC_IDMA_IDMABMODE                SDMMC_IDMA_IDMABMODE_Msk                /*!< Enable Linked List mode for IDMA */
35825 
35826 /*****************  Bit definition for SDMMC_IDMABSIZE register  ***************/
35827 #define SDMMC_IDMABSIZE_IDMABNDT_Pos        (6U)
35828 #define SDMMC_IDMABSIZE_IDMABNDT_Msk        (0x7FFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos) /*!< 0x0001FFC0 */
35829 #define SDMMC_IDMABSIZE_IDMABNDT            SDMMC_IDMABSIZE_IDMABNDT_Msk              /*!< Number of transfers per buffer */
35830 
35831 /*****************  Bit definition for SDMMC_IDMABASER register  ***************/
35832 #define SDMMC_IDMABASER_IDMABASER           ((uint32_t)0xFFFFFFFF)                  /*!< Memory base address register */
35833 
35834 /*****************  Bit definition for SDMMC_IDMALAR) register  ***************/
35835 #define SDMMC_IDMALAR_IDMALA_Pos            (0U)
35836 #define SDMMC_IDMALAR_IDMALA_Msk            (0x3FFFUL << SDMMC_IDMALAR_IDMALA_Pos)  /*!< 0x00003FFF */
35837 #define SDMMC_IDMALAR_IDMALA                SDMMC_IDMALAR_IDMALA_Msk                /*!< Linked list item address offset */
35838 #define SDMMC_IDMALAR_ABR_Pos               (29U)
35839 #define SDMMC_IDMALAR_ABR_Msk               (0x1UL << SDMMC_IDMALAR_ABR_Pos)        /*!< 0x20000000 */
35840 #define SDMMC_IDMALAR_ABR                   SDMMC_IDMALAR_ABR_Msk                   /*!< Acknowledge linked list buffer ready */
35841 #define SDMMC_IDMALAR_ULS_Pos               (30U)
35842 #define SDMMC_IDMALAR_ULS_Msk               (0x1UL << SDMMC_IDMALAR_ULS_Pos)        /*!< 0x40000000 */
35843 #define SDMMC_IDMALAR_ULS                   SDMMC_IDMALAR_ULS_Msk                   /*!< Update Size from linked list */
35844 #define SDMMC_IDMALAR_ULA_Pos               (31U)
35845 #define SDMMC_IDMALAR_ULA_Msk               (0x1UL << SDMMC_IDMALAR_ULA_Pos)        /*!< 0x80000000 */
35846 #define SDMMC_IDMALAR_ULA                   SDMMC_IDMALAR_ULA_Msk                   /*!< Update Address from linked list */
35847 
35848 /*****************  Bit definition for SDMMC_IDMABAR) register  ***************/
35849 #define SDMMC_IDMABAR_IDMABAR               ((uint32_t)0xFFFFFFFF)                  /*!< linked list memory base register */
35850 
35851 
35852 /******************************************************************************/
35853 /*                                                                            */
35854 /*                   Serial Peripheral Interface (SPI)                        */
35855 /*                                                                            */
35856 /******************************************************************************/
35857 /*******************  Bit definition for SPI_CR1 register  ********************/
35858 #define SPI_CR1_SPE_Pos                     (0U)
35859 #define SPI_CR1_SPE_Msk                     (0x1UL << SPI_CR1_SPE_Pos)              /*!< 0x00000001 */
35860 #define SPI_CR1_SPE                         SPI_CR1_SPE_Msk                         /*!<Serial Peripheral Enable */
35861 #define SPI_CR1_MASRX_Pos                   (8U)
35862 #define SPI_CR1_MASRX_Msk                   (0x1UL << SPI_CR1_MASRX_Pos)            /*!< 0x00000100 */
35863 #define SPI_CR1_MASRX                       SPI_CR1_MASRX_Msk                       /*!<Master automatic SUSP in Receive mode */
35864 #define SPI_CR1_CSTART_Pos                  (9U)
35865 #define SPI_CR1_CSTART_Msk                  (0x1UL << SPI_CR1_CSTART_Pos)           /*!< 0x00000200 */
35866 #define SPI_CR1_CSTART                      SPI_CR1_CSTART_Msk                      /*!<Master transfer start  */
35867 #define SPI_CR1_CSUSP_Pos                   (10U)
35868 #define SPI_CR1_CSUSP_Msk                   (0x1UL << SPI_CR1_CSUSP_Pos)            /*!< 0x00000400 */
35869 #define SPI_CR1_CSUSP                       SPI_CR1_CSUSP_Msk                       /*!<Master SUSPend request */
35870 #define SPI_CR1_HDDIR_Pos                   (11U)
35871 #define SPI_CR1_HDDIR_Msk                   (0x1UL << SPI_CR1_HDDIR_Pos)            /*!< 0x00000800 */
35872 #define SPI_CR1_HDDIR                       SPI_CR1_HDDIR_Msk                       /*!<Rx/Tx direction at Half-duplex mode */
35873 #define SPI_CR1_SSI_Pos                     (12U)
35874 #define SPI_CR1_SSI_Msk                     (0x1UL << SPI_CR1_SSI_Pos)              /*!< 0x00001000 */
35875 #define SPI_CR1_SSI                         SPI_CR1_SSI_Msk                         /*!<Internal SS signal input level */
35876 #define SPI_CR1_CRC33_17_Pos                (13U)
35877 #define SPI_CR1_CRC33_17_Msk                (0x1UL << SPI_CR1_CRC33_17_Pos)         /*!< 0x00002000 */
35878 #define SPI_CR1_CRC33_17                    SPI_CR1_CRC33_17_Msk                    /*!<32-bit CRC polynomial configuration */
35879 #define SPI_CR1_RCRCINI_Pos                 (14U)
35880 #define SPI_CR1_RCRCINI_Msk                 (0x1UL << SPI_CR1_RCRCINI_Pos)          /*!< 0x00004000 */
35881 #define SPI_CR1_RCRCINI                     SPI_CR1_RCRCINI_Msk                     /*!<CRC init pattern control for receiver */
35882 #define SPI_CR1_TCRCINI_Pos                 (15U)
35883 #define SPI_CR1_TCRCINI_Msk                 (0x1UL << SPI_CR1_TCRCINI_Pos)          /*!< 0x00008000 */
35884 #define SPI_CR1_TCRCINI                     SPI_CR1_TCRCINI_Msk                     /*!<CRC init pattern control for transmitter */
35885 #define SPI_CR1_IOLOCK_Pos                  (16U)
35886 #define SPI_CR1_IOLOCK_Msk                  (0x1UL << SPI_CR1_IOLOCK_Pos)           /*!< 0x00010000 */
35887 #define SPI_CR1_IOLOCK                      SPI_CR1_IOLOCK_Msk                      /*!<Locking the AF configuration of associated IOs */
35888 
35889 /*******************  Bit definition for SPI_CR2 register  ********************/
35890 #define SPI_CR2_TSIZE_Pos                   (0U)
35891 #define SPI_CR2_TSIZE_Msk                   (0xFFFFUL << SPI_CR2_TSIZE_Pos)         /*!< 0x0000FFFF */
35892 #define SPI_CR2_TSIZE                       SPI_CR2_TSIZE_Msk                       /*!<Number of data at current transfer */
35893 
35894 /*******************  Bit definition for SPI_CFG1 register  *******************/
35895 #define SPI_CFG1_DSIZE_Pos                  (0U)
35896 #define SPI_CFG1_DSIZE_Msk                  (0x1FUL << SPI_CFG1_DSIZE_Pos)          /*!< 0x0000001F */
35897 #define SPI_CFG1_DSIZE                      SPI_CFG1_DSIZE_Msk                      /*!<DSIZE[4:0]: Bits number in single SPI data frame */
35898 #define SPI_CFG1_DSIZE_0                    (0x01UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000001 */
35899 #define SPI_CFG1_DSIZE_1                    (0x02UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000002 */
35900 #define SPI_CFG1_DSIZE_2                    (0x04UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000004 */
35901 #define SPI_CFG1_DSIZE_3                    (0x08UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000008 */
35902 #define SPI_CFG1_DSIZE_4                    (0x10UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000010 */
35903 #define SPI_CFG1_FTHLV_Pos                  (5U)
35904 #define SPI_CFG1_FTHLV_Msk                  (0xFUL << SPI_CFG1_FTHLV_Pos)           /*!< 0x000001E0 */
35905 #define SPI_CFG1_FTHLV                      SPI_CFG1_FTHLV_Msk                      /*!<FTHVL [3:0]: FIFO threshold level*/
35906 #define SPI_CFG1_FTHLV_0                    (0x1UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000020 */
35907 #define SPI_CFG1_FTHLV_1                    (0x2UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000040 */
35908 #define SPI_CFG1_FTHLV_2                    (0x4UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000080 */
35909 #define SPI_CFG1_FTHLV_3                    (0x8UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000100 */
35910 #define SPI_CFG1_UDRCFG_Pos                 (9U)
35911 #define SPI_CFG1_UDRCFG_Msk                 (0x1UL << SPI_CFG1_UDRCFG_Pos)          /*!< 0x00000600 */
35912 #define SPI_CFG1_UDRCFG                     SPI_CFG1_UDRCFG_Msk                     /*!<Behavior of Slave transmitter at underrun */
35913 #define SPI_CFG1_RXDMAEN_Pos                (14U)
35914 #define SPI_CFG1_RXDMAEN_Msk                (0x1UL << SPI_CFG1_RXDMAEN_Pos)         /*!< 0x00004000 */
35915 #define SPI_CFG1_RXDMAEN                    SPI_CFG1_RXDMAEN_Msk                    /*!<Rx DMA stream enable */
35916 #define SPI_CFG1_TXDMAEN_Pos                (15U)
35917 #define SPI_CFG1_TXDMAEN_Msk                (0x1UL << SPI_CFG1_TXDMAEN_Pos)         /*!< 0x00008000 */
35918 #define SPI_CFG1_TXDMAEN                    SPI_CFG1_TXDMAEN_Msk                    /*!<Tx DMA stream enable */
35919 #define SPI_CFG1_CRCSIZE_Pos                (16U)
35920 #define SPI_CFG1_CRCSIZE_Msk                (0x1FUL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x001F0000 */
35921 #define SPI_CFG1_CRCSIZE                    SPI_CFG1_CRCSIZE_Msk                    /*!<CRCSIZE [4:0]: Length of CRC frame */
35922 #define SPI_CFG1_CRCSIZE_0                  (0x01UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00010000 */
35923 #define SPI_CFG1_CRCSIZE_1                  (0x02UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00020000 */
35924 #define SPI_CFG1_CRCSIZE_2                  (0x04UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00040000 */
35925 #define SPI_CFG1_CRCSIZE_3                  (0x08UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00080000 */
35926 #define SPI_CFG1_CRCSIZE_4                  (0x10UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00100000 */
35927 #define SPI_CFG1_CRCEN_Pos                  (22U)
35928 #define SPI_CFG1_CRCEN_Msk                  (0x1UL << SPI_CFG1_CRCEN_Pos)           /*!< 0x00400000 */
35929 #define SPI_CFG1_CRCEN                      SPI_CFG1_CRCEN_Msk                      /*!<Hardware CRC computation enable */
35930 #define SPI_CFG1_MBR_Pos                    (28U)
35931 #define SPI_CFG1_MBR_Msk                    (0x7UL << SPI_CFG1_MBR_Pos)             /*!< 0x70000000 */
35932 #define SPI_CFG1_MBR                        SPI_CFG1_MBR_Msk                        /*!<Master baud rate */
35933 #define SPI_CFG1_MBR_0                      (0x1UL << SPI_CFG1_MBR_Pos)             /*!< 0x10000000 */
35934 #define SPI_CFG1_MBR_1                      (0x2UL << SPI_CFG1_MBR_Pos)             /*!< 0x20000000 */
35935 #define SPI_CFG1_MBR_2                      (0x4UL << SPI_CFG1_MBR_Pos)             /*!< 0x40000000 */
35936 #define SPI_CFG1_BPASS_Pos                  (31U)
35937 #define SPI_CFG1_BPASS_Msk                  (0x1UL << SPI_CFG1_BPASS_Pos)           /*!< 0x80000000 */
35938 #define SPI_CFG1_BPASS                      SPI_CFG1_BPASS_Msk                      /*!<Bypass of the prescaler */
35939 
35940 /*******************  Bit definition for SPI_CFG2 register  *******************/
35941 #define SPI_CFG2_MSSI_Pos                   (0U)
35942 #define SPI_CFG2_MSSI_Msk                   (0xFUL << SPI_CFG2_MSSI_Pos)            /*!< 0x0000000F */
35943 #define SPI_CFG2_MSSI                       SPI_CFG2_MSSI_Msk                       /*!<Master SS Idleness */
35944 #define SPI_CFG2_MSSI_0                     (0x1UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000001 */
35945 #define SPI_CFG2_MSSI_1                     (0x2UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000002 */
35946 #define SPI_CFG2_MSSI_2                     (0x4UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000004 */
35947 #define SPI_CFG2_MSSI_3                     (0x8UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000008 */
35948 #define SPI_CFG2_MIDI_Pos                   (4U)
35949 #define SPI_CFG2_MIDI_Msk                   (0xFUL << SPI_CFG2_MIDI_Pos)            /*!< 0x000000F0 */
35950 #define SPI_CFG2_MIDI                       SPI_CFG2_MIDI_Msk                       /*!<Master Inter-Data Idleness */
35951 #define SPI_CFG2_MIDI_0                     (0x1UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000010 */
35952 #define SPI_CFG2_MIDI_1                     (0x2UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000020 */
35953 #define SPI_CFG2_MIDI_2                     (0x4UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000040 */
35954 #define SPI_CFG2_MIDI_3                     (0x8UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000080 */
35955 #define SPI_CFG2_RDIOM_Pos                  (13U)
35956 #define SPI_CFG2_RDIOM_Msk                  (0x1UL << SPI_CFG2_RDIOM_Pos)           /*!< 0x00002000 */
35957 #define SPI_CFG2_RDIOM                      SPI_CFG2_RDIOM_Msk                      /*!<RDY signal input/output management */
35958 #define SPI_CFG2_RDIOP_Pos                  (14U)
35959 #define SPI_CFG2_RDIOP_Msk                  (0x1UL << SPI_CFG2_RDIOP_Pos)           /*!< 0x00004000 */
35960 #define SPI_CFG2_RDIOP                      SPI_CFG2_RDIOP_Msk                      /*!<RDY signal input/output polarity */
35961 #define SPI_CFG2_IOSWP_Pos                  (15U)
35962 #define SPI_CFG2_IOSWP_Msk                  (0x1UL << SPI_CFG2_IOSWP_Pos)           /*!< 0x00008000 */
35963 #define SPI_CFG2_IOSWP                      SPI_CFG2_IOSWP_Msk                      /*!<Swap functionality of MISO and MOSI pins */
35964 #define SPI_CFG2_COMM_Pos                   (17U)
35965 #define SPI_CFG2_COMM_Msk                   (0x3UL << SPI_CFG2_COMM_Pos)            /*!< 0x00060000 */
35966 #define SPI_CFG2_COMM                       SPI_CFG2_COMM_Msk                       /*!<COMM [1:0]: SPI Communication Mode*/
35967 #define SPI_CFG2_COMM_0                     (0x1UL << SPI_CFG2_COMM_Pos)            /*!< 0x00020000 */
35968 #define SPI_CFG2_COMM_1                     (0x2UL << SPI_CFG2_COMM_Pos)            /*!< 0x00040000 */
35969 #define SPI_CFG2_SP_Pos                     (19U)
35970 #define SPI_CFG2_SP_Msk                     (0x7UL << SPI_CFG2_SP_Pos)              /*!< 0x00380000 */
35971 #define SPI_CFG2_SP                         SPI_CFG2_SP_Msk                         /*!<SP[2:0]: Serial Protocol */
35972 #define SPI_CFG2_SP_0                       (0x1UL << SPI_CFG2_SP_Pos)              /*!< 0x00080000 */
35973 #define SPI_CFG2_SP_1                       (0x2UL << SPI_CFG2_SP_Pos)              /*!< 0x00100000 */
35974 #define SPI_CFG2_SP_2                       (0x4UL << SPI_CFG2_SP_Pos)              /*!< 0x00200000 */
35975 #define SPI_CFG2_MASTER_Pos                 (22U)
35976 #define SPI_CFG2_MASTER_Msk                 (0x1UL << SPI_CFG2_MASTER_Pos)          /*!< 0x00400000 */
35977 #define SPI_CFG2_MASTER                     SPI_CFG2_MASTER_Msk                     /*!<SPI Master */
35978 #define SPI_CFG2_LSBFRST_Pos                (23U)
35979 #define SPI_CFG2_LSBFRST_Msk                (0x1UL << SPI_CFG2_LSBFRST_Pos)         /*!< 0x00800000 */
35980 #define SPI_CFG2_LSBFRST                    SPI_CFG2_LSBFRST_Msk                    /*!<Data frame format */
35981 #define SPI_CFG2_CPHA_Pos                   (24U)
35982 #define SPI_CFG2_CPHA_Msk                   (0x1UL << SPI_CFG2_CPHA_Pos)            /*!< 0x01000000 */
35983 #define SPI_CFG2_CPHA                       SPI_CFG2_CPHA_Msk                       /*!<Clock Phase */
35984 #define SPI_CFG2_CPOL_Pos                   (25U)
35985 #define SPI_CFG2_CPOL_Msk                   (0x1UL << SPI_CFG2_CPOL_Pos)            /*!< 0x02000000 */
35986 #define SPI_CFG2_CPOL                       SPI_CFG2_CPOL_Msk                       /*!<Clock Polarity */
35987 #define SPI_CFG2_SSM_Pos                    (26U)
35988 #define SPI_CFG2_SSM_Msk                    (0x1UL << SPI_CFG2_SSM_Pos)             /*!< 0x04000000 */
35989 #define SPI_CFG2_SSM                        SPI_CFG2_SSM_Msk                        /*!<Software slave management */
35990 #define SPI_CFG2_SSIOP_Pos                  (28U)
35991 #define SPI_CFG2_SSIOP_Msk                  (0x1UL << SPI_CFG2_SSIOP_Pos)           /*!< 0x10000000 */
35992 #define SPI_CFG2_SSIOP                      SPI_CFG2_SSIOP_Msk                      /*!<SS input/output polarity */
35993 #define SPI_CFG2_SSOE_Pos                   (29U)
35994 #define SPI_CFG2_SSOE_Msk                   (0x1UL << SPI_CFG2_SSOE_Pos)            /*!< 0x20000000 */
35995 #define SPI_CFG2_SSOE                       SPI_CFG2_SSOE_Msk                       /*!<SS output enable */
35996 #define SPI_CFG2_SSOM_Pos                   (30U)
35997 #define SPI_CFG2_SSOM_Msk                   (0x1UL << SPI_CFG2_SSOM_Pos)            /*!< 0x40000000 */
35998 #define SPI_CFG2_SSOM                       SPI_CFG2_SSOM_Msk                       /*!<SS output management in master mode */
35999 #define SPI_CFG2_AFCNTR_Pos                 (31U)
36000 #define SPI_CFG2_AFCNTR_Msk                 (0x1UL << SPI_CFG2_AFCNTR_Pos)          /*!< 0x80000000 */
36001 #define SPI_CFG2_AFCNTR                     SPI_CFG2_AFCNTR_Msk                     /*!<Alternate function GPIOs control */
36002 
36003 /*******************  Bit definition for SPI_IER register  ********************/
36004 #define SPI_IER_RXPIE_Pos                   (0U)
36005 #define SPI_IER_RXPIE_Msk                   (0x1UL << SPI_IER_RXPIE_Pos)            /*!< 0x00000001 */
36006 #define SPI_IER_RXPIE                       SPI_IER_RXPIE_Msk                       /*!<RXP Interrupt Enable */
36007 #define SPI_IER_TXPIE_Pos                   (1U)
36008 #define SPI_IER_TXPIE_Msk                   (0x1UL << SPI_IER_TXPIE_Pos)            /*!< 0x00000002 */
36009 #define SPI_IER_TXPIE                       SPI_IER_TXPIE_Msk                       /*!<TXP interrupt enable */
36010 #define SPI_IER_DXPIE_Pos                   (2U)
36011 #define SPI_IER_DXPIE_Msk                   (0x1UL << SPI_IER_DXPIE_Pos)            /*!< 0x00000004 */
36012 #define SPI_IER_DXPIE                       SPI_IER_DXPIE_Msk                       /*!<DXP interrupt enable */
36013 #define SPI_IER_EOTIE_Pos                   (3U)
36014 #define SPI_IER_EOTIE_Msk                   (0x1UL << SPI_IER_EOTIE_Pos)            /*!< 0x00000008 */
36015 #define SPI_IER_EOTIE                       SPI_IER_EOTIE_Msk                       /*!<EOT/SUSP/TXC interrupt enable */
36016 #define SPI_IER_TXTFIE_Pos                  (4U)
36017 #define SPI_IER_TXTFIE_Msk                  (0x1UL << SPI_IER_TXTFIE_Pos)           /*!< 0x00000010 */
36018 #define SPI_IER_TXTFIE                      SPI_IER_TXTFIE_Msk                      /*!<TXTF interrupt enable */
36019 #define SPI_IER_UDRIE_Pos                   (5U)
36020 #define SPI_IER_UDRIE_Msk                   (0x1UL << SPI_IER_UDRIE_Pos)            /*!< 0x00000020 */
36021 #define SPI_IER_UDRIE                       SPI_IER_UDRIE_Msk                       /*!<UDR interrupt enable */
36022 #define SPI_IER_OVRIE_Pos                   (6U)
36023 #define SPI_IER_OVRIE_Msk                   (0x1UL << SPI_IER_OVRIE_Pos)            /*!< 0x00000040 */
36024 #define SPI_IER_OVRIE                       SPI_IER_OVRIE_Msk                       /*!<OVR interrupt enable */
36025 #define SPI_IER_CRCEIE_Pos                  (7U)
36026 #define SPI_IER_CRCEIE_Msk                  (0x1UL << SPI_IER_CRCEIE_Pos)           /*!< 0x00000080 */
36027 #define SPI_IER_CRCEIE                      SPI_IER_CRCEIE_Msk                      /*!<CRCE interrupt enable */
36028 #define SPI_IER_TIFREIE_Pos                 (8U)
36029 #define SPI_IER_TIFREIE_Msk                 (0x1UL << SPI_IER_TIFREIE_Pos)          /*!< 0x00000100 */
36030 #define SPI_IER_TIFREIE                     SPI_IER_TIFREIE_Msk                     /*!<TI Frame Error interrupt enable */
36031 #define SPI_IER_MODFIE_Pos                  (9U)
36032 #define SPI_IER_MODFIE_Msk                  (0x1UL << SPI_IER_MODFIE_Pos)           /*!< 0x00000200 */
36033 #define SPI_IER_MODFIE                      SPI_IER_MODFIE_Msk                      /*!<MODF interrupt enable */
36034 
36035 /*******************  Bit definition for SPI_SR register  *********************/
36036 #define SPI_SR_RXP_Pos                      (0U)
36037 #define SPI_SR_RXP_Msk                      (0x1UL << SPI_SR_RXP_Pos)               /*!< 0x00000001 */
36038 #define SPI_SR_RXP                          SPI_SR_RXP_Msk                          /*!<Rx-Packet available */
36039 #define SPI_SR_TXP_Pos                      (1U)
36040 #define SPI_SR_TXP_Msk                      (0x1UL << SPI_SR_TXP_Pos)               /*!< 0x00000002 */
36041 #define SPI_SR_TXP                          SPI_SR_TXP_Msk                          /*!<Tx-Packet space available */
36042 #define SPI_SR_DXP_Pos                      (2U)
36043 #define SPI_SR_DXP_Msk                      (0x1UL << SPI_SR_DXP_Pos)               /*!< 0x00000004 */
36044 #define SPI_SR_DXP                          SPI_SR_DXP_Msk                          /*!<Duplex Packet available */
36045 #define SPI_SR_EOT_Pos                      (3U)
36046 #define SPI_SR_EOT_Msk                      (0x1UL << SPI_SR_EOT_Pos)               /*!< 0x00000008 */
36047 #define SPI_SR_EOT                          SPI_SR_EOT_Msk                          /*!<Duplex Packet available */
36048 #define SPI_SR_TXTF_Pos                     (4U)
36049 #define SPI_SR_TXTF_Msk                     (0x1UL << SPI_SR_TXTF_Pos)              /*!< 0x00000010 */
36050 #define SPI_SR_TXTF                         SPI_SR_TXTF_Msk                         /*!<Transmission Transfer Filled */
36051 #define SPI_SR_UDR_Pos                      (5U)
36052 #define SPI_SR_UDR_Msk                      (0x1UL << SPI_SR_UDR_Pos)               /*!< 0x00000020 */
36053 #define SPI_SR_UDR                          SPI_SR_UDR_Msk                          /*!<UDR at Slave transmission */
36054 #define SPI_SR_OVR_Pos                      (6U)
36055 #define SPI_SR_OVR_Msk                      (0x1UL << SPI_SR_OVR_Pos)               /*!< 0x00000040 */
36056 #define SPI_SR_OVR                          SPI_SR_OVR_Msk                          /*!<Rx-Packet available */
36057 #define SPI_SR_CRCE_Pos                     (7U)
36058 #define SPI_SR_CRCE_Msk                     (0x1UL << SPI_SR_CRCE_Pos)              /*!< 0x00000080 */
36059 #define SPI_SR_CRCE                         SPI_SR_CRCE_Msk                         /*!<CRC Error Detected */
36060 #define SPI_SR_TIFRE_Pos                    (8U)
36061 #define SPI_SR_TIFRE_Msk                    (0x1UL << SPI_SR_TIFRE_Pos)             /*!< 0x00000100 */
36062 #define SPI_SR_TIFRE                        SPI_SR_TIFRE_Msk                        /*!<TI frame format error Detected */
36063 #define SPI_SR_MODF_Pos                     (9U)
36064 #define SPI_SR_MODF_Msk                     (0x1UL << SPI_SR_MODF_Pos)              /*!< 0x00000200 */
36065 #define SPI_SR_MODF                         SPI_SR_MODF_Msk                         /*!<Mode Fault Detected */
36066 #define SPI_SR_SUSP_Pos                     (11U)
36067 #define SPI_SR_SUSP_Msk                     (0x1UL << SPI_SR_SUSP_Pos)              /*!< 0x00000800 */
36068 #define SPI_SR_SUSP                         SPI_SR_SUSP_Msk                         /*!<SUSP is set by hardware */
36069 #define SPI_SR_TXC_Pos                      (12U)
36070 #define SPI_SR_TXC_Msk                      (0x1UL << SPI_SR_TXC_Pos)               /*!< 0x00001000 */
36071 #define SPI_SR_TXC                          SPI_SR_TXC_Msk                          /*!<TxFIFO transmission complete */
36072 #define SPI_SR_RXPLVL_Pos                   (13U)
36073 #define SPI_SR_RXPLVL_Msk                   (0x3UL << SPI_SR_RXPLVL_Pos)            /*!< 0x00006000 */
36074 #define SPI_SR_RXPLVL                       SPI_SR_RXPLVL_Msk                       /*!<RxFIFO Packing Level */
36075 #define SPI_SR_RXPLVL_0                     (0x1UL << SPI_SR_RXPLVL_Pos)            /*!< 0x00002000 */
36076 #define SPI_SR_RXPLVL_1                     (0x2UL << SPI_SR_RXPLVL_Pos)            /*!< 0x00004000 */
36077 #define SPI_SR_RXWNE_Pos                    (15U)
36078 #define SPI_SR_RXWNE_Msk                    (0x1UL << SPI_SR_RXWNE_Pos)             /*!< 0x00008000 */
36079 #define SPI_SR_RXWNE                        SPI_SR_RXWNE_Msk                        /*!<Rx FIFO Word Not Empty */
36080 #define SPI_SR_CTSIZE_Pos                   (16U)
36081 #define SPI_SR_CTSIZE_Msk                   (0xFFFFUL << SPI_SR_CTSIZE_Pos)         /*!< 0xFFFF0000 */
36082 #define SPI_SR_CTSIZE                       SPI_SR_CTSIZE_Msk                       /*!<Number of data frames remaining in TSIZE */
36083 
36084 /*******************  Bit definition for SPI_IFCR register  *******************/
36085 #define SPI_IFCR_EOTC_Pos                   (3U)
36086 #define SPI_IFCR_EOTC_Msk                   (0x1UL << SPI_IFCR_EOTC_Pos)            /*!< 0x00000008 */
36087 #define SPI_IFCR_EOTC                       SPI_IFCR_EOTC_Msk                       /*!<End Of Transfer flag clear */
36088 #define SPI_IFCR_TXTFC_Pos                  (4U)
36089 #define SPI_IFCR_TXTFC_Msk                  (0x1UL << SPI_IFCR_TXTFC_Pos)           /*!< 0x00000010 */
36090 #define SPI_IFCR_TXTFC                      SPI_IFCR_TXTFC_Msk                      /*!<Transmission Transfer Filled flag clear */
36091 #define SPI_IFCR_UDRC_Pos                   (5U)
36092 #define SPI_IFCR_UDRC_Msk                   (0x1UL << SPI_IFCR_UDRC_Pos)            /*!< 0x00000020 */
36093 #define SPI_IFCR_UDRC                       SPI_IFCR_UDRC_Msk                       /*!<Underrun flag clear */
36094 #define SPI_IFCR_OVRC_Pos                   (6U)
36095 #define SPI_IFCR_OVRC_Msk                   (0x1UL << SPI_IFCR_OVRC_Pos)            /*!< 0x00000040 */
36096 #define SPI_IFCR_OVRC                       SPI_IFCR_OVRC_Msk                       /*!<Overrun flag clear */
36097 #define SPI_IFCR_CRCEC_Pos                  (7U)
36098 #define SPI_IFCR_CRCEC_Msk                  (0x1UL << SPI_IFCR_CRCEC_Pos)           /*!< 0x00000080 */
36099 #define SPI_IFCR_CRCEC                      SPI_IFCR_CRCEC_Msk                      /*!<CRC Error flag clear */
36100 #define SPI_IFCR_TIFREC_Pos                 (8U)
36101 #define SPI_IFCR_TIFREC_Msk                 (0x1UL << SPI_IFCR_TIFREC_Pos)          /*!< 0x00000100 */
36102 #define SPI_IFCR_TIFREC                     SPI_IFCR_TIFREC_Msk                     /*!<TI frame format error flag clear */
36103 #define SPI_IFCR_MODFC_Pos                  (9U)
36104 #define SPI_IFCR_MODFC_Msk                  (0x1UL << SPI_IFCR_MODFC_Pos)           /*!< 0x00000200 */
36105 #define SPI_IFCR_MODFC                      SPI_IFCR_MODFC_Msk                      /*!<Mode Fault flag clear */
36106 #define SPI_IFCR_SUSPC_Pos                  (11U)
36107 #define SPI_IFCR_SUSPC_Msk                  (0x1UL << SPI_IFCR_SUSPC_Pos)           /*!< 0x00000800 */
36108 #define SPI_IFCR_SUSPC                      SPI_IFCR_SUSPC_Msk                      /*!<SUSPend flag clear */
36109 
36110 /*******************  Bit definition for SPI_TXDR register  *******************/
36111 #define SPI_TXDR_TXDR_Pos                   (0U)
36112 #define SPI_TXDR_TXDR_Msk                   (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos)     /*!< 0xFFFFFFFF */
36113 #define SPI_TXDR_TXDR                       SPI_TXDR_TXDR_Msk                       /* Transmit Data Register */
36114 
36115 /*******************  Bit definition for SPI_RXDR register  *******************/
36116 #define SPI_RXDR_RXDR_Pos                   (0U)
36117 #define SPI_RXDR_RXDR_Msk                   (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos)     /*!< 0xFFFFFFFF */
36118 #define SPI_RXDR_RXDR                       SPI_RXDR_RXDR_Msk                       /* Receive Data Register */
36119 
36120 /*******************  Bit definition for SPI_CRCPOLY register  ****************/
36121 #define SPI_CRCPOLY_CRCPOLY_Pos             (0U)
36122 #define SPI_CRCPOLY_CRCPOLY_Msk             (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos) /*!< 0xFFFFFFFF */
36123 #define SPI_CRCPOLY_CRCPOLY                 SPI_CRCPOLY_CRCPOLY_Msk                 /* CRC Polynomial register */
36124 
36125 /*******************  Bit definition for SPI_TXCRC register  ******************/
36126 #define SPI_TXCRC_TXCRC_Pos                 (0U)
36127 #define SPI_TXCRC_TXCRC_Msk                 (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos)   /*!< 0xFFFFFFFF */
36128 #define SPI_TXCRC_TXCRC                     SPI_TXCRC_TXCRC_Msk                     /* CRCRegister for transmitter */
36129 
36130 /*******************  Bit definition for SPI_RXCRC register  ******************/
36131 #define SPI_RXCRC_RXCRC_Pos                 (0U)
36132 #define SPI_RXCRC_RXCRC_Msk                 (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos)   /*!< 0xFFFFFFFF */
36133 #define SPI_RXCRC_RXCRC                     SPI_RXCRC_RXCRC_Msk                     /* CRCRegister for receiver */
36134 
36135 /*******************  Bit definition for SPI_UDRDR register  ******************/
36136 #define SPI_UDRDR_UDRDR_Pos                 (0U)
36137 #define SPI_UDRDR_UDRDR_Msk                 (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos)   /*!< 0xFFFFFFFF */
36138 #define SPI_UDRDR_UDRDR                     SPI_UDRDR_UDRDR_Msk                     /* Data at slave underrun condition */
36139 
36140 /*******************  Bits definition for SPI_I2SCFGR register  ***************/
36141 #define SPI_I2SCFGR_I2SMOD_Pos              (0U)
36142 #define SPI_I2SCFGR_I2SMOD_Msk              (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)        /*!< 0x00000001 */
36143 #define SPI_I2SCFGR_I2SMOD                  SPI_I2SCFGR_I2SMOD_Msk                  /*!<I2S mode selection */
36144 #define SPI_I2SCFGR_I2SCFG_Pos              (1U)
36145 #define SPI_I2SCFGR_I2SCFG_Msk              (0x7UL << SPI_I2SCFGR_I2SCFG_Pos)        /*!< 0x0000000E */
36146 #define SPI_I2SCFGR_I2SCFG                  SPI_I2SCFGR_I2SCFG_Msk                  /*!<I2SCFGR[1:0] bits (I2S configuration mode) */
36147 #define SPI_I2SCFGR_I2SCFG_0                (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)        /*!< 0x00000002 */
36148 #define SPI_I2SCFGR_I2SCFG_1                (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)        /*!< 0x00000004 */
36149 #define SPI_I2SCFGR_I2SCFG_2                (0x4UL << SPI_I2SCFGR_I2SCFG_Pos)        /*!< 0x00000008 */
36150 #define SPI_I2SCFGR_I2SSTD_Pos              (4U)
36151 #define SPI_I2SCFGR_I2SSTD_Msk              (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)        /*!< 0x00000030 */
36152 #define SPI_I2SCFGR_I2SSTD                  SPI_I2SCFGR_I2SSTD_Msk                  /*!<I2SSTD[1:0] I2S standard selection */
36153 #define SPI_I2SCFGR_I2SSTD_0                (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)        /*!< 0x00000010 */
36154 #define SPI_I2SCFGR_I2SSTD_1                (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)        /*!< 0x00000020 */
36155 #define SPI_I2SCFGR_PCMSYNC_Pos             (7U)
36156 #define SPI_I2SCFGR_PCMSYNC_Msk             (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)       /*!< 0x00000080 */
36157 #define SPI_I2SCFGR_PCMSYNC                 SPI_I2SCFGR_PCMSYNC_Msk                 /*!<PCM frame synchronization */
36158 #define SPI_I2SCFGR_DATLEN_Pos              (8U)
36159 #define SPI_I2SCFGR_DATLEN_Msk              (0x3UL << SPI_I2SCFGR_DATLEN_Pos)        /*!< 0x00000300 */
36160 #define SPI_I2SCFGR_DATLEN                  SPI_I2SCFGR_DATLEN_Msk                  /*!<DATLEN[1:0] Data length to be transferred */
36161 #define SPI_I2SCFGR_DATLEN_0                (0x1UL << SPI_I2SCFGR_DATLEN_Pos)        /*!< 0x00000100 */
36162 #define SPI_I2SCFGR_DATLEN_1                (0x2UL << SPI_I2SCFGR_DATLEN_Pos)        /*!< 0x00000200 */
36163 #define SPI_I2SCFGR_CHLEN_Pos               (10U)
36164 #define SPI_I2SCFGR_CHLEN_Msk               (0x1UL << SPI_I2SCFGR_CHLEN_Pos)         /*!< 0x00000400 */
36165 #define SPI_I2SCFGR_CHLEN                   SPI_I2SCFGR_CHLEN_Msk                   /*!<Channel length (number of bits per audio channel) */
36166 #define SPI_I2SCFGR_CKPOL_Pos               (11U)
36167 #define SPI_I2SCFGR_CKPOL_Msk               (0x1UL << SPI_I2SCFGR_CKPOL_Pos)         /*!< 0x00000800 */
36168 #define SPI_I2SCFGR_CKPOL                   SPI_I2SCFGR_CKPOL_Msk                   /*!<Serial audio clock polarity */
36169 #define SPI_I2SCFGR_FIXCH_Pos               (12U)
36170 #define SPI_I2SCFGR_FIXCH_Msk               (0x1UL << SPI_I2SCFGR_FIXCH_Pos)         /*!< 0x00001000 */
36171 #define SPI_I2SCFGR_FIXCH                   SPI_I2SCFGR_FIXCH_Msk                   /*!<Fixed channel length in SLAVE */
36172 #define SPI_I2SCFGR_WSINV_Pos               (13U)
36173 #define SPI_I2SCFGR_WSINV_Msk               (0x1UL << SPI_I2SCFGR_WSINV_Pos)         /*!< 0x00002000 */
36174 #define SPI_I2SCFGR_WSINV                   SPI_I2SCFGR_WSINV_Msk                   /*!<Word select inversion */
36175 #define SPI_I2SCFGR_DATFMT_Pos              (14U)
36176 #define SPI_I2SCFGR_DATFMT_Msk              (0x1UL << SPI_I2SCFGR_DATFMT_Pos)        /*!< 0x00003000 */
36177 #define SPI_I2SCFGR_DATFMT                  SPI_I2SCFGR_DATFMT_Msk                  /*!<Data format */
36178 #define SPI_I2SCFGR_I2SDIV_Pos              (16U)
36179 #define SPI_I2SCFGR_I2SDIV_Msk              (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos)       /*!< 0x00FF0000 */
36180 #define SPI_I2SCFGR_I2SDIV                  SPI_I2SCFGR_I2SDIV_Msk                  /*!<I2S Linear prescaler */
36181 #define SPI_I2SCFGR_ODD_Pos                 (24U)
36182 #define SPI_I2SCFGR_ODD_Msk                 (0x1UL << SPI_I2SCFGR_ODD_Pos)           /*!< 0x01000000 */
36183 #define SPI_I2SCFGR_ODD                     SPI_I2SCFGR_ODD_Msk                     /*!<Odd factor for the prescaler */
36184 #define SPI_I2SCFGR_MCKOE_Pos               (25U)
36185 #define SPI_I2SCFGR_MCKOE_Msk               (0x1UL << SPI_I2SCFGR_MCKOE_Pos)         /*!< 0x02000000 */
36186 #define SPI_I2SCFGR_MCKOE                   SPI_I2SCFGR_MCKOE_Msk                   /*!<Master Clock Output Enable */
36187 
36188 
36189 /******************************************************************************/
36190 /*                                                                            */
36191 /*                              SPDIF-RX Interface                            */
36192 /*                                                                            */
36193 /******************************************************************************/
36194 /********************  Bit definition for SPDIF_CR register  ******************/
36195 #define SPDIFRX_CR_SPDIFRXEN_Pos       (0U)
36196 #define SPDIFRX_CR_SPDIFRXEN_Msk       (0x3UL << SPDIFRX_CR_SPDIFRXEN_Pos)     /*!< 0x00000003 */
36197 #define SPDIFRX_CR_SPDIFRXEN           SPDIFRX_CR_SPDIFRXEN_Msk                /*!<Peripheral Block Enable                      */
36198 #define SPDIFRX_CR_SPDIFRXEN_0         (0x01UL << SPDIFRX_CR_SPDIFRXEN_Pos)    /*!< 0x00000001 */
36199 #define SPDIFRX_CR_SPDIFRXEN_1         (0x02UL << SPDIFRX_CR_SPDIFRXEN_Pos)    /*!< 0x00000002 */
36200 #define SPDIFRX_CR_RXDMAEN_Pos         (2U)
36201 #define SPDIFRX_CR_RXDMAEN_Msk         (0x1UL << SPDIFRX_CR_RXDMAEN_Pos)       /*!< 0x00000004 */
36202 #define SPDIFRX_CR_RXDMAEN             SPDIFRX_CR_RXDMAEN_Msk                  /*!<Receiver DMA Enable for data flow            */
36203 #define SPDIFRX_CR_RXSTEO_Pos          (3U)
36204 #define SPDIFRX_CR_RXSTEO_Msk          (0x1UL << SPDIFRX_CR_RXSTEO_Pos)        /*!< 0x00000008 */
36205 #define SPDIFRX_CR_RXSTEO              SPDIFRX_CR_RXSTEO_Msk                   /*!<Stereo Mode                                  */
36206 #define SPDIFRX_CR_DRFMT_Pos           (4U)
36207 #define SPDIFRX_CR_DRFMT_Msk           (0x3UL << SPDIFRX_CR_DRFMT_Pos)         /*!< 0x00000030 */
36208 #define SPDIFRX_CR_DRFMT               SPDIFRX_CR_DRFMT_Msk                    /*!<RX Data format                               */
36209 #define SPDIFRX_CR_PMSK_Pos            (6U)
36210 #define SPDIFRX_CR_PMSK_Msk            (0x1UL << SPDIFRX_CR_PMSK_Pos)          /*!< 0x00000040 */
36211 #define SPDIFRX_CR_PMSK                SPDIFRX_CR_PMSK_Msk                     /*!<Mask Parity error bit                        */
36212 #define SPDIFRX_CR_VMSK_Pos            (7U)
36213 #define SPDIFRX_CR_VMSK_Msk            (0x1UL << SPDIFRX_CR_VMSK_Pos)          /*!< 0x00000080 */
36214 #define SPDIFRX_CR_VMSK                SPDIFRX_CR_VMSK_Msk                     /*!<Mask of Validity bit                         */
36215 #define SPDIFRX_CR_CUMSK_Pos           (8U)
36216 #define SPDIFRX_CR_CUMSK_Msk           (0x1UL << SPDIFRX_CR_CUMSK_Pos)         /*!< 0x00000100 */
36217 #define SPDIFRX_CR_CUMSK               SPDIFRX_CR_CUMSK_Msk                    /*!<Mask of channel status and user bits         */
36218 #define SPDIFRX_CR_PTMSK_Pos           (9U)
36219 #define SPDIFRX_CR_PTMSK_Msk           (0x1UL << SPDIFRX_CR_PTMSK_Pos)         /*!< 0x00000200 */
36220 #define SPDIFRX_CR_PTMSK               SPDIFRX_CR_PTMSK_Msk                    /*!<Mask of Preamble Type bits                   */
36221 #define SPDIFRX_CR_CBDMAEN_Pos         (10U)
36222 #define SPDIFRX_CR_CBDMAEN_Msk         (0x1UL << SPDIFRX_CR_CBDMAEN_Pos)       /*!< 0x00000400 */
36223 #define SPDIFRX_CR_CBDMAEN             SPDIFRX_CR_CBDMAEN_Msk                  /*!<Control Buffer DMA ENable for control flow   */
36224 #define SPDIFRX_CR_CHSEL_Pos           (11U)
36225 #define SPDIFRX_CR_CHSEL_Msk           (0x1UL << SPDIFRX_CR_CHSEL_Pos)         /*!< 0x00000800 */
36226 #define SPDIFRX_CR_CHSEL               SPDIFRX_CR_CHSEL_Msk                    /*!<Channel Selection                            */
36227 #define SPDIFRX_CR_NBTR_Pos            (12U)
36228 #define SPDIFRX_CR_NBTR_Msk            (0x3UL << SPDIFRX_CR_NBTR_Pos)          /*!< 0x00003000 */
36229 #define SPDIFRX_CR_NBTR                SPDIFRX_CR_NBTR_Msk                     /*!<Maximum allowed re-tries during synchronization phase */
36230 #define SPDIFRX_CR_WFA_Pos             (14U)
36231 #define SPDIFRX_CR_WFA_Msk             (0x1UL << SPDIFRX_CR_WFA_Pos)           /*!< 0x00004000 */
36232 #define SPDIFRX_CR_WFA                 SPDIFRX_CR_WFA_Msk                      /*!<Wait For Activity     */
36233 #define SPDIFRX_CR_INSEL_Pos           (16U)
36234 #define SPDIFRX_CR_INSEL_Msk           (0x7UL << SPDIFRX_CR_INSEL_Pos)         /*!< 0x00070000 */
36235 #define SPDIFRX_CR_INSEL               SPDIFRX_CR_INSEL_Msk                    /*!<SPDIF input selection */
36236 #define SPDIFRX_CR_CKSEN_Pos           (20U)
36237 #define SPDIFRX_CR_CKSEN_Msk           (0x1UL << SPDIFRX_CR_CKSEN_Pos)         /*!< 0x00100000 */
36238 #define SPDIFRX_CR_CKSEN               SPDIFRX_CR_CKSEN_Msk                    /*!<Symbol Clock Enable */
36239 #define SPDIFRX_CR_CKSBKPEN_Pos        (21U)
36240 #define SPDIFRX_CR_CKSBKPEN_Msk        (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos)      /*!< 0x00200000 */
36241 #define SPDIFRX_CR_CKSBKPEN            SPDIFRX_CR_CKSBKPEN_Msk                 /*!<Backup Symbol Clock Enable */
36242 
36243 /*******************  Bit definition for SPDIFRX_IMR register  *******************/
36244 #define SPDIFRX_IMR_RXNEIE_Pos         (0U)
36245 #define SPDIFRX_IMR_RXNEIE_Msk         (0x1UL << SPDIFRX_IMR_RXNEIE_Pos)       /*!< 0x00000001 */
36246 #define SPDIFRX_IMR_RXNEIE             SPDIFRX_IMR_RXNEIE_Msk                  /*!<RXNE interrupt enable                              */
36247 #define SPDIFRX_IMR_CSRNEIE_Pos        (1U)
36248 #define SPDIFRX_IMR_CSRNEIE_Msk        (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos)      /*!< 0x00000002 */
36249 #define SPDIFRX_IMR_CSRNEIE            SPDIFRX_IMR_CSRNEIE_Msk                 /*!<Control Buffer Ready Interrupt Enable              */
36250 #define SPDIFRX_IMR_PERRIE_Pos         (2U)
36251 #define SPDIFRX_IMR_PERRIE_Msk         (0x1UL << SPDIFRX_IMR_PERRIE_Pos)       /*!< 0x00000004 */
36252 #define SPDIFRX_IMR_PERRIE             SPDIFRX_IMR_PERRIE_Msk                  /*!<Parity error interrupt enable                      */
36253 #define SPDIFRX_IMR_OVRIE_Pos          (3U)
36254 #define SPDIFRX_IMR_OVRIE_Msk          (0x1UL << SPDIFRX_IMR_OVRIE_Pos)        /*!< 0x00000008 */
36255 #define SPDIFRX_IMR_OVRIE              SPDIFRX_IMR_OVRIE_Msk                   /*!<Overrun error Interrupt Enable                     */
36256 #define SPDIFRX_IMR_SBLKIE_Pos         (4U)
36257 #define SPDIFRX_IMR_SBLKIE_Msk         (0x1UL << SPDIFRX_IMR_SBLKIE_Pos)       /*!< 0x00000010 */
36258 #define SPDIFRX_IMR_SBLKIE             SPDIFRX_IMR_SBLKIE_Msk                  /*!<Synchronization Block Detected Interrupt Enable    */
36259 #define SPDIFRX_IMR_SYNCDIE_Pos        (5U)
36260 #define SPDIFRX_IMR_SYNCDIE_Msk        (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos)      /*!< 0x00000020 */
36261 #define SPDIFRX_IMR_SYNCDIE            SPDIFRX_IMR_SYNCDIE_Msk                 /*!<Synchronization Done                               */
36262 #define SPDIFRX_IMR_IFEIE_Pos          (6U)
36263 #define SPDIFRX_IMR_IFEIE_Msk          (0x1UL << SPDIFRX_IMR_IFEIE_Pos)        /*!< 0x00000040 */
36264 #define SPDIFRX_IMR_IFEIE              SPDIFRX_IMR_IFEIE_Msk                   /*!<Serial Interface Error Interrupt Enable            */
36265 
36266 /*******************  Bit definition for SPDIFRX_SR register  *******************/
36267 #define SPDIFRX_SR_RXNE_Pos            (0U)
36268 #define SPDIFRX_SR_RXNE_Msk            (0x1UL << SPDIFRX_SR_RXNE_Pos)          /*!< 0x00000001 */
36269 #define SPDIFRX_SR_RXNE                SPDIFRX_SR_RXNE_Msk                     /*!<Read data register not empty                          */
36270 #define SPDIFRX_SR_CSRNE_Pos           (1U)
36271 #define SPDIFRX_SR_CSRNE_Msk           (0x1UL << SPDIFRX_SR_CSRNE_Pos)         /*!< 0x00000002 */
36272 #define SPDIFRX_SR_CSRNE               SPDIFRX_SR_CSRNE_Msk                    /*!<The Control Buffer register is not empty              */
36273 #define SPDIFRX_SR_PERR_Pos            (2U)
36274 #define SPDIFRX_SR_PERR_Msk            (0x1UL << SPDIFRX_SR_PERR_Pos)          /*!< 0x00000004 */
36275 #define SPDIFRX_SR_PERR                SPDIFRX_SR_PERR_Msk                     /*!<Parity error                                          */
36276 #define SPDIFRX_SR_OVR_Pos             (3U)
36277 #define SPDIFRX_SR_OVR_Msk             (0x1UL << SPDIFRX_SR_OVR_Pos)           /*!< 0x00000008 */
36278 #define SPDIFRX_SR_OVR                 SPDIFRX_SR_OVR_Msk                      /*!<Overrun error                                         */
36279 #define SPDIFRX_SR_SBD_Pos             (4U)
36280 #define SPDIFRX_SR_SBD_Msk             (0x1UL << SPDIFRX_SR_SBD_Pos)           /*!< 0x00000010 */
36281 #define SPDIFRX_SR_SBD                 SPDIFRX_SR_SBD_Msk                      /*!<Synchronization Block Detected                        */
36282 #define SPDIFRX_SR_SYNCD_Pos           (5U)
36283 #define SPDIFRX_SR_SYNCD_Msk           (0x1UL << SPDIFRX_SR_SYNCD_Pos)         /*!< 0x00000020 */
36284 #define SPDIFRX_SR_SYNCD               SPDIFRX_SR_SYNCD_Msk                    /*!<Synchronization Done                                  */
36285 #define SPDIFRX_SR_FERR_Pos            (6U)
36286 #define SPDIFRX_SR_FERR_Msk            (0x1UL << SPDIFRX_SR_FERR_Pos)          /*!< 0x00000040 */
36287 #define SPDIFRX_SR_FERR                SPDIFRX_SR_FERR_Msk                     /*!<Framing error                                         */
36288 #define SPDIFRX_SR_SERR_Pos            (7U)
36289 #define SPDIFRX_SR_SERR_Msk            (0x1UL << SPDIFRX_SR_SERR_Pos)          /*!< 0x00000080 */
36290 #define SPDIFRX_SR_SERR                SPDIFRX_SR_SERR_Msk                     /*!<Synchronization error                                 */
36291 #define SPDIFRX_SR_TERR_Pos            (8U)
36292 #define SPDIFRX_SR_TERR_Msk            (0x1UL << SPDIFRX_SR_TERR_Pos)          /*!< 0x00000100 */
36293 #define SPDIFRX_SR_TERR                SPDIFRX_SR_TERR_Msk                     /*!<Time-out error                                        */
36294 #define SPDIFRX_SR_WIDTH5_Pos          (16U)
36295 #define SPDIFRX_SR_WIDTH5_Msk          (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos)     /*!< 0x7FFF0000 */
36296 #define SPDIFRX_SR_WIDTH5              SPDIFRX_SR_WIDTH5_Msk                   /*!<Duration of 5 symbols counted with spdif_clk          */
36297 
36298 /*******************  Bit definition for SPDIFRX_IFCR register  *******************/
36299 #define SPDIFRX_IFCR_PERRCF_Pos        (2U)
36300 #define SPDIFRX_IFCR_PERRCF_Msk        (0x1UL << SPDIFRX_IFCR_PERRCF_Pos)      /*!< 0x00000004 */
36301 #define SPDIFRX_IFCR_PERRCF            SPDIFRX_IFCR_PERRCF_Msk                 /*!<Clears the Parity error flag                         */
36302 #define SPDIFRX_IFCR_OVRCF_Pos         (3U)
36303 #define SPDIFRX_IFCR_OVRCF_Msk         (0x1UL << SPDIFRX_IFCR_OVRCF_Pos)       /*!< 0x00000008 */
36304 #define SPDIFRX_IFCR_OVRCF             SPDIFRX_IFCR_OVRCF_Msk                  /*!<Clears the Overrun error flag                        */
36305 #define SPDIFRX_IFCR_SBDCF_Pos         (4U)
36306 #define SPDIFRX_IFCR_SBDCF_Msk         (0x1UL << SPDIFRX_IFCR_SBDCF_Pos)       /*!< 0x00000010 */
36307 #define SPDIFRX_IFCR_SBDCF             SPDIFRX_IFCR_SBDCF_Msk                  /*!<Clears the Synchronization Block Detected flag       */
36308 #define SPDIFRX_IFCR_SYNCDCF_Pos       (5U)
36309 #define SPDIFRX_IFCR_SYNCDCF_Msk       (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos)     /*!< 0x00000020 */
36310 #define SPDIFRX_IFCR_SYNCDCF           SPDIFRX_IFCR_SYNCDCF_Msk                /*!<Clears the Synchronization Done flag                 */
36311 
36312 /*******************  Bit definition for SPDIFRX_DR register     (DRFMT = 0b00 case) *******************/
36313 #define SPDIFRX_DR0_DR_Pos             (0U)
36314 #define SPDIFRX_DR0_DR_Msk             (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos)      /*!< 0x00FFFFFF */
36315 #define SPDIFRX_DR0_DR                 SPDIFRX_DR0_DR_Msk                      /*!<Data value            */
36316 #define SPDIFRX_DR0_PE_Pos             (24U)
36317 #define SPDIFRX_DR0_PE_Msk             (0x1UL << SPDIFRX_DR0_PE_Pos)           /*!< 0x01000000 */
36318 #define SPDIFRX_DR0_PE                 SPDIFRX_DR0_PE_Msk                      /*!<Parity Error bit      */
36319 #define SPDIFRX_DR0_V_Pos              (25U)
36320 #define SPDIFRX_DR0_V_Msk              (0x1UL << SPDIFRX_DR0_V_Pos)            /*!< 0x02000000 */
36321 #define SPDIFRX_DR0_V                  SPDIFRX_DR0_V_Msk                       /*!<Validity bit          */
36322 #define SPDIFRX_DR0_U_Pos              (26U)
36323 #define SPDIFRX_DR0_U_Msk              (0x1UL << SPDIFRX_DR0_U_Pos)            /*!< 0x04000000 */
36324 #define SPDIFRX_DR0_U                  SPDIFRX_DR0_U_Msk                       /*!<User bit              */
36325 #define SPDIFRX_DR0_C_Pos              (27U)
36326 #define SPDIFRX_DR0_C_Msk              (0x1UL << SPDIFRX_DR0_C_Pos)            /*!< 0x08000000 */
36327 #define SPDIFRX_DR0_C                  SPDIFRX_DR0_C_Msk                       /*!<Channel Status bit    */
36328 #define SPDIFRX_DR0_PT_Pos             (28U)
36329 #define SPDIFRX_DR0_PT_Msk             (0x3UL << SPDIFRX_DR0_PT_Pos)           /*!< 0x30000000 */
36330 #define SPDIFRX_DR0_PT                 SPDIFRX_DR0_PT_Msk                      /*!<Preamble Type         */
36331 
36332 /*******************  Bit definition for SPDIFRX_DR register     (DRFMT = 0b01 case) *******************/
36333 #define SPDIFRX_DR1_DR_Pos             (8U)
36334 #define SPDIFRX_DR1_DR_Msk             (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos)      /*!< 0xFFFFFF00 */
36335 #define SPDIFRX_DR1_DR                 SPDIFRX_DR1_DR_Msk                      /*!<Data value            */
36336 #define SPDIFRX_DR1_PT_Pos             (4U)
36337 #define SPDIFRX_DR1_PT_Msk             (0x3UL << SPDIFRX_DR1_PT_Pos)           /*!< 0x00000030 */
36338 #define SPDIFRX_DR1_PT                 SPDIFRX_DR1_PT_Msk                      /*!<Preamble Type         */
36339 #define SPDIFRX_DR1_C_Pos              (3U)
36340 #define SPDIFRX_DR1_C_Msk              (0x1UL << SPDIFRX_DR1_C_Pos)            /*!< 0x00000008 */
36341 #define SPDIFRX_DR1_C                  SPDIFRX_DR1_C_Msk                       /*!<Channel Status bit    */
36342 #define SPDIFRX_DR1_U_Pos              (2U)
36343 #define SPDIFRX_DR1_U_Msk              (0x1UL << SPDIFRX_DR1_U_Pos)            /*!< 0x00000004 */
36344 #define SPDIFRX_DR1_U                  SPDIFRX_DR1_U_Msk                       /*!<User bit              */
36345 #define SPDIFRX_DR1_V_Pos              (1U)
36346 #define SPDIFRX_DR1_V_Msk              (0x1UL << SPDIFRX_DR1_V_Pos)            /*!< 0x00000002 */
36347 #define SPDIFRX_DR1_V                  SPDIFRX_DR1_V_Msk                       /*!<Validity bit          */
36348 #define SPDIFRX_DR1_PE_Pos             (0U)
36349 #define SPDIFRX_DR1_PE_Msk             (0x1UL << SPDIFRX_DR1_PE_Pos)           /*!< 0x00000001 */
36350 #define SPDIFRX_DR1_PE                 SPDIFRX_DR1_PE_Msk                      /*!<Parity Error bit      */
36351 
36352 /*******************  Bit definition for SPDIFRX_DR register     (DRFMT = 0b10 case) *******************/
36353 #define SPDIFRX_DR1_DRNL1_Pos          (16U)
36354 #define SPDIFRX_DR1_DRNL1_Msk          (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos)     /*!< 0xFFFF0000 */
36355 #define SPDIFRX_DR1_DRNL1              SPDIFRX_DR1_DRNL1_Msk                   /*!<Data value Channel B      */
36356 #define SPDIFRX_DR1_DRNL2_Pos          (0U)
36357 #define SPDIFRX_DR1_DRNL2_Msk          (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos)     /*!< 0x0000FFFF */
36358 #define SPDIFRX_DR1_DRNL2              SPDIFRX_DR1_DRNL2_Msk                   /*!<Data value Channel A      */
36359 
36360 /*******************  Bit definition for SPDIFRX_CSR register   *******************/
36361 #define SPDIFRX_CSR_USR_Pos            (0U)
36362 #define SPDIFRX_CSR_USR_Msk            (0xFFFFUL << SPDIFRX_CSR_USR_Pos)       /*!< 0x0000FFFF */
36363 #define SPDIFRX_CSR_USR                SPDIFRX_CSR_USR_Msk                     /*!<User data information           */
36364 #define SPDIFRX_CSR_CS_Pos             (16U)
36365 #define SPDIFRX_CSR_CS_Msk             (0xFFUL << SPDIFRX_CSR_CS_Pos)          /*!< 0x00FF0000 */
36366 #define SPDIFRX_CSR_CS                 SPDIFRX_CSR_CS_Msk                      /*!<Channel A status information    */
36367 #define SPDIFRX_CSR_SOB_Pos            (24U)
36368 #define SPDIFRX_CSR_SOB_Msk            (0x1UL << SPDIFRX_CSR_SOB_Pos)          /*!< 0x01000000 */
36369 #define SPDIFRX_CSR_SOB                SPDIFRX_CSR_SOB_Msk                     /*!<Start Of Block                  */
36370 
36371 /*******************  Bit definition for SPDIFRX_DIR register    *******************/
36372 #define SPDIFRX_DIR_THI_Pos            (0U)
36373 #define SPDIFRX_DIR_THI_Msk            (0x1FFFUL << SPDIFRX_DIR_THI_Pos)       /*!< 0x00001FFF */
36374 #define SPDIFRX_DIR_THI                SPDIFRX_DIR_THI_Msk                     /*!<Threshold LOW      */
36375 #define SPDIFRX_DIR_TLO_Pos            (16U)
36376 #define SPDIFRX_DIR_TLO_Msk            (0x1FFFUL << SPDIFRX_DIR_TLO_Pos)       /*!< 0x1FFF0000 */
36377 #define SPDIFRX_DIR_TLO                SPDIFRX_DIR_TLO_Msk                     /*!<Threshold HIGH     */
36378 
36379 
36380 /******************************************************************************/
36381 /*                                                                            */
36382 /*                                 SYSCFG                                     */
36383 /*                                                                            */
36384 /******************************************************************************/
36385 /******************  Bit definition for SYSCFG_BOOTCR register  ****************/
36386 #define SYSCFG_BOOTCR_BOOT0_PD_Pos          (0U)
36387 #define SYSCFG_BOOTCR_BOOT0_PD_Msk          (0x1UL << SYSCFG_BOOTCR_BOOT0_PD_Pos)   /*!< 0x00000001 */
36388 #define SYSCFG_BOOTCR_BOOT0_PD              SYSCFG_BOOTCR_BOOT0_PD_Msk              /*!< BOOT0 pin pull-down disable */
36389 #define SYSCFG_BOOTCR_BOOT1_PD_Pos          (1U)
36390 #define SYSCFG_BOOTCR_BOOT1_PD_Msk          (0x1UL << SYSCFG_BOOTCR_BOOT1_PD_Pos)   /*!< 0x00000002 */
36391 #define SYSCFG_BOOTCR_BOOT1_PD              SYSCFG_BOOTCR_BOOT1_PD_Msk              /*!< BOOT1 pin pull-down disable */
36392 
36393 /******************  Bit definition for SYSCFG_CM55CR register  ****************/
36394 #define SYSCFG_CM55CR_FPU_IT_EN_Pos         (0U)
36395 #define SYSCFG_CM55CR_FPU_IT_EN_Msk         (0x3FUL << SYSCFG_CM55CR_FPU_IT_EN_Pos) /*!< 0x0000003F */
36396 #define SYSCFG_CM55CR_FPU_IT_EN             SYSCFG_CM55CR_FPU_IT_EN_Msk             /*!< Enable FPU exception */
36397 #define SYSCFG_CM55CR_FPU_IT_EN_0           (0x1UL << SYSCFG_CM55CR_FPU_IT_EN_Pos)   /*!< 0x00000001 */
36398 #define SYSCFG_CM55CR_FPU_IT_EN_1           (0x2UL << SYSCFG_CM55CR_FPU_IT_EN_Pos)   /*!< 0x00000002 */
36399 #define SYSCFG_CM55CR_FPU_IT_EN_2           (0x4UL << SYSCFG_CM55CR_FPU_IT_EN_Pos)   /*!< 0x00000004 */
36400 #define SYSCFG_CM55CR_FPU_IT_EN_3           (0x8UL << SYSCFG_CM55CR_FPU_IT_EN_Pos)   /*!< 0x00000008 */
36401 #define SYSCFG_CM55CR_FPU_IT_EN_4           (0x10UL << SYSCFG_CM55CR_FPU_IT_EN_Pos)  /*!< 0x00000010 */
36402 #define SYSCFG_CM55CR_FPU_IT_EN_5           (0x20UL << SYSCFG_CM55CR_FPU_IT_EN_Pos)  /*!< 0x00000020 */
36403 #define SYSCFG_CM55CR_LOCKSVTAIRCR_Pos      (16U)
36404 #define SYSCFG_CM55CR_LOCKSVTAIRCR_Msk      (0x1UL << SYSCFG_CM55CR_LOCKSVTAIRCR_Pos) /*!< 0x00010000 */
36405 #define SYSCFG_CM55CR_LOCKSVTAIRCR          SYSCFG_CM55CR_LOCKSVTAIRCR_Msk
36406 #define SYSCFG_CM55CR_LOCKNSVTOR_Pos        (17U)
36407 #define SYSCFG_CM55CR_LOCKNSVTOR_Msk        (0x1UL << SYSCFG_CM55CR_LOCKNSVTOR_Pos) /*!< 0x00020000 */
36408 #define SYSCFG_CM55CR_LOCKNSVTOR            SYSCFG_CM55CR_LOCKNSVTOR_Msk            /*!< Prevent changes to the non-secure vector table base address */
36409 #define SYSCFG_CM55CR_LOCKSMPU_Pos          (18U)
36410 #define SYSCFG_CM55CR_LOCKSMPU_Msk          (0x1UL << SYSCFG_CM55CR_LOCKSMPU_Pos)   /*!< 0x00040000 */
36411 #define SYSCFG_CM55CR_LOCKSMPU              SYSCFG_CM55CR_LOCKSMPU_Msk              /*!< Prevent changes to programmed secure MPU memory regions */
36412 #define SYSCFG_CM55CR_LOCKNSMPU_Pos         (19U)
36413 #define SYSCFG_CM55CR_LOCKNSMPU_Msk         (0x1UL << SYSCFG_CM55CR_LOCKNSMPU_Pos)  /*!< 0x00080000 */
36414 #define SYSCFG_CM55CR_LOCKNSMPU             SYSCFG_CM55CR_LOCKNSMPU_Msk             /*!< Prevent changes to programmed non-secure MPU memory regions */
36415 #define SYSCFG_CM55CR_LOCKSAU_Pos           (20U)
36416 #define SYSCFG_CM55CR_LOCKSAU_Msk           (0x1UL << SYSCFG_CM55CR_LOCKSAU_Pos)    /*!< 0x00100000 */
36417 #define SYSCFG_CM55CR_LOCKSAU               SYSCFG_CM55CR_LOCKSAU_Msk               /*!< Prevent changes to secure SAU memory regions already programmed */
36418 #define SYSCFG_CM55CR_LOCKDCAIC_Pos         (21U)
36419 #define SYSCFG_CM55CR_LOCKDCAIC_Msk         (0x1UL << SYSCFG_CM55CR_LOCKDCAIC_Pos)  /*!< 0x00200000 */
36420 #define SYSCFG_CM55CR_LOCKDCAIC             SYSCFG_CM55CR_LOCKDCAIC_Msk
36421 
36422 /******************  Bit definition for SYSCFG_CM55TCMCR register  ***************/
36423 #define SYSCFG_CM55TCMCR_CFGITCMSZ_Pos      (0U)
36424 #define SYSCFG_CM55TCMCR_CFGITCMSZ_Msk      (0xFUL << SYSCFG_CM55TCMCR_CFGITCMSZ_Pos)    /*!< 0x0000000F */
36425 #define SYSCFG_CM55TCMCR_CFGITCMSZ          SYSCFG_CM55TCMCR_CFGITCMSZ_Msk               /*!< Select ITCM memory size */
36426 #define SYSCFG_CM55TCMCR_CFGITCMSZ_0        (0x1UL << SYSCFG_CM55TCMCR_CFGITCMSZ_Pos)    /*!< 0x00000001 */
36427 #define SYSCFG_CM55TCMCR_CFGITCMSZ_1        (0x2UL << SYSCFG_CM55TCMCR_CFGITCMSZ_Pos)    /*!< 0x00000002 */
36428 #define SYSCFG_CM55TCMCR_CFGITCMSZ_2        (0x4UL << SYSCFG_CM55TCMCR_CFGITCMSZ_Pos)    /*!< 0x00000004 */
36429 #define SYSCFG_CM55TCMCR_CFGITCMSZ_3        (0x8UL << SYSCFG_CM55TCMCR_CFGITCMSZ_Pos)    /*!< 0x00000008 */
36430 #define SYSCFG_CM55TCMCR_CFGDTCMSZ_Pos      (4U)
36431 #define SYSCFG_CM55TCMCR_CFGDTCMSZ_Msk      (0xFUL << SYSCFG_CM55TCMCR_CFGDTCMSZ_Pos)    /*!< 0x000000F0 */
36432 #define SYSCFG_CM55TCMCR_CFGDTCMSZ          SYSCFG_CM55TCMCR_CFGDTCMSZ_Msk               /*!< Select DTCM memory size */
36433 #define SYSCFG_CM55TCMCR_CFGDTCMSZ_0        (0x1UL << SYSCFG_CM55TCMCR_CFGDTCMSZ_Pos)    /*!< 0x00000010 */
36434 #define SYSCFG_CM55TCMCR_CFGDTCMSZ_1        (0x2UL << SYSCFG_CM55TCMCR_CFGDTCMSZ_Pos)    /*!< 0x00000020 */
36435 #define SYSCFG_CM55TCMCR_CFGDTCMSZ_2        (0x4UL << SYSCFG_CM55TCMCR_CFGDTCMSZ_Pos)    /*!< 0x00000040 */
36436 #define SYSCFG_CM55TCMCR_CFGDTCMSZ_3        (0x8UL << SYSCFG_CM55TCMCR_CFGDTCMSZ_Pos)    /*!< 0x00000080 */
36437 #define SYSCFG_CM55TCMCR_LOCKTCM_Pos        (16U)
36438 #define SYSCFG_CM55TCMCR_LOCKTCM_Msk        (0x1UL << SYSCFG_CM55TCMCR_LOCKTCM_Pos)      /*!< 0x00010000 */
36439 #define SYSCFG_CM55TCMCR_LOCKTCM            SYSCFG_CM55TCMCR_LOCKTCM_Msk                 /*!< Disable writes to registers associated with the TCM region */
36440 #define SYSCFG_CM55TCMCR_LOCKITGU_Pos       (17U)
36441 #define SYSCFG_CM55TCMCR_LOCKITGU_Msk       (0x1UL << SYSCFG_CM55TCMCR_LOCKITGU_Pos)     /*!< 0x00020000 */
36442 #define SYSCFG_CM55TCMCR_LOCKITGU           SYSCFG_CM55TCMCR_LOCKITGU_Msk                /*!< Disable writes to registers associated with the ITCM interface security/gating */
36443 #define SYSCFG_CM55TCMCR_LOCKDTGU_Pos       (18U)
36444 #define SYSCFG_CM55TCMCR_LOCKDTGU_Msk       (0x1UL << SYSCFG_CM55TCMCR_LOCKDTGU_Pos)     /*!< 0x00040000 */
36445 #define SYSCFG_CM55TCMCR_LOCKDTGU           SYSCFG_CM55TCMCR_LOCKDTGU_Msk                /*!< Disable writes to registers associated with the DTCM interface security/gating. */
36446 #define SYSCFG_CM55TCMCR_ITCMWSDISABLE_Pos  (23U)
36447 #define SYSCFG_CM55TCMCR_ITCMWSDISABLE_Msk  (0x1UL << SYSCFG_CM55TCMCR_ITCMWSDISABLE_Pos) /*!< 0x00800000 */
36448 #define SYSCFG_CM55TCMCR_ITCMWSDISABLE      SYSCFG_CM55TCMCR_ITCMWSDISABLE_Msk            /*!< Disable wait-state applied by default on extended ITCM memory */
36449 #define SYSCFG_CM55TCMCR_DTCMWSDISABLE_Pos  (24U)
36450 #define SYSCFG_CM55TCMCR_DTCMWSDISABLE_Msk  (0x1UL << SYSCFG_CM55TCMCR_DTCMWSDISABLE_Pos) /*!< 0x01000000 */
36451 #define SYSCFG_CM55TCMCR_DTCMWSDISABLE      SYSCFG_CM55TCMCR_DTCMWSDISABLE_Msk            /*!< Disable wait-state applied by default on extended DTCM memory */
36452 
36453 
36454 /******************  Bit definition for SYSCFG_CM55RWMCR register  **************/
36455 #define SYSCFG_CM55RWMCR_RME_TCM_Pos        (0U)
36456 #define SYSCFG_CM55RWMCR_RME_TCM_Msk        (0x1UL << SYSCFG_CM55RWMCR_RME_TCM_Pos)   /*!< 0x00000001 */
36457 #define SYSCFG_CM55RWMCR_RME_TCM            SYSCFG_CM55RWMCR_RME_TCM_Msk              /*!< RW margin enable input for TCM memories */
36458 #define SYSCFG_CM55RWMCR_RM_TCM_Pos         (1U)
36459 #define SYSCFG_CM55RWMCR_RM_TCM_Msk         (0xFUL << SYSCFG_CM55RWMCR_RM_TCM_Pos)    /*!< 0x0000001E */
36460 #define SYSCFG_CM55RWMCR_RM_TCM             SYSCFG_CM55RWMCR_RM_TCM_Msk               /*!< External RW margin inputs for TCM memories */
36461 #define SYSCFG_CM55RWMCR_BC1_TCM_Pos        (5U)
36462 #define SYSCFG_CM55RWMCR_BC1_TCM_Msk        (0x1UL << SYSCFG_CM55RWMCR_BC1_TCM_Pos)   /*!< 0x00000020 */
36463 #define SYSCFG_CM55RWMCR_BC1_TCM            SYSCFG_CM55RWMCR_BC1_TCM_Msk              /*!< Biasing level adjust input recommended for Vnom */
36464 #define SYSCFG_CM55RWMCR_BC2_TCM_Pos        (6U)
36465 #define SYSCFG_CM55RWMCR_BC2_TCM_Msk        (0x1UL << SYSCFG_CM55RWMCR_BC2_TCM_Pos)   /*!< 0x00000040 */
36466 #define SYSCFG_CM55RWMCR_BC2_TCM            SYSCFG_CM55RWMCR_BC2_TCM_Msk              /*!< Biasing level adjust input recommended for Vnom + 10% */
36467 #define SYSCFG_CM55RWMCR_RME_CACHE_Pos      (7U)
36468 #define SYSCFG_CM55RWMCR_RME_CACHE_Msk      (0x1UL << SYSCFG_CM55RWMCR_RME_CACHE_Pos) /*!< 0x00000080 */
36469 #define SYSCFG_CM55RWMCR_RME_CACHE          SYSCFG_CM55RWMCR_RME_CACHE_Msk            /*!< RW margin enable input for caches memories */
36470 #define SYSCFG_CM55RWMCR_RM_CACHE_Pos       (8U)
36471 #define SYSCFG_CM55RWMCR_RM_CACHE_Msk       (0xFUL << SYSCFG_CM55RWMCR_RM_CACHE_Pos)  /*!< 0x00000F00 */
36472 #define SYSCFG_CM55RWMCR_RM_CACHE           SYSCFG_CM55RWMCR_RM_CACHE_Msk             /*!< External read/write (RW) margin inputs for caches memories */
36473 #define SYSCFG_CM55RWMCR_BC1_CACHE_Pos      (12U)
36474 #define SYSCFG_CM55RWMCR_BC1_CACHE_Msk      (0x1UL << SYSCFG_CM55RWMCR_BC1_CACHE_Pos) /*!< 0x0001000 */
36475 #define SYSCFG_CM55RWMCR_BC1_CACHE          SYSCFG_CM55RWMCR_BC1_CACHE_Msk            /*!< Biasing level adjust input recommended for Vnom */
36476 #define SYSCFG_CM55RWMCR_BC2_CACHE_Pos      (13U)
36477 #define SYSCFG_CM55RWMCR_BC2_CACHE_Msk      (0x1UL << SYSCFG_CM55RWMCR_BC2_CACHE_Pos) /*!< 0x00002000 */
36478 #define SYSCFG_CM55RWMCR_BC2_CACHE          SYSCFG_CM55RWMCR_BC2_CACHE_Msk            /*!< Biasing level adjust input recommended for Vnom + 10% */
36479 
36480 /******************  Bit definition for SYSCFG_INITSVTORCR register  **************/
36481 #define SYSCFG_INITSVTORCR_SVTOR_ADDR_Pos   (7U)
36482 #define SYSCFG_INITSVTORCR_SVTOR_ADDR_Msk   (0x1FFFFFFUL << SYSCFG_INITSVTORCR_SVTOR_ADDR_Pos)   /*!< 0xFFFFFF80 */
36483 #define SYSCFG_INITSVTORCR_SVTOR_ADDR       SYSCFG_INITSVTORCR_SVTOR_ADDR_Msk                    /*!< Secure vector table base address */
36484 
36485 /******************  Bit definition for SYSCFG_INITNSVTORCR register  **************/
36486 #define SYSCFG_INITNSVTORCR_NSVTOR_ADDR_Pos  (7U)
36487 #define SYSCFG_INITNSVTORCR_NSVTOR_ADDR_Msk  (0x1FFFFFFUL << SYSCFG_INITNSVTORCR_NSVTOR_ADDR_Pos)  /*!< 0xFFFFFF80 */
36488 #define SYSCFG_INITNSVTORCR_NSVTOR_ADDR      SYSCFG_INITNSVTORCR_NSVTOR_ADDR_Msk                   /*!< Non-Secure vector table base address */
36489 
36490 /******************  Bit definition for SYSCFG_CM55RSTCR register  **************/
36491 #define SYSCFG_CM55RSTCR_CORE_RESET_TYPE_Pos     (0U)
36492 #define SYSCFG_CM55RSTCR_CORE_RESET_TYPE_Msk     (0x1UL << SYSCFG_CM55RSTCR_CORE_RESET_TYPE_Pos) /*!< 0x00000001 */
36493 #define SYSCFG_CM55RSTCR_CORE_RESET_TYPE         SYSCFG_CM55RSTCR_CORE_RESET_TYPE_Msk            /*!< Select reset to apply on core upon SYSRESETREQ */
36494 #define SYSCFG_CM55RSTCR_LOCKUP_RST_EN_Pos       (1U)
36495 #define SYSCFG_CM55RSTCR_LOCKUP_RST_EN_Msk       (0x1UL << SYSCFG_CM55RSTCR_LOCKUP_RST_EN_Pos)   /*!< 0x00000002 */
36496 #define SYSCFG_CM55RSTCR_LOCKUP_RST_EN           SYSCFG_CM55RSTCR_LOCKUP_RST_EN_Msk              /*!< Select action to perform on a lockup state on the core */
36497 #define SYSCFG_CM55RSTCR_LOCKUP_NMI_EN_Pos       (2U)
36498 #define SYSCFG_CM55RSTCR_LOCKUP_NMI_EN_Msk       (0x1UL << SYSCFG_CM55RSTCR_LOCKUP_NMI_EN_Pos)   /*!< 0x00000004 */
36499 #define SYSCFG_CM55RSTCR_LOCKUP_NMI_EN           SYSCFG_CM55RSTCR_LOCKUP_NMI_EN_Msk              /*!< Select action to perform on a lockup state on the core */
36500 
36501 /******************  Bit definition for SYSCFG_CM55PAHBWPR register  **************/
36502 #define SYSCFG_CM55PAHBWPR_PAHB_ERROR_ACK_Pos       (0U)
36503 #define SYSCFG_CM55PAHBWPR_PAHB_ERROR_ACK_Msk       (0x1UL << SYSCFG_CM55PAHBWPR_PAHB_ERROR_ACK_Pos) /*!< 0x00000001 */
36504 #define SYSCFG_CM55PAHBWPR_PAHB_ERROR_ACK           SYSCFG_CM55PAHBWPR_PAHB_ERROR_ACK_Msk            /*!< Error capture in write posting buffer */
36505 
36506 /******************  Bit definition for SYSCFG_VENCRAMCR register  **************/
36507 #define SYSCFG_VENCRAMCR_VENCRAM_EN_Pos     (0U)
36508 #define SYSCFG_VENCRAMCR_VENCRAM_EN_Msk     (0x1UL << SYSCFG_VENCRAMCR_VENCRAM_EN_Pos)               /*!< 0x00000001 */
36509 #define SYSCFG_VENCRAMCR_VENCRAM_EN         SYSCFG_VENCRAMCR_VENCRAM_EN_Msk                          /*!< VENCRAM allocation VENC if active, or to system (if VENC inactive) */
36510 
36511 /******************  Bit definition for SYSCFG_POTTAMPRSTCR register  **************/
36512 #define SYSCFG_POTTAMPRSTCR_POTTAMPERSETMASK_Pos       (0U)
36513 #define SYSCFG_POTTAMPRSTCR_POTTAMPERSETMASK_Msk       (0x1UL << SYSCFG_POTTAMPRSTCR_POTTAMPERSETMASK_Pos) /*!< 0x00000001 */
36514 #define SYSCFG_POTTAMPRSTCR_POTTAMPERSETMASK           SYSCFG_POTTAMPRSTCR_POTTAMPERSETMASK_Msk            /*!< mask PKA, SAES, CRYP1/2, and HASH reset, in case of potential tamper */
36515 
36516 /******************  Bit definition for SYSCFG_NPUNICQOSCR register  **************/
36517 #define SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_Pos    (0U)
36518 #define SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_Msk    (0xFUL << SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_Pos) /*!< 0x0000000F */
36519 #define SYSCFG_NPUNICQOSCR_NPU1_ARQOSR         SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_Msk           /*!< NPUNIC read QoS information for NPU1 master port */
36520 #define SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_0      (0x1UL << SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_Pos) /*!< 0x00000001 */
36521 #define SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_1      (0x2UL << SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_Pos) /*!< 0x00000002 */
36522 #define SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_2      (0x4UL << SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_Pos) /*!< 0x00000004 */
36523 #define SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_3      (0x8UL << SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_Pos) /*!< 0x00000008 */
36524 
36525 #define SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_Pos    (4U)
36526 #define SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_Msk    (0xFUL << SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_Pos) /*!< 0x0000000F */
36527 #define SYSCFG_NPUNICQOSCR_NPU1_ARQOSW         SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_Msk           /*!< NPUNIC write QoS information for NPU1 master port */
36528 #define SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_0      (0x1UL << SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_Pos) /*!< 0x00000001 */
36529 #define SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_1      (0x2UL << SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_Pos) /*!< 0x00000002 */
36530 #define SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_2      (0x4UL << SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_Pos) /*!< 0x00000004 */
36531 #define SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_3      (0x8UL << SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_Pos) /*!< 0x00000008 */
36532 
36533 #define SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_Pos    (8U)
36534 #define SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_Msk    (0xFUL << SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_Pos) /*!< 0x0000000F */
36535 #define SYSCFG_NPUNICQOSCR_NPU2_ARQOSR         SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_Msk           /*!< NPUNIC read QoS information for NPU2 master port */
36536 #define SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_0      (0x1UL << SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_Pos) /*!< 0x00000001 */
36537 #define SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_1      (0x2UL << SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_Pos) /*!< 0x00000002 */
36538 #define SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_2      (0x4UL << SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_Pos) /*!< 0x00000004 */
36539 #define SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_3      (0x8UL << SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_Pos) /*!< 0x00000008 */
36540 
36541 #define SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_Pos    (12U)
36542 #define SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_Msk    (0xFUL << SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_Pos) /*!< 0x0000000F */
36543 #define SYSCFG_NPUNICQOSCR_NPU2_ARQOSW         SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_Msk           /*!< NPUNIC write QoS information for NPU2 master port */
36544 #define SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_0      (0x1UL << SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_Pos) /*!< 0x00000001 */
36545 #define SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_1      (0x2UL << SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_Pos) /*!< 0x00000002 */
36546 #define SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_2      (0x4UL << SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_Pos) /*!< 0x00000004 */
36547 #define SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_3      (0x8UL << SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_Pos) /*!< 0x00000008 */
36548 
36549 #define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_Pos   (16U)
36550 #define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_Msk   (0xFUL << SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_Pos) /*!< 0x0000000F */
36551 #define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR        SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_Msk           /*!< NPUNIC read QoS information for master port from CPUSS */
36552 #define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_0     (0x1UL << SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_Pos) /*!< 0x00000001 */
36553 #define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_1     (0x2UL << SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_Pos) /*!< 0x00000002 */
36554 #define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_2     (0x4UL << SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_Pos) /*!< 0x00000004 */
36555 #define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_3     (0x8UL << SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_Pos) /*!< 0x00000008 */
36556 
36557 #define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_Pos   (20U)
36558 #define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_Msk   (0xFUL << SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_Pos) /*!< 0x0000000F */
36559 #define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW        SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_Msk           /*!< NPUNIC write QoS information for master port from CPUSS */
36560 #define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_0     (0x1UL << SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_Pos) /*!< 0x00000001 */
36561 #define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_1     (0x2UL << SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_Pos) /*!< 0x00000002 */
36562 #define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_2     (0x4UL << SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_Pos) /*!< 0x00000004 */
36563 #define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_3     (0x8UL << SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_Pos) /*!< 0x00000008 */
36564 
36565 /******************  Bit definition for SYSCFG_ICNEWRCR register  **************/
36566 #define SYSCFG_ICNEWRCR_SDMMC1_EARLY_WR_RSP_ENABLE_Pos     (0U)
36567 #define SYSCFG_ICNEWRCR_SDMMC1_EARLY_WR_RSP_ENABLE_Msk     (0x1UL << SYSCFG_ICNEWRCR_SDMMC1_EARLY_WR_RSP_ENABLE_Pos) /*!< 0x00000001 */
36568 #define SYSCFG_ICNEWRCR_SDMMC1_EARLY_WR_RSP_ENABLE         SYSCFG_ICNEWRCR_SDMMC1_EARLY_WR_RSP_ENABLE_Msk            /*!< SDMMC1 early-write response */
36569 #define SYSCFG_ICNEWRCR_SDMMC2_EARLY_WR_RSP_ENABLE_Pos     (1U)
36570 #define SYSCFG_ICNEWRCR_SDMMC2_EARLY_WR_RSP_ENABLE_Msk     (0x1UL << SYSCFG_ICNEWRCR_SDMMC2_EARLY_WR_RSP_ENABLE_Pos) /*!< 0x00000002 */
36571 #define SYSCFG_ICNEWRCR_SDMMC2_EARLY_WR_RSP_ENABLE         SYSCFG_ICNEWRCR_SDMMC2_EARLY_WR_RSP_ENABLE_Msk            /*!< SDMMC2 early-write response */
36572 #define SYSCFG_ICNEWRCR_USB1_EARLY_WR_RSP_ENABLE_Pos       (2U)
36573 #define SYSCFG_ICNEWRCR_USB1_EARLY_WR_RSP_ENABLE_Msk       (0x1UL << SYSCFG_ICNEWRCR_USB1_EARLY_WR_RSP_ENABLE_Pos)   /*!< 0x00000004 */
36574 #define SYSCFG_ICNEWRCR_USB1_EARLY_WR_RSP_ENABLE           SYSCFG_ICNEWRCR_USB1_EARLY_WR_RSP_ENABLE_Msk              /*!< USB1 early-write response */
36575 #define SYSCFG_ICNEWRCR_USB2_EARLY_WR_RSP_ENABLE_Pos       (3U)
36576 #define SYSCFG_ICNEWRCR_USB2_EARLY_WR_RSP_ENABLE_Msk       (0x1UL << SYSCFG_ICNEWRCR_USB2_EARLY_WR_RSP_ENABLE_Pos)   /*!< 0x00000008 */
36577 #define SYSCFG_ICNEWRCR_USB2_EARLY_WR_RSP_ENABLE           SYSCFG_ICNEWRCR_USB2_EARLY_WR_RSP_ENABLE_Msk              /*!< USB2 early-write response */
36578 
36579 /******************  Bit definition for SYSCFG_ICNCGCR register  **************/
36580 #define SYSCFG_ICNCGCR_NPU_NIC_CG_DISABLE_Pos              (0U)
36581 #define SYSCFG_ICNCGCR_NPU_NIC_CG_DISABLE_Msk              (0x1UL << SYSCFG_ICNCGCR_NPU_NIC_CG_DISABLE_Pos) /*!< 0x00000001 */
36582 #define SYSCFG_ICNCGCR_NPU_NIC_CG_DISABLE                  SYSCFG_ICNCGCR_NPU_NIC_CG_DISABLE_Msk            /*!< NPU_NIC clock gating disable */
36583 #define SYSCFG_ICNCGCR_CPU_NIC_CG_DISABLE_Pos              (1U)
36584 #define SYSCFG_ICNCGCR_CPU_NIC_CG_DISABLE_Msk              (0x1UL << SYSCFG_ICNCGCR_CPU_NIC_CG_DISABLE_Pos) /*!< 0x00000002 */
36585 #define SYSCFG_ICNCGCR_CPU_NIC_CG_DISABLE                  SYSCFG_ICNCGCR_CPU_NIC_CG_DISABLE_Msk            /*!< CPU_NIC clock gating disable */
36586 #define SYSCFG_ICNCGCR_CPU_NOC_CG_DISABLE_Pos              (2U)
36587 #define SYSCFG_ICNCGCR_CPU_NOC_CG_DISABLE_Msk              (0x1UL << SYSCFG_ICNCGCR_CPU_NOC_CG_DISABLE_Pos) /*!< 0x00000004 */
36588 #define SYSCFG_ICNCGCR_CPU_NOC_CG_DISABLE                  SYSCFG_ICNCGCR_CPU_NOC_CG_DISABLE_Msk            /*!< CPU_NOC clock gating disable */
36589 
36590 /******************  Bit definition for SYSCFG_IOCR register  **************/
36591 #define SYSCFG_IOCR_IOCR_Pos                (0U)
36592 #define SYSCFG_IOCR_IOCR_Msk                (0xFFFFFFFFUL << SYSCFG_IOCR_IOCR_Pos)         /*!< 0xFFFFFFFF */
36593 #define SYSCFG_IOCR_IOCR                    SYSCFG_IOCR_IOCR_Msk                           /*!< Digital or analog pins */
36594 
36595 /******************  Bit definition for SYSCFG_VDDIO2CCCR register  **************/
36596 #define SYSCFG_VDDIO2CCCR_RANSRC_Pos        (0U)
36597 #define SYSCFG_VDDIO2CCCR_RANSRC_Msk        (0xFUL << SYSCFG_VDDIO2CCCR_RANSRC_Pos)        /*!< 0x0000000F */
36598 #define SYSCFG_VDDIO2CCCR_RANSRC            SYSCFG_VDDIO2CCCR_RANSRC_Msk                   /*!< I/O compensation code for NMOS transistors */
36599 #define SYSCFG_VDDIO2CCCR_RANSRC_0          (0x1UL << SYSCFG_VDDIO2CCCR_RANSRC_Pos)        /*!< 0x00000001 */
36600 #define SYSCFG_VDDIO2CCCR_RANSRC_1          (0x2UL << SYSCFG_VDDIO2CCCR_RANSRC_Pos)        /*!< 0x00000002 */
36601 #define SYSCFG_VDDIO2CCCR_RANSRC_2          (0x4UL << SYSCFG_VDDIO2CCCR_RANSRC_Pos)        /*!< 0x00000004 */
36602 #define SYSCFG_VDDIO2CCCR_RANSRC_3          (0x8UL << SYSCFG_VDDIO2CCCR_RANSRC_Pos)        /*!< 0x00000008 */
36603 #define SYSCFG_VDDIO2CCCR_RAPSRC_Pos        (4U)
36604 #define SYSCFG_VDDIO2CCCR_RAPSRC_Msk        (0xFUL << SYSCFG_VDDIO2CCCR_RAPSRC_Pos)        /*!< 0x000000F0 */
36605 #define SYSCFG_VDDIO2CCCR_RAPSRC            SYSCFG_VDDIO2CCCR_RAPSRC_Msk                   /*!< I/O compensation code for PMOS transistors */
36606 #define SYSCFG_VDDIO2CCCR_RAPSRC_0          (0x1UL << SYSCFG_VDDIO2CCCR_RAPSRC_Pos)        /*!< 0x00000010 */
36607 #define SYSCFG_VDDIO2CCCR_RAPSRC_1          (0x2UL << SYSCFG_VDDIO2CCCR_RAPSRC_Pos)        /*!< 0x00000020 */
36608 #define SYSCFG_VDDIO2CCCR_RAPSRC_2          (0x4UL << SYSCFG_VDDIO2CCCR_RAPSRC_Pos)        /*!< 0x00000040 */
36609 #define SYSCFG_VDDIO2CCCR_RAPSRC_3          (0x8UL << SYSCFG_VDDIO2CCCR_RAPSRC_Pos)        /*!< 0x00000080 */
36610 #define SYSCFG_VDDIO2CCCR_EN_Pos            (8U)
36611 #define SYSCFG_VDDIO2CCCR_EN_Msk            (0x1UL << SYSCFG_VDDIO2CCCR_EN_Pos)            /*!< 0x00000100 */
36612 #define SYSCFG_VDDIO2CCCR_EN                SYSCFG_VDDIO2CCCR_EN_Msk                       /*!< Enables the compensation cell of I/Os supplied by VDDIO2 */
36613 #define SYSCFG_VDDIO2CCCR_CS_Pos            (9U)
36614 #define SYSCFG_VDDIO2CCCR_CS_Msk            (0x1UL << SYSCFG_VDDIO2CCCR_CS_Pos)            /*!< 0x00000200 */
36615 #define SYSCFG_VDDIO2CCCR_CS                SYSCFG_VDDIO2CCCR_CS_Msk                       /*!< Code selection for the compensation cell of I/Os supplied by VDDIO2 */
36616 
36617 /******************  Bit definition for SYSCFG_VDDIO2CCSR register  **************/
36618 #define SYSCFG_VDDIO2CCSR_ANSRC_Pos         (0U)
36619 #define SYSCFG_VDDIO2CCSR_ANSRC_Msk         (0xFUL << SYSCFG_VDDIO2CCSR_ANSRC_Pos)         /*!< 0x0000000F */
36620 #define SYSCFG_VDDIO2CCSR_ANSRC             SYSCFG_VDDIO2CCSR_ANSRC_Msk
36621 #define SYSCFG_VDDIO2CCSR_ANSRC_0           (0x1UL << SYSCFG_VDDIO2CCSR_ANSRC_Pos)         /*!< 0x00000001 */
36622 #define SYSCFG_VDDIO2CCSR_ANSRC_1           (0x2UL << SYSCFG_VDDIO2CCSR_ANSRC_Pos)         /*!< 0x00000002 */
36623 #define SYSCFG_VDDIO2CCSR_ANSRC_2           (0x4UL << SYSCFG_VDDIO2CCSR_ANSRC_Pos)         /*!< 0x00000004 */
36624 #define SYSCFG_VDDIO2CCSR_ANSRC_3           (0x8UL << SYSCFG_VDDIO2CCSR_ANSRC_Pos)         /*!< 0x00000008 */
36625 #define SYSCFG_VDDIO2CCSR_APSRC_Pos         (4U)
36626 #define SYSCFG_VDDIO2CCSR_APSRC_Msk         (0xFUL << SYSCFG_VDDIO2CCSR_APSRC_Pos)         /*!< 0x000000F0 */
36627 #define SYSCFG_VDDIO2CCSR_APSRC             SYSCFG_VDDIO2CCSR_APSRC_Msk
36628 #define SYSCFG_VDDIO2CCSR_APSRC_0           (0x1UL << SYSCFG_VDDIO2CCSR_APSRC_Pos)         /*!< 0x00000010 */
36629 #define SYSCFG_VDDIO2CCSR_APSRC_1           (0x2UL << SYSCFG_VDDIO2CCSR_APSRC_Pos)         /*!< 0x00000020 */
36630 #define SYSCFG_VDDIO2CCSR_APSRC_2           (0x4UL << SYSCFG_VDDIO2CCSR_APSRC_Pos)         /*!< 0x00000040 */
36631 #define SYSCFG_VDDIO2CCSR_APSRC_3           (0x8UL << SYSCFG_VDDIO2CCSR_APSRC_Pos)         /*!< 0x00000080 */
36632 #define SYSCFG_VDDIO2CCSR_READY_Pos         (8U)
36633 #define SYSCFG_VDDIO2CCSR_READY_Msk         (0x1UL << SYSCFG_VDDIO2CCSR_READY_Pos)         /*!< 0x00000100 */
36634 #define SYSCFG_VDDIO2CCSR_READY             SYSCFG_VDDIO2CCSR_READY_Msk                    /*!< Provides the compensation cell status of I/Os supplied by VDDIO2 */
36635 
36636 /******************  Bit definition for SYSCFG_VDDIO3CCCR register  **************/
36637 #define SYSCFG_VDDIO3CCCR_RANSRC_Pos        (0U)
36638 #define SYSCFG_VDDIO3CCCR_RANSRC_Msk        (0xFUL << SYSCFG_VDDIO3CCCR_RANSRC_Pos)        /*!< 0x0000000F */
36639 #define SYSCFG_VDDIO3CCCR_RANSRC            SYSCFG_VDDIO3CCCR_RANSRC_Msk                   /*!< I/O compensation code for NMOS transistors */
36640 #define SYSCFG_VDDIO3CCCR_RANSRC_0          (0x1UL << SYSCFG_VDDIO3CCCR_RANSRC_Pos)        /*!< 0x00000001 */
36641 #define SYSCFG_VDDIO3CCCR_RANSRC_1          (0x2UL << SYSCFG_VDDIO3CCCR_RANSRC_Pos)        /*!< 0x00000002 */
36642 #define SYSCFG_VDDIO3CCCR_RANSRC_2          (0x4UL << SYSCFG_VDDIO3CCCR_RANSRC_Pos)        /*!< 0x00000004 */
36643 #define SYSCFG_VDDIO3CCCR_RANSRC_3          (0x8UL << SYSCFG_VDDIO3CCCR_RANSRC_Pos)        /*!< 0x00000008 */
36644 #define SYSCFG_VDDIO3CCCR_RAPSRC_Pos        (4U)
36645 #define SYSCFG_VDDIO3CCCR_RAPSRC_Msk        (0xFUL << SYSCFG_VDDIO3CCCR_RAPSRC_Pos)        /*!< 0x000000F0 */
36646 #define SYSCFG_VDDIO3CCCR_RAPSRC            SYSCFG_VDDIO3CCCR_RAPSRC_Msk                   /*!< I/O compensation code for PMOS transistors */
36647 #define SYSCFG_VDDIO3CCCR_RAPSRC_0          (0x1UL << SYSCFG_VDDIO3CCCR_RAPSRC_Pos)        /*!< 0x00000010 */
36648 #define SYSCFG_VDDIO3CCCR_RAPSRC_1          (0x2UL << SYSCFG_VDDIO3CCCR_RAPSRC_Pos)        /*!< 0x00000020 */
36649 #define SYSCFG_VDDIO3CCCR_RAPSRC_2          (0x4UL << SYSCFG_VDDIO3CCCR_RAPSRC_Pos)        /*!< 0x00000040 */
36650 #define SYSCFG_VDDIO3CCCR_RAPSRC_3          (0x8UL << SYSCFG_VDDIO3CCCR_RAPSRC_Pos)        /*!< 0x00000080 */
36651 #define SYSCFG_VDDIO3CCCR_EN_Pos            (8U)
36652 #define SYSCFG_VDDIO3CCCR_EN_Msk            (0x1UL << SYSCFG_VDDIO3CCCR_EN_Pos)            /*!< 0x00000100 */
36653 #define SYSCFG_VDDIO3CCCR_EN                SYSCFG_VDDIO3CCCR_EN_Msk                       /*!< Enables the compensation cell of I/Os supplied by VDDIO3 */
36654 #define SYSCFG_VDDIO3CCCR_CS_Pos            (9U)
36655 #define SYSCFG_VDDIO3CCCR_CS_Msk            (0x1UL << SYSCFG_VDDIO3CCCR_CS_Pos)            /*!< 0x00000200 */
36656 #define SYSCFG_VDDIO3CCCR_CS                SYSCFG_VDDIO3CCCR_CS_Msk                       /*!< Code selection for the compensation cell of I/Os supplied by VDDIO3 */
36657 
36658 /******************  Bit definition for SYSCFG_VDDIO3CCSR register  **************/
36659 #define SYSCFG_VDDIO3CCSR_ANSRC_Pos         (0U)
36660 #define SYSCFG_VDDIO3CCSR_ANSRC_Msk         (0xFUL << SYSCFG_VDDIO3CCSR_ANSRC_Pos)         /*!< 0x0000000F */
36661 #define SYSCFG_VDDIO3CCSR_ANSRC             SYSCFG_VDDIO3CCSR_ANSRC_Msk
36662 #define SYSCFG_VDDIO3CCSR_ANSRC_0           (0x1UL << SYSCFG_VDDIO3CCSR_ANSRC_Pos)         /*!< 0x00000001 */
36663 #define SYSCFG_VDDIO3CCSR_ANSRC_1           (0x2UL << SYSCFG_VDDIO3CCSR_ANSRC_Pos)         /*!< 0x00000002 */
36664 #define SYSCFG_VDDIO3CCSR_ANSRC_2           (0x4UL << SYSCFG_VDDIO3CCSR_ANSRC_Pos)         /*!< 0x00000004 */
36665 #define SYSCFG_VDDIO3CCSR_ANSRC_3           (0x8UL << SYSCFG_VDDIO3CCSR_ANSRC_Pos)         /*!< 0x00000008 */
36666 #define SYSCFG_VDDIO3CCSR_APSRC_Pos         (4U)
36667 #define SYSCFG_VDDIO3CCSR_APSRC_Msk         (0xFUL << SYSCFG_VDDIO3CCSR_APSRC_Pos)         /*!< 0x000000F0 */
36668 #define SYSCFG_VDDIO3CCSR_APSRC             SYSCFG_VDDIO3CCSR_APSRC_Msk
36669 #define SYSCFG_VDDIO3CCSR_APSRC_0           (0x1UL << SYSCFG_VDDIO3CCSR_APSRC_Pos)         /*!< 0x00000010 */
36670 #define SYSCFG_VDDIO3CCSR_APSRC_1           (0x2UL << SYSCFG_VDDIO3CCSR_APSRC_Pos)         /*!< 0x00000020 */
36671 #define SYSCFG_VDDIO3CCSR_APSRC_2           (0x4UL << SYSCFG_VDDIO3CCSR_APSRC_Pos)         /*!< 0x00000040 */
36672 #define SYSCFG_VDDIO3CCSR_APSRC_3           (0x8UL << SYSCFG_VDDIO3CCSR_APSRC_Pos)         /*!< 0x00000080 */
36673 #define SYSCFG_VDDIO3CCSR_READY_Pos         (8U)
36674 #define SYSCFG_VDDIO3CCSR_READY_Msk         (0x1UL << SYSCFG_VDDIO3CCSR_READY_Pos)         /*!< 0x00000100 */
36675 #define SYSCFG_VDDIO3CCSR_READY             SYSCFG_VDDIO3CCSR_READY_Msk                    /*!< Provides the compensation cell status of I/Os supplied by VDDIO3 */
36676 
36677 /******************  Bit definition for SYSCFG_VDDIO4CCCR register  **************/
36678 #define SYSCFG_VDDIO4CCCR_RANSRC_Pos        (0U)
36679 #define SYSCFG_VDDIO4CCCR_RANSRC_Msk        (0xFUL << SYSCFG_VDDIO4CCCR_RANSRC_Pos)        /*!< 0x0000000F */
36680 #define SYSCFG_VDDIO4CCCR_RANSRC            SYSCFG_VDDIO4CCCR_RANSRC_Msk                   /*!< I/O compensation code for NMOS transistors */
36681 #define SYSCFG_VDDIO4CCCR_RANSRC_0          (0x1UL << SYSCFG_VDDIO4CCCR_RANSRC_Pos)        /*!< 0x00000001 */
36682 #define SYSCFG_VDDIO4CCCR_RANSRC_1          (0x2UL << SYSCFG_VDDIO4CCCR_RANSRC_Pos)        /*!< 0x00000002 */
36683 #define SYSCFG_VDDIO4CCCR_RANSRC_2          (0x4UL << SYSCFG_VDDIO4CCCR_RANSRC_Pos)        /*!< 0x00000004 */
36684 #define SYSCFG_VDDIO4CCCR_RANSRC_3          (0x8UL << SYSCFG_VDDIO4CCCR_RANSRC_Pos)        /*!< 0x00000008 */
36685 #define SYSCFG_VDDIO4CCCR_RAPSRC_Pos        (4U)
36686 #define SYSCFG_VDDIO4CCCR_RAPSRC_Msk        (0xFUL << SYSCFG_VDDIO4CCCR_RAPSRC_Pos)        /*!< 0x000000F0 */
36687 #define SYSCFG_VDDIO4CCCR_RAPSRC            SYSCFG_VDDIO4CCCR_RAPSRC_Msk                   /*!< I/O compensation code for PMOS transistors */
36688 #define SYSCFG_VDDIO4CCCR_RAPSRC_0          (0x1UL << SYSCFG_VDDIO4CCCR_RAPSRC_Pos)        /*!< 0x00000010 */
36689 #define SYSCFG_VDDIO4CCCR_RAPSRC_1          (0x2UL << SYSCFG_VDDIO4CCCR_RAPSRC_Pos)        /*!< 0x00000020 */
36690 #define SYSCFG_VDDIO4CCCR_RAPSRC_2          (0x4UL << SYSCFG_VDDIO4CCCR_RAPSRC_Pos)        /*!< 0x00000040 */
36691 #define SYSCFG_VDDIO4CCCR_RAPSRC_3          (0x8UL << SYSCFG_VDDIO4CCCR_RAPSRC_Pos)        /*!< 0x00000080 */
36692 #define SYSCFG_VDDIO4CCCR_EN_Pos            (8U)
36693 #define SYSCFG_VDDIO4CCCR_EN_Msk            (0x1UL << SYSCFG_VDDIO4CCCR_EN_Pos)            /*!< 0x00000100 */
36694 #define SYSCFG_VDDIO4CCCR_EN                SYSCFG_VDDIO4CCCR_EN_Msk                       /*!< Enables the compensation cell of I/Os supplied by VDDIO4 */
36695 #define SYSCFG_VDDIO4CCCR_CS_Pos            (9U)
36696 #define SYSCFG_VDDIO4CCCR_CS_Msk            (0x1UL << SYSCFG_VDDIO4CCCR_CS_Pos)            /*!< 0x00000200 */
36697 #define SYSCFG_VDDIO4CCCR_CS                SYSCFG_VDDIO4CCCR_CS_Msk                       /*!< Code selection for the compensation cell of I/Os supplied by VDDIO4 */
36698 
36699 /******************  Bit definition for SYSCFG_VDDIO4CCSR register  **************/
36700 #define SYSCFG_VDDIO4CCSR_ANSRC_Pos         (0U)
36701 #define SYSCFG_VDDIO4CCSR_ANSRC_Msk         (0xFUL << SYSCFG_VDDIO4CCSR_ANSRC_Pos)         /*!< 0x0000000F */
36702 #define SYSCFG_VDDIO4CCSR_ANSRC             SYSCFG_VDDIO4CCSR_ANSRC_Msk
36703 #define SYSCFG_VDDIO4CCSR_ANSRC_0           (0x1UL << SYSCFG_VDDIO4CCSR_ANSRC_Pos)         /*!< 0x00000001 */
36704 #define SYSCFG_VDDIO4CCSR_ANSRC_1           (0x2UL << SYSCFG_VDDIO4CCSR_ANSRC_Pos)         /*!< 0x00000002 */
36705 #define SYSCFG_VDDIO4CCSR_ANSRC_2           (0x4UL << SYSCFG_VDDIO4CCSR_ANSRC_Pos)         /*!< 0x00000004 */
36706 #define SYSCFG_VDDIO4CCSR_ANSRC_3           (0x8UL << SYSCFG_VDDIO4CCSR_ANSRC_Pos)         /*!< 0x00000008 */
36707 #define SYSCFG_VDDIO4CCSR_APSRC_Pos         (4U)
36708 #define SYSCFG_VDDIO4CCSR_APSRC_Msk         (0xFUL << SYSCFG_VDDIO4CCSR_APSRC_Pos)         /*!< 0x000000F0 */
36709 #define SYSCFG_VDDIO4CCSR_APSRC             SYSCFG_VDDIO4CCSR_APSRC_Msk
36710 #define SYSCFG_VDDIO4CCSR_APSRC_0           (0x1UL << SYSCFG_VDDIO4CCSR_APSRC_Pos)         /*!< 0x00000010 */
36711 #define SYSCFG_VDDIO4CCSR_APSRC_1           (0x2UL << SYSCFG_VDDIO4CCSR_APSRC_Pos)         /*!< 0x00000020 */
36712 #define SYSCFG_VDDIO4CCSR_APSRC_2           (0x4UL << SYSCFG_VDDIO4CCSR_APSRC_Pos)         /*!< 0x00000040 */
36713 #define SYSCFG_VDDIO4CCSR_APSRC_3           (0x8UL << SYSCFG_VDDIO4CCSR_APSRC_Pos)         /*!< 0x00000080 */
36714 #define SYSCFG_VDDIO4CCSR_READY_Pos         (8U)
36715 #define SYSCFG_VDDIO4CCSR_READY_Msk         (0x1UL << SYSCFG_VDDIO4CCSR_READY_Pos)         /*!< 0x00000100 */
36716 #define SYSCFG_VDDIO4CCSR_READY             SYSCFG_VDDIO4CCSR_READY_Msk                    /*!< Provides the compensation cell status of I/Os supplied by VDDIO4 */
36717 
36718 /******************  Bit definition for SYSCFG_VDDIO5CCCR register  **************/
36719 #define SYSCFG_VDDIO5CCCR_RANSRC_Pos        (0U)
36720 #define SYSCFG_VDDIO5CCCR_RANSRC_Msk        (0xFUL << SYSCFG_VDDIO5CCCR_RANSRC_Pos)        /*!< 0x0000000F */
36721 #define SYSCFG_VDDIO5CCCR_RANSRC            SYSCFG_VDDIO5CCCR_RANSRC_Msk                   /*!< I/O compensation code for NMOS transistors */
36722 #define SYSCFG_VDDIO5CCCR_RANSRC_0          (0x1UL << SYSCFG_VDDIO5CCCR_RANSRC_Pos)        /*!< 0x00000001 */
36723 #define SYSCFG_VDDIO5CCCR_RANSRC_1          (0x2UL << SYSCFG_VDDIO5CCCR_RANSRC_Pos)        /*!< 0x00000002 */
36724 #define SYSCFG_VDDIO5CCCR_RANSRC_2          (0x4UL << SYSCFG_VDDIO5CCCR_RANSRC_Pos)        /*!< 0x00000004 */
36725 #define SYSCFG_VDDIO5CCCR_RANSRC_3          (0x8UL << SYSCFG_VDDIO5CCCR_RANSRC_Pos)        /*!< 0x00000008 */
36726 #define SYSCFG_VDDIO5CCCR_RAPSRC_Pos        (4U)
36727 #define SYSCFG_VDDIO5CCCR_RAPSRC_Msk        (0xFUL << SYSCFG_VDDIO5CCCR_RAPSRC_Pos)        /*!< 0x000000F0 */
36728 #define SYSCFG_VDDIO5CCCR_RAPSRC            SYSCFG_VDDIO5CCCR_RAPSRC_Msk                   /*!< I/O compensation code for PMOS transistors */
36729 #define SYSCFG_VDDIO5CCCR_RAPSRC_0          (0x1UL << SYSCFG_VDDIO5CCCR_RAPSRC_Pos)        /*!< 0x00000010 */
36730 #define SYSCFG_VDDIO5CCCR_RAPSRC_1          (0x2UL << SYSCFG_VDDIO5CCCR_RAPSRC_Pos)        /*!< 0x00000020 */
36731 #define SYSCFG_VDDIO5CCCR_RAPSRC_2          (0x4UL << SYSCFG_VDDIO5CCCR_RAPSRC_Pos)        /*!< 0x00000040 */
36732 #define SYSCFG_VDDIO5CCCR_RAPSRC_3          (0x8UL << SYSCFG_VDDIO5CCCR_RAPSRC_Pos)        /*!< 0x00000080 */
36733 #define SYSCFG_VDDIO5CCCR_EN_Pos            (8U)
36734 #define SYSCFG_VDDIO5CCCR_EN_Msk            (0x1UL << SYSCFG_VDDIO5CCCR_EN_Pos)            /*!< 0x00000100 */
36735 #define SYSCFG_VDDIO5CCCR_EN                SYSCFG_VDDIO5CCCR_EN_Msk                       /*!< Enables the compensation cell of I/Os supplied by VDDIO5 */
36736 #define SYSCFG_VDDIO5CCCR_CS_Pos            (9U)
36737 #define SYSCFG_VDDIO5CCCR_CS_Msk            (0x1UL << SYSCFG_VDDIO5CCCR_CS_Pos)            /*!< 0x00000200 */
36738 #define SYSCFG_VDDIO5CCCR_CS                SYSCFG_VDDIO5CCCR_CS_Msk                       /*!< Code selection for the compensation cell of I/Os supplied by VDDIO5 */
36739 
36740 /******************  Bit definition for SYSCFG_VDDIO5CCSR register  **************/
36741 #define SYSCFG_VDDIO5CCSR_ANSRC_Pos         (0U)
36742 #define SYSCFG_VDDIO5CCSR_ANSRC_Msk         (0xFUL << SYSCFG_VDDIO5CCSR_ANSRC_Pos)         /*!< 0x0000000F */
36743 #define SYSCFG_VDDIO5CCSR_ANSRC             SYSCFG_VDDIO5CCSR_ANSRC_Msk
36744 #define SYSCFG_VDDIO5CCSR_ANSRC_0           (0x1UL << SYSCFG_VDDIO5CCSR_ANSRC_Pos)         /*!< 0x00000001 */
36745 #define SYSCFG_VDDIO5CCSR_ANSRC_1           (0x2UL << SYSCFG_VDDIO5CCSR_ANSRC_Pos)         /*!< 0x00000002 */
36746 #define SYSCFG_VDDIO5CCSR_ANSRC_2           (0x4UL << SYSCFG_VDDIO5CCSR_ANSRC_Pos)         /*!< 0x00000004 */
36747 #define SYSCFG_VDDIO5CCSR_ANSRC_3           (0x8UL << SYSCFG_VDDIO5CCSR_ANSRC_Pos)         /*!< 0x00000008 */
36748 #define SYSCFG_VDDIO5CCSR_APSRC_Pos         (4U)
36749 #define SYSCFG_VDDIO5CCSR_APSRC_Msk         (0xFUL << SYSCFG_VDDIO5CCSR_APSRC_Pos)         /*!< 0x000000F0 */
36750 #define SYSCFG_VDDIO5CCSR_APSRC             SYSCFG_VDDIO5CCSR_APSRC_Msk
36751 #define SYSCFG_VDDIO5CCSR_APSRC_0           (0x1UL << SYSCFG_VDDIO5CCSR_APSRC_Pos)         /*!< 0x00000010 */
36752 #define SYSCFG_VDDIO5CCSR_APSRC_1           (0x2UL << SYSCFG_VDDIO5CCSR_APSRC_Pos)         /*!< 0x00000020 */
36753 #define SYSCFG_VDDIO5CCSR_APSRC_2           (0x4UL << SYSCFG_VDDIO5CCSR_APSRC_Pos)         /*!< 0x00000040 */
36754 #define SYSCFG_VDDIO5CCSR_APSRC_3           (0x8UL << SYSCFG_VDDIO5CCSR_APSRC_Pos)         /*!< 0x00000080 */
36755 #define SYSCFG_VDDIO5CCSR_READY_Pos         (8U)
36756 #define SYSCFG_VDDIO5CCSR_READY_Msk         (0x1UL << SYSCFG_VDDIO5CCSR_READY_Pos)         /*!< 0x00000100 */
36757 #define SYSCFG_VDDIO5CCSR_READY             SYSCFG_VDDIO5CCSR_READY_Msk                    /*!< Provides the compensation cell status of I/Os supplied by VDDIO5 */
36758 
36759 /******************  Bit definition for SYSCFG_VDDCCCR register  **************/
36760 #define SYSCFG_VDDCCCR_RANSRC_Pos           (0U)
36761 #define SYSCFG_VDDCCCR_RANSRC_Msk           (0xFUL << SYSCFG_VDDCCCR_RANSRC_Pos)           /*!< 0x0000000F */
36762 #define SYSCFG_VDDCCCR_RANSRC               SYSCFG_VDDCCCR_RANSRC_Msk                      /*!< I/O compensation code for NMOS transistors */
36763 #define SYSCFG_VDDCCCR_RANSRC_0             (0x1UL << SYSCFG_VDDCCCR_RANSRC_Pos)           /*!< 0x00000001 */
36764 #define SYSCFG_VDDCCCR_RANSRC_1             (0x2UL << SYSCFG_VDDCCCR_RANSRC_Pos)           /*!< 0x00000002 */
36765 #define SYSCFG_VDDCCCR_RANSRC_2             (0x4UL << SYSCFG_VDDCCCR_RANSRC_Pos)           /*!< 0x00000004 */
36766 #define SYSCFG_VDDCCCR_RANSRC_3             (0x8UL << SYSCFG_VDDCCCR_RANSRC_Pos)           /*!< 0x00000008 */
36767 #define SYSCFG_VDDCCCR_RAPSRC_Pos           (4U)
36768 #define SYSCFG_VDDCCCR_RAPSRC_Msk           (0xFUL << SYSCFG_VDDCCCR_RAPSRC_Pos)           /*!< 0x000000F0 */
36769 #define SYSCFG_VDDCCCR_RAPSRC               SYSCFG_VDDCCCR_RAPSRC_Msk                      /*!< I/O compensation code for PMOS transistors */
36770 #define SYSCFG_VDDCCCR_RAPSRC_0             (0x1UL << SYSCFG_VDDCCCR_RAPSRC_Pos)           /*!< 0x00000010 */
36771 #define SYSCFG_VDDCCCR_RAPSRC_1             (0x2UL << SYSCFG_VDDCCCR_RAPSRC_Pos)           /*!< 0x00000020 */
36772 #define SYSCFG_VDDCCCR_RAPSRC_2             (0x4UL << SYSCFG_VDDCCCR_RAPSRC_Pos)           /*!< 0x00000040 */
36773 #define SYSCFG_VDDCCCR_RAPSRC_3             (0x8UL << SYSCFG_VDDCCCR_RAPSRC_Pos)           /*!< 0x00000080 */
36774 #define SYSCFG_VDDCCCR_EN_Pos               (8U)
36775 #define SYSCFG_VDDCCCR_EN_Msk               (0x1UL << SYSCFG_VDDCCCR_EN_Pos)               /*!< 0x00000100 */
36776 #define SYSCFG_VDDCCCR_EN                   SYSCFG_VDDCCCR_EN_Msk                          /*!< Enables the compensation cell of I/Os supplied by VDD */
36777 #define SYSCFG_VDDCCCR_CS_Pos               (9U)
36778 #define SYSCFG_VDDCCCR_CS_Msk               (0x1UL << SYSCFG_VDDCCCR_CS_Pos)               /*!< 0x00000200 */
36779 #define SYSCFG_VDDCCCR_CS                   SYSCFG_VDDCCCR_CS_Msk                          /*!< Code selection for the compensation cell of I/Os supplied by VDD */
36780 
36781 /******************  Bit definition for SYSCFG_VDDCCSR register  **************/
36782 #define SYSCFG_VDDCCSR_ANSRC_Pos            (0U)
36783 #define SYSCFG_VDDCCSR_ANSRC_Msk            (0xFUL << SYSCFG_VDDCCSR_ANSRC_Pos)            /*!< 0x0000000F */
36784 #define SYSCFG_VDDCCSR_ANSRC                SYSCFG_VDDCCSR_ANSRC_Msk
36785 #define SYSCFG_VDDCCSR_ANSRC_0              (0x1UL << SYSCFG_VDDCCSR_ANSRC_Pos)            /*!< 0x00000001 */
36786 #define SYSCFG_VDDCCSR_ANSRC_1              (0x2UL << SYSCFG_VDDCCSR_ANSRC_Pos)            /*!< 0x00000002 */
36787 #define SYSCFG_VDDCCSR_ANSRC_2              (0x4UL << SYSCFG_VDDCCSR_ANSRC_Pos)            /*!< 0x00000004 */
36788 #define SYSCFG_VDDCCSR_ANSRC_3              (0x8UL << SYSCFG_VDDCCSR_ANSRC_Pos)            /*!< 0x00000008 */
36789 #define SYSCFG_VDDCCSR_APSRC_Pos            (4U)
36790 #define SYSCFG_VDDCCSR_APSRC_Msk            (0xFUL << SYSCFG_VDDCCSR_APSRC_Pos)            /*!< 0x000000F0 */
36791 #define SYSCFG_VDDCCSR_APSRC                SYSCFG_VDDCCSR_APSRC_Msk
36792 #define SYSCFG_VDDCCSR_APSRC_0              (0x1UL << SYSCFG_VDDCCSR_APSRC_Pos)            /*!< 0x00000010 */
36793 #define SYSCFG_VDDCCSR_APSRC_1              (0x2UL << SYSCFG_VDDCCSR_APSRC_Pos)            /*!< 0x00000020 */
36794 #define SYSCFG_VDDCCSR_APSRC_2              (0x4UL << SYSCFG_VDDCCSR_APSRC_Pos)            /*!< 0x00000040 */
36795 #define SYSCFG_VDDCCSR_APSRC_3              (0x8UL << SYSCFG_VDDCCSR_APSRC_Pos)            /*!< 0x00000080 */
36796 #define SYSCFG_VDDCCSR_READY_Pos            (8U)
36797 #define SYSCFG_VDDCCSR_READY_Msk            (0x1UL << SYSCFG_VDDCCSR_READY_Pos)            /*!< 0x00000100 */
36798 #define SYSCFG_VDDCCSR_READY                SYSCFG_VDDCCSR_READY_Msk                       /*!< Provides the compensation cell status of I/Os supplied by VDD */
36799 
36800 /******************  Bit definition for SYSCFG_CBR register  **************/
36801 #define SYSCFG_CBR_CM55L_Pos                (0U)
36802 #define SYSCFG_CBR_CM55L_Msk                (0x1UL << SYSCFG_CBR_CM55L_Pos)                /*!< 0x00000001 */
36803 #define SYSCFG_CBR_CM55L                    SYSCFG_CBR_CM55L_Msk                           /*!< CM55 lockup lock enable */
36804 #define SYSCFG_CBR_PVDL_LOCK_Pos            (2U)
36805 #define SYSCFG_CBR_PVDL_LOCK_Msk            (0x1UL << SYSCFG_CBR_PVDL_LOCK_Pos)            /*!< 0x00000004 */
36806 #define SYSCFG_CBR_PVDL_LOCK                SYSCFG_CBR_PVDL_LOCK_Msk                       /*!< PVD lock enable */
36807 #define SYSCFG_CBR_BKPRAML_Pos              (8U)
36808 #define SYSCFG_CBR_BKPRAML_Msk              (0x1UL << SYSCFG_CBR_BKPRAML_Pos)              /*!< 0x00000100 */
36809 #define SYSCFG_CBR_BKPRAML                  SYSCFG_CBR_BKPRAML_Msk                         /*!< Backup SRAM double ECC error lock */
36810 #define SYSCFG_CBR_CM55CACHEL_Pos           (9U)
36811 #define SYSCFG_CBR_CM55CACHEL_Msk           (0x1UL << SYSCFG_CBR_CM55CACHEL_Pos)           /*!< 0x00000200 */
36812 #define SYSCFG_CBR_CM55CACHEL               SYSCFG_CBR_CM55CACHEL_Msk                      /*!< CM55 cache double ECC error lock */
36813 #define SYSCFG_CBR_CM55TCML_Pos             (10U)
36814 #define SYSCFG_CBR_CM55TCML_Msk             (0x1UL << SYSCFG_CBR_CM55TCML_Pos)             /*!< 0x00000400 */
36815 #define SYSCFG_CBR_CM55TCML                 SYSCFG_CBR_CM55TCML_Msk                        /*!< CM55 TCM double ECC error lock */
36816 
36817 /******************  Bit definition for SYSCFG_SEC_AIDCR register  **************/
36818 #define SYSCFG_SEC_AIDCR_DMACID_SEC_Pos     (0U)
36819 #define SYSCFG_SEC_AIDCR_DMACID_SEC_Msk     (0x7UL << SYSCFG_SEC_AIDCR_DMACID_SEC_Pos)     /*!< 0x0000000F */
36820 #define SYSCFG_SEC_AIDCR_DMACID_SEC         SYSCFG_SEC_AIDCR_DMACID_SEC_Msk                /* Secure OS allocates specific CID to DMA channel through these bits */
36821 #define SYSCFG_SEC_AIDCR_DMACID_SEC_0       (0x1UL << SYSCFG_SEC_AIDCR_DMACID_SEC_Pos)     /*!< 0x00000001 */
36822 #define SYSCFG_SEC_AIDCR_DMACID_SEC_1       (0x2UL << SYSCFG_SEC_AIDCR_DMACID_SEC_Pos)     /*!< 0x00000002 */
36823 #define SYSCFG_SEC_AIDCR_DMACID_SEC_2       (0x4UL << SYSCFG_SEC_AIDCR_DMACID_SEC_Pos)     /*!< 0x00000004 */
36824 
36825 /******************  Bit definition for SYSCFG_FMC_RETIMECR register  **************/
36826 #define SYSCFG_FMC_RETIMECR_CFG_RETIME_RX_Pos       (0U)
36827 #define SYSCFG_FMC_RETIMECR_CFG_RETIME_RX_Msk       (0x1UL << SYSCFG_FMC_RETIMECR_CFG_RETIME_RX_Pos) /*!< 0x00000001 */
36828 #define SYSCFG_FMC_RETIMECR_CFG_RETIME_RX           SYSCFG_FMC_RETIMECR_CFG_RETIME_RX_Msk            /*!< Retiming on Rx path */
36829 #define SYSCFG_FMC_RETIMECR_CFG_RETIME_TX_Pos       (1U)
36830 #define SYSCFG_FMC_RETIMECR_CFG_RETIME_TX_Msk       (0x1UL << SYSCFG_FMC_RETIMECR_CFG_RETIME_TX_Pos) /*!< 0x00000002 */
36831 #define SYSCFG_FMC_RETIMECR_CFG_RETIME_TX           SYSCFG_FMC_RETIMECR_CFG_RETIME_TX_Msk            /*!< Retiming on Tx path */
36832 #define SYSCFG_FMC_RETIMECR_SDFBCLK_180_Pos         (2U)
36833 #define SYSCFG_FMC_RETIMECR_SDFBCLK_180_Msk         (0x1UL << SYSCFG_FMC_RETIMECR_SDFBCLK_180_Pos)   /*!< 0x00000004 */
36834 #define SYSCFG_FMC_RETIMECR_SDFBCLK_180             SYSCFG_FMC_RETIMECR_SDFBCLK_180_Msk              /*!< Delay on feedback clock */
36835 
36836 /******************  Bit definition for SYSCFG_NPU_ICNCR register  **************/
36837 #define SYSCFG_NPU_ICNCR_INTERLEAVING_ACTIVE_Pos    (0U)
36838 #define SYSCFG_NPU_ICNCR_INTERLEAVING_ACTIVE_Msk    (0x1UL << SYSCFG_NPU_ICNCR_INTERLEAVING_ACTIVE_Pos) /*!< 0x00000001 */
36839 #define SYSCFG_NPU_ICNCR_INTERLEAVING_ACTIVE        SYSCFG_NPU_ICNCR_INTERLEAVING_ACTIVE_Msk            /*!< Control interleaving on NPU RAMs */
36840 
36841 /******************  Bit definition for SYSCFG_BOOTSR register  **************/
36842 #define SYSCFG_BOOTSR_BOOT0_Pos             (0U)
36843 #define SYSCFG_BOOTSR_BOOT0_Msk             (0x1UL << SYSCFG_BOOTSR_BOOT0_Pos)             /*!< 0x00000001 */
36844 #define SYSCFG_BOOTSR_BOOT0                 SYSCFG_BOOTSR_BOOT0_Msk                        /*!< BOOT0 pin value */
36845 #define SYSCFG_BOOTSR_BOOT1_Pos             (1U)
36846 #define SYSCFG_BOOTSR_BOOT1_Msk             (0x1UL << SYSCFG_BOOTSR_BOOT1_Pos)             /*!< 0x00000002 */
36847 #define SYSCFG_BOOTSR_BOOT1                 SYSCFG_BOOTSR_BOOT1_Msk                        /*!< BOOT1 pin value */
36848 
36849 /******************  Bit definition for SYSCFG_AHBWP_ERROR_SR register  **************/
36850 #define SYSCFG_AHBWP_ERROR_SR_PAHB_ERROR_ADDR_Pos  (0U)
36851 #define SYSCFG_AHBWP_ERROR_SR_PAHB_ERROR_ADDR_Msk  (0xFFFFFFFFUL << SYSCFG_AHBWP_ERROR_SR_PAHB_ERROR_ADDR_Pos) /*!< 0xFFFFFFFF */
36852 #define SYSCFG_AHBWP_ERROR_SR_PAHB_ERROR_ADDR      SYSCFG_AHBWP_ERROR_SR_PAHB_ERROR_ADDR_Msk                   /*!< Reports address of the first error in P-AHB write-posting buffer */
36853 
36854 /******************  Bit definition for SYSCFG_SECPRIV_AIDCR register  **************/
36855 #define SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_Pos  (0U)
36856 #define SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_Msk  (0x7UL << SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_Pos)  /*!< 0x0000000F */
36857 #define SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC      SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_Msk             /* Non-Secure OS allocates specific CID to DMA channel through these bits */
36858 #define SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_0    (0x1UL << SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_Pos)  /*!< 0x00000001 */
36859 #define SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_1    (0x2UL << SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_Pos)  /*!< 0x00000002 */
36860 #define SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_2    (0x4UL << SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_Pos)  /*!< 0x00000004 */
36861 
36862 
36863 /******************************************************************************/
36864 /*                                                                            */
36865 /*                     Tamper and backup register (TAMP)                      */
36866 /*                                                                            */
36867 /******************************************************************************/
36868 /********************  Bits definition for TAMP_CR1 register  *****************/
36869 #define TAMP_CR1_TAMP1E_Pos                 (0U)
36870 #define TAMP_CR1_TAMP1E_Msk                 (0x1UL << TAMP_CR1_TAMP1E_Pos)          /*!< 0x00000001 */
36871 #define TAMP_CR1_TAMP1E                     TAMP_CR1_TAMP1E_Msk
36872 #define TAMP_CR1_TAMP2E_Pos                 (1U)
36873 #define TAMP_CR1_TAMP2E_Msk                 (0x1UL << TAMP_CR1_TAMP2E_Pos)          /*!< 0x00000002 */
36874 #define TAMP_CR1_TAMP2E                     TAMP_CR1_TAMP2E_Msk
36875 #define TAMP_CR1_TAMP3E_Pos                 (2U)
36876 #define TAMP_CR1_TAMP3E_Msk                 (0x1UL << TAMP_CR1_TAMP3E_Pos)          /*!< 0x00000004 */
36877 #define TAMP_CR1_TAMP3E                     TAMP_CR1_TAMP3E_Msk
36878 #define TAMP_CR1_TAMP4E_Pos                 (3U)
36879 #define TAMP_CR1_TAMP4E_Msk                 (0x1UL << TAMP_CR1_TAMP4E_Pos)          /*!< 0x00000008 */
36880 #define TAMP_CR1_TAMP4E                     TAMP_CR1_TAMP4E_Msk
36881 #define TAMP_CR1_TAMP5E_Pos                 (4U)
36882 #define TAMP_CR1_TAMP5E_Msk                 (0x1UL << TAMP_CR1_TAMP5E_Pos)          /*!< 0x00000010 */
36883 #define TAMP_CR1_TAMP5E                     TAMP_CR1_TAMP5E_Msk
36884 #define TAMP_CR1_TAMP6E_Pos                 (5U)
36885 #define TAMP_CR1_TAMP6E_Msk                 (0x1UL << TAMP_CR1_TAMP6E_Pos)          /*!< 0x00000020 */
36886 #define TAMP_CR1_TAMP6E                     TAMP_CR1_TAMP6E_Msk
36887 #define TAMP_CR1_TAMP7E_Pos                 (6U)
36888 #define TAMP_CR1_TAMP7E_Msk                 (0x1UL << TAMP_CR1_TAMP7E_Pos)          /*!< 0x00000040 */
36889 #define TAMP_CR1_TAMP7E                     TAMP_CR1_TAMP7E_Msk
36890 #define TAMP_CR1_ITAMP1E_Pos                (16U)
36891 #define TAMP_CR1_ITAMP1E_Msk                (0x1UL << TAMP_CR1_ITAMP1E_Pos)         /*!< 0x00010000 */
36892 #define TAMP_CR1_ITAMP1E                    TAMP_CR1_ITAMP1E_Msk
36893 #define TAMP_CR1_ITAMP2E_Pos                (17U)
36894 #define TAMP_CR1_ITAMP2E_Msk                (0x1UL << TAMP_CR1_ITAMP2E_Pos)         /*!< 0x00020000 */
36895 #define TAMP_CR1_ITAMP2E                    TAMP_CR1_ITAMP2E_Msk
36896 #define TAMP_CR1_ITAMP3E_Pos                (18U)
36897 #define TAMP_CR1_ITAMP3E_Msk                (0x1UL << TAMP_CR1_ITAMP3E_Pos)         /*!< 0x00040000 */
36898 #define TAMP_CR1_ITAMP3E                    TAMP_CR1_ITAMP3E_Msk
36899 #define TAMP_CR1_ITAMP4E_Pos                (19U)
36900 #define TAMP_CR1_ITAMP4E_Msk                (0x1UL << TAMP_CR1_ITAMP4E_Pos)         /*!< 0x00080000 */
36901 #define TAMP_CR1_ITAMP4E                    TAMP_CR1_ITAMP4E_Msk
36902 #define TAMP_CR1_ITAMP5E_Pos                (20U)
36903 #define TAMP_CR1_ITAMP5E_Msk                (0x1UL << TAMP_CR1_ITAMP5E_Pos)         /*!< 0x00100000 */
36904 #define TAMP_CR1_ITAMP5E                    TAMP_CR1_ITAMP5E_Msk
36905 #define TAMP_CR1_ITAMP6E_Pos                (21U)
36906 #define TAMP_CR1_ITAMP6E_Msk                (0x1UL << TAMP_CR1_ITAMP6E_Pos)         /*!< 0x00200000 */
36907 #define TAMP_CR1_ITAMP6E                    TAMP_CR1_ITAMP6E_Msk
36908 #define TAMP_CR1_ITAMP7E_Pos                (22U)
36909 #define TAMP_CR1_ITAMP7E_Msk                (0x1UL << TAMP_CR1_ITAMP7E_Pos)         /*!< 0x00400000 */
36910 #define TAMP_CR1_ITAMP7E                    TAMP_CR1_ITAMP7E_Msk
36911 #define TAMP_CR1_ITAMP8E_Pos                (23U)
36912 #define TAMP_CR1_ITAMP8E_Msk                (0x1UL << TAMP_CR1_ITAMP8E_Pos)         /*!< 0x00800000 */
36913 #define TAMP_CR1_ITAMP8E                    TAMP_CR1_ITAMP8E_Msk
36914 #define TAMP_CR1_ITAMP9E_Pos                (24U)
36915 #define TAMP_CR1_ITAMP9E_Msk                (0x1UL << TAMP_CR1_ITAMP9E_Pos)         /*!< 0x01000000 */
36916 #define TAMP_CR1_ITAMP9E                    TAMP_CR1_ITAMP9E_Msk
36917 #define TAMP_CR1_ITAMP11E_Pos               (26U)
36918 #define TAMP_CR1_ITAMP11E_Msk               (0x1UL << TAMP_CR1_ITAMP11E_Pos)        /*!< 0x04000000 */
36919 #define TAMP_CR1_ITAMP11E                   TAMP_CR1_ITAMP11E_Msk
36920 
36921 /********************  Bits definition for TAMP_CR2 register  *****************/
36922 #define TAMP_CR2_TAMP1POM_Pos               (0U)
36923 #define TAMP_CR2_TAMP1POM_Msk               (0x1UL << TAMP_CR2_TAMP1POM_Pos)        /*!< 0x00000001 */
36924 #define TAMP_CR2_TAMP1POM                   TAMP_CR2_TAMP1POM_Msk
36925 #define TAMP_CR2_TAMP2POM_Pos               (1U)
36926 #define TAMP_CR2_TAMP2POM_Msk               (0x1UL << TAMP_CR2_TAMP2POM_Pos)        /*!< 0x00000002 */
36927 #define TAMP_CR2_TAMP2POM                   TAMP_CR2_TAMP2POM_Msk
36928 #define TAMP_CR2_TAMP3POM_Pos               (2U)
36929 #define TAMP_CR2_TAMP3POM_Msk               (0x1UL << TAMP_CR2_TAMP3POM_Pos)        /*!< 0x00000004 */
36930 #define TAMP_CR2_TAMP3POM                   TAMP_CR2_TAMP3POM_Msk
36931 #define TAMP_CR2_TAMP4POM_Pos               (3U)
36932 #define TAMP_CR2_TAMP4POM_Msk               (0x1UL << TAMP_CR2_TAMP4POM_Pos)        /*!< 0x00000008 */
36933 #define TAMP_CR2_TAMP4POM                   TAMP_CR2_TAMP4POM_Msk
36934 #define TAMP_CR2_TAMP5POM_Pos               (4U)
36935 #define TAMP_CR2_TAMP5POM_Msk               (0x1UL << TAMP_CR2_TAMP5POM_Pos)        /*!< 0x00000010 */
36936 #define TAMP_CR2_TAMP5POM                   TAMP_CR2_TAMP5POM_Msk
36937 #define TAMP_CR2_TAMP6POM_Pos               (5U)
36938 #define TAMP_CR2_TAMP6POM_Msk               (0x1UL << TAMP_CR2_TAMP6POM_Pos)        /*!< 0x00000020 */
36939 #define TAMP_CR2_TAMP6POM                   TAMP_CR2_TAMP6POM_Msk
36940 #define TAMP_CR2_TAMP7POM_Pos               (6U)
36941 #define TAMP_CR2_TAMP7POM_Msk               (0x1UL << TAMP_CR2_TAMP7POM_Pos)        /*!< 0x00000040 */
36942 #define TAMP_CR2_TAMP7POM                   TAMP_CR2_TAMP7POM_Msk
36943 #define TAMP_CR2_TAMP1MSK_Pos               (16U)
36944 #define TAMP_CR2_TAMP1MSK_Msk               (0x1UL << TAMP_CR2_TAMP1MSK_Pos)        /*!< 0x00010000 */
36945 #define TAMP_CR2_TAMP1MSK                   TAMP_CR2_TAMP1MSK_Msk
36946 #define TAMP_CR2_TAMP2MSK_Pos               (17U)
36947 #define TAMP_CR2_TAMP2MSK_Msk               (0x1UL << TAMP_CR2_TAMP2MSK_Pos)        /*!< 0x00020000 */
36948 #define TAMP_CR2_TAMP2MSK                   TAMP_CR2_TAMP2MSK_Msk
36949 #define TAMP_CR2_TAMP3MSK_Pos               (18U)
36950 #define TAMP_CR2_TAMP3MSK_Msk               (0x1UL << TAMP_CR2_TAMP3MSK_Pos)        /*!< 0x00040000 */
36951 #define TAMP_CR2_TAMP3MSK                   TAMP_CR2_TAMP3MSK_Msk
36952 #define TAMP_CR2_BKBLOCK_Pos                (22U)
36953 #define TAMP_CR2_BKBLOCK_Msk                (0x1UL << TAMP_CR2_BKBLOCK_Pos)         /*!< 0x00400000 */
36954 #define TAMP_CR2_BKBLOCK                    TAMP_CR2_BKBLOCK_Msk
36955 #define TAMP_CR2_BKERASE_Pos                (23U)
36956 #define TAMP_CR2_BKERASE_Msk                (0x1UL << TAMP_CR2_BKERASE_Pos)         /*!< 0x00800000 */
36957 #define TAMP_CR2_BKERASE                    TAMP_CR2_BKERASE_Msk
36958 #define TAMP_CR2_TAMP1TRG_Pos               (24U)
36959 #define TAMP_CR2_TAMP1TRG_Msk               (0x1UL << TAMP_CR2_TAMP1TRG_Pos)        /*!< 0x01000000 */
36960 #define TAMP_CR2_TAMP1TRG                   TAMP_CR2_TAMP1TRG_Msk
36961 #define TAMP_CR2_TAMP2TRG_Pos               (25U)
36962 #define TAMP_CR2_TAMP2TRG_Msk               (0x1UL << TAMP_CR2_TAMP2TRG_Pos)        /*!< 0x02000000 */
36963 #define TAMP_CR2_TAMP2TRG                   TAMP_CR2_TAMP2TRG_Msk
36964 #define TAMP_CR2_TAMP3TRG_Pos               (26U)
36965 #define TAMP_CR2_TAMP3TRG_Msk               (0x1UL << TAMP_CR2_TAMP3TRG_Pos)        /*!< 0x02000000 */
36966 #define TAMP_CR2_TAMP3TRG                   TAMP_CR2_TAMP3TRG_Msk
36967 #define TAMP_CR2_TAMP4TRG_Pos               (27U)
36968 #define TAMP_CR2_TAMP4TRG_Msk               (0x1UL << TAMP_CR2_TAMP4TRG_Pos)        /*!< 0x02000000 */
36969 #define TAMP_CR2_TAMP4TRG                   TAMP_CR2_TAMP4TRG_Msk
36970 #define TAMP_CR2_TAMP5TRG_Pos               (28U)
36971 #define TAMP_CR2_TAMP5TRG_Msk               (0x1UL << TAMP_CR2_TAMP5TRG_Pos)        /*!< 0x02000000 */
36972 #define TAMP_CR2_TAMP5TRG                   TAMP_CR2_TAMP5TRG_Msk
36973 #define TAMP_CR2_TAMP6TRG_Pos               (29U)
36974 #define TAMP_CR2_TAMP6TRG_Msk               (0x1UL << TAMP_CR2_TAMP6TRG_Pos)        /*!< 0x02000000 */
36975 #define TAMP_CR2_TAMP6TRG                   TAMP_CR2_TAMP6TRG_Msk
36976 #define TAMP_CR2_TAMP7TRG_Pos               (30U)
36977 #define TAMP_CR2_TAMP7TRG_Msk               (0x1UL << TAMP_CR2_TAMP7TRG_Pos)        /*!< 0x02000000 */
36978 #define TAMP_CR2_TAMP7TRG                   TAMP_CR2_TAMP7TRG_Msk
36979 
36980 /********************  Bits definition for TAMP_CR3 register  *****************/
36981 #define TAMP_CR3_ITAMP1POM_Pos              (0U)
36982 #define TAMP_CR3_ITAMP1POM_Msk              (0x1UL << TAMP_CR3_ITAMP1POM_Pos)       /*!< 0x00000001 */
36983 #define TAMP_CR3_ITAMP1POM                  TAMP_CR3_ITAMP1POM_Msk
36984 #define TAMP_CR3_ITAMP2POM_Pos              (1U)
36985 #define TAMP_CR3_ITAMP2POM_Msk              (0x1UL << TAMP_CR3_ITAMP2POM_Pos)       /*!< 0x00000002 */
36986 #define TAMP_CR3_ITAMP2POM                  TAMP_CR3_ITAMP2POM_Msk
36987 #define TAMP_CR3_ITAMP3POM_Pos              (2U)
36988 #define TAMP_CR3_ITAMP3POM_Msk              (0x1UL << TAMP_CR3_ITAMP3POM_Pos)       /*!< 0x00000004 */
36989 #define TAMP_CR3_ITAMP3POM                  TAMP_CR3_ITAMP3POM_Msk
36990 #define TAMP_CR3_ITAMP4POM_Pos              (3U)
36991 #define TAMP_CR3_ITAMP4POM_Msk              (0x1UL << TAMP_CR3_ITAMP4POM_Pos)       /*!< 0x00000008 */
36992 #define TAMP_CR3_ITAMP4POM                  TAMP_CR3_ITAMP4POM_Msk
36993 #define TAMP_CR3_ITAMP5POM_Pos              (4U)
36994 #define TAMP_CR3_ITAMP5POM_Msk              (0x1UL << TAMP_CR3_ITAMP5POM_Pos)       /*!< 0x00000010 */
36995 #define TAMP_CR3_ITAMP5POM                  TAMP_CR3_ITAMP5POM_Msk
36996 #define TAMP_CR3_ITAMP6POM_Pos              (5U)
36997 #define TAMP_CR3_ITAMP6POM_Msk              (0x1UL << TAMP_CR3_ITAMP6POM_Pos)       /*!< 0x00000020 */
36998 #define TAMP_CR3_ITAMP6POM                  TAMP_CR3_ITAMP6POM_Msk
36999 #define TAMP_CR3_ITAMP7POM_Pos              (6U)
37000 #define TAMP_CR3_ITAMP7POM_Msk              (0x1UL << TAMP_CR3_ITAMP7POM_Pos)       /*!< 0x00000040 */
37001 #define TAMP_CR3_ITAMP7POM                  TAMP_CR3_ITAMP7POM_Msk
37002 #define TAMP_CR3_ITAMP8POM_Pos              (7U)
37003 #define TAMP_CR3_ITAMP8POM_Msk              (0x1UL << TAMP_CR3_ITAMP8POM_Pos)       /*!< 0x00000080 */
37004 #define TAMP_CR3_ITAMP8POM                  TAMP_CR3_ITAMP8POM_Msk
37005 #define TAMP_CR3_ITAMP9POM_Pos              (8U)
37006 #define TAMP_CR3_ITAMP9POM_Msk              (0x1UL << TAMP_CR3_ITAMP9POM_Pos)       /*!< 0x00000100 */
37007 #define TAMP_CR3_ITAMP9POM                  TAMP_CR3_ITAMP9POM_Msk
37008 #define TAMP_CR3_ITAMP11POM_Pos             (10U)
37009 #define TAMP_CR3_ITAMP11POM_Msk             (0x1UL << TAMP_CR3_ITAMP11POM_Pos)      /*!< 0x00000400 */
37010 #define TAMP_CR3_ITAMP11POM                 TAMP_CR3_ITAMP11POM_Msk
37011 
37012 /********************  Bits definition for TAMP_FLTCR register  ***************/
37013 #define TAMP_FLTCR_TAMPFREQ_Pos             (0U)
37014 #define TAMP_FLTCR_TAMPFREQ_Msk             (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000007 */
37015 #define TAMP_FLTCR_TAMPFREQ                 TAMP_FLTCR_TAMPFREQ_Msk
37016 #define TAMP_FLTCR_TAMPFREQ_0               (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000001 */
37017 #define TAMP_FLTCR_TAMPFREQ_1               (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000002 */
37018 #define TAMP_FLTCR_TAMPFREQ_2               (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000004 */
37019 #define TAMP_FLTCR_TAMPFLT_Pos              (3U)
37020 #define TAMP_FLTCR_TAMPFLT_Msk              (0x3UL << TAMP_FLTCR_TAMPFLT_Pos)       /*!< 0x00000018 */
37021 #define TAMP_FLTCR_TAMPFLT                  TAMP_FLTCR_TAMPFLT_Msk
37022 #define TAMP_FLTCR_TAMPFLT_0                (0x1UL << TAMP_FLTCR_TAMPFLT_Pos)       /*!< 0x00000008 */
37023 #define TAMP_FLTCR_TAMPFLT_1                (0x2UL << TAMP_FLTCR_TAMPFLT_Pos)       /*!< 0x00000010 */
37024 #define TAMP_FLTCR_TAMPPRCH_Pos             (5U)
37025 #define TAMP_FLTCR_TAMPPRCH_Msk             (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos)      /*!< 0x00000060 */
37026 #define TAMP_FLTCR_TAMPPRCH                 TAMP_FLTCR_TAMPPRCH_Msk
37027 #define TAMP_FLTCR_TAMPPRCH_0               (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos)      /*!< 0x00000020 */
37028 #define TAMP_FLTCR_TAMPPRCH_1               (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos)      /*!< 0x00000040 */
37029 #define TAMP_FLTCR_TAMPPUDIS_Pos            (7U)
37030 #define TAMP_FLTCR_TAMPPUDIS_Msk            (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos)     /*!< 0x00000080 */
37031 #define TAMP_FLTCR_TAMPPUDIS                TAMP_FLTCR_TAMPPUDIS_Msk
37032 
37033 /********************  Bits definition for TAMP_ATCR1 register  ***************/
37034 #define TAMP_ATCR1_TAMP1AM_Pos              (0U)
37035 #define TAMP_ATCR1_TAMP1AM_Msk              (0x1UL << TAMP_ATCR1_TAMP1AM_Pos)       /*!< 0x00000001 */
37036 #define TAMP_ATCR1_TAMP1AM                  TAMP_ATCR1_TAMP1AM_Msk
37037 #define TAMP_ATCR1_TAMP2AM_Pos              (1U)
37038 #define TAMP_ATCR1_TAMP2AM_Msk              (0x1UL << TAMP_ATCR1_TAMP2AM_Pos)       /*!< 0x00000002 */
37039 #define TAMP_ATCR1_TAMP2AM                  TAMP_ATCR1_TAMP2AM_Msk
37040 #define TAMP_ATCR1_TAMP3AM_Pos              (2U)
37041 #define TAMP_ATCR1_TAMP3AM_Msk              (0x1UL << TAMP_ATCR1_TAMP3AM_Pos)       /*!< 0x00000004 */
37042 #define TAMP_ATCR1_TAMP3AM                  TAMP_ATCR1_TAMP3AM_Msk
37043 #define TAMP_ATCR1_TAMP4AM_Pos              (3U)
37044 #define TAMP_ATCR1_TAMP4AM_Msk              (0x1UL << TAMP_ATCR1_TAMP4AM_Pos)       /*!< 0x00000008 */
37045 #define TAMP_ATCR1_TAMP4AM                  TAMP_ATCR1_TAMP4AM_Msk
37046 #define TAMP_ATCR1_TAMP5AM_Pos              (4U)
37047 #define TAMP_ATCR1_TAMP5AM_Msk              (0x1UL << TAMP_ATCR1_TAMP5AM_Pos)       /*!< 0x00000010 */
37048 #define TAMP_ATCR1_TAMP5AM                  TAMP_ATCR1_TAMP5AM_Msk
37049 #define TAMP_ATCR1_TAMP6AM_Pos              (5U)
37050 #define TAMP_ATCR1_TAMP6AM_Msk              (0x1UL << TAMP_ATCR1_TAMP6AM_Pos)       /*!< 0x00000010 */
37051 #define TAMP_ATCR1_TAMP6AM                  TAMP_ATCR1_TAMP6AM_Msk
37052 #define TAMP_ATCR1_TAMP7AM_Pos              (6U)
37053 #define TAMP_ATCR1_TAMP7AM_Msk              (0x1UL << TAMP_ATCR1_TAMP7AM_Pos)       /*!< 0x00000040 */
37054 #define TAMP_ATCR1_TAMP7AM                  TAMP_ATCR1_TAMP7AM_Msk
37055 #define TAMP_ATCR1_ATOSEL1_Pos              (8U)
37056 #define TAMP_ATCR1_ATOSEL1_Msk              (0x3UL << TAMP_ATCR1_ATOSEL1_Pos)       /*!< 0x00000300 */
37057 #define TAMP_ATCR1_ATOSEL1                  TAMP_ATCR1_ATOSEL1_Msk
37058 #define TAMP_ATCR1_ATOSEL1_0                (0x1UL << TAMP_ATCR1_ATOSEL1_Pos)       /*!< 0x00000100 */
37059 #define TAMP_ATCR1_ATOSEL1_1                (0x2UL << TAMP_ATCR1_ATOSEL1_Pos)       /*!< 0x00000200 */
37060 #define TAMP_ATCR1_ATOSEL2_Pos              (10U)
37061 #define TAMP_ATCR1_ATOSEL2_Msk              (0x3UL << TAMP_ATCR1_ATOSEL2_Pos)       /*!< 0x00000C00 */
37062 #define TAMP_ATCR1_ATOSEL2                  TAMP_ATCR1_ATOSEL2_Msk
37063 #define TAMP_ATCR1_ATOSEL2_0                (0x1UL << TAMP_ATCR1_ATOSEL2_Pos)       /*!< 0x00000400 */
37064 #define TAMP_ATCR1_ATOSEL2_1                (0x2UL << TAMP_ATCR1_ATOSEL2_Pos)       /*!< 0x00000800 */
37065 #define TAMP_ATCR1_ATOSEL3_Pos              (12U)
37066 #define TAMP_ATCR1_ATOSEL3_Msk              (0x3UL << TAMP_ATCR1_ATOSEL3_Pos)       /*!< 0x00003000 */
37067 #define TAMP_ATCR1_ATOSEL3                  TAMP_ATCR1_ATOSEL3_Msk
37068 #define TAMP_ATCR1_ATOSEL3_0                (0x1UL << TAMP_ATCR1_ATOSEL3_Pos)       /*!< 0x00001000 */
37069 #define TAMP_ATCR1_ATOSEL3_1                (0x2UL << TAMP_ATCR1_ATOSEL3_Pos)       /*!< 0x00002000 */
37070 #define TAMP_ATCR1_ATOSEL4_Pos              (14U)
37071 #define TAMP_ATCR1_ATOSEL4_Msk              (0x3UL << TAMP_ATCR1_ATOSEL4_Pos)       /*!< 0x0000C000 */
37072 #define TAMP_ATCR1_ATOSEL4                  TAMP_ATCR1_ATOSEL4_Msk
37073 #define TAMP_ATCR1_ATOSEL4_0                (0x1UL << TAMP_ATCR1_ATOSEL4_Pos)       /*!< 0x00004000 */
37074 #define TAMP_ATCR1_ATOSEL4_1                (0x2UL << TAMP_ATCR1_ATOSEL4_Pos)       /*!< 0x00008000 */
37075 #define TAMP_ATCR1_ATCKSEL_Pos              (16U)
37076 #define TAMP_ATCR1_ATCKSEL_Msk              (0xFUL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x000F0000 */
37077 #define TAMP_ATCR1_ATCKSEL                  TAMP_ATCR1_ATCKSEL_Msk
37078 #define TAMP_ATCR1_ATCKSEL_0                (0x1UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00010000 */
37079 #define TAMP_ATCR1_ATCKSEL_1                (0x2UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00020000 */
37080 #define TAMP_ATCR1_ATCKSEL_2                (0x4UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00040000 */
37081 #define TAMP_ATCR1_ATCKSEL_3                (0x8UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00080000 */
37082 #define TAMP_ATCR1_ATPER_Pos                (24U)
37083 #define TAMP_ATCR1_ATPER_Msk                (0x7UL << TAMP_ATCR1_ATPER_Pos)         /*!< 0x07000000 */
37084 #define TAMP_ATCR1_ATPER                    TAMP_ATCR1_ATPER_Msk
37085 #define TAMP_ATCR1_ATPER_0                  (0x1UL << TAMP_ATCR1_ATPER_Pos)         /*!< 0x01000000 */
37086 #define TAMP_ATCR1_ATPER_1                  (0x2UL << TAMP_ATCR1_ATPER_Pos)         /*!< 0x02000000 */
37087 #define TAMP_ATCR1_ATPER_2                  (0x4UL << TAMP_ATCR1_ATPER_Pos)         /*!< 0x04000000 */
37088 #define TAMP_ATCR1_ATOSHARE_Pos             (30U)
37089 #define TAMP_ATCR1_ATOSHARE_Msk             (0x1UL << TAMP_ATCR1_ATOSHARE_Pos)      /*!< 0x40000000 */
37090 #define TAMP_ATCR1_ATOSHARE                 TAMP_ATCR1_ATOSHARE_Msk
37091 #define TAMP_ATCR1_FLTEN_Pos                (31U)
37092 #define TAMP_ATCR1_FLTEN_Msk                (0x1UL << TAMP_ATCR1_FLTEN_Pos)         /*!< 0x80000000 */
37093 #define TAMP_ATCR1_FLTEN                    TAMP_ATCR1_FLTEN_Msk
37094 
37095 /********************  Bits definition for TAMP_ATSEEDR register  ******************/
37096 #define TAMP_ATSEEDR_SEED_Pos               (0U)
37097 #define TAMP_ATSEEDR_SEED_Msk               (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */
37098 #define TAMP_ATSEEDR_SEED                   TAMP_ATSEEDR_SEED_Msk
37099 
37100 /********************  Bits definition for TAMP_ATOR register  ******************/
37101 #define TAMP_ATOR_PRNG_Pos                  (0U)
37102 #define TAMP_ATOR_PRNG_Msk                  (0xFFUL << TAMP_ATOR_PRNG_Pos)          /*!< 0x000000FF */
37103 #define TAMP_ATOR_PRNG                      TAMP_ATOR_PRNG_Msk
37104 #define TAMP_ATOR_PRNG_0                    (0x1UL << TAMP_ATOR_PRNG_Pos)           /*!< 0x00000001 */
37105 #define TAMP_ATOR_PRNG_1                    (0x2UL << TAMP_ATOR_PRNG_Pos)           /*!< 0x00000002 */
37106 #define TAMP_ATOR_PRNG_2                    (0x4UL << TAMP_ATOR_PRNG_Pos)           /*!< 0x00000004 */
37107 #define TAMP_ATOR_PRNG_3                    (0x8UL << TAMP_ATOR_PRNG_Pos)           /*!< 0x00000008 */
37108 #define TAMP_ATOR_PRNG_4                    (0x10UL << TAMP_ATOR_PRNG_Pos)          /*!< 0x00000010 */
37109 #define TAMP_ATOR_PRNG_5                    (0x20UL << TAMP_ATOR_PRNG_Pos)          /*!< 0x00000020 */
37110 #define TAMP_ATOR_PRNG_6                    (0x40UL << TAMP_ATOR_PRNG_Pos)          /*!< 0x00000040 */
37111 #define TAMP_ATOR_PRNG_7                    (0x80UL << TAMP_ATOR_PRNG_Pos)          /*!< 0x00000080 */
37112 #define TAMP_ATOR_SEEDF_Pos                 (14U)
37113 #define TAMP_ATOR_SEEDF_Msk                 (1UL << TAMP_ATOR_SEEDF_Pos)            /*!< 0x00004000 */
37114 #define TAMP_ATOR_SEEDF                     TAMP_ATOR_SEEDF_Msk
37115 #define TAMP_ATOR_INITS_Pos                 (15U)
37116 #define TAMP_ATOR_INITS_Msk                 (1UL << TAMP_ATOR_INITS_Pos)            /*!< 0x00008000 */
37117 #define TAMP_ATOR_INITS                     TAMP_ATOR_INITS_Msk
37118 
37119 /********************  Bits definition for TAMP_ATCR2 register  ***************/
37120 #define TAMP_ATCR2_ATOSEL1_Pos              (8U)
37121 #define TAMP_ATCR2_ATOSEL1_Msk              (0x7UL << TAMP_ATCR2_ATOSEL1_Pos)       /*!< 0x00000700 */
37122 #define TAMP_ATCR2_ATOSEL1                  TAMP_ATCR2_ATOSEL1_Msk
37123 #define TAMP_ATCR2_ATOSEL1_0                (0x1UL << TAMP_ATCR2_ATOSEL1_Pos)       /*!< 0x00000100 */
37124 #define TAMP_ATCR2_ATOSEL1_1                (0x2UL << TAMP_ATCR2_ATOSEL1_Pos)       /*!< 0x00000200 */
37125 #define TAMP_ATCR2_ATOSEL1_2                (0x4UL << TAMP_ATCR2_ATOSEL1_Pos)       /*!< 0x00000400 */
37126 #define TAMP_ATCR2_ATOSEL2_Pos              (11U)
37127 #define TAMP_ATCR2_ATOSEL2_Msk              (0x7UL << TAMP_ATCR2_ATOSEL2_Pos)       /*!< 0x00003800 */
37128 #define TAMP_ATCR2_ATOSEL2                  TAMP_ATCR2_ATOSEL2_Msk
37129 #define TAMP_ATCR2_ATOSEL2_0                (0x1UL << TAMP_ATCR2_ATOSEL2_Pos)       /*!< 0x00000800 */
37130 #define TAMP_ATCR2_ATOSEL2_1                (0x2UL << TAMP_ATCR2_ATOSEL2_Pos)       /*!< 0x00001000 */
37131 #define TAMP_ATCR2_ATOSEL2_2                (0x4UL << TAMP_ATCR2_ATOSEL2_Pos)       /*!< 0x00002000 */
37132 #define TAMP_ATCR2_ATOSEL3_Pos              (14U)
37133 #define TAMP_ATCR2_ATOSEL3_Msk              (0x7UL << TAMP_ATCR2_ATOSEL3_Pos)       /*!< 0x0001C000 */
37134 #define TAMP_ATCR2_ATOSEL3                  TAMP_ATCR2_ATOSEL3_Msk
37135 #define TAMP_ATCR2_ATOSEL3_0                (0x1UL << TAMP_ATCR2_ATOSEL3_Pos)       /*!< 0x00004000 */
37136 #define TAMP_ATCR2_ATOSEL3_1                (0x2UL << TAMP_ATCR2_ATOSEL3_Pos)       /*!< 0x00008000 */
37137 #define TAMP_ATCR2_ATOSEL3_2                (0x4UL << TAMP_ATCR2_ATOSEL3_Pos)       /*!< 0x00010000 */
37138 #define TAMP_ATCR2_ATOSEL4_Pos              (17U)
37139 #define TAMP_ATCR2_ATOSEL4_Msk              (0x7UL << TAMP_ATCR2_ATOSEL4_Pos)       /*!< 0x000E0000 */
37140 #define TAMP_ATCR2_ATOSEL4                  TAMP_ATCR2_ATOSEL4_Msk
37141 #define TAMP_ATCR2_ATOSEL4_0                (0x1UL << TAMP_ATCR2_ATOSEL4_Pos)       /*!< 0x00020000 */
37142 #define TAMP_ATCR2_ATOSEL4_1                (0x2UL << TAMP_ATCR2_ATOSEL4_Pos)       /*!< 0x00040000 */
37143 #define TAMP_ATCR2_ATOSEL4_2                (0x4UL << TAMP_ATCR2_ATOSEL4_Pos)       /*!< 0x00080000 */
37144 #define TAMP_ATCR2_ATOSEL5_Pos              (20U)
37145 #define TAMP_ATCR2_ATOSEL5_Msk              (0x7UL << TAMP_ATCR2_ATOSEL5_Pos)       /*!< 0x00700000 */
37146 #define TAMP_ATCR2_ATOSEL5                  TAMP_ATCR2_ATOSEL5_Msk
37147 #define TAMP_ATCR2_ATOSEL5_0                (0x1UL << TAMP_ATCR2_ATOSEL5_Pos)       /*!< 0x00100000 */
37148 #define TAMP_ATCR2_ATOSEL5_1                (0x2UL << TAMP_ATCR2_ATOSEL5_Pos)       /*!< 0x00200000 */
37149 #define TAMP_ATCR2_ATOSEL5_2                (0x4UL << TAMP_ATCR2_ATOSEL5_Pos)       /*!< 0x00400000 */
37150 #define TAMP_ATCR2_ATOSEL6_Pos              (23U)
37151 #define TAMP_ATCR2_ATOSEL6_Msk              (0x7UL << TAMP_ATCR2_ATOSEL6_Pos)       /*!< 0x03800000 */
37152 #define TAMP_ATCR2_ATOSEL6                  TAMP_ATCR2_ATOSEL6_Msk
37153 #define TAMP_ATCR2_ATOSEL6_0                (0x1UL << TAMP_ATCR2_ATOSEL6_Pos)       /*!< 0x00800000 */
37154 #define TAMP_ATCR2_ATOSEL6_1                (0x2UL << TAMP_ATCR2_ATOSEL6_Pos)       /*!< 0x01000000 */
37155 #define TAMP_ATCR2_ATOSEL6_2                (0x4UL << TAMP_ATCR2_ATOSEL6_Pos)       /*!< 0x02000000 */
37156 #define TAMP_ATCR2_ATOSEL7_Pos              (26U)
37157 #define TAMP_ATCR2_ATOSEL7_Msk              (0x7UL << TAMP_ATCR2_ATOSEL7_Pos)       /*!< 0x1C000000 */
37158 #define TAMP_ATCR2_ATOSEL7                  TAMP_ATCR2_ATOSEL7_Msk
37159 #define TAMP_ATCR2_ATOSEL7_0                (0x1UL << TAMP_ATCR2_ATOSEL7_Pos)       /*!< 0x04000000 */
37160 #define TAMP_ATCR2_ATOSEL7_1                (0x2UL << TAMP_ATCR2_ATOSEL7_Pos)       /*!< 0x08000000 */
37161 #define TAMP_ATCR2_ATOSEL7_2                (0x4UL << TAMP_ATCR2_ATOSEL7_Pos)       /*!< 0x10000000 */
37162 
37163 /********************  Bits definition for TAMP_SECCFGR register  *************/
37164 #define TAMP_SECCFGR_BKPRWSEC_Pos           (0U)
37165 #define TAMP_SECCFGR_BKPRWSEC_Msk           (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x000000FF */
37166 #define TAMP_SECCFGR_BKPRWSEC               TAMP_SECCFGR_BKPRWSEC_Msk
37167 #define TAMP_SECCFGR_BKPRWSEC_0             (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos)    /*!< 0x00000001 */
37168 #define TAMP_SECCFGR_BKPRWSEC_1             (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos)    /*!< 0x00000002 */
37169 #define TAMP_SECCFGR_BKPRWSEC_2             (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos)    /*!< 0x00000004 */
37170 #define TAMP_SECCFGR_BKPRWSEC_3             (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos)    /*!< 0x00000008 */
37171 #define TAMP_SECCFGR_BKPRWSEC_4             (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x00000010 */
37172 #define TAMP_SECCFGR_BKPRWSEC_5             (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x00000020 */
37173 #define TAMP_SECCFGR_BKPRWSEC_6             (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x00000040 */
37174 #define TAMP_SECCFGR_BKPRWSEC_7             (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x00000080 */
37175 #define TAMP_SECCFGR_CNT1SEC_Pos            (15U)
37176 #define TAMP_SECCFGR_CNT1SEC_Msk            (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos)     /*!< 0x00008000 */
37177 #define TAMP_SECCFGR_CNT1SEC                TAMP_SECCFGR_CNT1SEC_Msk
37178 #define TAMP_SECCFGR_BKPWSEC_Pos            (16U)
37179 #define TAMP_SECCFGR_BKPWSEC_Msk            (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00FF0000 */
37180 #define TAMP_SECCFGR_BKPWSEC                TAMP_SECCFGR_BKPWSEC_Msk
37181 #define TAMP_SECCFGR_BKPWSEC_0              (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos)     /*!< 0x00010000 */
37182 #define TAMP_SECCFGR_BKPWSEC_1              (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos)     /*!< 0x00020000 */
37183 #define TAMP_SECCFGR_BKPWSEC_2              (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos)     /*!< 0x00040000 */
37184 #define TAMP_SECCFGR_BKPWSEC_3              (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos)     /*!< 0x00080000 */
37185 #define TAMP_SECCFGR_BKPWSEC_4              (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00100000 */
37186 #define TAMP_SECCFGR_BKPWSEC_5              (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00200000 */
37187 #define TAMP_SECCFGR_BKPWSEC_6              (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00400000 */
37188 #define TAMP_SECCFGR_BKPWSEC_7              (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00800000 */
37189 #define TAMP_SECCFGR_BHKLOCK_Pos            (30U)
37190 #define TAMP_SECCFGR_BHKLOCK_Msk            (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos)     /*!< 0x40000000 */
37191 #define TAMP_SECCFGR_BHKLOCK                TAMP_SECCFGR_BHKLOCK_Msk
37192 #define TAMP_SECCFGR_TAMPSEC_Pos            (31U)
37193 #define TAMP_SECCFGR_TAMPSEC_Msk            (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos)     /*!< 0x80000000 */
37194 #define TAMP_SECCFGR_TAMPSEC                TAMP_SECCFGR_TAMPSEC_Msk
37195 
37196 /********************  Bits definition for TAMP_PRIVCFGR register  ************/
37197 #define TAMP_PRIVCFGR_CNT1PRIV_Pos          (15U)
37198 #define TAMP_PRIVCFGR_CNT1PRIV_Msk          (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos)   /*!< 0x20000000 */
37199 #define TAMP_PRIVCFGR_CNT1PRIV              TAMP_PRIVCFGR_CNT1PRIV_Msk
37200 #define TAMP_PRIVCFGR_BKPRWPRIV_Pos         (29U)
37201 #define TAMP_PRIVCFGR_BKPRWPRIV_Msk         (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos)  /*!< 0x20000000 */
37202 #define TAMP_PRIVCFGR_BKPRWPRIV             TAMP_PRIVCFGR_BKPRWPRIV_Msk
37203 #define TAMP_PRIVCFGR_BKPWPRIV_Pos          (30U)
37204 #define TAMP_PRIVCFGR_BKPWPRIV_Msk          (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos)   /*!< 0x40000000 */
37205 #define TAMP_PRIVCFGR_BKPWPRIV              TAMP_PRIVCFGR_BKPWPRIV_Msk
37206 #define TAMP_PRIVCFGR_TAMPPRIV_Pos          (31U)
37207 #define TAMP_PRIVCFGR_TAMPPRIV_Msk          (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos)   /*!< 0x80000000 */
37208 #define TAMP_PRIVCFGR_TAMPPRIV              TAMP_PRIVCFGR_TAMPPRIV_Msk
37209 
37210 /********************  Bits definition for TAMP_IER register  *****************/
37211 #define TAMP_IER_TAMP1IE_Pos                (0U)
37212 #define TAMP_IER_TAMP1IE_Msk                (0x1UL << TAMP_IER_TAMP1IE_Pos)         /*!< 0x00000001 */
37213 #define TAMP_IER_TAMP1IE                    TAMP_IER_TAMP1IE_Msk
37214 #define TAMP_IER_TAMP2IE_Pos                (1U)
37215 #define TAMP_IER_TAMP2IE_Msk                (0x1UL << TAMP_IER_TAMP2IE_Pos)         /*!< 0x00000002 */
37216 #define TAMP_IER_TAMP2IE                    TAMP_IER_TAMP2IE_Msk
37217 #define TAMP_IER_TAMP3IE_Pos                (2U)
37218 #define TAMP_IER_TAMP3IE_Msk                (0x1UL << TAMP_IER_TAMP3IE_Pos)         /*!< 0x00000004 */
37219 #define TAMP_IER_TAMP3IE                    TAMP_IER_TAMP3IE_Msk
37220 #define TAMP_IER_TAMP4IE_Pos                (3U)
37221 #define TAMP_IER_TAMP4IE_Msk                (0x1UL << TAMP_IER_TAMP4IE_Pos)         /*!< 0x00000008 */
37222 #define TAMP_IER_TAMP4IE                    TAMP_IER_TAMP4IE_Msk
37223 #define TAMP_IER_TAMP5IE_Pos                (4U)
37224 #define TAMP_IER_TAMP5IE_Msk                (0x1UL << TAMP_IER_TAMP5IE_Pos)         /*!< 0x00000010 */
37225 #define TAMP_IER_TAMP5IE                    TAMP_IER_TAMP5IE_Msk
37226 #define TAMP_IER_TAMP6IE_Pos                (5U)
37227 #define TAMP_IER_TAMP6IE_Msk                (0x1UL << TAMP_IER_TAMP6IE_Pos)         /*!< 0x00000020 */
37228 #define TAMP_IER_TAMP6IE                    TAMP_IER_TAMP6IE_Msk
37229 #define TAMP_IER_TAMP7IE_Pos                (6U)
37230 #define TAMP_IER_TAMP7IE_Msk                (0x1UL << TAMP_IER_TAMP7IE_Pos)         /*!< 0x00000040 */
37231 #define TAMP_IER_TAMP7IE                    TAMP_IER_TAMP7IE_Msk
37232 #define TAMP_IER_ITAMP1IE_Pos               (16U)
37233 #define TAMP_IER_ITAMP1IE_Msk               (0x1UL << TAMP_IER_ITAMP1IE_Pos)        /*!< 0x00010000 */
37234 #define TAMP_IER_ITAMP1IE                   TAMP_IER_ITAMP1IE_Msk
37235 #define TAMP_IER_ITAMP2IE_Pos               (17U)
37236 #define TAMP_IER_ITAMP2IE_Msk               (0x1UL << TAMP_IER_ITAMP2IE_Pos)        /*!< 0x00020000 */
37237 #define TAMP_IER_ITAMP2IE                   TAMP_IER_ITAMP2IE_Msk
37238 #define TAMP_IER_ITAMP3IE_Pos               (18U)
37239 #define TAMP_IER_ITAMP3IE_Msk               (0x1UL << TAMP_IER_ITAMP3IE_Pos)        /*!< 0x00040000 */
37240 #define TAMP_IER_ITAMP3IE                   TAMP_IER_ITAMP3IE_Msk
37241 #define TAMP_IER_ITAMP4IE_Pos               (19U)
37242 #define TAMP_IER_ITAMP4IE_Msk               (0x1UL << TAMP_IER_ITAMP4IE_Pos)        /*!< 0x00080000 */
37243 #define TAMP_IER_ITAMP4IE                   TAMP_IER_ITAMP4IE_Msk
37244 #define TAMP_IER_ITAMP5IE_Pos               (20U)
37245 #define TAMP_IER_ITAMP5IE_Msk               (0x1UL << TAMP_IER_ITAMP5IE_Pos)        /*!< 0x00100000 */
37246 #define TAMP_IER_ITAMP5IE                   TAMP_IER_ITAMP5IE_Msk
37247 #define TAMP_IER_ITAMP6IE_Pos               (21U)
37248 #define TAMP_IER_ITAMP6IE_Msk               (0x1UL << TAMP_IER_ITAMP6IE_Pos)        /*!< 0x00200000 */
37249 #define TAMP_IER_ITAMP6IE                   TAMP_IER_ITAMP6IE_Msk
37250 #define TAMP_IER_ITAMP7IE_Pos               (22U)
37251 #define TAMP_IER_ITAMP7IE_Msk               (0x1UL << TAMP_IER_ITAMP7IE_Pos)        /*!< 0x00400000 */
37252 #define TAMP_IER_ITAMP7IE                   TAMP_IER_ITAMP7IE_Msk
37253 #define TAMP_IER_ITAMP8IE_Pos               (23U)
37254 #define TAMP_IER_ITAMP8IE_Msk               (0x1UL << TAMP_IER_ITAMP8IE_Pos)        /*!< 0x00800000 */
37255 #define TAMP_IER_ITAMP8IE                   TAMP_IER_ITAMP8IE_Msk
37256 #define TAMP_IER_ITAMP9IE_Pos               (24U)
37257 #define TAMP_IER_ITAMP9IE_Msk               (0x1UL << TAMP_IER_ITAMP9IE_Pos)        /*!< 0x01000000 */
37258 #define TAMP_IER_ITAMP9IE                   TAMP_IER_ITAMP9IE_Msk
37259 #define TAMP_IER_ITAMP11IE_Pos              (26U)
37260 #define TAMP_IER_ITAMP11IE_Msk              (0x1UL << TAMP_IER_ITAMP11IE_Pos)       /*!< 0x04000000 */
37261 #define TAMP_IER_ITAMP11IE                  TAMP_IER_ITAMP11IE_Msk
37262 
37263 /********************  Bits definition for TAMP_SR register  *****************/
37264 #define TAMP_SR_TAMP1F_Pos                  (0U)
37265 #define TAMP_SR_TAMP1F_Msk                  (0x1UL << TAMP_SR_TAMP1F_Pos)           /*!< 0x00000001 */
37266 #define TAMP_SR_TAMP1F                      TAMP_SR_TAMP1F_Msk
37267 #define TAMP_SR_TAMP2F_Pos                  (1U)
37268 #define TAMP_SR_TAMP2F_Msk                  (0x1UL << TAMP_SR_TAMP2F_Pos)           /*!< 0x00000002 */
37269 #define TAMP_SR_TAMP2F                      TAMP_SR_TAMP2F_Msk
37270 #define TAMP_SR_TAMP3F_Pos                  (2U)
37271 #define TAMP_SR_TAMP3F_Msk                  (0x1UL << TAMP_SR_TAMP3F_Pos)           /*!< 0x00000004 */
37272 #define TAMP_SR_TAMP3F                      TAMP_SR_TAMP3F_Msk
37273 #define TAMP_SR_TAMP4F_Pos                  (3U)
37274 #define TAMP_SR_TAMP4F_Msk                  (0x1UL << TAMP_SR_TAMP4F_Pos)           /*!< 0x00000008 */
37275 #define TAMP_SR_TAMP4F                      TAMP_SR_TAMP4F_Msk
37276 #define TAMP_SR_TAMP5F_Pos                  (4U)
37277 #define TAMP_SR_TAMP5F_Msk                  (0x1UL << TAMP_SR_TAMP5F_Pos)           /*!< 0x00000010 */
37278 #define TAMP_SR_TAMP5F                      TAMP_SR_TAMP5F_Msk
37279 #define TAMP_SR_TAMP6F_Pos                  (5U)
37280 #define TAMP_SR_TAMP6F_Msk                  (0x1UL << TAMP_SR_TAMP6F_Pos)           /*!< 0x00000020 */
37281 #define TAMP_SR_TAMP6F                      TAMP_SR_TAMP6F_Msk
37282 #define TAMP_SR_TAMP7F_Pos                  (6U)
37283 #define TAMP_SR_TAMP7F_Msk                  (0x1UL << TAMP_SR_TAMP7F_Pos)           /*!< 0x00000040 */
37284 #define TAMP_SR_TAMP7F                      TAMP_SR_TAMP7F_Msk
37285 #define TAMP_SR_ITAMP1F_Pos                 (16U)
37286 #define TAMP_SR_ITAMP1F_Msk                 (0x1UL << TAMP_SR_ITAMP1F_Pos)          /*!< 0x00010000 */
37287 #define TAMP_SR_ITAMP1F                     TAMP_SR_ITAMP1F_Msk
37288 #define TAMP_SR_ITAMP2F_Pos                 (17U)
37289 #define TAMP_SR_ITAMP2F_Msk                 (0x1UL << TAMP_SR_ITAMP2F_Pos)          /*!< 0x00020000 */
37290 #define TAMP_SR_ITAMP2F                     TAMP_SR_ITAMP2F_Msk
37291 #define TAMP_SR_ITAMP3F_Pos                 (18U)
37292 #define TAMP_SR_ITAMP3F_Msk                 (0x1UL << TAMP_SR_ITAMP3F_Pos)          /*!< 0x00040000 */
37293 #define TAMP_SR_ITAMP3F                     TAMP_SR_ITAMP3F_Msk
37294 #define TAMP_SR_ITAMP4F_Pos                 (19U)
37295 #define TAMP_SR_ITAMP4F_Msk                 (0x1UL << TAMP_SR_ITAMP4F_Pos)          /*!< 0x00080000 */
37296 #define TAMP_SR_ITAMP4F                     TAMP_SR_ITAMP4F_Msk
37297 #define TAMP_SR_ITAMP5F_Pos                 (20U)
37298 #define TAMP_SR_ITAMP5F_Msk                 (0x1UL << TAMP_SR_ITAMP5F_Pos)          /*!< 0x00100000 */
37299 #define TAMP_SR_ITAMP5F                     TAMP_SR_ITAMP5F_Msk
37300 #define TAMP_SR_ITAMP6F_Pos                 (21U)
37301 #define TAMP_SR_ITAMP6F_Msk                 (0x1UL << TAMP_SR_ITAMP6F_Pos)          /*!< 0x00200000 */
37302 #define TAMP_SR_ITAMP6F                     TAMP_SR_ITAMP6F_Msk
37303 #define TAMP_SR_ITAMP7F_Pos                 (22U)
37304 #define TAMP_SR_ITAMP7F_Msk                 (0x1UL << TAMP_SR_ITAMP7F_Pos)          /*!< 0x00400000 */
37305 #define TAMP_SR_ITAMP7F                     TAMP_SR_ITAMP7F_Msk
37306 #define TAMP_SR_ITAMP8F_Pos                 (23U)
37307 #define TAMP_SR_ITAMP8F_Msk                 (0x1UL << TAMP_SR_ITAMP8F_Pos)          /*!< 0x00800000 */
37308 #define TAMP_SR_ITAMP8F                     TAMP_SR_ITAMP8F_Msk
37309 #define TAMP_SR_ITAMP9F_Pos                 (24U)
37310 #define TAMP_SR_ITAMP9F_Msk                 (0x1UL << TAMP_SR_ITAMP9F_Pos)          /*!< 0x01000000 */
37311 #define TAMP_SR_ITAMP9F                     TAMP_SR_ITAMP9F_Msk
37312 #define TAMP_SR_ITAMP11F_Pos                (26U)
37313 #define TAMP_SR_ITAMP11F_Msk                (0x1UL << TAMP_SR_ITAMP11F_Pos)         /*!< 0x04000000 */
37314 #define TAMP_SR_ITAMP11F                    TAMP_SR_ITAMP11F_Msk
37315 
37316 /********************  Bits definition for TAMP_MISR register  ****************/
37317 #define TAMP_MISR_TAMP1MF_Pos               (0U)
37318 #define TAMP_MISR_TAMP1MF_Msk               (0x1UL << TAMP_MISR_TAMP1MF_Pos)        /*!< 0x00000001 */
37319 #define TAMP_MISR_TAMP1MF                   TAMP_MISR_TAMP1MF_Msk
37320 #define TAMP_MISR_TAMP2MF_Pos               (1U)
37321 #define TAMP_MISR_TAMP2MF_Msk               (0x1UL << TAMP_MISR_TAMP2MF_Pos)        /*!< 0x00000002 */
37322 #define TAMP_MISR_TAMP2MF                   TAMP_MISR_TAMP2MF_Msk
37323 #define TAMP_MISR_TAMP3MF_Pos               (2U)
37324 #define TAMP_MISR_TAMP3MF_Msk               (0x1UL << TAMP_MISR_TAMP3MF_Pos)        /*!< 0x00000004 */
37325 #define TAMP_MISR_TAMP3MF                   TAMP_MISR_TAMP3MF_Msk
37326 #define TAMP_MISR_TAMP4MF_Pos               (3U)
37327 #define TAMP_MISR_TAMP4MF_Msk               (0x1UL << TAMP_MISR_TAMP4MF_Pos)        /*!< 0x00000008 */
37328 #define TAMP_MISR_TAMP4MF                   TAMP_MISR_TAMP4MF_Msk
37329 #define TAMP_MISR_TAMP5MF_Pos               (4U)
37330 #define TAMP_MISR_TAMP5MF_Msk               (0x1UL << TAMP_MISR_TAMP5MF_Pos)        /*!< 0x00000010 */
37331 #define TAMP_MISR_TAMP5MF                   TAMP_MISR_TAMP5MF_Msk
37332 #define TAMP_MISR_TAMP6MF_Pos               (5U)
37333 #define TAMP_MISR_TAMP6MF_Msk               (0x1UL << TAMP_MISR_TAMP6MF_Pos)        /*!< 0x00000020 */
37334 #define TAMP_MISR_TAMP6MF                   TAMP_MISR_TAMP6MF_Msk
37335 #define TAMP_MISR_TAMP7MF_Pos               (6U)
37336 #define TAMP_MISR_TAMP7MF_Msk               (0x1UL << TAMP_MISR_TAMP7MF_Pos)        /*!< 0x00000040 */
37337 #define TAMP_MISR_TAMP7MF                   TAMP_MISR_TAMP7MF_Msk
37338 #define TAMP_MISR_ITAMP1MF_Pos              (16U)
37339 #define TAMP_MISR_ITAMP1MF_Msk              (0x1UL << TAMP_MISR_ITAMP1MF_Pos)       /*!< 0x00010000 */
37340 #define TAMP_MISR_ITAMP1MF                  TAMP_MISR_ITAMP1MF_Msk
37341 #define TAMP_MISR_ITAMP2MF_Pos              (17U)
37342 #define TAMP_MISR_ITAMP2MF_Msk              (0x1UL << TAMP_MISR_ITAMP2MF_Pos)       /*!< 0x00020000 */
37343 #define TAMP_MISR_ITAMP2MF                  TAMP_MISR_ITAMP2MF_Msk
37344 #define TAMP_MISR_ITAMP3MF_Pos              (18U)
37345 #define TAMP_MISR_ITAMP3MF_Msk              (0x1UL << TAMP_MISR_ITAMP3MF_Pos)       /*!< 0x00040000 */
37346 #define TAMP_MISR_ITAMP3MF                  TAMP_MISR_ITAMP3MF_Msk
37347 #define TAMP_MISR_ITAMP4MF_Pos              (19U)
37348 #define TAMP_MISR_ITAMP4MF_Msk              (0x1UL << TAMP_MISR_ITAMP4MF_Pos)       /*!< 0x00080000 */
37349 #define TAMP_MISR_ITAMP4MF                  TAMP_MISR_ITAMP4MF_Msk
37350 #define TAMP_MISR_ITAMP5MF_Pos              (20U)
37351 #define TAMP_MISR_ITAMP5MF_Msk              (0x1UL << TAMP_MISR_ITAMP5MF_Pos)       /*!< 0x00100000 */
37352 #define TAMP_MISR_ITAMP5MF                  TAMP_MISR_ITAMP5MF_Msk
37353 #define TAMP_MISR_ITAMP6MF_Pos              (21U)
37354 #define TAMP_MISR_ITAMP6MF_Msk              (0x1UL << TAMP_MISR_ITAMP6MF_Pos)       /*!< 0x00200000 */
37355 #define TAMP_MISR_ITAMP6MF                  TAMP_MISR_ITAMP6MF_Msk
37356 #define TAMP_MISR_ITAMP7MF_Pos              (22U)
37357 #define TAMP_MISR_ITAMP7MF_Msk              (0x1UL << TAMP_MISR_ITAMP7MF_Pos)       /*!< 0x00400000 */
37358 #define TAMP_MISR_ITAMP7MF                  TAMP_MISR_ITAMP7MF_Msk
37359 #define TAMP_MISR_ITAMP8MF_Pos              (23U)
37360 #define TAMP_MISR_ITAMP8MF_Msk              (0x1UL << TAMP_MISR_ITAMP8MF_Pos)       /*!< 0x00800000 */
37361 #define TAMP_MISR_ITAMP8MF                  TAMP_MISR_ITAMP8MF_Msk
37362 #define TAMP_MISR_ITAMP9MF_Pos              (24U)
37363 #define TAMP_MISR_ITAMP9MF_Msk              (0x1UL << TAMP_MISR_ITAMP9MF_Pos)       /*!< 0x01000000 */
37364 #define TAMP_MISR_ITAMP9MF                  TAMP_MISR_ITAMP9MF_Msk
37365 #define TAMP_MISR_ITAMP11MF_Pos             (26U)
37366 #define TAMP_MISR_ITAMP11MF_Msk             (0x1UL << TAMP_MISR_ITAMP11MF_Pos)      /*!< 0x04000000 */
37367 #define TAMP_MISR_ITAMP11MF                 TAMP_MISR_ITAMP11MF_Msk
37368 
37369 /********************  Bits definition for TAMP_SMISR register  ************ *****/
37370 #define TAMP_SMISR_TAMP1MF_Pos              (0U)
37371 #define TAMP_SMISR_TAMP1MF_Msk              (0x1UL << TAMP_SMISR_TAMP1MF_Pos)       /*!< 0x00000001 */
37372 #define TAMP_SMISR_TAMP1MF                  TAMP_SMISR_TAMP1MF_Msk
37373 #define TAMP_SMISR_TAMP2MF_Pos              (1U)
37374 #define TAMP_SMISR_TAMP2MF_Msk              (0x1UL << TAMP_SMISR_TAMP2MF_Pos)       /*!< 0x00000002 */
37375 #define TAMP_SMISR_TAMP2MF                  TAMP_SMISR_TAMP2MF_Msk
37376 #define TAMP_SMISR_TAMP3MF_Pos              (2U)
37377 #define TAMP_SMISR_TAMP3MF_Msk              (0x1UL << TAMP_SMISR_TAMP3MF_Pos)       /*!< 0x00000004 */
37378 #define TAMP_SMISR_TAMP3MF                  TAMP_SMISR_TAMP3MF_Msk
37379 #define TAMP_SMISR_TAMP4MF_Pos              (3U)
37380 #define TAMP_SMISR_TAMP4MF_Msk              (0x1UL << TAMP_SMISR_TAMP4MF_Pos)       /*!< 0x00000008 */
37381 #define TAMP_SMISR_TAMP4MF                  TAMP_SMISR_TAMP4MF_Msk
37382 #define TAMP_SMISR_TAMP5MF_Pos              (4U)
37383 #define TAMP_SMISR_TAMP5MF_Msk              (0x1UL << TAMP_SMISR_TAMP5MF_Pos)       /*!< 0x00000010 */
37384 #define TAMP_SMISR_TAMP5MF                  TAMP_SMISR_TAMP5MF_Msk
37385 #define TAMP_SMISR_TAMP6MF_Pos              (5U)
37386 #define TAMP_SMISR_TAMP6MF_Msk              (0x1UL << TAMP_SMISR_TAMP6MF_Pos)       /*!< 0x00000020 */
37387 #define TAMP_SMISR_TAMP6MF                  TAMP_SMISR_TAMP6MF_Msk
37388 #define TAMP_SMISR_TAMP7MF_Pos              (6U)
37389 #define TAMP_SMISR_TAMP7MF_Msk              (0x1UL << TAMP_SMISR_TAMP7MF_Pos)       /*!< 0x00000040 */
37390 #define TAMP_SMISR_TAMP7MF                  TAMP_SMISR_TAMP7MF_Msk
37391 #define TAMP_SMISR_ITAMP1MF_Pos             (16U)
37392 #define TAMP_SMISR_ITAMP1MF_Msk             (0x1UL << TAMP_SMISR_ITAMP1MF_Pos)      /*!< 0x00010000 */
37393 #define TAMP_SMISR_ITAMP1MF                 TAMP_SMISR_ITAMP1MF_Msk
37394 #define TAMP_SMISR_ITAMP2MF_Pos             (17U)
37395 #define TAMP_SMISR_ITAMP2MF_Msk             (0x1UL << TAMP_SMISR_ITAMP2MF_Pos)      /*!< 0x00020000 */
37396 #define TAMP_SMISR_ITAMP2MF                 TAMP_SMISR_ITAMP2MF_Msk
37397 #define TAMP_SMISR_ITAMP3MF_Pos             (18U)
37398 #define TAMP_SMISR_ITAMP3MF_Msk             (0x1UL << TAMP_SMISR_ITAMP3MF_Pos)      /*!< 0x00040000 */
37399 #define TAMP_SMISR_ITAMP3MF                 TAMP_SMISR_ITAMP3MF_Msk
37400 #define TAMP_SMISR_ITAMP4MF_Pos             (19U)
37401 #define TAMP_SMISR_ITAMP4MF_Msk             (0x1UL << TAMP_SMISR_ITAMP4MF_Pos)      /*!< 0x00080000 */
37402 #define TAMP_SMISR_ITAMP4MF                 TAMP_SMISR_ITAMP4MF_Msk
37403 #define TAMP_SMISR_ITAMP5MF_Pos             (20U)
37404 #define TAMP_SMISR_ITAMP5MF_Msk             (0x1UL << TAMP_SMISR_ITAMP5MF_Pos)      /*!< 0x00100000 */
37405 #define TAMP_SMISR_ITAMP5MF                 TAMP_SMISR_ITAMP5MF_Msk
37406 #define TAMP_SMISR_ITAMP6MF_Pos             (21U)
37407 #define TAMP_SMISR_ITAMP6MF_Msk             (0x1UL << TAMP_SMISR_ITAMP6MF_Pos)      /*!< 0x00200000 */
37408 #define TAMP_SMISR_ITAMP6MF                 TAMP_SMISR_ITAMP6MF_Msk
37409 #define TAMP_SMISR_ITAMP7MF_Pos             (22U)
37410 #define TAMP_SMISR_ITAMP7MF_Msk             (0x1UL << TAMP_SMISR_ITAMP7MF_Pos)      /*!< 0x00400000 */
37411 #define TAMP_SMISR_ITAMP7MF                 TAMP_SMISR_ITAMP7MF_Msk
37412 #define TAMP_SMISR_ITAMP8MF_Pos             (23U)
37413 #define TAMP_SMISR_ITAMP8MF_Msk             (0x1UL << TAMP_SMISR_ITAMP8MF_Pos)      /*!< 0x00800000 */
37414 #define TAMP_SMISR_ITAMP8MF                 TAMP_SMISR_ITAMP8MF_Msk
37415 #define TAMP_SMISR_ITAMP9MF_Pos             (24U)
37416 #define TAMP_SMISR_ITAMP9MF_Msk             (0x1UL << TAMP_SMISR_ITAMP9MF_Pos)      /*!< 0x00100000 */
37417 #define TAMP_SMISR_ITAMP9MF                 TAMP_SMISR_ITAMP9MF_Msk
37418 #define TAMP_SMISR_ITAMP11MF_Pos            (26U)
37419 #define TAMP_SMISR_ITAMP11MF_Msk            (0x1UL << TAMP_SMISR_ITAMP11MF_Pos)      /*!< 0x00400000 */
37420 #define TAMP_SMISR_ITAMP11MF                TAMP_SMISR_ITAMP11MF_Msk
37421 
37422 /********************  Bits definition for TAMP_SCR register  *****************/
37423 #define TAMP_SCR_CTAMP1F_Pos                (0U)
37424 #define TAMP_SCR_CTAMP1F_Msk                (0x1UL << TAMP_SCR_CTAMP1F_Pos)         /*!< 0x00000001 */
37425 #define TAMP_SCR_CTAMP1F                    TAMP_SCR_CTAMP1F_Msk
37426 #define TAMP_SCR_CTAMP2F_Pos                (1U)
37427 #define TAMP_SCR_CTAMP2F_Msk                (0x1UL << TAMP_SCR_CTAMP2F_Pos)         /*!< 0x00000002 */
37428 #define TAMP_SCR_CTAMP2F                    TAMP_SCR_CTAMP2F_Msk
37429 #define TAMP_SCR_CTAMP3F_Pos                (2U)
37430 #define TAMP_SCR_CTAMP3F_Msk                (0x1UL << TAMP_SCR_CTAMP3F_Pos)         /*!< 0x00000004 */
37431 #define TAMP_SCR_CTAMP3F                    TAMP_SCR_CTAMP3F_Msk
37432 #define TAMP_SCR_CTAMP4F_Pos                (3U)
37433 #define TAMP_SCR_CTAMP4F_Msk                (0x1UL << TAMP_SCR_CTAMP4F_Pos)         /*!< 0x00000008 */
37434 #define TAMP_SCR_CTAMP4F                    TAMP_SCR_CTAMP4F_Msk
37435 #define TAMP_SCR_CTAMP5F_Pos                (4U)
37436 #define TAMP_SCR_CTAMP5F_Msk                (0x1UL << TAMP_SCR_CTAMP5F_Pos)         /*!< 0x00000010 */
37437 #define TAMP_SCR_CTAMP5F                    TAMP_SCR_CTAMP5F_Msk
37438 #define TAMP_SCR_CTAMP6F_Pos                (5U)
37439 #define TAMP_SCR_CTAMP6F_Msk                (0x1UL << TAMP_SCR_CTAMP6F_Pos)         /*!< 0x00000020 */
37440 #define TAMP_SCR_CTAMP6F                    TAMP_SCR_CTAMP6F_Msk
37441 #define TAMP_SCR_CTAMP7F_Pos                (6U)
37442 #define TAMP_SCR_CTAMP7F_Msk                (0x1UL << TAMP_SCR_CTAMP7F_Pos)         /*!< 0x00000040 */
37443 #define TAMP_SCR_CTAMP7F                    TAMP_SCR_CTAMP7F_Msk
37444 #define TAMP_SCR_CTAMP8F_Pos                (7U)
37445 #define TAMP_SCR_CTAMP8F_Msk                (0x1UL << TAMP_SCR_CTAMP8F_Pos)         /*!< 0x00000080 */
37446 #define TAMP_SCR_CTAMP8F                    TAMP_SCR_CTAMP8F_Msk
37447 #define TAMP_SCR_CITAMP1F_Pos               (16U)
37448 #define TAMP_SCR_CITAMP1F_Msk               (0x1UL << TAMP_SCR_CITAMP1F_Pos)        /*!< 0x00010000 */
37449 #define TAMP_SCR_CITAMP1F                   TAMP_SCR_CITAMP1F_Msk
37450 #define TAMP_SCR_CITAMP2F_Pos               (17U)
37451 #define TAMP_SCR_CITAMP2F_Msk               (0x1UL << TAMP_SCR_CITAMP2F_Pos)        /*!< 0x00020000 */
37452 #define TAMP_SCR_CITAMP2F                   TAMP_SCR_CITAMP2F_Msk
37453 #define TAMP_SCR_CITAMP3F_Pos               (18U)
37454 #define TAMP_SCR_CITAMP3F_Msk               (0x1UL << TAMP_SCR_CITAMP3F_Pos)        /*!< 0x00040000 */
37455 #define TAMP_SCR_CITAMP3F                   TAMP_SCR_CITAMP3F_Msk
37456 #define TAMP_SCR_CITAMP4F_Pos               (19U)
37457 #define TAMP_SCR_CITAMP4F_Msk               (0x1UL << TAMP_SCR_CITAMP4F_Pos)        /*!< 0x00080000 */
37458 #define TAMP_SCR_CITAMP4F                   TAMP_SCR_CITAMP4F_Msk
37459 #define TAMP_SCR_CITAMP5F_Pos               (20U)
37460 #define TAMP_SCR_CITAMP5F_Msk               (0x1UL << TAMP_SCR_CITAMP5F_Pos)        /*!< 0x00100000 */
37461 #define TAMP_SCR_CITAMP5F                   TAMP_SCR_CITAMP5F_Msk
37462 #define TAMP_SCR_CITAMP6F_Pos               (21U)
37463 #define TAMP_SCR_CITAMP6F_Msk               (0x1UL << TAMP_SCR_CITAMP6F_Pos)        /*!< 0x00200000 */
37464 #define TAMP_SCR_CITAMP6F                   TAMP_SCR_CITAMP6F_Msk
37465 #define TAMP_SCR_CITAMP7F_Pos               (22U)
37466 #define TAMP_SCR_CITAMP7F_Msk               (0x1UL << TAMP_SCR_CITAMP7F_Pos)        /*!< 0x00400000 */
37467 #define TAMP_SCR_CITAMP7F                   TAMP_SCR_CITAMP7F_Msk
37468 #define TAMP_SCR_CITAMP8F_Pos               (23U)
37469 #define TAMP_SCR_CITAMP8F_Msk               (0x1UL << TAMP_SCR_CITAMP8F_Pos)        /*!< 0x00800000 */
37470 #define TAMP_SCR_CITAMP8F                   TAMP_SCR_CITAMP8F_Msk
37471 #define TAMP_SCR_CITAMP9F_Pos               (24U)
37472 #define TAMP_SCR_CITAMP9F_Msk               (0x1UL << TAMP_SCR_CITAMP9F_Pos)        /*!< 0x00100000 */
37473 #define TAMP_SCR_CITAMP9F                   TAMP_SCR_CITAMP9F_Msk
37474 #define TAMP_SCR_CITAMP11F_Pos              (26U)
37475 #define TAMP_SCR_CITAMP11F_Msk              (0x1UL << TAMP_SCR_CITAMP11F_Pos)       /*!< 0x00400000 */
37476 #define TAMP_SCR_CITAMP11F                  TAMP_SCR_CITAMP11F_Msk
37477 
37478 /********************  Bits definition for TAMP_COUNT1R register  ***************/
37479 #define TAMP_COUNT1R_COUNT_Pos              (0U)
37480 #define TAMP_COUNT1R_COUNT_Msk              (0xFFFFFFFFUL << TAMP_COUNT1R_COUNT_Pos)/*!< 0xFFFFFFFF */
37481 #define TAMP_COUNT1R_COUNT                  TAMP_COUNT1R_COUNT_Msk
37482 
37483 /********************  Bits definition for TAMP_OR register  ***************/
37484 #define TAMP_OR_VCOREMEN_Pos                (0U)
37485 #define TAMP_OR_VCOREMEN_Msk                (0x1UL << TAMP_OR_VCOREMEN_Pos)         /*!< 0x00000001 */
37486 #define TAMP_OR_VCOREMEN                    TAMP_OR_VCOREMEN_Msk
37487 
37488 /********************  Bits definition for TAMP_RPCFGR register  ***************/
37489 #define TAMP_RPCFGR_RPCFG0_Pos              (0U)
37490 #define TAMP_RPCFGR_RPCFG0_Msk              (0x1UL << TAMP_RPCFGR_RPCFG0_Pos)       /*!< 0x00000001 */
37491 #define TAMP_RPCFGR_RPCFG0                  TAMP_RPCFGR_RPCFG0_Msk
37492 
37493 /********************  Bits definition for TAMP_BKP0R register  ***************/
37494 #define TAMP_BKP0R_Pos                      (0U)
37495 #define TAMP_BKP0R_Msk                      (0xFFFFFFFFUL << TAMP_BKP0R_Pos)        /*!< 0xFFFFFFFF */
37496 #define TAMP_BKP0R                          TAMP_BKP0R_Msk
37497 
37498 /********************  Bits definition for TAMP_BKP1R register  ****************/
37499 #define TAMP_BKP1R_Pos                      (0U)
37500 #define TAMP_BKP1R_Msk                      (0xFFFFFFFFUL << TAMP_BKP1R_Pos)        /*!< 0xFFFFFFFF */
37501 #define TAMP_BKP1R                          TAMP_BKP1R_Msk
37502 
37503 /********************  Bits definition for TAMP_BKP2R register  ****************/
37504 #define TAMP_BKP2R_Pos                      (0U)
37505 #define TAMP_BKP2R_Msk                      (0xFFFFFFFFUL << TAMP_BKP2R_Pos)        /*!< 0xFFFFFFFF */
37506 #define TAMP_BKP2R                          TAMP_BKP2R_Msk
37507 
37508 /********************  Bits definition for TAMP_BKP3R register  ****************/
37509 #define TAMP_BKP3R_Pos                      (0U)
37510 #define TAMP_BKP3R_Msk                      (0xFFFFFFFFUL << TAMP_BKP3R_Pos)        /*!< 0xFFFFFFFF */
37511 #define TAMP_BKP3R                          TAMP_BKP3R_Msk
37512 
37513 /********************  Bits definition for TAMP_BKP4R register  ****************/
37514 #define TAMP_BKP4R_Pos                      (0U)
37515 #define TAMP_BKP4R_Msk                      (0xFFFFFFFFUL << TAMP_BKP4R_Pos)        /*!< 0xFFFFFFFF */
37516 #define TAMP_BKP4R                          TAMP_BKP4R_Msk
37517 
37518 /********************  Bits definition for TAMP_BKP5R register  ****************/
37519 #define TAMP_BKP5R_Pos                      (0U)
37520 #define TAMP_BKP5R_Msk                      (0xFFFFFFFFUL << TAMP_BKP5R_Pos)        /*!< 0xFFFFFFFF */
37521 #define TAMP_BKP5R                          TAMP_BKP5R_Msk
37522 
37523 /********************  Bits definition for TAMP_BKP6R register  ****************/
37524 #define TAMP_BKP6R_Pos                      (0U)
37525 #define TAMP_BKP6R_Msk                      (0xFFFFFFFFUL << TAMP_BKP6R_Pos)        /*!< 0xFFFFFFFF */
37526 #define TAMP_BKP6R                          TAMP_BKP6R_Msk
37527 
37528 /********************  Bits definition for TAMP_BKP7R register  ****************/
37529 #define TAMP_BKP7R_Pos                      (0U)
37530 #define TAMP_BKP7R_Msk                      (0xFFFFFFFFUL << TAMP_BKP7R_Pos)        /*!< 0xFFFFFFFF */
37531 #define TAMP_BKP7R                          TAMP_BKP7R_Msk
37532 
37533 /********************  Bits definition for TAMP_BKP8R register  ****************/
37534 #define TAMP_BKP8R_Pos                      (0U)
37535 #define TAMP_BKP8R_Msk                      (0xFFFFFFFFUL << TAMP_BKP8R_Pos)        /*!< 0xFFFFFFFF */
37536 #define TAMP_BKP8R                          TAMP_BKP8R_Msk
37537 
37538 /********************  Bits definition for TAMP_BKP9R register  ****************/
37539 #define TAMP_BKP9R_Pos                      (0U)
37540 #define TAMP_BKP9R_Msk                      (0xFFFFFFFFUL << TAMP_BKP9R_Pos)        /*!< 0xFFFFFFFF */
37541 #define TAMP_BKP9R                          TAMP_BKP9R_Msk
37542 
37543 /********************  Bits definition for TAMP_BKP10R register  ***************/
37544 #define TAMP_BKP10R_Pos                     (0U)
37545 #define TAMP_BKP10R_Msk                     (0xFFFFFFFFUL << TAMP_BKP10R_Pos)       /*!< 0xFFFFFFFF */
37546 #define TAMP_BKP10R                         TAMP_BKP10R_Msk
37547 
37548 /********************  Bits definition for TAMP_BKP11R register  ***************/
37549 #define TAMP_BKP11R_Pos                     (0U)
37550 #define TAMP_BKP11R_Msk                     (0xFFFFFFFFUL << TAMP_BKP11R_Pos)       /*!< 0xFFFFFFFF */
37551 #define TAMP_BKP11R                         TAMP_BKP11R_Msk
37552 
37553 /********************  Bits definition for TAMP_BKP12R register  ***************/
37554 #define TAMP_BKP12R_Pos                     (0U)
37555 #define TAMP_BKP12R_Msk                     (0xFFFFFFFFUL << TAMP_BKP12R_Pos)       /*!< 0xFFFFFFFF */
37556 #define TAMP_BKP12R                         TAMP_BKP12R_Msk
37557 
37558 /********************  Bits definition for TAMP_BKP13R register  ***************/
37559 #define TAMP_BKP13R_Pos                     (0U)
37560 #define TAMP_BKP13R_Msk                     (0xFFFFFFFFUL << TAMP_BKP13R_Pos)       /*!< 0xFFFFFFFF */
37561 #define TAMP_BKP13R                         TAMP_BKP13R_Msk
37562 
37563 /********************  Bits definition for TAMP_BKP14R register  ***************/
37564 #define TAMP_BKP14R_Pos                     (0U)
37565 #define TAMP_BKP14R_Msk                     (0xFFFFFFFFUL << TAMP_BKP14R_Pos)       /*!< 0xFFFFFFFF */
37566 #define TAMP_BKP14R                         TAMP_BKP14R_Msk
37567 
37568 /********************  Bits definition for TAMP_BKP15R register  ***************/
37569 #define TAMP_BKP15R_Pos                     (0U)
37570 #define TAMP_BKP15R_Msk                     (0xFFFFFFFFUL << TAMP_BKP15R_Pos)       /*!< 0xFFFFFFFF */
37571 #define TAMP_BKP15R                         TAMP_BKP15R_Msk
37572 
37573 /********************  Bits definition for TAMP_BKP16R register  ***************/
37574 #define TAMP_BKP16R_Pos                     (0U)
37575 #define TAMP_BKP16R_Msk                     (0xFFFFFFFFUL << TAMP_BKP16R_Pos)       /*!< 0xFFFFFFFF */
37576 #define TAMP_BKP16R                         TAMP_BKP16R_Msk
37577 
37578 /********************  Bits definition for TAMP_BKP17R register  ***************/
37579 #define TAMP_BKP17R_Pos                     (0U)
37580 #define TAMP_BKP17R_Msk                     (0xFFFFFFFFUL << TAMP_BKP17R_Pos)       /*!< 0xFFFFFFFF */
37581 #define TAMP_BKP17R                         TAMP_BKP17R_Msk
37582 
37583 /********************  Bits definition for TAMP_BKP18R register  ***************/
37584 #define TAMP_BKP18R_Pos                     (0U)
37585 #define TAMP_BKP18R_Msk                     (0xFFFFFFFFUL << TAMP_BKP18R_Pos)       /*!< 0xFFFFFFFF */
37586 #define TAMP_BKP18R                         TAMP_BKP18R_Msk
37587 
37588 /********************  Bits definition for TAMP_BKP19R register  ***************/
37589 #define TAMP_BKP19R_Pos                     (0U)
37590 #define TAMP_BKP19R_Msk                     (0xFFFFFFFFUL << TAMP_BKP19R_Pos)       /*!< 0xFFFFFFFF */
37591 #define TAMP_BKP19R                         TAMP_BKP19R_Msk
37592 
37593 /********************  Bits definition for TAMP_BKP20R register  ***************/
37594 #define TAMP_BKP20R_Pos                     (0U)
37595 #define TAMP_BKP20R_Msk                     (0xFFFFFFFFUL << TAMP_BKP20R_Pos)       /*!< 0xFFFFFFFF */
37596 #define TAMP_BKP20R                         TAMP_BKP20R_Msk
37597 
37598 /********************  Bits definition for TAMP_BKP21R register  ***************/
37599 #define TAMP_BKP21R_Pos                     (0U)
37600 #define TAMP_BKP21R_Msk                     (0xFFFFFFFFUL << TAMP_BKP21R_Pos)       /*!< 0xFFFFFFFF */
37601 #define TAMP_BKP21R                         TAMP_BKP21R_Msk
37602 
37603 /********************  Bits definition for TAMP_BKP22R register  ***************/
37604 #define TAMP_BKP22R_Pos                     (0U)
37605 #define TAMP_BKP22R_Msk                     (0xFFFFFFFFUL << TAMP_BKP22R_Pos)       /*!< 0xFFFFFFFF */
37606 #define TAMP_BKP22R                         TAMP_BKP22R_Msk
37607 
37608 /********************  Bits definition for TAMP_BKP23R register  ***************/
37609 #define TAMP_BKP23R_Pos                     (0U)
37610 #define TAMP_BKP23R_Msk                     (0xFFFFFFFFUL << TAMP_BKP23R_Pos)       /*!< 0xFFFFFFFF */
37611 #define TAMP_BKP23R                         TAMP_BKP23R_Msk
37612 
37613 /********************  Bits definition for TAMP_BKP24R register  ***************/
37614 #define TAMP_BKP24R_Pos                     (0U)
37615 #define TAMP_BKP24R_Msk                     (0xFFFFFFFFUL << TAMP_BKP24R_Pos)       /*!< 0xFFFFFFFF */
37616 #define TAMP_BKP24R                         TAMP_BKP24R_Msk
37617 
37618 /********************  Bits definition for TAMP_BKP25R register  ***************/
37619 #define TAMP_BKP25R_Pos                     (0U)
37620 #define TAMP_BKP25R_Msk                     (0xFFFFFFFFUL << TAMP_BKP25R_Pos)       /*!< 0xFFFFFFFF */
37621 #define TAMP_BKP25R                         TAMP_BKP25R_Msk
37622 
37623 /********************  Bits definition for TAMP_BKP26R register  ***************/
37624 #define TAMP_BKP26R_Pos                     (0U)
37625 #define TAMP_BKP26R_Msk                     (0xFFFFFFFFUL << TAMP_BKP26R_Pos)       /*!< 0xFFFFFFFF */
37626 #define TAMP_BKP26R                         TAMP_BKP26R_Msk
37627 
37628 /********************  Bits definition for TAMP_BKP27R register  ***************/
37629 #define TAMP_BKP27R_Pos                     (0U)
37630 #define TAMP_BKP27R_Msk                     (0xFFFFFFFFUL << TAMP_BKP27R_Pos)       /*!< 0xFFFFFFFF */
37631 #define TAMP_BKP27R                         TAMP_BKP27R_Msk
37632 
37633 /********************  Bits definition for TAMP_BKP28R register  ***************/
37634 #define TAMP_BKP28R_Pos                     (0U)
37635 #define TAMP_BKP28R_Msk                     (0xFFFFFFFFUL << TAMP_BKP28R_Pos)       /*!< 0xFFFFFFFF */
37636 #define TAMP_BKP28R                         TAMP_BKP28R_Msk
37637 
37638 /********************  Bits definition for TAMP_BKP29R register  ***************/
37639 #define TAMP_BKP29R_Pos                     (0U)
37640 #define TAMP_BKP29R_Msk                     (0xFFFFFFFFUL << TAMP_BKP29R_Pos)       /*!< 0xFFFFFFFF */
37641 #define TAMP_BKP29R                         TAMP_BKP29R_Msk
37642 
37643 /********************  Bits definition for TAMP_BKP30R register  ***************/
37644 #define TAMP_BKP30R_Pos                     (0U)
37645 #define TAMP_BKP30R_Msk                     (0xFFFFFFFFUL << TAMP_BKP30R_Pos)       /*!< 0xFFFFFFFF */
37646 #define TAMP_BKP30R                         TAMP_BKP30R_Msk
37647 
37648 /********************  Bits definition for TAMP_BKP31R register  ***************/
37649 #define TAMP_BKP31R_Pos                     (0U)
37650 #define TAMP_BKP31R_Msk                     (0xFFFFFFFFUL << TAMP_BKP31R_Pos)       /*!< 0xFFFFFFFF */
37651 #define TAMP_BKP31R                         TAMP_BKP31R_Msk
37652 
37653 
37654 /******************************************************************************/
37655 /*                                                                            */
37656 /*                                    TIM                                     */
37657 /*                                                                            */
37658 /******************************************************************************/
37659 /*******************  Bit definition for TIM_CR1 register  ********************/
37660 #define TIM_CR1_CEN_Pos           (0U)
37661 #define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */
37662 #define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
37663 #define TIM_CR1_UDIS_Pos          (1U)
37664 #define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */
37665 #define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
37666 #define TIM_CR1_URS_Pos           (2U)
37667 #define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */
37668 #define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
37669 #define TIM_CR1_OPM_Pos           (3U)
37670 #define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */
37671 #define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
37672 #define TIM_CR1_DIR_Pos           (4U)
37673 #define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */
37674 #define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
37675 #define TIM_CR1_CMS_Pos           (5U)
37676 #define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */
37677 #define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
37678 #define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000020 */
37679 #define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000040 */
37680 #define TIM_CR1_ARPE_Pos          (7U)
37681 #define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */
37682 #define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
37683 #define TIM_CR1_CKD_Pos           (8U)
37684 #define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */
37685 #define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
37686 #define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000100 */
37687 #define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000200 */
37688 #define TIM_CR1_UIFREMAP_Pos      (11U)
37689 #define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */
37690 #define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */
37691 #define TIM_CR1_DITHEN_Pos        (12U)
37692 #define TIM_CR1_DITHEN_Msk        (0x1UL << TIM_CR1_DITHEN_Pos)                /*!< 0x00001000 */
37693 #define TIM_CR1_DITHEN            TIM_CR1_DITHEN_Msk                           /*!<Dithering enable */
37694 
37695 /*******************  Bit definition for TIM_CR2 register  ********************/
37696 #define TIM_CR2_CCPC_Pos          (0U)
37697 #define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */
37698 #define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
37699 #define TIM_CR2_CCUS_Pos          (2U)
37700 #define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */
37701 #define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
37702 #define TIM_CR2_CCDS_Pos          (3U)
37703 #define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */
37704 #define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
37705 #define TIM_CR2_MMS_Pos           (4U)
37706 #define TIM_CR2_MMS_Msk           (0x200007UL << TIM_CR2_MMS_Pos)              /*!< 0x02000070 */
37707 #define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[3:0] bits (Master Mode Selection) */
37708 #define TIM_CR2_MMS_0             (     0x1UL << TIM_CR2_MMS_Pos)              /*!< 0x00000010 */
37709 #define TIM_CR2_MMS_1             (     0x2UL << TIM_CR2_MMS_Pos)              /*!< 0x00000020 */
37710 #define TIM_CR2_MMS_2             (     0x4UL << TIM_CR2_MMS_Pos)              /*!< 0x00000040 */
37711 #define TIM_CR2_MMS_3             (0x200000UL << TIM_CR2_MMS_Pos)              /*!< 0x02000000 */
37712 #define TIM_CR2_TI1S_Pos          (7U)
37713 #define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */
37714 #define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
37715 #define TIM_CR2_OIS1_Pos          (8U)
37716 #define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */
37717 #define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
37718 #define TIM_CR2_OIS1N_Pos         (9U)
37719 #define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */
37720 #define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
37721 #define TIM_CR2_OIS2_Pos          (10U)
37722 #define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */
37723 #define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
37724 #define TIM_CR2_OIS2N_Pos         (11U)
37725 #define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */
37726 #define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
37727 #define TIM_CR2_OIS3_Pos          (12U)
37728 #define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */
37729 #define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
37730 #define TIM_CR2_OIS3N_Pos         (13U)
37731 #define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */
37732 #define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
37733 #define TIM_CR2_OIS4_Pos          (14U)
37734 #define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */
37735 #define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
37736 #define TIM_CR2_OIS4N_Pos         (15U)
37737 #define TIM_CR2_OIS4N_Msk         (0x1UL << TIM_CR2_OIS4N_Pos)                 /*!< 0x00008000 */
37738 #define TIM_CR2_OIS4N             TIM_CR2_OIS4N_Msk                            /*!<Output Idle state 4 (OC4N output) */
37739 #define TIM_CR2_OIS5_Pos          (16U)
37740 #define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
37741 #define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 5 (OC5 output) */
37742 #define TIM_CR2_OIS6_Pos          (18U)
37743 #define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
37744 #define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 6 (OC6 output) */
37745 #define TIM_CR2_MMS2_Pos          (20U)
37746 #define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */
37747 #define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */
37748 #define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00100000 */
37749 #define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00200000 */
37750 #define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00400000 */
37751 #define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00800000 */
37752 #define TIM_CR2_ADSYNC_Pos        (28U)
37753 #define TIM_CR2_ADSYNC_Msk        (0x1UL << TIM_CR2_ADSYNC_Pos)                /*!< 0x10000000 */
37754 #define TIM_CR2_ADSYNC            TIM_CR2_ADSYNC_Msk                           /*!<ADC synchronization */
37755 
37756 /*******************  Bit definition for TIM_SMCR register  *******************/
37757 #define TIM_SMCR_SMS_Pos          (0U)
37758 #define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */
37759 #define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
37760 #define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000001 */
37761 #define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000002 */
37762 #define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000004 */
37763 #define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010000 */
37764 #define TIM_SMCR_TS_Pos           (4U)
37765 #define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */
37766 #define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
37767 #define TIM_SMCR_TS_0             (0x00001UL << TIM_SMCR_TS_Pos)               /*!< 0x00000010 */
37768 #define TIM_SMCR_TS_1             (0x00002UL << TIM_SMCR_TS_Pos)               /*!< 0x00000020 */
37769 #define TIM_SMCR_TS_2             (0x00004UL << TIM_SMCR_TS_Pos)               /*!< 0x00000040 */
37770 #define TIM_SMCR_TS_3             (0x10000UL << TIM_SMCR_TS_Pos)               /*!< 0x00100000 */
37771 #define TIM_SMCR_TS_4             (0x20000UL << TIM_SMCR_TS_Pos)               /*!< 0x00200000 */
37772 #define TIM_SMCR_MSM_Pos          (7U)
37773 #define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */
37774 #define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
37775 #define TIM_SMCR_ETF_Pos          (8U)
37776 #define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */
37777 #define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
37778 #define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000100 */
37779 #define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000200 */
37780 #define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000400 */
37781 #define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000800 */
37782 #define TIM_SMCR_ETPS_Pos         (12U)
37783 #define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */
37784 #define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
37785 #define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00001000 */
37786 #define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00002000 */
37787 #define TIM_SMCR_ECE_Pos          (14U)
37788 #define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */
37789 #define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
37790 #define TIM_SMCR_ETP_Pos          (15U)
37791 #define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */
37792 #define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
37793 #define TIM_SMCR_SMSPE_Pos        (24U)
37794 #define TIM_SMCR_SMSPE_Msk        (0x1UL << TIM_SMCR_SMSPE_Pos)                /*!< 0x02000000 */
37795 #define TIM_SMCR_SMSPE            TIM_SMCR_SMSPE_Msk                           /*!<SMS preload enable */
37796 #define TIM_SMCR_SMSPS_Pos        (25U)
37797 #define TIM_SMCR_SMSPS_Msk        (0x1UL << TIM_SMCR_SMSPS_Pos)                /*!< 0x04000000 */
37798 #define TIM_SMCR_SMSPS            TIM_SMCR_SMSPS_Msk                           /*!<SMS preload source */
37799 
37800 /*******************  Bit definition for TIM_DIER register  *******************/
37801 #define TIM_DIER_UIE_Pos          (0U)
37802 #define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */
37803 #define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
37804 #define TIM_DIER_CC1IE_Pos        (1U)
37805 #define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */
37806 #define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
37807 #define TIM_DIER_CC2IE_Pos        (2U)
37808 #define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */
37809 #define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
37810 #define TIM_DIER_CC3IE_Pos        (3U)
37811 #define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */
37812 #define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
37813 #define TIM_DIER_CC4IE_Pos        (4U)
37814 #define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */
37815 #define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
37816 #define TIM_DIER_COMIE_Pos        (5U)
37817 #define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */
37818 #define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
37819 #define TIM_DIER_TIE_Pos          (6U)
37820 #define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */
37821 #define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
37822 #define TIM_DIER_BIE_Pos          (7U)
37823 #define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */
37824 #define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
37825 #define TIM_DIER_UDE_Pos          (8U)
37826 #define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */
37827 #define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
37828 #define TIM_DIER_CC1DE_Pos        (9U)
37829 #define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */
37830 #define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
37831 #define TIM_DIER_CC2DE_Pos        (10U)
37832 #define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */
37833 #define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
37834 #define TIM_DIER_CC3DE_Pos        (11U)
37835 #define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */
37836 #define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
37837 #define TIM_DIER_CC4DE_Pos        (12U)
37838 #define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */
37839 #define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
37840 #define TIM_DIER_COMDE_Pos        (13U)
37841 #define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */
37842 #define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
37843 #define TIM_DIER_TDE_Pos          (14U)
37844 #define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */
37845 #define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
37846 #define TIM_DIER_IDXIE_Pos        (20U)
37847 #define TIM_DIER_IDXIE_Msk        (0x1UL << TIM_DIER_IDXIE_Pos)                /*!< 0x00100000 */
37848 #define TIM_DIER_IDXIE            TIM_DIER_IDXIE_Msk                           /*!<Encoder index interrupt enable */
37849 #define TIM_DIER_DIRIE_Pos        (21U)
37850 #define TIM_DIER_DIRIE_Msk        (0x1UL << TIM_DIER_DIRIE_Pos)                /*!< 0x00200000 */
37851 #define TIM_DIER_DIRIE            TIM_DIER_DIRIE_Msk                           /*!<Encoder direction change interrupt enable */
37852 #define TIM_DIER_IERRIE_Pos       (22U)
37853 #define TIM_DIER_IERRIE_Msk       (0x1UL << TIM_DIER_IERRIE_Pos)               /*!< 0x00400000 */
37854 #define TIM_DIER_IERRIE           TIM_DIER_IERRIE_Msk                          /*!<Encoder index error enable */
37855 #define TIM_DIER_TERRIE_Pos       (23U)
37856 #define TIM_DIER_TERRIE_Msk       (0x1UL << TIM_DIER_TERRIE_Pos)               /*!< 0x00800000 */
37857 #define TIM_DIER_TERRIE           TIM_DIER_TERRIE_Msk                          /*!<Encoder transition error enable */
37858 
37859 /********************  Bit definition for TIM_SR register  ********************/
37860 #define TIM_SR_UIF_Pos            (0U)
37861 #define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */
37862 #define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
37863 #define TIM_SR_CC1IF_Pos          (1U)
37864 #define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */
37865 #define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
37866 #define TIM_SR_CC2IF_Pos          (2U)
37867 #define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */
37868 #define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
37869 #define TIM_SR_CC3IF_Pos          (3U)
37870 #define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */
37871 #define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
37872 #define TIM_SR_CC4IF_Pos          (4U)
37873 #define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */
37874 #define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
37875 #define TIM_SR_COMIF_Pos          (5U)
37876 #define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */
37877 #define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
37878 #define TIM_SR_TIF_Pos            (6U)
37879 #define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */
37880 #define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
37881 #define TIM_SR_BIF_Pos            (7U)
37882 #define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */
37883 #define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
37884 #define TIM_SR_B2IF_Pos           (8U)
37885 #define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */
37886 #define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break 2 interrupt Flag */
37887 #define TIM_SR_CC1OF_Pos          (9U)
37888 #define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */
37889 #define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
37890 #define TIM_SR_CC2OF_Pos          (10U)
37891 #define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */
37892 #define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
37893 #define TIM_SR_CC3OF_Pos          (11U)
37894 #define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */
37895 #define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
37896 #define TIM_SR_CC4OF_Pos          (12U)
37897 #define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */
37898 #define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
37899 #define TIM_SR_SBIF_Pos           (13U)
37900 #define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */
37901 #define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!<System Break interrupt Flag */
37902 #define TIM_SR_CC5IF_Pos          (16U)
37903 #define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */
37904 #define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */
37905 #define TIM_SR_CC6IF_Pos          (17U)
37906 #define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */
37907 #define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */
37908 #define TIM_SR_IDXF_Pos           (20U)
37909 #define TIM_SR_IDXF_Msk           (0x1UL << TIM_SR_IDXF_Pos)                   /*!< 0x00100000 */
37910 #define TIM_SR_IDXF               TIM_SR_IDXF_Msk                              /*!<Encoder index interrupt flag */
37911 #define TIM_SR_DIRF_Pos           (21U)
37912 #define TIM_SR_DIRF_Msk           (0x1UL << TIM_SR_DIRF_Pos)                   /*!< 0x00200000 */
37913 #define TIM_SR_DIRF               TIM_SR_DIRF_Msk                              /*!<Encoder direction change interrupt flag */
37914 #define TIM_SR_IERRF_Pos          (22U)
37915 #define TIM_SR_IERRF_Msk          (0x1UL << TIM_SR_IERRF_Pos)                  /*!< 0x00400000 */
37916 #define TIM_SR_IERRF              TIM_SR_IERRF_Msk                             /*!<Encoder index error flag */
37917 #define TIM_SR_TERRF_Pos          (23U)
37918 #define TIM_SR_TERRF_Msk          (0x1UL << TIM_SR_TERRF_Pos)                  /*!< 0x00800000 */
37919 #define TIM_SR_TERRF              TIM_SR_TERRF_Msk                             /*!<Encoder transition error flag */
37920 
37921 /*******************  Bit definition for TIM_EGR register  ********************/
37922 #define TIM_EGR_UG_Pos            (0U)
37923 #define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */
37924 #define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
37925 #define TIM_EGR_CC1G_Pos          (1U)
37926 #define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */
37927 #define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
37928 #define TIM_EGR_CC2G_Pos          (2U)
37929 #define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */
37930 #define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
37931 #define TIM_EGR_CC3G_Pos          (3U)
37932 #define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */
37933 #define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
37934 #define TIM_EGR_CC4G_Pos          (4U)
37935 #define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */
37936 #define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
37937 #define TIM_EGR_COMG_Pos          (5U)
37938 #define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */
37939 #define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
37940 #define TIM_EGR_TG_Pos            (6U)
37941 #define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */
37942 #define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
37943 #define TIM_EGR_BG_Pos            (7U)
37944 #define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */
37945 #define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
37946 #define TIM_EGR_B2G_Pos           (8U)
37947 #define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */
37948 #define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break 2 Generation */
37949 
37950 /******************  Bit definition for TIM_CCMR1 register  *******************/
37951 #define TIM_CCMR1_CC1S_Pos        (0U)
37952 #define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */
37953 #define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
37954 #define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000001 */
37955 #define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000002 */
37956 #define TIM_CCMR1_OC1FE_Pos       (2U)
37957 #define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */
37958 #define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
37959 #define TIM_CCMR1_OC1PE_Pos       (3U)
37960 #define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */
37961 #define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
37962 #define TIM_CCMR1_OC1M_Pos        (4U)
37963 #define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */
37964 #define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
37965 #define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000010 */
37966 #define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000020 */
37967 #define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000040 */
37968 #define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010000 */
37969 #define TIM_CCMR1_OC1CE_Pos       (7U)
37970 #define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */
37971 #define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1 Clear Enable */
37972 #define TIM_CCMR1_CC2S_Pos        (8U)
37973 #define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */
37974 #define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
37975 #define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000100 */
37976 #define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000200 */
37977 #define TIM_CCMR1_OC2FE_Pos       (10U)
37978 #define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */
37979 #define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
37980 #define TIM_CCMR1_OC2PE_Pos       (11U)
37981 #define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */
37982 #define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
37983 #define TIM_CCMR1_OC2M_Pos        (12U)
37984 #define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */
37985 #define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
37986 #define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00001000 */
37987 #define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00002000 */
37988 #define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00004000 */
37989 #define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01000000 */
37990 #define TIM_CCMR1_OC2CE_Pos       (15U)
37991 #define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */
37992 #define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
37993 
37994 /*----------------------------------------------------------------------------*/
37995 #define TIM_CCMR1_IC1PSC_Pos      (2U)
37996 #define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */
37997 #define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
37998 #define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000004 */
37999 #define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000008 */
38000 #define TIM_CCMR1_IC1F_Pos        (4U)
38001 #define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */
38002 #define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
38003 #define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000010 */
38004 #define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000020 */
38005 #define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000040 */
38006 #define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000080 */
38007 #define TIM_CCMR1_IC2PSC_Pos      (10U)
38008 #define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */
38009 #define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
38010 #define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000400 */
38011 #define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000800 */
38012 #define TIM_CCMR1_IC2F_Pos        (12U)
38013 #define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */
38014 #define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
38015 #define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00001000 */
38016 #define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00002000 */
38017 #define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00004000 */
38018 #define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00008000 */
38019 
38020 /******************  Bit definition for TIM_CCMR2 register  *******************/
38021 #define TIM_CCMR2_CC3S_Pos        (0U)
38022 #define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */
38023 #define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
38024 #define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000001 */
38025 #define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000002 */
38026 #define TIM_CCMR2_OC3FE_Pos       (2U)
38027 #define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */
38028 #define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
38029 #define TIM_CCMR2_OC3PE_Pos       (3U)
38030 #define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */
38031 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
38032 #define TIM_CCMR2_OC3M_Pos        (4U)
38033 #define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010070 */
38034 #define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
38035 #define TIM_CCMR2_OC3M_0          (0x0001UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000010 */
38036 #define TIM_CCMR2_OC3M_1          (0x0002UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000020 */
38037 #define TIM_CCMR2_OC3M_2          (0x0004UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000040 */
38038 #define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010000 */
38039 #define TIM_CCMR2_OC3CE_Pos       (7U)
38040 #define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */
38041 #define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
38042 #define TIM_CCMR2_CC4S_Pos        (8U)
38043 #define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */
38044 #define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
38045 #define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000100 */
38046 #define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000200 */
38047 #define TIM_CCMR2_OC4FE_Pos       (10U)
38048 #define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */
38049 #define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
38050 #define TIM_CCMR2_OC4PE_Pos       (11U)
38051 #define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */
38052 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
38053 #define TIM_CCMR2_OC4M_Pos        (12U)
38054 #define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01007000 */
38055 #define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
38056 #define TIM_CCMR2_OC4M_0          (0x0001UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00001000 */
38057 #define TIM_CCMR2_OC4M_1          (0x0002UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00002000 */
38058 #define TIM_CCMR2_OC4M_2          (0x0004UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00004000 */
38059 #define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01000000 */
38060 #define TIM_CCMR2_OC4CE_Pos       (15U)
38061 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
38062 #define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
38063 
38064 /*----------------------------------------------------------------------------*/
38065 #define TIM_CCMR2_IC3PSC_Pos      (2U)
38066 #define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */
38067 #define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
38068 #define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000004 */
38069 #define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000008 */
38070 #define TIM_CCMR2_IC3F_Pos        (4U)
38071 #define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */
38072 #define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
38073 #define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000010 */
38074 #define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000020 */
38075 #define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000040 */
38076 #define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000080 */
38077 #define TIM_CCMR2_IC4PSC_Pos      (10U)
38078 #define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */
38079 #define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
38080 #define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000400 */
38081 #define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000800 */
38082 #define TIM_CCMR2_IC4F_Pos        (12U)
38083 #define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */
38084 #define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
38085 #define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00001000 */
38086 #define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00002000 */
38087 #define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00004000 */
38088 #define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00008000 */
38089 
38090 /*******************  Bit definition for TIM_CCER register  *******************/
38091 #define TIM_CCER_CC1E_Pos         (0U)
38092 #define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */
38093 #define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
38094 #define TIM_CCER_CC1P_Pos         (1U)
38095 #define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */
38096 #define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
38097 #define TIM_CCER_CC1NE_Pos        (2U)
38098 #define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */
38099 #define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
38100 #define TIM_CCER_CC1NP_Pos        (3U)
38101 #define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */
38102 #define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
38103 #define TIM_CCER_CC2E_Pos         (4U)
38104 #define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */
38105 #define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
38106 #define TIM_CCER_CC2P_Pos         (5U)
38107 #define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */
38108 #define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
38109 #define TIM_CCER_CC2NE_Pos        (6U)
38110 #define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */
38111 #define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
38112 #define TIM_CCER_CC2NP_Pos        (7U)
38113 #define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */
38114 #define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
38115 #define TIM_CCER_CC3E_Pos         (8U)
38116 #define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */
38117 #define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
38118 #define TIM_CCER_CC3P_Pos         (9U)
38119 #define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */
38120 #define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
38121 #define TIM_CCER_CC3NE_Pos        (10U)
38122 #define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */
38123 #define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
38124 #define TIM_CCER_CC3NP_Pos        (11U)
38125 #define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */
38126 #define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
38127 #define TIM_CCER_CC4E_Pos         (12U)
38128 #define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */
38129 #define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
38130 #define TIM_CCER_CC4P_Pos         (13U)
38131 #define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */
38132 #define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
38133 #define TIM_CCER_CC4NE_Pos        (14U)
38134 #define TIM_CCER_CC4NE_Msk        (0x1UL << TIM_CCER_CC4NE_Pos)                /*!< 0x00004000 */
38135 #define TIM_CCER_CC4NE            TIM_CCER_CC4NE_Msk                           /*!<Capture/Compare 4 Complementary output enable */
38136 #define TIM_CCER_CC4NP_Pos        (15U)
38137 #define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */
38138 #define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
38139 #define TIM_CCER_CC5E_Pos         (16U)
38140 #define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */
38141 #define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */
38142 #define TIM_CCER_CC5P_Pos         (17U)
38143 #define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */
38144 #define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */
38145 #define TIM_CCER_CC6E_Pos         (20U)
38146 #define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */
38147 #define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */
38148 #define TIM_CCER_CC6P_Pos         (21U)
38149 #define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */
38150 #define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */
38151 
38152 /*******************  Bit definition for TIM_CNT register  ********************/
38153 #define TIM_CNT_CNT_Pos           (0U)
38154 #define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */
38155 #define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
38156 #define TIM_CNT_UIFCPY_Pos        (31U)
38157 #define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */
38158 #define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy (if UIFREMAP=1) */
38159 
38160 /*******************  Bit definition for TIM_PSC register  ********************/
38161 #define TIM_PSC_PSC_Pos           (0U)
38162 #define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */
38163 #define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
38164 
38165 /*******************  Bit definition for TIM_ARR register  ********************/
38166 #define TIM_ARR_ARR_Pos           (0U)
38167 #define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */
38168 #define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<Actual auto-reload Value */
38169 
38170 /*******************  Bit definition for TIM_RCR register  ********************/
38171 #define TIM_RCR_REP_Pos           (0U)
38172 #define TIM_RCR_REP_Msk           (0xFFFFUL << TIM_RCR_REP_Pos)                /*!< 0x0000FFFF */
38173 #define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
38174 
38175 /*******************  Bit definition for TIM_CCR1 register  *******************/
38176 #define TIM_CCR1_CCR1_Pos         (0U)
38177 #define TIM_CCR1_CCR1_Msk         (0xFFFFFFFFUL << TIM_CCR1_CCR1_Pos)          /*!< 0xFFFFFFFF */
38178 #define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
38179 
38180 /*******************  Bit definition for TIM_CCR2 register  *******************/
38181 #define TIM_CCR2_CCR2_Pos         (0U)
38182 #define TIM_CCR2_CCR2_Msk         (0xFFFFFFFFUL << TIM_CCR2_CCR2_Pos)          /*!< 0xFFFFFFFF */
38183 #define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
38184 
38185 /*******************  Bit definition for TIM_CCR3 register  *******************/
38186 #define TIM_CCR3_CCR3_Pos         (0U)
38187 #define TIM_CCR3_CCR3_Msk         (0xFFFFFFFFUL << TIM_CCR3_CCR3_Pos)          /*!< 0xFFFFFFFF */
38188 #define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
38189 
38190 /*******************  Bit definition for TIM_CCR4 register  *******************/
38191 #define TIM_CCR4_CCR4_Pos         (0U)
38192 #define TIM_CCR4_CCR4_Msk         (0xFFFFFFFFUL << TIM_CCR4_CCR4_Pos)          /*!< 0xFFFFFFFF */
38193 #define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
38194 
38195 /*******************  Bit definition for TIM_BDTR register  *******************/
38196 #define TIM_BDTR_DTG_Pos          (0U)
38197 #define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */
38198 #define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
38199 #define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000001 */
38200 #define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000002 */
38201 #define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000004 */
38202 #define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000008 */
38203 #define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000010 */
38204 #define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000020 */
38205 #define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000040 */
38206 #define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000080 */
38207 #define TIM_BDTR_LOCK_Pos         (8U)
38208 #define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */
38209 #define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
38210 #define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000100 */
38211 #define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000200 */
38212 #define TIM_BDTR_OSSI_Pos         (10U)
38213 #define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */
38214 #define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
38215 #define TIM_BDTR_OSSR_Pos         (11U)
38216 #define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */
38217 #define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
38218 #define TIM_BDTR_BKE_Pos          (12U)
38219 #define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */
38220 #define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break 1 */
38221 #define TIM_BDTR_BKP_Pos          (13U)
38222 #define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */
38223 #define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break 1 */
38224 #define TIM_BDTR_AOE_Pos          (14U)
38225 #define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */
38226 #define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
38227 #define TIM_BDTR_MOE_Pos          (15U)
38228 #define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */
38229 #define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
38230 #define TIM_BDTR_BKF_Pos          (16U)
38231 #define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */
38232 #define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break 1 */
38233 #define TIM_BDTR_BK2F_Pos         (20U)
38234 #define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */
38235 #define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break 2 */
38236 #define TIM_BDTR_BK2E_Pos         (24U)
38237 #define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */
38238 #define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break 2 */
38239 #define TIM_BDTR_BK2P_Pos         (25U)
38240 #define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */
38241 #define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break 2 */
38242 #define TIM_BDTR_BKDSRM_Pos       (26U)
38243 #define TIM_BDTR_BKDSRM_Msk       (0x1UL << TIM_BDTR_BKDSRM_Pos)               /*!< 0x04000000 */
38244 #define TIM_BDTR_BKDSRM           TIM_BDTR_BKDSRM_Msk                          /*!<Break disarming/re-arming */
38245 #define TIM_BDTR_BK2DSRM_Pos      (27U)
38246 #define TIM_BDTR_BK2DSRM_Msk      (0x1UL << TIM_BDTR_BK2DSRM_Pos)              /*!< 0x08000000 */
38247 #define TIM_BDTR_BK2DSRM          TIM_BDTR_BK2DSRM_Msk                         /*!<Break2 disarming/re-arming */
38248 #define TIM_BDTR_BKBID_Pos        (28U)
38249 #define TIM_BDTR_BKBID_Msk        (0x1UL << TIM_BDTR_BKBID_Pos)                /*!< 0x10000000 */
38250 #define TIM_BDTR_BKBID            TIM_BDTR_BKBID_Msk                           /*!<Break BIDirectional */
38251 #define TIM_BDTR_BK2BID_Pos       (29U)
38252 #define TIM_BDTR_BK2BID_Msk       (0x1UL << TIM_BDTR_BK2BID_Pos)               /*!< 0x20000000 */
38253 #define TIM_BDTR_BK2BID           TIM_BDTR_BK2BID_Msk                          /*!<Break2 BIDirectional */
38254 
38255 /*******************  Bit definition for TIM_CCR5 register  *******************/
38256 #define TIM_CCR5_CCR5_Pos         (0U)
38257 #define TIM_CCR5_CCR5_Msk         (0xFFFFFUL << TIM_CCR5_CCR5_Pos)             /*!< 0x000FFFFF */
38258 #define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */
38259 #define TIM_CCR5_GC5C1_Pos        (29U)
38260 #define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */
38261 #define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */
38262 #define TIM_CCR5_GC5C2_Pos        (30U)
38263 #define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */
38264 #define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */
38265 #define TIM_CCR5_GC5C3_Pos        (31U)
38266 #define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */
38267 #define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */
38268 
38269 /*******************  Bit definition for TIM_CCR6 register  *******************/
38270 #define TIM_CCR6_CCR6_Pos         (0U)
38271 #define TIM_CCR6_CCR6_Msk         (0xFFFFFUL << TIM_CCR6_CCR6_Pos)             /*!< 0x000FFFFF */
38272 #define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */
38273 
38274 /******************  Bit definition for TIM_CCMR3 register  *******************/
38275 #define TIM_CCMR3_OC5FE_Pos       (2U)
38276 #define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */
38277 #define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */
38278 #define TIM_CCMR3_OC5PE_Pos       (3U)
38279 #define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */
38280 #define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
38281 #define TIM_CCMR3_OC5M_Pos        (4U)
38282 #define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010070 */
38283 #define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
38284 #define TIM_CCMR3_OC5M_0          (0x0001UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000010 */
38285 #define TIM_CCMR3_OC5M_1          (0x0002UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000020 */
38286 #define TIM_CCMR3_OC5M_2          (0x0004UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000040 */
38287 #define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010000 */
38288 #define TIM_CCMR3_OC5CE_Pos       (7U)
38289 #define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */
38290 #define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */
38291 #define TIM_CCMR3_OC6FE_Pos       (10U)
38292 #define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */
38293 #define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 6 Fast enable */
38294 #define TIM_CCMR3_OC6PE_Pos       (11U)
38295 #define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */
38296 #define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 6 Preload enable */
38297 #define TIM_CCMR3_OC6M_Pos        (12U)
38298 #define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01007000 */
38299 #define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
38300 #define TIM_CCMR3_OC6M_0          (0x0001UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00001000 */
38301 #define TIM_CCMR3_OC6M_1          (0x0002UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00002000 */
38302 #define TIM_CCMR3_OC6M_2          (0x0004UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00004000 */
38303 #define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01000000 */
38304 #define TIM_CCMR3_OC6CE_Pos       (15U)
38305 #define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
38306 #define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 6 Clear Enable */
38307 
38308 /*******************  Bit definition for TIM_DTR2 register  *********************/
38309 #define TIM_DTR2_DTGF_Pos         (0U)
38310 #define TIM_DTR2_DTGF_Msk         (0xFFUL << TIM_DTR2_DTGF_Pos)                /*!< 0x0000000F */
38311 #define TIM_DTR2_DTGF             TIM_DTR2_DTGF_Msk                            /*!<DTGF[7:0] bits (Deadtime falling edge generator setup)*/
38312 #define TIM_DTR2_DTGF_0           (0x01UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000001 */
38313 #define TIM_DTR2_DTGF_1           (0x02UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000002 */
38314 #define TIM_DTR2_DTGF_2           (0x04UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000004 */
38315 #define TIM_DTR2_DTGF_3           (0x08UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000008 */
38316 #define TIM_DTR2_DTGF_4           (0x10UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000010 */
38317 #define TIM_DTR2_DTGF_5           (0x20UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000020 */
38318 #define TIM_DTR2_DTGF_6           (0x40UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000040 */
38319 #define TIM_DTR2_DTGF_7           (0x80UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000080 */
38320 #define TIM_DTR2_DTAE_Pos         (16U)
38321 #define TIM_DTR2_DTAE_Msk         (0x1UL << TIM_DTR2_DTAE_Pos)                 /*!< 0x00004000 */
38322 #define TIM_DTR2_DTAE             TIM_DTR2_DTAE_Msk                            /*!<Deadtime asymmetric enable */
38323 #define TIM_DTR2_DTPE_Pos         (17U)
38324 #define TIM_DTR2_DTPE_Msk         (0x1UL << TIM_DTR2_DTPE_Pos)                 /*!< 0x00008000 */
38325 #define TIM_DTR2_DTPE             TIM_DTR2_DTPE_Msk                            /*!<Deadtime preload enable */
38326 
38327 /*******************  Bit definition for TIM_ECR register  *********************/
38328 #define TIM_ECR_IE_Pos            (0U)
38329 #define TIM_ECR_IE_Msk            (0x1UL << TIM_ECR_IE_Pos)                    /*!< 0x00000001 */
38330 #define TIM_ECR_IE                TIM_ECR_IE_Msk                               /*!<Index enable */
38331 #define TIM_ECR_IDIR_Pos          (1U)
38332 #define TIM_ECR_IDIR_Msk          (0x3UL << TIM_ECR_IDIR_Pos)                  /*!< 0x00000006 */
38333 #define TIM_ECR_IDIR              TIM_ECR_IDIR_Msk                             /*!<IDIR[1:0] bits (Index direction)*/
38334 #define TIM_ECR_IDIR_0            (0x01UL << TIM_ECR_IDIR_Pos)                 /*!< 0x00000001 */
38335 #define TIM_ECR_IDIR_1            (0x02UL << TIM_ECR_IDIR_Pos)                 /*!< 0x00000002 */
38336 #define TIM_ECR_IBLK_Pos          (3U)
38337 #define TIM_ECR_IBLK_Msk          (0x3UL << TIM_ECR_IBLK_Pos)                  /*!< 0x00000018 */
38338 #define TIM_ECR_IBLK              TIM_ECR_IBLK_Msk                             /*!<IBLK[1:0] bits (Index blanking)*/
38339 #define TIM_ECR_IBLK_0            (0x01UL << TIM_ECR_IBLK_Pos)                 /*!< 0x00000008 */
38340 #define TIM_ECR_IBLK_1            (0x02UL << TIM_ECR_IBLK_Pos)                 /*!< 0x00000010 */
38341 #define TIM_ECR_FIDX_Pos          (5U)
38342 #define TIM_ECR_FIDX_Msk          (0x1UL << TIM_ECR_FIDX_Pos)                  /*!< 0x00000020 */
38343 #define TIM_ECR_FIDX              TIM_ECR_FIDX_Msk                             /*!<First index enable */
38344 #define TIM_ECR_IPOS_Pos          (6U)
38345 #define TIM_ECR_IPOS_Msk          (0x3UL << TIM_ECR_IPOS_Pos)                  /*!< 0x000000C0 */
38346 #define TIM_ECR_IPOS              TIM_ECR_IPOS_Msk                             /*!<IPOS[1:0] bits (Index positioning)*/
38347 #define TIM_ECR_IPOS_0            (0x01UL << TIM_ECR_IPOS_Pos)                 /*!< 0x00000040 */
38348 #define TIM_ECR_IPOS_1            (0x02UL << TIM_ECR_IPOS_Pos)                 /*!< 0x00000080 */
38349 #define TIM_ECR_PW_Pos            (16U)
38350 #define TIM_ECR_PW_Msk            (0xFFUL << TIM_ECR_PW_Pos)                   /*!< 0x00FF0000 */
38351 #define TIM_ECR_PW                TIM_ECR_PW_Msk                               /*!<PW[7:0] bits (Pulse width)*/
38352 #define TIM_ECR_PW_0              (0x01UL << TIM_ECR_PW_Pos)                   /*!< 0x00010000 */
38353 #define TIM_ECR_PW_1              (0x02UL << TIM_ECR_PW_Pos)                   /*!< 0x00020000 */
38354 #define TIM_ECR_PW_2              (0x04UL << TIM_ECR_PW_Pos)                   /*!< 0x00040000 */
38355 #define TIM_ECR_PW_3              (0x08UL << TIM_ECR_PW_Pos)                   /*!< 0x00080000 */
38356 #define TIM_ECR_PW_4              (0x10UL << TIM_ECR_PW_Pos)                   /*!< 0x00100000 */
38357 #define TIM_ECR_PW_5              (0x20UL << TIM_ECR_PW_Pos)                   /*!< 0x00200000 */
38358 #define TIM_ECR_PW_6              (0x40UL << TIM_ECR_PW_Pos)                   /*!< 0x00400000 */
38359 #define TIM_ECR_PW_7              (0x80UL << TIM_ECR_PW_Pos)                   /*!< 0x00800000 */
38360 #define TIM_ECR_PWPRSC_Pos        (24U)
38361 #define TIM_ECR_PWPRSC_Msk        (0x7UL << TIM_ECR_PWPRSC_Pos)                /*!< 0x07000000 */
38362 #define TIM_ECR_PWPRSC            TIM_ECR_PWPRSC_Msk                           /*!<PWPRSC[2:0] bits (Pulse width prescaler)*/
38363 #define TIM_ECR_PWPRSC_0          (0x01UL << TIM_ECR_PWPRSC_Pos)               /*!< 0x01000000 */
38364 #define TIM_ECR_PWPRSC_1          (0x02UL << TIM_ECR_PWPRSC_Pos)               /*!< 0x02000000 */
38365 #define TIM_ECR_PWPRSC_2          (0x04UL << TIM_ECR_PWPRSC_Pos)               /*!< 0x04000000 */
38366 
38367 /*******************  Bit definition for TIM_TISEL register  *********************/
38368 #define TIM_TISEL_TI1SEL_Pos      (0U)
38369 #define TIM_TISEL_TI1SEL_Msk      (0xFUL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x0000000F */
38370 #define TIM_TISEL_TI1SEL          TIM_TISEL_TI1SEL_Msk                         /*!<TI1SEL[3:0] bits */
38371 #define TIM_TISEL_TI1SEL_0        (0x1UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000001 */
38372 #define TIM_TISEL_TI1SEL_1        (0x2UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000002 */
38373 #define TIM_TISEL_TI1SEL_2        (0x4UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000004 */
38374 #define TIM_TISEL_TI1SEL_3        (0x8UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000008 */
38375 #define TIM_TISEL_TI2SEL_Pos      (8U)
38376 #define TIM_TISEL_TI2SEL_Msk      (0xFUL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000F00 */
38377 #define TIM_TISEL_TI2SEL          TIM_TISEL_TI2SEL_Msk                         /*!<TI2SEL[3:0] bits */
38378 #define TIM_TISEL_TI2SEL_0        (0x1UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000100 */
38379 #define TIM_TISEL_TI2SEL_1        (0x2UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000200 */
38380 #define TIM_TISEL_TI2SEL_2        (0x4UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000400 */
38381 #define TIM_TISEL_TI2SEL_3        (0x8UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000800 */
38382 #define TIM_TISEL_TI3SEL_Pos      (16U)
38383 #define TIM_TISEL_TI3SEL_Msk      (0xFUL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x000F0000 */
38384 #define TIM_TISEL_TI3SEL          TIM_TISEL_TI3SEL_Msk                         /*!<TI3SEL[3:0] bits */
38385 #define TIM_TISEL_TI3SEL_0        (0x1UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00010000 */
38386 #define TIM_TISEL_TI3SEL_1        (0x2UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00020000 */
38387 #define TIM_TISEL_TI3SEL_2        (0x4UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00040000 */
38388 #define TIM_TISEL_TI3SEL_3        (0x8UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00080000 */
38389 #define TIM_TISEL_TI4SEL_Pos      (24U)
38390 #define TIM_TISEL_TI4SEL_Msk      (0xFUL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x0F000000 */
38391 #define TIM_TISEL_TI4SEL          TIM_TISEL_TI4SEL_Msk                         /*!<TI4SEL[3:0] bits */
38392 #define TIM_TISEL_TI4SEL_0        (0x1UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x01000000 */
38393 #define TIM_TISEL_TI4SEL_1        (0x2UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x02000000 */
38394 #define TIM_TISEL_TI4SEL_2        (0x4UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x04000000 */
38395 #define TIM_TISEL_TI4SEL_3        (0x8UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x08000000 */
38396 
38397 /*******************  Bit definition for TIM_AF1 register  ********************/
38398 #define TIM_AF1_BKINE_Pos        (0U)
38399 #define TIM_AF1_BKINE_Msk        (0x1UL << TIM_AF1_BKINE_Pos)                  /*!< 0x00000001 */
38400 #define TIM_AF1_BKINE            TIM_AF1_BKINE_Msk                             /*!<BRK BKIN input enable */
38401 #define TIM_AF1_BKCMP1E_Pos      (1U)
38402 #define TIM_AF1_BKCMP1E_Msk      (0x1UL << TIM_AF1_BKCMP1E_Pos)                /*!< 0x00000002 */
38403 #define TIM_AF1_BKCMP1E          TIM_AF1_BKCMP1E_Msk                           /*!<BRK CMP1 enable */
38404 #define TIM_AF1_BKCMP2E_Pos      (2U)
38405 #define TIM_AF1_BKCMP2E_Msk      (0x1UL << TIM_AF1_BKCMP2E_Pos)                /*!< 0x00000004 */
38406 #define TIM_AF1_BKCMP2E          TIM_AF1_BKCMP2E_Msk                           /*!<BRK CMP2 enable */
38407 #define TIM_AF1_BKCMP3E_Pos      (3U)
38408 #define TIM_AF1_BKCMP3E_Msk      (0x1UL << TIM_AF1_BKCMP3E_Pos)                /*!< 0x00000008 */
38409 #define TIM_AF1_BKCMP3E          TIM_AF1_BKCMP3E_Msk                           /*!<BRK CMP3 enable */
38410 #define TIM_AF1_BKCMP4E_Pos      (4U)
38411 #define TIM_AF1_BKCMP4E_Msk      (0x1UL << TIM_AF1_BKCMP4E_Pos)                /*!< 0x00000010 */
38412 #define TIM_AF1_BKCMP4E          TIM_AF1_BKCMP4E_Msk                           /*!<BRK CMP4 enable */
38413 #define TIM_AF1_BKCMP5E_Pos      (5U)
38414 #define TIM_AF1_BKCMP5E_Msk      (0x1UL << TIM_AF1_BKCMP5E_Pos)                /*!< 0x00000020 */
38415 #define TIM_AF1_BKCMP5E          TIM_AF1_BKCMP5E_Msk                           /*!<BRK CMP5 enable */
38416 #define TIM_AF1_BKCMP6E_Pos      (6U)
38417 #define TIM_AF1_BKCMP6E_Msk      (0x1UL << TIM_AF1_BKCMP6E_Pos)                /*!< 0x00000040 */
38418 #define TIM_AF1_BKCMP6E          TIM_AF1_BKCMP6E_Msk                           /*!<BRK CMP6 enable */
38419 #define TIM_AF1_BKCMP7E_Pos      (7U)
38420 #define TIM_AF1_BKCMP7E_Msk      (0x1UL << TIM_AF1_BKCMP7E_Pos)                /*!< 0x00000080 */
38421 #define TIM_AF1_BKCMP7E          TIM_AF1_BKCMP7E_Msk                           /*!<BRK CMP7 enable */
38422 #define TIM_AF1_BKCMP8E_Pos      (8U)
38423 #define TIM_AF1_BKCMP8E_Msk      (0x1UL << TIM_AF1_BKCMP8E_Pos)                /*!< 0x00000100 */
38424 #define TIM_AF1_BKCMP8E          TIM_AF1_BKCMP8E_Msk                           /*!<BRK CMP8 enable */
38425 #define TIM_AF1_BKINP_Pos        (9U)
38426 #define TIM_AF1_BKINP_Msk        (0x1UL << TIM_AF1_BKINP_Pos)                  /*!< 0x00000200 */
38427 #define TIM_AF1_BKINP            TIM_AF1_BKINP_Msk                             /*!<BRK BKIN input polarity */
38428 #define TIM_AF1_BKCMP1P_Pos      (10U)
38429 #define TIM_AF1_BKCMP1P_Msk      (0x1UL << TIM_AF1_BKCMP1P_Pos)                /*!< 0x00000400 */
38430 #define TIM_AF1_BKCMP1P          TIM_AF1_BKCMP1P_Msk                           /*!<BRK CMP1 input polarity */
38431 #define TIM_AF1_BKCMP2P_Pos      (11U)
38432 #define TIM_AF1_BKCMP2P_Msk      (0x1UL << TIM_AF1_BKCMP2P_Pos)                /*!< 0x00000800 */
38433 #define TIM_AF1_BKCMP2P          TIM_AF1_BKCMP2P_Msk                           /*!<BRK CMP1 input polarity */
38434 #define TIM_AF1_BKCMP3P_Pos      (12U)
38435 #define TIM_AF1_BKCMP3P_Msk      (0x1UL << TIM_AF1_BKCMP3P_Pos)                /*!< 0x00001000 */
38436 #define TIM_AF1_BKCMP3P          TIM_AF1_BKCMP3P_Msk                           /*!<BRK CMP1 input polarity */
38437 #define TIM_AF1_BKCMP4P_Pos      (13U)
38438 #define TIM_AF1_BKCMP4P_Msk      (0x1UL << TIM_AF1_BKCMP4P_Pos)                /*!< 0x00002000 */
38439 #define TIM_AF1_BKCMP4P          TIM_AF1_BKCMP4P_Msk                           /*!<BRK CMP1 input polarity */
38440 #define TIM_AF1_ETRSEL_Pos       (14U)
38441 #define TIM_AF1_ETRSEL_Msk       (0xFUL << TIM_AF1_ETRSEL_Pos)                 /*!< 0x0003C000 */
38442 #define TIM_AF1_ETRSEL           TIM_AF1_ETRSEL_Msk                            /*!<ETRSEL[3:0] bits (TIM1 ETR source selection) */
38443 #define TIM_AF1_ETRSEL_0         (0x1UL << TIM_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */
38444 #define TIM_AF1_ETRSEL_1         (0x2UL << TIM_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */
38445 #define TIM_AF1_ETRSEL_2         (0x4UL << TIM_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */
38446 #define TIM_AF1_ETRSEL_3         (0x8UL << TIM_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */
38447 
38448 /*******************  Bit definition for TIM_AF2 register  ********************/
38449 #define TIM_AF2_BK2INE_Pos       (0U)
38450 #define TIM_AF2_BK2INE_Msk       (0x1UL << TIM_AF2_BK2INE_Pos)                 /*!< 0x00000001 */
38451 #define TIM_AF2_BK2INE           TIM_AF2_BK2INE_Msk                            /*!<BRK2 BKIN input enable */
38452 #define TIM_AF2_BK2CMP8E_Pos     (8U)
38453 #define TIM_AF2_BK2CMP8E_Msk     (0x1UL << TIM_AF2_BK2CMP8E_Pos)               /*!< 0x00000100 */
38454 #define TIM_AF2_BK2CMP8E         TIM_AF2_BK2CMP8E_Msk                          /*!<BRK2 CMP8 enable */
38455 #define TIM_AF2_BK2INP_Pos       (9U)
38456 #define TIM_AF2_BK2INP_Msk       (0x1UL << TIM_AF2_BK2INP_Pos)                 /*!< 0x00000200 */
38457 #define TIM_AF2_BK2INP           TIM_AF2_BK2INP_Msk                            /*!<BRK2 BKIN input polarity */
38458 
38459 /*******************  Bit definition for TIM_DCR register  ********************/
38460 #define TIM_DCR_DBA_Pos           (0U)
38461 #define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */
38462 #define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
38463 #define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000001 */
38464 #define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000002 */
38465 #define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000004 */
38466 #define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000008 */
38467 #define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000010 */
38468 #define TIM_DCR_DBL_Pos           (8U)
38469 #define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */
38470 #define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
38471 #define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000100 */
38472 #define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000200 */
38473 #define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000400 */
38474 #define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000800 */
38475 #define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                  /*!< 0x00001000 */
38476 #define TIM_DCR_DBSS_Pos          (16U)
38477 #define TIM_DCR_DBSS_Msk          (0xFUL << TIM_DCR_DBSS_Pos)                  /*!< 0x000F0000 */
38478 #define TIM_DCR_DBSS              TIM_DCR_DBSS_Msk                             /*!<DBSS[19:16] bits (DMA Burst Source Selection) */
38479 #define TIM_DCR_DBSS_0            (0x01UL << TIM_DCR_DBSS_Pos)                 /*!< 0x00010000 */
38480 #define TIM_DCR_DBSS_1            (0x02UL << TIM_DCR_DBSS_Pos)                 /*!< 0x00020000 */
38481 #define TIM_DCR_DBSS_2            (0x04UL << TIM_DCR_DBSS_Pos)                 /*!< 0x00040000 */
38482 #define TIM_DCR_DBSS_3            (0x08UL << TIM_DCR_DBSS_Pos)                 /*!< 0x00080000 */
38483 
38484 /*******************  Bit definition for TIM_DMAR register  *******************/
38485 #define TIM_DMAR_DMAB_Pos         (0U)
38486 #define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)              /*!< 0x0000FFFF */
38487 #define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
38488 
38489 
38490 /*********************************************************************************/
38491 /*                                                                               */
38492 /*                                    UCPD                                       */
38493 /*                                                                               */
38494 /*********************************************************************************/
38495 /********************  Bits definition for UCPD_CFG1 register  *******************/
38496 #define UCPD_CFG1_HBITCLKDIV_Pos            (0U)
38497 #define UCPD_CFG1_HBITCLKDIV_Msk            (0x3FUL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x0000003F */
38498 #define UCPD_CFG1_HBITCLKDIV                UCPD_CFG1_HBITCLKDIV_Msk             /*!< Number of cycles (minus 1) for a half bit clock */
38499 #define UCPD_CFG1_HBITCLKDIV_0              (0x01UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000001 */
38500 #define UCPD_CFG1_HBITCLKDIV_1              (0x02UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000002 */
38501 #define UCPD_CFG1_HBITCLKDIV_2              (0x04UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000004 */
38502 #define UCPD_CFG1_HBITCLKDIV_3              (0x08UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000008 */
38503 #define UCPD_CFG1_HBITCLKDIV_4              (0x10UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000010 */
38504 #define UCPD_CFG1_HBITCLKDIV_5              (0x20UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000020 */
38505 #define UCPD_CFG1_IFRGAP_Pos                (6U)
38506 #define UCPD_CFG1_IFRGAP_Msk                (0x1FUL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x000007C0 */
38507 #define UCPD_CFG1_IFRGAP                    UCPD_CFG1_IFRGAP_Msk                 /*!< Clock divider value to generates Interframe gap */
38508 #define UCPD_CFG1_IFRGAP_0                  (0x01UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000040 */
38509 #define UCPD_CFG1_IFRGAP_1                  (0x02UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000080 */
38510 #define UCPD_CFG1_IFRGAP_2                  (0x04UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000100 */
38511 #define UCPD_CFG1_IFRGAP_3                  (0x08UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000200 */
38512 #define UCPD_CFG1_IFRGAP_4                  (0x10UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000400 */
38513 #define UCPD_CFG1_TRANSWIN_Pos              (11U)
38514 #define UCPD_CFG1_TRANSWIN_Msk              (0x1FUL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x0000F800 */
38515 #define UCPD_CFG1_TRANSWIN                  UCPD_CFG1_TRANSWIN_Msk               /*!< Number of cycles (minus 1) of the half bit clock */
38516 #define UCPD_CFG1_TRANSWIN_0                (0x01UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00000800 */
38517 #define UCPD_CFG1_TRANSWIN_1                (0x02UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00001000 */
38518 #define UCPD_CFG1_TRANSWIN_2                (0x04UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00002000 */
38519 #define UCPD_CFG1_TRANSWIN_3                (0x08UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00004000 */
38520 #define UCPD_CFG1_TRANSWIN_4                (0x10UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00008000 */
38521 #define UCPD_CFG1_PSC_UCPDCLK_Pos           (17U)
38522 #define UCPD_CFG1_PSC_UCPDCLK_Msk           (0x7UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x000E0000 */
38523 #define UCPD_CFG1_PSC_UCPDCLK               UCPD_CFG1_PSC_UCPDCLK_Msk            /*!< Prescaler for UCPDCLK */
38524 #define UCPD_CFG1_PSC_UCPDCLK_0             (0x1UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00020000 */
38525 #define UCPD_CFG1_PSC_UCPDCLK_1             (0x2UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00040000 */
38526 #define UCPD_CFG1_PSC_UCPDCLK_2             (0x4UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00080000 */
38527 #define UCPD_CFG1_RXORDSETEN_Pos            (20U)
38528 #define UCPD_CFG1_RXORDSETEN_Msk            (0x1FFUL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x1FF00000 */
38529 #define UCPD_CFG1_RXORDSETEN                UCPD_CFG1_RXORDSETEN_Msk             /*!< Receiver ordered set detection enable */
38530 #define UCPD_CFG1_RXORDSETEN_0              (0x001UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00100000 */
38531 #define UCPD_CFG1_RXORDSETEN_1              (0x002UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00200000 */
38532 #define UCPD_CFG1_RXORDSETEN_2              (0x004UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00400000 */
38533 #define UCPD_CFG1_RXORDSETEN_3              (0x008UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00800000 */
38534 #define UCPD_CFG1_RXORDSETEN_4              (0x010UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x01000000 */
38535 #define UCPD_CFG1_RXORDSETEN_5              (0x020UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x02000000 */
38536 #define UCPD_CFG1_RXORDSETEN_6              (0x040UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x04000000 */
38537 #define UCPD_CFG1_RXORDSETEN_7              (0x080UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x08000000 */
38538 #define UCPD_CFG1_RXORDSETEN_8              (0x100UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x10000000 */
38539 #define UCPD_CFG1_TXDMAEN_Pos               (29U)
38540 #define UCPD_CFG1_TXDMAEN_Msk               (0x1UL << UCPD_CFG1_TXDMAEN_Pos)     /*!< 0x20000000 */
38541 #define UCPD_CFG1_TXDMAEN                   UCPD_CFG1_TXDMAEN_Msk                /*!< DMA transmission requests enable   */
38542 #define UCPD_CFG1_RXDMAEN_Pos               (30U)
38543 #define UCPD_CFG1_RXDMAEN_Msk               (0x1UL << UCPD_CFG1_RXDMAEN_Pos)     /*!< 0x40000000 */
38544 #define UCPD_CFG1_RXDMAEN                   UCPD_CFG1_RXDMAEN_Msk                /*!< DMA reception requests enable   */
38545 #define UCPD_CFG1_UCPDEN_Pos                (31U)
38546 #define UCPD_CFG1_UCPDEN_Msk                (0x1UL << UCPD_CFG1_UCPDEN_Pos)      /*!< 0x80000000 */
38547 #define UCPD_CFG1_UCPDEN                    UCPD_CFG1_UCPDEN_Msk                 /*!< USB Power Delivery Block Enable */
38548 
38549 /********************  Bits definition for UCPD_CFG2 register  *******************/
38550 #define UCPD_CFG2_RXFILTDIS_Pos             (0U)
38551 #define UCPD_CFG2_RXFILTDIS_Msk             (0x1UL << UCPD_CFG2_RXFILTDIS_Pos)   /*!< 0x00000001 */
38552 #define UCPD_CFG2_RXFILTDIS                 UCPD_CFG2_RXFILTDIS_Msk              /*!< Enables an Rx pre-filter for the BMC decoder */
38553 #define UCPD_CFG2_RXFILT2N3_Pos             (1U)
38554 #define UCPD_CFG2_RXFILT2N3_Msk             (0x1UL << UCPD_CFG2_RXFILT2N3_Pos)   /*!< 0x00000002 */
38555 #define UCPD_CFG2_RXFILT2N3                 UCPD_CFG2_RXFILT2N3_Msk              /*!< Controls the sampling method for an Rx pre-filter for the BMC decode */
38556 #define UCPD_CFG2_FORCECLK_Pos              (2U)
38557 #define UCPD_CFG2_FORCECLK_Msk              (0x1UL << UCPD_CFG2_FORCECLK_Pos)    /*!< 0x00000004 */
38558 #define UCPD_CFG2_FORCECLK                  UCPD_CFG2_FORCECLK_Msk               /*!< Controls forcing of the clock request UCPDCLK_REQ */
38559 #define UCPD_CFG2_WUPEN_Pos                 (3U)
38560 #define UCPD_CFG2_WUPEN_Msk                 (0x1UL << UCPD_CFG2_WUPEN_Pos)       /*!< 0x00000008 */
38561 #define UCPD_CFG2_WUPEN                     UCPD_CFG2_WUPEN_Msk                  /*!< Wakeup from STOP enable */
38562 #define UCPD_CFG2_RXAFILTEN_Pos             (8U)
38563 #define UCPD_CFG2_RXAFILTEN_Msk             (0x1UL << UCPD_CFG2_RXAFILTEN_Pos)   /*!< 0x00000100 */
38564 #define UCPD_CFG2_RXAFILTEN                 UCPD_CFG2_RXAFILTEN_Msk              /*!< Rx analog filter enable */
38565 
38566 /********************  Bits definition for UCPD_CR register  *********************/
38567 #define UCPD_CR_TXMODE_Pos                  (0U)
38568 #define UCPD_CR_TXMODE_Msk                  (0x3UL << UCPD_CR_TXMODE_Pos)        /*!< 0x00000003 */
38569 #define UCPD_CR_TXMODE                      UCPD_CR_TXMODE_Msk                   /*!< Type of Tx packet  */
38570 #define UCPD_CR_TXMODE_0                    (0x1UL << UCPD_CR_TXMODE_Pos)        /*!< 0x00000001 */
38571 #define UCPD_CR_TXMODE_1                    (0x2UL << UCPD_CR_TXMODE_Pos)        /*!< 0x00000002 */
38572 #define UCPD_CR_TXSEND_Pos                  (2U)
38573 #define UCPD_CR_TXSEND_Msk                  (0x1UL << UCPD_CR_TXSEND_Pos)        /*!< 0x00000004 */
38574 #define UCPD_CR_TXSEND                      UCPD_CR_TXSEND_Msk                   /*!< Type of Tx packet  */
38575 #define UCPD_CR_TXHRST_Pos                  (3U)
38576 #define UCPD_CR_TXHRST_Msk                  (0x1UL << UCPD_CR_TXHRST_Pos)        /*!< 0x00000008 */
38577 #define UCPD_CR_TXHRST                      UCPD_CR_TXHRST_Msk                   /*!< Command to send a Tx Hard Reset  */
38578 #define UCPD_CR_RXMODE_Pos                  (4U)
38579 #define UCPD_CR_RXMODE_Msk                  (0x1UL << UCPD_CR_RXMODE_Pos)        /*!< 0x00000010 */
38580 #define UCPD_CR_RXMODE                      UCPD_CR_RXMODE_Msk                   /*!< Receiver mode  */
38581 #define UCPD_CR_PHYRXEN_Pos                 (5U)
38582 #define UCPD_CR_PHYRXEN_Msk                 (0x1UL << UCPD_CR_PHYRXEN_Pos)       /*!< 0x00000020 */
38583 #define UCPD_CR_PHYRXEN                     UCPD_CR_PHYRXEN_Msk                  /*!< Controls enable of USB Power Delivery receiver  */
38584 #define UCPD_CR_PHYCCSEL_Pos                (6U)
38585 #define UCPD_CR_PHYCCSEL_Msk                (0x1UL << UCPD_CR_PHYCCSEL_Pos)      /*!< 0x00000040 */
38586 #define UCPD_CR_PHYCCSEL                    UCPD_CR_PHYCCSEL_Msk                 /*!<  */
38587 #define UCPD_CR_ANASUBMODE_Pos              (7U)
38588 #define UCPD_CR_ANASUBMODE_Msk              (0x3UL << UCPD_CR_ANASUBMODE_Pos)    /*!< 0x00000180 */
38589 #define UCPD_CR_ANASUBMODE                  UCPD_CR_ANASUBMODE_Msk               /*!< Analog PHY sub-mode   */
38590 #define UCPD_CR_ANASUBMODE_0                (0x1UL << UCPD_CR_ANASUBMODE_Pos)    /*!< 0x00000080 */
38591 #define UCPD_CR_ANASUBMODE_1                (0x2UL << UCPD_CR_ANASUBMODE_Pos)    /*!< 0x00000100 */
38592 #define UCPD_CR_ANAMODE_Pos                 (9U)
38593 #define UCPD_CR_ANAMODE_Msk                 (0x1UL << UCPD_CR_ANAMODE_Pos)       /*!< 0x00000200 */
38594 #define UCPD_CR_ANAMODE                     UCPD_CR_ANAMODE_Msk                  /*!< Analog PHY working mode   */
38595 #define UCPD_CR_CCENABLE_Pos                (10U)
38596 #define UCPD_CR_CCENABLE_Msk                (0x3UL << UCPD_CR_CCENABLE_Pos)      /*!< 0x00000C00 */
38597 #define UCPD_CR_CCENABLE                    UCPD_CR_CCENABLE_Msk                 /*!<  */
38598 #define UCPD_CR_CCENABLE_0                  (0x1UL << UCPD_CR_CCENABLE_Pos)      /*!< 0x00000400 */
38599 #define UCPD_CR_CCENABLE_1                  (0x2UL << UCPD_CR_CCENABLE_Pos)      /*!< 0x00000800 */
38600 #define UCPD_CR_USEEXTPHY_Pos               (12U)
38601 #define UCPD_CR_USEEXTPHY_Msk               (0x1UL << UCPD_CR_USEEXTPHY_Pos)     /*!< 0x00001000 */
38602 #define UCPD_CR_USEEXTPHY                   UCPD_CR_USEEXTPHY_Msk                /*!< Controls enable of USB Power Delivery transmitter */
38603 #define UCPD_CR_CC2VCONNEN_Pos              (13U)
38604 #define UCPD_CR_CC2VCONNEN_Msk              (0x1UL << UCPD_CR_CC2VCONNEN_Pos)    /*!< 0x00002000 */
38605 #define UCPD_CR_CC2VCONNEN                  UCPD_CR_CC2VCONNEN_Msk               /*!< VCONN enable for CC2 */
38606 #define UCPD_CR_CC1VCONNEN_Pos              (14U)
38607 #define UCPD_CR_CC1VCONNEN_Msk              (0x1UL << UCPD_CR_CC1VCONNEN_Pos)    /*!< 0x00004000 */
38608 #define UCPD_CR_CC1VCONNEN                  UCPD_CR_CC1VCONNEN_Msk               /*!< VCONN enable for CC1 */
38609 #define UCPD_CR_DBATEN_Pos                  (15U)
38610 #define UCPD_CR_DBATEN_Msk                  (0x1UL << UCPD_CR_DBATEN_Pos)        /*!< 0x00008000 */
38611 #define UCPD_CR_DBATEN                      UCPD_CR_DBATEN_Msk                   /*!< Enable dead battery behavior (Active High) */
38612 #define UCPD_CR_FRSTX_Pos                   (17U)
38613 #define UCPD_CR_FRSTX_Msk                   (0x1UL << UCPD_CR_FRSTX_Pos)         /*!< 0x00020000 */
38614 #define UCPD_CR_FRSTX                       UCPD_CR_FRSTX_Msk                    /*!< Signal Fast Role Swap request */
38615 #define UCPD_CR_RDCH_Pos                    (18U)
38616 #define UCPD_CR_RDCH_Msk                    (0x1UL << UCPD_CR_RDCH_Pos)          /*!< 0x00040000 */
38617 #define UCPD_CR_RDCH                        UCPD_CR_RDCH_Msk                     /*!<  */
38618 #define UCPD_CR_RPUSBABSENT_Pos             (19U)
38619 #define UCPD_CR_RPUSBABSENT_Msk             (0x1UL << UCPD_CR_RPUSBABSENT_Pos)   /*!< 0x00080000 */
38620 #define UCPD_CR_RPUSBABSENT                 UCPD_CR_RPUSBABSENT_Msk              /*!<  */
38621 #define UCPD_CR_CC1TCDIS_Pos                (20U)
38622 #define UCPD_CR_CC1TCDIS_Msk                (0x1UL << UCPD_CR_CC1TCDIS_Pos)      /*!< 0x00100000 */
38623 #define UCPD_CR_CC1TCDIS                    UCPD_CR_CC1TCDIS_Msk                 /*!< The bit allows the Type-C detector for CC0 to be disabled. */
38624 #define UCPD_CR_CC2TCDIS_Pos                (21U)
38625 #define UCPD_CR_CC2TCDIS_Msk                (0x1UL << UCPD_CR_CC2TCDIS_Pos)      /*!< 0x00200000 */
38626 #define UCPD_CR_CC2TCDIS                    UCPD_CR_CC2TCDIS_Msk                 /*!< The bit allows the Type-C detector for CC2 to be disabled. */
38627 
38628 /********************  Bits definition for UCPD_IMR register  ********************/
38629 #define UCPD_IMR_TXISIE_Pos                 (0U)
38630 #define UCPD_IMR_TXISIE_Msk                 (0x1UL << UCPD_IMR_TXISIE_Pos)       /*!< 0x00000001 */
38631 #define UCPD_IMR_TXISIE                     UCPD_IMR_TXISIE_Msk                  /*!< Enable TXIS interrupt  */
38632 #define UCPD_IMR_TXMSGDISCIE_Pos            (1U)
38633 #define UCPD_IMR_TXMSGDISCIE_Msk            (0x1UL << UCPD_IMR_TXMSGDISCIE_Pos)  /*!< 0x00000002 */
38634 #define UCPD_IMR_TXMSGDISCIE                UCPD_IMR_TXMSGDISCIE_Msk             /*!< Enable TXMSGDISC interrupt  */
38635 #define UCPD_IMR_TXMSGSENTIE_Pos            (2U)
38636 #define UCPD_IMR_TXMSGSENTIE_Msk            (0x1UL << UCPD_IMR_TXMSGSENTIE_Pos)  /*!< 0x00000004 */
38637 #define UCPD_IMR_TXMSGSENTIE                UCPD_IMR_TXMSGSENTIE_Msk             /*!< Enable TXMSGSENT interrupt  */
38638 #define UCPD_IMR_TXMSGABTIE_Pos             (3U)
38639 #define UCPD_IMR_TXMSGABTIE_Msk             (0x1UL << UCPD_IMR_TXMSGABTIE_Pos)   /*!< 0x00000008 */
38640 #define UCPD_IMR_TXMSGABTIE                 UCPD_IMR_TXMSGABTIE_Msk              /*!< Enable TXMSGABT interrupt  */
38641 #define UCPD_IMR_HRSTDISCIE_Pos             (4U)
38642 #define UCPD_IMR_HRSTDISCIE_Msk             (0x1UL << UCPD_IMR_HRSTDISCIE_Pos)   /*!< 0x00000010 */
38643 #define UCPD_IMR_HRSTDISCIE                 UCPD_IMR_HRSTDISCIE_Msk              /*!< Enable HRSTDISC interrupt  */
38644 #define UCPD_IMR_HRSTSENTIE_Pos             (5U)
38645 #define UCPD_IMR_HRSTSENTIE_Msk             (0x1UL << UCPD_IMR_HRSTSENTIE_Pos)   /*!< 0x00000020 */
38646 #define UCPD_IMR_HRSTSENTIE                 UCPD_IMR_HRSTSENTIE_Msk              /*!< Enable HRSTSENT interrupt  */
38647 #define UCPD_IMR_TXUNDIE_Pos                (6U)
38648 #define UCPD_IMR_TXUNDIE_Msk                (0x1UL << UCPD_IMR_TXUNDIE_Pos)      /*!< 0x00000040 */
38649 #define UCPD_IMR_TXUNDIE                    UCPD_IMR_TXUNDIE_Msk                 /*!< Enable TXUND interrupt  */
38650 #define UCPD_IMR_RXNEIE_Pos                 (8U)
38651 #define UCPD_IMR_RXNEIE_Msk                 (0x1UL << UCPD_IMR_RXNEIE_Pos)       /*!< 0x00000100 */
38652 #define UCPD_IMR_RXNEIE                     UCPD_IMR_RXNEIE_Msk                  /*!< Enable RXNE interrupt  */
38653 #define UCPD_IMR_RXORDDETIE_Pos             (9U)
38654 #define UCPD_IMR_RXORDDETIE_Msk             (0x1UL << UCPD_IMR_RXORDDETIE_Pos)   /*!< 0x00000200 */
38655 #define UCPD_IMR_RXORDDETIE                 UCPD_IMR_RXORDDETIE_Msk              /*!< Enable RXORDDET interrupt  */
38656 #define UCPD_IMR_RXHRSTDETIE_Pos            (10U)
38657 #define UCPD_IMR_RXHRSTDETIE_Msk            (0x1UL << UCPD_IMR_RXHRSTDETIE_Pos)  /*!< 0x00000400 */
38658 #define UCPD_IMR_RXHRSTDETIE                UCPD_IMR_RXHRSTDETIE_Msk             /*!< Enable RXHRSTDET interrupt  */
38659 #define UCPD_IMR_RXOVRIE_Pos                (11U)
38660 #define UCPD_IMR_RXOVRIE_Msk                (0x1UL << UCPD_IMR_RXOVRIE_Pos)      /*!< 0x00000800 */
38661 #define UCPD_IMR_RXOVRIE                    UCPD_IMR_RXOVRIE_Msk                 /*!< Enable RXOVR interrupt  */
38662 #define UCPD_IMR_RXMSGENDIE_Pos             (12U)
38663 #define UCPD_IMR_RXMSGENDIE_Msk             (0x1UL << UCPD_IMR_RXMSGENDIE_Pos)   /*!< 0x00001000 */
38664 #define UCPD_IMR_RXMSGENDIE                 UCPD_IMR_RXMSGENDIE_Msk              /*!< Enable RXMSGEND interrupt  */
38665 #define UCPD_IMR_TYPECEVT1IE_Pos            (14U)
38666 #define UCPD_IMR_TYPECEVT1IE_Msk            (0x1UL << UCPD_IMR_TYPECEVT1IE_Pos)  /*!< 0x00004000 */
38667 #define UCPD_IMR_TYPECEVT1IE                UCPD_IMR_TYPECEVT1IE_Msk             /*!< Enable TYPECEVT1IE interrupt  */
38668 #define UCPD_IMR_TYPECEVT2IE_Pos            (15U)
38669 #define UCPD_IMR_TYPECEVT2IE_Msk            (0x1UL << UCPD_IMR_TYPECEVT2IE_Pos)  /*!< 0x00008000 */
38670 #define UCPD_IMR_TYPECEVT2IE                UCPD_IMR_TYPECEVT2IE_Msk             /*!< Enable TYPECEVT2IE interrupt  */
38671 
38672 /********************  Bits definition for UCPD_SR register  *********************/
38673 #define UCPD_SR_TXIS_Pos                    (0U)
38674 #define UCPD_SR_TXIS_Msk                    (0x1UL << UCPD_SR_TXIS_Pos)          /*!< 0x00000001 */
38675 #define UCPD_SR_TXIS                        UCPD_SR_TXIS_Msk                     /*!< Transmit interrupt status  */
38676 #define UCPD_SR_TXMSGDISC_Pos               (1U)
38677 #define UCPD_SR_TXMSGDISC_Msk               (0x1UL << UCPD_SR_TXMSGDISC_Pos)     /*!< 0x00000002 */
38678 #define UCPD_SR_TXMSGDISC                   UCPD_SR_TXMSGDISC_Msk                /*!< Transmit message discarded interrupt  */
38679 #define UCPD_SR_TXMSGSENT_Pos               (2U)
38680 #define UCPD_SR_TXMSGSENT_Msk               (0x1UL << UCPD_SR_TXMSGSENT_Pos)     /*!< 0x00000004 */
38681 #define UCPD_SR_TXMSGSENT                   UCPD_SR_TXMSGSENT_Msk                /*!< Transmit message sent interrupt  */
38682 #define UCPD_SR_TXMSGABT_Pos                (3U)
38683 #define UCPD_SR_TXMSGABT_Msk                (0x1UL << UCPD_SR_TXMSGABT_Pos)      /*!< 0x00000008 */
38684 #define UCPD_SR_TXMSGABT                    UCPD_SR_TXMSGABT_Msk                 /*!< Transmit message abort interrupt  */
38685 #define UCPD_SR_HRSTDISC_Pos                (4U)
38686 #define UCPD_SR_HRSTDISC_Msk                (0x1UL << UCPD_SR_HRSTDISC_Pos)      /*!< 0x00000010 */
38687 #define UCPD_SR_HRSTDISC                    UCPD_SR_HRSTDISC_Msk                 /*!< HRST discarded interrupt  */
38688 #define UCPD_SR_HRSTSENT_Pos                (5U)
38689 #define UCPD_SR_HRSTSENT_Msk                (0x1UL << UCPD_SR_HRSTSENT_Pos)      /*!< 0x00000020 */
38690 #define UCPD_SR_HRSTSENT                    UCPD_SR_HRSTSENT_Msk                 /*!< HRST sent interrupt  */
38691 #define UCPD_SR_TXUND_Pos                   (6U)
38692 #define UCPD_SR_TXUND_Msk                   (0x1UL << UCPD_SR_TXUND_Pos)         /*!< 0x00000040 */
38693 #define UCPD_SR_TXUND                       UCPD_SR_TXUND_Msk                    /*!< Tx data underrun condition interrupt  */
38694 #define UCPD_SR_RXNE_Pos                    (8U)
38695 #define UCPD_SR_RXNE_Msk                    (0x1UL << UCPD_SR_RXNE_Pos)          /*!< 0x00000100 */
38696 #define UCPD_SR_RXNE                        UCPD_SR_RXNE_Msk                     /*!< Receive data register not empty interrupt  */
38697 #define UCPD_SR_RXORDDET_Pos                (9U)
38698 #define UCPD_SR_RXORDDET_Msk                (0x1UL << UCPD_SR_RXORDDET_Pos)      /*!< 0x00000200 */
38699 #define UCPD_SR_RXORDDET                    UCPD_SR_RXORDDET_Msk                 /*!< Rx ordered set (4 K-codes) detected interrupt  */
38700 #define UCPD_SR_RXHRSTDET_Pos               (10U)
38701 #define UCPD_SR_RXHRSTDET_Msk               (0x1UL << UCPD_SR_RXHRSTDET_Pos)     /*!< 0x00000400 */
38702 #define UCPD_SR_RXHRSTDET                   UCPD_SR_RXHRSTDET_Msk                /*!< Rx Hard Reset detect interrupt  */
38703 #define UCPD_SR_RXOVR_Pos                   (11U)
38704 #define UCPD_SR_RXOVR_Msk                   (0x1UL << UCPD_SR_RXOVR_Pos)         /*!< 0x00000800 */
38705 #define UCPD_SR_RXOVR                       UCPD_SR_RXOVR_Msk                    /*!< Rx data overflow interrupt  */
38706 #define UCPD_SR_RXMSGEND_Pos                (12U)
38707 #define UCPD_SR_RXMSGEND_Msk                (0x1UL << UCPD_SR_RXMSGEND_Pos)      /*!< 0x00001000 */
38708 #define UCPD_SR_RXMSGEND                    UCPD_SR_RXMSGEND_Msk                 /*!< Rx message received  */
38709 #define UCPD_SR_RXERR_Pos                   (13U)
38710 #define UCPD_SR_RXERR_Msk                   (0x1UL << UCPD_SR_RXERR_Pos)         /*!< 0x00002000 */
38711 #define UCPD_SR_RXERR                       UCPD_SR_RXERR_Msk                    /*!< RX Error */
38712 #define UCPD_SR_TYPECEVT1_Pos               (14U)
38713 #define UCPD_SR_TYPECEVT1_Msk               (0x1UL << UCPD_SR_TYPECEVT1_Pos)     /*!< 0x00004000 */
38714 #define UCPD_SR_TYPECEVT1                   UCPD_SR_TYPECEVT1_Msk                /*!< Type C voltage level event on CC1  */
38715 #define UCPD_SR_TYPECEVT2_Pos               (15U)
38716 #define UCPD_SR_TYPECEVT2_Msk               (0x1UL << UCPD_SR_TYPECEVT2_Pos)     /*!< 0x00008000 */
38717 #define UCPD_SR_TYPECEVT2                   UCPD_SR_TYPECEVT2_Msk                /*!< Type C voltage level event on CC2  */
38718 #define UCPD_SR_TYPEC_VSTATE_CC1_Pos        (16U)
38719 #define UCPD_SR_TYPEC_VSTATE_CC1_Msk        (0x3UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00030000 */
38720 #define UCPD_SR_TYPEC_VSTATE_CC1            UCPD_SR_TYPEC_VSTATE_CC1_Msk           /*!< Status of DC level on CC1 pin  */
38721 #define UCPD_SR_TYPEC_VSTATE_CC1_0          (0x1UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00010000 */
38722 #define UCPD_SR_TYPEC_VSTATE_CC1_1          (0x2UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00020000 */
38723 #define UCPD_SR_TYPEC_VSTATE_CC2_Pos        (18U)
38724 #define UCPD_SR_TYPEC_VSTATE_CC2_Msk        (0x3UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x000C0000 */
38725 #define UCPD_SR_TYPEC_VSTATE_CC2            UCPD_SR_TYPEC_VSTATE_CC2_Msk           /*!<Status of DC level on CC2 pin  */
38726 #define UCPD_SR_TYPEC_VSTATE_CC2_0          (0x1UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x00040000 */
38727 #define UCPD_SR_TYPEC_VSTATE_CC2_1          (0x2UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x00080000 */
38728 
38729 /********************  Bits definition for UCPD_ICR register  ********************/
38730 #define UCPD_ICR_TXMSGDISCCF_Pos            (1U)
38731 #define UCPD_ICR_TXMSGDISCCF_Msk            (0x1UL << UCPD_ICR_TXMSGDISCCF_Pos)  /*!< 0x00000002 */
38732 #define UCPD_ICR_TXMSGDISCCF                UCPD_ICR_TXMSGDISCCF_Msk             /*!< Tx message discarded flag (TXMSGDISC) clear  */
38733 #define UCPD_ICR_TXMSGSENTCF_Pos            (2U)
38734 #define UCPD_ICR_TXMSGSENTCF_Msk            (0x1UL << UCPD_ICR_TXMSGSENTCF_Pos)  /*!< 0x00000004 */
38735 #define UCPD_ICR_TXMSGSENTCF                UCPD_ICR_TXMSGSENTCF_Msk             /*!< Tx message sent flag (TXMSGSENT) clear  */
38736 #define UCPD_ICR_TXMSGABTCF_Pos             (3U)
38737 #define UCPD_ICR_TXMSGABTCF_Msk             (0x1UL << UCPD_ICR_TXMSGABTCF_Pos)   /*!< 0x00000008 */
38738 #define UCPD_ICR_TXMSGABTCF                 UCPD_ICR_TXMSGABTCF_Msk              /*!< Tx message abort flag (TXMSGABT) clear  */
38739 #define UCPD_ICR_HRSTDISCCF_Pos             (4U)
38740 #define UCPD_ICR_HRSTDISCCF_Msk             (0x1UL << UCPD_ICR_HRSTDISCCF_Pos)   /*!< 0x00000010 */
38741 #define UCPD_ICR_HRSTDISCCF                 UCPD_ICR_HRSTDISCCF_Msk              /*!< Hard reset discarded flag (HRSTDISC) clear  */
38742 #define UCPD_ICR_HRSTSENTCF_Pos             (5U)
38743 #define UCPD_ICR_HRSTSENTCF_Msk             (0x1UL << UCPD_ICR_HRSTSENTCF_Pos)   /*!< 0x00000020 */
38744 #define UCPD_ICR_HRSTSENTCF                 UCPD_ICR_HRSTSENTCF_Msk              /*!< Hard reset sent flag (HRSTSENT) clear  */
38745 #define UCPD_ICR_TXUNDCF_Pos                (6U)
38746 #define UCPD_ICR_TXUNDCF_Msk                (0x1UL << UCPD_ICR_TXUNDCF_Pos)      /*!< 0x00000040 */
38747 #define UCPD_ICR_TXUNDCF                    UCPD_ICR_TXUNDCF_Msk                 /*!< Tx underflow flag (TXUND) clear  */
38748 #define UCPD_ICR_RXORDDETCF_Pos             (9U)
38749 #define UCPD_ICR_RXORDDETCF_Msk             (0x1UL << UCPD_ICR_RXORDDETCF_Pos)   /*!< 0x00000200 */
38750 #define UCPD_ICR_RXORDDETCF                 UCPD_ICR_RXORDDETCF_Msk              /*!< Rx ordered set detect flag (RXORDDET) clear  */
38751 #define UCPD_ICR_RXHRSTDETCF_Pos            (10U)
38752 #define UCPD_ICR_RXHRSTDETCF_Msk            (0x1UL << UCPD_ICR_RXHRSTDETCF_Pos)  /*!< 0x00000400 */
38753 #define UCPD_ICR_RXHRSTDETCF                UCPD_ICR_RXHRSTDETCF_Msk             /*!< Rx Hard Reset detected flag (RXHRSTDET) clear  */
38754 #define UCPD_ICR_RXOVRCF_Pos                (11U)
38755 #define UCPD_ICR_RXOVRCF_Msk                (0x1UL << UCPD_ICR_RXOVRCF_Pos)      /*!< 0x00000800 */
38756 #define UCPD_ICR_RXOVRCF                    UCPD_ICR_RXOVRCF_Msk                 /*!< Rx overflow flag (RXOVR) clear  */
38757 #define UCPD_ICR_RXMSGENDCF_Pos             (12U)
38758 #define UCPD_ICR_RXMSGENDCF_Msk             (0x1UL << UCPD_ICR_RXMSGENDCF_Pos)   /*!< 0x00001000 */
38759 #define UCPD_ICR_RXMSGENDCF                 UCPD_ICR_RXMSGENDCF_Msk              /*!< Rx message received flag (RXMSGEND) clear  */
38760 #define UCPD_ICR_TYPECEVT1CF_Pos            (14U)
38761 #define UCPD_ICR_TYPECEVT1CF_Msk            (0x1UL << UCPD_ICR_TYPECEVT1CF_Pos)  /*!< 0x00004000 */
38762 #define UCPD_ICR_TYPECEVT1CF                UCPD_ICR_TYPECEVT1CF_Msk             /*!< TypeC event (CC1) flag (TYPECEVT1) clear  */
38763 #define UCPD_ICR_TYPECEVT2CF_Pos            (15U)
38764 #define UCPD_ICR_TYPECEVT2CF_Msk            (0x1UL << UCPD_ICR_TYPECEVT2CF_Pos)  /*!< 0x00008000 */
38765 #define UCPD_ICR_TYPECEVT2CF                UCPD_ICR_TYPECEVT2CF_Msk             /*!< TypeC event (CC2) flag (TYPECEVT2) clear  */
38766 
38767 /********************  Bits definition for UCPD_TXORDSET register  ***************/
38768 #define UCPD_TX_ORDSET_TXORDSET_Pos         (0U)
38769 #define UCPD_TX_ORDSET_TXORDSET_Msk         (0xFFFFFUL << UCPD_TX_ORDSET_TXORDSET_Pos)/*!< 0x000FFFFF */
38770 #define UCPD_TX_ORDSET_TXORDSET             UCPD_TX_ORDSET_TXORDSET_Msk               /*!< Tx Ordered Set */
38771 
38772 /********************  Bits definition for UCPD_TXPAYSZ register  ****************/
38773 #define UCPD_TX_PAYSZ_TXPAYSZ_Pos           (0U)
38774 #define UCPD_TX_PAYSZ_TXPAYSZ_Msk           (0x3FFUL << UCPD_TX_PAYSZ_TXPAYSZ_Pos)/*!< 0x000003FF */
38775 #define UCPD_TX_PAYSZ_TXPAYSZ               UCPD_TX_PAYSZ_TXPAYSZ_Msk             /*!< Tx payload size in bytes  */
38776 
38777 /********************  Bits definition for UCPD_TXDR register  *******************/
38778 #define UCPD_TXDR_TXDATA_Pos                (0U)
38779 #define UCPD_TXDR_TXDATA_Msk                (0xFFUL << UCPD_TXDR_TXDATA_Pos)     /*!< 0x000000FF */
38780 #define UCPD_TXDR_TXDATA                    UCPD_TXDR_TXDATA_Msk                 /*!< Tx Data Register */
38781 
38782 /********************  Bits definition for UCPD_RXORDSET register  ***************/
38783 #define UCPD_RX_ORDSET_RXORDSET_Pos         (0U)
38784 #define UCPD_RX_ORDSET_RXORDSET_Msk         (0x7UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000007 */
38785 #define UCPD_RX_ORDSET_RXORDSET             UCPD_RX_ORDSET_RXORDSET_Msk            /*!< Rx Ordered Set Code detected  */
38786 #define UCPD_RX_ORDSET_RXORDSET_0           (0x1UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000001 */
38787 #define UCPD_RX_ORDSET_RXORDSET_1           (0x2UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000002 */
38788 #define UCPD_RX_ORDSET_RXORDSET_2           (0x4UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000004 */
38789 #define UCPD_RX_ORDSET_RXSOP3OF4_Pos        (3U)
38790 #define UCPD_RX_ORDSET_RXSOP3OF4_Msk        (0x1UL << UCPD_RX_ORDSET_RXSOP3OF4_Pos)/*!< 0x00000008 */
38791 #define UCPD_RX_ORDSET_RXSOP3OF4            UCPD_RX_ORDSET_RXSOP3OF4_Msk           /*!< Rx Ordered Set Debug indication */
38792 #define UCPD_RX_ORDSET_RXSOPKINVALID_Pos    (4U)
38793 #define UCPD_RX_ORDSET_RXSOPKINVALID_Msk    (0x7UL << UCPD_RX_ORDSET_RXSOPKINVALID_Pos)/*!< 0x00000070 */
38794 #define UCPD_RX_ORDSET_RXSOPKINVALID        UCPD_RX_ORDSET_RXSOPKINVALID_Msk           /*!< Rx Ordered Set corrupted K-Codes (Debug) */
38795 
38796 /********************  Bits definition for UCPD_RXPAYSZ register  ****************/
38797 #define UCPD_RX_PAYSZ_RXPAYSZ_Pos           (0U)
38798 #define UCPD_RX_PAYSZ_RXPAYSZ_Msk           (0x3FFUL << UCPD_RX_PAYSZ_RXPAYSZ_Pos)/*!< 0x000003FF */
38799 #define UCPD_RX_PAYSZ_RXPAYSZ               UCPD_RX_PAYSZ_RXPAYSZ_Msk             /*!< Rx payload size in bytes  */
38800 
38801 /********************  Bits definition for UCPD_RXDR register  *******************/
38802 #define UCPD_RXDR_RXDATA_Pos                (0U)
38803 #define UCPD_RXDR_RXDATA_Msk                (0xFFUL << UCPD_RXDR_RXDATA_Pos)     /*!< 0x000000FF */
38804 #define UCPD_RXDR_RXDATA                    UCPD_RXDR_RXDATA_Msk                 /*!< 8-bit receive data  */
38805 
38806 /********************  Bits definition for UCPD_RXORDEXT1 register  **************/
38807 #define UCPD_RX_ORDEXT1_RXSOPX1_Pos         (0U)
38808 #define UCPD_RX_ORDEXT1_RXSOPX1_Msk         (0xFFFFFUL << UCPD_RX_ORDEXT1_RXSOPX1_Pos)/*!< 0x000FFFFF */
38809 #define UCPD_RX_ORDEXT1_RXSOPX1             UCPD_RX_ORDEXT1_RXSOPX1_Msk               /*!< RX Ordered Set Extension Register 1 */
38810 
38811 /********************  Bits definition for UCPD_RXORDEXT2 register  **************/
38812 #define UCPD_RX_ORDEXT2_RXSOPX2_Pos         (0U)
38813 #define UCPD_RX_ORDEXT2_RXSOPX2_Msk         (0xFFFFFUL << UCPD_RX_ORDEXT2_RXSOPX2_Pos)/*!< 0x000FFFFF */
38814 #define UCPD_RX_ORDEXT2_RXSOPX2             UCPD_RX_ORDEXT2_RXSOPX2_Msk               /*!< RX Ordered Set Extension Register 1 */
38815 
38816 
38817 /******************************************************************************/
38818 /*                                                                            */
38819 /*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
38820 /*                                                                            */
38821 /******************************************************************************/
38822 /******************  Bit definition for USART_CR1 register  *******************/
38823 #define USART_CR1_UE_Pos                    (0U)
38824 #define USART_CR1_UE_Msk                    (0x1UL << USART_CR1_UE_Pos)             /*!< 0x00000001 */
38825 #define USART_CR1_UE                        USART_CR1_UE_Msk                        /*!< USART Enable */
38826 #define USART_CR1_UESM_Pos                  (1U)
38827 #define USART_CR1_UESM_Msk                  (0x1UL << USART_CR1_UESM_Pos)           /*!< 0x00000002 */
38828 #define USART_CR1_UESM                      USART_CR1_UESM_Msk                      /*!< USART Enable in STOP Mode */
38829 #define USART_CR1_RE_Pos                    (2U)
38830 #define USART_CR1_RE_Msk                    (0x1UL << USART_CR1_RE_Pos)             /*!< 0x00000004 */
38831 #define USART_CR1_RE                        USART_CR1_RE_Msk                        /*!< Receiver Enable */
38832 #define USART_CR1_TE_Pos                    (3U)
38833 #define USART_CR1_TE_Msk                    (0x1UL << USART_CR1_TE_Pos)             /*!< 0x00000008 */
38834 #define USART_CR1_TE                        USART_CR1_TE_Msk                        /*!< Transmitter Enable */
38835 #define USART_CR1_IDLEIE_Pos                (4U)
38836 #define USART_CR1_IDLEIE_Msk                (0x1UL << USART_CR1_IDLEIE_Pos)         /*!< 0x00000010 */
38837 #define USART_CR1_IDLEIE                    USART_CR1_IDLEIE_Msk                    /*!< IDLE Interrupt Enable */
38838 #define USART_CR1_RXNEIE_Pos                (5U)
38839 #define USART_CR1_RXNEIE_Msk                (0x1UL << USART_CR1_RXNEIE_Pos)         /*!< 0x00000020 */
38840 #define USART_CR1_RXNEIE                    USART_CR1_RXNEIE_Msk                    /*!< RXNE Interrupt Enable */
38841 #define USART_CR1_RXNEIE_RXFNEIE_Pos        USART_CR1_RXNEIE_Pos
38842 #define USART_CR1_RXNEIE_RXFNEIE_Msk        USART_CR1_RXNEIE_Msk                    /*!< 0x00000020 */
38843 #define USART_CR1_RXNEIE_RXFNEIE            USART_CR1_RXNEIE_Msk                    /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
38844 #define USART_CR1_TCIE_Pos                  (6U)
38845 #define USART_CR1_TCIE_Msk                  (0x1UL << USART_CR1_TCIE_Pos)           /*!< 0x00000040 */
38846 #define USART_CR1_TCIE                      USART_CR1_TCIE_Msk                      /*!< Transmission Complete Interrupt Enable */
38847 #define USART_CR1_TXEIE_Pos                 (7U)
38848 #define USART_CR1_TXEIE_Msk                 (0x1UL << USART_CR1_TXEIE_Pos)          /*!< 0x00000080 */
38849 #define USART_CR1_TXEIE                     USART_CR1_TXEIE_Msk                     /*!< TXE Interrupt Enable */
38850 #define USART_CR1_TXEIE_TXFNFIE_Pos         (7U)
38851 #define USART_CR1_TXEIE_TXFNFIE_Msk         (0x1UL << USART_CR1_TXEIE_Pos)          /*!< 0x00000080 */
38852 #define USART_CR1_TXEIE_TXFNFIE             USART_CR1_TXEIE                         /*!< TXE and TX FIFO Not Full Interrupt Enable */
38853 #define USART_CR1_PEIE_Pos                  (8U)
38854 #define USART_CR1_PEIE_Msk                  (0x1UL << USART_CR1_PEIE_Pos)           /*!< 0x00000100 */
38855 #define USART_CR1_PEIE                      USART_CR1_PEIE_Msk                      /*!< PE Interrupt Enable */
38856 #define USART_CR1_PS_Pos                    (9U)
38857 #define USART_CR1_PS_Msk                    (0x1UL << USART_CR1_PS_Pos)             /*!< 0x00000200 */
38858 #define USART_CR1_PS                        USART_CR1_PS_Msk                        /*!< Parity Selection */
38859 #define USART_CR1_PCE_Pos                   (10U)
38860 #define USART_CR1_PCE_Msk                   (0x1UL << USART_CR1_PCE_Pos)            /*!< 0x00000400 */
38861 #define USART_CR1_PCE                       USART_CR1_PCE_Msk                       /*!< Parity Control Enable */
38862 #define USART_CR1_WAKE_Pos                  (11U)
38863 #define USART_CR1_WAKE_Msk                  (0x1UL << USART_CR1_WAKE_Pos)           /*!< 0x00000800 */
38864 #define USART_CR1_WAKE                      USART_CR1_WAKE_Msk                      /*!< Receiver Wakeup method */
38865 #define USART_CR1_M_Pos                     (12U)
38866 #define USART_CR1_M_Msk                     (0x10001UL << USART_CR1_M_Pos)         /*!< 0x10001000 */
38867 #define USART_CR1_M                         USART_CR1_M_Msk                        /*!< Word length */
38868 #define USART_CR1_M0_Pos                    (12U)
38869 #define USART_CR1_M0_Msk                    (0x1UL << USART_CR1_M0_Pos)             /*!< 0x00001000 */
38870 #define USART_CR1_M0                        USART_CR1_M0_Msk                        /*!< Word length - Bit 0 */
38871 #define USART_CR1_MME_Pos                   (13U)
38872 #define USART_CR1_MME_Msk                   (0x1UL << USART_CR1_MME_Pos)            /*!< 0x00002000 */
38873 #define USART_CR1_MME                       USART_CR1_MME_Msk                       /*!< Mute Mode Enable */
38874 #define USART_CR1_CMIE_Pos                  (14U)
38875 #define USART_CR1_CMIE_Msk                  (0x1UL << USART_CR1_CMIE_Pos)           /*!< 0x00004000 */
38876 #define USART_CR1_CMIE                      USART_CR1_CMIE_Msk                      /*!< Character match Interrupt Enable */
38877 #define USART_CR1_OVER8_Pos                 (15U)
38878 #define USART_CR1_OVER8_Msk                 (0x1UL << USART_CR1_OVER8_Pos)          /*!< 0x00008000 */
38879 #define USART_CR1_OVER8                     USART_CR1_OVER8_Msk                     /*!< Oversampling by 8-bit or 16-bit mode */
38880 #define USART_CR1_DEDT_Pos                  (16U)
38881 #define USART_CR1_DEDT_Msk                  (0x1FUL << USART_CR1_DEDT_Pos)          /*!< 0x001F0000 */
38882 #define USART_CR1_DEDT                      USART_CR1_DEDT_Msk                      /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
38883 #define USART_CR1_DEDT_0                    (0x01UL << USART_CR1_DEDT_Pos)          /*!< 0x00010000 */
38884 #define USART_CR1_DEDT_1                    (0x02UL << USART_CR1_DEDT_Pos)          /*!< 0x00020000 */
38885 #define USART_CR1_DEDT_2                    (0x04UL << USART_CR1_DEDT_Pos)          /*!< 0x00040000 */
38886 #define USART_CR1_DEDT_3                    (0x08UL << USART_CR1_DEDT_Pos)          /*!< 0x00080000 */
38887 #define USART_CR1_DEDT_4                    (0x10UL << USART_CR1_DEDT_Pos)          /*!< 0x00100000 */
38888 #define USART_CR1_DEAT_Pos                  (21U)
38889 #define USART_CR1_DEAT_Msk                  (0x1FUL << USART_CR1_DEAT_Pos)          /*!< 0x03E00000 */
38890 #define USART_CR1_DEAT                      USART_CR1_DEAT_Msk                      /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
38891 #define USART_CR1_DEAT_0                    (0x01UL << USART_CR1_DEAT_Pos)          /*!< 0x00200000 */
38892 #define USART_CR1_DEAT_1                    (0x02UL << USART_CR1_DEAT_Pos)          /*!< 0x00400000 */
38893 #define USART_CR1_DEAT_2                    (0x04UL << USART_CR1_DEAT_Pos)          /*!< 0x00800000 */
38894 #define USART_CR1_DEAT_3                    (0x08UL << USART_CR1_DEAT_Pos)          /*!< 0x01000000 */
38895 #define USART_CR1_DEAT_4                    (0x10UL << USART_CR1_DEAT_Pos)          /*!< 0x02000000 */
38896 #define USART_CR1_RTOIE_Pos                 (26U)
38897 #define USART_CR1_RTOIE_Msk                 (0x1UL << USART_CR1_RTOIE_Pos)          /*!< 0x04000000 */
38898 #define USART_CR1_RTOIE                     USART_CR1_RTOIE_Msk                     /*!< Receive Time Out Interrupt Enable */
38899 #define USART_CR1_EOBIE_Pos                 (27U)
38900 #define USART_CR1_EOBIE_Msk                 (0x1UL << USART_CR1_EOBIE_Pos)          /*!< 0x08000000 */
38901 #define USART_CR1_EOBIE                     USART_CR1_EOBIE_Msk                     /*!< End of Block Interrupt Enable */
38902 #define USART_CR1_M1_Pos                    (28U)
38903 #define USART_CR1_M1_Msk                    (0x1UL << USART_CR1_M1_Pos)             /*!< 0x10000000 */
38904 #define USART_CR1_M1                        USART_CR1_M1_Msk                        /*!< Word length - Bit 1 */
38905 #define USART_CR1_FIFOEN_Pos                (29U)
38906 #define USART_CR1_FIFOEN_Msk                (0x1UL << USART_CR1_FIFOEN_Pos)         /*!< 0x20000000 */
38907 #define USART_CR1_FIFOEN                    USART_CR1_FIFOEN_Msk                    /*!< FIFO mode enable */
38908 #define USART_CR1_TXFEIE_Pos                (30U)
38909 #define USART_CR1_TXFEIE_Msk                (0x1UL << USART_CR1_TXFEIE_Pos)         /*!< 0x40000000 */
38910 #define USART_CR1_TXFEIE                    USART_CR1_TXFEIE_Msk                    /*!< TX FIFO Empty Interrupt Enable */
38911 #define USART_CR1_RXFFIE_Pos                (31U)
38912 #define USART_CR1_RXFFIE_Msk                (0x1UL << USART_CR1_RXFFIE_Pos)         /*!< 0x80000000 */
38913 #define USART_CR1_RXFFIE                    USART_CR1_RXFFIE_Msk                    /*!< RX FIFO Full Interrupt Enable */
38914 
38915 /******************  Bit definition for USART_CR2 register  *******************/
38916 #define USART_CR2_SLVEN_Pos                 (0U)
38917 #define USART_CR2_SLVEN_Msk                 (0x1UL << USART_CR2_SLVEN_Pos)          /*!< 0x00000001 */
38918 #define USART_CR2_SLVEN                     USART_CR2_SLVEN_Msk                     /*!< Synchronous Slave mode enable */
38919 #define USART_CR2_DIS_NSS_Pos               (3U)
38920 #define USART_CR2_DIS_NSS_Msk               (0x1UL << USART_CR2_DIS_NSS_Pos)        /*!< 0x00000008 */
38921 #define USART_CR2_DIS_NSS                   USART_CR2_DIS_NSS_Msk                   /*!< Slave Select (NSS) pin management */
38922 #define USART_CR2_ADDM7_Pos                 (4U)
38923 #define USART_CR2_ADDM7_Msk                 (0x1UL << USART_CR2_ADDM7_Pos)          /*!< 0x00000010 */
38924 #define USART_CR2_ADDM7                     USART_CR2_ADDM7_Msk                     /*!< 7-bit or 4-bit Address Detection */
38925 #define USART_CR2_LBDL_Pos                  (5U)
38926 #define USART_CR2_LBDL_Msk                  (0x1UL << USART_CR2_LBDL_Pos)           /*!< 0x00000020 */
38927 #define USART_CR2_LBDL                      USART_CR2_LBDL_Msk                      /*!< LIN Break Detection Length */
38928 #define USART_CR2_LBDIE_Pos                 (6U)
38929 #define USART_CR2_LBDIE_Msk                 (0x1UL << USART_CR2_LBDIE_Pos)          /*!< 0x00000040 */
38930 #define USART_CR2_LBDIE                     USART_CR2_LBDIE_Msk                     /*!< LIN Break Detection Interrupt Enable */
38931 #define USART_CR2_LBCL_Pos                  (8U)
38932 #define USART_CR2_LBCL_Msk                  (0x1UL << USART_CR2_LBCL_Pos)           /*!< 0x00000100 */
38933 #define USART_CR2_LBCL                      USART_CR2_LBCL_Msk                      /*!< Last Bit Clock pulse */
38934 #define USART_CR2_CPHA_Pos                  (9U)
38935 #define USART_CR2_CPHA_Msk                  (0x1UL << USART_CR2_CPHA_Pos)           /*!< 0x00000200 */
38936 #define USART_CR2_CPHA                      USART_CR2_CPHA_Msk                      /*!< Clock Phase */
38937 #define USART_CR2_CPOL_Pos                  (10U)
38938 #define USART_CR2_CPOL_Msk                  (0x1UL << USART_CR2_CPOL_Pos)           /*!< 0x00000400 */
38939 #define USART_CR2_CPOL                      USART_CR2_CPOL_Msk                      /*!< Clock Polarity */
38940 #define USART_CR2_CLKEN_Pos                 (11U)
38941 #define USART_CR2_CLKEN_Msk                 (0x1UL << USART_CR2_CLKEN_Pos)          /*!< 0x00000800 */
38942 #define USART_CR2_CLKEN                     USART_CR2_CLKEN_Msk                     /*!< Clock Enable */
38943 #define USART_CR2_STOP_Pos                  (12U)
38944 #define USART_CR2_STOP_Msk                  (0x3UL << USART_CR2_STOP_Pos)           /*!< 0x00003000 */
38945 #define USART_CR2_STOP                      USART_CR2_STOP_Msk                      /*!< STOP[1:0] bits (STOP bits) */
38946 #define USART_CR2_STOP_0                    (0x1UL << USART_CR2_STOP_Pos)           /*!< 0x00001000 */
38947 #define USART_CR2_STOP_1                    (0x2UL << USART_CR2_STOP_Pos)           /*!< 0x00002000 */
38948 #define USART_CR2_LINEN_Pos                 (14U)
38949 #define USART_CR2_LINEN_Msk                 (0x1UL << USART_CR2_LINEN_Pos)          /*!< 0x00004000 */
38950 #define USART_CR2_LINEN                     USART_CR2_LINEN_Msk                     /*!< LIN mode enable */
38951 #define USART_CR2_SWAP_Pos                  (15U)
38952 #define USART_CR2_SWAP_Msk                  (0x1UL << USART_CR2_SWAP_Pos)           /*!< 0x00008000 */
38953 #define USART_CR2_SWAP                      USART_CR2_SWAP_Msk                      /*!< SWAP TX/RX pins */
38954 #define USART_CR2_RXINV_Pos                 (16U)
38955 #define USART_CR2_RXINV_Msk                 (0x1UL << USART_CR2_RXINV_Pos)          /*!< 0x00010000 */
38956 #define USART_CR2_RXINV                     USART_CR2_RXINV_Msk                     /*!< RX pin active level inversion */
38957 #define USART_CR2_TXINV_Pos                 (17U)
38958 #define USART_CR2_TXINV_Msk                 (0x1UL << USART_CR2_TXINV_Pos)          /*!< 0x00020000 */
38959 #define USART_CR2_TXINV                     USART_CR2_TXINV_Msk                     /*!< TX pin active level inversion */
38960 #define USART_CR2_DATAINV_Pos               (18U)
38961 #define USART_CR2_DATAINV_Msk               (0x1UL << USART_CR2_DATAINV_Pos)        /*!< 0x00040000 */
38962 #define USART_CR2_DATAINV                   USART_CR2_DATAINV_Msk                   /*!< Binary data inversion */
38963 #define USART_CR2_MSBFIRST_Pos              (19U)
38964 #define USART_CR2_MSBFIRST_Msk              (0x1UL << USART_CR2_MSBFIRST_Pos)       /*!< 0x00080000 */
38965 #define USART_CR2_MSBFIRST                  USART_CR2_MSBFIRST_Msk                  /*!< Most Significant Bit First */
38966 #define USART_CR2_ABREN_Pos                 (20U)
38967 #define USART_CR2_ABREN_Msk                 (0x1UL << USART_CR2_ABREN_Pos)          /*!< 0x00100000 */
38968 #define USART_CR2_ABREN                     USART_CR2_ABREN_Msk                     /*!< Auto Baud-Rate Enable*/
38969 #define USART_CR2_ABRMODE_Pos               (21U)
38970 #define USART_CR2_ABRMODE_Msk               (0x3UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00600000 */
38971 #define USART_CR2_ABRMODE                   USART_CR2_ABRMODE_Msk                   /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
38972 #define USART_CR2_ABRMODE_0                 (0x1UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00200000 */
38973 #define USART_CR2_ABRMODE_1                 (0x2UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00400000 */
38974 #define USART_CR2_RTOEN_Pos                 (23U)
38975 #define USART_CR2_RTOEN_Msk                 (0x1UL << USART_CR2_RTOEN_Pos)          /*!< 0x00800000 */
38976 #define USART_CR2_RTOEN                     USART_CR2_RTOEN_Msk                     /*!< Receiver Time-Out enable */
38977 #define USART_CR2_ADD_Pos                   (24U)
38978 #define USART_CR2_ADD_Msk                   (0xFFUL << USART_CR2_ADD_Pos)           /*!< 0xFF000000 */
38979 #define USART_CR2_ADD                       USART_CR2_ADD_Msk                       /*!< Address of the USART node */
38980 
38981 /******************  Bit definition for USART_CR3 register  *******************/
38982 #define USART_CR3_EIE_Pos                   (0U)
38983 #define USART_CR3_EIE_Msk                   (0x1UL << USART_CR3_EIE_Pos)            /*!< 0x00000001 */
38984 #define USART_CR3_EIE                       USART_CR3_EIE_Msk                       /*!< Error Interrupt Enable */
38985 #define USART_CR3_IREN_Pos                  (1U)
38986 #define USART_CR3_IREN_Msk                  (0x1UL << USART_CR3_IREN_Pos)           /*!< 0x00000002 */
38987 #define USART_CR3_IREN                      USART_CR3_IREN_Msk                      /*!< IrDA mode Enable */
38988 #define USART_CR3_IRLP_Pos                  (2U)
38989 #define USART_CR3_IRLP_Msk                  (0x1UL << USART_CR3_IRLP_Pos)           /*!< 0x00000004 */
38990 #define USART_CR3_IRLP                      USART_CR3_IRLP_Msk                      /*!< IrDA Low-Power */
38991 #define USART_CR3_HDSEL_Pos                 (3U)
38992 #define USART_CR3_HDSEL_Msk                 (0x1UL << USART_CR3_HDSEL_Pos)          /*!< 0x00000008 */
38993 #define USART_CR3_HDSEL                     USART_CR3_HDSEL_Msk                     /*!< Half-Duplex Selection */
38994 #define USART_CR3_NACK_Pos                  (4U)
38995 #define USART_CR3_NACK_Msk                  (0x1UL << USART_CR3_NACK_Pos)           /*!< 0x00000010 */
38996 #define USART_CR3_NACK                      USART_CR3_NACK_Msk                      /*!< SmartCard NACK enable */
38997 #define USART_CR3_SCEN_Pos                  (5U)
38998 #define USART_CR3_SCEN_Msk                  (0x1UL << USART_CR3_SCEN_Pos)           /*!< 0x00000020 */
38999 #define USART_CR3_SCEN                      USART_CR3_SCEN_Msk                      /*!< SmartCard mode enable */
39000 #define USART_CR3_DMAR_Pos                  (6U)
39001 #define USART_CR3_DMAR_Msk                  (0x1UL << USART_CR3_DMAR_Pos)           /*!< 0x00000040 */
39002 #define USART_CR3_DMAR                      USART_CR3_DMAR_Msk                      /*!< DMA Enable Receiver */
39003 #define USART_CR3_DMAT_Pos                  (7U)
39004 #define USART_CR3_DMAT_Msk                  (0x1UL << USART_CR3_DMAT_Pos)           /*!< 0x00000080 */
39005 #define USART_CR3_DMAT                      USART_CR3_DMAT_Msk                      /*!< DMA Enable Transmitter */
39006 #define USART_CR3_RTSE_Pos                  (8U)
39007 #define USART_CR3_RTSE_Msk                  (0x1UL << USART_CR3_RTSE_Pos)           /*!< 0x00000100 */
39008 #define USART_CR3_RTSE                      USART_CR3_RTSE_Msk                      /*!< RTS Enable */
39009 #define USART_CR3_CTSE_Pos                  (9U)
39010 #define USART_CR3_CTSE_Msk                  (0x1UL << USART_CR3_CTSE_Pos)           /*!< 0x00000200 */
39011 #define USART_CR3_CTSE                      USART_CR3_CTSE_Msk                      /*!< CTS Enable */
39012 #define USART_CR3_CTSIE_Pos                 (10U)
39013 #define USART_CR3_CTSIE_Msk                 (0x1UL << USART_CR3_CTSIE_Pos)          /*!< 0x00000400 */
39014 #define USART_CR3_CTSIE                     USART_CR3_CTSIE_Msk                     /*!< CTS Interrupt Enable */
39015 #define USART_CR3_ONEBIT_Pos                (11U)
39016 #define USART_CR3_ONEBIT_Msk                (0x1UL << USART_CR3_ONEBIT_Pos)         /*!< 0x00000800 */
39017 #define USART_CR3_ONEBIT                    USART_CR3_ONEBIT_Msk                    /*!< One sample bit method enable */
39018 #define USART_CR3_OVRDIS_Pos                (12U)
39019 #define USART_CR3_OVRDIS_Msk                (0x1UL << USART_CR3_OVRDIS_Pos)         /*!< 0x00001000 */
39020 #define USART_CR3_OVRDIS                    USART_CR3_OVRDIS_Msk                    /*!< Overrun Disable */
39021 #define USART_CR3_DDRE_Pos                  (13U)
39022 #define USART_CR3_DDRE_Msk                  (0x1UL << USART_CR3_DDRE_Pos)           /*!< 0x00002000 */
39023 #define USART_CR3_DDRE                      USART_CR3_DDRE_Msk                      /*!< DMA Disable on Reception Error */
39024 #define USART_CR3_DEM_Pos                   (14U)
39025 #define USART_CR3_DEM_Msk                   (0x1UL << USART_CR3_DEM_Pos)            /*!< 0x00004000 */
39026 #define USART_CR3_DEM                       USART_CR3_DEM_Msk                       /*!< Driver Enable Mode */
39027 #define USART_CR3_DEP_Pos                   (15U)
39028 #define USART_CR3_DEP_Msk                   (0x1UL << USART_CR3_DEP_Pos)            /*!< 0x00008000 */
39029 #define USART_CR3_DEP                       USART_CR3_DEP_Msk                       /*!< Driver Enable Polarity Selection */
39030 #define USART_CR3_SCARCNT_Pos               (17U)
39031 #define USART_CR3_SCARCNT_Msk               (0x7UL << USART_CR3_SCARCNT_Pos)        /*!< 0x000E0000 */
39032 #define USART_CR3_SCARCNT                   USART_CR3_SCARCNT_Msk                   /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
39033 #define USART_CR3_SCARCNT_0                 (0x1UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00020000 */
39034 #define USART_CR3_SCARCNT_1                 (0x2UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00040000 */
39035 #define USART_CR3_SCARCNT_2                 (0x4UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00080000 */
39036 #define USART_CR3_WUS_Pos                   (20U)
39037 #define USART_CR3_WUS_Msk                   (0x3UL << USART_CR3_WUS_Pos)            /*!< 0x00300000 */
39038 #define USART_CR3_WUS                       USART_CR3_WUS_Msk                       /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
39039 #define USART_CR3_WUS_0                     (0x1UL << USART_CR3_WUS_Pos)            /*!< 0x00100000 */
39040 #define USART_CR3_WUS_1                     (0x2UL << USART_CR3_WUS_Pos)            /*!< 0x00200000 */
39041 #define USART_CR3_WUFIE_Pos                 (22U)
39042 #define USART_CR3_WUFIE_Msk                 (0x1UL << USART_CR3_WUFIE_Pos)          /*!< 0x00400000 */
39043 #define USART_CR3_WUFIE                     USART_CR3_WUFIE_Msk                     /*!< Wake Up Interrupt Enable */
39044 #define USART_CR3_TXFTIE_Pos                (23U)
39045 #define USART_CR3_TXFTIE_Msk                (0x1UL << USART_CR3_TXFTIE_Pos)         /*!< 0x00800000 */
39046 #define USART_CR3_TXFTIE                    USART_CR3_TXFTIE_Msk                    /*!< TX FIFO Threshold Interrupt Enable */
39047 #define USART_CR3_TCBGTIE_Pos               (24U)
39048 #define USART_CR3_TCBGTIE_Msk               (0x1UL << USART_CR3_TCBGTIE_Pos)        /*!< 0x01000000 */
39049 #define USART_CR3_TCBGTIE                   USART_CR3_TCBGTIE_Msk                   /*!< Transmission Complete Before Guard Time Interrupt Enable */
39050 #define USART_CR3_RXFTCFG_Pos               (25U)
39051 #define USART_CR3_RXFTCFG_Msk               (0x7UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x0E000000 */
39052 #define USART_CR3_RXFTCFG                   USART_CR3_RXFTCFG_Msk                   /*!< RX FIFO Threshold Configuration */
39053 #define USART_CR3_RXFTCFG_0                 (0x1UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x02000000 */
39054 #define USART_CR3_RXFTCFG_1                 (0x2UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x04000000 */
39055 #define USART_CR3_RXFTCFG_2                 (0x4UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x08000000 */
39056 #define USART_CR3_RXFTIE_Pos                (28U)
39057 #define USART_CR3_RXFTIE_Msk                (0x1UL << USART_CR3_RXFTIE_Pos)         /*!< 0x10000000 */
39058 #define USART_CR3_RXFTIE                    USART_CR3_RXFTIE_Msk                    /*!< RX FIFO Threshold Interrupt Enable */
39059 #define USART_CR3_TXFTCFG_Pos               (29U)
39060 #define USART_CR3_TXFTCFG_Msk               (0x7UL << USART_CR3_TXFTCFG_Pos)        /*!< 0xE0000000 */
39061 #define USART_CR3_TXFTCFG                   USART_CR3_TXFTCFG_Msk                   /*!< TX FIFO Threshold configuration */
39062 #define USART_CR3_TXFTCFG_0                 (0x1UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x20000000 */
39063 #define USART_CR3_TXFTCFG_1                 (0x2UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x40000000 */
39064 #define USART_CR3_TXFTCFG_2                 (0x4UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x80000000 */
39065 
39066 /******************  Bit definition for USART_BRR register  *******************/
39067 #define USART_BRR_LPUART                    ((uint32_t)0x000FFFFF)                  /*!< LPUART Baud rate register [19:0] */
39068 #define USART_BRR_BRR                       ((uint16_t)0xFFFF)                      /*!< USART  Baud rate register [15:0] */
39069 
39070 /******************  Bit definition for USART_GTPR register  ******************/
39071 #define USART_GTPR_PSC_Pos                  (0U)
39072 #define USART_GTPR_PSC_Msk                  (0xFFUL << USART_GTPR_PSC_Pos)          /*!< 0x000000FF */
39073 #define USART_GTPR_PSC                      USART_GTPR_PSC_Msk                      /*!< PSC[7:0] bits (Prescaler value) */
39074 #define USART_GTPR_GT_Pos                   (8U)
39075 #define USART_GTPR_GT_Msk                   (0xFFUL << USART_GTPR_GT_Pos)           /*!< 0x0000FF00 */
39076 #define USART_GTPR_GT                       USART_GTPR_GT_Msk                       /*!< GT[7:0] bits (Guard time value) */
39077 
39078 /*******************  Bit definition for USART_RTOR register  *****************/
39079 #define USART_RTOR_RTO_Pos                  (0U)
39080 #define USART_RTOR_RTO_Msk                  (0xFFFFFFUL << USART_RTOR_RTO_Pos)      /*!< 0x00FFFFFF */
39081 #define USART_RTOR_RTO                      USART_RTOR_RTO_Msk                      /*!< Receiver Timeout Value */
39082 #define USART_RTOR_BLEN_Pos                 (24U)
39083 #define USART_RTOR_BLEN_Msk                 (0xFFUL << USART_RTOR_BLEN_Pos)         /*!< 0xFF000000 */
39084 #define USART_RTOR_BLEN                     USART_RTOR_BLEN_Msk                     /*!< Block Length */
39085 
39086 /*******************  Bit definition for USART_RQR register  ******************/
39087 #define USART_RQR_ABRRQ_Pos                 (0U)
39088 #define USART_RQR_ABRRQ_Msk                 (0x1UL << USART_RQR_ABRRQ_Pos)          /*!< 0x00000001 */
39089 #define USART_RQR_ABRRQ                     USART_RQR_ABRRQ_Msk                     /*!< Auto-Baud Rate Request */
39090 #define USART_RQR_SBKRQ_Pos                 (1U)
39091 #define USART_RQR_SBKRQ_Msk                 (0x1UL << USART_RQR_SBKRQ_Pos)          /*!< 0x00000002 */
39092 #define USART_RQR_SBKRQ                     USART_RQR_SBKRQ_Msk                     /*!< Send Break Request */
39093 #define USART_RQR_MMRQ_Pos                  (2U)
39094 #define USART_RQR_MMRQ_Msk                  (0x1UL << USART_RQR_MMRQ_Pos)           /*!< 0x00000004 */
39095 #define USART_RQR_MMRQ                      USART_RQR_MMRQ_Msk                      /*!< Mute Mode Request */
39096 #define USART_RQR_RXFRQ_Pos                 (3U)
39097 #define USART_RQR_RXFRQ_Msk                 (0x1UL << USART_RQR_RXFRQ_Pos)          /*!< 0x00000008 */
39098 #define USART_RQR_RXFRQ                     USART_RQR_RXFRQ_Msk                     /*!< Receive Data flush Request */
39099 #define USART_RQR_TXFRQ_Pos                 (4U)
39100 #define USART_RQR_TXFRQ_Msk                 (0x1UL << USART_RQR_TXFRQ_Pos)          /*!< 0x00000010 */
39101 #define USART_RQR_TXFRQ                     USART_RQR_TXFRQ_Msk                     /*!< Transmit Data flush Request */
39102 
39103 /*******************  Bit definition for USART_ISR register  ******************/
39104 #define USART_ISR_PE_Pos                    (0U)
39105 #define USART_ISR_PE_Msk                    (0x1UL << USART_ISR_PE_Pos)             /*!< 0x00000001 */
39106 #define USART_ISR_PE                        USART_ISR_PE_Msk                        /*!< Parity Error */
39107 #define USART_ISR_FE_Pos                    (1U)
39108 #define USART_ISR_FE_Msk                    (0x1UL << USART_ISR_FE_Pos)             /*!< 0x00000002 */
39109 #define USART_ISR_FE                        USART_ISR_FE_Msk                        /*!< Framing Error */
39110 #define USART_ISR_NE_Pos                    (2U)
39111 #define USART_ISR_NE_Msk                    (0x1UL << USART_ISR_NE_Pos)             /*!< 0x00000004 */
39112 #define USART_ISR_NE                        USART_ISR_NE_Msk                        /*!< Noise Error detection Flag */
39113 #define USART_ISR_ORE_Pos                   (3U)
39114 #define USART_ISR_ORE_Msk                   (0x1UL << USART_ISR_ORE_Pos)            /*!< 0x00000008 */
39115 #define USART_ISR_ORE                       USART_ISR_ORE_Msk                       /*!< OverRun Error */
39116 #define USART_ISR_IDLE_Pos                  (4U)
39117 #define USART_ISR_IDLE_Msk                  (0x1UL << USART_ISR_IDLE_Pos)           /*!< 0x00000010 */
39118 #define USART_ISR_IDLE                      USART_ISR_IDLE_Msk                      /*!< IDLE line detected */
39119 #define USART_ISR_RXNE_Pos                  (5U)
39120 #define USART_ISR_RXNE_Msk                  (0x1UL << USART_ISR_RXNE_Pos)           /*!< 0x00000020 */
39121 #define USART_ISR_RXNE                      USART_ISR_RXNE_Msk                      /*!< Read Data Register Not Empty */
39122 #define USART_ISR_RXNE_RXFNE_Pos            USART_ISR_RXNE_Pos
39123 #define USART_ISR_RXNE_RXFNE_Msk            USART_ISR_RXNE_Msk                      /*!< 0x00000020 */
39124 #define USART_ISR_RXNE_RXFNE                USART_ISR_RXNE_Msk                      /*!< Read Data Register or RX FIFO Not Empty */
39125 #define USART_ISR_TC_Pos                    (6U)
39126 #define USART_ISR_TC_Msk                    (0x1UL << USART_ISR_TC_Pos)             /*!< 0x00000040 */
39127 #define USART_ISR_TC                        USART_ISR_TC_Msk                        /*!< Transmission Complete */
39128 #define USART_ISR_TXE_Pos                   (7U)
39129 #define USART_ISR_TXE_Msk                   (0x1UL << USART_ISR_TXE_Pos)            /*!< 0x00000080 */
39130 #define USART_ISR_TXE                       USART_ISR_TXE_Msk                       /*!< Transmit Data Register Empty */
39131 #define USART_ISR_TXE_TXFNF_Pos             USART_ISR_TXE_Pos
39132 #define USART_ISR_TXE_TXFNF_Msk             USART_ISR_TXE_Msk                       /*!< 0x00000080 */
39133 #define USART_ISR_TXE_TXFNF                 USART_ISR_TXE_Msk                       /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
39134 #define USART_ISR_LBDF_Pos                  (8U)
39135 #define USART_ISR_LBDF_Msk                  (0x1UL << USART_ISR_LBDF_Pos)           /*!< 0x00000100 */
39136 #define USART_ISR_LBDF                      USART_ISR_LBDF_Msk                      /*!< LIN Break Detection Flag */
39137 #define USART_ISR_CTSIF_Pos                 (9U)
39138 #define USART_ISR_CTSIF_Msk                 (0x1UL << USART_ISR_CTSIF_Pos)          /*!< 0x00000200 */
39139 #define USART_ISR_CTSIF                     USART_ISR_CTSIF_Msk                     /*!< CTS interrupt Flag */
39140 #define USART_ISR_CTS_Pos                   (10U)
39141 #define USART_ISR_CTS_Msk                   (0x1UL << USART_ISR_CTS_Pos)            /*!< 0x00000400 */
39142 #define USART_ISR_CTS                       USART_ISR_CTS_Msk                       /*!< CTS Flag */
39143 #define USART_ISR_RTOF_Pos                  (11U)
39144 #define USART_ISR_RTOF_Msk                  (0x1UL << USART_ISR_RTOF_Pos)           /*!< 0x00000800 */
39145 #define USART_ISR_RTOF                      USART_ISR_RTOF_Msk                      /*!< Receiver Timeout */
39146 #define USART_ISR_EOBF_Pos                  (12U)
39147 #define USART_ISR_EOBF_Msk                  (0x1UL << USART_ISR_EOBF_Pos)           /*!< 0x00001000 */
39148 #define USART_ISR_EOBF                      USART_ISR_EOBF_Msk                      /*!< End Of Block Flag */
39149 #define USART_ISR_UDR_Pos                   (13U)
39150 #define USART_ISR_UDR_Msk                   (0x1UL << USART_ISR_UDR_Pos)            /*!< 0x00002000 */
39151 #define USART_ISR_UDR                       USART_ISR_UDR_Msk                       /*!< SPI Slave Underrun error Flag */
39152 #define USART_ISR_ABRE_Pos                  (14U)
39153 #define USART_ISR_ABRE_Msk                  (0x1UL << USART_ISR_ABRE_Pos)           /*!< 0x00004000 */
39154 #define USART_ISR_ABRE                      USART_ISR_ABRE_Msk                      /*!< Auto-Baud Rate Error */
39155 #define USART_ISR_ABRF_Pos                  (15U)
39156 #define USART_ISR_ABRF_Msk                  (0x1UL << USART_ISR_ABRF_Pos)           /*!< 0x00008000 */
39157 #define USART_ISR_ABRF                      USART_ISR_ABRF_Msk                      /*!< Auto-Baud Rate Flag */
39158 #define USART_ISR_BUSY_Pos                  (16U)
39159 #define USART_ISR_BUSY_Msk                  (0x1UL << USART_ISR_BUSY_Pos)           /*!< 0x00010000 */
39160 #define USART_ISR_BUSY                      USART_ISR_BUSY_Msk                      /*!< Busy Flag */
39161 #define USART_ISR_CMF_Pos                   (17U)
39162 #define USART_ISR_CMF_Msk                   (0x1UL << USART_ISR_CMF_Pos)            /*!< 0x00020000 */
39163 #define USART_ISR_CMF                       USART_ISR_CMF_Msk                       /*!< Character Match Flag */
39164 #define USART_ISR_SBKF_Pos                  (18U)
39165 #define USART_ISR_SBKF_Msk                  (0x1UL << USART_ISR_SBKF_Pos)           /*!< 0x00040000 */
39166 #define USART_ISR_SBKF                      USART_ISR_SBKF_Msk                      /*!< Send Break Flag */
39167 #define USART_ISR_RWU_Pos                   (19U)
39168 #define USART_ISR_RWU_Msk                   (0x1UL << USART_ISR_RWU_Pos)            /*!< 0x00080000 */
39169 #define USART_ISR_RWU                       USART_ISR_RWU_Msk                       /*!< Receive Wake Up from mute mode Flag */
39170 #define USART_ISR_WUF_Pos                   (20U)
39171 #define USART_ISR_WUF_Msk                   (0x1UL << USART_ISR_WUF_Pos)            /*!< 0x00100000 */
39172 #define USART_ISR_WUF                       USART_ISR_WUF_Msk                       /*!< Wake Up from low power mode Flag */
39173 #define USART_ISR_TEACK_Pos                 (21U)
39174 #define USART_ISR_TEACK_Msk                 (0x1UL << USART_ISR_TEACK_Pos)          /*!< 0x00200000 */
39175 #define USART_ISR_TEACK                     USART_ISR_TEACK_Msk                     /*!< Transmit Enable Acknowledge Flag */
39176 #define USART_ISR_REACK_Pos                 (22U)
39177 #define USART_ISR_REACK_Msk                 (0x1UL << USART_ISR_REACK_Pos)          /*!< 0x00400000 */
39178 #define USART_ISR_REACK                     USART_ISR_REACK_Msk                     /*!< Receive Enable Acknowledge Flag */
39179 #define USART_ISR_TXFE_Pos                  (23U)
39180 #define USART_ISR_TXFE_Msk                  (0x1UL << USART_ISR_TXFE_Pos)           /*!< 0x00800000 */
39181 #define USART_ISR_TXFE                      USART_ISR_TXFE_Msk                      /*!< TX FIFO Empty Flag */
39182 #define USART_ISR_RXFF_Pos                  (24U)
39183 #define USART_ISR_RXFF_Msk                  (0x1UL << USART_ISR_RXFF_Pos)           /*!< 0x01000000 */
39184 #define USART_ISR_RXFF                      USART_ISR_RXFF_Msk                      /*!< RX FIFO Full Flag */
39185 #define USART_ISR_TCBGT_Pos                 (25U)
39186 #define USART_ISR_TCBGT_Msk                 (0x1UL << USART_ISR_TCBGT_Pos)          /*!< 0x02000000 */
39187 #define USART_ISR_TCBGT                     USART_ISR_TCBGT_Msk                     /*!< Transmission Complete Before Guard Time completion */
39188 #define USART_ISR_RXFT_Pos                  (26U)
39189 #define USART_ISR_RXFT_Msk                  (0x1UL << USART_ISR_RXFT_Pos)           /*!< 0x04000000 */
39190 #define USART_ISR_RXFT                      USART_ISR_RXFT_Msk                      /*!< RX FIFO Threshold Flag */
39191 #define USART_ISR_TXFT_Pos                  (27U)
39192 #define USART_ISR_TXFT_Msk                 (0x1UL << USART_ISR_TXFT_Pos)           /*!< 0x08000000 */
39193 #define USART_ISR_TXFT                      USART_ISR_TXFT_Msk                      /*!< TX FIFO Threshold Flag */
39194 
39195 /*******************  Bit definition for USART_ICR register  ******************/
39196 #define USART_ICR_PECF_Pos                  (0U)
39197 #define USART_ICR_PECF_Msk                  (0x1UL << USART_ICR_PECF_Pos)           /*!< 0x00000001 */
39198 #define USART_ICR_PECF                      USART_ICR_PECF_Msk                      /*!< Parity Error Clear Flag */
39199 #define USART_ICR_FECF_Pos                  (1U)
39200 #define USART_ICR_FECF_Msk                  (0x1UL << USART_ICR_FECF_Pos)           /*!< 0x00000002 */
39201 #define USART_ICR_FECF                      USART_ICR_FECF_Msk                      /*!< Framing Error Clear Flag */
39202 #define USART_ICR_NECF_Pos                  (2U)
39203 #define USART_ICR_NECF_Msk                  (0x1UL << USART_ICR_NECF_Pos)           /*!< 0x00000004 */
39204 #define USART_ICR_NECF                      USART_ICR_NECF_Msk                      /*!< Noise Error detected Clear Flag */
39205 #define USART_ICR_ORECF_Pos                 (3U)
39206 #define USART_ICR_ORECF_Msk                 (0x1UL << USART_ICR_ORECF_Pos)          /*!< 0x00000008 */
39207 #define USART_ICR_ORECF                     USART_ICR_ORECF_Msk                     /*!< OverRun Error Clear Flag */
39208 #define USART_ICR_IDLECF_Pos                (4U)
39209 #define USART_ICR_IDLECF_Msk                (0x1UL << USART_ICR_IDLECF_Pos)         /*!< 0x00000010 */
39210 #define USART_ICR_IDLECF                    USART_ICR_IDLECF_Msk                    /*!< IDLE line detected Clear Flag */
39211 #define USART_ICR_TXFECF_Pos                (5U)
39212 #define USART_ICR_TXFECF_Msk                (0x1UL << USART_ICR_TXFECF_Pos)         /*!< 0x00000020 */
39213 #define USART_ICR_TXFECF                    USART_ICR_TXFECF_Msk                    /*!< TX FIFO Empty Clear Flag */
39214 #define USART_ICR_TCCF_Pos                  (6U)
39215 #define USART_ICR_TCCF_Msk                  (0x1UL << USART_ICR_TCCF_Pos)           /*!< 0x00000040 */
39216 #define USART_ICR_TCCF                      USART_ICR_TCCF_Msk                      /*!< Transmission Complete Clear Flag */
39217 #define USART_ICR_TCBGTCF_Pos               (7U)
39218 #define USART_ICR_TCBGTCF_Msk               (0x1UL << USART_ICR_TCBGTCF_Pos)        /*!< 0x00000080 */
39219 #define USART_ICR_TCBGTCF                   USART_ICR_TCBGTCF_Msk                   /*!< Transmission Complete Before Guard Time Clear Flag */
39220 #define USART_ICR_LBDCF_Pos                 (8U)
39221 #define USART_ICR_LBDCF_Msk                 (0x1UL << USART_ICR_LBDCF_Pos)          /*!< 0x00000100 */
39222 #define USART_ICR_LBDCF                     USART_ICR_LBDCF_Msk                     /*!< LIN Break Detection Clear Flag */
39223 #define USART_ICR_CTSCF_Pos                 (9U)
39224 #define USART_ICR_CTSCF_Msk                 (0x1UL << USART_ICR_CTSCF_Pos)          /*!< 0x00000200 */
39225 #define USART_ICR_CTSCF                     USART_ICR_CTSCF_Msk                     /*!< CTS Interrupt Clear Flag */
39226 #define USART_ICR_RTOCF_Pos                 (11U)
39227 #define USART_ICR_RTOCF_Msk                 (0x1UL << USART_ICR_RTOCF_Pos)          /*!< 0x00000800 */
39228 #define USART_ICR_RTOCF                     USART_ICR_RTOCF_Msk                     /*!< Receiver Time Out Clear Flag */
39229 #define USART_ICR_EOBCF_Pos                 (12U)
39230 #define USART_ICR_EOBCF_Msk                 (0x1UL << USART_ICR_EOBCF_Pos)          /*!< 0x00001000 */
39231 #define USART_ICR_EOBCF                     USART_ICR_EOBCF_Msk                     /*!< End Of Block Clear Flag */
39232 #define USART_ICR_UDRCF_Pos                 (13U)
39233 #define USART_ICR_UDRCF_Msk                 (0x1UL << USART_ICR_UDRCF_Pos)          /*!< 0x00002000 */
39234 #define USART_ICR_UDRCF                     USART_ICR_UDRCF_Msk                     /*!< SPI Slave Underrun Clear Flag */
39235 #define USART_ICR_CMCF_Pos                  (17U)
39236 #define USART_ICR_CMCF_Msk                  (0x1UL << USART_ICR_CMCF_Pos)           /*!< 0x00020000 */
39237 #define USART_ICR_CMCF                      USART_ICR_CMCF_Msk                      /*!< Character Match Clear Flag */
39238 #define USART_ICR_WUCF_Pos                  (20U)
39239 #define USART_ICR_WUCF_Msk                  (0x1UL << USART_ICR_WUCF_Pos)           /*!< 0x00100000 */
39240 #define USART_ICR_WUCF                      USART_ICR_WUCF_Msk                      /*!< Wake Up from stop mode Clear Flag */
39241 
39242 /*******************  Bit definition for USART_RDR register  ******************/
39243 #define USART_RDR_RDR                       ((uint16_t)0x01FF)                      /*!< RDR[8:0] bits (Receive Data value) */
39244 
39245 /*******************  Bit definition for USART_TDR register  ******************/
39246 #define USART_TDR_TDR                       ((uint16_t)0x01FF)                      /*!< TDR[8:0] bits (Transmit Data value) */
39247 
39248 /*******************  Bit definition for USART_PRESC register  ****************/
39249 #define USART_PRESC_PRESCALER_Pos           (0U)
39250 #define USART_PRESC_PRESCALER_Msk           (0xFUL << USART_PRESC_PRESCALER_Pos)    /*!< 0x0000000F */
39251 #define USART_PRESC_PRESCALER               USART_PRESC_PRESCALER_Msk               /*!< PRESCALER[3:0] bits (Clock prescaler) */
39252 #define USART_PRESC_PRESCALER_0             (0x1UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000001 */
39253 #define USART_PRESC_PRESCALER_1             (0x2UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000002 */
39254 #define USART_PRESC_PRESCALER_2             (0x4UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000004 */
39255 #define USART_PRESC_PRESCALER_3             (0x8UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000008 */
39256 
39257 
39258 /******************************************************************************/
39259 /*                                                                            */
39260 /*                                       USB_OTG                              */
39261 /*                                                                            */
39262 /******************************************************************************/
39263 /********************  Bit definition for USB_OTG_GOTGCTL register  ********************/
39264 #define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)
39265 #define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
39266 #define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */
39267 #define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)
39268 #define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
39269 #define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
39270 #define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)
39271 #define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
39272 #define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */
39273 #define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)
39274 #define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
39275 #define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */
39276 #define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)
39277 #define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
39278 #define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */
39279 #define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)
39280 #define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
39281 #define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */
39282 #define USB_OTG_GOTGCTL_EHEN_Pos                 (12U)
39283 #define USB_OTG_GOTGCTL_EHEN_Msk                 (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
39284 #define USB_OTG_GOTGCTL_EHEN                     USB_OTG_GOTGCTL_EHEN_Msk      /*!< Embedded host enable */
39285 #define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)
39286 #define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
39287 #define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */
39288 #define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)
39289 #define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
39290 #define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */
39291 #define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)
39292 #define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
39293 #define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */
39294 #define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)
39295 #define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
39296 #define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!< B-session valid */
39297 #define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)
39298 #define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
39299 #define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */
39300 #define USB_OTG_GOTGCTL_CURMOD_Pos               (21U)
39301 #define USB_OTG_GOTGCTL_CURMOD_Msk               (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
39302 #define USB_OTG_GOTGCTL_CURMOD                   USB_OTG_GOTGCTL_CURMOD_Msk    /*!< Current mode of operation */
39303 
39304 /********************  Bit definition for USB_OTG_HCFG register  ********************/
39305 
39306 #define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)
39307 #define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
39308 #define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */
39309 #define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
39310 #define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
39311 #define USB_OTG_HCFG_FSLSS_Pos                   (2U)
39312 #define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
39313 #define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */
39314 
39315 /********************  Bit definition for USB_OTG_DCFG register  ********************/
39316 
39317 #define USB_OTG_DCFG_DSPD_Pos                    (0U)
39318 #define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
39319 #define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */
39320 #define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
39321 #define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
39322 #define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)
39323 #define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
39324 #define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */
39325 
39326 #define USB_OTG_DCFG_DAD_Pos                     (4U)
39327 #define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
39328 #define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk             /*!< Device address */
39329 #define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
39330 #define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
39331 #define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
39332 #define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
39333 #define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
39334 #define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
39335 #define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
39336 
39337 #define USB_OTG_DCFG_PFIVL_Pos                   (11U)
39338 #define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
39339 #define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk            /*!< Periodic (micro)frame interval */
39340 #define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
39341 #define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
39342 
39343 #define USB_OTG_DCFG_ERRATIM_Pos                 (15U)
39344 #define USB_OTG_DCFG_ERRATIM_Msk                 (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
39345 #define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk            /*!< Erratic error interrupt mask */
39346 
39347 #define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)
39348 #define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
39349 #define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk            /*!< Periodic scheduling interval */
39350 #define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
39351 #define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
39352 
39353 /********************  Bit definition for USB_OTG_PCGCR register  ********************/
39354 #define USB_OTG_PCGCR_STPPCLK_Pos                (0U)
39355 #define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
39356 #define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */
39357 #define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)
39358 #define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
39359 #define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */
39360 #define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)
39361 #define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
39362 #define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */
39363 
39364 /********************  Bit definition for USB_OTG_GOTGINT register  ********************/
39365 #define USB_OTG_GOTGINT_SEDET_Pos                (2U)
39366 #define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
39367 #define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */
39368 #define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)
39369 #define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
39370 #define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */
39371 #define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)
39372 #define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
39373 #define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */
39374 #define USB_OTG_GOTGINT_HNGDET_Pos               (17U)
39375 #define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
39376 #define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */
39377 #define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)
39378 #define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
39379 #define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */
39380 #define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)
39381 #define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
39382 #define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */
39383 
39384 /********************  Bit definition for USB_OTG_DCTL register  ********************/
39385 #define USB_OTG_DCTL_RWUSIG_Pos                  (0U)
39386 #define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
39387 #define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */
39388 #define USB_OTG_DCTL_SDIS_Pos                    (1U)
39389 #define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
39390 #define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */
39391 #define USB_OTG_DCTL_GINSTS_Pos                  (2U)
39392 #define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
39393 #define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */
39394 #define USB_OTG_DCTL_GONSTS_Pos                  (3U)
39395 #define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
39396 #define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */
39397 
39398 #define USB_OTG_DCTL_TCTL_Pos                    (4U)
39399 #define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
39400 #define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */
39401 #define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
39402 #define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
39403 #define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
39404 #define USB_OTG_DCTL_SGINAK_Pos                  (7U)
39405 #define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
39406 #define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */
39407 #define USB_OTG_DCTL_CGINAK_Pos                  (8U)
39408 #define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
39409 #define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */
39410 #define USB_OTG_DCTL_SGONAK_Pos                  (9U)
39411 #define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
39412 #define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */
39413 #define USB_OTG_DCTL_CGONAK_Pos                  (10U)
39414 #define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
39415 #define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */
39416 #define USB_OTG_DCTL_POPRGDNE_Pos                (11U)
39417 #define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
39418 #define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
39419 #define USB_OTG_DCTL_DSBESLRJCT_Pos              (18U)
39420 #define USB_OTG_DCTL_DSBESLRJCT_Msk              (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
39421 #define USB_OTG_DCTL_DSBESLRJCT                  USB_OTG_DCTL_DSBESLRJCT_Msk  /*!< Deep sleep BESL reject */
39422 
39423 /********************  Bit definition for USB_OTG_HFIR register  ********************/
39424 #define USB_OTG_HFIR_FRIVL_Pos                   (0U)
39425 #define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
39426 #define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */
39427 
39428 /********************  Bit definition for USB_OTG_HFNUM register  ********************/
39429 #define USB_OTG_HFNUM_FRNUM_Pos                  (0U)
39430 #define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
39431 #define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */
39432 #define USB_OTG_HFNUM_FTREM_Pos                  (16U)
39433 #define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
39434 #define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */
39435 
39436 /********************  Bit definition for USB_OTG_DSTS register  ********************/
39437 #define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)
39438 #define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
39439 #define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */
39440 
39441 #define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)
39442 #define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
39443 #define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */
39444 #define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
39445 #define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
39446 #define USB_OTG_DSTS_EERR_Pos                    (3U)
39447 #define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
39448 #define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */
39449 #define USB_OTG_DSTS_FNSOF_Pos                   (8U)
39450 #define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
39451 #define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */
39452 
39453 /********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
39454 #define USB_OTG_GAHBCFG_GINT_Pos                 (0U)
39455 #define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
39456 #define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */
39457 
39458 #define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)
39459 #define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
39460 #define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */
39461 #define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
39462 #define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
39463 #define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
39464 #define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
39465 #define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
39466 #define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)
39467 #define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
39468 #define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */
39469 #define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)
39470 #define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
39471 #define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */
39472 #define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)
39473 #define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
39474 #define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */
39475 
39476 /********************  Bit definition for USB_OTG_GUSBCFG register  ********************/
39477 #define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)
39478 #define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
39479 #define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */
39480 #define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
39481 #define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
39482 #define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
39483 #define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)
39484 #define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
39485 #define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
39486 #define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)
39487 #define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
39488 #define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */
39489 #define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)
39490 #define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
39491 #define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */
39492 
39493 #define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)
39494 #define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
39495 #define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */
39496 #define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
39497 #define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
39498 #define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
39499 #define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
39500 #define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)
39501 #define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
39502 #define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */
39503 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)
39504 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
39505 #define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */
39506 #define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)
39507 #define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
39508 #define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */
39509 #define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)
39510 #define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
39511 #define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */
39512 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)
39513 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
39514 #define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */
39515 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)
39516 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
39517 #define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */
39518 #define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)
39519 #define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
39520 #define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */
39521 #define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)
39522 #define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
39523 #define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */
39524 #define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)
39525 #define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
39526 #define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */
39527 #define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)
39528 #define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
39529 #define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */
39530 #define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)
39531 #define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
39532 #define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */
39533 #define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)
39534 #define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
39535 #define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
39536 #define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)
39537 #define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
39538 #define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
39539 
39540 /********************  Bit definition for USB_OTG_GRSTCTL register  ********************/
39541 #define USB_OTG_GRSTCTL_CSRST_Pos                (0U)
39542 #define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
39543 #define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */
39544 #define USB_OTG_GRSTCTL_HSRST_Pos                (1U)
39545 #define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
39546 #define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */
39547 #define USB_OTG_GRSTCTL_FCRST_Pos                (2U)
39548 #define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
39549 #define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */
39550 #define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)
39551 #define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
39552 #define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */
39553 #define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)
39554 #define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
39555 #define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */
39556 
39557 #define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)
39558 #define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
39559 #define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */
39560 #define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
39561 #define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
39562 #define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
39563 #define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
39564 #define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
39565 #define USB_OTG_GRSTCTL_CSRSTDONE_Pos            (29U)
39566 #define USB_OTG_GRSTCTL_CSRSTDONE_Msk            (0x1UL << USB_OTG_GRSTCTL_CSRSTDONE_Pos) /*!< 0x20000000 */
39567 #define USB_OTG_GRSTCTL_CSRSTDONE                USB_OTG_GRSTCTL_CSRSTDONE_Msk   /*!< Core soft reset done            */
39568 #define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)
39569 #define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
39570 #define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */
39571 #define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)
39572 #define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
39573 #define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */
39574 
39575 /********************  Bit definition for USB_OTG_DIEPMSK register  ********************/
39576 #define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)
39577 #define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
39578 #define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */
39579 #define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)
39580 #define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
39581 #define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */
39582 #define USB_OTG_DIEPMSK_TOM_Pos                  (3U)
39583 #define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
39584 #define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */
39585 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)
39586 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
39587 #define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
39588 #define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)
39589 #define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
39590 #define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */
39591 #define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)
39592 #define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
39593 #define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */
39594 #define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)
39595 #define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
39596 #define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */
39597 #define USB_OTG_DIEPMSK_BIM_Pos                  (9U)
39598 #define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
39599 #define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */
39600 
39601 /********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
39602 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)
39603 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
39604 #define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */
39605 
39606 #define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)
39607 #define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
39608 #define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */
39609 #define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
39610 #define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
39611 #define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
39612 #define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
39613 #define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
39614 #define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
39615 #define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
39616 #define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
39617 
39618 #define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)
39619 #define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
39620 #define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */
39621 #define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
39622 #define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
39623 #define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
39624 #define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
39625 #define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
39626 #define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
39627 #define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
39628 #define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
39629 
39630 /********************  Bit definition for USB_OTG_HAINT register  ********************/
39631 #define USB_OTG_HAINT_HAINT_Pos                  (0U)
39632 #define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
39633 #define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */
39634 
39635 /********************  Bit definition for USB_OTG_DOEPMSK register  ********************/
39636 #define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)
39637 #define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
39638 #define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */
39639 #define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)
39640 #define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
39641 #define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */
39642 #define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)
39643 #define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
39644 #define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk      /*!< OUT transaction AHB Error interrupt mask               */
39645 #define USB_OTG_DOEPMSK_STUPM_Pos                (3U)
39646 #define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
39647 #define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */
39648 #define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)
39649 #define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
39650 #define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */
39651 #define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)
39652 #define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
39653 #define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */
39654 #define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)
39655 #define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
39656 #define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */
39657 #define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)
39658 #define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
39659 #define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */
39660 #define USB_OTG_DOEPMSK_BERRM_Pos                (12U)
39661 #define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
39662 #define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask               */
39663 #define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)
39664 #define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
39665 #define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask               */
39666 #define USB_OTG_DOEPMSK_NYETM_Pos                (14U)
39667 #define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
39668 #define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk      /*!< NYET interrupt mask                */
39669 
39670 /********************  Bit definition for USB_OTG_GINTSTS register  ********************/
39671 #define USB_OTG_GINTSTS_CMOD_Pos                 (0U)
39672 #define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
39673 #define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */
39674 #define USB_OTG_GINTSTS_MMIS_Pos                 (1U)
39675 #define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
39676 #define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */
39677 #define USB_OTG_GINTSTS_OTGINT_Pos               (2U)
39678 #define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
39679 #define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */
39680 #define USB_OTG_GINTSTS_SOF_Pos                  (3U)
39681 #define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
39682 #define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */
39683 #define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)
39684 #define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
39685 #define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */
39686 #define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)
39687 #define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
39688 #define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */
39689 #define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)
39690 #define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
39691 #define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */
39692 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)
39693 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
39694 #define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */
39695 #define USB_OTG_GINTSTS_ESUSP_Pos                (10U)
39696 #define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
39697 #define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */
39698 #define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)
39699 #define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
39700 #define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */
39701 #define USB_OTG_GINTSTS_USBRST_Pos               (12U)
39702 #define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
39703 #define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */
39704 #define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)
39705 #define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
39706 #define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */
39707 #define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)
39708 #define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
39709 #define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */
39710 #define USB_OTG_GINTSTS_EOPF_Pos                 (15U)
39711 #define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
39712 #define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */
39713 #define USB_OTG_GINTSTS_IEPINT_Pos               (18U)
39714 #define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
39715 #define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */
39716 #define USB_OTG_GINTSTS_OEPINT_Pos               (19U)
39717 #define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
39718 #define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */
39719 #define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)
39720 #define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
39721 #define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */
39722 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)
39723 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
39724 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */
39725 #define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)
39726 #define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
39727 #define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */
39728 #define USB_OTG_GINTSTS_RSTDET_Pos               (23U)
39729 #define USB_OTG_GINTSTS_RSTDET_Msk               (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
39730 #define USB_OTG_GINTSTS_RSTDET                   USB_OTG_GINTSTS_RSTDET_Msk    /*!< Reset detected interrupt                       */
39731 #define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)
39732 #define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
39733 #define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */
39734 #define USB_OTG_GINTSTS_HCINT_Pos                (25U)
39735 #define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
39736 #define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */
39737 #define USB_OTG_GINTSTS_PTXFE_Pos                (26U)
39738 #define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
39739 #define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */
39740 #define USB_OTG_GINTSTS_LPMINT_Pos               (27U)
39741 #define USB_OTG_GINTSTS_LPMINT_Msk               (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
39742 #define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt                                  */
39743 #define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)
39744 #define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
39745 #define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */
39746 #define USB_OTG_GINTSTS_DISCINT_Pos              (29U)
39747 #define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
39748 #define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */
39749 #define USB_OTG_GINTSTS_SRQINT_Pos               (30U)
39750 #define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
39751 #define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */
39752 #define USB_OTG_GINTSTS_WKUINT_Pos               (31U)
39753 #define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
39754 #define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */
39755 
39756 /********************  Bit definition for USB_OTG_GINTMSK register  ********************/
39757 #define USB_OTG_GINTMSK_MMISM_Pos                (1U)
39758 #define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
39759 #define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */
39760 #define USB_OTG_GINTMSK_OTGINT_Pos               (2U)
39761 #define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
39762 #define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */
39763 #define USB_OTG_GINTMSK_SOFM_Pos                 (3U)
39764 #define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
39765 #define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */
39766 #define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)
39767 #define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
39768 #define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */
39769 #define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)
39770 #define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
39771 #define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */
39772 #define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)
39773 #define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
39774 #define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */
39775 #define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)
39776 #define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
39777 #define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */
39778 #define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)
39779 #define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
39780 #define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */
39781 #define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)
39782 #define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
39783 #define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */
39784 #define USB_OTG_GINTMSK_USBRST_Pos               (12U)
39785 #define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
39786 #define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */
39787 #define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)
39788 #define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
39789 #define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */
39790 #define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)
39791 #define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
39792 #define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */
39793 #define USB_OTG_GINTMSK_EOPFM_Pos                (15U)
39794 #define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
39795 #define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */
39796 #define USB_OTG_GINTMSK_EPMISM_Pos               (17U)
39797 #define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
39798 #define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */
39799 #define USB_OTG_GINTMSK_IEPINT_Pos               (18U)
39800 #define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
39801 #define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */
39802 #define USB_OTG_GINTMSK_OEPINT_Pos               (19U)
39803 #define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
39804 #define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */
39805 #define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)
39806 #define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
39807 #define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */
39808 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)
39809 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
39810 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */
39811 #define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)
39812 #define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
39813 #define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */
39814 #define USB_OTG_GINTMSK_RSTDEM_Pos               (23U)
39815 #define USB_OTG_GINTMSK_RSTDEM_Msk               (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */
39816 #define USB_OTG_GINTMSK_RSTDEM                   USB_OTG_GINTMSK_RSTDEM_Msk    /*!< Reset detected interrupt mask                      */
39817 #define USB_OTG_GINTMSK_PRTIM_Pos                (24U)
39818 #define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
39819 #define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */
39820 #define USB_OTG_GINTMSK_HCIM_Pos                 (25U)
39821 #define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
39822 #define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */
39823 #define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)
39824 #define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
39825 #define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */
39826 #define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)
39827 #define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
39828 #define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask                                  */
39829 #define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)
39830 #define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
39831 #define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */
39832 #define USB_OTG_GINTMSK_DISCINT_Pos              (29U)
39833 #define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
39834 #define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */
39835 #define USB_OTG_GINTMSK_SRQIM_Pos                (30U)
39836 #define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
39837 #define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */
39838 #define USB_OTG_GINTMSK_WUIM_Pos                 (31U)
39839 #define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
39840 #define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */
39841 
39842 /********************  Bit definition for USB_OTG_DAINT register  ********************/
39843 #define USB_OTG_DAINT_IEPINT_Pos                 (0U)
39844 #define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
39845 #define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */
39846 #define USB_OTG_DAINT_OEPINT_Pos                 (16U)
39847 #define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
39848 #define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */
39849 
39850 /********************  Bit definition for USB_OTG_HAINTMSK register  ********************/
39851 #define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)
39852 #define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
39853 #define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */
39854 
39855 /********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
39856 #define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)
39857 #define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
39858 #define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */
39859 #define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)
39860 #define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
39861 #define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */
39862 #define USB_OTG_GRXSTSP_DPID_Pos                 (15U)
39863 #define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
39864 #define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */
39865 #define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)
39866 #define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
39867 #define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */
39868 
39869 /********************  Bit definition for USB_OTG_DAINTMSK register  ********************/
39870 #define USB_OTG_DAINTMSK_IEPM_Pos                (0U)
39871 #define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
39872 #define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */
39873 #define USB_OTG_DAINTMSK_OEPM_Pos                (16U)
39874 #define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
39875 #define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */
39876 
39877 /********************  Bit definition for OTG register  ********************/
39878 #define USB_OTG_CHNUM_Pos                        (0U)
39879 #define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)  /*!< 0x0000000F */
39880 #define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */
39881 #define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */
39882 #define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */
39883 #define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */
39884 #define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */
39885 #define USB_OTG_BCNT_Pos                         (4U)
39886 #define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
39887 #define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */
39888 
39889 #define USB_OTG_DPID_Pos                         (15U)
39890 #define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)   /*!< 0x00018000 */
39891 #define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */
39892 #define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */
39893 #define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */
39894 
39895 #define USB_OTG_PKTSTS_Pos                       (17U)
39896 #define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
39897 #define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */
39898 #define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */
39899 #define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */
39900 #define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */
39901 #define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */
39902 
39903 #define USB_OTG_EPNUM_Pos                        (0U)
39904 #define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)  /*!< 0x0000000F */
39905 #define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */
39906 #define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */
39907 #define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */
39908 #define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */
39909 #define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */
39910 
39911 #define USB_OTG_FRMNUM_Pos                       (21U)
39912 #define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
39913 #define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */
39914 #define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */
39915 #define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */
39916 #define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */
39917 #define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */
39918 
39919 /********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/
39920 #define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)
39921 #define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
39922 #define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */
39923 
39924 /********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/
39925 #define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)
39926 #define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
39927 #define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */
39928 
39929 /********************  Bit definition for OTG register  ********************/
39930 #define USB_OTG_NPTXFSA_Pos                      (0U)
39931 #define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
39932 #define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */
39933 #define USB_OTG_NPTXFD_Pos                       (16U)
39934 #define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
39935 #define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */
39936 #define USB_OTG_TX0FSA_Pos                       (0U)
39937 #define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
39938 #define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */
39939 #define USB_OTG_TX0FD_Pos                        (16U)
39940 #define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
39941 #define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */
39942 
39943 /********************  Bit definition for USB_OTG_DVBUSPULSE register  ********************/
39944 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)
39945 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
39946 #define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
39947 
39948 /********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/
39949 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)
39950 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
39951 #define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
39952 
39953 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)
39954 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
39955 #define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
39956 #define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
39957 #define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
39958 #define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
39959 #define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
39960 #define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
39961 #define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
39962 #define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
39963 #define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
39964 
39965 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)
39966 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
39967 #define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
39968 #define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
39969 #define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
39970 #define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
39971 #define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
39972 #define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
39973 #define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
39974 #define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
39975 
39976 /********************  Bit definition for USB_OTG_DTHRCTL register  ********************/
39977 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)
39978 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
39979 #define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
39980 #define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)
39981 #define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
39982 #define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */
39983 
39984 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)
39985 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
39986 #define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */
39987 #define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
39988 #define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
39989 #define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
39990 #define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
39991 #define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
39992 #define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
39993 #define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
39994 #define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
39995 #define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
39996 #define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)
39997 #define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
39998 #define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */
39999 
40000 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)
40001 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
40002 #define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */
40003 #define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
40004 #define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
40005 #define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
40006 #define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
40007 #define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
40008 #define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
40009 #define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
40010 #define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
40011 #define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
40012 #define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)
40013 #define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
40014 #define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */
40015 
40016 /********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/
40017 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)
40018 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
40019 #define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
40020 
40021 /********************  Bit definition for USB_OTG_DEACHINT register  ********************/
40022 #define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)
40023 #define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
40024 #define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */
40025 #define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)
40026 #define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
40027 #define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */
40028 
40029 /********************  Bit definition for USB_OTG_HS_GCCFG register  ********************/
40030 #define USB_OTG_GCCFG_CHGDET_Pos                 (0U)
40031 #define USB_OTG_GCCFG_CHGDET_Msk                 (0x1U << USB_OTG_GCCFG_CHGDET_Pos)           /*!< 0x00000001 */
40032 #define USB_OTG_GCCFG_CHGDET                     USB_OTG_GCCFG_CHGDET_Msk                     /*!< Battery Charger Detection */
40033 #define USB_OTG_GCCFG_FSVPLUS_Pos                (1U)
40034 #define USB_OTG_GCCFG_FSVPLUS_Msk                (0x1U << USB_OTG_GCCFG_FSVPLUS_Pos)          /*!< 0x00000002 */
40035 #define USB_OTG_GCCFG_FSVPLUS                    USB_OTG_GCCFG_FSVPLUS_Msk                    /*!< Single-Ended DP2 indicator DP voltage level  */
40036 #define USB_OTG_GCCFG_FSVMINUS_Pos               (2U)
40037 #define USB_OTG_GCCFG_FSVMINUS_Msk               0x1U << USB_OTG_GCCFG_FSVMINUS_Pos)         /*!< 0x00000004 */
40038 #define USB_OTG_GCCFG_FSVMINUS                   USB_OTG_GCCFG_FSVMINUS_Msk                  /*!< Single-Ended DM2 indicator DM voltage level  */
40039 #define USB_OTG_GCCFG_SESSVLD_Pos                (3U)
40040 #define USB_OTG_GCCFG_SESSVLD_Msk                (0x1U << USB_OTG_GCCFG_SESSVLD_Pos)          /*!< 0x00000008 */
40041 #define USB_OTG_GCCFG_SESSVLD                    USB_OTG_GCCFG_SESSVLD_Msk                    /*!< VBUS session valid indicator: Vbus is above VBUS session threshold.  */
40042 #define USB_OTG_GCCFG_VBUSVLD_Pos                (4U)
40043 #define USB_OTG_GCCFG_VBUSVLD_Msk                (0x1U << USB_OTG_GCCFG_VBUSVLD_Pos)          /*!< 0x00000010 */
40044 #define USB_OTG_GCCFG_VBUSVLD                    USB_OTG_GCCFG_VBUSVLD_Msk                    /*!< VBUS session valid indicator: VBUS is above VBUS valid threshold.  */
40045 #define USB_OTG_GCCFG_H_CDPEN_Pos                (16U)
40046 #define USB_OTG_GCCFG_H_CDPEN_Msk                (0x1U << USB_OTG_GCCFG_H_CDPEN_Pos)          /*!< 0x00010000 */
40047 #define USB_OTG_GCCFG_H_CDPEN                    USB_OTG_GCCFG_H_CDPEN_Msk                    /*!< VBUS session valid indicator Vbus voltage level  */
40048 #define USB_OTG_GCCFG_H_CDPDETEN_Pos             (17U)
40049 #define USB_OTG_GCCFG_H_CDPDETEN_Msk             (0x1U << USB_OTG_GCCFG_H_CDPDETEN_Pos)       /*!< 0x00020000 */
40050 #define USB_OTG_GCCFG_H_CDPDETEN                 USB_OTG_GCCFG_H_CDPDETEN_Msk                 /*!< Enable of voltage detector on DP for CDP port  */
40051 #define USB_OTG_GCCFG_H_VDMSRCEN_Pos             (18U)
40052 #define USB_OTG_GCCFG_H_VDMSRCEN_Msk             (0x1U << USB_OTG_GCCFG_H_VDMSRCEN_Pos)       /*!< 0x00040000 */
40053 #define USB_OTG_GCCFG_H_VDMSRCEN                 USB_OTG_GCCFG_H_VDMSRCEN_Msk                 /*!< Enable Voltage source on DM for CDP port */
40054 #define USB_OTG_GCCFG_DCDETEN_Pos                (19U)
40055 #define USB_OTG_GCCFG_DCDETEN_Msk                (0x1U << USB_OTG_GCCFG_DCDETEN_Pos)          /*!< 0x00080000 */
40056 #define USB_OTG_GCCFG_DCDETEN                    USB_OTG_GCCFG_DCDETEN_Msk                    /*!< Data contact detection (DCD) mode enable */
40057 #define USB_OTG_GCCFG_PDETEN_Pos                 (20U)
40058 #define USB_OTG_GCCFG_PDETEN_Msk                 (0x1U << USB_OTG_GCCFG_PDETEN_Pos)           /*!< 0x00080000 */
40059 #define USB_OTG_GCCFG_PDETEN                     USB_OTG_GCCFG_PDETEN_Msk                     /*!< Primary detection (PD) mode enable */
40060 #define USB_OTG_GCCFG_SDETEN_Pos                 (22U)
40061 #define USB_OTG_GCCFG_SDETEN_Msk                 (0x1U << USB_OTG_GCCFG_SDETEN_Pos)           /*!< 0x00400000 */
40062 #define USB_OTG_GCCFG_SDETEN                     USB_OTG_GCCFG_SDETEN_Msk                     /*!< Secondary detection (PD) mode enable */
40063 #define USB_OTG_GCCFG_VBVALOVAL_Pos              (23U)
40064 #define USB_OTG_GCCFG_VBVALOVAL_Msk              (0x1U << USB_OTG_GCCFG_VBVALOVAL_Pos)        /*!< 0x00800000 */
40065 #define USB_OTG_GCCFG_VBVALOVAL                  USB_OTG_GCCFG_VBVALOVAL_Msk                  /*!< Value of VBUSVLDEXT0 PHY input */
40066 #define USB_OTG_GCCFG_VBVALEXTOEN_Pos            (24U)
40067 #define USB_OTG_GCCFG_VBVALEXTOEN_Msk            (0x1U << USB_OTG_GCCFG_VBVALEXTOEN_Pos)      /*!< 0x01000000 */
40068 #define USB_OTG_GCCFG_VBVALEXTOEN                USB_OTG_GCCFG_VBVALEXTOEN_Msk                /*!< Enables of VBUSVLDEXT0 PHY input override */
40069 #define USB_OTG_GCCFG_PULLDOWNEN_Pos             (25U)
40070 #define USB_OTG_GCCFG_PULLDOWNEN_Msk             (0x1U << USB_OTG_GCCFG_PULLDOWNEN_Pos)       /*!< 0x02000000 */
40071 #define USB_OTG_GCCFG_PULLDOWNEN                 USB_OTG_GCCFG_PULLDOWNEN_Msk                 /*!< Enables Host pulldown resistors, used when ID PAD is disabled */
40072 #define USB_OTG_GCCFG_FORCEBCMODE_Pos            (26U)
40073 #define USB_OTG_GCCFG_FORCEBCMODE_Msk            (0x1U << USB_OTG_GCCFG_FORCEBCMODE_Pos)      /*!< 0x04000000 */
40074 #define USB_OTG_GCCFG_FORCEBCMODE                USB_OTG_GCCFG_FORCEBCMODE_Msk                /*!< Force Battery charging (BC) mode */
40075 #define USB_OTG_GCCFG_IDPULLUP_DIS_Pos           (28U)
40076 #define USB_OTG_GCCFG_IDPULLUP_DIS_Msk           (0x1U << USB_OTG_GCCFG_IDPULLUP_DIS_Pos)      /*!< 0x10000000 */
40077 #define USB_OTG_GCCFG_IDPULLUP_DIS               USB_OTG_GCCFG_IDPULLUP_DIS_Msk                /*!< Analog ID Input Sample Disable: disable sampling on the analog ID line */
40078 
40079 /********************  Bit definition for USB_OTG_GPWRDN) register  ********************/
40080 #define USB_OTG_GPWRDN_ADPMEN_Pos                (0U)
40081 #define USB_OTG_GPWRDN_ADPMEN_Msk                (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */
40082 #define USB_OTG_GPWRDN_ADPMEN                    USB_OTG_GPWRDN_ADPMEN_Msk     /*!< ADP module enable */
40083 #define USB_OTG_GPWRDN_ADPIF_Pos                 (23U)
40084 #define USB_OTG_GPWRDN_ADPIF_Msk                 (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */
40085 #define USB_OTG_GPWRDN_ADPIF                     USB_OTG_GPWRDN_ADPIF_Msk      /*!< ADP Interrupt flag */
40086 
40087 /********************  Bit definition for USB_OTG_DEACHINTMSK register  ********************/
40088 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)
40089 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
40090 #define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */
40091 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)
40092 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
40093 #define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
40094 
40095 /********************  Bit definition for USB_OTG_CID register  ********************/
40096 #define USB_OTG_CID_PRODUCT_ID_Pos               (0U)
40097 #define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
40098 #define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */
40099 
40100 /********************  Bit definition for USB_OTG_GLPMCFG register  ********************/
40101 #define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)
40102 #define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
40103 #define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /*!< LPM support enable                                     */
40104 #define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)
40105 #define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
40106 #define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /*!< LPM Token acknowledge enable                           */
40107 #define USB_OTG_GLPMCFG_BESL_Pos                 (2U)
40108 #define USB_OTG_GLPMCFG_BESL_Msk                 (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
40109 #define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /*!< BESL value received with last ACKed LPM Token          */
40110 #define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)
40111 #define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
40112 #define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /*!< bRemoteWake value received with last ACKed LPM Token   */
40113 #define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)
40114 #define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
40115 #define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /*!< L1 shallow sleep enable                                */
40116 #define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)
40117 #define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
40118 #define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /*!< BESL threshold                                         */
40119 #define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)
40120 #define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
40121 #define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /*!< L1 deep sleep enable                                   */
40122 #define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)
40123 #define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
40124 #define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /*!< LPM response                                           */
40125 #define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)
40126 #define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
40127 #define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /*!< Port sleep status                                      */
40128 #define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)
40129 #define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
40130 #define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk   /*!< Sleep State Resume OK                                  */
40131 #define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)
40132 #define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
40133 #define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /*!< LPM Channel Index                                      */
40134 #define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)
40135 #define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
40136 #define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /*!< LPM retry count                                        */
40137 #define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)
40138 #define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
40139 #define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /*!< Send LPM transaction                                   */
40140 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)
40141 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
40142 #define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status                                 */
40143 #define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)
40144 #define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
40145 #define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /*!< Enable best effort service latency                     */
40146 
40147 /********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/
40148 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)
40149 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
40150 #define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */
40151 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)
40152 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
40153 #define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */
40154 #define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)
40155 #define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
40156 #define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */
40157 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)
40158 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
40159 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
40160 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)
40161 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
40162 #define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */
40163 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)
40164 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
40165 #define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */
40166 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)
40167 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
40168 #define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
40169 #define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)
40170 #define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
40171 #define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */
40172 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)
40173 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
40174 #define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
40175 
40176 /********************  Bit definition for USB_OTG_HPRT register  ********************/
40177 #define USB_OTG_HPRT_PCSTS_Pos                   (0U)
40178 #define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
40179 #define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */
40180 #define USB_OTG_HPRT_PCDET_Pos                   (1U)
40181 #define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
40182 #define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */
40183 #define USB_OTG_HPRT_PENA_Pos                    (2U)
40184 #define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
40185 #define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */
40186 #define USB_OTG_HPRT_PENCHNG_Pos                 (3U)
40187 #define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
40188 #define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */
40189 #define USB_OTG_HPRT_POCA_Pos                    (4U)
40190 #define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
40191 #define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */
40192 #define USB_OTG_HPRT_POCCHNG_Pos                 (5U)
40193 #define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
40194 #define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */
40195 #define USB_OTG_HPRT_PRES_Pos                    (6U)
40196 #define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
40197 #define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume   */
40198 #define USB_OTG_HPRT_PSUSP_Pos                   (7U)
40199 #define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
40200 #define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend  */
40201 #define USB_OTG_HPRT_PRST_Pos                    (8U)
40202 #define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
40203 #define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset    */
40204 
40205 #define USB_OTG_HPRT_PLSTS_Pos                   (10U)
40206 #define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
40207 #define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status */
40208 #define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
40209 #define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
40210 #define USB_OTG_HPRT_PPWR_Pos                    (12U)
40211 #define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
40212 #define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power */
40213 
40214 #define USB_OTG_HPRT_PTCTL_Pos                   (13U)
40215 #define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
40216 #define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control */
40217 #define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
40218 #define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
40219 #define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
40220 #define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
40221 
40222 #define USB_OTG_HPRT_PSPD_Pos                    (17U)
40223 #define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
40224 #define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed */
40225 #define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
40226 #define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
40227 
40228 /********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/
40229 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)
40230 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
40231 #define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
40232 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)
40233 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
40234 #define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
40235 #define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)
40236 #define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
40237 #define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask */
40238 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)
40239 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
40240 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
40241 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)
40242 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
40243 #define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
40244 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)
40245 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
40246 #define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
40247 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)
40248 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
40249 #define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
40250 #define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)
40251 #define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
40252 #define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */
40253 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)
40254 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
40255 #define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
40256 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)
40257 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
40258 #define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
40259 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)
40260 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
40261 #define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
40262 
40263 /********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/
40264 #define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)
40265 #define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
40266 #define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address */
40267 #define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)
40268 #define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
40269 #define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth */
40270 
40271 /********************  Bit definition for USB_OTG_DIEPCTL register  ********************/
40272 #define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)
40273 #define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
40274 #define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size */
40275 #define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)
40276 #define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
40277 #define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint */
40278 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)
40279 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
40280 #define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
40281 #define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)
40282 #define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
40283 #define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status */
40284 
40285 #define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)
40286 #define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
40287 #define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type */
40288 #define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
40289 #define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
40290 #define USB_OTG_DIEPCTL_STALL_Pos                (21U)
40291 #define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
40292 #define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake */
40293 
40294 #define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)
40295 #define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
40296 #define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number */
40297 #define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
40298 #define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
40299 #define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
40300 #define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
40301 #define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)
40302 #define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
40303 #define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK */
40304 #define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)
40305 #define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
40306 #define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */
40307 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)
40308 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
40309 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
40310 #define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)
40311 #define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
40312 #define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame */
40313 #define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)
40314 #define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
40315 #define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable */
40316 #define USB_OTG_DIEPCTL_EPENA_Pos                (31U)
40317 #define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
40318 #define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable */
40319 
40320 /********************  Bit definition for USB_OTG_HCCHAR register  ********************/
40321 #define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)
40322 #define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
40323 #define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */
40324 
40325 #define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)
40326 #define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
40327 #define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */
40328 #define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
40329 #define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
40330 #define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
40331 #define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
40332 #define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)
40333 #define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
40334 #define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */
40335 #define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)
40336 #define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
40337 #define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */
40338 
40339 #define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)
40340 #define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
40341 #define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */
40342 #define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
40343 #define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
40344 
40345 #define USB_OTG_HCCHAR_MC_Pos                    (20U)
40346 #define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
40347 #define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */
40348 #define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
40349 #define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
40350 
40351 #define USB_OTG_HCCHAR_DAD_Pos                   (22U)
40352 #define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
40353 #define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */
40354 #define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
40355 #define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
40356 #define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
40357 #define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
40358 #define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
40359 #define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
40360 #define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
40361 #define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)
40362 #define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
40363 #define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */
40364 #define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)
40365 #define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
40366 #define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */
40367 #define USB_OTG_HCCHAR_CHENA_Pos                 (31U)
40368 #define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
40369 #define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */
40370 
40371 /********************  Bit definition for USB_OTG_HCSPLT register  ********************/
40372 #define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)
40373 #define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
40374 #define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */
40375 #define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
40376 #define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
40377 #define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
40378 #define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
40379 #define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
40380 #define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
40381 #define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
40382 
40383 #define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)
40384 #define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
40385 #define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */
40386 #define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
40387 #define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
40388 #define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
40389 #define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
40390 #define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
40391 #define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
40392 #define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
40393 
40394 #define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)
40395 #define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
40396 #define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */
40397 #define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
40398 #define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
40399 #define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)
40400 #define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
40401 #define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */
40402 #define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)
40403 #define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
40404 #define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */
40405 
40406 /********************  Bit definition for USB_OTG_HCINT register  ********************/
40407 #define USB_OTG_HCINT_XFRC_Pos                   (0U)
40408 #define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
40409 #define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */
40410 #define USB_OTG_HCINT_CHH_Pos                    (1U)
40411 #define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
40412 #define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */
40413 #define USB_OTG_HCINT_AHBERR_Pos                 (2U)
40414 #define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
40415 #define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */
40416 #define USB_OTG_HCINT_STALL_Pos                  (3U)
40417 #define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
40418 #define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */
40419 #define USB_OTG_HCINT_NAK_Pos                    (4U)
40420 #define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
40421 #define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */
40422 #define USB_OTG_HCINT_ACK_Pos                    (5U)
40423 #define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
40424 #define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */
40425 #define USB_OTG_HCINT_NYET_Pos                   (6U)
40426 #define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
40427 #define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */
40428 #define USB_OTG_HCINT_TXERR_Pos                  (7U)
40429 #define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
40430 #define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */
40431 #define USB_OTG_HCINT_BBERR_Pos                  (8U)
40432 #define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
40433 #define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */
40434 #define USB_OTG_HCINT_FRMOR_Pos                  (9U)
40435 #define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
40436 #define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */
40437 #define USB_OTG_HCINT_DTERR_Pos                  (10U)
40438 #define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
40439 #define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */
40440 
40441 /********************  Bit definition for USB_OTG_DIEPINT register  ********************/
40442 #define USB_OTG_DIEPINT_XFRC_Pos                 (0U)
40443 #define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
40444 #define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
40445 #define USB_OTG_DIEPINT_EPDISD_Pos               (1U)
40446 #define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
40447 #define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
40448 #define USB_OTG_DIEPINT_AHBERR_Pos               (2U)
40449 #define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
40450 #define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */
40451 #define USB_OTG_DIEPINT_TOC_Pos                  (3U)
40452 #define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
40453 #define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */
40454 #define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)
40455 #define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
40456 #define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */
40457 #define USB_OTG_DIEPINT_INEPNM_Pos               (5U)
40458 #define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */
40459 #define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */
40460 #define USB_OTG_DIEPINT_INEPNE_Pos               (6U)
40461 #define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
40462 #define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */
40463 #define USB_OTG_DIEPINT_TXFE_Pos                 (7U)
40464 #define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
40465 #define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */
40466 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)
40467 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
40468 #define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
40469 #define USB_OTG_DIEPINT_BNA_Pos                  (9U)
40470 #define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
40471 #define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */
40472 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)
40473 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
40474 #define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
40475 #define USB_OTG_DIEPINT_BERR_Pos                 (12U)
40476 #define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
40477 #define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */
40478 #define USB_OTG_DIEPINT_NAK_Pos                  (13U)
40479 #define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
40480 #define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */
40481 
40482 /********************  Bit definition for USB_OTG_HCINTMSK register  ********************/
40483 #define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)
40484 #define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
40485 #define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */
40486 #define USB_OTG_HCINTMSK_CHHM_Pos                (1U)
40487 #define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
40488 #define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */
40489 #define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)
40490 #define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
40491 #define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */
40492 #define USB_OTG_HCINTMSK_STALLM_Pos              (3U)
40493 #define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
40494 #define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */
40495 #define USB_OTG_HCINTMSK_NAKM_Pos                (4U)
40496 #define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
40497 #define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */
40498 #define USB_OTG_HCINTMSK_ACKM_Pos                (5U)
40499 #define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
40500 #define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */
40501 #define USB_OTG_HCINTMSK_NYET_Pos                (6U)
40502 #define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
40503 #define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */
40504 #define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)
40505 #define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
40506 #define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */
40507 #define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)
40508 #define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
40509 #define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */
40510 #define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)
40511 #define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
40512 #define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */
40513 #define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)
40514 #define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
40515 #define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */
40516 
40517 /********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
40518 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)
40519 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
40520 #define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
40521 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)
40522 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
40523 #define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */
40524 #define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)
40525 #define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
40526 #define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */
40527 
40528 /********************  Bit definition for USB_OTG_HCTSIZ register  ********************/
40529 #define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)
40530 #define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
40531 #define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */
40532 #define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)
40533 #define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
40534 #define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */
40535 #define USB_OTG_HCTSIZ_DOPING_Pos                (31U)
40536 #define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
40537 #define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */
40538 #define USB_OTG_HCTSIZ_DPID_Pos                  (29U)
40539 #define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
40540 #define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */
40541 #define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
40542 #define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
40543 
40544 /********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
40545 #define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)
40546 #define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
40547 #define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */
40548 
40549 /********************  Bit definition for USB_OTG_HCDMA register  ********************/
40550 #define USB_OTG_HCDMA_DMAADDR_Pos                (0U)
40551 #define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
40552 #define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */
40553 
40554 /********************  Bit definition for USB_OTG_DTXFSTS register  ********************/
40555 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)
40556 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
40557 #define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
40558 
40559 /********************  Bit definition for USB_OTG_DIEPTXF register  ********************/
40560 #define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)
40561 #define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
40562 #define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */
40563 #define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)
40564 #define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
40565 #define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */
40566 
40567 /********************  Bit definition for USB_OTG_DOEPCTL register  ********************/
40568 #define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)
40569 #define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
40570 #define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */
40571 #define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)
40572 #define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
40573 #define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */
40574 #define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)
40575 #define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
40576 #define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */
40577 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)
40578 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
40579 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
40580 #define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)
40581 #define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
40582 #define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */
40583 #define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)
40584 #define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
40585 #define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */
40586 #define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
40587 #define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
40588 #define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)
40589 #define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
40590 #define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */
40591 #define USB_OTG_DOEPCTL_STALL_Pos                (21U)
40592 #define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
40593 #define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */
40594 #define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)
40595 #define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
40596 #define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */
40597 #define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)
40598 #define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
40599 #define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */
40600 #define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)
40601 #define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
40602 #define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */
40603 #define USB_OTG_DOEPCTL_EPENA_Pos                (31U)
40604 #define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
40605 #define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */
40606 
40607 /********************  Bit definition for USB_OTG_DOEPINT register  ********************/
40608 #define USB_OTG_DOEPINT_XFRC_Pos                 (0U)
40609 #define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
40610 #define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
40611 #define USB_OTG_DOEPINT_EPDISD_Pos               (1U)
40612 #define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
40613 #define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
40614 #define USB_OTG_DOEPINT_AHBERR_Pos               (2U)
40615 #define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
40616 #define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */
40617 #define USB_OTG_DOEPINT_STUP_Pos                 (3U)
40618 #define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
40619 #define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */
40620 #define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)
40621 #define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
40622 #define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */
40623 #define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)
40624 #define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
40625 #define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< OUT Status Phase Received interrupt */
40626 #define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)
40627 #define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
40628 #define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */
40629 #define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)
40630 #define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
40631 #define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */
40632 #define USB_OTG_DOEPINT_BERR_Pos                 (12U)
40633 #define USB_OTG_DOEPINT_BERR_Msk                 (0x1UL << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */
40634 #define USB_OTG_DOEPINT_BERR                      USB_OTG_DOEPINT_BERR_Msk   /*!< Babble error interrupt */
40635 #define USB_OTG_DOEPINT_NAK_Pos                  (13U)
40636 #define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
40637 #define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */
40638 #define USB_OTG_DOEPINT_NYET_Pos                 (14U)
40639 #define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
40640 #define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */
40641 #define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)
40642 #define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
40643 #define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */
40644 
40645 /********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/
40646 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)
40647 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
40648 #define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
40649 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)
40650 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
40651 #define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */
40652 
40653 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)
40654 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
40655 #define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */
40656 #define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
40657 #define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
40658 
40659 /********************  Bit definition for USB_OTG_PCGCCTL register  ********************/
40660 #define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)
40661 #define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
40662 #define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */
40663 #define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)
40664 #define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
40665 #define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */
40666 #define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)
40667 #define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
40668 #define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */
40669 
40670 /********************  Bit definition for USB_OTG_PCGCCTL1 register  ********************/
40671 #define USB_OTG_PCGCCTL1_GATEEN_Pos               (0U)
40672 #define USB_OTG_PCGCCTL1_GATEEN_Msk               (0x1UL << USB_OTG_PCGCCTL1_GATEEN_Pos) /*!< 0x00000001 */
40673 #define USB_OTG_PCGCCTL1_GATEEN                   USB_OTG_PCGCCTL1_GATEEN_Msk   /*!< Enable Active Clock Gating */
40674 #define USB_OTG_PCGCCTL1_COUNTER_Pos              (1U)
40675 #define USB_OTG_PCGCCTL1_COUNTER_Msk              (0x3UL << USB_OTG_PCGCCTL1_COUNTER_Pos) /*!< 0x00000002 */
40676 #define USB_OTG_PCGCCTL1_COUNTER                  USB_OTG_PCGCCTL1_COUNTER_Msk   /*!< Count to Gate Clock */
40677 #define USB_OTG_PCGCCTL1_RAMGATEEN_Pos            (3U)
40678 #define USB_OTG_PCGCCTL1_RAMGATEEN_Msk            (0x1UL << USB_OTG_PCGCCTL1_RAMGATEEN_Pos) /*!< 0x00000010 */
40679 #define USB_OTG_PCGCCTL1_RAMGATEEN                USB_OTG_PCGCCTL1_RAMGATEEN_Msk   /*!< RAM Clock Gating Enable */
40680 
40681 /*!< USB registers base address */
40682 #define USB_OTG_GLOBAL_BASE                       (0x000UL)
40683 #define USB_OTG_DEVICE_BASE                       (0x800UL)
40684 #define USB_OTG_IN_ENDPOINT_BASE                  (0x900UL)
40685 #define USB_OTG_OUT_ENDPOINT_BASE                 (0xB00UL)
40686 #define USB_OTG_EP_REG_SIZE                       (0x20UL)
40687 #define USB_OTG_HOST_BASE                         (0x400UL)
40688 #define USB_OTG_HOST_PORT_BASE                    (0x440UL)
40689 #define USB_OTG_HOST_CHANNEL_BASE                 (0x500UL)
40690 #define USB_OTG_HOST_CHANNEL_SIZE                 (0x20UL)
40691 #define USB_OTG_PCGCCTL_BASE                      (0xE00UL)
40692 #define USB_OTG_FIFO_BASE                         (0x1000UL)
40693 #define USB_OTG_FIFO_SIZE                         (0x1000UL)
40694 #define USB_OTG_HS_EP_NBR                         (9UL)            /*!< Number of USB HS Device endpoints */
40695 #define USB_OTG_HS_CH_NBR                         (16UL)           /*!< Number of USB HS Host channels */
40696 
40697 /********************  Bit definition for USB_USBPHYC_CR register  ********************/
40698 #define USB_USBPHYC_CR_RETENABLEN1_Pos          (0U)
40699 #define USB_USBPHYC_CR_RETENABLEN1_Msk          (0x1UL << USB_USBPHYC_CR_RETENABLEN1_Pos)    /*!< 0x00000001 */
40700 #define USB_USBPHYC_CR_RETENABLEN1              USB_USBPHYC_CR_RETENABLEN1_Msk               /*!< Retention mode enable */
40701 #define USB_USBPHYC_CR_AUTORSMENB1_Pos          (1U)
40702 #define USB_USBPHYC_CR_AUTORSMENB1_Msk          (0x1UL << USB_USBPHYC_CR_AUTORSMENB1_Pos)    /*!< 0x00000002 */
40703 #define USB_USBPHYC_CR_AUTORSMENB1              USB_USBPHYC_CR_AUTORSMENB1_Msk               /*!< Auto-resume mode enable */
40704 #define USB_USBPHYC_CR_CMN_Pos                  (2U)
40705 #define USB_USBPHYC_CR_CMN_Msk                  (0x1UL << USB_USBPHYC_CR_CMN_Pos)            /*!< 0x00000004 */
40706 #define USB_USBPHYC_CR_CMN                      USB_USBPHYC_CR_CMN_Msk                       /*!< Controls the power down of analog blocks during Suspend and Sleep */
40707 #define USB_USBPHYC_CR_FSEL_Pos                 (4U)
40708 #define USB_USBPHYC_CR_FSEL_Msk                 (0x7UL << USB_USBPHYC_CR_FSEL_Pos)           /*!< 0x00000070 */
40709 #define USB_USBPHYC_CR_FSEL                     USB_USBPHYC_CR_FSEL_Msk                      /*!< Frequency selection */
40710 #define USB_USBPHYC_CR_FSEL_0                   (0x1UL << USB_USBPHYC_CR_FSEL_Pos)           /*!< 0x00000010 */
40711 #define USB_USBPHYC_CR_FSEL_1                   (0x2UL << USB_USBPHYC_CR_FSEL_Pos)           /*!< 0x00000020 */
40712 #define USB_USBPHYC_CR_FSEL_2                   (0x3UL << USB_USBPHYC_CR_FSEL_Pos)           /*!< 0x00000040 */
40713 #define USB_USBPHYC_CR_OTGDISABLE0_Pos          (16U)
40714 #define USB_USBPHYC_CR_OTGDISABLE0_Msk          (0x1UL << USB_USBPHYC_CR_OTGDISABLE0_Pos)    /*!< 0x00010000 */
40715 #define USB_USBPHYC_CR_OTGDISABLE0              USB_USBPHYC_CR_OTGDISABLE0_Msk               /*!< OTG disable 0 */
40716 #define USB_USBPHYC_CR_DRVVBUS0_Pos             (17U)
40717 #define USB_USBPHYC_CR_DRVVBUS0_Msk             (0x1UL << USB_USBPHYC_CR_DRVVBUS0_Pos)       /*!< 0x00020000 */
40718 #define USB_USBPHYC_CR_DRVVBUS0                 USB_USBPHYC_CR_DRVVBUS0_Msk                  /*!< Drive VBUS 0 */
40719 #define USB_USBPHYC_CR_SELOTGDBG_Pos            (31U)
40720 #define USB_USBPHYC_CR_SELOTGDBG_Msk            (0x1UL << USB_USBPHYC_CR_SELOTGDBG_Pos)      /*!< 0x80000000 */
40721 #define USB_USBPHYC_CR_SELOTGDBG                USB_USBPHYC_CR_SELOTGDBG_Msk                 /*!< Select HS PHY debug port */
40722 
40723 
40724 /******************************************************************************/
40725 /*                                                                            */
40726 /*                                 VREFBUF                                    */
40727 /*                                                                            */
40728 /******************************************************************************/
40729 /*******************  Bit definition for VREFBUF_CSR register  ****************/
40730 #define VREFBUF_CSR_ENVR_Pos    (0U)
40731 #define VREFBUF_CSR_ENVR_Msk    (0x1UL << VREFBUF_CSR_ENVR_Pos)                     /*!< 0x00000001 */
40732 #define VREFBUF_CSR_ENVR        VREFBUF_CSR_ENVR_Msk                                /*!<Voltage reference buffer enable */
40733 #define VREFBUF_CSR_HIZ_Pos     (1U)
40734 #define VREFBUF_CSR_HIZ_Msk     (0x1UL << VREFBUF_CSR_HIZ_Pos)                      /*!< 0x00000002 */
40735 #define VREFBUF_CSR_HIZ         VREFBUF_CSR_HIZ_Msk                                 /*!<High impedance mode             */
40736 #define VREFBUF_CSR_VRR_Pos     (3U)
40737 #define VREFBUF_CSR_VRR_Msk     (0x1UL << VREFBUF_CSR_VRR_Pos)                      /*!< 0x00000008 */
40738 #define VREFBUF_CSR_VRR         VREFBUF_CSR_VRR_Msk                                 /*!<Voltage reference buffer ready  */
40739 #define VREFBUF_CSR_VRS_Pos     (4U)
40740 #define VREFBUF_CSR_VRS_Msk     (0x7UL << VREFBUF_CSR_VRS_Pos)                      /*!< 0x00000070 */
40741 #define VREFBUF_CSR_VRS         VREFBUF_CSR_VRS_Msk                                 /*!<Voltage reference scale         */
40742 #define VREFBUF_CSR_VRS_0       (0x01UL<< VREFBUF_CSR_VRS_Pos)                      /*!< 0x000O0010 */
40743 #define VREFBUF_CSR_VRS_1       (0x02UL<< VREFBUF_CSR_VRS_Pos)                      /*!< 0x00000020 */
40744 #define VREFBUF_CSR_VRS_2       (0x04UL<< VREFBUF_CSR_VRS_Pos)                      /*!< 0x00000040 */
40745 
40746 /*******************  Bit definition for VREFBUF_CCR register  ******************/
40747 #define VREFBUF_CCR_TRIM_Pos                (0U)
40748 #define VREFBUF_CCR_TRIM_Msk                (0x3FUL << VREFBUF_CCR_TRIM_Pos)        /*!< 0x0000003F */
40749 #define VREFBUF_CCR_TRIM                    VREFBUF_CCR_TRIM_Msk                    /*!<TRIM[5:0] bits (Trimming code)  */
40750 
40751 
40752 /******************************************************************************/
40753 /*                                                                            */
40754 /*                            Window WATCHDOG                                 */
40755 /*                                                                            */
40756 /******************************************************************************/
40757 /*******************  Bit definition for WWDG_CR register  ********************/
40758 #define WWDG_CR_T_Pos                       (0U)
40759 #define WWDG_CR_T_Msk                       (0x7FUL << WWDG_CR_T_Pos)               /*!< 0x0000007F */
40760 #define WWDG_CR_T                           WWDG_CR_T_Msk                           /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
40761 #define WWDG_CR_T_0                         (0x01UL << WWDG_CR_T_Pos)               /*!< 0x00000001 */
40762 #define WWDG_CR_T_1                         (0x02UL << WWDG_CR_T_Pos)               /*!< 0x00000002 */
40763 #define WWDG_CR_T_2                         (0x04UL << WWDG_CR_T_Pos)               /*!< 0x00000004 */
40764 #define WWDG_CR_T_3                         (0x08UL << WWDG_CR_T_Pos)               /*!< 0x00000008 */
40765 #define WWDG_CR_T_4                         (0x10UL << WWDG_CR_T_Pos)               /*!< 0x00000010 */
40766 #define WWDG_CR_T_5                         (0x20UL << WWDG_CR_T_Pos)               /*!< 0x00000020 */
40767 #define WWDG_CR_T_6                         (0x40UL << WWDG_CR_T_Pos)               /*!< 0x00000040 */
40768 #define WWDG_CR_WDGA_Pos                    (7U)
40769 #define WWDG_CR_WDGA_Msk                    (0x1UL << WWDG_CR_WDGA_Pos)             /*!< 0x00000080 */
40770 #define WWDG_CR_WDGA                        WWDG_CR_WDGA_Msk                        /*!<Activation bit */
40771 
40772 /*******************  Bit definition for WWDG_CFR register  *******************/
40773 #define WWDG_CFR_W_Pos                      (0U)
40774 #define WWDG_CFR_W_Msk                      (0x7FUL << WWDG_CFR_W_Pos)              /*!< 0x0000007F */
40775 #define WWDG_CFR_W                          WWDG_CFR_W_Msk                          /*!<W[6:0] bits (7-bit window value) */
40776 #define WWDG_CFR_W_0                        (0x01UL << WWDG_CFR_W_Pos)              /*!< 0x00000001 */
40777 #define WWDG_CFR_W_1                        (0x02UL << WWDG_CFR_W_Pos)              /*!< 0x00000002 */
40778 #define WWDG_CFR_W_2                        (0x04UL << WWDG_CFR_W_Pos)              /*!< 0x00000004 */
40779 #define WWDG_CFR_W_3                        (0x08UL << WWDG_CFR_W_Pos)              /*!< 0x00000008 */
40780 #define WWDG_CFR_W_4                        (0x10UL << WWDG_CFR_W_Pos)              /*!< 0x00000010 */
40781 #define WWDG_CFR_W_5                        (0x20UL << WWDG_CFR_W_Pos)              /*!< 0x00000020 */
40782 #define WWDG_CFR_W_6                        (0x40UL << WWDG_CFR_W_Pos)              /*!< 0x00000040 */
40783 #define WWDG_CFR_EWI_Pos                    (9U)
40784 #define WWDG_CFR_EWI_Msk                    (0x1UL << WWDG_CFR_EWI_Pos)             /*!< 0x00000200 */
40785 #define WWDG_CFR_EWI                        WWDG_CFR_EWI_Msk                        /*!<Early Wakeup Interrupt */
40786 #define WWDG_CFR_WDGTB_Pos                  (11U)
40787 #define WWDG_CFR_WDGTB_Msk                  (0x7UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00003800 */
40788 #define WWDG_CFR_WDGTB                      WWDG_CFR_WDGTB_Msk                      /*!<WDGTB[2:0] bits (Timer Base) */
40789 #define WWDG_CFR_WDGTB_0                    (0x1UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00000800 */
40790 #define WWDG_CFR_WDGTB_1                    (0x2UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00001000 */
40791 #define WWDG_CFR_WDGTB_2                    (0x4UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00002000 */
40792 
40793 /*******************  Bit definition for WWDG_SR register  ********************/
40794 #define WWDG_SR_EWIF_Pos                    (0U)
40795 #define WWDG_SR_EWIF_Msk                    (0x1UL << WWDG_SR_EWIF_Pos)             /*!< 0x00000001 */
40796 #define WWDG_SR_EWIF                        WWDG_SR_EWIF_Msk                        /*!<Early Wakeup Interrupt Flag */
40797 
40798 
40799 /******************************************************************************/
40800 /*                                                                            */
40801 /*                      Extended-SPI Interface (XSPI)                         */
40802 /*                                                                            */
40803 /******************************************************************************/
40804 /*****************  Bit definition for XSPI_CR register  *******************/
40805 #define XSPI_CR_EN_Pos                   (0U)
40806 #define XSPI_CR_EN_Msk                   (0x1UL << XSPI_CR_EN_Pos)            /*!< 0x00000001 */
40807 #define XSPI_CR_EN                       XSPI_CR_EN_Msk                       /*!< Enable */
40808 #define XSPI_CR_ABORT_Pos                (1U)
40809 #define XSPI_CR_ABORT_Msk                (0x1UL << XSPI_CR_ABORT_Pos)         /*!< 0x00000002 */
40810 #define XSPI_CR_ABORT                    XSPI_CR_ABORT_Msk                    /*!< Abort request */
40811 #define XSPI_CR_DMAEN_Pos                (2U)
40812 #define XSPI_CR_DMAEN_Msk                (0x1UL << XSPI_CR_DMAEN_Pos)         /*!< 0x00000004 */
40813 #define XSPI_CR_DMAEN                    XSPI_CR_DMAEN_Msk                    /*!< DMA Enable */
40814 #define XSPI_CR_TCEN_Pos                 (3U)
40815 #define XSPI_CR_TCEN_Msk                 (0x1UL << XSPI_CR_TCEN_Pos)          /*!< 0x00000008 */
40816 #define XSPI_CR_TCEN                     XSPI_CR_TCEN_Msk                     /*!< Timeout Counter Enable */
40817 #define XSPI_CR_DMM_Pos                  (6U)
40818 #define XSPI_CR_DMM_Msk                  (0x1UL << XSPI_CR_DMM_Pos)           /*!< 0x00000040 */
40819 #define XSPI_CR_DMM                      XSPI_CR_DMM_Msk                      /*!< Dual Memory Mode */
40820 #define XSPI_CR_FSEL_Pos                 (7U)
40821 #define XSPI_CR_FSEL_Msk                 (0x1UL << XSPI_CR_FSEL_Pos)          /*!< 0x00000080 */
40822 #define XSPI_CR_FSEL                     XSPI_CR_FSEL_Msk                     /*!< Flash Select */
40823 #define XSPI_CR_FTHRES_Pos               (8U)
40824 #define XSPI_CR_FTHRES_Msk               (0x3FUL << XSPI_CR_FTHRES_Pos)       /*!< 0x00003F00 */
40825 #define XSPI_CR_FTHRES                   XSPI_CR_FTHRES_Msk                   /*!< FIFO Threshold Level */
40826 #define XSPI_CR_TEIE_Pos                 (16U)
40827 #define XSPI_CR_TEIE_Msk                 (0x1UL << XSPI_CR_TEIE_Pos)          /*!< 0x00010000 */
40828 #define XSPI_CR_TEIE                     XSPI_CR_TEIE_Msk                     /*!< Transfer Error Interrupt Enable */
40829 #define XSPI_CR_TCIE_Pos                 (17U)
40830 #define XSPI_CR_TCIE_Msk                 (0x1UL << XSPI_CR_TCIE_Pos)          /*!< 0x00020000 */
40831 #define XSPI_CR_TCIE                     XSPI_CR_TCIE_Msk                     /*!< Transfer Complete Interrupt Enable */
40832 #define XSPI_CR_FTIE_Pos                 (18U)
40833 #define XSPI_CR_FTIE_Msk                 (0x1UL << XSPI_CR_FTIE_Pos)          /*!< 0x00040000 */
40834 #define XSPI_CR_FTIE                     XSPI_CR_FTIE_Msk                     /*!< FIFO Threshold Interrupt Enable */
40835 #define XSPI_CR_SMIE_Pos                 (19U)
40836 #define XSPI_CR_SMIE_Msk                 (0x1UL << XSPI_CR_SMIE_Pos)          /*!< 0x00080000 */
40837 #define XSPI_CR_SMIE                     XSPI_CR_SMIE_Msk                     /*!< Status Match Interrupt Enable */
40838 #define XSPI_CR_TOIE_Pos                 (20U)
40839 #define XSPI_CR_TOIE_Msk                 (0x1UL << XSPI_CR_TOIE_Pos)          /*!< 0x00100000 */
40840 #define XSPI_CR_TOIE                     XSPI_CR_TOIE_Msk                     /*!< TimeOut Interrupt Enable */
40841 #define XSPI_CR_APMS_Pos                 (22U)
40842 #define XSPI_CR_APMS_Msk                 (0x1UL << XSPI_CR_APMS_Pos)          /*!< 0x00400000 */
40843 #define XSPI_CR_APMS                     XSPI_CR_APMS_Msk                     /*!< Automatic Poll Mode Stop */
40844 #define XSPI_CR_PMM_Pos                  (23U)
40845 #define XSPI_CR_PMM_Msk                  (0x1UL << XSPI_CR_PMM_Pos)           /*!< 0x00800000 */
40846 #define XSPI_CR_PMM                      XSPI_CR_PMM_Msk                      /*!< Polling Match Mode */
40847 #define XSPI_CR_CSSEL_Pos                (24U)
40848 #define XSPI_CR_CSSEL_Msk                (0x1UL << XSPI_CR_CSSEL_Pos)         /*!< 0x01000000 */
40849 #define XSPI_CR_CSSEL                    XSPI_CR_CSSEL_Msk                    /*!< Chip Select Selection */
40850 #define XSPI_CR_NOPREF_Pos               (25U)
40851 #define XSPI_CR_NOPREF_Msk               (0x1UL << XSPI_CR_NOPREF_Pos)        /*!< 0x02000000 */
40852 #define XSPI_CR_NOPREF                   XSPI_CR_NOPREF_Msk                   /*!< No Prefetch Data */
40853 #define XSPI_CR_NOPREF_AXI_Pos           (26U)
40854 #define XSPI_CR_NOPREF_AXI_Msk           (0x1UL << XSPI_CR_NOPREF_AXI_Pos)    /*!< 0x04000000 */
40855 #define XSPI_CR_NOPREF_AXI               XSPI_CR_NOPREF_AXI_Msk               /*!< No Prefetch For Signaled AXI Transactions */
40856 #define XSPI_CR_FMODE_Pos                (28U)
40857 #define XSPI_CR_FMODE_Msk                (0x3UL << XSPI_CR_FMODE_Pos)         /*!< 0x30000000 */
40858 #define XSPI_CR_FMODE                    XSPI_CR_FMODE_Msk                    /*!< Functional Mode */
40859 #define XSPI_CR_FMODE_0                  (0x1UL << XSPI_CR_FMODE_Pos)         /*!< 0x10000000 */
40860 #define XSPI_CR_FMODE_1                  (0x2UL << XSPI_CR_FMODE_Pos)         /*!< 0x20000000 */
40861 #define XSPI_CR_MSEL_Pos                 (30U)
40862 #define XSPI_CR_MSEL_Msk                 (0x3UL << XSPI_CR_MSEL_Pos)          /*!< 0xC0000000 */
40863 #define XSPI_CR_MSEL                     XSPI_CR_MSEL_Msk                     /*!< Memory Select */
40864 #define XSPI_CR_MSEL_0                   (0x1UL << XSPI_CR_MSEL_Pos)          /*!< 0x40000000 */
40865 #define XSPI_CR_MSEL_1                   (0x2UL << XSPI_CR_MSEL_Pos)          /*!< 0x80000000 */
40866 
40867 /****************  Bit definition for XSPI_DCR1 register  ******************/
40868 #define XSPI_DCR1_CKMODE_Pos             (0U)
40869 #define XSPI_DCR1_CKMODE_Msk             (0x1UL << XSPI_DCR1_CKMODE_Pos)      /*!< 0x00000001 */
40870 #define XSPI_DCR1_CKMODE                 XSPI_DCR1_CKMODE_Msk                 /*!< Mode 0 / Mode 3 */
40871 #define XSPI_DCR1_FRCK_Pos               (1U)
40872 #define XSPI_DCR1_FRCK_Msk               (0x1UL << XSPI_DCR1_FRCK_Pos)        /*!< 0x00000002 */
40873 #define XSPI_DCR1_FRCK                   XSPI_DCR1_FRCK_Msk                   /*!< Free Running Clock */
40874 #define XSPI_DCR1_CSHT_Pos               (8U)
40875 #define XSPI_DCR1_CSHT_Msk               (0x3FUL << XSPI_DCR1_CSHT_Pos)       /*!< 0x00003F00 */
40876 #define XSPI_DCR1_CSHT                   XSPI_DCR1_CSHT_Msk                   /*!< Chip Select High Time */
40877 #define XSPI_DCR1_DEVSIZE_Pos            (16U)
40878 #define XSPI_DCR1_DEVSIZE_Msk            (0x1FUL << XSPI_DCR1_DEVSIZE_Pos)    /*!< 0x001F0000 */
40879 #define XSPI_DCR1_DEVSIZE                XSPI_DCR1_DEVSIZE_Msk                /*!< Device Size */
40880 #define XSPI_DCR1_EXTENDMEM_Pos          (21U)
40881 #define XSPI_DCR1_EXTENDMEM_Msk          (0x1UL << XSPI_DCR1_EXTENDMEM_Pos)   /*!< 0x00200000 */
40882 #define XSPI_DCR1_EXTENDMEM              XSPI_DCR1_EXTENDMEM_Msk              /*!< Extended Memory Support */
40883 #define XSPI_DCR1_MTYP_Pos               (24U)
40884 #define XSPI_DCR1_MTYP_Msk               (0x7UL << XSPI_DCR1_MTYP_Pos)        /*!< 0x07000000 */
40885 #define XSPI_DCR1_MTYP                   XSPI_DCR1_MTYP_Msk                   /*!< Memory Type */
40886 #define XSPI_DCR1_MTYP_0                 (0x1UL << XSPI_DCR1_MTYP_Pos)        /*!< 0x01000000 */
40887 #define XSPI_DCR1_MTYP_1                 (0x2UL << XSPI_DCR1_MTYP_Pos)        /*!< 0x02000000 */
40888 #define XSPI_DCR1_MTYP_2                 (0x4UL << XSPI_DCR1_MTYP_Pos)        /*!< 0x04000000 */
40889 
40890 /****************  Bit definition for XSPI_DCR2 register  ******************/
40891 #define XSPI_DCR2_PRESCALER_Pos          (0U)
40892 #define XSPI_DCR2_PRESCALER_Msk          (0xFFUL << XSPI_DCR2_PRESCALER_Pos)  /*!< 0x000000FF */
40893 #define XSPI_DCR2_PRESCALER              XSPI_DCR2_PRESCALER_Msk              /*!< Clock prescaler */
40894 #define XSPI_DCR2_WRAPSIZE_Pos           (16U)
40895 #define XSPI_DCR2_WRAPSIZE_Msk           (0x7UL << XSPI_DCR2_WRAPSIZE_Pos)    /*!< 0x00070000 */
40896 #define XSPI_DCR2_WRAPSIZE               XSPI_DCR2_WRAPSIZE_Msk               /*!< Wrap Size */
40897 #define XSPI_DCR2_WRAPSIZE_0             (0x1UL << XSPI_DCR2_WRAPSIZE_Pos)    /*!< 0x00010000 */
40898 #define XSPI_DCR2_WRAPSIZE_1             (0x2UL << XSPI_DCR2_WRAPSIZE_Pos)    /*!< 0x00020000 */
40899 #define XSPI_DCR2_WRAPSIZE_2             (0x4UL << XSPI_DCR2_WRAPSIZE_Pos)    /*!< 0x00040000 */
40900 
40901 /****************  Bit definition for XSPI_DCR3 register  ******************/
40902 #define XSPI_DCR3_MAXTRAN_Pos            (0U)
40903 #define XSPI_DCR3_MAXTRAN_Msk            (0xFFUL << XSPI_DCR3_MAXTRAN_Pos)    /*!< 0x000000FF */
40904 #define XSPI_DCR3_MAXTRAN                XSPI_DCR3_MAXTRAN_Msk                /*!< Maximum transfer */
40905 #define XSPI_DCR3_CSBOUND_Pos            (16U)
40906 #define XSPI_DCR3_CSBOUND_Msk            (0x1FUL << XSPI_DCR3_CSBOUND_Pos)    /*!< 0x001F0000 */
40907 #define XSPI_DCR3_CSBOUND                XSPI_DCR3_CSBOUND_Msk                /*!< Maximum transfer */
40908 
40909 /****************  Bit definition for XSPI_DCR4 register  ******************/
40910 #define XSPI_DCR4_REFRESH_Pos            (0U)
40911 #define XSPI_DCR4_REFRESH_Msk            (0xFFFFFFFFUL << XSPI_DCR4_REFRESH_Pos) /*!< 0xFFFFFFFF */
40912 #define XSPI_DCR4_REFRESH                XSPI_DCR4_REFRESH_Msk                /*!< Refresh rate */
40913 
40914 /*****************  Bit definition for XSPI_SR register  *******************/
40915 #define XSPI_SR_TEF_Pos                  (0U)
40916 #define XSPI_SR_TEF_Msk                  (0x1UL << XSPI_SR_TEF_Pos)           /*!< 0x00000001 */
40917 #define XSPI_SR_TEF                      XSPI_SR_TEF_Msk                      /*!< Transfer Error Flag */
40918 #define XSPI_SR_TCF_Pos                  (1U)
40919 #define XSPI_SR_TCF_Msk                  (0x1UL << XSPI_SR_TCF_Pos)           /*!< 0x00000002 */
40920 #define XSPI_SR_TCF                      XSPI_SR_TCF_Msk                      /*!< Transfer Complete Flag */
40921 #define XSPI_SR_FTF_Pos                  (2U)
40922 #define XSPI_SR_FTF_Msk                  (0x1UL << XSPI_SR_FTF_Pos)           /*!< 0x00000004 */
40923 #define XSPI_SR_FTF                      XSPI_SR_FTF_Msk                      /*!< FIFO Threshold Flag */
40924 #define XSPI_SR_SMF_Pos                  (3U)
40925 #define XSPI_SR_SMF_Msk                  (0x1UL << XSPI_SR_SMF_Pos)           /*!< 0x00000008 */
40926 #define XSPI_SR_SMF                      XSPI_SR_SMF_Msk                      /*!< Status Match Flag */
40927 #define XSPI_SR_TOF_Pos                  (4U)
40928 #define XSPI_SR_TOF_Msk                  (0x1UL << XSPI_SR_TOF_Pos)           /*!< 0x00000010 */
40929 #define XSPI_SR_TOF                      XSPI_SR_TOF_Msk                      /*!< Timeout Flag */
40930 #define XSPI_SR_BUSY_Pos                 (5U)
40931 #define XSPI_SR_BUSY_Msk                 (0x1UL << XSPI_SR_BUSY_Pos)          /*!< 0x00000020 */
40932 #define XSPI_SR_BUSY                     XSPI_SR_BUSY_Msk                     /*!< Busy */
40933 #define XSPI_SR_FLEVEL_Pos               (8U)
40934 #define XSPI_SR_FLEVEL_Msk               (0x7FUL << XSPI_SR_FLEVEL_Pos)       /*!< 0x00007F00 */
40935 #define XSPI_SR_FLEVEL                   XSPI_SR_FLEVEL_Msk                   /*!< FIFO Level */
40936 
40937 /****************  Bit definition for XSPI_FCR register  *******************/
40938 #define XSPI_FCR_CTEF_Pos                (0U)
40939 #define XSPI_FCR_CTEF_Msk                (0x1UL << XSPI_FCR_CTEF_Pos)         /*!< 0x00000001 */
40940 #define XSPI_FCR_CTEF                    XSPI_FCR_CTEF_Msk                    /*!< Clear Transfer Error Flag */
40941 #define XSPI_FCR_CTCF_Pos                (1U)
40942 #define XSPI_FCR_CTCF_Msk                (0x1UL << XSPI_FCR_CTCF_Pos)         /*!< 0x00000002 */
40943 #define XSPI_FCR_CTCF                    XSPI_FCR_CTCF_Msk                    /*!< Clear Transfer Complete Flag */
40944 #define XSPI_FCR_CSMF_Pos                (3U)
40945 #define XSPI_FCR_CSMF_Msk                (0x1UL << XSPI_FCR_CSMF_Pos)         /*!< 0x00000008 */
40946 #define XSPI_FCR_CSMF                    XSPI_FCR_CSMF_Msk                    /*!< Clear Status Match Flag */
40947 #define XSPI_FCR_CTOF_Pos                (4U)
40948 #define XSPI_FCR_CTOF_Msk                (0x1UL << XSPI_FCR_CTOF_Pos)         /*!< 0x00000010 */
40949 #define XSPI_FCR_CTOF                    XSPI_FCR_CTOF_Msk                    /*!< Clear Timeout Flag */
40950 
40951 /****************  Bit definition for XSPI_DLR register  *******************/
40952 #define XSPI_DLR_DL_Pos                  (0U)
40953 #define XSPI_DLR_DL_Msk                  (0xFFFFFFFFUL << XSPI_DLR_DL_Pos)    /*!< 0xFFFFFFFF */
40954 #define XSPI_DLR_DL                      XSPI_DLR_DL_Msk                      /*!< Data Length */
40955 
40956 /*****************  Bit definition for XSPI_AR register  *******************/
40957 #define XSPI_AR_ADDRESS_Pos              (0U)
40958 #define XSPI_AR_ADDRESS_Msk              (0xFFFFFFFFUL << XSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
40959 #define XSPI_AR_ADDRESS                  XSPI_AR_ADDRESS_Msk                  /*!< Address */
40960 
40961 /*****************  Bit definition for XSPI_DR register  *******************/
40962 #define XSPI_DR_DATA_Pos                 (0U)
40963 #define XSPI_DR_DATA_Msk                 (0xFFFFFFFFUL << XSPI_DR_DATA_Pos)   /*!< 0xFFFFFFFF */
40964 #define XSPI_DR_DATA                     XSPI_DR_DATA_Msk                     /*!< Data */
40965 
40966 /***************  Bit definition for XSPI_PSMKR register  ******************/
40967 #define XSPI_PSMKR_MASK_Pos              (0U)
40968 #define XSPI_PSMKR_MASK_Msk              (0xFFFFFFFFUL << XSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
40969 #define XSPI_PSMKR_MASK                  XSPI_PSMKR_MASK_Msk                  /*!< Status mask */
40970 
40971 /***************  Bit definition for XSPI_PSMAR register  ******************/
40972 #define XSPI_PSMAR_MATCH_Pos             (0U)
40973 #define XSPI_PSMAR_MATCH_Msk             (0xFFFFFFFFUL << XSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
40974 #define XSPI_PSMAR_MATCH                 XSPI_PSMAR_MATCH_Msk                 /*!< Status match */
40975 
40976 /****************  Bit definition for XSPI_PIR register  *******************/
40977 #define XSPI_PIR_INTERVAL_Pos            (0U)
40978 #define XSPI_PIR_INTERVAL_Msk            (0xFFFFUL << XSPI_PIR_INTERVAL_Pos)  /*!< 0x0000FFFF */
40979 #define XSPI_PIR_INTERVAL                XSPI_PIR_INTERVAL_Msk                /*!< Polling Interval */
40980 
40981 /****************  Bit definition for XSPI_CCR register  *******************/
40982 #define XSPI_CCR_IMODE_Pos               (0U)
40983 #define XSPI_CCR_IMODE_Msk               (0x7UL << XSPI_CCR_IMODE_Pos)        /*!< 0x00000007 */
40984 #define XSPI_CCR_IMODE                   XSPI_CCR_IMODE_Msk                   /*!< Instruction Mode */
40985 #define XSPI_CCR_IMODE_0                 (0x1UL << XSPI_CCR_IMODE_Pos)        /*!< 0x00000001 */
40986 #define XSPI_CCR_IMODE_1                 (0x2UL << XSPI_CCR_IMODE_Pos)        /*!< 0x00000002 */
40987 #define XSPI_CCR_IMODE_2                 (0x4UL << XSPI_CCR_IMODE_Pos)        /*!< 0x00000004 */
40988 #define XSPI_CCR_IDTR_Pos                (3U)
40989 #define XSPI_CCR_IDTR_Msk                (0x1UL << XSPI_CCR_IDTR_Pos)         /*!< 0x00000008 */
40990 #define XSPI_CCR_IDTR                    XSPI_CCR_IDTR_Msk                    /*!< Instruction Double Transfer Rate */
40991 #define XSPI_CCR_ISIZE_Pos               (4U)
40992 #define XSPI_CCR_ISIZE_Msk               (0x3UL << XSPI_CCR_ISIZE_Pos)        /*!< 0x00000030 */
40993 #define XSPI_CCR_ISIZE                   XSPI_CCR_ISIZE_Msk                   /*!< Instruction Size */
40994 #define XSPI_CCR_ISIZE_0                 (0x1UL << XSPI_CCR_ISIZE_Pos)        /*!< 0x00000010 */
40995 #define XSPI_CCR_ISIZE_1                 (0x2UL << XSPI_CCR_ISIZE_Pos)        /*!< 0x00000020 */
40996 #define XSPI_CCR_ADMODE_Pos              (8U)
40997 #define XSPI_CCR_ADMODE_Msk              (0x7UL << XSPI_CCR_ADMODE_Pos)       /*!< 0x00000700 */
40998 #define XSPI_CCR_ADMODE                  XSPI_CCR_ADMODE_Msk                  /*!< Address Mode */
40999 #define XSPI_CCR_ADMODE_0                (0x1UL << XSPI_CCR_ADMODE_Pos)       /*!< 0x00000100 */
41000 #define XSPI_CCR_ADMODE_1                (0x2UL << XSPI_CCR_ADMODE_Pos)       /*!< 0x00000200 */
41001 #define XSPI_CCR_ADMODE_2                (0x4UL << XSPI_CCR_ADMODE_Pos)       /*!< 0x00000400 */
41002 #define XSPI_CCR_ADDTR_Pos               (11U)
41003 #define XSPI_CCR_ADDTR_Msk               (0x1UL << XSPI_CCR_ADDTR_Pos)        /*!< 0x00000800 */
41004 #define XSPI_CCR_ADDTR                   XSPI_CCR_ADDTR_Msk                   /*!< Address Double Transfer Rate */
41005 #define XSPI_CCR_ADSIZE_Pos              (12U)
41006 #define XSPI_CCR_ADSIZE_Msk              (0x3UL << XSPI_CCR_ADSIZE_Pos)       /*!< 0x00003000 */
41007 #define XSPI_CCR_ADSIZE                  XSPI_CCR_ADSIZE_Msk                  /*!< Address Size */
41008 #define XSPI_CCR_ADSIZE_0                (0x1UL << XSPI_CCR_ADSIZE_Pos)       /*!< 0x00001000 */
41009 #define XSPI_CCR_ADSIZE_1                (0x2UL << XSPI_CCR_ADSIZE_Pos)       /*!< 0x00002000 */
41010 #define XSPI_CCR_ABMODE_Pos              (16U)
41011 #define XSPI_CCR_ABMODE_Msk              (0x7UL << XSPI_CCR_ABMODE_Pos)       /*!< 0x00070000 */
41012 #define XSPI_CCR_ABMODE                  XSPI_CCR_ABMODE_Msk                  /*!< Alternate Bytes Mode */
41013 #define XSPI_CCR_ABMODE_0                (0x1UL << XSPI_CCR_ABMODE_Pos)       /*!< 0x00010000 */
41014 #define XSPI_CCR_ABMODE_1                (0x2UL << XSPI_CCR_ABMODE_Pos)       /*!< 0x00020000 */
41015 #define XSPI_CCR_ABMODE_2                (0x4UL << XSPI_CCR_ABMODE_Pos)       /*!< 0x00040000 */
41016 #define XSPI_CCR_ABDTR_Pos               (19U)
41017 #define XSPI_CCR_ABDTR_Msk               (0x1UL << XSPI_CCR_ABDTR_Pos)        /*!< 0x00080000 */
41018 #define XSPI_CCR_ABDTR                   XSPI_CCR_ABDTR_Msk                   /*!< Alternate Bytes Double Transfer Rate */
41019 #define XSPI_CCR_ABSIZE_Pos              (20U)
41020 #define XSPI_CCR_ABSIZE_Msk              (0x3UL << XSPI_CCR_ABSIZE_Pos)       /*!< 0x00300000 */
41021 #define XSPI_CCR_ABSIZE                  XSPI_CCR_ABSIZE_Msk                  /*!< Alternate Bytes Size */
41022 #define XSPI_CCR_ABSIZE_0                (0x1UL << XSPI_CCR_ABSIZE_Pos)       /*!< 0x00100000 */
41023 #define XSPI_CCR_ABSIZE_1                (0x2UL << XSPI_CCR_ABSIZE_Pos)       /*!< 0x00200000 */
41024 #define XSPI_CCR_DMODE_Pos               (24U)
41025 #define XSPI_CCR_DMODE_Msk               (0x7UL << XSPI_CCR_DMODE_Pos)        /*!< 0x07000000 */
41026 #define XSPI_CCR_DMODE                   XSPI_CCR_DMODE_Msk                   /*!< Data Mode */
41027 #define XSPI_CCR_DMODE_0                 (0x1UL << XSPI_CCR_DMODE_Pos)        /*!< 0x01000000 */
41028 #define XSPI_CCR_DMODE_1                 (0x2UL << XSPI_CCR_DMODE_Pos)        /*!< 0x02000000 */
41029 #define XSPI_CCR_DMODE_2                 (0x4UL << XSPI_CCR_DMODE_Pos)        /*!< 0x04000000 */
41030 #define XSPI_CCR_DDTR_Pos                (27U)
41031 #define XSPI_CCR_DDTR_Msk                (0x1UL << XSPI_CCR_DDTR_Pos)         /*!< 0x08000000 */
41032 #define XSPI_CCR_DDTR                    XSPI_CCR_DDTR_Msk                    /*!< Data Double Transfer Rate */
41033 #define XSPI_CCR_DQSE_Pos                (29U)
41034 #define XSPI_CCR_DQSE_Msk                (0x1UL << XSPI_CCR_DQSE_Pos)         /*!< 0x20000000 */
41035 #define XSPI_CCR_DQSE                    XSPI_CCR_DQSE_Msk                    /*!< DQS Enable */
41036 
41037 /****************  Bit definition for XSPI_TCR register  *******************/
41038 #define XSPI_TCR_DCYC_Pos                (0U)
41039 #define XSPI_TCR_DCYC_Msk                (0x1FUL << XSPI_TCR_DCYC_Pos)        /*!< 0x0000001F */
41040 #define XSPI_TCR_DCYC                    XSPI_TCR_DCYC_Msk                    /*!< Number of Dummy Cycles */
41041 #define XSPI_TCR_DHQC_Pos                (28U)
41042 #define XSPI_TCR_DHQC_Msk                (0x1UL << XSPI_TCR_DHQC_Pos)         /*!< 0x10000000 */
41043 #define XSPI_TCR_DHQC                    XSPI_TCR_DHQC_Msk                    /*!< Delay Hold Quarter Cycle */
41044 #define XSPI_TCR_SSHIFT_Pos              (30U)
41045 #define XSPI_TCR_SSHIFT_Msk              (0x1UL << XSPI_TCR_SSHIFT_Pos)       /*!< 0x40000000 */
41046 #define XSPI_TCR_SSHIFT                  XSPI_TCR_SSHIFT_Msk                  /*!< Sample Shift */
41047 
41048 /*****************  Bit definition for XSPI_IR register  *******************/
41049 #define XSPI_IR_INSTRUCTION_Pos          (0U)
41050 #define XSPI_IR_INSTRUCTION_Msk          (0xFFFFFFFFUL << XSPI_IR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */
41051 #define XSPI_IR_INSTRUCTION              XSPI_IR_INSTRUCTION_Msk              /*!< Instruction */
41052 
41053 /****************  Bit definition for XSPI_ABR register  *******************/
41054 #define XSPI_ABR_ALTERNATE_Pos           (0U)
41055 #define XSPI_ABR_ALTERNATE_Msk           (0xFFFFFFFFUL << XSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
41056 #define XSPI_ABR_ALTERNATE               XSPI_ABR_ALTERNATE_Msk               /*!< Alternate Bytes */
41057 
41058 /****************  Bit definition for XSPI_LPTR register  ******************/
41059 #define XSPI_LPTR_TIMEOUT_Pos            (0U)
41060 #define XSPI_LPTR_TIMEOUT_Msk            (0xFFFFUL << XSPI_LPTR_TIMEOUT_Pos)  /*!< 0x0000FFFF */
41061 #define XSPI_LPTR_TIMEOUT                XSPI_LPTR_TIMEOUT_Msk                /*!< Timeout period */
41062 
41063 /****************  Bit definition for XSPI_WPCCR register  *******************/
41064 #define XSPI_WPCCR_IMODE_Pos             (0U)
41065 #define XSPI_WPCCR_IMODE_Msk             (0x7UL << XSPI_WPCCR_IMODE_Pos)      /*!< 0x00000007 */
41066 #define XSPI_WPCCR_IMODE                 XSPI_WPCCR_IMODE_Msk                 /*!< Instruction Mode */
41067 #define XSPI_WPCCR_IMODE_0               (0x1UL << XSPI_WPCCR_IMODE_Pos)      /*!< 0x00000001 */
41068 #define XSPI_WPCCR_IMODE_1               (0x2UL << XSPI_WPCCR_IMODE_Pos)      /*!< 0x00000002 */
41069 #define XSPI_WPCCR_IMODE_2               (0x4UL << XSPI_WPCCR_IMODE_Pos)      /*!< 0x00000004 */
41070 #define XSPI_WPCCR_IDTR_Pos              (3U)
41071 #define XSPI_WPCCR_IDTR_Msk              (0x1UL << XSPI_WPCCR_IDTR_Pos)       /*!< 0x00000008 */
41072 #define XSPI_WPCCR_IDTR                  XSPI_WPCCR_IDTR_Msk                  /*!< Instruction Double Transfer Rate */
41073 #define XSPI_WPCCR_ISIZE_Pos             (4U)
41074 #define XSPI_WPCCR_ISIZE_Msk             (0x3UL << XSPI_WPCCR_ISIZE_Pos)      /*!< 0x00000030 */
41075 #define XSPI_WPCCR_ISIZE                 XSPI_WPCCR_ISIZE_Msk                 /*!< Instruction Size */
41076 #define XSPI_WPCCR_ISIZE_0               (0x1UL << XSPI_WPCCR_ISIZE_Pos)      /*!< 0x00000010 */
41077 #define XSPI_WPCCR_ISIZE_1               (0x2UL << XSPI_WPCCR_ISIZE_Pos)      /*!< 0x00000020 */
41078 #define XSPI_WPCCR_ADMODE_Pos            (8U)
41079 #define XSPI_WPCCR_ADMODE_Msk            (0x7UL << XSPI_WPCCR_ADMODE_Pos)     /*!< 0x00000700 */
41080 #define XSPI_WPCCR_ADMODE                XSPI_WPCCR_ADMODE_Msk                /*!< Address Mode */
41081 #define XSPI_WPCCR_ADMODE_0              (0x1UL << XSPI_WPCCR_ADMODE_Pos)     /*!< 0x00000100 */
41082 #define XSPI_WPCCR_ADMODE_1              (0x2UL << XSPI_WPCCR_ADMODE_Pos)     /*!< 0x00000200 */
41083 #define XSPI_WPCCR_ADMODE_2              (0x4UL << XSPI_WPCCR_ADMODE_Pos)     /*!< 0x00000400 */
41084 #define XSPI_WPCCR_ADDTR_Pos             (11U)
41085 #define XSPI_WPCCR_ADDTR_Msk             (0x1UL << XSPI_WPCCR_ADDTR_Pos)      /*!< 0x00000800 */
41086 #define XSPI_WPCCR_ADDTR                 XSPI_WPCCR_ADDTR_Msk                 /*!< Address Double Transfer Rate */
41087 #define XSPI_WPCCR_ADSIZE_Pos            (12U)
41088 #define XSPI_WPCCR_ADSIZE_Msk            (0x3UL << XSPI_WPCCR_ADSIZE_Pos)     /*!< 0x00003000 */
41089 #define XSPI_WPCCR_ADSIZE                XSPI_WPCCR_ADSIZE_Msk                /*!< Address Size */
41090 #define XSPI_WPCCR_ADSIZE_0              (0x1UL << XSPI_WPCCR_ADSIZE_Pos)     /*!< 0x00001000 */
41091 #define XSPI_WPCCR_ADSIZE_1              (0x2UL << XSPI_WPCCR_ADSIZE_Pos)     /*!< 0x00002000 */
41092 #define XSPI_WPCCR_ABMODE_Pos            (16U)
41093 #define XSPI_WPCCR_ABMODE_Msk            (0x7UL << XSPI_WPCCR_ABMODE_Pos)     /*!< 0x00070000 */
41094 #define XSPI_WPCCR_ABMODE                XSPI_WPCCR_ABMODE_Msk                /*!< Alternate Bytes Mode */
41095 #define XSPI_WPCCR_ABMODE_0              (0x1UL << XSPI_WPCCR_ABMODE_Pos)     /*!< 0x00010000 */
41096 #define XSPI_WPCCR_ABMODE_1              (0x2UL << XSPI_WPCCR_ABMODE_Pos)     /*!< 0x00020000 */
41097 #define XSPI_WPCCR_ABMODE_2              (0x4UL << XSPI_WPCCR_ABMODE_Pos)     /*!< 0x00040000 */
41098 #define XSPI_WPCCR_ABDTR_Pos             (19U)
41099 #define XSPI_WPCCR_ABDTR_Msk             (0x1UL << XSPI_WPCCR_ABDTR_Pos)      /*!< 0x00080000 */
41100 #define XSPI_WPCCR_ABDTR                 XSPI_WPCCR_ABDTR_Msk                 /*!< Alternate Bytes Double Transfer Rate */
41101 #define XSPI_WPCCR_ABSIZE_Pos            (20U)
41102 #define XSPI_WPCCR_ABSIZE_Msk            (0x3UL << XSPI_WPCCR_ABSIZE_Pos)     /*!< 0x00300000 */
41103 #define XSPI_WPCCR_ABSIZE                XSPI_WPCCR_ABSIZE_Msk                /*!< Alternate Bytes Size */
41104 #define XSPI_WPCCR_ABSIZE_0              (0x1UL << XSPI_WPCCR_ABSIZE_Pos)     /*!< 0x00100000 */
41105 #define XSPI_WPCCR_ABSIZE_1              (0x2UL << XSPI_WPCCR_ABSIZE_Pos)     /*!< 0x00200000 */
41106 #define XSPI_WPCCR_DMODE_Pos             (24U)
41107 #define XSPI_WPCCR_DMODE_Msk             (0x7UL << XSPI_WPCCR_DMODE_Pos)      /*!< 0x07000000 */
41108 #define XSPI_WPCCR_DMODE                 XSPI_WPCCR_DMODE_Msk                 /*!< Data Mode */
41109 #define XSPI_WPCCR_DMODE_0               (0x1UL << XSPI_WPCCR_DMODE_Pos)      /*!< 0x01000000 */
41110 #define XSPI_WPCCR_DMODE_1               (0x2UL << XSPI_WPCCR_DMODE_Pos)      /*!< 0x02000000 */
41111 #define XSPI_WPCCR_DMODE_2               (0x4UL << XSPI_WPCCR_DMODE_Pos)      /*!< 0x04000000 */
41112 #define XSPI_WPCCR_DDTR_Pos              (27U)
41113 #define XSPI_WPCCR_DDTR_Msk              (0x1UL << XSPI_WPCCR_DDTR_Pos)       /*!< 0x08000000 */
41114 #define XSPI_WPCCR_DDTR                  XSPI_WPCCR_DDTR_Msk                  /*!< Data Double Transfer Rate */
41115 #define XSPI_WPCCR_DQSE_Pos              (29U)
41116 #define XSPI_WPCCR_DQSE_Msk              (0x1UL << XSPI_WPCCR_DQSE_Pos)       /*!< 0x20000000 */
41117 #define XSPI_WPCCR_DQSE                  XSPI_WPCCR_DQSE_Msk                  /*!< DQS Enable */
41118 
41119 /****************  Bit definition for XSPI_WPTCR register  *******************/
41120 #define XSPI_WPTCR_DCYC_Pos              (0U)
41121 #define XSPI_WPTCR_DCYC_Msk              (0x1FUL << XSPI_WPTCR_DCYC_Pos)      /*!< 0x0000001F */
41122 #define XSPI_WPTCR_DCYC                  XSPI_WPTCR_DCYC_Msk                  /*!< Number of Dummy Cycles */
41123 #define XSPI_WPTCR_DHQC_Pos              (28U)
41124 #define XSPI_WPTCR_DHQC_Msk              (0x1UL << XSPI_WPTCR_DHQC_Pos)       /*!< 0x10000000 */
41125 #define XSPI_WPTCR_DHQC                  XSPI_WPTCR_DHQC_Msk                  /*!< Delay Hold Quarter Cycle */
41126 #define XSPI_WPTCR_SSHIFT_Pos            (30U)
41127 #define XSPI_WPTCR_SSHIFT_Msk            (0x1UL << XSPI_WPTCR_SSHIFT_Pos)     /*!< 0x40000000 */
41128 #define XSPI_WPTCR_SSHIFT                XSPI_WPTCR_SSHIFT_Msk                /*!< Sample Shift */
41129 
41130 /*****************  Bit definition for XSPI_WPIR register  *******************/
41131 #define XSPI_WPIR_INSTRUCTION_Pos        (0U)
41132 #define XSPI_WPIR_INSTRUCTION_Msk        (0xFFFFFFFFUL << XSPI_WPIR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */
41133 #define XSPI_WPIR_INSTRUCTION            XSPI_WPIR_INSTRUCTION_Msk            /*!< Instruction */
41134 
41135 /****************  Bit definition for XSPI_WPABR register  *******************/
41136 #define XSPI_WPABR_ALTERNATE_Pos         (0U)
41137 #define XSPI_WPABR_ALTERNATE_Msk         (0xFFFFFFFFUL << XSPI_WPABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
41138 #define XSPI_WPABR_ALTERNATE             XSPI_WPABR_ALTERNATE_Msk             /*!< Alternate Bytes */
41139 
41140 /****************  Bit definition for XSPI_WCCR register  ******************/
41141 #define XSPI_WCCR_IMODE_Pos              (0U)
41142 #define XSPI_WCCR_IMODE_Msk              (0x7UL << XSPI_WCCR_IMODE_Pos)       /*!< 0x00000007 */
41143 #define XSPI_WCCR_IMODE                  XSPI_WCCR_IMODE_Msk                  /*!< Instruction Mode */
41144 #define XSPI_WCCR_IMODE_0                (0x1UL << XSPI_WCCR_IMODE_Pos)       /*!< 0x00000001 */
41145 #define XSPI_WCCR_IMODE_1                (0x2UL << XSPI_WCCR_IMODE_Pos)       /*!< 0x00000002 */
41146 #define XSPI_WCCR_IMODE_2                (0x4UL << XSPI_WCCR_IMODE_Pos)       /*!< 0x00000004 */
41147 #define XSPI_WCCR_IDTR_Pos               (3U)
41148 #define XSPI_WCCR_IDTR_Msk               (0x1UL << XSPI_WCCR_IDTR_Pos)        /*!< 0x00000008 */
41149 #define XSPI_WCCR_IDTR                   XSPI_WCCR_IDTR_Msk                   /*!< Instruction Double Transfer Rate */
41150 #define XSPI_WCCR_ISIZE_Pos              (4U)
41151 #define XSPI_WCCR_ISIZE_Msk              (0x3UL << XSPI_WCCR_ISIZE_Pos)       /*!< 0x00000030 */
41152 #define XSPI_WCCR_ISIZE                  XSPI_WCCR_ISIZE_Msk                  /*!< Instruction Size */
41153 #define XSPI_WCCR_ISIZE_0                (0x1UL << XSPI_WCCR_ISIZE_Pos)       /*!< 0x00000010 */
41154 #define XSPI_WCCR_ISIZE_1                (0x2UL << XSPI_WCCR_ISIZE_Pos)       /*!< 0x00000020 */
41155 #define XSPI_WCCR_ADMODE_Pos             (8U)
41156 #define XSPI_WCCR_ADMODE_Msk             (0x7UL << XSPI_WCCR_ADMODE_Pos)      /*!< 0x00000700 */
41157 #define XSPI_WCCR_ADMODE                 XSPI_WCCR_ADMODE_Msk                 /*!< Address Mode */
41158 #define XSPI_WCCR_ADMODE_0               (0x1UL << XSPI_WCCR_ADMODE_Pos)      /*!< 0x00000100 */
41159 #define XSPI_WCCR_ADMODE_1               (0x2UL << XSPI_WCCR_ADMODE_Pos)      /*!< 0x00000200 */
41160 #define XSPI_WCCR_ADMODE_2               (0x4UL << XSPI_WCCR_ADMODE_Pos)      /*!< 0x00000400 */
41161 #define XSPI_WCCR_ADDTR_Pos              (11U)
41162 #define XSPI_WCCR_ADDTR_Msk              (0x1UL << XSPI_WCCR_ADDTR_Pos)       /*!< 0x00000800 */
41163 #define XSPI_WCCR_ADDTR                  XSPI_WCCR_ADDTR_Msk                  /*!< Address Double Transfer Rate */
41164 #define XSPI_WCCR_ADSIZE_Pos             (12U)
41165 #define XSPI_WCCR_ADSIZE_Msk             (0x3UL << XSPI_WCCR_ADSIZE_Pos)      /*!< 0x00003000 */
41166 #define XSPI_WCCR_ADSIZE                 XSPI_WCCR_ADSIZE_Msk                 /*!< Address Size */
41167 #define XSPI_WCCR_ADSIZE_0               (0x1UL << XSPI_WCCR_ADSIZE_Pos)      /*!< 0x00001000 */
41168 #define XSPI_WCCR_ADSIZE_1               (0x2UL << XSPI_WCCR_ADSIZE_Pos)      /*!< 0x00002000 */
41169 #define XSPI_WCCR_ABMODE_Pos             (16U)
41170 #define XSPI_WCCR_ABMODE_Msk             (0x7UL << XSPI_WCCR_ABMODE_Pos)      /*!< 0x00070000 */
41171 #define XSPI_WCCR_ABMODE                 XSPI_WCCR_ABMODE_Msk                 /*!< Alternate Bytes Mode */
41172 #define XSPI_WCCR_ABMODE_0               (0x1UL << XSPI_WCCR_ABMODE_Pos)      /*!< 0x00010000 */
41173 #define XSPI_WCCR_ABMODE_1               (0x2UL << XSPI_WCCR_ABMODE_Pos)      /*!< 0x00020000 */
41174 #define XSPI_WCCR_ABMODE_2               (0x4UL << XSPI_WCCR_ABMODE_Pos)      /*!< 0x00040000 */
41175 #define XSPI_WCCR_ABDTR_Pos              (19U)
41176 #define XSPI_WCCR_ABDTR_Msk              (0x1UL << XSPI_WCCR_ABDTR_Pos)       /*!< 0x00080000 */
41177 #define XSPI_WCCR_ABDTR                  XSPI_WCCR_ABDTR_Msk                  /*!< Alternate Bytes Double Transfer Rate */
41178 #define XSPI_WCCR_ABSIZE_Pos             (20U)
41179 #define XSPI_WCCR_ABSIZE_Msk             (0x3UL << XSPI_WCCR_ABSIZE_Pos)      /*!< 0x00300000 */
41180 #define XSPI_WCCR_ABSIZE                 XSPI_WCCR_ABSIZE_Msk                 /*!< Alternate Bytes Size */
41181 #define XSPI_WCCR_ABSIZE_0               (0x1UL << XSPI_WCCR_ABSIZE_Pos)      /*!< 0x00100000 */
41182 #define XSPI_WCCR_ABSIZE_1               (0x2UL << XSPI_WCCR_ABSIZE_Pos)      /*!< 0x00200000 */
41183 #define XSPI_WCCR_DMODE_Pos              (24U)
41184 #define XSPI_WCCR_DMODE_Msk              (0x7UL << XSPI_WCCR_DMODE_Pos)       /*!< 0x07000000 */
41185 #define XSPI_WCCR_DMODE                  XSPI_WCCR_DMODE_Msk                  /*!< Data Mode */
41186 #define XSPI_WCCR_DMODE_0                (0x1UL << XSPI_WCCR_DMODE_Pos)       /*!< 0x01000000 */
41187 #define XSPI_WCCR_DMODE_1                (0x2UL << XSPI_WCCR_DMODE_Pos)       /*!< 0x02000000 */
41188 #define XSPI_WCCR_DMODE_2                (0x4UL << XSPI_WCCR_DMODE_Pos)       /*!< 0x04000000 */
41189 #define XSPI_WCCR_DDTR_Pos               (27U)
41190 #define XSPI_WCCR_DDTR_Msk               (0x1UL << XSPI_WCCR_DDTR_Pos)        /*!< 0x08000000 */
41191 #define XSPI_WCCR_DDTR                   XSPI_WCCR_DDTR_Msk                   /*!< Data Double Transfer Rate */
41192 #define XSPI_WCCR_DQSE_Pos               (29U)
41193 #define XSPI_WCCR_DQSE_Msk               (0x1UL << XSPI_WCCR_DQSE_Pos)        /*!< 0x20000000 */
41194 #define XSPI_WCCR_DQSE                   XSPI_WCCR_DQSE_Msk                   /*!< DQS Enable */
41195 
41196 /****************  Bit definition for XSPI_WTCR register  ******************/
41197 #define XSPI_WTCR_DCYC_Pos               (0U)
41198 #define XSPI_WTCR_DCYC_Msk               (0x1FUL << XSPI_WTCR_DCYC_Pos)       /*!< 0x0000001F */
41199 #define XSPI_WTCR_DCYC                   XSPI_WTCR_DCYC_Msk                   /*!< Number of Dummy Cycles */
41200 
41201 /****************  Bit definition for XSPI_WIR register  *******************/
41202 #define XSPI_WIR_INSTRUCTION_Pos         (0U)
41203 #define XSPI_WIR_INSTRUCTION_Msk         (0xFFFFFFFFUL << XSPI_WIR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */
41204 #define XSPI_WIR_INSTRUCTION             XSPI_WIR_INSTRUCTION_Msk             /*!< Instruction */
41205 
41206 /****************  Bit definition for XSPI_WABR register  ******************/
41207 #define XSPI_WABR_ALTERNATE_Pos          (0U)
41208 #define XSPI_WABR_ALTERNATE_Msk          (0xFFFFFFFFUL << XSPI_WABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
41209 #define XSPI_WABR_ALTERNATE              XSPI_WABR_ALTERNATE_Msk              /*!< Alternate Bytes */
41210 
41211 /****************  Bit definition for XSPI_HLCR register  ******************/
41212 #define XSPI_HLCR_LM_Pos                 (0U)
41213 #define XSPI_HLCR_LM_Msk                 (0x1UL << XSPI_HLCR_LM_Pos)          /*!< 0x00000001 */
41214 #define XSPI_HLCR_LM                     XSPI_HLCR_LM_Msk                     /*!< Latency Mode */
41215 #define XSPI_HLCR_WZL_Pos                (1U)
41216 #define XSPI_HLCR_WZL_Msk                (0x1UL << XSPI_HLCR_WZL_Pos)         /*!< 0x00000002 */
41217 #define XSPI_HLCR_WZL                    XSPI_HLCR_WZL_Msk                    /*!< Write Zero Latency */
41218 #define XSPI_HLCR_TACC_Pos               (8U)
41219 #define XSPI_HLCR_TACC_Msk               (0xFFUL << XSPI_HLCR_TACC_Pos)       /*!< 0x0000FF00 */
41220 #define XSPI_HLCR_TACC                   XSPI_HLCR_TACC_Msk                   /*!< Access Time */
41221 #define XSPI_HLCR_TRWR_Pos               (16U)
41222 #define XSPI_HLCR_TRWR_Msk               (0xFFUL << XSPI_HLCR_TRWR_Pos)       /*!< 0x00FF0000 */
41223 #define XSPI_HLCR_TRWR                   XSPI_HLCR_TRWR_Msk                   /*!< Read Write Recovery Time */
41224 
41225 /****************  Bit definition for XSPI_CALFCR register  ****************/
41226 #define XSPI_CALFCR_FINE_Pos             (0U)
41227 #define XSPI_CALFCR_FINE_Msk             (0x7FUL << XSPI_CALFCR_FINE_Pos)     /*!< 0x0000007F */
41228 #define XSPI_CALFCR_FINE                 XSPI_CALFCR_FINE_Msk                 /*!< Fine Calibration */
41229 #define XSPI_CALFCR_COARSE_Pos           (16U)
41230 #define XSPI_CALFCR_COARSE_Msk           (0x1FUL << XSPI_CALFCR_COARSE_Pos)   /*!< 0x001F0000 */
41231 #define XSPI_CALFCR_COARSE               XSPI_CALFCR_COARSE_Msk               /*!< Coarse Calibration */
41232 #define XSPI_CALFCR_CALMAX_Pos           (31U)
41233 #define XSPI_CALFCR_CALMAX_Msk           (0x1UL << XSPI_CALFCR_CALMAX_Pos)    /*!< 0x80000000 */
41234 #define XSPI_CALFCR_CALMAX               XSPI_CALFCR_CALMAX_Msk               /*!< Max Value */
41235 
41236 /****************  Bit definition for XSPI_CALMR register  *****************/
41237 #define XSPI_CALMR_FINE_Pos              (0U)
41238 #define XSPI_CALMR_FINE_Msk              (0x7FUL << XSPI_CALMR_FINE_Pos)      /*!< 0x0000007F */
41239 #define XSPI_CALMR_FINE                  XSPI_CALMR_FINE_Msk                  /*!< Fine Calibration */
41240 #define XSPI_CALMR_COARSE_Pos            (16U)
41241 #define XSPI_CALMR_COARSE_Msk            (0x1FUL << XSPI_CALMR_COARSE_Pos)    /*!< 0x001F0000 */
41242 #define XSPI_CALMR_COARSE                XSPI_CALMR_COARSE_Msk                /*!< Coarse Calibration */
41243 
41244 /****************  Bit definition for XSPI_CALSOR register  ****************/
41245 #define XSPI_CALSOR_FINE_Pos             (0U)
41246 #define XSPI_CALSOR_FINE_Msk             (0x7FUL << XSPI_CALSOR_FINE_Pos)     /*!< 0x0000007F */
41247 #define XSPI_CALSOR_FINE                 XSPI_CALSOR_FINE_Msk                 /*!< Fine Calibration */
41248 #define XSPI_CALSOR_COARSE_Pos           (16U)
41249 #define XSPI_CALSOR_COARSE_Msk           (0x1FUL << XSPI_CALSOR_COARSE_Pos)   /*!< 0x001F0000 */
41250 #define XSPI_CALSOR_COARSE               XSPI_CALSOR_COARSE_Msk               /*!< Coarse Calibration */
41251 
41252 /****************  Bit definition for XSPI_CALSIR register  ****************/
41253 #define XSPI_CALSIR_FINE_Pos             (0U)
41254 #define XSPI_CALSIR_FINE_Msk             (0x7FUL << XSPI_CALSIR_FINE_Pos)     /*!< 0x0000007F */
41255 #define XSPI_CALSIR_FINE                 XSPI_CALSIR_FINE_Msk                 /*!< Fine Calibration */
41256 #define XSPI_CALSIR_COARSE_Pos           (16U)
41257 #define XSPI_CALSIR_COARSE_Msk           (0x1FUL << XSPI_CALSIR_COARSE_Pos)   /*!< 0x001F0000 */
41258 #define XSPI_CALSIR_COARSE               XSPI_CALSIR_COARSE_Msk               /*!< Coarse Calibration */
41259 
41260 /******************************************************************************/
41261 /*                                                                            */
41262 /*                                 XSPIM                                      */
41263 /*                                                                            */
41264 /******************************************************************************/
41265 /***************  Bit definition for XSPIM_CR register  ********************/
41266 #define XSPIM_CR_MUXEN_Pos               (0U)
41267 #define XSPIM_CR_MUXEN_Msk               (0x1UL << XSPIM_CR_MUXEN_Pos)        /*!< 0x00000001 */
41268 #define XSPIM_CR_MUXEN                   XSPIM_CR_MUXEN_Msk                   /*!< Multiplexed Mode Enable */
41269 #define XSPIM_CR_MODE_Pos                (1U)
41270 #define XSPIM_CR_MODE_Msk                (0x1UL << XSPIM_CR_MODE_Pos)         /*!< 0x00000002 */
41271 #define XSPIM_CR_MODE                    XSPIM_CR_MODE_Msk                    /*!< Multiplexing Mode */
41272 #define XSPIM_CR_CSSEL_OVR_EN_Pos        (4U)
41273 #define XSPIM_CR_CSSEL_OVR_EN_Msk        (0x1UL << XSPIM_CR_CSSEL_OVR_EN_Pos) /*!< 0x00000010 */
41274 #define XSPIM_CR_CSSEL_OVR_EN            XSPIM_CR_CSSEL_OVR_EN_Msk            /*!< Chip Select Selector Override Enable */
41275 #define XSPIM_CR_CSSEL_OVR_O1_Pos        (5U)
41276 #define XSPIM_CR_CSSEL_OVR_O1_Msk        (0x1UL << XSPIM_CR_CSSEL_OVR_O1_Pos) /*!< 0x00000020 */
41277 #define XSPIM_CR_CSSEL_OVR_O1            XSPIM_CR_CSSEL_OVR_O1_Msk            /*!< Chip Select Selector Override Setting For XSPI1 */
41278 #define XSPIM_CR_CSSEL_OVR_O2_Pos        (6U)
41279 #define XSPIM_CR_CSSEL_OVR_O2_Msk        (0x1UL << XSPIM_CR_CSSEL_OVR_O2_Pos) /*!< 0x00000040 */
41280 #define XSPIM_CR_CSSEL_OVR_O2            XSPIM_CR_CSSEL_OVR_O2_Msk            /*!< Chip Select Selector Override Setting For XSPI2 */
41281 #define XSPIM_CR_REQ2ACK_TIME_Pos        (16U)
41282 #define XSPIM_CR_REQ2ACK_TIME_Msk        (0xFFUL << XSPIM_CR_REQ2ACK_TIME_Pos)/*!< 0x00FF0000 */
41283 #define XSPIM_CR_REQ2ACK_TIME            XSPIM_CR_REQ2ACK_TIME_Msk            /*!< REQ to ACK Time */
41284 
41285 /** @} */ /* End of group STM32N6xx_Peripheral_declaration */
41286 
41287 /** @addtogroup STM32N6xx_Peripheral_Exported_macros
41288   * @{
41289   */
41290 #if defined (CPU_IN_SECURE_STATE)
41291 /* Instances allowed from Secure state */
41292 
41293 /******************************* ADC Instances *******************************/
41294 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_S) || ((INSTANCE) == ADC1_NS) || \
41295                                        ((INSTANCE) == ADC2_S) || ((INSTANCE) == ADC2_NS))
41296 
41297 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_S) || ((INSTANCE) == ADC1_NS))
41298 
41299 #define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON_S) || ((INSTANCE) == ADC12_COMMON_NS))
41300 
41301 /****************************** BSEC Instances *******************************/
41302 #define IS_BSEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == BSEC_S)
41303 
41304 /******************************* CACHEAXI Instances ***************************/
41305 #define IS_CACHEAXI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CACHEAXI_S) || ((INSTANCE) == CACHEAXI_NS))
41306 
41307 /******************************* CRC Instances *******************************/
41308 #define IS_CRC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CRC_S) || ((INSTANCE) == CRC_NS))
41309 
41310 /******************************* DCMI Instances ******************************/
41311 #define IS_DCMI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DCMI_S) || ((INSTANCE) == DCMI_NS))
41312 
41313 /******************************* DCMIPP Instances ****************************/
41314 #define IS_DCMIPP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DCMIPP_S) || ((INSTANCE) == DCMIPP_NS))
41315 
41316 /********************************* DLYB Instances ****************************/
41317 #define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1_S) || ((INSTANCE) == DLYB_SDMMC1_NS) || \
41318                                         ((INSTANCE) == DLYB_SDMMC2_S) || ((INSTANCE) == DLYB_SDMMC2_NS))
41319 
41320 /******************************** DMA Instances ******************************/
41321 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_S) || ((INSTANCE) == GPDMA1_Channel0_NS) || \
41322                                        ((INSTANCE) == GPDMA1_Channel1_S) || ((INSTANCE) == GPDMA1_Channel1_NS) || \
41323                                        ((INSTANCE) == GPDMA1_Channel2_S) || ((INSTANCE) == GPDMA1_Channel2_NS) || \
41324                                        ((INSTANCE) == GPDMA1_Channel3_S) || ((INSTANCE) == GPDMA1_Channel3_NS) || \
41325                                        ((INSTANCE) == GPDMA1_Channel4_S) || ((INSTANCE) == GPDMA1_Channel4_NS) || \
41326                                        ((INSTANCE) == GPDMA1_Channel5_S) || ((INSTANCE) == GPDMA1_Channel5_NS) || \
41327                                        ((INSTANCE) == GPDMA1_Channel6_S) || ((INSTANCE) == GPDMA1_Channel6_NS) || \
41328                                        ((INSTANCE) == GPDMA1_Channel7_S) || ((INSTANCE) == GPDMA1_Channel7_NS) || \
41329                                        ((INSTANCE) == GPDMA1_Channel8_S) || ((INSTANCE) == GPDMA1_Channel8_NS) || \
41330                                        ((INSTANCE) == GPDMA1_Channel9_S) || ((INSTANCE) == GPDMA1_Channel9_NS) || \
41331                                        ((INSTANCE) == GPDMA1_Channel10_S) || ((INSTANCE) == GPDMA1_Channel10_NS) || \
41332                                        ((INSTANCE) == GPDMA1_Channel11_S) || ((INSTANCE) == GPDMA1_Channel11_NS) || \
41333                                        ((INSTANCE) == GPDMA1_Channel12_S) || ((INSTANCE) == GPDMA1_Channel12_NS) || \
41334                                        ((INSTANCE) == GPDMA1_Channel13_S) || ((INSTANCE) == GPDMA1_Channel13_NS) || \
41335                                        ((INSTANCE) == GPDMA1_Channel14_S) || ((INSTANCE) == GPDMA1_Channel14_NS) || \
41336                                        ((INSTANCE) == GPDMA1_Channel15_S) || ((INSTANCE) == GPDMA1_Channel15_NS) || \
41337                                        ((INSTANCE) == HPDMA1_Channel0_S) || ((INSTANCE) == HPDMA1_Channel0_NS) || \
41338                                        ((INSTANCE) == HPDMA1_Channel1_S) || ((INSTANCE) == HPDMA1_Channel1_NS) || \
41339                                        ((INSTANCE) == HPDMA1_Channel2_S) || ((INSTANCE) == HPDMA1_Channel2_NS) || \
41340                                        ((INSTANCE) == HPDMA1_Channel3_S) || ((INSTANCE) == HPDMA1_Channel3_NS) || \
41341                                        ((INSTANCE) == HPDMA1_Channel4_S) || ((INSTANCE) == HPDMA1_Channel4_NS) || \
41342                                        ((INSTANCE) == HPDMA1_Channel5_S) || ((INSTANCE) == HPDMA1_Channel5_NS) || \
41343                                        ((INSTANCE) == HPDMA1_Channel6_S) || ((INSTANCE) == HPDMA1_Channel6_NS) || \
41344                                        ((INSTANCE) == HPDMA1_Channel7_S) || ((INSTANCE) == HPDMA1_Channel7_NS) || \
41345                                        ((INSTANCE) == HPDMA1_Channel8_S) || ((INSTANCE) == HPDMA1_Channel8_NS) || \
41346                                        ((INSTANCE) == HPDMA1_Channel9_S) || ((INSTANCE) == HPDMA1_Channel9_NS) || \
41347                                        ((INSTANCE) == HPDMA1_Channel10_S) || ((INSTANCE) == HPDMA1_Channel10_NS) || \
41348                                        ((INSTANCE) == HPDMA1_Channel11_S) || ((INSTANCE) == HPDMA1_Channel11_NS) || \
41349                                        ((INSTANCE) == HPDMA1_Channel12_S) || ((INSTANCE) == HPDMA1_Channel12_NS) || \
41350                                        ((INSTANCE) == HPDMA1_Channel13_S) || ((INSTANCE) == HPDMA1_Channel13_NS) || \
41351                                        ((INSTANCE) == HPDMA1_Channel14_S) || ((INSTANCE) == HPDMA1_Channel14_NS) || \
41352                                        ((INSTANCE) == HPDMA1_Channel15_S) || ((INSTANCE) == HPDMA1_Channel15_NS))
41353 
41354 #define IS_GPDMA_INSTANCE(INSTANCE)  (((INSTANCE) == GPDMA1_Channel0_S) || ((INSTANCE) == GPDMA1_Channel0_NS) || \
41355                                       ((INSTANCE) == GPDMA1_Channel1_S) || ((INSTANCE) == GPDMA1_Channel1_NS) || \
41356                                       ((INSTANCE) == GPDMA1_Channel2_S) || ((INSTANCE) == GPDMA1_Channel2_NS) || \
41357                                       ((INSTANCE) == GPDMA1_Channel3_S) || ((INSTANCE) == GPDMA1_Channel3_NS) || \
41358                                       ((INSTANCE) == GPDMA1_Channel4_S) || ((INSTANCE) == GPDMA1_Channel4_NS) || \
41359                                       ((INSTANCE) == GPDMA1_Channel5_S) || ((INSTANCE) == GPDMA1_Channel5_NS) || \
41360                                       ((INSTANCE) == GPDMA1_Channel6_S) || ((INSTANCE) == GPDMA1_Channel6_NS) || \
41361                                       ((INSTANCE) == GPDMA1_Channel7_S) || ((INSTANCE) == GPDMA1_Channel7_NS) || \
41362                                       ((INSTANCE) == GPDMA1_Channel8_S) || ((INSTANCE) == GPDMA1_Channel8_NS) || \
41363                                       ((INSTANCE) == GPDMA1_Channel9_S) || ((INSTANCE) == GPDMA1_Channel9_NS) || \
41364                                       ((INSTANCE) == GPDMA1_Channel10_S) || ((INSTANCE) == GPDMA1_Channel10_NS) || \
41365                                       ((INSTANCE) == GPDMA1_Channel11_S) || ((INSTANCE) == GPDMA1_Channel11_NS) || \
41366                                       ((INSTANCE) == GPDMA1_Channel12_S) || ((INSTANCE) == GPDMA1_Channel12_NS) || \
41367                                       ((INSTANCE) == GPDMA1_Channel13_S) || ((INSTANCE) == GPDMA1_Channel13_NS) || \
41368                                       ((INSTANCE) == GPDMA1_Channel14_S) || ((INSTANCE) == GPDMA1_Channel14_NS) || \
41369                                       ((INSTANCE) == GPDMA1_Channel15_S) || ((INSTANCE) == GPDMA1_Channel15_NS))
41370 
41371 #define IS_HPDMA_INSTANCE(INSTANCE)  (((INSTANCE) == HPDMA1_Channel0_S) || ((INSTANCE) == HPDMA1_Channel0_NS) || \
41372                                       ((INSTANCE) == HPDMA1_Channel1_S) || ((INSTANCE) == HPDMA1_Channel1_NS) || \
41373                                       ((INSTANCE) == HPDMA1_Channel2_S) || ((INSTANCE) == HPDMA1_Channel2_NS) || \
41374                                       ((INSTANCE) == HPDMA1_Channel3_S) || ((INSTANCE) == HPDMA1_Channel3_NS) || \
41375                                       ((INSTANCE) == HPDMA1_Channel4_S) || ((INSTANCE) == HPDMA1_Channel4_NS) || \
41376                                       ((INSTANCE) == HPDMA1_Channel5_S) || ((INSTANCE) == HPDMA1_Channel5_NS) || \
41377                                       ((INSTANCE) == HPDMA1_Channel6_S) || ((INSTANCE) == HPDMA1_Channel6_NS) || \
41378                                       ((INSTANCE) == HPDMA1_Channel7_S) || ((INSTANCE) == HPDMA1_Channel7_NS) || \
41379                                       ((INSTANCE) == HPDMA1_Channel8_S) || ((INSTANCE) == HPDMA1_Channel8_NS) || \
41380                                       ((INSTANCE) == HPDMA1_Channel9_S) || ((INSTANCE) == HPDMA1_Channel9_NS) || \
41381                                       ((INSTANCE) == HPDMA1_Channel10_S) || ((INSTANCE) == HPDMA1_Channel10_NS) || \
41382                                       ((INSTANCE) == HPDMA1_Channel11_S) || ((INSTANCE) == HPDMA1_Channel11_NS) || \
41383                                       ((INSTANCE) == HPDMA1_Channel12_S) || ((INSTANCE) == HPDMA1_Channel12_NS) || \
41384                                       ((INSTANCE) == HPDMA1_Channel13_S) || ((INSTANCE) == HPDMA1_Channel13_NS) || \
41385                                       ((INSTANCE) == HPDMA1_Channel14_S) || ((INSTANCE) == HPDMA1_Channel14_NS) || \
41386                                       ((INSTANCE) == HPDMA1_Channel15_S) || ((INSTANCE) == HPDMA1_Channel15_NS))
41387 
41388 #define IS_DMA_2D_ADDRESSING_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel12_S) || ((INSTANCE) == GPDMA1_Channel12_NS) || \
41389                                                  ((INSTANCE) == GPDMA1_Channel13_S) || ((INSTANCE) == GPDMA1_Channel13_NS) || \
41390                                                  ((INSTANCE) == GPDMA1_Channel14_S) || ((INSTANCE) == GPDMA1_Channel14_NS) || \
41391                                                  ((INSTANCE) == GPDMA1_Channel15_S) || ((INSTANCE) == GPDMA1_Channel15_NS) || \
41392                                                  ((INSTANCE) == HPDMA1_Channel12_S) || ((INSTANCE) == HPDMA1_Channel12_NS) || \
41393                                                  ((INSTANCE) == HPDMA1_Channel13_S) || ((INSTANCE) == HPDMA1_Channel13_NS) || \
41394                                                  ((INSTANCE) == HPDMA1_Channel14_S) || ((INSTANCE) == HPDMA1_Channel14_NS) || \
41395                                                  ((INSTANCE) == HPDMA1_Channel15_S) || ((INSTANCE) == HPDMA1_Channel15_NS))
41396 
41397 #define IS_DMA_LIMIT_INSTANCE(INSTANCE) (((INSTANCE) == HPDMA1_Channel12_S) || ((INSTANCE) == HPDMA1_Channel12_NS) || \
41398                                          ((INSTANCE) == HPDMA1_Channel13_S) || ((INSTANCE) == HPDMA1_Channel13_NS) || \
41399                                          ((INSTANCE) == HPDMA1_Channel14_S) || ((INSTANCE) == HPDMA1_Channel14_NS) || \
41400                                          ((INSTANCE) == HPDMA1_Channel15_S) || ((INSTANCE) == HPDMA1_Channel15_NS))
41401 
41402 #define IS_DMA_PFREQ_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_S)  || ((INSTANCE) == GPDMA1_Channel0_NS)  || \
41403                                          ((INSTANCE) == GPDMA1_Channel1_S)  || ((INSTANCE) == GPDMA1_Channel1_NS)  || \
41404                                          ((INSTANCE) == GPDMA1_Channel15_S) || ((INSTANCE) == GPDMA1_Channel15_NS) || \
41405                                          ((INSTANCE) == HPDMA1_Channel0_S)  || ((INSTANCE) == HPDMA1_Channel0_NS)  || \
41406                                          ((INSTANCE) == HPDMA1_Channel1_S)  || ((INSTANCE) == HPDMA1_Channel1_NS)  || \
41407                                          ((INSTANCE) == HPDMA1_Channel15_S) || ((INSTANCE) == HPDMA1_Channel15_NS))
41408 
41409 /******************************* DMA2D Instances *****************************/
41410 #define IS_DMA2D_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA2D_S) || ((INSTANCE) == DMA2D_NS))
41411 
41412 /******************************* DTS Instances *****************************/
41413 #define IS_DTS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DTS_S) || ((INSTANCE) == DTS_NS))
41414 
41415 /******************************* ETH Instances *******************************/
41416 #define IS_ETH_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ETH1_S) || ((INSTANCE) == ETH1_NS))
41417 
41418 /******************************* FDCAN Instances *****************************/
41419 #define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1_S) || ((INSTANCE) == FDCAN1_NS) || \
41420                                          ((INSTANCE) == FDCAN2_S) || ((INSTANCE) == FDCAN2_NS) || \
41421                                          ((INSTANCE) == FDCAN3_S) || ((INSTANCE) == FDCAN3_NS))
41422 
41423 #define IS_FDCAN_CONFIG_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN_CONFIG_S) || ((INSTANCE) == FDCAN_CONFIG_NS))
41424 
41425 #define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1_S)
41426 
41427 /******************************* GFXMMU Instance *****************************/
41428 #define IS_GFXMMU_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GFXMMU_S) || ((INSTANCE) == GFXMMU_NS))
41429 
41430 /******************************* GFXTIM Instance *****************************/
41431 #define IS_GFXTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GFXTIM_S) || ((INSTANCE) == GFXTIM_NS))
41432 
41433 /********************************* GPIO Instances ****************************/
41434 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_S) || ((INSTANCE) == GPIOA_NS) || \
41435                                         ((INSTANCE) == GPIOB_S) || ((INSTANCE) == GPIOB_NS) || \
41436                                         ((INSTANCE) == GPIOC_S) || ((INSTANCE) == GPIOC_NS) || \
41437                                         ((INSTANCE) == GPIOD_S) || ((INSTANCE) == GPIOD_NS) || \
41438                                         ((INSTANCE) == GPIOE_S) || ((INSTANCE) == GPIOE_NS) || \
41439                                         ((INSTANCE) == GPIOF_S) || ((INSTANCE) == GPIOF_NS) || \
41440                                         ((INSTANCE) == GPIOG_S) || ((INSTANCE) == GPIOG_NS) || \
41441                                         ((INSTANCE) == GPIOH_S) || ((INSTANCE) == GPIOH_NS) || \
41442                                         ((INSTANCE) == GPION_S) || ((INSTANCE) == GPION_NS) || \
41443                                         ((INSTANCE) == GPIOO_S) || ((INSTANCE) == GPIOO_NS) || \
41444                                         ((INSTANCE) == GPIOP_S) || ((INSTANCE) == GPIOP_NS) || \
41445                                         ((INSTANCE) == GPIOQ_S) || ((INSTANCE) == GPIOQ_NS))
41446 
41447 /******************************* GPIO AF Instances ***************************/
41448 /* All GPIO Banks support AF */
41449 #define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
41450 
41451 /**************************** GPIO Lock Instances ****************************/
41452 /* All GPIO Banks support the Lock mechanism */
41453 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
41454 
41455 /******************************* GPU2D Instances *****************************/
41456 #define IS_GPU2D_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPU2D_BASE_S) || ((INSTANCE) == GPU2D_BASE_NS))
41457 
41458 /******************************** I2C Instances ******************************/
41459 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_S) || ((INSTANCE) == I2C1_NS) || \
41460                                        ((INSTANCE) == I2C2_S) || ((INSTANCE) == I2C2_NS) || \
41461                                        ((INSTANCE) == I2C3_S) || ((INSTANCE) == I2C3_NS) || \
41462                                        ((INSTANCE) == I2C4_S) || ((INSTANCE) == I2C4_NS))
41463 
41464 /****************** I2C Instances : wakeup capability from stop modes ********/
41465 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
41466 
41467 /******************************** I3C Instances *******************************/
41468 #define IS_I3C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I3C1_S) || ((INSTANCE) == I3C1_NS) || \
41469                                        ((INSTANCE) == I3C2_S) || ((INSTANCE) == I3C2_NS))
41470 
41471 /****************************** IWDG Instances *******************************/
41472 #define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG_S) || ((INSTANCE) == IWDG_NS))
41473 
41474 /******************************* JPEG Instances ******************************/
41475 #define IS_JPEG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == JPEG_S) || ((INSTANCE) == JPEG_NS))
41476 
41477 /****************************** LTDC Instances *******************************/
41478 #define IS_LTDC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == LTDC_S) || ((INSTANCE) == LTDC_NS))
41479 
41480 /******************************* MCE Instances *******************************/
41481 #define IS_MCE_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MCE1_S) || ((INSTANCE) == MCE1_NS) || \
41482                                        ((INSTANCE) == MCE2_S) || ((INSTANCE) == MCE2_NS) || \
41483                                        ((INSTANCE) == MCE3_S) || ((INSTANCE) == MCE3_NS) || \
41484                                        ((INSTANCE) == MCE4_S) || ((INSTANCE) == MCE4_NS))
41485 
41486 /******************************* MDF/ADF Instances ***************************/
41487 #define IS_MDF_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDF1_Filter0_S) || ((INSTANCE) == MDF1_Filter0_NS) || \
41488                                        ((INSTANCE) == MDF1_Filter1_S) || ((INSTANCE) == MDF1_Filter1_NS) || \
41489                                        ((INSTANCE) == MDF1_Filter2_S) || ((INSTANCE) == MDF1_Filter2_NS) || \
41490                                        ((INSTANCE) == MDF1_Filter3_S) || ((INSTANCE) == MDF1_Filter3_NS) || \
41491                                        ((INSTANCE) == MDF1_Filter4_S) || ((INSTANCE) == MDF1_Filter4_NS) || \
41492                                        ((INSTANCE) == MDF1_Filter5_S) || ((INSTANCE) == MDF1_Filter5_NS) || \
41493                                        ((INSTANCE) == ADF1_Filter0_S) || ((INSTANCE) == ADF1_Filter0_NS))
41494 
41495 /****************************** MDIOS Instances ******************************/
41496 #define IS_MDIOS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDIOS_S) || ((INSTANCE) == MDIOS_NS))
41497 
41498 /******************************* PKA Instances *******************************/
41499 #define IS_PKA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PKA_S) || ((INSTANCE) == PKA_NS))
41500 
41501 /******************************* PSSI Instances ******************************/
41502 #define IS_PSSI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PSSI_S) || ((INSTANCE) == PSSI_NS))
41503 
41504 /****************************** RAMCFG Instances ********************************/
41505 #define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_AHB_S)  || ((INSTANCE) == RAMCFG_SRAM1_AHB_NS)  || \
41506                                           ((INSTANCE) == RAMCFG_SRAM2_AHB_S)  || ((INSTANCE) == RAMCFG_SRAM2_AHB_NS)  || \
41507                                           ((INSTANCE) == RAMCFG_SRAM1_AXI_S)  || ((INSTANCE) == RAMCFG_SRAM1_AXI_NS)  || \
41508                                           ((INSTANCE) == RAMCFG_SRAM2_AXI_S)  || ((INSTANCE) == RAMCFG_SRAM2_AXI_NS)  || \
41509                                           ((INSTANCE) == RAMCFG_SRAM3_AXI_S)  || ((INSTANCE) == RAMCFG_SRAM3_AXI_NS)  || \
41510                                           ((INSTANCE) == RAMCFG_SRAM4_AXI_S)  || ((INSTANCE) == RAMCFG_SRAM4_AXI_NS)  || \
41511                                           ((INSTANCE) == RAMCFG_SRAM5_AXI_S)  || ((INSTANCE) == RAMCFG_SRAM5_AXI_NS)  || \
41512                                           ((INSTANCE) == RAMCFG_SRAM6_AXI_S)  || ((INSTANCE) == RAMCFG_SRAM6_AXI_NS)  || \
41513                                           ((INSTANCE) == RAMCFG_BKPSRAM_S)    || ((INSTANCE) == RAMCFG_BKPSRAM_NS)    || \
41514                                           ((INSTANCE) == RAMCFG_FLEXRAM_S)    || ((INSTANCE) == RAMCFG_FLEXRAM_NS)    || \
41515                                           ((INSTANCE) == RAMCFG_VENC_RAM_S)   || ((INSTANCE) == RAMCFG_VENC_RAM_NS))
41516 
41517 /***************************** RAMCFG ECC Instances *****************************/
41518 #define IS_RAMCFG_ECC_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_BKPSRAM_S)  || ((INSTANCE) == RAMCFG_BKPSRAM_NS)  || \
41519                                           ((INSTANCE) == RAMCFG_FLEXRAM_S)  || ((INSTANCE) == RAMCFG_FLEXRAM_NS))
41520 
41521 /***************************** RAMCFG AXISRAM POWERDOWN Instances ***************/
41522 #define IS_RAMCFG_AXISRAM_POWERDOWN_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_AXI_S) || ((INSTANCE) == RAMCFG_SRAM2_AXI_NS) || \
41523                                                         ((INSTANCE) == RAMCFG_SRAM3_AXI_S) || ((INSTANCE) == RAMCFG_SRAM3_AXI_NS) || \
41524                                                         ((INSTANCE) == RAMCFG_SRAM4_AXI_S) || ((INSTANCE) == RAMCFG_SRAM4_AXI_NS) || \
41525                                                         ((INSTANCE) == RAMCFG_SRAM5_AXI_S) || ((INSTANCE) == RAMCFG_SRAM5_AXI_NS) || \
41526                                                         ((INSTANCE) == RAMCFG_SRAM6_AXI_S) || ((INSTANCE) == RAMCFG_SRAM6_AXI_NS))
41527 
41528 /******************************* RNG Instances *******************************/
41529 #define IS_RNG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RNG_S) || ((INSTANCE) == RNG_NS))
41530 
41531 /******************************* RTC Instances *******************************/
41532 #define IS_RTC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RTC_S) || ((INSTANCE) == RTC_NS))
41533 
41534 /******************************** SAI Instances ******************************/
41535 #define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_S) || ((INSTANCE) == SAI1_Block_A_NS) || \
41536                                        ((INSTANCE) == SAI1_Block_B_S) || ((INSTANCE) == SAI1_Block_B_NS) || \
41537                                        ((INSTANCE) == SAI2_Block_A_S) || ((INSTANCE) == SAI2_Block_A_NS) || \
41538                                        ((INSTANCE) == SAI2_Block_B_S) || ((INSTANCE) == SAI2_Block_B_NS))
41539 
41540 /******************************* SDMMC Instances *****************************/
41541 #define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1_S) || ((INSTANCE) == SDMMC1_NS) || \
41542                                          ((INSTANCE) == SDMMC2_S) || ((INSTANCE) == SDMMC2_NS))
41543 
41544 /******************************** SMBUS Instances ****************************/
41545 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_S) || ((INSTANCE) == I2C1_NS) || \
41546                                          ((INSTANCE) == I2C2_S) || ((INSTANCE) == I2C2_NS) || \
41547                                          ((INSTANCE) == I2C3_S) || ((INSTANCE) == I2C3_NS) || \
41548                                          ((INSTANCE) == I2C4_S) || ((INSTANCE) == I2C4_NS))
41549 
41550 /****************************** SPDIFRX Instances ****************************/
41551 #define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPDIFRX_S) || ((INSTANCE) == SPDIFRX_NS))
41552 
41553 /******************************** SPI Instances ******************************/
41554 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_S) || ((INSTANCE) == SPI1_NS) || \
41555                                        ((INSTANCE) == SPI2_S) || ((INSTANCE) == SPI2_NS) || \
41556                                        ((INSTANCE) == SPI3_S) || ((INSTANCE) == SPI3_NS) || \
41557                                        ((INSTANCE) == SPI4_S) || ((INSTANCE) == SPI4_NS) || \
41558                                        ((INSTANCE) == SPI5_S) || ((INSTANCE) == SPI5_NS) || \
41559                                        ((INSTANCE) == SPI6_S) || ((INSTANCE) == SPI6_NS))
41560 
41561 #define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_S) || ((INSTANCE) == SPI1_NS) || \
41562                                         ((INSTANCE) == SPI2_S) || ((INSTANCE) == SPI2_NS) || \
41563                                         ((INSTANCE) == SPI3_S) || ((INSTANCE) == SPI3_NS) || \
41564                                         ((INSTANCE) == SPI6_S) || ((INSTANCE) == SPI6_NS))
41565 
41566 #define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI4_S) || ((INSTANCE) == SPI4_NS) || \
41567                                            ((INSTANCE) == SPI5_S) || ((INSTANCE) == SPI5_NS))
41568 
41569 /******************************** I2S Instances ******************************/
41570 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_S) || ((INSTANCE) == SPI1_NS) || \
41571                                        ((INSTANCE) == SPI2_S) || ((INSTANCE) == SPI2_NS) || \
41572                                        ((INSTANCE) == SPI3_S) || ((INSTANCE) == SPI3_NS) || \
41573                                        ((INSTANCE) == SPI6_S) || ((INSTANCE) == SPI6_NS))
41574 
41575 /****************************** UCPD Instances *******************************/
41576 #define IS_UCPD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == UCPD1_S) || ((INSTANCE) == UCPD1_NS))
41577 
41578 /******************************* OTG HS HCD Instances *************************/
41579 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB1_OTG_HS_S) || ((INSTANCE) == USB1_OTG_HS_NS) || \
41580                                        ((INSTANCE) == USB2_OTG_HS_S) || ((INSTANCE) == USB2_OTG_HS_NS))
41581 
41582 /******************************* OTG HS PCD Instances *************************/
41583 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB1_OTG_HS_S) || ((INSTANCE) == USB1_OTG_HS_NS) || \
41584                                        ((INSTANCE) == USB2_OTG_HS_S) || ((INSTANCE) == USB2_OTG_HS_NS))
41585 
41586 /******************************* USB HS PHY Instances *************************/
41587 #define IS_USBPHYC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB1_HS_PHYC_S) || ((INSTANCE) == USB1_HS_PHYC_NS) || \
41588                                            ((INSTANCE) == USB2_HS_PHYC_S) || ((INSTANCE) == USB2_HS_PHYC_NS))
41589 
41590 /******************** USART Instances : Synchronous mode *********************/
41591 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS) || \
41592                                      ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS) || \
41593                                      ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS) || \
41594                                      ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS) || \
41595                                      ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS))
41596 
41597 /******************** UART Instances : Asynchronous mode *********************/
41598 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS) || \
41599                                     ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS) || \
41600                                     ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS) || \
41601                                     ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)  || \
41602                                     ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)  || \
41603                                     ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS) || \
41604                                     ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)  || \
41605                                     ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)  || \
41606                                     ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)  || \
41607                                     ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS))
41608 
41609 /*********************** UART Instances : FIFO mode **************************/
41610 #define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
41611                                          ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
41612                                          ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
41613                                          ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)   || \
41614                                          ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)   || \
41615                                          ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
41616                                          ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)   || \
41617                                          ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)   || \
41618                                          ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)   || \
41619                                          ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS) || \
41620                                          ((INSTANCE) == LPUART1_S) || ((INSTANCE) == LPUART1_NS))
41621 
41622 /*********************** UART Instances : SPI Slave mode **********************/
41623 #define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
41624                                               ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
41625                                               ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
41626                                               ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
41627                                               ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS))
41628 
41629 /****************** UART Instances : Auto Baud Rate detection ****************/
41630 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
41631                                                             ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
41632                                                             ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
41633                                                             ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)   || \
41634                                                             ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)   || \
41635                                                             ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
41636                                                             ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)   || \
41637                                                             ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)   || \
41638                                                             ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)   || \
41639                                                             ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS))
41640 
41641 /****************** UART Instances : Driver Enable ***************************/
41642 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
41643                                                   ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
41644                                                   ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
41645                                                   ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)   || \
41646                                                   ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)   || \
41647                                                   ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
41648                                                   ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)   || \
41649                                                   ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)   || \
41650                                                   ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)   || \
41651                                                   ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS) || \
41652                                                   ((INSTANCE) == LPUART1_S) || ((INSTANCE) == LPUART1_NS))
41653 
41654 /******************** UART Instances : Half-Duplex mode **********************/
41655 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
41656                                                ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
41657                                                ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
41658                                                ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)   || \
41659                                                ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)   || \
41660                                                ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
41661                                                ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)   || \
41662                                                ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)   || \
41663                                                ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)   || \
41664                                                ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS) || \
41665                                                ((INSTANCE) == LPUART1_S) || ((INSTANCE) == LPUART1_NS))
41666 
41667 /****************** UART Instances : Hardware Flow control *******************/
41668 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
41669                                            ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
41670                                            ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
41671                                            ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)   || \
41672                                            ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)   || \
41673                                            ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
41674                                            ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)   || \
41675                                            ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)   || \
41676                                            ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)   || \
41677                                            ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS) || \
41678                                            ((INSTANCE) == LPUART1_S) || ((INSTANCE) == LPUART1_NS))
41679 
41680 /******************** UART Instances : LIN mode ******************************/
41681 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
41682                                         ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
41683                                         ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
41684                                         ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)   || \
41685                                         ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)   || \
41686                                         ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
41687                                         ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)   || \
41688                                         ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)   || \
41689                                         ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)   || \
41690                                         ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS))
41691 
41692 /******************** UART Instances : Wake-up from Stop mode ****************/
41693 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
41694                                                     ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
41695                                                     ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
41696                                                     ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)   || \
41697                                                     ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)   || \
41698                                                     ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
41699                                                     ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)   || \
41700                                                     ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)   || \
41701                                                     ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)   || \
41702                                                     ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS) || \
41703                                                     ((INSTANCE) == LPUART1_S) || ((INSTANCE) == LPUART1_NS))
41704 
41705 /*********************** UART Instances : IRDA mode **************************/
41706 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
41707                                     ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
41708                                     ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
41709                                     ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)   || \
41710                                     ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)   || \
41711                                     ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
41712                                     ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)   || \
41713                                     ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)   || \
41714                                     ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)   || \
41715                                     ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS))
41716 
41717 /********************* USART Instances : Smard card mode *********************/
41718 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
41719                                          ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
41720                                          ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
41721                                          ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
41722                                          ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS))
41723 
41724 /******************** LPUART Instance ****************************************/
41725 #define IS_LPUART_INSTANCE(INSTANCE) (((INSTANCE) == LPUART1_S) || ((INSTANCE) == LPUART1_NS))
41726 
41727 /****************** LPTIM Instances : All supported instances *****************/
41728 #define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1_S) || ((INSTANCE) == LPTIM1_NS) || \
41729                                          ((INSTANCE) == LPTIM2_S) || ((INSTANCE) == LPTIM2_NS) || \
41730                                          ((INSTANCE) == LPTIM3_S) || ((INSTANCE) == LPTIM3_NS) || \
41731                                          ((INSTANCE) == LPTIM4_S) || ((INSTANCE) == LPTIM4_NS) || \
41732                                          ((INSTANCE) == LPTIM5_S) || ((INSTANCE) == LPTIM5_NS))
41733 
41734 /****************** LPTIM Instances : DMA supported instances *****************/
41735 #define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_S) || ((INSTANCE) == LPTIM1_NS) || \
41736                                          ((INSTANCE) == LPTIM2_S) || ((INSTANCE) == LPTIM2_NS) || \
41737                                          ((INSTANCE) == LPTIM3_S) || ((INSTANCE) == LPTIM3_NS))
41738 
41739 /************* LPTIM Instances : at least 1 capture/compare channel ***********/
41740 #define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_S) || ((INSTANCE) == LPTIM1_NS) || \
41741                                          ((INSTANCE) == LPTIM2_S) || ((INSTANCE) == LPTIM2_NS) || \
41742                                          ((INSTANCE) == LPTIM3_S) || ((INSTANCE) == LPTIM3_NS) || \
41743                                          ((INSTANCE) == LPTIM4_S) || ((INSTANCE) == LPTIM4_NS) || \
41744                                          ((INSTANCE) == LPTIM5_S) || ((INSTANCE) == LPTIM5_NS))
41745 
41746 /************* LPTIM Instances : at least 2 capture/compare channel ***********/
41747 #define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_S) || ((INSTANCE) == LPTIM1_NS) || \
41748                                          ((INSTANCE) == LPTIM2_S) || ((INSTANCE) == LPTIM2_NS) || \
41749                                          ((INSTANCE) == LPTIM3_S) || ((INSTANCE) == LPTIM3_NS))
41750 
41751 /****************** LPTIM Instances : supporting encoder interface **************/
41752 #define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_S) || ((INSTANCE) == LPTIM1_NS) || \
41753                                                        ((INSTANCE) == LPTIM2_S) || ((INSTANCE) == LPTIM2_NS) || \
41754                                                        ((INSTANCE) == LPTIM3_S) || ((INSTANCE) == LPTIM3_NS))
41755 
41756 
41757 /****************** LPTIM Instances : supporting Input Capture **************/
41758 #define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_S) || ((INSTANCE) == LPTIM1_NS) || \
41759                                                    ((INSTANCE) == LPTIM2_S) || ((INSTANCE) == LPTIM2_NS) || \
41760                                                    ((INSTANCE) == LPTIM3_S) || ((INSTANCE) == LPTIM3_NS))
41761 
41762 /****************** TIM Instances : All supported instances *******************/
41763 #define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1_S)   || ((INSTANCE) == TIM1_NS)  || \
41764                                          ((INSTANCE) == TIM2_S)   || ((INSTANCE) == TIM2_NS)  || \
41765                                          ((INSTANCE) == TIM3_S)   || ((INSTANCE) == TIM3_NS)  || \
41766                                          ((INSTANCE) == TIM4_S)   || ((INSTANCE) == TIM4_NS)  || \
41767                                          ((INSTANCE) == TIM5_S)   || ((INSTANCE) == TIM5_NS)  || \
41768                                          ((INSTANCE) == TIM6_S)   || ((INSTANCE) == TIM6_NS)  || \
41769                                          ((INSTANCE) == TIM7_S)   || ((INSTANCE) == TIM7_NS)  || \
41770                                          ((INSTANCE) == TIM8_S)   || ((INSTANCE) == TIM8_NS)  || \
41771                                          ((INSTANCE) == TIM9_S)   || ((INSTANCE) == TIM9_NS)  || \
41772                                          ((INSTANCE) == TIM10_S)  || ((INSTANCE) == TIM10_NS) || \
41773                                          ((INSTANCE) == TIM11_S)  || ((INSTANCE) == TIM11_NS) || \
41774                                          ((INSTANCE) == TIM12_S)  || ((INSTANCE) == TIM12_NS) || \
41775                                          ((INSTANCE) == TIM13_S)  || ((INSTANCE) == TIM13_NS) || \
41776                                          ((INSTANCE) == TIM14_S)  || ((INSTANCE) == TIM14_NS) || \
41777                                          ((INSTANCE) == TIM15_S)  || ((INSTANCE) == TIM15_NS) || \
41778                                          ((INSTANCE) == TIM16_S)  || ((INSTANCE) == TIM16_NS) || \
41779                                          ((INSTANCE) == TIM17_S)  || ((INSTANCE) == TIM17_NS) || \
41780                                          ((INSTANCE) == TIM18_S)  || ((INSTANCE) == TIM18_NS))
41781 
41782 /****************** TIM Instances : supporting 32 bits counter ****************/
41783 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
41784                                                ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
41785                                                ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
41786                                                ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS))
41787 
41788 /****************** TIM Instances : supporting the break function *************/
41789 #define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
41790                                             ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
41791                                             ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
41792                                             ((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
41793                                             ((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
41794 
41795 /************** TIM Instances : supporting Break source selection *************/
41796 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
41797                                                ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
41798                                                ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
41799                                                ((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
41800                                                ((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
41801 
41802 /****************** TIM Instances : supporting 2 break inputs *****************/
41803 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS) || \
41804                                             ((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS))
41805 
41806 /************* TIM Instances : at least 1 capture/compare channel *************/
41807 #define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_S)   || ((INSTANCE) == TIM1_NS)  || \
41808                                          ((INSTANCE) == TIM2_S)   || ((INSTANCE) == TIM2_NS)  || \
41809                                          ((INSTANCE) == TIM3_S)   || ((INSTANCE) == TIM3_NS)  || \
41810                                          ((INSTANCE) == TIM4_S)   || ((INSTANCE) == TIM4_NS)  || \
41811                                          ((INSTANCE) == TIM5_S)   || ((INSTANCE) == TIM5_NS)  || \
41812                                          ((INSTANCE) == TIM8_S)   || ((INSTANCE) == TIM8_NS)  || \
41813                                          ((INSTANCE) == TIM9_S)   || ((INSTANCE) == TIM9_NS)  || \
41814                                          ((INSTANCE) == TIM10_S)  || ((INSTANCE) == TIM10_NS) || \
41815                                          ((INSTANCE) == TIM11_S)  || ((INSTANCE) == TIM11_NS) || \
41816                                          ((INSTANCE) == TIM12_S)  || ((INSTANCE) == TIM12_NS) || \
41817                                          ((INSTANCE) == TIM13_S)  || ((INSTANCE) == TIM13_NS) || \
41818                                          ((INSTANCE) == TIM14_S)  || ((INSTANCE) == TIM14_NS) || \
41819                                          ((INSTANCE) == TIM15_S)  || ((INSTANCE) == TIM15_NS) || \
41820                                          ((INSTANCE) == TIM16_S)  || ((INSTANCE) == TIM16_NS) || \
41821                                          ((INSTANCE) == TIM17_S)  || ((INSTANCE) == TIM17_NS))
41822 
41823 /************ TIM Instances : at least 2 capture/compare channels *************/
41824 #define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
41825                                          ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
41826                                          ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
41827                                          ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
41828                                          ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
41829                                          ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
41830                                          ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
41831                                          ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
41832                                          ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS))
41833 
41834 /************ TIM Instances : at least 3 capture/compare channels *************/
41835 #define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
41836                                          ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
41837                                          ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
41838                                          ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
41839                                          ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS) || \
41840                                          ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
41841 
41842 /************ TIM Instances : at least 4 capture/compare channels *************/
41843 #define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
41844                                          ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
41845                                          ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
41846                                          ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
41847                                          ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS) || \
41848                                          ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
41849 
41850 /****************** TIM Instances : at least 5 capture/compare channels *******/
41851 #define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
41852                                          ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
41853 
41854 /****************** TIM Instances : at least 6 capture/compare channels *******/
41855 #define IS_TIM_CC6_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
41856                                         ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
41857 
41858 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
41859 #define IS_TIM_DMA_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_S)   || ((INSTANCE) == TIM1_NS)  || \
41860                                          ((INSTANCE) == TIM2_S)   || ((INSTANCE) == TIM2_NS)  || \
41861                                          ((INSTANCE) == TIM3_S)   || ((INSTANCE) == TIM3_NS)  || \
41862                                          ((INSTANCE) == TIM4_S)   || ((INSTANCE) == TIM4_NS)  || \
41863                                          ((INSTANCE) == TIM5_S)   || ((INSTANCE) == TIM5_NS)  || \
41864                                          ((INSTANCE) == TIM6_S)   || ((INSTANCE) == TIM6_NS)  || \
41865                                          ((INSTANCE) == TIM7_S)   || ((INSTANCE) == TIM7_NS)  || \
41866                                          ((INSTANCE) == TIM8_S)   || ((INSTANCE) == TIM8_NS)  || \
41867                                          ((INSTANCE) == TIM15_S)  || ((INSTANCE) == TIM15_NS) || \
41868                                          ((INSTANCE) == TIM16_S)  || ((INSTANCE) == TIM16_NS) || \
41869                                          ((INSTANCE) == TIM17_S)  || ((INSTANCE) == TIM17_NS))
41870 
41871 /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
41872 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)   || ((INSTANCE) == TIM1_NS)  || \
41873                                           ((INSTANCE) == TIM2_S)   || ((INSTANCE) == TIM2_NS)  || \
41874                                           ((INSTANCE) == TIM3_S)   || ((INSTANCE) == TIM3_NS)  || \
41875                                           ((INSTANCE) == TIM4_S)   || ((INSTANCE) == TIM4_NS)  || \
41876                                           ((INSTANCE) == TIM5_S)   || ((INSTANCE) == TIM5_NS)  || \
41877                                           ((INSTANCE) == TIM8_S)   || ((INSTANCE) == TIM8_NS)  || \
41878                                           ((INSTANCE) == TIM15_S)  || ((INSTANCE) == TIM15_NS) || \
41879                                           ((INSTANCE) == TIM16_S)  || ((INSTANCE) == TIM16_NS) || \
41880                                           ((INSTANCE) == TIM17_S)  || ((INSTANCE) == TIM17_NS))
41881 
41882 /******************** TIM Instances : DMA burst feature ***********************/
41883 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
41884                                             ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
41885                                             ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
41886                                             ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
41887                                             ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
41888                                             ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
41889                                             ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
41890                                             ((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
41891                                             ((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
41892 
41893 /******************* TIM Instances : output(s) available **********************/
41894 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
41895     (((((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS))  &&   \
41896      (((CHANNEL) == TIM_CHANNEL_1) ||                            \
41897       ((CHANNEL) == TIM_CHANNEL_2) ||                            \
41898       ((CHANNEL) == TIM_CHANNEL_3) ||                            \
41899       ((CHANNEL) == TIM_CHANNEL_4) ||                            \
41900       ((CHANNEL) == TIM_CHANNEL_5) ||                            \
41901       ((CHANNEL) == TIM_CHANNEL_6)))                             \
41902      ||                                                          \
41903      ((((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS))  &&   \
41904      (((CHANNEL) == TIM_CHANNEL_1) ||                            \
41905       ((CHANNEL) == TIM_CHANNEL_2) ||                            \
41906       ((CHANNEL) == TIM_CHANNEL_3) ||                            \
41907       ((CHANNEL) == TIM_CHANNEL_4)))                             \
41908      ||                                                          \
41909      ((((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS))  &&   \
41910      (((CHANNEL) == TIM_CHANNEL_1) ||                            \
41911       ((CHANNEL) == TIM_CHANNEL_2) ||                            \
41912       ((CHANNEL) == TIM_CHANNEL_3) ||                            \
41913       ((CHANNEL) == TIM_CHANNEL_4)))                             \
41914      ||                                                          \
41915      ((((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS))  &&   \
41916      (((CHANNEL) == TIM_CHANNEL_1) ||                            \
41917       ((CHANNEL) == TIM_CHANNEL_2) ||                            \
41918       ((CHANNEL) == TIM_CHANNEL_3) ||                            \
41919       ((CHANNEL) == TIM_CHANNEL_4)))                             \
41920      ||                                                          \
41921      ((((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS))  &&   \
41922      (((CHANNEL) == TIM_CHANNEL_1) ||                            \
41923       ((CHANNEL) == TIM_CHANNEL_2) ||                            \
41924       ((CHANNEL) == TIM_CHANNEL_3) ||                            \
41925       ((CHANNEL) == TIM_CHANNEL_4)))                             \
41926      ||                                                          \
41927      ((((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))  &&   \
41928      (((CHANNEL) == TIM_CHANNEL_1) ||                            \
41929       ((CHANNEL) == TIM_CHANNEL_2) ||                            \
41930       ((CHANNEL) == TIM_CHANNEL_3) ||                            \
41931       ((CHANNEL) == TIM_CHANNEL_4) ||                            \
41932       ((CHANNEL) == TIM_CHANNEL_5) ||                            \
41933       ((CHANNEL) == TIM_CHANNEL_6)))                             \
41934      ||                                                          \
41935      ((((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS))  &&   \
41936      (((CHANNEL) == TIM_CHANNEL_1) ||                            \
41937       ((CHANNEL) == TIM_CHANNEL_2)))                             \
41938      ||                                                          \
41939      ((((INSTANCE) == TIM10_S)  || ((INSTANCE) == TIM10_NS))  && \
41940      (((CHANNEL) == TIM_CHANNEL_1)))                             \
41941      ||                                                          \
41942      ((((INSTANCE) == TIM11_S)  || ((INSTANCE) == TIM11_NS))  && \
41943      (((CHANNEL) == TIM_CHANNEL_1)))                             \
41944      ||                                                          \
41945      ((((INSTANCE) == TIM12_S)  || ((INSTANCE) == TIM12_NS))  && \
41946      (((CHANNEL) == TIM_CHANNEL_1) ||                            \
41947       ((CHANNEL) == TIM_CHANNEL_2)))                             \
41948      ||                                                          \
41949      ((((INSTANCE) == TIM13_S)  || ((INSTANCE) == TIM13_NS))  && \
41950      (((CHANNEL) == TIM_CHANNEL_1)))                             \
41951      ||                                                          \
41952      ((((INSTANCE) == TIM14_S)  || ((INSTANCE) == TIM14_NS))  && \
41953      (((CHANNEL) == TIM_CHANNEL_1)))                             \
41954      ||                                                          \
41955      (((INSTANCE) == TIM15_S)   &&                               \
41956      (((CHANNEL) == TIM_CHANNEL_1) ||                            \
41957       ((CHANNEL) == TIM_CHANNEL_2)))                             \
41958      ||                                                          \
41959      ((((INSTANCE) == TIM16_S)  || ((INSTANCE) == TIM16_NS))  && \
41960      (((CHANNEL) == TIM_CHANNEL_1)))                             \
41961      ||                                                          \
41962      ((((INSTANCE) == TIM17_S)  || ((INSTANCE) == TIM17_NS))  && \
41963      (((CHANNEL) == TIM_CHANNEL_1))))
41964 
41965 /****************** TIM Instances : supporting complementary output(s) ********/
41966 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL)                  \
41967     (((((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS))  &&   \
41968      (((CHANNEL) == TIM_CHANNEL_1) ||                            \
41969       ((CHANNEL) == TIM_CHANNEL_2) ||                            \
41970       ((CHANNEL) == TIM_CHANNEL_3) ||                            \
41971       ((CHANNEL) == TIM_CHANNEL_4)))                             \
41972      ||                                                          \
41973      ((((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))  &&   \
41974      (((CHANNEL) == TIM_CHANNEL_1) ||                            \
41975       ((CHANNEL) == TIM_CHANNEL_2) ||                            \
41976       ((CHANNEL) == TIM_CHANNEL_3) ||                            \
41977       ((CHANNEL) == TIM_CHANNEL_4)))                             \
41978      ||                                                          \
41979      ((((INSTANCE) == TIM15_S)  || ((INSTANCE) == TIM15_NS))  && \
41980      ((CHANNEL) == TIM_CHANNEL_1))                               \
41981      ||                                                          \
41982      ((((INSTANCE) == TIM16_S)  || ((INSTANCE) == TIM16_NS))  && \
41983      ((CHANNEL) == TIM_CHANNEL_1))                               \
41984      ||                                                          \
41985      ((((INSTANCE) == TIM17_S)  || ((INSTANCE) == TIM17_NS))  && \
41986      ((CHANNEL) == TIM_CHANNEL_1)))
41987 
41988 /****************** TIM Instances : supporting clock division *****************/
41989 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
41990                                                     ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
41991                                                     ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
41992                                                     ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
41993                                                     ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
41994                                                     ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
41995                                                     ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
41996                                                     ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
41997                                                     ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
41998                                                     ((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
41999                                                     ((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
42000 
42001 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
42002 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
42003                                                         ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
42004                                                         ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
42005                                                         ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
42006                                                         ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS) || \
42007                                                         ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
42008 
42009 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
42010 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
42011                                                         ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
42012                                                         ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
42013                                                         ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
42014                                                         ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS) || \
42015                                                         ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
42016 
42017 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
42018 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
42019                                                         ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
42020                                                         ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
42021                                                         ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
42022                                                         ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
42023                                                         ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
42024                                                         ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
42025                                                         ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
42026                                                         ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS))
42027 
42028 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
42029 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
42030                                                         ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
42031                                                         ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
42032                                                         ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
42033                                                         ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
42034                                                         ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
42035                                                         ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
42036                                                         ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
42037                                                         ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS))
42038 
42039 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
42040 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
42041                                                      ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
42042 
42043 /****************** TIM Instances : supporting commutation event generation ***/
42044 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
42045                                                      ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
42046                                                      ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
42047                                                      ((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
42048                                                      ((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
42049 
42050 /****************** TIM Instances : supporting counting mode selection ********/
42051 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
42052                                                         ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
42053                                                         ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
42054                                                         ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
42055                                                         ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS) || \
42056                                                         ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
42057 
42058 /****************** TIM Instances : supporting encoder interface **************/
42059 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
42060                                                       ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
42061                                                       ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
42062                                                       ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
42063                                                       ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS) || \
42064                                                       ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
42065 
42066 /****************** TIM Instances : supporting Hall sensor interface **********/
42067 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
42068                                                          ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
42069                                                          ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
42070                                                          ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
42071                                                          ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
42072                                                          ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
42073                                                          ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
42074                                                          ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
42075                                                          ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS))
42076 
42077 /**************** TIM Instances : external trigger input available ************/
42078 #define IS_TIM_ETR_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
42079                                              ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
42080                                              ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
42081                                              ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
42082                                              ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS) || \
42083                                              ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
42084 
42085 /************* TIM Instances : supporting ETR source selection ***************/
42086 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
42087                                              ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
42088                                              ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
42089                                              ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
42090                                              ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
42091                                              ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
42092 
42093 /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
42094 #define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
42095                                             ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
42096                                             ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
42097                                             ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
42098                                             ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
42099                                             ((INSTANCE) == TIM6_S)  || ((INSTANCE) == TIM6_NS)  || \
42100                                             ((INSTANCE) == TIM7_S)  || ((INSTANCE) == TIM7_NS)  || \
42101                                             ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
42102                                             ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
42103                                             ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
42104                                             ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS))
42105 
42106 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
42107 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
42108                                             ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
42109                                             ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
42110                                             ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
42111                                             ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
42112                                             ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
42113                                             ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
42114                                             ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
42115                                             ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS))
42116 
42117 /****************** TIM Instances : supporting OCxREF clear *******************/
42118 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
42119                                                 ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
42120                                                 ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
42121                                                 ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
42122                                                 ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
42123                                                 ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
42124                                                 ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
42125                                                 ((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
42126                                                 ((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
42127 
42128 /****************** TIM Instances : remapping capability **********************/
42129 #define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
42130                                             ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
42131                                             ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
42132                                             ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
42133                                             ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS) || \
42134                                             ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
42135 
42136 /****************** TIM Instances : supporting repetition counter *************/
42137 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
42138                                                        ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
42139                                                        ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
42140                                                        ((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
42141                                                        ((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
42142 
42143 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
42144 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
42145                                             ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
42146 
42147 /******************* TIM Instances : Timer input XOR function *****************/
42148 #define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
42149                                             ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
42150                                             ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
42151                                             ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
42152                                             ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
42153                                             ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
42154                                             ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
42155                                             ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
42156                                             ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS))
42157 
42158 /******************* TIM Instances : Timer input selection ********************/
42159 #define IS_TIM_TISEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
42160                                             ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
42161                                             ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
42162                                             ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
42163                                             ((INSTANCE) == TIM10_S) || ((INSTANCE) == TIM10_NS) || \
42164                                             ((INSTANCE) == TIM11_S) || ((INSTANCE) == TIM11_NS) || \
42165                                             ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
42166                                             ((INSTANCE) == TIM13_S) || ((INSTANCE) == TIM13_NS) || \
42167                                             ((INSTANCE) == TIM14_S) || ((INSTANCE) == TIM14_NS) || \
42168                                             ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
42169                                             ((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
42170                                             ((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
42171 
42172 /****************** TIM Instances : Advanced timer instances *******************/
42173 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS) || \
42174                                             ((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS))
42175 
42176 /****************************** WWDG Instances *******************************/
42177 #define IS_WWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == WWDG_S) || ((INSTANCE) == WWDG_NS))
42178 
42179 /******************************** XSPI Instances *****************************/
42180 #define IS_XSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == XSPI1_S) || ((INSTANCE) == XSPI1_NS) || \
42181                                         ((INSTANCE) == XSPI2_S) || ((INSTANCE) == XSPI2_NS) || \
42182                                         ((INSTANCE) == XSPI3_S) || ((INSTANCE) == XSPI3_NS))
42183 
42184 /****************************** XSPIM Instances ***************************/
42185 #define IS_XSPIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == XSPIM_S) || ((INSTANCE) == XSPIM_NS))
42186 
42187 #else
42188 /* Instances allowed from Non-Secure state - only alias Non-Secure */
42189 
42190 /******************************* ADC Instances *******************************/
42191 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \
42192                                        ((INSTANCE) == ADC2_NS))
42193 
42194 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_NS)
42195 
42196 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON_NS)
42197 
42198 /******************************* CACHEAXI Instances ***************************/
42199 #define IS_CACHEAXI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CACHEAXI_NS)
42200 
42201 /******************************* CRC Instances *******************************/
42202 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC_NS)
42203 
42204 /******************************* DCMI Instances ******************************/
42205 #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI_NS)
42206 
42207 /******************************* DCMIPP Instances ****************************/
42208 #define IS_DCMIPP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMIPP_NS)
42209 
42210 /******************************* DLYB Instances ****************************/
42211 #define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1_NS) || \
42212                                         ((INSTANCE) == DLYB_SDMMC2_NS))
42213 
42214 /******************************** DMA Instances ******************************/
42215 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || \
42216                                        ((INSTANCE) == GPDMA1_Channel1_NS) || \
42217                                        ((INSTANCE) == GPDMA1_Channel2_NS) || \
42218                                        ((INSTANCE) == GPDMA1_Channel3_NS) || \
42219                                        ((INSTANCE) == GPDMA1_Channel4_NS) || \
42220                                        ((INSTANCE) == GPDMA1_Channel5_NS) || \
42221                                        ((INSTANCE) == GPDMA1_Channel6_NS) || \
42222                                        ((INSTANCE) == GPDMA1_Channel7_NS) || \
42223                                        ((INSTANCE) == GPDMA1_Channel8_NS) || \
42224                                        ((INSTANCE) == GPDMA1_Channel9_NS) || \
42225                                        ((INSTANCE) == GPDMA1_Channel10_NS) || \
42226                                        ((INSTANCE) == GPDMA1_Channel11_NS) || \
42227                                        ((INSTANCE) == GPDMA1_Channel12_NS) || \
42228                                        ((INSTANCE) == GPDMA1_Channel13_NS) || \
42229                                        ((INSTANCE) == GPDMA1_Channel14_NS) || \
42230                                        ((INSTANCE) == GPDMA1_Channel15_NS) || \
42231                                        ((INSTANCE) == HPDMA1_Channel0_NS) || \
42232                                        ((INSTANCE) == HPDMA1_Channel1_NS) || \
42233                                        ((INSTANCE) == HPDMA1_Channel2_NS) || \
42234                                        ((INSTANCE) == HPDMA1_Channel3_NS) || \
42235                                        ((INSTANCE) == HPDMA1_Channel4_NS) || \
42236                                        ((INSTANCE) == HPDMA1_Channel5_NS) || \
42237                                        ((INSTANCE) == HPDMA1_Channel6_NS) || \
42238                                        ((INSTANCE) == HPDMA1_Channel7_NS) || \
42239                                        ((INSTANCE) == HPDMA1_Channel8_NS) || \
42240                                        ((INSTANCE) == HPDMA1_Channel9_NS) || \
42241                                        ((INSTANCE) == HPDMA1_Channel10_NS) || \
42242                                        ((INSTANCE) == HPDMA1_Channel11_NS) || \
42243                                        ((INSTANCE) == HPDMA1_Channel12_NS) || \
42244                                        ((INSTANCE) == HPDMA1_Channel13_NS) || \
42245                                        ((INSTANCE) == HPDMA1_Channel14_NS) || \
42246                                        ((INSTANCE) == HPDMA1_Channel15_NS))
42247 
42248 #define IS_GPDMA_INSTANCE(INSTANCE)  (((INSTANCE) == GPDMA1_Channel0_NS) || \
42249                                       ((INSTANCE) == GPDMA1_Channel1_NS) || \
42250                                       ((INSTANCE) == GPDMA1_Channel2_NS) || \
42251                                       ((INSTANCE) == GPDMA1_Channel3_NS) || \
42252                                       ((INSTANCE) == GPDMA1_Channel4_NS) || \
42253                                       ((INSTANCE) == GPDMA1_Channel5_NS) || \
42254                                       ((INSTANCE) == GPDMA1_Channel6_NS) || \
42255                                       ((INSTANCE) == GPDMA1_Channel7_NS) || \
42256                                       ((INSTANCE) == GPDMA1_Channel8_NS) || \
42257                                       ((INSTANCE) == GPDMA1_Channel9_NS) || \
42258                                       ((INSTANCE) == GPDMA1_Channel10_NS) || \
42259                                       ((INSTANCE) == GPDMA1_Channel11_NS) || \
42260                                       ((INSTANCE) == GPDMA1_Channel12_NS) || \
42261                                       ((INSTANCE) == GPDMA1_Channel13_NS) || \
42262                                       ((INSTANCE) == GPDMA1_Channel14_NS) || \
42263                                       ((INSTANCE) == GPDMA1_Channel15_NS))
42264 
42265 #define IS_HPDMA_INSTANCE(INSTANCE)  (((INSTANCE) == HPDMA1_Channel0_NS) || \
42266                                       ((INSTANCE) == HPDMA1_Channel1_NS) || \
42267                                       ((INSTANCE) == HPDMA1_Channel2_NS) || \
42268                                       ((INSTANCE) == HPDMA1_Channel3_NS) || \
42269                                       ((INSTANCE) == HPDMA1_Channel4_NS) || \
42270                                       ((INSTANCE) == HPDMA1_Channel5_NS) || \
42271                                       ((INSTANCE) == HPDMA1_Channel6_NS) || \
42272                                       ((INSTANCE) == HPDMA1_Channel7_NS) || \
42273                                       ((INSTANCE) == HPDMA1_Channel8_NS) || \
42274                                       ((INSTANCE) == HPDMA1_Channel9_NS) || \
42275                                       ((INSTANCE) == HPDMA1_Channel10_NS) || \
42276                                       ((INSTANCE) == HPDMA1_Channel11_NS) || \
42277                                       ((INSTANCE) == HPDMA1_Channel12_NS) || \
42278                                       ((INSTANCE) == HPDMA1_Channel13_NS) || \
42279                                       ((INSTANCE) == HPDMA1_Channel14_NS) || \
42280                                       ((INSTANCE) == HPDMA1_Channel15_NS))
42281 
42282 #define IS_DMA_2D_ADDRESSING_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel12_NS) || \
42283                                                  ((INSTANCE) == GPDMA1_Channel13_NS) || \
42284                                                  ((INSTANCE) == GPDMA1_Channel14_NS) || \
42285                                                  ((INSTANCE) == GPDMA1_Channel15_NS) || \
42286                                                  ((INSTANCE) == HPDMA1_Channel12_NS) || \
42287                                                  ((INSTANCE) == HPDMA1_Channel13_NS) || \
42288                                                  ((INSTANCE) == HPDMA1_Channel14_NS) || \
42289                                                  ((INSTANCE) == HPDMA1_Channel15_NS))
42290 
42291 #define IS_DMA_LIMIT_INSTANCE(INSTANCE) (((INSTANCE) == HPDMA1_Channel12_NS) || ((INSTANCE) == HPDMA1_Channel13_NS) || \
42292                                          ((INSTANCE) == HPDMA1_Channel14_NS) || ((INSTANCE) == HPDMA1_Channel15_NS))
42293 
42294 #define IS_DMA_PFREQ_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS)  || \
42295                                          ((INSTANCE) == GPDMA1_Channel1_NS)  || \
42296                                          ((INSTANCE) == GPDMA1_Channel15_NS) || \
42297                                          ((INSTANCE) == HPDMA1_Channel0_NS)  || \
42298                                          ((INSTANCE) == HPDMA1_Channel1_NS)  || \
42299                                          ((INSTANCE) == HPDMA1_Channel15_NS))
42300 
42301 /******************************* DMA2D Instances *****************************/
42302 #define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D_NS)
42303 
42304 /******************************* DTS Instances *****************************/
42305 #define IS_DTS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DTS_NS)
42306 
42307 /******************************* ETH Instances *******************************/
42308 #define IS_ETH_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ETH1_NS)
42309 
42310 /******************************* FDCAN Instances *****************************/
42311 #define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1_NS) || \
42312                                          ((INSTANCE) == FDCAN2_NS) || \
42313                                          ((INSTANCE) == FDCAN3_NS))
42314 
42315 #define IS_FDCAN_CONFIG_INSTANCE(INSTANCE) ((INSTANCE) == FDCAN_CONFIG_NS)
42316 
42317 #define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1_NS)
42318 
42319 /******************************* GFXMMU Instance *****************************/
42320 #define IS_GFXMMU_ALL_INSTANCE(INSTANCE) ((INSTANCE) == GFXMMU_NS)
42321 
42322 /******************************* GFXTIM Instance *****************************/
42323 #define IS_GFXTIM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == GFXTIM_NS)
42324 
42325 /********************************* GPIO Instances ****************************/
42326 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_NS) || \
42327                                         ((INSTANCE) == GPIOB_NS) || \
42328                                         ((INSTANCE) == GPIOC_NS) || \
42329                                         ((INSTANCE) == GPIOD_NS) || \
42330                                         ((INSTANCE) == GPIOE_NS) || \
42331                                         ((INSTANCE) == GPIOF_NS) || \
42332                                         ((INSTANCE) == GPIOG_NS) || \
42333                                         ((INSTANCE) == GPIOH_NS) || \
42334                                         ((INSTANCE) == GPION_NS) || \
42335                                         ((INSTANCE) == GPIOO_NS) || \
42336                                         ((INSTANCE) == GPIOP_NS) || \
42337                                         ((INSTANCE) == GPIOQ_NS))
42338 
42339 /******************************* GPIO AF Instances ***************************/
42340 /* All GPIO Banks support AF */
42341 #define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
42342 
42343 /**************************** GPIO Lock Instances ****************************/
42344 /* All GPIO Banks support the Lock mechanism */
42345 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
42346 
42347 /******************************* GPU2D Instances *****************************/
42348 #define IS_GPU2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == GPU2D_BASE_NS)
42349 
42350 /******************************** I2C Instances ******************************/
42351 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || \
42352                                        ((INSTANCE) == I2C2_NS) || \
42353                                        ((INSTANCE) == I2C3_NS) || \
42354                                        ((INSTANCE) == I2C4_NS))
42355 
42356 /****************** I2C Instances : wakeup capability from stop modes ********/
42357 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
42358 
42359 /******************************** I3C Instances *******************************/
42360 #define IS_I3C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I3C1_NS) || \
42361                                       ((INSTANCE) == I3C2_NS))
42362 
42363 /****************************** IWDG Instances *******************************/
42364 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG_NS)
42365 
42366 /******************************* JPEG Instances ******************************/
42367 #define IS_JPEG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == JPEG_NS)
42368 
42369 /****************************** LTDC Instances *******************************/
42370 #define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC_NS)
42371 
42372 /******************************* MCE Instances *******************************/
42373 #define IS_MCE_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MCE1_NS) || \
42374                                        ((INSTANCE) == MCE2_NS) || \
42375                                        ((INSTANCE) == MCE3_NS) || \
42376                                        ((INSTANCE) == MCE4_NS))
42377 
42378 /******************************* MDF/ADF Instances ***************************/
42379 #define IS_MDF_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDF1_Filter0_NS) || \
42380                                        ((INSTANCE) == MDF1_Filter1_NS) || \
42381                                        ((INSTANCE) == MDF1_Filter2_NS) || \
42382                                        ((INSTANCE) == MDF1_Filter3_NS) || \
42383                                        ((INSTANCE) == MDF1_Filter4_NS) || \
42384                                        ((INSTANCE) == MDF1_Filter5_NS) || \
42385                                        ((INSTANCE) == ADF1_Filter0_NS))
42386 
42387 /****************************** MDIOS Instances ******************************/
42388 #define IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS_NS)
42389 
42390 /******************************* PKA Instances *******************************/
42391 #define IS_PKA_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PKA_NS)
42392 
42393 /******************************* PSSI Instances ******************************/
42394 #define IS_PSSI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PSSI_NS)
42395 
42396 /****************************** RAMCFG Instances ********************************/
42397 #define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_AHB_NS) || \
42398                                           ((INSTANCE) == RAMCFG_SRAM2_AHB_NS) || \
42399                                           ((INSTANCE) == RAMCFG_SRAM1_AXI_NS) || \
42400                                           ((INSTANCE) == RAMCFG_SRAM2_AXI_NS) || \
42401                                           ((INSTANCE) == RAMCFG_SRAM3_AXI_NS) || \
42402                                           ((INSTANCE) == RAMCFG_SRAM4_AXI_NS) || \
42403                                           ((INSTANCE) == RAMCFG_SRAM5_AXI_NS) || \
42404                                           ((INSTANCE) == RAMCFG_SRAM6_AXI_NS) || \
42405                                           ((INSTANCE) == RAMCFG_BKPSRAM_NS)   || \
42406                                           ((INSTANCE) == RAMCFG_FLEXRAM_NS)   || \
42407                                           ((INSTANCE) == RAMCFG_VENC_RAM_NS))
42408 
42409 /***************************** RAMCFG ECC Instances *****************************/
42410 #define IS_RAMCFG_ECC_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_BKPSRAM_NS) || \
42411                                           ((INSTANCE) == RAMCFG_FLEXRAM_NS))
42412 
42413 /***************************** RAMCFG AXISRAM POWERDOWN Instances ***************/
42414 #define IS_RAMCFG_AXISRAM_POWERDOWN_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_AXI_NS) || \
42415                                                         ((INSTANCE) == RAMCFG_SRAM3_AXI_NS) || \
42416                                                         ((INSTANCE) == RAMCFG_SRAM4_AXI_NS) || \
42417                                                         ((INSTANCE) == RAMCFG_SRAM5_AXI_NS) || \
42418                                                         ((INSTANCE) == RAMCFG_SRAM6_AXI_NS))
42419 
42420 /******************************* RNG Instances *******************************/
42421 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG_NS)
42422 
42423 /******************************* RTC Instances *******************************/
42424 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC_NS)
42425 
42426 /******************************** SAI Instances ******************************/
42427 #define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_NS) || \
42428                                        ((INSTANCE) == SAI1_Block_B_NS) || \
42429                                        ((INSTANCE) == SAI2_Block_A_NS) || \
42430                                        ((INSTANCE) == SAI2_Block_B_NS))
42431 
42432 /******************************* SDMMC Instances *****************************/
42433 #define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1_NS) || \
42434                                          ((INSTANCE) == SDMMC2_NS))
42435 
42436 /******************************** SMBUS Instances ****************************/
42437 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || \
42438                                          ((INSTANCE) == I2C2_NS) || \
42439                                          ((INSTANCE) == I2C3_NS) || \
42440                                          ((INSTANCE) == I2C4_NS))
42441 
42442 /****************************** SPDIFRX Instances ****************************/
42443 #define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX_NS)
42444 
42445 /******************************** SPI Instances ******************************/
42446 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || \
42447                                        ((INSTANCE) == SPI2_NS) || \
42448                                        ((INSTANCE) == SPI3_NS) || \
42449                                        ((INSTANCE) == SPI4_NS) || \
42450                                        ((INSTANCE) == SPI5_NS) || \
42451                                        ((INSTANCE) == SPI6_NS))
42452 
42453 #define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || \
42454                                         ((INSTANCE) == SPI2_NS) || \
42455                                         ((INSTANCE) == SPI3_NS) || \
42456                                         ((INSTANCE) == SPI6_NS))
42457 
42458 #define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI4_NS) || \
42459                                            ((INSTANCE) == SPI5_NS))
42460 
42461 /******************************** I2S Instances ******************************/
42462 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || \
42463                                        ((INSTANCE) == SPI2_NS) || \
42464                                        ((INSTANCE) == SPI3_NS) || \
42465                                        ((INSTANCE) == SPI6_NS))
42466 
42467 /****************************** UCPD Instances *******************************/
42468 #define IS_UCPD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == UCPD1_NS)
42469 
42470 /******************************* OTG HS HCD Instances *************************/
42471 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB1_OTG_HS_NS) || \
42472                                        ((INSTANCE) == USB2_OTG_HS_NS))
42473 
42474 /******************************* OTG HS PCD Instances *************************/
42475 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB1_OTG_HS_NS) || \
42476                                        ((INSTANCE) == USB2_OTG_HS_NS))
42477 
42478 /******************************* USB HS PHY Instances *************************/
42479 #define IS_USBPHYC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB1_HS_PHYC_NS) || \
42480                                            ((INSTANCE) == USB2_HS_PHYC_NS))
42481 
42482 /******************** USART Instances : Synchronous mode *********************/
42483 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
42484                                      ((INSTANCE) == USART2_NS) || \
42485                                      ((INSTANCE) == USART3_NS) || \
42486                                      ((INSTANCE) == USART6_NS) || \
42487                                      ((INSTANCE) == USART10_NS))
42488 
42489 /******************** UART Instances : Asynchronous mode *********************/
42490 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
42491                                     ((INSTANCE) == USART2_NS) || \
42492                                     ((INSTANCE) == USART3_NS) || \
42493                                     ((INSTANCE) == UART4_NS)  || \
42494                                     ((INSTANCE) == UART5_NS)  || \
42495                                     ((INSTANCE) == USART6_NS) || \
42496                                     ((INSTANCE) == UART7_NS)  || \
42497                                     ((INSTANCE) == UART8_NS)  || \
42498                                     ((INSTANCE) == UART9_NS)  || \
42499                                     ((INSTANCE) == USART10_NS))
42500 
42501 /*********************** UART Instances : FIFO mode **************************/
42502 #define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
42503                                          ((INSTANCE) == USART2_NS)  || \
42504                                          ((INSTANCE) == USART3_NS)  || \
42505                                          ((INSTANCE) == UART4_NS)   || \
42506                                          ((INSTANCE) == UART5_NS)   || \
42507                                          ((INSTANCE) == USART6_NS)  || \
42508                                          ((INSTANCE) == UART7_NS)   || \
42509                                          ((INSTANCE) == UART8_NS)   || \
42510                                          ((INSTANCE) == UART9_NS)   || \
42511                                          ((INSTANCE) == USART10_NS) || \
42512                                          ((INSTANCE) == LPUART1_NS))
42513 
42514 /*********************** UART Instances : SPI Slave mode **********************/
42515 #define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
42516                                               ((INSTANCE) == USART2_NS)  || \
42517                                               ((INSTANCE) == USART3_NS)  || \
42518                                               ((INSTANCE) == USART6_NS)  || \
42519                                               ((INSTANCE) == USART10_NS))
42520 
42521 /****************** UART Instances : Auto Baud Rate detection ****************/
42522 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
42523                                                             ((INSTANCE) == USART2_NS)  || \
42524                                                             ((INSTANCE) == USART3_NS)  || \
42525                                                             ((INSTANCE) == UART4_NS)   || \
42526                                                             ((INSTANCE) == UART5_NS)   || \
42527                                                             ((INSTANCE) == USART6_NS)  || \
42528                                                             ((INSTANCE) == UART7_NS)   || \
42529                                                             ((INSTANCE) == UART8_NS)   || \
42530                                                             ((INSTANCE) == UART9_NS)   || \
42531                                                             ((INSTANCE) == USART10_NS))
42532 
42533 /****************** UART Instances : Driver Enable ***************************/
42534 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
42535                                                   ((INSTANCE) == USART2_NS)  || \
42536                                                   ((INSTANCE) == USART3_NS)  || \
42537                                                   ((INSTANCE) == UART4_NS)   || \
42538                                                   ((INSTANCE) == UART5_NS)   || \
42539                                                   ((INSTANCE) == USART6_NS)  || \
42540                                                   ((INSTANCE) == UART7_NS)   || \
42541                                                   ((INSTANCE) == UART8_NS)   || \
42542                                                   ((INSTANCE) == UART9_NS)   || \
42543                                                   ((INSTANCE) == USART10_NS) || \
42544                                                   ((INSTANCE) == LPUART1_NS))
42545 
42546 /******************** UART Instances : Half-Duplex mode **********************/
42547 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
42548                                                ((INSTANCE) == USART2_NS)  || \
42549                                                ((INSTANCE) == USART3_NS)  || \
42550                                                ((INSTANCE) == UART4_NS)   || \
42551                                                ((INSTANCE) == UART5_NS)   || \
42552                                                ((INSTANCE) == USART6_NS)  || \
42553                                                ((INSTANCE) == UART7_NS)   || \
42554                                                ((INSTANCE) == UART8_NS)   || \
42555                                                ((INSTANCE) == UART9_NS)   || \
42556                                                ((INSTANCE) == USART10_NS) || \
42557                                                ((INSTANCE) == LPUART1_NS))
42558 
42559 /****************** UART Instances : Hardware Flow control *******************/
42560 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
42561                                            ((INSTANCE) == USART2_NS)  || \
42562                                            ((INSTANCE) == USART3_NS)  || \
42563                                            ((INSTANCE) == UART4_NS)   || \
42564                                            ((INSTANCE) == UART5_NS)   || \
42565                                            ((INSTANCE) == USART6_NS)  || \
42566                                            ((INSTANCE) == UART7_NS)   || \
42567                                            ((INSTANCE) == UART8_NS)   || \
42568                                            ((INSTANCE) == UART9_NS)   || \
42569                                            ((INSTANCE) == USART10_NS) || \
42570                                            ((INSTANCE) == LPUART1_NS))
42571 
42572 /******************** UART Instances : LIN mode ******************************/
42573 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
42574                                         ((INSTANCE) == USART2_NS)  || \
42575                                         ((INSTANCE) == USART3_NS)  || \
42576                                         ((INSTANCE) == UART4_NS)   || \
42577                                         ((INSTANCE) == UART5_NS)   || \
42578                                         ((INSTANCE) == USART6_NS)  || \
42579                                         ((INSTANCE) == UART7_NS)   || \
42580                                         ((INSTANCE) == UART8_NS)   || \
42581                                         ((INSTANCE) == UART9_NS)   || \
42582                                         ((INSTANCE) == USART10_NS))
42583 
42584 /******************** UART Instances : Wake-up from Stop mode ****************/
42585 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
42586                                                     ((INSTANCE) == USART2_NS)  || \
42587                                                     ((INSTANCE) == USART3_NS)  || \
42588                                                     ((INSTANCE) == UART4_NS)   || \
42589                                                     ((INSTANCE) == UART5_NS)   || \
42590                                                     ((INSTANCE) == USART6_NS)  || \
42591                                                     ((INSTANCE) == UART7_NS)   || \
42592                                                     ((INSTANCE) == UART8_NS)   || \
42593                                                     ((INSTANCE) == UART9_NS)   || \
42594                                                     ((INSTANCE) == USART10_NS) || \
42595                                                     ((INSTANCE) == LPUART1_NS))
42596 
42597 /*********************** UART Instances : IRDA mode **************************/
42598 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
42599                                     ((INSTANCE) == USART2_NS)  || \
42600                                     ((INSTANCE) == USART3_NS)  || \
42601                                     ((INSTANCE) == UART4_NS)   || \
42602                                     ((INSTANCE) == UART5_NS)   || \
42603                                     ((INSTANCE) == USART6_NS)  || \
42604                                     ((INSTANCE) == UART7_NS)   || \
42605                                     ((INSTANCE) == UART8_NS)   || \
42606                                     ((INSTANCE) == UART9_NS)   || \
42607                                     ((INSTANCE) == USART10_NS))
42608 
42609 /********************* USART Instances : Smard card mode *********************/
42610 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
42611                                          ((INSTANCE) == USART2_NS)  || \
42612                                          ((INSTANCE) == USART3_NS)  || \
42613                                          ((INSTANCE) == USART6_NS)  || \
42614                                          ((INSTANCE) == USART10_NS))
42615 
42616 /******************** LPUART Instance ****************************************/
42617 #define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1_NS)
42618 
42619 /****************** LPTIM Instances : All supported instances *****************/
42620 #define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1_NS) || \
42621                                          ((INSTANCE) == LPTIM2_NS) || \
42622                                          ((INSTANCE) == LPTIM3_NS) || \
42623                                          ((INSTANCE) == LPTIM4_NS) || \
42624                                          ((INSTANCE) == LPTIM5_NS))
42625 
42626 /****************** LPTIM Instances : DMA supported instances *****************/
42627 #define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || \
42628                                          ((INSTANCE) == LPTIM2_NS) || \
42629                                          ((INSTANCE) == LPTIM3_NS))
42630 
42631 /************* LPTIM Instances : at least 1 capture/compare channel ***********/
42632 #define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || \
42633                                          ((INSTANCE) == LPTIM2_NS) || \
42634                                          ((INSTANCE) == LPTIM3_NS) || \
42635                                          ((INSTANCE) == LPTIM4_NS) || \
42636                                          ((INSTANCE) == LPTIM5_NS))
42637 
42638 /************* LPTIM Instances : at least 2 capture/compare channel ***********/
42639 #define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || \
42640                                          ((INSTANCE) == LPTIM2_NS) || \
42641                                          ((INSTANCE) == LPTIM3_NS))
42642 
42643 /****************** LPTIM Instances : supporting encoder interface **************/
42644 #define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || \
42645                                                        ((INSTANCE) == LPTIM2_NS) || \
42646                                                        ((INSTANCE) == LPTIM3_NS))
42647 
42648 
42649 /****************** LPTIM Instances : supporting Input Capture **************/
42650 #define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || \
42651                                                    ((INSTANCE) == LPTIM2_NS) || \
42652                                                    ((INSTANCE) == LPTIM3_NS))
42653 
42654 /****************** TIM Instances : All supported instances *******************/
42655 #define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1_NS)   || \
42656                                          ((INSTANCE) == TIM2_NS)   || \
42657                                          ((INSTANCE) == TIM3_NS)   || \
42658                                          ((INSTANCE) == TIM4_NS)   || \
42659                                          ((INSTANCE) == TIM5_NS)   || \
42660                                          ((INSTANCE) == TIM6_NS)   || \
42661                                          ((INSTANCE) == TIM7_NS)   || \
42662                                          ((INSTANCE) == TIM8_NS)   || \
42663                                          ((INSTANCE) == TIM9_NS)   || \
42664                                          ((INSTANCE) == TIM10_NS)  || \
42665                                          ((INSTANCE) == TIM11_NS)  || \
42666                                          ((INSTANCE) == TIM12_NS)  || \
42667                                          ((INSTANCE) == TIM13_NS)  || \
42668                                          ((INSTANCE) == TIM14_NS)  || \
42669                                          ((INSTANCE) == TIM15_NS)  || \
42670                                          ((INSTANCE) == TIM16_NS)  || \
42671                                          ((INSTANCE) == TIM17_NS)  || \
42672                                          ((INSTANCE) == TIM18_NS))
42673 
42674 /****************** TIM Instances : supporting 32 bits counter ****************/
42675 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS)  || \
42676                                                ((INSTANCE) == TIM3_NS)  || \
42677                                                ((INSTANCE) == TIM4_NS)  || \
42678                                                ((INSTANCE) == TIM5_NS))
42679 
42680 /****************** TIM Instances : supporting the break function *************/
42681 #define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || \
42682                                             ((INSTANCE) == TIM8_NS)  || \
42683                                             ((INSTANCE) == TIM15_NS) || \
42684                                             ((INSTANCE) == TIM16_NS) || \
42685                                             ((INSTANCE) == TIM17_NS))
42686 
42687 /************** TIM Instances : supporting Break source selection *************/
42688 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
42689                                                ((INSTANCE) == TIM8_NS)  || \
42690                                                ((INSTANCE) == TIM15_NS) || \
42691                                                ((INSTANCE) == TIM16_NS) || \
42692                                                ((INSTANCE) == TIM17_NS))
42693 
42694 /****************** TIM Instances : supporting 2 break inputs *****************/
42695 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || \
42696                                             ((INSTANCE) == TIM8_NS))
42697 
42698 /************* TIM Instances : at least 1 capture/compare channel *************/
42699 #define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)   || \
42700                                          ((INSTANCE) == TIM2_NS)   || \
42701                                          ((INSTANCE) == TIM3_NS)   || \
42702                                          ((INSTANCE) == TIM4_NS)   || \
42703                                          ((INSTANCE) == TIM5_NS)   || \
42704                                          ((INSTANCE) == TIM8_NS)   || \
42705                                          ((INSTANCE) == TIM9_NS)   || \
42706                                          ((INSTANCE) == TIM10_NS)  || \
42707                                          ((INSTANCE) == TIM11_NS)  || \
42708                                          ((INSTANCE) == TIM12_NS)  || \
42709                                          ((INSTANCE) == TIM13_NS)  || \
42710                                          ((INSTANCE) == TIM14_NS)  || \
42711                                          ((INSTANCE) == TIM15_NS)  || \
42712                                          ((INSTANCE) == TIM16_NS)  || \
42713                                          ((INSTANCE) == TIM17_NS))
42714 
42715 /************ TIM Instances : at least 2 capture/compare channels *************/
42716 #define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
42717                                          ((INSTANCE) == TIM2_NS)  || \
42718                                          ((INSTANCE) == TIM3_NS)  || \
42719                                          ((INSTANCE) == TIM4_NS)  || \
42720                                          ((INSTANCE) == TIM5_NS)  || \
42721                                          ((INSTANCE) == TIM8_NS)  || \
42722                                          ((INSTANCE) == TIM9_NS)  || \
42723                                          ((INSTANCE) == TIM12_NS) || \
42724                                          ((INSTANCE) == TIM15_NS))
42725 
42726 /************ TIM Instances : at least 3 capture/compare channels *************/
42727 #define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
42728                                          ((INSTANCE) == TIM2_NS)  || \
42729                                          ((INSTANCE) == TIM3_NS)  || \
42730                                          ((INSTANCE) == TIM4_NS)  || \
42731                                          ((INSTANCE) == TIM5_NS)  || \
42732                                          ((INSTANCE) == TIM8_NS))
42733 
42734 /************ TIM Instances : at least 4 capture/compare channels *************/
42735 #define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
42736                                          ((INSTANCE) == TIM2_NS)  || \
42737                                          ((INSTANCE) == TIM3_NS)  || \
42738                                          ((INSTANCE) == TIM4_NS)  || \
42739                                          ((INSTANCE) == TIM5_NS)  || \
42740                                          ((INSTANCE) == TIM8_NS))
42741 
42742 /****************** TIM Instances : at least 5 capture/compare channels *******/
42743 #define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
42744                                          ((INSTANCE) == TIM8_NS))
42745 
42746 /****************** TIM Instances : at least 6 capture/compare channels *******/
42747 #define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
42748                                          ((INSTANCE) == TIM8_NS))
42749 
42750 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
42751 #define IS_TIM_DMA_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)   || \
42752                                          ((INSTANCE) == TIM2_NS)   || \
42753                                          ((INSTANCE) == TIM3_NS)   || \
42754                                          ((INSTANCE) == TIM4_NS)   || \
42755                                          ((INSTANCE) == TIM5_NS)   || \
42756                                          ((INSTANCE) == TIM6_NS)   || \
42757                                          ((INSTANCE) == TIM7_NS)   || \
42758                                          ((INSTANCE) == TIM8_NS)   || \
42759                                          ((INSTANCE) == TIM15_NS)  || \
42760                                          ((INSTANCE) == TIM16_NS)  || \
42761                                          ((INSTANCE) == TIM17_NS)  || \
42762                                          ((INSTANCE) == TIM18_NS))
42763 
42764 /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
42765 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)   || \
42766                                           ((INSTANCE) == TIM2_NS)   || \
42767                                           ((INSTANCE) == TIM3_NS)   || \
42768                                           ((INSTANCE) == TIM4_NS)   || \
42769                                           ((INSTANCE) == TIM5_NS)   || \
42770                                           ((INSTANCE) == TIM8_NS)   || \
42771                                           ((INSTANCE) == TIM15_NS)  || \
42772                                           ((INSTANCE) == TIM16_NS)  || \
42773                                           ((INSTANCE) == TIM17_NS))
42774 
42775 /******************** TIM Instances : DMA burst feature ***********************/
42776 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
42777                                             ((INSTANCE) == TIM2_NS)  || \
42778                                             ((INSTANCE) == TIM3_NS)  || \
42779                                             ((INSTANCE) == TIM4_NS)  || \
42780                                             ((INSTANCE) == TIM5_NS)  || \
42781                                             ((INSTANCE) == TIM8_NS)  || \
42782                                             ((INSTANCE) == TIM15_NS) || \
42783                                             ((INSTANCE) == TIM16_NS) || \
42784                                             ((INSTANCE) == TIM17_NS))
42785 
42786 /******************* TIM Instances : output(s) available **********************/
42787 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
42788     ((((INSTANCE) == TIM1_NS)    &&             \
42789      (((CHANNEL) == TIM_CHANNEL_1) ||          \
42790       ((CHANNEL) == TIM_CHANNEL_2) ||          \
42791       ((CHANNEL) == TIM_CHANNEL_3) ||          \
42792       ((CHANNEL) == TIM_CHANNEL_4) ||          \
42793       ((CHANNEL) == TIM_CHANNEL_5) ||          \
42794       ((CHANNEL) == TIM_CHANNEL_6)))           \
42795      ||                                        \
42796      (((INSTANCE) == TIM2_NS)    &&             \
42797      (((CHANNEL) == TIM_CHANNEL_1) ||          \
42798       ((CHANNEL) == TIM_CHANNEL_2) ||          \
42799       ((CHANNEL) == TIM_CHANNEL_3) ||          \
42800       ((CHANNEL) == TIM_CHANNEL_4)))           \
42801      ||                                        \
42802      (((INSTANCE) == TIM3_NS)    &&             \
42803      (((CHANNEL) == TIM_CHANNEL_1) ||          \
42804       ((CHANNEL) == TIM_CHANNEL_2) ||          \
42805       ((CHANNEL) == TIM_CHANNEL_3) ||          \
42806       ((CHANNEL) == TIM_CHANNEL_4)))           \
42807      ||                                        \
42808      (((INSTANCE) == TIM4_NS)    &&             \
42809      (((CHANNEL) == TIM_CHANNEL_1) ||          \
42810       ((CHANNEL) == TIM_CHANNEL_2) ||          \
42811       ((CHANNEL) == TIM_CHANNEL_3) ||          \
42812       ((CHANNEL) == TIM_CHANNEL_4)))           \
42813      ||                                        \
42814      (((INSTANCE) == TIM5_NS)    &&             \
42815      (((CHANNEL) == TIM_CHANNEL_1) ||          \
42816       ((CHANNEL) == TIM_CHANNEL_2) ||          \
42817       ((CHANNEL) == TIM_CHANNEL_3) ||          \
42818       ((CHANNEL) == TIM_CHANNEL_4)))           \
42819      ||                                        \
42820      (((INSTANCE) == TIM8_NS)    &&             \
42821      (((CHANNEL) == TIM_CHANNEL_1) ||          \
42822       ((CHANNEL) == TIM_CHANNEL_2) ||          \
42823       ((CHANNEL) == TIM_CHANNEL_3) ||          \
42824       ((CHANNEL) == TIM_CHANNEL_4) ||          \
42825       ((CHANNEL) == TIM_CHANNEL_5) ||          \
42826       ((CHANNEL) == TIM_CHANNEL_6)))           \
42827      ||                                        \
42828      (((INSTANCE) == TIM9_NS)   &&              \
42829      (((CHANNEL) == TIM_CHANNEL_1) ||          \
42830       ((CHANNEL) == TIM_CHANNEL_2)))           \
42831      ||                                        \
42832      (((INSTANCE) == TIM10_NS)   &&             \
42833      (((CHANNEL) == TIM_CHANNEL_1)))           \
42834      ||                                        \
42835      (((INSTANCE) == TIM11_NS)   &&             \
42836      (((CHANNEL) == TIM_CHANNEL_1)))           \
42837      ||                                        \
42838      (((INSTANCE) == TIM12_NS)   &&             \
42839      (((CHANNEL) == TIM_CHANNEL_1) ||          \
42840       ((CHANNEL) == TIM_CHANNEL_2)))           \
42841      ||                                        \
42842      (((INSTANCE) == TIM13_NS)   &&             \
42843      (((CHANNEL) == TIM_CHANNEL_1)))           \
42844      ||                                        \
42845      (((INSTANCE) == TIM14_NS)   &&             \
42846      (((CHANNEL) == TIM_CHANNEL_1)))           \
42847      ||                                        \
42848      (((INSTANCE) == TIM15_NS)   &&             \
42849      (((CHANNEL) == TIM_CHANNEL_1) ||          \
42850       ((CHANNEL) == TIM_CHANNEL_2)))           \
42851      ||                                        \
42852      (((INSTANCE) == TIM16_NS)   &&             \
42853      (((CHANNEL) == TIM_CHANNEL_1)))           \
42854      ||                                        \
42855      (((INSTANCE) == TIM17_NS)   &&             \
42856      (((CHANNEL) == TIM_CHANNEL_1))))
42857 
42858 /****************** TIM Instances : supporting complementary output(s) ********/
42859 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
42860     ((((INSTANCE) == TIM1_NS)    &&              \
42861      (((CHANNEL) == TIM_CHANNEL_1) ||           \
42862       ((CHANNEL) == TIM_CHANNEL_2) ||           \
42863       ((CHANNEL) == TIM_CHANNEL_3) ||           \
42864       ((CHANNEL) == TIM_CHANNEL_4)))            \
42865      ||                                         \
42866      (((INSTANCE) == TIM8_NS)    &&              \
42867      (((CHANNEL) == TIM_CHANNEL_1) ||           \
42868       ((CHANNEL) == TIM_CHANNEL_2) ||           \
42869       ((CHANNEL) == TIM_CHANNEL_3) ||           \
42870       ((CHANNEL) == TIM_CHANNEL_4)))            \
42871      ||                                         \
42872      (((INSTANCE) == TIM15_NS)   &&              \
42873      ((CHANNEL) == TIM_CHANNEL_1))              \
42874      ||                                         \
42875      (((INSTANCE) == TIM16_NS)   &&              \
42876      ((CHANNEL) == TIM_CHANNEL_1))              \
42877      ||                                         \
42878      (((INSTANCE) == TIM17_NS)   &&              \
42879      ((CHANNEL) == TIM_CHANNEL_1)))
42880 
42881 /****************** TIM Instances : supporting clock division *****************/
42882 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
42883                                                     ((INSTANCE) == TIM2_NS)  || \
42884                                                     ((INSTANCE) == TIM3_NS)  || \
42885                                                     ((INSTANCE) == TIM4_NS)  || \
42886                                                     ((INSTANCE) == TIM5_NS)  || \
42887                                                     ((INSTANCE) == TIM8_NS)  || \
42888                                                     ((INSTANCE) == TIM9_NS)  || \
42889                                                     ((INSTANCE) == TIM12_NS) || \
42890                                                     ((INSTANCE) == TIM15_NS) || \
42891                                                     ((INSTANCE) == TIM16_NS) || \
42892                                                     ((INSTANCE) == TIM17_NS))
42893 
42894 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
42895 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
42896                                                         ((INSTANCE) == TIM2_NS)  || \
42897                                                         ((INSTANCE) == TIM3_NS)  || \
42898                                                         ((INSTANCE) == TIM4_NS)  || \
42899                                                         ((INSTANCE) == TIM5_NS)  || \
42900                                                         ((INSTANCE) == TIM8_NS))
42901 
42902 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
42903 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
42904                                                         ((INSTANCE) == TIM2_NS)  || \
42905                                                         ((INSTANCE) == TIM3_NS)  || \
42906                                                         ((INSTANCE) == TIM4_NS)  || \
42907                                                         ((INSTANCE) == TIM5_NS)  || \
42908                                                         ((INSTANCE) == TIM8_NS))
42909 
42910 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
42911 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1_NS)  || \
42912                                                         ((INSTANCE) == TIM2_NS)  || \
42913                                                         ((INSTANCE) == TIM3_NS)  || \
42914                                                         ((INSTANCE) == TIM4_NS)  || \
42915                                                         ((INSTANCE) == TIM5_NS)  || \
42916                                                         ((INSTANCE) == TIM8_NS)  || \
42917                                                         ((INSTANCE) == TIM9_NS)  || \
42918                                                         ((INSTANCE) == TIM12_NS) || \
42919                                                         ((INSTANCE) == TIM15_NS))
42920 
42921 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
42922 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1_NS)  || \
42923                                                         ((INSTANCE) == TIM2_NS)  || \
42924                                                         ((INSTANCE) == TIM3_NS)  || \
42925                                                         ((INSTANCE) == TIM4_NS)  || \
42926                                                         ((INSTANCE) == TIM5_NS)  || \
42927                                                         ((INSTANCE) == TIM8_NS)  || \
42928                                                         ((INSTANCE) == TIM9_NS)  || \
42929                                                         ((INSTANCE) == TIM12_NS) || \
42930                                                         ((INSTANCE) == TIM15_NS))
42931 
42932 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
42933 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
42934                                                      ((INSTANCE) == TIM8_NS))
42935 
42936 /****************** TIM Instances : supporting commutation event generation ***/
42937 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
42938                                                      ((INSTANCE) == TIM8_NS)  || \
42939                                                      ((INSTANCE) == TIM15_NS) || \
42940                                                      ((INSTANCE) == TIM16_NS) || \
42941                                                      ((INSTANCE) == TIM17_NS))
42942 
42943 /****************** TIM Instances : supporting counting mode selection ********/
42944 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)  || \
42945                                                         ((INSTANCE) == TIM2_NS)  || \
42946                                                         ((INSTANCE) == TIM3_NS)  || \
42947                                                         ((INSTANCE) == TIM4_NS)  || \
42948                                                         ((INSTANCE) == TIM5_NS)  || \
42949                                                         ((INSTANCE) == TIM8_NS))
42950 
42951 /****************** TIM Instances : supporting encoder interface **************/
42952 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)  || \
42953                                                       ((INSTANCE) == TIM2_NS)  || \
42954                                                       ((INSTANCE) == TIM3_NS)  || \
42955                                                       ((INSTANCE) == TIM4_NS)  || \
42956                                                       ((INSTANCE) == TIM5_NS)  || \
42957                                                       ((INSTANCE) == TIM8_NS))
42958 
42959 /****************** TIM Instances : supporting Hall sensor interface **********/
42960 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
42961                                                          ((INSTANCE) == TIM2_NS)  || \
42962                                                          ((INSTANCE) == TIM3_NS)  || \
42963                                                          ((INSTANCE) == TIM4_NS)  || \
42964                                                          ((INSTANCE) == TIM5_NS)  || \
42965                                                          ((INSTANCE) == TIM8_NS)  || \
42966                                                          ((INSTANCE) == TIM9_NS)  || \
42967                                                          ((INSTANCE) == TIM12_NS) || \
42968                                                          ((INSTANCE) == TIM15_NS))
42969 
42970 /**************** TIM Instances : external trigger input available ************/
42971 #define IS_TIM_ETR_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1_NS)  || \
42972                                              ((INSTANCE) == TIM2_NS)  || \
42973                                              ((INSTANCE) == TIM3_NS)  || \
42974                                              ((INSTANCE) == TIM4_NS)  || \
42975                                              ((INSTANCE) == TIM5_NS)  || \
42976                                              ((INSTANCE) == TIM8_NS))
42977 
42978 /************* TIM Instances : supporting ETR source selection ***************/
42979 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || \
42980                                              ((INSTANCE) == TIM2_NS)  || \
42981                                              ((INSTANCE) == TIM3_NS)  || \
42982                                              ((INSTANCE) == TIM4_NS)  || \
42983                                              ((INSTANCE) == TIM5_NS)  || \
42984                                              ((INSTANCE) == TIM8_NS))
42985 
42986 /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
42987 #define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
42988                                             ((INSTANCE) == TIM2_NS)  || \
42989                                             ((INSTANCE) == TIM3_NS)  || \
42990                                             ((INSTANCE) == TIM4_NS)  || \
42991                                             ((INSTANCE) == TIM5_NS)  || \
42992                                             ((INSTANCE) == TIM6_NS)  || \
42993                                             ((INSTANCE) == TIM7_NS)  || \
42994                                             ((INSTANCE) == TIM8_NS)  || \
42995                                             ((INSTANCE) == TIM9_NS)  || \
42996                                             ((INSTANCE) == TIM12_NS) || \
42997                                             ((INSTANCE) == TIM15_NS))
42998 
42999 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
43000 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || \
43001                                             ((INSTANCE) == TIM2_NS)  || \
43002                                             ((INSTANCE) == TIM3_NS)  || \
43003                                             ((INSTANCE) == TIM4_NS)  || \
43004                                             ((INSTANCE) == TIM5_NS)  || \
43005                                             ((INSTANCE) == TIM8_NS)  || \
43006                                             ((INSTANCE) == TIM9_NS)  || \
43007                                             ((INSTANCE) == TIM12_NS) || \
43008                                             ((INSTANCE) == TIM15_NS))
43009 
43010 /****************** TIM Instances : supporting OCxREF clear *******************/
43011 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
43012                                                 ((INSTANCE) == TIM2_NS)  || \
43013                                                 ((INSTANCE) == TIM3_NS)  || \
43014                                                 ((INSTANCE) == TIM4_NS)  || \
43015                                                 ((INSTANCE) == TIM5_NS)  || \
43016                                                 ((INSTANCE) == TIM8_NS)  || \
43017                                                 ((INSTANCE) == TIM15_NS) || \
43018                                                 ((INSTANCE) == TIM16_NS) || \
43019                                                 ((INSTANCE) == TIM17_NS))
43020 
43021 /****************** TIM Instances : remapping capability **********************/
43022 #define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || \
43023                                             ((INSTANCE) == TIM2_NS)  || \
43024                                             ((INSTANCE) == TIM3_NS)  || \
43025                                             ((INSTANCE) == TIM4_NS)  || \
43026                                             ((INSTANCE) == TIM5_NS)  || \
43027                                             ((INSTANCE) == TIM8_NS))
43028 
43029 /****************** TIM Instances : supporting repetition counter *************/
43030 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)  || \
43031                                                        ((INSTANCE) == TIM8_NS)  || \
43032                                                        ((INSTANCE) == TIM15_NS) || \
43033                                                        ((INSTANCE) == TIM16_NS) || \
43034                                                        ((INSTANCE) == TIM17_NS))
43035 
43036 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
43037 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || \
43038                                             ((INSTANCE) == TIM8_NS))
43039 
43040 /******************* TIM Instances : Timer input XOR function *****************/
43041 #define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1_NS)  || \
43042                                             ((INSTANCE) == TIM2_NS)  || \
43043                                             ((INSTANCE) == TIM3_NS)  || \
43044                                             ((INSTANCE) == TIM4_NS)  || \
43045                                             ((INSTANCE) == TIM5_NS)  || \
43046                                             ((INSTANCE) == TIM8_NS)  || \
43047                                             ((INSTANCE) == TIM9_NS)  || \
43048                                             ((INSTANCE) == TIM12_NS) || \
43049                                             ((INSTANCE) == TIM15_NS))
43050 
43051 /******************* TIM Instances : Timer input selection ********************/
43052 #define IS_TIM_TISEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM2_NS)  || \
43053                                             ((INSTANCE) == TIM3_NS)  || \
43054                                             ((INSTANCE) == TIM5_NS)  || \
43055                                             ((INSTANCE) == TIM9_NS)  || \
43056                                             ((INSTANCE) == TIM10_NS) || \
43057                                             ((INSTANCE) == TIM11_NS) || \
43058                                             ((INSTANCE) == TIM12_NS) || \
43059                                             ((INSTANCE) == TIM13_NS) || \
43060                                             ((INSTANCE) == TIM14_NS) || \
43061                                             ((INSTANCE) == TIM15_NS) || \
43062                                             ((INSTANCE) == TIM16_NS) || \
43063                                             ((INSTANCE) == TIM17_NS))
43064 
43065 /****************** TIM Instances : Advanced timer instances *******************/
43066 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
43067                                             ((INSTANCE) == TIM8_NS))
43068 
43069 /****************************** WWDG Instances *******************************/
43070 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG_NS)
43071 
43072 /******************************** XSPI Instances *****************************/
43073 #define IS_XSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == XSPI1_NS) || \
43074                                         ((INSTANCE) == XSPI2_NS) || \
43075                                         ((INSTANCE) == XSPI3_NS))
43076 
43077 /****************************** XSPIM Instances ***************************/
43078 #define IS_XSPIM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == XSPIM_NS)
43079 
43080 #endif
43081 
43082 /** @} */ /* End of group STM32N6xx_Peripheral_Exported_macros */
43083 
43084 /** @} */ /* End of group STM32N657xx */
43085 
43086 /** @} */ /* End of group ST */
43087 
43088 #ifdef __cplusplus
43089  }
43090 #endif /* __cplusplus */
43091 
43092 #endif /* STM32N657xx_H */
43093