/** ****************************************************************************** * @file stm32n657xx.h * @author MCD Application Team * @brief CMSIS STM32N657xx Device Peripheral Access Layer Header File. * * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention * * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ #ifndef STM32N657xx_H #define STM32N657xx_H #ifdef __cplusplus extern "C" { #endif /** @addtogroup ST * @{ */ /** @addtogroup STM32N657xx * @{ */ /** @addtogroup Configuration_of_CMSIS * @{ */ /* =========================================================================================================================== */ /* ================ Interrupt Number Definition ================ */ /* =========================================================================================================================== */ typedef enum { /* ====================================== ARM Cortex-M55 Specific Interrupt Numbers ======================================== */ NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) SecureFault_IRQn = -9, /*!< -9 Secure Fault */ #endif SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ SysTick_IRQn = -1, /*!< -1 System Tick Timer */ /* ====================================== STM32N6xx Specific Interrupt Numbers ============================================= */ PVD_PVM_IRQn = 0, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection */ DTS_IRQn = 2, /*!< Thermal Sensor interruption */ RCC_IRQn = 3, /*!< RCC non-secure global interrupts through EXTI Line detection */ LOCKUP_IRQn = 4, /*!< LOCKUP / (no Overstack in CM55) */ CACHE_ECC_IRQn = 5, /*!< Error ECC cache interrupt */ TCM_ECC_IRQn = 6, /*!< TCM ECC interrupts */ BKP_ECC_IRQn = 7, /*!< Backup RAM Interrupts */ FPU_IRQn = 8, /*!< FPU interrupt */ RTC_S_IRQn = 10, /*!< RTC secure interrupts through EXTI Line detection */ TAMP_IRQn = 11, /*!< Tamper secure and non-secure interrupts through EXTI Line detection */ RIFSC_TAMPER_IRQn = 12, /*!< RIF Tamper interrupts */ IAC_IRQn = 13, /*!< IAC interrupt */ RCC_S_IRQn = 14, /*!< RCC secure global interrupts through EXTI Line detection */ RTC_IRQn = 16, /*!< RTC non-secure interrupts through EXTI Line detection */ IWDG_IRQn = 18, /*!< Internal Watchdog interrupt */ WWDG_IRQn = 19, /*!< Window Watchdog interrupt */ EXTI0_IRQn = 20, /*!< EXTI Line0 interrupt */ EXTI1_IRQn = 21, /*!< EXTI Line1 interrupt */ EXTI2_IRQn = 22, /*!< EXTI Line2 interrupt */ EXTI3_IRQn = 23, /*!< EXTI Line3 interrupt */ EXTI4_IRQn = 24, /*!< EXTI Line4 interrupt */ EXTI5_IRQn = 25, /*!< EXTI Line5 interrupt */ EXTI6_IRQn = 26, /*!< EXTI Line6 interrupt */ EXTI7_IRQn = 27, /*!< EXTI Line7 interrupt */ EXTI8_IRQn = 28, /*!< EXTI Line8 interrupt */ EXTI9_IRQn = 29, /*!< EXTI Line9 interrupt */ EXTI10_IRQn = 30, /*!< EXTI Line10 interrupt */ EXTI11_IRQn = 31, /*!< EXTI Line11 interrupt */ EXTI12_IRQn = 32, /*!< EXTI Line12 interrupt */ EXTI13_IRQn = 33, /*!< EXTI Line13 interrupt */ EXTI14_IRQn = 34, /*!< EXTI Line14 interrupt */ EXTI15_IRQn = 35, /*!< EXTI Line15 interrupt */ SAES_IRQn = 36, /*!< SAES interrupt */ CRYP_IRQn = 37, /*!< CRYP interrupt */ PKA_IRQn = 38, /*!< PKA interrupt */ HASH_IRQn = 39, /*!< HASH interrupt */ RNG_IRQn = 40, /*!< RNG global interrupt */ MCE1_IRQn = 42, /*!< MCE1 global interrupt */ MCE2_IRQn = 43, /*!< MCE2 global interrupt */ MCE3_IRQn = 44, /*!< MCE3 global interrupt */ MCE4_IRQn = 45, /*!< MCE4 global interrupt */ ADC1_2_IRQn = 46, /*!< ADC1 & ADC2 interrupt */ CSI_IRQn = 47, /*!< CSI global interrupt */ DCMIPP_IRQn = 48, /*!< DCMIPP global interrupt */ PAHB_ERR_IRQn = 52, /*!< PAHB error interrupt */ NPU0_IRQn = 53, /*!< NPU mst_ints[0] line interrupt */ NPU1_IRQn = 54, /*!< NPU mst_ints[1] line interrupt */ NPU2_IRQn = 55, /*!< NPU mst_ints[2] line interrupt */ NPU3_IRQn = 56, /*!< NPU mst_ints[3] line interrupt */ CACHEAXI_IRQn = 57, /*!< NPU cache interrupt */ LTDC_LO_IRQn = 58, /*!< LTDC low-layer global interrupt */ LTDC_LO_ERR_IRQn = 59, /*!< LTDC low-layer error interrupt */ DMA2D_IRQn = 60, /*!< DMA2D global interrupt */ JPEG_IRQn = 61, /*!< JPEG global interrupt */ VENC_IRQn = 62, /*!< VENC global interrupt */ GFXMMU_IRQn = 63, /*!< GFXMMU global interrupt */ GFXTIM_IRQn = 64, /*!< GFXTIM global interrupt */ GPU2D_IRQn = 65, /*!< GPU2D interrupt */ GPU2D_ER_IRQn = 66, /*!< GPU2D error interrupt */ ICACHE_IRQn = 67, /*!< GPU2D cache interrupt */ HPDMA1_Channel0_IRQn = 68, /*!< HPDMA1 Channel 0 global interrupt */ HPDMA1_Channel1_IRQn = 69, /*!< HPDMA1 Channel 1 global interrupt */ HPDMA1_Channel2_IRQn = 70, /*!< HPDMA1 Channel 2 global interrupt */ HPDMA1_Channel3_IRQn = 71, /*!< HPDMA1 Channel 3 global interrupt */ HPDMA1_Channel4_IRQn = 72, /*!< HPDMA1 Channel 4 global interrupt */ HPDMA1_Channel5_IRQn = 73, /*!< HPDMA1 Channel 5 global interrupt */ HPDMA1_Channel6_IRQn = 74, /*!< HPDMA1 Channel 6 global interrupt */ HPDMA1_Channel7_IRQn = 75, /*!< HPDMA1 Channel 7 global interrupt */ HPDMA1_Channel8_IRQn = 76, /*!< HPDMA1 Channel 8 global interrupt */ HPDMA1_Channel9_IRQn = 77, /*!< HPDMA1 Channel 9 global interrupt */ HPDMA1_Channel10_IRQn = 78, /*!< HPDMA1 Channel 10 global interrupt */ HPDMA1_Channel11_IRQn = 79, /*!< HPDMA1 Channel 11 global interrupt */ HPDMA1_Channel12_IRQn = 80, /*!< HPDMA1 Channel 12 global interrupt */ HPDMA1_Channel13_IRQn = 81, /*!< HPDMA1 Channel 13 global interrupt */ HPDMA1_Channel14_IRQn = 82, /*!< HPDMA1 Channel 14 global interrupt */ HPDMA1_Channel15_IRQn = 83, /*!< HPDMA1 Channel 15 global interrupt */ GPDMA1_Channel0_IRQn = 84, /*!< GPDMA1 Channel 0 interrupt */ GPDMA1_Channel1_IRQn = 85, /*!< GPDMA1 Channel 1 interrupt */ GPDMA1_Channel2_IRQn = 86, /*!< GPDMA1 Channel 2 interrupt */ GPDMA1_Channel3_IRQn = 87, /*!< GPDMA1 Channel 3 interrupt */ GPDMA1_Channel4_IRQn = 88, /*!< GPDMA1 Channel 4 interrupt */ GPDMA1_Channel5_IRQn = 89, /*!< GPDMA1 Channel 5 interrupt */ GPDMA1_Channel6_IRQn = 90, /*!< GPDMA1 Channel 6 interrupt */ GPDMA1_Channel7_IRQn = 91, /*!< GPDMA1 Channel 7 interrupt */ GPDMA1_Channel8_IRQn = 92, /*!< GPDMA1 Channel 8 interrupt */ GPDMA1_Channel9_IRQn = 93, /*!< GPDMA1 Channel 9 interrupt */ GPDMA1_Channel10_IRQn = 94, /*!< GPDMA1 Channel 10 interrupt */ GPDMA1_Channel11_IRQn = 95, /*!< GPDMA1 Channel 11 interrupt */ GPDMA1_Channel12_IRQn = 96, /*!< GPDMA1 Channel 12 interrupt */ GPDMA1_Channel13_IRQn = 97, /*!< GPDMA1 Channel 13 interrupt */ GPDMA1_Channel14_IRQn = 98, /*!< GPDMA1 Channel 14 interrupt */ GPDMA1_Channel15_IRQn = 99, /*!< GPDMA1 Channel 15 interrupt */ I2C1_EV_IRQn = 100, /*!< I2C1 event interrupt */ I2C1_ER_IRQn = 101, /*!< I2C1 error interrupt */ I2C2_EV_IRQn = 102, /*!< I2C2 event interrupt */ I2C2_ER_IRQn = 103, /*!< I2C2 error interrupt */ I2C3_EV_IRQn = 104, /*!< I2C3 event interrupt */ I2C3_ER_IRQn = 105, /*!< I2C3 error interrupt */ I2C4_EV_IRQn = 106, /*!< I2C4 event interrupt */ I2C4_ER_IRQn = 107, /*!< I2C4 error interrupt */ I3C1_EV_IRQn = 108, /*!< I3C1 event interrupt */ I3C1_ER_IRQn = 109, /*!< I3C1 error interrupt */ I3C2_EV_IRQn = 110, /*!< I3C2 event interrupt */ I3C2_ER_IRQn = 111, /*!< I3C2 error interrupt */ TIM1_BRK_IRQn = 112, /*!< TIM1 Break interrupt */ TIM1_UP_IRQn = 113, /*!< TIM1 Update interrupt */ TIM1_TRG_COM_IRQn = 114, /*!< TIM1 Trigger and Commutation interrupt */ TIM1_CC_IRQn = 115, /*!< TIM1 Capture Compare interrupt */ TIM2_IRQn = 116, /*!< TIM2 global interrupt */ TIM3_IRQn = 117, /*!< TIM3 global interrupt */ TIM4_IRQn = 118, /*!< TIM4 global interrupt */ TIM5_IRQn = 119, /*!< TIM5 global interrupt */ TIM6_IRQn = 120, /*!< TIM6 global interrupt */ TIM7_IRQn = 121, /*!< TIM7 global interrupt */ TIM8_BRK_IRQn = 122, /*!< TIM8 Break interrupt */ TIM8_UP_IRQn = 123, /*!< TIM8 Update interrupt */ TIM8_TRG_COM_IRQn = 124, /*!< TIM8 Trigger and Commutation interrupt */ TIM8_CC_IRQn = 125, /*!< TIM8 Capture Compare interrupt */ TIM9_IRQn = 126, /*!< TIM9 global interrupt */ TIM10_IRQn = 127, /*!< TIM10 global interrupt */ TIM11_IRQn = 128, /*!< TIM11 global interrupt */ TIM12_IRQn = 129, /*!< TIM12 global interrupt */ TIM13_IRQn = 130, /*!< TIM13 global interrupt */ TIM14_IRQn = 131, /*!< TIM14 global interrupt */ TIM15_IRQn = 132, /*!< TIM15 global interrupt */ TIM16_IRQn = 133, /*!< TIM16 global interrupt */ TIM17_IRQn = 134, /*!< TIM17 global interrupt */ TIM18_IRQn = 135, /*!< TIM18 global interrupt */ LPTIM1_IRQn = 136, /*!< LPTIM1 global interrupt */ LPTIM2_IRQn = 137, /*!< LPTIM2 global interrupt */ LPTIM3_IRQn = 138, /*!< LPTIM3 global interrupt */ LPTIM4_IRQn = 139, /*!< LPTIM4 global interrupt */ LPTIM5_IRQn = 140, /*!< LPTIM5 global interrupt */ ADF1_FLT0_IRQn = 141, /*!< ADF1 Filter 0 global interrupt */ MDF1_FLT0_IRQn = 142, /*!< MDF1 Filter 0 global interrupt */ MDF1_FLT1_IRQn = 143, /*!< MDF1 Filter 1 global interrupt */ MDF1_FLT2_IRQn = 144, /*!< MDF1 Filter 2 global interrupt */ MDF1_FLT3_IRQn = 145, /*!< MDF1 Filter 3 global interrupt */ MDF1_FLT4_IRQn = 146, /*!< MDF1 Filter 4 global interrupt */ MDF1_FLT5_IRQn = 147, /*!< MDF1 Filter 5 global interrupt */ SAI1_A_IRQn = 148, /*!< Serial Audio Interface 1 block A interrupt */ SAI1_B_IRQn = 149, /*!< Serial Audio Interface 1 block B interrupt */ SAI2_A_IRQn = 150, /*!< Serial Audio Interface 2 block A interrupt */ SAI2_B_IRQn = 151, /*!< Serial Audio Interface 2 block B interrupt */ SPDIFRX1_IRQn = 152, /*!< SPDIFRX1 interrupt */ SPI1_IRQn = 153, /*!< SPI1 global interrupt */ SPI2_IRQn = 154, /*!< SPI2 global interrupt */ SPI3_IRQn = 155, /*!< SPI3 global interrupt */ SPI4_IRQn = 156, /*!< SPI4 global interrupt */ SPI5_IRQn = 157, /*!< SPI5 global interrupt */ SPI6_IRQn = 158, /*!< SPI6 global interrupt */ USART1_IRQn = 159, /*!< USART1 global interrupt */ USART2_IRQn = 160, /*!< USART2 global interrupt */ USART3_IRQn = 161, /*!< USART3 global interrupt */ UART4_IRQn = 162, /*!< UART4 global interrupt */ UART5_IRQn = 163, /*!< UART5 global interrupt */ USART6_IRQn = 164, /*!< USART3 global interrupt */ UART7_IRQn = 165, /*!< UART7 global interrupt */ UART8_IRQn = 166, /*!< UART8 global interrupt */ UART9_IRQn = 167, /*!< UART9 global interrupt */ USART10_IRQn = 168, /*!< USART10 global interrupt */ LPUART1_IRQn = 169, /*!< LPUART1 global interrupt */ XSPI1_IRQn = 170, /*!< XSPI1 global interrupt */ XSPI2_IRQn = 171, /*!< XSPI2 global interrupt */ XSPI3_IRQn = 172, /*!< XSPI3 global interrupt */ FMC_IRQn = 173, /*!< FMC global interrupt */ SDMMC1_IRQn = 174, /*!< SDMMC1 global interrupt */ SDMMC2_IRQn = 175, /*!< SDMMC2 global interrupt */ UCPD1_IRQn = 176, /*!< UCPD1 global interrupt */ USB1_OTG_HS_IRQn = 177, /*!< USB1 OTG HS interrupt */ USB2_OTG_HS_IRQn = 178, /*!< USB2 OTG HS interrupt */ ETH1_IRQn = 179, /*!< ETH1 global interrupt */ FDCAN1_IT0_IRQn = 180, /*!< FDCAN1 interrupt 0 */ FDCAN1_IT1_IRQn = 181, /*!< FDCAN1 interrupt 1 */ FDCAN2_IT0_IRQn = 182, /*!< FDCAN2 interrupt 0 */ FDCAN2_IT1_IRQn = 183, /*!< FDCAN2 interrupt 1 */ FDCAN3_IT0_IRQn = 184, /*!< FDCAN3 interrupt 0 */ FDCAN3_IT1_IRQn = 185, /*!< FDCAN3 interrupt 1 */ FDCAN_CU_IRQn = 186, /*!< FDCAN Clock Unit interrupt */ MDIOS_IRQn = 187, /*!< MDIOS global interrupt */ DCMI_PSSI_IRQn = 188, /*!< DCMI/PSSI global interrupt */ WAKEUP_PIN_IRQn = 189, /*!< Wake-up pins interrupt */ CTI_INT0_IRQn = 190, /*!< CTI INT0 interrupt */ CTI_INT1_IRQn = 191, /*!< CTI INT1 interrupt */ LTDC_UP_IRQn = 193, /*!< LTDC up-layer global interrupt */ LTDC_UP_ERR_IRQn = 194, /*!< LTDC up-layer error interrupt */ } IRQn_Type; /* =========================================================================================================================== */ /* ================ Processor and Core Peripheral Section ================ */ /* =========================================================================================================================== */ /** * @brief Configuration of the Cortex-M55 Processor and Core Peripherals */ #define __CM55_REV 0x0101U /*!< Cortex-M55 revision r1p1 */ #define __FPU_PRESENT 1U /*!< CM55 Floating Point Unit present */ #define __DSP_PRESENT 1U /*!< CM55 Digital Signal Processing Unit present */ #define __MPU_PRESENT 1U /*!< CM55 Memory Programming Unit present */ #define __ICACHE_PRESENT 1U /*!< CM55 Instruction cache present */ #define __DCACHE_PRESENT 1U /*!< CM55 Data cache present */ #define __VTOR_PRESENT 1U /*!< CM55 Vector table offset register present */ #define __PMU_PRESENT 1U /*!< CM55 Performance Monitoring Unit present */ #define __PMU_NUM_EVENTCNT 8U /*!< CM55 can monitor up to 8 PMU events */ #define __NVIC_PRIO_BITS 4U /*!< CM55 uses 4 bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ #define __SAUREGION_PRESENT 1U /*!< SAU regions present */ /** @} */ /* End of group Configuration_of_CMSIS */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define CPU_IN_SECURE_STATE #endif #define CPU_AS_TRUSTED_DOMAIN #include "core_cm55.h" /*!< ARM Cortex-M55 processor and core peripherals */ #include "system_stm32n6xx.h" /*!< STM32N6xx System */ /* =========================================================================================================================== */ /* ================ Device Specific Peripheral Section ================ */ /* =========================================================================================================================== */ /** @addtogroup STM32N6xx_peripherals * @{ */ /** * @brief Analog to Digital Converter (ADC) */ typedef struct { __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ __IO uint32_t PCSEL; /*!< ADC channel preselection register, Address offset: 0x1C */ uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x020-0x02C */ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x044-0x048 */ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ __IO uint32_t OFCFGR1; /*!< ADC offset configuration register 1, Address offset: 0x50 */ __IO uint32_t OFCFGR2; /*!< ADC offset configuration register 2, Address offset: 0x54 */ __IO uint32_t OFCFGR3; /*!< ADC offset configuration register 3, Address offset: 0x58 */ __IO uint32_t OFCFGR4; /*!< ADC offset configuration register 4, Address offset: 0x5C */ __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ __IO uint32_t GCOMP; /*!< ADC gain compensation register, Address offset: 0x70 */ uint32_t RESERVED3[3]; /*!< Reserved, Address offset: 0x074-0x07C */ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ uint32_t RESERVED4[4]; /*!< Reserved, Address offset: 0x090-0x09C */ __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */ __IO uint32_t AWD1LTR; /*!< ADC analog watchdog 1 low threshold register, Address offset: 0xA8 */ __IO uint32_t AWD1HTR; /*!< ADC analog watchdog 1 high threshold register, Address offset: 0xAC */ __IO uint32_t AWD2LTR; /*!< ADC analog watchdog 2 low threshold register, Address offset: 0xB0 */ __IO uint32_t AWD2HTR; /*!< ADC analog watchdog 2 high threshold register, Address offset: 0xB4 */ __IO uint32_t AWD3LTR; /*!< ADC analog watchdog 3 low threshold register, Address offset: 0xB8 */ __IO uint32_t AWD3HTR; /*!< ADC analog watchdog 3 high threshold register, Address offset: 0xBC */ __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xC0 */ __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xC4 */ uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x0C8-0x0CC */ __IO uint32_t OR; /*!< ADC option register, Address offset: 0xD0 */ } ADC_TypeDef; typedef struct { __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 */ uint32_t RESERVED; /*!< Reserved, Address offset: 0x304 */ __IO uint32_t CCR; /*!< ADC common control register, Address offset: 0x308 */ __IO uint32_t CDR; /*!< ADC common regular data register for dual mode, Address offset: 0x30C */ __IO uint32_t CDR2; /*!< ADC common regular data register for dual mode 32-bit, Address offset: 0x310 */ } ADC_Common_TypeDef; /** * @brief Boot and Security */ typedef struct { __IO uint32_t FVRw[384]; /*!< BSEC fuse word (0-383) value register, Address offset: 0x000-0x5FC */ uint32_t RESERVED0[128]; /*!< Reserved, Address offset: 0x600-0x7FC */ __IO uint32_t SPLOCKx[12]; /*!< BSEC sticky program lock register (0-11), Address offset: 0x800-0x82C */ uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x830-0x83C */ __IO uint32_t SWLOCKx[12]; /*!< BSEC sticky write lock register (0-11), Address offset: 0x840-0x86C */ uint32_t RESERVED2[4]; /*!< Reserved, Address offset: 0x870-0x87C */ __IO uint32_t SRLOCKx[12]; /*!< BSEC sticky reload lock register (0-11), Address offset: 0x880-0x8AC */ uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x8B0-0x8BC */ __IO uint32_t OTPVLDRx[12]; /*!< BSEC OTP valid register (0-11), Address offset: 0x8C0-0x8EC */ uint32_t RESERVED4[20]; /*!< Reserved, Address offset: 0x8F0-0x93C */ __IO uint32_t SFSRx[12]; /*!< BSEC shadowed fuses status register (0-11), Address offset: 0x940-0x96C */ uint32_t RESERVED5[165]; /*!< Reserved, Address offset: 0x970-0xC00 */ __IO uint32_t OTPCR; /*!< BSEC OTP control register, Address offset: 0xC04 */ __IO uint32_t WDR; /*!< BSEC write data register, Address offset: 0xC08 */ uint32_t RESERVED6[125]; /*!< Reserved, Address offset: 0xC0C-0xDFC */ __IO uint32_t SCRATCHRx[4]; /*!< BSEC scratch register (0-3), Address offset: 0xE00-0xE0C */ __IO uint32_t LOCKR; /*!< BSEC lock register, Address offset: 0xE10 */ __IO uint32_t JTAGINR; /*!< BSEC JTAG input register, Address offset: 0xE14 */ __IO uint32_t JTAGOUTR; /*!< BSEC JTAG output register, Address offset: 0xE18 */ uint32_t RESERVED7[2]; /*!< Reserved, Address offset: 0xE1C-0xE20 */ __IO uint32_t UNMAPR; /*!< BSEC unmap register, Address offset: 0xE24 */ uint32_t RESERVED8[6]; /*!< Reserved, Address offset: 0xE28-0xE3C */ __IO uint32_t SR; /*!< BSEC status register, Address offset: 0xE40 */ __IO uint32_t OTPSR; /*!< BSEC OTP status register, Address offset: 0xE44 */ uint32_t RESERVED9[14]; /*!< Reserved, Address offset: 0xE48-0xE7C */ __IO uint32_t EPOCHRx[2]; /*!< BSEC epoch register (0-1), Address offset: 0xE80-0xE84 */ __IO uint32_t EPOCHSELR; /*!< BSEC epoch select register, Address offset: 0xE88 */ __IO uint32_t DBGCR; /*!< BSEC debug control register, Address offset: 0xE8C */ __IO uint32_t AP_UNLOCK; /*!< BSEC AP unlock, Address offset: 0xE90 */ __IO uint32_t HDPLSR; /*!< BSEC hide protection level status register, Address offset: 0xE94 */ __IO uint32_t HDPLCR; /*!< BSEC hide protection level control register, Address offset: 0xE98 */ __IO uint32_t NEXTLR; /*!< BSEC next hide protection level register, Address offset: 0xE9C */ uint32_t RESERVED10[40]; /*!< Reserved, Address offset: 0xEA0-0xF3C */ __IO uint32_t WOSCRx[8]; /*!< BSEC write once scratch register (0-7), Address offset: 0xF40-0xF5C */ uint32_t RESERVED11[34]; /*!< Reserved, Address offset: 0xF60-0xFE4 */ __IO uint32_t HRCR; /*!< BSEC hot reset count register, Address offset: 0xFE8 */ __IO uint32_t WRCR; /*!< BSEC warm reset count register, Address offset: 0xFEC */ } BSEC_TypeDef; /** * @brief Axi Cache */ typedef struct { __IO uint32_t CR1; /*!< CACHEAXI control register 1, Address offset: 0x00 */ __IO uint32_t SR; /*!< CACHEAXI status register, Address offset: 0x04 */ __IO uint32_t IER; /*!< CACHEAXI interrupt enable register, Address offset: 0x08 */ __IO uint32_t FCR; /*!< CACHEAXI flag clear register, Address offset: 0x0C */ __IO uint32_t RHMONR; /*!< CACHEAXI read hit monitor register, Address offset: 0x10 */ __IO uint32_t RMMONR; /*!< CACHEAXI read miss monitor register, Address offset: 0x14 */ __IO uint32_t RAMMONR; /*!< CACHEAXI read-allocate miss monitor register, Address offset: 0x18 */ __IO uint32_t EVIMONR; /*!< CACHEAXI eviction monitor register, Address offset: 0x1C */ __IO uint32_t WHMONR; /*!< CACHEAXI write-hit monitor register, Address offset: 0x20 */ __IO uint32_t WMMONR; /*!< CACHEAXI write-miss monitor register, Address offset: 0x24 */ __IO uint32_t WAMMONR; /*!< CACHEAXI write-allocate miss monitor register, Address offset: 0x28 */ __IO uint32_t WTMONR; /*!< CACHEAXI write-through monitor register, Address offset: 0x2C */ uint32_t RESERVED1[52]; /*!< Reserved, Address offset: 0x30-0xFC */ __IO uint32_t CR2; /*!< CACHEAXI control register 2, Address offset: 0x100 */ __IO uint32_t CMDRSADDRR; /*!< CACHEAXI command start address register, Address offset: 0x104 */ __IO uint32_t CMDREADDRR; /*!< CACHEAXI command end address register, Address offset: 0x108 */ } CACHEAXI_TypeDef; /** * @brief CRC calculation unit */ typedef struct { __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ uint32_t RESERVED1; /*!< Reserved, 0x0C */ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ } CRC_TypeDef; /** * @brief Cryp Processor */ typedef struct { __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */ __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */ __IO uint32_t DIN; /*!< CRYP data input register, Address offset: 0x08 */ __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */ __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */ __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */ __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */ __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */ __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */ __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */ __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */ __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */ __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */ __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */ __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */ __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */ __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */ __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */ __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */ __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */ __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */ __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */ __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */ __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */ __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */ __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */ __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */ __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */ __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */ __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */ __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */ __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */ __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */ __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */ __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */ __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */ } CRYP_TypeDef; /* * @brief (CSI) */ typedef struct { __IO uint32_t CR; /*!< CSI-2 Host control register Address offset: 0x0000 */ __IO uint32_t PCR; /*!< CSI-2 Host DPHY_RX control register Address offset: 0x0004 */ uint32_t RESERVED0[2]; /*!< Reserved Address offset: 0x0008-0x000C */ __IO uint32_t VC0CFGR1; /*!< CSI-2 Host virtual channel 0 configuration register 1 Address offset: 0x0010 */ __IO uint32_t VC0CFGR2; /*!< CSI-2 Host virtual channel 0 configuration register 2 Address offset: 0x0014 */ __IO uint32_t VC0CFGR3; /*!< CSI-2 Host virtual channel 0 configuration register 3 Address offset: 0x0018 */ __IO uint32_t VC0CFGR4; /*!< CSI-2 Host virtual channel 0 configuration register 4 Address offset: 0x001C */ __IO uint32_t VC1CFGR1; /*!< CSI-2 Host virtual channel 1 configuration register 1 Address offset: 0x0020 */ __IO uint32_t VC1CFGR2; /*!< CSI-2 Host virtual channel 1 configuration register 2 Address offset: 0x0024 */ __IO uint32_t VC1CFGR3; /*!< CSI-2 Host virtual channel 1 configuration register 3 Address offset: 0x0028 */ __IO uint32_t VC1CFGR4; /*!< CSI-2 Host virtual channel 1 configuration register 4 Address offset: 0x002C */ __IO uint32_t VC2CFGR1; /*!< CSI-2 Host virtual channel 2 configuration register 1 Address offset: 0x0030 */ __IO uint32_t VC2CFGR2; /*!< CSI-2 Host virtual channel 2 configuration register 2 Address offset: 0x0034 */ __IO uint32_t VC2CFGR3; /*!< CSI-2 Host virtual channel 2 configuration register 3 Address offset: 0x0038 */ __IO uint32_t VC2CFGR4; /*!< CSI-2 Host virtual channel 2 configuration register 4 Address offset: 0x003C */ __IO uint32_t VC3CFGR1; /*!< CSI-2 Host virtual channel 3 configuration register 1 Address offset: 0x0040 */ __IO uint32_t VC3CFGR2; /*!< CSI-2 Host virtual channel 3 configuration register 2 Address offset: 0x0044 */ __IO uint32_t VC3CFGR3; /*!< CSI-2 Host virtual channel 3 configuration register 3 Address offset: 0x0048 */ __IO uint32_t VC3CFGR4; /*!< CSI-2 Host virtual channel 3 configuration register 4 Address offset: 0x004C */ __IO uint32_t LB0CFGR; /*!< CSI-2 Host line byte 0 configuration register Address offset: 0x0050 */ __IO uint32_t LB1CFGR; /*!< CSI-2 Host line byte 1 configuration register Address offset: 0x0054 */ __IO uint32_t LB2CFGR; /*!< CSI-2 Host line byte 2 configuration register Address offset: 0x0058 */ __IO uint32_t LB3CFGR; /*!< CSI-2 Host line byte 3 configuration register Address offset: 0x005C */ __IO uint32_t TIM0CFGR; /*!< CSI-2 Host timer 0 configuration register Address offset: 0x0060 */ __IO uint32_t TIM1CFGR; /*!< CSI-2 Host timer 1 configuration register Address offset: 0x0064 */ __IO uint32_t TIM2CFGR; /*!< CSI-2 Host timer 2 configuration register Address offset: 0x0068 */ __IO uint32_t TIM3CFGR; /*!< CSI-2 Host timer 3 configuration register Address offset: 0x006C */ __IO uint32_t LMCFGR; /*!< CSI-2 Host lane merger configuration register Address offset: 0x0070 */ __IO uint32_t PRGITR; /*!< CSI-2 Host program interrupt register Address offset: 0x0074 */ __IO uint32_t WDR; /*!< CSI-2 Host watchdog register Address offset: 0x0078 */ uint32_t RESERVED1; /*!< Reserved Address offset: 0x007C */ __IO uint32_t IER0; /*!< CSI-2 Host Interrupt enable register 0 Address offset: 0x0080 */ __IO uint32_t IER1; /*!< CSI-2 Host Interrupt enable register 1 Address offset: 0x0084 */ uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x0088-0x008C */ __IO uint32_t SR0; /*!< CSI-2 Host status register 0 Address offset: 0x0090 */ __IO uint32_t SR1; /*!< CSI-2 Host status register 1 Address offset: 0x0094 */ uint32_t RESERVED3[26]; /*!< Reserved Address offset: 0x0098-0x00FC */ __IO uint32_t FCR0; /*!< CSI-2 Host Flag clear register 0 Address offset: 0x0100 */ __IO uint32_t FCR1; /*!< CSI-2 Host Flag clear register 1 Address offset: 0x0104 */ uint32_t RESERVED4[2]; /*!< Reserved Address offset: 0x0108-0x010C */ __IO uint32_t SPDFR; /*!< CSI-2 Host short packet data field register Address offset: 0x0110 */ __IO uint32_t ERR1; /*!< CSI-2 Host error register 1 Address offset: 0x0114 */ __IO uint32_t ERR2; /*!< CSI-2 Host error register 2 Address offset: 0x0118 */ uint32_t RESERVED5[953]; /*!< Reserved Address offset: 0x011C-0x0FFC */ __IO uint32_t PRCR; /*!< CSI PHY reset control register Address offset: 0x1000 */ __IO uint32_t PMCR; /*!< CSI PHY mode control register Address offset: 0x1004 */ __IO uint32_t PFCR; /*!< CSI PHY frequency control register Address offset: 0x1008 */ uint32_t RESERVED6; /*!< Reserved Address offset: 0x100C */ __IO uint32_t PTCR0; /*!< CSI PHY test control register 0 Address offset: 0x1010 */ __IO uint32_t PTCR1; /*!< CSI PHY test control register 1 Address offset: 0x1014 */ __IO uint32_t PTSR; /*!< CSI PHY test status register Address offset: 0x1018 */ uint32_t RESERVED7[1017]; /*!< Reserved Address offset: 0x101C-0x1FFC */ } CSI_TypeDef; /** * @brief Debug MCU */ typedef struct { __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ __IO uint32_t APB1LFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x10 */ __IO uint32_t APB1HFZ1; /*!< Debug MCU APB1HFZ1 freeze register, Address offset: 0x14 */ __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register, Address offset: 0x18 */ __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register, Address offset: 0x1C */ __IO uint32_t APB5FZ1; /*!< Debug MCU APB5FZ1 freeze register, Address offset: 0x20 */ __IO uint32_t AHB1FZ1; /*!< Debug MCU AHB1FZ1 freeze register, Address offset: 0x24 */ __IO uint32_t AHB5FZ1; /*!< Debug MCU AHB5FZ1 freeze register, Address offset: 0x28 */ uint32_t RESERVED2[52]; /*!< Reserved, Address offset: 0x2C-0xF8 */ __IO uint32_t SR; /*!< Debug MCU status register, Address offset: 0xFC */ __IO uint32_t DBG_AUTH_HOST; /*!< Debug MCU authentication host register, Address offset: 0x100 */ __IO uint32_t DBG_AUTH_DEV; /*!< Debug MCU authentication device register, Address offset: 0x104 */ __IO uint32_t DBG_AUTH_ACK; /*!< Debug MCU acknowledge authentication register, Address offset: 0x104 */ } DBGMCU_TypeDef; /** * @brief DCMI */ typedef struct { __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ } DCMI_TypeDef; #define DCMIPP_NUM_OF_PIPES 0x03U typedef struct { uint32_t PxRIxCR1; /*! DCMIPP Pipex ROIx configuration register 1 Address offset: 0x924 + (x - 1) * 0x400, (x = 1 to 2) */ uint32_t PxRIxCR2; /*! DCMIPP Pipex ROIx configuration register 2 Address offset: 0x928 + (x - 1) * 0x400, (x = 1 to 2) */ } DCMIPP_Region_TypeDef; /* * @brief Digital camera interface pixel pipeline DCMIPP */ typedef struct { __IO uint32_t IPGR1; /*!< DCMIPP IPPLUG global register 1 Address offset: 0x000 */ __IO uint32_t IPGR2; /*!< DCMIPP IPPLUG global register 2 Address offset: 0x004 */ __IO uint32_t IPGR3; /*!< DCMIPP IPPLUG global register 3 Address offset: 0x008 */ uint32_t RESERVED0[4]; /*!< Reserved Address offset: 0x00C-0x018 */ __IO uint32_t IPGR8; /*!< DCMIPP IPPLUG identification register Address offset: 0x01C */ __IO uint32_t IPC1R1; /*!< DCMIPP IPPLUG Clientx register 1 Address offset: 0x020 + 0x10 * (x - 1), (x = 1 to 5) */ __IO uint32_t IPC1R2; /*!< DCMIPP IPPLUG Clientx register 2 Address offset: 0x024 + 0x10 * (x - 1), (x = 1 to 5) */ __IO uint32_t IPC1R3; /*!< DCMIPP IPPLUG Clientx register 3 Address offset: 0x028 + 0x10 * (x - 1), (x = 1 to 5) */ uint32_t RESERVED1; /*!< Reserved Address offset: 0x02C */ __IO uint32_t IPC2R1; /*!< DCMIPP IPPLUG Clientx register 1 Address offset: 0x030 */ __IO uint32_t IPC2R2; /*!< DCMIPP IPPLUG Clientx register 2 Address offset: 0x034 */ __IO uint32_t IPC2R3; /*!< DCMIPP IPPLUG Clientx register 3 Address offset: 0x038 */ uint32_t RESERVED2; /*!< Reserved Address offset: 0x03C */ __IO uint32_t IPC3R1; /*!< DCMIPP IPPLUG Clientx register 1 Address offset: 0x040 */ __IO uint32_t IPC3R2; /*!< DCMIPP IPPLUG Clientx register 2 Address offset: 0x044 */ __IO uint32_t IPC3R3; /*!< DCMIPP IPPLUG Clientx register 3 Address offset: 0x048 */ uint32_t RESERVED3; /*!< Reserved Address offset: 0x04C */ __IO uint32_t IPC4R1; /*!< DCMIPP IPPLUG Clientx register 1 Address offset: 0x050 */ __IO uint32_t IPC4R2; /*!< DCMIPP IPPLUG Clientx register 2 Address offset: 0x054 */ __IO uint32_t IPC4R3; /*!< DCMIPP IPPLUG Clientx register 3 Address offset: 0x058 */ uint32_t RESERVED4; /*!< Reserved Address offset: 0x05C */ __IO uint32_t IPC5R1; /*!< DCMIPP IPPLUG Clientx register 1 Address offset: 0x060 */ __IO uint32_t IPC5R2; /*!< DCMIPP IPPLUG Clientx register 2 Address offset: 0x064 */ __IO uint32_t IPC5R3; /*!< DCMIPP IPPLUG Clientx register 3 Address offset: 0x068 */ uint32_t RESERVED5[38]; /*!< Reserved Address offset: 0x06C-0x100 */ __IO uint32_t PRCR; /*!< DCMIPP parallel interface control register Address offset: 0x104 */ __IO uint32_t PRESCR; /*!< DCMIPP parallel interface embedded synchronization code register Address offset: 0x108 */ __IO uint32_t PRESUR; /*!< DCMIPP parallel interface embedded synchronization unmask register Address offset: 0x10C */ uint32_t RESERVED6[57]; /*!< Reserved Address offset: 0x110-0x1F0 */ __IO uint32_t PRIER; /*!< DCMIPP parallel interface interrupt enable register Address offset: 0x1F4 */ __IO uint32_t PRSR; /*!< DCMIPP parallel interface status register Address offset: 0x1F8 */ __IO uint32_t PRFCR; /*!< DCMIPP parallel interface interrupt clear register Address offset: 0x1FC */ uint32_t RESERVED7; /*!< Reserved Address offset: 0x200 */ __IO uint32_t CMCR; /*!< DCMIPP common configuration register Address offset: 0x204 */ __IO uint32_t CMFRCR; /*!< DCMIPP common frame counter register Address offset: 0x208 */ uint32_t RESERVED8[121]; /*!< Reserved Address offset: 0x20C-0x3EC */ __IO uint32_t CMIER; /*!< DCMIPP common interrupt enable register Address offset: 0x3F0 */ __IO uint32_t CMSR1; /*!< DCMIPP common status register 1 Address offset: 0x3F4 */ __IO uint32_t CMSR2; /*!< DCMIPP common status register 2 Address offset: 0x3F8 */ __IO uint32_t CMFCR; /*!< DCMIPP common interrupt clear register Address offset: 0x3FC */ uint32_t RESERVED9; /*!< Reserved Address offset: 0x400 */ __IO uint32_t P0FSCR; /*!< DCMIPP Pipe0 flow selection configuration register Address offset: 0x404 */ uint32_t RESERVED10[62]; /*!< Reserved Address offset: 0x408-0x4FC */ __IO uint32_t P0FCTCR; /*!< DCMIPP Pipe0 flow control configuration register Address offset: 0x500 */ __IO uint32_t P0SCSTR; /*!< DCMIPP Pipe0 stat/crop start register Address offset: 0x504 */ __IO uint32_t P0SCSZR; /*!< DCMIPP Pipe0 stat/crop size register Address offset: 0x508 */ uint32_t RESERVED11[41]; /*!< Reserved Address offset: 0x50C-0x5AC */ __IO uint32_t P0DCCNTR; /*!< DCMIPP Pipe0 dump counter register Address offset: 0x5B0 */ __IO uint32_t P0DCLMTR; /*!< DCMIPP Pipe0 dump limit register Address offset: 0x5B4 */ uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x5B8-0x5BC */ __IO uint32_t P0PPCR; /*!< DCMIPP Pipe0 pixel packer configuration register Address offset: 0x5C0 */ __IO uint32_t P0PPM0AR1; /*!< DCMIPP Pipe0 pixel packer Memory0 address register 1 Address offset: 0x5C4 */ __IO uint32_t P0PPM0AR2; /*!< DCMIPP Pipe0 pixel packer Memory0 address register 2 Address offset: 0x5C8 */ uint32_t RESERVED13; /*!< Reserved Address offset: 0x5C8-0x5CC */ __IO uint32_t P0STM0AR; /*!< DCMIPP Pipe0 status Memory0 address register Address offset: 0x5D0 */ uint32_t RESERVED14[8]; /*!< Reserved Address offset: 0x5D4-0x5F0 */ __IO uint32_t P0IER; /*!< DCMIPP Pipe0 interrupt enable register Address offset: 0x5F4 */ __IO uint32_t P0SR; /*!< DCMIPP Pipe0 status register Address offset: 0x5F8 */ __IO uint32_t P0FCR; /*!< DCMIPP Pipe0 interrupt clear register Address offset: 0x5FC */ uint32_t RESERVED15; /*!< Reserved Address offset: 0x600 */ __IO uint32_t P0CFSCR; /*!< DCMIPP Pipe0 current flow selection configuration register Address offset: 0x604 */ uint32_t RESERVED17[62]; /*!< Reserved Address offset: 0x608-0x6FC */ __IO uint32_t P0CFCTCR; /*!< DCMIPP Pipe0 current flow control configuration register Address offset: 0x700 */ __IO uint32_t P0CSCSTR; /*!< DCMIPP Pipe0 current stat/crop start register Address offset: 0x704 */ __IO uint32_t P0CSCSZR; /*!< DCMIPP Pipe0 current stat/crop size register Address offset: 0x708 */ uint32_t RESERVED18[45]; /*!< Reserved Address offset: 0x70C-0x7BC */ __IO uint32_t P0CPPCR; /*!< DCMIPP Pipe0 current pixel packer configuration register Address offset: 0x7C0 */ __IO uint32_t P0CPPM0AR1; /*!< DCMIPP Pipe0 current pixel packer Memory0 address register 1 Address offset: 0x7C4 */ __IO uint32_t P0CPPM0AR2; /*!< DCMIPP Pipe0 current pixel packer Memory0 address register 2 Address offset: */ uint32_t RESERVED19[14]; /*!< Reserved Address offset: 0x7C8-0x7FC */ __IO uint32_t P1FSCR; /*!< DCMIPP Pipe1 flow selection configuration register Address offset: 0x804 */ uint32_t RESERVED20[6]; /*!< Reserved Address offset: 0x808-0x81C */ __IO uint32_t P1SRCR; /*!< DCMIPP Pipe1 stat removal configuration register Address offset: 0x820 */ __IO uint32_t P1BPRCR; /*!< DCMIPP Pipe1 bad pixel removal control register Address offset: 0x824 */ __IO uint32_t P1BPRSR; /*!< DCMIPP Pipe1 bad pixel removal status register Address offset: 0x828 */ uint32_t RESERVED21; /*!< Reserved Address offset: 0x82C */ __IO uint32_t P1DECR; /*!< DCMIPP Pipe1 decimation register Address offset: 0x830 */ uint32_t RESERVED22[3]; /*!< Reserved Address offset: 0x834-0x83C */ __IO uint32_t P1BLCCR; /*!< DCMIPP Pipe1 black level calibration control register Address offset: 0x840 */ __IO uint32_t P1EXCR1; /*!< DCMIPP Pipe1 exposure control register 1 Address offset: 0x844 */ __IO uint32_t P1EXCR2; /*!< DCMIPP Pipe1 exposure control register 2 Address offset: 0x848 */ uint32_t RESERVED23; /*!< Reserved Address offset: 0x84C */ __IO uint32_t P1ST1CR; /*!< DCMIPP Pipe1 statistics 1 control register Address offset: 0x850 */ __IO uint32_t P1ST2CR; /*!< DCMIPP Pipe1 statistics 2 control register Address offset: 0x854 */ __IO uint32_t P1ST3CR; /*!< DCMIPP Pipe1 statistics 3 control register Address offset: 0x858 */ __IO uint32_t P1STSTR; /*!< DCMIPP Pipe1 statistics window start register Address offset: 0x85C */ __IO uint32_t P1STSZR; /*!< DCMIPP Pipe1 statistics window size register Address offset: 0x860 */ __IO uint32_t P1ST1SR; /*!< DCMIPP Pipe1 statistics 1 status register Address offset: 0x864 */ __IO uint32_t P1ST2SR; /*!< DCMIPP Pipe1 statistics 2 status register Address offset: 0x868 */ __IO uint32_t P1ST3SR; /*!< DCMIPP Pipe1 statistics 3 status register Address offset: 0x86C */ __IO uint32_t P1DMCR; /*!< DCMIPP Pipe1 demosaicing configuration register Address offset: 0x870 */ uint32_t RESERVED24[3]; /*!< Reserved Address offset: 0x874-0x87C */ __IO uint32_t P1CCCR; /*!< DCMIPP Pipe1 ColorConv configuration register Address offset: 0x880 */ __IO uint32_t P1CCRR1; /*!< DCMIPP Pipe1 ColorConv red coefficient register 1 Address offset: 0x884 */ __IO uint32_t P1CCRR2; /*!< DCMIPP Pipe1 ColorConv red coefficient register 2 Address offset: 0x888 */ __IO uint32_t P1CCGR1; /*!< DCMIPP Pipe1 ColorConv green coefficient register 1 Address offset: 0x88C */ __IO uint32_t P1CCGR2; /*!< DCMIPP Pipe1 ColorConv green coefficient register 2 Address offset: 0x890 */ __IO uint32_t P1CCBR1; /*!< DCMIPP Pipe1 ColorConv blue coefficient register 1 Address offset: 0x894 */ __IO uint32_t P1CCBR2; /*!< DCMIPP Pipe1 ColorConv blue coefficient register 2 Address offset: 0x898 */ uint32_t RESERVED25; /*!< Reserved Address offset: 0x89C */ __IO uint32_t P1CTCR1; /*!< DCMIPP Pipe1 contrast control register 1 Address offset: 0x8A0 */ __IO uint32_t P1CTCR2; /*!< DCMIPP Pipe1 contrast control register 2 Address offset: 0x8A4 */ __IO uint32_t P1CTCR3; /*!< DCMIPP Pipe1 contrast control register 3 Address offset: 0x8A8 */ uint32_t RESERVED26[21]; /*!< Reserved Address offset: 0x8AC-0x8FC */ __IO uint32_t P1FCTCR; /*!< DCMIPP Pipe1 flow control configuration register Address offset: 0x900 */ __IO uint32_t P1CRSTR; /*!< DCMIPP Pipe1 crop window start register Address offset: 0x904 */ __IO uint32_t P1CRSZR; /*!< DCMIPP Pipe1 crop window size register Address offset: 0x908 */ __IO uint32_t P1DCCR; /*!< DCMIPP Pipe1 decimation register Address offset: 0x90C */ __IO uint32_t P1DSCR; /*!< DCMIPP Pipe1 downsize configuration register Address offset: 0x910 */ __IO uint32_t P1DSRTIOR; /*!< DCMIPP Pipe1 downsize ratio register Address offset: 0x914 */ __IO uint32_t P1DSSZR; /*!< DCMIPP Pipe1 downsize destination size register Address offset: 0x918 */ uint32_t RESERVED28; /*!< Reserved Address offset: */ __IO uint32_t P1CMRICR; /*!< DCMIPP Pipe1 common ROI configuration register Address offset: 0x920 */ __IO uint32_t P1RIxCR1; /*!< DCMIPP Pipe1 ROIx configuration register 1 Address offset: 0x924 + (x - 1) * 0x8, (x = 1 to 8) */ __IO uint32_t P1RIxCR2; /*!< DCMIPP Pipe1 ROIx configuration register 2 Address offset: 0x928 + (x - 1) * 0x8, (x = 1 to 8) */ uint32_t RESERVED29[17]; /*!< Reserved Address offset: */ __IO uint32_t P1GMCR; /*!< DCMIPP Pipe1 gamma configuration register Address offset: 0x970 */ uint32_t RESERVED30[3]; /*!< Reserved Address offset: 0x974-0x97C */ __IO uint32_t P1YUVCR; /*!< DCMIPP Pipe1 YUVConv configuration register Address offset: 0x980 */ __IO uint32_t P1YUVRR1; /*!< DCMIPP Pipe1 YUVConv red coefficient register 1 Address offset: 0x984 */ __IO uint32_t P1YUVRR2; /*!< DCMIPP Pipe1 YUVConv red coefficient register 2 Address offset: 0x988 */ __IO uint32_t P1YUVGR1; /*!< DCMIPP Pipe1 YUVConv green coefficient register 1 Address offset: 0x98C */ __IO uint32_t P1YUVGR2; /*!< DCMIPP Pipe1 YUVConv green coefficient register 2 Address offset: 0x990 */ __IO uint32_t P1YUVBR1; /*!< DCMIPP Pipe1 YUVConv blue coefficient register 1 Address offset: 0x994 */ __IO uint32_t P1YUVBR2; /*!< DCMIPP Pipe1 YUV blue coefficient register 2 Address offset: 0x998 */ uint32_t RESERVED31[9]; /*!< Reserved Address offset: 0x99C-0x9BC */ __IO uint32_t P1PPCR; /*!< DCMIPP Pipe1 pixel packer configuration register Address offset: 0x9C0 */ __IO uint32_t P1PPM0AR1; /*!< DCMIPP Pipe1 pixel packer Memory0 address register 1 Address offset: 0x9C4 */ __IO uint32_t P1PPM0AR2; /*!< DCMIPP Pipe1 pixel packer Memory0 address register 2 Address offset: 0x9C8 */ __IO uint32_t P1PPM0PR; /*!< DCMIPP Pipe1 pixel packer Memory0 pitch register Address offset: 0x9CC */ __IO uint32_t P1STM0AR; /*!< DCMIPP Pipe1 status Memory0 address register Address offset: 0x9D0 */ __IO uint32_t P1PPM1AR1; /*!< DCMIPP Pipe1 pixel packer Memory1 address register 1 Address offset: 0x9D4 */ __IO uint32_t P1PPM1AR2; /*!< DCMIPP Pipe1 pixel packer Memory1 address register 2 Address offset: 0x9D8 */ __IO uint32_t P1PPM1PR; /*!< DCMIPP Pipe1 pixel packer Memory1 pitch register Address offset: 0x9DC */ __IO uint32_t P1STM1AR; /*!< DCMIPP Pipe1 status Memory1 address register Address offset: 0x9E0 */ __IO uint32_t P1PPM2AR1; /*!< DCMIPP Pipe1 pixel packer memory2 address register 1 Address offset: 0x9E4 */ __IO uint32_t P1PPM2AR2; /*!< DCMIPP Pipe1 pixel packer memory2 address register 2 Address offset: 0x9E8 */ __IO uint32_t RESERVED34; /*!< Reserved Address offset: 0x9EC */ __IO uint32_t P1STM2AR; /*!< DCMIPP Pipe1 status Memory2 address register Address offset: 0x9F0 */ __IO uint32_t P1IER; /*!< DCMIPP Pipe1 interrupt enable register Address offset: 0x9F4 */ __IO uint32_t P1SR; /*!< DCMIPP Pipe1 status register Address offset: 0x9F8 */ __IO uint32_t P1FCR; /*!< DCMIPP Pipe1 interrupt clear register Address offset: 0x9FC */ uint32_t RESERVED35; /*!< Reserved Address offset: 0xA00 */ __IO uint32_t P1CFSCR; /*!< DCMIPP Pipe1 current flow selection configuration register Address offset: 0xA04 */ uint32_t RESERVED36[7]; /*!< Reserved Address offset: 0xA08-0xA20 */ __IO uint32_t P1CBPRCR; /*!< DCMIPP Pipe1 current bad pixel removal register Address offset: 0xA24 */ uint32_t RESERVED37[6]; /*!< Reserved Address offset: 0xA28-0xA3C */ __IO uint32_t P1CBLCCR; /*!< DCMIPP Pipe1 current black level calibration control register Address offset: 0xA40 */ __IO uint32_t P1CEXCR1; /*!< DCMIPP Pipe1 current exposure control register 1 Address offset: 0xA44 */ __IO uint32_t P1CEXCR2; /*!< DCMIPP Pipe1 current exposure control register 2 Address offset: 0xA48 */ uint32_t RESERVED38; /*!< Reserved Address offset: 0xA4C */ __IO uint32_t P1CST1CR; /*!< DCMIPP Pipe1 current statistics 1 control register Address offset: 0xA50 */ __IO uint32_t P1CST2CR; /*!< DCMIPP Pipe1 current statistics 2 control register Address offset: 0xA54 */ __IO uint32_t P1CST3CR; /*!< DCMIPP Pipe1 current statistics 3 control register Address offset: 0xA58 */ __IO uint32_t P1CSTSTR; /*!< DCMIPP Pipe1 current statistics window start register Address offset: 0xA5C */ __IO uint32_t P1CSTSZR; /*!< DCMIPP Pipe1 current statistics window size register Address offset: 0xA60 */ uint32_t RESERVED39[7]; /*!< Reserved Address offset: 0xA64-0xA7C */ __IO uint32_t P1CCCCR; /*!< DCMIPP Pipe1 current ColorConv configuration register Address offset: 0xA80 */ __IO uint32_t P1CCCRR1; /*!< DCMIPP Pipe1 current ColorConv red coefficient register 1 Address offset: 0xA84 */ __IO uint32_t P1CCCRR2; /*!< DCMIPP Pipe1 current ColorConv red coefficient register 2 Address offset: 0xA88 */ __IO uint32_t P1CCCGR1; /*!< DCMIPP Pipe1 current ColorConv green coefficient register 1 Address offset: 0xA8C */ __IO uint32_t P1CCCGR2; /*!< DCMIPP Pipe1 current ColorConv green coefficient register 2 Address offset: 0xA90 */ __IO uint32_t P1CCCBR1; /*!< DCMIPP Pipe1 current ColorConv blue coefficient register 1 Address offset: 0xA94 */ __IO uint32_t P1CCCBR2; /*!< DCMIPP Pipe1 current ColorConv blue coefficient register 2 Address offset: 0xA98 */ uint32_t RESERVED40; /*!< Reserved Address offset: 0xA9C */ __IO uint32_t P1CCTCR1; /*!< DCMIPP Pipe1 current contrast control register 1 Address offset: 0xAA0 */ __IO uint32_t P1CCTCR2; /*!< DCMIPP Pipe1 current contrast control register 2 Address offset: 0xAA4 */ __IO uint32_t P1CCTCR3; /*!< DCMIPP Pipe1 current contrast control register 3 Address offset: 0xAA8 */ uint32_t RESERVED41[21]; /*!< Reserved Address offset: 0xAAC-0xAFC */ __IO uint32_t P1CFCTCR; /*!< DCMIPP Pipe1 current flow control configuration register Address offset: 0xB00 */ __IO uint32_t P1CCRSTR; /*!< DCMIPP Pipe1 current crop window start register Address offset: 0xB04 */ __IO uint32_t P1CCRSZR; /*!< DCMIPP Pipe1 current crop window size register Address offset: 0xB08 */ __IO uint32_t P1CDCCR; /*!< DCMIPP Pipe1 current decimation register Address offset: 0xB0C */ __IO uint32_t P1CDSCR; /*!< DCMIPP Pipe1 current downsize configuration register Address offset: 0xB10 */ __IO uint32_t P1CDSRTIOR; /*!< DCMIPP Pipe1 current downsize ratio register Address offset: 0xB14 */ __IO uint32_t P1CDSSZR; /*!< DCMIPP Pipe1 current downsize destination size register Address offset: 0xB18 */ uint32_t RESERVED43; /*!< Reserved Address offset: 0xB1C */ uint32_t P1CCMRICR; /*!< DCMIPP Pipe1 current common ROI configuration register Address offset: 0xB20 */ __IO uint32_t P1CRIxCR1; /*!< DCMIPP Pipe1 current ROIx configuration register 1 Address offset: 0xB24 + 0x8 * (x - 1), (x = 1 to 8) */ __IO uint32_t P1CRIxCR2; /*!< DCMIPP Pipe1 current ROIx configuration register 2 Address offset: 0xB28 + 0x8 * (x - 1), (x = 1 to 8) */ uint32_t RESERVED44[37]; /*!< Reserved Address offset: 0xB64-0xBBC */ __IO uint32_t P1CPPCR; /*!< DCMIPP Pipe1 current pixel packer configuration register Address offset: 0xBC0 */ __IO uint32_t P1CPPM0AR1; /*!< DCMIPP Pipe1 current pixel packer Memory0 address register 1 Address offset: 0xBC4 */ __IO uint32_t P1CPPM0AR2; /*!< DCMIPP Pipe1 current pixel packer Memory0 address register 1 Address offset: 0xBC8 */ __IO uint32_t P1CPPM0PR; /*!< DCMIPP Pipe1 current pixel packer Memory0 pitch register Address offset: 0xBCC */ uint32_t RESERVED45; /*!< Reserved Address offset: 0xBD0 */ __IO uint32_t P1CPPM1AR1; /*!< DCMIPP Pipe1 current pixel packer Memory1 address register 1 Address offset: 0xBD4 */ __IO uint32_t P1CPPM1AR2; /*!< DCMIPP Pipe1 current pixel packer Memory1 address register 2 Address offset: 0xBD8 */ __IO uint32_t P1CPPM1PR; /*!< DCMIPP Pipe1 current pixel packer Memory1 pitch register Address offset: 0xBDC */ uint32_t RESERVED47; /*!< Reserved Address offset: 0xBE0 */ __IO uint32_t P1CPPM2AR1; /*!< DCMIPP Pipe1 current pixel packer memory2 address register 1 Address offset: 0xBE4 */ __IO uint32_t P1CPPM2AR2; /*!< DCMIPP Pipe1 current pixel packer Memory2 address register 2 Address offset: 0xBE8 */ uint32_t RESERVED48[6]; /*!< Reserved Address offset: 0xBE8-0xBFC */ __IO uint32_t P2FSCR; /*!< DCMIPP Pipe2 flow selection configuration register Address offset: 0xC04 */ uint32_t RESERVED49[62]; /*!< Reserved Address offset: 0xC08-0xCFC */ __IO uint32_t P2FCTCR; /*!< DCMIPP Pipe2 flow control configuration register Address offset: 0xD00 */ __IO uint32_t P2CRSTR; /*!< DCMIPP Pipe2 crop window start register Address offset: 0xD04 */ __IO uint32_t P2CRSZR; /*!< DCMIPP Pipe2 crop window size register Address offset: 0xD08 */ __IO uint32_t P2DCCR; /*!< DCMIPP Pipe2 decimation register Address offset: 0xD0C */ __IO uint32_t P2DSCR; /*!< DCMIPP Pipe2 downsize configuration register Address offset: 0xD10 */ __IO uint32_t P2DSRTIOR; /*!< DCMIPP Pipe2 downsize ratio register Address offset: 0xD14 */ __IO uint32_t P2DSSZR; /*!< DCMIPP Pipe2 downsize destination size register Address offset: 0xD18 */ uint32_t RESERVED51; /*!< Reserved Address offset: 0xD1C */ __IO uint32_t P2CMRICR; /*!< DCMIPP Pipe2 common ROI configuration register Address offset: 0xD20 */ __IO uint32_t P2RIxCR1; /*!< DCMIPP Pipe2 ROIx configuration register 1 Address offset: 0xD24 + (x - 1) * 0x8, (x = 1 to 8) */ __IO uint32_t P2RIxCR2; /*!< DCMIPP Pipe2 ROIx configuration register 2 Address offset: 0xD28 + (x - 1) * 0x8, (x = 1 to 8) */ uint32_t RESERVED53[17]; /*!< Reserved Address offset: */ __IO uint32_t P2GMCR; /*!< DCMIPP Pipe2 gamma configuration register Address offset: 0xD70 */ uint32_t RESERVED54[19]; /*!< Reserved Address offset: 0xD74-0xDBC */ __IO uint32_t P2PPCR; /*!< DCMIPP Pipe2 pixel packer configuration register Address offset: 0xDC0 */ __IO uint32_t P2PPM0AR1; /*!< DCMIPP Pipe2 pixel packer Memory0 address register 1 Address offset: 0xDC4 */ __IO uint32_t P2PPM0AR2; /*!< DCMIPP Pipe2 pixel packer Memory0 address register 2 Address offset: 0xDC8 */ __IO uint32_t P2PPM0PR; /*!< DCMIPP Pipe2 pixel packer Memory0 pitch register Address offset: 0xDCC */ __IO uint32_t P2STM0AR; /*!< DCMIPP Pipe2 status Memory0 address register Address offset: 0xDD0 */ uint32_t RESERVED55[8]; /*!< Reserved Address offset: 0xDD4-0xDF0 */ __IO uint32_t P2IER; /*!< DCMIPP Pipe2 interrupt enable register Address offset: 0xDF4 */ __IO uint32_t P2SR; /*!< DCMIPP Pipe2 status register Address offset: 0xDF8 */ __IO uint32_t P2FCR; /*!< DCMIPP Pipe2 interrupt clear register Address offset: 0xDFC */ uint32_t RESERVED56; /*!< Reserved Address offset: 0xE00 */ __IO uint32_t P2CFSCR; /*!< DCMIPP Pipe2 current flow selection configuration register Address offset: 0xE04 */ uint32_t RESERVED57[62]; /*!< Reserved Address offset: 0xE08-0xEFC */ __IO uint32_t P2CFCTCR; /*!< DCMIPP Pipe2 current flow control configuration register Address offset: 0xF00 */ __IO uint32_t P2CCRSTR; /*!< DCMIPP Pipe2 current crop window start register Address offset: 0xF04 */ __IO uint32_t P2CCRSZR; /*!< DCMIPP Pipe2 current crop window size register Address offset: 0xF08 */ __IO uint32_t P2CDCCR; /*!< DCMIPP Pipe2 current decimation register Address offset: 0xF0C */ __IO uint32_t P2CDSCR; /*!< DCMIPP Pipe2 current downsize configuration register Address offset: 0xF10 */ __IO uint32_t P2CDSRTIOR; /*!< DCMIPP Pipe2 current downsize ratio register Address offset: 0xF14 */ __IO uint32_t P2CDSSZR; /*!< DCMIPP Pipe2 current downsize destination size register Address offset: 0xF18 */ __IO uint32_t RESERVED59[2]; /*!< Reserved Address offset: 0xF1C-0xF20 */ __IO uint32_t P2CRIxCR1; /*!< Pipe2 current ROIx configuration register 1 Address offset: 0xF24 + (x - 1) * 0x8, (x = 1 to 8)*/ __IO uint32_t P2CRIxCR2; /*!< Pipe2 current ROIx configuration register 2 Address offset: 0xF28 + (x - 1) * 0x8, (x = 1 to 8)*/ uint32_t RESERVED60[37]; /*!< Reserved Address offset: 0xF64-0xFBC */ __IO uint32_t P2CPPCR; /*!< DCMIPP Pipe2 current pixel packer configuration register Address offset: 0xFC0 */ __IO uint32_t P2CPPM0AR1; /*!< DCMIPP Pipe2 current pixel packer Memory0 address register 1 Address offset: 0xFC4 */ __IO uint32_t P2CPPM0AR2; /*!< DCMIPP Pipe2 current pixel packer Memory0 address register 2 Address offset: 0xFC8 */ __IO uint32_t P2CPPM0PR; /*!< DCMIPP Pipe2 current pixel packer Memory0 pitch register Address offset: 0xFCC */ uint32_t RESERVED61[7]; /*!< Reserved Address offset: 0xFD0-0xFE8 */ __IO uint32_t HWCFGR2; /*!< DCMIPP hardware configuration register 2 Address offset: 0xFEC */ __IO uint32_t HWCFGR1; /*!< DCMIPP hardware configuration register 1 Address offset: 0xFF0 */ __IO uint32_t VERR; /*!< DCMIPP version register Address offset: 0xFF4 */ __IO uint32_t IPIDR; /*!< DCMIPP identification register Address offset: 0xFF8 */ __IO uint32_t SIDR; /*!< DCMIPP size identification register Address offset: 0xFFC */ } DCMIPP_TypeDef; /** * @ brief Delay Block */ typedef struct { __IO uint32_t CR; /*!< Delay Block Control Register, Address offset: 0x00 */ __IO uint32_t CFGR; /*!< Delay Block Configuration Register, Address offset: 0x04 */ } DLYB_TypeDef; /** * @brief DMA Controller */ typedef struct { __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ __IO uint32_t RCFGLOCKR; /*!< DMA configuration lock register, Address offset: 0x08 */ __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ } DMA_TypeDef; typedef struct { __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ __IO uint32_t CCIDCFGR; /*!< DMA channel x CID register, Address offset: 0x54 + (x * 0x80) */ uint32_t RESERVED1[1]; /*!< Reserved 1, Address offset: 0x58 + (x * 0x80) */ __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ uint32_t RESERVED2[10]; /*!< Reserved 2, Address offset: 0x68 -- 0x8C + (x * 0x80) */ __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 + (x * 0x80) */ __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ } DMA_Channel_TypeDef; /** * @brief DMA2D Controller */ typedef struct { __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ uint32_t RESERVED[236]; /*!< Reserved, Address offset: 0x50-0x3FF */ __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:0x400-0x7FF */ __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:0x800-0xBFF */ } DMA2D_TypeDef; /** * @brief DTS Controller */ typedef struct { uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x00-0x0F */ __IO uint32_t PVTREG_LOCKR; /*!< DTS PVT Register Lock Register, Address offset: 0x10 */ __IO uint32_t PVTLOCK_SR; /*!< DTS PVT Lock Status Register, Address offset: 0x14 */ uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x18-0x1F */ __IO uint32_t PVTTMR_CR; /*!< DTS PVT Timer Control Register, Address offset: 0x20 */ __IO uint32_t PVTTMR_SR; /*!< DTS PVT Timer Status Register, Address offset: 0x24 */ uint32_t RESERVED3[6]; /*!< Reserved, Address offset: 0x28-0x3F */ __IO uint32_t PVT_IER; /*!< DTS PVT IRQ Enable Register, Address offset: 0x40 */ uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4F */ __IO uint32_t PVTIRQTRMASKR; /*!< DTS PVT IRQ Timer Mask Register, Address offset: 0x50 */ __IO uint32_t TS_MR; /*!< DTS PVT IRQ TS Mask Register, Address offset: 0x54 */ uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x58-0x5F */ __IO uint32_t PVTTR_SR; /*!< DTS PVT IRQ Timer Status Register, Address offset: 0x60 */ __IO uint32_t TS_ISR; /*!< DTS PVT IRQ TS Status Register, Address offset: 0x64 */ uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x68-0x6F */ __IO uint32_t PVTTMRRAW_ISR; /*!< DTS PVT IRQ Timer Raw Status Register, Address offset: 0x70 */ __IO uint32_t TSRAW_ISR; /*!< DTS PVT IRQ TS Raw Status Register, Address offset: 0x74 */ uint32_t RESERVED7[2]; /*!< Reserved, Address offset: 0x78-0x7F */ __IO uint32_t TSCCLKSYNTHR; /*!< DTS TSC Clock Synthesizer Register, Address offset: 0x80 */ __IO uint32_t TSCSDIFDISABLER; /*!< DTS TSC SDIF Interface Disable Register, Address offset: 0x84 */ __IO uint32_t TSCSDIF_SR; /*!< DTS TSC SDIF Status Register, Address offset: 0x88 */ __IO uint32_t TSCSDIF_CR; /*!< DTS TSC SDIF Register, Address offset: 0x8C */ __IO uint32_t TSCSDIFHALTR; /*!< DTS TSC SDIF Halt Register, Address offset: 0x90 */ __IO uint32_t TSCSDIF_CFGR; /*!< DTS TSC SDIF Control Register, Address offset: 0x94 */ uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0x98-0x9F */ __IO uint32_t TSCSMPL_CR; /*!< DTS TSC Sample Control Register, Address offset: 0xA0 */ __IO uint32_t TSCSDIFSMPLCLRR; /*!< DTS TSC Sample Clear Register, Address offset: 0xA4 */ __IO uint32_t TSCSMPLCNTR; /*!< DTS TSC Sample Count Register, Address offset: 0xA8 */ } DTS_TypeDef; /** * @brief DTS Sensor Controller */ typedef struct { __IO uint32_t TS_IER; /*!< DTS TSx IRQ Enable Register, Address offset: 0xC0 + 0x40 * x, (x = 0 to 1) */ __IO uint32_t TS_ISR; /*!< DTS TSx IRQ Status Register, Address offset: 0xC4 + 0x40 * x, (x = 0 to 1) */ __IO uint32_t TS_ICR; /*!< DTS TSx IRQ Clear Register, Address offset: 0xC8 + 0x40 * x, (x = 0 to 1) */ __IO uint32_t TSIRQTESTR; /*!< DTS TSx IRQ Test Register, Address offset: 0xCC + 0x40 * x, (x = 0 to 1) */ __IO uint32_t TSSDIFRDATAR; /*!< DTS TSx SDIF RDATA Register, Address offset: 0xD0 + 0x40 * x, (x = 0 to 1) */ __IO uint32_t TSSDIFDONER; /*!< DTS TSx SDIF Done Register, Address offset: 0xD4 + 0x40 * x, (x = 0 to 1) */ __IO uint32_t TSSDIFDATAR; /*!< DTS TSx SDIF Data Register, Address offset: 0xD8 + 0x40 * x, (x = 0 to 1) */ uint32_t RESERVED1[1]; /*!< Reserved, Address offset: 0xDC + 0x40 * x, (x = 0 to 1) */ __IO uint32_t TSALARMA_CFGR; /*!< DTS TSx Alarm A Configuration Register, Address offset: 0xE0 + 0x40 * x, (x = 0 to 1) */ __IO uint32_t TSALARMB_CFGR; /*!< DTS TSx Alarm B Configuration Register, Address offset: 0xE4 + 0x40 * x, (x = 0 to 1) */ __IO uint32_t TSHLSAMPLER; /*!< DTS TSx High/Low Sample Register, Address offset: 0xE8 + 0x40 * x, (x = 0 to 1) */ __IO uint32_t TSHILORESETR; /*!< DTS TSx High/Low Reset Register, Address offset: 0xEC + 0x40 * x, (x = 0 to 1) */ } DTS_SensorTypeDef; /** * @brief Ethernet MAC */ typedef struct { __IO uint32_t MACCR; /*!< Operating mode configuration register, Address offset: 0x00 */ __IO uint32_t MACECR; /*!< Extended operating mode configuration register, Address offset: 0x04 */ __IO uint32_t MACPFR; /*!< Packet filtering control register , Address offset: 0x08 */ __IO uint32_t MACWTR; /*!< Watchdog timeout register, Address offset: 0x0C */ __IO uint32_t MACHT0R; /*!< Hash Table 0 register, Address offset: 0x10 */ __IO uint32_t MACHT1R; /*!< Hash Table 1 register, Address offset: 0x14 */ uint32_t RESERVED1[14]; __IO uint32_t MACVTCR; /*!< VLAN tag Control register, Address offset: 0x50 */ __IO uint32_t MACVTDR; /*!< VLAN tag data register, Address offset: 0x54 */ __IO uint32_t MACVHTR; /*!< VLAN Hash table register, Address offset: 0x58 */ uint32_t RESERVED2; __IO uint32_t MACVIR; /*!< VLAN inclusion register, Address offset: 0x60 */ __IO uint32_t MACIVIR; /*!< Inner VLAN inclusion register, Address offset: 0x64 */ uint32_t RESERVED3[2]; __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register, Address offset: 0x70 */ uint32_t RESERVED4[7]; __IO uint32_t MACRXFCR; /*!< Rx flow control register, Address offset: 0x90 */ __IO uint32_t MACRXQCR; /*!< Rx Queue control register, Address offset: 0x94 */ uint32_t RESERVED5[2]; __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register, Address offset: 0xA0 */ __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register, Address offset: 0xA4 */ __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register, Address offset: 0xA8 */ uint32_t RESERVED6; __IO uint32_t MACISR; /*!< Interrupt status register, Address offset: 0xB0 */ __IO uint32_t MACIER; /*!< Interrupt enable register, Address offset: 0xB4 */ __IO uint32_t MACRXTXSR; /*!< Rx Tx status register, Address offset: 0xB8 */ uint32_t RESERVED7; __IO uint32_t MACPCSR; /*!< PMT control status register, Address offset: 0xC0 */ __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register, Address offset: 0xC4 */ uint32_t RESERVED8[2]; __IO uint32_t MACLCSR; /*!< LPI control and status register, Address offset: 0xD0 */ __IO uint32_t MACLTCR; /*!< LPI timers control register, Address offset: 0xD4 */ __IO uint32_t MACLETR; /*!< LPI entry timer register, Address offset: 0xD8 */ __IO uint32_t MAC1USTCR; /*!< One-microsecond-tick counter register, Address offset: 0xDC */ uint32_t RESERVED9[6]; __IO uint32_t MACPHYCSR; /*!< PHYIF control status register, Address offset: 0xF8 */ uint32_t RESERVED10[5]; __IO uint32_t MACVR; /*!< Version register, Address offset: 0x110 */ __IO uint32_t MACDR; /*!< Debug register, Address offset: 0x114 */ uint32_t RESERVED11; __IO uint32_t MACHWF0R; /*!< HW feature 0 register, Address offset: 0x11C */ __IO uint32_t MACHWF1R; /*!< HW feature 1 register, Address offset: 0x120 */ __IO uint32_t MACHWF2R; /*!< HW feature 2 register, Address offset: 0x124 */ __IO uint32_t MACHWF3R; /*!< HW feature 3 register, Address offset: 0x128 */ uint32_t RESERVED12[53]; __IO uint32_t MACMDIOAR; /*!< MDIO address register, Address offset: 0x200 */ __IO uint32_t MACMDIODR; /*!< MDIO data register, Address offset: 0x204 */ uint32_t RESERVED13[2]; __IO uint32_t MACARPAR; /*!< ARP address register, Address offset: 0x210 */ uint32_t RESERVED14[7]; __IO uint32_t MACCSRSWCR; /*!< CSR software control register, Address offset: 0x230 */ __IO uint32_t MACFPECSR; /*!< FPE control and status register, Address offset: 0x234 */ uint32_t RESERVED15[2]; __IO uint32_t MACPRSTIMR; /*!< MAC presentation time register, Address offset: 0x0240 */ __IO uint32_t MACPRSTIMUR; /*!< MAC presentation time update register, Address offset: 0x0244 */ uint32_t RESERVED16[46]; __IO uint32_t MACA0HR; /*!< MAC Address 0 high register, Address offset: 0x0300 */ __IO uint32_t MACA0LR; /*!< MAC Address 0 low register, Address offset: 0x0304 */ __IO uint32_t MACA1HR; /*!< MAC Address 1 high register, Address offset: 0x0308 */ __IO uint32_t MACA1LR; /*!< MAC Address 1 low register, Address offset: 0x030C */ __IO uint32_t MACA2HR; /*!< MAC Address 2 high register, Address offset: 0x0310 */ __IO uint32_t MACA2LR; /*!< MAC Address 2 low register, Address offset: 0x0314 */ __IO uint32_t MACA3HR; /*!< MAC Address 3 high register, Address offset: 0x0318 */ __IO uint32_t MACA3LR; /*!< MAC Address 3 low register, Address offset: 0x031C */ uint32_t RESERVED17[248]; __IO uint32_t MMCCR; /*!< MMC control register, Address offset: 0x0700 */ __IO uint32_t MMCRIR; /*!< MMC Rx interrupt register, Address offset: 0x0704 */ __IO uint32_t MMCTIR; /*!< MMC Tx interrupt register, Address offset: 0x0708 */ __IO uint32_t MMCRIMR; /*!< MMC Rx interrupt mask register, Address offset: 0x070C */ __IO uint32_t MMCTIMR; /*!< MMC Tx interrupt mask register, Address offset: 0x0710 */ uint32_t RESERVED18[14]; __IO uint32_t MMCTSCGPR; /*!< Tx single collision good packets register, Address offset: 0x074C */ __IO uint32_t MMCTMCGPR; /*!< Tx multiple collision good packets register, Address offset: 0x0750 */ uint32_t RESERVED19[5]; __IO uint32_t MMCTPCGR; /*!< Tx packet count good register, Address offset: 0x0768 */ uint32_t RESERVED20[10]; __IO uint32_t MMCRCRCEPR; /*!< Rx CRC error packets register, Address offset: 0x0794 */ __IO uint32_t MMCRAEPR; /*!< Rx alignment error packets register, Address offset: 0x0798 */ uint32_t RESERVED21[10]; __IO uint32_t MMCRUPGR; /*!< Rx unicast packets good register, Address offset: 0x07C4 */ uint32_t RESERVED22[9]; __IO uint32_t MMCTLPIMSTR; /*!< Tx LPI microsecond timer register, Address offset: 0x07EC */ __IO uint32_t MMCTLPITCR; /*!< Tx LPI transition counter register, Address offset: 0x07F0 */ __IO uint32_t MMCRLPIMSTR; /*!< Rx LPI microsecond counter register, Address offset: 0x07F4 */ __IO uint32_t MMCRLPITCR; /*!< Rx LPI transition counter register, Address offset: 0x07F8 */ uint32_t RESERVED23[41]; __IO uint32_t MMCFPETISR; /*!< MMC FPE Tx interrupt status register, Address offset: 0x08A0 */ __IO uint32_t MMCFPETIMR; /*!< MMC FPE Tx interrupt mask register, Address offset: 0x08A4 */ __IO uint32_t MMCFPETFCR; /*!< MMC FPE Tx fragment counter register, - Address offset: 0x08A8 */ __IO uint32_t MMCTHRCR; /*!< MMC Tx hold request counter register, Address offset: 0x08AC */ uint32_t RESERVED24[4]; __IO uint32_t MMCFPERISR; /*!< MMC FPE Rx interrupt status register, Address offset: 0x08C0 */ __IO uint32_t MMCFPERIMR; /*!< MMC FPE Rx interrupt mask register, Address offset: 0x08C4 */ __IO uint32_t MMCRPAER; /*!< MMC Rx packet assembly error register, Address offset: 0x08C8 */ __IO uint32_t MMCRPSMDER; /*!< MMC Rx packet SMD error register, Address offset: 0x08CC */ __IO uint32_t MMCRPAOKR; /*!< MMC Rx packet assembly OK register, Address offset: 0x08D0 */ __IO uint32_t MMCFPERFCR; /*!< MMC Rx FPE fragments counter register, Address offset: 0x08D4 */ uint32_t RESERVED25[10]; __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register, Address offset: 0x0900 */ __IO uint32_t MACL4A0R; /*!< Layer4 Address filter 0 register, Address offset: 0x0904 */ uint32_t RESERVED26[2]; __IO uint32_t MACL3A0R0R; /*!< Layer3 Address 0 filter 0 register, Address offset: 0x0910 */ __IO uint32_t MACL3A1R0R; /*!< Layer3 Address 1 filter 0 register, Address offset: 0x0914 */ __IO uint32_t MACL3A2R0R; /*!< Layer3 Address 2 filter 0 register, Address offset: 0x0918 */ __IO uint32_t MACL3A3R0R; /*!< Layer3 Address 3 filter 0 register, Address offset: 0x091C */ uint32_t RESERVED27[4]; __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register, Address offset: 0x0930 */ __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register, Address offset: 0x0934 */ uint32_t RESERVED28[2]; __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register, Address offset: 0x0940 */ __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register, Address offset: 0x0944 */ __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register, Address offset: 0x0948 */ __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register, Address offset: 0x094C */ uint32_t RESERVED29[72]; __IO uint32_t MACIACR; /*!< MAC Indirect Access Control register, Address offset: 0x0A70 */ __IO uint32_t MACTMRQR; /*!< MAC type-based Rx Queue mapping register, Address offset: 0x0A74 */ uint32_t RESERVED30[34]; __IO uint32_t MACTSCR; /*!< Timestamp control Register, Address offset: 0x0B00 */ __IO uint32_t MACSSIR; /*!< Subsecond increment register, Address offset: 0x0B04 */ __IO uint32_t MACSTSR; /*!< System time seconds register, Address offset: 0x0B08 */ __IO uint32_t MACSTNR; /*!< System time nanoseconds register, Address offset: 0x0B0C */ __IO uint32_t MACSTSUR; /*!< System time seconds update register, Address offset: 0x0B10 */ __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register, Address offset: 0x0B14 */ __IO uint32_t MACTSAR; /*!< Timestamp addend register, Address offset: 0x0B18 */ uint32_t RESERVED31; __IO uint32_t MACTSSR; /*!< Timestamp status register, Address offset: 0x0B20 */ uint32_t RESERVED32[3]; __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register, Address offset: 0x0B30 */ __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register, Address offset: 0x0B34 */ uint32_t RESERVED33[2]; __IO uint32_t MACACR; /*!< Auxiliary control register, Address offset: 0x0B40 */ uint32_t RESERVED34; __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register, Address offset: 0x0B48 */ __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register, Address offset: 0x0B4C */ __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register, Address offset: 0x0B50 */ __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register, Address offset: 0x0B54 */ __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register, Address offset: 0x0B58 */ __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register, Address offset: 0x0B5C */ uint32_t RESERVED35[2]; __IO uint32_t MACTSILR; /*!< Timestamp Ingress Latency register, Address offset: 0x0B68 */ __IO uint32_t MACTSELR; /*!< Timestamp Egress Latency register, Address offset: 0x0B6C */ __IO uint32_t MACPPSCR; /*!< PPS control register, Address offset: 0x0B70 */ uint32_t RESERVED36[3]; __IO uint32_t MACPPSTTS0R; /*!< PPS 0 target time seconds register, Address offset: 0x0B80 */ __IO uint32_t MACPPSTTN0R; /*!< PPS 0 target time nanoseconds register, Address offset: 0x0B84 */ __IO uint32_t MACPPSI0R; /*!< PPS 0 interval register, Address offset: 0x0B88 */ __IO uint32_t MACPPSW0R; /*!< PPS 0 width register, Address offset: 0x0B8C */ __IO uint32_t MACPPSTTS1R; /*!< PPS 1 target time seconds register, Address offset: 0x0B90 */ __IO uint32_t MACPPSTTN1R; /*!< PPS 1 target time nanoseconds register, Address offset: 0x0B94 */ __IO uint32_t MACPPSI1R; /*!< PPS 1 interval register, Address offset: 0x0B98 */ __IO uint32_t MACPPSW1R; /*!< PPS 1 width register, Address offset: 0x0B9C */ uint32_t RESERVED37[8]; __IO uint32_t MACPOCR; /*!< PTP Offload control register, Address offset: 0x0BC0 */ __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register, Address offset: 0x0BC4 */ __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register, Address offset: 0x0BC8 */ __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register, Address offset: 0x0BCC */ __IO uint32_t MACLMIR; /*!< Log message interval register, Address offset: 0x0BD0 */ uint32_t RESERVED38[11]; __IO uint32_t MTLOMR; /*!< Operating mode Register, Address offset: 0x0C00 */ uint32_t RESERVED39[7]; __IO uint32_t MTLISR; /*!< Interrupt status Register, Address offset: 0x0C20 */ uint32_t RESERVED40[3]; __IO uint32_t MTLRXQDMAMR; /*!< Rx Queue and DMA Channel Mapping Register, Address offset: 0x0C30 */ uint32_t RESERVED41[3]; __IO uint32_t MTLTBSCR; /*!< TBS control register, Address offset: 0x0C40 */ uint32_t RESERVED42[3]; __IO uint32_t MTLESTCR; /*!< EST Control Register, Address offset: 0x0C50 */ __IO uint32_t MTLESTECR; /*!< EST Extended Control Register, Address offset: 0x0C54 */ __IO uint32_t MTLESTSR; /*!< EST Status Register, Address offset: 0x0C58 */ uint32_t RESERVED43; __IO uint32_t MTLESTSCHER; /*!< EST Schedule Error Register, Address offset: 0x0C60 */ __IO uint32_t MTLESTFSER; /*!< EST Frame size Error Register, Address offset: 0x0C64 */ __IO uint32_t MTLESTFSCR; /*!< EST Frame size Capture Register, Address offset: 0x0C68 */ uint32_t RESERVED44; __IO uint32_t MTLESTIER; /*!< EST Interrupt Enable Register, Address offset: 0x0C70 */ uint32_t RESERVED45[3]; __IO uint32_t MTLESTGCLCR; /*!< EST Gate Control List Register, Address offset: 0x0C80 */ __IO uint32_t MTLESTGCLDR; /*!< EST Gate Control List Data Register, Address offset: 0x0C84 */ uint32_t RESERVED46[2]; __IO uint32_t MTLFPECSR; /*!< FPE Frame Preemption Control Status Register, Address offset: 0x0C90 */ __IO uint32_t MTLFPEAR; /*!< FPE Frame Preemption Advance Register, Address offset: 0x0C94 */ uint32_t RESERVED47[26]; struct { __IO uint32_t MTLTXQOMR; /*!< Tx queue x operating mode Register, Address offset: 0x0D00 */ __IO uint32_t MTLTXQUR; /*!< Tx queue x underflow register, Address offset: 0x0D04 */ __IO uint32_t MTLTXQDR; /*!< Tx queue x debug register, Address offset: 0x0D08 */ uint32_t RESERVED48[1]; __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register, Address offset: 0x0D50 */ __IO uint32_t MTLTXQESR; /*!< Tx queue x ETS status Register, Address offset: 0x0D14 */ __IO uint32_t MTLTXQQWR; /*!< Tx queue x quantum weight register, Address offset: 0x0D18 */ __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register, Address offset: 0x0D5C */ __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register, Address offset: 0x0D60 */ __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register, Address offset: 0x0D64 */ uint32_t RESERVED49[1]; __IO uint32_t MTLQICSR; /*!< Queue 0 interrupt control status Register, Address offset: 0x0D2C */ __IO uint32_t MTLRXQOMR; /*!< Rx queue x operating mode register, Address offset: 0x0D30 */ __IO uint32_t MTLRXQMPOCR; /*!< Rx queue x missed packet and overflow counter register, Address offset: 0x0D34 */ __IO uint32_t MTLRXQDR; /*!< Rx queue x debug register, Address offset: 0x0D38 */ __IO uint32_t MTLRXQCR; /*!< Rx queue x control register, Address offset: 0x0D3C */ } MTL_QUEUE[2]; uint32_t RESERVED52[160]; __IO uint32_t DMAMR; /*!< DMA mode register, Address offset: 0x1000 */ __IO uint32_t DMASBMR; /*!< System bus mode register, Address offset: 0x1004 */ __IO uint32_t DMAISR; /*!< Interrupt status register, Address offset: 0x1008 */ __IO uint32_t DMADSR; /*!< Debug status register, Address offset: 0x100C */ uint32_t RESERVED53[4]; __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register, Address offset: 0x1020 */ __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register, Address offset: 0x1024 */ __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register, Address offset: 0x1028 */ uint32_t RESERVED54[5]; __IO uint32_t DMALPIEI; /*!< AXI4 LPI Entry Interval register, Address offset: 0x1040 */ uint32_t RESERVED55[3]; __IO uint32_t DMATBSCTRL0R; /*!< DMA TBS control register 0, Address offset: 0x1050 */ uint32_t RESERVED56[37]; struct { uint32_t RESERVED57[6]; __IO uint32_t DMACCR; /*!< Channel x control register, Address offset: 0x1100 */ __IO uint32_t DMACTXCR; /*!< Channel x transmit control register, Address offset: 0x1104 */ __IO uint32_t DMACRXCR; /*!< Channel x receive control register, Address offset: 0x1108 */ uint32_t RESERVED58[2]; __IO uint32_t DMACTXDLAR; /*!< Channel x Tx descriptor list address register, Address offset: 0x1114 */ uint32_t RESERVED59; __IO uint32_t DMACRXDLAR; /*!< Channel x Rx descriptor list address register, Address offset: 0x111C */ __IO uint32_t DMACTXDTPR; /*!< Channel x Tx descriptor tail pointer register, Address offset: 0x1120 */ uint32_t RESERVED60; __IO uint32_t DMACRXDTPR; /*!< Channel x Rx descriptor tail pointer register, Address offset: 0x1128 */ __IO uint32_t DMACTXRLR; /*!< Channel x Tx descriptor ring length register, Address offset: 0x112C */ __IO uint32_t DMACRXRLR; /*!< Channel x Rx descriptor ring length register, Address offset: 0x1130 */ __IO uint32_t DMACIER; /*!< Channel x interrupt enable register, Address offset: 0x1134 */ __IO uint32_t DMACRXIWTR; /*!< Channel x Rx interrupt watchdog timer register, Address offset: 0x1138 */ __IO uint32_t DMACSFCSR; /*!< Channel x slot function control status register, Address offset: 0x113C */ uint32_t RESERVED61; __IO uint32_t DMACCATXDR; /*!< Channel x current application transmit descriptor register, Address offset: 0x1144 */ uint32_t RESERVED62; __IO uint32_t DMACCARXDR; /*!< Channel x current application receive descriptor register, Address offset: 0x114C */ uint32_t RESERVED63; __IO uint32_t DMACCATXBR; /*!< Channel x current application transmit buffer register, Address offset: 0x1154 */ uint32_t RESERVED64; __IO uint32_t DMACCARXBR; /*!< Channel x current application receive buffer register, Address offset: 0x115C */ __IO uint32_t DMACSR; /*!< Channel x status register, Address offset: 0x1160 */ __IO uint32_t DMACMFCR; /*!< Channel x missed frame count register, Address offset: 0x1164 */ } DMA_CH[2]; }ETH_TypeDef; /** * @brief External Interrupt/Event Controller */ typedef struct { __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ uint32_t RESERVED1; /*!< Reserved 1, Address offset: 0x1C */ __IO uint32_t RTSR2; /*!< EXTI Rising Trigger Selection Register 2, Address offset: 0x20 */ __IO uint32_t FTSR2; /*!< EXTI Falling Trigger Selection Register 2, Address offset: 0x24 */ __IO uint32_t SWIER2; /*!< EXTI Software Interrupt event Register 2, Address offset: 0x28 */ __IO uint32_t RPR2; /*!< EXTI Rising Pending Register 2, Address offset: 0x2C */ __IO uint32_t FPR2; /*!< EXTI Falling Pending Register 2, Address offset: 0x30 */ __IO uint32_t SECCFGR2; /*!< EXTI Security Configuration Register 2, Address offset: 0x34 */ __IO uint32_t PRIVCFGR2; /*!< EXTI Privilege Configuration Register 2, Address offset: 0x38 */ uint32_t RESERVED2; /*!< Reserved 2, Address offset: 0x3C */ __IO uint32_t RTSR3; /*!< EXTI Rising Trigger Selection Register 3, Address offset: 0x40 */ __IO uint32_t FTSR3; /*!< EXTI Falling Trigger Selection Register 3, Address offset: 0x44 */ __IO uint32_t SWIER3; /*!< EXTI Software Interrupt event Register 3, Address offset: 0x48 */ __IO uint32_t RPR3; /*!< EXTI Rising Pending Register 3, Address offset: 0x4C */ __IO uint32_t FPR3; /*!< EXTI Falling Pending Register 3, Address offset: 0x50 */ __IO uint32_t SECCFGR3; /*!< EXTI Security Configuration Register 3, Address offset: 0x54 */ __IO uint32_t PRIVCFGR3; /*!< EXTI Privilege Configuration Register 3, Address offset: 0x58 */ uint32_t RESERVED3; /*!< Reserved 3, Address offset: 0x5C */ __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ uint32_t RESERVED4[3]; /*!< Reserved 4, 0x74 -- 0x7C */ __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ uint32_t RESERVED5[2]; /*!< Reserved 5, 0x88 -- 0x8C */ __IO uint32_t IMR2; /*!< EXTI Interrupt Mask Register 2, Address offset: 0x90 */ __IO uint32_t EMR2; /*!< EXTI Event Mask Register 2, Address offset: 0x94 */ uint32_t RESERVED6[2]; /*!< Reserved 6, 0x98 -- 0x9C */ __IO uint32_t IMR3; /*!< EXTI Interrupt Mask Register 3, Address offset: 0xA0 */ __IO uint32_t EMR3; /*!< EXTI Event Mask Register 3, Address offset: 0xA4 */ } EXTI_TypeDef; /** * @brief FD Controller Area Network */ typedef struct { __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */ __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */ __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */ __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */ __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */ __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */ __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */ __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */ __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */ __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */ __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */ __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */ __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */ __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */ __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */ __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */ __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */ __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */ __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */ __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */ __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */ __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */ __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */ __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */ __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */ __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */ __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */ __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */ __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */ __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */ } FDCAN_GlobalTypeDef; /** * @brief TTFD Controller Area Network */ typedef struct { __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */ __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */ __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */ __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */ __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */ __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */ __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */ __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */ __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */ __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */ __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */ __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */ __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */ __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */ __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */ __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */ __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */ __IO uint32_t RESERVED1[111];/*!< Reserved, 0x144 - 0x2FC */ __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */ } TTCAN_TypeDef; /** * @brief FD Controller Area Network */ typedef struct { __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */ __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */ __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */ __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */ __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */ __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */ } FDCAN_ClockCalibrationUnit_TypeDef; /** * @brief FD Controller Area Network Configuration */ typedef struct { __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ uint32_t RESERVED1[128]; /*!< Reserved, 0x100 + 0x004 - 0x100 + 0x200 */ __IO uint32_t OPTR; /*!< FDCAN option register, Address offset: 0x100 + 0x204 */ uint32_t RESERVED2[58]; /*!< Reserved, 0x100 + 0x208 - 0x100 + 0x2EC */ __IO uint32_t HWCFG; /*!< FDCAN hardware configuration register, Address offset: 0x100 + 0x2F0 */ __IO uint32_t VERR; /*!< FDCAN IP version register, Address offset: 0x100 + 0x2F4 */ __IO uint32_t IPIDR; /*!< FDCAN IP ID register, Address offset: 0x100 + 0x2F8 */ __IO uint32_t SIDR; /*!< FDCAN size ID register, Address offset: 0x100 + 0x2FC */ } FDCAN_Config_TypeDef; /** * @brief Flexible Memory Controller Bank1 */ typedef struct { __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ } FMC_Bank1_TypeDef; /** * @brief Flexible Memory Controller Bank1E */ typedef struct { __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ } FMC_Bank1E_TypeDef; /** * @brief Flexible Memory Controller Bank2 */ typedef struct { __IO uint32_t SDCR[2]; /*!< SDRAM device 1/2 control register Address offset: 0x140-0x144 */ __IO uint32_t SDTR; /*!< SDRAM timing register Address offset: 0x148 */ uint32_t RESERVED0; /*!< Reserved Address offset: 0x14C */ __IO uint32_t SDCMR; /*!< SDRAM command mode register Address offset: 0x150 */ __IO uint32_t SDRTR; /*!< SDRAM refresh timer register Address offset: 0x154 */ __IO uint32_t SDSR; /*!< SDRAM status register Address offset: 0x158 */ } FMC_Bank5_6_TypeDef; /** * @brief Flexible Memory Controller Bank3 */ typedef struct { __IO uint32_t PCR; /*!< NAND Flash Programmable control register Address offset: 0x080 */ __IO uint32_t SR; /*!< FMC status register Address offset: 0x084 */ __IO uint32_t PMEM; /*!< Common memory space timing register Address offset: 0x088 */ __IO uint32_t PATT; /*!< Attribute memory space timing registers Address offset: 0x08C */ __IO uint32_t HPR; /*!< FMC Hamming parity result registers Address offset: 0x090 */ __IO uint32_t HECCR; /*!< FMC Hamming code ECC result register Address offset: 0x094 */ uint32_t RESERVED0[58]; /*!< Reserved Address offset: 0x098-0x17C */ __IO uint32_t IER; /*!< FMC NAND Interrupt Enable Register Address offset: 0x180 */ __IO uint32_t ISR; /*!< FMC Controller Interrupt Status Register Address offset: 0x184 */ __IO uint32_t ICR; /*!< FMC NAND Controller Interrupt Clear Register Address offset: 0x188 */ uint32_t RESERVED1[29]; /*!< Reserved Address offset: 0x18C-0x1FC */ __IO uint32_t CSQCR; /*!< FMC NAND Command Sequencer Control Register Address offset: 0x200 */ __IO uint32_t CSQCFGR1; /*!< FMC NAND Command Sequencer Configuration Register 1 Address offset: 0x204 */ __IO uint32_t CSQCFGR2; /*!< FMC NAND Command Sequencer Configuration Register 2 Address offset: 0x208 */ __IO uint32_t CSQCFGR3; /*!< FMC NAND sequencer configuration register 3 Address offset: 0x20C */ __IO uint32_t CSQAR1; /*!< FMC NAND Command Sequencer Address Register 1 Address offset: 0x210 */ __IO uint32_t CSQAR2; /*!< FMC NAND Command Sequencer Address Register 2 Address offset: 0x214 */ uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x218-0x21C */ __IO uint32_t CSQIER; /*!< FMC NAND Command Sequencer Interrupt Enable Register Address offset: 0x220 */ __IO uint32_t CSQISR; /*!< FMC NAND Command Sequencer Interrupt Status Register Address offset: 0x224 */ __IO uint32_t CSQICR; /*!< FMC NAND Command Sequencer Interrupt Clear Register Address offset: 0x228 */ uint32_t RESERVED3; /*!< Reserved Address offset: 0x22C */ __IO uint32_t CSQEMSR; /*!< FMC Command Sequencer Error Mapping Status register Address offset: 0x230 */ uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x234-0x24C */ __IO uint32_t BCHIER; /*!< FMC BCH Interrupt enable register Address offset: 0x250 */ __IO uint32_t BCHISR; /*!< FMC BCH Interrupt and Status Register Address offset: 0x254 */ __IO uint32_t BCHICR; /*!< FMC BCH Interrupt Clear Register Address offset: 0x258 */ uint32_t RESERVED5; /*!< Reserved Address offset: 0x25C */ __IO uint32_t BCHPBR1; /*!< FMC BCH Parity Bits Register 1 Address offset: 0x260 */ __IO uint32_t BCHPBR2; /*!< FMC BCH Parity Bits Register 2 Address offset: 0x264 */ __IO uint32_t BCHPBR3; /*!< FMC BCH Parity Bits Register 3 Address offset: 0x268 */ __IO uint32_t BCHPBR4; /*!< FMC BCH Parity Bits Register 4 Address offset: 0x26C */ uint32_t RESERVED6[3]; /*!< Reserved Address offset: 0x270-0x278 */ __IO uint32_t BCHDSR0; /*!< FMC BCH Decoder Status register 0 Address offset: 0x27C */ __IO uint32_t BCHDSR1; /*!< FMC BCH Decoder Status register for bank 1 Address offset: 0x280 */ __IO uint32_t BCHDSR2; /*!< FMC BCH Decoder Status register for bank 2 Address offset: 0x284 */ __IO uint32_t BCHDSR3; /*!< FMC BCH Decoder Status register for bank 3 Address offset: 0x288 */ __IO uint32_t BCHDSR4; /*!< FMC BCH Decoder Status register for bank 4 Address offset: 0x28C */ } FMC_Bank3_TypeDef; /** * @brief Flexible Memory Controller Common */ typedef struct{ __IO uint32_t CFGR; /*!< FMC common configuration register Address offset: 0x020 */ } FMC_Common_TypeDef; /** * @brief General Purpose I/O */ typedef struct { __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ uint32_t RESERVED0; /*!< Reserved, Address offset: 0x2C */ __IO uint32_t SECCFGR; /*!< GPIO port secure configuration register, Address offset: 0x30 */ __IO uint32_t PRIVCFGR; /*!< GPIO port privileged configuration register, Address offset: 0x34 */ __IO uint32_t RCFGLOCKR; /*!< GPIO port resource configuration register, Address offset: 0x38 */ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x3C */ __IO uint32_t DELAYR[2]; /*!< GPIO port delay register, Address offset: 0x40-0x44 */ __IO uint32_t ADVCFGR[2]; /*!< GPIO port advanced configuration register, Address offset: 0x48-0x4C */ } GPIO_TypeDef; /** * @brief GFXMMU */ typedef struct { __IO uint32_t CR; /*!< GFXMMU configuration register, Address offset: 0x00 */ __IO uint32_t SR; /*!< GFXMMU status register, Address offset: 0x04 */ __IO uint32_t FCR; /*!< GFXMMU flag clear register, Address offset: 0x08 */ uint32_t RESERVED0; /*!< Reserved0, Address offset: 0x0C */ __IO uint32_t DVR; /*!< GFXMMU default value register, Address offset: 0x10 */ __IO uint32_t DAR; /*!< GFXMMU default alpha register, Address offset: 0x14 */ uint32_t RESERVED1[2]; /*!< Reserved1, Address offset: 0x18 to 0x1C */ __IO uint32_t B0CR; /*!< GFXMMU buffer 0 configuration register, Address offset: 0x20 */ __IO uint32_t B1CR; /*!< GFXMMU buffer 1 configuration register, Address offset: 0x24 */ __IO uint32_t B2CR; /*!< GFXMMU buffer 2 configuration register, Address offset: 0x28 */ __IO uint32_t B3CR; /*!< GFXMMU buffer 3 configuration register, Address offset: 0x2C */ uint32_t RESERVED2[1012]; /*!< Reserved2, Address offset: 0x30 to 0xFFC */ __IO uint32_t LUT[2048]; /*!< GFXMMU LUT registers, Address offset: 0x1000 to 0x2FFC For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */ } GFXMMU_TypeDef; /** * @brief GFXTIM */ typedef struct { __IO uint32_t CR; /*!< GFXTIM configuration register, Address offset: 0x00 */ __IO uint32_t CGCR; /*!< GFXTIM clock generator configuration register, Address offset: 0x04 */ __IO uint32_t TCR; /*!< GFXTIM timers configuration register, Address offset: 0x08 */ __IO uint32_t TDR; /*!< GFXTIM timers disable register, Address offset: 0x0C */ __IO uint32_t EVCR; /*!< GFXTIM events control register, Address offset: 0x10 */ __IO uint32_t EVSR; /*!< GFXTIM events selection register, Address offset: 0x14 */ uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ __IO uint32_t WDGTCR; /*!< GFXTIM watchdog timer configuration register, Address offset: 0x20 */ uint32_t RESERVED2[3]; /*!< Reserved, Address offset: 0x24-0x2C */ __IO uint32_t ISR; /*!< GFXTIM interrupt status register, Address offset: 0x30 */ __IO uint32_t ICR; /*!< GFXTIM interrupt clear register, Address offset: 0x34 */ __IO uint32_t IER; /*!< GFXTIM interrupt enable register, Address offset: 0x38 */ __IO uint32_t TSR; /*!< GFXTIM timers status register, Address offset: 0x3C */ __IO uint32_t LCCRR; /*!< GFXTIM line clock counter reload register, Address offset: 0x40 */ __IO uint32_t FCCRR; /*!< GFXTIM frame clock counter reload register, Address offset: 0x44 */ uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x48-0x4C */ __IO uint32_t ATR; /*!< GFXTIM absolute time register, Address offset: 0x50 */ __IO uint32_t AFCR; /*!< GFXTIM absolute frame counter register, Address offset: 0x54 */ __IO uint32_t ALCR; /*!< GFXTIM absolute line counter register, Address offset: 0x58 */ uint32_t RESERVED4[1]; /*!< Reserved, Address offset: 0x5C */ __IO uint32_t AFCC1R; /*!< GFXTIM absolute frame counter compare 1 register, Address offset: 0x60 */ uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x64-0X6C */ __IO uint32_t ALCC1R; /*!< GFXTIM absolute line counter compare 1 register, Address offset: 0x70 */ __IO uint32_t ALCC2R; /*!< GFXTIM absolute line counter compare 2 register, Address offset: 0x74 */ uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x78-0X7C */ __IO uint32_t RFC1R; /*!< GFXTIM relative frame counter 1 register, Address offset: 0x80 */ __IO uint32_t RFC1RR; /*!< GFXTIM relative frame counter 1 reload register, Address offset: 0x84 */ __IO uint32_t RFC2R; /*!< GFXTIM relative frame counter 2 register, Address offset: 0x88 */ __IO uint32_t RFC2RR; /*!< GFXTIM relative frame counter 2 reload register, Address offset: 0x8C */ uint32_t RESERVED7[4]; /*!< Reserved, Address offset: 0x90-0X9C */ __IO uint32_t WDGCR; /*!< GFXTIM watchdog counter register, Address offset: 0xA0 */ __IO uint32_t WDGRR; /*!< GFXTIM watchdog reload register, Address offset: 0xA4 */ __IO uint32_t WDGPAR; /*!< GFXTIM watchdog pre-alarm register, Address offset: 0xA8 */ uint32_t RESERVED8[209]; /*!< Reserved, Address offset: 0xAC-0X3EC */ __IO uint32_t HWCFGR; /*!< GFXTIM HW configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< GFXTIM version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< GFXTIM identification register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< GFXTIM size identification register, Address offset: 0x3FC */ } GFXTIM_TypeDef; /** * @brief HASH */ typedef struct { __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ __IO uint32_t CSR[103]; /*!< HASH context swap registers, Address offset: 0x0F8-0x290 */ } HASH_TypeDef; /** * @brief HASH_DIGEST */ typedef struct { __IO uint32_t HR[16]; /*!< HASH digest registers, Address offset: 0x310-0x34C */ } HASH_DIGEST_TypeDef; /** * @brief Inter-integrated Circuit Interface */ typedef struct { __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ } I2C_TypeDef; /** * @brief Improved Inter-integrated Circuit Interface */ typedef struct { __IO uint32_t CR; /*!< I3C Control register, Address offset: 0x00 */ __IO uint32_t CFGR; /*!< I3C Controller Configuration register, Address offset: 0x04 */ uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ __IO uint32_t RDR; /*!< I3C Received Data register, Address offset: 0x10 */ __IO uint32_t RDWR; /*!< I3C Received Data Word register, Address offset: 0x14 */ __IO uint32_t TDR; /*!< I3C Transmit Data register, Address offset: 0x18 */ __IO uint32_t TDWR; /*!< I3C Transmit Data Word register, Address offset: 0x1C */ __IO uint32_t IBIDR; /*!< I3C IBI payload Data register, Address offset: 0x20 */ __IO uint32_t TGTTDR; /*!< I3C Target Transmit register, Address offset: 0x24 */ uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x28-0x2C */ __IO uint32_t SR; /*!< I3C Status register, Address offset: 0x30 */ __IO uint32_t SER; /*!< I3C Status Error register, Address offset: 0x34 */ uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x38-0x3C */ __IO uint32_t RMR; /*!< I3C Received Message register, Address offset: 0x40 */ uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4C */ __IO uint32_t EVR; /*!< I3C Event register, Address offset: 0x50 */ __IO uint32_t IER; /*!< I3C Interrupt Enable register, Address offset: 0x54 */ __IO uint32_t CEVR; /*!< I3C Clear Event register, Address offset: 0x58 */ uint32_t RESERVED5; /*!< Reserved, Address offset: 0x5C */ __IO uint32_t DEVR0; /*!< I3C own Target characteristics register, Address offset: 0x60 */ __IO uint32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */ uint32_t RESERVED6[7]; /*!< Reserved, Address offset: 0x74-0x8C */ __IO uint32_t MAXRLR; /*!< I3C Maximum Read Length register, Address offset: 0x90 */ __IO uint32_t MAXWLR; /*!< I3C Maximum Write Length register, Address offset: 0x94 */ uint32_t RESERVED7[2]; /*!< Reserved, Address offset: 0x98-0x9C */ __IO uint32_t TIMINGR0; /*!< I3C Timing 0 register, Address offset: 0xA0 */ __IO uint32_t TIMINGR1; /*!< I3C Timing 1 register, Address offset: 0xA4 */ __IO uint32_t TIMINGR2; /*!< I3C Timing 2 register, Address offset: 0xA8 */ uint32_t RESERVED9[5]; /*!< Reserved, Address offset: 0xAC-0xBC */ __IO uint32_t BCR; /*!< I3C Bus Characteristics register, Address offset: 0xC0 */ __IO uint32_t DCR; /*!< I3C Device Characteristics register, Address offset: 0xC4 */ __IO uint32_t GETCAPR; /*!< I3C GET CAPabilities register, Address offset: 0xC8 */ __IO uint32_t CRCAPR; /*!< I3C Controller CAPabilities register, Address offset: 0xCC */ __IO uint32_t GETMXDSR; /*!< I3C GET Max Data Speed register, Address offset: 0xD0 */ __IO uint32_t EPIDR; /*!< I3C Extended Provisioned ID register, Address offset: 0xD4 */ } I3C_TypeDef; /** * @brief Illegal Access Controller */ typedef struct { __IO uint32_t IER[5]; /*!< Interrupt Enable register, Address offset: 0x000 */ uint32_t RESERVED1[27]; /*!< Reserved, Address offset: 0x014-0x07C */ __IO uint32_t ISR[5]; /*!< Interrupt Status register, Address offset: 0x080 */ uint32_t RESERVED2[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ __IO uint32_t ICR[5]; /*!< Interrupt Clear register, Address offset: 0x100 */ } IAC_TypeDef; /** * @brief Instruction Cache */ typedef struct { __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ __IO uint32_t FCR; /*!< ICACHE flag clear register, Address offset: 0x0C */ __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ } ICACHE_TypeDef; typedef struct { __IO uint32_t KR; /*!< IWDG key register Address offset: 0x000 */ __IO uint32_t PR; /*!< IWDG prescaler register Address offset: 0x004 */ __IO uint32_t RLR; /*!< IWDG reload register Address offset: 0x008 */ __IO uint32_t SR; /*!< IWDG status register Address offset: 0x00C */ __IO uint32_t WINR; /*!< IWDG window register Address offset: 0x010 */ __IO uint32_t EWCR; /*!< IWDG early wakeup interrupt register Address offset: 0x014 */ __IO uint32_t ICR; /*!< IWDG interrupt clear register Address offset: 0x018 */ } IWDG_TypeDef; /** * @brief JPEG Codec */ typedef struct { __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */ __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */ __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */ __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */ __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */ __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */ __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */ __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */ __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */ uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */ __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */ __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */ __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */ __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */ } JPEG_TypeDef; /** * @brief LCD-TFT Display Controller (LTDC) */ typedef struct { uint32_t RESERVED0[2]; /*!< Reserved Address offset: 0x00-0x04 */ __IO uint32_t SSCR; /*!< LTDC synchronization size configuration register Address offset: 0x8 */ __IO uint32_t BPCR; /*!< LTDC back porch configuration register Address offset: 0xc */ __IO uint32_t AWCR; /*!< LTDC active width configuration register Address offset: 0x10 */ __IO uint32_t TWCR; /*!< LTDC total width configuration register Address offset: 0x14 */ __IO uint32_t GCR; /*!< LTDC global control register Address offset: 0x18 */ uint32_t RESERVED1[2]; /*!< Reserved Address offset: */ __IO uint32_t SRCR; /*!< LTDC shadow reload configuration register Address offset: 0x24 */ __IO uint32_t GCCR; /*!< LTDC gamma correction configuration register Address offset: 0x28 */ __IO uint32_t BCCR; /*!< LTDC background color configuration register Address offset: 0x2c */ uint32_t RESERVED2; /*!< Reserved Address offset: 0x30 */ __IO uint32_t IER; /*!< LTDC interrupt enable register Address offset: 0x34 */ __IO uint32_t ISR; /*!< LTDC interrupt status register Address offset: 0x38 */ __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register Address offset: 0x3c */ __IO uint32_t LIPCR; /*!< LTDC line interrupt position configuration register Address offset: 0x40 */ __IO uint32_t CPSR; /*!< LTDC current position status register Address offset: 0x44 */ __IO uint32_t CDSR; /*!< LTDC current display status register Address offset: 0x48 */ uint32_t RESERVED3[5]; /*!< Reserved Address offset: 0x4c */ __IO uint32_t EDCR; /*!< LTDC external display control register Address offset: 0x60 */ __IO uint32_t IER2; /*!< LTDC interrupt enable register 2 Address offset: 0x64 */ __IO uint32_t ISR2; /*!< LTDC interrupt status register 2 Address offset: 0x68 */ __IO uint32_t ICR2; /*!< LTDC Interrupt Clear Register 2 Address offset: 0x6c */ __IO uint32_t LIPCR2; /*!< LTDC line interrupt position configuration register 2 Address offset: 0x70 */ uint32_t RESERVED4; /*!< Reserved Address offset: 0x74 */ __IO uint32_t ECRCR; /*!< LTDC expected CRC register Address offset: 0x78 */ __IO uint32_t CCRCR; /*!< LTDC computed CRC register Address offset: 0x7c */ __IO uint32_t RB0AR; /*!< LTDC rotation buffer 0 address register Address offset: 0x80 */ __IO uint32_t RB1AR; /*!< LTDC rotation buffer 1 address register Address offset: 0x84 */ __IO uint32_t RBPR; /*!< LTDC rotation buffer pitch register Address offset: 0x88 */ __IO uint32_t RIFCR; /*!< LTDC rotation intermediate frame color register Address offset: 0x8c */ __IO uint32_t FUTR; /*!< LTDC FIFO underrun threshold register Address offset: 0x90 */ } LTDC_TypeDef; /** * @brief LCD-TFT Display layer x Controller (LTDC) */ typedef struct { __IO uint32_t C0R; /*!< LTDC layer x configuration 0 register Address offset: 0x100 */ __IO uint32_t C1R; /*!< LTDC layer x configuration 1 register Address offset: 0x104 */ __IO uint32_t RCR; /*!< LTDC layer x reload control register Address offset: 0x108 */ __IO uint32_t CR; /*!< LTDC layer x control register Address offset: 0x10c */ __IO uint32_t WHPCR; /*!< LTDC layer x window horizontal position configuration register Address offset: 0x110 */ __IO uint32_t WVPCR; /*!< LTDC layer x window vertical position configuration register Address offset: 0x114 */ __IO uint32_t CKCR; /*!< LTDC layer x color keying configuration register Address offset: 0x118 */ __IO uint32_t PFCR; /*!< LTDC layer x pixel format configuration register Address offset: 0x11c */ __IO uint32_t CACR; /*!< LTDC layer x constant alpha configuration register Address offset: 0x120 */ __IO uint32_t DCCR; /*!< LTDC layer x default color configuration register Address offset: 0x124 */ __IO uint32_t BFCR; /*!< LTDC layer x blending factors configuration register Address offset: 0x128 */ __IO uint32_t BLCR; /*!< LTDC layer x burst length configuration register Address offset: 0x12c */ __IO uint32_t PCR; /*!< LTDC layer x planar configuration register Address offset: 0x130 */ __IO uint32_t CFBAR; /*!< LTDC layer x color frame buffer address register Address offset: 0x134 */ __IO uint32_t CFBLR; /*!< LTDC layer x color frame buffer length register Address offset: 0x138 */ __IO uint32_t CFBLNR; /*!< LTDC layer x color frame buffer line number register Address offset: 0x13c */ __IO uint32_t AFBA0R; /*!< LTDC layer x auxiliary frame buffer address 0 register Address offset: 0x140 */ __IO uint32_t AFBA1R; /*!< LTDC layer x auxiliary frame buffer address 1 register Address offset: 0x144 */ __IO uint32_t AFBLR; /*!< LTDC layer x auxiliary frame buffer length register Address offset: 0x148 */ __IO uint32_t AFBLNR; /*!< LTDC layer x auxiliary frame buffer line number register Address offset: 0x14c */ __IO uint32_t CLUTWR; /*!< LTDC layer x CLUT write register Address offset: 0x150 */ __IO uint32_t SISR; /*!< LTDC layer x Scaler Input Size register Address offset: 0x154 */ __IO uint32_t SOSR; /*!< LTDC layer x Scaler Output Size register Address offset: 0x158 */ __IO uint32_t SVSFR; /*!< LTDC layer x Scaler Vertical Scaling Factor register Address offset: 0x15c */ __IO uint32_t SVSPR; /*!< LTDC layer x Scaler Vertical Scaling Phase register Address offset: 0x160 */ __IO uint32_t SHSFR; /*!< LTDC layer x Scaler Horizontal Scaling Factor register Address offset: 0x164 */ __IO uint32_t SHSPR; /*!< LTDC layer x Scaler Horizontal Scaling Phase register Address offset: 0x168 */ __IO uint32_t CYR0R; /*!< LTDC layer x Conversion YCbCr RGB 0 register Address offset: 0x16c */ __IO uint32_t CYR1R; /*!< LTDC layer x Conversion YCbCr RGB 1 register Address offset: 0x170 */ __IO uint32_t FPF0R; /*!< LTDC layer x Flexible Pixel Format 0 register Address offset: 0x174 */ __IO uint32_t FPF1R; /*!< LTDC layer x Flexible Pixel Format 1 register Address offset: 0x178 */ } LTDC_Layer_TypeDef; /** * @brief LPTIMER */ typedef struct { __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x20 */ __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ __IO uint32_t RESERVED2; /*!< Reserved, Address offset: 0x30 */ __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ } LPTIM_TypeDef; /** * @brief Memory Cipher Engine (MCE) */ typedef struct { __IO uint32_t REGCR; /*!< MCE region configuration register, Address offset: 0x040 + 0x10 * (x-1) (x = 1 to 4) */ __IO uint32_t SADDR; /*!< MCE region start address register, Address offset: 0x044 + 0x10 * (x-1) (x = 1 to 4) */ __IO uint32_t EADDR; /*!< MCE region end address register, Address offset: 0x048 + 0x10 * (x-1) (x = 1 to 4) */ } MCE_Region_TypeDef; typedef struct { __IO uint32_t CCCFGR; /*!< MCE cipher context configuration register, Address offset: 0x240 + 0x30 * (x-1) (x = 1 to 2) */ __IO uint32_t CCNR0; /*!< MCE cipher context nonce register 0, Address offset: 0x244 + 0x30 * (x-1) (x = 1 to 2) */ __IO uint32_t CCNR1; /*!< MCE cipher context nonce register 1, Address offset: 0x248 + 0x30 * (x-1) (x = 1 to 2) */ __IO uint32_t CCKEYR0; /*!< MCE cipher context key register 0, Address offset: 0x24C + 0x30 * (x-1) (x = 1 to 2) */ __IO uint32_t CCKEYR1; /*!< MCE cipher context key register 1, Address offset: 0x250 + 0x30 * (x-1) (x = 1 to 2) */ __IO uint32_t CCKEYR2; /*!< MCE cipher context key register 2, Address offset: 0x254 + 0x30 * (x-1) (x = 1 to 2) */ __IO uint32_t CCKEYR3; /*!< MCE cipher context key register 3, Address offset: 0x258 + 0x30 * (x-1) (x = 1 to 2) */ } MCE_Context_TypeDef; typedef struct { __IO uint32_t CR; /*!< MCE configuration register, Address offset: 0x000 */ __IO uint32_t SR; /*!< MCE status register, Address offset: 0x004 */ __IO uint32_t IASR; /*!< MCE illegal access status register, Address offset: 0x008 */ __IO uint32_t IACR; /*!< MCE illegal access clear register, Address offset: 0x00C */ __IO uint32_t IAIER; /*!< MCE illegal access interrupt enable register, Address offset: 0x010 */ uint32_t RESERVED0[4]; /*!< Reserved, Address offset: 0x014-0x20 */ __IO uint32_t IADDR; /*!< MCE illegal address register, Address offset: 0x024 */ uint32_t RESERVED1[118]; /*!< Reserved, Address offset: 0x028-0x1FC */ __IO uint32_t MKEYR0; /*!< MCE master key register 0, Address offset: 0x200 */ __IO uint32_t MKEYR1; /*!< MCE master key register 1, Address offset: 0x204 */ __IO uint32_t MKEYR2; /*!< MCE master key register 2, Address offset: 0x208 */ __IO uint32_t MKEYR3; /*!< MCE master key register 3, Address offset: 0x20C */ __IO uint32_t MKEYR4; /*!< MCE master key register 4, Address offset: 0x210 */ __IO uint32_t MKEYR5; /*!< MCE master key register 5, Address offset: 0x214 */ __IO uint32_t MKEYR6; /*!< MCE master key register 6, Address offset: 0x218 */ __IO uint32_t MKEYR7; /*!< MCE master key register 7, Address offset: 0x21C */ __IO uint32_t FMKEYR0; /*!< MCE fast master key register 0, Address offset: 0x220 */ __IO uint32_t FMKEYR1; /*!< MCE fast master key register 1, Address offset: 0x224 */ __IO uint32_t FMKEYR2; /*!< MCE fast master key register 2, Address offset: 0x228 */ __IO uint32_t FMKEYR3; /*!< MCE fast master key register 3, Address offset: 0x22C */ __IO uint32_t FMKEYR4; /*!< MCE fast master key register 4, Address offset: 0x230 */ __IO uint32_t FMKEYR5; /*!< MCE fast master key register 5, Address offset: 0x234 */ __IO uint32_t FMKEYR6; /*!< MCE fast master key register 6, Address offset: 0x238 */ __IO uint32_t FMKEYR7; /*!< MCE fast master key register 7, Address offset: 0x23C */ } MCE_TypeDef; /** * @brief ADF */ typedef struct { __IO uint32_t GCR; /*!< MDF Global Control register, Address offset: 0x00 */ __IO uint32_t CKGCR; /*!< MDF Clock Generator Control Register, Address offset: 0x04 */ uint32_t RESERVED1[6]; /*!< Reserved, 0x08-0x1C */ __IO uint32_t OR; /*!< MDF Option Register, Address offset: 0x20 */ } MDF_TypeDef; /** * @brief ADF filter */ typedef struct { __IO uint32_t SITFCR; /*!< MDF Serial Interface Control Register, Address offset: 0x80 */ __IO uint32_t BSMXCR; /*!< MDF Bitstream Matrix Control Register, Address offset: 0x84 */ __IO uint32_t DFLTCR; /*!< MDF Digital Filter Control Register, Address offset: 0x88 */ __IO uint32_t DFLTCICR; /*!< MDF MCIC Configuration Register, Address offset: 0x8C */ __IO uint32_t DFLTRSFR; /*!< MDF Reshape Filter Configuration Register, Address offset: 0x90 */ __IO uint32_t DFLTINTR; /*!< MDF Integrator Configuration Register, Address offset: 0x94 */ __IO uint32_t OLDCR; /*!< MDF Out-Of Limit Detector Control Register, Address offset: 0x98 */ __IO uint32_t OLDTHLR; /*!< MDF OLD Threshold Low Register, Address offset: 0x9C */ __IO uint32_t OLDTHHR; /*!< MDF OLD Threshold High Register, Address offset: 0xA0 */ __IO uint32_t DLYCR; /*!< MDF Delay control Register, Address offset: 0xA4 */ __IO uint32_t SCDCR; /*!< MDF short circuit detector control Register, Address offset: 0xA8 */ __IO uint32_t DFLTIER; /*!< MDF DFLT Interrupt enable Register, Address offset: 0xAC */ __IO uint32_t DFLTISR; /*!< MDF DFLT Interrupt status Register, Address offset: 0xB0 */ __IO uint32_t OECCR; /*!< MDF Offset Error Compensation Control Register, Address offset: 0xB4 */ __IO uint32_t SADCR; /*!< MDF SAD Control Register, Address offset: 0xB8 */ __IO uint32_t SADCFGR; /*!< MDF SAD configuration register, Address offset: 0xBC */ __IO uint32_t SADSDLVR; /*!< MDF SAD Sound level Register, Address offset: 0xC0 */ __IO uint32_t SADANLVR; /*!< MDF SAD Ambient Noise level Register, Address offset: 0xC4 */ uint32_t RESERVED1[9]; /*!< Reserved, 0xC8-0xE8 */ __IO uint32_t SNPSDR; /*!< MDF Snapshot Data Register, Address offset: 0xEC */ __IO uint32_t DFLTDR; /*!< MDF Digital Filter Data Register, Address offset: 0xF0 */ } MDF_Filter_TypeDef; /** * @brief MDIOS */ typedef struct { __IO uint32_t CR; __IO uint32_t WRFR; __IO uint32_t CWRFR; __IO uint32_t RDFR; __IO uint32_t CRDFR; __IO uint32_t SR; __IO uint32_t CLRFR; uint32_t RESERVED[57]; __IO uint32_t DINR0; __IO uint32_t DINR1; __IO uint32_t DINR2; __IO uint32_t DINR3; __IO uint32_t DINR4; __IO uint32_t DINR5; __IO uint32_t DINR6; __IO uint32_t DINR7; __IO uint32_t DINR8; __IO uint32_t DINR9; __IO uint32_t DINR10; __IO uint32_t DINR11; __IO uint32_t DINR12; __IO uint32_t DINR13; __IO uint32_t DINR14; __IO uint32_t DINR15; __IO uint32_t DINR16; __IO uint32_t DINR17; __IO uint32_t DINR18; __IO uint32_t DINR19; __IO uint32_t DINR20; __IO uint32_t DINR21; __IO uint32_t DINR22; __IO uint32_t DINR23; __IO uint32_t DINR24; __IO uint32_t DINR25; __IO uint32_t DINR26; __IO uint32_t DINR27; __IO uint32_t DINR28; __IO uint32_t DINR29; __IO uint32_t DINR30; __IO uint32_t DINR31; __IO uint32_t DOUTR0; __IO uint32_t DOUTR1; __IO uint32_t DOUTR2; __IO uint32_t DOUTR3; __IO uint32_t DOUTR4; __IO uint32_t DOUTR5; __IO uint32_t DOUTR6; __IO uint32_t DOUTR7; __IO uint32_t DOUTR8; __IO uint32_t DOUTR9; __IO uint32_t DOUTR10; __IO uint32_t DOUTR11; __IO uint32_t DOUTR12; __IO uint32_t DOUTR13; __IO uint32_t DOUTR14; __IO uint32_t DOUTR15; __IO uint32_t DOUTR16; __IO uint32_t DOUTR17; __IO uint32_t DOUTR18; __IO uint32_t DOUTR19; __IO uint32_t DOUTR20; __IO uint32_t DOUTR21; __IO uint32_t DOUTR22; __IO uint32_t DOUTR23; __IO uint32_t DOUTR24; __IO uint32_t DOUTR25; __IO uint32_t DOUTR26; __IO uint32_t DOUTR27; __IO uint32_t DOUTR28; __IO uint32_t DOUTR29; __IO uint32_t DOUTR30; __IO uint32_t DOUTR31; } MDIOS_TypeDef; /** * @brief PSSI */ typedef struct { __IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */ __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */ __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ } PSSI_TypeDef; /** * @brief Power Control */ typedef struct { __IO uint32_t CR1; /*!< PWR Control register 1 Address offset: 0x000 */ __IO uint32_t CR2; /*!< PWR Control Register 2 Address offset: 0x004 */ __IO uint32_t CR3; /*!< PWR Control Register 3 Address offset: 0x008 */ __IO uint32_t CR4; /*!< PWR Control Register 4 Address offset: 0x00C */ uint32_t RESERVED0[4]; /*!< Reserved Address offset: 0x010-0x01C */ __IO uint32_t VOSCR; /*!< PWR Voltage scaling control register Address offset: 0x020 */ __IO uint32_t BDCR1; /*!< PWR Backup domain control register 1 Address offset: 0x024 */ __IO uint32_t BDCR2; /*!< PWR Backup domain control register 2 Address offset: 0x028 */ __IO uint32_t DBPCR; /*!< PWR Disable backup protection control register Address offset: 0x02C */ __IO uint32_t CPUCR; /*!< PWR CPU control register Address offset: 0x030 */ __IO uint32_t SVMCR1; /*!< PWR Supply voltage monitoring control register 1 Address offset: 0x034 */ __IO uint32_t SVMCR2; /*!< PWR Supply voltage monitoring control register 2 Address offset: 0x038 */ __IO uint32_t SVMCR3; /*!< PWR Supply voltage monitoring control register 3 Address offset: 0x03C */ uint32_t RESERVED1[4]; /*!< Reserved Address offset: 0x040-0x04C */ __IO uint32_t WKUPCR; /*!< PWR Wakeup control register 1 Address offset: 0x050 */ __IO uint32_t WKUPSR; /*!< PWR Wakeup control register 2 Address offset: 0x054 */ __IO uint32_t WKUPEPR; /*!< PWR Wakeup control register 3 Address offset: 0x058 */ uint32_t RESERVED2[5]; /*!< Reserved Address offset: 0x05C-0x06C */ __IO uint32_t SECCFGR; /*!< PWR Security configuration register Address offset: 0x070 */ __IO uint32_t PRIVCFGR; /*!< PWR Privilege configuration register Address offset: 0x074 */ } PWR_TypeDef; /** * @brief PKA */ typedef struct { __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03FC */ __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */ } PKA_TypeDef; /** * @brief RAMs configuration controller */ typedef struct { __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x04 */ __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x08 */ __IO uint32_t ESEAR; /*!< ECC Single Error Address Register, Address offset: 0x0C */ __IO uint32_t EDEAR; /*!< ECC Double Error Address Register, Address offset: 0x10 */ __IO uint32_t ICR; /*!< Interrupt Clear Register, Address offset: 0x14 */ uint32_t RESERVED[3]; /*!< Reserved, Address offset: 0x18-0x20 */ __IO uint32_t ECCKEYR; /*!< RAM ECC Key Register, Address offset: 0x24 */ __IO uint32_t ERKEYR; /*!< RAM Erase Key Register, Address offset: 0x28 */ }RAMCFG_TypeDef; /** * @brief Reset and Clock Control */ typedef struct { __IO uint32_t CR; /*!< RCC control register Address offset: 0x0000 */ __IO uint32_t SR; /*!< RCC status register Address offset: 0x0004 */ __IO uint32_t STOPCR; /*!< RCC Stop mode control register Address offset: 0x0008 */ uint32_t RESERVED0[5]; /*!< Reserved Address offset: 0x000C-0x001C */ __IO uint32_t CFGR1; /*!< RCC configuration register 1 Address offset: 0x0020 */ __IO uint32_t CFGR2; /*!< RCC configuration register 2 Address offset: 0x0024 */ uint32_t RESERVED1; /*!< Reserved Address offset: 0x0028 */ __IO uint32_t BDCR; /*!< RCC backup domain protection register Address offset: 0x002C */ __IO uint32_t HWRSR; /*!< RCC reset status register for hardware Address offset: 0x0030 */ __IO uint32_t RSR; /*!< RCC reset register Address offset: 0x0034 */ uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x0038-0x003C */ __IO uint32_t LSECFGR; /*!< RCC LSE configuration register Address offset: 0x0040 */ __IO uint32_t MSICFGR; /*!< RCC MSI configuration register Address offset: 0x0044 */ __IO uint32_t HSICFGR; /*!< RCC HSI configuration register Address offset: 0x0048 */ __IO uint32_t HSIMCR; /*!< RCC HSI Monitor control register Address offset: 0x004C */ __IO uint32_t HSIMSR; /*!< RCC HSI Monitor status register Address offset: 0x0050 */ __IO uint32_t HSECFGR; /*!< RCC HSE configuration register Address offset: 0x0054 */ uint32_t RESERVED3[10]; /*!< Reserved Address offset: 0x0058-0x007C */ __IO uint32_t PLL1CFGR1; /*!< RCC PLL1 configuration register 1 Address offset: 0x0080 */ __IO uint32_t PLL1CFGR2; /*!< RCC PLL1 configuration register 2 Address offset: 0x0084 */ __IO uint32_t PLL1CFGR3; /*!< RCC PLL1 configuration register 3 Address offset: 0x0088 */ uint32_t RESERVED4; /*!< Reserved Address offset: 0x008C */ __IO uint32_t PLL2CFGR1; /*!< RCC PLL2 configuration register 1 Address offset: 0x0090 */ __IO uint32_t PLL2CFGR2; /*!< RCC PLL2 configuration register 2 Address offset: 0x0094 */ __IO uint32_t PLL2CFGR3; /*!< RCC PLL2 configuration register 3 Address offset: 0x0098 */ uint32_t RESERVED5; /*!< Reserved Address offset: 0x009C */ __IO uint32_t PLL3CFGR1; /*!< RCC PLL3 configuration register 1 Address offset: 0x00A0 */ __IO uint32_t PLL3CFGR2; /*!< RCC PLL3 configuration register 2 Address offset: 0x00A4 */ __IO uint32_t PLL3CFGR3; /*!< RCC PLL3 configuration register 3 Address offset: 0x00A8 */ uint32_t RESERVED6; /*!< Reserved Address offset: 0x00AC */ __IO uint32_t PLL4CFGR1; /*!< RCC PLL4 configuration register 1 Address offset: 0x00B0 */ __IO uint32_t PLL4CFGR2; /*!< RCC PLL4 configuration register 2 Address offset: 0x00B4 */ __IO uint32_t PLL4CFGR3; /*!< RCC PLL4 configuration register 3 Address offset: 0x00B8 */ uint32_t RESERVED7[2]; /*!< Reserved Address offset: 0x00BC-0x00C0 */ __IO uint32_t IC1CFGR; /*!< RCC IC1 configuration register Address offset: 0x00C4 */ __IO uint32_t IC2CFGR; /*!< RCC IC2 configuration register Address offset: 0x00C8 */ __IO uint32_t IC3CFGR; /*!< RCC IC3 configuration register Address offset: 0x00CC */ __IO uint32_t IC4CFGR; /*!< RCC IC4 configuration register Address offset: 0x00D0 */ __IO uint32_t IC5CFGR; /*!< RCC IC5 configuration register Address offset: 0x00D4 */ __IO uint32_t IC6CFGR; /*!< RCC IC6 configuration register Address offset: 0x00D8 */ __IO uint32_t IC7CFGR; /*!< RCC IC7 configuration register Address offset: 0x00DC */ __IO uint32_t IC8CFGR; /*!< RCC IC8 configuration register Address offset: 0x00E0 */ __IO uint32_t IC9CFGR; /*!< RCC IC9 configuration register Address offset: 0x00E4 */ __IO uint32_t IC10CFGR; /*!< RCC IC10 configuration register Address offset: 0x00E8 */ __IO uint32_t IC11CFGR; /*!< RCC IC11 configuration register Address offset: 0x00EC */ __IO uint32_t IC12CFGR; /*!< RCC IC12 configuration register Address offset: 0x00F0 */ __IO uint32_t IC13CFGR; /*!< RCC IC13 configuration register Address offset: 0x00F4 */ __IO uint32_t IC14CFGR; /*!< RCC IC14 configuration register Address offset: 0x00F8 */ __IO uint32_t IC15CFGR; /*!< RCC IC15 configuration register Address offset: 0x00FC */ __IO uint32_t IC16CFGR; /*!< RCC IC16 configuration register Address offset: 0x0100 */ __IO uint32_t IC17CFGR; /*!< RCC IC17 configuration register Address offset: 0x0104 */ __IO uint32_t IC18CFGR; /*!< RCC IC18 configuration register Address offset: 0x0108 */ __IO uint32_t IC19CFGR; /*!< RCC IC19 configuration register Address offset: 0x010C */ __IO uint32_t IC20CFGR; /*!< RCC IC20 configuration register Address offset: 0x0110 */ uint32_t RESERVED8[4]; /*!< Reserved Address offset: 0x0114-0x0120 */ __IO uint32_t CIER; /*!< RCC clock-source interrupt enable register Address offset: 0x0124 */ __IO uint32_t CIFR; /*!< RCC clock-source interrupt flag register Address offset: 0x0128 */ __IO uint32_t CICR; /*!< RCC clock-source interrupt clear register Address offset: 0x012C */ uint32_t RESERVED9[5]; /*!< Reserved Address offset: 0x0130-0x0140 */ __IO uint32_t CCIPR1; /*!< RCC clock configuration for independent peripheral register 1 Address offset: 0x0144 */ __IO uint32_t CCIPR2; /*!< RCC clock configuration for independent peripheral register 2 Address offset: 0x0148 */ __IO uint32_t CCIPR3; /*!< RCC clock configuration for independent peripheral register 3 Address offset: 0x014C */ __IO uint32_t CCIPR4; /*!< RCC clock configuration for independent peripheral register 4 Address offset: 0x0150 */ __IO uint32_t CCIPR5; /*!< RCC clock configuration for independent peripheral register 5 Address offset: 0x0154 */ __IO uint32_t CCIPR6; /*!< RCC clock configuration for independent peripheral register 6 Address offset: 0x0158 */ __IO uint32_t CCIPR7; /*!< RCC clock configuration for independent peripheral register 7 Address offset: 0x015C */ __IO uint32_t CCIPR8; /*!< RCC clock configuration for independent peripheral register 8 Address offset: 0x0160 */ __IO uint32_t CCIPR9; /*!< RCC clock configuration for independent peripheral register 9 Address offset: 0x0164 */ uint32_t RESERVED10[2]; /*!< Reserved Address offset: 0x0168-0x016C */ __IO uint32_t CCIPR12; /*!< RCC clock configuration for independent peripheral register 12 Address offset: 0x0170 */ __IO uint32_t CCIPR13; /*!< RCC clock configuration for independent peripheral register 13 Address offset: 0x0174 */ __IO uint32_t CCIPR14; /*!< RCC clock configuration for independent peripheral register 14 Address offset: 0x0178 */ uint32_t RESERVED11[35]; /*!< Reserved Address offset: 0x017C-0x0204 */ __IO uint32_t MISCRSTR; /*!< RCC miscellaneous configurations reset register Address offset: 0x0208 */ __IO uint32_t MEMRSTR; /*!< RCC embedded memories reset register Address offset: 0x020C */ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 reset register Address offset: 0x0210 */ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 reset register Address offset: 0x0214 */ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 reset register Address offset: 0x0218 */ __IO uint32_t AHB4RSTR; /*!< RCC AHB4 reset register Address offset: 0x021C */ __IO uint32_t AHB5RSTR; /*!< RCC AHB5 reset register Address offset: 0x0220 */ __IO uint32_t APB1RSTR1; /*!< RCC APB1 reset register 1 Address offset: 0x0224 */ __IO uint32_t APB1RSTR2; /*!< RCC APB1 reset register 2 Address offset: 0x0228 */ __IO uint32_t APB2RSTR; /*!< RCC APB2 reset register Address offset: 0x022C */ uint32_t RESERVED12; /*!< Reserved Address offset: 0x0230 */ __IO uint32_t APB4RSTR1; /*!< RCC APB4 reset register 1 Address offset: 0x0234 */ __IO uint32_t APB4RSTR2; /*!< RCC APB4 reset register 2 Address offset: 0x0238 */ __IO uint32_t APB5RSTR; /*!< RCC APB5 reset register Address offset: 0x023C */ __IO uint32_t DIVENR; /*!< RCC IC dividers enable register Address offset: 0x0240 */ __IO uint32_t BUSENR; /*!< RCC embedded buses enable register Address offset: 0x0244 */ __IO uint32_t MISCENR; /*!< RCC miscellaneous configurations enable register Address offset: 0x0248 */ __IO uint32_t MEMENR; /*!< RCC embedded memories enable register Address offset: 0x024C */ __IO uint32_t AHB1ENR; /*!< RCC AHB1 enable register Address offset: 0x0250 */ __IO uint32_t AHB2ENR; /*!< RCC AHB2 enable register Address offset: 0x0254 */ __IO uint32_t AHB3ENR; /*!< RCC AHB3 enable register Address offset: 0x0258 */ __IO uint32_t AHB4ENR; /*!< RCC AHB4 enable register Address offset: 0x025C */ __IO uint32_t AHB5ENR; /*!< RCC AHB5 enable register Address offset: 0x0260 */ __IO uint32_t APB1ENR1; /*!< RCC APB1 enable register 1 Address offset: 0x0264 */ __IO uint32_t APB1ENR2; /*!< RCC APB1 enable register 2 Address offset: 0x0268 */ __IO uint32_t APB2ENR; /*!< RCC APB2 enable register Address offset: 0x026C */ __IO uint32_t APB3ENR; /*!< RCC APB3 enable register Address offset: 0x0270 */ __IO uint32_t APB4ENR1; /*!< RCC APB4 enable register 1 Address offset: 0x0274 */ __IO uint32_t APB4ENR2; /*!< RCC APB4 enable register 2 Address offset: 0x0278 */ __IO uint32_t APB5ENR; /*!< RCC APB5 enable register Address offset: 0x027C */ uint32_t RESERVED13; /*!< Reserved Address offset: 0x0280 */ __IO uint32_t BUSLPENR; /*!< RCC embedded buses sleep enable register Address offset: 0x0284 */ __IO uint32_t MISCLPENR; /*!< RCC miscellaneous configurations sleep enable register Address offset: 0x0288 */ __IO uint32_t MEMLPENR; /*!< RCC embedded memories sleep enable register Address offset: 0x028C */ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 sleep enable register Address offset: 0x0290 */ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 sleep enable register Address offset: 0x0294 */ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 sleep enable register Address offset: 0x0298 */ __IO uint32_t AHB4LPENR; /*!< RCC AHB4 sleep enable register Address offset: 0x029C */ __IO uint32_t AHB5LPENR; /*!< RCC AHB5 sleep enable register Address offset: 0x02A0 */ __IO uint32_t APB1LPENR1; /*!< RCC APB1 sleep enable register 1 Address offset: 0x02A4 */ __IO uint32_t APB1LPENR2; /*!< RCC APB1 sleep enable register 2 Address offset: 0x02A8 */ __IO uint32_t APB2LPENR; /*!< RCC APB2 sleep enable register Address offset: 0x02AC */ __IO uint32_t APB3LPENR; /*!< RCC APB3 sleep enable register Address offset: 0x02B0 */ __IO uint32_t APB4LPENR1; /*!< RCC APB4 sleep enable register 1 Address offset: 0x02B4 */ __IO uint32_t APB4LPENR2; /*!< RCC APB4 sleep enable register 2 Address offset: 0x02B8 */ __IO uint32_t APB5LPENR; /*!< RCC APB5 sleep enable register Address offset: 0x02BC */ uint32_t RESERVED14[99]; /*!< Reserved Address offset: 0x02C0-0x0448 */ __IO uint32_t RDCR; /*!< RCC reset duration control register Address offset: 0x044C */ uint32_t RESERVED15[204]; /*!< Reserved Address offset: 0x0450-0x077C */ __IO uint32_t SECCFGR0; /*!< RCC oscillator secure configuration register 0 Address offset: 0x0780 */ __IO uint32_t PRIVCFGR0; /*!< RCC oscillator privilege configuration register 0 Address offset: 0x0784 */ __IO uint32_t LOCKCFGR0; /*!< RCC oscillator lock configuration register 0 Address offset: 0x0788 */ __IO uint32_t PUBCFGR0; /*!< RCC oscillator public configuration register 0 Address offset: 0x078C */ __IO uint32_t SECCFGR1; /*!< RCC PLL secure configuration register 1 Address offset: 0x0790 */ __IO uint32_t PRIVCFGR1; /*!< RCC PLL privilege configuration register 1 Address offset: 0x0794 */ __IO uint32_t LOCKCFGR1; /*!< RCC PLL lock configuration register 1 Address offset: 0x0798 */ __IO uint32_t PUBCFGR1; /*!< RCC PLL public configuration register 1 Address offset: 0x079C */ __IO uint32_t SECCFGR2; /*!< RCC divider secure configuration register 2 Address offset: 0x07A0 */ __IO uint32_t PRIVCFGR2; /*!< RCC divider privilege configuration register 2 Address offset: 0x07A4 */ __IO uint32_t LOCKCFGR2; /*!< RCC divider lock configuration register 2 Address offset: 0x07A8 */ __IO uint32_t PUBCFGR2; /*!< RCC divider public configuration register 2 Address offset: 0x07AC */ __IO uint32_t SECCFGR3; /*!< RCC system secure configuration register 3 Address offset: 0x07B0 */ __IO uint32_t PRIVCFGR3; /*!< RCC system privilege configuration register 3 Address offset: 0x07B4 */ __IO uint32_t LOCKCFGR3; /*!< RCC system lock configuration register 3 Address offset: 0x07B8 */ __IO uint32_t PUBCFGR3; /*!< RCC system public configuration register 3 Address offset: 0x07BC */ __IO uint32_t SECCFGR4; /*!< RCC bus secure configuration register 4 Address offset: 0x07C0 */ __IO uint32_t PRIVCFGR4; /*!< RCC bus privilege configuration register 4 Address offset: 0x07C4 */ __IO uint32_t LOCKCFGR4; /*!< RCC bus lock configuration register 4 Address offset: 0x07C8 */ __IO uint32_t PUBCFGR4; /*!< RCC bus public configuration register 4 Address offset: 0x07CC */ __IO uint32_t PUBCFGR5; /*!< RCC bus public configuration register 4 Address offset: 0x07D0 */ uint32_t RESERVED16[11]; /*!< Reserved Address offset: 0x07D4-0x07FC */ __IO uint32_t CSR; /*!< RCC control Set register Address offset: 0x0800 */ uint32_t RESERVED17; /*!< Reserved Address offset: 0x0804 */ __IO uint32_t STOPCSR; /*!< RCC STOPCSR configuration register Address offset: 0x0808 */ uint32_t RESERVED18[127]; /*!< Reserved Address offset: 0x080C-0x0A00 */ __IO uint32_t MISCRSTSR; /*!< RCC miscellaneous reset register Address offset: 0x0A08 */ __IO uint32_t MEMRSTSR; /*!< RCC memory reset register Address offset: 0x0A0C */ __IO uint32_t AHB1RSTSR; /*!< RCC AHB1 reset register Address offset: 0x0A10 */ __IO uint32_t AHB2RSTSR; /*!< RCC AHB2 reset register Address offset: 0x0A14 */ __IO uint32_t AHB3RSTSR; /*!< RCC AHB3 reset register Address offset: 0x0A18 */ __IO uint32_t AHB4RSTSR; /*!< RCC AHB4 reset register Address offset: 0x0A1C */ __IO uint32_t AHB5RSTSR; /*!< RCC AHB5 reset register Address offset: 0x0A20 */ __IO uint32_t APB1RSTSR1; /*!< RCC APB1 reset register 1 Address offset: 0x0A24 */ __IO uint32_t APB1RSTSR2; /*!< RCC APB1 reset register 2 Address offset: 0x0A28 */ __IO uint32_t APB2RSTSR; /*!< RCC APB2 reset register Address offset: 0x0A2C */ uint32_t RESERVED19; /*!< Reserved Address offset: 0x0A30 */ __IO uint32_t APB4RSTSR1; /*!< RCC APB4 reset register 1 Address offset: 0x0A34 */ __IO uint32_t APB4RSTSR2; /*!< RCC APB4 reset register 2 Address offset: 0x0A38 */ __IO uint32_t APB5RSTSR; /*!< RCC APB5 reset register Address offset: 0x0A3C */ __IO uint32_t DIVENSR; /*!< RCC divider enable register Address offset: 0x0A40 */ __IO uint32_t BUSENSR; /*!< RCC bus enable register Address offset: 0x0A44 */ __IO uint32_t MISCENSR; /*!< RCC miscellaneous enable register Address offset: 0x0A48 */ __IO uint32_t MEMENSR; /*!< RCC memory enable register Address offset: 0x0A4C */ __IO uint32_t AHB1ENSR; /*!< RCC AHB1 enable register Address offset: 0x0A50 */ __IO uint32_t AHB2ENSR; /*!< RCC AHB2 enable register Address offset: 0x0A54 */ __IO uint32_t AHB3ENSR; /*!< RCC AHB3 enable register Address offset: 0x0A58 */ __IO uint32_t AHB4ENSR; /*!< RCC AHB4 enable register Address offset: 0x0A5C */ __IO uint32_t AHB5ENSR; /*!< RCC AHB5 enable register Address offset: 0x0A60 */ __IO uint32_t APB1ENSR1; /*!< RCC APB1 enable register 1 Address offset: 0x0A64 */ __IO uint32_t APB1ENSR2; /*!< RCC APB1 enable register 2 Address offset: 0x0A68 */ __IO uint32_t APB2ENSR; /*!< RCC APB2 enable register Address offset: 0x0A6C */ __IO uint32_t APB3ENSR; /*!< RCC APB3 enable register Address offset: 0x0A70 */ __IO uint32_t APB4ENSR1; /*!< RCC APB4 enable register 1 Address offset: 0x0A74 */ __IO uint32_t APB4ENSR2; /*!< RCC APB4 enable register 2 Address offset: 0x0A78 */ __IO uint32_t APB5ENSR; /*!< RCC APB5 enable register Address offset: 0x0A7C */ uint32_t RESERVED20; /*!< Reserved Address offset: 0x0A80 */ __IO uint32_t BUSLPENSR; /*!< RCC bus sleep enable register Address offset: 0x0A84 */ __IO uint32_t MISCLPENSR; /*!< RCC miscellaneous sleep enable register Address offset: 0x0A88 */ __IO uint32_t MEMLPENSR; /*!< RCC memory sleep enable register Address offset: 0x0A8C */ __IO uint32_t AHB1LPENSR; /*!< RCC AHB1 sleep enable register Address offset: 0x0A90 */ __IO uint32_t AHB2LPENSR; /*!< RCC AHB2 sleep enable register Address offset: 0x0A94 */ __IO uint32_t AHB3LPENSR; /*!< RCC AHB3 sleep enable register Address offset: 0x0A98 */ __IO uint32_t AHB4LPENSR; /*!< RCC AHB4 sleep enable register Address offset: 0x0A9C */ __IO uint32_t AHB5LPENSR; /*!< RCC AHB5 sleep enable register Address offset: 0x0AA0 */ __IO uint32_t APB1LPENSR1; /*!< RCC APB1 sleep enable register 1 Address offset: 0x0AA4 */ __IO uint32_t APB1LPENSR2; /*!< RCC APB1 sleep enable register 2 Address offset: 0x0AA8 */ __IO uint32_t APB2LPENSR; /*!< RCC APB2 sleep enable register Address offset: 0x0AAC */ __IO uint32_t APB3LPENSR; /*!< RCC APB3 sleep enable register Address offset: 0x0AB0 */ __IO uint32_t APB4LPENSR1; /*!< RCC APB4 sleep enable register 1 Address offset: 0x0AB4 */ __IO uint32_t APB4LPENSR2; /*!< RCC APB4 sleep enable register 2 Address offset: 0x0AB8 */ __IO uint32_t APB5LPENSR; /*!< RCC APB5 sleep enable register Address offset: 0x0ABC */ uint32_t RESERVED21[305]; /*!< Reserved Address offset: 0x0AC0-0x0F80 */ __IO uint32_t PRIVCFGSR0; /*!< RCC oscillator privilege configuration set register 0 Address offset: 0x0F84 */ uint32_t RESERVED22; /*!< Reserved Address offset: 0x0F88 */ __IO uint32_t PUBCFGSR0; /*!< RCC oscillator public configuration set register 0 Address offset: 0x0F8C */ uint32_t RESERVED23; /*!< Reserved Address offset: 0x0F90 */ __IO uint32_t PRIVCFGSR1; /*!< RCC PLL privilege configuration set register 1 Address offset: 0x0F94 */ uint32_t RESERVED24; /*!< Reserved Address offset: 0x0F98 */ __IO uint32_t PUBCFGSR1; /*!< RCC PLL public configuration set register 1 Address offset: 0x0F9C */ uint32_t RESERVED25; /*!< Reserved Address offset: 0x0FA0 */ __IO uint32_t PRIVCFGSR2; /*!< RCC divider privilege configuration set register 2 Address offset: 0x0FA4 */ uint32_t RESERVED26; /*!< Reserved Address offset: 0x0FA8 */ __IO uint32_t PUBCFGSR2; /*!< RCC divider public configuration set register 2 Address offset: 0x0FAC */ uint32_t RESERVED27; /*!< Reserved Address offset: 0x0FB0 */ __IO uint32_t PRIVCFGSR3; /*!< RCC system privilege configuration set register 3 Address offset: 0x0FB4 */ uint32_t RESERVED28; /*!< Reserved Address offset: 0x0FB8 */ __IO uint32_t PUBCFGSR3; /*!< RCC system public configuration set register 3 Address offset: 0x0FBC */ uint32_t RESERVED29; /*!< Reserved Address offset: 0x0FC0 */ __IO uint32_t PRIVCFGSR4; /*!< RCC privilege configuration set register 4 Address offset: 0x0FC4 */ uint32_t RESERVED30; /*!< Reserved Address offset: 0x0FC8 */ __IO uint32_t PUBCFGSR4; /*!< RCC public configuration set register 4 Address offset: 0x0FCC */ __IO uint32_t PUBCFGSR5; /*!< RCC public configuration set register 5 Address offset: 0x0FD0 */ uint32_t RESERVED31[11]; /*!< Reserved Address offset: 0x0FD4-0x0FFC */ __IO uint32_t CCR; /*!< RCC control clear register Address offset: 0x1000 */ uint32_t RESERVED32; /*!< Reserved Address offset: 0x1004 */ __IO uint32_t STOPCCR; /*!< RCC Stop mode configuration clear register Address offset: 0x1008 */ uint32_t RESERVED33[127]; /*!< Reserved Address offset: 0x100C-0x1200 */ __IO uint32_t MISCRSTCR; /*!< RCC miscellaneous reset clear register Address offset: 0x1208 */ __IO uint32_t MEMRSTCR; /*!< RCC memory reset clear register Address offset: 0x120C */ __IO uint32_t AHB1RSTCR; /*!< RCC AHB1 reset clear register Address offset: 0x1210 */ __IO uint32_t AHB2RSTCR; /*!< RCC AHB2 reset clear register Address offset: 0x1214 */ __IO uint32_t AHB3RSTCR; /*!< RCC AHB3 reset r clear register Address offset: 0x1218 */ __IO uint32_t AHB4RSTCR; /*!< RCC AHB4 reset clear register Address offset: 0x121C */ __IO uint32_t AHB5RSTCR; /*!< RCC AHB5 reset clear register Address offset: 0x1220 */ __IO uint32_t APB1RSTCR1; /*!< RCC APB1 reset clear register 1 Address offset: 0x1224 */ __IO uint32_t APB1RSTCR2; /*!< RCC APB1 reset clear register 2 Address offset: 0x1228 */ __IO uint32_t APB2RSTCR; /*!< RCC APB2 reset clear register Address offset: 0x122C */ uint32_t RESERVED34; /*!< Reserved Address offset: 0x1230 */ __IO uint32_t APB4RSTCR1; /*!< RCC APB4 reset clear register 1 Address offset: 0x1234 */ __IO uint32_t APB4RSTCR2; /*!< RCC APB4 reset clear register 2 Address offset: 0x1238 */ __IO uint32_t APB5RSTCR; /*!< RCC APB5 reset clear register Address offset: 0x123C */ __IO uint32_t DIVENCR; /*!< RCC divider enable clear register Address offset: 0x1240 */ __IO uint32_t BUSENCR; /*!< RCC bus enable clear register Address offset: 0x1244 */ __IO uint32_t MISCENCR; /*!< RCC miscellaneous enable clear register Address offset: 0x1248 */ __IO uint32_t MEMENCR; /*!< RCC memory enable clear register Address offset: 0x124C */ __IO uint32_t AHB1ENCR; /*!< RCC AHB1 enable clear register Address offset: 0x1250 */ __IO uint32_t AHB2ENCR; /*!< RCC AHB2 enable clear register Address offset: 0x1254 */ __IO uint32_t AHB3ENCR; /*!< RCC AHB3 enable clear register Address offset: 0x1258 */ __IO uint32_t AHB4ENCR; /*!< RCC AHB4 enable clear register Address offset: 0x125C */ __IO uint32_t AHB5ENCR; /*!< RCC AHB5 enable clear register Address offset: 0x1260 */ __IO uint32_t APB1ENCR1; /*!< RCC APB1 enable clear register 1 Address offset: 0x1264 */ __IO uint32_t APB1ENCR2; /*!< RCC APB1 enable clear register 2 Address offset: 0x1268 */ __IO uint32_t APB2ENCR; /*!< RCC APB2 enable clear register Address offset: 0x126C */ __IO uint32_t APB3ENCR; /*!< RCC APB3 enable clear register Address offset: 0x1270 */ __IO uint32_t APB4ENCR1; /*!< RCC APB4 enable clear register 1 Address offset: 0x1274 */ __IO uint32_t APB4ENCR2; /*!< RCC APB4 enable clear register 2 Address offset: 0x1278 */ __IO uint32_t APB5ENCR; /*!< RCC APB5 enable clear register Address offset: 0x127C */ uint32_t RESERVED35; /*!< Reserved Address offset: 0x1280 */ __IO uint32_t BUSLPENCR; /*!< RCC bus sleep enable clear register Address offset: 0x1284 */ __IO uint32_t MISCLPENCR; /*!< RCC miscellaneous sleep enable clear register Address offset: 0x1288 */ __IO uint32_t MEMLPENCR; /*!< RCC memory sleep enable clear register Address offset: 0x128C */ __IO uint32_t AHB1LPENCR; /*!< RCC AHB1 sleep enable clear register Address offset: 0x1290 */ __IO uint32_t AHB2LPENCR; /*!< RCC AHB2 sleep enable clear register Address offset: 0x1294 */ __IO uint32_t AHB3LPENCR; /*!< RCC AHB3 sleep enable clear register Address offset: 0x1298 */ __IO uint32_t AHB4LPENCR; /*!< RCC AHB4 sleep enable clear register Address offset: 0x129C */ __IO uint32_t AHB5LPENCR; /*!< RCC AHB5 sleep enable clear register Address offset: 0x12A0 */ __IO uint32_t APB1LPENCR1; /*!< RCC APB1 sleep enable clear register 1 Address offset: 0x12A4 */ __IO uint32_t APB1LPENCR2; /*!< RCC APB1 sleep enable clear register 2 Address offset: 0x12A8 */ __IO uint32_t APB2LPENCR; /*!< RCC APB2 sleep enable clear register Address offset: 0x12AC */ __IO uint32_t APB3LPENCR; /*!< RCC APB3 sleep enable clear register Address offset: 0x12B0 */ __IO uint32_t APB4LPENCR1; /*!< RCC APB4 sleep enable clear register 1 Address offset: 0x12B4 */ __IO uint32_t APB4LPENCR2; /*!< RCC APB4 sleep enable clear register 2 Address offset: 0x12B8 */ __IO uint32_t APB5LPENCR; /*!< RCC APB5 sleep enable clear register Address offset: 0x12BC */ uint32_t RESERVED36[305]; /*!< Reserved Address offset: 0x12C0-0x1780 */ __IO uint32_t PRIVCFGCR0; /*!< RCC oscillator privilege configuration clear register 0 Address offset: 0x1784 */ uint32_t RESERVED37; /*!< Reserved Address offset: 0x1788 */ __IO uint32_t PUBCFGCR0; /*!< RCC oscillator public configuration clear register 0 Address offset: 0x178C */ uint32_t RESERVED38; /*!< Reserved Address offset: 0x1790 */ __IO uint32_t PRIVCFGCR1; /*!< RCC PLL privilege configuration clear register 1 Address offset: 0x1794 */ uint32_t RESERVED39; /*!< Reserved Address offset: 0x1798 */ __IO uint32_t PUBCFGCR1; /*!< RCC PLL public configuration clear register 1 Address offset: 0x179C */ uint32_t RESERVED40; /*!< Reserved Address offset: 0x17A0 */ __IO uint32_t PRIVCFGCR2; /*!< RCC divider privilege configuration clear register 2 Address offset: 0x17A4 */ uint32_t RESERVED41; /*!< Reserved Address offset: 0x17A8 */ __IO uint32_t PUBCFGCR2; /*!< RCC divider public configuration clear register 2 Address offset: 0x17AC */ uint32_t RESERVED42; /*!< Reserved Address offset: 0x17B0 */ __IO uint32_t PRIVCFGCR3; /*!< RCC system privilege configuration clear register 3 Address offset: 0x17B4 */ uint32_t RESERVED43; /*!< Reserved Address offset: 0x17B8 */ __IO uint32_t PUBCFGCR3; /*!< RCC system public configuration clear register 3 Address offset: 0x17BC */ uint32_t RESERVED44; /*!< Reserved Address offset: 0x17C0 */ __IO uint32_t PRIVCFGCR4; /*!< RCC privilege configuration clear register 4 Address offset: 0x17C4 */ uint32_t RESERVED45; /*!< Reserved Address offset: 0x17C8 */ __IO uint32_t PUBCFGCR4; /*!< RCC public configuration clear register 4 Address offset: 0x17CC */ __IO uint32_t PUBCFGCR5; /*!< RCC public configuration clear register 5 Address offset: 0x17D0 */ } RCC_TypeDef; /* * @brief RIFSC Resource Isolation Framework Security Controller (full version) (RIFSC User Spec Rev 1.1) */ typedef struct { __IO uint32_t RISC_CR; /*!< RIFSC RISC slave configuration register x Address offset: 0x000 */ uint32_t RESERVED0[3]; /*!< Reserved Address offset: 0x004-0x00C */ __IO uint32_t RISC_SECCFGRx[6]; /*!< RIFSC RISC slave security configuration register x Address offset: 0x010-0x24 */ uint32_t RESERVED1[2]; /*!< Reserved Address offset: 0x028-0x02C */ __IO uint32_t RISC_PRIVCFGRx[6]; /*!< RIFSC RISFC slave privileged register x Address offset: 0x030-0x44 */ uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x048-0x04C */ __IO uint32_t RISC_RCFGLOCKRx[6]; /*!< RIFSC RISC slave resource configuration lock register x Address offset: 0x050 - 0x64 */ uint32_t RESERVED3[742]; /*!< Reserved Address offset: 0x068-0xBFC */ __IO uint32_t RIMC_CR; /*!< RIFSC RIMC master configuration register Address offset: 0xC00 */ uint32_t RESERVED4[3]; /*!< Reserved Address offset: 0xC04-0xC0C */ __IO uint32_t RIMC_ATTRx[13]; /*!< RIFSC RIMC master attribute register x Address offset: 0xC10-0xC40 */ uint32_t RESERVED5[219]; /*!< Reserved Address offset: 0xC40-0xFAC */ __IO uint32_t PPSRx[6]; /*!< RIFSC peripheral protection status register x Address offset: 0xFB0-0xFC4 */ uint32_t RESERVED6[8]; /*!< Reserved Address offset: 0xFC8-0xFE4 */ } RIFSC_TypeDef; /** * @brief RISAF Resource Isolation Slave Unit for Address Space Protection (full version) */ typedef struct { __IO uint32_t CFGR; /*!< RISAF Region X configuration register */ __IO uint32_t STARTR; /*!< RISAF Region X start address register */ __IO uint32_t ENDR; /*!< RISAF Region X end address register */ __IO uint32_t CIDCFGR; /*!< RISAF Region X CID configuration register */ __IO uint32_t ACFGR; /*!< RISAF Region X subregion A configuration register */ __IO uint32_t ASTARTR; /*!< RISAF Region X subregion A start address register */ __IO uint32_t AENDR; /*!< RISAF Region X subregion A end address register */ __IO uint32_t ANESTR; /*!< RISAF Region X subregion A nested mode register */ __IO uint32_t BCFGR; /*!< RISAF Region X subregion B configuration register */ __IO uint32_t BSTARTR; /*!< RISAF Region X subregion B start address register */ __IO uint32_t BENDR; /*!< RISAF Region X subregion B end address register */ __IO uint32_t BNESTR; /*!< RISAF Region X subregion B nested mode register */ uint32_t RESERVED0[4]; /*!< Reserved */ } RISAF_Region_TypeDef; /** * @brief RISAF Resource Isolation Slave Unit for Address Space Protection (full version) Illegal Access Register (RIF User Spec Rev 1.0.14) */ typedef struct { __IO uint32_t IAESR; /*!< RISAF Illegal access error status register */ __IO uint32_t IADDR; /*!< RISAF Illegal address register, */ } RISAF_Illegal_TypeDef; /** * @brief RISAF Resource Isolation Slave Unit for Address Space Protection (full version) (RIF User Spec Rev 1.0.14) */ typedef struct { __IO uint32_t CR; /*!< RISAF Configuration register, Address offset: 0x000 */ __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x004 */ __IO uint32_t IASR; /*!< RISAF Illegal access status register, Address offset: 0x008 */ __IO uint32_t IACR; /*!< RISAF Illegal access clear register, Address offset: 0x00C */ uint32_t RESERVED1[4]; /*!< Reserved, 0x010-0x01C */ RISAF_Illegal_TypeDef IAR[1]; /*!< RISAF Illegal access error status and address register, 0x020-0x024 */ uint32_t RESERVED2[6]; /*!< Reserved, 0x028-0x03C */ RISAF_Region_TypeDef REG[15]; /*!< RISAF Region X configuration register, 0x040-0x3FC */ } RISAF_TypeDef; /** * @brief RNG */ typedef struct { __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ uint32_t RESERVED; __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ } RNG_TypeDef; /* * @brief RTC Specific device feature definitions */ #define RTC_BKP_NB 32U #define RTC_TAMP_NB 7U /** * @brief Real-Time Clock */ typedef struct { __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x3C */ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ uint32_t RESERVED3[4];/*!< Reserved, Address offset: 0x58 */ __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ } RTC_TypeDef; /** * @brief SAES Processor */ typedef struct { __IO uint32_t CR; /*!< SAES control register, Address offset: 0x000 */ __IO uint32_t SR; /*!< SAES status register, Address offset: 0x004 */ __IO uint32_t DINR; /*!< SAES data input register, Address offset: 0x008 */ __IO uint32_t DOUTR; /*!< SAES data output register, Address offset: 0x00C */ __IO uint32_t KEYR0; /*!< SAES key register 0, Address offset: 0x010 */ __IO uint32_t KEYR1; /*!< SAES key register 1, Address offset: 0x014 */ __IO uint32_t KEYR2; /*!< SAES key register 2, Address offset: 0x018 */ __IO uint32_t KEYR3; /*!< SAES key register 3, Address offset: 0x01C */ __IO uint32_t IVR0; /*!< SAES initialization vector register 0, Address offset: 0x020 */ __IO uint32_t IVR1; /*!< SAES initialization vector register 1, Address offset: 0x024 */ __IO uint32_t IVR2; /*!< SAES initialization vector register 2, Address offset: 0x028 */ __IO uint32_t IVR3; /*!< SAES initialization vector register 3, Address offset: 0x02C */ __IO uint32_t KEYR4; /*!< SAES key register 4, Address offset: 0x030 */ __IO uint32_t KEYR5; /*!< SAES key register 5, Address offset: 0x034 */ __IO uint32_t KEYR6; /*!< SAES key register 6, Address offset: 0x038 */ __IO uint32_t KEYR7; /*!< SAES key register 7, Address offset: 0x03C */ uint32_t RESERVED1[48]; /*!< Reserved, Address offset: 0x040 -- 0x0FC */ __IO uint32_t DPACFGR; /*!< SAES DPA configuration register, Address offset: 0x100 */ uint32_t RESERVED2[127]; /*!< Reserved, Address offset: 0x104 -- 0x2FC */ __IO uint32_t IER; /*!< SAES Interrupt Enable Register, Address offset: 0x300 */ __IO uint32_t ISR; /*!< SAES Interrupt Status Register, Address offset: 0x304 */ __IO uint32_t ICR; /*!< SAES Interrupt Clear Register, Address offset: 0x308 */ } SAES_TypeDef; /** * @brief Serial Audio Interface */ typedef struct { __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ } SAI_TypeDef; typedef struct { __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ } SAI_Block_TypeDef; /** * @brief Secure digital input/output Interface */ typedef struct { __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ __IO uint32_t FIFOTHR; /*!< SDMMC data FIFO threshold register, Address offset: 0x44 */ uint32_t RESERVED0[2]; /*!< Reserved, 0x48 - 0x4C */ __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */ uint32_t RESERVED1[2]; /*!< Reserved, 0x5C - 0x60 */ __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */ uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ } SDMMC_TypeDef; /** * @brief SPI */ typedef struct { __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ __IO uint32_t IER; /*!< SPI/I2S Interrupt Enable register, Address offset: 0x10 */ __IO uint32_t SR; /*!< SPI/I2S Status register, Address offset: 0x14 */ __IO uint32_t IFCR; /*!< SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18 */ uint32_t RESERVED0; /*!< Reserved, 0x1C */ __IO uint32_t TXDR; /*!< SPI/I2S Transmit data register, Address offset: 0x20 */ uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ __IO uint32_t RXDR; /*!< SPI/I2S Receive data register, Address offset: 0x30 */ uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ __IO uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */ } SPI_TypeDef; /** * @brief UCPD */ typedef struct { __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ __IO uint32_t RESERVED0; /*!< UCPD reserved register, Address offset: 0x08 */ __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ } UCPD_TypeDef; /** * @brief USB_OTG_Core_register */ typedef struct { __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register, Address offset: 000h */ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register, Address offset: 004h */ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register, Address offset: 008h */ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register, Address offset: 00Ch */ __IO uint32_t GRSTCTL; /*!< Core Reset Register, Address offset: 010h */ __IO uint32_t GINTSTS; /*!< Core Interrupt Register, Address offset: 014h */ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register, Address offset: 018h */ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register, Address offset: 01Ch */ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register, Address offset: 020h */ __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register, Address offset: 024h */ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register, Address offset: 028h */ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg, Address offset: 02Ch */ __IO uint32_t Reserved30[2]; /*!< Reserved, Address offset: 030h */ __IO uint32_t GCCFG; /*!< General Purpose IO Register, Address offset: 038h */ __IO uint32_t CID; /*!< User ID Register, Address offset: 03Ch */ __IO uint32_t GSNPSID; /*!< USB_OTG core ID, Address offset: 040h */ __IO uint32_t GHWCFG1; /*!< User HW config1, Address offset: 044h */ __IO uint32_t GHWCFG2; /*!< User HW config2, Address offset: 048h */ __IO uint32_t GHWCFG3; /*!< User HW config3, Address offset: 04Ch */ __IO uint32_t Reserved6; /*!< Reserved, Address offset: 050h */ __IO uint32_t GLPMCFG; /*!< LPM Register, Address offset: 054h */ __IO uint32_t GPWRDN; /*!< Power Down Register, Address offset: 058h */ __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register, Address offset: 05Ch */ __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register, Address offset: 60Ch */ __IO uint32_t Reserved43[39]; /*!< Reserved, Address offset: 058h */ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg, Address offset: 100h */ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 104h */ } USB_OTG_GlobalTypeDef; typedef struct { __IO uint32_t USBPHYC_CR; /*!< USB_OTG Control and Status Register, Address offset: 000h */ __IO uint32_t USBPHYC_TRIM1CR; /*!< USB_OTG Interrupt Register, Address offset: 004h */ __IO uint32_t USBPHYC_TRIM2CR; /*!< Core AHB Configuration Register, Address offset: 008h */ } USB_PHY_GlobalTypeDef; /** * @brief USB_OTG_device_Registers */ typedef struct { __IO uint32_t DCFG; /*!< dev Configuration Register, Address offset: 800h */ __IO uint32_t DCTL; /*!< dev Control Register, Address offset: 804h */ __IO uint32_t DSTS; /*!< dev Status Register (RO), Address offset: 808h */ __IO uint32_t Reserved0C; /*!< Reserved, Address offset: 80Ch */ __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask, Address offset: 810h */ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask, Address offset: 814h */ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg, Address offset: 818h */ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask, Address offset: 81Ch */ __IO uint32_t Reserved20; /*!< Reserved, Address offset: 820h */ __IO uint32_t Reserved9; /*!< Reserved, Address offset: 824h */ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register, Address offset: 828h */ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register, Address offset: 82Ch */ __IO uint32_t DTHRCTL; /*!< dev threshold, Address offset: 830h */ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk, Address offset: 834h */ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt, Address offset: 838h */ __IO uint32_t DEACHMSK; /*!< dedicated EP msk, Address offset: 83Ch */ __IO uint32_t Reserved40; /*!< dedicated EP mask, Address offset: 840h */ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask, Address offset: 844h */ __IO uint32_t Reserved44[15]; /*!< Reserved, Address offset: 844-87Ch */ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk, Address offset: 884h */ } USB_OTG_DeviceTypeDef; /** * @brief USB_OTG_IN_Endpoint-Specific_Register */ typedef struct { __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Register, Address offset: 900h + (ep_num * 20h) + 00h */ __IO uint32_t Reserved04; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 04h */ __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Register, Address offset: 900h + (ep_num * 20h) + 08h */ __IO uint32_t Reserved0C; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 0Ch */ __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size Register, Address offset: 900h + (ep_num * 20h) + 10h */ __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Register, Address offset: 900h + (ep_num * 20h) + 14h */ __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Register, Address offset: 900h + (ep_num * 20h) + 18h */ __IO uint32_t Reserved18; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 1Ch */ } USB_OTG_INEndpointTypeDef; /** * @brief USB_OTG_OUT_Endpoint-Specific_Registers */ typedef struct { __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Register, Address offset: B00h + (ep_num * 20h) + 00h */ __IO uint32_t Reserved04; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 04h */ __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Register, Address offset: B00h + (ep_num * 20h) + 08h */ __IO uint32_t Reserved0C; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 0Ch */ __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size Register, Address offset: B00h + (ep_num * 20h) + 10h */ __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address Register, Address offset: B00h + (ep_num * 20h) + 14h */ __IO uint32_t Reserved18[2]; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 18h */ } USB_OTG_OUTEndpointTypeDef; /** * @brief USB_OTG_Host_Mode_Register_Structures */ typedef struct { __IO uint32_t HCFG; /*!< Host Configuration Register, Address offset: 400h */ __IO uint32_t HFIR; /*!< Host Frame Interval Register, Address offset: 404h */ __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining, Address offset: 408h */ __IO uint32_t Reserved40C; /*!< Reserved, Address offset: 40Ch */ __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status, Address offset: 410h */ __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register, Address offset: 414h */ __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask, Address offset: 418h */ } USB_OTG_HostTypeDef; /** * @brief USB_OTG_Host_Channel_Specific_Registers */ typedef struct { __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register, Address offset: 500h */ __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register, Address offset: 504h */ __IO uint32_t HCINT; /*!< Host Channel Interrupt Register, Address offset: 508h */ __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register, Address offset: 50Ch */ __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register, Address offset: 510h */ __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register, Address offset: 514h */ uint32_t Reserved[2]; /*!< Reserved, Address offset: 518h */ } USB_OTG_HostChannelTypeDef; typedef struct { __IO uint32_t USBPHYC_CR; /*!< USB HS PHY Control Register, Address offset: 000h */ __IO uint32_t USBPHYC_TRIM1CR; /*!< USB HS PHY Trimming_1 Register, Address offset: 004h */ __IO uint32_t USBPHYC_TRIM2CR; /*!< USB HS PHY Trimming_2 Register, Address offset: 008h */ } USB_HS_PHYC_GlobalTypeDef; /** * @brief SPDIF-RX Interface */ typedef struct { __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ } SPDIFRX_TypeDef; /** * @brief System configuration controller */ typedef struct { __IO uint32_t BOOTCR; /*!< SYSCFG boot pin control register, Address offset: 0x00 */ __IO uint32_t CM55CR; /*!< SYSCFG Cortex-M55 control register, Address offset: 0x04 */ __IO uint32_t CM55TCMCR; /*!< SYSCFG Cortex-M55 TCM control register, Address offset: 0x08 */ __IO uint32_t CM55RWMCR; /*!< SYSCFG Cortex-M55 memory RW margin register, Address offset: 0x0C */ __IO uint32_t INITSVTORCR; /*!< SYSCFG Cortex-M55 SVTOR control register, Address offset: 0x10 */ __IO uint32_t INITNSVTORCR; /*!< Cortex-M55 NSVTOR control register, Address offset: 0x14 */ __IO uint32_t CM55RSTCR; /*!< SYSCFG Cortex-M55 reset type control register, Address offset: 0x18 */ __IO uint32_t CM55PAHBWPR; /*!< SYSCFG Cortex-M55 P-AHB write posting control register, Address offset: 0x1C */ __IO uint32_t VENCRAMCR; /*!< SYSCFG VENCRAM control register, Address offset: 0x20 */ __IO uint32_t POTTAMPRSTCR; /*!< SYSCFG potential tamper reset register, Address offset: 0x24 */ __IO uint32_t NPUNICQOSCR; /*!< SYSCFG NPUNIC QoS control register, Address offset: 0x28 */ uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x2C-0x30 */ __IO uint32_t ICNEWRCR; /*!< SYSCFG AHB-AXI bridge early write response, Address offset: 0x34 */ __IO uint32_t ICNCGCR; /*!< SYSCFG ICN clock gating control register, Address offset: 0x38 */ uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x3C-0x40 */ __IO uint32_t VDDIO2CCCR; /*!< SYSCFG VDDIO2 compensation cell control register, Address offset: 0x44 */ __IO uint32_t VDDIO2CCSR; /*!< SYSCFG VDDIO2 compensation cell status register, Address offset: 0x48 */ __IO uint32_t VDDIO3CCCR; /*!< SYSCFG VDDIO3 compensation cell control register, Address offset: 0x4C */ __IO uint32_t VDDIO3CCSR; /*!< SYSCFG VDDIO3 compensation cell status register, Address offset: 0x50 */ __IO uint32_t VDDIO4CCCR; /*!< SYSCFG VDDIO4 compensation cell control register, Address offset: 0x54 */ __IO uint32_t VDDIO4CCSR; /*!< SYSCFG VDDIO4 compensation cell status register, Address offset: 0x58 */ __IO uint32_t VDDIO5CCCR; /*!< SYSCFG VDDIO5 compensation cell control register, Address offset: 0x5C */ __IO uint32_t VDDIO5CCSR; /*!< SYSCFG VDDIO5 compensation cell status register, Address offset: 0x60 */ __IO uint32_t VDDCCCR; /*!< SYSCFG VDD compensation cell control register, Address offset: 0x64 */ __IO uint32_t VDDCCSR; /*!< SYSCFG VDD compensation cell status register, Address offset: 0x68 */ __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x6C */ __IO uint32_t SEC_AIDCR; /*!< SYSCFG DMA CID secure control register, Address offset: 0x70 */ __IO uint32_t FMC_RETIMECR; /*!< SYSCFG FMC retiming logic control register, Address offset: 0x74 */ __IO uint32_t NPU_ICNCR; /*!< SYSCFG NPU RAM interleaving control register, Address offset: 0x78 */ uint32_t RESERVED3[33]; /*!< Reserved, Address offset: 0x7C-0xFC */ __IO uint32_t BOOTSR; /*!< SYSCFG boot pin status register, Address offset: 0x100 */ __IO uint32_t AHBWP_ERROR_SR; /*!< SYSCFG AHB write posting address error register, Address offset: 0x104 */ uint32_t RESERVED4[446]; /*!< Reserved, Address offset: 0x108-0x3FC */ __IO uint32_t SECPRIV_AIDCR; /*!< SYSCFG DMA CID non-secure control register, Address offset: 0x800 */ uint32_t RESERVED5[507]; /*!< Reserved, Address offset: 0x804-0xFEC */ __IO uint32_t DEVICEID; /*!< SYSCFG Device ID, Address offset: 0xFF0 */ } SYSCFG_TypeDef; /** * @brief Tamper and backup registers */ typedef struct { __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x28 */ __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register, Address offset: 0x38 */ __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ __IO uint32_t COUNT1R; /*!< TAMP monotonic counter register, Address offset: 0x40 */ uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x43 -- 0x4C */ __IO uint32_t OR; /*!< TAMP option register, Address offset: 0x50 */ __IO uint32_t RPCFGR; /*!< TAMP resources protection configuration register, Address offset: 0x54 */ uint32_t RESERVED5[42]; /*!< Reserved, Address offset: 0x58 -- 0xFC */ __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ } TAMP_TypeDef; /** * @brief TIM */ typedef struct { __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ uint32_t RESERVED1[221]; /*!< Reserved, 0x6C-0x3D8 */ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ } TIM_TypeDef; /** * @brief Universal Synchronous Asynchronous Receiver Transmitter */ typedef struct { __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ } USART_TypeDef; /** * @brief VREFBUF */ typedef struct { __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ } VREFBUF_TypeDef; /** * @brief Window Watchdog */ typedef struct { __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ } WWDG_TypeDef; /** * @brief Extended-SPI Interface */ typedef struct { __IO uint32_t CR; /*!< XSPI Control Register, Address offset: 0x000 */ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x004 */ __IO uint32_t DCR1; /*!< XSPI Device Configuration Register 1, Address offset: 0x008 */ __IO uint32_t DCR2; /*!< XSPI Device Configuration Register 2, Address offset: 0x00C */ __IO uint32_t DCR3; /*!< XSPI Device Configuration Register 3, Address offset: 0x010 */ __IO uint32_t DCR4; /*!< XSPI Device Configuration Register 4, Address offset: 0x014 */ uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x018 - 0x01C */ __IO uint32_t SR; /*!< XSPI Status Register, Address offset: 0x020 */ __IO uint32_t FCR; /*!< XSPI Flag Clear Register, Address offset: 0x024 */ uint32_t RESERVED3[6]; /*!< Reserved, Address offset: 0x028 - 0x03C */ __IO uint32_t DLR; /*!< XSPI Data Length Register, Address offset: 0x040 */ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x044 */ __IO uint32_t AR; /*!< XSPI Address Register, Address offset: 0x048 */ uint32_t RESERVED5; /*!< Reserved, Address offset: 0x04C */ __IO uint32_t DR; /*!< XSPI Data Register, Address offset: 0x050 */ uint32_t RESERVED6[11]; /*!< Reserved, Address offset: 0x054 - 0x07C */ __IO uint32_t PSMKR; /*!< XSPI Polling Status Mask Register, Address offset: 0x080 */ uint32_t RESERVED7; /*!< Reserved, Address offset: 0x084 */ __IO uint32_t PSMAR; /*!< XSPI Polling Status Match Register, Address offset: 0x088 */ uint32_t RESERVED8; /*!< Reserved, Address offset: 0x08C */ __IO uint32_t PIR; /*!< XSPI Polling Interval Register, Address offset: 0x090 */ uint32_t RESERVED9[27]; /*!< Reserved, Address offset: 0x094 - 0x0FC */ __IO uint32_t CCR; /*!< XSPI Communication Configuration Register, Address offset: 0x100 */ uint32_t RESERVED10; /*!< Reserved, Address offset: 0x104 */ __IO uint32_t TCR; /*!< XSPI Timing Configuration Register, Address offset: 0x108 */ uint32_t RESERVED11; /*!< Reserved, Address offset: 0x10C */ __IO uint32_t IR; /*!< XSPI Instruction Register, Address offset: 0x110 */ uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x114 - 0x11C */ __IO uint32_t ABR; /*!< XSPI Alternate Bytes Register, Address offset: 0x120 */ uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x124 - 0x12C */ __IO uint32_t LPTR; /*!< XSPI Low-Power Timeout Register, Address offset: 0x130 */ uint32_t RESERVED14[3]; /*!< Reserved, Address offset: 0x134 - 0x13C */ __IO uint32_t WPCCR; /*!< XSPI Wrap Communication Configuration Register, Address offset: 0x140 */ uint32_t RESERVED15; /*!< Reserved, Address offset: 0x144 */ __IO uint32_t WPTCR; /*!< XSPI Wrap Timing Configuration Register, Address offset: 0x148 */ uint32_t RESERVED16; /*!< Reserved, Address offset: 0x14C */ __IO uint32_t WPIR; /*!< XSPI Wrap Instruction Register, Address offset: 0x150 */ uint32_t RESERVED17[3]; /*!< Reserved, Address offset: 0x154 - 0x15C */ __IO uint32_t WPABR; /*!< XSPI Wrap Alternate Bytes Register, Address offset: 0x160 */ uint32_t RESERVED18[7]; /*!< Reserved, Address offset: 0x164 - 0x17C */ __IO uint32_t WCCR; /*!< XSPI Write Communication Configuration Register, Address offset: 0x180 */ uint32_t RESERVED19; /*!< Reserved, Address offset: 0x184 */ __IO uint32_t WTCR; /*!< XSPI Write Timing Configuration Register, Address offset: 0x188 */ uint32_t RESERVED20; /*!< Reserved, Address offset: 0x18C */ __IO uint32_t WIR; /*!< XSPI Write Instruction Register, Address offset: 0x190 */ uint32_t RESERVED21[3]; /*!< Reserved, Address offset: 0x194 - 0x19C */ __IO uint32_t WABR; /*!< XSPI Write Alternate Bytes Register, Address offset: 0x1A0 */ uint32_t RESERVED22[23]; /*!< Reserved, Address offset: 0x1A4 - 0x1FC */ __IO uint32_t HLCR; /*!< XSPI HyperBus Latency Configuration Register, Address offset: 0x200 */ uint32_t RESERVED23[3]; /*!< Reserved, Address offset: 0x204 - 0x20C */ __IO uint32_t CALFCR; /*!< XSPI Full-Cycle Calibration Configuration Register, Address offset: 0x210 */ uint32_t RESERVED24; /*!< Reserved, Address offset: 0x214 */ __IO uint32_t CALMR; /*!< XSPI DLL Master Calibration Configuration Register, Address offset: 0x218 */ uint32_t RESERVED25; /*!< Reserved, Address offset: 0x21C */ __IO uint32_t CALSOR; /*!< XSPI Slave Output Calibration Configuration Register, Address offset: 0x220 */ uint32_t RESERVED26; /*!< Reserved, Address offset: 0x224 */ __IO uint32_t CALSIR; /*!< XSPI Slave Input Calibration Configuration Register, Address offset: 0x228 */ } XSPI_TypeDef; /** * @brief XSPI IO Manager */ typedef struct { __IO uint32_t CR; /*!< XSPI IO Manager Control Register, Address offset: 0x00 */ } XSPIM_TypeDef; /** @} */ /* End of group STM32N6xx_peripherals */ /* =========================================================================================================================== */ /* ================ Device Specific Peripheral Address Map ================ */ /* =========================================================================================================================== */ /** @addtogroup STM32N6xx_Peripheral_peripheralAddr * @{ */ /* Internal RAMs sizes */ #define SRAM1_AXI_SIZE 0x100000UL /*!< SRAM1_AXI = 1024 Kbytes */ #define SRAM2_AXI_SIZE 0x100000UL /*!< SRAM2_AXI = 1024 Kbytes */ #define FLEXRAM_SIZE 0x64000UL /*!< FLEXRAM <= 400 Kbytes */ #define SRAM3_AXI_SIZE 0x70000UL /*!< SRAM3_AXI = 448 Kbytes */ #define SRAM4_AXI_SIZE 0x70000UL /*!< SRAM4_AXI = 448 Kbytes */ #define SRAM5_AXI_SIZE 0x70000UL /*!< SRAM5_AXI = 448 Kbytes */ #define SRAM6_AXI_SIZE 0x70000UL /*!< SRAM6_AXI = 448 Kbytes */ #define SRAM1_AHB_SIZE 0x4000UL /*!< SRAM1_AHB = 16 Kbytes */ #define SRAM2_AHB_SIZE 0x4000UL /*!< SRAM2_AHB = 16 Kbytes */ #define VENC_RAM_SIZE 0x20000UL /*!< VENC RAM = 128 Kbytes */ #define CACHEAXI_RAM_SIZE 0x40000UL /*!< CACHEAXI RAM = 256 Kbytes */ #define BKPSRAM_SIZE 0x2000UL /*!< BKPSRAM = 8 Kbytes */ #define FMC_BASE 0x60000000UL /*!< Base address of : FMC NOR/RAM memories accessible over AXI */ #define FMC_BANK1 FMC_BASE #define FMC_BANK1_1 FMC_BANK1 #define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) #define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) #define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) #define FMC_BANK5 0xC0000000UL /*!< Base address of : FMC SDRAM memories accessible over AXI */ #define FMC_BANK5_1 FMC_BANK5 #define FMC_BANK5_2 (FMC_BANK5 + 0x04000000UL) #define FMC_BANK5_3 (FMC_BANK5 + 0x08000000UL) #define FMC_BANK5_4 (FMC_BANK5 + 0x0C000000UL) #define FMC_BANK6 0xD0000000UL /*!< Base address of : FMC SDRAM memories accessible over AXI */ #define FMC_BANK6_1 FMC_BANK6 #define FMC_BANK6_2 (FMC_BANK6 + 0x04000000UL) #define FMC_BANK6_3 (FMC_BANK6 + 0x08000000UL) #define FMC_BANK6_4 (FMC_BANK6 + 0x0C000000UL) #define XSPI1_BASE 0x90000000UL /*!< Base address of : XSPI1 memories accessible over AXI */ #define XSPI2_BASE 0x70000000UL /*!< Base address of : XSPI2 memories accessible over AXI */ #define XSPI3_BASE 0x80000000UL /*!< Base address of : XSPI3 memories accessible over AXI */ /**************************************************************************/ /* */ /* Peripheral and internal SRAMs base addresses - Non secure (aliased_NS) */ /* */ /**************************************************************************/ #define ITCM_BASE_NS 0x00000000UL /*!< Base address of ITCM from 64 KB up to 256 KB */ #define BOOTROM_BASE_NS 0x08000000UL /*!< Base address of 128 KB boot ROM accessible over AXI */ #define DTCM_BASE_NS 0x20000000UL /*!< Base address of DTCM from 128 KB up to 256 KB */ #define SRAM1_AXI_BASE_NS 0x24000000UL /*!< Base address of up to 1 MB system RAM 1 accessible over AXI */ #define SRAM2_AXI_BASE_NS 0x24100000UL /*!< Base address of 1 MB system RAM 2 accessible over AXI */ #define SRAM3_AXI_BASE_NS 0x24200000UL /*!< Base address of 448 KB system RAM 3 accessible over AXI */ #define SRAM4_AXI_BASE_NS 0x24270000UL /*!< Base address of 448 KB system RAM 4 accessible over AXI */ #define SRAM5_AXI_BASE_NS 0x242E0000UL /*!< Base address of 448 KB system RAM 5 accessible over AXI */ #define SRAM6_AXI_BASE_NS 0x24350000UL /*!< Base address of 448 KB system RAM 6 accessible over AXI */ #define SRAM_AXI_BASE_NS SRAM1_AXI_BASE_NS /*!< Base address of 3.792 MB system RAM accessible over AXI */ #define CACHEAXI_RAM_BASE_NS 0x243C0000UL /*!< Base address of 256 KB NPU Cache RAM accessible over AXI */ #define VENC_RAM_BASE_NS 0x24400000UL /*!< Base address of 128 KB of Video Encoder RAM accessible over AXI */ #define GFXMMU_VIRTUAL_BUFFER0_BASE_NS 0x25000000UL /*!< Base address of 4 MB GFXMMU virtual buffer 0 */ #define GFXMMU_VIRTUAL_BUFFER1_BASE_NS 0x25400000UL /*!< Base address of 4 MB GFXMMU virtual buffer 1 */ #define GFXMMU_VIRTUAL_BUFFER2_BASE_NS 0x25800000UL /*!< Base address of 4 MB GFXMMU virtual buffer 2 */ #define GFXMMU_VIRTUAL_BUFFER3_BASE_NS 0x25C00000UL /*!< Base address of 4 MB GFXMMU virtual buffer 3 */ #define STM500_CHANNELS_BASE_NS 0x27F00000UL /*!< Base address of 1 MB of STM500 Channels (System Trace) */ #define SRAM1_AHB_BASE_NS 0x28000000UL /*!< Base address of 16 KB system RAM 1 over AXI->AHB Bridge */ #define SRAM2_AHB_BASE_NS 0x28004000UL /*!< Base address of 16 KB system RAM 2 over AXI->AHB Bridge */ #define SRAM_AHB_BASE_NS SRAM1_AHB_BASE_NS /*!< Base address of 32 KB system RAM over AXI->AHB Bridge */ #define BKPSRAM_BASE_NS 0x2C000000UL /*!< Base address of 8 KB Backup SRAM over AXI->AHB Bridge */ #define PERIPH_BASE_NS 0x40000000UL /*!< Base address of : AHB/APB Peripherals */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE_NS PERIPH_BASE_NS #define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) #define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02000000UL) #define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) #define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x04000000UL) #define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x04020000UL) #define APB4PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) #define AHB4PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06020000UL) #define APB5PERIPH_BASE_NS (PERIPH_BASE_NS + 0x08000000UL) #define AHB5PERIPH_BASE_NS (PERIPH_BASE_NS + 0x08020000UL) /*!< APB1 peripherals */ #define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL) #define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) #define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL) #define TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL) #define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL) #define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL) #define TIM12_BASE_NS (APB1PERIPH_BASE_NS + 0x1800UL) #define TIM13_BASE_NS (APB1PERIPH_BASE_NS + 0x1C00UL) #define TIM14_BASE_NS (APB1PERIPH_BASE_NS + 0x2000UL) #define LPTIM1_BASE_NS (APB1PERIPH_BASE_NS + 0x2400UL) #define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) #define TIM10_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) #define TIM11_BASE_NS (APB1PERIPH_BASE_NS + 0x3400UL) #define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL) #define SPI3_BASE_NS (APB1PERIPH_BASE_NS + 0x3C00UL) #define SPDIFRX_BASE_NS (APB1PERIPH_BASE_NS + 0x4000UL) #define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL) #define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL) #define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL) #define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL) #define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) #define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL) #define I2C3_BASE_NS (APB1PERIPH_BASE_NS + 0x5C00UL) #define I3C1_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL) #define I3C2_BASE_NS (APB1PERIPH_BASE_NS + 0x6400UL) #define UART7_BASE_NS (APB1PERIPH_BASE_NS + 0x7800UL) #define UART8_BASE_NS (APB1PERIPH_BASE_NS + 0x7C00UL) #define MDIOS_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) #define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA000UL) #define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0xA100UL) #define FDCAN2_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL) #define FDCAN_CCU_BASE_NS (APB1PERIPH_BASE_NS + 0xA800UL) #define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xC000UL) #define FDCAN3_BASE_NS (APB1PERIPH_BASE_NS + 0xE800UL) #define UCPD1_BASE_NS (APB1PERIPH_BASE_NS + 0xFC00UL) /*!< AHB1 peripherals */ #define GPDMA1_BASE_NS (AHB1PERIPH_BASE_NS + 0x1000UL) #define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) #define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) #define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) #define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) #define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) #define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) #define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) #define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) #define GPDMA1_Channel8_BASE_NS (GPDMA1_BASE_NS + 0x0450UL) #define GPDMA1_Channel9_BASE_NS (GPDMA1_BASE_NS + 0x04D0UL) #define GPDMA1_Channel10_BASE_NS (GPDMA1_BASE_NS + 0x0550UL) #define GPDMA1_Channel11_BASE_NS (GPDMA1_BASE_NS + 0x05D0UL) #define GPDMA1_Channel12_BASE_NS (GPDMA1_BASE_NS + 0x0650UL) #define GPDMA1_Channel13_BASE_NS (GPDMA1_BASE_NS + 0x06D0UL) #define GPDMA1_Channel14_BASE_NS (GPDMA1_BASE_NS + 0x0750UL) #define GPDMA1_Channel15_BASE_NS (GPDMA1_BASE_NS + 0x07D0UL) #define ADC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x2000UL) #define ADC2_BASE_NS (AHB1PERIPH_BASE_NS + 0x2100UL) #define ADC12_COMMON_BASE_NS (AHB1PERIPH_BASE_NS + 0x2300UL) /*!< APB2 peripherals */ #define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x0000UL) #define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x0400UL) #define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x1000UL) #define USART6_BASE_NS (APB2PERIPH_BASE_NS + 0x1400UL) #define UART9_BASE_NS (APB2PERIPH_BASE_NS + 0x1800UL) #define USART10_BASE_NS (APB2PERIPH_BASE_NS + 0x1C00UL) #define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) #define SPI4_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL) #define TIM18_BASE_NS (APB2PERIPH_BASE_NS + 0x3C00UL) #define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL) #define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x4400UL) #define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x4800UL) #define TIM9_BASE_NS (APB2PERIPH_BASE_NS + 0x4C00UL) #define SPI5_BASE_NS (APB2PERIPH_BASE_NS + 0x5000UL) #define SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x5800UL) #define SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x0004UL) #define SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x0024UL) #define SAI2_BASE_NS (APB2PERIPH_BASE_NS + 0x5C00UL) #define SAI2_Block_A_BASE_NS (SAI2_BASE_NS + 0x0004UL) #define SAI2_Block_B_BASE_NS (SAI2_BASE_NS + 0x0024UL) /*!< AHB2 peripherals */ #define RAMCFG_BASE_NS (AHB2PERIPH_BASE_NS + 0x3000UL) #define RAMCFG_SRAM1_AXI_BASE_NS (RAMCFG_BASE_NS) #define RAMCFG_SRAM2_AXI_BASE_NS (RAMCFG_BASE_NS + 0x0080UL) #define RAMCFG_SRAM3_AXI_BASE_NS (RAMCFG_BASE_NS + 0x0100UL) #define RAMCFG_SRAM4_AXI_BASE_NS (RAMCFG_BASE_NS + 0x0180UL) #define RAMCFG_SRAM5_AXI_BASE_NS (RAMCFG_BASE_NS + 0x0200UL) #define RAMCFG_SRAM6_AXI_BASE_NS (RAMCFG_BASE_NS + 0x0280UL) #define RAMCFG_SRAM1_AHB_BASE_NS (RAMCFG_BASE_NS + 0x0300UL) #define RAMCFG_SRAM2_AHB_BASE_NS (RAMCFG_BASE_NS + 0x0380UL) #define RAMCFG_VENC_RAM_BASE_NS (RAMCFG_BASE_NS + 0x0400UL) #define RAMCFG_BKPSRAM_BASE_NS (RAMCFG_BASE_NS + 0x0480UL) #define RAMCFG_FLEXRAM_BASE_NS (RAMCFG_BASE_NS + 0x0500UL) #define MDF1_BASE_NS (AHB2PERIPH_BASE_NS + 0x5000UL) #define MDF1_Filter0_BASE_NS (MDF1_BASE_NS + 0x0080UL) #define MDF1_Filter1_BASE_NS (MDF1_BASE_NS + 0x0100UL) #define MDF1_Filter2_BASE_NS (MDF1_BASE_NS + 0x0180UL) #define MDF1_Filter3_BASE_NS (MDF1_BASE_NS + 0x0200UL) #define MDF1_Filter4_BASE_NS (MDF1_BASE_NS + 0x0280UL) #define MDF1_Filter5_BASE_NS (MDF1_BASE_NS + 0x0300UL) #define ADF1_BASE_NS (AHB2PERIPH_BASE_NS + 0x6000UL) #define ADF1_Filter0_BASE_NS (ADF1_BASE_NS + 0x0080UL) /*!< APB3 peripherals */ #define DAP_ROM_BASE_NS (APB3PERIPH_BASE_NS + 0x0000UL) #define DBGMCU_BASE_NS (APB3PERIPH_BASE_NS + 0x1000UL) #define DFT_APB_BASE_NS (APB3PERIPH_BASE_NS + 0x2000UL) /*!< AHB3 peripherals */ #define RNG_BASE_NS (AHB3PERIPH_BASE_NS + 0x0000UL) #define HASH_BASE_NS (AHB3PERIPH_BASE_NS + 0x0400UL) #define HASH_DIGEST_BASE_NS (AHB3PERIPH_BASE_NS + 0x0710UL) #define CRYP_BASE_NS (AHB3PERIPH_BASE_NS + 0x0800UL) #define SAES_BASE_NS (AHB3PERIPH_BASE_NS + 0x1000UL) #define PKA_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL) #define RIFSC_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL) #define RISAF1_BASE_NS (AHB3PERIPH_BASE_NS + 0x6000UL) #define RISAF2_BASE_NS (AHB3PERIPH_BASE_NS + 0x7000UL) #define RISAF3_BASE_NS (AHB3PERIPH_BASE_NS + 0x8000UL) #define RISAF4_BASE_NS (AHB3PERIPH_BASE_NS + 0x9000UL) #define RISAF5_BASE_NS (AHB3PERIPH_BASE_NS + 0xA000UL) #define RISAF6_BASE_NS (AHB3PERIPH_BASE_NS + 0xB000UL) #define RISAF7_BASE_NS (AHB3PERIPH_BASE_NS + 0xC000UL) #define RISAF8_BASE_NS (AHB3PERIPH_BASE_NS + 0xD000UL) #define RISAF9_BASE_NS (AHB3PERIPH_BASE_NS + 0xE000UL) #define RISAF11_BASE_NS (AHB3PERIPH_BASE_NS + 0x010000UL) #define RISAF12_BASE_NS (AHB3PERIPH_BASE_NS + 0x011000UL) #define RISAF13_BASE_NS (AHB3PERIPH_BASE_NS + 0x012000UL) #define RISAF14_BASE_NS (AHB3PERIPH_BASE_NS + 0x013000UL) #define RISAF15_BASE_NS (AHB3PERIPH_BASE_NS + 0x014000UL) #define RISAF21_BASE_NS (AHB3PERIPH_BASE_NS + 0x015000UL) #define RISAF22_BASE_NS (AHB3PERIPH_BASE_NS + 0x016000UL) #define RISAF23_BASE_NS (AHB3PERIPH_BASE_NS + 0x017000UL) /*!< APB4 peripherals */ #define HDP_BASE_NS (APB4PERIPH_BASE_NS + 0x0800UL) #define LPUART1_BASE_NS (APB4PERIPH_BASE_NS + 0x0C00UL) #define SPI6_BASE_NS (APB4PERIPH_BASE_NS + 0x1400UL) #define I2C4_BASE_NS (APB4PERIPH_BASE_NS + 0x1C00UL) #define LPTIM2_BASE_NS (APB4PERIPH_BASE_NS + 0x2400UL) #define LPTIM3_BASE_NS (APB4PERIPH_BASE_NS + 0x2800UL) #define LPTIM4_BASE_NS (APB4PERIPH_BASE_NS + 0x2C00UL) #define LPTIM5_BASE_NS (APB4PERIPH_BASE_NS + 0x3000UL) #define VREFBUF_BASE_NS (APB4PERIPH_BASE_NS + 0x3C00UL) #define RTC_BASE_NS (APB4PERIPH_BASE_NS + 0x4000UL) #define TAMP_BASE_NS (APB4PERIPH_BASE_NS + 0x4400UL) #define IWDG_BASE_NS (APB4PERIPH_BASE_NS + 0x4800UL) #define SERC_BASE_NS (APB4PERIPH_BASE_NS + 0x7C00UL) #define SYSCFG_BASE_NS (APB4PERIPH_BASE_NS + 0x8000UL) #define BSEC_BASE_NS (APB4PERIPH_BASE_NS + 0x9000UL) #define DTS_BASE_NS (APB4PERIPH_BASE_NS + 0xA000UL) #define DTS_Sensor0_BASE_NS (DTS_BASE_NS + 0x0C0UL) #define DTS_Sensor1_BASE_NS (DTS_BASE_NS + 0x100UL) /*!< AHB4 peripherals */ #define GPIOA_BASE_NS (AHB4PERIPH_BASE_NS + 0x0000UL) #define GPIOB_BASE_NS (AHB4PERIPH_BASE_NS + 0x0400UL) #define GPIOC_BASE_NS (AHB4PERIPH_BASE_NS + 0x0800UL) #define GPIOD_BASE_NS (AHB4PERIPH_BASE_NS + 0x0C00UL) #define GPIOE_BASE_NS (AHB4PERIPH_BASE_NS + 0x1000UL) #define GPIOF_BASE_NS (AHB4PERIPH_BASE_NS + 0x1400UL) #define GPIOG_BASE_NS (AHB4PERIPH_BASE_NS + 0x1800UL) #define GPIOH_BASE_NS (AHB4PERIPH_BASE_NS + 0x1C00UL) #define GPION_BASE_NS (AHB4PERIPH_BASE_NS + 0x3400UL) #define GPIOO_BASE_NS (AHB4PERIPH_BASE_NS + 0x3800UL) #define GPIOP_BASE_NS (AHB4PERIPH_BASE_NS + 0x3C00UL) #define GPIOQ_BASE_NS (AHB4PERIPH_BASE_NS + 0x4000UL) #define PWR_BASE_NS (AHB4PERIPH_BASE_NS + 0x4800UL) #define CRC_BASE_NS (AHB4PERIPH_BASE_NS + 0x4C00UL) #define EXTI_BASE_NS (AHB4PERIPH_BASE_NS + 0x5000UL) #define RCC_BASE_NS (AHB4PERIPH_BASE_NS + 0x8000UL) /*!< APB5 peripherals */ #define LTDC_BASE_NS (APB5PERIPH_BASE_NS + 0x1000UL) #define LTDC_Layer1_BASE_NS (LTDC_BASE_NS + 0x0100UL) #define LTDC_Layer2_BASE_NS (LTDC_BASE_NS + 0x0200UL) #define DCMIPP_BASE_NS (APB5PERIPH_BASE_NS + 0x2000UL) #define GFXTIM_BASE_NS (APB5PERIPH_BASE_NS + 0x4000UL) #define VENC_BASE_NS (APB5PERIPH_BASE_NS + 0x5000UL) #define CSI_BASE_NS (APB5PERIPH_BASE_NS + 0x6000UL) /*!< AHB5 peripherals */ #define HPDMA1_BASE_NS (AHB5PERIPH_BASE_NS + 0x0000UL) #define HPDMA1_Channel0_BASE_NS (HPDMA1_BASE_NS + 0x0050UL) #define HPDMA1_Channel1_BASE_NS (HPDMA1_BASE_NS + 0x00D0UL) #define HPDMA1_Channel2_BASE_NS (HPDMA1_BASE_NS + 0x0150UL) #define HPDMA1_Channel3_BASE_NS (HPDMA1_BASE_NS + 0x01D0UL) #define HPDMA1_Channel4_BASE_NS (HPDMA1_BASE_NS + 0x0250UL) #define HPDMA1_Channel5_BASE_NS (HPDMA1_BASE_NS + 0x02D0UL) #define HPDMA1_Channel6_BASE_NS (HPDMA1_BASE_NS + 0x0350UL) #define HPDMA1_Channel7_BASE_NS (HPDMA1_BASE_NS + 0x03D0UL) #define HPDMA1_Channel8_BASE_NS (HPDMA1_BASE_NS + 0x0450UL) #define HPDMA1_Channel9_BASE_NS (HPDMA1_BASE_NS + 0x04D0UL) #define HPDMA1_Channel10_BASE_NS (HPDMA1_BASE_NS + 0x0550UL) #define HPDMA1_Channel11_BASE_NS (HPDMA1_BASE_NS + 0x05D0UL) #define HPDMA1_Channel12_BASE_NS (HPDMA1_BASE_NS + 0x0650UL) #define HPDMA1_Channel13_BASE_NS (HPDMA1_BASE_NS + 0x06D0UL) #define HPDMA1_Channel14_BASE_NS (HPDMA1_BASE_NS + 0x0750UL) #define HPDMA1_Channel15_BASE_NS (HPDMA1_BASE_NS + 0x07D0UL) #define DMA2D_BASE_NS (AHB5PERIPH_BASE_NS + 0x1000UL) #define JPEG_BASE_NS (AHB5PERIPH_BASE_NS + 0x3000UL) #define FMC_R_BASE_NS (AHB5PERIPH_BASE_NS + 0x4000UL) #define FMC_Bank1_R_BASE_NS (FMC_R_BASE_NS + 0x0000UL) #define FMC_Bank1E_R_BASE_NS (FMC_R_BASE_NS + 0x0104UL) #define FMC_Bank3_R_BASE_NS (FMC_R_BASE_NS + 0x0080UL) #define FMC_Bank5_6_R_BASE_NS (FMC_R_BASE_NS + 0x0140UL) #define FMC_Common_R_BASE_NS (FMC_R_BASE_NS + 0x0020UL) #define XSPI1_BASE_NS (AHB5PERIPH_BASE_NS + 0x5000UL) #define PSSI_BASE_NS (AHB5PERIPH_BASE_NS + 0x6400UL) #define SDMMC2_BASE_NS (AHB5PERIPH_BASE_NS + 0x6800UL) #define DLYB_SDMMC2_BASE_NS (AHB5PERIPH_BASE_NS + 0x6C00UL) #define SDMMC1_BASE_NS (AHB5PERIPH_BASE_NS + 0x7000UL) #define DLYB_SDMMC1_BASE_NS (AHB5PERIPH_BASE_NS + 0x8000UL) #define DCMI_BASE_NS (AHB5PERIPH_BASE_NS + 0x8400UL) #define XSPI2_BASE_NS (AHB5PERIPH_BASE_NS + 0xA000UL) #define XSPIM_BASE_NS (AHB5PERIPH_BASE_NS + 0xB400UL) #define MCE1_BASE_NS (AHB5PERIPH_BASE_NS + 0xB800UL) #define MCE1_REGION1_BASE_NS (MCE1_BASE_NS + 0x040UL) #define MCE1_REGION2_BASE_NS (MCE1_BASE_NS + 0x050UL) #define MCE1_REGION3_BASE_NS (MCE1_BASE_NS + 0x060UL) #define MCE1_REGION4_BASE_NS (MCE1_BASE_NS + 0x070UL) #define MCE1_CONTEXT1_BASE_NS (MCE1_BASE_NS + 0x240UL) #define MCE1_CONTEXT2_BASE_NS (MCE1_BASE_NS + 0x270UL) #define MCE2_BASE_NS (AHB5PERIPH_BASE_NS + 0xBC00UL) #define MCE2_REGION1_BASE_NS (MCE2_BASE_NS + 0x040UL) #define MCE2_REGION2_BASE_NS (MCE2_BASE_NS + 0x050UL) #define MCE2_REGION3_BASE_NS (MCE2_BASE_NS + 0x060UL) #define MCE2_REGION4_BASE_NS (MCE2_BASE_NS + 0x070UL) #define MCE2_CONTEXT1_BASE_NS (MCE2_BASE_NS + 0x240UL) #define MCE2_CONTEXT2_BASE_NS (MCE2_BASE_NS + 0x270UL) #define MCE3_BASE_NS (AHB5PERIPH_BASE_NS + 0xC000UL) #define MCE3_REGION1_BASE_NS (MCE3_BASE_NS + 0x040UL) #define MCE3_REGION2_BASE_NS (MCE3_BASE_NS + 0x050UL) #define MCE3_REGION3_BASE_NS (MCE3_BASE_NS + 0x060UL) #define MCE3_REGION4_BASE_NS (MCE3_BASE_NS + 0x070UL) #define MCE3_CONTEXT1_BASE_NS (MCE3_BASE_NS + 0x240UL) #define MCE3_CONTEXT2_BASE_NS (MCE3_BASE_NS + 0x270UL) #define MCE4_BASE_NS (AHB5PERIPH_BASE_NS + 0xE000UL) #define MCE4_REGION1_BASE_NS (MCE4_BASE_NS + 0x040UL) #define MCE4_REGION2_BASE_NS (MCE4_BASE_NS + 0x050UL) #define MCE4_REGION3_BASE_NS (MCE4_BASE_NS + 0x060UL) #define MCE4_REGION4_BASE_NS (MCE4_BASE_NS + 0x070UL) #define MCE4_CONTEXT1_BASE_NS (MCE4_BASE_NS + 0x240UL) #define MCE4_CONTEXT2_BASE_NS (MCE4_BASE_NS + 0x270UL) #define XSPI3_BASE_NS (AHB5PERIPH_BASE_NS + 0xD000UL) #define GFXMMU_BASE_NS (AHB5PERIPH_BASE_NS + 0x010000UL) #define GPU2D_BASE_NS (AHB5PERIPH_BASE_NS + 0x014000UL) #define GPUCACHE_BASE_NS (AHB5PERIPH_BASE_NS + 0x015000UL) #define ICACHE_BASE_NS (AHB5PERIPH_BASE_NS + 0x015000UL) #define ETH1_BASE_NS (AHB5PERIPH_BASE_NS + 0x016000UL) #define ETH1_MAC_BASE_NS (ETH1_BASE_NS) #define USB1_HS_PHYC_BASE_NS (AHB5PERIPH_BASE_NS + 0x01FC00UL) #define USB2_HS_PHYC_BASE_NS (AHB5PERIPH_BASE_NS + 0x0A0000UL) #define USB1_OTG_HS_BASE_NS (AHB5PERIPH_BASE_NS + 0x020000UL) #define USB2_OTG_HS_BASE_NS (AHB5PERIPH_BASE_NS + 0x060000UL) #define CACHEAXI_BASE_NS (AHB5PERIPH_BASE_NS + 0x0BFC00UL) #define NPU_BASE_NS (AHB5PERIPH_BASE_NS + 0x0C0000UL) /*!< Unique device ID register base address */ #define UID_BASE_NS (0x46009014UL) /*!< Revision ID base address */ #define REVID_BASE_NS (BOOTROM_BASE_NS + 0x0047ECUL) #if defined (CPU_IN_SECURE_STATE) /*********************************************************************/ /* */ /* Peripheral and internal SRAMs base addresses - Secure (aliased_S) */ /* */ /*********************************************************************/ #define ITCM_BASE_S 0x10000000UL /*!< Base address of ITCM from 64 KB up to 256 KB */ #define BOOTROM_BASE_S 0x18000000UL /*!< Base address of 128 KB boot ROM accessible over AXI */ #define DTCM_BASE_S 0x30000000UL /*!< Base address of DTCM from 128 KB up to 256 KB */ #define SRAM1_AXI_BASE_S 0x34000000UL /*!< Base address of up to 1 MB system RAM 1 accessible over AXI */ #define SRAM2_AXI_BASE_S 0x34100000UL /*!< Base address of 1 MB system RAM 2 accessible over AXI */ #define SRAM3_AXI_BASE_S 0x34200000UL /*!< Base address of 448 KB system RAM 3 accessible over AXI */ #define SRAM4_AXI_BASE_S 0x34270000UL /*!< Base address of 448 KB system RAM 4 accessible over AXI */ #define SRAM5_AXI_BASE_S 0x342E0000UL /*!< Base address of 448 KB system RAM 5 accessible over AXI */ #define SRAM6_AXI_BASE_S 0x34350000UL /*!< Base address of 448 KB system RAM 6 accessible over AXI */ #define SRAM_AXI_BASE_S SRAM1_AXI_BASE_NS /*!< Base address of 3.792 MB system RAM accessible over AXI */ #define CACHEAXI_RAM_BASE_S 0x343C0000UL /*!< Base address of 256 KB NPU Cache RAM accessible over AXI */ #define VENC_RAM_BASE_S 0x34400000UL /*!< Base address of 128 KB of Video Encoder RAM accessible over AXI */ #define GFXMMU_VIRTUAL_BUFFER0_BASE_S 0x35000000UL /*!< Base address of 4 MB GFXMMU virtual buffer 0 */ #define GFXMMU_VIRTUAL_BUFFER1_BASE_S 0x35400000UL /*!< Base address of 4 MB GFXMMU virtual buffer 1 */ #define GFXMMU_VIRTUAL_BUFFER2_BASE_S 0x35800000UL /*!< Base address of 4 MB GFXMMU virtual buffer 2 */ #define GFXMMU_VIRTUAL_BUFFER3_BASE_S 0x35C00000UL /*!< Base address of 4 MB GFXMMU virtual buffer 3 */ #define STM500_CHANNELS_BASE_S 0x37F00000UL /*!< Base address of 1 MB of STM500 Channels (System Trace) */ #define SRAM1_AHB_BASE_S 0x38000000UL /*!< Base address of 16 KB system RAM 1 over AXI->AHB Bridge */ #define SRAM2_AHB_BASE_S 0x38004000UL /*!< Base address of 16 KB system RAM 2 over AXI->AHB Bridge */ #define SRAM_AHB_BASE_S SRAM1_AHB_BASE_S /*!< Base address of 32 KB system RAM over AXI->AHB Bridge */ #define BKPSRAM_BASE_S 0x3C000000UL /*!< Base address of 8 KB Backup SRAM over AXI->AHB Bridge */ #define PERIPH_BASE_S 0x50000000UL /*!< Base address of : AHB/APB Peripherals */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE_S PERIPH_BASE_S #define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) #define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02000000UL) #define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) #define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x04000000UL) #define AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x04020000UL) #define APB4PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) #define AHB4PERIPH_BASE_S (PERIPH_BASE_S + 0x06020000UL) #define APB5PERIPH_BASE_S (PERIPH_BASE_S + 0x08000000UL) #define AHB5PERIPH_BASE_S (PERIPH_BASE_S + 0x08020000UL) /*!< APB1 peripherals */ #define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL) #define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) #define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL) #define TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL) #define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL) #define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL) #define TIM12_BASE_S (APB1PERIPH_BASE_S + 0x1800UL) #define TIM13_BASE_S (APB1PERIPH_BASE_S + 0x1C00UL) #define TIM14_BASE_S (APB1PERIPH_BASE_S + 0x2000UL) #define LPTIM1_BASE_S (APB1PERIPH_BASE_S + 0x2400UL) #define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) #define TIM10_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) #define TIM11_BASE_S (APB1PERIPH_BASE_S + 0x3400UL) #define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL) #define SPI3_BASE_S (APB1PERIPH_BASE_S + 0x3C00UL) #define SPDIFRX_BASE_S (APB1PERIPH_BASE_S + 0x4000UL) #define USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL) #define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL) #define UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL) #define UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL) #define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) #define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL) #define I2C3_BASE_S (APB1PERIPH_BASE_S + 0x5C00UL) #define I3C1_BASE_S (APB1PERIPH_BASE_S + 0x6000UL) #define I3C2_BASE_S (APB1PERIPH_BASE_S + 0x6400UL) #define UART7_BASE_S (APB1PERIPH_BASE_S + 0x7800UL) #define UART8_BASE_S (APB1PERIPH_BASE_S + 0x7C00UL) #define MDIOS_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) #define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA000UL) #define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0xA100UL) #define FDCAN2_BASE_S (APB1PERIPH_BASE_S + 0xA400UL) #define FDCAN_CCU_BASE_S (APB1PERIPH_BASE_S + 0xA800UL) #define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xC000UL) #define FDCAN3_BASE_S (APB1PERIPH_BASE_S + 0xE800UL) #define UCPD1_BASE_S (APB1PERIPH_BASE_S + 0xFC00UL) /*!< AHB1 peripherals */ #define GPDMA1_BASE_S (AHB1PERIPH_BASE_S + 0x1000UL) #define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) #define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) #define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) #define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) #define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) #define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) #define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) #define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) #define GPDMA1_Channel8_BASE_S (GPDMA1_BASE_S + 0x0450UL) #define GPDMA1_Channel9_BASE_S (GPDMA1_BASE_S + 0x04D0UL) #define GPDMA1_Channel10_BASE_S (GPDMA1_BASE_S + 0x0550UL) #define GPDMA1_Channel11_BASE_S (GPDMA1_BASE_S + 0x05D0UL) #define GPDMA1_Channel12_BASE_S (GPDMA1_BASE_S + 0x0650UL) #define GPDMA1_Channel13_BASE_S (GPDMA1_BASE_S + 0x06D0UL) #define GPDMA1_Channel14_BASE_S (GPDMA1_BASE_S + 0x0750UL) #define GPDMA1_Channel15_BASE_S (GPDMA1_BASE_S + 0x07D0UL) #define ADC1_BASE_S (AHB1PERIPH_BASE_S + 0x2000UL) #define ADC2_BASE_S (AHB1PERIPH_BASE_S + 0x2100UL) #define ADC12_COMMON_BASE_S (AHB1PERIPH_BASE_S + 0x2300UL) /*!< APB2 peripherals */ #define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x0000UL) #define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x0400UL) #define USART1_BASE_S (APB2PERIPH_BASE_S + 0x1000UL) #define USART6_BASE_S (APB2PERIPH_BASE_S + 0x1400UL) #define UART9_BASE_S (APB2PERIPH_BASE_S + 0x1800UL) #define USART10_BASE_S (APB2PERIPH_BASE_S + 0x1C00UL) #define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) #define SPI4_BASE_S (APB2PERIPH_BASE_S + 0x3400UL) #define TIM18_BASE_S (APB2PERIPH_BASE_S + 0x3C00UL) #define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL) #define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x4400UL) #define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x4800UL) #define TIM9_BASE_S (APB2PERIPH_BASE_S + 0x4C00UL) #define SPI5_BASE_S (APB2PERIPH_BASE_S + 0x5000UL) #define SAI1_BASE_S (APB2PERIPH_BASE_S + 0x5800UL) #define SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x0004UL) #define SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x0024UL) #define SAI2_BASE_S (APB2PERIPH_BASE_S + 0x5C00UL) #define SAI2_Block_A_BASE_S (SAI2_BASE_S + 0x0004UL) #define SAI2_Block_B_BASE_S (SAI2_BASE_S + 0x0024UL) /*!< AHB2 peripherals */ #define RAMCFG_BASE_S (AHB2PERIPH_BASE_S + 0x3000UL) #define RAMCFG_SRAM1_AXI_BASE_S (RAMCFG_BASE_S) #define RAMCFG_SRAM2_AXI_BASE_S (RAMCFG_BASE_S + 0x0080UL) #define RAMCFG_SRAM3_AXI_BASE_S (RAMCFG_BASE_S + 0x0100UL) #define RAMCFG_SRAM4_AXI_BASE_S (RAMCFG_BASE_S + 0x0180UL) #define RAMCFG_SRAM5_AXI_BASE_S (RAMCFG_BASE_S + 0x0200UL) #define RAMCFG_SRAM6_AXI_BASE_S (RAMCFG_BASE_S + 0x0280UL) #define RAMCFG_SRAM1_AHB_BASE_S (RAMCFG_BASE_S + 0x0300UL) #define RAMCFG_SRAM2_AHB_BASE_S (RAMCFG_BASE_S + 0x0380UL) #define RAMCFG_VENC_RAM_BASE_S (RAMCFG_BASE_S + 0x0400UL) #define RAMCFG_BKPSRAM_BASE_S (RAMCFG_BASE_S + 0x0480UL) #define RAMCFG_FLEXRAM_BASE_S (RAMCFG_BASE_S + 0x0500UL) #define MDF1_BASE_S (AHB2PERIPH_BASE_S + 0x5000UL) #define MDF1_Filter0_BASE_S (MDF1_BASE_S + 0x0080UL) #define MDF1_Filter1_BASE_S (MDF1_BASE_S + 0x0100UL) #define MDF1_Filter2_BASE_S (MDF1_BASE_S + 0x0180UL) #define MDF1_Filter3_BASE_S (MDF1_BASE_S + 0x0200UL) #define MDF1_Filter4_BASE_S (MDF1_BASE_S + 0x0280UL) #define MDF1_Filter5_BASE_S (MDF1_BASE_S + 0x0300UL) #define ADF1_BASE_S (AHB2PERIPH_BASE_S + 0x6000UL) #define ADF1_Filter0_BASE_S (ADF1_BASE_S + 0x0080UL) /*!< APB3 peripherals */ #define DAP_ROM_BASE_S (APB3PERIPH_BASE_S + 0x0000UL) #define DBGMCU_BASE_S (APB3PERIPH_BASE_S + 0x1000UL) #define DFT_APB_BASE_S (APB3PERIPH_BASE_S + 0x2000UL) /*!< AHB3 peripherals */ #define RNG_BASE_S (AHB3PERIPH_BASE_S + 0x0000UL) #define HASH_BASE_S (AHB3PERIPH_BASE_S + 0x0400UL) #define HASH_DIGEST_BASE_S (AHB3PERIPH_BASE_S + 0x0710UL) #define CRYP_BASE_S (AHB3PERIPH_BASE_S + 0x0800UL) #define SAES_BASE_S (AHB3PERIPH_BASE_S + 0x1000UL) #define PKA_BASE_S (AHB3PERIPH_BASE_S + 0x2000UL) #define RIFSC_BASE_S (AHB3PERIPH_BASE_S + 0x4000UL) #define IAC_BASE_S (AHB3PERIPH_BASE_S + 0x5000UL) #define RISAF1_BASE_S (AHB3PERIPH_BASE_S + 0x6000UL) #define RISAF2_BASE_S (AHB3PERIPH_BASE_S + 0x7000UL) #define RISAF3_BASE_S (AHB3PERIPH_BASE_S + 0x8000UL) #define RISAF4_BASE_S (AHB3PERIPH_BASE_S + 0x9000UL) #define RISAF5_BASE_S (AHB3PERIPH_BASE_S + 0xA000UL) #define RISAF6_BASE_S (AHB3PERIPH_BASE_S + 0xB000UL) #define RISAF7_BASE_S (AHB3PERIPH_BASE_S + 0xC000UL) #define RISAF8_BASE_S (AHB3PERIPH_BASE_S + 0xD000UL) #define RISAF9_BASE_S (AHB3PERIPH_BASE_S + 0xE000UL) #define RISAF11_BASE_S (AHB3PERIPH_BASE_S + 0x010000UL) #define RISAF12_BASE_S (AHB3PERIPH_BASE_S + 0x011000UL) #define RISAF13_BASE_S (AHB3PERIPH_BASE_S + 0x012000UL) #define RISAF14_BASE_S (AHB3PERIPH_BASE_S + 0x013000UL) #define RISAF15_BASE_S (AHB3PERIPH_BASE_S + 0x014000UL) #define RISAF21_BASE_S (AHB3PERIPH_BASE_S + 0x015000UL) #define RISAF22_BASE_S (AHB3PERIPH_BASE_S + 0x016000UL) #define RISAF23_BASE_S (AHB3PERIPH_BASE_S + 0x017000UL) /*!< APB4 peripherals */ #define HDP_BASE_S (APB4PERIPH_BASE_S + 0x0800UL) #define LPUART1_BASE_S (APB4PERIPH_BASE_S + 0x0C00UL) #define SPI6_BASE_S (APB4PERIPH_BASE_S + 0x1400UL) #define I2C4_BASE_S (APB4PERIPH_BASE_S + 0x1C00UL) #define LPTIM2_BASE_S (APB4PERIPH_BASE_S + 0x2400UL) #define LPTIM3_BASE_S (APB4PERIPH_BASE_S + 0x2800UL) #define LPTIM4_BASE_S (APB4PERIPH_BASE_S + 0x2C00UL) #define LPTIM5_BASE_S (APB4PERIPH_BASE_S + 0x3000UL) #define VREFBUF_BASE_S (APB4PERIPH_BASE_S + 0x3C00UL) #define RTC_BASE_S (APB4PERIPH_BASE_S + 0x4000UL) #define TAMP_BASE_S (APB4PERIPH_BASE_S + 0x4400UL) #define IWDG_BASE_S (APB4PERIPH_BASE_S + 0x4800UL) #define SERC_BASE_S (APB4PERIPH_BASE_S + 0x7C00UL) #define SYSCFG_BASE_S (APB4PERIPH_BASE_S + 0x8000UL) #define BSEC_BASE_S (APB4PERIPH_BASE_S + 0x9000UL) #define DTS_BASE_S (APB4PERIPH_BASE_S + 0xA000UL) #define DTS_Sensor0_BASE_S (DTS_BASE_S + 0x0C0UL) #define DTS_Sensor1_BASE_S (DTS_BASE_S + 0x100UL) /*!< AHB4 peripherals */ #define GPIOA_BASE_S (AHB4PERIPH_BASE_S + 0x0000UL) #define GPIOB_BASE_S (AHB4PERIPH_BASE_S + 0x0400UL) #define GPIOC_BASE_S (AHB4PERIPH_BASE_S + 0x0800UL) #define GPIOD_BASE_S (AHB4PERIPH_BASE_S + 0x0C00UL) #define GPIOE_BASE_S (AHB4PERIPH_BASE_S + 0x1000UL) #define GPIOF_BASE_S (AHB4PERIPH_BASE_S + 0x1400UL) #define GPIOG_BASE_S (AHB4PERIPH_BASE_S + 0x1800UL) #define GPIOH_BASE_S (AHB4PERIPH_BASE_S + 0x1C00UL) #define GPION_BASE_S (AHB4PERIPH_BASE_S + 0x3400UL) #define GPIOO_BASE_S (AHB4PERIPH_BASE_S + 0x3800UL) #define GPIOP_BASE_S (AHB4PERIPH_BASE_S + 0x3C00UL) #define GPIOQ_BASE_S (AHB4PERIPH_BASE_S + 0x4000UL) #define PWR_BASE_S (AHB4PERIPH_BASE_S + 0x4800UL) #define CRC_BASE_S (AHB4PERIPH_BASE_S + 0x4C00UL) #define EXTI_BASE_S (AHB4PERIPH_BASE_S + 0x5000UL) #define RCC_BASE_S (AHB4PERIPH_BASE_S + 0x8000UL) /*!< APB5 peripherals */ #define LTDC_BASE_S (APB5PERIPH_BASE_S + 0x1000UL) #define LTDC_Layer1_BASE_S (LTDC_BASE_S + 0x0100UL) #define LTDC_Layer2_BASE_S (LTDC_BASE_S + 0x0200UL) #define DCMIPP_BASE_S (APB5PERIPH_BASE_S + 0x2000UL) #define GFXTIM_BASE_S (APB5PERIPH_BASE_S + 0x4000UL) #define VENC_BASE_S (APB5PERIPH_BASE_S + 0x5000UL) #define CSI_BASE_S (APB5PERIPH_BASE_S + 0x6000UL) /*!< AHB5 peripherals */ #define HPDMA1_BASE_S (AHB5PERIPH_BASE_S + 0x0000UL) #define HPDMA1_Channel0_BASE_S (HPDMA1_BASE_S + 0x0050UL) #define HPDMA1_Channel1_BASE_S (HPDMA1_BASE_S + 0x00D0UL) #define HPDMA1_Channel2_BASE_S (HPDMA1_BASE_S + 0x0150UL) #define HPDMA1_Channel3_BASE_S (HPDMA1_BASE_S + 0x01D0UL) #define HPDMA1_Channel4_BASE_S (HPDMA1_BASE_S + 0x0250UL) #define HPDMA1_Channel5_BASE_S (HPDMA1_BASE_S + 0x02D0UL) #define HPDMA1_Channel6_BASE_S (HPDMA1_BASE_S + 0x0350UL) #define HPDMA1_Channel7_BASE_S (HPDMA1_BASE_S + 0x03D0UL) #define HPDMA1_Channel8_BASE_S (HPDMA1_BASE_S + 0x0450UL) #define HPDMA1_Channel9_BASE_S (HPDMA1_BASE_S + 0x04D0UL) #define HPDMA1_Channel10_BASE_S (HPDMA1_BASE_S + 0x0550UL) #define HPDMA1_Channel11_BASE_S (HPDMA1_BASE_S + 0x05D0UL) #define HPDMA1_Channel12_BASE_S (HPDMA1_BASE_S + 0x0650UL) #define HPDMA1_Channel13_BASE_S (HPDMA1_BASE_S + 0x06D0UL) #define HPDMA1_Channel14_BASE_S (HPDMA1_BASE_S + 0x0750UL) #define HPDMA1_Channel15_BASE_S (HPDMA1_BASE_S + 0x07D0UL) #define DMA2D_BASE_S (AHB5PERIPH_BASE_S + 0x1000UL) #define JPEG_BASE_S (AHB5PERIPH_BASE_S + 0x3000UL) #define FMC_R_BASE_S (AHB5PERIPH_BASE_S + 0x4000UL) #define FMC_Bank1_R_BASE_S (FMC_R_BASE_S + 0x0000UL) #define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL) #define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL) #define FMC_Bank5_6_R_BASE_S (FMC_R_BASE_S + 0x0140UL) #define FMC_Common_R_BASE_S (FMC_R_BASE_S + 0x0020UL) #define XSPI1_BASE_S (AHB5PERIPH_BASE_S + 0x5000UL) #define PSSI_BASE_S (AHB5PERIPH_BASE_S + 0x6400UL) #define SDMMC2_BASE_S (AHB5PERIPH_BASE_S + 0x6800UL) #define DLYB_SDMMC2_BASE_S (AHB5PERIPH_BASE_S + 0x6C00UL) #define SDMMC1_BASE_S (AHB5PERIPH_BASE_S + 0x7000UL) #define DLYB_SDMMC1_BASE_S (AHB5PERIPH_BASE_S + 0x8000UL) #define DCMI_BASE_S (AHB5PERIPH_BASE_S + 0x8400UL) #define XSPI2_BASE_S (AHB5PERIPH_BASE_S + 0xA000UL) #define XSPIM_BASE_S (AHB5PERIPH_BASE_S + 0xB400UL) #define MCE1_BASE_S (AHB5PERIPH_BASE_S + 0xB800UL) #define MCE1_REGION1_BASE_S (MCE1_BASE_S + 0x040UL) #define MCE1_REGION2_BASE_S (MCE1_BASE_S + 0x050UL) #define MCE1_REGION3_BASE_S (MCE1_BASE_S + 0x060UL) #define MCE1_REGION4_BASE_S (MCE1_BASE_S + 0x070UL) #define MCE1_CONTEXT1_BASE_S (MCE1_BASE_S + 0x240UL) #define MCE1_CONTEXT2_BASE_S (MCE1_BASE_S + 0x270UL) #define MCE2_BASE_S (AHB5PERIPH_BASE_S + 0xBC00UL) #define MCE2_REGION1_BASE_S (MCE2_BASE_S + 0x040UL) #define MCE2_REGION2_BASE_S (MCE2_BASE_S + 0x050UL) #define MCE2_REGION3_BASE_S (MCE2_BASE_S + 0x060UL) #define MCE2_REGION4_BASE_S (MCE2_BASE_S + 0x070UL) #define MCE2_CONTEXT1_BASE_S (MCE2_BASE_S + 0x240UL) #define MCE2_CONTEXT2_BASE_S (MCE2_BASE_S + 0x270UL) #define MCE3_BASE_S (AHB5PERIPH_BASE_S + 0xC000UL) #define MCE3_REGION1_BASE_S (MCE3_BASE_S + 0x040UL) #define MCE3_REGION2_BASE_S (MCE3_BASE_S + 0x050UL) #define MCE3_REGION3_BASE_S (MCE3_BASE_S + 0x060UL) #define MCE3_REGION4_BASE_S (MCE3_BASE_S + 0x070UL) #define MCE3_CONTEXT1_BASE_S (MCE3_BASE_S + 0x240UL) #define MCE3_CONTEXT2_BASE_S (MCE3_BASE_S + 0x270UL) #define MCE4_BASE_S (AHB5PERIPH_BASE_S + 0xE000UL) #define MCE4_REGION1_BASE_S (MCE4_BASE_S + 0x040UL) #define MCE4_REGION2_BASE_S (MCE4_BASE_S + 0x050UL) #define MCE4_REGION3_BASE_S (MCE4_BASE_S + 0x060UL) #define MCE4_REGION4_BASE_S (MCE4_BASE_S + 0x070UL) #define MCE4_CONTEXT1_BASE_S (MCE4_BASE_S + 0x240UL) #define MCE4_CONTEXT2_BASE_S (MCE4_BASE_S + 0x270UL) #define XSPI3_BASE_S (AHB5PERIPH_BASE_S + 0xD000UL) #define GFXMMU_BASE_S (AHB5PERIPH_BASE_S + 0x010000UL) #define GPU2D_BASE_S (AHB5PERIPH_BASE_S + 0x014000UL) #define GPUCACHE_BASE_S (AHB5PERIPH_BASE_S + 0x015000UL) #define ICACHE_BASE_S (AHB5PERIPH_BASE_S + 0x015000UL) #define ETH1_BASE_S (AHB5PERIPH_BASE_S + 0x016000UL) #define ETH1_MAC_BASE_S (ETH1_BASE_S) #define USB1_HS_PHYC_BASE_S (AHB5PERIPH_BASE_S + 0x01FC00UL) #define USB2_HS_PHYC_BASE_S (AHB5PERIPH_BASE_S + 0x0A0000UL) #define USB1_OTG_HS_BASE_S (AHB5PERIPH_BASE_S + 0x020000UL) #define USB2_OTG_HS_BASE_S (AHB5PERIPH_BASE_S + 0x060000UL) #define CACHEAXI_BASE_S (AHB5PERIPH_BASE_S + 0x0BFC00UL) #define NPU_BASE_S (AHB5PERIPH_BASE_S + 0x0C0000UL) /*!< Unique device ID register base address */ #define UID_BASE_S (0x56009014UL) /*!< Revision ID base address */ #define REVID_BASE_S (BOOTROM_BASE_S + 0x0047ECUL) #endif /** @} */ /* End of group STM32N6xx_Peripheral_peripheralAddr */ /* =========================================================================================================================== */ /* ================ Peripheral declaration ================ */ /* =========================================================================================================================== */ /** @addtogroup STM32N6xx_Peripheral_declaration * @{ */ #define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) #define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) #define ADC2_NS ((ADC_TypeDef *) ADC2_BASE_NS) #define ADF1_NS ((MDF_TypeDef *) ADF1_BASE_NS) #define ADF1_Filter0_NS ((MDF_Filter_TypeDef *) ADF1_Filter0_BASE_NS) #define BSEC_NS ((BSEC_TypeDef *) BSEC_BASE_NS) #define CACHEAXI_NS ((CACHEAXI_TypeDef *) CACHEAXI_BASE_NS) #define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) #define CRYP_NS ((CRYP_TypeDef *) CRYP_BASE_NS) #define CSI_NS ((CSI_TypeDef *) CSI_BASE_NS) #define DBGMCU_NS ((DBGMCU_TypeDef *) DBGMCU_BASE_NS) #define DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS) #define DCMIPP_NS ((DCMIPP_TypeDef *) DCMIPP_BASE_NS) #define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) #define DLYB_SDMMC2_NS ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_NS) #define DMA2D_NS ((DMA2D_TypeDef *) DMA2D_BASE_NS) #define DTS_NS ((DTS_TypeDef *) DTS_BASE_NS) #define DTS_Sensor0_NS ((DTS_SensorTypeDef *) DTS_Sensor0_BASE_NS) #define DTS_Sensor1_NS ((DTS_SensorTypeDef *) DTS_Sensor1_BASE_NS) #define ETH1_NS ((ETH_TypeDef *) ETH1_BASE_NS) #define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) #define FDCAN1_NS ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS) #define FDCAN2_NS ((FDCAN_GlobalTypeDef *) FDCAN2_BASE_NS) #define FDCAN3_NS ((FDCAN_GlobalTypeDef *) FDCAN3_BASE_NS) #define FDCAN_CCU_NS ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE_NS) #define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_NS) #define FMC_Bank1E_R_NS ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS) #define FMC_Bank1_R_NS ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS) #define FMC_Bank3_R_NS ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS) #define FMC_Bank5_6_R_NS ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE_NS) #define FMC_Common_R_NS ((FMC_Common_TypeDef *) FMC_Common_R_BASE_NS) #define GFXMMU_NS ((GFXMMU_TypeDef *) GFXMMU_BASE_NS) #define GFXTIM_NS ((GFXTIM_TypeDef *) GFXTIM_BASE_NS) #define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) #define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) #define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) #define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) #define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) #define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) #define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) #define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) #define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) #define GPDMA1_Channel8_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_NS) #define GPDMA1_Channel9_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_NS) #define GPDMA1_Channel10_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_NS) #define GPDMA1_Channel11_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_NS) #define GPDMA1_Channel12_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_NS) #define GPDMA1_Channel13_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_NS) #define GPDMA1_Channel14_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_NS) #define GPDMA1_Channel15_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_NS) #define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) #define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) #define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) #define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) #define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) #define GPIOF_NS ((GPIO_TypeDef *) GPIOF_BASE_NS) #define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) #define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) #define GPION_NS ((GPIO_TypeDef *) GPION_BASE_NS) #define GPIOO_NS ((GPIO_TypeDef *) GPIOO_BASE_NS) #define GPIOP_NS ((GPIO_TypeDef *) GPIOP_BASE_NS) #define GPIOQ_NS ((GPIO_TypeDef *) GPIOQ_BASE_NS) #define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) #define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) #define HPDMA1_NS ((DMA_TypeDef *) HPDMA1_BASE_NS) #define HPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel0_BASE_NS) #define HPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel1_BASE_NS) #define HPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel2_BASE_NS) #define HPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel3_BASE_NS) #define HPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel4_BASE_NS) #define HPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel5_BASE_NS) #define HPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel6_BASE_NS) #define HPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel7_BASE_NS) #define HPDMA1_Channel8_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel8_BASE_NS) #define HPDMA1_Channel9_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel9_BASE_NS) #define HPDMA1_Channel10_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel10_BASE_NS) #define HPDMA1_Channel11_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel11_BASE_NS) #define HPDMA1_Channel12_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel12_BASE_NS) #define HPDMA1_Channel13_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel13_BASE_NS) #define HPDMA1_Channel14_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel14_BASE_NS) #define HPDMA1_Channel15_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel15_BASE_NS) #define I2C1_NS ((I2C_TypeDef *) I2C1_BASE_NS) #define I2C2_NS ((I2C_TypeDef *) I2C2_BASE_NS) #define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) #define I2C4_NS ((I2C_TypeDef *) I2C4_BASE_NS) #define I3C1_NS ((I3C_TypeDef *) I3C1_BASE_NS) #define I3C2_NS ((I3C_TypeDef *) I3C2_BASE_NS) #define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) #define IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS) #define JPEG_NS ((JPEG_TypeDef *) JPEG_BASE_NS) #define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) #define LPTIM2_NS ((LPTIM_TypeDef *) LPTIM2_BASE_NS) #define LPTIM3_NS ((LPTIM_TypeDef *) LPTIM3_BASE_NS) #define LPTIM4_NS ((LPTIM_TypeDef *) LPTIM4_BASE_NS) #define LPTIM5_NS ((LPTIM_TypeDef *) LPTIM5_BASE_NS) #define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) #define LTDC_NS ((LTDC_TypeDef *)LTDC_BASE_NS) #define LTDC_Layer1_NS ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE_NS) #define LTDC_Layer2_NS ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE_NS) #define MCE1_NS ((MCE_TypeDef *) MCE1_BASE_NS) #define MCE1_REGION1_NS ((MCE_Region_TypeDef *) MCE1_REGION1_BASE_NS) #define MCE1_REGION2_NS ((MCE_Region_TypeDef *) MCE1_REGION2_BASE_NS) #define MCE1_REGION3_NS ((MCE_Region_TypeDef *) MCE1_REGION3_BASE_NS) #define MCE1_REGION4_NS ((MCE_Region_TypeDef *) MCE1_REGION4_BASE_NS) #define MCE1_CONTEXT1_NS ((MCE_Context_TypeDef *) MCE1_CONTEXT1_BASE_NS) #define MCE1_CONTEXT2_NS ((MCE_Context_TypeDef *) MCE1_CONTEXT2_BASE_NS) #define MCE2_NS ((MCE_TypeDef *) MCE2_BASE_NS) #define MCE2_REGION1_NS ((MCE_Region_TypeDef *) MCE2_REGION1_BASE_NS) #define MCE2_REGION2_NS ((MCE_Region_TypeDef *) MCE2_REGION2_BASE_NS) #define MCE2_REGION3_NS ((MCE_Region_TypeDef *) MCE2_REGION3_BASE_NS) #define MCE2_REGION4_NS ((MCE_Region_TypeDef *) MCE2_REGION4_BASE_NS) #define MCE2_CONTEXT1_NS ((MCE_Context_TypeDef *) MCE2_CONTEXT1_BASE_NS) #define MCE2_CONTEXT2_NS ((MCE_Context_TypeDef *) MCE2_CONTEXT2_BASE_NS) #define MCE3_NS ((MCE_TypeDef *) MCE3_BASE_NS) #define MCE3_REGION1_NS ((MCE_Region_TypeDef *) MCE3_REGION1_BASE_NS) #define MCE3_REGION2_NS ((MCE_Region_TypeDef *) MCE3_REGION2_BASE_NS) #define MCE3_REGION3_NS ((MCE_Region_TypeDef *) MCE3_REGION3_BASE_NS) #define MCE3_REGION4_NS ((MCE_Region_TypeDef *) MCE3_REGION4_BASE_NS) #define MCE3_CONTEXT1_NS ((MCE_Context_TypeDef *) MCE3_CONTEXT1_BASE_NS) #define MCE3_CONTEXT2_NS ((MCE_Context_TypeDef *) MCE3_CONTEXT2_BASE_NS) #define MCE4_NS ((MCE_TypeDef *) MCE4_BASE_NS) #define MCE4_REGION1_NS ((MCE_Region_TypeDef *) MCE4_REGION1_BASE_NS) #define MCE4_REGION2_NS ((MCE_Region_TypeDef *) MCE4_REGION2_BASE_NS) #define MCE4_REGION3_NS ((MCE_Region_TypeDef *) MCE4_REGION3_BASE_NS) #define MCE4_REGION4_NS ((MCE_Region_TypeDef *) MCE4_REGION4_BASE_NS) #define MCE4_CONTEXT1_NS ((MCE_Context_TypeDef *) MCE4_CONTEXT1_BASE_NS) #define MCE4_CONTEXT2_NS ((MCE_Context_TypeDef *) MCE4_CONTEXT2_BASE_NS) #define MDF1_NS ((MDF_TypeDef *) MDF1_BASE_NS) #define MDF1_Filter0_NS ((MDF_Filter_TypeDef *) MDF1_Filter0_BASE_NS) #define MDF1_Filter1_NS ((MDF_Filter_TypeDef *) MDF1_Filter1_BASE_NS) #define MDF1_Filter2_NS ((MDF_Filter_TypeDef *) MDF1_Filter2_BASE_NS) #define MDF1_Filter3_NS ((MDF_Filter_TypeDef *) MDF1_Filter3_BASE_NS) #define MDF1_Filter4_NS ((MDF_Filter_TypeDef *) MDF1_Filter4_BASE_NS) #define MDF1_Filter5_NS ((MDF_Filter_TypeDef *) MDF1_Filter5_BASE_NS) #define MDIOS_NS ((MDIOS_TypeDef *) MDIOS_BASE_NS) #define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) #define PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS) #define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) #define RAMCFG_NS ((RAMCFG_TypeDef *) RAMCFG_BASE_NS) #define RAMCFG_SRAM1_AXI_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AXI_BASE_NS) #define RAMCFG_SRAM2_AXI_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AXI_BASE_NS) #define RAMCFG_SRAM3_AXI_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM3_AXI_BASE_NS) #define RAMCFG_SRAM4_AXI_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM4_AXI_BASE_NS) #define RAMCFG_SRAM5_AXI_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM5_AXI_BASE_NS) #define RAMCFG_SRAM6_AXI_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM6_AXI_BASE_NS) #define RAMCFG_SRAM1_AHB_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AHB_BASE_NS) #define RAMCFG_SRAM2_AHB_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AHB_BASE_NS) #define RAMCFG_VENC_RAM_NS ((RAMCFG_TypeDef *) RAMCFG_VENC_RAM_BASE_NS) #define RAMCFG_BKPSRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPSRAM_BASE_NS) #define RAMCFG_FLEXRAM_NS ((RAMCFG_TypeDef *) RAMCFG_FLEXRAM_BASE_NS) #define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) #define RIFSC_NS ((RIFSC_TypeDef *) RIFSC_BASE_NS) #define RISAF1_NS ((RISAF_TypeDef *) RISAF1_BASE_NS) #define RISAF2_NS ((RISAF_TypeDef *) RISAF2_BASE_NS) #define RISAF3_NS ((RISAF_TypeDef *) RISAF3_BASE_NS) #define RISAF4_NS ((RISAF_TypeDef *) RISAF4_BASE_NS) #define RISAF5_NS ((RISAF_TypeDef *) RISAF5_BASE_NS) #define RISAF6_NS ((RISAF_TypeDef *) RISAF6_BASE_NS) #define RISAF7_NS ((RISAF_TypeDef *) RISAF7_BASE_NS) #define RISAF8_NS ((RISAF_TypeDef *) RISAF8_BASE_NS) #define RISAF9_NS ((RISAF_TypeDef *) RISAF9_BASE_NS) #define RISAF11_NS ((RISAF_TypeDef *) RISAF11_BASE_NS) #define RISAF12_NS ((RISAF_TypeDef *) RISAF12_BASE_NS) #define RISAF13_NS ((RISAF_TypeDef *) RISAF13_BASE_NS) #define RISAF14_NS ((RISAF_TypeDef *) RISAF14_BASE_NS) #define RISAF15_NS ((RISAF_TypeDef *) RISAF15_BASE_NS) #define RISAF21_NS ((RISAF_TypeDef *) RISAF21_BASE_NS) #define RISAF22_NS ((RISAF_TypeDef *) RISAF22_BASE_NS) #define RISAF23_NS ((RISAF_TypeDef *) RISAF23_BASE_NS) #define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) #define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) #define SAES_NS ((SAES_TypeDef *) SAES_BASE_NS) #define SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS) #define SAI1_Block_A_NS ((SAI_Block_TypeDef *) SAI1_Block_A_BASE_NS) #define SAI1_Block_B_NS ((SAI_Block_TypeDef *) SAI1_Block_B_BASE_NS) #define SAI2_NS ((SAI_TypeDef *) SAI2_BASE_NS) #define SAI2_Block_A_NS ((SAI_Block_TypeDef *) SAI2_Block_A_BASE_NS) #define SAI2_Block_B_NS ((SAI_Block_TypeDef *) SAI2_Block_B_BASE_NS) #define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) #define SDMMC2_NS ((SDMMC_TypeDef *) SDMMC2_BASE_NS) #define SPDIFRX_NS ((SPDIFRX_TypeDef *) SPDIFRX_BASE_NS) #define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) #define SPI2_NS ((SPI_TypeDef *) SPI2_BASE_NS) #define SPI3_NS ((SPI_TypeDef *) SPI3_BASE_NS) #define SPI4_NS ((SPI_TypeDef *) SPI4_BASE_NS) #define SPI5_NS ((SPI_TypeDef *) SPI5_BASE_NS) #define SPI6_NS ((SPI_TypeDef *) SPI6_BASE_NS) #define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS) #define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) #define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) #define TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS) #define TIM3_NS ((TIM_TypeDef *) TIM3_BASE_NS) #define TIM4_NS ((TIM_TypeDef *) TIM4_BASE_NS) #define TIM5_NS ((TIM_TypeDef *) TIM5_BASE_NS) #define TIM6_NS ((TIM_TypeDef *) TIM6_BASE_NS) #define TIM7_NS ((TIM_TypeDef *) TIM7_BASE_NS) #define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS) #define TIM9_NS ((TIM_TypeDef *) TIM9_BASE_NS) #define TIM10_NS ((TIM_TypeDef *) TIM10_BASE_NS) #define TIM11_NS ((TIM_TypeDef *) TIM11_BASE_NS) #define TIM12_NS ((TIM_TypeDef *) TIM12_BASE_NS) #define TIM13_NS ((TIM_TypeDef *) TIM13_BASE_NS) #define TIM14_NS ((TIM_TypeDef *) TIM14_BASE_NS) #define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) #define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS) #define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS) #define TIM18_NS ((TIM_TypeDef *) TIM18_BASE_NS) #define UART4_NS ((USART_TypeDef *) UART4_BASE_NS) #define UART5_NS ((USART_TypeDef *) UART5_BASE_NS) #define UART7_NS ((USART_TypeDef *) UART7_BASE_NS) #define UART8_NS ((USART_TypeDef *) UART8_BASE_NS) #define UART9_NS ((USART_TypeDef *) UART9_BASE_NS) #define UCPD1_NS ((UCPD_TypeDef *) UCPD1_BASE_NS) #define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) #define USART2_NS ((USART_TypeDef *) USART2_BASE_NS) #define USART3_NS ((USART_TypeDef *) USART3_BASE_NS) #define USART6_NS ((USART_TypeDef *) USART6_BASE_NS) #define USART10_NS ((USART_TypeDef *) USART10_BASE_NS) #define USB1_OTG_HS_NS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_BASE_NS) #define USB2_OTG_HS_NS ((USB_OTG_GlobalTypeDef *) USB2_OTG_HS_BASE_NS) #define USB1_HS_PHYC_NS ((USB_HS_PHYC_GlobalTypeDef *) USB1_HS_PHYC_BASE_NS) #define USB2_HS_PHYC_NS ((USB_HS_PHYC_GlobalTypeDef *) USB2_HS_PHYC_BASE_NS) #define VENC_NS ((VENC_TypeDef *) VENC_BASE_NS) #define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) #define WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS) #define XSPI1_NS ((XSPI_TypeDef *) XSPI1_BASE_NS) #define XSPI2_NS ((XSPI_TypeDef *) XSPI2_BASE_NS) #define XSPI3_NS ((XSPI_TypeDef *) XSPI3_BASE_NS) #define XSPIM_NS ((XSPIM_TypeDef *) XSPIM_BASE_NS) #if defined (CPU_IN_SECURE_STATE) #define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) #define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) #define ADC2_S ((ADC_TypeDef *) ADC2_BASE_S) #define ADF1_S ((MDF_TypeDef *) ADF1_BASE_S) #define ADF1_Filter0_S ((MDF_Filter_TypeDef *) ADF1_Filter0_BASE_S) #define BSEC_S ((BSEC_TypeDef *) BSEC_BASE_S) #define CACHEAXI_S ((CACHEAXI_TypeDef *) CACHEAXI_BASE_S) #define CRC_S ((CRC_TypeDef *) CRC_BASE_S) #define CRYP_S ((CRYP_TypeDef *) CRYP_BASE_S) #define CSI_S ((CSI_TypeDef *) CSI_BASE_S) #define DBGMCU_S ((DBGMCU_TypeDef *) DBGMCU_BASE_S) #define DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S) #define DCMIPP_S ((DCMIPP_TypeDef *) DCMIPP_BASE_S) #define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) #define DLYB_SDMMC2_S ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_S) #define DMA2D_S ((DMA2D_TypeDef *) DMA2D_BASE_S) #define DTS_S ((DTS_TypeDef *) DTS_BASE_S) #define DTS_Sensor0_S ((DTS_SensorTypeDef *) DTS_Sensor0_BASE_S) #define DTS_Sensor1_S ((DTS_SensorTypeDef *) DTS_Sensor1_BASE_S) #define ETH1_S ((ETH_TypeDef *) ETH1_BASE_S) #define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) #define FDCAN1_S ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S) #define FDCAN2_S ((FDCAN_GlobalTypeDef *) FDCAN2_BASE_S) #define FDCAN3_S ((FDCAN_GlobalTypeDef *) FDCAN3_BASE_S) #define FDCAN_CCU_S ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE_S) #define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_S) #define FMC_Bank1E_R_S ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S) #define FMC_Bank1_R_S ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S) #define FMC_Bank3_R_S ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S) #define FMC_Bank5_6_R_S ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE_S) #define FMC_Common_R_S ((FMC_Common_TypeDef *) FMC_Common_R_BASE_S) #define GFXMMU_S ((GFXMMU_TypeDef *) GFXMMU_BASE_S) #define GFXTIM_S ((GFXTIM_TypeDef *) GFXTIM_BASE_S) #define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) #define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) #define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) #define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) #define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) #define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) #define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) #define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) #define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) #define GPDMA1_Channel8_S ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_S) #define GPDMA1_Channel9_S ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_S) #define GPDMA1_Channel10_S ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_S) #define GPDMA1_Channel11_S ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_S) #define GPDMA1_Channel12_S ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_S) #define GPDMA1_Channel13_S ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_S) #define GPDMA1_Channel14_S ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_S) #define GPDMA1_Channel15_S ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_S) #define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) #define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) #define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) #define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) #define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) #define GPIOF_S ((GPIO_TypeDef *) GPIOF_BASE_S) #define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) #define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) #define GPION_S ((GPIO_TypeDef *) GPION_BASE_S) #define GPIOO_S ((GPIO_TypeDef *) GPIOO_BASE_S) #define GPIOP_S ((GPIO_TypeDef *) GPIOP_BASE_S) #define GPIOQ_S ((GPIO_TypeDef *) GPIOQ_BASE_S) #define HASH_S ((HASH_TypeDef *) HASH_BASE_S) #define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) #define HPDMA1_S ((DMA_TypeDef *) HPDMA1_BASE_S) #define HPDMA1_Channel0_S ((DMA_Channel_TypeDef *) HPDMA1_Channel0_BASE_S) #define HPDMA1_Channel1_S ((DMA_Channel_TypeDef *) HPDMA1_Channel1_BASE_S) #define HPDMA1_Channel2_S ((DMA_Channel_TypeDef *) HPDMA1_Channel2_BASE_S) #define HPDMA1_Channel3_S ((DMA_Channel_TypeDef *) HPDMA1_Channel3_BASE_S) #define HPDMA1_Channel4_S ((DMA_Channel_TypeDef *) HPDMA1_Channel4_BASE_S) #define HPDMA1_Channel5_S ((DMA_Channel_TypeDef *) HPDMA1_Channel5_BASE_S) #define HPDMA1_Channel6_S ((DMA_Channel_TypeDef *) HPDMA1_Channel6_BASE_S) #define HPDMA1_Channel7_S ((DMA_Channel_TypeDef *) HPDMA1_Channel7_BASE_S) #define HPDMA1_Channel8_S ((DMA_Channel_TypeDef *) HPDMA1_Channel8_BASE_S) #define HPDMA1_Channel9_S ((DMA_Channel_TypeDef *) HPDMA1_Channel9_BASE_S) #define HPDMA1_Channel10_S ((DMA_Channel_TypeDef *) HPDMA1_Channel10_BASE_S) #define HPDMA1_Channel11_S ((DMA_Channel_TypeDef *) HPDMA1_Channel11_BASE_S) #define HPDMA1_Channel12_S ((DMA_Channel_TypeDef *) HPDMA1_Channel12_BASE_S) #define HPDMA1_Channel13_S ((DMA_Channel_TypeDef *) HPDMA1_Channel13_BASE_S) #define HPDMA1_Channel14_S ((DMA_Channel_TypeDef *) HPDMA1_Channel14_BASE_S) #define HPDMA1_Channel15_S ((DMA_Channel_TypeDef *) HPDMA1_Channel15_BASE_S) #define I2C1_S ((I2C_TypeDef *) I2C1_BASE_S) #define I2C2_S ((I2C_TypeDef *) I2C2_BASE_S) #define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) #define I2C4_S ((I2C_TypeDef *) I2C4_BASE_S) #define I3C1_S ((I3C_TypeDef *) I3C1_BASE_S) #define I3C2_S ((I3C_TypeDef *) I3C2_BASE_S) #define IAC_S ((IAC_TypeDef *) IAC_BASE_S) #define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) #define IWDG_S ((IWDG_TypeDef *) IWDG_BASE_S) #define JPEG_S ((JPEG_TypeDef *) JPEG_BASE_S) #define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) #define LPTIM2_S ((LPTIM_TypeDef *) LPTIM2_BASE_S) #define LPTIM3_S ((LPTIM_TypeDef *) LPTIM3_BASE_S) #define LPTIM4_S ((LPTIM_TypeDef *) LPTIM4_BASE_S) #define LPTIM5_S ((LPTIM_TypeDef *) LPTIM5_BASE_S) #define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) #define LTDC_S ((LTDC_TypeDef *)LTDC_BASE_S) #define LTDC_Layer1_S ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE_S) #define LTDC_Layer2_S ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE_S) #define MCE1_S ((MCE_TypeDef *) MCE1_BASE_S) #define MCE1_REGION1_S ((MCE_Region_TypeDef *) MCE1_REGION1_BASE_S) #define MCE1_REGION2_S ((MCE_Region_TypeDef *) MCE1_REGION2_BASE_S) #define MCE1_REGION3_S ((MCE_Region_TypeDef *) MCE1_REGION3_BASE_S) #define MCE1_REGION4_S ((MCE_Region_TypeDef *) MCE1_REGION4_BASE_S) #define MCE1_CONTEXT1_S ((MCE_Context_TypeDef *) MCE1_CONTEXT1_BASE_S) #define MCE1_CONTEXT2_S ((MCE_Context_TypeDef *) MCE1_CONTEXT2_BASE_S) #define MCE2_S ((MCE_TypeDef *) MCE2_BASE_S) #define MCE2_REGION1_S ((MCE_Region_TypeDef *) MCE2_REGION1_BASE_S) #define MCE2_REGION2_S ((MCE_Region_TypeDef *) MCE2_REGION2_BASE_S) #define MCE2_REGION3_S ((MCE_Region_TypeDef *) MCE2_REGION3_BASE_S) #define MCE2_REGION4_S ((MCE_Region_TypeDef *) MCE2_REGION4_BASE_S) #define MCE2_CONTEXT1_S ((MCE_Context_TypeDef *) MCE2_CONTEXT1_BASE_S) #define MCE2_CONTEXT2_S ((MCE_Context_TypeDef *) MCE2_CONTEXT2_BASE_S) #define MCE3_S ((MCE_TypeDef *) MCE3_BASE_S) #define MCE3_REGION1_S ((MCE_Region_TypeDef *) MCE3_REGION1_BASE_S) #define MCE3_REGION2_S ((MCE_Region_TypeDef *) MCE3_REGION2_BASE_S) #define MCE3_REGION3_S ((MCE_Region_TypeDef *) MCE3_REGION3_BASE_S) #define MCE3_REGION4_S ((MCE_Region_TypeDef *) MCE3_REGION4_BASE_S) #define MCE3_CONTEXT1_S ((MCE_Context_TypeDef *) MCE3_CONTEXT1_BASE_S) #define MCE3_CONTEXT2_S ((MCE_Context_TypeDef *) MCE3_CONTEXT2_BASE_S) #define MCE4_S ((MCE_TypeDef *) MCE4_BASE_S) #define MCE4_REGION1_S ((MCE_Region_TypeDef *) MCE4_REGION1_BASE_S) #define MCE4_REGION2_S ((MCE_Region_TypeDef *) MCE4_REGION2_BASE_S) #define MCE4_REGION3_S ((MCE_Region_TypeDef *) MCE4_REGION3_BASE_S) #define MCE4_REGION4_S ((MCE_Region_TypeDef *) MCE4_REGION4_BASE_S) #define MCE4_CONTEXT1_S ((MCE_Context_TypeDef *) MCE4_CONTEXT1_BASE_S) #define MCE4_CONTEXT2_S ((MCE_Context_TypeDef *) MCE4_CONTEXT2_BASE_S) #define MDF1_S ((MDF_TypeDef *) MDF1_BASE_S) #define MDF1_Filter0_S ((MDF_Filter_TypeDef *) MDF1_Filter0_BASE_S) #define MDF1_Filter1_S ((MDF_Filter_TypeDef *) MDF1_Filter1_BASE_S) #define MDF1_Filter2_S ((MDF_Filter_TypeDef *) MDF1_Filter2_BASE_S) #define MDF1_Filter3_S ((MDF_Filter_TypeDef *) MDF1_Filter3_BASE_S) #define MDF1_Filter4_S ((MDF_Filter_TypeDef *) MDF1_Filter4_BASE_S) #define MDF1_Filter5_S ((MDF_Filter_TypeDef *) MDF1_Filter5_BASE_S) #define MDIOS_S ((MDIOS_TypeDef *) MDIOS_BASE_S) #define PKA_S ((PKA_TypeDef *) PKA_BASE_S) #define PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S) #define PWR_S ((PWR_TypeDef *) PWR_BASE_S) #define RAMCFG_S ((RAMCFG_TypeDef *) RAMCFG_BASE_S) #define RAMCFG_SRAM1_AXI_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AXI_BASE_S) #define RAMCFG_SRAM2_AXI_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AXI_BASE_S) #define RAMCFG_SRAM3_AXI_S ((RAMCFG_TypeDef *) RAMCFG_SRAM3_AXI_BASE_S) #define RAMCFG_SRAM4_AXI_S ((RAMCFG_TypeDef *) RAMCFG_SRAM4_AXI_BASE_S) #define RAMCFG_SRAM5_AXI_S ((RAMCFG_TypeDef *) RAMCFG_SRAM5_AXI_BASE_S) #define RAMCFG_SRAM6_AXI_S ((RAMCFG_TypeDef *) RAMCFG_SRAM6_AXI_BASE_S) #define RAMCFG_SRAM1_AHB_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AHB_BASE_S) #define RAMCFG_SRAM2_AHB_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AHB_BASE_S) #define RAMCFG_VENC_RAM_S ((RAMCFG_TypeDef *) RAMCFG_VENC_RAM_BASE_NS) #define RAMCFG_BKPSRAM_S ((RAMCFG_TypeDef *) RAMCFG_BKPSRAM_BASE_S) #define RAMCFG_FLEXRAM_S ((RAMCFG_TypeDef *) RAMCFG_FLEXRAM_BASE_S) #define RCC_S ((RCC_TypeDef *) RCC_BASE_S) #define RIFSC_S ((RIFSC_TypeDef *) RIFSC_BASE_S) #define RISAF1_S ((RISAF_TypeDef *) RISAF1_BASE_S) #define RISAF2_S ((RISAF_TypeDef *) RISAF2_BASE_S) #define RISAF3_S ((RISAF_TypeDef *) RISAF3_BASE_S) #define RISAF4_S ((RISAF_TypeDef *) RISAF4_BASE_S) #define RISAF5_S ((RISAF_TypeDef *) RISAF5_BASE_S) #define RISAF6_S ((RISAF_TypeDef *) RISAF6_BASE_S) #define RISAF7_S ((RISAF_TypeDef *) RISAF7_BASE_S) #define RISAF8_S ((RISAF_TypeDef *) RISAF8_BASE_S) #define RISAF9_S ((RISAF_TypeDef *) RISAF9_BASE_S) #define RISAF11_S ((RISAF_TypeDef *) RISAF11_BASE_S) #define RISAF12_S ((RISAF_TypeDef *) RISAF12_BASE_S) #define RISAF13_S ((RISAF_TypeDef *) RISAF13_BASE_S) #define RISAF14_S ((RISAF_TypeDef *) RISAF14_BASE_S) #define RISAF15_S ((RISAF_TypeDef *) RISAF15_BASE_S) #define RISAF21_S ((RISAF_TypeDef *) RISAF21_BASE_S) #define RISAF22_S ((RISAF_TypeDef *) RISAF22_BASE_S) #define RISAF23_S ((RISAF_TypeDef *) RISAF23_BASE_S) #define RNG_S ((RNG_TypeDef *) RNG_BASE_S) #define RTC_S ((RTC_TypeDef *) RTC_BASE_S) #define SAES_S ((SAES_TypeDef *) SAES_BASE_S) #define SAI1_S ((SAI_TypeDef *) SAI1_BASE_S) #define SAI1_Block_A_S ((SAI_Block_TypeDef *) SAI1_Block_A_BASE_S) #define SAI1_Block_B_S ((SAI_Block_TypeDef *) SAI1_Block_B_BASE_S) #define SAI2_S ((SAI_TypeDef *) SAI2_BASE_S) #define SAI2_Block_A_S ((SAI_Block_TypeDef *) SAI2_Block_A_BASE_S) #define SAI2_Block_B_S ((SAI_Block_TypeDef *) SAI2_Block_B_BASE_S) #define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) #define SDMMC2_S ((SDMMC_TypeDef *) SDMMC2_BASE_S) #define SPDIFRX_S ((SPDIFRX_TypeDef *) SPDIFRX_BASE_S) #define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) #define SPI2_S ((SPI_TypeDef *) SPI2_BASE_S) #define SPI3_S ((SPI_TypeDef *) SPI3_BASE_S) #define SPI4_S ((SPI_TypeDef *) SPI4_BASE_S) #define SPI5_S ((SPI_TypeDef *) SPI5_BASE_S) #define SPI6_S ((SPI_TypeDef *) SPI6_BASE_S) #define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE_S) #define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) #define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) #define TIM2_S ((TIM_TypeDef *) TIM2_BASE_S) #define TIM3_S ((TIM_TypeDef *) TIM3_BASE_S) #define TIM4_S ((TIM_TypeDef *) TIM4_BASE_S) #define TIM5_S ((TIM_TypeDef *) TIM5_BASE_S) #define TIM6_S ((TIM_TypeDef *) TIM6_BASE_S) #define TIM7_S ((TIM_TypeDef *) TIM7_BASE_S) #define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) #define TIM9_S ((TIM_TypeDef *) TIM9_BASE_S) #define TIM10_S ((TIM_TypeDef *) TIM10_BASE_S) #define TIM11_S ((TIM_TypeDef *) TIM11_BASE_S) #define TIM12_S ((TIM_TypeDef *) TIM12_BASE_S) #define TIM13_S ((TIM_TypeDef *) TIM13_BASE_S) #define TIM14_S ((TIM_TypeDef *) TIM14_BASE_S) #define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) #define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S) #define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S) #define TIM18_S ((TIM_TypeDef *) TIM18_BASE_S) #define UART4_S ((USART_TypeDef *) UART4_BASE_S) #define UART5_S ((USART_TypeDef *) UART5_BASE_S) #define UART7_S ((USART_TypeDef *) UART7_BASE_S) #define UART8_S ((USART_TypeDef *) UART8_BASE_S) #define UART9_S ((USART_TypeDef *) UART9_BASE_S) #define UCPD1_S ((UCPD_TypeDef *) UCPD1_BASE_S) #define USART1_S ((USART_TypeDef *) USART1_BASE_S) #define USART2_S ((USART_TypeDef *) USART2_BASE_S) #define USART3_S ((USART_TypeDef *) USART3_BASE_S) #define USART6_S ((USART_TypeDef *) USART6_BASE_S) #define USART10_S ((USART_TypeDef *) USART10_BASE_S) #define USB1_OTG_HS_S ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_BASE_S) #define USB2_OTG_HS_S ((USB_OTG_GlobalTypeDef *) USB2_OTG_HS_BASE_S) #define USB1_HS_PHYC_S ((USB_HS_PHYC_GlobalTypeDef *) USB1_HS_PHYC_BASE_S) #define USB2_HS_PHYC_S ((USB_HS_PHYC_GlobalTypeDef *) USB2_HS_PHYC_BASE_S) #define VENC_S ((VENC_TypeDef *) VENC_BASE_S) #define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) #define WWDG_S ((WWDG_TypeDef *) WWDG_BASE_S) #define XSPI1_S ((XSPI_TypeDef *) XSPI1_BASE_S) #define XSPI2_S ((XSPI_TypeDef *) XSPI2_BASE_S) #define XSPI3_S ((XSPI_TypeDef *) XSPI3_BASE_S) #define XSPIM_S ((XSPIM_TypeDef *) XSPIM_BASE_S) #endif /*!< Peripheral Instance aliases for Non-Secure/Secure execution */ #if defined (CPU_IN_SECURE_STATE) #define ADC12_COMMON ADC12_COMMON_S #define ADC12_COMMON_BASE ADC12_COMMON_BASE_S #define ADC1 ADC1_S #define ADC1_BASE ADC1_BASE_S #define ADC2 ADC2_S #define ADC2_BASE ADC2_BASE_S #define ADF1 ADF1_S #define ADF1_BASE ADF1_BASE_S #define ADF1_Filter0 ADF1_Filter0_S #define ADF1_Filter0_BASE ADF1_Filter0_BASE_S #define BSEC BSEC_S #define BSEC_BASE BSEC_BASE_S #define CACHEAXI CACHEAXI_S #define CACHEAXI_BASE CACHEAXI_BASE_S #define CRC CRC_S #define CRC_BASE CRC_BASE_S #define CRYP CRYP_S #define CRYP_BASE CRYP_BASE_S #define CSI CSI_S #define CSI_BASE CSI_BASE_S #define DBGMCU DBGMCU_S #define DBGMCU_BASE DBGMCU_BASE_S #define DCMI DCMI_S #define DCMI_BASE DCMI_BASE_S #define DCMIPP DCMIPP_S #define DCMIPP_BASE DCMIPP_BASE_S #define DLYB_SDMMC1 DLYB_SDMMC1_S #define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S #define DLYB_SDMMC2 DLYB_SDMMC2_S #define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_S #define DMA2D DMA2D_S #define DMA2D_BASE DMA2D_BASE_S #define DTS DTS_S #define DTS_BASE DTS_BASE_S #define DTS_Sensor0 DTS_Sensor0_S #define DTS_Sensor0_BASE DTS_Sensor0_BASE_S #define DTS_Sensor1 DTS_Sensor1_S #define DTS_Sensor1_BASE DTS_Sensor1_BASE_S #define ETH1 ETH1_S #define ETH1_BASE ETH1_BASE_S #define EXTI EXTI_S #define EXTI_BASE EXTI_BASE_S #define FDCAN1 FDCAN1_S #define FDCAN1_BASE FDCAN1_BASE_S #define FDCAN2 FDCAN2_S #define FDCAN2_BASE FDCAN2_BASE_S #define FDCAN3 FDCAN3_S #define FDCAN3_BASE FDCAN3_BASE_S #define FDCAN_CCU FDCAN_CCU_S #define FDCAN_CCU_BASE FDCAN_CCU_BASE_S #define FDCAN_CONFIG FDCAN_CONFIG_S #define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S #define FMC_R_BASE FMC_R_BASE_S #define FMC_Bank1E_R FMC_Bank1E_R_S #define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_S #define FMC_Bank1_R FMC_Bank1_R_S #define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_S #define FMC_Bank3_R FMC_Bank3_R_S #define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_S #define FMC_Bank5_6_R FMC_Bank5_6_R_S #define FMC_Bank5_6_R_BASE FMC_Bank5_6_R_BASE_S #define FMC_Common_R FMC_Common_R_S #define FMC_Common_R_BASE FMC_Common_R_BASE_S #define GFXMMU GFXMMU_S #define GFXMMU_BASE GFXMMU_BASE_S #define GFXMMU_VIRTUAL_BUFFER0_BASE GFXMMU_VIRTUAL_BUFFER0_BASE_S #define GFXMMU_VIRTUAL_BUFFER1_BASE GFXMMU_VIRTUAL_BUFFER1_BASE_S #define GFXMMU_VIRTUAL_BUFFER2_BASE GFXMMU_VIRTUAL_BUFFER2_BASE_S #define GFXMMU_VIRTUAL_BUFFER3_BASE GFXMMU_VIRTUAL_BUFFER3_BASE_S #define GFXTIM GFXTIM_S #define GFXTIM_BASE GFXTIM_BASE_S #define GPDMA1 GPDMA1_S #define GPDMA1_BASE GPDMA1_BASE_S #define GPDMA1_Channel0 GPDMA1_Channel0_S #define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S #define GPDMA1_Channel1 GPDMA1_Channel1_S #define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S #define GPDMA1_Channel2 GPDMA1_Channel2_S #define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S #define GPDMA1_Channel3 GPDMA1_Channel3_S #define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S #define GPDMA1_Channel4 GPDMA1_Channel4_S #define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S #define GPDMA1_Channel5 GPDMA1_Channel5_S #define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S #define GPDMA1_Channel6 GPDMA1_Channel6_S #define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S #define GPDMA1_Channel7 GPDMA1_Channel7_S #define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S #define GPDMA1_Channel8 GPDMA1_Channel8_S #define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_S #define GPDMA1_Channel9 GPDMA1_Channel9_S #define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_S #define GPDMA1_Channel10 GPDMA1_Channel10_S #define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_S #define GPDMA1_Channel11 GPDMA1_Channel11_S #define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_S #define GPDMA1_Channel12 GPDMA1_Channel12_S #define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_S #define GPDMA1_Channel13 GPDMA1_Channel13_S #define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_S #define GPDMA1_Channel14 GPDMA1_Channel14_S #define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_S #define GPDMA1_Channel15 GPDMA1_Channel15_S #define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_S #define GPIOA GPIOA_S #define GPIOA_BASE GPIOA_BASE_S #define GPIOB GPIOB_S #define GPIOB_BASE GPIOB_BASE_S #define GPIOC GPIOC_S #define GPIOC_BASE GPIOC_BASE_S #define GPIOD GPIOD_S #define GPIOD_BASE GPIOD_BASE_S #define GPIOE GPIOE_S #define GPIOE_BASE GPIOE_BASE_S #define GPIOF GPIOF_S #define GPIOF_BASE GPIOF_BASE_S #define GPIOG GPIOG_S #define GPIOG_BASE GPIOG_BASE_S #define GPIOH GPIOH_S #define GPIOH_BASE GPIOH_BASE_S #define GPION GPION_S #define GPION_BASE GPION_BASE_S #define GPIOO GPIOO_S #define GPIOO_BASE GPIOO_BASE_S #define GPIOP GPIOP_S #define GPIOP_BASE GPIOP_BASE_S #define GPIOQ GPIOQ_S #define GPIOQ_BASE GPIOQ_BASE_S #define GPU2D GPU2D_BASE_S #define GPU2D_BASE GPU2D_BASE_S #define HASH HASH_S #define HASH_BASE HASH_BASE_S #define HASH_DIGEST HASH_DIGEST_S #define HASH_DIGEST_BASE HASH_DIGEST_BASE_S #define HPDMA1 HPDMA1_S #define HPDMA1_BASE HPDMA1_BASE_S #define HPDMA1_Channel0 HPDMA1_Channel0_S #define HPDMA1_Channel0_BASE HPDMA1_Channel0_BASE_S #define HPDMA1_Channel1 HPDMA1_Channel1_S #define HPDMA1_Channel1_BASE HPDMA1_Channel1_BASE_S #define HPDMA1_Channel2 HPDMA1_Channel2_S #define HPDMA1_Channel2_BASE HPDMA1_Channel2_BASE_S #define HPDMA1_Channel3 HPDMA1_Channel3_S #define HPDMA1_Channel3_BASE HPDMA1_Channel3_BASE_S #define HPDMA1_Channel4 HPDMA1_Channel4_S #define HPDMA1_Channel4_BASE HPDMA1_Channel4_BASE_S #define HPDMA1_Channel5 HPDMA1_Channel5_S #define HPDMA1_Channel5_BASE HPDMA1_Channel5_BASE_S #define HPDMA1_Channel6 HPDMA1_Channel6_S #define HPDMA1_Channel6_BASE HPDMA1_Channel6_BASE_S #define HPDMA1_Channel7 HPDMA1_Channel7_S #define HPDMA1_Channel7_BASE HPDMA1_Channel7_BASE_S #define HPDMA1_Channel8 HPDMA1_Channel8_S #define HPDMA1_Channel8_BASE HPDMA1_Channel8_BASE_S #define HPDMA1_Channel9 HPDMA1_Channel9_S #define HPDMA1_Channel9_BASE HPDMA1_Channel9_BASE_S #define HPDMA1_Channel10 HPDMA1_Channel10_S #define HPDMA1_Channel10_BASE HPDMA1_Channel10_BASE_S #define HPDMA1_Channel11 HPDMA1_Channel11_S #define HPDMA1_Channel11_BASE HPDMA1_Channel11_BASE_S #define HPDMA1_Channel12 HPDMA1_Channel12_S #define HPDMA1_Channel12_BASE HPDMA1_Channel12_BASE_S #define HPDMA1_Channel13 HPDMA1_Channel13_S #define HPDMA1_Channel13_BASE HPDMA1_Channel13_BASE_S #define HPDMA1_Channel14 HPDMA1_Channel14_S #define HPDMA1_Channel14_BASE HPDMA1_Channel14_BASE_S #define HPDMA1_Channel15 HPDMA1_Channel15_S #define HPDMA1_Channel15_BASE HPDMA1_Channel15_BASE_S #define I2C1 I2C1_S #define I2C1_BASE I2C1_BASE_S #define I2C2 I2C2_S #define I2C2_BASE I2C2_BASE_S #define I2C3 I2C3_S #define I2C3_BASE I2C3_BASE_S #define I2C4 I2C4_S #define I2C4_BASE I2C4_BASE_S #define I3C1 I3C1_S #define I3C1_BASE I3C1_BASE_S #define I3C2 I3C2_S #define I3C2_BASE I3C2_BASE_S #define IAC IAC_S #define IAC_BASE IAC_BASE_S #define ICACHE ICACHE_S #define ICACHE_BASE ICACHE_BASE_S #define IWDG IWDG_S #define IWDG_BASE IWDG_BASE_S #define JPEG JPEG_S #define JPEG_BASE JPEG_BASE_S #define LPTIM1 LPTIM1_S #define LPTIM1_BASE LPTIM1_BASE_S #define LPTIM2 LPTIM2_S #define LPTIM2_BASE LPTIM2_BASE_S #define LPTIM3 LPTIM3_S #define LPTIM3_BASE LPTIM3_BASE_S #define LPTIM4 LPTIM4_S #define LPTIM4_BASE LPTIM4_BASE_S #define LPTIM5 LPTIM5_S #define LPTIM5_BASE LPTIM5_BASE_S #define LPUART1 LPUART1_S #define LPUART1_BASE LPUART1_BASE_S #define LTDC LTDC_S #define LTDC_BASE LTDC_BASE_S #define LTDC_Layer1 LTDC_Layer1_S #define LTDC_Layer1_BASE LTDC_Layer1_BASE_S #define LTDC_Layer2 LTDC_Layer2_S #define LTDC_Layer2_BASE LTDC_Layer2_BASE_S #define MCE1 MCE1_S #define MCE1_BASE MCE1_BASE_S #define MCE1_REGION1 MCE1_REGION1_S #define MCE1_REGION1_BASE MCE1_REGION1_BASE_S #define MCE1_REGION2 MCE1_REGION2_S #define MCE1_REGION2_BASE MCE1_REGION2_BASE_S #define MCE1_REGION3 MCE1_REGION3_S #define MCE1_REGION3_BASE MCE1_REGION3_BASE_S #define MCE1_REGION4 MCE1_REGION4_S #define MCE1_REGION4_BASE MCE1_REGION4_BASE_S #define MCE1_CONTEXT1 MCE1_CONTEXT1_S #define MCE1_CONTEXT1_BASE MCE1_CONTEXT1_BASE_S #define MCE1_CONTEXT2 MCE1_CONTEXT2_S #define MCE1_CONTEXT2_BASE MCE1_CONTEXT2_BASE_S #define MCE2 MCE2_S #define MCE2_BASE MCE2_BASE_S #define MCE2_REGION1 MCE2_REGION1_S #define MCE2_REGION1_BASE MCE2_REGION1_BASE_S #define MCE2_REGION2 MCE2_REGION2_S #define MCE2_REGION2_BASE MCE2_REGION2_BASE_S #define MCE2_REGION3 MCE2_REGION3_S #define MCE2_REGION3_BASE MCE2_REGION3_BASE_S #define MCE2_REGION4 MCE2_REGION4_S #define MCE2_REGION4_BASE MCE2_REGION4_BASE_S #define MCE2_CONTEXT1 MCE2_CONTEXT1_S #define MCE2_CONTEXT1_BASE MCE2_CONTEXT1_BASE_S #define MCE2_CONTEXT2 MCE2_CONTEXT2_S #define MCE2_CONTEXT2_BASE MCE2_CONTEXT2_BASE_S #define MCE3 MCE3_S #define MCE3_BASE MCE3_BASE_S #define MCE3_REGION1 MCE3_REGION1_S #define MCE3_REGION1_BASE MCE3_REGION1_BASE_S #define MCE3_REGION2 MCE3_REGION2_S #define MCE3_REGION2_BASE MCE3_REGION2_BASE_S #define MCE3_REGION3 MCE3_REGION3_S #define MCE3_REGION3_BASE MCE3_REGION3_BASE_S #define MCE3_REGION4 MCE3_REGION4_S #define MCE3_REGION4_BASE MCE3_REGION4_BASE_S #define MCE3_CONTEXT1 MCE3_CONTEXT1_S #define MCE3_CONTEXT1_BASE MCE3_CONTEXT1_BASE_S #define MCE3_CONTEXT2 MCE3_CONTEXT2_S #define MCE3_CONTEXT2_BASE MCE3_CONTEXT2_BASE_S #define MCE4 MCE4_S #define MCE4_BASE MCE4_BASE_S #define MCE4_REGION1 MCE4_REGION1_S #define MCE4_REGION1_BASE MCE4_REGION1_BASE_S #define MCE4_REGION2 MCE4_REGION2_S #define MCE4_REGION2_BASE MCE4_REGION2_BASE_S #define MCE4_REGION3 MCE4_REGION3_S #define MCE4_REGION3_BASE MCE4_REGION3_BASE_S #define MCE4_REGION4 MCE4_REGION4_S #define MCE4_REGION4_BASE MCE4_REGION4_BASE_S #define MCE4_CONTEXT1 MCE4_CONTEXT1_S #define MCE4_CONTEXT1_BASE MCE4_CONTEXT1_BASE_S #define MCE4_CONTEXT2 MCE4_CONTEXT2_S #define MCE4_CONTEXT2_BASE MCE4_CONTEXT2_BASE_S #define MDF1 MDF1_S #define MDF1_BASE MDF1_BASE_S #define MDF1_Filter0 MDF1_Filter0_S #define MDF1_Filter0_BASE MDF1_Filter0_BASE_S #define MDF1_Filter1 MDF1_Filter1_S #define MDF1_Filter1_BASE MDF1_Filter1_BASE_S #define MDF1_Filter2 MDF1_Filter2_S #define MDF1_Filter2_BASE MDF1_Filter2_BASE_S #define MDF1_Filter3 MDF1_Filter3_S #define MDF1_Filter3_BASE MDF1_Filter3_BASE_S #define MDF1_Filter4 MDF1_Filter4_S #define MDF1_Filter4_BASE MDF1_Filter4_BASE_S #define MDF1_Filter5 MDF1_Filter5_S #define MDF1_Filter5_BASE MDF1_Filter5_BASE_S #define MDIOS MDIOS_S #define MDIOS_BASE MDIOS_BASE_S #define NPU_PRESENT #define NPU_BASE NPU_BASE_S #define PKA PKA_S #define PKA_BASE PKA_BASE_S #define PSSI PSSI_S #define PSSI_BASE PSSI_BASE_S #define PWR PWR_S #define PWR_BASE PWR_BASE_S #define RAMCFG RAMCFG_S #define RAMCFG_BASE RAMCFG_BASE_S #define RAMCFG_SRAM1_AXI RAMCFG_SRAM1_AXI_S #define RAMCFG_SRAM1_AXI_BASE RAMCFG_SRAM1_AXI_BASE_S #define RAMCFG_SRAM2_AXI RAMCFG_SRAM2_AXI_S #define RAMCFG_SRAM2_AXI_BASE RAMCFG_SRAM2_AXI_BASE_S #define RAMCFG_SRAM3_AXI RAMCFG_SRAM3_AXI_S #define RAMCFG_SRAM3_AXI_BASE RAMCFG_SRAM3_AXI_BASE_S #define RAMCFG_SRAM4_AXI RAMCFG_SRAM4_AXI_S #define RAMCFG_SRAM4_AXI_BASE RAMCFG_SRAM4_AXI_BASE_S #define RAMCFG_SRAM5_AXI RAMCFG_SRAM5_AXI_S #define RAMCFG_SRAM5_AXI_BASE RAMCFG_SRAM5_AXI_BASE_S #define RAMCFG_SRAM6_AXI RAMCFG_SRAM6_AXI_S #define RAMCFG_SRAM6_AXI_BASE RAMCFG_SRAM6_AXI_BASE_S #define RAMCFG_SRAM1_AHB RAMCFG_SRAM1_AHB_S #define RAMCFG_SRAM1_AHB_BASE RAMCFG_SRAM1_AHB_BASE_S #define RAMCFG_SRAM2_AHB RAMCFG_SRAM2_AHB_S #define RAMCFG_SRAM2_AHB_BASE RAMCFG_SRAM2_AHB_BASE_S #define RAMCFG_VENC_RAM RAMCFG_VENC_RAM_S #define RAMCFG_VENC_RAM_BASE RAMCFG_VENC_RAM_BASE_S #define RAMCFG_BKPSRAM RAMCFG_BKPSRAM_S #define RAMCFG_BKPSRAM_BASE RAMCFG_BKPSRAM_BASE_S #define RAMCFG_FLEXRAM RAMCFG_FLEXRAM_S #define RAMCFG_FLEXRAM_BASE RAMCFG_FLEXRAM_BASE_S #define RCC RCC_S #define RCC_BASE RCC_BASE_S #define RIFSC RIFSC_S #define RIFSC_BASE RIFSC_BASE_S #define RISAF1 RISAF1_S #define RISAF1_BASE RISAF1_BASE_S #define RISAF2 RISAF2_S #define RISAF2_BASE RISAF2_BASE_S #define RISAF3 RISAF3_S #define RISAF3_BASE RISAF3_BASE_S #define RISAF4 RISAF4_S #define RISAF4_BASE RISAF4_BASE_S #define RISAF5 RISAF5_S #define RISAF5_BASE RISAF5_BASE_S #define RISAF6 RISAF6_S #define RISAF6_BASE RISAF6_BASE_S #define RISAF7 RISAF7_S #define RISAF7_BASE RISAF7_BASE_S #define RISAF8 RISAF8_S #define RISAF8_BASE RISAF8_BASE_S #define RISAF9 RISAF9_S #define RISAF9_BASE RISAF9_BASE_S #define RISAF11 RISAF11_S #define RISAF11_BASE RISAF11_BASE_S #define RISAF12 RISAF12_S #define RISAF12_BASE RISAF12_BASE_S #define RISAF13 RISAF13_S #define RISAF13_BASE RISAF13_BASE_S #define RISAF14 RISAF14_S #define RISAF14_BASE RISAF14_BASE_S #define RISAF15 RISAF15_S #define RISAF15_BASE RISAF15_BASE_S #define RISAF21 RISAF21_S #define RISAF21_BASE RISAF21_BASE_S #define RISAF22 RISAF22_S #define RISAF22_BASE RISAF22_BASE_S #define RISAF23 RISAF23_S #define RISAF23_BASE RISAF23_BASE_S #define RNG RNG_S #define RNG_BASE RNG_BASE_S #define RTC RTC_S #define RTC_BASE RTC_BASE_S #define SAES SAES_S #define SAES_BASE SAES_BASE_S #define SAI1 SAI1_S #define SAI1_BASE SAI1_BASE_S #define SAI1_Block_A SAI1_Block_A_S #define SAI1_Block_A_BASE SAI1_Block_A_BASE_S #define SAI1_Block_B SAI1_Block_B_S #define SAI1_Block_B_BASE SAI1_Block_B_BASE_S #define SAI2 SAI2_S #define SAI2_BASE SAI2_BASE_S #define SAI2_Block_A SAI2_Block_A_S #define SAI2_Block_A_BASE SAI2_Block_A_BASE_S #define SAI2_Block_B SAI2_Block_B_S #define SAI2_Block_B_BASE SAI2_Block_B_BASE_S #define SDMMC1 SDMMC1_S #define SDMMC1_BASE SDMMC1_BASE_S #define SDMMC2 SDMMC2_S #define SDMMC2_BASE SDMMC2_BASE_S #define SPDIFRX SPDIFRX_S #define SPDIFRX_BASE SPDIFRX_BASE_S #define SPI1 SPI1_S #define SPI1_BASE SPI1_BASE_S #define SPI2 SPI2_S #define SPI2_BASE SPI2_BASE_S #define SPI3 SPI3_S #define SPI3_BASE SPI3_BASE_S #define SPI4 SPI4_S #define SPI4_BASE SPI4_BASE_S #define SPI5 SPI5_S #define SPI5_BASE SPI5_BASE_S #define SPI6 SPI6_S #define SPI6_BASE SPI6_BASE_S #define SRAMCAN_BASE SRAMCAN_BASE_S #define SYSCFG SYSCFG_S #define SYSCFG_BASE SYSCFG_BASE_S #define TAMP TAMP_S #define TAMP_BASE TAMP_BASE_S #define TIM1 TIM1_S #define TIM1_BASE TIM1_BASE_S #define TIM2 TIM2_S #define TIM2_BASE TIM2_BASE_S #define TIM3 TIM3_S #define TIM3_BASE TIM3_BASE_S #define TIM4 TIM4_S #define TIM4_BASE TIM4_BASE_S #define TIM5 TIM5_S #define TIM5_BASE TIM5_BASE_S #define TIM6 TIM6_S #define TIM6_BASE TIM6_BASE_S #define TIM7 TIM7_S #define TIM7_BASE TIM7_BASE_S #define TIM8 TIM8_S #define TIM8_BASE TIM8_BASE_S #define TIM9 TIM9_S #define TIM9_BASE TIM9_BASE_S #define TIM10 TIM10_S #define TIM10_BASE TIM10_BASE_S #define TIM11 TIM11_S #define TIM11_BASE TIM11_BASE_S #define TIM12 TIM12_S #define TIM12_BASE TIM12_BASE_S #define TIM13 TIM13_S #define TIM13_BASE TIM13_BASE_S #define TIM14 TIM14_S #define TIM14_BASE TIM14_BASE_S #define TIM15 TIM15_S #define TIM15_BASE TIM15_BASE_S #define TIM16 TIM16_S #define TIM16_BASE TIM16_BASE_S #define TIM17 TIM17_S #define TIM17_BASE TIM17_BASE_S #define TIM18 TIM18_S #define TIM18_BASE TIM18_BASE_S #define UART4 UART4_S #define UART4_BASE UART4_BASE_S #define UART5 UART5_S #define UART5_BASE UART5_BASE_S #define UART7 UART7_S #define UART7_BASE UART7_BASE_S #define UART8 UART8_S #define UART8_BASE UART8_BASE_S #define UART9 UART9_S #define UART9_BASE UART9_BASE_S #define UCPD1 UCPD1_S #define UCPD1_BASE UCPD1_BASE_S #define USART1 USART1_S #define USART1_BASE USART1_BASE_S #define USART2 USART2_S #define USART2_BASE USART2_BASE_S #define USART3 USART3_S #define USART3_BASE USART3_BASE_S #define USART6 USART6_S #define USART6_BASE USART6_BASE_S #define USART10 USART10_S #define USART10_BASE USART10_BASE_S #define USB1_OTG_HS USB1_OTG_HS_S #define USB1_OTG_HS_BASE USB1_OTG_HS_BASE_S #define USB2_OTG_HS USB2_OTG_HS_S #define USB2_OTG_HS_BASE USB2_OTG_HS_BASE_S #define USB1_HS_PHYC USB1_HS_PHYC_S #define USB1_HS_PHYC_BASE USB1_HS_PHYC_BASE_S #define USB2_HS_PHYC USB2_HS_PHYC_S #define USB2_HS_PHYC_BASE USB2_HS_PHYC_BASE_S #define VENC VENC_S #define VENC_BASE VENC_BASE_S #define VREFBUF VREFBUF_S #define VREFBUF_BASE VREFBUF_BASE_S #define WWDG WWDG_S #define WWDG_BASE WWDG_BASE_S #define XSPI1 XSPI1_S #define XSPI2 XSPI2_S #define XSPI3 XSPI3_S #define XSPIM XSPIM_S #define XSPIM_BASE XSPIM_BASE_S /*!< Unique device ID register base address */ #define UID_BASE UID_BASE_S /*!< Revision ID base address */ #define REVID_BASE REVID_BASE_S #else #define ADC12_COMMON ADC12_COMMON_NS #define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS #define ADC1 ADC1_NS #define ADC1_BASE ADC1_BASE_NS #define ADC2 ADC2_NS #define ADC2_BASE ADC2_BASE_NS #define ADF1 ADF1_NS #define ADF1_BASE ADF1_BASE_NS #define ADF1_Filter0 ADF1_Filter0_NS #define ADF1_Filter0_BASE ADF1_Filter0_BASE_NS #define BSEC BSEC_NS #define BSEC_BASE BSEC_BASE_NS #define CACHEAXI CACHEAXI_NS #define CACHEAXI_BASE CACHEAXI_BASE_NS #define CRC CRC_NS #define CRC_BASE CRC_BASE_NS #define CRYP CRYP_NS #define CRYP_BASE CRYP_BASE_NS #define CSI CSI_NS #define CSI_BASE CSI_BASE_NS #define DBGMCU DBGMCU_NS #define DBGMCU_BASE DBGMCU_BASE_NS #define DCMI DCMI_NS #define DCMI_BASE DCMI_BASE_NS #define DCMIPP DCMIPP_NS #define DCMIPP_BASE DCMIPP_BASE_NS #define DLYB_SDMMC1 DLYB_SDMMC1_NS #define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS #define DLYB_SDMMC2 DLYB_SDMMC2_NS #define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_NS #define DMA2D DMA2D_NS #define DMA2D_BASE DMA2D_BASE_NS #define DTS DTS_NS #define DTS_BASE DTS_BASE_NS #define DTS_Sensor0 DTS_Sensor0_NS #define DTS_Sensor0_BASE DTS_Sensor0_BASE_NS #define DTS_Sensor1 DTS_Sensor1_NS #define DTS_Sensor1_BASE DTS_Sensor1_BASE_NS #define ETH1 ETH1_NS #define ETH1_BASE ETH1_BASE_NS #define EXTI EXTI_NS #define EXTI_BASE EXTI_BASE_NS #define FDCAN1 FDCAN1_NS #define FDCAN1_BASE FDCAN1_BASE_NS #define FDCAN2 FDCAN2_NS #define FDCAN2_BASE FDCAN2_BASE_NS #define FDCAN3 FDCAN3_NS #define FDCAN3_BASE FDCAN3_BASE_NS #define FDCAN_CCU FDCAN_CCU_NS #define FDCAN_CCU_BASE FDCAN_CCU_BASE_NS #define FDCAN_CONFIG FDCAN_CONFIG_NS #define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS #define FMC_R_BASE FMC_R_BASE_NS #define FMC_R_BASE_BASE FMC_R_BASE_BASE_NS #define FMC_Bank1E_R FMC_Bank1E_R_NS #define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_NS #define FMC_Bank1_R FMC_Bank1_R_NS #define FMC_Bank1_Rv FMC_Bank1_R_BASE_NS #define FMC_Bank3_R FMC_Bank3_R_NS #define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_NS #define FMC_Bank5_6_R FMC_Bank5_6_R_NS #define FMC_Bank5_6_R_BASE FMC_Bank5_6_R_BASE_NS #define FMC_Common_R FMC_Common_R_NS #define FMC_Common_R_BASE FMC_Common_R_BASE_NS #define GFXMMU GFXMMU_NS #define GFXMMU_BASE GFXMMU_BASE_NS #define GFXMMU_VIRTUAL_BUFFER0_BASE GFXMMU_VIRTUAL_BUFFER0_BASE_NS #define GFXMMU_VIRTUAL_BUFFER1_BASE GFXMMU_VIRTUAL_BUFFER1_BASE_NS #define GFXMMU_VIRTUAL_BUFFER2_BASE GFXMMU_VIRTUAL_BUFFER2_BASE_NS #define GFXMMU_VIRTUAL_BUFFER3_BASE GFXMMU_VIRTUAL_BUFFER3_BASE_NS #define GFXTIM GFXTIM_NS #define GFXTIM_BASE GFXTIM_BASE_NS #define GPDMA1 GPDMA1_NS #define GPDMA1_BASE GPDMA1_BASE_NS #define GPDMA1_Channel0 GPDMA1_Channel0_NS #define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS #define GPDMA1_Channel1 GPDMA1_Channel1_NS #define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS #define GPDMA1_Channel2 GPDMA1_Channel2_NS #define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS #define GPDMA1_Channel3 GPDMA1_Channel3_NS #define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS #define GPDMA1_Channel4 GPDMA1_Channel4_NS #define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS #define GPDMA1_Channel5 GPDMA1_Channel5_NS #define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS #define GPDMA1_Channel6 GPDMA1_Channel6_NS #define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS #define GPDMA1_Channel7 GPDMA1_Channel7_NS #define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS #define GPDMA1_Channel8 GPDMA1_Channel8_NS #define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_NS #define GPDMA1_Channel9 GPDMA1_Channel9_NS #define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_NS #define GPDMA1_Channel10 GPDMA1_Channel10_NS #define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_NS #define GPDMA1_Channel11 GPDMA1_Channel11_NS #define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_NS #define GPDMA1_Channel12 GPDMA1_Channel12_NS #define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_NS #define GPDMA1_Channel13 GPDMA1_Channel13_NS #define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_NS #define GPDMA1_Channel14 GPDMA1_Channel14_NS #define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_NS #define GPDMA1_Channel15 GPDMA1_Channel15_NS #define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_NS #define GPIOA GPIOA_NS #define GPIOA_BASE GPIOA_BASE_NS #define GPIOB GPIOB_NS #define GPIOB_BASE GPIOB_BASE_NS #define GPIOC GPIOC_NS #define GPIOC_BASE GPIOC_BASE_NS #define GPIOD GPIOD_NS #define GPIOD_BASE GPIOD_BASE_NS #define GPIOE GPIOE_NS #define GPIOE_BASE GPIOE_BASE_NS #define GPIOF GPIOF_NS #define GPIOF_BASE GPIOF_BASE_NS #define GPIOG GPIOG_NS #define GPIOG_BASE GPIOG_BASE_NS #define GPIOH GPIOH_NS #define GPIOH_BASE GPIOH_BASE_NS #define GPION GPION_NS #define GPION_BASE GPION_BASE_NS #define GPIOO GPIOO_NS #define GPIOO_BASE GPIOO_BASE_NS #define GPIOP GPIOP_NS #define GPIOP_BASE GPIOP_BASE_NS #define GPIOQ GPIOQ_NS #define GPIOQ_BASE GPIOQ_BASE_NS #define GPU2D GPU2D_BASE_NS #define GPU2D_BASE GPU2D_BASE_NS #define HASH HASH_NS #define HASH_BASE HASH_BASE_NS #define HASH_DIGEST HASH_DIGEST_NS #define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS #define HPDMA1 HPDMA1_NS #define HPDMA1_BASE HPDMA1_BASE_NS #define HPDMA1_Channel0 HPDMA1_Channel0_NS #define HPDMA1_Channel0_BASE HPDMA1_Channel0_BASE_NS #define HPDMA1_Channel1 HPDMA1_Channel1_NS #define HPDMA1_Channel1_BASE HPDMA1_Channel1_BASE_NS #define HPDMA1_Channel2 HPDMA1_Channel2_NS #define HPDMA1_Channel2_BASE HPDMA1_Channel2_BASE_NS #define HPDMA1_Channel3 HPDMA1_Channel3_NS #define HPDMA1_Channel3_BASE HPDMA1_Channel3_BASE_NS #define HPDMA1_Channel4 HPDMA1_Channel4_NS #define HPDMA1_Channel4_BASE HPDMA1_Channel4_BASE_NS #define HPDMA1_Channel5 HPDMA1_Channel5_NS #define HPDMA1_Channel5_BASE HPDMA1_Channel5_BASE_NS #define HPDMA1_Channel6 HPDMA1_Channel6_NS #define HPDMA1_Channel6_BASE HPDMA1_Channel6_BASE_NS #define HPDMA1_Channel7 HPDMA1_Channel7_NS #define HPDMA1_Channel7_BASE HPDMA1_Channel7_BASE_NS #define HPDMA1_Channel8 HPDMA1_Channel8_NS #define HPDMA1_Channel8_BASE HPDMA1_Channel8_BASE_NS #define HPDMA1_Channel9 HPDMA1_Channel9_NS #define HPDMA1_Channel9_BASE HPDMA1_Channel9_BASE_NS #define HPDMA1_Channel10 HPDMA1_Channel10_NS #define HPDMA1_Channel10_BASE HPDMA1_Channel10_BASE_NS #define HPDMA1_Channel11 HPDMA1_Channel11_NS #define HPDMA1_Channel11_BASE HPDMA1_Channel11_BASE_NS #define HPDMA1_Channel12 HPDMA1_Channel12_NS #define HPDMA1_Channel12_BASE HPDMA1_Channel12_BASE_NS #define HPDMA1_Channel13 HPDMA1_Channel13_NS #define HPDMA1_Channel13_BASE HPDMA1_Channel13_BASE_NS #define HPDMA1_Channel14 HPDMA1_Channel14_NS #define HPDMA1_Channel14_BASE HPDMA1_Channel14_BASE_NS #define HPDMA1_Channel15 HPDMA1_Channel15_NS #define HPDMA1_Channel15_BASE HPDMA1_Channel15_BASE_NS #define I2C1 I2C1_NS #define I2C1_BASE I2C1_BASE_NS #define I2C2 I2C2_NS #define I2C2_BASE I2C2_BASE_NS #define I2C3 I2C3_NS #define I2C3_BASE I2C3_BASE_NS #define I2C4 I2C4_NS #define I2C4_BASE I2C4_BASE_NS #define I3C1 I3C1_NS #define I3C1_BASE I3C1_BASE_NS #define I3C2 I3C2_NS #define I3C2_BASE I3C2_BASE_NS #define ICACHE ICACHE_NS #define ICACHE_BASE ICACHE_BASE_NS #define IWDG IWDG_NS #define IWDG_BASE IWDG_BASE_NS #define JPEG JPEG_NS #define JPEG_BASE JPEG_BASE_NS #define LPTIM1 LPTIM1_NS #define LPTIM1_BASE LPTIM1_BASE_NS #define LPTIM2 LPTIM2_NS #define LPTIM2_BASE LPTIM2_BASE_NS #define LPTIM3 LPTIM3_NS #define LPTIM3_BASE LPTIM3_BASE_NS #define LPTIM4 LPTIM4_NS #define LPTIM4_BASE LPTIM4_BASE_NS #define LPTIM5 LPTIM5_NS #define LPTIM5_BASE LPTIM5_BASE_NS #define LPUART1 LPUART1_NS #define LPUART1_BASE LPUART1_BASE_NS #define LTDC LTDC_NS #define LTDC_BASE LTDC_BASE_NS #define LTDC_Layer1 LTDC_Layer1_NS #define LTDC_Layer1_BASE LTDC_Layer1_BASE_NS #define LTDC_Layer2 LTDC_Layer2_NS #define LTDC_Layer2_BASE LTDC_Layer2_BASE_NS #define MCE1 MCE1_NS #define MCE1_BASE MCE1_BASE_NS #define MCE1_REGION1 MCE1_REGION1_NS #define MCE1_REGION1_BASE MCE1_REGION1_BASE_NS #define MCE1_REGION2 MCE1_REGION2_NS #define MCE1_REGION2_BASE MCE1_REGION2_BASE_NS #define MCE1_REGION3 MCE1_REGION3_NS #define MCE1_REGION3_BASE MCE1_REGION3_BASE_NS #define MCE1_REGION4 MCE1_REGION4_NS #define MCE1_REGION4_BASE MCE1_REGION4_BASE_NS #define MCE1_CONTEXT1 MCE1_CONTEXT1_NS #define MCE1_CONTEXT1_BASE MCE1_CONTEXT1_BASE_NS #define MCE1_CONTEXT2 MCE1_CONTEXT2_NS #define MCE1_CONTEXT2_BASE MCE1_CONTEXT2_BASE_NS #define MCE2 MCE2_NS #define MCE2_BASE MCE2_BASE_NS #define MCE2_REGION1 MCE2_REGION1_NS #define MCE2_REGION1_BASE MCE2_REGION1_BASE_NS #define MCE2_REGION2 MCE2_REGION2_NS #define MCE2_REGION2_BASE MCE2_REGION2_BASE_NS #define MCE2_REGION3 MCE2_REGION3_NS #define MCE2_REGION3_BASE MCE2_REGION3_BASE_NS #define MCE2_REGION4 MCE2_REGION4_NS #define MCE2_REGION4_BASE MCE2_REGION4_BASE_NS #define MCE2_CONTEXT1 MCE2_CONTEXT1_NS #define MCE2_CONTEXT1_BASE MCE2_CONTEXT1_BASE_NS #define MCE2_CONTEXT2 MCE2_CONTEXT2_NS #define MCE2_CONTEXT2_BASE MCE2_CONTEXT2_BASE_NS #define MCE3 MCE3_NS #define MCE3_BASE MCE3_BASE_NS #define MCE3_REGION1 MCE3_REGION1_NS #define MCE3_REGION1_BASE MCE3_REGION1_BASE_NS #define MCE3_REGION2 MCE3_REGION2_NS #define MCE3_REGION2_BASE MCE3_REGION2_BASE_NS #define MCE3_REGION3 MCE3_REGION3_NS #define MCE3_REGION3_BASE MCE3_REGION3_BASE_NS #define MCE3_REGION4 MCE3_REGION4_NS #define MCE3_REGION4_BASE MCE3_REGION4_BASE_NS #define MCE3_CONTEXT1 MCE3_CONTEXT1_NS #define MCE3_CONTEXT1_BASE MCE3_CONTEXT1_BASE_NS #define MCE3_CONTEXT2 MCE3_CONTEXT2_NS #define MCE3_CONTEXT2_BASE MCE3_CONTEXT2_BASE_NS #define MCE4 MCE4_NS #define MCE4_BASE MCE4_BASE_NS #define MCE4_REGION1 MCE4_REGION1_NS #define MCE4_REGION1_BASE MCE4_REGION1_BASE_NS #define MCE4_REGION2 MCE4_REGION2_NS #define MCE4_REGION2_BASE MCE4_REGION2_BASE_NS #define MCE4_REGION3 MCE4_REGION3_NS #define MCE4_REGION3_BASE MCE4_REGION3_BASE_NS #define MCE4_REGION4 MCE4_REGION4_NS #define MCE4_REGION4_BASE MCE4_REGION4_BASE_NS #define MCE4_CONTEXT1 MCE4_CONTEXT1_NS #define MCE4_CONTEXT1_BASE MCE4_CONTEXT1_BASE_NS #define MCE4_CONTEXT2 MCE4_CONTEXT2_NS #define MCE4_CONTEXT2_BASE MCE4_CONTEXT2_BASE_NS #define MDF1 MDF1_NS #define MDF1_BASE MDF1_BASE_NS #define MDF1_Filter0 MDF1_Filter0_NS #define MDF1_Filter0_BASE MDF1_Filter0_BASE_NS #define MDF1_Filter1 MDF1_Filter1_NS #define MDF1_Filter1_BASE MDF1_Filter1_BASE_NS #define MDF1_Filter2 MDF1_Filter2_NS #define MDF1_Filter2_BASE MDF1_Filter2_BASE_NS #define MDF1_Filter3 MDF1_Filter3_NS #define MDF1_Filter3_BASE MDF1_Filter3_BASE_NS #define MDF1_Filter4 MDF1_Filter4_NS #define MDF1_Filter4_BASE MDF1_Filter4_BASE_NS #define MDF1_Filter5 MDF1_Filter5_NS #define MDF1_Filter5_BASE MDF1_Filter5_BASE_NS #define MDIOS MDIOS_NS #define MDIOS_BASE MDIOS_BASE_NS #define NPU_PRESENT #define NPU_BASE NPU_BASE_NS #define PKA PKA_NS #define PKA_BASE PKA_BASE_NS #define PSSI PSSI_NS #define PSSI_BASE PSSI_BASE_NS #define PWR PWR_NS #define PWR_BASE PWR_BASE_NS #define RAMCFG RAMCFG_NS #define RAMCFG_BASE RAMCFG_BASE_NS #define RAMCFG_SRAM1_AXI RAMCFG_SRAM1_AXI_NS #define RAMCFG_SRAM1_AXI_BASE RAMCFG_SRAM1_AXI_BASE_NS #define RAMCFG_SRAM2_AXI RAMCFG_SRAM2_AXI_NS #define RAMCFG_SRAM2_AXI_BASE RAMCFG_SRAM2_AXI_BASE_NS #define RAMCFG_SRAM3_AXI RAMCFG_SRAM3_AXI_NS #define RAMCFG_SRAM3_AXI_BASE RAMCFG_SRAM3_AXI_BASE_NS #define RAMCFG_SRAM4_AXI RAMCFG_SRAM4_AXI_NS #define RAMCFG_SRAM4_AXI_BASE RAMCFG_SRAM4_AXI_BASE_NS #define RAMCFG_SRAM5_AXI RAMCFG_SRAM5_AXI_NS #define RAMCFG_SRAM5_AXI_BASE RAMCFG_SRAM5_AXI_BASE_NS #define RAMCFG_SRAM6_AXI RAMCFG_SRAM6_AXI_NS #define RAMCFG_SRAM6_AXI_BASE RAMCFG_SRAM6_AXI_BASE_NS #define RAMCFG_SRAM1_AHB RAMCFG_SRAM1_AHB_NS #define RAMCFG_SRAM1_AHB_BASE RAMCFG_SRAM1_AHB_BASE_NS #define RAMCFG_SRAM2_AHB RAMCFG_SRAM2_AHB_NS #define RAMCFG_SRAM2_AHB_BASE RAMCFG_SRAM2_AHB_BASE_NS #define RAMCFG_VENC_RAM RAMCFG_VENC_RAM_NS #define RAMCFG_VENC_RAM_BASE RAMCFG_VENC_RAM_BASE_NS #define RAMCFG_BKPSRAM RAMCFG_BKPSRAM_NS #define RAMCFG_BKPSRAM_BASE RAMCFG_BKPSRAM_BASE_NS #define RAMCFG_FLEXRAM RAMCFG_FLEXRAM_NS #define RAMCFG_FLEXRAM_BASE RAMCFG_FLEXRAM_BASE_NS #define RCC RCC_NS #define RCC_BASE RCC_BASE_NS #define RIFSC RIFSC_NS #define RIFSC_BASE RIFSC_BASE_NS #define RISAF1 RISAF1_NS #define RISAF1_BASE RISAF1_BASE_NS #define RISAF2 RISAF2_NS #define RISAF2_BASE RISAF2_BASE_NS #define RISAF3 RISAF3_NS #define RISAF3_BASE RISAF3_BASE_NS #define RISAF4 RISAF4_NS #define RISAF4_BASE RISAF4_BASE_NS #define RISAF5 RISAF5_NS #define RISAF5_BASE RISAF5_BASE_NS #define RISAF6 RISAF6_NS #define RISAF6_BASE RISAF6_BASE_NS #define RISAF7 RISAF7_NS #define RISAF7_BASE RISAF7_BASE_NS #define RISAF8 RISAF8_NS #define RISAF8_BASE RISAF8_BASE_NS #define RISAF9 RISAF9_NS #define RISAF9_BASE RISAF9_BASE_NS #define RISAF11 RISAF11_NS #define RISAF11_BASE RISAF11_BASE_NS #define RISAF12 RISAF12_NS #define RISAF12_BASE RISAF12_BASE_NS #define RISAF13 RISAF13_NS #define RISAF13_BASE RISAF13_BASE_NS #define RISAF14 RISAF14_NS #define RISAF14_BASE RISAF14_BASE_NS #define RISAF15 RISAF15_NS #define RISAF15_BASE RISAF15_BASE_NS #define RISAF21 RISAF21_NS #define RISAF21_BASE RISAF21_BASE_NS #define RISAF22 RISAF22_NS #define RISAF22_BASE RISAF22_BASE_NS #define RISAF23 RISAF23_NS #define RISAF23_BASE RISAF23_BASE_NS #define RNG RNG_NS #define RNG_BASE RNG_BASE_NS #define RTC RTC_NS #define RTC_BASE RTC_BASE_NS #define SAES SAES_NS #define SAES_BASE SAES_BASE_NS #define SAI1 SAI1_NS #define SAI1_BASE SAI1_BASE_NS #define SAI1_Block_A SAI1_Block_A_NS #define SAI1_Block_A_BASE SAI1_Block_A_BASE_NS #define SAI1_Block_B SAI1_Block_B_NS #define SAI1_Block_B_BASE SAI1_Block_B_BASE_NS #define SAI2 SAI2_NS #define SAI2_BASE SAI2_BASE_NS #define SAI2_Block_A SAI2_Block_A_NS #define SAI2_Block_A_BASE SAI2_Block_A_BASE_NS #define SAI2_Block_B SAI2_Block_B_NS #define SAI2_Block_B_BASE SAI2_Block_B_BASE_NS #define SDMMC1 SDMMC1_NS #define SDMMC1_BASE SDMMC1_BASE_NS #define SDMMC2 SDMMC2_NS #define SDMMC2_BASE SDMMC2_BASE_NS #define SPDIFRX SPDIFRX_NS #define SPDIFRX_BASE SPDIFRX_BASE_NS #define SPI1 SPI1_NS #define SPI1_BASE SPI1_BASE_NS #define SPI2 SPI2_NS #define SPI2_BASE SPI2_BASE_NS #define SPI3 SPI3_NS #define SPI3_BASE SPI3_BASE_NS #define SPI4 SPI4_NS #define SPI4_BASE SPI4_BASE_NS #define SPI5 SPI5_NS #define SPI5_BASE SPI5_BASE_NS #define SPI6 SPI6_NS #define SPI6_BASE SPI6_BASE_NS #define SRAMCAN_BASE SRAMCAN_BASE_NS #define SYSCFG SYSCFG_NS #define SYSCFG_BASE SYSCFG_BASE_NS #define TAMP TAMP_NS #define TAMP_BASE TAMP_BASE_NS #define TIM1 TIM1_NS #define TIM1_BASE TIM1_BASE_NS #define TIM2 TIM2_NS #define TIM2_BASE TIM2_BASE_NS #define TIM3 TIM3_NS #define TIM3_BASE TIM3_BASE_NS #define TIM4 TIM4_NS #define TIM4_BASE TIM4_BASE_NS #define TIM5 TIM5_NS #define TIM5_BASE TIM5_BASE_NS #define TIM6 TIM6_NS #define TIM6_BASE TIM6_BASE_NS #define TIM7 TIM7_NS #define TIM7_BASE TIM7_BASE_NS #define TIM8 TIM8_NS #define TIM8_BASE TIM8_BASE_NS #define TIM9 TIM9_NS #define TIM9_BASE TIM9_BASE_NS #define TIM10 TIM10_NS #define TIM10_BASE TIM10_BASE_NS #define TIM11 TIM11_NS #define TIM11_BASE TIM11_BASE_NS #define TIM12 TIM12_NS #define TIM12_BASE TIM12_BASE_NS #define TIM13 TIM13_NS #define TIM13_BASE TIM13_BASE_NS #define TIM14 TIM14_NS #define TIM14_BASE TIM14_BASE_NS #define TIM15 TIM15_NS #define TIM15_BASE TIM15_BASE_NS #define TIM16 TIM16_NS #define TIM16_BASE TIM16_BASE_NS #define TIM17 TIM17_NS #define TIM17_BASE TIM17_BASE_NS #define TIM18 TIM18_NS #define TIM18_BASE TIM18_BASE_NS #define UART4 UART4_NS #define UART4_BASE UART4_BASE_NS #define UART5 UART5_NS #define UART5_BASE UART5_BASE_NS #define UART7 UART7_NS #define UART7_BASE UART7_BASE_NS #define UART8 UART8_NS #define UART8_BASE UART8_BASE_NS #define UART9 UART9_NS #define UART9_BASE UART9_BASE_NS #define UCPD1 UCPD1_NS #define UCPD1_BASE UCPD1_BASE_NS #define USART1 USART1_NS #define USART1_BASE USART1_BASE_NS #define USART2 USART2_NS #define USART2_BASE USART2_BASE_NS #define USART3 USART3_NS #define USART3_BASE USART3_BASE_NS #define USART6 USART6_NS #define USART6_BASE USART6_BASE_NS #define USART10 USART10_NS #define USART10_BASE USART10_BASE_NS #define USB1_OTG_HS USB1_OTG_HS_NS #define USB1_OTG_HS_BASE USB1_OTG_HS_BASE_NS #define USB2_OTG_HS USB2_OTG_HS_NS #define USB2_OTG_HS_BASE USB2_OTG_HS_BASE_NS #define USB1_HS_PHYC USB1_HS_PHYC_NS #define USB1_HS_PHYC_BASE USB1_HS_PHYC_BASE_NS #define USB2_HS_PHYC USB2_HS_PHYC_NS #define USB2_HS_PHYC_BASE USB2_HS_PHYC_BASE_NS #define VENC VENC_NS #define VENC_BASE VENC_BASE_NS #define VREFBUF VREFBUF_NS #define VREFBUF_BASE VREFBUF_BASE_NS #define WWDG WWDG_NS #define WWDG_BASE WWDG_BASE_NS #define XSPI1 XSPI1_NS #define XSPI2 XSPI2_NS #define XSPI3 XSPI3_NS #define XSPIM XSPIM_NS #define XSPIM_BASE XSPIM_BASE_NS /*!< Unique device ID register base address */ #define UID_BASE UID_BASE_NS /*!< Revision ID base address */ #define REVID_BASE REVID_BASE_NS #endif /** @} */ /* End of group STM32N6xx_Peripheral_declaration */ /** @addtogroup STM32N6xx_Peripheral_Timing_Definition * @{ */ #define LSI_STARTUP_TIME 16000U /*!< LSI Maximum startup time in us : 4 cycles @ 250 Hz = 16 ms */ /** @} */ /* End of group STM32N6xx_Peripheral_Timing_Definition */ /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ /******************************************************************************/ /* */ /* Analog to Digital Converter (ADC) */ /* */ /******************************************************************************/ /* Specific device feature definitions */ #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ /******************** Bit definition for ADC_ISR register *******************/ #define ADC_ISR_ADRDY_Pos (0U) #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ #define ADC_ISR_EOSMP_Pos (1U) #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ #define ADC_ISR_EOC_Pos (2U) #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ #define ADC_ISR_EOS_Pos (3U) #define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ #define ADC_ISR_OVR_Pos (4U) #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ #define ADC_ISR_JEOC_Pos (5U) #define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ #define ADC_ISR_JEOS_Pos (6U) #define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ #define ADC_ISR_AWD1_Pos (7U) #define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ #define ADC_ISR_AWD2_Pos (8U) #define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ #define ADC_ISR_AWD3_Pos (9U) #define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ /******************** Bit definition for ADC_IER register *******************/ #define ADC_IER_ADRDYIE_Pos (0U) #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ #define ADC_IER_EOSMPIE_Pos (1U) #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ #define ADC_IER_EOCIE_Pos (2U) #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ #define ADC_IER_EOSIE_Pos (3U) #define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ #define ADC_IER_OVRIE_Pos (4U) #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ #define ADC_IER_JEOCIE_Pos (5U) #define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ #define ADC_IER_JEOSIE_Pos (6U) #define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ #define ADC_IER_AWD1IE_Pos (7U) #define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ #define ADC_IER_AWD2IE_Pos (8U) #define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ #define ADC_IER_AWD3IE_Pos (9U) #define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ /******************** Bit definition for ADC_CR register ********************/ #define ADC_CR_ADEN_Pos (0U) #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ #define ADC_CR_ADDIS_Pos (1U) #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ #define ADC_CR_ADSTART_Pos (2U) #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ #define ADC_CR_JADSTART_Pos (3U) #define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ #define ADC_CR_ADSTP_Pos (4U) #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ #define ADC_CR_JADSTP_Pos (5U) #define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ #define ADC_CR_DEEPPWD_Pos (29U) #define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ #define ADC_CR_ADCALDIF_Pos (30U) #define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ #define ADC_CR_ADCAL_Pos (31U) #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ /******************** Bit definition for ADC_CFGR1 register ******************/ #define ADC_CFGR1_DMNGT_Pos (0U) #define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ #define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< ADC data management configuration */ #define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ #define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ #define ADC_CFGR1_RES_Pos (2U) #define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ #define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ #define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ #define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ #define ADC_CFGR1_EXTSEL_Pos (5U) #define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ #define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ #define ADC_CFGR1_EXTSEL_0 (0x01UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ #define ADC_CFGR1_EXTSEL_1 (0x02UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ #define ADC_CFGR1_EXTSEL_2 (0x04UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ #define ADC_CFGR1_EXTSEL_3 (0x08UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ #define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ #define ADC_CFGR1_EXTEN_Pos (10U) #define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ #define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ #define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ #define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ #define ADC_CFGR1_OVRMOD_Pos (12U) #define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ #define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ #define ADC_CFGR1_CONT_Pos (13U) #define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ #define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ #define ADC_CFGR1_AUTDLY_Pos (14U) #define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ #define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< ADC low power auto wait */ #define ADC_CFGR1_DISCEN_Pos (16U) #define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ #define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ #define ADC_CFGR1_DISCNUM_Pos (17U) #define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ #define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ #define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ #define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ #define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ #define ADC_CFGR1_JDISCEN_Pos (20U) #define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ #define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ #define ADC_CFGR1_AWD1SGL_Pos (22U) #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ #define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ #define ADC_CFGR1_AWD1EN_Pos (23U) #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ #define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ #define ADC_CFGR1_JAWD1EN_Pos (24U) #define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ #define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ #define ADC_CFGR1_JAUTO_Pos (25U) #define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ #define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ #define ADC_CFGR1_AWD1CH_Pos (26U) #define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ #define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ #define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ #define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ #define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ #define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ #define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ /******************** Bit definition for ADC_CFGR2 register *****************/ #define ADC_CFGR2_ROVSE_Pos (0U) #define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ #define ADC_CFGR2_JOVSE_Pos (1U) #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ #define ADC_CFGR2_OVSS_Pos (5U) #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ #define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ #define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ #define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ #define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ #define ADC_CFGR2_TROVS_Pos (9U) #define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ #define ADC_CFGR2_ROVSM_Pos (10U) #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ #define ADC_CFGR2_BULB_Pos (13U) #define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ #define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC bulb sampling mode */ #define ADC_CFGR2_SWTRIG_Pos (14U) #define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ #define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC software trigger bit for sampling time control trigger mode */ #define ADC_CFGR2_SMPTRIG_Pos (15U) #define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ #define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC sampling time control trigger mode */ #define ADC_CFGR2_OVSR_Pos (16U) #define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ #define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ #define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ #define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ #define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ #define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ #define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ #define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ #define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ #define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ #define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ #define ADC_CFGR2_LSHIFT_Pos (28U) #define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ #define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC left shift factor */ #define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ #define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ #define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ #define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_SMPR1 register *****************/ #define ADC_SMPR1_SMP0_Pos (0U) #define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ #define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ #define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ #define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ #define ADC_SMPR1_SMP1_Pos (3U) #define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ #define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ #define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ #define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ #define ADC_SMPR1_SMP2_Pos (6U) #define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ #define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ #define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ #define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ #define ADC_SMPR1_SMP3_Pos (9U) #define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ #define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ #define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ #define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ #define ADC_SMPR1_SMP4_Pos (12U) #define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ #define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ #define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ #define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ #define ADC_SMPR1_SMP5_Pos (15U) #define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ #define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ #define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ #define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ #define ADC_SMPR1_SMP6_Pos (18U) #define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ #define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ #define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ #define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ #define ADC_SMPR1_SMP7_Pos (21U) #define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ #define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ #define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ #define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ #define ADC_SMPR1_SMP8_Pos (24U) #define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ #define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ #define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ #define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ #define ADC_SMPR1_SMP9_Pos (27U) #define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ #define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ #define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ #define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ /******************** Bit definition for ADC_SMPR2 register *****************/ #define ADC_SMPR2_SMP10_Pos (0U) #define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ #define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ #define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ #define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ #define ADC_SMPR2_SMP11_Pos (3U) #define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ #define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ #define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ #define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ #define ADC_SMPR2_SMP12_Pos (6U) #define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ #define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ #define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ #define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ #define ADC_SMPR2_SMP13_Pos (9U) #define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ #define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ #define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ #define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ #define ADC_SMPR2_SMP14_Pos (12U) #define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ #define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ #define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ #define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ #define ADC_SMPR2_SMP15_Pos (15U) #define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ #define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ #define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ #define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ #define ADC_SMPR2_SMP16_Pos (18U) #define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ #define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ #define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ #define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ #define ADC_SMPR2_SMP17_Pos (21U) #define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ #define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ #define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ #define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ #define ADC_SMPR2_SMP18_Pos (24U) #define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ #define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ #define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ #define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ #define ADC_SMPR2_SMP19_Pos (27U) #define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ #define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ #define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ #define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ #define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ /******************** Bit definition for ADC_PCSEL register *****************/ #define ADC_PCSEL_PCSEL_Pos (0U) #define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ #define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC channel preselection */ #define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ #define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ #define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ #define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ #define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ #define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ #define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ #define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ #define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ #define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ #define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ #define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ #define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ #define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ #define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ #define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ #define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ #define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ #define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ #define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ /******************** Bit definition for ADC_SQR1 register ******************/ #define ADC_SQR1_L_Pos (0U) #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ #define ADC_SQR1_SQ1_Pos (6U) #define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ #define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ #define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ #define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ #define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ #define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ #define ADC_SQR1_SQ2_Pos (12U) #define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ #define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ #define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ #define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ #define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ #define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ #define ADC_SQR1_SQ3_Pos (18U) #define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ #define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ #define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ #define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ #define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ #define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ #define ADC_SQR1_SQ4_Pos (24U) #define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ #define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ #define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ #define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ #define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ #define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR2 register ******************/ #define ADC_SQR2_SQ5_Pos (0U) #define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ #define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ #define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ #define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ #define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ #define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ #define ADC_SQR2_SQ6_Pos (6U) #define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ #define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ #define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ #define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ #define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ #define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ #define ADC_SQR2_SQ7_Pos (12U) #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ #define ADC_SQR2_SQ8_Pos (18U) #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ #define ADC_SQR2_SQ9_Pos (24U) #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR3 register ******************/ #define ADC_SQR3_SQ10_Pos (0U) #define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ #define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ #define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ #define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ #define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ #define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ #define ADC_SQR3_SQ11_Pos (6U) #define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ #define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ #define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ #define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ #define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ #define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ #define ADC_SQR3_SQ12_Pos (12U) #define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ #define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ #define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ #define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ #define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ #define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ #define ADC_SQR3_SQ13_Pos (18U) #define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ #define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ #define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ #define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ #define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ #define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ #define ADC_SQR3_SQ14_Pos (24U) #define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ #define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ #define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ #define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ #define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ #define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR4 register ******************/ #define ADC_SQR4_SQ15_Pos (0U) #define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ #define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ #define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ #define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ #define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ #define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ #define ADC_SQR4_SQ16_Pos (6U) #define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ #define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ #define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ #define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ #define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ #define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_RDATA_Pos (0U) #define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ #define ADC_DR_RDATA_0 (0x00000001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ #define ADC_DR_RDATA_1 (0x00000002UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ #define ADC_DR_RDATA_2 (0x00000004UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ #define ADC_DR_RDATA_3 (0x00000008UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ #define ADC_DR_RDATA_4 (0x00000010UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ #define ADC_DR_RDATA_5 (0x00000020UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ #define ADC_DR_RDATA_6 (0x00000040UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ #define ADC_DR_RDATA_7 (0x00000080UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ #define ADC_DR_RDATA_8 (0x00000100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ #define ADC_DR_RDATA_9 (0x00000200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ #define ADC_DR_RDATA_10 (0x00000400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ #define ADC_DR_RDATA_11 (0x00000800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ #define ADC_DR_RDATA_12 (0x00001000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ #define ADC_DR_RDATA_13 (0x00002000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ #define ADC_DR_RDATA_14 (0x00004000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ #define ADC_DR_RDATA_15 (0x00008000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ #define ADC_DR_RDATA_16 (0x00010000UL << ADC_DR_RDATA_Pos) /*!< 0x00010000 */ #define ADC_DR_RDATA_17 (0x00020000UL << ADC_DR_RDATA_Pos) /*!< 0x00020000 */ #define ADC_DR_RDATA_18 (0x00040000UL << ADC_DR_RDATA_Pos) /*!< 0x00040000 */ #define ADC_DR_RDATA_19 (0x00080000UL << ADC_DR_RDATA_Pos) /*!< 0x00080000 */ #define ADC_DR_RDATA_20 (0x00100000UL << ADC_DR_RDATA_Pos) /*!< 0x00100000 */ #define ADC_DR_RDATA_21 (0x00200000UL << ADC_DR_RDATA_Pos) /*!< 0x00200000 */ #define ADC_DR_RDATA_22 (0x00400000UL << ADC_DR_RDATA_Pos) /*!< 0x00400000 */ #define ADC_DR_RDATA_23 (0x00800000UL << ADC_DR_RDATA_Pos) /*!< 0x00800000 */ #define ADC_DR_RDATA_24 (0x01000000UL << ADC_DR_RDATA_Pos) /*!< 0x01000000 */ #define ADC_DR_RDATA_25 (0x02000000UL << ADC_DR_RDATA_Pos) /*!< 0x02000000 */ #define ADC_DR_RDATA_26 (0x04000000UL << ADC_DR_RDATA_Pos) /*!< 0x04000000 */ #define ADC_DR_RDATA_27 (0x08000000UL << ADC_DR_RDATA_Pos) /*!< 0x08000000 */ #define ADC_DR_RDATA_28 (0x10000000UL << ADC_DR_RDATA_Pos) /*!< 0x10000000 */ #define ADC_DR_RDATA_29 (0x20000000UL << ADC_DR_RDATA_Pos) /*!< 0x20000000 */ #define ADC_DR_RDATA_30 (0x40000000UL << ADC_DR_RDATA_Pos) /*!< 0x40000000 */ #define ADC_DR_RDATA_31 (0x80000000UL << ADC_DR_RDATA_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_JSQR register ******************/ #define ADC_JSQR_JL_Pos (0U) #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ #define ADC_JSQR_JEXTSEL_Pos (2U) #define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ #define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ #define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ #define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ #define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ #define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ #define ADC_JSQR_JEXTEN_Pos (7U) #define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ #define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ #define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ #define ADC_JSQR_JSQ1_Pos (9U) #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ #define ADC_JSQR_JSQ2_Pos (15U) #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ #define ADC_JSQR_JSQ3_Pos (21U) #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ #define ADC_JSQR_JSQ4_Pos (27U) #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_OFCFGR1 register ***************/ #define ADC_OFCFGR1_POSOFF_Pos (24U) #define ADC_OFCFGR1_POSOFF_Msk (0x01UL << ADC_OFCFGR1_POSOFF_Pos) /*!< 0x01000000 */ #define ADC_OFCFGR1_POSOFF ADC_OFCFGR1_POSOFF_Msk /*!< ADC offset instance 1 positive offset enable */ #define ADC_OFCFGR1_USAT_Pos (25U) #define ADC_OFCFGR1_USAT_Msk (0x01UL << ADC_OFCFGR1_USAT_Pos) /*!< 0x02000000 */ #define ADC_OFCFGR1_USAT ADC_OFCFGR1_USAT_Msk /*!< ADC offset instance 1 unsigned saturation value */ #define ADC_OFCFGR1_SSAT_Pos (26U) #define ADC_OFCFGR1_SSAT_Msk (0x01UL << ADC_OFCFGR1_SSAT_Pos) /*!< 0x04000000 */ #define ADC_OFCFGR1_SSAT ADC_OFCFGR1_SSAT_Msk /*!< ADC offset instance 1 signed satuaration enable */ #define ADC_OFCFGR1_OFFSET_CH_Pos (27U) #define ADC_OFCFGR1_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0xF8000000 */ #define ADC_OFCFGR1_OFFSET_CH ADC_OFCFGR1_OFFSET_CH_Msk /*!< ADC offset instance 1 channel selection */ #define ADC_OFCFGR1_OFFSET_CH_0 (0x01UL << ADC_OFCFGR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ #define ADC_OFCFGR1_OFFSET_CH_1 (0x02UL << ADC_OFCFGR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ #define ADC_OFCFGR1_OFFSET_CH_2 (0x03UL << ADC_OFCFGR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ #define ADC_OFCFGR1_OFFSET_CH_3 (0x04UL << ADC_OFCFGR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ #define ADC_OFCFGR1_OFFSET_CH_4 (0x05UL << ADC_OFCFGR1_OFFSET1_CH_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_OFCFGR2 register ***************/ #define ADC_OFCFGR2_POSOFF_Pos (24U) #define ADC_OFCFGR2_POSOFF_Msk (0x01UL << ADC_OFCFGR2_POSOFF_Pos) /*!< 0x01000000 */ #define ADC_OFCFGR2_POSOFF ADC_OFCFGR2_POSOFF_Msk /*!< ADC offset instance 2 positive offset enable */ #define ADC_OFCFGR2_USAT_Pos (25U) #define ADC_OFCFGR2_USAT_Msk (0x01UL << ADC_OFCFGR2_USAT_Pos) /*!< 0x02000000 */ #define ADC_OFCFGR2_USAT ADC_OFCFGR2_USAT_Msk /*!< ADC offset instance 2 unsigned saturation value */ #define ADC_OFCFGR2_SSAT_Pos (26U) #define ADC_OFCFGR2_SSAT_Msk (0x01UL << ADC_OFCFGR2_SSAT_Pos) /*!< 0x04000000 */ #define ADC_OFCFGR2_SSAT ADC_OFCFGR2_SSAT_Msk /*!< ADC offset instance 2 signed satuaration enable */ #define ADC_OFCFGR2_OFFSET_CH_Pos (27U) #define ADC_OFCFGR2_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0xF8000000 */ #define ADC_OFCFGR2_OFFSET_CH ADC_OFCFGR2_OFFSET_CH_Msk /*!< ADC offset instance 2 channel selection */ #define ADC_OFCFGR2_OFFSET_CH_0 (0x01UL << ADC_OFCFGR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ #define ADC_OFCFGR2_OFFSET_CH_1 (0x02UL << ADC_OFCFGR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ #define ADC_OFCFGR2_OFFSET_CH_2 (0x03UL << ADC_OFCFGR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ #define ADC_OFCFGR2_OFFSET_CH_3 (0x04UL << ADC_OFCFGR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ #define ADC_OFCFGR2_OFFSET_CH_4 (0x05UL << ADC_OFCFGR2_OFFSET1_CH_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_OFCFGR3 register ***************/ #define ADC_OFCFGR3_POSOFF_Pos (24U) #define ADC_OFCFGR3_POSOFF_Msk (0x01UL << ADC_OFCFGR3_POSOFF_Pos) /*!< 0x01000000 */ #define ADC_OFCFGR3_POSOFF ADC_OFCFGR3_POSOFF_Msk /*!< ADC offset instance 3 positive offset enable */ #define ADC_OFCFGR3_USAT_Pos (25U) #define ADC_OFCFGR3_USAT_Msk (0x01UL << ADC_OFCFGR3_USAT_Pos) /*!< 0x02000000 */ #define ADC_OFCFGR3_USAT ADC_OFCFGR3_USAT_Msk /*!< ADC offset instance 3 unsigned saturation value */ #define ADC_OFCFGR3_SSAT_Pos (26U) #define ADC_OFCFGR3_SSAT_Msk (0x01UL << ADC_OFCFGR3_SSAT_Pos) /*!< 0x04000000 */ #define ADC_OFCFGR3_SSAT ADC_OFCFGR3_SSAT_Msk /*!< ADC offset instance 3 signed satuaration enable */ #define ADC_OFCFGR3_OFFSET_CH_Pos (27U) #define ADC_OFCFGR3_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0xF8000000 */ #define ADC_OFCFGR3_OFFSET_CH ADC_OFCFGR3_OFFSET_CH_Msk /*!< ADC offset instance 3 channel selection for the data offset */ #define ADC_OFCFGR3_OFFSET_CH_0 (0x01UL << ADC_OFCFGR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ #define ADC_OFCFGR3_OFFSET_CH_1 (0x02UL << ADC_OFCFGR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ #define ADC_OFCFGR3_OFFSET_CH_2 (0x03UL << ADC_OFCFGR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ #define ADC_OFCFGR3_OFFSET_CH_3 (0x04UL << ADC_OFCFGR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ #define ADC_OFCFGR3_OFFSET_CH_4 (0x05UL << ADC_OFCFGR3_OFFSET3_CH_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_OFCFGR4 register ***************/ #define ADC_OFCFGR4_POSOFF_Pos (24U) #define ADC_OFCFGR4_POSOFF_Msk (0x01UL << ADC_OFCFGR4_POSOFF_Pos) /*!< 0x01000000 */ #define ADC_OFCFGR4_POSOFF ADC_OFCFGR4_POSOFF_Msk /*!< ADC offset instance 4 positive offset enable */ #define ADC_OFCFGR4_USAT_Pos (25U) #define ADC_OFCFGR4_USAT_Msk (0x01UL << ADC_OFCFGR4_USAT_Pos) /*!< 0x02000000 */ #define ADC_OFCFGR4_USAT ADC_OFCFGR4_USAT_Msk /*!< ADC offset instance 4 unsigned saturation value */ #define ADC_OFCFGR4_SSAT_Pos (26U) #define ADC_OFCFGR4_SSAT_Msk (0x01UL << ADC_OFCFGR4_SSAT_Pos) /*!< 0x04000000 */ #define ADC_OFCFGR4_SSAT ADC_OFCFGR4_SSAT_Msk /*!< ADC offset instance 4 signed satuaration enable */ #define ADC_OFCFGR4_OFFSET_CH_Pos (27U) #define ADC_OFCFGR4_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0xF8000000 */ #define ADC_OFCFGR4_OFFSET_CH ADC_OFCFGR4_OFFSET_CH_Msk /*!< ADC offset instance 4 channel selection for the data offset */ #define ADC_OFCFGR4_OFFSET_CH_0 (0x01UL << ADC_OFCFGR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ #define ADC_OFCFGR4_OFFSET_CH_1 (0x02UL << ADC_OFCFGR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ #define ADC_OFCFGR4_OFFSET_CH_2 (0x03UL << ADC_OFCFGR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ #define ADC_OFCFGR4_OFFSET_CH_3 (0x04UL << ADC_OFCFGR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ #define ADC_OFCFGR4_OFFSET_CH_4 (0x05UL << ADC_OFCFGR4_OFFSET4_CH_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_OFR1 register ******************/ #define ADC_OFR1_OFFSET_Pos (0U) #define ADC_OFR1_OFFSET_Msk (0x03FFFFFUL << ADC_OFR1_OFFSET_Pos) /*!< 0x003FFFFF */ #define ADC_OFR1_OFFSET ADC_OFR1_OFFSET_Msk /*!< ADC offset instance 1 offset level */ #define ADC_OFR1_OFFSET_0 (0x0000001UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000001 */ #define ADC_OFR1_OFFSET_1 (0x0000002UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000002 */ #define ADC_OFR1_OFFSET_2 (0x0000004UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000004 */ #define ADC_OFR1_OFFSET_3 (0x0000008UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000008 */ #define ADC_OFR1_OFFSET_4 (0x0000010UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000010 */ #define ADC_OFR1_OFFSET_5 (0x0000020UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000020 */ #define ADC_OFR1_OFFSET_6 (0x0000040UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000040 */ #define ADC_OFR1_OFFSET_7 (0x0000080UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000080 */ #define ADC_OFR1_OFFSET_8 (0x0000100UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000100 */ #define ADC_OFR1_OFFSET_9 (0x0000200UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000200 */ #define ADC_OFR1_OFFSET_10 (0x0000400UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000400 */ #define ADC_OFR1_OFFSET_11 (0x0000800UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000800 */ #define ADC_OFR1_OFFSET_12 (0x0001000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00001000 */ #define ADC_OFR1_OFFSET_13 (0x0002000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00002000 */ #define ADC_OFR1_OFFSET_14 (0x0004000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00004000 */ #define ADC_OFR1_OFFSET_15 (0x0008000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00008000 */ #define ADC_OFR1_OFFSET_16 (0x0010000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00010000 */ #define ADC_OFR1_OFFSET_17 (0x0020000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00020000 */ #define ADC_OFR1_OFFSET_18 (0x0040000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00040000 */ #define ADC_OFR1_OFFSET_19 (0x0080000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00080000 */ #define ADC_OFR1_OFFSET_20 (0x0100000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00100000 */ #define ADC_OFR1_OFFSET_21 (0x0200000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00200000 */ /******************** Bit definition for ADC_OFR2 register ******************/ #define ADC_OFR2_OFFSET_Pos (0U) #define ADC_OFR2_OFFSET_Msk (0x03FFFFFUL << ADC_OFR2_OFFSET_Pos) /*!< 0x003FFFFF */ #define ADC_OFR2_OFFSET ADC_OFR2_OFFSET_Msk /*!< ADC offset instance 2 offset level */ #define ADC_OFR2_OFFSET_0 (0x0000001UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000001 */ #define ADC_OFR2_OFFSET_1 (0x0000002UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000002 */ #define ADC_OFR2_OFFSET_2 (0x0000004UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000004 */ #define ADC_OFR2_OFFSET_3 (0x0000008UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000008 */ #define ADC_OFR2_OFFSET_4 (0x0000010UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000010 */ #define ADC_OFR2_OFFSET_5 (0x0000020UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000020 */ #define ADC_OFR2_OFFSET_6 (0x0000040UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000040 */ #define ADC_OFR2_OFFSET_7 (0x0000080UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000080 */ #define ADC_OFR2_OFFSET_8 (0x0000100UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000100 */ #define ADC_OFR2_OFFSET_9 (0x0000200UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000200 */ #define ADC_OFR2_OFFSET_10 (0x0000400UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000400 */ #define ADC_OFR2_OFFSET_11 (0x0000800UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000800 */ #define ADC_OFR2_OFFSET_12 (0x0001000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00001000 */ #define ADC_OFR2_OFFSET_13 (0x0002000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00002000 */ #define ADC_OFR2_OFFSET_14 (0x0004000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00004000 */ #define ADC_OFR2_OFFSET_15 (0x0008000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00008000 */ #define ADC_OFR2_OFFSET_16 (0x0010000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00010000 */ #define ADC_OFR2_OFFSET_17 (0x0020000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00020000 */ #define ADC_OFR2_OFFSET_18 (0x0040000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00040000 */ #define ADC_OFR2_OFFSET_19 (0x0080000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00080000 */ #define ADC_OFR2_OFFSET_20 (0x0100000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00100000 */ #define ADC_OFR2_OFFSET_21 (0x0200000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00200000 */ /******************** Bit definition for ADC_OFR3 register ******************/ #define ADC_OFR3_OFFSET_Pos (0U) #define ADC_OFR3_OFFSET_Msk (0x03FFFFFUL << ADC_OFR3_OFFSET_Pos) /*!< 0x003FFFFF */ #define ADC_OFR3_OFFSET ADC_OFR3_OFFSET_Msk /*!< ADC offset instance 3 offset level */ #define ADC_OFR3_OFFSET_0 (0x0000001UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000001 */ #define ADC_OFR3_OFFSET_1 (0x0000002UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000002 */ #define ADC_OFR3_OFFSET_2 (0x0000004UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000004 */ #define ADC_OFR3_OFFSET_3 (0x0000008UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000008 */ #define ADC_OFR3_OFFSET_4 (0x0000010UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000010 */ #define ADC_OFR3_OFFSET_5 (0x0000020UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000020 */ #define ADC_OFR3_OFFSET_6 (0x0000040UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000040 */ #define ADC_OFR3_OFFSET_7 (0x0000080UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000080 */ #define ADC_OFR3_OFFSET_8 (0x0000100UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000100 */ #define ADC_OFR3_OFFSET_9 (0x0000200UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000200 */ #define ADC_OFR3_OFFSET_10 (0x0000400UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000400 */ #define ADC_OFR3_OFFSET_11 (0x0000800UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000800 */ #define ADC_OFR3_OFFSET_12 (0x0001000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00001000 */ #define ADC_OFR3_OFFSET_13 (0x0002000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00002000 */ #define ADC_OFR3_OFFSET_14 (0x0004000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00004000 */ #define ADC_OFR3_OFFSET_15 (0x0008000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00008000 */ #define ADC_OFR3_OFFSET_16 (0x0010000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00010000 */ #define ADC_OFR3_OFFSET_17 (0x0020000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00020000 */ #define ADC_OFR3_OFFSET_18 (0x0040000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00040000 */ #define ADC_OFR3_OFFSET_19 (0x0080000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00080000 */ #define ADC_OFR3_OFFSET_20 (0x0100000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00100000 */ #define ADC_OFR3_OFFSET_21 (0x0200000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00200000 */ /******************** Bit definition for ADC_OFR4 register ******************/ #define ADC_OFR4_OFFSET_Pos (0U) #define ADC_OFR4_OFFSET_Msk (0x03FFFFFUL << ADC_OFR4_OFFSET_Pos) /*!< 0x003FFFFF */ #define ADC_OFR4_OFFSET ADC_OFR4_OFFSET_Msk /*!< ADC offset instance 4 offset level */ #define ADC_OFR4_OFFSET_0 (0x0000001UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000001 */ #define ADC_OFR4_OFFSET_1 (0x0000002UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000002 */ #define ADC_OFR4_OFFSET_2 (0x0000004UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000004 */ #define ADC_OFR4_OFFSET_3 (0x0000008UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000008 */ #define ADC_OFR4_OFFSET_4 (0x0000010UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000010 */ #define ADC_OFR4_OFFSET_5 (0x0000020UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000020 */ #define ADC_OFR4_OFFSET_6 (0x0000040UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000040 */ #define ADC_OFR4_OFFSET_7 (0x0000080UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000080 */ #define ADC_OFR4_OFFSET_8 (0x0000100UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000100 */ #define ADC_OFR4_OFFSET_9 (0x0000200UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000200 */ #define ADC_OFR4_OFFSET_10 (0x0000400UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000400 */ #define ADC_OFR4_OFFSET_11 (0x0000800UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000800 */ #define ADC_OFR4_OFFSET_12 (0x0001000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00001000 */ #define ADC_OFR4_OFFSET_13 (0x0002000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00002000 */ #define ADC_OFR4_OFFSET_14 (0x0004000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00004000 */ #define ADC_OFR4_OFFSET_15 (0x0008000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00008000 */ #define ADC_OFR4_OFFSET_16 (0x0010000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00010000 */ #define ADC_OFR4_OFFSET_17 (0x0020000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00020000 */ #define ADC_OFR4_OFFSET_18 (0x0040000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00040000 */ #define ADC_OFR4_OFFSET_19 (0x0080000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00080000 */ #define ADC_OFR4_OFFSET_20 (0x0100000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00100000 */ #define ADC_OFR4_OFFSET_21 (0x0200000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00200000 */ /******************** Bit definition for ADC_GCOMP register *****************/ #define ADC_GCOMP_GCOMPCOEFF_Pos (0U) #define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */ #define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< Gain compensation coefficient */ #define ADC_GCOMP_GCOMP_Pos (31U) #define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x80000000 */ #define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< Gain compensation mode */ /******************** Bit definition for ADC_JDR1 register ******************/ #define ADC_JDR1_JDATA_Pos (0U) #define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ #define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ #define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ #define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ #define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ #define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ #define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ #define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ #define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ #define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ #define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ #define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ #define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ #define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ #define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ #define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ #define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ #define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ #define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ #define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ #define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ #define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ #define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ #define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ #define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ #define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ #define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ #define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ #define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ #define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ #define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ #define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_JDR2 register ********************/ #define ADC_JDR2_JDATA_Pos (0U) #define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ #define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ #define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ #define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ #define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ #define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ #define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ #define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ #define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ #define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ #define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ #define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ #define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ #define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ #define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ #define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ #define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ #define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ #define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ #define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ #define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ #define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ #define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ #define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ #define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ #define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ #define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ #define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ #define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ #define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ #define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ #define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_JDR3 register ********************/ #define ADC_JDR3_JDATA_Pos (0U) #define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ #define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ #define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ #define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ #define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ #define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ #define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ #define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ #define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ #define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ #define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ #define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ #define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ #define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ #define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ #define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ #define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ #define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ #define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ #define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ #define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ #define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ #define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ #define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ #define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ #define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ #define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ #define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ #define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ #define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ #define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ #define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_JDR4 register ********************/ #define ADC_JDR4_JDATA_Pos (0U) #define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ #define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ #define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ #define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ #define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ #define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ #define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ #define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ #define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ #define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ #define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ #define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ #define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ #define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ #define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ #define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ #define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ #define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ #define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ #define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ #define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ #define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ #define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ #define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ #define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ #define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ #define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ #define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ #define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ #define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ #define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ #define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_AWD2CR register ****************/ #define ADC_AWD2CR_AWD2CH_Pos (0U) #define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */ #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ #define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ #define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ #define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ #define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ #define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ #define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ #define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ #define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ #define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ #define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ #define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ #define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ #define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ #define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ #define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ #define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ #define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ #define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ #define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ #define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ /******************** Bit definition for ADC_AWD3CR register ****************/ #define ADC_AWD3CR_AWD3CH_Pos (0U) #define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */ #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ #define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ #define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ #define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ #define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ #define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ #define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ #define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ #define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ #define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ #define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ #define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ #define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ #define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ #define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ #define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ #define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ #define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ #define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ #define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ #define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ /******************** Bit definition for ADC_AWD1TR_LT register *************/ #define ADC_AWD1LTR_LTR_Pos (0U) #define ADC_AWD1LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD1LTR_LTR_Pos) /*!< 0x007FFFFF */ #define ADC_AWD1LTR_LTR ADC_AWD1LTR_LTR_Msk /*!< ADC analog watchdog 1 threshold low */ #define ADC_AWD1LTR_LTR_0 (0x000001UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000001 */ #define ADC_AWD1LTR_LTR_1 (0x000002UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000002 */ #define ADC_AWD1LTR_LTR_2 (0x000004UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000004 */ #define ADC_AWD1LTR_LTR_3 (0x000008UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000008 */ #define ADC_AWD1LTR_LTR_4 (0x000010UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000010 */ #define ADC_AWD1LTR_LTR_5 (0x000020UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000020 */ #define ADC_AWD1LTR_LTR_6 (0x000040UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000040 */ #define ADC_AWD1LTR_LTR_7 (0x000080UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000080 */ #define ADC_AWD1LTR_LTR_8 (0x000100UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000100 */ #define ADC_AWD1LTR_LTR_9 (0x000200UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000200 */ #define ADC_AWD1LTR_LTR_10 (0x000400UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000400 */ #define ADC_AWD1LTR_LTR_11 (0x000800UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000800 */ #define ADC_AWD1LTR_LTR_12 (0x001000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00001000 */ #define ADC_AWD1LTR_LTR_13 (0x002000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00002000 */ #define ADC_AWD1LTR_LTR_14 (0x004000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00004000 */ #define ADC_AWD1LTR_LTR_15 (0x008000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00008000 */ #define ADC_AWD1LTR_LTR_16 (0x010000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00010000 */ #define ADC_AWD1LTR_LTR_17 (0x020000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00020000 */ #define ADC_AWD1LTR_LTR_18 (0x040000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00040000 */ #define ADC_AWD1LTR_LTR_19 (0x080000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00080000 */ #define ADC_AWD1LTR_LTR_20 (0x100000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00100000 */ #define ADC_AWD1LTR_LTR_21 (0x200000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00200000 */ #define ADC_AWD1LTR_LTR_22 (0x400000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00400000 */ /******************** Bit definition for ADC_AWD1TR_HT register *******************/ #define ADC_AWD1HTR_HTR_Pos (0U) #define ADC_AWD1HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD1HTR_HTR_Pos) /*!< 0x007FFFFF */ #define ADC_AWD1HTR_HTR ADC_AWD1HTR_HTR_Msk /*!< ADC analog watchdog 1 threshold high */ #define ADC_AWD1HTR_HTR_0 (0x000001UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000001 */ #define ADC_AWD1HTR_HTR_1 (0x000002UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000002 */ #define ADC_AWD1HTR_HTR_2 (0x000004UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000004 */ #define ADC_AWD1HTR_HTR_3 (0x000008UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000008 */ #define ADC_AWD1HTR_HTR_4 (0x000010UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000010 */ #define ADC_AWD1HTR_HTR_5 (0x000020UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000020 */ #define ADC_AWD1HTR_HTR_6 (0x000040UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000040 */ #define ADC_AWD1HTR_HTR_7 (0x000080UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000080 */ #define ADC_AWD1HTR_HTR_8 (0x000100UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000100 */ #define ADC_AWD1HTR_HTR_9 (0x000200UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000200 */ #define ADC_AWD1HTR_HTR_10 (0x000400UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000400 */ #define ADC_AWD1HTR_HTR_11 (0x000800UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000800 */ #define ADC_AWD1HTR_HTR_12 (0x001000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00001000 */ #define ADC_AWD1HTR_HTR_13 (0x002000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00002000 */ #define ADC_AWD1HTR_HTR_14 (0x004000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00004000 */ #define ADC_AWD1HTR_HTR_15 (0x008000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00008000 */ #define ADC_AWD1HTR_HTR_16 (0x010000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00010000 */ #define ADC_AWD1HTR_HTR_17 (0x020000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00020000 */ #define ADC_AWD1HTR_HTR_18 (0x040000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00040000 */ #define ADC_AWD1HTR_HTR_19 (0x080000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00080000 */ #define ADC_AWD1HTR_HTR_20 (0x100000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00100000 */ #define ADC_AWD1HTR_HTR_21 (0x200000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00200000 */ #define ADC_AWD1HTR_HTR_22 (0x400000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00400000 */ #define ADC_AWD1HTR_AWDFILT_Pos (29U) #define ADC_AWD1HTR_AWDFILT_Msk (0x7UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000007 */ #define ADC_AWD1HTR_AWDFILT ADC_AWD1HTR_AWDFILT_Msk /*!< ADC analog watchdog 1 filtering */ #define ADC_AWD1HTR_AWDFILT_0 (0x000001UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000001 */ #define ADC_AWD1HTR_AWDFILT_1 (0x000002UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000002 */ #define ADC_AWD1HTR_AWDFILT_2 (0x000004UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000004 */ /******************** Bit definition for ADC_AWD2TR_LT register *******************/ #define ADC_AWD2LTR_LTR_Pos (0U) #define ADC_AWD2LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD2LTR_LTR_Pos) /*!< 0x007FFFFF */ #define ADC_AWD2LTR_LTR ADC_AWD2LTR_LTR_Msk /*!< ADC analog watchdog 2 threshold low */ #define ADC_AWD2LTR_LTR_0 (0x000001UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000001 */ #define ADC_AWD2LTR_LTR_1 (0x000002UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000002 */ #define ADC_AWD2LTR_LTR_2 (0x000004UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000004 */ #define ADC_AWD2LTR_LTR_3 (0x000008UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000008 */ #define ADC_AWD2LTR_LTR_4 (0x000010UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000010 */ #define ADC_AWD2LTR_LTR_5 (0x000020UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000020 */ #define ADC_AWD2LTR_LTR_6 (0x000040UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000040 */ #define ADC_AWD2LTR_LTR_7 (0x000080UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000080 */ #define ADC_AWD2LTR_LTR_8 (0x000100UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000100 */ #define ADC_AWD2LTR_LTR_9 (0x000200UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000200 */ #define ADC_AWD2LTR_LTR_10 (0x000400UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000400 */ #define ADC_AWD2LTR_LTR_11 (0x000800UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000800 */ #define ADC_AWD2LTR_LTR_12 (0x001000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00001000 */ #define ADC_AWD2LTR_LTR_13 (0x002000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00002000 */ #define ADC_AWD2LTR_LTR_14 (0x004000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00004000 */ #define ADC_AWD2LTR_LTR_15 (0x008000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00008000 */ #define ADC_AWD2LTR_LTR_16 (0x010000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00010000 */ #define ADC_AWD2LTR_LTR_17 (0x020000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00020000 */ #define ADC_AWD2LTR_LTR_18 (0x040000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00040000 */ #define ADC_AWD2LTR_LTR_19 (0x080000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00080000 */ #define ADC_AWD2LTR_LTR_20 (0x100000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00100000 */ #define ADC_AWD2LTR_LTR_21 (0x200000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00200000 */ #define ADC_AWD2LTR_LTR_22 (0x400000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00400000 */ /******************** Bit definition for ADC_AWD2TR_HT register *******************/ #define ADC_AWD2HTR_HTR_Pos (0U) #define ADC_AWD2HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD2HTR_HTR_Pos) /*!< 0x007FFFFF */ #define ADC_AWD2HTR_HTR ADC_AWD2HTR_HTR_Msk /*!< ADC analog watchdog 2 threshold high */ #define ADC_AWD2HTR_HTR_0 (0x000001UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000001 */ #define ADC_AWD2HTR_HTR_1 (0x000002UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000002 */ #define ADC_AWD2HTR_HTR_2 (0x000004UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000004 */ #define ADC_AWD2HTR_HTR_3 (0x000008UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000008 */ #define ADC_AWD2HTR_HTR_4 (0x000010UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000010 */ #define ADC_AWD2HTR_HTR_5 (0x000020UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000020 */ #define ADC_AWD2HTR_HTR_6 (0x000040UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000040 */ #define ADC_AWD2HTR_HTR_7 (0x000080UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000080 */ #define ADC_AWD2HTR_HTR_8 (0x000100UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000100 */ #define ADC_AWD2HTR_HTR_9 (0x000200UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000200 */ #define ADC_AWD2HTR_HTR_10 (0x000400UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000400 */ #define ADC_AWD2HTR_HTR_11 (0x000800UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000800 */ #define ADC_AWD2HTR_HTR_12 (0x001000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00001000 */ #define ADC_AWD2HTR_HTR_13 (0x002000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00002000 */ #define ADC_AWD2HTR_HTR_14 (0x004000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00004000 */ #define ADC_AWD2HTR_HTR_15 (0x008000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00008000 */ #define ADC_AWD2HTR_HTR_16 (0x010000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00010000 */ #define ADC_AWD2HTR_HTR_17 (0x020000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00020000 */ #define ADC_AWD2HTR_HTR_18 (0x040000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00040000 */ #define ADC_AWD2HTR_HTR_19 (0x080000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00080000 */ #define ADC_AWD2HTR_HTR_20 (0x100000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00100000 */ #define ADC_AWD2HTR_HTR_21 (0x200000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00200000 */ #define ADC_AWD2HTR_HTR_22 (0x400000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00400000 */ /******************** Bit definition for ADC_AWD3TR_LT register *******************/ #define ADC_AWD3LTR_LTR_Pos (0U) #define ADC_AWD3LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD3LTR_LTR_Pos) /*!< 0x007FFFFF */ #define ADC_AWD3LTR_LTR ADC_AWD3LTR_LTR_Msk /*!< ADC analog watchdog 3 threshold low */ #define ADC_AWD3LTR_LTR_0 (0x000001UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000001 */ #define ADC_AWD3LTR_LTR_1 (0x000002UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000002 */ #define ADC_AWD3LTR_LTR_2 (0x000004UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000004 */ #define ADC_AWD3LTR_LTR_3 (0x000008UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000008 */ #define ADC_AWD3LTR_LTR_4 (0x000010UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000010 */ #define ADC_AWD3LTR_LTR_5 (0x000020UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000020 */ #define ADC_AWD3LTR_LTR_6 (0x000040UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000040 */ #define ADC_AWD3LTR_LTR_7 (0x000080UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000080 */ #define ADC_AWD3LTR_LTR_8 (0x000100UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000100 */ #define ADC_AWD3LTR_LTR_9 (0x000200UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000200 */ #define ADC_AWD3LTR_LTR_10 (0x000400UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000400 */ #define ADC_AWD3LTR_LTR_11 (0x000800UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000800 */ #define ADC_AWD3LTR_LTR_12 (0x001000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00001000 */ #define ADC_AWD3LTR_LTR_13 (0x002000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00002000 */ #define ADC_AWD3LTR_LTR_14 (0x004000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00004000 */ #define ADC_AWD3LTR_LTR_15 (0x008000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00008000 */ #define ADC_AWD3LTR_LTR_16 (0x010000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00010000 */ #define ADC_AWD3LTR_LTR_17 (0x020000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00020000 */ #define ADC_AWD3LTR_LTR_18 (0x040000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00040000 */ #define ADC_AWD3LTR_LTR_19 (0x080000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00080000 */ #define ADC_AWD3LTR_LTR_20 (0x100000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00100000 */ #define ADC_AWD3LTR_LTR_21 (0x200000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00200000 */ #define ADC_AWD3LTR_LTR_22 (0x400000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00400000 */ /******************** Bit definition for ADC_AWD3TR_HT register *******************/ #define ADC_AWD3HTR_HTR_Pos (0U) #define ADC_AWD3HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD3HTR_HTR_Pos) /*!< 0x007FFFFF */ #define ADC_AWD3HTR_HTR ADC_AWD3HTR_HTR_Msk /*!< ADC analog watchdog 3 threshold high */ #define ADC_AWD3HTR_HTR_0 (0x000001UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000001 */ #define ADC_AWD3HTR_HTR_1 (0x000002UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000002 */ #define ADC_AWD3HTR_HTR_2 (0x000004UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000004 */ #define ADC_AWD3HTR_HTR_3 (0x000008UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000008 */ #define ADC_AWD3HTR_HTR_4 (0x000010UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000010 */ #define ADC_AWD3HTR_HTR_5 (0x000020UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000020 */ #define ADC_AWD3HTR_HTR_6 (0x000040UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000040 */ #define ADC_AWD3HTR_HTR_7 (0x000080UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000080 */ #define ADC_AWD3HTR_HTR_8 (0x000100UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000100 */ #define ADC_AWD3HTR_HTR_9 (0x000200UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000200 */ #define ADC_AWD3HTR_HTR_10 (0x000400UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000400 */ #define ADC_AWD3HTR_HTR_11 (0x000800UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000800 */ #define ADC_AWD3HTR_HTR_12 (0x001000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00001000 */ #define ADC_AWD3HTR_HTR_13 (0x002000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00002000 */ #define ADC_AWD3HTR_HTR_14 (0x004000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00004000 */ #define ADC_AWD3HTR_HTR_15 (0x008000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00008000 */ #define ADC_AWD3HTR_HTR_16 (0x010000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00010000 */ #define ADC_AWD3HTR_HTR_17 (0x020000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00020000 */ #define ADC_AWD3HTR_HTR_18 (0x040000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00040000 */ #define ADC_AWD3HTR_HTR_19 (0x080000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00080000 */ #define ADC_AWD3HTR_HTR_20 (0x100000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00100000 */ #define ADC_AWD3HTR_HTR_21 (0x200000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00200000 */ #define ADC_AWD3HTR_HTR_22 (0x400000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00400000 */ /******************** Bit definition for ADC_DIFSEL register ****************/ #define ADC_DIFSEL_DIFSEL_Pos (0U) #define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode selection */ #define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ #define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ #define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ #define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ #define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ #define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ #define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ #define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ #define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ #define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ #define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ #define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ #define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ #define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ #define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ #define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ #define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ #define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ #define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ #define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ /******************** Bit definition for ADC_CALFACT register ***************/ #define ADC_CALFACT_CALFACT_S_Pos (0U) #define ADC_CALFACT_CALFACT_S_Msk (0x3FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000003FF */ #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ #define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ #define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ #define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ #define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ #define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ #define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ #define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ #define ADC_CALFACT_CALFACT_S_7 (0x80UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */ #define ADC_CALFACT_CALFACT_S_8 (0x100UL<< ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */ #define ADC_CALFACT_CALFACT_S_9 (0x200UL<< ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */ #define ADC_CALFACT_CALFACT_D_Pos (16U) #define ADC_CALFACT_CALFACT_D_Msk (0x3FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x03FF0000 */ #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ #define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ #define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ #define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ #define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ #define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ #define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ #define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ #define ADC_CALFACT_CALFACT_D_7 (0x80UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */ #define ADC_CALFACT_CALFACT_D_8 (0x100UL<< ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */ #define ADC_CALFACT_CALFACT_D_9 (0x200UL<< ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */ #define ADC_CALFACT_CALADDOS_Pos (31U) #define ADC_CALFACT_CALADDOS_Msk (0x01UL << ADC_CALFACT_CALADDOS_Pos) /*!< 0x80000000 */ #define ADC_CALFACT_CALADDOS ADC_CALFACT_CALADDOS_Msk /*!< ADC calibration additional offset mode */ /******************** Bit definition for ADC_OR option register ***************/ #define ADC_OR_OP0_Pos (0U) #define ADC_OR_OP0_Msk (0x1UL << ADC_OR_OP0_Pos) /*!< 0x00000001 */ #define ADC_OR_OP0 ADC_OR_OP0_Msk /*!< ADC internal reference voltage buffer */ #define ADC_OR_OP1_Pos (1U) #define ADC_OR_OP1_Msk (0x1UL << ADC_OR_OP1_Pos) /*!< 0x00000002 */ #define ADC_OR_OP1 ADC_OR_OP1_Msk /*!< ADC internal bandgap */ #define ADC_OR_OP2_Pos (2U) #define ADC_OR_OP2_Msk (0x1UL << ADC_OR_OP2_Pos) /*!< 0x00000004 */ #define ADC_OR_OP2 ADC_OR_OP2_Msk /*!< ADC internal path to VDDCORE */ /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CSR register *******************/ #define ADC_CSR_ADRDY_MST_Pos (0U) #define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ #define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ #define ADC_CSR_EOSMP_MST_Pos (1U) #define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ #define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ #define ADC_CSR_EOC_MST_Pos (2U) #define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ #define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ #define ADC_CSR_EOS_MST_Pos (3U) #define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ #define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ #define ADC_CSR_OVR_MST_Pos (4U) #define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ #define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ #define ADC_CSR_JEOC_MST_Pos (5U) #define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ #define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ #define ADC_CSR_JEOS_MST_Pos (6U) #define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ #define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ #define ADC_CSR_AWD1_MST_Pos (7U) #define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ #define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ #define ADC_CSR_AWD2_MST_Pos (8U) #define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ #define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ #define ADC_CSR_AWD3_MST_Pos (9U) #define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ #define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ #define ADC_CSR_ADRDY_SLV_Pos (16U) #define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ #define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ #define ADC_CSR_EOSMP_SLV_Pos (17U) #define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ #define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ #define ADC_CSR_EOC_SLV_Pos (18U) #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ #define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ #define ADC_CSR_EOS_SLV_Pos (19U) #define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ #define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ #define ADC_CSR_OVR_SLV_Pos (20U) #define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ #define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ #define ADC_CSR_JEOC_SLV_Pos (21U) #define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ #define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ #define ADC_CSR_JEOS_SLV_Pos (22U) #define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ #define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ #define ADC_CSR_AWD1_SLV_Pos (23U) #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ #define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ #define ADC_CSR_AWD2_SLV_Pos (24U) #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ #define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ #define ADC_CSR_AWD3_SLV_Pos (25U) #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ #define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ /******************** Bit definition for ADC_CCR register *******************/ #define ADC_CCR_DUAL_Pos (0U) #define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ #define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ #define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ #define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ #define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ #define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ #define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ #define ADC_CCR_DELAY_Pos (8U) #define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ #define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ #define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ #define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ #define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ #define ADC_CCR_DAMDF_Pos (14U) #define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ #define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< ADC multimode data format */ #define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */ #define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */ #define ADC_CCR_VREFEN_Pos (22U) #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ #define ADC_CCR_VBATEN_Pos (24U) #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ /******************** Bit definition for ADC_CDR register *******************/ #define ADC_CDR_RDATA_MST_Pos (0U) #define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ #define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ #define ADC_CDR_RDATA_SLV_Pos (16U) #define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ #define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ /******************** Bit definition for ADC_CDR2 register ******************/ #define ADC_CDR2_RDATA_ALT_Pos (0U) #define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ #define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< ADC multimode master or slave (alternated) group regular conversion data */ /******************************************************************************/ /* */ /* BSEC unit (Boot and Security) */ /* */ /******************************************************************************/ /****************** Bit definition for BSEC_FVRw register *******************/ #define BSEC_FVRw_FV_Pos (0U) #define BSEC_FVRw_FV_Msk (0xFFFFFFFFUL << BSEC_FVRw_FV_Pos) /*!< 0xFFFFFFFF */ #define BSEC_FVRw_FV BSEC_FVRw_FV_Msk /*!< Fuse value */ /***************** Bit definition for BSEC_SPLOCKx register *****************/ #define BSEC_SPLOCKx_SPLOCK0_Pos (0U) #define BSEC_SPLOCKx_SPLOCK0_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK0_Pos) /*!< 0x00000001 */ #define BSEC_SPLOCKx_SPLOCK0 BSEC_SPLOCKx_SPLOCK0_Msk /*!< Sticky programming lock for word (32*x) */ #define BSEC_SPLOCKx_SPLOCK1_Pos (1U) #define BSEC_SPLOCKx_SPLOCK1_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK1_Pos) /*!< 0x00000002 */ #define BSEC_SPLOCKx_SPLOCK1 BSEC_SPLOCKx_SPLOCK1_Msk /*!< Sticky programming lock for word (1+32*x) */ #define BSEC_SPLOCKx_SPLOCK2_Pos (2U) #define BSEC_SPLOCKx_SPLOCK2_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK2_Pos) /*!< 0x00000004 */ #define BSEC_SPLOCKx_SPLOCK2 BSEC_SPLOCKx_SPLOCK2_Msk /*!< Sticky programming lock for word (2+32*x) */ #define BSEC_SPLOCKx_SPLOCK3_Pos (3U) #define BSEC_SPLOCKx_SPLOCK3_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK3_Pos) /*!< 0x00000008 */ #define BSEC_SPLOCKx_SPLOCK3 BSEC_SPLOCKx_SPLOCK3_Msk /*!< Sticky programming lock for word (3+32*x) */ #define BSEC_SPLOCKx_SPLOCK4_Pos (4U) #define BSEC_SPLOCKx_SPLOCK4_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK4_Pos) /*!< 0x00000010 */ #define BSEC_SPLOCKx_SPLOCK4 BSEC_SPLOCKx_SPLOCK4_Msk /*!< Sticky programming lock for word (4+32*x) */ #define BSEC_SPLOCKx_SPLOCK5_Pos (5U) #define BSEC_SPLOCKx_SPLOCK5_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK5_Pos) /*!< 0x00000020 */ #define BSEC_SPLOCKx_SPLOCK5 BSEC_SPLOCKx_SPLOCK5_Msk /*!< Sticky programming lock for word (5+32*x) */ #define BSEC_SPLOCKx_SPLOCK6_Pos (6U) #define BSEC_SPLOCKx_SPLOCK6_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK6_Pos) /*!< 0x00000040 */ #define BSEC_SPLOCKx_SPLOCK6 BSEC_SPLOCKx_SPLOCK6_Msk /*!< Sticky programming lock for word (6+32*x) */ #define BSEC_SPLOCKx_SPLOCK7_Pos (7U) #define BSEC_SPLOCKx_SPLOCK7_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK7_Pos) /*!< 0x00000080 */ #define BSEC_SPLOCKx_SPLOCK7 BSEC_SPLOCKx_SPLOCK7_Msk /*!< Sticky programming lock for word (7+32*x) */ #define BSEC_SPLOCKx_SPLOCK8_Pos (8U) #define BSEC_SPLOCKx_SPLOCK8_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK8_Pos) /*!< 0x00000100 */ #define BSEC_SPLOCKx_SPLOCK8 BSEC_SPLOCKx_SPLOCK8_Msk /*!< Sticky programming lock for word (8+32*x) */ #define BSEC_SPLOCKx_SPLOCK9_Pos (9U) #define BSEC_SPLOCKx_SPLOCK9_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK9_Pos) /*!< 0x00000200 */ #define BSEC_SPLOCKx_SPLOCK9 BSEC_SPLOCKx_SPLOCK9_Msk /*!< Sticky programming lock for word (9+32*x) */ #define BSEC_SPLOCKx_SPLOCK10_Pos (10U) #define BSEC_SPLOCKx_SPLOCK10_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK10_Pos) /*!< 0x00000400 */ #define BSEC_SPLOCKx_SPLOCK10 BSEC_SPLOCKx_SPLOCK10_Msk /*!< Sticky programming lock for word (10+32*x) */ #define BSEC_SPLOCKx_SPLOCK11_Pos (11U) #define BSEC_SPLOCKx_SPLOCK11_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK11_Pos) /*!< 0x00000800 */ #define BSEC_SPLOCKx_SPLOCK11 BSEC_SPLOCKx_SPLOCK11_Msk /*!< Sticky programming lock for word (11+32*x) */ #define BSEC_SPLOCKx_SPLOCK12_Pos (12U) #define BSEC_SPLOCKx_SPLOCK12_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK12_Pos) /*!< 0x00001000 */ #define BSEC_SPLOCKx_SPLOCK12 BSEC_SPLOCKx_SPLOCK12_Msk /*!< Sticky programming lock for word (12+32*x) */ #define BSEC_SPLOCKx_SPLOCK13_Pos (13U) #define BSEC_SPLOCKx_SPLOCK13_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK13_Pos) /*!< 0x00002000 */ #define BSEC_SPLOCKx_SPLOCK13 BSEC_SPLOCKx_SPLOCK13_Msk /*!< Sticky programming lock for word (13+32*x) */ #define BSEC_SPLOCKx_SPLOCK14_Pos (14U) #define BSEC_SPLOCKx_SPLOCK14_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK14_Pos) /*!< 0x00004000 */ #define BSEC_SPLOCKx_SPLOCK14 BSEC_SPLOCKx_SPLOCK14_Msk /*!< Sticky programming lock for word (14+32*x) */ #define BSEC_SPLOCKx_SPLOCK15_Pos (15U) #define BSEC_SPLOCKx_SPLOCK15_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK15_Pos) /*!< 0x00008000 */ #define BSEC_SPLOCKx_SPLOCK15 BSEC_SPLOCKx_SPLOCK15_Msk /*!< Sticky programming lock for word (15+32*x) */ #define BSEC_SPLOCKx_SPLOCK16_Pos (16U) #define BSEC_SPLOCKx_SPLOCK16_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK16_Pos) /*!< 0x00010000 */ #define BSEC_SPLOCKx_SPLOCK16 BSEC_SPLOCKx_SPLOCK16_Msk /*!< Sticky programming lock for word (16+32*x) */ #define BSEC_SPLOCKx_SPLOCK17_Pos (17U) #define BSEC_SPLOCKx_SPLOCK17_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK17_Pos) /*!< 0x00020000 */ #define BSEC_SPLOCKx_SPLOCK17 BSEC_SPLOCKx_SPLOCK17_Msk /*!< Sticky programming lock for word (17+32*x) */ #define BSEC_SPLOCKx_SPLOCK18_Pos (18U) #define BSEC_SPLOCKx_SPLOCK18_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK18_Pos) /*!< 0x00040000 */ #define BSEC_SPLOCKx_SPLOCK18 BSEC_SPLOCKx_SPLOCK18_Msk /*!< Sticky programming lock for word (18+32*x) */ #define BSEC_SPLOCKx_SPLOCK19_Pos (19U) #define BSEC_SPLOCKx_SPLOCK19_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK19_Pos) /*!< 0x00080000 */ #define BSEC_SPLOCKx_SPLOCK19 BSEC_SPLOCKx_SPLOCK19_Msk /*!< Sticky programming lock for word (19+32*x) */ #define BSEC_SPLOCKx_SPLOCK20_Pos (20U) #define BSEC_SPLOCKx_SPLOCK20_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK20_Pos) /*!< 0x00100000 */ #define BSEC_SPLOCKx_SPLOCK20 BSEC_SPLOCKx_SPLOCK20_Msk /*!< Sticky programming lock for word (20+32*x) */ #define BSEC_SPLOCKx_SPLOCK21_Pos (21U) #define BSEC_SPLOCKx_SPLOCK21_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK21_Pos) /*!< 0x00200000 */ #define BSEC_SPLOCKx_SPLOCK21 BSEC_SPLOCKx_SPLOCK21_Msk /*!< Sticky programming lock for word (21+32*x) */ #define BSEC_SPLOCKx_SPLOCK22_Pos (22U) #define BSEC_SPLOCKx_SPLOCK22_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK22_Pos) /*!< 0x00400000 */ #define BSEC_SPLOCKx_SPLOCK22 BSEC_SPLOCKx_SPLOCK22_Msk /*!< Sticky programming lock for word (22+32*x) */ #define BSEC_SPLOCKx_SPLOCK23_Pos (23U) #define BSEC_SPLOCKx_SPLOCK23_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK23_Pos) /*!< 0x00800000 */ #define BSEC_SPLOCKx_SPLOCK23 BSEC_SPLOCKx_SPLOCK23_Msk /*!< Sticky programming lock for word (23+32*x) */ #define BSEC_SPLOCKx_SPLOCK24_Pos (24U) #define BSEC_SPLOCKx_SPLOCK24_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK24_Pos) /*!< 0x01000000 */ #define BSEC_SPLOCKx_SPLOCK24 BSEC_SPLOCKx_SPLOCK24_Msk /*!< Sticky programming lock for word (24+32*x) */ #define BSEC_SPLOCKx_SPLOCK25_Pos (25U) #define BSEC_SPLOCKx_SPLOCK25_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK25_Pos) /*!< 0x02000000 */ #define BSEC_SPLOCKx_SPLOCK25 BSEC_SPLOCKx_SPLOCK25_Msk /*!< Sticky programming lock for word (25+32*x) */ #define BSEC_SPLOCKx_SPLOCK26_Pos (26U) #define BSEC_SPLOCKx_SPLOCK26_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK26_Pos) /*!< 0x04000000 */ #define BSEC_SPLOCKx_SPLOCK26 BSEC_SPLOCKx_SPLOCK26_Msk /*!< Sticky programming lock for word (26+32*x) */ #define BSEC_SPLOCKx_SPLOCK27_Pos (27U) #define BSEC_SPLOCKx_SPLOCK27_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK27_Pos) /*!< 0x08000000 */ #define BSEC_SPLOCKx_SPLOCK27 BSEC_SPLOCKx_SPLOCK27_Msk /*!< Sticky programming lock for word (27+32*x) */ #define BSEC_SPLOCKx_SPLOCK28_Pos (28U) #define BSEC_SPLOCKx_SPLOCK28_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK28_Pos) /*!< 0x10000000 */ #define BSEC_SPLOCKx_SPLOCK28 BSEC_SPLOCKx_SPLOCK28_Msk /*!< Sticky programming lock for word (28+32*x) */ #define BSEC_SPLOCKx_SPLOCK29_Pos (29U) #define BSEC_SPLOCKx_SPLOCK29_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK29_Pos) /*!< 0x20000000 */ #define BSEC_SPLOCKx_SPLOCK29 BSEC_SPLOCKx_SPLOCK29_Msk /*!< Sticky programming lock for word (29+32*x) */ #define BSEC_SPLOCKx_SPLOCK30_Pos (30U) #define BSEC_SPLOCKx_SPLOCK30_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK30_Pos) /*!< 0x40000000 */ #define BSEC_SPLOCKx_SPLOCK30 BSEC_SPLOCKx_SPLOCK30_Msk /*!< Sticky programming lock for word (30+32*x) */ #define BSEC_SPLOCKx_SPLOCK31_Pos (31U) #define BSEC_SPLOCKx_SPLOCK31_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK31_Pos) /*!< 0x80000000 */ #define BSEC_SPLOCKx_SPLOCK31 BSEC_SPLOCKx_SPLOCK31_Msk /*!< Sticky programming lock for word (31+32*x) */ /***************** Bit definition for BSEC_SWLOCKx register *****************/ #define BSEC_SWLOCKx_SWLOCK0_Pos (0U) #define BSEC_SWLOCKx_SWLOCK0_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK0_Pos) /*!< 0x00000001 */ #define BSEC_SWLOCKx_SWLOCK0 BSEC_SWLOCKx_SWLOCK0_Msk /*!< Sticky write lock for shadow register (32*x) */ #define BSEC_SWLOCKx_SWLOCK1_Pos (1U) #define BSEC_SWLOCKx_SWLOCK1_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK1_Pos) /*!< 0x00000002 */ #define BSEC_SWLOCKx_SWLOCK1 BSEC_SWLOCKx_SWLOCK1_Msk /*!< Sticky write lock for shadow register (1+32*x) */ #define BSEC_SWLOCKx_SWLOCK2_Pos (2U) #define BSEC_SWLOCKx_SWLOCK2_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK2_Pos) /*!< 0x00000004 */ #define BSEC_SWLOCKx_SWLOCK2 BSEC_SWLOCKx_SWLOCK2_Msk /*!< Sticky write lock for shadow register (2+32*x) */ #define BSEC_SWLOCKx_SWLOCK3_Pos (3U) #define BSEC_SWLOCKx_SWLOCK3_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK3_Pos) /*!< 0x00000008 */ #define BSEC_SWLOCKx_SWLOCK3 BSEC_SWLOCKx_SWLOCK3_Msk /*!< Sticky write lock for shadow register (3+32*x) */ #define BSEC_SWLOCKx_SWLOCK4_Pos (4U) #define BSEC_SWLOCKx_SWLOCK4_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK4_Pos) /*!< 0x00000010 */ #define BSEC_SWLOCKx_SWLOCK4 BSEC_SWLOCKx_SWLOCK4_Msk /*!< Sticky write lock for shadow register (4+32*x) */ #define BSEC_SWLOCKx_SWLOCK5_Pos (5U) #define BSEC_SWLOCKx_SWLOCK5_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK5_Pos) /*!< 0x00000020 */ #define BSEC_SWLOCKx_SWLOCK5 BSEC_SWLOCKx_SWLOCK5_Msk /*!< Sticky write lock for shadow register (5+32*x) */ #define BSEC_SWLOCKx_SWLOCK6_Pos (6U) #define BSEC_SWLOCKx_SWLOCK6_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK6_Pos) /*!< 0x00000040 */ #define BSEC_SWLOCKx_SWLOCK6 BSEC_SWLOCKx_SWLOCK6_Msk /*!< Sticky write lock for shadow register (6+32*x) */ #define BSEC_SWLOCKx_SWLOCK7_Pos (7U) #define BSEC_SWLOCKx_SWLOCK7_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK7_Pos) /*!< 0x00000080 */ #define BSEC_SWLOCKx_SWLOCK7 BSEC_SWLOCKx_SWLOCK7_Msk /*!< Sticky write lock for shadow register (7+32*x) */ #define BSEC_SWLOCKx_SWLOCK8_Pos (8U) #define BSEC_SWLOCKx_SWLOCK8_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK8_Pos) /*!< 0x00000100 */ #define BSEC_SWLOCKx_SWLOCK8 BSEC_SWLOCKx_SWLOCK8_Msk /*!< Sticky write lock for shadow register (8+32*x) */ #define BSEC_SWLOCKx_SWLOCK9_Pos (9U) #define BSEC_SWLOCKx_SWLOCK9_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK9_Pos) /*!< 0x00000200 */ #define BSEC_SWLOCKx_SWLOCK9 BSEC_SWLOCKx_SWLOCK9_Msk /*!< Sticky write lock for shadow register (9+32*x) */ #define BSEC_SWLOCKx_SWLOCK10_Pos (10U) #define BSEC_SWLOCKx_SWLOCK10_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK10_Pos) /*!< 0x00000400 */ #define BSEC_SWLOCKx_SWLOCK10 BSEC_SWLOCKx_SWLOCK10_Msk /*!< Sticky write lock for shadow register (10+32*x) */ #define BSEC_SWLOCKx_SWLOCK11_Pos (11U) #define BSEC_SWLOCKx_SWLOCK11_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK11_Pos) /*!< 0x00000800 */ #define BSEC_SWLOCKx_SWLOCK11 BSEC_SWLOCKx_SWLOCK11_Msk /*!< Sticky write lock for shadow register (11+32*x) */ #define BSEC_SWLOCKx_SWLOCK12_Pos (12U) #define BSEC_SWLOCKx_SWLOCK12_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK12_Pos) /*!< 0x00001000 */ #define BSEC_SWLOCKx_SWLOCK12 BSEC_SWLOCKx_SWLOCK12_Msk /*!< Sticky write lock for shadow register (12+32*x) */ #define BSEC_SWLOCKx_SWLOCK13_Pos (13U) #define BSEC_SWLOCKx_SWLOCK13_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK13_Pos) /*!< 0x00002000 */ #define BSEC_SWLOCKx_SWLOCK13 BSEC_SWLOCKx_SWLOCK13_Msk /*!< Sticky write lock for shadow register (13+32*x) */ #define BSEC_SWLOCKx_SWLOCK14_Pos (14U) #define BSEC_SWLOCKx_SWLOCK14_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK14_Pos) /*!< 0x00004000 */ #define BSEC_SWLOCKx_SWLOCK14 BSEC_SWLOCKx_SWLOCK14_Msk /*!< Sticky write lock for shadow register (14+32*x) */ #define BSEC_SWLOCKx_SWLOCK15_Pos (15U) #define BSEC_SWLOCKx_SWLOCK15_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK15_Pos) /*!< 0x00008000 */ #define BSEC_SWLOCKx_SWLOCK15 BSEC_SWLOCKx_SWLOCK15_Msk /*!< Sticky write lock for shadow register (15+32*x) */ #define BSEC_SWLOCKx_SWLOCK16_Pos (16U) #define BSEC_SWLOCKx_SWLOCK16_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK16_Pos) /*!< 0x00010000 */ #define BSEC_SWLOCKx_SWLOCK16 BSEC_SWLOCKx_SWLOCK16_Msk /*!< Sticky write lock for shadow register (16+32*x) */ #define BSEC_SWLOCKx_SWLOCK17_Pos (17U) #define BSEC_SWLOCKx_SWLOCK17_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK17_Pos) /*!< 0x00020000 */ #define BSEC_SWLOCKx_SWLOCK17 BSEC_SWLOCKx_SWLOCK17_Msk /*!< Sticky write lock for shadow register (17+32*x) */ #define BSEC_SWLOCKx_SWLOCK18_Pos (18U) #define BSEC_SWLOCKx_SWLOCK18_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK18_Pos) /*!< 0x00040000 */ #define BSEC_SWLOCKx_SWLOCK18 BSEC_SWLOCKx_SWLOCK18_Msk /*!< Sticky write lock for shadow register (18+32*x) */ #define BSEC_SWLOCKx_SWLOCK19_Pos (19U) #define BSEC_SWLOCKx_SWLOCK19_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK19_Pos) /*!< 0x00080000 */ #define BSEC_SWLOCKx_SWLOCK19 BSEC_SWLOCKx_SWLOCK19_Msk /*!< Sticky write lock for shadow register (19+32*x) */ #define BSEC_SWLOCKx_SWLOCK20_Pos (20U) #define BSEC_SWLOCKx_SWLOCK20_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK20_Pos) /*!< 0x00100000 */ #define BSEC_SWLOCKx_SWLOCK20 BSEC_SWLOCKx_SWLOCK20_Msk /*!< Sticky write lock for shadow register (20+32*x) */ #define BSEC_SWLOCKx_SWLOCK21_Pos (21U) #define BSEC_SWLOCKx_SWLOCK21_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK21_Pos) /*!< 0x00200000 */ #define BSEC_SWLOCKx_SWLOCK21 BSEC_SWLOCKx_SWLOCK21_Msk /*!< Sticky write lock for shadow register (21+32*x) */ #define BSEC_SWLOCKx_SWLOCK22_Pos (22U) #define BSEC_SWLOCKx_SWLOCK22_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK22_Pos) /*!< 0x00400000 */ #define BSEC_SWLOCKx_SWLOCK22 BSEC_SWLOCKx_SWLOCK22_Msk /*!< Sticky write lock for shadow register (22+32*x) */ #define BSEC_SWLOCKx_SWLOCK23_Pos (23U) #define BSEC_SWLOCKx_SWLOCK23_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK23_Pos) /*!< 0x00800000 */ #define BSEC_SWLOCKx_SWLOCK23 BSEC_SWLOCKx_SWLOCK23_Msk /*!< Sticky write lock for shadow register (23+32*x) */ #define BSEC_SWLOCKx_SWLOCK24_Pos (24U) #define BSEC_SWLOCKx_SWLOCK24_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK24_Pos) /*!< 0x01000000 */ #define BSEC_SWLOCKx_SWLOCK24 BSEC_SWLOCKx_SWLOCK24_Msk /*!< Sticky write lock for shadow register (24+32*x) */ #define BSEC_SWLOCKx_SWLOCK25_Pos (25U) #define BSEC_SWLOCKx_SWLOCK25_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK25_Pos) /*!< 0x02000000 */ #define BSEC_SWLOCKx_SWLOCK25 BSEC_SWLOCKx_SWLOCK25_Msk /*!< Sticky write lock for shadow register (25+32*x) */ #define BSEC_SWLOCKx_SWLOCK26_Pos (26U) #define BSEC_SWLOCKx_SWLOCK26_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK26_Pos) /*!< 0x04000000 */ #define BSEC_SWLOCKx_SWLOCK26 BSEC_SWLOCKx_SWLOCK26_Msk /*!< Sticky write lock for shadow register (26+32*x) */ #define BSEC_SWLOCKx_SWLOCK27_Pos (27U) #define BSEC_SWLOCKx_SWLOCK27_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK27_Pos) /*!< 0x08000000 */ #define BSEC_SWLOCKx_SWLOCK27 BSEC_SWLOCKx_SWLOCK27_Msk /*!< Sticky write lock for shadow register (27+32*x) */ #define BSEC_SWLOCKx_SWLOCK28_Pos (28U) #define BSEC_SWLOCKx_SWLOCK28_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK28_Pos) /*!< 0x10000000 */ #define BSEC_SWLOCKx_SWLOCK28 BSEC_SWLOCKx_SWLOCK28_Msk /*!< Sticky write lock for shadow register (28+32*x) */ #define BSEC_SWLOCKx_SWLOCK29_Pos (29U) #define BSEC_SWLOCKx_SWLOCK29_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK29_Pos) /*!< 0x20000000 */ #define BSEC_SWLOCKx_SWLOCK29 BSEC_SWLOCKx_SWLOCK29_Msk /*!< Sticky write lock for shadow register (29+32*x) */ #define BSEC_SWLOCKx_SWLOCK30_Pos (30U) #define BSEC_SWLOCKx_SWLOCK30_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK30_Pos) /*!< 0x40000000 */ #define BSEC_SWLOCKx_SWLOCK30 BSEC_SWLOCKx_SWLOCK30_Msk /*!< Sticky write lock for shadow register (30+32*x) */ #define BSEC_SWLOCKx_SWLOCK31_Pos (31U) #define BSEC_SWLOCKx_SWLOCK31_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK31_Pos) /*!< 0x80000000 */ #define BSEC_SWLOCKx_SWLOCK31 BSEC_SWLOCKx_SWLOCK31_Msk /*!< Sticky write lock for shadow register (31+32*x) */ /***************** Bit definition for BSEC_SRLOCKx register *****************/ #define BSEC_SRLOCKx_SRLOCK0_Pos (0U) #define BSEC_SRLOCKx_SRLOCK0_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK0_Pos) /*!< 0x00000001 */ #define BSEC_SRLOCKx_SRLOCK0 BSEC_SRLOCKx_SRLOCK0_Msk /*!< Sticky reload lock for fuse word (32*x) */ #define BSEC_SRLOCKx_SRLOCK1_Pos (1U) #define BSEC_SRLOCKx_SRLOCK1_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK1_Pos) /*!< 0x00000002 */ #define BSEC_SRLOCKx_SRLOCK1 BSEC_SRLOCKx_SRLOCK1_Msk /*!< Sticky reload lock for fuse word (1+32*x) */ #define BSEC_SRLOCKx_SRLOCK2_Pos (2U) #define BSEC_SRLOCKx_SRLOCK2_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK2_Pos) /*!< 0x00000004 */ #define BSEC_SRLOCKx_SRLOCK2 BSEC_SRLOCKx_SRLOCK2_Msk /*!< Sticky reload lock for fuse word (2+32*x) */ #define BSEC_SRLOCKx_SRLOCK3_Pos (3U) #define BSEC_SRLOCKx_SRLOCK3_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK3_Pos) /*!< 0x00000008 */ #define BSEC_SRLOCKx_SRLOCK3 BSEC_SRLOCKx_SRLOCK3_Msk /*!< Sticky reload lock for fuse word (3+32*x) */ #define BSEC_SRLOCKx_SRLOCK4_Pos (4U) #define BSEC_SRLOCKx_SRLOCK4_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK4_Pos) /*!< 0x00000010 */ #define BSEC_SRLOCKx_SRLOCK4 BSEC_SRLOCKx_SRLOCK4_Msk /*!< Sticky reload lock for fuse word (4+32*x) */ #define BSEC_SRLOCKx_SRLOCK5_Pos (5U) #define BSEC_SRLOCKx_SRLOCK5_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK5_Pos) /*!< 0x00000020 */ #define BSEC_SRLOCKx_SRLOCK5 BSEC_SRLOCKx_SRLOCK5_Msk /*!< Sticky reload lock for fuse word (5+32*x) */ #define BSEC_SRLOCKx_SRLOCK6_Pos (6U) #define BSEC_SRLOCKx_SRLOCK6_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK6_Pos) /*!< 0x00000040 */ #define BSEC_SRLOCKx_SRLOCK6 BSEC_SRLOCKx_SRLOCK6_Msk /*!< Sticky reload lock for fuse word (6+32*x) */ #define BSEC_SRLOCKx_SRLOCK7_Pos (7U) #define BSEC_SRLOCKx_SRLOCK7_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK7_Pos) /*!< 0x00000080 */ #define BSEC_SRLOCKx_SRLOCK7 BSEC_SRLOCKx_SRLOCK7_Msk /*!< Sticky reload lock for fuse word (7+32*x) */ #define BSEC_SRLOCKx_SRLOCK8_Pos (8U) #define BSEC_SRLOCKx_SRLOCK8_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK8_Pos) /*!< 0x00000100 */ #define BSEC_SRLOCKx_SRLOCK8 BSEC_SRLOCKx_SRLOCK8_Msk /*!< Sticky reload lock for fuse word (8+32*x) */ #define BSEC_SRLOCKx_SRLOCK9_Pos (9U) #define BSEC_SRLOCKx_SRLOCK9_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK9_Pos) /*!< 0x00000200 */ #define BSEC_SRLOCKx_SRLOCK9 BSEC_SRLOCKx_SRLOCK9_Msk /*!< Sticky reload lock for fuse word (9+32*x) */ #define BSEC_SRLOCKx_SRLOCK10_Pos (10U) #define BSEC_SRLOCKx_SRLOCK10_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK10_Pos) /*!< 0x00000400 */ #define BSEC_SRLOCKx_SRLOCK10 BSEC_SRLOCKx_SRLOCK10_Msk /*!< Sticky reload lock for fuse word (10+2*x) */ #define BSEC_SRLOCKx_SRLOCK11_Pos (11U) #define BSEC_SRLOCKx_SRLOCK11_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK11_Pos) /*!< 0x00000800 */ #define BSEC_SRLOCKx_SRLOCK11 BSEC_SRLOCKx_SRLOCK11_Msk /*!< Sticky reload lock for fuse word (11+32*x) */ #define BSEC_SRLOCKx_SRLOCK12_Pos (12U) #define BSEC_SRLOCKx_SRLOCK12_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK12_Pos) /*!< 0x00001000 */ #define BSEC_SRLOCKx_SRLOCK12 BSEC_SRLOCKx_SRLOCK12_Msk /*!< Sticky reload lock for fuse word (12+32*x) */ #define BSEC_SRLOCKx_SRLOCK13_Pos (13U) #define BSEC_SRLOCKx_SRLOCK13_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK13_Pos) /*!< 0x00002000 */ #define BSEC_SRLOCKx_SRLOCK13 BSEC_SRLOCKx_SRLOCK13_Msk /*!< Sticky reload lock for fuse word (13+32*x) */ #define BSEC_SRLOCKx_SRLOCK14_Pos (14U) #define BSEC_SRLOCKx_SRLOCK14_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK14_Pos) /*!< 0x00004000 */ #define BSEC_SRLOCKx_SRLOCK14 BSEC_SRLOCKx_SRLOCK14_Msk /*!< Sticky reload lock for fuse word (14+32*x) */ #define BSEC_SRLOCKx_SRLOCK15_Pos (15U) #define BSEC_SRLOCKx_SRLOCK15_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK15_Pos) /*!< 0x00008000 */ #define BSEC_SRLOCKx_SRLOCK15 BSEC_SRLOCKx_SRLOCK15_Msk /*!< Sticky reload lock for fuse word (15+32*x) */ #define BSEC_SRLOCKx_SRLOCK16_Pos (16U) #define BSEC_SRLOCKx_SRLOCK16_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK16_Pos) /*!< 0x00010000 */ #define BSEC_SRLOCKx_SRLOCK16 BSEC_SRLOCKx_SRLOCK16_Msk /*!< Sticky reload lock for fuse word (16+32*x) */ #define BSEC_SRLOCKx_SRLOCK17_Pos (17U) #define BSEC_SRLOCKx_SRLOCK17_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK17_Pos) /*!< 0x00020000 */ #define BSEC_SRLOCKx_SRLOCK17 BSEC_SRLOCKx_SRLOCK17_Msk /*!< Sticky reload lock for fuse word (17+32*x) */ #define BSEC_SRLOCKx_SRLOCK18_Pos (18U) #define BSEC_SRLOCKx_SRLOCK18_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK18_Pos) /*!< 0x00040000 */ #define BSEC_SRLOCKx_SRLOCK18 BSEC_SRLOCKx_SRLOCK18_Msk /*!< Sticky reload lock for fuse word (18+32*x) */ #define BSEC_SRLOCKx_SRLOCK19_Pos (19U) #define BSEC_SRLOCKx_SRLOCK19_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK19_Pos) /*!< 0x00080000 */ #define BSEC_SRLOCKx_SRLOCK19 BSEC_SRLOCKx_SRLOCK19_Msk /*!< Sticky reload lock for fuse word (19+32*x) */ #define BSEC_SRLOCKx_SRLOCK20_Pos (20U) #define BSEC_SRLOCKx_SRLOCK20_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK20_Pos) /*!< 0x00100000 */ #define BSEC_SRLOCKx_SRLOCK20 BSEC_SRLOCKx_SRLOCK20_Msk /*!< Sticky reload lock for fuse word (20+32*x) */ #define BSEC_SRLOCKx_SRLOCK21_Pos (21U) #define BSEC_SRLOCKx_SRLOCK21_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK21_Pos) /*!< 0x00200000 */ #define BSEC_SRLOCKx_SRLOCK21 BSEC_SRLOCKx_SRLOCK21_Msk /*!< Sticky reload lock for fuse word (21+32*x) */ #define BSEC_SRLOCKx_SRLOCK22_Pos (22U) #define BSEC_SRLOCKx_SRLOCK22_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK22_Pos) /*!< 0x00400000 */ #define BSEC_SRLOCKx_SRLOCK22 BSEC_SRLOCKx_SRLOCK22_Msk /*!< Sticky reload lock for fuse word (22+32*x) */ #define BSEC_SRLOCKx_SRLOCK23_Pos (23U) #define BSEC_SRLOCKx_SRLOCK23_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK23_Pos) /*!< 0x00800000 */ #define BSEC_SRLOCKx_SRLOCK23 BSEC_SRLOCKx_SRLOCK23_Msk /*!< Sticky reload lock for fuse word (23+32*x) */ #define BSEC_SRLOCKx_SRLOCK24_Pos (24U) #define BSEC_SRLOCKx_SRLOCK24_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK24_Pos) /*!< 0x01000000 */ #define BSEC_SRLOCKx_SRLOCK24 BSEC_SRLOCKx_SRLOCK24_Msk /*!< Sticky reload lock for fuse word (24+32*x) */ #define BSEC_SRLOCKx_SRLOCK25_Pos (25U) #define BSEC_SRLOCKx_SRLOCK25_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK25_Pos) /*!< 0x02000000 */ #define BSEC_SRLOCKx_SRLOCK25 BSEC_SRLOCKx_SRLOCK25_Msk /*!< Sticky reload lock for fuse word (25+32*x) */ #define BSEC_SRLOCKx_SRLOCK26_Pos (26U) #define BSEC_SRLOCKx_SRLOCK26_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK26_Pos) /*!< 0x04000000 */ #define BSEC_SRLOCKx_SRLOCK26 BSEC_SRLOCKx_SRLOCK26_Msk /*!< Sticky reload lock for fuse word (26+32*x) */ #define BSEC_SRLOCKx_SRLOCK27_Pos (27U) #define BSEC_SRLOCKx_SRLOCK27_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK27_Pos) /*!< 0x08000000 */ #define BSEC_SRLOCKx_SRLOCK27 BSEC_SRLOCKx_SRLOCK27_Msk /*!< Sticky reload lock for fuse word (27+32*x) */ #define BSEC_SRLOCKx_SRLOCK28_Pos (28U) #define BSEC_SRLOCKx_SRLOCK28_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK28_Pos) /*!< 0x10000000 */ #define BSEC_SRLOCKx_SRLOCK28 BSEC_SRLOCKx_SRLOCK28_Msk /*!< Sticky reload lock for fuse word (28+32*x) */ #define BSEC_SRLOCKx_SRLOCK29_Pos (29U) #define BSEC_SRLOCKx_SRLOCK29_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK29_Pos) /*!< 0x20000000 */ #define BSEC_SRLOCKx_SRLOCK29 BSEC_SRLOCKx_SRLOCK29_Msk /*!< Sticky reload lock for fuse word (29+32*x) */ #define BSEC_SRLOCKx_SRLOCK30_Pos (30U) #define BSEC_SRLOCKx_SRLOCK30_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK30_Pos) /*!< 0x40000000 */ #define BSEC_SRLOCKx_SRLOCK30 BSEC_SRLOCKx_SRLOCK30_Msk /*!< Sticky reload lock for fuse word (30+32*x) */ #define BSEC_SRLOCKx_SRLOCK31_Pos (31U) #define BSEC_SRLOCKx_SRLOCK31_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK31_Pos) /*!< 0x80000000 */ #define BSEC_SRLOCKx_SRLOCK31 BSEC_SRLOCKx_SRLOCK31_Msk /*!< Sticky reload lock for fuse word (31+32*x) */ /**************** Bit definition for BSEC_OTPVLDRx register *****************/ #define BSEC_OTPVLDRx_VLDF0_Pos (0U) #define BSEC_OTPVLDRx_VLDF0_Msk (0x1UL << BSEC_OTPVLDRx_VLDF0_Pos) /*!< 0x00000001 */ #define BSEC_OTPVLDRx_VLDF0 BSEC_OTPVLDRx_VLDF0_Msk /*!< Valid flag for shadow register (32*x) */ #define BSEC_OTPVLDRx_VLDF1_Pos (1U) #define BSEC_OTPVLDRx_VLDF1_Msk (0x1UL << BSEC_OTPVLDRx_VLDF1_Pos) /*!< 0x00000002 */ #define BSEC_OTPVLDRx_VLDF1 BSEC_OTPVLDRx_VLDF1_Msk /*!< Valid flag for shadow register (1+32*x) */ #define BSEC_OTPVLDRx_VLDF2_Pos (2U) #define BSEC_OTPVLDRx_VLDF2_Msk (0x1UL << BSEC_OTPVLDRx_VLDF2_Pos) /*!< 0x00000004 */ #define BSEC_OTPVLDRx_VLDF2 BSEC_OTPVLDRx_VLDF2_Msk /*!< Valid flag for shadow register (2+32*x) */ #define BSEC_OTPVLDRx_VLDF3_Pos (3U) #define BSEC_OTPVLDRx_VLDF3_Msk (0x1UL << BSEC_OTPVLDRx_VLDF3_Pos) /*!< 0x00000008 */ #define BSEC_OTPVLDRx_VLDF3 BSEC_OTPVLDRx_VLDF3_Msk /*!< Valid flag for shadow register (3+32*x) */ #define BSEC_OTPVLDRx_VLDF4_Pos (4U) #define BSEC_OTPVLDRx_VLDF4_Msk (0x1UL << BSEC_OTPVLDRx_VLDF4_Pos) /*!< 0x00000010 */ #define BSEC_OTPVLDRx_VLDF4 BSEC_OTPVLDRx_VLDF4_Msk /*!< Valid flag for shadow register (4+32*x) */ #define BSEC_OTPVLDRx_VLDF5_Pos (5U) #define BSEC_OTPVLDRx_VLDF5_Msk (0x1UL << BSEC_OTPVLDRx_VLDF5_Pos) /*!< 0x00000020 */ #define BSEC_OTPVLDRx_VLDF5 BSEC_OTPVLDRx_VLDF5_Msk /*!< Valid flag for shadow register (5+32*x) */ #define BSEC_OTPVLDRx_VLDF6_Pos (6U) #define BSEC_OTPVLDRx_VLDF6_Msk (0x1UL << BSEC_OTPVLDRx_VLDF6_Pos) /*!< 0x00000040 */ #define BSEC_OTPVLDRx_VLDF6 BSEC_OTPVLDRx_VLDF6_Msk /*!< Valid flag for shadow register (6+32*x) */ #define BSEC_OTPVLDRx_VLDF7_Pos (7U) #define BSEC_OTPVLDRx_VLDF7_Msk (0x1UL << BSEC_OTPVLDRx_VLDF7_Pos) /*!< 0x00000080 */ #define BSEC_OTPVLDRx_VLDF7 BSEC_OTPVLDRx_VLDF7_Msk /*!< Valid flag for shadow register (7+32*x) */ #define BSEC_OTPVLDRx_VLDF8_Pos (8U) #define BSEC_OTPVLDRx_VLDF8_Msk (0x1UL << BSEC_OTPVLDRx_VLDF8_Pos) /*!< 0x00000100 */ #define BSEC_OTPVLDRx_VLDF8 BSEC_OTPVLDRx_VLDF8_Msk /*!< Valid flag for shadow register (8+32*x) */ #define BSEC_OTPVLDRx_VLDF9_Pos (9U) #define BSEC_OTPVLDRx_VLDF9_Msk (0x1UL << BSEC_OTPVLDRx_VLDF9_Pos) /*!< 0x00000200 */ #define BSEC_OTPVLDRx_VLDF9 BSEC_OTPVLDRx_VLDF9_Msk /*!< Valid flag for shadow register (9+32*x) */ #define BSEC_OTPVLDRx_VLDF10_Pos (10U) #define BSEC_OTPVLDRx_VLDF10_Msk (0x1UL << BSEC_OTPVLDRx_VLDF10_Pos) /*!< 0x00000400 */ #define BSEC_OTPVLDRx_VLDF10 BSEC_OTPVLDRx_VLDF10_Msk /*!< Valid flag for shadow register (10+32*x) */ #define BSEC_OTPVLDRx_VLDF11_Pos (11U) #define BSEC_OTPVLDRx_VLDF11_Msk (0x1UL << BSEC_OTPVLDRx_VLDF11_Pos) /*!< 0x00000800 */ #define BSEC_OTPVLDRx_VLDF11 BSEC_OTPVLDRx_VLDF11_Msk /*!< Valid flag for shadow register (11+32*x) */ #define BSEC_OTPVLDRx_VLDF12_Pos (12U) #define BSEC_OTPVLDRx_VLDF12_Msk (0x1UL << BSEC_OTPVLDRx_VLDF12_Pos) /*!< 0x00001000 */ #define BSEC_OTPVLDRx_VLDF12 BSEC_OTPVLDRx_VLDF12_Msk /*!< Valid flag for shadow register (12+32*x) */ #define BSEC_OTPVLDRx_VLDF13_Pos (13U) #define BSEC_OTPVLDRx_VLDF13_Msk (0x1UL << BSEC_OTPVLDRx_VLDF13_Pos) /*!< 0x00002000 */ #define BSEC_OTPVLDRx_VLDF13 BSEC_OTPVLDRx_VLDF13_Msk /*!< Valid flag for shadow register (13+32*x) */ #define BSEC_OTPVLDRx_VLDF14_Pos (14U) #define BSEC_OTPVLDRx_VLDF14_Msk (0x1UL << BSEC_OTPVLDRx_VLDF14_Pos) /*!< 0x00004000 */ #define BSEC_OTPVLDRx_VLDF14 BSEC_OTPVLDRx_VLDF14_Msk /*!< Valid flag for shadow register (14+32*x) */ #define BSEC_OTPVLDRx_VLDF15_Pos (15U) #define BSEC_OTPVLDRx_VLDF15_Msk (0x1UL << BSEC_OTPVLDRx_VLDF15_Pos) /*!< 0x00008000 */ #define BSEC_OTPVLDRx_VLDF15 BSEC_OTPVLDRx_VLDF15_Msk /*!< Valid flag for shadow register (15+32*x) */ #define BSEC_OTPVLDRx_VLDF16_Pos (16U) #define BSEC_OTPVLDRx_VLDF16_Msk (0x1UL << BSEC_OTPVLDRx_VLDF16_Pos) /*!< 0x00010000 */ #define BSEC_OTPVLDRx_VLDF16 BSEC_OTPVLDRx_VLDF16_Msk /*!< Valid flag for shadow register (16+32*x) */ #define BSEC_OTPVLDRx_VLDF17_Pos (17U) #define BSEC_OTPVLDRx_VLDF17_Msk (0x1UL << BSEC_OTPVLDRx_VLDF17_Pos) /*!< 0x00020000 */ #define BSEC_OTPVLDRx_VLDF17 BSEC_OTPVLDRx_VLDF17_Msk /*!< Valid flag for shadow register (17+32*x) */ #define BSEC_OTPVLDRx_VLDF18_Pos (18U) #define BSEC_OTPVLDRx_VLDF18_Msk (0x1UL << BSEC_OTPVLDRx_VLDF18_Pos) /*!< 0x00040000 */ #define BSEC_OTPVLDRx_VLDF18 BSEC_OTPVLDRx_VLDF18_Msk /*!< Valid flag for shadow register (18+32*x) */ #define BSEC_OTPVLDRx_VLDF19_Pos (19U) #define BSEC_OTPVLDRx_VLDF19_Msk (0x1UL << BSEC_OTPVLDRx_VLDF19_Pos) /*!< 0x00080000 */ #define BSEC_OTPVLDRx_VLDF19 BSEC_OTPVLDRx_VLDF19_Msk /*!< Valid flag for shadow register (19+32*x) */ #define BSEC_OTPVLDRx_VLDF20_Pos (20U) #define BSEC_OTPVLDRx_VLDF20_Msk (0x1UL << BSEC_OTPVLDRx_VLDF20_Pos) /*!< 0x00100000 */ #define BSEC_OTPVLDRx_VLDF20 BSEC_OTPVLDRx_VLDF20_Msk /*!< Valid flag for shadow register (20+32*x) */ #define BSEC_OTPVLDRx_VLDF21_Pos (21U) #define BSEC_OTPVLDRx_VLDF21_Msk (0x1UL << BSEC_OTPVLDRx_VLDF21_Pos) /*!< 0x00200000 */ #define BSEC_OTPVLDRx_VLDF21 BSEC_OTPVLDRx_VLDF21_Msk /*!< Valid flag for shadow register (21+32*x) */ #define BSEC_OTPVLDRx_VLDF22_Pos (22U) #define BSEC_OTPVLDRx_VLDF22_Msk (0x1UL << BSEC_OTPVLDRx_VLDF22_Pos) /*!< 0x00400000 */ #define BSEC_OTPVLDRx_VLDF22 BSEC_OTPVLDRx_VLDF22_Msk /*!< Valid flag for shadow register (22+32*x) */ #define BSEC_OTPVLDRx_VLDF23_Pos (23U) #define BSEC_OTPVLDRx_VLDF23_Msk (0x1UL << BSEC_OTPVLDRx_VLDF23_Pos) /*!< 0x00800000 */ #define BSEC_OTPVLDRx_VLDF23 BSEC_OTPVLDRx_VLDF23_Msk /*!< Valid flag for shadow register (23+32*x) */ #define BSEC_OTPVLDRx_VLDF24_Pos (24U) #define BSEC_OTPVLDRx_VLDF24_Msk (0x1UL << BSEC_OTPVLDRx_VLDF24_Pos) /*!< 0x01000000 */ #define BSEC_OTPVLDRx_VLDF24 BSEC_OTPVLDRx_VLDF24_Msk /*!< Valid flag for shadow register (24+32*x) */ #define BSEC_OTPVLDRx_VLDF25_Pos (25U) #define BSEC_OTPVLDRx_VLDF25_Msk (0x1UL << BSEC_OTPVLDRx_VLDF25_Pos) /*!< 0x02000000 */ #define BSEC_OTPVLDRx_VLDF25 BSEC_OTPVLDRx_VLDF25_Msk /*!< Valid flag for shadow register (25+32*x) */ #define BSEC_OTPVLDRx_VLDF26_Pos (26U) #define BSEC_OTPVLDRx_VLDF26_Msk (0x1UL << BSEC_OTPVLDRx_VLDF26_Pos) /*!< 0x04000000 */ #define BSEC_OTPVLDRx_VLDF26 BSEC_OTPVLDRx_VLDF26_Msk /*!< Valid flag for shadow register (26+32*x) */ #define BSEC_OTPVLDRx_VLDF27_Pos (27U) #define BSEC_OTPVLDRx_VLDF27_Msk (0x1UL << BSEC_OTPVLDRx_VLDF27_Pos) /*!< 0x08000000 */ #define BSEC_OTPVLDRx_VLDF27 BSEC_OTPVLDRx_VLDF27_Msk /*!< Valid flag for shadow register (27+32*x) */ #define BSEC_OTPVLDRx_VLDF28_Pos (28U) #define BSEC_OTPVLDRx_VLDF28_Msk (0x1UL << BSEC_OTPVLDRx_VLDF28_Pos) /*!< 0x10000000 */ #define BSEC_OTPVLDRx_VLDF28 BSEC_OTPVLDRx_VLDF28_Msk /*!< Valid flag for shadow register (28+32*x) */ #define BSEC_OTPVLDRx_VLDF29_Pos (29U) #define BSEC_OTPVLDRx_VLDF29_Msk (0x1UL << BSEC_OTPVLDRx_VLDF29_Pos) /*!< 0x20000000 */ #define BSEC_OTPVLDRx_VLDF29 BSEC_OTPVLDRx_VLDF29_Msk /*!< Valid flag for shadow register (29+32*x) */ #define BSEC_OTPVLDRx_VLDF30_Pos (30U) #define BSEC_OTPVLDRx_VLDF30_Msk (0x1UL << BSEC_OTPVLDRx_VLDF30_Pos) /*!< 0x40000000 */ #define BSEC_OTPVLDRx_VLDF30 BSEC_OTPVLDRx_VLDF30_Msk /*!< Valid flag for shadow register (30+32*x) */ #define BSEC_OTPVLDRx_VLDF31_Pos (31U) #define BSEC_OTPVLDRx_VLDF31_Msk (0x1UL << BSEC_OTPVLDRx_VLDF31_Pos) /*!< 0x80000000 */ #define BSEC_OTPVLDRx_VLDF31 BSEC_OTPVLDRx_VLDF31_Msk /*!< Valid flag for shadow register (31+32*x) */ /****************** Bit definition for BSEC_SFSRx register ******************/ #define BSEC_SFSRx_SFW0_Pos (0U) #define BSEC_SFSRx_SFW0_Msk (0x1UL << BSEC_SFSRx_SFW0_Pos) /*!< 0x00000001 */ #define BSEC_SFSRx_SFW0 BSEC_SFSRx_SFW0_Msk /*!< Shadowed fuse word (32*x) */ #define BSEC_SFSRx_SFW1_Pos (1U) #define BSEC_SFSRx_SFW1_Msk (0x1UL << BSEC_SFSRx_SFW1_Pos) /*!< 0x00000002 */ #define BSEC_SFSRx_SFW1 BSEC_SFSRx_SFW1_Msk /*!< Shadowed fuse word (1+32*x) */ #define BSEC_SFSRx_SFW2_Pos (2U) #define BSEC_SFSRx_SFW2_Msk (0x1UL << BSEC_SFSRx_SFW2_Pos) /*!< 0x00000004 */ #define BSEC_SFSRx_SFW2 BSEC_SFSRx_SFW2_Msk /*!< Shadowed fuse word (2+32*x) */ #define BSEC_SFSRx_SFW3_Pos (3U) #define BSEC_SFSRx_SFW3_Msk (0x1UL << BSEC_SFSRx_SFW3_Pos) /*!< 0x00000008 */ #define BSEC_SFSRx_SFW3 BSEC_SFSRx_SFW3_Msk /*!< Shadowed fuse word (3+32*x) */ #define BSEC_SFSRx_SFW4_Pos (4U) #define BSEC_SFSRx_SFW4_Msk (0x1UL << BSEC_SFSRx_SFW4_Pos) /*!< 0x00000010 */ #define BSEC_SFSRx_SFW4 BSEC_SFSRx_SFW4_Msk /*!< Shadowed fuse word (4+32*x) */ #define BSEC_SFSRx_SFW5_Pos (5U) #define BSEC_SFSRx_SFW5_Msk (0x1UL << BSEC_SFSRx_SFW5_Pos) /*!< 0x00000020 */ #define BSEC_SFSRx_SFW5 BSEC_SFSRx_SFW5_Msk /*!< Shadowed fuse word (5+32*x) */ #define BSEC_SFSRx_SFW6_Pos (6U) #define BSEC_SFSRx_SFW6_Msk (0x1UL << BSEC_SFSRx_SFW6_Pos) /*!< 0x00000040 */ #define BSEC_SFSRx_SFW6 BSEC_SFSRx_SFW6_Msk /*!< Shadowed fuse word (6+32*x) */ #define BSEC_SFSRx_SFW7_Pos (7U) #define BSEC_SFSRx_SFW7_Msk (0x1UL << BSEC_SFSRx_SFW7_Pos) /*!< 0x00000080 */ #define BSEC_SFSRx_SFW7 BSEC_SFSRx_SFW7_Msk /*!< Shadowed fuse word (7+32*x) */ #define BSEC_SFSRx_SFW8_Pos (8U) #define BSEC_SFSRx_SFW8_Msk (0x1UL << BSEC_SFSRx_SFW8_Pos) /*!< 0x00000100 */ #define BSEC_SFSRx_SFW8 BSEC_SFSRx_SFW8_Msk /*!< Shadowed fuse word (8+32*x) */ #define BSEC_SFSRx_SFW9_Pos (9U) #define BSEC_SFSRx_SFW9_Msk (0x1UL << BSEC_SFSRx_SFW9_Pos) /*!< 0x00000200 */ #define BSEC_SFSRx_SFW9 BSEC_SFSRx_SFW9_Msk /*!< Shadowed fuse word (9+32*x) */ #define BSEC_SFSRx_SFW10_Pos (10U) #define BSEC_SFSRx_SFW10_Msk (0x1UL << BSEC_SFSRx_SFW10_Pos) /*!< 0x00000400 */ #define BSEC_SFSRx_SFW10 BSEC_SFSRx_SFW10_Msk /*!< Shadowed fuse word (10+32*x) */ #define BSEC_SFSRx_SFW11_Pos (11U) #define BSEC_SFSRx_SFW11_Msk (0x1UL << BSEC_SFSRx_SFW11_Pos) /*!< 0x00000800 */ #define BSEC_SFSRx_SFW11 BSEC_SFSRx_SFW11_Msk /*!< Shadowed fuse word (11+32*x) */ #define BSEC_SFSRx_SFW12_Pos (12U) #define BSEC_SFSRx_SFW12_Msk (0x1UL << BSEC_SFSRx_SFW12_Pos) /*!< 0x00001000 */ #define BSEC_SFSRx_SFW12 BSEC_SFSRx_SFW12_Msk /*!< Shadowed fuse word (12+32*x) */ #define BSEC_SFSRx_SFW13_Pos (13U) #define BSEC_SFSRx_SFW13_Msk (0x1UL << BSEC_SFSRx_SFW13_Pos) /*!< 0x00002000 */ #define BSEC_SFSRx_SFW13 BSEC_SFSRx_SFW13_Msk /*!< Shadowed fuse word (13+32*x) */ #define BSEC_SFSRx_SFW14_Pos (14U) #define BSEC_SFSRx_SFW14_Msk (0x1UL << BSEC_SFSRx_SFW14_Pos) /*!< 0x00004000 */ #define BSEC_SFSRx_SFW14 BSEC_SFSRx_SFW14_Msk /*!< Shadowed fuse word (14+32*x) */ #define BSEC_SFSRx_SFW15_Pos (15U) #define BSEC_SFSRx_SFW15_Msk (0x1UL << BSEC_SFSRx_SFW15_Pos) /*!< 0x00008000 */ #define BSEC_SFSRx_SFW15 BSEC_SFSRx_SFW15_Msk /*!< Shadowed fuse word (15+32*x) */ #define BSEC_SFSRx_SFW16_Pos (16U) #define BSEC_SFSRx_SFW16_Msk (0x1UL << BSEC_SFSRx_SFW16_Pos) /*!< 0x00010000 */ #define BSEC_SFSRx_SFW16 BSEC_SFSRx_SFW16_Msk /*!< Shadowed fuse word (16+32*x) */ #define BSEC_SFSRx_SFW17_Pos (17U) #define BSEC_SFSRx_SFW17_Msk (0x1UL << BSEC_SFSRx_SFW17_Pos) /*!< 0x00020000 */ #define BSEC_SFSRx_SFW17 BSEC_SFSRx_SFW17_Msk /*!< Shadowed fuse word (17+32*x) */ #define BSEC_SFSRx_SFW18_Pos (18U) #define BSEC_SFSRx_SFW18_Msk (0x1UL << BSEC_SFSRx_SFW18_Pos) /*!< 0x00040000 */ #define BSEC_SFSRx_SFW18 BSEC_SFSRx_SFW18_Msk /*!< Shadowed fuse word (18+32*x) */ #define BSEC_SFSRx_SFW19_Pos (19U) #define BSEC_SFSRx_SFW19_Msk (0x1UL << BSEC_SFSRx_SFW19_Pos) /*!< 0x00080000 */ #define BSEC_SFSRx_SFW19 BSEC_SFSRx_SFW19_Msk /*!< Shadowed fuse word (19+32*x) */ #define BSEC_SFSRx_SFW20_Pos (20U) #define BSEC_SFSRx_SFW20_Msk (0x1UL << BSEC_SFSRx_SFW20_Pos) /*!< 0x00100000 */ #define BSEC_SFSRx_SFW20 BSEC_SFSRx_SFW20_Msk /*!< Shadowed fuse word (20+32*x) */ #define BSEC_SFSRx_SFW21_Pos (21U) #define BSEC_SFSRx_SFW21_Msk (0x1UL << BSEC_SFSRx_SFW21_Pos) /*!< 0x00200000 */ #define BSEC_SFSRx_SFW21 BSEC_SFSRx_SFW21_Msk /*!< Shadowed fuse word (21+32*x) */ #define BSEC_SFSRx_SFW22_Pos (22U) #define BSEC_SFSRx_SFW22_Msk (0x1UL << BSEC_SFSRx_SFW22_Pos) /*!< 0x00400000 */ #define BSEC_SFSRx_SFW22 BSEC_SFSRx_SFW22_Msk /*!< Shadowed fuse word (22+32*x) */ #define BSEC_SFSRx_SFW23_Pos (23U) #define BSEC_SFSRx_SFW23_Msk (0x1UL << BSEC_SFSRx_SFW23_Pos) /*!< 0x00800000 */ #define BSEC_SFSRx_SFW23 BSEC_SFSRx_SFW23_Msk /*!< Shadowed fuse word (23+32*x) */ #define BSEC_SFSRx_SFW24_Pos (24U) #define BSEC_SFSRx_SFW24_Msk (0x1UL << BSEC_SFSRx_SFW24_Pos) /*!< 0x01000000 */ #define BSEC_SFSRx_SFW24 BSEC_SFSRx_SFW24_Msk /*!< Shadowed fuse word (24+32*x) */ #define BSEC_SFSRx_SFW25_Pos (25U) #define BSEC_SFSRx_SFW25_Msk (0x1UL << BSEC_SFSRx_SFW25_Pos) /*!< 0x02000000 */ #define BSEC_SFSRx_SFW25 BSEC_SFSRx_SFW25_Msk /*!< Shadowed fuse word (25+32*x) */ #define BSEC_SFSRx_SFW26_Pos (26U) #define BSEC_SFSRx_SFW26_Msk (0x1UL << BSEC_SFSRx_SFW26_Pos) /*!< 0x04000000 */ #define BSEC_SFSRx_SFW26 BSEC_SFSRx_SFW26_Msk /*!< Shadowed fuse word (26+32*x) */ #define BSEC_SFSRx_SFW27_Pos (27U) #define BSEC_SFSRx_SFW27_Msk (0x1UL << BSEC_SFSRx_SFW27_Pos) /*!< 0x08000000 */ #define BSEC_SFSRx_SFW27 BSEC_SFSRx_SFW27_Msk /*!< Shadowed fuse word (27+32*x) */ #define BSEC_SFSRx_SFW28_Pos (28U) #define BSEC_SFSRx_SFW28_Msk (0x1UL << BSEC_SFSRx_SFW28_Pos) /*!< 0x10000000 */ #define BSEC_SFSRx_SFW28 BSEC_SFSRx_SFW28_Msk /*!< Shadowed fuse word (28+32*x) */ #define BSEC_SFSRx_SFW29_Pos (29U) #define BSEC_SFSRx_SFW29_Msk (0x1UL << BSEC_SFSRx_SFW29_Pos) /*!< 0x20000000 */ #define BSEC_SFSRx_SFW29 BSEC_SFSRx_SFW29_Msk /*!< Shadowed fuse word (29+32*x) */ #define BSEC_SFSRx_SFW30_Pos (30U) #define BSEC_SFSRx_SFW30_Msk (0x1UL << BSEC_SFSRx_SFW30_Pos) /*!< 0x40000000 */ #define BSEC_SFSRx_SFW30 BSEC_SFSRx_SFW30_Msk /*!< Shadowed fuse word (30+32*x) */ #define BSEC_SFSRx_SFW31_Pos (31U) #define BSEC_SFSRx_SFW31_Msk (0x1UL << BSEC_SFSRx_SFW31_Pos) /*!< 0x80000000 */ #define BSEC_SFSRx_SFW31 BSEC_SFSRx_SFW31_Msk /*!< Shadowed fuse word (31+32*x) */ /****************** Bit definition for BSEC_OTPCR register ******************/ #define BSEC_OTPCR_ADDR_Pos (0U) #define BSEC_OTPCR_ADDR_Msk (0x1FFUL << BSEC_OTPCR_ADDR_Pos) /*!< 0x000001FF */ #define BSEC_OTPCR_ADDR BSEC_OTPCR_ADDR_Msk /*!< Fuse word address */ #define BSEC_OTPCR_PROG_Pos (13U) #define BSEC_OTPCR_PROG_Msk (0x1UL << BSEC_OTPCR_PROG_Pos) /*!< 0x00002000 */ #define BSEC_OTPCR_PROG BSEC_OTPCR_PROG_Msk /*!< Fuse word programming */ #define BSEC_OTPCR_PPLOCK_Pos (14U) #define BSEC_OTPCR_PPLOCK_Msk (0x1UL << BSEC_OTPCR_PPLOCK_Pos) /*!< 0x00004000 */ #define BSEC_OTPCR_PPLOCK BSEC_OTPCR_PPLOCK_Msk /*!< Permanent programming lock */ #define BSEC_OTPCR_LASTCID_Pos (19U) #define BSEC_OTPCR_LASTCID_Msk (0x7UL << BSEC_OTPCR_LASTCID_Pos) /*!< 0x00380000 */ #define BSEC_OTPCR_LASTCID BSEC_OTPCR_LASTCID_Msk /*!< Last CID */ /******************* Bit definition for BSEC_WDR register *******************/ #define BSEC_WDR_WRDATA_Pos (0U) #define BSEC_WDR_WRDATA_Msk (0xFFFFFFFFUL << BSEC_WDR_WRDATA_Pos) /*!< 0xFFFFFFFF */ #define BSEC_WDR_WRDATA BSEC_WDR_WRDATA_Msk /*!< OTP write data */ /**************** Bit definition for BSEC_SCRATCHRx register ****************/ #define BSEC_SCRATCHRx_SDATA_Pos (0U) #define BSEC_SCRATCHRx_SDATA_Msk (0xFFFFFFFFUL << BSEC_SCRATCHRx_SDATA_Pos) /*!< 0xFFFFFFFF */ #define BSEC_SCRATCHRx_SDATA BSEC_SCRATCHRx_SDATA_Msk /*!< Scratch data */ /****************** Bit definition for BSEC_LOCKR register ******************/ #define BSEC_LOCKR_GWLOCK_Pos (0U) #define BSEC_LOCKR_GWLOCK_Msk (0x1UL << BSEC_LOCKR_GWLOCK_Pos) /*!< 0x00000001 */ #define BSEC_LOCKR_GWLOCK BSEC_LOCKR_GWLOCK_Msk /*!< Global write lock */ #define BSEC_LOCKR_HKLOCK_Pos (2U) #define BSEC_LOCKR_HKLOCK_Msk (0x1UL << BSEC_LOCKR_HKLOCK_Pos) /*!< 0x00000004 */ #define BSEC_LOCKR_HKLOCK BSEC_LOCKR_HKLOCK_Msk /*!< Hardware key lock */ /***************** Bit definition for BSEC_JTAGINR register *****************/ #define BSEC_JTAGINR_JDATAIN_Pos (0U) #define BSEC_JTAGINR_JDATAIN_Msk (0xFFFFFFFFUL << BSEC_JTAGINR_JDATAIN_Pos) /*!< 0xFFFFFFFF */ #define BSEC_JTAGINR_JDATAIN BSEC_JTAGINR_JDATAIN_Msk /*!< JTAG input data */ /**************** Bit definition for BSEC_JTAGOUTR register *****************/ #define BSEC_JTAGOUTR_JDATAOUT_Pos (0U) #define BSEC_JTAGOUTR_JDATAOUT_Msk (0xFFFFFFFFUL << BSEC_JTAGOUTR_JDATAOUT_Pos) /*!< 0xFFFFFFFF */ #define BSEC_JTAGOUTR_JDATAOUT BSEC_JTAGOUTR_JDATAOUT_Msk /*!< JTAG output data */ /***************** Bit definition for BSEC_UNMAPR register ******************/ #define BSEC_UNMAPR_UNMAP_Pos (0U) #define BSEC_UNMAPR_UNMAP_Msk (0xFFFFFFFFUL << BSEC_UNMAPR_UNMAP_Pos) /*!< 0xFFFFFFFF */ #define BSEC_UNMAPR_UNMAP BSEC_UNMAPR_UNMAP_Msk /*!< Unmap key */ /******************* Bit definition for BSEC_SR register ********************/ #define BSEC_SR_HVALID_Pos (1U) #define BSEC_SR_HVALID_Msk (0x1UL << BSEC_SR_HVALID_Pos) /*!< 0x00000002 */ #define BSEC_SR_HVALID BSEC_SR_HVALID_Msk /*!< Hardware key valid */ #define BSEC_SR_DBGREQ_Pos (16U) #define BSEC_SR_DBGREQ_Msk (0x1UL << BSEC_SR_DBGREQ_Pos) /*!< 0x00010000 */ #define BSEC_SR_DBGREQ BSEC_SR_DBGREQ_Msk /*!< Debug request */ #define BSEC_SR_NVSTATE_Pos (26U) #define BSEC_SR_NVSTATE_Msk (0x3FUL << BSEC_SR_NVSTATE_Pos) /*!< 0xFC000000 */ #define BSEC_SR_NVSTATE BSEC_SR_NVSTATE_Msk /*!< Non-volatile state */ /****************** Bit definition for BSEC_OTPSR register ******************/ #define BSEC_OTPSR_BUSY_Pos (0U) #define BSEC_OTPSR_BUSY_Msk (0x1UL << BSEC_OTPSR_BUSY_Pos) /*!< 0x00000001 */ #define BSEC_OTPSR_BUSY BSEC_OTPSR_BUSY_Msk /*!< Busy flag */ #define BSEC_OTPSR_INIT_DONE_Pos (1U) #define BSEC_OTPSR_INIT_DONE_Msk (0x1UL << BSEC_OTPSR_INIT_DONE_Pos) /*!< 0x00000002 */ #define BSEC_OTPSR_INIT_DONE BSEC_OTPSR_INIT_DONE_Msk /*!< Initialization done */ #define BSEC_OTPSR_HIDEUP_Pos (2U) #define BSEC_OTPSR_HIDEUP_Msk (0x1UL << BSEC_OTPSR_HIDEUP_Pos) /*!< 0x00000004 */ #define BSEC_OTPSR_HIDEUP BSEC_OTPSR_HIDEUP_Msk /*!< Hide upper fuse words */ #define BSEC_OTPSR_OTPNVIR_Pos (4U) #define BSEC_OTPSR_OTPNVIR_Msk (0x1UL << BSEC_OTPSR_OTPNVIR_Pos) /*!< 0x00000010 */ #define BSEC_OTPSR_OTPNVIR BSEC_OTPSR_OTPNVIR_Msk /*!< OTP not virgin */ #define BSEC_OTPSR_OTPERR_Pos (5U) #define BSEC_OTPSR_OTPERR_Msk (0x1UL << BSEC_OTPSR_OTPERR_Pos) /*!< 0x00000020 */ #define BSEC_OTPSR_OTPERR BSEC_OTPSR_OTPERR_Msk /*!< OTP with error */ #define BSEC_OTPSR_OTPSEC_Pos (6U) #define BSEC_OTPSR_OTPSEC_Msk (0x1UL << BSEC_OTPSR_OTPSEC_Pos) /*!< 0x00000040 */ #define BSEC_OTPSR_OTPSEC BSEC_OTPSR_OTPSEC_Msk /*!< OTP with single error correction */ #define BSEC_OTPSR_PROGFAIL_Pos (16U) #define BSEC_OTPSR_PROGFAIL_Msk (0x1UL << BSEC_OTPSR_PROGFAIL_Pos) /*!< 0x00010000 */ #define BSEC_OTPSR_PROGFAIL BSEC_OTPSR_PROGFAIL_Msk /*!< Programming failed */ #define BSEC_OTPSR_DISTURBF_Pos (17U) #define BSEC_OTPSR_DISTURBF_Msk (0x1UL << BSEC_OTPSR_DISTURBF_Pos) /*!< 0x00020000 */ #define BSEC_OTPSR_DISTURBF BSEC_OTPSR_DISTURBF_Msk /*!< Disturb flag */ #define BSEC_OTPSR_DEDF_Pos (18U) #define BSEC_OTPSR_DEDF_Msk (0x1UL << BSEC_OTPSR_DEDF_Pos) /*!< 0x00040000 */ #define BSEC_OTPSR_DEDF BSEC_OTPSR_DEDF_Msk /*!< Double error detection flag */ #define BSEC_OTPSR_SECF_Pos (19U) #define BSEC_OTPSR_SECF_Msk (0x1UL << BSEC_OTPSR_SECF_Pos) /*!< 0x00080000 */ #define BSEC_OTPSR_SECF BSEC_OTPSR_SECF_Msk /*!< Single error correction flag */ #define BSEC_OTPSR_PPLF_Pos (20U) #define BSEC_OTPSR_PPLF_Msk (0x1UL << BSEC_OTPSR_PPLF_Pos) /*!< 0x00100000 */ #define BSEC_OTPSR_PPLF BSEC_OTPSR_PPLF_Msk /*!< Permanent programming lock flag */ #define BSEC_OTPSR_PPLMF_Pos (21U) #define BSEC_OTPSR_PPLMF_Msk (0x1UL << BSEC_OTPSR_PPLMF_Pos) /*!< 0x00200000 */ #define BSEC_OTPSR_PPLMF BSEC_OTPSR_PPLMF_Msk /*!< Permanent programming lock mismatch flag */ #define BSEC_OTPSR_AMEF_Pos (22U) #define BSEC_OTPSR_AMEF_Msk (0x1UL << BSEC_OTPSR_AMEF_Pos) /*!< 0x00400000 */ #define BSEC_OTPSR_AMEF BSEC_OTPSR_AMEF_Msk /*!< Addresses mismatch error flag */ /***************** Bit definition for BSEC_EPOCHRx register *****************/ #define BSEC_EPOCHRx_EPOCH_Pos (0U) #define BSEC_EPOCHRx_EPOCH_Msk (0xFFFFFFFFUL << BSEC_EPOCHRx_EPOCH_Pos) /*!< 0xFFFFFFFF */ #define BSEC_EPOCHRx_EPOCH BSEC_EPOCHRx_EPOCH_Msk /*!< Epoch */ /**************** Bit definition for BSEC_EPOCHSELR register ****************/ #define BSEC_EPOCHSELR_EPSEL_Pos (0U) #define BSEC_EPOCHSELR_EPSEL_Msk (0x1UL << BSEC_EPOCHSELR_EPSEL_Pos) /*!< 0x00000001 */ #define BSEC_EPOCHSELR_EPSEL BSEC_EPOCHSELR_EPSEL_Msk /*!< Epoch selection */ /****************** Bit definition for BSEC_DBGCR register ******************/ #define BSEC_DBGCR_UNLOCK_Pos (8U) #define BSEC_DBGCR_UNLOCK_Msk (0xFFUL << BSEC_DBGCR_UNLOCK_Pos) /*!< 0x0000FF00 */ #define BSEC_DBGCR_UNLOCK BSEC_DBGCR_UNLOCK_Msk /*!< Non-secure debug authorization */ #define BSEC_DBGCR_AUTH_HDPL_Pos (16U) #define BSEC_DBGCR_AUTH_HDPL_Msk (0xFFUL << BSEC_DBGCR_AUTH_HDPL_Pos) /*!< 0x00FF0000 */ #define BSEC_DBGCR_AUTH_HDPL BSEC_DBGCR_AUTH_HDPL_Msk /*!< Level at which debug may be opened */ #define BSEC_DBGCR_AUTH_SEC_Pos (24U) #define BSEC_DBGCR_AUTH_SEC_Msk (0xFFUL << BSEC_DBGCR_AUTH_SEC_Pos) /*!< 0xFF000000 */ #define BSEC_DBGCR_AUTH_SEC BSEC_DBGCR_AUTH_SEC_Msk /*!< Secure debug authorization */ /*************** Bit definition for BSEC_AP_UNLOCK register *****************/ #define BSEC_AP_UNLOCK_UNLOCK_Pos (0U) #define BSEC_AP_UNLOCK_UNLOCK_Msk (0xFFUL << BSEC_AP_UNLOCK_UNLOCK_Pos) /*!< 0x000000FF */ #define BSEC_AP_UNLOCK_UNLOCK BSEC_AP_UNLOCK_UNLOCK_Msk /*!< Unlock DBG_MCU AP interface */ /***************** Bit definition for BSEC_HDPLSR register ******************/ #define BSEC_HDPLSR_HDPL_Pos (0U) #define BSEC_HDPLSR_HDPL_Msk (0xFFUL << BSEC_HDPLSR_HDPL_Pos) /*!< 0x000000FF */ #define BSEC_HDPLSR_HDPL BSEC_HDPLSR_HDPL_Msk /*!< Current HDPL */ /***************** Bit definition for BSEC_HDPLCR register ******************/ #define BSEC_HDPLCR_INCR_HDPL_Pos (0U) #define BSEC_HDPLCR_INCR_HDPL_Msk (0xFFFFFFFFUL << BSEC_HDPLCR_INCR_HDPL_Pos) /*!< 0xFFFFFFFF */ #define BSEC_HDPLCR_INCR_HDPL BSEC_HDPLCR_INCR_HDPL_Msk /*!< Increment HDPL */ /***************** Bit definition for BSEC_NEXTLR register ******************/ #define BSEC_NEXTLR_INCR_Pos (0U) #define BSEC_NEXTLR_INCR_Msk (0x3UL << BSEC_NEXTLR_INCR_Pos) /*!< 0x00000003 */ #define BSEC_NEXTLR_INCR BSEC_NEXTLR_INCR_Msk /*!< Increment */ /***************** Bit definition for BSEC_WOSCRx register ******************/ #define BSEC_WOSCRx_WOSDATA_Pos (0U) #define BSEC_WOSCRx_WOSDATA_Msk (0xFFFFFFFFUL << BSEC_WOSCRx_WOSDATA_Pos) /*!< 0xFFFFFFFF */ #define BSEC_WOSCRx_WOSDATA BSEC_WOSCRx_WOSDATA_Msk /*!< Write once scratch data */ /****************** Bit definition for BSEC_HRCR register *******************/ #define BSEC_HRCR_HRC_Pos (0U) #define BSEC_HRCR_HRC_Msk (0xFFFFFFFFUL << BSEC_HRCR_HRC_Pos) /*!< 0xFFFFFFFF */ #define BSEC_HRCR_HRC BSEC_HRCR_HRC_Msk /*!< Hot reset counter */ /****************** Bit definition for BSEC_WRCR register *******************/ #define BSEC_WRCR_WRC_Pos (0U) #define BSEC_WRCR_WRC_Msk (0xFFFFFFFFUL << BSEC_WRCR_WRC_Pos) /*!< 0xFFFFFFFF */ #define BSEC_WRCR_WRC BSEC_WRCR_WRC_Msk /*!< Warm reset counter */ /******************************************************************************/ /* */ /* CACHEAXI */ /* */ /******************************************************************************/ /**************** Bit definition for CACHEAXI_CR1 register ******************/ #define CACHEAXI_CR1_EN_Pos (0U) #define CACHEAXI_CR1_EN_Msk (0x1UL << CACHEAXI_CR1_EN_Pos) /*!< 0x00000001 */ #define CACHEAXI_CR1_EN CACHEAXI_CR1_EN_Msk /*!< Enable */ #define CACHEAXI_CR1_CACHEINV_Pos (1U) #define CACHEAXI_CR1_CACHEINV_Msk (0x1UL << CACHEAXI_CR1_CACHEINV_Pos) /*!< 0x00000002 */ #define CACHEAXI_CR1_CACHEINV CACHEAXI_CR1_CACHEINV_Msk /*!< Cache invalidation */ #define CACHEAXI_CR1_RHITMEN_Pos (16U) #define CACHEAXI_CR1_RHITMEN_Msk (0x1UL << CACHEAXI_CR1_RHITMEN_Pos) /*!< 0x00010000 */ #define CACHEAXI_CR1_RHITMEN CACHEAXI_CR1_RHITMEN_Msk /*!< Read Hit monitor enable */ #define CACHEAXI_CR1_RMISSMEN_Pos (17U) #define CACHEAXI_CR1_RMISSMEN_Msk (0x1UL << CACHEAXI_CR1_RMISSMEN_Pos) /*!< 0x00020000 */ #define CACHEAXI_CR1_RMISSMEN CACHEAXI_CR1_RMISSMEN_Msk /*!< Read Miss monitor enable */ #define CACHEAXI_CR1_RHITMRST_Pos (18U) #define CACHEAXI_CR1_RHITMRST_Msk (0x1UL << CACHEAXI_CR1_RHITMRST_Pos) /*!< 0x00040000 */ #define CACHEAXI_CR1_RHITMRST CACHEAXI_CR1_RHITMRST_Msk /*!< Read Hit monitor reset */ #define CACHEAXI_CR1_RMISSMRST_Pos (19U) #define CACHEAXI_CR1_RMISSMRST_Msk (0x1UL << CACHEAXI_CR1_RMISSMRST_Pos) /*!< 0x00080000 */ #define CACHEAXI_CR1_RMISSMRST CACHEAXI_CR1_RMISSMRST_Msk /*!< Read Miss monitor reset */ #define CACHEAXI_CR1_WHITMEN_Pos (20U) #define CACHEAXI_CR1_WHITMEN_Msk (0x1UL << CACHEAXI_CR1_WHITMEN_Pos) /*!< 0x00100000 */ #define CACHEAXI_CR1_WHITMEN CACHEAXI_CR1_WHITMEN_Msk /*!< Write Hit monitor enable */ #define CACHEAXI_CR1_WMISSMEN_Pos (21U) #define CACHEAXI_CR1_WMISSMEN_Msk (0x1UL << CACHEAXI_CR1_WMISSMEN_Pos) /*!< 0x00200000 */ #define CACHEAXI_CR1_WMISSMEN CACHEAXI_CR1_WMISSMEN_Msk /*!< Write Miss monitor enable */ #define CACHEAXI_CR1_WHITMRST_Pos (22U) #define CACHEAXI_CR1_WHITMRST_Msk (0x1UL << CACHEAXI_CR1_WHITMRST_Pos) /*!< 0x00400000 */ #define CACHEAXI_CR1_WHITMRST CACHEAXI_CR1_WHITMRST_Msk /*!< Write Hit monitor reset */ #define CACHEAXI_CR1_WMISSMRST_Pos (23U) #define CACHEAXI_CR1_WMISSMRST_Msk (0x1UL << CACHEAXI_CR1_WMISSMRST_Pos) /*!< 0x00800000 */ #define CACHEAXI_CR1_WMISSMRST CACHEAXI_CR1_WMISSMRST_Msk /*!< Write Miss monitor reset */ #define CACHEAXI_CR1_RAMMEN_Pos (24U) #define CACHEAXI_CR1_RAMMEN_Msk (0x1UL << CACHEAXI_CR1_RAMMEN_Pos) /*!< 0x01000000 */ #define CACHEAXI_CR1_RAMMEN CACHEAXI_CR1_RAMMEN_Msk /*!< Read-allocate miss monitor enable */ #define CACHEAXI_CR1_WAMMEN_Pos (25U) #define CACHEAXI_CR1_WAMMEN_Msk (0x1UL << CACHEAXI_CR1_WAMMEN_Pos) /*!< 0x02000000 */ #define CACHEAXI_CR1_WAMMEN CACHEAXI_CR1_WAMMEN_Msk /*!< Write-allocate miss monitor enable */ #define CACHEAXI_CR1_RAMMRST_Pos (26U) #define CACHEAXI_CR1_RAMMRST_Msk (0x1UL << CACHEAXI_CR1_RAMMRST_Pos) /*!< 0x04000000 */ #define CACHEAXI_CR1_RAMMRST CACHEAXI_CR1_RAMMRST_Msk /*!< Read-allocate miss monitor reset */ #define CACHEAXI_CR1_WAMMRST_Pos (27U) #define CACHEAXI_CR1_WAMMRST_Msk (0x1UL << CACHEAXI_CR1_WAMMRST_Pos) /*!< 0x08000000 */ #define CACHEAXI_CR1_WAMMRST CACHEAXI_CR1_WAMMRST_Msk /*!< Write-allocate miss monitor reset */ #define CACHEAXI_CR1_WTMEN_Pos (28U) #define CACHEAXI_CR1_WTMEN_Msk (0x1UL << CACHEAXI_CR1_WTMEN_Pos) /*!< 0x10000000 */ #define CACHEAXI_CR1_WTMEN CACHEAXI_CR1_WTMEN_Msk /*!< Write-through monitor enable */ #define CACHEAXI_CR1_EVIMEN_Pos (29U) #define CACHEAXI_CR1_EVIMEN_Msk (0x1UL << CACHEAXI_CR1_EVIMEN_Pos) /*!< 0x20000000 */ #define CACHEAXI_CR1_EVIMEN CACHEAXI_CR1_EVIMEN_Msk /*!< Eviction monitor enable */ #define CACHEAXI_CR1_WTMRST_Pos (30U) #define CACHEAXI_CR1_WTMRST_Msk (0x1UL << CACHEAXI_CR1_WTMRST_Pos) /*!< 0x40000000 */ #define CACHEAXI_CR1_WTMRST CACHEAXI_CR1_WTMRST_Msk /*!< Write-through monitor reset */ #define CACHEAXI_CR1_EVIMRST_Pos (31U) #define CACHEAXI_CR1_EVIMRST_Msk (0x1UL << CACHEAXI_CR1_EVIMRST_Pos) /*!< 0x80000000 */ #define CACHEAXI_CR1_EVIMRST CACHEAXI_CR1_EVIMRST_Msk /*!< Eviction monitor reset */ /****************** Bit definition for CACHEAXI_SR register *******************/ #define CACHEAXI_SR_BUSYF_Pos (0U) #define CACHEAXI_SR_BUSYF_Msk (0x1UL << CACHEAXI_SR_BUSYF_Pos) /*!< 0x00000001 */ #define CACHEAXI_SR_BUSYF CACHEAXI_SR_BUSYF_Msk /*!< Busy flag */ #define CACHEAXI_SR_BSYENDF_Pos (1U) #define CACHEAXI_SR_BSYENDF_Msk (0x1UL << CACHEAXI_SR_BSYENDF_Pos) /*!< 0x00000002 */ #define CACHEAXI_SR_BSYENDF CACHEAXI_SR_BSYENDF_Msk /*!< Busy end flag */ #define CACHEAXI_SR_ERRF_Pos (2U) #define CACHEAXI_SR_ERRF_Msk (0x1UL << CACHEAXI_SR_ERRF_Pos) /*!< 0x00000004 */ #define CACHEAXI_SR_ERRF CACHEAXI_SR_ERRF_Msk /*!< Cache error flag */ #define CACHEAXI_SR_BUSYCMDF_Pos (3U) #define CACHEAXI_SR_BUSYCMDF_Msk (0x1UL << CACHEAXI_SR_BUSYCMDF_Pos) /*!< 0x00000008 */ #define CACHEAXI_SR_BUSYCMDF CACHEAXI_SR_BUSYCMDF_Msk /*!< Busy command flag */ #define CACHEAXI_SR_CMDENDF_Pos (4U) #define CACHEAXI_SR_CMDENDF_Msk (0x1UL << CACHEAXI_SR_CMDENDF_Pos) /*!< 0x00000010 */ #define CACHEAXI_SR_CMDENDF CACHEAXI_SR_CMDENDF_Msk /*!< Command end flag */ /****************** Bit definition for CACHEAXI_IER register ******************/ #define CACHEAXI_IER_BSYENDIE_Pos (1U) #define CACHEAXI_IER_BSYENDIE_Msk (0x1UL << CACHEAXI_IER_BSYENDIE_Pos) /*!< 0x00000002 */ #define CACHEAXI_IER_BSYENDIE CACHEAXI_IER_BSYENDIE_Msk /*!< Busy end interrupt enable */ #define CACHEAXI_IER_ERRIE_Pos (2U) #define CACHEAXI_IER_ERRIE_Msk (0x1UL << CACHEAXI_IER_ERRIE_Pos) /*!< 0x00000004 */ #define CACHEAXI_IER_ERRIE CACHEAXI_IER_ERRIE_Msk /*!< Cache error interrupt enable */ #define CACHEAXI_IER_CMDENDIE_Pos (4U) #define CACHEAXI_IER_CMDENDIE_Msk (0x1UL << CACHEAXI_IER_CMDENDIE_Pos) /*!< 0x00000010 */ #define CACHEAXI_IER_CMDENDIE CACHEAXI_IER_CMDENDIE_Msk /*!< Command end interrupt enable */ /****************** Bit definition for CACHEAXI_FCR register ******************/ #define CACHEAXI_FCR_CBSYENDF_Pos (1U) #define CACHEAXI_FCR_CBSYENDF_Msk (0x1UL << CACHEAXI_FCR_CBSYENDF_Pos) /*!< 0x00000002 */ #define CACHEAXI_FCR_CBSYENDF CACHEAXI_FCR_CBSYENDF_Msk /*!< Busy end flag clear */ #define CACHEAXI_FCR_CERRF_Pos (2U) #define CACHEAXI_FCR_CERRF_Msk (0x1UL << CACHEAXI_FCR_CERRF_Pos) /*!< 0x00000004 */ #define CACHEAXI_FCR_CERRF CACHEAXI_FCR_CERRF_Msk /*!< Cache error flag clear */ #define CACHEAXI_FCR_CCMDENDF_Pos (4U) #define CACHEAXI_FCR_CCMDENDF_Msk (0x1UL << CACHEAXI_FCR_CCMDENDF_Pos) /*!< 0x00000010 */ #define CACHEAXI_FCR_CCMDENDF CACHEAXI_FCR_CCMDENDF_Msk /*!< Command end flag clear */ /****************** Bit definition for CACHEAXI_RHMONR register ****************/ #define CACHEAXI_RHMONR_RHITMON_Pos (0U) #define CACHEAXI_RHMONR_RHITMON_Msk (0xFFFFFFFFUL << CACHEAXI_RHMONR_RHITMON_Pos) /*!< 0xFFFFFFFF */ #define CACHEAXI_RHMONR_RHITMON CACHEAXI_RHMONR_RHITMON_Msk /*!< Cache read hit monitor register */ /****************** Bit definition for CACHEAXI_RMMONR register ****************/ #define CACHEAXI_RMMONR_RMISSMON_Pos (0U) #define CACHEAXI_RMMONR_RMISSMON_Msk (0xFFFFFFFFUL << CACHEAXI_RMMONR_RMISSMON_Pos) /*!< 0xFFFFFFFF */ #define CACHEAXI_RMMONR_RMISSMON CACHEAXI_RMMONR_RMISSMON_Msk /*!< Cache read miss monitor register */ /****************** Bit definition for CACHEAXI_RAMMONR register ****************/ #define CACHEAXI_RAMMONR_RAMMON_Pos (0U) #define CACHEAXI_RAMMONR_RAMMON_Msk (0xFFFFFFFFUL << CACHEAXI_RAMMONR_RAMMON_Pos) /*!< 0xFFFFFFFF */ #define CACHEAXI_RAMMONR_RAMMON CACHEAXI_RAMMONR_RAMMON_Msk /*!< Cache read-allocate miss monitor counter */ /****************** Bit definition for CACHEAXI_EVIMONR register ****************/ #define CACHEAXI_EVIMONR_EVIMON_Pos (0U) #define CACHEAXI_EVIMONR_EVIMON_Msk (0xFFFFFFFFUL << CACHEAXI_EVIMONR_EVIMON_Pos) /*!< 0xFFFFFFFF */ #define CACHEAXI_EVIMONR_EVIMON CACHEAXI_EVIMONR_EVIMON_Msk /*!< Cache eviction monitor counter */ /****************** Bit definition for CACHEAXI_WHMONR register ****************/ #define CACHEAXI_WHMONR_WHITMON_Pos (0U) #define CACHEAXI_WHMONR_WHITMON_Msk (0xFFFFFFFFUL << CACHEAXI_WHMONR_WHITMON_Pos) /*!< 0xFFFFFFFF */ #define CACHEAXI_WHMONR_WHITMON CACHEAXI_WHMONR_WHITMON_Msk /*!< Cache write hit monitor register */ /****************** Bit definition for CACHEAXI_WMMONR register ****************/ #define CACHEAXI_WMMONR_WMISSMON_Pos (0U) #define CACHEAXI_WMMONR_WMISSMON_Msk (0xFFFFFFFFUL << CACHEAXI_WMMONR_WMISSMON_Pos) /*!< 0xFFFFFFFF */ #define CACHEAXI_WMMONR_WMISSMON CACHEAXI_WMMONR_WMISSMON_Msk /*!< Cache write miss monitor register */ /****************** Bit definition for CACHEAXI_WAMMONR register ****************/ #define CACHEAXI_WAMMONR_WAMMON_Pos (0U) #define CACHEAXI_WAMMONR_WAMMON_Msk (0xFFFFFFFFUL << CACHEAXI_WAMMONR_WAMMON_Pos) /*!< 0xFFFFFFFF */ #define CACHEAXI_WAMMONR_WAMMON CACHEAXI_WAMMONR_WAMMON_Msk /*!< Cache write-allocate miss monitor register */ /****************** Bit definition for CACHEAXI_WTMONR register ****************/ #define CACHEAXI_WTMONR_WTMON_Pos (0U) #define CACHEAXI_WTMONR_WTMON_Msk (0xFFFFFFFFUL << CACHEAXI_WTMONR_WTMON_Pos) /*!< 0xFFFFFFFF */ #define CACHEAXI_WTMONR_WTMON CACHEAXI_WTMONR_WTMON_Msk /*!< Cache write-through monitor register */ /**************** Bit definition for CACHEAXI_CR2 register ******************/ #define CACHEAXI_CR2_STARTCMD_Pos (0U) #define CACHEAXI_CR2_STARTCMD_Msk (0x1UL << CACHEAXI_CR2_STARTCMD_Pos) /*!< 0x00000001 */ #define CACHEAXI_CR2_STARTCMD CACHEAXI_CR2_STARTCMD_Msk /*!< Starts maintenance range command */ #define CACHEAXI_CR2_CACHECMD_Pos (1U) #define CACHEAXI_CR2_CACHECMD_Msk (0x3UL << CACHEAXI_CR2_CACHECMD_Pos) /*!< 0x00000006 */ #define CACHEAXI_CR2_CACHECMD CACHEAXI_CR2_CACHECMD_Msk /*!< Cache command maintenance operation */ #define CACHEAXI_CR2_CACHECMD_0 (0x1UL << CACHEAXI_CR2_CACHECMD_Pos) /*!< 0x00000002 */ #define CACHEAXI_CR2_CACHECMD_1 (0x2UL << CACHEAXI_CR2_CACHECMD_Pos) /*!< 0x00000004 */ /****************** Bit definition for CACHEAXI_CMDRSADDRR register ****************/ #define CACHEAXI_CMDRSADDRR_CMDSTARTADDR_Pos (0U) #define CACHEAXI_CMDRSADDRR_CMDSTARTADDR_Msk (0xFFFFFFC0UL << CACHEAXI_CMDRSADDRR_CMDSTARTADDR_Pos) /*!< 0xFFFFFFC0 */ #define CACHEAXI_CMDRSADDRR_CMDSTARTADDR CACHEAXI_CMDRSADDRR_CMDSTARTADDR_Msk /*!< Command start address */ /****************** Bit definition for CACHEAXI_CMDREADDRR register ****************/ #define CACHEAXI_CMDREADDRR_CMDENDADDR_Pos (0U) #define CACHEAXI_CMDREADDRR_CMDENDADDR_Msk (0xFFFFFFC0UL << CACHEAXI_CMDREADDRR_CMDENDADDR_Pos) /*!< 0xFFFFFFC0 */ #define CACHEAXI_CMDREADDRR_CMDENDADDR CACHEAXI_CMDREADDRR_CMDENDADDR_Msk /*!< Command end address */ /******************************************************************************/ /* */ /* CRC calculation unit */ /* */ /******************************************************************************/ /******************* Bit definition for CRC_DR register *********************/ #define CRC_DR_DR_Pos (0U) #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ /******************* Bit definition for CRC_IDR register ********************/ #define CRC_IDR_IDR_Pos (0U) #define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ /******************** Bit definition for CRC_CR register ********************/ #define CRC_CR_RESET_Pos (0U) #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ #define CRC_CR_POLYSIZE_Pos (3U) #define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ #define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ #define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ #define CRC_CR_REV_IN_Pos (5U) #define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ #define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ #define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ #define CRC_CR_REV_OUT_Pos (7U) #define CRC_CR_REV_OUT_Msk (0x3UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000180 */ #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ #define CRC_CR_REV_OUT_0 (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ #define CRC_CR_REV_OUT_1 (0x2UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000100 */ #define CRC_CR_RTYPE_IN_Pos (9U) #define CRC_CR_RTYPE_IN_Msk (0x1UL << CRC_CR_RTYPE_IN_Pos) /*!< 0x00000200 */ #define CRC_CR_RTYPE_IN CRC_CR_RTYPE_IN_Msk /*!< Reverse type input */ #define CRC_CR_RTYPE_OUT_Pos (10U) #define CRC_CR_RTYPE_OUT_Msk (0x1UL << CRC_CR_RTYPE_OUT_Pos) /*!< 0x00000400 */ #define CRC_CR_RTYPE_OUT CRC_CR_RTYPE_OUT_Msk /*!< Reverse type output*/ /******************* Bit definition for CRC_INIT register *******************/ #define CRC_INIT_INIT_Pos (0U) #define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ /******************* Bit definition for CRC_POL register ********************/ #define CRC_POL_POL_Pos (0U) #define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ /******************************************************************************/ /* */ /* Cryp Processor */ /* */ /******************************************************************************/ /******************* Bits definition for CRYP_CR register ********************/ #define CRYP_CR_ALGODIR_Pos (2U) #define CRYP_CR_ALGODIR_Msk (0x1UL << CRYP_CR_ALGODIR_Pos) /*!< 0x00000004 */ #define CRYP_CR_ALGODIR CRYP_CR_ALGODIR_Msk /*!< Algorithm direction (Encrypt/Decrypt) */ #define CRYP_CR_ALGOMODE_Pos (3U) #define CRYP_CR_ALGOMODE_Msk (0x10007UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00080038 */ #define CRYP_CR_ALGOMODE CRYP_CR_ALGOMODE_Msk /*!< Algorithm mode */ #define CRYP_CR_ALGOMODE_0 (0x00001UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */ #define CRYP_CR_ALGOMODE_1 (0x00002UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */ #define CRYP_CR_ALGOMODE_2 (0x00004UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */ #define CRYP_CR_ALGOMODE_3 (0x10000UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00080000 */ #define CRYP_CR_ALGOMODE_AES_ECB_Pos (5U) #define CRYP_CR_ALGOMODE_AES_ECB_Msk (0x1UL << CRYP_CR_ALGOMODE_AES_ECB_Pos) /*!< 0x00000020 */ #define CRYP_CR_ALGOMODE_AES_ECB CRYP_CR_ALGOMODE_AES_ECB_Msk #define CRYP_CR_ALGOMODE_AES_CBC_Pos (3U) #define CRYP_CR_ALGOMODE_AES_CBC_Msk (0x5UL << CRYP_CR_ALGOMODE_AES_CBC_Pos) /*!< 0x00000028 */ #define CRYP_CR_ALGOMODE_AES_CBC CRYP_CR_ALGOMODE_AES_CBC_Msk #define CRYP_CR_ALGOMODE_AES_CTR_Pos (4U) #define CRYP_CR_ALGOMODE_AES_CTR_Msk (0x3UL << CRYP_CR_ALGOMODE_AES_CTR_Pos) /*!< 0x00000030 */ #define CRYP_CR_ALGOMODE_AES_CTR CRYP_CR_ALGOMODE_AES_CTR_Msk #define CRYP_CR_ALGOMODE_AES_KEY_Pos (3U) #define CRYP_CR_ALGOMODE_AES_KEY_Msk (0x7UL << CRYP_CR_ALGOMODE_AES_KEY_Pos) /*!< 0x00000038 */ #define CRYP_CR_ALGOMODE_AES_KEY CRYP_CR_ALGOMODE_AES_KEY_Msk #define CRYP_CR_ALGOMODE_AES_GCM_Pos (19U) #define CRYP_CR_ALGOMODE_AES_GCM_Msk (0x1UL << CRYP_CR_ALGOMODE_AES_GCM_Pos) /*!< 0x00080000 */ #define CRYP_CR_ALGOMODE_AES_GCM CRYP_CR_ALGOMODE_AES_GCM_Msk #define CRYP_CR_ALGOMODE_AES_CCM_Pos (3U) #define CRYP_CR_ALGOMODE_AES_CCM_Msk (0x10001UL << CRYP_CR_ALGOMODE_AES_CCM_Pos) /*!< 0x00080008 */ #define CRYP_CR_ALGOMODE_AES_CCM CRYP_CR_ALGOMODE_AES_CCM_Msk #define CRYP_CR_DATATYPE_Pos (6U) #define CRYP_CR_DATATYPE_Msk (0x3UL << CRYP_CR_DATATYPE_Pos) /*!< 0x000000C0 */ #define CRYP_CR_DATATYPE CRYP_CR_DATATYPE_Msk /*!< Data Type selection */ #define CRYP_CR_DATATYPE_0 (0x1UL << CRYP_CR_DATATYPE_Pos) /*!< 0x00000040 */ #define CRYP_CR_DATATYPE_1 (0x2UL << CRYP_CR_DATATYPE_Pos) /*!< 0x00000080 */ #define CRYP_CR_KEYSIZE_Pos (8U) #define CRYP_CR_KEYSIZE_Msk (0x3UL << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000300 */ #define CRYP_CR_KEYSIZE CRYP_CR_KEYSIZE_Msk /*!< Key Size selection */ #define CRYP_CR_KEYSIZE_0 (0x1UL << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000100 */ #define CRYP_CR_KEYSIZE_1 (0x2UL << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000200 */ #define CRYP_CR_FFLUSH_Pos (14U) #define CRYP_CR_FFLUSH_Msk (0x1UL << CRYP_CR_FFLUSH_Pos) /*!< 0x00004000 */ #define CRYP_CR_FFLUSH CRYP_CR_FFLUSH_Msk /*!< CRYP FIFO Flush */ #define CRYP_CR_CRYPEN_Pos (15U) #define CRYP_CR_CRYPEN_Msk (0x1UL << CRYP_CR_CRYPEN_Pos) /*!< 0x00008000 */ #define CRYP_CR_CRYPEN CRYP_CR_CRYPEN_Msk /*!< CRYP processor enable */ #define CRYP_CR_GCM_CCMPH_Pos (16U) #define CRYP_CR_GCM_CCMPH_Msk (0x3UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00030000 */ #define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk /*!< GCM or CCM Phase selection */ #define CRYP_CR_GCM_CCMPH_0 (0x1UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */ #define CRYP_CR_GCM_CCMPH_1 (0x2UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */ #define CRYP_CR_NPBLB_Pos (20U) #define CRYP_CR_NPBLB_Msk (0xFUL << CRYP_CR_NPBLB_Pos) /*!< 0x00F00000 */ #define CRYP_CR_NPBLB CRYP_CR_NPBLB_Msk /*!< Number of Padding Bytes in Last Block of payload */ #define CRYP_CR_KMOD_Pos (24U) #define CRYP_CR_KMOD_Msk (0x3UL << CRYP_CR_KMOD_Pos) /*!< 0x03000000 */ #define CRYP_CR_KMOD CRYP_CR_KMOD_Msk /*!< Key mode selection */ #define CRYP_CR_KMOD_0 (0x1UL << CRYP_CR_KMOD_Pos) /*!< 0x01000000 */ #define CRYP_CR_KMOD_1 (0x2UL << CRYP_CR_KMOD_Pos) /*!< 0x02000000 */ #define CRYP_CR_IPRST_Pos (31U) #define CRYP_CR_IPRST_Msk (0x1UL << CRYP_CR_IPRST_Pos) /*!< 0x80000000 */ #define CRYP_CR_IPRST CRYP_CR_IPRST_Msk /*!< CRYP peripheral software reset */ /****************** Bits definition for CRYP_SR register *********************/ #define CRYP_SR_IFEM_Pos (0U) #define CRYP_SR_IFEM_Msk (0x1UL << CRYP_SR_IFEM_Pos) /*!< 0x00000001 */ #define CRYP_SR_IFEM CRYP_SR_IFEM_Msk /*!< Input FIFO empty flag */ #define CRYP_SR_IFNF_Pos (1U) #define CRYP_SR_IFNF_Msk (0x1UL << CRYP_SR_IFNF_Pos) /*!< 0x00000002 */ #define CRYP_SR_IFNF CRYP_SR_IFNF_Msk /*!< Input FIFO not full flag */ #define CRYP_SR_OFNE_Pos (2U) #define CRYP_SR_OFNE_Msk (0x1UL << CRYP_SR_OFNE_Pos) /*!< 0x00000004 */ #define CRYP_SR_OFNE CRYP_SR_OFNE_Msk /*!< Output FIFO not empty flag */ #define CRYP_SR_OFFU_Pos (3U) #define CRYP_SR_OFFU_Msk (0x1UL << CRYP_SR_OFFU_Pos) /*!< 0x00000008 */ #define CRYP_SR_OFFU CRYP_SR_OFFU_Msk /*!< Output FIFO full flag */ #define CRYP_SR_BUSY_Pos (4U) #define CRYP_SR_BUSY_Msk (0x1UL << CRYP_SR_BUSY_Pos) /*!< 0x00000010 */ #define CRYP_SR_BUSY CRYP_SR_BUSY_Msk /*!< Busy bit */ #define CRYP_SR_KERF_Pos (6U) #define CRYP_SR_KERF_Msk (0x1UL << CRYP_SR_KERF_Pos) /*!< 0x00000040 */ #define CRYP_SR_KERF CRYP_SR_KERF_Msk /*!< Key error flag */ #define CRYP_SR_KEYVALID_Pos (7U) #define CRYP_SR_KEYVALID_Msk (0x1UL << CRYP_SR_KEYVALID_Pos) /*!< 0x00000080 */ #define CRYP_SR_KEYVALID CRYP_SR_KEYVALID_Msk /*!< Key valid flag */ /******************* Bit definition for CRYP_DIN register *******************/ #define CRYP_DIN_DATAIN_Pos (0U) #define CRYP_DIN_DATAIN_Msk (0xFFFFFFFFUL << CRYP_DIN_DATAIN_Pos) /*!< 0xFFFFFFFF */ #define CRYP_DIN_DATAIN CRYP_DIN_DATAIN_Msk /*!< CRYP Data Input */ /******************* Bit definition for CRYP_DIN register *******************/ #define CRYP_DOUT_DATAOUT_Pos (0U) #define CRYP_DOUT_DATAOUT_Msk (0xFFFFFFFFUL << CRYP_DOUT_DATAOUT_Pos) /*!< 0xFFFFFFFF */ #define CRYP_DOUT_DATAOUT CRYP_DOUT_DATAOUT_Msk /*!< CRYP Data Output */ /****************** Bits definition for CRYP_DMACR register ******************/ #define CRYP_DMACR_DIEN_Pos (0U) #define CRYP_DMACR_DIEN_Msk (0x1UL << CRYP_DMACR_DIEN_Pos) /*!< 0x00000001 */ #define CRYP_DMACR_DIEN CRYP_DMACR_DIEN_Msk /*!< DMA Input Enable */ #define CRYP_DMACR_DOEN_Pos (1U) #define CRYP_DMACR_DOEN_Msk (0x1UL << CRYP_DMACR_DOEN_Pos) /*!< 0x00000002 */ #define CRYP_DMACR_DOEN CRYP_DMACR_DOEN_Msk /*!< DMA Output Enable */ /***************** Bits definition for CRYP_IMSCR register ******************/ #define CRYP_IMSCR_INIM_Pos (0U) #define CRYP_IMSCR_INIM_Msk (0x1UL << CRYP_IMSCR_INIM_Pos) /*!< 0x00000001 */ #define CRYP_IMSCR_INIM CRYP_IMSCR_INIM_Msk /*!< Input FIFO service interrupt mask */ #define CRYP_IMSCR_OUTIM_Pos (1U) #define CRYP_IMSCR_OUTIM_Msk (0x1UL << CRYP_IMSCR_OUTIM_Pos) /*!< 0x00000002 */ #define CRYP_IMSCR_OUTIM CRYP_IMSCR_OUTIM_Msk /*!< Output FIFO service interrupt mask */ /****************** Bits definition for CRYP_RISR register *******************/ #define CRYP_RISR_INRIS_Pos (0U) #define CRYP_RISR_INRIS_Msk (0x1UL << CRYP_RISR_INRIS_Pos) /*!< 0x00000001 */ #define CRYP_RISR_INRIS CRYP_RISR_INRIS_Msk /*!< Input FIFO service raw interrupt status */ #define CRYP_RISR_OUTRIS_Pos (1U) #define CRYP_RISR_OUTRIS_Msk (0x1UL << CRYP_RISR_OUTRIS_Pos) /*!< 0x00000002 */ #define CRYP_RISR_OUTRIS CRYP_RISR_OUTRIS_Msk /*!< Output FIFO service raw interrupt mask */ /****************** Bits definition for CRYP_MISR register *******************/ #define CRYP_MISR_INMIS_Pos (0U) #define CRYP_MISR_INMIS_Msk (0x1UL << CRYP_MISR_INMIS_Pos) /*!< 0x00000001 */ #define CRYP_MISR_INMIS CRYP_MISR_INMIS_Msk /*!< Input FIFO service masked interrupt status */ #define CRYP_MISR_OUTMIS_Pos (1U) #define CRYP_MISR_OUTMIS_Msk (0x1UL << CRYP_MISR_OUTMIS_Pos) /*!< 0x00000002 */ #define CRYP_MISR_OUTMIS CRYP_MISR_OUTMIS_Msk /*!< Output FIFO service masked interrupt status */ /******************* Bit definition for CRYP_K0LR register ******************/ #define CRYP_K0LR_K_Pos (0U) #define CRYP_K0LR_K_Msk (0xFFFFFFFFUL << CRYP_K0LR_K_Pos) /*!< 0xFFFFFFFF */ #define CRYP_K0LR_K CRYP_K0LR_K_Msk /*!< AES key bit x (x= 224 to 255) */ /******************* Bit definition for CRYP_K0RR register ******************/ #define CRYP_K0RR_K_Pos (0U) #define CRYP_K0RR_K_Msk (0xFFFFFFFFUL << CRYP_K0RR_K_Pos) /*!< 0xFFFFFFFF */ #define CRYP_K0RR_K CRYP_K0RR_K_Msk /*!< AES key bit x (x= 192 to 223) */ /******************* Bit definition for CRYP_IV1LR register ******************/ #define CRYP_IV1LR_K_Pos (0U) #define CRYP_IV1LR_K_Msk (0xFFFFFFFFUL << CRYP_IV1LR_K_Pos) /*!< 0xFFFFFFFF */ #define CRYP_IV1LR_K CRYP_IV1LR_K_Msk /*!< AES key bit x (x= 160 to 291) */ /******************* Bit definition for CRYP_IV1RR register ******************/ #define CRYP_IV1RR_K_Pos (0U) #define CRYP_IV1RR_K_Msk (0xFFFFFFFFUL << CRYP_IV1RR_K_Pos) /*!< 0xFFFFFFFF */ #define CRYP_IV1RR_K CRYP_IV1RR_K_Msk /*!< AES key bit x (x= 128 to 159) */ /******************* Bit definition for CRYP_K2LR register ******************/ #define CRYP_K2LR_K_Pos (0U) #define CRYP_K2LR_K_Msk (0xFFFFFFFFUL << CRYP_K2LR_K_Pos) /*!< 0xFFFFFFFF */ #define CRYP_K2LR_K CRYP_K2LR_K_Msk /*!< AES key bit x (x= 96 to 127) */ /******************* Bit definition for CRYP_K2RR register ******************/ #define CRYP_K2RR_K_Pos (0U) #define CRYP_K2RR_K_Msk (0xFFFFFFFFUL << CRYP_K2RR_K_Pos) /*!< 0xFFFFFFFF */ #define CRYP_K2RR_K CRYP_K2RR_K_Msk /*!< AES key bit x (x= 64 to 95) */ /******************* Bit definition for CRYP_K3LR register ******************/ #define CRYP_K3LR_K_Pos (0U) #define CRYP_K3LR_K_Msk (0xFFFFFFFFUL << CRYP_K3LR_K_Pos) /*!< 0xFFFFFFFF */ #define CRYP_K3LR_K CRYP_K3LR_K_Msk /*!< AES key bit x (x= 32 to 63) */ /******************* Bit definition for CRYP_K3RR register ******************/ #define CRYP_K3RR_K_Pos (0U) #define CRYP_K3RR_K_Msk (0xFFFFFFFFUL << CRYP_K3RR_K_Pos) /*!< 0xFFFFFFFF */ #define CRYP_K3RR_K CRYP_K3RR_K_Msk /*!< AES key bit x (x= 0 to 31) */ /******************* Bit definition for CRYP_IV0LR register ******************/ #define CRYP_IV0LR_IV_Pos (0U) #define CRYP_IV0LR_IV_Msk (0xFFFFFFFFUL << CRYP_IV0LR_IV_Pos) /*!< 0xFFFFFFFF */ #define CRYP_IV0LR_IV CRYP_IV0LR_IV_Msk /*!< Initialization vector bit x (x= 0 to 31) */ /******************* Bit definition for CRYP_IV0RR register ******************/ #define CRYP_IV0RR_IV_Pos (0U) #define CRYP_IV0RR_IV_Msk (0xFFFFFFFFUL << CRYP_IV0RR_IV_Pos) /*!< 0xFFFFFFFF */ #define CRYP_IV0RR_IV CRYP_IV0RR_IV_Msk /*!< Initialization vector bit x (x= 32 to 63) */ /******************* Bit definition for CRYP_IV1LR register ******************/ #define CRYP_IV1LR_IV_Pos (0U) #define CRYP_IV1LR_IV_Msk (0xFFFFFFFFUL << CRYP_IV1LR_IV_Pos) /*!< 0xFFFFFFFF */ #define CRYP_IV1LR_IV CRYP_IV1LR_IV_Msk /*!< Initialization vector bit x (x= 64 to 95) */ /******************* Bit definition for CRYP_IV1RR register ******************/ #define CRYP_IV1RR_IV_Pos (0U) #define CRYP_IV1RR_IV_Msk (0xFFFFFFFFUL << CRYP_IV1RR_IV_Pos) /*!< 0xFFFFFFFF */ #define CRYP_IV1RR_IV CRYP_IV1RR_IV_Msk /*!< Initialization vector bit x (x= 96 to 127) */ /******************* Bit definition for CRYP_CSGCMCCM0R register ******************/ #define CRYP_CSGCMCCM0R_CSGCMCCM0_Pos (0U) #define CRYP_CSGCMCCM0R_CSGCMCCM0_Msk (0xFFFFFFFFUL << CRYP_CSGCMCCM0R_CSGCMCCM0_Pos) /*!< 0xFFFFFFFF */ #define CRYP_CSGCMCCM0R_CSGCMCCM0 CRYP_CSGCMCCM0R_CSGCMCCM0_Msk /*!< CRYP internal state registers for GCM, GMAC and CCM modes */ /******************* Bit definition for CRYP_CSGCMCCM1R register ******************/ #define CRYP_CSGCMCCM1R_CSGCMCCM1_Pos (0U) #define CRYP_CSGCMCCM1R_CSGCMCCM1_Msk (0xFFFFFFFFUL << CRYP_CSGCMCCM1R_CSGCMCCM1_Pos) /*!< 0xFFFFFFFF */ #define CRYP_CSGCMCCM1R_CSGCMCCM1 CRYP_CSGCMCCM1R_CSGCMCCM1_Msk /*!< CRYP internal state registers for GCM, GMAC and CCM modes */ /******************* Bit definition for CRYP_CSGCMCCM2R register ******************/ #define CRYP_CSGCMCCM2R_CSGCMCCM2_Pos (0U) #define CRYP_CSGCMCCM2R_CSGCMCCM2_Msk (0xFFFFFFFFUL << CRYP_CSGCMCCM2R_CSGCMCCM2_Pos) /*!< 0xFFFFFFFF */ #define CRYP_CSGCMCCM2R_CSGCMCCM2 CRYP_CSGCMCCM2R_CSGCMCCM2_Msk /*!< CRYP internal state registers for GCM, GMAC and CCM modes */ /******************* Bit definition for CRYP_CSGCMCCM3R register ******************/ #define CRYP_CSGCMCCM3R_CSGCMCCM3_Pos (0U) #define CRYP_CSGCMCCM3R_CSGCMCCM3_Msk (0xFFFFFFFFUL << CRYP_CSGCMCCM3R_CSGCMCCM3_Pos) /*!< 0xFFFFFFFF */ #define CRYP_CSGCMCCM3R_CSGCMCCM3 CRYP_CSGCMCCM3R_CSGCMCCM3_Msk /*!< CRYP internal state registers for GCM, GMAC and CCM modes */ /******************* Bit definition for CRYP_CSGCMCCM4R register ******************/ #define CRYP_CSGCMCCM4R_CSGCMCCM4_Pos (0U) #define CRYP_CSGCMCCM4R_CSGCMCCM4_Msk (0xFFFFFFFFUL << CRYP_CSGCMCCM4R_CSGCMCCM4_Pos) /*!< 0xFFFFFFFF */ #define CRYP_CSGCMCCM4R_CSGCMCCM4 CRYP_CSGCMCCM4R_CSGCMCCM4_Msk /*!< CRYP internal state registers for GCM, GMAC and CCM modes */ /******************* Bit definition for CRYP_CSGCMCCM5R register ******************/ #define CRYP_CSGCMCCM5R_CSGCMCCM5_Pos (0U) #define CRYP_CSGCMCCM5R_CSGCMCCM5_Msk (0xFFFFFFFFUL << CRYP_CSGCMCCM5R_CSGCMCCM5_Pos) /*!< 0xFFFFFFFF */ #define CRYP_CSGCMCCM5R_CSGCMCCM5 CRYP_CSGCMCCM5R_CSGCMCCM5_Msk /*!< CRYP internal state registers for GCM, GMAC and CCM modes */ /******************* Bit definition for CRYP_CSGCMCCM6R register ******************/ #define CRYP_CSGCMCCM6R_CSGCMCCM6_Pos (0U) #define CRYP_CSGCMCCM6R_CSGCMCCM6_Msk (0xFFFFFFFFUL << CRYP_CSGCMCCM6R_CSGCMCCM6_Pos) /*!< 0xFFFFFFFF */ #define CRYP_CSGCMCCM6R_CSGCMCCM6 CRYP_CSGCMCCM6R_CSGCMCCM6_Msk /*!< CRYP internal state registers for GCM, GMAC and CCM modes */ /******************* Bit definition for CRYP_CSGCMCCM7R register ******************/ #define CRYP_CSGCMCCM7R_CSGCMCCM7_Pos (0U) #define CRYP_CSGCMCCM7R_CSGCMCCM7_Msk (0xFFFFFFFFUL << CRYP_CSGCMCCM7R_CSGCMCCM7_Pos) /*!< 0xFFFFFFFF */ #define CRYP_CSGCMCCM7R_CSGCMCCM7 CRYP_CSGCMCCM7R_CSGCMCCM7_Msk /*!< CRYP internal state registers for GCM, GMAC and CCM modes */ /******************* Bit definition for CRYP_CSGCM0R register ******************/ #define CRYP_CSGCM0R_CSGCM0_Pos (0U) #define CRYP_CSGCM0R_CSGCM0_Msk (0xFFFFFFFFUL << CRYP_CSGCM0R_CSGCM0_Pos) /*!< 0xFFFFFFFF */ #define CRYP_CSGCM0R_CSGCM0 CRYP_CSGCM0R_CSGCM0_Msk /*!< CRYP internal state registers for GCM and GMAC modes */ /******************* Bit definition for CRYP_CSGCM1R register ******************/ #define CRYP_CSGCM1R_CSGCM1_Pos (0U) #define CRYP_CSGCM1R_CSGCM1_Msk (0xFFFFFFFFUL << CRYP_CSGCM1R_CSGCM1_Pos) /*!< 0xFFFFFFFF */ #define CRYP_CSGCM1R_CSGCM1 CRYP_CSGCM1R_CSGCM1_Msk /*!< CRYP internal state registers for GCM and GMAC modes */ /******************* Bit definition for CRYP_CSGCM2R register ******************/ #define CRYP_CSGCM2R_CSGCM2_Pos (0U) #define CRYP_CSGCM2R_CSGCM2_Msk (0xFFFFFFFFUL << CRYP_CSGCM2R_CSGCM2_Pos) /*!< 0xFFFFFFFF */ #define CRYP_CSGCM2R_CSGCM2 CRYP_CSGCM2R_CSGCM2_Msk /*!< CRYP internal state registers for GCM and GMAC modes */ /******************* Bit definition for CRYP_CSGCM3R register ******************/ #define CRYP_CSGCM3R_CSGCM3_Pos (0U) #define CRYP_CSGCM3R_CSGCM3_Msk (0xFFFFFFFFUL << CRYP_CSGCM3R_CSGCM3_Pos) /*!< 0xFFFFFFFF */ #define CRYP_CSGCM3R_CSGCM3 CRYP_CSGCM3R_CSGCM3_Msk /*!< CRYP internal state registers for GCM and GMAC modes */ /******************* Bit definition for CRYP_CSGCM4R register ******************/ #define CRYP_CSGCM4R_CSGCM4_Pos (0U) #define CRYP_CSGCM4R_CSGCM4_Msk (0xFFFFFFFFUL << CRYP_CSGCM4R_CSGCM4_Pos) /*!< 0xFFFFFFFF */ #define CRYP_CSGCM4R_CSGCM4 CRYP_CSGCM4R_CSGCM4_Msk /*!< CRYP internal state registers for GCM and GMAC modes */ /******************* Bit definition for CRYP_CSGCM5R register ******************/ #define CRYP_CSGCM5R_CSGCM5_Pos (0U) #define CRYP_CSGCM5R_CSGCM5_Msk (0xFFFFFFFFUL << CRYP_CSGCM5R_CSGCM5_Pos) /*!< 0xFFFFFFFF */ #define CRYP_CSGCM5R_CSGCM5 CRYP_CSGCM5R_CSGCM5_Msk /*!< CRYP internal state registers for GCM and GMAC modes */ /******************* Bit definition for CRYP_CSGCM6R register ******************/ #define CRYP_CSGCM6R_CSGCM6_Pos (0U) #define CRYP_CSGCM6R_CSGCM6_Msk (0xFFFFFFFFUL << CRYP_CSGCM6R_CSGCM6_Pos) /*!< 0xFFFFFFFF */ #define CRYP_CSGCM6R_CSGCM6 CRYP_CSGCM6R_CSGCM6_Msk /*!< CRYP internal state registers for GCM and GMAC modes */ /******************* Bit definition for CRYP_CSGCM7R register ******************/ #define CRYP_CSGCM7R_CSGCM7_Pos (0U) #define CRYP_CSGCM7R_CSGCM7_Msk (0xFFFFFFFFUL << CRYP_CSGCM7R_CSGCM7_Pos) /*!< 0xFFFFFFFF */ #define CRYP_CSGCM7R_CSGCM7 CRYP_CSGCM7R_CSGCM7_Msk /*!< CRYP internal state registers for GCM and GMAC modes */ /******************************************************************************/ /* */ /* (CSI) */ /* */ /******************************************************************************/ /******************** Bit definition for CSI_CR register ********************/ #define CSI_CR_CSIEN_Pos (0U) #define CSI_CR_CSIEN_Msk (0x1UL << CSI_CR_CSIEN_Pos) /*!< 0x00000001 */ #define CSI_CR_CSIEN CSI_CR_CSIEN_Msk /*!< CSI-2 enable */ #define CSI_CR_VC0START_Pos (2U) #define CSI_CR_VC0START_Msk (0x1UL << CSI_CR_VC0START_Pos) /*!< 0x00000004 */ #define CSI_CR_VC0START CSI_CR_VC0START_Msk /*!< Virtual channel 0 start */ #define CSI_CR_VC0STOP_Pos (3U) #define CSI_CR_VC0STOP_Msk (0x1UL << CSI_CR_VC0STOP_Pos) /*!< 0x00000008 */ #define CSI_CR_VC0STOP CSI_CR_VC0STOP_Msk /*!< Virtual channel 0 stop */ #define CSI_CR_VC1START_Pos (6U) #define CSI_CR_VC1START_Msk (0x1UL << CSI_CR_VC1START_Pos) /*!< 0x00000040 */ #define CSI_CR_VC1START CSI_CR_VC1START_Msk /*!< Virtual channel 1 start */ #define CSI_CR_VC1STOP_Pos (7U) #define CSI_CR_VC1STOP_Msk (0x1UL << CSI_CR_VC1STOP_Pos) /*!< 0x00000080 */ #define CSI_CR_VC1STOP CSI_CR_VC1STOP_Msk /*!< Virtual channel 1 stop */ #define CSI_CR_VC2START_Pos (10U) #define CSI_CR_VC2START_Msk (0x1UL << CSI_CR_VC2START_Pos) /*!< 0x00000400 */ #define CSI_CR_VC2START CSI_CR_VC2START_Msk /*!< Virtual channel 2 start */ #define CSI_CR_VC2STOP_Pos (11U) #define CSI_CR_VC2STOP_Msk (0x1UL << CSI_CR_VC2STOP_Pos) /*!< 0x00000800 */ #define CSI_CR_VC2STOP CSI_CR_VC2STOP_Msk /*!< Virtual channel 2 stop */ #define CSI_CR_VC3START_Pos (14U) #define CSI_CR_VC3START_Msk (0x1UL << CSI_CR_VC3START_Pos) /*!< 0x00004000 */ #define CSI_CR_VC3START CSI_CR_VC3START_Msk /*!< Virtual channel 3 start */ #define CSI_CR_VC3STOP_Pos (15U) #define CSI_CR_VC3STOP_Msk (0x1UL << CSI_CR_VC3STOP_Pos) /*!< 0x00008000 */ #define CSI_CR_VC3STOP CSI_CR_VC3STOP_Msk /*!< Virtual channel 3 stop */ /******************* Bit definition for CSI_PCR register ********************/ #define CSI_PCR_PWRDOWN_Pos (0U) #define CSI_PCR_PWRDOWN_Msk (0x1UL << CSI_PCR_PWRDOWN_Pos) /*!< 0x00000001 */ #define CSI_PCR_PWRDOWN CSI_PCR_PWRDOWN_Msk /*!< Virtual channel 3 start */ #define CSI_PCR_CLEN_Pos (1U) #define CSI_PCR_CLEN_Msk (0x1UL << CSI_PCR_CLEN_Pos) /*!< 0x00000002 */ #define CSI_PCR_CLEN CSI_PCR_CLEN_Msk /*!< Clock lane enable */ #define CSI_PCR_DL0EN_Pos (2U) #define CSI_PCR_DL0EN_Msk (0x1UL << CSI_PCR_DL0EN_Pos) /*!< 0x00000004 */ #define CSI_PCR_DL0EN CSI_PCR_DL0EN_Msk /*!< D-PHY_RX data lane 0 enable */ #define CSI_PCR_DL1EN_Pos (3U) #define CSI_PCR_DL1EN_Msk (0x1UL << CSI_PCR_DL1EN_Pos) /*!< 0x00000008 */ #define CSI_PCR_DL1EN CSI_PCR_DL1EN_Msk /*!< D-PHY_RX data lane 1 enable */ /***************** Bit definition for CSI_VC0CFGR1 register *****************/ #define CSI_VC0CFGR1_ALLDT_Pos (0U) #define CSI_VC0CFGR1_ALLDT_Msk (0x1UL << CSI_VC0CFGR1_ALLDT_Pos) /*!< 0x00000001 */ #define CSI_VC0CFGR1_ALLDT CSI_VC0CFGR1_ALLDT_Msk /*!< All data types enable for the virtual channel x */ #define CSI_VC0CFGR1_DT0EN_Pos (1U) #define CSI_VC0CFGR1_DT0EN_Msk (0x1UL << CSI_VC0CFGR1_DT0EN_Pos) /*!< 0x00000002 */ #define CSI_VC0CFGR1_DT0EN CSI_VC0CFGR1_DT0EN_Msk /*!< Data type 0 enable */ #define CSI_VC0CFGR1_DT1EN_Pos (2U) #define CSI_VC0CFGR1_DT1EN_Msk (0x1UL << CSI_VC0CFGR1_DT1EN_Pos) /*!< 0x00000004 */ #define CSI_VC0CFGR1_DT1EN CSI_VC0CFGR1_DT1EN_Msk /*!< Data type 1 enable */ #define CSI_VC0CFGR1_DT2EN_Pos (3U) #define CSI_VC0CFGR1_DT2EN_Msk (0x1UL << CSI_VC0CFGR1_DT2EN_Pos) /*!< 0x00000008 */ #define CSI_VC0CFGR1_DT2EN CSI_VC0CFGR1_DT2EN_Msk /*!< Data type 2 enable */ #define CSI_VC0CFGR1_DT3EN_Pos (4U) #define CSI_VC0CFGR1_DT3EN_Msk (0x1UL << CSI_VC0CFGR1_DT3EN_Pos) /*!< 0x00000010 */ #define CSI_VC0CFGR1_DT3EN CSI_VC0CFGR1_DT3EN_Msk /*!< Data type 3 enable */ #define CSI_VC0CFGR1_DT4EN_Pos (5U) #define CSI_VC0CFGR1_DT4EN_Msk (0x1UL << CSI_VC0CFGR1_DT4EN_Pos) /*!< 0x00000020 */ #define CSI_VC0CFGR1_DT4EN CSI_VC0CFGR1_DT4EN_Msk /*!< Data type 4 enable */ #define CSI_VC0CFGR1_DT5EN_Pos (6U) #define CSI_VC0CFGR1_DT5EN_Msk (0x1UL << CSI_VC0CFGR1_DT5EN_Pos) /*!< 0x00000040 */ #define CSI_VC0CFGR1_DT5EN CSI_VC0CFGR1_DT5EN_Msk /*!< Data type 5 enable */ #define CSI_VC0CFGR1_DT6EN_Pos (7U) #define CSI_VC0CFGR1_DT6EN_Msk (0x1UL << CSI_VC0CFGR1_DT6EN_Pos) /*!< 0x00000080 */ #define CSI_VC0CFGR1_DT6EN CSI_VC0CFGR1_DT6EN_Msk /*!< Data type 6 enable */ #define CSI_VC0CFGR1_CDTFT_Pos (8U) #define CSI_VC0CFGR1_CDTFT_Msk (0x1FUL << CSI_VC0CFGR1_CDTFT_Pos) /*!< 0x00001F00 */ #define CSI_VC0CFGR1_CDTFT CSI_VC0CFGR1_CDTFT_Msk /*!< Common format for all data types */ #define CSI_VC0CFGR1_DT0_Pos (16U) #define CSI_VC0CFGR1_DT0_Msk (0x3FUL << CSI_VC0CFGR1_DT0_Pos) /*!< 0x003F0000 */ #define CSI_VC0CFGR1_DT0 CSI_VC0CFGR1_DT0_Msk /*!< Data type 0 class selection for virtual channel x */ #define CSI_VC0CFGR1_DT0FT_Pos (24U) #define CSI_VC0CFGR1_DT0FT_Msk (0x1FUL << CSI_VC0CFGR1_DT0FT_Pos) /*!< 0x1F000000 */ #define CSI_VC0CFGR1_DT0FT CSI_VC0CFGR1_DT0FT_Msk /*!< Data type 0 format */ /***************** Bit definition for CSI_VC0CFGR2 register *****************/ #define CSI_VC0CFGR2_DT1_Pos (0U) #define CSI_VC0CFGR2_DT1_Msk (0x3FUL << CSI_VC0CFGR2_DT1_Pos) /*!< 0x0000003F */ #define CSI_VC0CFGR2_DT1 CSI_VC0CFGR2_DT1_Msk /*!< Data type 1 class selection for virtual channel x */ #define CSI_VC0CFGR2_DT1FT_Pos (8U) #define CSI_VC0CFGR2_DT1FT_Msk (0x1FUL << CSI_VC0CFGR2_DT1FT_Pos) /*!< 0x00001F00 */ #define CSI_VC0CFGR2_DT1FT CSI_VC0CFGR2_DT1FT_Msk /*!< Data type 1 format */ #define CSI_VC0CFGR2_DT2_Pos (16U) #define CSI_VC0CFGR2_DT2_Msk (0x3FUL << CSI_VC0CFGR2_DT2_Pos) /*!< 0x003F0000 */ #define CSI_VC0CFGR2_DT2 CSI_VC0CFGR2_DT2_Msk /*!< Data type 2 class selection for virtual channel x */ #define CSI_VC0CFGR2_DT2FT_Pos (24U) #define CSI_VC0CFGR2_DT2FT_Msk (0x1FUL << CSI_VC0CFGR2_DT2FT_Pos) /*!< 0x1F000000 */ #define CSI_VC0CFGR2_DT2FT CSI_VC0CFGR2_DT2FT_Msk /*!< Data type 2 format */ /***************** Bit definition for CSI_VC0CFGR3 register *****************/ #define CSI_VC0CFGR3_DT3_Pos (0U) #define CSI_VC0CFGR3_DT3_Msk (0x3FUL << CSI_VC0CFGR3_DT3_Pos) /*!< 0x0000003F */ #define CSI_VC0CFGR3_DT3 CSI_VC0CFGR3_DT3_Msk /*!< Data type 3 class selection for virtual channel x */ #define CSI_VC0CFGR3_DT3FT_Pos (8U) #define CSI_VC0CFGR3_DT3FT_Msk (0x1FUL << CSI_VC0CFGR3_DT3FT_Pos) /*!< 0x00001F00 */ #define CSI_VC0CFGR3_DT3FT CSI_VC0CFGR3_DT3FT_Msk /*!< Data type 3 format */ #define CSI_VC0CFGR3_DT4_Pos (16U) #define CSI_VC0CFGR3_DT4_Msk (0x3FUL << CSI_VC0CFGR3_DT4_Pos) /*!< 0x003F0000 */ #define CSI_VC0CFGR3_DT4 CSI_VC0CFGR3_DT4_Msk /*!< Data type 4 class selection for virtual channel x */ #define CSI_VC0CFGR3_DT4FT_Pos (24U) #define CSI_VC0CFGR3_DT4FT_Msk (0x1FUL << CSI_VC0CFGR3_DT4FT_Pos) /*!< 0x1F000000 */ #define CSI_VC0CFGR3_DT4FT CSI_VC0CFGR3_DT4FT_Msk /*!< Data type 4 format */ /***************** Bit definition for CSI_VC0CFGR4 register *****************/ #define CSI_VC0CFGR4_DT5_Pos (0U) #define CSI_VC0CFGR4_DT5_Msk (0x3FUL << CSI_VC0CFGR4_DT5_Pos) /*!< 0x0000003F */ #define CSI_VC0CFGR4_DT5 CSI_VC0CFGR4_DT5_Msk /*!< Data type 5 class selection for virtual channel x */ #define CSI_VC0CFGR4_DT5FT_Pos (8U) #define CSI_VC0CFGR4_DT5FT_Msk (0x1FUL << CSI_VC0CFGR4_DT5FT_Pos) /*!< 0x00001F00 */ #define CSI_VC0CFGR4_DT5FT CSI_VC0CFGR4_DT5FT_Msk /*!< Data type 5 format */ #define CSI_VC0CFGR4_DT6_Pos (16U) #define CSI_VC0CFGR4_DT6_Msk (0x3FUL << CSI_VC0CFGR4_DT6_Pos) /*!< 0x003F0000 */ #define CSI_VC0CFGR4_DT6 CSI_VC0CFGR4_DT6_Msk /*!< Data type 6 class selection for virtual channel x */ #define CSI_VC0CFGR4_DT6FT_Pos (24U) #define CSI_VC0CFGR4_DT6FT_Msk (0x1FUL << CSI_VC0CFGR4_DT6FT_Pos) /*!< 0x1F000000 */ #define CSI_VC0CFGR4_DT6FT CSI_VC0CFGR4_DT6FT_Msk /*!< Data type 6 format */ /***************** Bit definition for CSI_VC1CFGR1 register *****************/ #define CSI_VC1CFGR1_ALLDT_Pos (0U) #define CSI_VC1CFGR1_ALLDT_Msk (0x1UL << CSI_VC1CFGR1_ALLDT_Pos) /*!< 0x00000001 */ #define CSI_VC1CFGR1_ALLDT CSI_VC1CFGR1_ALLDT_Msk /*!< All data types enable for the virtual channel x */ #define CSI_VC1CFGR1_DT0EN_Pos (1U) #define CSI_VC1CFGR1_DT0EN_Msk (0x1UL << CSI_VC1CFGR1_DT0EN_Pos) /*!< 0x00000002 */ #define CSI_VC1CFGR1_DT0EN CSI_VC1CFGR1_DT0EN_Msk /*!< Data type 0 enable */ #define CSI_VC1CFGR1_DT1EN_Pos (2U) #define CSI_VC1CFGR1_DT1EN_Msk (0x1UL << CSI_VC1CFGR1_DT1EN_Pos) /*!< 0x00000004 */ #define CSI_VC1CFGR1_DT1EN CSI_VC1CFGR1_DT1EN_Msk /*!< Data type 1 enable */ #define CSI_VC1CFGR1_DT2EN_Pos (3U) #define CSI_VC1CFGR1_DT2EN_Msk (0x1UL << CSI_VC1CFGR1_DT2EN_Pos) /*!< 0x00000008 */ #define CSI_VC1CFGR1_DT2EN CSI_VC1CFGR1_DT2EN_Msk /*!< Data type 2 enable */ #define CSI_VC1CFGR1_DT3EN_Pos (4U) #define CSI_VC1CFGR1_DT3EN_Msk (0x1UL << CSI_VC1CFGR1_DT3EN_Pos) /*!< 0x00000010 */ #define CSI_VC1CFGR1_DT3EN CSI_VC1CFGR1_DT3EN_Msk /*!< Data type 3 enable */ #define CSI_VC1CFGR1_DT4EN_Pos (5U) #define CSI_VC1CFGR1_DT4EN_Msk (0x1UL << CSI_VC1CFGR1_DT4EN_Pos) /*!< 0x00000020 */ #define CSI_VC1CFGR1_DT4EN CSI_VC1CFGR1_DT4EN_Msk /*!< Data type 4 enable */ #define CSI_VC1CFGR1_DT5EN_Pos (6U) #define CSI_VC1CFGR1_DT5EN_Msk (0x1UL << CSI_VC1CFGR1_DT5EN_Pos) /*!< 0x00000040 */ #define CSI_VC1CFGR1_DT5EN CSI_VC1CFGR1_DT5EN_Msk /*!< Data type 5 enable */ #define CSI_VC1CFGR1_DT6EN_Pos (7U) #define CSI_VC1CFGR1_DT6EN_Msk (0x1UL << CSI_VC1CFGR1_DT6EN_Pos) /*!< 0x00000080 */ #define CSI_VC1CFGR1_DT6EN CSI_VC1CFGR1_DT6EN_Msk /*!< Data type 6 enable */ #define CSI_VC1CFGR1_CDTFT_Pos (8U) #define CSI_VC1CFGR1_CDTFT_Msk (0x1FUL << CSI_VC1CFGR1_CDTFT_Pos) /*!< 0x00001F00 */ #define CSI_VC1CFGR1_CDTFT CSI_VC1CFGR1_CDTFT_Msk /*!< Common format for all data types */ #define CSI_VC1CFGR1_DT0_Pos (16U) #define CSI_VC1CFGR1_DT0_Msk (0x3FUL << CSI_VC1CFGR1_DT0_Pos) /*!< 0x003F0000 */ #define CSI_VC1CFGR1_DT0 CSI_VC1CFGR1_DT0_Msk /*!< Data type 0 class selection for virtual channel x */ #define CSI_VC1CFGR1_DT0FT_Pos (24U) #define CSI_VC1CFGR1_DT0FT_Msk (0x1FUL << CSI_VC1CFGR1_DT0FT_Pos) /*!< 0x1F000000 */ #define CSI_VC1CFGR1_DT0FT CSI_VC1CFGR1_DT0FT_Msk /*!< Data type 0 format */ /***************** Bit definition for CSI_VC1CFGR2 register *****************/ #define CSI_VC1CFGR2_DT1_Pos (0U) #define CSI_VC1CFGR2_DT1_Msk (0x3FUL << CSI_VC1CFGR2_DT1_Pos) /*!< 0x0000003F */ #define CSI_VC1CFGR2_DT1 CSI_VC1CFGR2_DT1_Msk /*!< Data type 1 class selection for virtual channel x */ #define CSI_VC1CFGR2_DT1FT_Pos (8U) #define CSI_VC1CFGR2_DT1FT_Msk (0x1FUL << CSI_VC1CFGR2_DT1FT_Pos) /*!< 0x00001F00 */ #define CSI_VC1CFGR2_DT1FT CSI_VC1CFGR2_DT1FT_Msk /*!< Data type 1 format */ #define CSI_VC1CFGR2_DT2_Pos (16U) #define CSI_VC1CFGR2_DT2_Msk (0x3FUL << CSI_VC1CFGR2_DT2_Pos) /*!< 0x003F0000 */ #define CSI_VC1CFGR2_DT2 CSI_VC1CFGR2_DT2_Msk /*!< Data type 2 class selection for virtual channel x */ #define CSI_VC1CFGR2_DT2FT_Pos (24U) #define CSI_VC1CFGR2_DT2FT_Msk (0x1FUL << CSI_VC1CFGR2_DT2FT_Pos) /*!< 0x1F000000 */ #define CSI_VC1CFGR2_DT2FT CSI_VC1CFGR2_DT2FT_Msk /*!< Data type 2 format */ /***************** Bit definition for CSI_VC1CFGR3 register *****************/ #define CSI_VC1CFGR3_DT3_Pos (0U) #define CSI_VC1CFGR3_DT3_Msk (0x3FUL << CSI_VC1CFGR3_DT3_Pos) /*!< 0x0000003F */ #define CSI_VC1CFGR3_DT3 CSI_VC1CFGR3_DT3_Msk /*!< Data type 3 class selection for virtual channel x */ #define CSI_VC1CFGR3_DT3FT_Pos (8U) #define CSI_VC1CFGR3_DT3FT_Msk (0x1FUL << CSI_VC1CFGR3_DT3FT_Pos) /*!< 0x00001F00 */ #define CSI_VC1CFGR3_DT3FT CSI_VC1CFGR3_DT3FT_Msk /*!< Data type 3 format */ #define CSI_VC1CFGR3_DT4_Pos (16U) #define CSI_VC1CFGR3_DT4_Msk (0x3FUL << CSI_VC1CFGR3_DT4_Pos) /*!< 0x003F0000 */ #define CSI_VC1CFGR3_DT4 CSI_VC1CFGR3_DT4_Msk /*!< Data type 4 class selection for virtual channel x */ #define CSI_VC1CFGR3_DT4FT_Pos (24U) #define CSI_VC1CFGR3_DT4FT_Msk (0x1FUL << CSI_VC1CFGR3_DT4FT_Pos) /*!< 0x1F000000 */ #define CSI_VC1CFGR3_DT4FT CSI_VC1CFGR3_DT4FT_Msk /*!< Data type 4 format */ /***************** Bit definition for CSI_VC1CFGR4 register *****************/ #define CSI_VC1CFGR4_DT5_Pos (0U) #define CSI_VC1CFGR4_DT5_Msk (0x3FUL << CSI_VC1CFGR4_DT5_Pos) /*!< 0x0000003F */ #define CSI_VC1CFGR4_DT5 CSI_VC1CFGR4_DT5_Msk /*!< Data type 5 class selection for virtual channel x */ #define CSI_VC1CFGR4_DT5FT_Pos (8U) #define CSI_VC1CFGR4_DT5FT_Msk (0x1FUL << CSI_VC1CFGR4_DT5FT_Pos) /*!< 0x00001F00 */ #define CSI_VC1CFGR4_DT5FT CSI_VC1CFGR4_DT5FT_Msk /*!< Data type 5 format */ #define CSI_VC1CFGR4_DT6_Pos (16U) #define CSI_VC1CFGR4_DT6_Msk (0x3FUL << CSI_VC1CFGR4_DT6_Pos) /*!< 0x003F0000 */ #define CSI_VC1CFGR4_DT6 CSI_VC1CFGR4_DT6_Msk /*!< Data type 6 class selection for virtual channel x */ #define CSI_VC1CFGR4_DT6FT_Pos (24U) #define CSI_VC1CFGR4_DT6FT_Msk (0x1FUL << CSI_VC1CFGR4_DT6FT_Pos) /*!< 0x1F000000 */ #define CSI_VC1CFGR4_DT6FT CSI_VC1CFGR4_DT6FT_Msk /*!< Data type 6 format */ /***************** Bit definition for CSI_VC2CFGR1 register *****************/ #define CSI_VC2CFGR1_ALLDT_Pos (0U) #define CSI_VC2CFGR1_ALLDT_Msk (0x1UL << CSI_VC2CFGR1_ALLDT_Pos) /*!< 0x00000001 */ #define CSI_VC2CFGR1_ALLDT CSI_VC2CFGR1_ALLDT_Msk /*!< All data types enable for the virtual channel x */ #define CSI_VC2CFGR1_DT0EN_Pos (1U) #define CSI_VC2CFGR1_DT0EN_Msk (0x1UL << CSI_VC2CFGR1_DT0EN_Pos) /*!< 0x00000002 */ #define CSI_VC2CFGR1_DT0EN CSI_VC2CFGR1_DT0EN_Msk /*!< Data type 0 enable */ #define CSI_VC2CFGR1_DT1EN_Pos (2U) #define CSI_VC2CFGR1_DT1EN_Msk (0x1UL << CSI_VC2CFGR1_DT1EN_Pos) /*!< 0x00000004 */ #define CSI_VC2CFGR1_DT1EN CSI_VC2CFGR1_DT1EN_Msk /*!< Data type 1 enable */ #define CSI_VC2CFGR1_DT2EN_Pos (3U) #define CSI_VC2CFGR1_DT2EN_Msk (0x1UL << CSI_VC2CFGR1_DT2EN_Pos) /*!< 0x00000008 */ #define CSI_VC2CFGR1_DT2EN CSI_VC2CFGR1_DT2EN_Msk /*!< Data type 2 enable */ #define CSI_VC2CFGR1_DT3EN_Pos (4U) #define CSI_VC2CFGR1_DT3EN_Msk (0x1UL << CSI_VC2CFGR1_DT3EN_Pos) /*!< 0x00000010 */ #define CSI_VC2CFGR1_DT3EN CSI_VC2CFGR1_DT3EN_Msk /*!< Data type 3 enable */ #define CSI_VC2CFGR1_DT4EN_Pos (5U) #define CSI_VC2CFGR1_DT4EN_Msk (0x1UL << CSI_VC2CFGR1_DT4EN_Pos) /*!< 0x00000020 */ #define CSI_VC2CFGR1_DT4EN CSI_VC2CFGR1_DT4EN_Msk /*!< Data type 4 enable */ #define CSI_VC2CFGR1_DT5EN_Pos (6U) #define CSI_VC2CFGR1_DT5EN_Msk (0x1UL << CSI_VC2CFGR1_DT5EN_Pos) /*!< 0x00000040 */ #define CSI_VC2CFGR1_DT5EN CSI_VC2CFGR1_DT5EN_Msk /*!< Data type 5 enable */ #define CSI_VC2CFGR1_DT6EN_Pos (7U) #define CSI_VC2CFGR1_DT6EN_Msk (0x1UL << CSI_VC2CFGR1_DT6EN_Pos) /*!< 0x00000080 */ #define CSI_VC2CFGR1_DT6EN CSI_VC2CFGR1_DT6EN_Msk /*!< Data type 6 enable */ #define CSI_VC2CFGR1_CDTFT_Pos (8U) #define CSI_VC2CFGR1_CDTFT_Msk (0x1FUL << CSI_VC2CFGR1_CDTFT_Pos) /*!< 0x00001F00 */ #define CSI_VC2CFGR1_CDTFT CSI_VC2CFGR1_CDTFT_Msk /*!< Common format for all data types */ #define CSI_VC2CFGR1_DT0_Pos (16U) #define CSI_VC2CFGR1_DT0_Msk (0x3FUL << CSI_VC2CFGR1_DT0_Pos) /*!< 0x003F0000 */ #define CSI_VC2CFGR1_DT0 CSI_VC2CFGR1_DT0_Msk /*!< Data type 0 class selection for virtual channel x */ #define CSI_VC2CFGR1_DT0FT_Pos (24U) #define CSI_VC2CFGR1_DT0FT_Msk (0x1FUL << CSI_VC2CFGR1_DT0FT_Pos) /*!< 0x1F000000 */ #define CSI_VC2CFGR1_DT0FT CSI_VC2CFGR1_DT0FT_Msk /*!< Data type 0 format */ /***************** Bit definition for CSI_VC2CFGR2 register *****************/ #define CSI_VC2CFGR2_DT1_Pos (0U) #define CSI_VC2CFGR2_DT1_Msk (0x3FUL << CSI_VC2CFGR2_DT1_Pos) /*!< 0x0000003F */ #define CSI_VC2CFGR2_DT1 CSI_VC2CFGR2_DT1_Msk /*!< Data type 1 class selection for virtual channel x */ #define CSI_VC2CFGR2_DT1FT_Pos (8U) #define CSI_VC2CFGR2_DT1FT_Msk (0x1FUL << CSI_VC2CFGR2_DT1FT_Pos) /*!< 0x00001F00 */ #define CSI_VC2CFGR2_DT1FT CSI_VC2CFGR2_DT1FT_Msk /*!< Data type 1 format */ #define CSI_VC2CFGR2_DT2_Pos (16U) #define CSI_VC2CFGR2_DT2_Msk (0x3FUL << CSI_VC2CFGR2_DT2_Pos) /*!< 0x003F0000 */ #define CSI_VC2CFGR2_DT2 CSI_VC2CFGR2_DT2_Msk /*!< Data type 2 class selection for virtual channel x */ #define CSI_VC2CFGR2_DT2FT_Pos (24U) #define CSI_VC2CFGR2_DT2FT_Msk (0x1FUL << CSI_VC2CFGR2_DT2FT_Pos) /*!< 0x1F000000 */ #define CSI_VC2CFGR2_DT2FT CSI_VC2CFGR2_DT2FT_Msk /*!< Data type 2 format */ /***************** Bit definition for CSI_VC2CFGR3 register *****************/ #define CSI_VC2CFGR3_DT3_Pos (0U) #define CSI_VC2CFGR3_DT3_Msk (0x3FUL << CSI_VC2CFGR3_DT3_Pos) /*!< 0x0000003F */ #define CSI_VC2CFGR3_DT3 CSI_VC2CFGR3_DT3_Msk /*!< Data type 3 class selection for virtual channel x */ #define CSI_VC2CFGR3_DT3FT_Pos (8U) #define CSI_VC2CFGR3_DT3FT_Msk (0x1FUL << CSI_VC2CFGR3_DT3FT_Pos) /*!< 0x00001F00 */ #define CSI_VC2CFGR3_DT3FT CSI_VC2CFGR3_DT3FT_Msk /*!< Data type 3 format */ #define CSI_VC2CFGR3_DT4_Pos (16U) #define CSI_VC2CFGR3_DT4_Msk (0x3FUL << CSI_VC2CFGR3_DT4_Pos) /*!< 0x003F0000 */ #define CSI_VC2CFGR3_DT4 CSI_VC2CFGR3_DT4_Msk /*!< Data type 4 class selection for virtual channel x */ #define CSI_VC2CFGR3_DT4FT_Pos (24U) #define CSI_VC2CFGR3_DT4FT_Msk (0x1FUL << CSI_VC2CFGR3_DT4FT_Pos) /*!< 0x1F000000 */ #define CSI_VC2CFGR3_DT4FT CSI_VC2CFGR3_DT4FT_Msk /*!< Data type 4 format */ /***************** Bit definition for CSI_VC2CFGR4 register *****************/ #define CSI_VC2CFGR4_DT5_Pos (0U) #define CSI_VC2CFGR4_DT5_Msk (0x3FUL << CSI_VC2CFGR4_DT5_Pos) /*!< 0x0000003F */ #define CSI_VC2CFGR4_DT5 CSI_VC2CFGR4_DT5_Msk /*!< Data type 5 class selection for virtual channel x */ #define CSI_VC2CFGR4_DT5FT_Pos (8U) #define CSI_VC2CFGR4_DT5FT_Msk (0x1FUL << CSI_VC2CFGR4_DT5FT_Pos) /*!< 0x00001F00 */ #define CSI_VC2CFGR4_DT5FT CSI_VC2CFGR4_DT5FT_Msk /*!< Data type 5 format */ #define CSI_VC2CFGR4_DT6_Pos (16U) #define CSI_VC2CFGR4_DT6_Msk (0x3FUL << CSI_VC2CFGR4_DT6_Pos) /*!< 0x003F0000 */ #define CSI_VC2CFGR4_DT6 CSI_VC2CFGR4_DT6_Msk /*!< Data type 6 class selection for virtual channel x */ #define CSI_VC2CFGR4_DT6FT_Pos (24U) #define CSI_VC2CFGR4_DT6FT_Msk (0x1FUL << CSI_VC2CFGR4_DT6FT_Pos) /*!< 0x1F000000 */ #define CSI_VC2CFGR4_DT6FT CSI_VC2CFGR4_DT6FT_Msk /*!< Data type 6 format */ /***************** Bit definition for CSI_VC3CFGR1 register *****************/ #define CSI_VC3CFGR1_ALLDT_Pos (0U) #define CSI_VC3CFGR1_ALLDT_Msk (0x1UL << CSI_VC3CFGR1_ALLDT_Pos) /*!< 0x00000001 */ #define CSI_VC3CFGR1_ALLDT CSI_VC3CFGR1_ALLDT_Msk /*!< All data types enable for the virtual channel x */ #define CSI_VC3CFGR1_DT0EN_Pos (1U) #define CSI_VC3CFGR1_DT0EN_Msk (0x1UL << CSI_VC3CFGR1_DT0EN_Pos) /*!< 0x00000002 */ #define CSI_VC3CFGR1_DT0EN CSI_VC3CFGR1_DT0EN_Msk /*!< Data type 0 enable */ #define CSI_VC3CFGR1_DT1EN_Pos (2U) #define CSI_VC3CFGR1_DT1EN_Msk (0x1UL << CSI_VC3CFGR1_DT1EN_Pos) /*!< 0x00000004 */ #define CSI_VC3CFGR1_DT1EN CSI_VC3CFGR1_DT1EN_Msk /*!< Data type 1 enable */ #define CSI_VC3CFGR1_DT2EN_Pos (3U) #define CSI_VC3CFGR1_DT2EN_Msk (0x1UL << CSI_VC3CFGR1_DT2EN_Pos) /*!< 0x00000008 */ #define CSI_VC3CFGR1_DT2EN CSI_VC3CFGR1_DT2EN_Msk /*!< Data type 2 enable */ #define CSI_VC3CFGR1_DT3EN_Pos (4U) #define CSI_VC3CFGR1_DT3EN_Msk (0x1UL << CSI_VC3CFGR1_DT3EN_Pos) /*!< 0x00000010 */ #define CSI_VC3CFGR1_DT3EN CSI_VC3CFGR1_DT3EN_Msk /*!< Data type 3 enable */ #define CSI_VC3CFGR1_DT4EN_Pos (5U) #define CSI_VC3CFGR1_DT4EN_Msk (0x1UL << CSI_VC3CFGR1_DT4EN_Pos) /*!< 0x00000020 */ #define CSI_VC3CFGR1_DT4EN CSI_VC3CFGR1_DT4EN_Msk /*!< Data type 4 enable */ #define CSI_VC3CFGR1_DT5EN_Pos (6U) #define CSI_VC3CFGR1_DT5EN_Msk (0x1UL << CSI_VC3CFGR1_DT5EN_Pos) /*!< 0x00000040 */ #define CSI_VC3CFGR1_DT5EN CSI_VC3CFGR1_DT5EN_Msk /*!< Data type 5 enable */ #define CSI_VC3CFGR1_DT6EN_Pos (7U) #define CSI_VC3CFGR1_DT6EN_Msk (0x1UL << CSI_VC3CFGR1_DT6EN_Pos) /*!< 0x00000080 */ #define CSI_VC3CFGR1_DT6EN CSI_VC3CFGR1_DT6EN_Msk /*!< Data type 6 enable */ #define CSI_VC3CFGR1_CDTFT_Pos (8U) #define CSI_VC3CFGR1_CDTFT_Msk (0x1FUL << CSI_VC3CFGR1_CDTFT_Pos) /*!< 0x00001F00 */ #define CSI_VC3CFGR1_CDTFT CSI_VC3CFGR1_CDTFT_Msk /*!< Common format for all data types */ #define CSI_VC3CFGR1_DT0_Pos (16U) #define CSI_VC3CFGR1_DT0_Msk (0x3FUL << CSI_VC3CFGR1_DT0_Pos) /*!< 0x003F0000 */ #define CSI_VC3CFGR1_DT0 CSI_VC3CFGR1_DT0_Msk /*!< Data type 0 class selection for virtual channel x */ #define CSI_VC3CFGR1_DT0FT_Pos (24U) #define CSI_VC3CFGR1_DT0FT_Msk (0x1FUL << CSI_VC3CFGR1_DT0FT_Pos) /*!< 0x1F000000 */ #define CSI_VC3CFGR1_DT0FT CSI_VC3CFGR1_DT0FT_Msk /*!< Data type 0 format */ /***************** Bit definition for CSI_VC3CFGR2 register *****************/ #define CSI_VC3CFGR2_DT1_Pos (0U) #define CSI_VC3CFGR2_DT1_Msk (0x3FUL << CSI_VC3CFGR2_DT1_Pos) /*!< 0x0000003F */ #define CSI_VC3CFGR2_DT1 CSI_VC3CFGR2_DT1_Msk /*!< Data type 1 class selection for virtual channel x */ #define CSI_VC3CFGR2_DT1FT_Pos (8U) #define CSI_VC3CFGR2_DT1FT_Msk (0x1FUL << CSI_VC3CFGR2_DT1FT_Pos) /*!< 0x00001F00 */ #define CSI_VC3CFGR2_DT1FT CSI_VC3CFGR2_DT1FT_Msk /*!< Data type 1 format */ #define CSI_VC3CFGR2_DT2_Pos (16U) #define CSI_VC3CFGR2_DT2_Msk (0x3FUL << CSI_VC3CFGR2_DT2_Pos) /*!< 0x003F0000 */ #define CSI_VC3CFGR2_DT2 CSI_VC3CFGR2_DT2_Msk /*!< Data type 2 class selection for virtual channel x */ #define CSI_VC3CFGR2_DT2FT_Pos (24U) #define CSI_VC3CFGR2_DT2FT_Msk (0x1FUL << CSI_VC3CFGR2_DT2FT_Pos) /*!< 0x1F000000 */ #define CSI_VC3CFGR2_DT2FT CSI_VC3CFGR2_DT2FT_Msk /*!< Data type 2 format */ /***************** Bit definition for CSI_VC3CFGR3 register *****************/ #define CSI_VC3CFGR3_DT3_Pos (0U) #define CSI_VC3CFGR3_DT3_Msk (0x3FUL << CSI_VC3CFGR3_DT3_Pos) /*!< 0x0000003F */ #define CSI_VC3CFGR3_DT3 CSI_VC3CFGR3_DT3_Msk /*!< Data type 3 class selection for virtual channel x */ #define CSI_VC3CFGR3_DT3FT_Pos (8U) #define CSI_VC3CFGR3_DT3FT_Msk (0x1FUL << CSI_VC3CFGR3_DT3FT_Pos) /*!< 0x00001F00 */ #define CSI_VC3CFGR3_DT3FT CSI_VC3CFGR3_DT3FT_Msk /*!< Data type 3 format */ #define CSI_VC3CFGR3_DT4_Pos (16U) #define CSI_VC3CFGR3_DT4_Msk (0x3FUL << CSI_VC3CFGR3_DT4_Pos) /*!< 0x003F0000 */ #define CSI_VC3CFGR3_DT4 CSI_VC3CFGR3_DT4_Msk /*!< Data type 4 class selection for virtual channel x */ #define CSI_VC3CFGR3_DT4FT_Pos (24U) #define CSI_VC3CFGR3_DT4FT_Msk (0x1FUL << CSI_VC3CFGR3_DT4FT_Pos) /*!< 0x1F000000 */ #define CSI_VC3CFGR3_DT4FT CSI_VC3CFGR3_DT4FT_Msk /*!< Data type 4 format */ /***************** Bit definition for CSI_VC3CFGR4 register *****************/ #define CSI_VC3CFGR4_DT5_Pos (0U) #define CSI_VC3CFGR4_DT5_Msk (0x3FUL << CSI_VC3CFGR4_DT5_Pos) /*!< 0x0000003F */ #define CSI_VC3CFGR4_DT5 CSI_VC3CFGR4_DT5_Msk /*!< Data type 5 class selection for virtual channel x */ #define CSI_VC3CFGR4_DT5FT_Pos (8U) #define CSI_VC3CFGR4_DT5FT_Msk (0x1FUL << CSI_VC3CFGR4_DT5FT_Pos) /*!< 0x00001F00 */ #define CSI_VC3CFGR4_DT5FT CSI_VC3CFGR4_DT5FT_Msk /*!< Data type 5 format */ #define CSI_VC3CFGR4_DT6_Pos (16U) #define CSI_VC3CFGR4_DT6_Msk (0x3FUL << CSI_VC3CFGR4_DT6_Pos) /*!< 0x003F0000 */ #define CSI_VC3CFGR4_DT6 CSI_VC3CFGR4_DT6_Msk /*!< Data type 6 class selection for virtual channel x */ #define CSI_VC3CFGR4_DT6FT_Pos (24U) #define CSI_VC3CFGR4_DT6FT_Msk (0x1FUL << CSI_VC3CFGR4_DT6FT_Pos) /*!< 0x1F000000 */ #define CSI_VC3CFGR4_DT6FT CSI_VC3CFGR4_DT6FT_Msk /*!< Data type 6 format */ /***************** Bit definition for CSI_LB0CFGR register ******************/ #define CSI_LB0CFGR_BYTECNT_Pos (0U) #define CSI_LB0CFGR_BYTECNT_Msk (0xFFFFUL << CSI_LB0CFGR_BYTECNT_Pos) /*!< 0x0000FFFF */ #define CSI_LB0CFGR_BYTECNT CSI_LB0CFGR_BYTECNT_Msk /*!< Byte counter */ #define CSI_LB0CFGR_LINECNT_Pos (16U) #define CSI_LB0CFGR_LINECNT_Msk (0xFFFFUL << CSI_LB0CFGR_LINECNT_Pos) /*!< 0xFFFF0000 */ #define CSI_LB0CFGR_LINECNT CSI_LB0CFGR_LINECNT_Msk /*!< Line counter */ /***************** Bit definition for CSI_LB1CFGR register ******************/ #define CSI_LB1CFGR_BYTECNT_Pos (0U) #define CSI_LB1CFGR_BYTECNT_Msk (0xFFFFUL << CSI_LB1CFGR_BYTECNT_Pos) /*!< 0x0000FFFF */ #define CSI_LB1CFGR_BYTECNT CSI_LB1CFGR_BYTECNT_Msk /*!< Byte counter */ #define CSI_LB1CFGR_LINECNT_Pos (16U) #define CSI_LB1CFGR_LINECNT_Msk (0xFFFFUL << CSI_LB1CFGR_LINECNT_Pos) /*!< 0xFFFF0000 */ #define CSI_LB1CFGR_LINECNT CSI_LB1CFGR_LINECNT_Msk /*!< Line counter */ /***************** Bit definition for CSI_LB2CFGR register ******************/ #define CSI_LB2CFGR_BYTECNT_Pos (0U) #define CSI_LB2CFGR_BYTECNT_Msk (0xFFFFUL << CSI_LB2CFGR_BYTECNT_Pos) /*!< 0x0000FFFF */ #define CSI_LB2CFGR_BYTECNT CSI_LB2CFGR_BYTECNT_Msk /*!< Byte counter */ #define CSI_LB2CFGR_LINECNT_Pos (16U) #define CSI_LB2CFGR_LINECNT_Msk (0xFFFFUL << CSI_LB2CFGR_LINECNT_Pos) /*!< 0xFFFF0000 */ #define CSI_LB2CFGR_LINECNT CSI_LB2CFGR_LINECNT_Msk /*!< Line counter */ /***************** Bit definition for CSI_LB3CFGR register ******************/ #define CSI_LB3CFGR_BYTECNT_Pos (0U) #define CSI_LB3CFGR_BYTECNT_Msk (0xFFFFUL << CSI_LB3CFGR_BYTECNT_Pos) /*!< 0x0000FFFF */ #define CSI_LB3CFGR_BYTECNT CSI_LB3CFGR_BYTECNT_Msk /*!< Byte counter */ #define CSI_LB3CFGR_LINECNT_Pos (16U) #define CSI_LB3CFGR_LINECNT_Msk (0xFFFFUL << CSI_LB3CFGR_LINECNT_Pos) /*!< 0xFFFF0000 */ #define CSI_LB3CFGR_LINECNT CSI_LB3CFGR_LINECNT_Msk /*!< Line counter */ /***************** Bit definition for CSI_TIM0CFGR register *****************/ #define CSI_TIM0CFGR_COUNT_Pos (0U) #define CSI_TIM0CFGR_COUNT_Msk (0x1FFFFFFUL << CSI_TIM0CFGR_COUNT_Pos) /*!< 0x01FFFFFF */ #define CSI_TIM0CFGR_COUNT CSI_TIM0CFGR_COUNT_Msk /*!< Clock cycle counter */ /***************** Bit definition for CSI_TIM1CFGR register *****************/ #define CSI_TIM1CFGR_COUNT_Pos (0U) #define CSI_TIM1CFGR_COUNT_Msk (0x1FFFFFFUL << CSI_TIM1CFGR_COUNT_Pos) /*!< 0x01FFFFFF */ #define CSI_TIM1CFGR_COUNT CSI_TIM1CFGR_COUNT_Msk /*!< Clock cycle counter */ /***************** Bit definition for CSI_TIM2CFGR register *****************/ #define CSI_TIM2CFGR_COUNT_Pos (0U) #define CSI_TIM2CFGR_COUNT_Msk (0x1FFFFFFUL << CSI_TIM2CFGR_COUNT_Pos) /*!< 0x01FFFFFF */ #define CSI_TIM2CFGR_COUNT CSI_TIM2CFGR_COUNT_Msk /*!< Clock cycle counter */ /***************** Bit definition for CSI_TIM3CFGR register *****************/ #define CSI_TIM3CFGR_COUNT_Pos (0U) #define CSI_TIM3CFGR_COUNT_Msk (0x1FFFFFFUL << CSI_TIM3CFGR_COUNT_Pos) /*!< 0x01FFFFFF */ #define CSI_TIM3CFGR_COUNT CSI_TIM3CFGR_COUNT_Msk /*!< Clock cycle counter */ /****************** Bit definition for CSI_LMCFGR register ******************/ #define CSI_LMCFGR_LANENB_Pos (8U) #define CSI_LMCFGR_LANENB_Msk (0x7UL << CSI_LMCFGR_LANENB_Pos) /*!< 0x00000700 */ #define CSI_LMCFGR_LANENB CSI_LMCFGR_LANENB_Msk /*!< Number of lanes */ #define CSI_LMCFGR_DL0MAP_Pos (16U) #define CSI_LMCFGR_DL0MAP_Msk (0x7UL << CSI_LMCFGR_DL0MAP_Pos) /*!< 0x00070000 */ #define CSI_LMCFGR_DL0MAP CSI_LMCFGR_DL0MAP_Msk /*!< Physical mapping of logical data lane 0 */ #define CSI_LMCFGR_DL1MAP_Pos (20U) #define CSI_LMCFGR_DL1MAP_Msk (0x7UL << CSI_LMCFGR_DL1MAP_Pos) /*!< 0x00700000 */ #define CSI_LMCFGR_DL1MAP CSI_LMCFGR_DL1MAP_Msk /*!< Physical mapping of logical data lane 1 */ /****************** Bit definition for CSI_PRGITR register ******************/ #define CSI_PRGITR_LB0VC_Pos (0U) #define CSI_PRGITR_LB0VC_Msk (0x3UL << CSI_PRGITR_LB0VC_Pos) /*!< 0x00000003 */ #define CSI_PRGITR_LB0VC CSI_PRGITR_LB0VC_Msk /*!< Line/Byte counter 0 linked to a virtual channel */ #define CSI_PRGITR_LB0EN_Pos (3U) #define CSI_PRGITR_LB0EN_Msk (0x1UL << CSI_PRGITR_LB0EN_Pos) /*!< 0x00000008 */ #define CSI_PRGITR_LB0EN CSI_PRGITR_LB0EN_Msk /*!< Line/Byte 0counter enable */ #define CSI_PRGITR_LB1VC_Pos (4U) #define CSI_PRGITR_LB1VC_Msk (0x3UL << CSI_PRGITR_LB1VC_Pos) /*!< 0x00000030 */ #define CSI_PRGITR_LB1VC CSI_PRGITR_LB1VC_Msk /*!< Line/Byte counter 1 linked to a virtual channel */ #define CSI_PRGITR_LB1EN_Pos (7U) #define CSI_PRGITR_LB1EN_Msk (0x1UL << CSI_PRGITR_LB1EN_Pos) /*!< 0x00000080 */ #define CSI_PRGITR_LB1EN CSI_PRGITR_LB1EN_Msk /*!< Line/Byte 1 counter enable */ #define CSI_PRGITR_LB2VC_Pos (8U) #define CSI_PRGITR_LB2VC_Msk (0x3UL << CSI_PRGITR_LB2VC_Pos) /*!< 0x00000300 */ #define CSI_PRGITR_LB2VC CSI_PRGITR_LB2VC_Msk /*!< Line/Byte counter 2 linked to a virtual channel */ #define CSI_PRGITR_LB2EN_Pos (11U) #define CSI_PRGITR_LB2EN_Msk (0x1UL << CSI_PRGITR_LB2EN_Pos) /*!< 0x00000800 */ #define CSI_PRGITR_LB2EN CSI_PRGITR_LB2EN_Msk /*!< Line/Byte 2 counter enable */ #define CSI_PRGITR_LB3VC_Pos (12U) #define CSI_PRGITR_LB3VC_Msk (0x3UL << CSI_PRGITR_LB3VC_Pos) /*!< 0x00003000 */ #define CSI_PRGITR_LB3VC CSI_PRGITR_LB3VC_Msk /*!< Line/Byte counter 3 linked to a virtual channel */ #define CSI_PRGITR_LB3EN_Pos (15U) #define CSI_PRGITR_LB3EN_Msk (0x1UL << CSI_PRGITR_LB3EN_Pos) /*!< 0x00008000 */ #define CSI_PRGITR_LB3EN CSI_PRGITR_LB3EN_Msk /*!< Line/Byte 3 counter enable */ #define CSI_PRGITR_TIM0VC_Pos (16U) #define CSI_PRGITR_TIM0VC_Msk (0x3UL << CSI_PRGITR_TIM0VC_Pos) /*!< 0x00030000 */ #define CSI_PRGITR_TIM0VC CSI_PRGITR_TIM0VC_Msk /*!< TIM0 base time linked to a virtual channel */ #define CSI_PRGITR_TIM0EOF_Pos (18U) #define CSI_PRGITR_TIM0EOF_Msk (0x1UL << CSI_PRGITR_TIM0EOF_Pos) /*!< 0x00040000 */ #define CSI_PRGITR_TIM0EOF CSI_PRGITR_TIM0EOF_Msk /*!< TIM0 base time starting from the end of frame */ #define CSI_PRGITR_TIM0EN_Pos (19U) #define CSI_PRGITR_TIM0EN_Msk (0x1UL << CSI_PRGITR_TIM0EN_Pos) /*!< 0x00080000 */ #define CSI_PRGITR_TIM0EN CSI_PRGITR_TIM0EN_Msk /*!< TIM0 base time enable */ #define CSI_PRGITR_TIM1VC_Pos (20U) #define CSI_PRGITR_TIM1VC_Msk (0x3UL << CSI_PRGITR_TIM1VC_Pos) /*!< 0x00300000 */ #define CSI_PRGITR_TIM1VC CSI_PRGITR_TIM1VC_Msk /*!< TIM1 base time linked to a virtual channel */ #define CSI_PRGITR_TIM1EOF_Pos (22U) #define CSI_PRGITR_TIM1EOF_Msk (0x1UL << CSI_PRGITR_TIM1EOF_Pos) /*!< 0x00400000 */ #define CSI_PRGITR_TIM1EOF CSI_PRGITR_TIM1EOF_Msk /*!< TIM1 base time starting from the end of frame */ #define CSI_PRGITR_TIM1EN_Pos (23U) #define CSI_PRGITR_TIM1EN_Msk (0x1UL << CSI_PRGITR_TIM1EN_Pos) /*!< 0x00800000 */ #define CSI_PRGITR_TIM1EN CSI_PRGITR_TIM1EN_Msk /*!< TIM1 base time enable */ #define CSI_PRGITR_TIM2VC_Pos (24U) #define CSI_PRGITR_TIM2VC_Msk (0x3UL << CSI_PRGITR_TIM2VC_Pos) /*!< 0x03000000 */ #define CSI_PRGITR_TIM2VC CSI_PRGITR_TIM2VC_Msk /*!< TIM2 base time linked to a virtual channel */ #define CSI_PRGITR_TIM2EOF_Pos (26U) #define CSI_PRGITR_TIM2EOF_Msk (0x1UL << CSI_PRGITR_TIM2EOF_Pos) /*!< 0x04000000 */ #define CSI_PRGITR_TIM2EOF CSI_PRGITR_TIM2EOF_Msk /*!< TIM2 base time starting from the end of frame */ #define CSI_PRGITR_TIM2EN_Pos (27U) #define CSI_PRGITR_TIM2EN_Msk (0x1UL << CSI_PRGITR_TIM2EN_Pos) /*!< 0x08000000 */ #define CSI_PRGITR_TIM2EN CSI_PRGITR_TIM2EN_Msk /*!< TIM2 base time enable */ #define CSI_PRGITR_TIM3VC_Pos (28U) #define CSI_PRGITR_TIM3VC_Msk (0x3UL << CSI_PRGITR_TIM3VC_Pos) /*!< 0x30000000 */ #define CSI_PRGITR_TIM3VC CSI_PRGITR_TIM3VC_Msk /*!< TIM3 base time linked to a virtual channel */ #define CSI_PRGITR_TIM3EOF_Pos (30U) #define CSI_PRGITR_TIM3EOF_Msk (0x1UL << CSI_PRGITR_TIM3EOF_Pos) /*!< 0x40000000 */ #define CSI_PRGITR_TIM3EOF CSI_PRGITR_TIM3EOF_Msk /*!< TIM3 base time starting from the end of frame */ #define CSI_PRGITR_TIM3EN_Pos (31U) #define CSI_PRGITR_TIM3EN_Msk (0x1UL << CSI_PRGITR_TIM3EN_Pos) /*!< 0x80000000 */ #define CSI_PRGITR_TIM3EN CSI_PRGITR_TIM3EN_Msk /*!< TIM3 base time enable */ /******************* Bit definition for CSI_WDR register ********************/ #define CSI_WDR_CNT_Pos (0U) #define CSI_WDR_CNT_Msk (0xFFFFFFFFUL << CSI_WDR_CNT_Pos) /*!< 0xFFFFFFFF */ #define CSI_WDR_CNT CSI_WDR_CNT_Msk /*!< Watchdog counter */ /******************* Bit definition for CSI_IER0 register *******************/ #define CSI_IER0_LB0IE_Pos (0U) #define CSI_IER0_LB0IE_Msk (0x1UL << CSI_IER0_LB0IE_Pos) /*!< 0x00000001 */ #define CSI_IER0_LB0IE CSI_IER0_LB0IE_Msk /*!< Line byte counter 0 interrupt enable */ #define CSI_IER0_LB1IE_Pos (1U) #define CSI_IER0_LB1IE_Msk (0x1UL << CSI_IER0_LB1IE_Pos) /*!< 0x00000002 */ #define CSI_IER0_LB1IE CSI_IER0_LB1IE_Msk /*!< Line byte counter 1 interrupt enable */ #define CSI_IER0_LB2IE_Pos (2U) #define CSI_IER0_LB2IE_Msk (0x1UL << CSI_IER0_LB2IE_Pos) /*!< 0x00000004 */ #define CSI_IER0_LB2IE CSI_IER0_LB2IE_Msk /*!< Line byte counter 2 interrupt enable */ #define CSI_IER0_LB3IE_Pos (3U) #define CSI_IER0_LB3IE_Msk (0x1UL << CSI_IER0_LB3IE_Pos) /*!< 0x00000008 */ #define CSI_IER0_LB3IE CSI_IER0_LB3IE_Msk /*!< Line byte counter 3 interrupt enable */ #define CSI_IER0_TIM0IE_Pos (4U) #define CSI_IER0_TIM0IE_Msk (0x1UL << CSI_IER0_TIM0IE_Pos) /*!< 0x00000010 */ #define CSI_IER0_TIM0IE CSI_IER0_TIM0IE_Msk /*!< Timer 0 interrupt enable */ #define CSI_IER0_TIM1IE_Pos (5U) #define CSI_IER0_TIM1IE_Msk (0x1UL << CSI_IER0_TIM1IE_Pos) /*!< 0x00000020 */ #define CSI_IER0_TIM1IE CSI_IER0_TIM1IE_Msk /*!< Timer 1 interrupt enable */ #define CSI_IER0_TIM2IE_Pos (6U) #define CSI_IER0_TIM2IE_Msk (0x1UL << CSI_IER0_TIM2IE_Pos) /*!< 0x00000040 */ #define CSI_IER0_TIM2IE CSI_IER0_TIM2IE_Msk /*!< Timer 2 interrupt enable */ #define CSI_IER0_TIM3IE_Pos (7U) #define CSI_IER0_TIM3IE_Msk (0x1UL << CSI_IER0_TIM3IE_Pos) /*!< 0x00000080 */ #define CSI_IER0_TIM3IE CSI_IER0_TIM3IE_Msk /*!< Timer 3 interrupt enable */ #define CSI_IER0_SOF0IE_Pos (8U) #define CSI_IER0_SOF0IE_Msk (0x1UL << CSI_IER0_SOF0IE_Pos) /*!< 0x00000100 */ #define CSI_IER0_SOF0IE CSI_IER0_SOF0IE_Msk /*!< Start of frame for virtual channel 0 interrupt enable */ #define CSI_IER0_SOF1IE_Pos (9U) #define CSI_IER0_SOF1IE_Msk (0x1UL << CSI_IER0_SOF1IE_Pos) /*!< 0x00000200 */ #define CSI_IER0_SOF1IE CSI_IER0_SOF1IE_Msk /*!< Start of frame for virtual channel 1 interrupt enable */ #define CSI_IER0_SOF2IE_Pos (10U) #define CSI_IER0_SOF2IE_Msk (0x1UL << CSI_IER0_SOF2IE_Pos) /*!< 0x00000400 */ #define CSI_IER0_SOF2IE CSI_IER0_SOF2IE_Msk /*!< Start of frame for virtual channel 2 interrupt enable */ #define CSI_IER0_SOF3IE_Pos (11U) #define CSI_IER0_SOF3IE_Msk (0x1UL << CSI_IER0_SOF3IE_Pos) /*!< 0x00000800 */ #define CSI_IER0_SOF3IE CSI_IER0_SOF3IE_Msk /*!< Start of frame for virtual channel 3 interrupt enable */ #define CSI_IER0_EOF0IE_Pos (12U) #define CSI_IER0_EOF0IE_Msk (0x1UL << CSI_IER0_EOF0IE_Pos) /*!< 0x00001000 */ #define CSI_IER0_EOF0IE CSI_IER0_EOF0IE_Msk /*!< End of frame for virtual channel 0 interrupt enable */ #define CSI_IER0_EOF1IE_Pos (13U) #define CSI_IER0_EOF1IE_Msk (0x1UL << CSI_IER0_EOF1IE_Pos) /*!< 0x00002000 */ #define CSI_IER0_EOF1IE CSI_IER0_EOF1IE_Msk /*!< End of frame for virtual channel 1 interrupt enable */ #define CSI_IER0_EOF2IE_Pos (14U) #define CSI_IER0_EOF2IE_Msk (0x1UL << CSI_IER0_EOF2IE_Pos) /*!< 0x00004000 */ #define CSI_IER0_EOF2IE CSI_IER0_EOF2IE_Msk /*!< End of frame for virtual channel 2 interrupt enable */ #define CSI_IER0_EOF3IE_Pos (15U) #define CSI_IER0_EOF3IE_Msk (0x1UL << CSI_IER0_EOF3IE_Pos) /*!< 0x00008000 */ #define CSI_IER0_EOF3IE CSI_IER0_EOF3IE_Msk /*!< End of frame for virtual channel 3 interrupt enable */ #define CSI_IER0_SPKTIE_Pos (16U) #define CSI_IER0_SPKTIE_Msk (0x1UL << CSI_IER0_SPKTIE_Pos) /*!< 0x00010000 */ #define CSI_IER0_SPKTIE CSI_IER0_SPKTIE_Msk /*!< Short packet interrupt enable */ #define CSI_IER0_CCFIFOFIE_Pos (21U) #define CSI_IER0_CCFIFOFIE_Msk (0x1UL << CSI_IER0_CCFIFOFIE_Pos) /*!< 0x00200000 */ #define CSI_IER0_CCFIFOFIE CSI_IER0_CCFIFOFIE_Msk /*!< Clock changer FIFO full interrupt enable */ #define CSI_IER0_CRCERRIE_Pos (24U) #define CSI_IER0_CRCERRIE_Msk (0x1UL << CSI_IER0_CRCERRIE_Pos) /*!< 0x01000000 */ #define CSI_IER0_CRCERRIE CSI_IER0_CRCERRIE_Msk /*!< CRC error interrupt enable */ #define CSI_IER0_ECCERRIE_Pos (25U) #define CSI_IER0_ECCERRIE_Msk (0x1UL << CSI_IER0_ECCERRIE_Pos) /*!< 0x02000000 */ #define CSI_IER0_ECCERRIE CSI_IER0_ECCERRIE_Msk /*!< ECC error interrupt enable */ #define CSI_IER0_CECCERRIE_Pos (26U) #define CSI_IER0_CECCERRIE_Msk (0x1UL << CSI_IER0_CECCERRIE_Pos) /*!< 0x04000000 */ #define CSI_IER0_CECCERRIE CSI_IER0_CECCERRIE_Msk /*!< Corrected ECC error interrupt enable */ #define CSI_IER0_IDERRIE_Pos (27U) #define CSI_IER0_IDERRIE_Msk (0x1UL << CSI_IER0_IDERRIE_Pos) /*!< 0x08000000 */ #define CSI_IER0_IDERRIE CSI_IER0_IDERRIE_Msk /*!< Data type ID error interrupt enable */ #define CSI_IER0_SPKTERRIE_Pos (28U) #define CSI_IER0_SPKTERRIE_Msk (0x1UL << CSI_IER0_SPKTERRIE_Pos) /*!< 0x10000000 */ #define CSI_IER0_SPKTERRIE CSI_IER0_SPKTERRIE_Msk /*!< Short packet error interrupt enable */ #define CSI_IER0_WDERRIE_Pos (29U) #define CSI_IER0_WDERRIE_Msk (0x1UL << CSI_IER0_WDERRIE_Pos) /*!< 0x20000000 */ #define CSI_IER0_WDERRIE CSI_IER0_WDERRIE_Msk /*!< Watchdog error interrupt enable */ #define CSI_IER0_SYNCERRIE_Pos (30U) #define CSI_IER0_SYNCERRIE_Msk (0x1UL << CSI_IER0_SYNCERRIE_Pos) /*!< 0x40000000 */ #define CSI_IER0_SYNCERRIE CSI_IER0_SYNCERRIE_Msk /*!< Invalid synchronization error interrupt enable */ /******************* Bit definition for CSI_IER1 register *******************/ #define CSI_IER1_ESOTDL0IE_Pos (0U) #define CSI_IER1_ESOTDL0IE_Msk (0x1UL << CSI_IER1_ESOTDL0IE_Pos) /*!< 0x00000001 */ #define CSI_IER1_ESOTDL0IE CSI_IER1_ESOTDL0IE_Msk /*!< Start of transmission error interrupt enable on lane 0 */ #define CSI_IER1_ESOTSYNCDL0IE_Pos (1U) #define CSI_IER1_ESOTSYNCDL0IE_Msk (0x1UL << CSI_IER1_ESOTSYNCDL0IE_Pos) /*!< 0x00000002 */ #define CSI_IER1_ESOTSYNCDL0IE CSI_IER1_ESOTSYNCDL0IE_Msk /*!< Start of transmission synchronization interrupt error enable on lane 0 */ #define CSI_IER1_EESCDL0IE_Pos (2U) #define CSI_IER1_EESCDL0IE_Msk (0x1UL << CSI_IER1_EESCDL0IE_Pos) /*!< 0x00000004 */ #define CSI_IER1_EESCDL0IE CSI_IER1_EESCDL0IE_Msk /*!< D-PHY_RX lane 0 escape entry error interrupt enable */ #define CSI_IER1_ESYNCESCDL0IE_Pos (3U) #define CSI_IER1_ESYNCESCDL0IE_Msk (0x1UL << CSI_IER1_ESYNCESCDL0IE_Pos) /*!< 0x00000008 */ #define CSI_IER1_ESYNCESCDL0IE CSI_IER1_ESYNCESCDL0IE_Msk /*!< D-PHY_RX lane 0 low power data transmission synchronization error interrupt enable */ #define CSI_IER1_ECTRLDL0IE_Pos (4U) #define CSI_IER1_ECTRLDL0IE_Msk (0x1UL << CSI_IER1_ECTRLDL0IE_Pos) /*!< 0x00000010 */ #define CSI_IER1_ECTRLDL0IE CSI_IER1_ECTRLDL0IE_Msk /*!< D-PHY_RX lane 0 control error interrupt enable */ #define CSI_IER1_ESOTDL1IE_Pos (8U) #define CSI_IER1_ESOTDL1IE_Msk (0x1UL << CSI_IER1_ESOTDL1IE_Pos) /*!< 0x00000100 */ #define CSI_IER1_ESOTDL1IE CSI_IER1_ESOTDL1IE_Msk /*!< Start of transmission error interrupt enable on lane 1 */ #define CSI_IER1_ESOTSYNCDL1IE_Pos (9U) #define CSI_IER1_ESOTSYNCDL1IE_Msk (0x1UL << CSI_IER1_ESOTSYNCDL1IE_Pos) /*!< 0x00000200 */ #define CSI_IER1_ESOTSYNCDL1IE CSI_IER1_ESOTSYNCDL1IE_Msk /*!< Start of transmission synchronization interrupt error enable on lane 1 */ #define CSI_IER1_EESCDL1IE_Pos (10U) #define CSI_IER1_EESCDL1IE_Msk (0x1UL << CSI_IER1_EESCDL1IE_Pos) /*!< 0x00000400 */ #define CSI_IER1_EESCDL1IE CSI_IER1_EESCDL1IE_Msk /*!< D-PHY_RX lane 1 escape entry error interrupt enable */ #define CSI_IER1_ESYNCESCDL1IE_Pos (11U) #define CSI_IER1_ESYNCESCDL1IE_Msk (0x1UL << CSI_IER1_ESYNCESCDL1IE_Pos) /*!< 0x00000800 */ #define CSI_IER1_ESYNCESCDL1IE CSI_IER1_ESYNCESCDL1IE_Msk /*!< D-PHY_RX lane 1 low power data transmission synchronization error interrupt enable */ #define CSI_IER1_ECTRLDL1IE_Pos (12U) #define CSI_IER1_ECTRLDL1IE_Msk (0x1UL << CSI_IER1_ECTRLDL1IE_Pos) /*!< 0x00001000 */ #define CSI_IER1_ECTRLDL1IE CSI_IER1_ECTRLDL1IE_Msk /*!< D-PHY_RX lane 1 control error interrupt enable */ /******************* Bit definition for CSI_SR0 register ********************/ #define CSI_SR0_LB0F_Pos (0U) #define CSI_SR0_LB0F_Msk (0x1UL << CSI_SR0_LB0F_Pos) /*!< 0x00000001 */ #define CSI_SR0_LB0F CSI_SR0_LB0F_Msk /*!< Line byte counter 0 flag */ #define CSI_SR0_LB1F_Pos (1U) #define CSI_SR0_LB1F_Msk (0x1UL << CSI_SR0_LB1F_Pos) /*!< 0x00000002 */ #define CSI_SR0_LB1F CSI_SR0_LB1F_Msk /*!< Line byte counter 1 flag */ #define CSI_SR0_LB2F_Pos (2U) #define CSI_SR0_LB2F_Msk (0x1UL << CSI_SR0_LB2F_Pos) /*!< 0x00000004 */ #define CSI_SR0_LB2F CSI_SR0_LB2F_Msk /*!< Line byte counter 2 flag */ #define CSI_SR0_LB3F_Pos (3U) #define CSI_SR0_LB3F_Msk (0x1UL << CSI_SR0_LB3F_Pos) /*!< 0x00000008 */ #define CSI_SR0_LB3F CSI_SR0_LB3F_Msk /*!< Line byte counter 3 flag */ #define CSI_SR0_TIM0F_Pos (4U) #define CSI_SR0_TIM0F_Msk (0x1UL << CSI_SR0_TIM0F_Pos) /*!< 0x00000010 */ #define CSI_SR0_TIM0F CSI_SR0_TIM0F_Msk /*!< Timer 0 flag */ #define CSI_SR0_TIM1F_Pos (5U) #define CSI_SR0_TIM1F_Msk (0x1UL << CSI_SR0_TIM1F_Pos) /*!< 0x00000020 */ #define CSI_SR0_TIM1F CSI_SR0_TIM1F_Msk /*!< Timer 1 flag */ #define CSI_SR0_TIM2F_Pos (6U) #define CSI_SR0_TIM2F_Msk (0x1UL << CSI_SR0_TIM2F_Pos) /*!< 0x00000040 */ #define CSI_SR0_TIM2F CSI_SR0_TIM2F_Msk /*!< Timer 2 flag */ #define CSI_SR0_TIM3F_Pos (7U) #define CSI_SR0_TIM3F_Msk (0x1UL << CSI_SR0_TIM3F_Pos) /*!< 0x00000080 */ #define CSI_SR0_TIM3F CSI_SR0_TIM3F_Msk /*!< Timer 3 flag */ #define CSI_SR0_SOF0F_Pos (8U) #define CSI_SR0_SOF0F_Msk (0x1UL << CSI_SR0_SOF0F_Pos) /*!< 0x00000100 */ #define CSI_SR0_SOF0F CSI_SR0_SOF0F_Msk /*!< Start of frame flag for virtual channel 0 */ #define CSI_SR0_SOF1F_Pos (9U) #define CSI_SR0_SOF1F_Msk (0x1UL << CSI_SR0_SOF1F_Pos) /*!< 0x00000200 */ #define CSI_SR0_SOF1F CSI_SR0_SOF1F_Msk /*!< Start of frame flag for virtual channel 1 */ #define CSI_SR0_SOF2F_Pos (10U) #define CSI_SR0_SOF2F_Msk (0x1UL << CSI_SR0_SOF2F_Pos) /*!< 0x00000400 */ #define CSI_SR0_SOF2F CSI_SR0_SOF2F_Msk /*!< Start of frame flag for virtual channel 2 */ #define CSI_SR0_SOF3F_Pos (11U) #define CSI_SR0_SOF3F_Msk (0x1UL << CSI_SR0_SOF3F_Pos) /*!< 0x00000800 */ #define CSI_SR0_SOF3F CSI_SR0_SOF3F_Msk /*!< Start of frame flag for virtual channel 3 */ #define CSI_SR0_EOF0F_Pos (12U) #define CSI_SR0_EOF0F_Msk (0x1UL << CSI_SR0_EOF0F_Pos) /*!< 0x00001000 */ #define CSI_SR0_EOF0F CSI_SR0_EOF0F_Msk /*!< End of frame flag for virtual channel 0 */ #define CSI_SR0_EOF1F_Pos (13U) #define CSI_SR0_EOF1F_Msk (0x1UL << CSI_SR0_EOF1F_Pos) /*!< 0x00002000 */ #define CSI_SR0_EOF1F CSI_SR0_EOF1F_Msk /*!< End of frame flag for virtual channel 1 */ #define CSI_SR0_EOF2F_Pos (14U) #define CSI_SR0_EOF2F_Msk (0x1UL << CSI_SR0_EOF2F_Pos) /*!< 0x00004000 */ #define CSI_SR0_EOF2F CSI_SR0_EOF2F_Msk /*!< End of frame flag for virtual channel 2 */ #define CSI_SR0_EOF3F_Pos (15U) #define CSI_SR0_EOF3F_Msk (0x1UL << CSI_SR0_EOF3F_Pos) /*!< 0x00008000 */ #define CSI_SR0_EOF3F CSI_SR0_EOF3F_Msk /*!< End of frame flag for virtual channel 3 */ #define CSI_SR0_SPKTF_Pos (16U) #define CSI_SR0_SPKTF_Msk (0x1UL << CSI_SR0_SPKTF_Pos) /*!< 0x00010000 */ #define CSI_SR0_SPKTF CSI_SR0_SPKTF_Msk /*!< Short packet flag */ #define CSI_SR0_VC0STATEF_Pos (17U) #define CSI_SR0_VC0STATEF_Msk (0x1UL << CSI_SR0_VC0STATEF_Pos) /*!< 0x00020000 */ #define CSI_SR0_VC0STATEF CSI_SR0_VC0STATEF_Msk /*!< Virtual channel 0 state flag */ #define CSI_SR0_VC1STATEF_Pos (18U) #define CSI_SR0_VC1STATEF_Msk (0x1UL << CSI_SR0_VC1STATEF_Pos) /*!< 0x00040000 */ #define CSI_SR0_VC1STATEF CSI_SR0_VC1STATEF_Msk /*!< Virtual channel 1 state flag */ #define CSI_SR0_VC2STATEF_Pos (19U) #define CSI_SR0_VC2STATEF_Msk (0x1UL << CSI_SR0_VC2STATEF_Pos) /*!< 0x00080000 */ #define CSI_SR0_VC2STATEF CSI_SR0_VC2STATEF_Msk /*!< Virtual channel 2 state flag */ #define CSI_SR0_VC3STATEF_Pos (20U) #define CSI_SR0_VC3STATEF_Msk (0x1UL << CSI_SR0_VC3STATEF_Pos) /*!< 0x00100000 */ #define CSI_SR0_VC3STATEF CSI_SR0_VC3STATEF_Msk /*!< Virtual channel 3 state flag */ #define CSI_SR0_CCFIFOFF_Pos (21U) #define CSI_SR0_CCFIFOFF_Msk (0x1UL << CSI_SR0_CCFIFOFF_Pos) /*!< 0x00200000 */ #define CSI_SR0_CCFIFOFF CSI_SR0_CCFIFOFF_Msk /*!< Clock changer FIFO full flag */ #define CSI_SR0_CRCERRF_Pos (24U) #define CSI_SR0_CRCERRF_Msk (0x1UL << CSI_SR0_CRCERRF_Pos) /*!< 0x01000000 */ #define CSI_SR0_CRCERRF CSI_SR0_CRCERRF_Msk /*!< CRC error flag */ #define CSI_SR0_ECCERRF_Pos (25U) #define CSI_SR0_ECCERRF_Msk (0x1UL << CSI_SR0_ECCERRF_Pos) /*!< 0x02000000 */ #define CSI_SR0_ECCERRF CSI_SR0_ECCERRF_Msk /*!< ECC error flag */ #define CSI_SR0_CECCERRF_Pos (26U) #define CSI_SR0_CECCERRF_Msk (0x1UL << CSI_SR0_CECCERRF_Pos) /*!< 0x04000000 */ #define CSI_SR0_CECCERRF CSI_SR0_CECCERRF_Msk /*!< Corrected ECC error flag */ #define CSI_SR0_IDERRF_Pos (27U) #define CSI_SR0_IDERRF_Msk (0x1UL << CSI_SR0_IDERRF_Pos) /*!< 0x08000000 */ #define CSI_SR0_IDERRF CSI_SR0_IDERRF_Msk /*!< Data type ID error flag */ #define CSI_SR0_SPKTERRF_Pos (28U) #define CSI_SR0_SPKTERRF_Msk (0x1UL << CSI_SR0_SPKTERRF_Pos) /*!< 0x10000000 */ #define CSI_SR0_SPKTERRF CSI_SR0_SPKTERRF_Msk /*!< Short packet error flag */ #define CSI_SR0_WDERRF_Pos (29U) #define CSI_SR0_WDERRF_Msk (0x1UL << CSI_SR0_WDERRF_Pos) /*!< 0x20000000 */ #define CSI_SR0_WDERRF CSI_SR0_WDERRF_Msk /*!< Watchdog error flag */ #define CSI_SR0_SYNCERRF_Pos (30U) #define CSI_SR0_SYNCERRF_Msk (0x1UL << CSI_SR0_SYNCERRF_Pos) /*!< 0x40000000 */ #define CSI_SR0_SYNCERRF CSI_SR0_SYNCERRF_Msk /*!< Invalid synchronization error flag */ /******************* Bit definition for CSI_SR1 register ********************/ #define CSI_SR1_ESOTDL0F_Pos (0U) #define CSI_SR1_ESOTDL0F_Msk (0x1UL << CSI_SR1_ESOTDL0F_Pos) /*!< 0x00000001 */ #define CSI_SR1_ESOTDL0F CSI_SR1_ESOTDL0F_Msk /*!< Start of transmission error flag on lane 0 */ #define CSI_SR1_ESOTSYNCDL0F_Pos (1U) #define CSI_SR1_ESOTSYNCDL0F_Msk (0x1UL << CSI_SR1_ESOTSYNCDL0F_Pos) /*!< 0x00000002 */ #define CSI_SR1_ESOTSYNCDL0F CSI_SR1_ESOTSYNCDL0F_Msk /*!< Start of transmission synchronization error flag on lane 0 */ #define CSI_SR1_EESCDL0F_Pos (2U) #define CSI_SR1_EESCDL0F_Msk (0x1UL << CSI_SR1_EESCDL0F_Pos) /*!< 0x00000004 */ #define CSI_SR1_EESCDL0F CSI_SR1_EESCDL0F_Msk /*!< D-PHY_RX lane 0 escape entry error flag */ #define CSI_SR1_ESYNCESCDL0F_Pos (3U) #define CSI_SR1_ESYNCESCDL0F_Msk (0x1UL << CSI_SR1_ESYNCESCDL0F_Pos) /*!< 0x00000008 */ #define CSI_SR1_ESYNCESCDL0F CSI_SR1_ESYNCESCDL0F_Msk /*!< D-PHY_RX lane 0 low power data transmission synchronization error flag */ #define CSI_SR1_ECTRLDL0F_Pos (4U) #define CSI_SR1_ECTRLDL0F_Msk (0x1UL << CSI_SR1_ECTRLDL0F_Pos) /*!< 0x00000010 */ #define CSI_SR1_ECTRLDL0F CSI_SR1_ECTRLDL0F_Msk /*!< D-PHY_RX lane 0 control error flag */ #define CSI_SR1_ESOTDL1F_Pos (8U) #define CSI_SR1_ESOTDL1F_Msk (0x1UL << CSI_SR1_ESOTDL1F_Pos) /*!< 0x00000100 */ #define CSI_SR1_ESOTDL1F CSI_SR1_ESOTDL1F_Msk /*!< Start of transmission error flag on lane 1 */ #define CSI_SR1_ESOTSYNCDL1F_Pos (9U) #define CSI_SR1_ESOTSYNCDL1F_Msk (0x1UL << CSI_SR1_ESOTSYNCDL1F_Pos) /*!< 0x00000200 */ #define CSI_SR1_ESOTSYNCDL1F CSI_SR1_ESOTSYNCDL1F_Msk /*!< Start of transmission synchronization error flag on lane 1 */ #define CSI_SR1_EESCDL1F_Pos (10U) #define CSI_SR1_EESCDL1F_Msk (0x1UL << CSI_SR1_EESCDL1F_Pos) /*!< 0x00000400 */ #define CSI_SR1_EESCDL1F CSI_SR1_EESCDL1F_Msk /*!< D-PHY_RX lane 1 escape entry error flag */ #define CSI_SR1_ESYNCESCDL1F_Pos (11U) #define CSI_SR1_ESYNCESCDL1F_Msk (0x1UL << CSI_SR1_ESYNCESCDL1F_Pos) /*!< 0x00000800 */ #define CSI_SR1_ESYNCESCDL1F CSI_SR1_ESYNCESCDL1F_Msk /*!< D-PHY_RX lane 1 low power data transmission synchronization error flag */ #define CSI_SR1_ECTRLDL1F_Pos (12U) #define CSI_SR1_ECTRLDL1F_Msk (0x1UL << CSI_SR1_ECTRLDL1F_Pos) /*!< 0x00001000 */ #define CSI_SR1_ECTRLDL1F CSI_SR1_ECTRLDL1F_Msk /*!< D-PHY_RX lane 1 control error flag */ #define CSI_SR1_ACTDL0F_Pos (16U) #define CSI_SR1_ACTDL0F_Msk (0x1UL << CSI_SR1_ACTDL0F_Pos) /*!< 0x00010000 */ #define CSI_SR1_ACTDL0F CSI_SR1_ACTDL0F_Msk /*!< D-PHY_RX lane 0 High speed reception active */ #define CSI_SR1_SYNCDL0F_Pos (17U) #define CSI_SR1_SYNCDL0F_Msk (0x1UL << CSI_SR1_SYNCDL0F_Pos) /*!< 0x00020000 */ #define CSI_SR1_SYNCDL0F CSI_SR1_SYNCDL0F_Msk /*!< D-PHY_RX lane 0 receiver synchronization observed */ #define CSI_SR1_SKCALDL0F_Pos (18U) #define CSI_SR1_SKCALDL0F_Msk (0x1UL << CSI_SR1_SKCALDL0F_Pos) /*!< 0x00040000 */ #define CSI_SR1_SKCALDL0F CSI_SR1_SKCALDL0F_Msk /*!< D-PHY_RX lane 0 High speed skew calibration */ #define CSI_SR1_STOPDL0F_Pos (19U) #define CSI_SR1_STOPDL0F_Msk (0x1UL << CSI_SR1_STOPDL0F_Pos) /*!< 0x00080000 */ #define CSI_SR1_STOPDL0F CSI_SR1_STOPDL0F_Msk /*!< D-PHY_RX receiver data lane 0 in stop state */ #define CSI_SR1_ULPNDL0F_Pos (20U) #define CSI_SR1_ULPNDL0F_Msk (0x1UL << CSI_SR1_ULPNDL0F_Pos) /*!< 0x00100000 */ #define CSI_SR1_ULPNDL0F CSI_SR1_ULPNDL0F_Msk /*!< D-PHY_RX receiver Ultra low power state (not) Active on data lane 00 */ #define CSI_SR1_ACTDL1F_Pos (22U) #define CSI_SR1_ACTDL1F_Msk (0x1UL << CSI_SR1_ACTDL1F_Pos) /*!< 0x00400000 */ #define CSI_SR1_ACTDL1F CSI_SR1_ACTDL1F_Msk /*!< D-PHY_RX lane 1 High speed reception active */ #define CSI_SR1_SYNCDL1F_Pos (23U) #define CSI_SR1_SYNCDL1F_Msk (0x1UL << CSI_SR1_SYNCDL1F_Pos) /*!< 0x00800000 */ #define CSI_SR1_SYNCDL1F CSI_SR1_SYNCDL1F_Msk /*!< D-PHY_RX lane 1 receiver synchronization observed */ #define CSI_SR1_SKCALDL1F_Pos (24U) #define CSI_SR1_SKCALDL1F_Msk (0x1UL << CSI_SR1_SKCALDL1F_Pos) /*!< 0x01000000 */ #define CSI_SR1_SKCALDL1F CSI_SR1_SKCALDL1F_Msk /*!< D-PHY_RX lane 1 High speed skew calibration */ #define CSI_SR1_STOPDL1F_Pos (25U) #define CSI_SR1_STOPDL1F_Msk (0x1UL << CSI_SR1_STOPDL1F_Pos) /*!< 0x02000000 */ #define CSI_SR1_STOPDL1F CSI_SR1_STOPDL1F_Msk /*!< D-PHY_RX receiver data lane 1 in stop state */ #define CSI_SR1_ULPNDL1F_Pos (26U) #define CSI_SR1_ULPNDL1F_Msk (0x1UL << CSI_SR1_ULPNDL1F_Pos) /*!< 0x04000000 */ #define CSI_SR1_ULPNDL1F CSI_SR1_ULPNDL1F_Msk /*!< D-PHY_RX receiver Ultra low power state (not) Active on data lane 1 */ #define CSI_SR1_STOPCLF_Pos (28U) #define CSI_SR1_STOPCLF_Msk (0x1UL << CSI_SR1_STOPCLF_Pos) /*!< 0x10000000 */ #define CSI_SR1_STOPCLF CSI_SR1_STOPCLF_Msk /*!< D-PHY_RX receiver in stop state for the clock lane */ #define CSI_SR1_ULPNACTF_Pos (29U) #define CSI_SR1_ULPNACTF_Msk (0x1UL << CSI_SR1_ULPNACTF_Pos) /*!< 0x20000000 */ #define CSI_SR1_ULPNACTF CSI_SR1_ULPNACTF_Msk /*!< D-PHY_RX receiver ULP state (not) active */ #define CSI_SR1_ULPNCLF_Pos (30U) #define CSI_SR1_ULPNCLF_Msk (0x1UL << CSI_SR1_ULPNCLF_Pos) /*!< 0x40000000 */ #define CSI_SR1_ULPNCLF CSI_SR1_ULPNCLF_Msk /*!< D-PHY_RX receiver Ultra-Low power state (not) on clock lane */ #define CSI_SR1_ACTCLF_Pos (31U) #define CSI_SR1_ACTCLF_Msk (0x1UL << CSI_SR1_ACTCLF_Pos) /*!< 0x80000000 */ #define CSI_SR1_ACTCLF CSI_SR1_ACTCLF_Msk /*!< D-PHY_RX receiver clock active flag */ /******************* Bit definition for CSI_FCR0 register *******************/ #define CSI_FCR0_CLB0F_Pos (0U) #define CSI_FCR0_CLB0F_Msk (0x1UL << CSI_FCR0_CLB0F_Pos) /*!< 0x00000001 */ #define CSI_FCR0_CLB0F CSI_FCR0_CLB0F_Msk /*!< Clear Line byte counter 0 flag */ #define CSI_FCR0_CLB1F_Pos (1U) #define CSI_FCR0_CLB1F_Msk (0x1UL << CSI_FCR0_CLB1F_Pos) /*!< 0x00000002 */ #define CSI_FCR0_CLB1F CSI_FCR0_CLB1F_Msk /*!< Clear Line byte counter 1 flag */ #define CSI_FCR0_CLB2F_Pos (2U) #define CSI_FCR0_CLB2F_Msk (0x1UL << CSI_FCR0_CLB2F_Pos) /*!< 0x00000004 */ #define CSI_FCR0_CLB2F CSI_FCR0_CLB2F_Msk /*!< Clear Line byte counter 2 flag */ #define CSI_FCR0_CLB3F_Pos (3U) #define CSI_FCR0_CLB3F_Msk (0x1UL << CSI_FCR0_CLB3F_Pos) /*!< 0x00000008 */ #define CSI_FCR0_CLB3F CSI_FCR0_CLB3F_Msk /*!< Clear Line byte counter 3 flag */ #define CSI_FCR0_CTIM0F_Pos (4U) #define CSI_FCR0_CTIM0F_Msk (0x1UL << CSI_FCR0_CTIM0F_Pos) /*!< 0x00000010 */ #define CSI_FCR0_CTIM0F CSI_FCR0_CTIM0F_Msk /*!< Clear Timer 0 flag */ #define CSI_FCR0_CTIM1F_Pos (5U) #define CSI_FCR0_CTIM1F_Msk (0x1UL << CSI_FCR0_CTIM1F_Pos) /*!< 0x00000020 */ #define CSI_FCR0_CTIM1F CSI_FCR0_CTIM1F_Msk /*!< Clear Timer 1 flag */ #define CSI_FCR0_CTIM2F_Pos (6U) #define CSI_FCR0_CTIM2F_Msk (0x1UL << CSI_FCR0_CTIM2F_Pos) /*!< 0x00000040 */ #define CSI_FCR0_CTIM2F CSI_FCR0_CTIM2F_Msk /*!< Clear Timer 2 flag */ #define CSI_FCR0_CTIM3F_Pos (7U) #define CSI_FCR0_CTIM3F_Msk (0x1UL << CSI_FCR0_CTIM3F_Pos) /*!< 0x00000080 */ #define CSI_FCR0_CTIM3F CSI_FCR0_CTIM3F_Msk /*!< Clear Timer 3 flag */ #define CSI_FCR0_CSOF0F_Pos (8U) #define CSI_FCR0_CSOF0F_Msk (0x1UL << CSI_FCR0_CSOF0F_Pos) /*!< 0x00000100 */ #define CSI_FCR0_CSOF0F CSI_FCR0_CSOF0F_Msk /*!< Clear Start of frame flag for virtual channel 0 */ #define CSI_FCR0_CSOF1F_Pos (9U) #define CSI_FCR0_CSOF1F_Msk (0x1UL << CSI_FCR0_CSOF1F_Pos) /*!< 0x00000200 */ #define CSI_FCR0_CSOF1F CSI_FCR0_CSOF1F_Msk /*!< Clear Start of frame flag for virtual channel 1 */ #define CSI_FCR0_CSOF2F_Pos (10U) #define CSI_FCR0_CSOF2F_Msk (0x1UL << CSI_FCR0_CSOF2F_Pos) /*!< 0x00000400 */ #define CSI_FCR0_CSOF2F CSI_FCR0_CSOF2F_Msk /*!< Clear Start of frame flag for virtual channel 2 */ #define CSI_FCR0_CSOF3F_Pos (11U) #define CSI_FCR0_CSOF3F_Msk (0x1UL << CSI_FCR0_CSOF3F_Pos) /*!< 0x00000800 */ #define CSI_FCR0_CSOF3F CSI_FCR0_CSOF3F_Msk /*!< Clear Start of frame flag for virtual channel 3 */ #define CSI_FCR0_CEOF0F_Pos (12U) #define CSI_FCR0_CEOF0F_Msk (0x1UL << CSI_FCR0_CEOF0F_Pos) /*!< 0x00001000 */ #define CSI_FCR0_CEOF0F CSI_FCR0_CEOF0F_Msk /*!< Clear End of frame flag for virtual channel 0 */ #define CSI_FCR0_CEOF1F_Pos (13U) #define CSI_FCR0_CEOF1F_Msk (0x1UL << CSI_FCR0_CEOF1F_Pos) /*!< 0x00002000 */ #define CSI_FCR0_CEOF1F CSI_FCR0_CEOF1F_Msk /*!< Clear End of frame flag for virtual channel 1 */ #define CSI_FCR0_CEOF2F_Pos (14U) #define CSI_FCR0_CEOF2F_Msk (0x1UL << CSI_FCR0_CEOF2F_Pos) /*!< 0x00004000 */ #define CSI_FCR0_CEOF2F CSI_FCR0_CEOF2F_Msk /*!< Clear End of frame flag for virtual channel 2 */ #define CSI_FCR0_CEOF3F_Pos (15U) #define CSI_FCR0_CEOF3F_Msk (0x1UL << CSI_FCR0_CEOF3F_Pos) /*!< 0x00008000 */ #define CSI_FCR0_CEOF3F CSI_FCR0_CEOF3F_Msk /*!< Clear End of frame flag for virtual channel 3 */ #define CSI_FCR0_CSPKTF_Pos (16U) #define CSI_FCR0_CSPKTF_Msk (0x1UL << CSI_FCR0_CSPKTF_Pos) /*!< 0x00010000 */ #define CSI_FCR0_CSPKTF CSI_FCR0_CSPKTF_Msk /*!< Clear Short packet flag */ #define CSI_FCR0_CCCFIFOFF_Pos (21U) #define CSI_FCR0_CCCFIFOFF_Msk (0x1UL << CSI_FCR0_CCCFIFOFF_Pos) /*!< 0x00200000 */ #define CSI_FCR0_CCCFIFOFF CSI_FCR0_CCCFIFOFF_Msk /*!< Clear Clock changer FIFO full flag */ #define CSI_FCR0_CCRCERRF_Pos (24U) #define CSI_FCR0_CCRCERRF_Msk (0x1UL << CSI_FCR0_CCRCERRF_Pos) /*!< 0x01000000 */ #define CSI_FCR0_CCRCERRF CSI_FCR0_CCRCERRF_Msk /*!< Clear CRC error flag */ #define CSI_FCR0_CECCERRF_Pos (25U) #define CSI_FCR0_CECCERRF_Msk (0x1UL << CSI_FCR0_CECCERRF_Pos) /*!< 0x02000000 */ #define CSI_FCR0_CECCERRF CSI_FCR0_CECCERRF_Msk /*!< Clear ECC error flag */ #define CSI_FCR0_CCECCERRF_Pos (26U) #define CSI_FCR0_CCECCERRF_Msk (0x1UL << CSI_FCR0_CCECCERRF_Pos) /*!< 0x04000000 */ #define CSI_FCR0_CCECCERRF CSI_FCR0_CCECCERRF_Msk /*!< Clear Corrected ECC error flag */ #define CSI_FCR0_CIDERRF_Pos (27U) #define CSI_FCR0_CIDERRF_Msk (0x1UL << CSI_FCR0_CIDERRF_Pos) /*!< 0x08000000 */ #define CSI_FCR0_CIDERRF CSI_FCR0_CIDERRF_Msk /*!< Clear Data type ID error flag */ #define CSI_FCR0_CSPKTERRF_Pos (28U) #define CSI_FCR0_CSPKTERRF_Msk (0x1UL << CSI_FCR0_CSPKTERRF_Pos) /*!< 0x10000000 */ #define CSI_FCR0_CSPKTERRF CSI_FCR0_CSPKTERRF_Msk /*!< Clear Short packet error flag */ #define CSI_FCR0_CWDERRF_Pos (29U) #define CSI_FCR0_CWDERRF_Msk (0x1UL << CSI_FCR0_CWDERRF_Pos) /*!< 0x20000000 */ #define CSI_FCR0_CWDERRF CSI_FCR0_CWDERRF_Msk /*!< Clear Watchdog error flag */ #define CSI_FCR0_CSYNCERRF_Pos (30U) #define CSI_FCR0_CSYNCERRF_Msk (0x1UL << CSI_FCR0_CSYNCERRF_Pos) /*!< 0x40000000 */ #define CSI_FCR0_CSYNCERRF CSI_FCR0_CSYNCERRF_Msk /*!< Clear Invalid synchronization error flag */ /******************* Bit definition for CSI_FCR1 register *******************/ #define CSI_FCR1_CESOTDL0F_Pos (0U) #define CSI_FCR1_CESOTDL0F_Msk (0x1UL << CSI_FCR1_CESOTDL0F_Pos) /*!< 0x00000001 */ #define CSI_FCR1_CESOTDL0F CSI_FCR1_CESOTDL0F_Msk /*!< Clear Start of transmission error flag on lane 0 */ #define CSI_FCR1_CESOTSYNCDL0F_Pos (1U) #define CSI_FCR1_CESOTSYNCDL0F_Msk (0x1UL << CSI_FCR1_CESOTSYNCDL0F_Pos) /*!< 0x00000002 */ #define CSI_FCR1_CESOTSYNCDL0F CSI_FCR1_CESOTSYNCDL0F_Msk /*!< Clear Start of transmission synchronization error flag on lane 0 */ #define CSI_FCR1_CEESCDL0F_Pos (2U) #define CSI_FCR1_CEESCDL0F_Msk (0x1UL << CSI_FCR1_CEESCDL0F_Pos) /*!< 0x00000004 */ #define CSI_FCR1_CEESCDL0F CSI_FCR1_CEESCDL0F_Msk /*!< Clear D-PHY_RX lane 0 escape entry error flag */ #define CSI_FCR1_CESYNCESCDL0F_Pos (3U) #define CSI_FCR1_CESYNCESCDL0F_Msk (0x1UL << CSI_FCR1_CESYNCESCDL0F_Pos) /*!< 0x00000008 */ #define CSI_FCR1_CESYNCESCDL0F CSI_FCR1_CESYNCESCDL0F_Msk /*!< Clear D-PHY_RX lane 0 low power data transmission synchronization error flag */ #define CSI_FCR1_CECTRLDL0F_Pos (4U) #define CSI_FCR1_CECTRLDL0F_Msk (0x1UL << CSI_FCR1_CECTRLDL0F_Pos) /*!< 0x00000010 */ #define CSI_FCR1_CECTRLDL0F CSI_FCR1_CECTRLDL0F_Msk /*!< Clear D-PHY_RX lane 0 control error flag */ #define CSI_FCR1_CESOTDL1F_Pos (8U) #define CSI_FCR1_CESOTDL1F_Msk (0x1UL << CSI_FCR1_CESOTDL1F_Pos) /*!< 0x00000100 */ #define CSI_FCR1_CESOTDL1F CSI_FCR1_CESOTDL1F_Msk /*!< Clear Start of transmission error flag on lane 1 */ #define CSI_FCR1_CESOTSYNCDL1F_Pos (9U) #define CSI_FCR1_CESOTSYNCDL1F_Msk (0x1UL << CSI_FCR1_CESOTSYNCDL1F_Pos) /*!< 0x00000200 */ #define CSI_FCR1_CESOTSYNCDL1F CSI_FCR1_CESOTSYNCDL1F_Msk /*!< Clear Start of transmission synchronization error flag on lane 1 */ #define CSI_FCR1_CEESCDL1F_Pos (10U) #define CSI_FCR1_CEESCDL1F_Msk (0x1UL << CSI_FCR1_CEESCDL1F_Pos) /*!< 0x00000400 */ #define CSI_FCR1_CEESCDL1F CSI_FCR1_CEESCDL1F_Msk /*!< Clear D-PHY_RX lane 1 escape entry error flag */ #define CSI_FCR1_CESYNCESCDL1F_Pos (11U) #define CSI_FCR1_CESYNCESCDL1F_Msk (0x1UL << CSI_FCR1_CESYNCESCDL1F_Pos) /*!< 0x00000800 */ #define CSI_FCR1_CESYNCESCDL1F CSI_FCR1_CESYNCESCDL1F_Msk /*!< Clear D-PHY_RX lane 1 low power data transmission synchronization error flag */ #define CSI_FCR1_CECTRLDL1F_Pos (12U) #define CSI_FCR1_CECTRLDL1F_Msk (0x1UL << CSI_FCR1_CECTRLDL1F_Pos) /*!< 0x00001000 */ #define CSI_FCR1_CECTRLDL1F CSI_FCR1_CECTRLDL1F_Msk /*!< Clear D-PHY_RX lane 1 control error flag */ /****************** Bit definition for CSI_SPDFR register *******************/ #define CSI_SPDFR_DATAFIELD_Pos (0U) #define CSI_SPDFR_DATAFIELD_Msk (0xFFFFUL << CSI_SPDFR_DATAFIELD_Pos) /*!< 0x0000FFFF */ #define CSI_SPDFR_DATAFIELD CSI_SPDFR_DATAFIELD_Msk /*!< Data field */ #define CSI_SPDFR_DATATYPE_Pos (16U) #define CSI_SPDFR_DATATYPE_Msk (0x3FUL << CSI_SPDFR_DATATYPE_Pos) /*!< 0x003F0000 */ #define CSI_SPDFR_DATATYPE CSI_SPDFR_DATATYPE_Msk /*!< Data type class */ #define CSI_SPDFR_VCHANNEL_Pos (22U) #define CSI_SPDFR_VCHANNEL_Msk (0x3UL << CSI_SPDFR_VCHANNEL_Pos) /*!< 0x00C00000 */ #define CSI_SPDFR_VCHANNEL CSI_SPDFR_VCHANNEL_Msk /*!< Virtual channel */ /******************* Bit definition for CSI_ERR1 register *******************/ #define CSI_ERR1_CRCDTERR_Pos (0U) #define CSI_ERR1_CRCDTERR_Msk (0x3FUL << CSI_ERR1_CRCDTERR_Pos) /*!< 0x0000003F */ #define CSI_ERR1_CRCDTERR CSI_ERR1_CRCDTERR_Msk /*!< Data type having a CRC error */ #define CSI_ERR1_CRCVCERR_Pos (6U) #define CSI_ERR1_CRCVCERR_Msk (0x3UL << CSI_ERR1_CRCVCERR_Pos) /*!< 0x000000C0 */ #define CSI_ERR1_CRCVCERR CSI_ERR1_CRCVCERR_Msk /*!< Virtual channel having a CRC error */ #define CSI_ERR1_CECCDTERR_Pos (8U) #define CSI_ERR1_CECCDTERR_Msk (0x3FUL << CSI_ERR1_CECCDTERR_Pos) /*!< 0x00003F00 */ #define CSI_ERR1_CECCDTERR CSI_ERR1_CECCDTERR_Msk /*!< Data type having a corrected ECC error */ #define CSI_ERR1_CECCVCERR_Pos (14U) #define CSI_ERR1_CECCVCERR_Msk (0x3UL << CSI_ERR1_CECCVCERR_Pos) /*!< 0x0000C000 */ #define CSI_ERR1_CECCVCERR CSI_ERR1_CECCVCERR_Msk /*!< Virtual channel having a corrected ECC error */ #define CSI_ERR1_IDDTERR_Pos (16U) #define CSI_ERR1_IDDTERR_Msk (0x3FUL << CSI_ERR1_IDDTERR_Pos) /*!< 0x003F0000 */ #define CSI_ERR1_IDDTERR CSI_ERR1_IDDTERR_Msk /*!< Data type in error */ #define CSI_ERR1_IDVCERR_Pos (22U) #define CSI_ERR1_IDVCERR_Msk (0x3UL << CSI_ERR1_IDVCERR_Pos) /*!< 0x00C00000 */ #define CSI_ERR1_IDVCERR CSI_ERR1_IDVCERR_Msk /*!< Virtual channel having ID error */ /******************* Bit definition for CSI_ERR2 register *******************/ #define CSI_ERR2_SPKTDTERR_Pos (0U) #define CSI_ERR2_SPKTDTERR_Msk (0x3FUL << CSI_ERR2_SPKTDTERR_Pos) /*!< 0x0000003F */ #define CSI_ERR2_SPKTDTERR CSI_ERR2_SPKTDTERR_Msk /*!< Data type having a short packet error */ #define CSI_ERR2_SPKTVCERR_Pos (6U) #define CSI_ERR2_SPKTVCERR_Msk (0x3UL << CSI_ERR2_SPKTVCERR_Pos) /*!< 0x000000C0 */ #define CSI_ERR2_SPKTVCERR CSI_ERR2_SPKTVCERR_Msk /*!< Virtual channel having a short packet error */ #define CSI_ERR2_WDVCERR_Pos (16U) #define CSI_ERR2_WDVCERR_Msk (0x3UL << CSI_ERR2_WDVCERR_Pos) /*!< 0x00030000 */ #define CSI_ERR2_WDVCERR CSI_ERR2_WDVCERR_Msk /*!< Virtual channel having a watchdog error */ #define CSI_ERR2_SYNCVCERR_Pos (18U) #define CSI_ERR2_SYNCVCERR_Msk (0x3UL << CSI_ERR2_SYNCVCERR_Pos) /*!< 0x000C0000 */ #define CSI_ERR2_SYNCVCERR CSI_ERR2_SYNCVCERR_Msk /*!< Virtual channel having synchronization error */ /******************* Bit definition for CSI_PRCR register *******************/ #define CSI_PRCR_PEN_Pos (1U) #define CSI_PRCR_PEN_Msk (0x1UL << CSI_PRCR_PEN_Pos) /*!< 0x00000002 */ #define CSI_PRCR_PEN CSI_PRCR_PEN_Msk /*!< When set to 0, this bit places the digital section of the D-PHY in the reset state */ /******************* Bit definition for CSI_PMCR register *******************/ #define CSI_PMCR_FRXMDL0_Pos (0U) #define CSI_PMCR_FRXMDL0_Msk (0x1UL << CSI_PMCR_FRXMDL0_Pos) /*!< 0x00000001 */ #define CSI_PMCR_FRXMDL0 CSI_PMCR_FRXMDL0_Msk /*!< Force to Rx Mode the Data Lane 0 */ #define CSI_PMCR_FRXMDL1_Pos (1U) #define CSI_PMCR_FRXMDL1_Msk (0x1UL << CSI_PMCR_FRXMDL1_Pos) /*!< 0x00000002 */ #define CSI_PMCR_FRXMDL1 CSI_PMCR_FRXMDL1_Msk /*!< Force to Rx Mode the Data Lane 1 */ #define CSI_PMCR_FTXSMDL0_Pos (2U) #define CSI_PMCR_FTXSMDL0_Msk (0x1UL << CSI_PMCR_FTXSMDL0_Pos) /*!< 0x00000004 */ #define CSI_PMCR_FTXSMDL0 CSI_PMCR_FTXSMDL0_Msk /*!< Force to Tx Stop Mode the Data Lane 0 */ #define CSI_PMCR_DTDL_Pos (4U) #define CSI_PMCR_DTDL_Msk (0x1UL << CSI_PMCR_DTDL_Pos) /*!< 0x00000010 */ #define CSI_PMCR_DTDL CSI_PMCR_DTDL_Msk /*!< Disable Turn-around Data Lane 0 */ #define CSI_PMCR_RTDL0_Pos (8U) #define CSI_PMCR_RTDL0_Msk (0x1UL << CSI_PMCR_RTDL0_Pos) /*!< 0x00000100 */ #define CSI_PMCR_RTDL0 CSI_PMCR_RTDL0_Msk /*!< Turn-around Request Data Lane 0 */ #define CSI_PMCR_TUESDL0_Pos (12U) #define CSI_PMCR_TUESDL0_Msk (0x1UL << CSI_PMCR_TUESDL0_Pos) /*!< 0x00001000 */ #define CSI_PMCR_TUESDL0 CSI_PMCR_TUESDL0_Msk /*!< Tx ULP Escape-mode Data Lane 0 */ #define CSI_PMCR_TUEXDL0_Pos (16U) #define CSI_PMCR_TUEXDL0_Msk (0x1UL << CSI_PMCR_TUEXDL0_Pos) /*!< 0x00010000 */ #define CSI_PMCR_TUEXDL0 CSI_PMCR_TUEXDL0_Msk /*!< Tx ULP Exit-sequence Data Lane 0 */ /******************* Bit definition for CSI_PFCR register *******************/ #define CSI_PFCR_CCFR_Pos (0U) #define CSI_PFCR_CCFR_Msk (0x3FUL << CSI_PFCR_CCFR_Pos) /*!< 0x0000003F */ #define CSI_PFCR_CCFR CSI_PFCR_CCFR_Msk /*!< Configuration Clock Frequency Range selection */ #define CSI_PFCR_HSFR_Pos (8U) #define CSI_PFCR_HSFR_Msk (0x7FUL << CSI_PFCR_HSFR_Pos) /*!< 0x00007F00 */ #define CSI_PFCR_HSFR CSI_PFCR_HSFR_Msk /*!< PHY-high-speed Frequency Range selection */ #define CSI_PFCR_DLD_Pos (16U) #define CSI_PFCR_DLD_Msk (0x1UL << CSI_PFCR_DLD_Pos) /*!< 0x00010000 */ #define CSI_PFCR_DLD CSI_PFCR_DLD_Msk /*!< Data Lane Direction of lane0 */ /****************** Bit definition for CSI_PTCR0 register *******************/ #define CSI_PTCR0_TCKEN_Pos (0U) #define CSI_PTCR0_TCKEN_Msk (0x1UL << CSI_PTCR0_TCKEN_Pos) /*!< 0x00000001 */ #define CSI_PTCR0_TCKEN CSI_PTCR0_TCKEN_Msk /*!< Test-interface Clock Enable for the TDI bus into the PHY */ #define CSI_PTCR0_TRSEN_Pos (1U) #define CSI_PTCR0_TRSEN_Msk (0x1UL << CSI_PTCR0_TRSEN_Pos) /*!< 0x00000002 */ #define CSI_PTCR0_TRSEN CSI_PTCR0_TRSEN_Msk /*!< Test-interface Reset Enable for the TDI bus into the PHY */ /****************** Bit definition for CSI_PTCR1 register *******************/ #define CSI_PTCR1_TDI_Pos (0U) #define CSI_PTCR1_TDI_Msk (0xFFUL << CSI_PTCR1_TDI_Pos) /*!< 0x000000FF */ #define CSI_PTCR1_TDI CSI_PTCR1_TDI_Msk /*!< Test-interface Data In */ #define CSI_PTCR1_TWM_Pos (16U) #define CSI_PTCR1_TWM_Msk (0x1UL << CSI_PTCR1_TWM_Pos) /*!< 0x00010000 */ #define CSI_PTCR1_TWM CSI_PTCR1_TWM_Msk /*!< Test-interface Write Mode selector */ /******************* Bit definition for CSI_PTSR register *******************/ #define CSI_PTSR_TDO_Pos (0U) #define CSI_PTSR_TDO_Msk (0xFFUL << CSI_PTSR_TDO_Pos) /*!< 0x000000FF */ #define CSI_PTSR_TDO CSI_PTSR_TDO_Msk /*!< CSI PHY test interface data output bus for read-back and internal probing functionalities */ /*********************************************************************************/ /* */ /* DBGMCU */ /* */ /*********************************************************************************/ /******************** Bit definition for DBGMCU_IDCODE register ****************/ #define DBGMCU_IDCODE_DEV_ID_Pos (0U) #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device ID */ #define DBGMCU_IDCODE_REV_ID_Pos (16U) #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< Revision ID */ /******************** Bit definition for DBGMCU_CR register ********************/ #define DBGMCU_CR_DBG_SLEEP_Pos (0U) #define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Allow debug in Sleep mode */ #define DBGMCU_CR_DBG_STOP_Pos (1U) #define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Allow debug in Stop mode */ #define DBGMCU_CR_DBG_STANDBY_Pos (2U) #define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Allow debug in Standby mode */ #define DBGMCU_CR_DBGCLKEN_Pos (20U) #define DBGMCU_CR_DBGCLKEN_Msk (0x1UL << DBGMCU_CR_DBGCLKEN_Pos) /*!< 0x00100000 */ #define DBGMCU_CR_DBGCLKEN DBGMCU_CR_DBGCLKEN_Msk /*!< Debug clock enable through software */ #define DBGMCU_CR_TRACECLKEN_Pos (21U) #define DBGMCU_CR_TRACECLKEN_Msk (0x1UL << DBGMCU_CR_TRACECLKEN_Pos) /*!< 0x00200000 */ #define DBGMCU_CR_TRACECLKEN DBGMCU_CR_TRACECLKEN_Msk /*!< TPIU export clock enable through software */ #define DBGMCU_CR_DBTRGOEN_Pos (28U) #define DBGMCU_CR_DBTRGOEN_Msk (0x1UL << DBGMCU_CR_DBTRGOEN_Pos) /*!< 0x10000000 */ #define DBGMCU_CR_DBTRGOEN DBGMCU_CR_DBTRGOEN_Msk /*!< DBTRGIO connection control */ #define DBGMCU_CR_HLT_TSGEN_EN_Pos (31U) #define DBGMCU_CR_HLT_TSGEN_EN_Msk (0x1UL << DBGMCU_CR_HLT_TSGEN_EN_Pos) /*!< 0x80000000 */ #define DBGMCU_CR_HLT_TSGEN_EN DBGMCU_CR_HLT_TSGEN_EN_Msk /*!< TSGEN halt enable */ /******************** Bit definition for DBGMCU_APB1LFZ1 register ***************/ #define DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Pos (0U) #define DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ #define DBGMCU_APB1LFZ1_DBG_TIM2_STOP DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Msk /*!< TIM2 stop in debug */ #define DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Pos (1U) #define DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */ #define DBGMCU_APB1LFZ1_DBG_TIM3_STOP DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Msk /*!< TIM3 stop in debug */ #define DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Pos (2U) #define DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */ #define DBGMCU_APB1LFZ1_DBG_TIM4_STOP DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Msk /*!< TIM4 stop in debug */ #define DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Pos (3U) #define DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */ #define DBGMCU_APB1LFZ1_DBG_TIM5_STOP DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Msk /*!< TIM5 stop in debug */ #define DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Pos (4U) #define DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */ #define DBGMCU_APB1LFZ1_DBG_TIM6_STOP DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Msk /*!< TIM6 stop in debug */ #define DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Pos (5U) #define DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */ #define DBGMCU_APB1LFZ1_DBG_TIM7_STOP DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Msk /*!< TIM7 stop in debug */ #define DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Pos (6U) #define DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */ #define DBGMCU_APB1LFZ1_DBG_TIM12_STOP DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Msk /*!< TIM12 stop in debug */ #define DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Pos (7U) #define DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */ #define DBGMCU_APB1LFZ1_DBG_TIM13_STOP DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Msk /*!< TIM13 stop in debug */ #define DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Pos (8U) #define DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */ #define DBGMCU_APB1LFZ1_DBG_TIM14_STOP DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Msk /*!< TIM14 stop in debug */ #define DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Pos (9U) #define DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Pos) /*!< 0x00000200 */ #define DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Msk /*!< LPTIM1 stop in debug */ #define DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Pos (11U) #define DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Pos) /*!< 0x00000800 */ #define DBGMCU_APB1LFZ1_DBG_WWDG1_STOP DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Msk /*!< WWDG1 stop in debug */ #define DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Pos (12U) #define DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Pos) /*!< 0x00001000 */ #define DBGMCU_APB1LFZ1_DBG_TIM10_STOP DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Msk /*!< TIM10 stop in debug */ #define DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Pos (13U) #define DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Pos) /*!< 0x00002000 */ #define DBGMCU_APB1LFZ1_DBG_TIM11_STOP DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Msk /*!< TIM11 stop in debug */ #define DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Pos (21U) #define DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */ #define DBGMCU_APB1LFZ1_DBG_I2C1_STOP DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout stop in debug */ #define DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Pos (22U) #define DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */ #define DBGMCU_APB1LFZ1_DBG_I2C2_STOP DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS timeout stop in debug */ #define DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Pos (23U) #define DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */ #define DBGMCU_APB1LFZ1_DBG_I2C3_STOP DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Msk /*!< I2C3 SMBUS timeout stop in debug */ #define DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Pos (24U) #define DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Pos) /*!< 0x01000000 */ #define DBGMCU_APB1LFZ1_DBG_I3C1_STOP DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Msk /*!< I3C1 SMBUS timeout stop in debug */ #define DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Pos (25U) #define DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Pos) /*!< 0x00008000 */ #define DBGMCU_APB1LFZ1_DBG_I3C2_STOP DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Msk /*!< I3C2 SMBUS timeout stop in debug */ /******************** Bit definition for DBGMCU_APB1HFZ1 register ***************/ #define DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Pos (8U) #define DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Pos) /*!< 0x00000100 */ #define DBGMCU_APB1HFZ1_DBG_FDCAN_STOP DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Msk /*!< FDCAN stop in debug */ /******************** Bit definition for DBGMCU_APB2FZ1 register ***************/ #define DBGMCU_APB2FZ1_DBG_TIM1_STOP_Pos (0U) #define DBGMCU_APB2FZ1_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */ #define DBGMCU_APB2FZ1_DBG_TIM1_STOP DBGMCU_APB2FZ1_DBG_TIM1_STOP_Msk /*!< TIM1 stop in debug */ #define DBGMCU_APB2FZ1_DBG_TIM8_STOP_Pos (1U) #define DBGMCU_APB2FZ1_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */ #define DBGMCU_APB2FZ1_DBG_TIM8_STOP DBGMCU_APB2FZ1_DBG_TIM8_STOP_Msk /*!< TIM8 stop in debug */ #define DBGMCU_APB2FZ1_DBG_TIM18_STOP_Pos (15U) #define DBGMCU_APB2FZ1_DBG_TIM18_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM18_STOP_Pos) /*!< 0x00008000 */ #define DBGMCU_APB2FZ1_DBG_TIM18_STOP DBGMCU_APB2FZ1_DBG_TIM18_STOP_Msk /*!< TIM18 stop in debug */ #define DBGMCU_APB2FZ1_DBG_TIM15_STOP_Pos (16U) #define DBGMCU_APB2FZ1_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */ #define DBGMCU_APB2FZ1_DBG_TIM15_STOP DBGMCU_APB2FZ1_DBG_TIM15_STOP_Msk /*!< TIM15 stop in debug */ #define DBGMCU_APB2FZ1_DBG_TIM16_STOP_Pos (17U) #define DBGMCU_APB2FZ1_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */ #define DBGMCU_APB2FZ1_DBG_TIM16_STOP DBGMCU_APB2FZ1_DBG_TIM16_STOP_Msk /*!< TIM16 stop in debug */ #define DBGMCU_APB2FZ1_DBG_TIM17_STOP_Pos (18U) #define DBGMCU_APB2FZ1_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */ #define DBGMCU_APB2FZ1_DBG_TIM17_STOP DBGMCU_APB2FZ1_DBG_TIM17_STOP_Msk /*!< TIM17 stop in debug */ #define DBGMCU_APB2FZ1_DBG_TIM9_STOP_Pos (19U) #define DBGMCU_APB2FZ1_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM9_STOP_Pos) /*!< 0x00080000 */ #define DBGMCU_APB2FZ1_DBG_TIM9_STOP DBGMCU_APB2FZ1_DBG_TIM9_STOP_Msk /*!< TIM9 stop in debug */ /******************** Bit definition for DBGMCU_APB4FZ1 register ***************/ #define DBGMCU_APB4FZ1_DBG_I2C4_STOP_Pos (8U) #define DBGMCU_APB4FZ1_DBG_I2C4_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_STOP_Pos) /*!< 0x00000100 */ #define DBGMCU_APB4FZ1_DBG_I2C4_STOP DBGMCU_APB4FZ1_DBG_I2C4_STOP_Msk /*!< I2C4 stop in debug */ #define DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Pos (9U) #define DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Pos) /*!< 0x00000200 */ #define DBGMCU_APB4FZ1_DBG_LPTIM2_STOP DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Msk /*!< LPTIM2 stop in debug */ #define DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Pos (10U) #define DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Pos) /*!< 0x00000400 */ #define DBGMCU_APB4FZ1_DBG_LPTIM3_STOP DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Msk /*!< LPTIM3 stop in debug */ #define DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Pos (11U) #define DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Pos) /*!< 0x00000800 */ #define DBGMCU_APB4FZ1_DBG_LPTIM4_STOP DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Msk /*!< LPTIM4 stop in debug */ #define DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Pos (12U) #define DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Pos) /*!< 0x00001000 */ #define DBGMCU_APB4FZ1_DBG_LPTIM5_STOP DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Msk /*!< LPTIM5 stop in debug */ #define DBGMCU_APB4FZ1_DBG_RTC_STOP_Pos (16U) #define DBGMCU_APB4FZ1_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_STOP_Pos) /*!< 0x00010000 */ #define DBGMCU_APB4FZ1_DBG_RTC_STOP DBGMCU_APB4FZ1_DBG_RTC_STOP_Msk /*!< RTC stop in debug */ #define DBGMCU_APB4FZ1_DBG_IWDG_STOP_Pos (18U) #define DBGMCU_APB4FZ1_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG_STOP_Pos) /*!< 0x00040000 */ #define DBGMCU_APB4FZ1_DBG_IWDG_STOP DBGMCU_APB4FZ1_DBG_IWDG_STOP_Msk /*!< IWDG stop in debug */ /******************** Bit definition for DBGMCU_APB5FZ1 register ***************/ #define DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Pos (4U) #define DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Msk (0x1UL << DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Pos) /*!< 0x00000010 */ #define DBGMCU_APB5FZ1_DBG_GFXTIM_STOP DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Msk /*!< GFXTIM stop in debug */ /******************** Bit definition for DBGMCU_AHB1FZ1 register ***************/ #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Pos (0U) #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Pos) /*!< 0x00000001 */ #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Msk /*!< GPDMA1_CH0 suspend in debug */ #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Pos (1U) #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Pos) /*!< 0x00000002 */ #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Msk /*!< GPDMA1_CH1 suspend in debug */ #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Pos (2U) #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Pos) /*!< 0x00000004 */ #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Msk /*!< GPDMA1_CH2 suspend in debug */ #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Pos (3U) #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Pos) /*!< 0x00000008 */ #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Msk /*!< GPDMA1_CH3 suspend in debug */ #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Pos (4U) #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Pos) /*!< 0x00000010 */ #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Msk /*!< GPDMA1_CH4 suspend in debug */ #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Pos (5U) #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Pos) /*!< 0x00000020 */ #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Msk /*!< GPDMA1_CH5 suspend in debug */ #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Pos (6U) #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Pos) /*!< 0x00000040 */ #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Msk /*!< GPDMA1_CH6 suspend in debug */ #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Pos (7U) #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Pos) /*!< 0x00000080 */ #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Msk /*!< GPDMA1_CH7 suspend in debug */ #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Pos (8U) #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Pos) /*!< 0x00000100 */ #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Msk /*!< GPDMA1_CH8 suspend in debug */ #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Pos (9U) #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Pos) /*!< 0x00000200 */ #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Msk /*!< GPDMA1_CH9 suspend in debug */ #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Pos (10U) #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Pos) /*!< 0x00000400 */ #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Msk /*!< GPDMA1_CH10 suspend in debug */ #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Pos (11U) #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Pos) /*!< 0x00000800 */ #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Msk /*!< GPDMA1_CH11 suspend in debug */ #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Pos (12U) #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Pos) /*!< 0x00001000 */ #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Msk /*!< GPDMA1_CH12 suspend in debug */ #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Pos (13U) #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Pos) /*!< 0x00002000 */ #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Msk /*!< GPDMA1_CH13 suspend in debug */ #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Pos (14U) #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Pos) /*!< 0x00004000 */ #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Msk /*!< GPDMA1_CH14 suspend in debug */ #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Pos (15U) #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Pos) /*!< 0x00008000 */ #define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Msk /*!< GPDMA1_CH15 suspend in debug */ /******************** Bit definition for DBGMCU_AHB5FZ1 register ***************/ #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Pos (0U) #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Pos) /*!< 0x00000001 */ #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Msk /*!< HPDMA1_CH0 suspend in debug */ #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Pos (1U) #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Pos) /*!< 0x00000002 */ #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Msk /*!< HPDMA1_CH1 suspend in debug */ #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Pos (2U) #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Pos) /*!< 0x00000004 */ #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Msk /*!< HPDMA1_CH2 suspend in debug */ #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Pos (3U) #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Pos) /*!< 0x00000008 */ #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Msk /*!< HPDMA1_CH3 suspend in debug */ #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Pos (4U) #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Pos) /*!< 0x00000010 */ #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Msk /*!< HPDMA1_CH4 suspend in debug */ #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Pos (5U) #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Pos) /*!< 0x00000020 */ #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Msk /*!< HPDMA1_CH5 suspend in debug */ #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Pos (6U) #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Pos) /*!< 0x00000040 */ #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Msk /*!< HPDMA1_CH6 suspend in debug */ #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Pos (7U) #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Pos) /*!< 0x00000080 */ #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Msk /*!< HPDMA1_CH7 suspend in debug */ #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Pos (8U) #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Pos) /*!< 0x00000100 */ #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Msk /*!< HPDMA1_CH8 suspend in debug */ #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Pos (9U) #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Pos) /*!< 0x00000200 */ #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Msk /*!< HPDMA1_CH9 suspend in debug */ #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Pos (10U) #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Pos) /*!< 0x00000400 */ #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Msk /*!< HPDMA1_CH10 suspend in debug */ #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Pos (11U) #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Pos) /*!< 0x00000800 */ #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Msk /*!< HPDMA1_CH11 suspend in debug */ #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Pos (12U) #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Pos) /*!< 0x00001000 */ #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Msk /*!< HPDMA1_CH12 suspend in debug */ #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Pos (13U) #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Pos) /*!< 0x00002000 */ #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Msk /*!< HPDMA1_CH13 suspend in debug */ #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Pos (14U) #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Pos) /*!< 0x00004000 */ #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Msk /*!< HPDMA1_CH14 suspend in debug */ #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Pos (15U) #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Pos) /*!< 0x00008000 */ #define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Msk /*!< HPDMA1_CH15 suspend in debug */ #define DBGMCU_AHB5FZ1_NPU_DBG_FREEZE_Pos (16U) #define DBGMCU_AHB5FZ1_NPU_DBG_FREEZE_Msk (0x1UL << DBGMCU_AHB5FZ1_NPU_DBG_FREEZE_Pos) /*!< 0x00010000 */ #define DBGMCU_AHB5FZ1_NPU_DBG_FREEZE DBGMCU_AHB5FZ1_NPU_DBG_FREEZE_Msk /*!< NPU stop in debug mode */ /******************** Bit definition for DBGMCU_SR register ***************/ #define DBGMCU_SR_AP0_PRESENT_Pos (0U) #define DBGMCU_SR_AP0_PRESENT_Msk (0x1UL << DBGMCU_SR_AP0_PRESENT_Pos) /*!< 0x00000001 */ #define DBGMCU_SR_AP0_PRESENT DBGMCU_SR_AP0_PRESENT_Msk /*!< Access point 0 presence */ #define DBGMCU_SR_AP1_PRESENT_Pos (1U) #define DBGMCU_SR_AP1_PRESENT_Msk (0x1UL << DBGMCU_SR_AP1_PRESENT_Pos) /*!< 0x00000002 */ #define DBGMCU_SR_AP1_PRESENT DBGMCU_SR_AP1_PRESENT_Msk /*!< Access point 1 presence */ #define DBGMCU_SR_AP0_ENABLE_Pos (16U) #define DBGMCU_SR_AP0_ENABLE_Msk (0x1UL << DBGMCU_SR_AP0_ENABLE_Pos) /*!< 0x00010000 */ #define DBGMCU_SR_AP0_ENABLE DBGMCU_SR_AP0_ENABLE_Msk /*!< Access point 0 enable */ #define DBGMCU_SR_AP1_ENABLE_Pos (17U) #define DBGMCU_SR_AP1_ENABLE_Msk (0x1UL << DBGMCU_SR_AP1_ENABLE_Pos) /*!< 0x00020000 */ #define DBGMCU_SR_AP1_ENABLE DBGMCU_SR_AP1_ENABLE_Msk /*!< Access point 1 enable */ /****************** Bit definition for DBGMCU_DBG_AUTH_HOST register **********************/ #define DBGMCU_DBG_AUTH_HOST_MESSAGE_Pos (0U) #define DBGMCU_DBG_AUTH_HOST_MESSAGE_Msk (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_HOST_MESSAGE_Pos) /*!< 0xFFFFFFFF */ #define DBGMCU_DBG_AUTH_HOST_MESSAGE DBGMCU_DBG_AUTH_HOST_MESSAGE_Msk /*!< Message[31:0] */ /****************** Bit definition for DBGMCU_DBG_AUTH_DEV register ***********/ #define DBGMCU_DBG_AUTH_DEV_MESSAGE_Pos (0U) #define DBGMCU_DBG_AUTH_DEV_MESSAGE_Msk (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_DEV_MESSAGE_Pos) /*!< 0xFFFFFFFF */ #define DBGMCU_DBG_AUTH_DEV_MESSAGE DBGMCU_DBG_AUTH_DEV_MESSAGE_Msk /*!< Message[31:0] */ /******************** Bit definition for DBGMCU_DBG_AUTH_ACK register ***************/ #define DBGMCU_DBG_AUTH_ACK_HOST_ACK_Pos (0U) #define DBGMCU_DBG_AUTH_ACK_HOST_ACK_Msk (0x1UL << DBGMCU_DBG_AUTH_ACK_HOST_ACK_Pos) /*!< 0x00000001 */ #define DBGMCU_DBG_AUTH_ACK_HOST_ACK DBGMCU_DBG_AUTH_ACK_HOST_ACK_Msk /*!< Access status to DBG_AUTH_HOST register */ #define DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Pos (1U) #define DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Msk (0x1UL << DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Pos) /*!< 0x00000002 */ #define DBGMCU_DBG_AUTH_ACK_DEVICE_ACK DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Msk /*!< Access status to DBG_AUTH_DEV register */ /******************************************************************************/ /* */ /* DCMI */ /* */ /******************************************************************************/ /******************** Bits definition for DCMI_CR register ******************/ #define DCMI_CR_CAPTURE_Pos (0U) #define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */ #define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk #define DCMI_CR_CM_Pos (1U) #define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos) /*!< 0x00000002 */ #define DCMI_CR_CM DCMI_CR_CM_Msk #define DCMI_CR_CROP_Pos (2U) #define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos) /*!< 0x00000004 */ #define DCMI_CR_CROP DCMI_CR_CROP_Msk #define DCMI_CR_JPEG_Pos (3U) #define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */ #define DCMI_CR_JPEG DCMI_CR_JPEG_Msk #define DCMI_CR_ESS_Pos (4U) #define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos) /*!< 0x00000010 */ #define DCMI_CR_ESS DCMI_CR_ESS_Msk #define DCMI_CR_PCKPOL_Pos (5U) #define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */ #define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk #define DCMI_CR_HSPOL_Pos (6U) #define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */ #define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk #define DCMI_CR_VSPOL_Pos (7U) #define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */ #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk #define DCMI_CR_FCRC_Pos (8U) #define DCMI_CR_FCRC_Msk (0x3UL << DCMI_CR_FCRC_Pos) /*!< 0x00000300 */ #define DCMI_CR_FCRC DCMI_CR_FCRC_Msk /*!< DCMI Frame capture rate control FCRC[1:0] */ #define DCMI_CR_FCRC_0 (0x1UL << DCMI_CR_FCRC_Pos) /*!< 0x00000100 */ #define DCMI_CR_FCRC_1 (0x2UL << DCMI_CR_FCRC_Pos) /*!< 0x00000200 */ #define DCMI_CR_EDM_Pos (10U) #define DCMI_CR_EDM_Msk (0x3UL << DCMI_CR_EDM_Pos) /*!< 0x00000C00 */ #define DCMI_CR_EDM DCMI_CR_EDM_Msk /*!< DCMI Extended data mode EDM[1:0] */ #define DCMI_CR_EDM_0 (0x1UL << DCMI_CR_EDM_Pos) /*!< 0x00000400 */ #define DCMI_CR_EDM_1 (0x2UL << DCMI_CR_EDM_Pos) /*!< 0x00000800 */ #define DCMI_CR_ENABLE_Pos (14U) #define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */ #define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk #define DCMI_CR_BSM_Pos (16U) #define DCMI_CR_BSM_Msk (0x3UL << DCMI_CR_BSM_Pos) /*!< 0x00030000 */ #define DCMI_CR_BSM DCMI_CR_BSM_Msk #define DCMI_CR_BSM_0 (0x1UL << DCMI_CR_BSM_Pos) /*!< 0x00010000 */ #define DCMI_CR_BSM_1 (0x2UL << DCMI_CR_BSM_Pos) /*!< 0x00020000 */ #define DCMI_CR_OEBS_Pos (18U) #define DCMI_CR_OEBS_Msk (0x1UL << DCMI_CR_OEBS_Pos) /*!< 0x00040000 */ #define DCMI_CR_OEBS DCMI_CR_OEBS_Msk #define DCMI_CR_LSM_Pos (19U) #define DCMI_CR_LSM_Msk (0x1UL << DCMI_CR_LSM_Pos) /*!< 0x00080000 */ #define DCMI_CR_LSM DCMI_CR_LSM_Msk #define DCMI_CR_OELS_Pos (20U) #define DCMI_CR_OELS_Msk (0x1UL << DCMI_CR_OELS_Pos) /*!< 0x00100000 */ #define DCMI_CR_OELS DCMI_CR_OELS_Msk #define DCMI_CR_PSDM_Pos (31U) #define DCMI_CR_PSDM_Msk (0x0UL << DCMI_CR_PSDM_Pos) /*!< 0x00000000 */ #define DCMI_CR_PSDM DCMI_CR_PSDM_Msk /*PSDM: Parallel Synchronous raw Data Mode (PSDM = 0)*/ /******************** Bits definition for DCMI_SR register ******************/ #define DCMI_SR_HSYNC_Pos (0U) #define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */ #define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk #define DCMI_SR_VSYNC_Pos (1U) #define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */ #define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk #define DCMI_SR_FNE_Pos (2U) #define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos) /*!< 0x00000004 */ #define DCMI_SR_FNE DCMI_SR_FNE_Msk /******************** Bits definition for DCMI_RIS register ****************/ #define DCMI_RIS_FRAME_RIS_Pos (0U) #define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */ #define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk #define DCMI_RIS_OVR_RIS_Pos (1U) #define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */ #define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk #define DCMI_RIS_ERR_RIS_Pos (2U) #define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */ #define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk #define DCMI_RIS_VSYNC_RIS_Pos (3U) #define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */ #define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk #define DCMI_RIS_LINE_RIS_Pos (4U) #define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */ #define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk /******************** Bits definition for DCMI_IER register *****************/ #define DCMI_IER_FRAME_IE_Pos (0U) #define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */ #define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk #define DCMI_IER_OVR_IE_Pos (1U) #define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */ #define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk #define DCMI_IER_ERR_IE_Pos (2U) #define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */ #define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk #define DCMI_IER_VSYNC_IE_Pos (3U) #define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */ #define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk #define DCMI_IER_LINE_IE_Pos (4U) #define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */ #define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk /******************** Bits definition for DCMI_MIS register *****************/ #define DCMI_MIS_FRAME_MIS_Pos (0U) #define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */ #define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk #define DCMI_MIS_OVR_MIS_Pos (1U) #define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */ #define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk #define DCMI_MIS_ERR_MIS_Pos (2U) #define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */ #define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk #define DCMI_MIS_VSYNC_MIS_Pos (3U) #define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */ #define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk #define DCMI_MIS_LINE_MIS_Pos (4U) #define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */ #define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk /******************** Bits definition for DCMI_ICR register *****************/ #define DCMI_ICR_FRAME_ISC_Pos (0U) #define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */ #define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk #define DCMI_ICR_OVR_ISC_Pos (1U) #define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */ #define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk #define DCMI_ICR_ERR_ISC_Pos (2U) #define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */ #define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk #define DCMI_ICR_VSYNC_ISC_Pos (3U) #define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */ #define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk #define DCMI_ICR_LINE_ISC_Pos (4U) #define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */ #define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk /******************** Bits definition for DCMI_ESCR register ******************/ #define DCMI_ESCR_FSC_Pos (0U) #define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */ #define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk #define DCMI_ESCR_LSC_Pos (8U) #define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */ #define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk #define DCMI_ESCR_LEC_Pos (16U) #define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */ #define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk #define DCMI_ESCR_FEC_Pos (24U) #define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */ #define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk /******************** Bits definition for DCMI_ESUR register ******************/ #define DCMI_ESUR_FSU_Pos (0U) #define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */ #define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk #define DCMI_ESUR_LSU_Pos (8U) #define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */ #define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk #define DCMI_ESUR_LEU_Pos (16U) #define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */ #define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk #define DCMI_ESUR_FEU_Pos (24U) #define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */ #define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk /******************** Bits definition for DCMI_CWSTRT register ******************/ #define DCMI_CWSTRT_HOFFCNT_Pos (0U) #define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */ #define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk #define DCMI_CWSTRT_VST_Pos (16U) #define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */ #define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk /******************** Bits definition for DCMI_CWSIZE register ******************/ #define DCMI_CWSIZE_CAPCNT_Pos (0U) #define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */ #define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk #define DCMI_CWSIZE_VLINE_Pos (16U) #define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */ #define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk /******************** Bits definition for DCMI_DR register ******************/ #define DCMI_DR_BYTE0_Pos (0U) #define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */ #define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk #define DCMI_DR_BYTE1_Pos (8U) #define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */ #define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk #define DCMI_DR_BYTE2_Pos (16U) #define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */ #define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk #define DCMI_DR_BYTE3_Pos (24U) #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */ #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk /******************************************************************************/ /* */ /* DCMIPP */ /* */ /******************************************************************************/ /***************** Bit definition for DCMIPP_IPGR1 register *****************/ #define DCMIPP_IPGR1_MEMORYPAGE_Pos (0U) #define DCMIPP_IPGR1_MEMORYPAGE_Msk (0x7UL << DCMIPP_IPGR1_MEMORYPAGE_Pos) /*!< 0x00000007 */ #define DCMIPP_IPGR1_MEMORYPAGE DCMIPP_IPGR1_MEMORYPAGE_Msk /*!< Memory page size, as power of 2 of 64-byte units: */ #define DCMIPP_IPGR1_QOS_MODE_Pos (24U) #define DCMIPP_IPGR1_QOS_MODE_Msk (0x1UL << DCMIPP_IPGR1_QOS_MODE_Pos) /*!< 0x01000000 */ #define DCMIPP_IPGR1_QOS_MODE DCMIPP_IPGR1_QOS_MODE_Msk /*!< Quality of service */ /***************** Bit definition for DCMIPP_IPGR2 register *****************/ #define DCMIPP_IPGR2_PSTART_Pos (0U) #define DCMIPP_IPGR2_PSTART_Msk (0x1UL << DCMIPP_IPGR2_PSTART_Pos) /*!< 0x00000001 */ #define DCMIPP_IPGR2_PSTART DCMIPP_IPGR2_PSTART_Msk /*!< Request to lock the IP-Plug, to allow reconfiguration */ /***************** Bit definition for DCMIPP_IPGR3 register *****************/ #define DCMIPP_IPGR3_IDLE_Pos (0U) #define DCMIPP_IPGR3_IDLE_Msk (0x1UL << DCMIPP_IPGR3_IDLE_Pos) /*!< 0x00000001 */ #define DCMIPP_IPGR3_IDLE DCMIPP_IPGR3_IDLE_Msk /*!< Status of IP-Plug */ /***************** Bit definition for DCMIPP_IPGR8 register *****************/ #define DCMIPP_IPGR8_DID_Pos (0U) #define DCMIPP_IPGR8_DID_Msk (0x3FUL << DCMIPP_IPGR8_DID_Pos) /*!< 0x0000003F */ #define DCMIPP_IPGR8_DID DCMIPP_IPGR8_DID_Msk /*!< Division identifier (0x14) */ #define DCMIPP_IPGR8_REVID_Pos (8U) #define DCMIPP_IPGR8_REVID_Msk (0x1FUL << DCMIPP_IPGR8_REVID_Pos) /*!< 0x00001F00 */ #define DCMIPP_IPGR8_REVID DCMIPP_IPGR8_REVID_Msk /*!< Revision identifier (0x03) */ #define DCMIPP_IPGR8_ARCHIID_Pos (16U) #define DCMIPP_IPGR8_ARCHIID_Msk (0x1FUL << DCMIPP_IPGR8_ARCHIID_Pos) /*!< 0x001F0000 */ #define DCMIPP_IPGR8_ARCHIID DCMIPP_IPGR8_ARCHIID_Msk /*!< Architecture identifier (0x04) */ #define DCMIPP_IPGR8_IPPID_Pos (24U) #define DCMIPP_IPGR8_IPPID_Msk (0xFFUL << DCMIPP_IPGR8_IPPID_Pos) /*!< 0xFF000000 */ #define DCMIPP_IPGR8_IPPID DCMIPP_IPGR8_IPPID_Msk /*!< IP identifier (0xAA) */ /**************** Bit definition for DCMIPP_IPC1R1 register *****************/ #define DCMIPP_IPC1R1_TRAFFIC_Pos (0U) #define DCMIPP_IPC1R1_TRAFFIC_Msk (0x7UL << DCMIPP_IPC1R1_TRAFFIC_Pos) /*!< 0x00000007 */ #define DCMIPP_IPC1R1_TRAFFIC DCMIPP_IPC1R1_TRAFFIC_Msk /*!< Burst size as power of 2 of 8 bytes units */ #define DCMIPP_IPC1R1_OTR_Pos (8U) #define DCMIPP_IPC1R1_OTR_Msk (0xFUL << DCMIPP_IPC1R1_OTR_Pos) /*!< 0x00000F00 */ #define DCMIPP_IPC1R1_OTR DCMIPP_IPC1R1_OTR_Msk /*!< max outstanding transactions: */ /**************** Bit definition for DCMIPP_IPC1R2 register *****************/ #define DCMIPP_IPC1R2_WLRU_Pos (16U) #define DCMIPP_IPC1R2_WLRU_Msk (0xFUL << DCMIPP_IPC1R2_WLRU_Pos) /*!< 0x000F0000 */ #define DCMIPP_IPC1R2_WLRU DCMIPP_IPC1R2_WLRU_Msk /*!< Ratio for WLRU[3:0] arbitration: */ /**************** Bit definition for DCMIPP_IPC1R3 register *****************/ #define DCMIPP_IPC1R3_DPREGSTART_Pos (0U) #define DCMIPP_IPC1R3_DPREGSTART_Msk (0x3FFUL << DCMIPP_IPC1R3_DPREGSTART_Pos) /*!< 0x000003FF */ #define DCMIPP_IPC1R3_DPREGSTART DCMIPP_IPC1R3_DPREGSTART_Msk /*!< Start word (AXI width = 64 bits) of the FIFO of this client */ #define DCMIPP_IPC1R3_DPREGEND_Pos (16U) #define DCMIPP_IPC1R3_DPREGEND_Msk (0x3FFUL << DCMIPP_IPC1R3_DPREGEND_Pos) /*!< 0x03FF0000 */ #define DCMIPP_IPC1R3_DPREGEND DCMIPP_IPC1R3_DPREGEND_Msk /*!< End word (AXI width = 64 bits) of the FIFO of this client */ /**************** Bit definition for DCMIPP_IPC2R1 register *****************/ #define DCMIPP_IPC2R1_TRAFFIC_Pos (0U) #define DCMIPP_IPC2R1_TRAFFIC_Msk (0x7UL << DCMIPP_IPC2R1_TRAFFIC_Pos) /*!< 0x00000007 */ #define DCMIPP_IPC2R1_TRAFFIC DCMIPP_IPC2R1_TRAFFIC_Msk /*!< Burst size as power of 2 of 8 bytes units */ #define DCMIPP_IPC2R1_OTR_Pos (8U) #define DCMIPP_IPC2R1_OTR_Msk (0xFUL << DCMIPP_IPC2R1_OTR_Pos) /*!< 0x00000F00 */ #define DCMIPP_IPC2R1_OTR DCMIPP_IPC2R1_OTR_Msk /*!< max outstanding transactions: */ /**************** Bit definition for DCMIPP_IPC2R2 register *****************/ #define DCMIPP_IPC2R2_WLRU_Pos (16U) #define DCMIPP_IPC2R2_WLRU_Msk (0xFUL << DCMIPP_IPC2R2_WLRU_Pos) /*!< 0x000F0000 */ #define DCMIPP_IPC2R2_WLRU DCMIPP_IPC2R2_WLRU_Msk /*!< Ratio for WLRU[3:0] arbitration: */ /**************** Bit definition for DCMIPP_IPC2R3 register *****************/ #define DCMIPP_IPC2R3_DPREGSTART_Pos (0U) #define DCMIPP_IPC2R3_DPREGSTART_Msk (0x3FFUL << DCMIPP_IPC2R3_DPREGSTART_Pos) /*!< 0x000003FF */ #define DCMIPP_IPC2R3_DPREGSTART DCMIPP_IPC2R3_DPREGSTART_Msk /*!< Start word (AXI width = 64 bits) of the FIFO of this client */ #define DCMIPP_IPC2R3_DPREGEND_Pos (16U) #define DCMIPP_IPC2R3_DPREGEND_Msk (0x3FFUL << DCMIPP_IPC2R3_DPREGEND_Pos) /*!< 0x03FF0000 */ #define DCMIPP_IPC2R3_DPREGEND DCMIPP_IPC2R3_DPREGEND_Msk /*!< End word (AXI width = 64 bits) of the FIFO of this client */ /**************** Bit definition for DCMIPP_IPC3R1 register *****************/ #define DCMIPP_IPC3R1_TRAFFIC_Pos (0U) #define DCMIPP_IPC3R1_TRAFFIC_Msk (0x7UL << DCMIPP_IPC3R1_TRAFFIC_Pos) /*!< 0x00000007 */ #define DCMIPP_IPC3R1_TRAFFIC DCMIPP_IPC3R1_TRAFFIC_Msk /*!< Burst size as power of 2 of 8 bytes units */ #define DCMIPP_IPC3R1_OTR_Pos (8U) #define DCMIPP_IPC3R1_OTR_Msk (0xFUL << DCMIPP_IPC3R1_OTR_Pos) /*!< 0x00000F00 */ #define DCMIPP_IPC3R1_OTR DCMIPP_IPC3R1_OTR_Msk /*!< max outstanding transactions: */ /**************** Bit definition for DCMIPP_IPC3R2 register *****************/ #define DCMIPP_IPC3R2_WLRU_Pos (16U) #define DCMIPP_IPC3R2_WLRU_Msk (0xFUL << DCMIPP_IPC3R2_WLRU_Pos) /*!< 0x000F0000 */ #define DCMIPP_IPC3R2_WLRU DCMIPP_IPC3R2_WLRU_Msk /*!< Ratio for WLRU[3:0] arbitration: */ /**************** Bit definition for DCMIPP_IPC3R3 register *****************/ #define DCMIPP_IPC3R3_DPREGSTART_Pos (0U) #define DCMIPP_IPC3R3_DPREGSTART_Msk (0x3FFUL << DCMIPP_IPC3R3_DPREGSTART_Pos) /*!< 0x000003FF */ #define DCMIPP_IPC3R3_DPREGSTART DCMIPP_IPC3R3_DPREGSTART_Msk /*!< Start word (AXI width = 64 bits) of the FIFO of this client */ #define DCMIPP_IPC3R3_DPREGEND_Pos (16U) #define DCMIPP_IPC3R3_DPREGEND_Msk (0x3FFUL << DCMIPP_IPC3R3_DPREGEND_Pos) /*!< 0x03FF0000 */ #define DCMIPP_IPC3R3_DPREGEND DCMIPP_IPC3R3_DPREGEND_Msk /*!< End word (AXI width = 64 bits) of the FIFO of this client */ /**************** Bit definition for DCMIPP_IPC4R1 register *****************/ #define DCMIPP_IPC4R1_TRAFFIC_Pos (0U) #define DCMIPP_IPC4R1_TRAFFIC_Msk (0x7UL << DCMIPP_IPC4R1_TRAFFIC_Pos) /*!< 0x00000007 */ #define DCMIPP_IPC4R1_TRAFFIC DCMIPP_IPC4R1_TRAFFIC_Msk /*!< Burst size as power of 2 of 8 bytes units */ #define DCMIPP_IPC4R1_OTR_Pos (8U) #define DCMIPP_IPC4R1_OTR_Msk (0xFUL << DCMIPP_IPC4R1_OTR_Pos) /*!< 0x00000F00 */ #define DCMIPP_IPC4R1_OTR DCMIPP_IPC4R1_OTR_Msk /*!< max outstanding transactions: */ /**************** Bit definition for DCMIPP_IPC4R2 register *****************/ #define DCMIPP_IPC4R2_WLRU_Pos (16U) #define DCMIPP_IPC4R2_WLRU_Msk (0xFUL << DCMIPP_IPC4R2_WLRU_Pos) /*!< 0x000F0000 */ #define DCMIPP_IPC4R2_WLRU DCMIPP_IPC4R2_WLRU_Msk /*!< Ratio for WLRU[3:0] arbitration: */ /**************** Bit definition for DCMIPP_IPC4R3 register *****************/ #define DCMIPP_IPC4R3_DPREGSTART_Pos (0U) #define DCMIPP_IPC4R3_DPREGSTART_Msk (0x3FFUL << DCMIPP_IPC4R3_DPREGSTART_Pos) /*!< 0x000003FF */ #define DCMIPP_IPC4R3_DPREGSTART DCMIPP_IPC4R3_DPREGSTART_Msk /*!< Start word (AXI width = 64 bits) of the FIFO of this client */ #define DCMIPP_IPC4R3_DPREGEND_Pos (16U) #define DCMIPP_IPC4R3_DPREGEND_Msk (0x3FFUL << DCMIPP_IPC4R3_DPREGEND_Pos) /*!< 0x03FF0000 */ #define DCMIPP_IPC4R3_DPREGEND DCMIPP_IPC4R3_DPREGEND_Msk /*!< End word (AXI width = 64 bits) of the FIFO of this client */ /**************** Bit definition for DCMIPP_IPC5R1 register *****************/ #define DCMIPP_IPC5R1_TRAFFIC_Pos (0U) #define DCMIPP_IPC5R1_TRAFFIC_Msk (0x7UL << DCMIPP_IPC5R1_TRAFFIC_Pos) /*!< 0x00000007 */ #define DCMIPP_IPC5R1_TRAFFIC DCMIPP_IPC5R1_TRAFFIC_Msk /*!< Burst size as power of 2 of 8 bytes units */ #define DCMIPP_IPC5R1_OTR_Pos (8U) #define DCMIPP_IPC5R1_OTR_Msk (0xFUL << DCMIPP_IPC5R1_OTR_Pos) /*!< 0x00000F00 */ #define DCMIPP_IPC5R1_OTR DCMIPP_IPC5R1_OTR_Msk /*!< max outstanding transactions: */ /**************** Bit definition for DCMIPP_IPC5R2 register *****************/ #define DCMIPP_IPC5R2_WLRU_Pos (16U) #define DCMIPP_IPC5R2_WLRU_Msk (0xFUL << DCMIPP_IPC5R2_WLRU_Pos) /*!< 0x000F0000 */ #define DCMIPP_IPC5R2_WLRU DCMIPP_IPC5R2_WLRU_Msk /*!< Ratio for WLRU[3:0] arbitration: */ /**************** Bit definition for DCMIPP_IPC5R3 register *****************/ #define DCMIPP_IPC5R3_DPREGSTART_Pos (0U) #define DCMIPP_IPC5R3_DPREGSTART_Msk (0x3FFUL << DCMIPP_IPC5R3_DPREGSTART_Pos) /*!< 0x000003FF */ #define DCMIPP_IPC5R3_DPREGSTART DCMIPP_IPC5R3_DPREGSTART_Msk /*!< Start word (AXI width = 64 bits) of the FIFO of this client */ #define DCMIPP_IPC5R3_DPREGEND_Pos (16U) #define DCMIPP_IPC5R3_DPREGEND_Msk (0x3FFUL << DCMIPP_IPC5R3_DPREGEND_Pos) /*!< 0x03FF0000 */ #define DCMIPP_IPC5R3_DPREGEND DCMIPP_IPC5R3_DPREGEND_Msk /*!< End word (AXI width = 64 bits) of the FIFO of this client */ /*************** Bit definition for DCMIPP_PRHWCFGR register ****************/ /***************** Bit definition for DCMIPP_PRCR register ******************/ #define DCMIPP_PRCR_ESS_Pos (4U) #define DCMIPP_PRCR_ESS_Msk (0x1UL << DCMIPP_PRCR_ESS_Pos) /*!< 0x00000010 */ #define DCMIPP_PRCR_ESS DCMIPP_PRCR_ESS_Msk /*!< Embedded synchronization select */ #define DCMIPP_PRCR_PCKPOL_Pos (5U) #define DCMIPP_PRCR_PCKPOL_Msk (0x1UL << DCMIPP_PRCR_PCKPOL_Pos) /*!< 0x00000020 */ #define DCMIPP_PRCR_PCKPOL DCMIPP_PRCR_PCKPOL_Msk /*!< Pixel clock polarity */ #define DCMIPP_PRCR_HSPOL_Pos (6U) #define DCMIPP_PRCR_HSPOL_Msk (0x1UL << DCMIPP_PRCR_HSPOL_Pos) /*!< 0x00000040 */ #define DCMIPP_PRCR_HSPOL DCMIPP_PRCR_HSPOL_Msk /*!< Horizontal synchronization polarity */ #define DCMIPP_PRCR_VSPOL_Pos (7U) #define DCMIPP_PRCR_VSPOL_Msk (0x1UL << DCMIPP_PRCR_VSPOL_Pos) /*!< 0x00000080 */ #define DCMIPP_PRCR_VSPOL DCMIPP_PRCR_VSPOL_Msk /*!< Vertical synchronization polarity */ #define DCMIPP_PRCR_EDM_Pos (10U) #define DCMIPP_PRCR_EDM_Msk (0x7UL << DCMIPP_PRCR_EDM_Pos) /*!< 0x00001C00 */ #define DCMIPP_PRCR_EDM DCMIPP_PRCR_EDM_Msk /*!< Extended data mode */ #define DCMIPP_PRCR_ENABLE_Pos (14U) #define DCMIPP_PRCR_ENABLE_Msk (0x1UL << DCMIPP_PRCR_ENABLE_Pos) /*!< 0x00004000 */ #define DCMIPP_PRCR_ENABLE DCMIPP_PRCR_ENABLE_Msk /*!< Parallel interface enable */ #define DCMIPP_PRCR_FORMAT_Pos (16U) #define DCMIPP_PRCR_FORMAT_Msk (0xFFUL << DCMIPP_PRCR_FORMAT_Pos) /*!< 0x00FF0000 */ #define DCMIPP_PRCR_FORMAT DCMIPP_PRCR_FORMAT_Msk /*!< Other values: Data is captured and output as-is through the data/dump pipeline only (e */ #define DCMIPP_PRCR_SWAPCYCLES_Pos (25U) #define DCMIPP_PRCR_SWAPCYCLES_Msk (0x1UL << DCMIPP_PRCR_SWAPCYCLES_Pos) /*!< 0x02000000 */ #define DCMIPP_PRCR_SWAPCYCLES DCMIPP_PRCR_SWAPCYCLES_Msk /*!< Swap data from cycle 0 vs */ #define DCMIPP_PRCR_SWAPBITS_Pos (26U) #define DCMIPP_PRCR_SWAPBITS_Msk (0x1UL << DCMIPP_PRCR_SWAPBITS_Pos) /*!< 0x04000000 */ #define DCMIPP_PRCR_SWAPBITS DCMIPP_PRCR_SWAPBITS_Msk /*!< Swap LSB vs */ /**************** Bit definition for DCMIPP_PRESCR register *****************/ #define DCMIPP_PRESCR_FSC_Pos (0U) #define DCMIPP_PRESCR_FSC_Msk (0xFFUL << DCMIPP_PRESCR_FSC_Pos) /*!< 0x000000FF */ #define DCMIPP_PRESCR_FSC DCMIPP_PRESCR_FSC_Msk /*!< Frame start delimiter code */ #define DCMIPP_PRESCR_LSC_Pos (8U) #define DCMIPP_PRESCR_LSC_Msk (0xFFUL << DCMIPP_PRESCR_LSC_Pos) /*!< 0x0000FF00 */ #define DCMIPP_PRESCR_LSC DCMIPP_PRESCR_LSC_Msk /*!< Line start delimiter code */ #define DCMIPP_PRESCR_LEC_Pos (16U) #define DCMIPP_PRESCR_LEC_Msk (0xFFUL << DCMIPP_PRESCR_LEC_Pos) /*!< 0x00FF0000 */ #define DCMIPP_PRESCR_LEC DCMIPP_PRESCR_LEC_Msk /*!< Line end delimiter code */ #define DCMIPP_PRESCR_FEC_Pos (24U) #define DCMIPP_PRESCR_FEC_Msk (0xFFUL << DCMIPP_PRESCR_FEC_Pos) /*!< 0xFF000000 */ #define DCMIPP_PRESCR_FEC DCMIPP_PRESCR_FEC_Msk /*!< Frame end delimiter code */ /**************** Bit definition for DCMIPP_PRESUR register *****************/ #define DCMIPP_PRESUR_FSU_Pos (0U) #define DCMIPP_PRESUR_FSU_Msk (0xFFUL << DCMIPP_PRESUR_FSU_Pos) /*!< 0x000000FF */ #define DCMIPP_PRESUR_FSU DCMIPP_PRESUR_FSU_Msk /*!< Frame start delimiter unmask */ #define DCMIPP_PRESUR_LSU_Pos (8U) #define DCMIPP_PRESUR_LSU_Msk (0xFFUL << DCMIPP_PRESUR_LSU_Pos) /*!< 0x0000FF00 */ #define DCMIPP_PRESUR_LSU DCMIPP_PRESUR_LSU_Msk /*!< Line start delimiter unmask */ #define DCMIPP_PRESUR_LEU_Pos (16U) #define DCMIPP_PRESUR_LEU_Msk (0xFFUL << DCMIPP_PRESUR_LEU_Pos) /*!< 0x00FF0000 */ #define DCMIPP_PRESUR_LEU DCMIPP_PRESUR_LEU_Msk /*!< Line end delimiter unmask */ #define DCMIPP_PRESUR_FEU_Pos (24U) #define DCMIPP_PRESUR_FEU_Msk (0xFFUL << DCMIPP_PRESUR_FEU_Pos) /*!< 0xFF000000 */ #define DCMIPP_PRESUR_FEU DCMIPP_PRESUR_FEU_Msk /*!< Frame end delimiter unmask */ /***************** Bit definition for DCMIPP_PRIER register *****************/ #define DCMIPP_PRIER_ERRIE_Pos (6U) #define DCMIPP_PRIER_ERRIE_Msk (0x1UL << DCMIPP_PRIER_ERRIE_Pos) /*!< 0x00000040 */ #define DCMIPP_PRIER_ERRIE DCMIPP_PRIER_ERRIE_Msk /*!< Synchronization error interrupt enable */ /***************** Bit definition for DCMIPP_PRSR register ******************/ #define DCMIPP_PRSR_ERRF_Pos (6U) #define DCMIPP_PRSR_ERRF_Msk (0x1UL << DCMIPP_PRSR_ERRF_Pos) /*!< 0x00000040 */ #define DCMIPP_PRSR_ERRF DCMIPP_PRSR_ERRF_Msk /*!< Synchronization error raw interrupt status */ #define DCMIPP_PRSR_HSYNC_Pos (16U) #define DCMIPP_PRSR_HSYNC_Msk (0x1UL << DCMIPP_PRSR_HSYNC_Pos) /*!< 0x00010000 */ #define DCMIPP_PRSR_HSYNC DCMIPP_PRSR_HSYNC_Msk /*!< This bit gives the state of the HSYNC pin with the correct programmed polarity if the ENABLE bit is */ #define DCMIPP_PRSR_VSYNC_Pos (17U) #define DCMIPP_PRSR_VSYNC_Msk (0x1UL << DCMIPP_PRSR_VSYNC_Pos) /*!< 0x00020000 */ #define DCMIPP_PRSR_VSYNC DCMIPP_PRSR_VSYNC_Msk /*!< This bit gives the state of the VSYNC pin with the correct programmed polarity if the ENABLE bit is */ /***************** Bit definition for DCMIPP_PRFCR register *****************/ #define DCMIPP_PRFCR_CERRF_Pos (6U) #define DCMIPP_PRFCR_CERRF_Msk (0x1UL << DCMIPP_PRFCR_CERRF_Pos) /*!< 0x00000040 */ #define DCMIPP_PRFCR_CERRF DCMIPP_PRFCR_CERRF_Msk /*!< Synchronization error interrupt status clear */ /***************** Bit definition for DCMIPP_CMCR register ******************/ #define DCMIPP_CMCR_INSEL_Pos (0U) #define DCMIPP_CMCR_INSEL_Msk (0x1UL << DCMIPP_CMCR_INSEL_Pos) /*!< 0x00000001 */ #define DCMIPP_CMCR_INSEL DCMIPP_CMCR_INSEL_Msk /*!< input selection */ #define DCMIPP_CMCR_PSFC_Pos (1U) #define DCMIPP_CMCR_PSFC_Msk (0x3UL << DCMIPP_CMCR_PSFC_Pos) /*!< 0x00000006 */ #define DCMIPP_CMCR_PSFC DCMIPP_CMCR_PSFC_Msk /*!< Pipe selection for the frame counter */ #define DCMIPP_CMCR_CFC_Pos (4U) #define DCMIPP_CMCR_CFC_Msk (0x1UL << DCMIPP_CMCR_CFC_Pos) /*!< 0x00000010 */ #define DCMIPP_CMCR_CFC DCMIPP_CMCR_CFC_Msk /*!< Clear frame counter */ #define DCMIPP_CMCR_SWAPRB_Pos (7U) #define DCMIPP_CMCR_SWAPRB_Msk (0x1UL << DCMIPP_CMCR_SWAPRB_Pos) /*!< 0x00000080 */ #define DCMIPP_CMCR_SWAPRB DCMIPP_CMCR_SWAPRB_Msk /*!< Swap R/U and B/V */ /**************** Bit definition for DCMIPP_CMFRCR register *****************/ #define DCMIPP_CMFRCR_FRMCNT_Pos (0U) #define DCMIPP_CMFRCR_FRMCNT_Msk (0xFFFFFFFFUL << DCMIPP_CMFRCR_FRMCNT_Pos) /*!< 0xFFFFFFFF */ #define DCMIPP_CMFRCR_FRMCNT DCMIPP_CMFRCR_FRMCNT_Msk /*!< Frame counter, read-only, loops around */ /***************** Bit definition for DCMIPP_CMIER register *****************/ #define DCMIPP_CMIER_ATXERRIE_Pos (5U) #define DCMIPP_CMIER_ATXERRIE_Msk (0x1UL << DCMIPP_CMIER_ATXERRIE_Pos) /*!< 0x00000020 */ #define DCMIPP_CMIER_ATXERRIE DCMIPP_CMIER_ATXERRIE_Msk /*!< AXI Transfer error interrupt enable for IPPLUG */ #define DCMIPP_CMIER_PRERRIE_Pos (6U) #define DCMIPP_CMIER_PRERRIE_Msk (0x1UL << DCMIPP_CMIER_PRERRIE_Pos) /*!< 0x00000040 */ #define DCMIPP_CMIER_PRERRIE DCMIPP_CMIER_PRERRIE_Msk /*!< limit interrupt enable for the Parallel Interface */ #define DCMIPP_CMIER_P0LINEIE_Pos (8U) #define DCMIPP_CMIER_P0LINEIE_Msk (0x1UL << DCMIPP_CMIER_P0LINEIE_Pos) /*!< 0x00000100 */ #define DCMIPP_CMIER_P0LINEIE DCMIPP_CMIER_P0LINEIE_Msk /*!< multi-Line Capture complete interrupt enable for the Pipe0 */ #define DCMIPP_CMIER_P0FRAMEIE_Pos (9U) #define DCMIPP_CMIER_P0FRAMEIE_Msk (0x1UL << DCMIPP_CMIER_P0FRAMEIE_Pos) /*!< 0x00000200 */ #define DCMIPP_CMIER_P0FRAMEIE DCMIPP_CMIER_P0FRAMEIE_Msk /*!< Frame Capture complete interrupt enable for the Pipe0 */ #define DCMIPP_CMIER_P0VSYNCIE_Pos (10U) #define DCMIPP_CMIER_P0VSYNCIE_Msk (0x1UL << DCMIPP_CMIER_P0VSYNCIE_Pos) /*!< 0x00000400 */ #define DCMIPP_CMIER_P0VSYNCIE DCMIPP_CMIER_P0VSYNCIE_Msk /*!< Vertical sync interrupt enable for the Pipe0 */ #define DCMIPP_CMIER_P0LIMITIE_Pos (14U) #define DCMIPP_CMIER_P0LIMITIE_Msk (0x1UL << DCMIPP_CMIER_P0LIMITIE_Pos) /*!< 0x00004000 */ #define DCMIPP_CMIER_P0LIMITIE DCMIPP_CMIER_P0LIMITIE_Msk /*!< limit interrupt enable for the Pipe0 */ #define DCMIPP_CMIER_P0OVRIE_Pos (15U) #define DCMIPP_CMIER_P0OVRIE_Msk (0x1UL << DCMIPP_CMIER_P0OVRIE_Pos) /*!< 0x00008000 */ #define DCMIPP_CMIER_P0OVRIE DCMIPP_CMIER_P0OVRIE_Msk /*!< Overrun interrupt enable for the Pipe0 */ #define DCMIPP_CMIER_P1LINEIE_Pos (16U) #define DCMIPP_CMIER_P1LINEIE_Msk (0x1UL << DCMIPP_CMIER_P1LINEIE_Pos) /*!< 0x00010000 */ #define DCMIPP_CMIER_P1LINEIE DCMIPP_CMIER_P1LINEIE_Msk /*!< multi-Line Capture complete interrupt status clear for the Pipe1 */ #define DCMIPP_CMIER_P1FRAMEIE_Pos (17U) #define DCMIPP_CMIER_P1FRAMEIE_Msk (0x1UL << DCMIPP_CMIER_P1FRAMEIE_Pos) /*!< 0x00020000 */ #define DCMIPP_CMIER_P1FRAMEIE DCMIPP_CMIER_P1FRAMEIE_Msk /*!< Frame Capture complete interrupt enable for the Pipe1 */ #define DCMIPP_CMIER_P1VSYNCIE_Pos (18U) #define DCMIPP_CMIER_P1VSYNCIE_Msk (0x1UL << DCMIPP_CMIER_P1VSYNCIE_Pos) /*!< 0x00040000 */ #define DCMIPP_CMIER_P1VSYNCIE DCMIPP_CMIER_P1VSYNCIE_Msk /*!< Vertical sync interrupt enable for the Pipe1 */ #define DCMIPP_CMIER_P1OVRIE_Pos (23U) #define DCMIPP_CMIER_P1OVRIE_Msk (0x1UL << DCMIPP_CMIER_P1OVRIE_Pos) /*!< 0x00800000 */ #define DCMIPP_CMIER_P1OVRIE DCMIPP_CMIER_P1OVRIE_Msk /*!< Overrun interrupt enable for the Pipe1 */ #define DCMIPP_CMIER_P2LINEIE_Pos (24U) #define DCMIPP_CMIER_P2LINEIE_Msk (0x1UL << DCMIPP_CMIER_P2LINEIE_Pos) /*!< 0x01000000 */ #define DCMIPP_CMIER_P2LINEIE DCMIPP_CMIER_P2LINEIE_Msk /*!< multi-Line Capture complete interrupt enable for the Pipe2 */ #define DCMIPP_CMIER_P2FRAMEIE_Pos (25U) #define DCMIPP_CMIER_P2FRAMEIE_Msk (0x1UL << DCMIPP_CMIER_P2FRAMEIE_Pos) /*!< 0x02000000 */ #define DCMIPP_CMIER_P2FRAMEIE DCMIPP_CMIER_P2FRAMEIE_Msk /*!< Frame Capture complete interrupt enable for the Pipe2 */ #define DCMIPP_CMIER_P2VSYNCIE_Pos (26U) #define DCMIPP_CMIER_P2VSYNCIE_Msk (0x1UL << DCMIPP_CMIER_P2VSYNCIE_Pos) /*!< 0x04000000 */ #define DCMIPP_CMIER_P2VSYNCIE DCMIPP_CMIER_P2VSYNCIE_Msk /*!< Vertical sync interrupt enable for the Pipe2 */ #define DCMIPP_CMIER_P2OVRIE_Pos (31U) #define DCMIPP_CMIER_P2OVRIE_Msk (0x1UL << DCMIPP_CMIER_P2OVRIE_Pos) /*!< 0x80000000 */ #define DCMIPP_CMIER_P2OVRIE DCMIPP_CMIER_P2OVRIE_Msk /*!< Overrun interrupt status enable for the Pipe2 */ /***************** Bit definition for DCMIPP_CMSR1 register *****************/ #define DCMIPP_CMSR1_PRHSYNC_Pos (0U) #define DCMIPP_CMSR1_PRHSYNC_Msk (0x1UL << DCMIPP_CMSR1_PRHSYNC_Pos) /*!< 0x00000001 */ #define DCMIPP_CMSR1_PRHSYNC DCMIPP_CMSR1_PRHSYNC_Msk /*!< This bit gives the state of the HSYNC pin with the correct programmed polarity on the parallel inte */ #define DCMIPP_CMSR1_PRVSYNC_Pos (1U) #define DCMIPP_CMSR1_PRVSYNC_Msk (0x1UL << DCMIPP_CMSR1_PRVSYNC_Pos) /*!< 0x00000002 */ #define DCMIPP_CMSR1_PRVSYNC DCMIPP_CMSR1_PRVSYNC_Msk /*!< This bit gives the state of the VSYNC pin with the correct programmed polarity on the parallel inte */ #define DCMIPP_CMSR1_P0LSTLINE_Pos (8U) #define DCMIPP_CMSR1_P0LSTLINE_Msk (0x1UL << DCMIPP_CMSR1_P0LSTLINE_Pos) /*!< 0x00000100 */ #define DCMIPP_CMSR1_P0LSTLINE DCMIPP_CMSR1_P0LSTLINE_Msk /*!< Last Line LSB bit, sampled at Frame capture complete event for Pipe0 */ #define DCMIPP_CMSR1_P0LSTFRM_Pos (9U) #define DCMIPP_CMSR1_P0LSTFRM_Msk (0x1UL << DCMIPP_CMSR1_P0LSTFRM_Pos) /*!< 0x00000200 */ #define DCMIPP_CMSR1_P0LSTFRM DCMIPP_CMSR1_P0LSTFRM_Msk /*!< Last frame LSB bit, sampled at Frame capture complete event for Pipe0 */ #define DCMIPP_CMSR1_P0CPTACT_Pos (15U) #define DCMIPP_CMSR1_P0CPTACT_Msk (0x1UL << DCMIPP_CMSR1_P0CPTACT_Pos) /*!< 0x00008000 */ #define DCMIPP_CMSR1_P0CPTACT DCMIPP_CMSR1_P0CPTACT_Msk /*!< Active frame capture (active from start-of-frame to frame complete) for Pipe0 */ #define DCMIPP_CMSR1_P1LSTLINE_Pos (16U) #define DCMIPP_CMSR1_P1LSTLINE_Msk (0x1UL << DCMIPP_CMSR1_P1LSTLINE_Pos) /*!< 0x00010000 */ #define DCMIPP_CMSR1_P1LSTLINE DCMIPP_CMSR1_P1LSTLINE_Msk /*!< Last Line LSB bit, sampled at Frame capture complete event for Pipe1 */ #define DCMIPP_CMSR1_P1LSTFRM_Pos (17U) #define DCMIPP_CMSR1_P1LSTFRM_Msk (0x1UL << DCMIPP_CMSR1_P1LSTFRM_Pos) /*!< 0x00020000 */ #define DCMIPP_CMSR1_P1LSTFRM DCMIPP_CMSR1_P1LSTFRM_Msk /*!< Last frame LSB bit, sampled at frame capture complete event for Pipe1 */ #define DCMIPP_CMSR1_P1CPTACT_Pos (23U) #define DCMIPP_CMSR1_P1CPTACT_Msk (0x1UL << DCMIPP_CMSR1_P1CPTACT_Pos) /*!< 0x00800000 */ #define DCMIPP_CMSR1_P1CPTACT DCMIPP_CMSR1_P1CPTACT_Msk /*!< Active frame capture (active from start-of-frame to frame complete) for Pipe1 */ #define DCMIPP_CMSR1_P2LSTLINE_Pos (24U) #define DCMIPP_CMSR1_P2LSTLINE_Msk (0x1UL << DCMIPP_CMSR1_P2LSTLINE_Pos) /*!< 0x01000000 */ #define DCMIPP_CMSR1_P2LSTLINE DCMIPP_CMSR1_P2LSTLINE_Msk /*!< Last line LSB bit, sampled at Frame capture complete event for Pipe2 */ #define DCMIPP_CMSR1_P2LSTFRM_Pos (25U) #define DCMIPP_CMSR1_P2LSTFRM_Msk (0x1UL << DCMIPP_CMSR1_P2LSTFRM_Pos) /*!< 0x02000000 */ #define DCMIPP_CMSR1_P2LSTFRM DCMIPP_CMSR1_P2LSTFRM_Msk /*!< Last frame LSB bit, sampled at frame capture complete event for Pipe2 */ #define DCMIPP_CMSR1_P2CPTACT_Pos (31U) #define DCMIPP_CMSR1_P2CPTACT_Msk (0x1UL << DCMIPP_CMSR1_P2CPTACT_Pos) /*!< 0x80000000 */ #define DCMIPP_CMSR1_P2CPTACT DCMIPP_CMSR1_P2CPTACT_Msk /*!< Active frame capture (active from start-of-frame to frame complete) for Pipe2 */ /***************** Bit definition for DCMIPP_CMSR2 register *****************/ #define DCMIPP_CMSR2_ATXERRF_Pos (5U) #define DCMIPP_CMSR2_ATXERRF_Msk (0x1UL << DCMIPP_CMSR2_ATXERRF_Pos) /*!< 0x00000020 */ #define DCMIPP_CMSR2_ATXERRF DCMIPP_CMSR2_ATXERRF_Msk /*!< AXI transfer error interrupt status flag for the IPPLUG */ #define DCMIPP_CMSR2_PRERRF_Pos (6U) #define DCMIPP_CMSR2_PRERRF_Msk (0x1UL << DCMIPP_CMSR2_PRERRF_Pos) /*!< 0x00000040 */ #define DCMIPP_CMSR2_PRERRF DCMIPP_CMSR2_PRERRF_Msk /*!< Synchronization error raw interrupt status for the parallel interface */ #define DCMIPP_CMSR2_P0LINEF_Pos (8U) #define DCMIPP_CMSR2_P0LINEF_Msk (0x1UL << DCMIPP_CMSR2_P0LINEF_Pos) /*!< 0x00000100 */ #define DCMIPP_CMSR2_P0LINEF DCMIPP_CMSR2_P0LINEF_Msk /*!< Multi-line capture completed raw interrupt status for Pipe0 */ #define DCMIPP_CMSR2_P0FRAMEF_Pos (9U) #define DCMIPP_CMSR2_P0FRAMEF_Msk (0x1UL << DCMIPP_CMSR2_P0FRAMEF_Pos) /*!< 0x00000200 */ #define DCMIPP_CMSR2_P0FRAMEF DCMIPP_CMSR2_P0FRAMEF_Msk /*!< Frame capture completed raw interrupt status for Pipe0 */ #define DCMIPP_CMSR2_P0VSYNCF_Pos (10U) #define DCMIPP_CMSR2_P0VSYNCF_Msk (0x1UL << DCMIPP_CMSR2_P0VSYNCF_Pos) /*!< 0x00000400 */ #define DCMIPP_CMSR2_P0VSYNCF DCMIPP_CMSR2_P0VSYNCF_Msk /*!< VSYNC raw interrupt status for Pipe0 */ #define DCMIPP_CMSR2_P0LIMITF_Pos (14U) #define DCMIPP_CMSR2_P0LIMITF_Msk (0x1UL << DCMIPP_CMSR2_P0LIMITF_Pos) /*!< 0x00004000 */ #define DCMIPP_CMSR2_P0LIMITF DCMIPP_CMSR2_P0LIMITF_Msk /*!< Limit raw interrupt status for Pipe0 */ #define DCMIPP_CMSR2_P0OVRF_Pos (15U) #define DCMIPP_CMSR2_P0OVRF_Msk (0x1UL << DCMIPP_CMSR2_P0OVRF_Pos) /*!< 0x00008000 */ #define DCMIPP_CMSR2_P0OVRF DCMIPP_CMSR2_P0OVRF_Msk /*!< Overrun raw interrupt status for Pipe0 */ #define DCMIPP_CMSR2_P1LINEF_Pos (16U) #define DCMIPP_CMSR2_P1LINEF_Msk (0x1UL << DCMIPP_CMSR2_P1LINEF_Pos) /*!< 0x00010000 */ #define DCMIPP_CMSR2_P1LINEF DCMIPP_CMSR2_P1LINEF_Msk /*!< Multi-line capture completed raw interrupt status for Pipe1 */ #define DCMIPP_CMSR2_P1FRAMEF_Pos (17U) #define DCMIPP_CMSR2_P1FRAMEF_Msk (0x1UL << DCMIPP_CMSR2_P1FRAMEF_Pos) /*!< 0x00020000 */ #define DCMIPP_CMSR2_P1FRAMEF DCMIPP_CMSR2_P1FRAMEF_Msk /*!< Frame capture completed raw interrupt status for Pipe1 */ #define DCMIPP_CMSR2_P1VSYNCF_Pos (18U) #define DCMIPP_CMSR2_P1VSYNCF_Msk (0x1UL << DCMIPP_CMSR2_P1VSYNCF_Pos) /*!< 0x00040000 */ #define DCMIPP_CMSR2_P1VSYNCF DCMIPP_CMSR2_P1VSYNCF_Msk /*!< VSYNC raw interrupt status for Pipe1 */ #define DCMIPP_CMSR2_P1OVRF_Pos (23U) #define DCMIPP_CMSR2_P1OVRF_Msk (0x1UL << DCMIPP_CMSR2_P1OVRF_Pos) /*!< 0x00800000 */ #define DCMIPP_CMSR2_P1OVRF DCMIPP_CMSR2_P1OVRF_Msk /*!< Overrun raw interrupt status for Pipe1 */ #define DCMIPP_CMSR2_P2LINEF_Pos (24U) #define DCMIPP_CMSR2_P2LINEF_Msk (0x1UL << DCMIPP_CMSR2_P2LINEF_Pos) /*!< 0x01000000 */ #define DCMIPP_CMSR2_P2LINEF DCMIPP_CMSR2_P2LINEF_Msk /*!< Multi-line capture completed raw interrupt status for Pipe2 */ #define DCMIPP_CMSR2_P2FRAMEF_Pos (25U) #define DCMIPP_CMSR2_P2FRAMEF_Msk (0x1UL << DCMIPP_CMSR2_P2FRAMEF_Pos) /*!< 0x02000000 */ #define DCMIPP_CMSR2_P2FRAMEF DCMIPP_CMSR2_P2FRAMEF_Msk /*!< Frame capture completed raw interrupt status for Pipe2 */ #define DCMIPP_CMSR2_P2VSYNCF_Pos (26U) #define DCMIPP_CMSR2_P2VSYNCF_Msk (0x1UL << DCMIPP_CMSR2_P2VSYNCF_Pos) /*!< 0x04000000 */ #define DCMIPP_CMSR2_P2VSYNCF DCMIPP_CMSR2_P2VSYNCF_Msk /*!< VSYNC raw interrupt status for Pipe2 */ #define DCMIPP_CMSR2_P2OVRF_Pos (31U) #define DCMIPP_CMSR2_P2OVRF_Msk (0x1UL << DCMIPP_CMSR2_P2OVRF_Pos) /*!< 0x80000000 */ #define DCMIPP_CMSR2_P2OVRF DCMIPP_CMSR2_P2OVRF_Msk /*!< Overrun raw interrupt status for Pipe2 */ /***************** Bit definition for DCMIPP_CMFCR register *****************/ #define DCMIPP_CMFCR_CATXERRF_Pos (5U) #define DCMIPP_CMFCR_CATXERRF_Msk (0x1UL << DCMIPP_CMFCR_CATXERRF_Pos) /*!< 0x00000020 */ #define DCMIPP_CMFCR_CATXERRF DCMIPP_CMFCR_CATXERRF_Msk /*!< AXI Transfer error interrupt status clear */ #define DCMIPP_CMFCR_CPRERRF_Pos (6U) #define DCMIPP_CMFCR_CPRERRF_Msk (0x1UL << DCMIPP_CMFCR_CPRERRF_Pos) /*!< 0x00000040 */ #define DCMIPP_CMFCR_CPRERRF DCMIPP_CMFCR_CPRERRF_Msk /*!< Synchronization error interrupt status clear */ #define DCMIPP_CMFCR_CP0LINEF_Pos (8U) #define DCMIPP_CMFCR_CP0LINEF_Msk (0x1UL << DCMIPP_CMFCR_CP0LINEF_Pos) /*!< 0x00000100 */ #define DCMIPP_CMFCR_CP0LINEF DCMIPP_CMFCR_CP0LINEF_Msk /*!< Multi-line capture complete interrupt status clear */ #define DCMIPP_CMFCR_CP0FRAMEF_Pos (9U) #define DCMIPP_CMFCR_CP0FRAMEF_Msk (0x1UL << DCMIPP_CMFCR_CP0FRAMEF_Pos) /*!< 0x00000200 */ #define DCMIPP_CMFCR_CP0FRAMEF DCMIPP_CMFCR_CP0FRAMEF_Msk /*!< Frame capture complete interrupt status clear */ #define DCMIPP_CMFCR_CP0VSYNCF_Pos (10U) #define DCMIPP_CMFCR_CP0VSYNCF_Msk (0x1UL << DCMIPP_CMFCR_CP0VSYNCF_Pos) /*!< 0x00000400 */ #define DCMIPP_CMFCR_CP0VSYNCF DCMIPP_CMFCR_CP0VSYNCF_Msk /*!< Vertical synchronization interrupt status clear */ #define DCMIPP_CMFCR_CP0LIMITF_Pos (14U) #define DCMIPP_CMFCR_CP0LIMITF_Msk (0x1UL << DCMIPP_CMFCR_CP0LIMITF_Pos) /*!< 0x00004000 */ #define DCMIPP_CMFCR_CP0LIMITF DCMIPP_CMFCR_CP0LIMITF_Msk /*!< limit interrupt status clear */ #define DCMIPP_CMFCR_CP0OVRF_Pos (15U) #define DCMIPP_CMFCR_CP0OVRF_Msk (0x1UL << DCMIPP_CMFCR_CP0OVRF_Pos) /*!< 0x00008000 */ #define DCMIPP_CMFCR_CP0OVRF DCMIPP_CMFCR_CP0OVRF_Msk /*!< Overrun interrupt status clear */ #define DCMIPP_CMFCR_CP1LINEF_Pos (16U) #define DCMIPP_CMFCR_CP1LINEF_Msk (0x1UL << DCMIPP_CMFCR_CP1LINEF_Pos) /*!< 0x00010000 */ #define DCMIPP_CMFCR_CP1LINEF DCMIPP_CMFCR_CP1LINEF_Msk /*!< Multi-line capture complete interrupt status clear */ #define DCMIPP_CMFCR_CP1FRAMEF_Pos (17U) #define DCMIPP_CMFCR_CP1FRAMEF_Msk (0x1UL << DCMIPP_CMFCR_CP1FRAMEF_Pos) /*!< 0x00020000 */ #define DCMIPP_CMFCR_CP1FRAMEF DCMIPP_CMFCR_CP1FRAMEF_Msk /*!< Frame capture complete interrupt status clear */ #define DCMIPP_CMFCR_CP1VSYNCF_Pos (18U) #define DCMIPP_CMFCR_CP1VSYNCF_Msk (0x1UL << DCMIPP_CMFCR_CP1VSYNCF_Pos) /*!< 0x00040000 */ #define DCMIPP_CMFCR_CP1VSYNCF DCMIPP_CMFCR_CP1VSYNCF_Msk /*!< Vertical synchronization interrupt status clear */ #define DCMIPP_CMFCR_CP1OVRF_Pos (23U) #define DCMIPP_CMFCR_CP1OVRF_Msk (0x1UL << DCMIPP_CMFCR_CP1OVRF_Pos) /*!< 0x00800000 */ #define DCMIPP_CMFCR_CP1OVRF DCMIPP_CMFCR_CP1OVRF_Msk /*!< Overrun interrupt status clear */ #define DCMIPP_CMFCR_CP2LINEF_Pos (24U) #define DCMIPP_CMFCR_CP2LINEF_Msk (0x1UL << DCMIPP_CMFCR_CP2LINEF_Pos) /*!< 0x01000000 */ #define DCMIPP_CMFCR_CP2LINEF DCMIPP_CMFCR_CP2LINEF_Msk /*!< Multi-line capture complete interrupt status clear */ #define DCMIPP_CMFCR_CP2FRAMEF_Pos (25U) #define DCMIPP_CMFCR_CP2FRAMEF_Msk (0x1UL << DCMIPP_CMFCR_CP2FRAMEF_Pos) /*!< 0x02000000 */ #define DCMIPP_CMFCR_CP2FRAMEF DCMIPP_CMFCR_CP2FRAMEF_Msk /*!< Frame capture complete interrupt status clear */ #define DCMIPP_CMFCR_CP2VSYNCF_Pos (26U) #define DCMIPP_CMFCR_CP2VSYNCF_Msk (0x1UL << DCMIPP_CMFCR_CP2VSYNCF_Pos) /*!< 0x04000000 */ #define DCMIPP_CMFCR_CP2VSYNCF DCMIPP_CMFCR_CP2VSYNCF_Msk /*!< Vertical synchronization interrupt status clear */ #define DCMIPP_CMFCR_CP2OVRF_Pos (31U) #define DCMIPP_CMFCR_CP2OVRF_Msk (0x1UL << DCMIPP_CMFCR_CP2OVRF_Pos) /*!< 0x80000000 */ #define DCMIPP_CMFCR_CP2OVRF DCMIPP_CMFCR_CP2OVRF_Msk /*!< Overrun interrupt status clear */ /**************** Bit definition for DCMIPP_P0FSCR register *****************/ #define DCMIPP_P0FSCR_DTIDA_Pos (0U) #define DCMIPP_P0FSCR_DTIDA_Msk (0x3FUL << DCMIPP_P0FSCR_DTIDA_Pos) /*!< 0x0000003F */ #define DCMIPP_P0FSCR_DTIDA DCMIPP_P0FSCR_DTIDA_Msk /*!< Data type selection ID A */ #define DCMIPP_P0FSCR_DTIDB_Pos (8U) #define DCMIPP_P0FSCR_DTIDB_Msk (0x3FUL << DCMIPP_P0FSCR_DTIDB_Pos) /*!< 0x00003F00 */ #define DCMIPP_P0FSCR_DTIDB DCMIPP_P0FSCR_DTIDB_Msk /*!< Data type selection ID B */ #define DCMIPP_P0FSCR_DTMODE_Pos (16U) #define DCMIPP_P0FSCR_DTMODE_Msk (0x3UL << DCMIPP_P0FSCR_DTMODE_Pos) /*!< 0x00030000 */ #define DCMIPP_P0FSCR_DTMODE DCMIPP_P0FSCR_DTMODE_Msk /*!< Flow selection mode */ #define DCMIPP_P0FSCR_VC_Pos (19U) #define DCMIPP_P0FSCR_VC_Msk (0x3UL << DCMIPP_P0FSCR_VC_Pos) /*!< 0x00180000 */ #define DCMIPP_P0FSCR_VC DCMIPP_P0FSCR_VC_Msk /*!< Flow selection mode */ #define DCMIPP_P0FSCR_PIPEN_Pos (31U) #define DCMIPP_P0FSCR_PIPEN_Msk (0x1UL << DCMIPP_P0FSCR_PIPEN_Pos) /*!< 0x80000000 */ #define DCMIPP_P0FSCR_PIPEN DCMIPP_P0FSCR_PIPEN_Msk /*!< Activation of PipeN */ /**************** Bit definition for DCMIPP_P0FCTCR register ****************/ #define DCMIPP_P0FCTCR_FRATE_Pos (0U) #define DCMIPP_P0FCTCR_FRATE_Msk (0x3UL << DCMIPP_P0FCTCR_FRATE_Pos) /*!< 0x00000003 */ #define DCMIPP_P0FCTCR_FRATE DCMIPP_P0FCTCR_FRATE_Msk /*!< Frame capture rate control */ #define DCMIPP_P0FCTCR_CPTMODE_Pos (2U) #define DCMIPP_P0FCTCR_CPTMODE_Msk (0x1UL << DCMIPP_P0FCTCR_CPTMODE_Pos) /*!< 0x00000004 */ #define DCMIPP_P0FCTCR_CPTMODE DCMIPP_P0FCTCR_CPTMODE_Msk /*!< Capture mode */ #define DCMIPP_P0FCTCR_CPTREQ_Pos (3U) #define DCMIPP_P0FCTCR_CPTREQ_Msk (0x1UL << DCMIPP_P0FCTCR_CPTREQ_Pos) /*!< 0x00000008 */ #define DCMIPP_P0FCTCR_CPTREQ DCMIPP_P0FCTCR_CPTREQ_Msk /*!< Capture requested */ /**************** Bit definition for DCMIPP_P0SCSTR register ****************/ #define DCMIPP_P0SCSTR_HSTART_Pos (0U) #define DCMIPP_P0SCSTR_HSTART_Msk (0xFFFUL << DCMIPP_P0SCSTR_HSTART_Pos) /*!< 0x00000FFF */ #define DCMIPP_P0SCSTR_HSTART DCMIPP_P0SCSTR_HSTART_Msk /*!< Horizontal start, from 0 to 4094 words wide */ #define DCMIPP_P0SCSTR_VSTART_Pos (16U) #define DCMIPP_P0SCSTR_VSTART_Msk (0xFFFUL << DCMIPP_P0SCSTR_VSTART_Pos) /*!< 0x0FFF0000 */ #define DCMIPP_P0SCSTR_VSTART DCMIPP_P0SCSTR_VSTART_Msk /*!< Vertical start, from 0 to 4094 pixels high */ /**************** Bit definition for DCMIPP_P0SCSZR register ****************/ #define DCMIPP_P0SCSZR_HSIZE_Pos (0U) #define DCMIPP_P0SCSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P0SCSZR_HSIZE_Pos) /*!< 0x00000FFF */ #define DCMIPP_P0SCSZR_HSIZE DCMIPP_P0SCSZR_HSIZE_Msk /*!< Horizontal size, from 0 to 4094 word wide (data 32-bit) */ #define DCMIPP_P0SCSZR_VSIZE_Pos (16U) #define DCMIPP_P0SCSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P0SCSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ #define DCMIPP_P0SCSZR_VSIZE DCMIPP_P0SCSZR_VSIZE_Msk /*!< Vertical size, from 0 to 4094 pixels high */ #define DCMIPP_P0SCSZR_POSNEG_Pos (30U) #define DCMIPP_P0SCSZR_POSNEG_Msk (0x1UL << DCMIPP_P0SCSZR_POSNEG_Pos) /*!< 0x40000000 */ #define DCMIPP_P0SCSZR_POSNEG DCMIPP_P0SCSZR_POSNEG_Msk /*!< This bit is set and cleared by software */ #define DCMIPP_P0SCSZR_ENABLE_Pos (31U) #define DCMIPP_P0SCSZR_ENABLE_Msk (0x1UL << DCMIPP_P0SCSZR_ENABLE_Pos) /*!< 0x80000000 */ #define DCMIPP_P0SCSZR_ENABLE DCMIPP_P0SCSZR_ENABLE_Msk /*!< This bit is set and cleared by software */ /*************** Bit definition for DCMIPP_P0DCCNTR register ****************/ #define DCMIPP_P0DCCNTR_CNT_Pos (0U) #define DCMIPP_P0DCCNTR_CNT_Msk (0x3FFFFFFUL << DCMIPP_P0DCCNTR_CNT_Pos) /*!< 0x03FFFFFF */ #define DCMIPP_P0DCCNTR_CNT DCMIPP_P0DCCNTR_CNT_Msk /*!< Number of data dumped during the frame */ /*************** Bit definition for DCMIPP_P0DCLMTR register ****************/ #define DCMIPP_P0DCLMTR_LIMIT_Pos (0U) #define DCMIPP_P0DCLMTR_LIMIT_Msk (0xFFFFFFUL << DCMIPP_P0DCLMTR_LIMIT_Pos) /*!< 0x00FFFFFF */ #define DCMIPP_P0DCLMTR_LIMIT DCMIPP_P0DCLMTR_LIMIT_Msk /*!< Maximum number of 32-bit data that can be dumped during a frame, after the crop 2D operation */ #define DCMIPP_P0DCLMTR_ENABLE_Pos (31U) #define DCMIPP_P0DCLMTR_ENABLE_Msk (0x1UL << DCMIPP_P0DCLMTR_ENABLE_Pos) /*!< 0x80000000 */ #define DCMIPP_P0DCLMTR_ENABLE DCMIPP_P0DCLMTR_ENABLE_Msk /*!< */ /**************** Bit definition for DCMIPP_P0PPCR register *****************/ #define DCMIPP_P0PPCR_SWAPYUV_Pos (0U) #define DCMIPP_P0PPCR_SWAPYUV_Msk (0x1UL << DCMIPP_P0PPCR_SWAPYUV_Pos) /*!< 0x00000001 */ #define DCMIPP_P0PPCR_SWAPYUV DCMIPP_P0PPCR_SWAPYUV_Msk /*!< SwapY vs UV bits, when the YUV mode is active */ #define DCMIPP_P0PPCR_PAD_Pos (5U) #define DCMIPP_P0PPCR_PAD_Msk (0x1UL << DCMIPP_P0PPCR_PAD_Pos) /*!< 0x00000020 */ #define DCMIPP_P0PPCR_PAD DCMIPP_P0PPCR_PAD_Msk /*!< Pad mode for monochrome and raw Bayer 10/12/14 bpp: MSB vs */ #define DCMIPP_P0PPCR_HEADEREN_Pos (6U) #define DCMIPP_P0PPCR_HEADEREN_Msk (0x1UL << DCMIPP_P0PPCR_HEADEREN_Pos) /*!< 0x00000040 */ #define DCMIPP_P0PPCR_HEADEREN DCMIPP_P0PPCR_HEADEREN_Msk /*!< CSI header dump enable */ #define DCMIPP_P0PPCR_BSM_Pos (7U) #define DCMIPP_P0PPCR_BSM_Msk (0x3UL << DCMIPP_P0PPCR_BSM_Pos) /*!< 0x00000180 */ #define DCMIPP_P0PPCR_BSM DCMIPP_P0PPCR_BSM_Msk /*!< Byte select mode */ #define DCMIPP_P0PPCR_OEBS_Pos (9U) #define DCMIPP_P0PPCR_OEBS_Msk (0x1UL << DCMIPP_P0PPCR_OEBS_Pos) /*!< 0x00000200 */ #define DCMIPP_P0PPCR_OEBS DCMIPP_P0PPCR_OEBS_Msk /*!< Odd/even byte select (byte select start) */ #define DCMIPP_P0PPCR_LSM_Pos (10U) #define DCMIPP_P0PPCR_LSM_Msk (0x1UL << DCMIPP_P0PPCR_LSM_Pos) /*!< 0x00000400 */ #define DCMIPP_P0PPCR_LSM DCMIPP_P0PPCR_LSM_Msk /*!< Line select mode */ #define DCMIPP_P0PPCR_OELS_Pos (11U) #define DCMIPP_P0PPCR_OELS_Msk (0x1UL << DCMIPP_P0PPCR_OELS_Pos) /*!< 0x00000800 */ #define DCMIPP_P0PPCR_OELS DCMIPP_P0PPCR_OELS_Msk /*!< Odd/even line select (line select start) */ #define DCMIPP_P0PPCR_LINEMULT_Pos (13U) #define DCMIPP_P0PPCR_LINEMULT_Msk (0x7UL << DCMIPP_P0PPCR_LINEMULT_Pos) /*!< 0x0000E000 */ #define DCMIPP_P0PPCR_LINEMULT DCMIPP_P0PPCR_LINEMULT_Msk /*!< Amount of capture completed lines for LINE Event and Interrupt */ #define DCMIPP_P0PPCR_DBM_Pos (16U) #define DCMIPP_P0PPCR_DBM_Msk (0x1UL << DCMIPP_P0PPCR_DBM_Pos) /*!< 0x00010000 */ #define DCMIPP_P0PPCR_DBM DCMIPP_P0PPCR_DBM_Msk /*!< Double buffer mode */ /*************** Bit definition for DCMIPP_P0PPM0AR1 register ***************/ #define DCMIPP_P0PPM0AR1_M0A_Pos (0U) #define DCMIPP_P0PPM0AR1_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P0PPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */ #define DCMIPP_P0PPM0AR1_M0A DCMIPP_P0PPM0AR1_M0A_Msk /*!< Memory0 address */ /*************** Bit definition for DCMIPP_P0PPM0AR2 register ***************/ #define DCMIPP_P0PPM0AR2_M0A_Pos (0U) #define DCMIPP_P0PPM0AR2_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P0PPM0AR2_M0A_Pos) /*!< 0xFFFFFFFF */ #define DCMIPP_P0PPM0AR2_M0A DCMIPP_P0PPM0AR2_M0A_Msk /*!< Memory0 address */ /***************** Bit definition for DCMIPP_P0IER register *****************/ #define DCMIPP_P0IER_LINEIE_Pos (0U) #define DCMIPP_P0IER_LINEIE_Msk (0x1UL << DCMIPP_P0IER_LINEIE_Pos) /*!< 0x00000001 */ #define DCMIPP_P0IER_LINEIE DCMIPP_P0IER_LINEIE_Msk /*!< Multi-line capture completed interrupt enable */ #define DCMIPP_P0IER_FRAMEIE_Pos (1U) #define DCMIPP_P0IER_FRAMEIE_Msk (0x1UL << DCMIPP_P0IER_FRAMEIE_Pos) /*!< 0x00000002 */ #define DCMIPP_P0IER_FRAMEIE DCMIPP_P0IER_FRAMEIE_Msk /*!< Frame capture completed interrupt enable */ #define DCMIPP_P0IER_VSYNCIE_Pos (2U) #define DCMIPP_P0IER_VSYNCIE_Msk (0x1UL << DCMIPP_P0IER_VSYNCIE_Pos) /*!< 0x00000004 */ #define DCMIPP_P0IER_VSYNCIE DCMIPP_P0IER_VSYNCIE_Msk /*!< VSYNC interrupt enable */ #define DCMIPP_P0IER_LIMITIE_Pos (6U) #define DCMIPP_P0IER_LIMITIE_Msk (0x1UL << DCMIPP_P0IER_LIMITIE_Pos) /*!< 0x00000040 */ #define DCMIPP_P0IER_LIMITIE DCMIPP_P0IER_LIMITIE_Msk /*!< Limit interrupt enable */ #define DCMIPP_P0IER_OVRIE_Pos (7U) #define DCMIPP_P0IER_OVRIE_Msk (0x1UL << DCMIPP_P0IER_OVRIE_Pos) /*!< 0x00000080 */ #define DCMIPP_P0IER_OVRIE DCMIPP_P0IER_OVRIE_Msk /*!< Overrun interrupt enable */ /***************** Bit definition for DCMIPP_P0SR register ******************/ #define DCMIPP_P0SR_LINEF_Pos (0U) #define DCMIPP_P0SR_LINEF_Msk (0x1UL << DCMIPP_P0SR_LINEF_Pos) /*!< 0x00000001 */ #define DCMIPP_P0SR_LINEF DCMIPP_P0SR_LINEF_Msk /*!< Multi-line capture completed raw interrupt status */ #define DCMIPP_P0SR_FRAMEF_Pos (1U) #define DCMIPP_P0SR_FRAMEF_Msk (0x1UL << DCMIPP_P0SR_FRAMEF_Pos) /*!< 0x00000002 */ #define DCMIPP_P0SR_FRAMEF DCMIPP_P0SR_FRAMEF_Msk /*!< Frame capture completed raw interrupt status */ #define DCMIPP_P0SR_VSYNCF_Pos (2U) #define DCMIPP_P0SR_VSYNCF_Msk (0x1UL << DCMIPP_P0SR_VSYNCF_Pos) /*!< 0x00000004 */ #define DCMIPP_P0SR_VSYNCF DCMIPP_P0SR_VSYNCF_Msk /*!< VSYNC raw interrupt status */ #define DCMIPP_P0SR_LIMITF_Pos (6U) #define DCMIPP_P0SR_LIMITF_Msk (0x1UL << DCMIPP_P0SR_LIMITF_Pos) /*!< 0x00000040 */ #define DCMIPP_P0SR_LIMITF DCMIPP_P0SR_LIMITF_Msk /*!< Limit raw interrupt status */ #define DCMIPP_P0SR_OVRF_Pos (7U) #define DCMIPP_P0SR_OVRF_Msk (0x1UL << DCMIPP_P0SR_OVRF_Pos) /*!< 0x00000080 */ #define DCMIPP_P0SR_OVRF DCMIPP_P0SR_OVRF_Msk /*!< Overrun raw interrupt status */ #define DCMIPP_P0SR_LSTLINE_Pos (16U) #define DCMIPP_P0SR_LSTLINE_Msk (0x1UL << DCMIPP_P0SR_LSTLINE_Pos) /*!< 0x00010000 */ #define DCMIPP_P0SR_LSTLINE DCMIPP_P0SR_LSTLINE_Msk /*!< Last line LSB bit, sampled at frame capture complete event */ #define DCMIPP_P0SR_LSTFRM_Pos (17U) #define DCMIPP_P0SR_LSTFRM_Msk (0x1UL << DCMIPP_P0SR_LSTFRM_Pos) /*!< 0x00020000 */ #define DCMIPP_P0SR_LSTFRM DCMIPP_P0SR_LSTFRM_Msk /*!< Last frame LSB bit, sampled at frame capture complete event */ #define DCMIPP_P0SR_CPTACT_Pos (23U) #define DCMIPP_P0SR_CPTACT_Msk (0x1UL << DCMIPP_P0SR_CPTACT_Pos) /*!< 0x00800000 */ #define DCMIPP_P0SR_CPTACT DCMIPP_P0SR_CPTACT_Msk /*!< Capture immediate status */ /***************** Bit definition for DCMIPP_P0FCR register *****************/ #define DCMIPP_P0FCR_CLINEF_Pos (0U) #define DCMIPP_P0FCR_CLINEF_Msk (0x1UL << DCMIPP_P0FCR_CLINEF_Pos) /*!< 0x00000001 */ #define DCMIPP_P0FCR_CLINEF DCMIPP_P0FCR_CLINEF_Msk /*!< Multi-line capture complete interrupt status clear */ #define DCMIPP_P0FCR_CFRAMEF_Pos (1U) #define DCMIPP_P0FCR_CFRAMEF_Msk (0x1UL << DCMIPP_P0FCR_CFRAMEF_Pos) /*!< 0x00000002 */ #define DCMIPP_P0FCR_CFRAMEF DCMIPP_P0FCR_CFRAMEF_Msk /*!< Frame capture complete interrupt status clear */ #define DCMIPP_P0FCR_CVSYNCF_Pos (2U) #define DCMIPP_P0FCR_CVSYNCF_Msk (0x1UL << DCMIPP_P0FCR_CVSYNCF_Pos) /*!< 0x00000004 */ #define DCMIPP_P0FCR_CVSYNCF DCMIPP_P0FCR_CVSYNCF_Msk /*!< Vertical synchronization interrupt status clear */ #define DCMIPP_P0FCR_CLIMITF_Pos (6U) #define DCMIPP_P0FCR_CLIMITF_Msk (0x1UL << DCMIPP_P0FCR_CLIMITF_Pos) /*!< 0x00000040 */ #define DCMIPP_P0FCR_CLIMITF DCMIPP_P0FCR_CLIMITF_Msk /*!< limit interrupt status clear */ #define DCMIPP_P0FCR_COVRF_Pos (7U) #define DCMIPP_P0FCR_COVRF_Msk (0x1UL << DCMIPP_P0FCR_COVRF_Pos) /*!< 0x00000080 */ #define DCMIPP_P0FCR_COVRF DCMIPP_P0FCR_COVRF_Msk /*!< Overrun interrupt status clear */ /**************** Bit definition for DCMIPP_P0CFSCR register ****************/ #define DCMIPP_P0CFSCR_DTIDA_Pos (0U) #define DCMIPP_P0CFSCR_DTIDA_Msk (0x3FUL << DCMIPP_P0CFSCR_DTIDA_Pos) /*!< 0x0000003F */ #define DCMIPP_P0CFSCR_DTIDA DCMIPP_P0CFSCR_DTIDA_Msk /*!< Current Data type selection ID A */ #define DCMIPP_P0CFSCR_DTIDB_Pos (8U) #define DCMIPP_P0CFSCR_DTIDB_Msk (0x3FUL << DCMIPP_P0CFSCR_DTIDB_Pos) /*!< 0x00003F00 */ #define DCMIPP_P0CFSCR_DTIDB DCMIPP_P0CFSCR_DTIDB_Msk /*!< Current Data type selection ID B */ #define DCMIPP_P0CFSCR_DTMODE_Pos (16U) #define DCMIPP_P0CFSCR_DTMODE_Msk (0x3UL << DCMIPP_P0CFSCR_DTMODE_Pos) /*!< 0x00030000 */ #define DCMIPP_P0CFSCR_DTMODE DCMIPP_P0CFSCR_DTMODE_Msk /*!< Flow selection mode */ #define DCMIPP_P0CFSCR_VC_Pos (19U) #define DCMIPP_P0CFSCR_VC_Msk (0x3UL << DCMIPP_P0CFSCR_VC_Pos) /*!< 0x00180000 */ #define DCMIPP_P0CFSCR_VC DCMIPP_P0CFSCR_VC_Msk /*!< Current flow selection mode */ #define DCMIPP_P0CFSCR_PIPEN_Pos (31U) #define DCMIPP_P0CFSCR_PIPEN_Msk (0x1UL << DCMIPP_P0CFSCR_PIPEN_Pos) /*!< 0x80000000 */ #define DCMIPP_P0CFSCR_PIPEN DCMIPP_P0CFSCR_PIPEN_Msk /*!< Current activation of PipeN */ /*************** Bit definition for DCMIPP_P0CFCTCR register ****************/ #define DCMIPP_P0CFCTCR_FRATE_Pos (0U) #define DCMIPP_P0CFCTCR_FRATE_Msk (0x3UL << DCMIPP_P0CFCTCR_FRATE_Pos) /*!< 0x00000003 */ #define DCMIPP_P0CFCTCR_FRATE DCMIPP_P0CFCTCR_FRATE_Msk /*!< Frame capture rate control */ #define DCMIPP_P0CFCTCR_CPTMODE_Pos (2U) #define DCMIPP_P0CFCTCR_CPTMODE_Msk (0x1UL << DCMIPP_P0CFCTCR_CPTMODE_Pos) /*!< 0x00000004 */ #define DCMIPP_P0CFCTCR_CPTMODE DCMIPP_P0CFCTCR_CPTMODE_Msk /*!< Capture mode */ #define DCMIPP_P0CFCTCR_CPTREQ_Pos (3U) #define DCMIPP_P0CFCTCR_CPTREQ_Msk (0x1UL << DCMIPP_P0CFCTCR_CPTREQ_Pos) /*!< 0x00000008 */ #define DCMIPP_P0CFCTCR_CPTREQ DCMIPP_P0CFCTCR_CPTREQ_Msk /*!< Capture requested */ /*************** Bit definition for DCMIPP_P0CSCSTR register ****************/ #define DCMIPP_P0CSCSTR_HSTART_Pos (0U) #define DCMIPP_P0CSCSTR_HSTART_Msk (0xFFFUL << DCMIPP_P0CSCSTR_HSTART_Pos) /*!< 0x00000FFF */ #define DCMIPP_P0CSCSTR_HSTART DCMIPP_P0CSCSTR_HSTART_Msk /*!< Current horizontal start, from 0 to 4094 words wide */ #define DCMIPP_P0CSCSTR_VSTART_Pos (16U) #define DCMIPP_P0CSCSTR_VSTART_Msk (0xFFFUL << DCMIPP_P0CSCSTR_VSTART_Pos) /*!< 0x0FFF0000 */ #define DCMIPP_P0CSCSTR_VSTART DCMIPP_P0CSCSTR_VSTART_Msk /*!< Current vertical start, from 0 to 4094 pixels high */ /*************** Bit definition for DCMIPP_P0CSCSZR register ****************/ #define DCMIPP_P0CSCSZR_HSIZE_Pos (0U) #define DCMIPP_P0CSCSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P0CSCSZR_HSIZE_Pos) /*!< 0x00000FFF */ #define DCMIPP_P0CSCSZR_HSIZE DCMIPP_P0CSCSZR_HSIZE_Msk /*!< Current horizontal size, from 0 to 4094 word wide (data 32-bit) */ #define DCMIPP_P0CSCSZR_VSIZE_Pos (16U) #define DCMIPP_P0CSCSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P0CSCSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ #define DCMIPP_P0CSCSZR_VSIZE DCMIPP_P0CSCSZR_VSIZE_Msk /*!< Current vertical size, from 0 to 4094 pixels high */ #define DCMIPP_P0CSCSZR_POSNEG_Pos (30U) #define DCMIPP_P0CSCSZR_POSNEG_Msk (0x1UL << DCMIPP_P0CSCSZR_POSNEG_Pos) /*!< 0x40000000 */ #define DCMIPP_P0CSCSZR_POSNEG DCMIPP_P0CSCSZR_POSNEG_Msk /*!< Current value of the POSNEG bit */ #define DCMIPP_P0CSCSZR_ENABLE_Pos (31U) #define DCMIPP_P0CSCSZR_ENABLE_Msk (0x1UL << DCMIPP_P0CSCSZR_ENABLE_Pos) /*!< 0x80000000 */ #define DCMIPP_P0CSCSZR_ENABLE DCMIPP_P0CSCSZR_ENABLE_Msk /*!< Current value of the ENABLE bit */ /**************** Bit definition for DCMIPP_P0CPPCR register ****************/ #define DCMIPP_P0CPPCR_SWAPYUV_Pos (0U) #define DCMIPP_P0CPPCR_SWAPYUV_Msk (0x1UL << DCMIPP_P0CPPCR_SWAPYUV_Pos) /*!< 0x00000001 */ #define DCMIPP_P0CPPCR_SWAPYUV DCMIPP_P0CPPCR_SWAPYUV_Msk /*!< SwapY vs UV bits, when the YUV mode is active */ #define DCMIPP_P0CPPCR_PAD_Pos (5U) #define DCMIPP_P0CPPCR_PAD_Msk (0x1UL << DCMIPP_P0CPPCR_PAD_Pos) /*!< 0x00000020 */ #define DCMIPP_P0CPPCR_PAD DCMIPP_P0CPPCR_PAD_Msk /*!< Current Pad mode for monochrome and raw Bayer 10/12/14 bpp: MSB vs */ #define DCMIPP_P0CPPCR_HEADEREN_Pos (6U) #define DCMIPP_P0CPPCR_HEADEREN_Msk (0x1UL << DCMIPP_P0CPPCR_HEADEREN_Pos) /*!< 0x00000040 */ #define DCMIPP_P0CPPCR_HEADEREN DCMIPP_P0CPPCR_HEADEREN_Msk /*!< Current CSI header dump enable */ #define DCMIPP_P0CPPCR_BSM_Pos (7U) #define DCMIPP_P0CPPCR_BSM_Msk (0x3UL << DCMIPP_P0CPPCR_BSM_Pos) /*!< 0x00000180 */ #define DCMIPP_P0CPPCR_BSM DCMIPP_P0CPPCR_BSM_Msk /*!< Current Byte select mode */ #define DCMIPP_P0CPPCR_OEBS_Pos (9U) #define DCMIPP_P0CPPCR_OEBS_Msk (0x1UL << DCMIPP_P0CPPCR_OEBS_Pos) /*!< 0x00000200 */ #define DCMIPP_P0CPPCR_OEBS DCMIPP_P0CPPCR_OEBS_Msk /*!< Current odd/even byte select (Byte select start) */ #define DCMIPP_P0CPPCR_LSM_Pos (10U) #define DCMIPP_P0CPPCR_LSM_Msk (0x1UL << DCMIPP_P0CPPCR_LSM_Pos) /*!< 0x00000400 */ #define DCMIPP_P0CPPCR_LSM DCMIPP_P0CPPCR_LSM_Msk /*!< Current Line select mode */ #define DCMIPP_P0CPPCR_OELS_Pos (11U) #define DCMIPP_P0CPPCR_OELS_Msk (0x1UL << DCMIPP_P0CPPCR_OELS_Pos) /*!< 0x00000800 */ #define DCMIPP_P0CPPCR_OELS DCMIPP_P0CPPCR_OELS_Msk /*!< Current odd/even line select (Line select start) */ #define DCMIPP_P0CPPCR_LINEMULT_Pos (13U) #define DCMIPP_P0CPPCR_LINEMULT_Msk (0x7UL << DCMIPP_P0CPPCR_LINEMULT_Pos) /*!< 0x0000E000 */ #define DCMIPP_P0CPPCR_LINEMULT DCMIPP_P0CPPCR_LINEMULT_Msk /*!< Current amount of capture completed lines for LINE Event and Interrupt */ #define DCMIPP_P0CPPCR_DBM_Pos (16U) #define DCMIPP_P0CPPCR_DBM_Msk (0x1UL << DCMIPP_P0CPPCR_LINEMULT_Pos) /*!< 0x00010000 */ #define DCMIPP_P0CPPCR_DBM DCMIPP_P0CPPCR_LINEMULT_Msk /*!< Double buffer mode */ /************** Bit definition for DCMIPP_P0CPPM0AR1 register ***************/ #define DCMIPP_P0CPPM0AR1_M0A_Pos (0U) #define DCMIPP_P0CPPM0AR1_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P0CPPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */ #define DCMIPP_P0CPPM0AR1_M0A DCMIPP_P0CPPM0AR1_M0A_Msk /*!< Memory0 address */ /**************** Bit definition for DCMIPP_P1FSCR register *****************/ #define DCMIPP_P1FSCR_DTIDA_Pos (0U) #define DCMIPP_P1FSCR_DTIDA_Msk (0x3FUL << DCMIPP_P1FSCR_DTIDA_Pos) /*!< 0x0000003F */ #define DCMIPP_P1FSCR_DTIDA DCMIPP_P1FSCR_DTIDA_Msk /*!< Data type ID A */ #define DCMIPP_P1FSCR_DTIDB_Pos (8U) #define DCMIPP_P1FSCR_DTIDB_Msk (0x3FUL << DCMIPP_P1FSCR_DTIDB_Pos) /*!< 0x00003F00 */ #define DCMIPP_P1FSCR_DTIDB DCMIPP_P1FSCR_DTIDB_Msk /*!< Data type ID B */ #define DCMIPP_P1FSCR_DTMODE_Pos (16U) #define DCMIPP_P1FSCR_DTMODE_Msk (0x3UL << DCMIPP_P1FSCR_DTMODE_Pos) /*!< 0x00030000 */ #define DCMIPP_P1FSCR_DTMODE DCMIPP_P1FSCR_DTMODE_Msk /*!< Flow selection mode */ #define DCMIPP_P1FSCR_PIPEDIFF_Pos (18U) #define DCMIPP_P1FSCR_PIPEDIFF_Msk (0x1UL << DCMIPP_P1FSCR_PIPEDIFF_Pos) /*!< 0x00040000 */ #define DCMIPP_P1FSCR_PIPEDIFF DCMIPP_P1FSCR_PIPEDIFF_Msk /*!< Differentiates Pipe2 vs */ #define DCMIPP_P1FSCR_VC_Pos (19U) #define DCMIPP_P1FSCR_VC_Msk (0x3UL << DCMIPP_P1FSCR_VC_Pos) /*!< 0x00180000 */ #define DCMIPP_P1FSCR_VC DCMIPP_P1FSCR_VC_Msk /*!< Flow selection mode */ #define DCMIPP_P1FSCR_FDTF_Pos (24U) #define DCMIPP_P1FSCR_FDTF_Msk (0x3FUL << DCMIPP_P1FSCR_FDTF_Pos) /*!< 0x3F000000 */ #define DCMIPP_P1FSCR_FDTF DCMIPP_P1FSCR_FDTF_Msk /*!< Force Data type format */ #define DCMIPP_P1FSCR_FDTFEN_Pos (30U) #define DCMIPP_P1FSCR_FDTFEN_Msk (0x1UL << DCMIPP_P1FSCR_FDTFEN_Pos) /*!< 0x40000000 */ #define DCMIPP_P1FSCR_FDTFEN DCMIPP_P1FSCR_FDTFEN_Msk /*!< Force Data type format enable */ #define DCMIPP_P1FSCR_PIPEN_Pos (31U) #define DCMIPP_P1FSCR_PIPEN_Msk (0x1UL << DCMIPP_P1FSCR_PIPEN_Pos) /*!< 0x80000000 */ #define DCMIPP_P1FSCR_PIPEN DCMIPP_P1FSCR_PIPEN_Msk /*!< Activation of PipeN */ /**************** Bit definition for DCMIPP_P1SRCR register *****************/ #define DCMIPP_P1SRCR_LASTLINE_Pos (0U) #define DCMIPP_P1SRCR_LASTLINE_Msk (0xFFFUL << DCMIPP_P1SRCR_LASTLINE_Pos) /*!< 0x00000FFF */ #define DCMIPP_P1SRCR_LASTLINE DCMIPP_P1SRCR_LASTLINE_Msk /*!< Number of the last line to be kept when CROPEN = 1 */ #define DCMIPP_P1SRCR_FIRSTLINEDEL_Pos (12U) #define DCMIPP_P1SRCR_FIRSTLINEDEL_Msk (0x7UL << DCMIPP_P1SRCR_FIRSTLINEDEL_Pos) /*!< 0x00007000 */ #define DCMIPP_P1SRCR_FIRSTLINEDEL DCMIPP_P1SRCR_FIRSTLINEDEL_Msk /*!< Number of lines to be deleted when CROPEN = 1 */ #define DCMIPP_P1SRCR_CROPEN_Pos (15U) #define DCMIPP_P1SRCR_CROPEN_Msk (0x1UL << DCMIPP_P1SRCR_CROPEN_Pos) /*!< 0x00008000 */ #define DCMIPP_P1SRCR_CROPEN DCMIPP_P1SRCR_CROPEN_Msk /*!< Crop line enable */ /**************** Bit definition for DCMIPP_P1BPRCR register ****************/ #define DCMIPP_P1BPRCR_ENABLE_Pos (0U) #define DCMIPP_P1BPRCR_ENABLE_Msk (0x1UL << DCMIPP_P1BPRCR_ENABLE_Pos) /*!< 0x00000001 */ #define DCMIPP_P1BPRCR_ENABLE DCMIPP_P1BPRCR_ENABLE_Msk /*!< Bad pixel detection must be enabled only for raw Bayer flows, as it corrupts RGB flows */ #define DCMIPP_P1BPRCR_STRENGTH_Pos (1U) #define DCMIPP_P1BPRCR_STRENGTH_Msk (0x7UL << DCMIPP_P1BPRCR_STRENGTH_Pos) /*!< 0x0000000E */ #define DCMIPP_P1BPRCR_STRENGTH DCMIPP_P1BPRCR_STRENGTH_Msk /*!< Strength (aggressivity) of the bad pixel detection: */ /**************** Bit definition for DCMIPP_P1BPRSR register ****************/ #define DCMIPP_P1BPRSR_BADCNT_Pos (0U) #define DCMIPP_P1BPRSR_BADCNT_Msk (0xFFFUL << DCMIPP_P1BPRSR_BADCNT_Pos) /*!< 0x00000FFF */ #define DCMIPP_P1BPRSR_BADCNT DCMIPP_P1BPRSR_BADCNT_Msk /*!< Amount of detected bad pixels */ /**************** Bit definition for DCMIPP_P1DECR register *****************/ #define DCMIPP_P1DECR_ENABLE_Pos (0U) #define DCMIPP_P1DECR_ENABLE_Msk (0x1UL << DCMIPP_P1DECR_ENABLE_Pos) /*!< 0x00000001 */ #define DCMIPP_P1DECR_ENABLE DCMIPP_P1DECR_ENABLE_Msk /*!< */ #define DCMIPP_P1DECR_HDEC_Pos (1U) #define DCMIPP_P1DECR_HDEC_Msk (0x3UL << DCMIPP_P1DECR_HDEC_Pos) /*!< 0x00000006 */ #define DCMIPP_P1DECR_HDEC DCMIPP_P1DECR_HDEC_Msk /*!< Horizontal decimation ratio */ #define DCMIPP_P1DECR_VDEC_Pos (3U) #define DCMIPP_P1DECR_VDEC_Msk (0x3UL << DCMIPP_P1DECR_VDEC_Pos) /*!< 0x00000018 */ #define DCMIPP_P1DECR_VDEC DCMIPP_P1DECR_VDEC_Msk /*!< Vertical decimation ratio */ /**************** Bit definition for DCMIPP_P1BLCCR register ****************/ #define DCMIPP_P1BLCCR_ENABLE_Pos (0U) #define DCMIPP_P1BLCCR_ENABLE_Msk (0x1UL << DCMIPP_P1BLCCR_ENABLE_Pos) /*!< 0x00000001 */ #define DCMIPP_P1BLCCR_ENABLE DCMIPP_P1BLCCR_ENABLE_Msk /*!< Black level calibration */ #define DCMIPP_P1BLCCR_BLCB_Pos (8U) #define DCMIPP_P1BLCCR_BLCB_Msk (0xFFUL << DCMIPP_P1BLCCR_BLCB_Pos) /*!< 0x0000FF00 */ #define DCMIPP_P1BLCCR_BLCB DCMIPP_P1BLCCR_BLCB_Msk /*!< Black level calibration - Blue */ #define DCMIPP_P1BLCCR_BLCG_Pos (16U) #define DCMIPP_P1BLCCR_BLCG_Msk (0xFFUL << DCMIPP_P1BLCCR_BLCG_Pos) /*!< 0x00FF0000 */ #define DCMIPP_P1BLCCR_BLCG DCMIPP_P1BLCCR_BLCG_Msk /*!< Black level calibration - Green */ #define DCMIPP_P1BLCCR_BLCR_Pos (24U) #define DCMIPP_P1BLCCR_BLCR_Msk (0xFFUL << DCMIPP_P1BLCCR_BLCR_Pos) /*!< 0xFF000000 */ #define DCMIPP_P1BLCCR_BLCR DCMIPP_P1BLCCR_BLCR_Msk /*!< Black level calibration - Red */ /**************** Bit definition for DCMIPP_P1EXCR1 register ****************/ #define DCMIPP_P1EXCR1_ENABLE_Pos (0U) #define DCMIPP_P1EXCR1_ENABLE_Msk (0x1UL << DCMIPP_P1EXCR1_ENABLE_Pos) /*!< 0x00000001 */ #define DCMIPP_P1EXCR1_ENABLE DCMIPP_P1EXCR1_ENABLE_Msk /*!< Exposure control (multiplication and shift) of all red, green and blue */ #define DCMIPP_P1EXCR1_MULTR_Pos (20U) #define DCMIPP_P1EXCR1_MULTR_Msk (0xFFUL << DCMIPP_P1EXCR1_MULTR_Pos) /*!< 0x0FF00000 */ #define DCMIPP_P1EXCR1_MULTR DCMIPP_P1EXCR1_MULTR_Msk /*!< Exposure multiplier - Red */ #define DCMIPP_P1EXCR1_SHFR_Pos (28U) #define DCMIPP_P1EXCR1_SHFR_Msk (0x7UL << DCMIPP_P1EXCR1_SHFR_Pos) /*!< 0x70000000 */ #define DCMIPP_P1EXCR1_SHFR DCMIPP_P1EXCR1_SHFR_Msk /*!< Exposure shift - Red */ /**************** Bit definition for DCMIPP_P1EXCR2 register ****************/ #define DCMIPP_P1EXCR2_MULTB_Pos (4U) #define DCMIPP_P1EXCR2_MULTB_Msk (0xFFUL << DCMIPP_P1EXCR2_MULTB_Pos) /*!< 0x00000FF0 */ #define DCMIPP_P1EXCR2_MULTB DCMIPP_P1EXCR2_MULTB_Msk /*!< Exposure multiplier - Blue */ #define DCMIPP_P1EXCR2_SHFB_Pos (12U) #define DCMIPP_P1EXCR2_SHFB_Msk (0x7UL << DCMIPP_P1EXCR2_SHFB_Pos) /*!< 0x00007000 */ #define DCMIPP_P1EXCR2_SHFB DCMIPP_P1EXCR2_SHFB_Msk /*!< Exposure shift - Blue */ #define DCMIPP_P1EXCR2_MULTG_Pos (20U) #define DCMIPP_P1EXCR2_MULTG_Msk (0xFFUL << DCMIPP_P1EXCR2_MULTG_Pos) /*!< 0x0FF00000 */ #define DCMIPP_P1EXCR2_MULTG DCMIPP_P1EXCR2_MULTG_Msk /*!< Exposure multiplier - Green */ #define DCMIPP_P1EXCR2_SHFG_Pos (28U) #define DCMIPP_P1EXCR2_SHFG_Msk (0x7UL << DCMIPP_P1EXCR2_SHFG_Pos) /*!< 0x70000000 */ #define DCMIPP_P1EXCR2_SHFG DCMIPP_P1EXCR2_SHFG_Msk /*!< Exposure shift - Green */ /**************** Bit definition for DCMIPP_P1ST1CR register ****************/ #define DCMIPP_P1ST1CR_ENABLE_Pos (0U) #define DCMIPP_P1ST1CR_ENABLE_Msk (0x1UL << DCMIPP_P1ST1CR_ENABLE_Pos) /*!< 0x00000001 */ #define DCMIPP_P1ST1CR_ENABLE DCMIPP_P1ST1CR_ENABLE_Msk /*!< */ #define DCMIPP_P1ST1CR_BINS_Pos (2U) #define DCMIPP_P1ST1CR_BINS_Msk (0x3UL << DCMIPP_P1ST1CR_BINS_Pos) /*!< 0x0000000C */ #define DCMIPP_P1ST1CR_BINS DCMIPP_P1ST1CR_BINS_Msk /*!< Bin definition */ #define DCMIPP_P1ST1CR_SRC_Pos (4U) #define DCMIPP_P1ST1CR_SRC_Msk (0x7UL << DCMIPP_P1ST1CR_SRC_Pos) /*!< 0x00000070 */ #define DCMIPP_P1ST1CR_SRC DCMIPP_P1ST1CR_SRC_Msk /*!< Statistics source */ #define DCMIPP_P1ST1CR_MODE_Pos (7U) #define DCMIPP_P1ST1CR_MODE_Msk (0x1UL << DCMIPP_P1ST1CR_MODE_Pos) /*!< 0x00000080 */ #define DCMIPP_P1ST1CR_MODE DCMIPP_P1ST1CR_MODE_Msk /*!< Statistics mode */ /**************** Bit definition for DCMIPP_P1ST2CR register ****************/ #define DCMIPP_P1ST2CR_ENABLE_Pos (0U) #define DCMIPP_P1ST2CR_ENABLE_Msk (0x1UL << DCMIPP_P1ST2CR_ENABLE_Pos) /*!< 0x00000001 */ #define DCMIPP_P1ST2CR_ENABLE DCMIPP_P1ST2CR_ENABLE_Msk /*!< */ #define DCMIPP_P1ST2CR_BINS_Pos (2U) #define DCMIPP_P1ST2CR_BINS_Msk (0x3UL << DCMIPP_P1ST2CR_BINS_Pos) /*!< 0x0000000C */ #define DCMIPP_P1ST2CR_BINS DCMIPP_P1ST2CR_BINS_Msk /*!< Bin definition */ #define DCMIPP_P1ST2CR_SRC_Pos (4U) #define DCMIPP_P1ST2CR_SRC_Msk (0x7UL << DCMIPP_P1ST2CR_SRC_Pos) /*!< 0x00000070 */ #define DCMIPP_P1ST2CR_SRC DCMIPP_P1ST2CR_SRC_Msk /*!< Statistics source */ #define DCMIPP_P1ST2CR_MODE_Pos (7U) #define DCMIPP_P1ST2CR_MODE_Msk (0x1UL << DCMIPP_P1ST2CR_MODE_Pos) /*!< 0x00000080 */ #define DCMIPP_P1ST2CR_MODE DCMIPP_P1ST2CR_MODE_Msk /*!< Statistics mode */ /**************** Bit definition for DCMIPP_P1ST3CR register ****************/ #define DCMIPP_P1ST3CR_ENABLE_Pos (0U) #define DCMIPP_P1ST3CR_ENABLE_Msk (0x1UL << DCMIPP_P1ST3CR_ENABLE_Pos) /*!< 0x00000001 */ #define DCMIPP_P1ST3CR_ENABLE DCMIPP_P1ST3CR_ENABLE_Msk /*!< */ #define DCMIPP_P1ST3CR_BINS_Pos (2U) #define DCMIPP_P1ST3CR_BINS_Msk (0x3UL << DCMIPP_P1ST3CR_BINS_Pos) /*!< 0x0000000C */ #define DCMIPP_P1ST3CR_BINS DCMIPP_P1ST3CR_BINS_Msk /*!< Bin definition */ #define DCMIPP_P1ST3CR_SRC_Pos (4U) #define DCMIPP_P1ST3CR_SRC_Msk (0x7UL << DCMIPP_P1ST3CR_SRC_Pos) /*!< 0x00000070 */ #define DCMIPP_P1ST3CR_SRC DCMIPP_P1ST3CR_SRC_Msk /*!< Statistics source */ #define DCMIPP_P1ST3CR_MODE_Pos (7U) #define DCMIPP_P1ST3CR_MODE_Msk (0x1UL << DCMIPP_P1ST3CR_MODE_Pos) /*!< 0x00000080 */ #define DCMIPP_P1ST3CR_MODE DCMIPP_P1ST3CR_MODE_Msk /*!< Statistics mode */ /**************** Bit definition for DCMIPP_P1STSTR register ****************/ #define DCMIPP_P1STSTR_HSTART_Pos (0U) #define DCMIPP_P1STSTR_HSTART_Msk (0xFFFUL << DCMIPP_P1STSTR_HSTART_Pos) /*!< 0x00000FFF */ #define DCMIPP_P1STSTR_HSTART DCMIPP_P1STSTR_HSTART_Msk /*!< Horizontal start, from 0 to 4094 pixels wide */ #define DCMIPP_P1STSTR_VSTART_Pos (16U) #define DCMIPP_P1STSTR_VSTART_Msk (0xFFFUL << DCMIPP_P1STSTR_VSTART_Pos) /*!< 0x0FFF0000 */ #define DCMIPP_P1STSTR_VSTART DCMIPP_P1STSTR_VSTART_Msk /*!< Vertical start, from 0 to 4094 pixels high */ /**************** Bit definition for DCMIPP_P1STSZR register ****************/ #define DCMIPP_P1STSZR_HSIZE_Pos (0U) #define DCMIPP_P1STSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P1STSZR_HSIZE_Pos) /*!< 0x00000FFF */ #define DCMIPP_P1STSZR_HSIZE DCMIPP_P1STSZR_HSIZE_Msk /*!< Horizontal size, from 0 to 4094 pixels wide */ #define DCMIPP_P1STSZR_VSIZE_Pos (16U) #define DCMIPP_P1STSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P1STSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ #define DCMIPP_P1STSZR_VSIZE DCMIPP_P1STSZR_VSIZE_Msk /*!< Vertical size, from 0 to 4094 pixels high */ #define DCMIPP_P1STSZR_CROPEN_Pos (31U) #define DCMIPP_P1STSZR_CROPEN_Msk (0x1UL << DCMIPP_P1STSZR_CROPEN_Pos) /*!< 0x80000000 */ #define DCMIPP_P1STSZR_CROPEN DCMIPP_P1STSZR_CROPEN_Msk /*!< */ /**************** Bit definition for DCMIPP_P1ST1SR register ****************/ #define DCMIPP_P1ST1SR_ACCU_Pos (0U) #define DCMIPP_P1ST1SR_ACCU_Msk (0xFFFFFFUL << DCMIPP_P1ST1SR_ACCU_Pos) /*!< 0x00FFFFFF */ #define DCMIPP_P1ST1SR_ACCU DCMIPP_P1ST1SR_ACCU_Msk /*!< Accumulation result, divided by 256 */ /**************** Bit definition for DCMIPP_P1ST2SR register ****************/ #define DCMIPP_P1ST2SR_ACCU_Pos (0U) #define DCMIPP_P1ST2SR_ACCU_Msk (0xFFFFFFUL << DCMIPP_P1ST2SR_ACCU_Pos) /*!< 0x00FFFFFF */ #define DCMIPP_P1ST2SR_ACCU DCMIPP_P1ST2SR_ACCU_Msk /*!< accumulation result, divided by 256 */ /**************** Bit definition for DCMIPP_P1ST3SR register ****************/ #define DCMIPP_P1ST3SR_ACCU_Pos (0U) #define DCMIPP_P1ST3SR_ACCU_Msk (0xFFFFFFUL << DCMIPP_P1ST3SR_ACCU_Pos) /*!< 0x00FFFFFF */ #define DCMIPP_P1ST3SR_ACCU DCMIPP_P1ST3SR_ACCU_Msk /*!< accumulation result, divided by 256 */ /**************** Bit definition for DCMIPP_P1DMCR register *****************/ #define DCMIPP_P1DMCR_ENABLE_Pos (0U) #define DCMIPP_P1DMCR_ENABLE_Msk (0x1UL << DCMIPP_P1DMCR_ENABLE_Pos) /*!< 0x00000001 */ #define DCMIPP_P1DMCR_ENABLE DCMIPP_P1DMCR_ENABLE_Msk /*!< */ #define DCMIPP_P1DMCR_TYPE_Pos (1U) #define DCMIPP_P1DMCR_TYPE_Msk (0x3UL << DCMIPP_P1DMCR_TYPE_Pos) /*!< 0x00000006 */ #define DCMIPP_P1DMCR_TYPE DCMIPP_P1DMCR_TYPE_Msk /*!< Raw Bayer type */ #define DCMIPP_P1DMCR_PEAK_Pos (16U) #define DCMIPP_P1DMCR_PEAK_Msk (0x7UL << DCMIPP_P1DMCR_PEAK_Pos) /*!< 0x00070000 */ #define DCMIPP_P1DMCR_PEAK DCMIPP_P1DMCR_PEAK_Msk /*!< Strength of the peak detection */ #define DCMIPP_P1DMCR_LINEV_Pos (20U) #define DCMIPP_P1DMCR_LINEV_Msk (0x7UL << DCMIPP_P1DMCR_LINEV_Pos) /*!< 0x00700000 */ #define DCMIPP_P1DMCR_LINEV DCMIPP_P1DMCR_LINEV_Msk /*!< Strength of the vertical line detection */ #define DCMIPP_P1DMCR_LINEH_Pos (24U) #define DCMIPP_P1DMCR_LINEH_Msk (0x7UL << DCMIPP_P1DMCR_LINEH_Pos) /*!< 0x07000000 */ #define DCMIPP_P1DMCR_LINEH DCMIPP_P1DMCR_LINEH_Msk /*!< Strength of the horizontal line detection */ #define DCMIPP_P1DMCR_EDGE_Pos (28U) #define DCMIPP_P1DMCR_EDGE_Msk (0x7UL << DCMIPP_P1DMCR_EDGE_Pos) /*!< 0x70000000 */ #define DCMIPP_P1DMCR_EDGE DCMIPP_P1DMCR_EDGE_Msk /*!< Strength of the edge detection */ /**************** Bit definition for DCMIPP_P1CCCR register *****************/ #define DCMIPP_P1CCCR_ENABLE_Pos (0U) #define DCMIPP_P1CCCR_ENABLE_Msk (0x1UL << DCMIPP_P1CCCR_ENABLE_Pos) /*!< 0x00000001 */ #define DCMIPP_P1CCCR_ENABLE DCMIPP_P1CCCR_ENABLE_Msk /*!< */ #define DCMIPP_P1CCCR_TYPE_Pos (1U) #define DCMIPP_P1CCCR_TYPE_Msk (0x1UL << DCMIPP_P1CCCR_TYPE_Pos) /*!< 0x00000002 */ #define DCMIPP_P1CCCR_TYPE DCMIPP_P1CCCR_TYPE_Msk /*!< output samples type used while CLAMP is activated */ #define DCMIPP_P1CCCR_CLAMP_Pos (2U) #define DCMIPP_P1CCCR_CLAMP_Msk (0x1UL << DCMIPP_P1CCCR_CLAMP_Pos) /*!< 0x00000004 */ #define DCMIPP_P1CCCR_CLAMP DCMIPP_P1CCCR_CLAMP_Msk /*!< Clamp the output samples */ /**************** Bit definition for DCMIPP_P1CCRR1 register ****************/ #define DCMIPP_P1CCRR1_RR_Pos (0U) #define DCMIPP_P1CCRR1_RR_Msk (0x7FFUL << DCMIPP_P1CCRR1_RR_Pos) /*!< 0x000007FF */ #define DCMIPP_P1CCRR1_RR DCMIPP_P1CCRR1_RR_Msk /*!< Coefficient row 1 column 1 of the matrix */ #define DCMIPP_P1CCRR1_RG_Pos (16U) #define DCMIPP_P1CCRR1_RG_Msk (0x7FFUL << DCMIPP_P1CCRR1_RG_Pos) /*!< 0x07FF0000 */ #define DCMIPP_P1CCRR1_RG DCMIPP_P1CCRR1_RG_Msk /*!< Coefficient row 1 column 2 of the matrix */ /**************** Bit definition for DCMIPP_P1CCRR2 register ****************/ #define DCMIPP_P1CCRR2_RB_Pos (0U) #define DCMIPP_P1CCRR2_RB_Msk (0x7FFUL << DCMIPP_P1CCRR2_RB_Pos) /*!< 0x000007FF */ #define DCMIPP_P1CCRR2_RB DCMIPP_P1CCRR2_RB_Msk /*!< Coefficient row 1 column 3 of the matrix */ #define DCMIPP_P1CCRR2_RA_Pos (16U) #define DCMIPP_P1CCRR2_RA_Msk (0x3FFUL << DCMIPP_P1CCRR2_RA_Pos) /*!< 0x03FF0000 */ #define DCMIPP_P1CCRR2_RA DCMIPP_P1CCRR2_RA_Msk /*!< Coefficient row 1 of the added column (signed integer value) */ /**************** Bit definition for DCMIPP_P1CCGR1 register ****************/ #define DCMIPP_P1CCGR1_GR_Pos (0U) #define DCMIPP_P1CCGR1_GR_Msk (0x7FFUL << DCMIPP_P1CCGR1_GR_Pos) /*!< 0x000007FF */ #define DCMIPP_P1CCGR1_GR DCMIPP_P1CCGR1_GR_Msk /*!< Coefficient row 2 column 1 of the matrix */ #define DCMIPP_P1CCGR1_GG_Pos (16U) #define DCMIPP_P1CCGR1_GG_Msk (0x7FFUL << DCMIPP_P1CCGR1_GG_Pos) /*!< 0x07FF0000 */ #define DCMIPP_P1CCGR1_GG DCMIPP_P1CCGR1_GG_Msk /*!< Coefficient row 2 column 2 of the matrix */ /**************** Bit definition for DCMIPP_P1CCGR2 register ****************/ #define DCMIPP_P1CCGR2_GB_Pos (0U) #define DCMIPP_P1CCGR2_GB_Msk (0x7FFUL << DCMIPP_P1CCGR2_GB_Pos) /*!< 0x000007FF */ #define DCMIPP_P1CCGR2_GB DCMIPP_P1CCGR2_GB_Msk /*!< Coefficient row 2 column 3 of the matrix */ #define DCMIPP_P1CCGR2_GA_Pos (16U) #define DCMIPP_P1CCGR2_GA_Msk (0x3FFUL << DCMIPP_P1CCGR2_GA_Pos) /*!< 0x03FF0000 */ #define DCMIPP_P1CCGR2_GA DCMIPP_P1CCGR2_GA_Msk /*!< Coefficient row 2 of the added column (signed integer value) */ /**************** Bit definition for DCMIPP_P1CCBR1 register ****************/ #define DCMIPP_P1CCBR1_BR_Pos (0U) #define DCMIPP_P1CCBR1_BR_Msk (0x7FFUL << DCMIPP_P1CCBR1_BR_Pos) /*!< 0x000007FF */ #define DCMIPP_P1CCBR1_BR DCMIPP_P1CCBR1_BR_Msk /*!< Coefficient row 3 column 1 of the matrix */ #define DCMIPP_P1CCBR1_BG_Pos (16U) #define DCMIPP_P1CCBR1_BG_Msk (0x7FFUL << DCMIPP_P1CCBR1_BG_Pos) /*!< 0x07FF0000 */ #define DCMIPP_P1CCBR1_BG DCMIPP_P1CCBR1_BG_Msk /*!< Coefficient row 3 column 2 of the matrix */ /**************** Bit definition for DCMIPP_P1CCBR2 register ****************/ #define DCMIPP_P1CCBR2_BB_Pos (0U) #define DCMIPP_P1CCBR2_BB_Msk (0x7FFUL << DCMIPP_P1CCBR2_BB_Pos) /*!< 0x000007FF */ #define DCMIPP_P1CCBR2_BB DCMIPP_P1CCBR2_BB_Msk /*!< Coefficient row 3 column 3 of the matrix */ #define DCMIPP_P1CCBR2_BA_Pos (16U) #define DCMIPP_P1CCBR2_BA_Msk (0x3FFUL << DCMIPP_P1CCBR2_BA_Pos) /*!< 0x03FF0000 */ #define DCMIPP_P1CCBR2_BA DCMIPP_P1CCBR2_BA_Msk /*!< Coefficient row 3 of the added column (signed integer value) */ /**************** Bit definition for DCMIPP_P1CTCR1 register ****************/ #define DCMIPP_P1CTCR1_ENABLE_Pos (0U) #define DCMIPP_P1CTCR1_ENABLE_Msk (0x1UL << DCMIPP_P1CTCR1_ENABLE_Pos) /*!< 0x00000001 */ #define DCMIPP_P1CTCR1_ENABLE DCMIPP_P1CTCR1_ENABLE_Msk /*!< */ #define DCMIPP_P1CTCR1_LUM0_Pos (9U) #define DCMIPP_P1CTCR1_LUM0_Msk (0x3FUL << DCMIPP_P1CTCR1_LUM0_Pos) /*!< 0x00007E00 */ #define DCMIPP_P1CTCR1_LUM0 DCMIPP_P1CTCR1_LUM0_Msk /*!< Luminance increase for input luminance of 0 (increase is idle with LUMx = 16) */ /**************** Bit definition for DCMIPP_P1CTCR2 register ****************/ #define DCMIPP_P1CTCR2_LUM4_Pos (1U) #define DCMIPP_P1CTCR2_LUM4_Msk (0x3FUL << DCMIPP_P1CTCR2_LUM4_Pos) /*!< 0x0000007E */ #define DCMIPP_P1CTCR2_LUM4 DCMIPP_P1CTCR2_LUM4_Msk /*!< Luminance increase for input luminance of 128 (increase is idle with LUMx = 16) */ #define DCMIPP_P1CTCR2_LUM3_Pos (9U) #define DCMIPP_P1CTCR2_LUM3_Msk (0x3FUL << DCMIPP_P1CTCR2_LUM3_Pos) /*!< 0x00007E00 */ #define DCMIPP_P1CTCR2_LUM3 DCMIPP_P1CTCR2_LUM3_Msk /*!< Luminance increase for input luminance of 96 (increase is idle with LUMx = 16) */ #define DCMIPP_P1CTCR2_LUM2_Pos (17U) #define DCMIPP_P1CTCR2_LUM2_Msk (0x3FUL << DCMIPP_P1CTCR2_LUM2_Pos) /*!< 0x007E0000 */ #define DCMIPP_P1CTCR2_LUM2 DCMIPP_P1CTCR2_LUM2_Msk /*!< Luminance increase for input luminance of 64 (increase is idle with LUMx = 16) */ #define DCMIPP_P1CTCR2_LUM1_Pos (25U) #define DCMIPP_P1CTCR2_LUM1_Msk (0x3FUL << DCMIPP_P1CTCR2_LUM1_Pos) /*!< 0x7E000000 */ #define DCMIPP_P1CTCR2_LUM1 DCMIPP_P1CTCR2_LUM1_Msk /*!< Luminance increase for input luminance of 32 (increase is idle with LUMx = 16) */ /**************** Bit definition for DCMIPP_P1CTCR3 register ****************/ #define DCMIPP_P1CTCR3_LUM8_Pos (1U) #define DCMIPP_P1CTCR3_LUM8_Msk (0x3FUL << DCMIPP_P1CTCR3_LUM8_Pos) /*!< 0x0000007E */ #define DCMIPP_P1CTCR3_LUM8 DCMIPP_P1CTCR3_LUM8_Msk /*!< Luminance increase for input luminance of 256 (increase is idle with LUMx = 16) */ #define DCMIPP_P1CTCR3_LUM7_Pos (9U) #define DCMIPP_P1CTCR3_LUM7_Msk (0x3FUL << DCMIPP_P1CTCR3_LUM7_Pos) /*!< 0x00007E00 */ #define DCMIPP_P1CTCR3_LUM7 DCMIPP_P1CTCR3_LUM7_Msk /*!< Luminance increase for input luminance of 224 (increase is idle with LUMx = 16) */ #define DCMIPP_P1CTCR3_LUM6_Pos (17U) #define DCMIPP_P1CTCR3_LUM6_Msk (0x3FUL << DCMIPP_P1CTCR3_LUM6_Pos) /*!< 0x007E0000 */ #define DCMIPP_P1CTCR3_LUM6 DCMIPP_P1CTCR3_LUM6_Msk /*!< Luminance increase for input luminance of 192 (increase is idle with LUMx = 16) */ #define DCMIPP_P1CTCR3_LUM5_Pos (25U) #define DCMIPP_P1CTCR3_LUM5_Msk (0x3FUL << DCMIPP_P1CTCR3_LUM5_Pos) /*!< 0x7E000000 */ #define DCMIPP_P1CTCR3_LUM5 DCMIPP_P1CTCR3_LUM5_Msk /*!< Luminance increase for input luminance of 160 (increase is idle with LUMx = 16) */ /**************** Bit definition for DCMIPP_P1FCTCR register ****************/ #define DCMIPP_P1FCTCR_FRATE_Pos (0U) #define DCMIPP_P1FCTCR_FRATE_Msk (0x3UL << DCMIPP_P1FCTCR_FRATE_Pos) /*!< 0x00000003 */ #define DCMIPP_P1FCTCR_FRATE DCMIPP_P1FCTCR_FRATE_Msk /*!< Frame capture rate control */ #define DCMIPP_P1FCTCR_CPTMODE_Pos (2U) #define DCMIPP_P1FCTCR_CPTMODE_Msk (0x1UL << DCMIPP_P1FCTCR_CPTMODE_Pos) /*!< 0x00000004 */ #define DCMIPP_P1FCTCR_CPTMODE DCMIPP_P1FCTCR_CPTMODE_Msk /*!< Capture mode */ #define DCMIPP_P1FCTCR_CPTREQ_Pos (3U) #define DCMIPP_P1FCTCR_CPTREQ_Msk (0x1UL << DCMIPP_P1FCTCR_CPTREQ_Pos) /*!< 0x00000008 */ #define DCMIPP_P1FCTCR_CPTREQ DCMIPP_P1FCTCR_CPTREQ_Msk /*!< Capture requested */ /**************** Bit definition for DCMIPP_P1CRSTR register ****************/ #define DCMIPP_P1CRSTR_HSTART_Pos (0U) #define DCMIPP_P1CRSTR_HSTART_Msk (0xFFFUL << DCMIPP_P1CRSTR_HSTART_Pos) /*!< 0x00000FFF */ #define DCMIPP_P1CRSTR_HSTART DCMIPP_P1CRSTR_HSTART_Msk /*!< Horizontal start, from 0 to 4094 pixels wide */ #define DCMIPP_P1CRSTR_VSTART_Pos (16U) #define DCMIPP_P1CRSTR_VSTART_Msk (0xFFFUL << DCMIPP_P1CRSTR_VSTART_Pos) /*!< 0x0FFF0000 */ #define DCMIPP_P1CRSTR_VSTART DCMIPP_P1CRSTR_VSTART_Msk /*!< Vertical start, from 0 to 4094 pixels high */ /**************** Bit definition for DCMIPP_P1CRSZR register ****************/ #define DCMIPP_P1CRSZR_HSIZE_Pos (0U) #define DCMIPP_P1CRSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P1CRSZR_HSIZE_Pos) /*!< 0x00000FFF */ #define DCMIPP_P1CRSZR_HSIZE DCMIPP_P1CRSZR_HSIZE_Msk /*!< Horizontal size, from 0 to 4094 pixels wide */ #define DCMIPP_P1CRSZR_VSIZE_Pos (16U) #define DCMIPP_P1CRSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P1CRSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ #define DCMIPP_P1CRSZR_VSIZE DCMIPP_P1CRSZR_VSIZE_Msk /*!< Vertical size, from 0 to 4094 pixels high */ #define DCMIPP_P1CRSZR_ENABLE_Pos (31U) #define DCMIPP_P1CRSZR_ENABLE_Msk (0x1UL << DCMIPP_P1CRSZR_ENABLE_Pos) /*!< 0x80000000 */ #define DCMIPP_P1CRSZR_ENABLE DCMIPP_P1CRSZR_ENABLE_Msk /*!< */ /**************** Bit definition for DCMIPP_P1DCCR register *****************/ #define DCMIPP_P1DCCR_ENABLE_Pos (0U) #define DCMIPP_P1DCCR_ENABLE_Msk (0x1UL << DCMIPP_P1DCCR_ENABLE_Pos) /*!< 0x00000001 */ #define DCMIPP_P1DCCR_ENABLE DCMIPP_P1DCCR_ENABLE_Msk /*!< Decimation enable */ #define DCMIPP_P1DCCR_HDEC_Pos (1U) #define DCMIPP_P1DCCR_HDEC_Msk (0x3UL << DCMIPP_P1DCCR_HDEC_Pos) /*!< 0x00000006 */ #define DCMIPP_P1DCCR_HDEC DCMIPP_P1DCCR_HDEC_Msk /*!< Horizontal decimation ratio */ #define DCMIPP_P1DCCR_VDEC_Pos (3U) #define DCMIPP_P1DCCR_VDEC_Msk (0x3UL << DCMIPP_P1DCCR_VDEC_Pos) /*!< 0x00000018 */ #define DCMIPP_P1DCCR_VDEC DCMIPP_P1DCCR_VDEC_Msk /*!< Vertical decimation ratio */ /**************** Bit definition for DCMIPP_P1DSCR register *****************/ #define DCMIPP_P1DSCR_HDIV_Pos (0U) #define DCMIPP_P1DSCR_HDIV_Msk (0x3FFUL << DCMIPP_P1DSCR_HDIV_Pos) /*!< 0x000003FF */ #define DCMIPP_P1DSCR_HDIV DCMIPP_P1DSCR_HDIV_Msk /*!< Horizontal division factor, from 128 (8x) to 1023 (1x) */ #define DCMIPP_P1DSCR_VDIV_Pos (16U) #define DCMIPP_P1DSCR_VDIV_Msk (0x3FFUL << DCMIPP_P1DSCR_VDIV_Pos) /*!< 0x03FF0000 */ #define DCMIPP_P1DSCR_VDIV DCMIPP_P1DSCR_VDIV_Msk /*!< Vertical division factor, from 128 (8x) to 1023 (1x) */ #define DCMIPP_P1DSCR_ENABLE_Pos (31U) #define DCMIPP_P1DSCR_ENABLE_Msk (0x1UL << DCMIPP_P1DSCR_ENABLE_Pos) /*!< 0x80000000 */ #define DCMIPP_P1DSCR_ENABLE DCMIPP_P1DSCR_ENABLE_Msk /*!< Downscaler Enable */ /*************** Bit definition for DCMIPP_P1DSRTIOR register ***************/ #define DCMIPP_P1DSRTIOR_HRATIO_Pos (0U) #define DCMIPP_P1DSRTIOR_HRATIO_Msk (0xFFFFUL << DCMIPP_P1DSRTIOR_HRATIO_Pos) /*!< 0x0000FFFF */ #define DCMIPP_P1DSRTIOR_HRATIO DCMIPP_P1DSRTIOR_HRATIO_Msk /*!< Horizontal ratio, from 8192 (1x) to 65535 (8x) */ #define DCMIPP_P1DSRTIOR_VRATIO_Pos (16U) #define DCMIPP_P1DSRTIOR_VRATIO_Msk (0xFFFFUL << DCMIPP_P1DSRTIOR_VRATIO_Pos) /*!< 0xFFFF0000 */ #define DCMIPP_P1DSRTIOR_VRATIO DCMIPP_P1DSRTIOR_VRATIO_Msk /*!< Vertical ratio, from 8192 (1x) to 65535 (8x) */ /**************** Bit definition for DCMIPP_P1DSSZR register ****************/ #define DCMIPP_P1DSSZR_HSIZE_Pos (0U) #define DCMIPP_P1DSSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P1DSSZR_HSIZE_Pos) /*!< 0x00000FFF */ #define DCMIPP_P1DSSZR_HSIZE DCMIPP_P1DSSZR_HSIZE_Msk /*!< Horizontal size, from 0 to 4094 pixels wide */ #define DCMIPP_P1DSSZR_VSIZE_Pos (16U) #define DCMIPP_P1DSSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P1DSSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ #define DCMIPP_P1DSSZR_VSIZE DCMIPP_P1DSSZR_VSIZE_Msk /*!< Vertical size, from 0 to 4094 pixels high */ /*************** Bit definition for DCMIPP_P1CMRICR register ***************/ #define DCMIPP_P1CMRICR_ROILSZ_Pos (0U) #define DCMIPP_P1CMRICR_ROILSZ_Msk (0x3UL << DCMIPP_P1CMRICR_ROILSZ_Pos) /*!< 0x00000003 */ #define DCMIPP_P1CMRICR_ROILSZ DCMIPP_P1CMRICR_ROILSZ_Msk /*!< Region of interest line size width */ #define DCMIPP_P1CMRICR_ROI1EN_Pos (16U) #define DCMIPP_P1CMRICR_ROI1EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI1EN_Pos) /*!< 0x00010000 */ #define DCMIPP_P1CMRICR_ROI1EN DCMIPP_P1CMRICR_ROI1EN_Msk /*!< Region Of Interest 1 Enable */ #define DCMIPP_P1CMRICR_ROI2EN_Pos (17U) #define DCMIPP_P1CMRICR_ROI2EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI2EN_Pos) /*!< 0x00020000 */ #define DCMIPP_P1CMRICR_ROI2EN DCMIPP_P1CMRICR_ROI2EN_Msk /*!< Region Of Interest 2 Enable */ #define DCMIPP_P1CMRICR_ROI3EN_Pos (18U) #define DCMIPP_P1CMRICR_ROI3EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI3EN_Pos) /*!< 0x00040000 */ #define DCMIPP_P1CMRICR_ROI3EN DCMIPP_P1CMRICR_ROI3EN_Msk /*!< Region Of Interest 3 Enable */ #define DCMIPP_P1CMRICR_ROI4EN_Pos (19U) #define DCMIPP_P1CMRICR_ROI4EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI4EN_Pos) /*!< 0x00080000 */ #define DCMIPP_P1CMRICR_ROI4EN DCMIPP_P1CMRICR_ROI4EN_Msk /*!< Region Of Interest 4 Enable */ #define DCMIPP_P1CMRICR_ROI5EN_Pos (20U) #define DCMIPP_P1CMRICR_ROI5EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI5EN_Pos) /*!< 0x00100000 */ #define DCMIPP_P1CMRICR_ROI5EN DCMIPP_P1CMRICR_ROI5EN_Msk /*!< Region Of Interest 5 Enable */ #define DCMIPP_P1CMRICR_ROI6EN_Pos (21U) #define DCMIPP_P1CMRICR_ROI6EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI6EN_Pos) /*!< 0x00200000 */ #define DCMIPP_P1CMRICR_ROI6EN DCMIPP_P1CMRICR_ROI6EN_Msk /*!< Region Of Interest 6 Enable */ #define DCMIPP_P1CMRICR_ROI7EN_Pos (22U) #define DCMIPP_P1CMRICR_ROI7EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI7EN_Pos) /*!< 0x00400000 */ #define DCMIPP_P1CMRICR_ROI7EN DCMIPP_P1CMRICR_ROI7EN_Msk /*!< Region Of Interest 7 Enable */ #define DCMIPP_P1CMRICR_ROI8EN_Pos (23U) #define DCMIPP_P1CMRICR_ROI8EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI8EN_Pos) /*!< 0x00800000 */ #define DCMIPP_P1CMRICR_ROI8EN DCMIPP_P1CMRICR_ROI8EN_Msk /*!< Region Of Interest 8 Enable */ /*************** Bit definition for DCMIPP_P1RIxCR1 register ***************/ #define DCMIPP_P1RIxCR1_HSTART_Pos (0U) #define DCMIPP_P1RIxCR1_HSTART_Msk (0xFFFUL << DCMIPP_P1RIxCR1_HSTART_Pos) /*!< 0x00000FFF */ #define DCMIPP_P1RIxCR1_HSTART DCMIPP_P1RIxCR1_HSTART_Msk /*!< Horizontal start */ #define DCMIPP_P1RIxCR1_CLB_Pos (12U) #define DCMIPP_P1RIxCR1_CLB_Msk (0x3UL << DCMIPP_P1RIxCR1_CLB_Pos) /*!< 0x00003000 */ #define DCMIPP_P1RIxCR1_CLB DCMIPP_P1RIxCR1_CLB_Msk /*!< Color line blue */ #define DCMIPP_P1RIxCR1_CLG_Pos (14U) #define DCMIPP_P1RIxCR1_CLG_Msk (0x3UL << DCMIPP_P1RIxCR1_CLG_Pos) /*!< 0x0000C000 */ #define DCMIPP_P1RIxCR1_CLG DCMIPP_P1RIxCR1_CLG_Msk /*!< Color line green */ #define DCMIPP_P1RIxCR1_VSTART_Pos (16U) #define DCMIPP_P1RIxCR1_VSTART_Msk (0xFFFUL << DCMIPP_P1RIxCR1_VSTART_Pos) /*!< 0x0FFF0000 */ #define DCMIPP_P1RIxCR1_VSTART DCMIPP_P1RIxCR1_VSTART_Msk /*!< Vertical start */ #define DCMIPP_P1RIxCR1_CLR_Pos (28U) #define DCMIPP_P1RIxCR1_CLR_Msk (0x3UL << DCMIPP_P1RIxCR1_CLR_Pos) /*!< 0x30000000 */ #define DCMIPP_P1RIxCR1_CLR DCMIPP_P1RIxCR1_CLR_Msk /*!< Color line red */ /*************** Bit definition for DCMIPP_P1RIxCR2 register ***************/ #define DCMIPP_P1RIxCR2_VSIZE_Pos (0U) #define DCMIPP_P1RIxCR2_VSIZE_Msk (0xFFFUL << DCMIPP_P1RIxCR2_VSIZE_Pos) /*!< 0x00000FFF */ #define DCMIPP_P1RIxCR2_VSIZE DCMIPP_P1RIxCR2_VSIZE_Msk /*!< Vertical Size */ #define DCMIPP_P1RIxCR2_HSIZE_Pos (16U) #define DCMIPP_P1RIxCR2_HSIZE_Msk (0xFFFUL << DCMIPP_P1RIxCR2_HSIZE_Pos) /*!< 0x07FF8000 */ #define DCMIPP_P1RIxCR2_HSIZE DCMIPP_P1RIxCR2_HSIZE_Msk /*!< Horizontal Size */ /**************** Bit definition for DCMIPP_P1GMCR register *****************/ #define DCMIPP_P1GMCR_ENABLE_Pos (0U) #define DCMIPP_P1GMCR_ENABLE_Msk (0x1UL << DCMIPP_P1GMCR_ENABLE_Pos) /*!< 0x00000001 */ #define DCMIPP_P1GMCR_ENABLE DCMIPP_P1GMCR_ENABLE_Msk /*!< Gamma enable*/ /**************** Bit definition for DCMIPP_P1YUVCR register ****************/ #define DCMIPP_P1YUVCR_ENABLE_Pos (0U) #define DCMIPP_P1YUVCR_ENABLE_Msk (0x1UL << DCMIPP_P1YUVCR_ENABLE_Pos) /*!< 0x00000001 */ #define DCMIPP_P1YUVCR_ENABLE DCMIPP_P1YUVCR_ENABLE_Msk /*!< */ #define DCMIPP_P1YUVCR_TYPE_Pos (1U) #define DCMIPP_P1YUVCR_TYPE_Msk (0x1UL << DCMIPP_P1YUVCR_TYPE_Pos) /*!< 0x00000002 */ #define DCMIPP_P1YUVCR_TYPE DCMIPP_P1YUVCR_TYPE_Msk /*!< Output samples type used while CLAMP is activated */ #define DCMIPP_P1YUVCR_CLAMP_Pos (2U) #define DCMIPP_P1YUVCR_CLAMP_Msk (0x1UL << DCMIPP_P1YUVCR_CLAMP_Pos) /*!< 0x00000004 */ #define DCMIPP_P1YUVCR_CLAMP DCMIPP_P1YUVCR_CLAMP_Msk /*!< Clamp the output samples */ /*************** Bit definition for DCMIPP_P1YUVRR1 register ****************/ #define DCMIPP_P1YUVRR1_RR_Pos (0U) #define DCMIPP_P1YUVRR1_RR_Msk (0x7FFUL << DCMIPP_P1YUVRR1_RR_Pos) /*!< 0x000007FF */ #define DCMIPP_P1YUVRR1_RR DCMIPP_P1YUVRR1_RR_Msk /*!< Coefficient row 1 column 1 of the matrix */ #define DCMIPP_P1YUVRR1_RG_Pos (16U) #define DCMIPP_P1YUVRR1_RG_Msk (0x7FFUL << DCMIPP_P1YUVRR1_RG_Pos) /*!< 0x07FF0000 */ #define DCMIPP_P1YUVRR1_RG DCMIPP_P1YUVRR1_RG_Msk /*!< Coefficient row 1 column 2 of the matrix */ /*************** Bit definition for DCMIPP_P1YUVRR2 register ****************/ #define DCMIPP_P1YUVRR2_RB_Pos (0U) #define DCMIPP_P1YUVRR2_RB_Msk (0x7FFUL << DCMIPP_P1YUVRR2_RB_Pos) /*!< 0x000007FF */ #define DCMIPP_P1YUVRR2_RB DCMIPP_P1YUVRR2_RB_Msk /*!< Coefficient row 1 column 3 of the matrix */ #define DCMIPP_P1YUVRR2_RA_Pos (16U) #define DCMIPP_P1YUVRR2_RA_Msk (0x3FFUL << DCMIPP_P1YUVRR2_RA_Pos) /*!< 0x03FF0000 */ #define DCMIPP_P1YUVRR2_RA DCMIPP_P1YUVRR2_RA_Msk /*!< Coefficient row 1 of the added column (signed integer value) */ /*************** Bit definition for DCMIPP_P1YUVGR1 register ****************/ #define DCMIPP_P1YUVGR1_GR_Pos (0U) #define DCMIPP_P1YUVGR1_GR_Msk (0x7FFUL << DCMIPP_P1YUVGR1_GR_Pos) /*!< 0x000007FF */ #define DCMIPP_P1YUVGR1_GR DCMIPP_P1YUVGR1_GR_Msk /*!< Coefficient row 2 column 1 of the matrix */ #define DCMIPP_P1YUVGR1_GG_Pos (16U) #define DCMIPP_P1YUVGR1_GG_Msk (0x7FFUL << DCMIPP_P1YUVGR1_GG_Pos) /*!< 0x07FF0000 */ #define DCMIPP_P1YUVGR1_GG DCMIPP_P1YUVGR1_GG_Msk /*!< Coefficient row 2 column 2 of the matrix */ /*************** Bit definition for DCMIPP_P1YUVGR2 register ****************/ #define DCMIPP_P1YUVGR2_GB_Pos (0U) #define DCMIPP_P1YUVGR2_GB_Msk (0x7FFUL << DCMIPP_P1YUVGR2_GB_Pos) /*!< 0x000007FF */ #define DCMIPP_P1YUVGR2_GB DCMIPP_P1YUVGR2_GB_Msk /*!< Coefficient row 2 column 3 of the matrix */ #define DCMIPP_P1YUVGR2_GA_Pos (16U) #define DCMIPP_P1YUVGR2_GA_Msk (0x3FFUL << DCMIPP_P1YUVGR2_GA_Pos) /*!< 0x03FF0000 */ #define DCMIPP_P1YUVGR2_GA DCMIPP_P1YUVGR2_GA_Msk /*!< Coefficient row 2 of the added column (signed integer value) */ /*************** Bit definition for DCMIPP_P1YUVBR1 register ****************/ #define DCMIPP_P1YUVBR1_BR_Pos (0U) #define DCMIPP_P1YUVBR1_BR_Msk (0x7FFUL << DCMIPP_P1YUVBR1_BR_Pos) /*!< 0x000007FF */ #define DCMIPP_P1YUVBR1_BR DCMIPP_P1YUVBR1_BR_Msk /*!< Coefficient row 3 column 1 of the matrix */ #define DCMIPP_P1YUVBR1_BG_Pos (16U) #define DCMIPP_P1YUVBR1_BG_Msk (0x7FFUL << DCMIPP_P1YUVBR1_BG_Pos) /*!< 0x07FF0000 */ #define DCMIPP_P1YUVBR1_BG DCMIPP_P1YUVBR1_BG_Msk /*!< Coefficient row 3 column 2 of the matrix */ /*************** Bit definition for DCMIPP_P1YUVBR2 register ****************/ #define DCMIPP_P1YUVBR2_BB_Pos (0U) #define DCMIPP_P1YUVBR2_BB_Msk (0x7FFUL << DCMIPP_P1YUVBR2_BB_Pos) /*!< 0x000007FF */ #define DCMIPP_P1YUVBR2_BB DCMIPP_P1YUVBR2_BB_Msk /*!< Coefficient row 3 column 3 of the matrix */ #define DCMIPP_P1YUVBR2_BA_Pos (16U) #define DCMIPP_P1YUVBR2_BA_Msk (0x3FFUL << DCMIPP_P1YUVBR2_BA_Pos) /*!< 0x03FF0000 */ #define DCMIPP_P1YUVBR2_BA DCMIPP_P1YUVBR2_BA_Msk /*!< Coefficient row 3 of the added column (signed integer value) */ /**************** Bit definition for DCMIPP_P1PPCR register *****************/ #define DCMIPP_P1PPCR_FORMAT_Pos (0U) #define DCMIPP_P1PPCR_FORMAT_Msk (0xFUL << DCMIPP_P1PPCR_FORMAT_Pos) /*!< 0x0000000F */ #define DCMIPP_P1PPCR_FORMAT DCMIPP_P1PPCR_FORMAT_Msk /*!< Memory format */ #define DCMIPP_P1PPCR_SWAPRB_Pos (4U) #define DCMIPP_P1PPCR_SWAPRB_Msk (0x1UL << DCMIPP_P1PPCR_SWAPRB_Pos) /*!< 0x00000010 */ #define DCMIPP_P1PPCR_SWAPRB DCMIPP_P1PPCR_SWAPRB_Msk /*!< Swaps R-vs-B components if RGB, and U-vs-V components if YUV */ #define DCMIPP_P1PPCR_LINEMULT_Pos (13U) #define DCMIPP_P1PPCR_LINEMULT_Msk (0x7UL << DCMIPP_P1PPCR_LINEMULT_Pos) /*!< 0x0000E000 */ #define DCMIPP_P1PPCR_LINEMULT DCMIPP_P1PPCR_LINEMULT_Msk /*!< Amount of capture completed lines for LINE Event and Interrupt */ #define DCMIPP_P1PPCR_DBM_Pos (16U) #define DCMIPP_P1PPCR_DBM_Msk (0x1UL << DCMIPP_P1PPCR_DBM_Pos) /*!< 0x00010000 */ #define DCMIPP_P1PPCR_DBM DCMIPP_P1PPCR_DBM_Msk /*!< Double buffer mode */ #define DCMIPP_P1PPCR_LMAWM_Pos (17U) #define DCMIPP_P1PPCR_LMAWM_Msk (0x7UL << DCMIPP_P1PPCR_LMAWM_Pos) /*!< 0x000E0000 */ #define DCMIPP_P1PPCR_LMAWM DCMIPP_P1PPCR_LMAWM_Msk /*!< Line multi address wrapping modulo */ #define DCMIPP_P1PPCR_LMAWE_Pos (20U) #define DCMIPP_P1PPCR_LMAWE_Msk (0x1UL << DCMIPP_P1PPCR_LMAWE_Pos) /*!< 0x00100000 */ #define DCMIPP_P1PPCR_LMAWE DCMIPP_P1PPCR_LMAWE_Msk /*!< Line multi address wrapping enable */ /*************** Bit definition for DCMIPP_P1PPM0AR1 register ***************/ #define DCMIPP_P1PPM0AR1_M0A_Pos (0U) #define DCMIPP_P1PPM0AR1_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P1PPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */ #define DCMIPP_P1PPM0AR1_M0A DCMIPP_P1PPM0AR1_M0A_Msk /*!< Memory0 address register 1*/ /*************** Bit definition for DCMIPP_P1PPM0AR2 register ***************/ #define DCMIPP_P1PPM0AR2_M0A_Pos (0U) #define DCMIPP_P1PPM0AR2_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P1PPM0AR2_M0A_Pos) /*!< 0xFFFFFFFF */ #define DCMIPP_P1PPM0AR2_M0A DCMIPP_P1PPM0AR2_M0A_Msk /*!< Memory0 address register 2 */ /*************** Bit definition for DCMIPP_P1PPM0PR register ****************/ #define DCMIPP_P1PPM0PR_PITCH_Pos (0U) #define DCMIPP_P1PPM0PR_PITCH_Msk (0x7FFFUL << DCMIPP_P1PPM0PR_PITCH_Pos) /*!< 0x00007FFF */ #define DCMIPP_P1PPM0PR_PITCH DCMIPP_P1PPM0PR_PITCH_Msk /*!< Number of bytes between the address of two consecutive lines */ /*************** Bit definition for DCMIPP_P1PPM1AR1 register ***************/ #define DCMIPP_P1PPM1AR1_M1A_Pos (0U) #define DCMIPP_P1PPM1AR1_M1A_Msk (0xFFFFFFFFUL << DCMIPP_P1PPM1AR1_M1A_Pos) /*!< 0xFFFFFFFF */ #define DCMIPP_P1PPM1AR1_M1A DCMIPP_P1PPM1AR1_M1A_Msk /*!< Memory1 address */ /*************** Bit definition for DCMIPP_P1PPM1AR2 register ***************/ #define DCMIPP_P1PPM1AR2_M1A_Pos (0U) #define DCMIPP_P1PPM1AR2_M1A_Msk (0xFFFFFFFFUL << DCMIPP_P1PPM1AR2_M1A_Pos) /*!< 0xFFFFFFFF */ #define DCMIPP_P1PPM1AR2_M1A DCMIPP_P1PPM1AR2_M1A_Msk /*!< Memory1 address */ /*************** Bit definition for DCMIPP_P1PPM1PR register ****************/ #define DCMIPP_P1PPM1PR_PITCH_Pos (0U) #define DCMIPP_P1PPM1PR_PITCH_Msk (0x7FFFUL << DCMIPP_P1PPM1PR_PITCH_Pos) /*!< 0x00007FFF */ #define DCMIPP_P1PPM1PR_PITCH DCMIPP_P1PPM1PR_PITCH_Msk /*!< Number of bytes between the address of two consecutive lines */ /*************** Bit definition for DCMIPP_P1STM1AR register ****************/ #define DCMIPP_P1STM1AR_M1A_Pos (0U) #define DCMIPP_P1STM1AR_M1A_Msk (0x7FFFUL << DCMIPP_P1STM1AR_M1A_Pos) /*!< 0xFFFFFFFF */ #define DCMIPP_P1STM1AR_M1A DCMIPP_P1STM1AR_M1A_Msk /*!< status Memory1 address register */ /*************** Bit definition for DCMIPP_P1PPM2AR1 register ***************/ #define DCMIPP_P1PPM2AR1_M2A_Pos (0U) #define DCMIPP_P1PPM2AR1_M2A_Msk (0xFFFFFFFFUL << DCMIPP_P1PPM2AR1_M2A_Pos) /*!< 0xFFFFFFFF */ #define DCMIPP_P1PPM2AR1_M2A DCMIPP_P1PPM2AR1_M2A_Msk /*!< Memory2 address register 1*/ /*************** Bit definition for DCMIPP_P1PPM2AR2 register ***************/ #define DCMIPP_P1PPM2AR2_M2A_Pos (0U) #define DCMIPP_P1PPM2AR2_M2A_Msk (0xFFFFFFFFUL << DCMIPP_P1PPM2AR2_M2A_Pos) /*!< 0xFFFFFFFF */ #define DCMIPP_P1PPM2AR2_M2A DCMIPP_P1PPM2AR2_M2A_Msk /*!< Memory2 address register 2 */ /*************** Bit definition for DCMIPP_P1STM2AR register ****************/ #define DCMIPP_P1STM2AR_M2A_Pos (0U) #define DCMIPP_P1STM2AR_M2A_Msk (0xFFFFFFFFUL << DCMIPP_P1STM2AR_M2A_Pos) /*!< 0xFFFFFFFF */ #define DCMIPP_P1STM2AR_M2A DCMIPP_P1STM2AR_M2A_Msk /*!< status Memory2 address register */ /***************** Bit definition for DCMIPP_P1IER register *****************/ #define DCMIPP_P1IER_LINEIE_Pos (0U) #define DCMIPP_P1IER_LINEIE_Msk (0x1UL << DCMIPP_P1IER_LINEIE_Pos) /*!< 0x00000001 */ #define DCMIPP_P1IER_LINEIE DCMIPP_P1IER_LINEIE_Msk /*!< Multi-line capture completed interrupt enable */ #define DCMIPP_P1IER_FRAMEIE_Pos (1U) #define DCMIPP_P1IER_FRAMEIE_Msk (0x1UL << DCMIPP_P1IER_FRAMEIE_Pos) /*!< 0x00000002 */ #define DCMIPP_P1IER_FRAMEIE DCMIPP_P1IER_FRAMEIE_Msk /*!< Frame capture completed interrupt enable */ #define DCMIPP_P1IER_VSYNCIE_Pos (2U) #define DCMIPP_P1IER_VSYNCIE_Msk (0x1UL << DCMIPP_P1IER_VSYNCIE_Pos) /*!< 0x00000004 */ #define DCMIPP_P1IER_VSYNCIE DCMIPP_P1IER_VSYNCIE_Msk /*!< VSYNC interrupt enable */ #define DCMIPP_P1IER_OVRIE_Pos (7U) #define DCMIPP_P1IER_OVRIE_Msk (0x1UL << DCMIPP_P1IER_OVRIE_Pos) /*!< 0x00000080 */ #define DCMIPP_P1IER_OVRIE DCMIPP_P1IER_OVRIE_Msk /*!< Overrun interrupt enable */ /***************** Bit definition for DCMIPP_P1SR register ******************/ #define DCMIPP_P1SR_LINEF_Pos (0U) #define DCMIPP_P1SR_LINEF_Msk (0x1UL << DCMIPP_P1SR_LINEF_Pos) /*!< 0x00000001 */ #define DCMIPP_P1SR_LINEF DCMIPP_P1SR_LINEF_Msk /*!< Multi-line capture completed raw interrupt status */ #define DCMIPP_P1SR_FRAMEF_Pos (1U) #define DCMIPP_P1SR_FRAMEF_Msk (0x1UL << DCMIPP_P1SR_FRAMEF_Pos) /*!< 0x00000002 */ #define DCMIPP_P1SR_FRAMEF DCMIPP_P1SR_FRAMEF_Msk /*!< Frame capture completed raw interrupt status */ #define DCMIPP_P1SR_VSYNCF_Pos (2U) #define DCMIPP_P1SR_VSYNCF_Msk (0x1UL << DCMIPP_P1SR_VSYNCF_Pos) /*!< 0x00000004 */ #define DCMIPP_P1SR_VSYNCF DCMIPP_P1SR_VSYNCF_Msk /*!< VSYNC raw interrupt status */ #define DCMIPP_P1SR_OVRF_Pos (7U) #define DCMIPP_P1SR_OVRF_Msk (0x1UL << DCMIPP_P1SR_OVRF_Pos) /*!< 0x00000080 */ #define DCMIPP_P1SR_OVRF DCMIPP_P1SR_OVRF_Msk /*!< Overrun raw interrupt status */ #define DCMIPP_P1SR_LSTLINE_Pos (16U) #define DCMIPP_P1SR_LSTLINE_Msk (0x1UL << DCMIPP_P1SR_LSTLINE_Pos) /*!< 0x00010000 */ #define DCMIPP_P1SR_LSTLINE DCMIPP_P1SR_LSTLINE_Msk /*!< Last line LSB bit, sampled at frame capture complete event */ #define DCMIPP_P1SR_LSTFRM_Pos (17U) #define DCMIPP_P1SR_LSTFRM_Msk (0x1UL << DCMIPP_P1SR_LSTFRM_Pos) /*!< 0x00020000 */ #define DCMIPP_P1SR_LSTFRM DCMIPP_P1SR_LSTFRM_Msk /*!< Last frame LSB bit, sampled at frame capture complete event */ #define DCMIPP_P1SR_CPTACT_Pos (23U) #define DCMIPP_P1SR_CPTACT_Msk (0x1UL << DCMIPP_P1SR_CPTACT_Pos) /*!< 0x00800000 */ #define DCMIPP_P1SR_CPTACT DCMIPP_P1SR_CPTACT_Msk /*!< Capture immediate status */ /***************** Bit definition for DCMIPP_P1FCR register *****************/ #define DCMIPP_P1FCR_CLINEF_Pos (0U) #define DCMIPP_P1FCR_CLINEF_Msk (0x1UL << DCMIPP_P1FCR_CLINEF_Pos) /*!< 0x00000001 */ #define DCMIPP_P1FCR_CLINEF DCMIPP_P1FCR_CLINEF_Msk /*!< Multi-line capture complete interrupt status clear */ #define DCMIPP_P1FCR_CFRAMEF_Pos (1U) #define DCMIPP_P1FCR_CFRAMEF_Msk (0x1UL << DCMIPP_P1FCR_CFRAMEF_Pos) /*!< 0x00000002 */ #define DCMIPP_P1FCR_CFRAMEF DCMIPP_P1FCR_CFRAMEF_Msk /*!< Frame capture complete interrupt status clear */ #define DCMIPP_P1FCR_CVSYNCF_Pos (2U) #define DCMIPP_P1FCR_CVSYNCF_Msk (0x1UL << DCMIPP_P1FCR_CVSYNCF_Pos) /*!< 0x00000004 */ #define DCMIPP_P1FCR_CVSYNCF DCMIPP_P1FCR_CVSYNCF_Msk /*!< Vertical synchronization interrupt status clear */ #define DCMIPP_P1FCR_COVRF_Pos (7U) #define DCMIPP_P1FCR_COVRF_Msk (0x1UL << DCMIPP_P1FCR_COVRF_Pos) /*!< 0x00000080 */ #define DCMIPP_P1FCR_COVRF DCMIPP_P1FCR_COVRF_Msk /*!< Overrun interrupt status clear */ /**************** Bit definition for DCMIPP_P1CFSCR register ****************/ #define DCMIPP_P1CFSCR_DTIDA_Pos (0U) #define DCMIPP_P1CFSCR_DTIDA_Msk (0x3FUL << DCMIPP_P1CFSCR_DTIDA_Pos) /*!< 0x0000003F */ #define DCMIPP_P1CFSCR_DTIDA DCMIPP_P1CFSCR_DTIDA_Msk /*!< Current Data type ID A */ #define DCMIPP_P1CFSCR_DTIDB_Pos (8U) #define DCMIPP_P1CFSCR_DTIDB_Msk (0x3FUL << DCMIPP_P1CFSCR_DTIDB_Pos) /*!< 0x00003F00 */ #define DCMIPP_P1CFSCR_DTIDB DCMIPP_P1CFSCR_DTIDB_Msk /*!< Current Data type ID B */ #define DCMIPP_P1CFSCR_DTMODE_Pos (16U) #define DCMIPP_P1CFSCR_DTMODE_Msk (0x3UL << DCMIPP_P1CFSCR_DTMODE_Pos) /*!< 0x00030000 */ #define DCMIPP_P1CFSCR_DTMODE DCMIPP_P1CFSCR_DTMODE_Msk /*!< Flow selection mode */ #define DCMIPP_P1CFSCR_PIPEDIFF_Pos (18U) #define DCMIPP_P1CFSCR_PIPEDIFF_Msk (0x1UL << DCMIPP_P1CFSCR_PIPEDIFF_Pos) /*!< 0x00040000 */ #define DCMIPP_P1CFSCR_PIPEDIFF DCMIPP_P1CFSCR_PIPEDIFF_Msk /*!< Current differentiates Pipe2 vs */ #define DCMIPP_P1CFSCR_VC_Pos (19U) #define DCMIPP_P1CFSCR_VC_Msk (0x3UL << DCMIPP_P1CFSCR_VC_Pos) /*!< 0x00180000 */ #define DCMIPP_P1CFSCR_VC DCMIPP_P1CFSCR_VC_Msk /*!< Current flow selection mode */ #define DCMIPP_P1CFSCR_FDTF_Pos (24U) #define DCMIPP_P1CFSCR_FDTF_Msk (0x3FUL << DCMIPP_P1CFSCR_FDTF_Pos) /*!< 0x3F000000 */ #define DCMIPP_P1CFSCR_FDTF DCMIPP_P1CFSCR_FDTF_Msk /*!< Current force Data type format */ #define DCMIPP_P1CFSCR_FDTFEN_Pos (30U) #define DCMIPP_P1CFSCR_FDTFEN_Msk (0x1UL << DCMIPP_P1CFSCR_FDTFEN_Pos) /*!< 0x40000000 */ #define DCMIPP_P1CFSCR_FDTFEN DCMIPP_P1CFSCR_FDTFEN_Msk /*!< Current force Data type format enable */ #define DCMIPP_P1CFSCR_PIPEN_Pos (31U) #define DCMIPP_P1CFSCR_PIPEN_Msk (0x1UL << DCMIPP_P1CFSCR_PIPEN_Pos) /*!< 0x80000000 */ #define DCMIPP_P1CFSCR_PIPEN DCMIPP_P1CFSCR_PIPEN_Msk /*!< Current activation of PipeN */ /*************** Bit definition for DCMIPP_P1CBPRCR register ****************/ #define DCMIPP_P1CBPRCR_ENABLE_Pos (0U) #define DCMIPP_P1CBPRCR_ENABLE_Msk (0x1UL << DCMIPP_P1CBPRCR_ENABLE_Pos) /*!< 0x00000001 */ #define DCMIPP_P1CBPRCR_ENABLE DCMIPP_P1CBPRCR_ENABLE_Msk /*!< Current status of enable bit */ #define DCMIPP_P1CBPRCR_STRENGTH_Pos (1U) #define DCMIPP_P1CBPRCR_STRENGTH_Msk (0x7UL << DCMIPP_P1CBPRCR_STRENGTH_Pos) /*!< 0x0000000E */ #define DCMIPP_P1CBPRCR_STRENGTH DCMIPP_P1CBPRCR_STRENGTH_Msk /*!< Current strength (aggressivity) of the bad pixel detection: */ /*************** Bit definition for DCMIPP_P1CBLCCR register ****************/ #define DCMIPP_P1CBLCCR_ENABLE_Pos (0U) #define DCMIPP_P1CBLCCR_ENABLE_Msk (0x1UL << DCMIPP_P1CBLCCR_ENABLE_Pos) /*!< 0x00000001 */ #define DCMIPP_P1CBLCCR_ENABLE DCMIPP_P1CBLCCR_ENABLE_Msk /*!< For current black level calibration */ #define DCMIPP_P1CBLCCR_BLCB_Pos (8U) #define DCMIPP_P1CBLCCR_BLCB_Msk (0xFFUL << DCMIPP_P1CBLCCR_BLCB_Pos) /*!< 0x0000FF00 */ #define DCMIPP_P1CBLCCR_BLCB DCMIPP_P1CBLCCR_BLCB_Msk /*!< Current black level calibration - Blue */ #define DCMIPP_P1CBLCCR_BLCG_Pos (16U) #define DCMIPP_P1CBLCCR_BLCG_Msk (0xFFUL << DCMIPP_P1CBLCCR_BLCG_Pos) /*!< 0x00FF0000 */ #define DCMIPP_P1CBLCCR_BLCG DCMIPP_P1CBLCCR_BLCG_Msk /*!< Current black level calibration - Green */ #define DCMIPP_P1CBLCCR_BLCR_Pos (24U) #define DCMIPP_P1CBLCCR_BLCR_Msk (0xFFUL << DCMIPP_P1CBLCCR_BLCR_Pos) /*!< 0xFF000000 */ #define DCMIPP_P1CBLCCR_BLCR DCMIPP_P1CBLCCR_BLCR_Msk /*!< Current black level calibration - Red */ /*************** Bit definition for DCMIPP_P1CEXCR1 register ****************/ #define DCMIPP_P1CEXCR1_ENABLE_Pos (0U) #define DCMIPP_P1CEXCR1_ENABLE_Msk (0x1UL << DCMIPP_P1CEXCR1_ENABLE_Pos) /*!< 0x00000001 */ #define DCMIPP_P1CEXCR1_ENABLE DCMIPP_P1CEXCR1_ENABLE_Msk /*!< for exposure control (multiplication and shift) */ #define DCMIPP_P1CEXCR1_MULTR_Pos (20U) #define DCMIPP_P1CEXCR1_MULTR_Msk (0xFFUL << DCMIPP_P1CEXCR1_MULTR_Pos) /*!< 0x0FF00000 */ #define DCMIPP_P1CEXCR1_MULTR DCMIPP_P1CEXCR1_MULTR_Msk /*!< Current exposure multiplier - Red */ #define DCMIPP_P1CEXCR1_SHFR_Pos (28U) #define DCMIPP_P1CEXCR1_SHFR_Msk (0x7UL << DCMIPP_P1CEXCR1_SHFR_Pos) /*!< 0x70000000 */ #define DCMIPP_P1CEXCR1_SHFR DCMIPP_P1CEXCR1_SHFR_Msk /*!< Current exposure shift - Red */ /*************** Bit definition for DCMIPP_P1CEXCR2 register ****************/ #define DCMIPP_P1CEXCR2_MULTB_Pos (4U) #define DCMIPP_P1CEXCR2_MULTB_Msk (0xFFUL << DCMIPP_P1CEXCR2_MULTB_Pos) /*!< 0x00000FF0 */ #define DCMIPP_P1CEXCR2_MULTB DCMIPP_P1CEXCR2_MULTB_Msk /*!< Current exposure multiplier - Blue */ #define DCMIPP_P1CEXCR2_SHFB_Pos (12U) #define DCMIPP_P1CEXCR2_SHFB_Msk (0x7UL << DCMIPP_P1CEXCR2_SHFB_Pos) /*!< 0x00007000 */ #define DCMIPP_P1CEXCR2_SHFB DCMIPP_P1CEXCR2_SHFB_Msk /*!< Current exposure shift - Blue */ #define DCMIPP_P1CEXCR2_MULTG_Pos (20U) #define DCMIPP_P1CEXCR2_MULTG_Msk (0xFFUL << DCMIPP_P1CEXCR2_MULTG_Pos) /*!< 0x0FF00000 */ #define DCMIPP_P1CEXCR2_MULTG DCMIPP_P1CEXCR2_MULTG_Msk /*!< Current exposure multiplier - Green */ #define DCMIPP_P1CEXCR2_SHFG_Pos (28U) #define DCMIPP_P1CEXCR2_SHFG_Msk (0x7UL << DCMIPP_P1CEXCR2_SHFG_Pos) /*!< 0x70000000 */ #define DCMIPP_P1CEXCR2_SHFG DCMIPP_P1CEXCR2_SHFG_Msk /*!< Current exposure shift - Green */ /*************** Bit definition for DCMIPP_P1CST1CR register ****************/ #define DCMIPP_P1CST1CR_ENABLE_Pos (0U) #define DCMIPP_P1CST1CR_ENABLE_Msk (0x1UL << DCMIPP_P1CST1CR_ENABLE_Pos) /*!< 0x00000001 */ #define DCMIPP_P1CST1CR_ENABLE DCMIPP_P1CST1CR_ENABLE_Msk /*!< Current enable bit value */ #define DCMIPP_P1CST1CR_BINS_Pos (2U) #define DCMIPP_P1CST1CR_BINS_Msk (0x3UL << DCMIPP_P1CST1CR_BINS_Pos) /*!< 0x0000000C */ #define DCMIPP_P1CST1CR_BINS DCMIPP_P1CST1CR_BINS_Msk /*!< Current bin definition */ #define DCMIPP_P1CST1CR_SRC_Pos (4U) #define DCMIPP_P1CST1CR_SRC_Msk (0x7UL << DCMIPP_P1CST1CR_SRC_Pos) /*!< 0x00000070 */ #define DCMIPP_P1CST1CR_SRC DCMIPP_P1CST1CR_SRC_Msk /*!< Current source of statistics */ #define DCMIPP_P1CST1CR_MODE_Pos (7U) #define DCMIPP_P1CST1CR_MODE_Msk (0x1UL << DCMIPP_P1CST1CR_MODE_Pos) /*!< 0x00000080 */ #define DCMIPP_P1CST1CR_MODE DCMIPP_P1CST1CR_MODE_Msk /*!< Current statistics mode */ #define DCMIPP_P1CST1CR_ACCU_Pos (8U) #define DCMIPP_P1CST1CR_ACCU_Msk (0xFFFFFFUL << DCMIPP_P1CST1CR_ACCU_Pos) /*!< 0xFFFFFF00 */ #define DCMIPP_P1CST1CR_ACCU DCMIPP_P1CST1CR_ACCU_Msk /*!< Current accumulation result, divided by 256 */ /*************** Bit definition for DCMIPP_P1CST2CR register ****************/ #define DCMIPP_P1CST2CR_ENABLE_Pos (0U) #define DCMIPP_P1CST2CR_ENABLE_Msk (0x1UL << DCMIPP_P1CST2CR_ENABLE_Pos) /*!< 0x00000001 */ #define DCMIPP_P1CST2CR_ENABLE DCMIPP_P1CST2CR_ENABLE_Msk /*!< */ #define DCMIPP_P1CST2CR_BINS_Pos (2U) #define DCMIPP_P1CST2CR_BINS_Msk (0x3UL << DCMIPP_P1CST2CR_BINS_Pos) /*!< 0x0000000C */ #define DCMIPP_P1CST2CR_BINS DCMIPP_P1CST2CR_BINS_Msk /*!< Bin definition */ #define DCMIPP_P1CST2CR_SRC_Pos (4U) #define DCMIPP_P1CST2CR_SRC_Msk (0x7UL << DCMIPP_P1CST2CR_SRC_Pos) /*!< 0x00000070 */ #define DCMIPP_P1CST2CR_SRC DCMIPP_P1CST2CR_SRC_Msk /*!< source of stat */ #define DCMIPP_P1CST2CR_MODE_Pos (7U) #define DCMIPP_P1CST2CR_MODE_Msk (0x1UL << DCMIPP_P1CST2CR_MODE_Pos) /*!< 0x00000080 */ #define DCMIPP_P1CST2CR_MODE DCMIPP_P1CST2CR_MODE_Msk /*!< statistics mode */ #define DCMIPP_P1CST2CR_ACCU_Pos (8U) #define DCMIPP_P1CST2CR_ACCU_Msk (0xFFFFFFUL << DCMIPP_P1CST2CR_ACCU_Pos) /*!< 0xFFFFFF00 */ #define DCMIPP_P1CST2CR_ACCU DCMIPP_P1CST2CR_ACCU_Msk /*!< Accumulation result, divided by 256 */ /*************** Bit definition for DCMIPP_P1CST3CR register ****************/ #define DCMIPP_P1CST3CR_ENABLE_Pos (0U) #define DCMIPP_P1CST3CR_ENABLE_Msk (0x1UL << DCMIPP_P1CST3CR_ENABLE_Pos) /*!< 0x00000001 */ #define DCMIPP_P1CST3CR_ENABLE DCMIPP_P1CST3CR_ENABLE_Msk /*!< */ #define DCMIPP_P1CST3CR_BINS_Pos (2U) #define DCMIPP_P1CST3CR_BINS_Msk (0x3UL << DCMIPP_P1CST3CR_BINS_Pos) /*!< 0x0000000C */ #define DCMIPP_P1CST3CR_BINS DCMIPP_P1CST3CR_BINS_Msk /*!< Bin definition */ #define DCMIPP_P1CST3CR_SRC_Pos (4U) #define DCMIPP_P1CST3CR_SRC_Msk (0x7UL << DCMIPP_P1CST3CR_SRC_Pos) /*!< 0x00000070 */ #define DCMIPP_P1CST3CR_SRC DCMIPP_P1CST3CR_SRC_Msk /*!< Statistics source */ #define DCMIPP_P1CST3CR_MODE_Pos (7U) #define DCMIPP_P1CST3CR_MODE_Msk (0x1UL << DCMIPP_P1CST3CR_MODE_Pos) /*!< 0x00000080 */ #define DCMIPP_P1CST3CR_MODE DCMIPP_P1CST3CR_MODE_Msk /*!< Statistics mode */ #define DCMIPP_P1CST3CR_ACCU_Pos (8U) #define DCMIPP_P1CST3CR_ACCU_Msk (0xFFFFFFUL << DCMIPP_P1CST3CR_ACCU_Pos) /*!< 0xFFFFFF00 */ #define DCMIPP_P1CST3CR_ACCU DCMIPP_P1CST3CR_ACCU_Msk /*!< Accumulation result, divided by 256 */ /*************** Bit definition for DCMIPP_P1CSTSTR register ****************/ #define DCMIPP_P1CSTSTR_HSTART_Pos (0U) #define DCMIPP_P1CSTSTR_HSTART_Msk (0xFFFUL << DCMIPP_P1CSTSTR_HSTART_Pos) /*!< 0x00000FFF */ #define DCMIPP_P1CSTSTR_HSTART DCMIPP_P1CSTSTR_HSTART_Msk /*!< Current horizontal start, from 0 to 4094 pixels wide */ #define DCMIPP_P1CSTSTR_VSTART_Pos (16U) #define DCMIPP_P1CSTSTR_VSTART_Msk (0xFFFUL << DCMIPP_P1CSTSTR_VSTART_Pos) /*!< 0x0FFF0000 */ #define DCMIPP_P1CSTSTR_VSTART DCMIPP_P1CSTSTR_VSTART_Msk /*!< Current vertical start, from 0 to 4094 pixels high */ /*************** Bit definition for DCMIPP_P1CSTSZR register ****************/ #define DCMIPP_P1CSTSZR_HSIZE_Pos (0U) #define DCMIPP_P1CSTSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P1CSTSZR_HSIZE_Pos) /*!< 0x00000FFF */ #define DCMIPP_P1CSTSZR_HSIZE DCMIPP_P1CSTSZR_HSIZE_Msk /*!< Current horizontal size, from 0 to 4094 pixels wide */ #define DCMIPP_P1CSTSZR_VSIZE_Pos (16U) #define DCMIPP_P1CSTSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P1CSTSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ #define DCMIPP_P1CSTSZR_VSIZE DCMIPP_P1CSTSZR_VSIZE_Msk /*!< Current vertical size, from 0 to 4094 pixels high */ #define DCMIPP_P1CSTSZR_CROPEN_Pos (31U) #define DCMIPP_P1CSTSZR_CROPEN_Msk (0x1UL << DCMIPP_P1CSTSZR_CROPEN_Pos) /*!< 0x80000000 */ #define DCMIPP_P1CSTSZR_CROPEN DCMIPP_P1CSTSZR_CROPEN_Msk /*!< Current CROPEN bit value */ /**************** Bit definition for DCMIPP_P1CCCCR register ****************/ #define DCMIPP_P1CCCCR_ENABLE_Pos (0U) #define DCMIPP_P1CCCCR_ENABLE_Msk (0x1UL << DCMIPP_P1CCCCR_ENABLE_Pos) /*!< 0x00000001 */ #define DCMIPP_P1CCCCR_ENABLE DCMIPP_P1CCCCR_ENABLE_Msk /*!< This bit indicates the current value applied */ #define DCMIPP_P1CCCCR_TYPE_Pos (1U) #define DCMIPP_P1CCCCR_TYPE_Msk (0x1UL << DCMIPP_P1CCCCR_TYPE_Pos) /*!< 0x00000002 */ #define DCMIPP_P1CCCCR_TYPE DCMIPP_P1CCCCR_TYPE_Msk /*!< output samples type used while CLAMP is activated */ #define DCMIPP_P1CCCCR_CLAMP_Pos (2U) #define DCMIPP_P1CCCCR_CLAMP_Msk (0x1UL << DCMIPP_P1CCCCR_CLAMP_Pos) /*!< 0x00000004 */ #define DCMIPP_P1CCCCR_CLAMP DCMIPP_P1CCCCR_CLAMP_Msk /*!< Clamp the output samples */ /*************** Bit definition for DCMIPP_P1CCCRR1 register ****************/ #define DCMIPP_P1CCCRR1_RR_Pos (0U) #define DCMIPP_P1CCCRR1_RR_Msk (0x7FFUL << DCMIPP_P1CCCRR1_RR_Pos) /*!< 0x000007FF */ #define DCMIPP_P1CCCRR1_RR DCMIPP_P1CCCRR1_RR_Msk /*!< Current coefficient row 1 column 1 of the matrix */ #define DCMIPP_P1CCCRR1_RG_Pos (16U) #define DCMIPP_P1CCCRR1_RG_Msk (0x7FFUL << DCMIPP_P1CCCRR1_RG_Pos) /*!< 0x07FF0000 */ #define DCMIPP_P1CCCRR1_RG DCMIPP_P1CCCRR1_RG_Msk /*!< Current coefficient row 1 column 2 of the matrix */ /*************** Bit definition for DCMIPP_P1CCCRR2 register ****************/ #define DCMIPP_P1CCCRR2_RB_Pos (0U) #define DCMIPP_P1CCCRR2_RB_Msk (0x7FFUL << DCMIPP_P1CCCRR2_RB_Pos) /*!< 0x000007FF */ #define DCMIPP_P1CCCRR2_RB DCMIPP_P1CCCRR2_RB_Msk /*!< Current coefficient row 1 column 3 of the matrix */ #define DCMIPP_P1CCCRR2_RA_Pos (16U) #define DCMIPP_P1CCCRR2_RA_Msk (0x3FFUL << DCMIPP_P1CCCRR2_RA_Pos) /*!< 0x03FF0000 */ #define DCMIPP_P1CCCRR2_RA DCMIPP_P1CCCRR2_RA_Msk /*!< Current coefficient row 1 of the added column (signed integer value) */ /*************** Bit definition for DCMIPP_P1CCCGR1 register ****************/ #define DCMIPP_P1CCCGR1_GR_Pos (0U) #define DCMIPP_P1CCCGR1_GR_Msk (0x7FFUL << DCMIPP_P1CCCGR1_GR_Pos) /*!< 0x000007FF */ #define DCMIPP_P1CCCGR1_GR DCMIPP_P1CCCGR1_GR_Msk /*!< Current coefficient row 2 column 1 of the matrix */ #define DCMIPP_P1CCCGR1_GG_Pos (16U) #define DCMIPP_P1CCCGR1_GG_Msk (0x7FFUL << DCMIPP_P1CCCGR1_GG_Pos) /*!< 0x07FF0000 */ #define DCMIPP_P1CCCGR1_GG DCMIPP_P1CCCGR1_GG_Msk /*!< Current coefficient row 2 column 2 of the matrix */ /*************** Bit definition for DCMIPP_P1CCCGR2 register ****************/ #define DCMIPP_P1CCCGR2_GB_Pos (0U) #define DCMIPP_P1CCCGR2_GB_Msk (0x7FFUL << DCMIPP_P1CCCGR2_GB_Pos) /*!< 0x000007FF */ #define DCMIPP_P1CCCGR2_GB DCMIPP_P1CCCGR2_GB_Msk /*!< Current coefficient row 2 column 3 of the matrix */ #define DCMIPP_P1CCCGR2_GA_Pos (16U) #define DCMIPP_P1CCCGR2_GA_Msk (0x3FFUL << DCMIPP_P1CCCGR2_GA_Pos) /*!< 0x03FF0000 */ #define DCMIPP_P1CCCGR2_GA DCMIPP_P1CCCGR2_GA_Msk /*!< Current coefficient row 2 of the added column (signed integer value) */ /*************** Bit definition for DCMIPP_P1CCCBR1 register ****************/ #define DCMIPP_P1CCCBR1_BR_Pos (0U) #define DCMIPP_P1CCCBR1_BR_Msk (0x7FFUL << DCMIPP_P1CCCBR1_BR_Pos) /*!< 0x000007FF */ #define DCMIPP_P1CCCBR1_BR DCMIPP_P1CCCBR1_BR_Msk /*!< Current coefficient row 3 column 1 of the matrix */ #define DCMIPP_P1CCCBR1_BG_Pos (16U) #define DCMIPP_P1CCCBR1_BG_Msk (0x7FFUL << DCMIPP_P1CCCBR1_BG_Pos) /*!< 0x07FF0000 */ #define DCMIPP_P1CCCBR1_BG DCMIPP_P1CCCBR1_BG_Msk /*!< Current coefficient row 3 column 2 of the matrix */ /*************** Bit definition for DCMIPP_P1CCCBR2 register ****************/ #define DCMIPP_P1CCCBR2_BB_Pos (0U) #define DCMIPP_P1CCCBR2_BB_Msk (0x7FFUL << DCMIPP_P1CCCBR2_BB_Pos) /*!< 0x000007FF */ #define DCMIPP_P1CCCBR2_BB DCMIPP_P1CCCBR2_BB_Msk /*!< Current coefficient row 3 column 3 of the matrix */ #define DCMIPP_P1CCCBR2_BA_Pos (16U) #define DCMIPP_P1CCCBR2_BA_Msk (0x3FFUL << DCMIPP_P1CCCBR2_BA_Pos) /*!< 0x03FF0000 */ #define DCMIPP_P1CCCBR2_BA DCMIPP_P1CCCBR2_BA_Msk /*!< Current coefficient row 3 of the added column (signed integer value) */ /*************** Bit definition for DCMIPP_P1CCTCR1 register ****************/ #define DCMIPP_P1CCTCR1_ENABLE_Pos (0U) #define DCMIPP_P1CCTCR1_ENABLE_Msk (0x1UL << DCMIPP_P1CCTCR1_ENABLE_Pos) /*!< 0x00000001 */ #define DCMIPP_P1CCTCR1_ENABLE DCMIPP_P1CCTCR1_ENABLE_Msk /*!< Current ENABLE bit value */ #define DCMIPP_P1CCTCR1_LUM0_Pos (9U) #define DCMIPP_P1CCTCR1_LUM0_Msk (0x3FUL << DCMIPP_P1CCTCR1_LUM0_Pos) /*!< 0x00007E00 */ #define DCMIPP_P1CCTCR1_LUM0 DCMIPP_P1CCTCR1_LUM0_Msk /*!< Current luminance increase for input luminance of 0 (increase is idle with LUMx = 16) */ /*************** Bit definition for DCMIPP_P1CCTCR2 register ****************/ #define DCMIPP_P1CCTCR2_LUM4_Pos (1U) #define DCMIPP_P1CCTCR2_LUM4_Msk (0x3FUL << DCMIPP_P1CCTCR2_LUM4_Pos) /*!< 0x0000007E */ #define DCMIPP_P1CCTCR2_LUM4 DCMIPP_P1CCTCR2_LUM4_Msk /*!< Current luminance increase for input luminance of 128 (increase is idle with LUMx = 16) */ #define DCMIPP_P1CCTCR2_LUM3_Pos (9U) #define DCMIPP_P1CCTCR2_LUM3_Msk (0x3FUL << DCMIPP_P1CCTCR2_LUM3_Pos) /*!< 0x00007E00 */ #define DCMIPP_P1CCTCR2_LUM3 DCMIPP_P1CCTCR2_LUM3_Msk /*!< Current luminance increase for input luminance of 96 (increase is idle with LUMx = 16) */ #define DCMIPP_P1CCTCR2_LUM2_Pos (17U) #define DCMIPP_P1CCTCR2_LUM2_Msk (0x3FUL << DCMIPP_P1CCTCR2_LUM2_Pos) /*!< 0x007E0000 */ #define DCMIPP_P1CCTCR2_LUM2 DCMIPP_P1CCTCR2_LUM2_Msk /*!< Current luminance increase for input luminance of 64 (increase is idle with LUMx = 16) */ #define DCMIPP_P1CCTCR2_LUM1_Pos (25U) #define DCMIPP_P1CCTCR2_LUM1_Msk (0x3FUL << DCMIPP_P1CCTCR2_LUM1_Pos) /*!< 0x7E000000 */ #define DCMIPP_P1CCTCR2_LUM1 DCMIPP_P1CCTCR2_LUM1_Msk /*!< Current luminance increase for input luminance of 32 (increase is idle with LUMx = 16) */ /*************** Bit definition for DCMIPP_P1CCTCR3 register ****************/ #define DCMIPP_P1CCTCR3_LUM8_Pos (1U) #define DCMIPP_P1CCTCR3_LUM8_Msk (0x3FUL << DCMIPP_P1CCTCR3_LUM8_Pos) /*!< 0x0000007E */ #define DCMIPP_P1CCTCR3_LUM8 DCMIPP_P1CCTCR3_LUM8_Msk /*!< Luminance increase for input luminance of 256 (increase is idle with LUMx = 16) */ #define DCMIPP_P1CCTCR3_LUM7_Pos (9U) #define DCMIPP_P1CCTCR3_LUM7_Msk (0x3FUL << DCMIPP_P1CCTCR3_LUM7_Pos) /*!< 0x00007E00 */ #define DCMIPP_P1CCTCR3_LUM7 DCMIPP_P1CCTCR3_LUM7_Msk /*!< Luminance increase for input luminance of 224 (increase is idle with LUMx = 16) */ #define DCMIPP_P1CCTCR3_LUM6_Pos (17U) #define DCMIPP_P1CCTCR3_LUM6_Msk (0x3FUL << DCMIPP_P1CCTCR3_LUM6_Pos) /*!< 0x007E0000 */ #define DCMIPP_P1CCTCR3_LUM6 DCMIPP_P1CCTCR3_LUM6_Msk /*!< Luminance increase for input luminance of 192 (increase is idle with LUMx = 16) */ #define DCMIPP_P1CCTCR3_LUM5_Pos (25U) #define DCMIPP_P1CCTCR3_LUM5_Msk (0x3FUL << DCMIPP_P1CCTCR3_LUM5_Pos) /*!< 0x7E000000 */ #define DCMIPP_P1CCTCR3_LUM5 DCMIPP_P1CCTCR3_LUM5_Msk /*!< Luminance increase for input luminance of 160 (increase is idle with LUMx = 16) */ /*************** Bit definition for DCMIPP_P1CFCTCR register ****************/ #define DCMIPP_P1CFCTCR_FRATE_Pos (0U) #define DCMIPP_P1CFCTCR_FRATE_Msk (0x3UL << DCMIPP_P1CFCTCR_FRATE_Pos) /*!< 0x00000003 */ #define DCMIPP_P1CFCTCR_FRATE DCMIPP_P1CFCTCR_FRATE_Msk /*!< Frame capture rate control */ #define DCMIPP_P1CFCTCR_CPTMODE_Pos (2U) #define DCMIPP_P1CFCTCR_CPTMODE_Msk (0x1UL << DCMIPP_P1CFCTCR_CPTMODE_Pos) /*!< 0x00000004 */ #define DCMIPP_P1CFCTCR_CPTMODE DCMIPP_P1CFCTCR_CPTMODE_Msk /*!< Capture mode */ #define DCMIPP_P1CFCTCR_CPTREQ_Pos (3U) #define DCMIPP_P1CFCTCR_CPTREQ_Msk (0x1UL << DCMIPP_P1CFCTCR_CPTREQ_Pos) /*!< 0x00000008 */ #define DCMIPP_P1CFCTCR_CPTREQ DCMIPP_P1CFCTCR_CPTREQ_Msk /*!< Capture requested */ /*************** Bit definition for DCMIPP_P1CCRSTR register ****************/ #define DCMIPP_P1CCRSTR_HSTART_Pos (0U) #define DCMIPP_P1CCRSTR_HSTART_Msk (0xFFFUL << DCMIPP_P1CCRSTR_HSTART_Pos) /*!< 0x00000FFF */ #define DCMIPP_P1CCRSTR_HSTART DCMIPP_P1CCRSTR_HSTART_Msk /*!< Current horizontal start, from 0 to 4094 pixels wide */ #define DCMIPP_P1CCRSTR_VSTART_Pos (16U) #define DCMIPP_P1CCRSTR_VSTART_Msk (0xFFFUL << DCMIPP_P1CCRSTR_VSTART_Pos) /*!< 0x0FFF0000 */ #define DCMIPP_P1CCRSTR_VSTART DCMIPP_P1CCRSTR_VSTART_Msk /*!< Current vertical start, from 0 to 4094 pixels high */ /*************** Bit definition for DCMIPP_P1CCRSZR register ****************/ #define DCMIPP_P1CCRSZR_HSIZE_Pos (0U) #define DCMIPP_P1CCRSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P1CCRSZR_HSIZE_Pos) /*!< 0x00000FFF */ #define DCMIPP_P1CCRSZR_HSIZE DCMIPP_P1CCRSZR_HSIZE_Msk /*!< Current horizontal size, from 0 to 4094 pixels wide */ #define DCMIPP_P1CCRSZR_VSIZE_Pos (16U) #define DCMIPP_P1CCRSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P1CCRSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ #define DCMIPP_P1CCRSZR_VSIZE DCMIPP_P1CCRSZR_VSIZE_Msk /*!< Current vertical size, from 0 to 4094 pixels high */ #define DCMIPP_P1CCRSZR_ENABLE_Pos (31U) #define DCMIPP_P1CCRSZR_ENABLE_Msk (0x1UL << DCMIPP_P1CCRSZR_ENABLE_Pos) /*!< 0x80000000 */ #define DCMIPP_P1CCRSZR_ENABLE DCMIPP_P1CCRSZR_ENABLE_Msk /*!< Current ENABLE bit value */ /**************** Bit definition for DCMIPP_P1CDCCR register *****************/ #define DCMIPP_P1CDCCR_ENABLE_Pos (0U) #define DCMIPP_P1CDCCR_ENABLE_Msk (0x1UL << DCMIPP_P1CDCCR_ENABLE_Pos) /*!< 0x00000001 */ #define DCMIPP_P1CDCCR_ENABLE DCMIPP_P1CDCCR_ENABLE_Msk /*!< Decimation enable */ #define DCMIPP_P1CDCCR_HDEC_Pos (1U) #define DCMIPP_P1CDCCR_HDEC_Msk (0x3UL << DCMIPP_P1CDCCR_HDEC_Pos) /*!< 0x00000006 */ #define DCMIPP_P1CDCCR_HDEC DCMIPP_P1CDCCR_HDEC_Msk /*!< Horizontal decimation ratio */ #define DCMIPP_P1CDCCR_VDEC_Pos (3U) #define DCMIPP_P1CDCCR_VDEC_Msk (0x3UL << DCMIPP_P1CDCCR_VDEC_Pos) /*!< 0x00000018 */ #define DCMIPP_P1CDCCR_VDEC DCMIPP_P1CDCCR_VDEC_Msk /*!< Vertical decimation ratio */ /**************** Bit definition for DCMIPP_P1CDSCR register ****************/ #define DCMIPP_P1CDSCR_HDIV_Pos (0U) #define DCMIPP_P1CDSCR_HDIV_Msk (0x3FFUL << DCMIPP_P1CDSCR_HDIV_Pos) /*!< 0x000003FF */ #define DCMIPP_P1CDSCR_HDIV DCMIPP_P1CDSCR_HDIV_Msk /*!< Current horizontal division factor, from 128 (8x) to 1023 (1x) */ #define DCMIPP_P1CDSCR_VDIV_Pos (16U) #define DCMIPP_P1CDSCR_VDIV_Msk (0x3FFUL << DCMIPP_P1CDSCR_VDIV_Pos) /*!< 0x03FF0000 */ #define DCMIPP_P1CDSCR_VDIV DCMIPP_P1CDSCR_VDIV_Msk /*!< Current vertical division factor, from 128 (8x) to 1023 (1x) */ #define DCMIPP_P1CDSCR_ENABLE_Pos (31U) #define DCMIPP_P1CDSCR_ENABLE_Msk (0x1UL << DCMIPP_P1CDSCR_ENABLE_Pos) /*!< 0x80000000 */ #define DCMIPP_P1CDSCR_ENABLE DCMIPP_P1CDSCR_ENABLE_Msk /*!< Current value of the bit ENABLE */ /************** Bit definition for DCMIPP_P1CDSRTIOR register ***************/ #define DCMIPP_P1CDSRTIOR_HRATIO_Pos (0U) #define DCMIPP_P1CDSRTIOR_HRATIO_Msk (0xFFFFUL << DCMIPP_P1CDSRTIOR_HRATIO_Pos) /*!< 0x0000FFFF */ #define DCMIPP_P1CDSRTIOR_HRATIO DCMIPP_P1CDSRTIOR_HRATIO_Msk /*!< Current horizontal ratio, from 8192 (1x) to 65535 (8x) */ #define DCMIPP_P1CDSRTIOR_VRATIO_Pos (16U) #define DCMIPP_P1CDSRTIOR_VRATIO_Msk (0xFFFFUL << DCMIPP_P1CDSRTIOR_VRATIO_Pos) /*!< 0xFFFF0000 */ #define DCMIPP_P1CDSRTIOR_VRATIO DCMIPP_P1CDSRTIOR_VRATIO_Msk /*!< Current vertical ratio, from 8192 (1x) to 65535 (8x) */ /*************** Bit definition for DCMIPP_P1CDSSZR register ****************/ #define DCMIPP_P1CDSSZR_HSIZE_Pos (0U) #define DCMIPP_P1CDSSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P1CDSSZR_HSIZE_Pos) /*!< 0x00000FFF */ #define DCMIPP_P1CDSSZR_HSIZE DCMIPP_P1CDSSZR_HSIZE_Msk /*!< Current horizontal size, from 0 to 4094 pixels wide */ #define DCMIPP_P1CDSSZR_VSIZE_Pos (16U) #define DCMIPP_P1CDSSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P1CDSSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ #define DCMIPP_P1CDSSZR_VSIZE DCMIPP_P1CDSSZR_VSIZE_Msk /*!< Current vertical size, from 0 to 4094 pixels high */ /**************** Bit definition for DCMIPP_P1CPPCR register ****************/ #define DCMIPP_P1CPPCR_FORMAT_Pos (0U) #define DCMIPP_P1CPPCR_FORMAT_Msk (0xFUL << DCMIPP_P1CPPCR_FORMAT_Pos) /*!< 0x0000000F */ #define DCMIPP_P1CPPCR_FORMAT DCMIPP_P1CPPCR_FORMAT_Msk /*!< Memory format */ #define DCMIPP_P1CPPCR_SWAPRB_Pos (4U) #define DCMIPP_P1CPPCR_SWAPRB_Msk (0x1UL << DCMIPP_P1CPPCR_SWAPRB_Pos) /*!< 0x00000010 */ #define DCMIPP_P1CPPCR_SWAPRB DCMIPP_P1CPPCR_SWAPRB_Msk /*!< Swaps R-vs-B components if RGB, and U-vs-V components if YUV */ #define DCMIPP_P1CPPCR_LINEMULT_Pos (13U) #define DCMIPP_P1CPPCR_LINEMULT_Msk (0x7UL << DCMIPP_P1CPPCR_LINEMULT_Pos) /*!< 0x0000E000 */ #define DCMIPP_P1CPPCR_LINEMULT DCMIPP_P1CPPCR_LINEMULT_Msk /*!< Amount of capture completed lines for LINE Event and Interrupt */ /************** Bit definition for DCMIPP_P1CPPM0AR1 register ***************/ #define DCMIPP_P1CPPM0AR1_M0A_Pos (0U) #define DCMIPP_P1CPPM0AR1_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P1CPPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */ #define DCMIPP_P1CPPM0AR1_M0A DCMIPP_P1CPPM0AR1_M0A_Msk /*!< Memory0 address */ /*************** Bit definition for DCMIPP_P1CPPM0PR register ***************/ #define DCMIPP_P1CPPM0PR_PITCH_Pos (0U) #define DCMIPP_P1CPPM0PR_PITCH_Msk (0x7FFFUL << DCMIPP_P1CPPM0PR_PITCH_Pos) /*!< 0x00007FFF */ #define DCMIPP_P1CPPM0PR_PITCH DCMIPP_P1CPPM0PR_PITCH_Msk /*!< Number of bytes between the address of two consecutive lines */ /************** Bit definition for DCMIPP_P1CPPM1AR1 register ***************/ #define DCMIPP_P1CPPM1AR1_M1A_Pos (0U) #define DCMIPP_P1CPPM1AR1_M1A_Msk (0xFFFFFFFFUL << DCMIPP_P1CPPM1AR1_M1A_Pos) /*!< 0xFFFFFFFF */ #define DCMIPP_P1CPPM1AR1_M1A DCMIPP_P1CPPM1AR1_M1A_Msk /*!< Memory1 address */ /*************** Bit definition for DCMIPP_P1CPPM1PR register ***************/ #define DCMIPP_P1CPPM1PR_PITCH_Pos (0U) #define DCMIPP_P1CPPM1PR_PITCH_Msk (0x7FFFUL << DCMIPP_P1CPPM1PR_PITCH_Pos) /*!< 0x00007FFF */ #define DCMIPP_P1CPPM1PR_PITCH DCMIPP_P1CPPM1PR_PITCH_Msk /*!< Number of bytes between the address of two consecutive lines */ /************** Bit definition for DCMIPP_P1CPPM2AR1 register ***************/ #define DCMIPP_P1CPPM2AR1_M2A_Pos (0U) #define DCMIPP_P1CPPM2AR1_M2A_Msk (0xFFFFFFFFUL << DCMIPP_P1CPPM2AR1_M2A_Pos) /*!< 0xFFFFFFFF */ #define DCMIPP_P1CPPM2AR1_M2A DCMIPP_P1CPPM2AR1_M2A_Msk /*!< Memory 2 address */ /**************** Bit definition for DCMIPP_P2FSCR register *****************/ #define DCMIPP_P2FSCR_DTIDA_Pos (0U) #define DCMIPP_P2FSCR_DTIDA_Msk (0x3FUL << DCMIPP_P2FSCR_DTIDA_Pos) /*!< 0x0000003F */ #define DCMIPP_P2FSCR_DTIDA DCMIPP_P2FSCR_DTIDA_Msk /*!< Data type ID */ #define DCMIPP_P2FSCR_VC_Pos (19U) #define DCMIPP_P2FSCR_VC_Msk (0x3UL << DCMIPP_P2FSCR_VC_Pos) /*!< 0x00180000 */ #define DCMIPP_P2FSCR_VC DCMIPP_P2FSCR_VC_Msk /*!< Flow selection mode */ #define DCMIPP_P2FSCR_FDTF_Pos (24U) #define DCMIPP_P2FSCR_FDTF_Msk (0x3FUL << DCMIPP_P2FSCR_FDTF_Pos) /*!< 0x3F000000 */ #define DCMIPP_P2FSCR_FDTF DCMIPP_P2FSCR_FDTF_Msk /*!< Force Data type format */ #define DCMIPP_P2FSCR_FDTFEN_Pos (30U) #define DCMIPP_P2FSCR_FDTFEN_Msk (0x1UL << DCMIPP_P2FSCR_FDTFEN_Pos) /*!< 0x40000000 */ #define DCMIPP_P2FSCR_FDTFEN DCMIPP_P2FSCR_FDTFEN_Msk /*!< Force Data type format enable */ #define DCMIPP_P2FSCR_PIPEN_Pos (31U) #define DCMIPP_P2FSCR_PIPEN_Msk (0x1UL << DCMIPP_P2FSCR_PIPEN_Pos) /*!< 0x80000000 */ #define DCMIPP_P2FSCR_PIPEN DCMIPP_P2FSCR_PIPEN_Msk /*!< Activation of PipeN */ /**************** Bit definition for DCMIPP_P2FCTCR register ****************/ #define DCMIPP_P2FCTCR_FRATE_Pos (0U) #define DCMIPP_P2FCTCR_FRATE_Msk (0x3UL << DCMIPP_P2FCTCR_FRATE_Pos) /*!< 0x00000003 */ #define DCMIPP_P2FCTCR_FRATE DCMIPP_P2FCTCR_FRATE_Msk /*!< Frame capture rate control */ #define DCMIPP_P2FCTCR_CPTMODE_Pos (2U) #define DCMIPP_P2FCTCR_CPTMODE_Msk (0x1UL << DCMIPP_P2FCTCR_CPTMODE_Pos) /*!< 0x00000004 */ #define DCMIPP_P2FCTCR_CPTMODE DCMIPP_P2FCTCR_CPTMODE_Msk /*!< Capture mode */ #define DCMIPP_P2FCTCR_CPTREQ_Pos (3U) #define DCMIPP_P2FCTCR_CPTREQ_Msk (0x1UL << DCMIPP_P2FCTCR_CPTREQ_Pos) /*!< 0x00000008 */ #define DCMIPP_P2FCTCR_CPTREQ DCMIPP_P2FCTCR_CPTREQ_Msk /*!< Capture requested */ /**************** Bit definition for DCMIPP_P2CRSTR register ****************/ #define DCMIPP_P2CRSTR_HSTART_Pos (0U) #define DCMIPP_P2CRSTR_HSTART_Msk (0xFFFUL << DCMIPP_P2CRSTR_HSTART_Pos) /*!< 0x00000FFF */ #define DCMIPP_P2CRSTR_HSTART DCMIPP_P2CRSTR_HSTART_Msk /*!< Horizontal start, from 0 to 4094 pixels wide */ #define DCMIPP_P2CRSTR_VSTART_Pos (16U) #define DCMIPP_P2CRSTR_VSTART_Msk (0xFFFUL << DCMIPP_P2CRSTR_VSTART_Pos) /*!< 0x0FFF0000 */ #define DCMIPP_P2CRSTR_VSTART DCMIPP_P2CRSTR_VSTART_Msk /*!< Vertical start, from 0 to 4094 pixels high */ /**************** Bit definition for DCMIPP_P2CRSZR register ****************/ #define DCMIPP_P2CRSZR_HSIZE_Pos (0U) #define DCMIPP_P2CRSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P2CRSZR_HSIZE_Pos) /*!< 0x00000FFF */ #define DCMIPP_P2CRSZR_HSIZE DCMIPP_P2CRSZR_HSIZE_Msk /*!< Horizontal size, from 0 to 4094 pixels wide */ #define DCMIPP_P2CRSZR_VSIZE_Pos (16U) #define DCMIPP_P2CRSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P2CRSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ #define DCMIPP_P2CRSZR_VSIZE DCMIPP_P2CRSZR_VSIZE_Msk /*!< Vertical size, from 0 to 4094 pixels high */ #define DCMIPP_P2CRSZR_ENABLE_Pos (31U) #define DCMIPP_P2CRSZR_ENABLE_Msk (0x1UL << DCMIPP_P2CRSZR_ENABLE_Pos) /*!< 0x80000000 */ #define DCMIPP_P2CRSZR_ENABLE DCMIPP_P2CRSZR_ENABLE_Msk /*!< */ /**************** Bit definition for DCMIPP_P2DCCR register *****************/ #define DCMIPP_P2DCCR_ENABLE_Pos (0U) #define DCMIPP_P2DCCR_ENABLE_Msk (0x1UL << DCMIPP_P2DCCR_ENABLE_Pos) /*!< 0x00000001 */ #define DCMIPP_P2DCCR_ENABLE DCMIPP_P2DCCR_ENABLE_Msk /*!< Decimation enable */ #define DCMIPP_P2DCCR_HDEC_Pos (1U) #define DCMIPP_P2DCCR_HDEC_Msk (0x3UL << DCMIPP_P2DCCR_HDEC_Pos) /*!< 0x00000006 */ #define DCMIPP_P2DCCR_HDEC DCMIPP_P2DCCR_HDEC_Msk /*!< Horizontal decimation ratio */ #define DCMIPP_P2DCCR_VDEC_Pos (3U) #define DCMIPP_P2DCCR_VDEC_Msk (0x3UL << DCMIPP_P2DCCR_VDEC_Pos) /*!< 0x00000018 */ #define DCMIPP_P2DCCR_VDEC DCMIPP_P2DCCR_VDEC_Msk /*!< Vertical decimation ratio */ /**************** Bit definition for DCMIPP_P2DSCR register *****************/ #define DCMIPP_P2DSCR_HDIV_Pos (0U) #define DCMIPP_P2DSCR_HDIV_Msk (0x3FFUL << DCMIPP_P2DSCR_HDIV_Pos) /*!< 0x000003FF */ #define DCMIPP_P2DSCR_HDIV DCMIPP_P2DSCR_HDIV_Msk /*!< Horizontal division factor, from 128 (8x) to 1023 (1x) */ #define DCMIPP_P2DSCR_VDIV_Pos (16U) #define DCMIPP_P2DSCR_VDIV_Msk (0x3FFUL << DCMIPP_P2DSCR_VDIV_Pos) /*!< 0x03FF0000 */ #define DCMIPP_P2DSCR_VDIV DCMIPP_P2DSCR_VDIV_Msk /*!< Vertical division factor, from 128 (8x) to 1023 (1x) */ #define DCMIPP_P2DSCR_ENABLE_Pos (31U) #define DCMIPP_P2DSCR_ENABLE_Msk (0x1UL << DCMIPP_P2DSCR_ENABLE_Pos) /*!< 0x80000000 */ #define DCMIPP_P2DSCR_ENABLE DCMIPP_P2DSCR_ENABLE_Msk /*!< */ /*************** Bit definition for DCMIPP_P2DSRTIOR register ***************/ #define DCMIPP_P2DSRTIOR_HRATIO_Pos (0U) #define DCMIPP_P2DSRTIOR_HRATIO_Msk (0xFFFFUL << DCMIPP_P2DSRTIOR_HRATIO_Pos) /*!< 0x0000FFFF */ #define DCMIPP_P2DSRTIOR_HRATIO DCMIPP_P2DSRTIOR_HRATIO_Msk /*!< Horizontal ratio, from 8192 (1x) to 65535 (8x) */ #define DCMIPP_P2DSRTIOR_VRATIO_Pos (16U) #define DCMIPP_P2DSRTIOR_VRATIO_Msk (0xFFFFUL << DCMIPP_P2DSRTIOR_VRATIO_Pos) /*!< 0xFFFF0000 */ #define DCMIPP_P2DSRTIOR_VRATIO DCMIPP_P2DSRTIOR_VRATIO_Msk /*!< Vertical ratio, from 8192 (1x) to 65535 (8x) */ /**************** Bit definition for DCMIPP_P2DSSZR register ****************/ #define DCMIPP_P2DSSZR_HSIZE_Pos (0U) #define DCMIPP_P2DSSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P2DSSZR_HSIZE_Pos) /*!< 0x00000FFF */ #define DCMIPP_P2DSSZR_HSIZE DCMIPP_P2DSSZR_HSIZE_Msk /*!< Horizontal size, from 0 to 4094 pixels wide */ #define DCMIPP_P2DSSZR_VSIZE_Pos (16U) #define DCMIPP_P2DSSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P2DSSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ #define DCMIPP_P2DSSZR_VSIZE DCMIPP_P2DSSZR_VSIZE_Msk /*!< Vertical size, from 0 to 4094 pixels high */ /**************** Bit definition for DCMIPP_P2GMCR register *****************/ #define DCMIPP_P2GMCR_ENABLE_Pos (0U) #define DCMIPP_P2GMCR_ENABLE_Msk (0x1UL << DCMIPP_P2GMCR_ENABLE_Pos) /*!< 0x00000001 */ #define DCMIPP_P2GMCR_ENABLE DCMIPP_P2GMCR_ENABLE_Msk /*!< */ /*************** Bit definition for DCMIPP_P2CMRICR register ***************/ #define DCMIPP_P2CMRICR_ROILSZ_Pos (0U) #define DCMIPP_P2CMRICR_ROILSZ_Msk (0x3UL << DCMIPP_P2CMRICR_ROILSZ_Pos) /*!< 0x00000003 */ #define DCMIPP_P2CMRICR_ROILSZ DCMIPP_P2CMRICR_ROILSZ_Msk /*!< Region of interest line size width */ #define DCMIPP_P2CMRICR_ROI1EN_Pos (16U) #define DCMIPP_P2CMRICR_ROI1EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI1EN_Pos) /*!< 0x00010000 */ #define DCMIPP_P2CMRICR_ROI1EN DCMIPP_P2CMRICR_ROI1EN_Msk /*!< Region Of Interest 1 Enable */ #define DCMIPP_P2CMRICR_ROI2EN_Pos (17U) #define DCMIPP_P2CMRICR_ROI2EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI2EN_Pos) /*!< 0x00020000 */ #define DCMIPP_P2CMRICR_ROI2EN DCMIPP_P2CMRICR_ROI2EN_Msk /*!< Region Of Interest 2 Enable */ #define DCMIPP_P2CMRICR_ROI3EN_Pos (18U) #define DCMIPP_P2CMRICR_ROI3EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI3EN_Pos) /*!< 0x00040000 */ #define DCMIPP_P2CMRICR_ROI3EN DCMIPP_P2CMRICR_ROI3EN_Msk /*!< Region Of Interest 3 Enable */ #define DCMIPP_P2CMRICR_ROI4EN_Pos (19U) #define DCMIPP_P2CMRICR_ROI4EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI4EN_Pos) /*!< 0x00080000 */ #define DCMIPP_P2CMRICR_ROI4EN DCMIPP_P2CMRICR_ROI4EN_Msk /*!< Region Of Interest 4 Enable */ #define DCMIPP_P2CMRICR_ROI5EN_Pos (20U) #define DCMIPP_P2CMRICR_ROI5EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI5EN_Pos) /*!< 0x00100000 */ #define DCMIPP_P2CMRICR_ROI5EN DCMIPP_P2CMRICR_ROI5EN_Msk /*!< Region Of Interest 5 Enable */ #define DCMIPP_P2CMRICR_ROI6EN_Pos (21U) #define DCMIPP_P2CMRICR_ROI6EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI6EN_Pos) /*!< 0x00200000 */ #define DCMIPP_P2CMRICR_ROI6EN DCMIPP_P2CMRICR_ROI6EN_Msk /*!< Region Of Interest 6 Enable */ #define DCMIPP_P2CMRICR_ROI7EN_Pos (22U) #define DCMIPP_P2CMRICR_ROI7EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI7EN_Pos) /*!< 0x00400000 */ #define DCMIPP_P2CMRICR_ROI7EN DCMIPP_P2CMRICR_ROI7EN_Msk /*!< Region Of Interest 7 Enable */ #define DCMIPP_P2CMRICR_ROI8EN_Pos (23U) #define DCMIPP_P2CMRICR_ROI8EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI8EN_Pos) /*!< 0x00800000 */ #define DCMIPP_P2CMRICR_ROI8EN DCMIPP_P2CMRICR_ROI8EN_Msk /*!< Region Of Interest 8 Enable */ /*************** Bit definition for DCMIPP_P2RIxCR1 register ***************/ #define DCMIPP_P2RIxCR1_HSTART_Pos (0U) #define DCMIPP_P2RIxCR1_HSTART_Msk (0xFFFUL << DCMIPP_P2RIxCR1_HSTART_Pos) /*!< 0x00000FFF */ #define DCMIPP_P2RIxCR1_HSTART DCMIPP_P2RIxCR1_HSTART_Msk /*!< Horizontal start */ #define DCMIPP_P2RIxCR1_CLB_Pos (12U) #define DCMIPP_P2RIxCR1_CLB_Msk (0x3UL << DCMIPP_P2RIxCR1_CLB_Pos) /*!< 0x00003000 */ #define DCMIPP_P2RIxCR1_CLB DCMIPP_P2RIxCR1_CLB_Msk /*!< Color line blue */ #define DCMIPP_P2RIxCR1_CLG_Pos (14U) #define DCMIPP_P2RIxCR1_CLG_Msk (0x3UL << DCMIPP_P2RIxCR1_CLG_Pos) /*!< 0x0000C000 */ #define DCMIPP_P2RIxCR1_CLG DCMIPP_P2RIxCR1_CLG_Msk /*!< Color line green */ #define DCMIPP_P2RIxCR1_VSTART_Pos (16U) #define DCMIPP_P2RIxCR1_VSTART_Msk (0xFFFUL << DCMIPP_P2RIxCR1_VSTART_Pos) /*!< 0x0FFF0000 */ #define DCMIPP_P2RIxCR1_VSTART DCMIPP_P2RIxCR1_VSTART_Msk /*!< Vertical start */ #define DCMIPP_P2RIxCR1_CLR_Pos (28U) #define DCMIPP_P2RIxCR1_CLR_Msk (0x3UL << DCMIPP_P2RIxCR1_CLR_Pos) /*!< 0x30000000 */ #define DCMIPP_P2RIxCR1_CLR DCMIPP_P2RIxCR1_CLR_Msk /*!< Color line red */ /*************** Bit definition for DCMIPP_P2RIxCR2 register ***************/ #define DCMIPP_P2RIxCR2_VSIZE_Pos (0U) #define DCMIPP_P2RIxCR2_VSIZE_Msk (0xFFFUL << DCMIPP_P2RIxCR2_VSIZE_Pos) /*!< 0x00000FFF */ #define DCMIPP_P2RIxCR2_VSIZE DCMIPP_P2RIxCR2_VSIZE_Msk /*!< Vertical Size */ #define DCMIPP_P2RIxCR2_HSIZE_Pos (16U) #define DCMIPP_P2RIxCR2_HSIZE_Msk (0xFFFUL << DCMIPP_P2RIxCR2_HSIZE_Pos) /*!< 0x07FF8000 */ #define DCMIPP_P2RIxCR2_HSIZE DCMIPP_P2RIxCR2_HSIZE_Msk /*!< Horizontal Size */ /**************** Bit definition for DCMIPP_P2PPCR register *****************/ #define DCMIPP_P2PPCR_FORMAT_Pos (0U) #define DCMIPP_P2PPCR_FORMAT_Msk (0xFUL << DCMIPP_P2PPCR_FORMAT_Pos) /*!< 0x0000000F */ #define DCMIPP_P2PPCR_FORMAT DCMIPP_P2PPCR_FORMAT_Msk /*!< Memory format (only coplanar formats are supported in Pipe2) */ #define DCMIPP_P2PPCR_SWAPRB_Pos (4U) #define DCMIPP_P2PPCR_SWAPRB_Msk (0x1UL << DCMIPP_P2PPCR_SWAPRB_Pos) /*!< 0x00000010 */ #define DCMIPP_P2PPCR_SWAPRB DCMIPP_P2PPCR_SWAPRB_Msk /*!< Swaps R-vs-B components if RGB, and if YUV, swaps U-vs-V components */ #define DCMIPP_P2PPCR_LINEMULT_Pos (13U) #define DCMIPP_P2PPCR_LINEMULT_Msk (0x7UL << DCMIPP_P2PPCR_LINEMULT_Pos) /*!< 0x0000E000 */ #define DCMIPP_P2PPCR_LINEMULT DCMIPP_P2PPCR_LINEMULT_Msk /*!< Amount of capture completed lines for LINE Event and Interrupt */ #define DCMIPP_P2PPCR_DBM_Pos (16U) #define DCMIPP_P2PPCR_DBM_Msk (0x1UL << DCMIPP_P2PPCR_DBM_Pos) /*!< 0x00010000 */ #define DCMIPP_P2PPCR_DBM DCMIPP_P2PPCR_DBM_Msk /*!< Double buffer mode */ #define DCMIPP_P2PPCR_LMAWM_Pos (17U) #define DCMIPP_P2PPCR_LMAWM_Msk (0x7UL << DCMIPP_P2PPCR_LMAWM_Pos) /*!< 0x000E0000 */ #define DCMIPP_P2PPCR_LMAWM DCMIPP_P2PPCR_LMAWM_Msk /*!< Line multi address wrapping modulo */ #define DCMIPP_P2PPCR_LMAWE_Pos (20U) #define DCMIPP_P2PPCR_LMAWE_Msk (0x7UL << DCMIPP_P2PPCR_LMAWE_Pos) /*!< 0x00100000 */ #define DCMIPP_P2PPCR_LMAWE DCMIPP_P2PPCR_LMAWE_Msk /*!< Line multi address wrapping enable */ /*************** Bit definition for DCMIPP_P2PPM0AR1 register ***************/ #define DCMIPP_P2PPM0AR1_M0A_Pos (0U) #define DCMIPP_P2PPM0AR1_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P2PPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */ #define DCMIPP_P2PPM0AR1_M0A DCMIPP_P2PPM0AR1_M0A_Msk /*!< Memory0 address register 1 */ /*************** Bit definition for DCMIPP_P2PPM0AR2 register ***************/ #define DCMIPP_P2PPM0AR2_M0A_Pos (0U) #define DCMIPP_P2PPM0AR2_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P2PPM0AR2_M0A_Pos) /*!< 0xFFFFFFFF */ #define DCMIPP_P2PPM0AR2_M0A DCMIPP_P2PPM0AR2_M0A_Msk /*!< Memory0 address register 2*/ /*************** Bit definition for DCMIPP_P2PPM0PR register ****************/ #define DCMIPP_P2PPM0PR_PITCH_Pos (0U) #define DCMIPP_P2PPM0PR_PITCH_Msk (0x7FFFUL << DCMIPP_P2PPM0PR_PITCH_Pos) /*!< 0x00007FFF */ #define DCMIPP_P2PPM0PR_PITCH DCMIPP_P2PPM0PR_PITCH_Msk /*!< Number of bytes between the address of two consecutive lines */ /*************** Bit definition for DCMIPP_P2PPM0PR register ****************/ #define DCMIPP_P2STM0AR_Pos (0U) #define DCMIPP_P2STM0AR_Msk (0xFFFFFFFFUL << DCMIPP_P2STM0AR_Pos) /*!< 0xFFFFFFFF */ #define DCMIPP_P2STM0AR DCMIPP_P2STM0AR_Msk /*!< Pipe2 status Memory0 address register */ /***************** Bit definition for DCMIPP_P2IER register *****************/ #define DCMIPP_P2IER_LINEIE_Pos (0U) #define DCMIPP_P2IER_LINEIE_Msk (0x1UL << DCMIPP_P2IER_LINEIE_Pos) /*!< 0x00000001 */ #define DCMIPP_P2IER_LINEIE DCMIPP_P2IER_LINEIE_Msk /*!< Multi-line capture completed interrupt enable */ #define DCMIPP_P2IER_FRAMEIE_Pos (1U) #define DCMIPP_P2IER_FRAMEIE_Msk (0x1UL << DCMIPP_P2IER_FRAMEIE_Pos) /*!< 0x00000002 */ #define DCMIPP_P2IER_FRAMEIE DCMIPP_P2IER_FRAMEIE_Msk /*!< Frame capture completed interrupt enable */ #define DCMIPP_P2IER_VSYNCIE_Pos (2U) #define DCMIPP_P2IER_VSYNCIE_Msk (0x1UL << DCMIPP_P2IER_VSYNCIE_Pos) /*!< 0x00000004 */ #define DCMIPP_P2IER_VSYNCIE DCMIPP_P2IER_VSYNCIE_Msk /*!< VSYNC interrupt enable */ #define DCMIPP_P2IER_OVRIE_Pos (7U) #define DCMIPP_P2IER_OVRIE_Msk (0x1UL << DCMIPP_P2IER_OVRIE_Pos) /*!< 0x00000080 */ #define DCMIPP_P2IER_OVRIE DCMIPP_P2IER_OVRIE_Msk /*!< Overrun interrupt enable */ /***************** Bit definition for DCMIPP_P2SR register ******************/ #define DCMIPP_P2SR_LINEF_Pos (0U) #define DCMIPP_P2SR_LINEF_Msk (0x1UL << DCMIPP_P2SR_LINEF_Pos) /*!< 0x00000001 */ #define DCMIPP_P2SR_LINEF DCMIPP_P2SR_LINEF_Msk /*!< Multi-line capture completed raw interrupt status */ #define DCMIPP_P2SR_FRAMEF_Pos (1U) #define DCMIPP_P2SR_FRAMEF_Msk (0x1UL << DCMIPP_P2SR_FRAMEF_Pos) /*!< 0x00000002 */ #define DCMIPP_P2SR_FRAMEF DCMIPP_P2SR_FRAMEF_Msk /*!< Frame capture completed raw interrupt status */ #define DCMIPP_P2SR_VSYNCF_Pos (2U) #define DCMIPP_P2SR_VSYNCF_Msk (0x1UL << DCMIPP_P2SR_VSYNCF_Pos) /*!< 0x00000004 */ #define DCMIPP_P2SR_VSYNCF DCMIPP_P2SR_VSYNCF_Msk /*!< VSYNC raw interrupt status */ #define DCMIPP_P2SR_OVRF_Pos (7U) #define DCMIPP_P2SR_OVRF_Msk (0x1UL << DCMIPP_P2SR_OVRF_Pos) /*!< 0x00000080 */ #define DCMIPP_P2SR_OVRF DCMIPP_P2SR_OVRF_Msk /*!< Overrun raw interrupt status */ #define DCMIPP_P2SR_LSTLINE_Pos (16U) #define DCMIPP_P2SR_LSTLINE_Msk (0x1UL << DCMIPP_P2SR_LSTLINE_Pos) /*!< 0x00010000 */ #define DCMIPP_P2SR_LSTLINE DCMIPP_P2SR_LSTLINE_Msk /*!< Last line LSB bit, sampled at frame capture complete event */ #define DCMIPP_P2SR_LSTFRM_Pos (17U) #define DCMIPP_P2SR_LSTFRM_Msk (0x1UL << DCMIPP_P2SR_LSTFRM_Pos) /*!< 0x00020000 */ #define DCMIPP_P2SR_LSTFRM DCMIPP_P2SR_LSTFRM_Msk /*!< Last frame LSB bit, sampled at frame capture complete event */ #define DCMIPP_P2SR_CPTACT_Pos (23U) #define DCMIPP_P2SR_CPTACT_Msk (0x1UL << DCMIPP_P2SR_CPTACT_Pos) /*!< 0x00800000 */ #define DCMIPP_P2SR_CPTACT DCMIPP_P2SR_CPTACT_Msk /*!< Capture immediate status */ /***************** Bit definition for DCMIPP_P2FCR register *****************/ #define DCMIPP_P2FCR_CLINEF_Pos (0U) #define DCMIPP_P2FCR_CLINEF_Msk (0x1UL << DCMIPP_P2FCR_CLINEF_Pos) /*!< 0x00000001 */ #define DCMIPP_P2FCR_CLINEF DCMIPP_P2FCR_CLINEF_Msk /*!< Multi-line capture complete interrupt status clear */ #define DCMIPP_P2FCR_CFRAMEF_Pos (1U) #define DCMIPP_P2FCR_CFRAMEF_Msk (0x1UL << DCMIPP_P2FCR_CFRAMEF_Pos) /*!< 0x00000002 */ #define DCMIPP_P2FCR_CFRAMEF DCMIPP_P2FCR_CFRAMEF_Msk /*!< Frame capture complete interrupt status clear */ #define DCMIPP_P2FCR_CVSYNCF_Pos (2U) #define DCMIPP_P2FCR_CVSYNCF_Msk (0x1UL << DCMIPP_P2FCR_CVSYNCF_Pos) /*!< 0x00000004 */ #define DCMIPP_P2FCR_CVSYNCF DCMIPP_P2FCR_CVSYNCF_Msk /*!< Vertical synchronization interrupt status clear */ #define DCMIPP_P2FCR_COVRF_Pos (7U) #define DCMIPP_P2FCR_COVRF_Msk (0x1UL << DCMIPP_P2FCR_COVRF_Pos) /*!< 0x00000080 */ #define DCMIPP_P2FCR_COVRF DCMIPP_P2FCR_COVRF_Msk /*!< Overrun interrupt status clear */ /**************** Bit definition for DCMIPP_P2CFSCR register ****************/ #define DCMIPP_P2CFSCR_DTID_Pos (0U) #define DCMIPP_P2CFSCR_DTID_Msk (0x3FUL << DCMIPP_P2CFSCR_DTID_Pos) /*!< 0x0000003F */ #define DCMIPP_P2CFSCR_DTID DCMIPP_P2CFSCR_DTID_Msk /*!< Current Data type ID */ #define DCMIPP_P2CFSCR_VC_Pos (19U) #define DCMIPP_P2CFSCR_VC_Msk (0x3UL << DCMIPP_P2CFSCR_VC_Pos) /*!< 0x00180000 */ #define DCMIPP_P2CFSCR_VC DCMIPP_P2CFSCR_VC_Msk /*!< Current flow selection mode */ #define DCMIPP_P2CFSCR_FDTF_Pos (24U) #define DCMIPP_P2CFSCR_FDTF_Msk (0x3FUL << DCMIPP_P2CFSCR_FDTF_Pos) /*!< 0x3F000000 */ #define DCMIPP_P2CFSCR_FDTF DCMIPP_P2CFSCR_FDTF_Msk /*!< Current force Data type format */ #define DCMIPP_P2CFSCR_FDTFEN_Pos (30U) #define DCMIPP_P2CFSCR_FDTFEN_Msk (0x1UL << DCMIPP_P2CFSCR_FDTFEN_Pos) /*!< 0x40000000 */ #define DCMIPP_P2CFSCR_FDTFEN DCMIPP_P2CFSCR_FDTFEN_Msk /*!< Current force Data type format enable */ #define DCMIPP_P2CFSCR_PIPEN_Pos (31U) #define DCMIPP_P2CFSCR_PIPEN_Msk (0x1UL << DCMIPP_P2CFSCR_PIPEN_Pos) /*!< 0x80000000 */ #define DCMIPP_P2CFSCR_PIPEN DCMIPP_P2CFSCR_PIPEN_Msk /*!< Current activation of PipeN */ /*************** Bit definition for DCMIPP_P2CFCTCR register ****************/ #define DCMIPP_P2CFCTCR_FRATE_Pos (0U) #define DCMIPP_P2CFCTCR_FRATE_Msk (0x3UL << DCMIPP_P2CFCTCR_FRATE_Pos) /*!< 0x00000003 */ #define DCMIPP_P2CFCTCR_FRATE DCMIPP_P2CFCTCR_FRATE_Msk /*!< Frame capture rate control */ #define DCMIPP_P2CFCTCR_CPTMODE_Pos (2U) #define DCMIPP_P2CFCTCR_CPTMODE_Msk (0x1UL << DCMIPP_P2CFCTCR_CPTMODE_Pos) /*!< 0x00000004 */ #define DCMIPP_P2CFCTCR_CPTMODE DCMIPP_P2CFCTCR_CPTMODE_Msk /*!< Capture mode */ #define DCMIPP_P2CFCTCR_CPTREQ_Pos (3U) #define DCMIPP_P2CFCTCR_CPTREQ_Msk (0x1UL << DCMIPP_P2CFCTCR_CPTREQ_Pos) /*!< 0x00000008 */ #define DCMIPP_P2CFCTCR_CPTREQ DCMIPP_P2CFCTCR_CPTREQ_Msk /*!< Capture requested */ /*************** Bit definition for DCMIPP_P2CCRSTR register ****************/ #define DCMIPP_P2CCRSTR_HSTART_Pos (0U) #define DCMIPP_P2CCRSTR_HSTART_Msk (0xFFFUL << DCMIPP_P2CCRSTR_HSTART_Pos) /*!< 0x00000FFF */ #define DCMIPP_P2CCRSTR_HSTART DCMIPP_P2CCRSTR_HSTART_Msk /*!< Current horizontal start, from 0 to 4094 pixels wide */ #define DCMIPP_P2CCRSTR_VSTART_Pos (16U) #define DCMIPP_P2CCRSTR_VSTART_Msk (0xFFFUL << DCMIPP_P2CCRSTR_VSTART_Pos) /*!< 0x0FFF0000 */ #define DCMIPP_P2CCRSTR_VSTART DCMIPP_P2CCRSTR_VSTART_Msk /*!< Current vertical start, from 0 to 4094 pixels high */ /*************** Bit definition for DCMIPP_P2CCRSZR register ****************/ #define DCMIPP_P2CCRSZR_HSIZE_Pos (0U) #define DCMIPP_P2CCRSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P2CCRSZR_HSIZE_Pos) /*!< 0x00000FFF */ #define DCMIPP_P2CCRSZR_HSIZE DCMIPP_P2CCRSZR_HSIZE_Msk /*!< Current horizontal size, from 0 to 4094 pixels wide */ #define DCMIPP_P2CCRSZR_VSIZE_Pos (16U) #define DCMIPP_P2CCRSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P2CCRSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ #define DCMIPP_P2CCRSZR_VSIZE DCMIPP_P2CCRSZR_VSIZE_Msk /*!< Current vertical size, from 0 to 4094 pixels high */ #define DCMIPP_P2CCRSZR_ENABLE_Pos (31U) #define DCMIPP_P2CCRSZR_ENABLE_Msk (0x1UL << DCMIPP_P2CCRSZR_ENABLE_Pos) /*!< 0x80000000 */ #define DCMIPP_P2CCRSZR_ENABLE DCMIPP_P2CCRSZR_ENABLE_Msk /*!< Current ENABLE bit value */ /**************** Bit definition for DCMIPP_P2CDCCR register *****************/ #define DCMIPP_P2CDCCR_ENABLE_Pos (0U) #define DCMIPP_P2CDCCR_ENABLE_Msk (0x1UL << DCMIPP_P2CDCCR_ENABLE_Pos) /*!< 0x00000001 */ #define DCMIPP_P2CDCCR_ENABLE DCMIPP_P2CDCCR_ENABLE_Msk /*!< Decimation enable */ #define DCMIPP_P2CDCCR_HDEC_Pos (1U) #define DCMIPP_P2CDCCR_HDEC_Msk (0x3UL << DCMIPP_P2CDCCR_HDEC_Pos) /*!< 0x00000006 */ #define DCMIPP_P2CDCCR_HDEC DCMIPP_P2CDCCR_HDEC_Msk /*!< Horizontal decimation ratio */ #define DCMIPP_P2CDCCR_VDEC_Pos (3U) #define DCMIPP_P2CDCCR_VDEC_Msk (0x3UL << DCMIPP_P2CDCCR_VDEC_Pos) /*!< 0x00000018 */ #define DCMIPP_P2CDCCR_VDEC DCMIPP_P2CDCCR_VDEC_Msk /*!< Vertical decimation ratio */ /**************** Bit definition for DCMIPP_P2CDSCR register ****************/ #define DCMIPP_P2CDSCR_HDIV_Pos (0U) #define DCMIPP_P2CDSCR_HDIV_Msk (0x3FFUL << DCMIPP_P2CDSCR_HDIV_Pos) /*!< 0x000003FF */ #define DCMIPP_P2CDSCR_HDIV DCMIPP_P2CDSCR_HDIV_Msk /*!< Current horizontal division factor, from 128 (8x) to 1023 (1x) */ #define DCMIPP_P2CDSCR_VDIV_Pos (16U) #define DCMIPP_P2CDSCR_VDIV_Msk (0x3FFUL << DCMIPP_P2CDSCR_VDIV_Pos) /*!< 0x03FF0000 */ #define DCMIPP_P2CDSCR_VDIV DCMIPP_P2CDSCR_VDIV_Msk /*!< Current vertical division factor, from 128 (8x) to 1023 (1x) */ #define DCMIPP_P2CDSCR_ENABLE_Pos (31U) #define DCMIPP_P2CDSCR_ENABLE_Msk (0x1UL << DCMIPP_P2CDSCR_ENABLE_Pos) /*!< 0x80000000 */ #define DCMIPP_P2CDSCR_ENABLE DCMIPP_P2CDSCR_ENABLE_Msk /*!< Current value of the bit ENABLE */ /************** Bit definition for DCMIPP_P2CDSRTIOR register ***************/ #define DCMIPP_P2CDSRTIOR_HRATIO_Pos (0U) #define DCMIPP_P2CDSRTIOR_HRATIO_Msk (0xFFFFUL << DCMIPP_P2CDSRTIOR_HRATIO_Pos) /*!< 0x0000FFFF */ #define DCMIPP_P2CDSRTIOR_HRATIO DCMIPP_P2CDSRTIOR_HRATIO_Msk /*!< Current horizontal ratio, from 8192 (1x) to 65535 (8x) */ #define DCMIPP_P2CDSRTIOR_VRATIO_Pos (16U) #define DCMIPP_P2CDSRTIOR_VRATIO_Msk (0xFFFFUL << DCMIPP_P2CDSRTIOR_VRATIO_Pos) /*!< 0xFFFF0000 */ #define DCMIPP_P2CDSRTIOR_VRATIO DCMIPP_P2CDSRTIOR_VRATIO_Msk /*!< Current vertical ratio, from 8192 (1x) to 65535 (8x) */ /*************** Bit definition for DCMIPP_P2CDSSZR register ****************/ #define DCMIPP_P2CDSSZR_HSIZE_Pos (0U) #define DCMIPP_P2CDSSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P2CDSSZR_HSIZE_Pos) /*!< 0x00000FFF */ #define DCMIPP_P2CDSSZR_HSIZE DCMIPP_P2CDSSZR_HSIZE_Msk /*!< Current horizontal size, from 0 to 4094 pixels wide */ #define DCMIPP_P2CDSSZR_VSIZE_Pos (16U) #define DCMIPP_P2CDSSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P2CDSSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ #define DCMIPP_P2CDSSZR_VSIZE DCMIPP_P2CDSSZR_VSIZE_Msk /*!< Current vertical size, from 0 to 4094 pixels high */ /**************** Bit definition for DCMIPP_P2CPPCR register ****************/ #define DCMIPP_P2CPPCR_FORMAT_Pos (0U) #define DCMIPP_P2CPPCR_FORMAT_Msk (0xFUL << DCMIPP_P2CPPCR_FORMAT_Pos) /*!< 0x0000000F */ #define DCMIPP_P2CPPCR_FORMAT DCMIPP_P2CPPCR_FORMAT_Msk /*!< Memory format (only coplanar formats are supported in Pipe2) */ #define DCMIPP_P2CPPCR_SWAPRB_Pos (4U) #define DCMIPP_P2CPPCR_SWAPRB_Msk (0x1UL << DCMIPP_P2CPPCR_SWAPRB_Pos) /*!< 0x00000010 */ #define DCMIPP_P2CPPCR_SWAPRB DCMIPP_P2CPPCR_SWAPRB_Msk /*!< Swaps R-vs-B components if RGB, and if YUV, swaps U-vs-V components */ #define DCMIPP_P2CPPCR_LINEMULT_Pos (13U) #define DCMIPP_P2CPPCR_LINEMULT_Msk (0x7UL << DCMIPP_P2CPPCR_LINEMULT_Pos) /*!< 0x0000E000 */ #define DCMIPP_P2CPPCR_LINEMULT DCMIPP_P2CPPCR_LINEMULT_Msk /*!< Amount of capture completed lines for LINE Event and Interrupt */ #define DCMIPP_P2CPPCR_DBM_Pos (16U) #define DCMIPP_P2CPPCR_DBM_Msk (0x1UL << DCMIPP_P2CPPCR_DBM_Pos) /*!< 0x00010000 */ #define DCMIPP_P2CPPCR_DBM DCMIPP_P2CPPCR_DBM_Msk /*!< Double buffer mode */ #define DCMIPP_P2CPPCR_LMAWM_Pos (17U) #define DCMIPP_P2CPPCR_LMAWM_Msk (0x7UL << DCMIPP_P2CPPCR_LMAWM_Pos) /*!< 0x000E0000 */ #define DCMIPP_P2CPPCR_LMAWM DCMIPP_P2CPPCR_LMAWM_Msk /*!< Line multi address wrapping modulo */ #define DCMIPP_P2CPPCR_LMAWE_Pos (20U) #define DCMIPP_P2CPPCR_LMAWE_Msk (0x7UL << DCMIPP_P2CPPCR_LMAWE_Pos) /*!< 0x00100000 */ #define DCMIPP_P2CPPCR_LMAWE DCMIPP_P2CPPCR_LMAWE_Msk /*!< Line multi address wrapping enable */ /************** Bit definition for DCMIPP_P2CPPM0AR1 register ***************/ #define DCMIPP_P2CPPM0AR1_M0A_Pos (0U) #define DCMIPP_P2CPPM0AR1_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P2CPPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */ #define DCMIPP_P2CPPM0AR1_M0A DCMIPP_P2CPPM0AR1_M0A_Msk /*!< Memory0 address */ /************** Bit definition for DCMIPP_P2CPPM0AR2 register ***************/ #define DCMIPP_P2CPPM0AR2_M0A_Pos (0U) #define DCMIPP_P2CPPM0AR2_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P2CPPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */ #define DCMIPP_P2CPPM0AR2_M0A DCMIPP_P2CPPM0AR1_M0A_Msk /*!< Memory0 address Register 2 */ /*************** Bit definition for DCMIPP_P2CPPM0PR register ***************/ #define DCMIPP_P2CPPM0PR_PITCH_Pos (0U) #define DCMIPP_P2CPPM0PR_PITCH_Msk (0x7FFFUL << DCMIPP_P2CPPM0PR_PITCH_Pos) /*!< 0x00007FFF */ #define DCMIPP_P2CPPM0PR_PITCH DCMIPP_P2CPPM0PR_PITCH_Msk /*!< Number of bytes between the address of two consecutive lines */ /**************** Bit definition for DCMIPP_HWCFGR2 register ****************/ #define DCMIPP_HWCFGR2_VPFT_Pos (0U) #define DCMIPP_HWCFGR2_VPFT_Msk (0x7U << DCMIPP_HWCFGR2_VPFT_Pos) /*!< 0x00000007 */ #define DCMIPP_HWCFGR2_VPFT DCMIPP_HWCFGR2_VPFT_Msk /*!< Virtual pipe function */ #define DCMIPP_HWCFGR2_DBMFT_Pos (4U) #define DCMIPP_HWCFGR2_DBMFT_Msk (0x1U << DCMIPP_HWCFGR2_DBMFT_Pos) /*!< 0x00000010 */ #define DCMIPP_HWCFGR2_DBMFT DCMIPP_HWCFGR2_DBMFT_Msk /*!< Double buffer mode featured */ #define DCMIPP_HWCFGR2_PROCCLK_Pos (8U) #define DCMIPP_HWCFGR2_PROCCLK_Msk (0x1U << DCMIPP_HWCFGR2_PROCCLK_Pos) /*!< 0x00000100 */ #define DCMIPP_HWCFGR2_PROCCLK DCMIPP_HWCFGR2_PROCCLK_Msk /*!< Processing clock linked to AXI clock featured */ #define DCMIPP_HWCFGR2_ADDMOD_Pos (12U) #define DCMIPP_HWCFGR2_ADDMOD_Msk (0x1U << DCMIPP_HWCFGR2_ADDMOD_Pos) /*!< 0x00001000 */ #define DCMIPP_HWCFGR2_ADDMOD DCMIPP_HWCFGR2_ADDMOD_Msk /*!< Address modulo computation to access a small buffer in streaming featured */ #define DCMIPP_HWCFGR2_DEC1_Pos (16U) #define DCMIPP_HWCFGR2_DEC1_Msk (0x1U << DCMIPP_HWCFGR2_DEC1_Pos) /*!< 0x00010000 */ #define DCMIPP_HWCFGR2_DEC1 DCMIPP_HWCFGR2_DEC1_Msk /*!< Decimation on Pipe1 before downsize */ #define DCMIPP_HWCFGR2_DEC2_Pos (17U) #define DCMIPP_HWCFGR2_DEC2_Msk (0x1U << DCMIPP_HWCFGR2_DEC2_Pos) /*!< 0x00020000 */ #define DCMIPP_HWCFGR2_DEC2 DCMIPP_HWCFGR2_DEC2_Msk /*!< Decimation on Pipe2 before downsize */ #define DCMIPP_HWCFGR2_MCU_Pos (20U) #define DCMIPP_HWCFGR2_MCU_Msk (0x1U << DCMIPP_HWCFGR2_MCU_Pos) /*!< 0x00100000 */ #define DCMIPP_HWCFGR2_MCU DCMIPP_HWCFGR2_MCU_Msk /*!< Macroblock unit as pixel format */ #define DCMIPP_HWCFGR2_TPG_Pos (24U) #define DCMIPP_HWCFGR2_TPG_Msk (0x1U << DCMIPP_HWCFGR2_TPG_Pos) /*!< 0x01000000 */ #define DCMIPP_HWCFGR2_TPG DCMIPP_HWCFGR2_TPG_Msk /*!< Test Pattern Generator */ #define DCMIPP_HWCFGR2_STV_Pos (28U) #define DCMIPP_HWCFGR2_STV_Msk (0x1U << DCMIPP_HWCFGR2_STV_Pos) /*!< 0x10000000 */ #define DCMIPP_HWCFGR2_STV DCMIPP_HWCFGR2_STV_Msk /*!< Statistic Version */ /**************** Bit definition for DCMIPP_HWCFGR1 register ****************/ #define DCMIPP_HWCFGR1_CSIFT_Pos (0U) #define DCMIPP_HWCFGR1_CSIFT_Msk (0x1U << DCMIPP_HWCFGR1_CSIFT_Pos) /*!< 0x00000001 */ #define DCMIPP_HWCFGR1_CSIFT DCMIPP_HWCFGR1_CSIFT_Msk /*!< CSI2 host protocol compliant */ #define DCMIPP_HWCFGR1_PIPENB_Pos (4U) #define DCMIPP_HWCFGR1_PIPENB_Msk (0x3U << DCMIPP_HWCFGR1_PIPENB_Pos) /*!< 0x00000030 */ #define DCMIPP_HWCFGR1_PIPENB DCMIPP_HWCFGR1_PIPENB_Msk /*!< Number of pipes */ #define DCMIPP_HWCFGR1_IPPLUGCFG_Pos (8U) #define DCMIPP_HWCFGR1_IPPLUGCFG_Msk (0x1U << DCMIPP_HWCFGR1_IPPLUGCFG_Pos) /*!< 0x00000100 */ #define DCMIPP_HWCFGR1_IPPLUGCFG DCMIPP_HWCFGR1_IPPLUGCFG_Msk /*!< IP-Plug configuration */ #define DCMIPP_HWCFGR1_DSP1FT_Pos (12U) #define DCMIPP_HWCFGR1_DSP1FT_Msk (0x1U << DCMIPP_HWCFGR1_DSP1FT_Pos) /*!< 0x00001000 */ #define DCMIPP_HWCFGR1_DSP1FT DCMIPP_HWCFGR1_DSP1FT_Msk /*!< Down-sampling feature for the pixel Pipe1 */ #define DCMIPP_HWCFGR1_DSP2FT_Pos (13U) #define DCMIPP_HWCFGR1_DSP2FT_Msk (0x1U << DCMIPP_HWCFGR1_DSP2FT_Pos) /*!< 0x00002000 */ #define DCMIPP_HWCFGR1_DSP2FT DCMIPP_HWCFGR1_DSP2FT_Msk /*!< Down-sampling feature for the pixel Pipe2 */ #define DCMIPP_HWCFGR1_RB2RGB_Pos (16U) #define DCMIPP_HWCFGR1_RB2RGB_Msk (0x1U << DCMIPP_HWCFGR1_RB2RGB_Pos) /*!< 0x00010000 */ #define DCMIPP_HWCFGR1_RB2RGB DCMIPP_HWCFGR1_RB2RGB_Msk /*!< Raw Bayer to RGB feature (demosaicer) */ #define DCMIPP_HWCFGR1_PLANARFT_Pos (20U) #define DCMIPP_HWCFGR1_PLANARFT_Msk (0x3U << DCMIPP_HWCFGR1_PLANARFT_Pos) /*!< 0x00300000 */ #define DCMIPP_HWCFGR1_PLANARFT DCMIPP_HWCFGR1_PLANARFT_Msk /*!< Buffer features for Pipe1 */ #define DCMIPP_HWCFGR1_ROI1NB_Pos (24U) #define DCMIPP_HWCFGR1_ROI1NB_Msk (0xFU << DCMIPP_HWCFGR1_ROI1NB_Pos) /*!< 0x0F000000 */ #define DCMIPP_HWCFGR1_ROI1NB DCMIPP_HWCFGR1_ROI1NB_Msk /*!< Number of ROIs for Pipe1 */ #define DCMIPP_HWCFGR1_ROI2NB_Pos (28U) #define DCMIPP_HWCFGR1_ROI2NB_Msk (0xFU << DCMIPP_HWCFGR1_ROI2NB_Pos) /*!< 0xF0000000 */ #define DCMIPP_HWCFGR1_ROI2NB DCMIPP_HWCFGR1_ROI2NB_Msk /*!< Number of ROIs for Pipe2 */ /***************** Bit definition for DCMIPP_VERR register ******************/ #define DCMIPP_VERR_MINREV_Pos (0U) #define DCMIPP_VERR_MINREV_Msk (0xFU << DCMIPP_VERR_MINREV_Pos) /*!< 0x0000000F */ #define DCMIPP_VERR_MINREV DCMIPP_VERR_MINREV_Msk /*!< DCMIPP minor revision */ #define DCMIPP_VERR_MAJREV_Pos (4U) #define DCMIPP_VERR_MAJREV_Msk (0xFU << DCMIPP_VERR_MAJREV_Pos) /*!< 0x000000F0 */ #define DCMIPP_VERR_MAJREV DCMIPP_VERR_MAJREV_Msk /*!< DCMIPP major revision */ /***************** Bit definition for DCMIPP_IPIDR register *****************/ #define DCMIPP_IPIDR_IDR_Pos (0U) #define DCMIPP_IPIDR_IDR_Msk (0xFFFFFFFFU << DCMIPP_IPIDR_IDR_Pos) /*!< 0xFFFFFFFF */ #define DCMIPP_IPIDR_IDR DCMIPP_IPIDR_IDR_Msk /*!< Parallel camera interface (DCMI) and optional pixel processing (PP) */ /***************** Bit definition for DCMIPP_SIDR register ******************/ #define DCMIPP_SIDR_SID_Pos (0U) #define DCMIPP_SIDR_SID_Msk (0xFFFFFFFFU << DCMIPP_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ #define DCMIPP_SIDR_SID DCMIPP_SIDR_SID_Msk /*!< 4-Kbyte decoding space */ /******************************************************************************/ /* */ /* Delay Block Interface (DLYB) */ /* */ /******************************************************************************/ /******************* Bit definition for DLYB_CR register ********************/ #define DLYB_CR_DEN_Pos (0U) #define DLYB_CR_DEN_Msk (0x1UL << DLYB_CR_DEN_Pos) /*!< 0x00000001 */ #define DLYB_CR_DEN DLYB_CR_DEN_Msk /*!= AAW[15:0] bits (programmed in LTDC_AWCR register). */ #define LTDC_LxWHPCR_WHSPPOS_Pos (16U) #define LTDC_LxWHPCR_WHSPPOS_Msk (0xfffUL << LTDC_LxWHPCR_WHSPPOS_Pos) #define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk /*!< window horizontal stop positionThese bits configure the last visible pixel of a line of the layer window.WHSPPOS[15:0] must be <= AHBP[15:0] bits + 1 (programmed in LTDC_BPCR register). */ /* Bit fields for LTDC_LxWVPCR register */ #define LTDC_LxWVPCR_WVSTPOS_Pos (0U) #define LTDC_LxWVPCR_WVSTPOS_Msk (0xfffUL << LTDC_LxWVPCR_WVSTPOS_Pos) #define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk /*!< window vertical start positionThese bits configure the first visible line of the layer window.WVSTPOS[15:0] must be >= AAH[15:0] bits (programmed in LTDC_AWCR register). */ #define LTDC_LxWVPCR_WVSPPOS_Pos (16U) #define LTDC_LxWVPCR_WVSPPOS_Msk (0xfffUL << LTDC_LxWVPCR_WVSPPOS_Pos) #define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk /*!< window vertical stop positionThese bits configure the last visible line of the layer window.WVSPPOS[11:0] must be <= AVBP[15:0] bits + 1 (programmed in LTDC_BPCR register). */ /* Bit fields for LTDC_LxCKCR register */ #define LTDC_LxCKCR_CKBLUE_Pos (0U) #define LTDC_LxCKCR_CKBLUE_Msk (0xffUL << LTDC_LxCKCR_CKBLUE_Pos) #define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk /*!< color key blue value */ #define LTDC_LxCKCR_CKGREEN_Pos (8U) #define LTDC_LxCKCR_CKGREEN_Msk (0xffUL << LTDC_LxCKCR_CKGREEN_Pos) #define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk /*!< color key green value */ #define LTDC_LxCKCR_CKRED_Pos (16U) #define LTDC_LxCKCR_CKRED_Msk (0xffUL << LTDC_LxCKCR_CKRED_Pos) #define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk /*!< color key red value */ /* Bit fields for LTDC_LxPFCR register */ #define LTDC_LxPFCR_PF_Pos (0U) #define LTDC_LxPFCR_PF_Msk (0x7UL << LTDC_LxPFCR_PF_Pos) #define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk /*!< pixel formatThese bits configure the pixel format- 000: ARGB8888- 001: RGB888- 010: RGB565- 011: ARGB1555- 100: ARGB4444- 101: L8 (8-bit luminance)- 110: AL44 (4-bit alpha, 4-bit luminance)- 111: AL88 (8-bit alpha, 8-bit luminance) */ /* Bit fields for LTDC_LxCACR register */ #define LTDC_LxCACR_CONSTA_Pos (0U) #define LTDC_LxCACR_CONSTA_Msk (0xffUL << LTDC_LxCACR_CONSTA_Pos) #define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk /*!< constant alphaThese bits configure the constant alpha used for blending. The constant alpha is divided by 255 by hardware.Example: if the programmed constant alpha is 0xFF, the constant alpha value is 255 / 255 = 1. */ /* Bit fields for LTDC_LxDCCR register */ #define LTDC_LxDCCR_DCBLUE_Pos (0U) #define LTDC_LxDCCR_DCBLUE_Msk (0xffUL << LTDC_LxDCCR_DCBLUE_Pos) #define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk /*!< default color blueThese bits configure the default blue value. */ #define LTDC_LxDCCR_DCGREEN_Pos (8U) #define LTDC_LxDCCR_DCGREEN_Msk (0xffUL << LTDC_LxDCCR_DCGREEN_Pos) #define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk /*!< default color greenThese bits configure the default green value. */ #define LTDC_LxDCCR_DCRED_Pos (16U) #define LTDC_LxDCCR_DCRED_Msk (0xffUL << LTDC_LxDCCR_DCRED_Pos) #define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk /*!< default color redThese bits configure the default red value. */ #define LTDC_LxDCCR_DCALPHA_Pos (24U) #define LTDC_LxDCCR_DCALPHA_Msk (0xffUL << LTDC_LxDCCR_DCALPHA_Pos) #define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk /*!< default color alphaThese bits configure the default alpha value. */ /* Bit fields for LTDC_LxBFCR register */ #define LTDC_LxBFCR_BF2_Pos (0U) #define LTDC_LxBFCR_BF2_Msk (0x7UL << LTDC_LxBFCR_BF2_Pos) #define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk /*!< blending factor 2These bits select the blending factor F2- 000: reserved- 001: reserved- 010: reserved- 011: reserved- 100: reserved- 101: 1 - constant alpha- 110: reserved- 111: 1 - (pixel alpha x constant alpha) */ #define LTDC_LxBFCR_BF1_Pos (8U) #define LTDC_LxBFCR_BF1_Msk (0x7UL << LTDC_LxBFCR_BF1_Pos) #define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk /*!< blending factor 1These bits select the blending factor F1.- 000: reserved- 001: reserved- 010: reserved- 011: reserved- 100: constant alpha- 101: reserved- 110: pixel alpha x constant alpha- 111: reserved */ #define LTDC_LxBFCR_BOR_Pos (16U) #define LTDC_LxBFCR_BOR_Msk (0x1UL << LTDC_LxBFCR_BOR_Pos) #define LTDC_LxBFCR_BOR LTDC_LxBFCR_BOR_Msk /*!< blending orderThese bits select the blending orderBOR.BOR= 0000 is for the most background layer (usually hidden behind others)BOR= 1111 is for the most foreground layer (always visible, never hidden by any other).In case of inconsistency, like two layers at same order, the blending engine reverses to BOR[LayerID] = LayerID-1, so that Layer3 is in foreground and Layer1 is in background.Note: if the Layer3 is set as secure, to guarantee it is on the foreground, it should be configured with BOR(Layer3)=1111. */ /* Bit fields for LTDC_LxBLCR register */ #define LTDC_LxBLCR_BL_Pos (0U) #define LTDC_LxBLCR_BL_Msk (0x1fUL << LTDC_LxBLCR_BL_Pos) #define LTDC_LxBLCR_BL LTDC_LxBLCR_BL_Msk /*!< burst length- 0x00: maximum burst length (16 words 64bit, thus 128 Bytes)- 0x01: 1 word (of 64bit) per burst..- 0x10: 16 words (of 64bit) per burst- 0x11: reserved...- 0xFF: reserved. */ /* Bit fields for LTDC_LxPCR register */ #define LTDC_LxPCR_YCEN_Pos (3U) #define LTDC_LxPCR_YCEN_Msk (0x1UL << LTDC_LxPCR_YCEN_Pos) #define LTDC_LxPCR_YCEN LTDC_LxPCR_YCEN_Msk /*!< YCbCr-to-RGB Conversion Enable:- 0: conversion disabled.- 1: YCbCr conversion enabled, using the YCM setting above. */ #define LTDC_LxPCR_YCM_Pos (4U) #define LTDC_LxPCR_YCM_Msk (0x3UL << LTDC_LxPCR_YCM_Pos) #define LTDC_LxPCR_YCM LTDC_LxPCR_YCM_Msk /*!< YCbCr Conversion ModeDefined the type of input that is considered and converted to a YCbCr 444:- 00: interleaved 422 (Cb and Cr component are replicated horizontally for pixels P and P+1)- 01: semi-Planar 420: (Cb and Cr component are replicated horizontally and vertically. The layer main configuration defines the access to the Y buffer, and auxiliary registers define the access to the Cb and Cr buffers).- 10: full-Planar 420: (Cb and Cr component are replicated horizontally and vertically. The layer main configuration defines the access to the Y buffer, and auxiliary registers define the access to the Cb and Cr buffers).- 11: reserved. */ #define LTDC_LxPCR_YF_Pos (6U) #define LTDC_LxPCR_YF_Msk (0x1UL << LTDC_LxPCR_YF_Pos) #define LTDC_LxPCR_YF LTDC_LxPCR_YF_Msk /*!< Y Component FirstDefines if the byte 0 of a word (in LSB) contains the Y component.- 0: Y component disabled (thus Cr or Cb component is on byte 0)- 1: Y component enabled (thus Y component is on byte 0) */ #define LTDC_LxPCR_CBF_Pos (7U) #define LTDC_LxPCR_CBF_Msk (0x1UL << LTDC_LxPCR_CBF_Pos) #define LTDC_LxPCR_CBF LTDC_LxPCR_CBF_Msk /*!< Cb Component FirstDefines if the byte 0 and 1 of a word (in LSB) contains the Cb component. The setting impacts only for interleaved and semi-planar modes, as it has no meaning in full-planar mode)- 0: Cb disabled (thus Cr component is on byte 0 and 1)- 1: Cb enabled (thus Cb component is on byte 0 and 1) */ #define LTDC_LxPCR_OF_Pos (8U) #define LTDC_LxPCR_OF_Msk (0x1UL << LTDC_LxPCR_OF_Pos) #define LTDC_LxPCR_OF LTDC_LxPCR_OF_Msk /*!< Odd Pixel FirstDefines if the byte 0 of a word (in LSB) contains the Odd pixel.- 0: odd pixel disabled (thus even pixel on byte 0)- 1: odd pixel enabled (thus odd pixel on byte 0) */ #define LTDC_LxPCR_YREN_Pos (9U) #define LTDC_LxPCR_YREN_Msk (0x1UL << LTDC_LxPCR_YREN_Pos) #define LTDC_LxPCR_YREN LTDC_LxPCR_YREN_Msk /*!< Y Rescale EnableWhen enabled, incoming Y values in range 16..235 are re-scaled to range 0..255, - 0: rescaling disabled.- 1: rescaling enabled. */ /* Bit fields for LTDC_LxCFBAR register */ #define LTDC_LxCFBAR_CFBADD_Pos (0U) #define LTDC_LxCFBAR_CFBADD_Msk (0xffffffffUL << LTDC_LxCFBAR_CFBADD_Pos) #define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk /*!< color frame buffer start addressThese bits define the color frame buffer start address. */ /* Bit fields for LTDC_LxCFBLR register */ #define LTDC_LxCFBLR_CFBLL_Pos (0U) #define LTDC_LxCFBLR_CFBLL_Msk (0x3fffUL << LTDC_LxCFBLR_CFBLL_Pos) #define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk /*!< color frame buffer line lengthThese bits define the length of one line of pixels in bytes + 7.The line length is computed as follows:active high width * number of bytes per pixel + 7. */ #define LTDC_LxCFBLR_CFBP_Pos (16U) #define LTDC_LxCFBLR_CFBP_Msk (0x7fffUL << LTDC_LxCFBLR_CFBP_Pos) #define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk /*!< color frame buffer pitch in bytesThese bits define the pitch that is the increment from the start of one line of pixels to the start of the next line in bytes.Negative values (with msb bit = 1) are allowed, to read the buffer from bottom to top, and thus to flip is vertically. When vertically flipped, as the address register must provide the address of the first line to be read, the address register must point to the start of the bottom line of the buffer. */ /* Bit fields for LTDC_LxCFBLNR register */ #define LTDC_LxCFBLNR_CFBLNBR_Pos (0U) #define LTDC_LxCFBLNR_CFBLNBR_Msk (0xfffUL << LTDC_LxCFBLNR_CFBLNBR_Pos) #define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk /*!< frame buffer line numberThese bits define the number of lines in the frame buffer that corresponds to the active high width. */ /* Bit fields for LTDC_L1AFBA0R register */ #define LTDC_L1AFBA0R_AFBADD0_Pos (0U) #define LTDC_L1AFBA0R_AFBADD0_Msk (0xffffffffUL << LTDC_L1AFBA0R_AFBADD0_Pos) #define LTDC_L1AFBA0R_AFBADD0 LTDC_L1AFBA0R_AFBADD0_Msk /*!< color frame buffer start addressThese bits define the color frame buffer start address. */ /* Bit fields for LTDC_LxAFBA1R register */ #define LTDC_L1AFBA1R_AFBADD1_Pos (0U) #define LTDC_L1AFBA1R_AFBADD1_Msk (0xffffffffUL << LTDC_L1AFBA1R_AFBADD1_Pos) #define LTDC_L1AFBA1R_AFBADD1 LTDC_L1AFBA1R_AFBADD1_Msk /*!< color frame buffer start addressThese bits define the color frame buffer start address. */ /* Bit fields for LTDC_LxAFBLR register */ #define LTDC_L1AFBLR_AFBLL_Pos (0U) #define LTDC_L1AFBLR_AFBLL_Msk (0xffffUL << LTDC_L1AFBLR_AFBLL_Pos) #define LTDC_L1AFBLR_AFBLL LTDC_L1AFBLR_AFBLL_Msk /*!< color frame buffer line lengthThese bits define the length of one line of pixels in bytes + 7.The line length is computed as follows:active high width * number of bytes per pixel + 7. */ #define LTDC_L1AFBLR_AFBP_Pos (16U) #define LTDC_L1AFBLR_AFBP_Msk (0xffffUL << LTDC_L1AFBLR_AFBP_Pos) #define LTDC_L1AFBLR_AFBP LTDC_L1AFBLR_AFBP_Msk /*!< color frame buffer pitch in bytesThese bits define the pitch that is the increment from the start of one line of pixels to the start of the next line in bytes.Negative values (with msb bit = 1) are allowed, to read the buffer from bottom to top, and thus to flip is vertically. When vertically flipped, as the address register must provide the address of the first line to be read, the address register must point to the start of the bottom line of the buffer. */ /* Bit fields for LTDC_LxAFBLNR register */ #define LTDC_L1AFBLNR_AFBLNBR_Pos (0U) #define LTDC_L1AFBLNR_AFBLNBR_Msk (0xffffUL << LTDC_L1AFBLNR_AFBLNBR_Pos) #define LTDC_L1AFBLNR_AFBLNBR LTDC_L1AFBLNR_AFBLNBR_Msk /*!< frame buffer line numberThese bits define the number of lines in the frame buffer that corresponds to the active high width. */ /* Bit fields for LTDC_LxCLUTWR register */ #define LTDC_LxCLUTWR_BLUE_Pos (0U) #define LTDC_LxCLUTWR_BLUE_Msk (0xffUL << LTDC_LxCLUTWR_BLUE_Pos) #define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk /*!< blue valueThese bits configure the blue value. */ #define LTDC_LxCLUTWR_GREEN_Pos (8U) #define LTDC_LxCLUTWR_GREEN_Msk (0xffUL << LTDC_LxCLUTWR_GREEN_Pos) #define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk /*!< green valueThese bits configure the green value. */ #define LTDC_LxCLUTWR_RED_Pos (16U) #define LTDC_LxCLUTWR_RED_Msk (0xffUL << LTDC_LxCLUTWR_RED_Pos) #define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk /*!< red valueThese bits configure the red value. */ #define LTDC_LxCLUTWR_CLUTADD_Pos (24U) #define LTDC_LxCLUTWR_CLUTADD_Msk (0xffUL << LTDC_LxCLUTWR_CLUTADD_Pos) #define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT addressThese bits configure the CLUT address (color position within the CLUT) of each RGB value. */ /* Bit fields for LTDC_LxCYR0R register */ #define LTDC_LxCYR0R_CR2R_Pos (0U) #define LTDC_LxCYR0R_CR2R_Msk (0x3ffUL << LTDC_LxCYR0R_CR2R_Pos) #define LTDC_LxCYR0R_CR2R LTDC_LxCYR0R_CR2R_Msk /*!< Cr-to-Red coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */ #define LTDC_LxCYR0R_CB2B_Pos (16U) #define LTDC_LxCYR0R_CB2B_Msk (0x3ffUL << LTDC_LxCYR0R_CB2B_Pos) #define LTDC_LxCYR0R_CB2B LTDC_LxCYR0R_CB2B_Msk /*!< Cb-to-Blue coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */ /* Bit fields for LTDC_LxCYR1R register */ #define LTDC_LxCYR1R_CR2G_Pos (0U) #define LTDC_LxCYR1R_CR2G_Msk (0x3ffUL << LTDC_LxCYR1R_CR2G_Pos) #define LTDC_LxCYR1R_CR2G LTDC_LxCYR1R_CR2G_Msk /*!< Cr-to-Green coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */ #define LTDC_LxCYR1R_CB2G_Pos (16U) #define LTDC_LxCYR1R_CB2G_Msk (0x3ffUL << LTDC_LxCYR1R_CB2G_Pos) #define LTDC_LxCYR1R_CB2G LTDC_LxCYR1R_CB2G_Msk /*!< Cb-to-Green coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */ /* Bit fields for LTDC_LxFPF0R register */ #define LTDC_LxFPF0R_APOS_Pos (0U) #define LTDC_LxFPF0R_APOS_Msk (0x1fUL << LTDC_LxFPF0R_APOS_Pos) #define LTDC_LxFPF0R_APOS LTDC_LxFPF0R_APOS_Msk /*!< Location of the alpha component inside the pixel memory word (in bits). */ #define LTDC_LxFPF0R_ALEN_Pos (5U) #define LTDC_LxFPF0R_ALEN_Msk (0xfUL << LTDC_LxFPF0R_ALEN_Pos) #define LTDC_LxFPF0R_ALEN LTDC_LxFPF0R_ALEN_Msk /*!< Width of the alpha component (in bits). */ #define LTDC_LxFPF0R_RPOS_Pos (9U) #define LTDC_LxFPF0R_RPOS_Msk (0x1fUL << LTDC_LxFPF0R_RPOS_Pos) #define LTDC_LxFPF0R_RPOS LTDC_LxFPF0R_RPOS_Msk /*!< Location of the red component inside the pixel memory word (in bits). */ #define LTDC_LxFPF0R_RLEN_Pos (14U) #define LTDC_LxFPF0R_RLEN_Msk (0xfUL << LTDC_LxFPF0R_RLEN_Pos) #define LTDC_LxFPF0R_RLEN LTDC_LxFPF0R_RLEN_Msk /*!< Width of the red component (in bits). */ /* Bit fields for LTDC_LxFPF1R register */ #define LTDC_LxFPF1R_GPOS_Pos (0U) #define LTDC_LxFPF1R_GPOS_Msk (0x1fUL << LTDC_LxFPF1R_GPOS_Pos) #define LTDC_LxFPF1R_GPOS LTDC_LxFPF1R_GPOS_Msk /*!< Location of the alpha component inside the pixel memory word (in bits). */ #define LTDC_LxFPF1R_GLEN_Pos (5U) #define LTDC_LxFPF1R_GLEN_Msk (0xfUL << LTDC_LxFPF1R_GLEN_Pos) #define LTDC_LxFPF1R_GLEN LTDC_LxFPF1R_GLEN_Msk /*!< Width of the alpha component (in bits). */ #define LTDC_LxFPF1R_BPOS_Pos (9U) #define LTDC_LxFPF1R_BPOS_Msk (0x1fUL << LTDC_LxFPF1R_BPOS_Pos) #define LTDC_LxFPF1R_BPOS LTDC_LxFPF1R_BPOS_Msk /*!< Location of the red component inside the pixel memory word (in bits). */ #define LTDC_LxFPF1R_BLEN_Pos (14U) #define LTDC_LxFPF1R_BLEN_Msk (0xfUL << LTDC_LxFPF1R_BLEN_Pos) #define LTDC_LxFPF1R_BLEN LTDC_LxFPF1R_BLEN_Msk /*!< Width of the red component (in bits). */ #define LTDC_LxFPF1R_PSIZE_Pos (18U) #define LTDC_LxFPF1R_PSIZE_Msk (0x7UL << LTDC_LxFPF1R_PSIZE_Pos) #define LTDC_LxFPF1R_PSIZE LTDC_LxFPF1R_PSIZE_Msk /*!< Width of the red component (in bits). */ /******************************************************************************/ /* */ /* Memory Cipher Engine (MCE) */ /* */ /******************************************************************************/ /******************** Bit definition for MCE_CR register ********************/ #define MCE_CR_GLOCK_Pos (0U) #define MCE_CR_GLOCK_Msk (0x1UL << MCE_CR_GLOCK_Pos) /*!< 0x00000001 */ #define MCE_CR_GLOCK MCE_CR_GLOCK_Msk /*!< MCE global lock */ #define MCE_CR_MKLOCK_Pos (1U) #define MCE_CR_MKLOCK_Msk (0x1UL << MCE_CR_MKLOCK_Pos) /*!< 0x00000002 */ #define MCE_CR_MKLOCK MCE_CR_MKLOCK_Msk /*!< MCE master and fast master keys lock */ #define MCE_CR_CIPHERSEL_Pos (4U) #define MCE_CR_CIPHERSEL_Msk (0x3UL << MCE_CR_CIPHERSEL_Pos) /*!< 0x00000030 */ #define MCE_CR_CIPHERSEL MCE_CR_CIPHERSEL_Msk /*!< MCE Cipher selection */ #define MCE_CR_CIPHERSEL_0 (0x1UL << MCE_CR_CIPHERSEL_Pos) /*!< 0x00000010 */ #define MCE_CR_CIPHERSEL_1 (0x2UL << MCE_CR_CIPHERSEL_Pos) /*!< 0x00000020 */ /******************** Bit definition for MCE_SR register ********************/ #define MCE_SR_MKVALID_Pos (0U) #define MCE_SR_MKVALID_Msk (0x1UL << MCE_SR_MKVALID_Pos) /*!< 0x00000001 */ #define MCE_SR_MKVALID MCE_SR_MKVALID_Msk /*!< MCE master key valid flag */ #define MCE_SR_FMKVALID_Pos (2U) #define MCE_SR_FMKVALID_Msk (0x1UL << MCE_SR_FMKVALID_Pos) /*!< 0x00000004 */ #define MCE_SR_FMKVALID MCE_SR_FMKVALID_Msk /*!< MCE fast master key valid flag */ #define MCE_SR_ENCDIS_Pos (4U) #define MCE_SR_ENCDIS_Msk (0x1UL << MCE_SR_ENCDIS_Pos) /*!< 0x00000010 */ #define MCE_SR_ENCDIS MCE_SR_ENCDIS_Msk /*!< MCE encryption disabled flag */ /******************** Bit definition for MCE_IASR register ******************/ #define MCE_IASR_IAEF_Pos (1U) #define MCE_IASR_IAEF_Msk (0x1UL << MCE_IASR_IAEF_Pos) /*!< 0x00000002 */ #define MCE_IASR_IAEF MCE_IASR_IAEF_Msk /*!< MCE illegal access error flag */ /******************** Bit definition for MCE_IACR register ******************/ #define MCE_IACR_IAEF_Pos (1U) #define MCE_IACR_IAEF_Msk (0x1UL << MCE_IACR_IAEF_Pos) /*!< 0x00000002 */ #define MCE_IACR_IAEF MCE_IACR_IAEF_Msk /*!< MCE illegal access error clear bit */ /******************** Bit definition for MCE_IAIER register *****************/ #define MCE_IAIER_IAEIE_Pos (1U) #define MCE_IAIER_IAEIE_Msk (0x1UL << MCE_IAIER_IAEIE_Pos) /*!< 0x00000002 */ #define MCE_IAIER_IAEIE MCE_IAIER_IAEIE_Msk /*!< MCE illegal access error interrupt enable */ /******************** Bit definition for MCE_IADDR register *****************/ #define MCE_IADDR_IADD_Pos (0U) #define MCE_IADDR_IADD_Msk (0xFFFFFFFFUL << MCE_IADDR_IADD_Pos) /*!< 0xFFFFFFFF */ #define MCE_IADDR_IADD MCE_IADDR_IADD_Msk /*!< MCE illegal access */ /******************** Bit definition for MCE_REGCR register *****************/ #define MCE_REGCR_BREN_Pos (0U) #define MCE_REGCR_BREN_Msk (0x1UL << MCE_REGCR_BREN_Pos) /*!< 0x00000001 */ #define MCE_REGCR_BREN MCE_REGCR_BREN_Msk /*!< MCE base region enable */ #define MCE_REGCR_CTXID_Pos (9U) #define MCE_REGCR_CTXID_Msk (0x3UL << MCE_REGCR_CTXID_Pos) /*!< 0x00000600 */ #define MCE_REGCR_CTXID MCE_REGCR_CTXID_Msk /*!< MCE context ID */ #define MCE_REGCR_CTXID_0 (0x1UL << MCE_REGCR_CTXID_Pos) /*!< 0x00000200 */ #define MCE_REGCR_CTXID_1 (0x2UL << MCE_REGCR_CTXID_Pos) /*!< 0x00000400 */ #define MCE_REGCR_ENC_Pos (14U) #define MCE_REGCR_ENC_Msk (0x3UL << MCE_REGCR_ENC_Pos) /*!< 0x0000C000 */ #define MCE_REGCR_ENC MCE_REGCR_ENC_Msk /*!< MCE encrypted region */ #define MCE_REGCR_ENC_0 (0x1UL << MCE_REGCR_ENC_Pos) /*!< 0x00004000 */ #define MCE_REGCR_ENC_1 (0x2UL << MCE_REGCR_ENC_Pos) /*!< 0x00008000 */ /******************** Bit definition for MCE_SADDR register *****************/ #define MCE_SADDR_BADDSTART_Pos (12U) #define MCE_SADDR_BADDSTART_Msk (0xFFFFFUL << MCE_SADDR_BADDSTART_Pos) /*!< 0xFFFFF000 */ #define MCE_SADDR_BADDSTART MCE_SADDR_BADDSTART_Msk /*!< MCE region address start */ /******************** Bit definition for MCE_EADDR register *****************/ #define MCE_EADDR_BADDEND_Pos (12U) #define MCE_EADDR_BADDEND_Msk (0xFFFFFUL << MCE_EADDR_BADDEND_Pos) /*!< 0xFFFFF000 */ #define MCE_EADDR_BADDEND MCE_EADDR_BADDEND_Msk /*!< MCE region address end */ /******************** Bit definition for MCE_MKEYR0 register ****************/ #define MCE_MKEYR0_MKEY_Pos (0U) #define MCE_MKEYR0_MKEY_Msk (0xFFFFFFFFUL << MCE_MKEYR0_MKEY_Pos) /*!< 0xFFFFFFFF */ #define MCE_MKEYR0_MKEY MCE_MKEYR0_MKEY_Msk /*!< MCE master key, bits [31:0] */ /******************** Bit definition for MCE_MKEYR1 register ****************/ #define MCE_MKEYR1_MKEY_Pos (0U) #define MCE_MKEYR1_MKEY_Msk (0xFFFFFFFFUL << MCE_MKEYR1_MKEY_Pos) /*!< 0xFFFFFFFF */ #define MCE_MKEYR1_MKEY MCE_MKEYR1_MKEY_Msk /*!< MCE master key, bits [63:32] */ /******************** Bit definition for MCE_MKEYR2 register ****************/ #define MCE_MKEYR2_MKEY_Pos (0U) #define MCE_MKEYR2_MKEY_Msk (0xFFFFFFFFUL << MCE_MKEYR2_MKEY_Pos) /*!< 0xFFFFFFFF */ #define MCE_MKEYR2_MKEY MCE_MKEYR2_MKEY_Msk /*!< MCE master key, bits [95:64] */ /******************** Bit definition for MCE_MKEYR3 register ****************/ #define MCE_MKEYR3_MKEY_Pos (0U) #define MCE_MKEYR3_MKEY_Msk (0xFFFFFFFFUL << MCE_MKEYR3_MKEY_Pos) /*!< 0xFFFFFFFF */ #define MCE_MKEYR3_MKEY MCE_MKEYR3_MKEY_Msk /*!< MCE master key, bits [127:96] */ /******************** Bit definition for MCE_MKEYR4 register ****************/ #define MCE_MKEYR4_MKEY_Pos (0U) #define MCE_MKEYR4_MKEY_Msk (0xFFFFFFFFUL << MCE_MKEYR4_MKEY_Pos) /*!< 0xFFFFFFFF */ #define MCE_MKEYR4_MKEY MCE_MKEYR4_MKEY_Msk /*!< MCE master key, bits [159:128] */ /******************** Bit definition for MCE_MKEYR5 register ****************/ #define MCE_MKEYR5_MKEY_Pos (0U) #define MCE_MKEYR5_MKEY_Msk (0xFFFFFFFFUL << MCE_MKEYR5_MKEY_Pos) /*!< 0xFFFFFFFF */ #define MCE_MKEYR5_MKEY MCE_MKEYR5_MKEY_Msk /*!< MCE master key, bits [191:160] */ /******************** Bit definition for MCE_MKEYR6 register ****************/ #define MCE_MKEYR6_MKEY_Pos (0U) #define MCE_MKEYR6_MKEY_Msk (0xFFFFFFFFUL << MCE_MKEYR6_MKEY_Pos) /*!< 0xFFFFFFFF */ #define MCE_MKEYR6_MKEY MCE_MKEYR6_MKEY_Msk /*!< MCE master key, bits [223:192] */ /******************** Bit definition for MCE_MKEYR7 register ****************/ #define MCE_MKEYR7_MKEY_Pos (0U) #define MCE_MKEYR7_MKEY_Msk (0xFFFFFFFFUL << MCE_MKEYR7_MKEY_Pos) /*!< 0xFFFFFFFF */ #define MCE_MKEYR7_MKEY MCE_MKEYR7_MKEY_Msk /*!< MCE master key, bits [255:224] */ /******************** Bit definition for MCE_FMKEYR0 register ***************/ #define MCE_FMKEYR0_FMKEY_Pos (0U) #define MCE_FMKEYR0_FMKEY_Msk (0xFFFFFFFFUL << MCE_FMKEYR0_FMKEY_Pos) /*!< 0xFFFFFFFF */ #define MCE_FMKEYR0_FMKEY MCE_FMKEYR0_FMKEY_Msk /*!< MCE fast master key, bits [31:0] */ /******************** Bit definition for MCE_FMKEYR1 register ***************/ #define MCE_FMKEYR1_FMKEY_Pos (0U) #define MCE_FMKEYR1_FMKEY_Msk (0xFFFFFFFFUL << MCE_FMKEYR1_FMKEY_Pos) /*!< 0xFFFFFFFF */ #define MCE_FMKEYR1_FMKEY MCE_FMKEYR1_FMKEY_Msk /*!< MCE fast master key, bits [63:32] */ /******************** Bit definition for MCE_FMKEYR2 register ***************/ #define MCE_FMKEYR2_FMKEY_Pos (0U) #define MCE_FMKEYR2_FMKEY_Msk (0xFFFFFFFFUL << MCE_FMKEYR2_FMKEY_Pos) /*!< 0xFFFFFFFF */ #define MCE_FMKEYR2_FMKEY MCE_FMKEYR2_FMKEY_Msk /*!< MCE fast master key, bits [95:64] */ /******************** Bit definition for MCE_FMKEYR3 register ***************/ #define MCE_FMKEYR3_FMKEY_Pos (0U) #define MCE_FMKEYR3_FMKEY_Msk (0xFFFFFFFFUL << MCE_FMKEYR3_FMKEY_Pos) /*!< 0xFFFFFFFF */ #define MCE_FMKEYR3_FMKEY MCE_FMKEYR3_FMKEY_Msk /*!< MCE fast master key, bits [127:96] */ /******************** Bit definition for MCE_FMKEYR4 register ****************/ #define MCE_FMKEYR4_FMKEY_Pos (0U) #define MCE_FMKEYR4_FMKEY_Msk (0xFFFFFFFFUL << MCE_FMKEYR4_FMKEY_Pos) /*!< 0xFFFFFFFF */ #define MCE_FMKEYR4_FMKEY MCE_FMKEYR4_FMKEY_Msk /*!< MCE fast master key, bits [159:128] */ /******************** Bit definition for MCE_FMKEYR5 register ****************/ #define MCE_FMKEYR5_FMKEY_Pos (0U) #define MCE_FMKEYR5_FMKEY_Msk (0xFFFFFFFFUL << MCE_FMKEYR5_FMKEY_Pos) /*!< 0xFFFFFFFF */ #define MCE_FMKEYR5_FMKEY MCE_FMKEYR5_FMKEY_Msk /*!< MCE fast master key, bits [191:160] */ /******************** Bit definition for MCE_FMKEYR6 register ****************/ #define MCE_FMKEYR6_FMKEY_Pos (0U) #define MCE_FMKEYR6_FMKEY_Msk (0xFFFFFFFFUL << MCE_FMKEYR6_FMKEY_Pos) /*!< 0xFFFFFFFF */ #define MCE_FMKEYR6_FMKEY MCE_FMKEYR6_FMKEY_Msk /*!< MCE fast master key, bits [223:192] */ /******************** Bit definition for MCE_FMKEYR7 register ****************/ #define MCE_FMKEYR7_FMKEY_Pos (0U) #define MCE_FMKEYR7_FMKEY_Msk (0xFFFFFFFFUL << MCE_FMKEYR7_FMKEY_Pos) /*!< 0xFFFFFFFF */ #define MCE_FMKEYR7_FMKEY MCE_FMKEYR7_FMKEY_Msk /*!< MCE fast master key, bits [255:224] */ /******************** Bit definition for MCE_CCCFGR register ****************/ #define MCE_CCCFGR_CCEN_Pos (0U) #define MCE_CCCFGR_CCEN_Msk (0x1UL << MCE_CCCFGR_CCEN_Pos) /*!< 0x00000001 */ #define MCE_CCCFGR_CCEN MCE_CCCFGR_CCEN_Msk /*!< MCE cipher context enable */ #define MCE_CCCFGR_CCLOCK_Pos (1U) #define MCE_CCCFGR_CCLOCK_Msk (0x1UL << MCE_CCCFGR_CCLOCK_Pos) /*!< 0x00000002 */ #define MCE_CCCFGR_CCLOCK MCE_CCCFGR_CCLOCK_Msk /*!< MCE cipher context lock */ #define MCE_CCCFGR_KEYLOCK_Pos (2U) #define MCE_CCCFGR_KEYLOCK_Msk (0x1UL << MCE_CCCFGR_KEYLOCK_Pos) /*!< 0x00000004 */ #define MCE_CCCFGR_KEYLOCK MCE_CCCFGR_KEYLOCK_Msk /*!< MCE cipher context key lock */ #define MCE_CCCFGR_MODE_Pos (4U) #define MCE_CCCFGR_MODE_Msk (0x3UL << MCE_CCCFGR_MODE_Pos) /*!< 0x00000030 */ #define MCE_CCCFGR_MODE MCE_CCCFGR_MODE_Msk /*!< MCE authorized cipher mode */ #define MCE_CCCFGR_MODE_0 (0x1UL << MCE_CCCFGR_MODE_Pos) /*!< 0x00000010 */ #define MCE_CCCFGR_MODE_1 (0x2UL << MCE_CCCFGR_MODE_Pos) /*!< 0x00000020 */ #define MCE_CCCFGR_KEYCRC_Pos (8U) #define MCE_CCCFGR_KEYCRC_Msk (0xFFUL << MCE_CCCFGR_KEYCRC_Pos) /*!< 0x0000FF00 */ #define MCE_CCCFGR_KEYCRC MCE_CCCFGR_KEYCRC_Msk /*!< MCE cipher context key CRC */ #define MCE_CCCFGR_VERSION_Pos (16U) #define MCE_CCCFGR_VERSION_Msk (0xFFFFUL << MCE_CCCFGR_VERSION_Pos) /*!< 0xFFFF0000 */ #define MCE_CCCFGR_VERSION MCE_CCCFGR_VERSION_Msk /*!< MCE cipher context version */ /******************** Bit definition for MCE_CCNR0 register *****************/ #define MCE_CCNR0_SCNONCE_Pos (0U) #define MCE_CCNR0_SCNONCE_Msk (0xFFFFFFFFUL << MCE_CCNR0_SCNONCE_Pos) /*!< 0xFFFFFFFF */ #define MCE_CCNR0_SCNONCE MCE_CCNR0_SCNONCE_Msk /*!< MCE cipher context stream cipher nonce, bits [31:0] */ /******************** Bit definition for MCE_CCNR1 register ****************/ #define MCE_CCNR1_SCNONCE_Pos (0U) #define MCE_CCNR1_SCNONCE_Msk (0xFFFFFFFFUL << MCE_CCNR1_SCNONCE_Pos) /*!< 0xFFFFFFFF */ #define MCE_CCNR1_SCNONCE MCE_CCNR1_SCNONCE_Msk /*!< MCE cipher context stream cipher nonce, bits [63:32] */ /******************** Bit definition for MCE_CCKEYR0 register ***************/ #define MCE_CCKEYR0_KEY_Pos (0U) #define MCE_CCKEYR0_KEY_Msk (0xFFFFFFFFUL << MCE_CCKEYR0_KEY_Pos) /*!< 0xFFFFFFFF */ #define MCE_CCKEYR0_KEY MCE_CCKEYR0_KEY_Msk /*!< MCE cipher context key, bits [31:0] */ /******************** Bit definition for MCE_CCKEYR1 register ***************/ #define MCE_CCKEYR1_KEY_Pos (0U) #define MCE_CCKEYR1_KEY_Msk (0xFFFFFFFFUL << MCE_CCKEYR1_KEY_Pos) /*!< 0xFFFFFFFF */ #define MCE_CCKEYR1_KEY MCE_CCKEYR1_KEY_Msk /*!< MCE fast master key, bits [63:32] */ /******************** Bit definition for MCE_CCKEYR2 register ***************/ #define MCE_CCKEYR2_KEY_Pos (0U) #define MCE_CCKEYR2_KEY_Msk (0xFFFFFFFFUL << MCE_CCKEYR2_KEY_Pos) /*!< 0xFFFFFFFF */ #define MCE_CCKEYR2_KEY MCE_CCKEYR2_KEY_Msk /*!< MCE fast master key, bits [95:64] */ /******************** Bit definition for MCE_CCKEYR3 register ***************/ #define MCE_CCKEYR3_KEY_Pos (0U) #define MCE_CCKEYR3_KEY_Msk (0xFFFFFFFFUL << MCE_CCKEYR3_KEY_Pos) /*!< 0xFFFFFFFF */ #define MCE_CCKEYR3_KEY MCE_CCKEYR3_KEY_Msk /*!< MCE fast master key, bits [127:96] */ /******************************************************************************/ /* */ /* MDF/ADF */ /* */ /******************************************************************************/ /******************* Bit definition for MDF/ADF_GCR register ****************/ #define MDF_GCR_TRGO_Pos (0U) #define MDF_GCR_TRGO_Msk (0x1UL << MDF_GCR_TRGO_Pos) /*!< 0x00000001 */ #define MDF_GCR_TRGO MDF_GCR_TRGO_Msk /*!< Trigger output control */ #define MDF_GCR_ILVNB_Pos (4U) #define MDF_GCR_ILVNB_Msk (0xFUL << MDF_GCR_ILVNB_Pos) /*!< 0x000000F0 */ #define MDF_GCR_ILVNB MDF_GCR_ILVNB_Msk /*!< Interleaved Number */ /******************* Bit definition for MDF/ADF_CKGCR register ********************/ #define MDF_CKGCR_CKDEN_Pos (0U) #define MDF_CKGCR_CKDEN_Msk (0x1UL << MDF_CKGCR_CKDEN_Pos) /*!< 0x00000001 */ #define MDF_CKGCR_CKDEN MDF_CKGCR_CKDEN_Msk /*!>2) /*!< Input modulus number of bits */ #define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ /* Compute Montgomery parameter output data */ #define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ /* Compute modular exponentiation input data */ #define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ #define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ #define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ #define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ #define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ #define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ #define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ #define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ #define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ /* Compute modular exponentiation output data */ #define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ #define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ #define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ #define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ /* Compute ECC scalar multiplication input data */ #define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ #define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ #define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ #define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ #define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ #define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ #define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ #define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ #define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ #define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ /* Compute ECC scalar multiplication output data */ #define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ #define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ #define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ /* Point check input data */ #define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ #define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ #define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ #define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ #define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ #define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ #define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ #define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ /* Point check output data */ #define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ /* ECDSA signature input data */ #define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ #define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ #define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ #define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ #define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ #define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ #define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ #define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ #define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ #define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ #define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ #define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ /* ECDSA signature output data */ #define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ #define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ #define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ #define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ #define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ /* ECDSA verification input data */ #define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ #define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ #define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ #define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ #define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ #define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ #define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ #define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ #define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ #define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ #define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ #define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ #define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ /* ECDSA verification output data */ #define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* RSA CRT exponentiation input data */ #define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ #define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ #define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ #define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ #define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ #define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ #define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ /* RSA CRT exponentiation output data */ #define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Modular reduction input data */ #define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ #define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ #define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ #define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ /* Modular reduction output data */ #define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Arithmetic addition input data */ #define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ /* Arithmetic addition output data */ #define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Arithmetic subtraction input data */ #define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ /* Arithmetic subtraction output data */ #define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Arithmetic multiplication input data */ #define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ /* Arithmetic multiplication output data */ #define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Comparison input data */ #define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ /* Comparison output data */ #define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Modular addition input data */ #define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ #define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ /* Modular addition output data */ #define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Modular inversion input data */ #define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ /* Modular inversion output data */ #define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Modular subtraction input data */ #define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ #define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ /* Modular subtraction output data */ #define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Montgomery multiplication input data */ #define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ #define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ /* Montgomery multiplication output data */ #define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Generic Arithmetic input data */ #define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ #define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ /* Generic Arithmetic output data */ #define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ /* Compute ECC complete addition input data */ #define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ #define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ #define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ #define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ #define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ #define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ #define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ #define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ #define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ #define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ /* Compute ECC complete addition output data */ #define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ #define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ #define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ /* Compute ECC double base ladder input data */ #define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ #define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ #define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ #define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ #define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ #define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ #define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ #define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ #define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ #define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ #define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ #define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ #define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ /* Compute ECC double base ladder output data */ #define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ #define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ #define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ /* Compute ECC projective to affine conversion input data */ #define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ #define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ #define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ #define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ #define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ #define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ /* Compute ECC projective to affine conversion output data */ #define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ #define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ #define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ /******************************************************************************/ /* */ /* Parallel Synchronous Slave Interface (PSSI ) */ /* */ /******************************************************************************/ /******************** Bit definition for PSSI_CR register *******************/ #define PSSI_CR_CKPOL_Pos (5U) #define PSSI_CR_CKPOL_Msk (0x1UL << PSSI_CR_CKPOL_Pos) /*!< 0x00000020 */ #define PSSI_CR_CKPOL PSSI_CR_CKPOL_Msk /*!< Parallel data clock polarity */ #define PSSI_CR_DEPOL_Pos (6U) #define PSSI_CR_DEPOL_Msk (0x1UL << PSSI_CR_DEPOL_Pos) /*!< 0x00000040 */ #define PSSI_CR_DEPOL PSSI_CR_DEPOL_Msk /*!< Data enable polarity */ #define PSSI_CR_RDYPOL_Pos (8U) #define PSSI_CR_RDYPOL_Msk (0x1UL << PSSI_CR_RDYPOL_Pos) /*!< 0x00000100 */ #define PSSI_CR_RDYPOL PSSI_CR_RDYPOL_Msk /*!< Ready polarity */ #define PSSI_CR_EDM_Pos (10U) #define PSSI_CR_EDM_Msk (0x3UL << PSSI_CR_EDM_Pos) /*!< 0x00000C00 */ #define PSSI_CR_EDM PSSI_CR_EDM_Msk /*!< Extended data mode */ #define PSSI_CR_ENABLE_Pos (14U) #define PSSI_CR_ENABLE_Msk (0x1UL << PSSI_CR_ENABLE_Pos) /*!< 0x00004000 */ #define PSSI_CR_ENABLE PSSI_CR_ENABLE_Msk /*!< PSSI enable */ #define PSSI_CR_DERDYCFG_Pos (18U) #define PSSI_CR_DERDYCFG_Msk (0x7UL << PSSI_CR_DERDYCFG_Pos) /*!< 0x001C0000 */ #define PSSI_CR_DERDYCFG PSSI_CR_DERDYCFG_Msk /*!< Data enable and ready configuration */ #define PSSI_CR_CKSRC_Pos (29U) #define PSSI_CR_CKSRC_Msk (0x1UL << PSSI_CR_CKSRC_Pos) /*!< 0x20000000 */ #define PSSI_CR_CKSRC PSSI_CR_CKSRC_Msk /*!< Clock source */ #define PSSI_CR_DMAEN_Pos (30U) #define PSSI_CR_DMAEN_Msk (0x1UL << PSSI_CR_DMAEN_Pos) /*!< 0x40000000 */ #define PSSI_CR_DMAEN PSSI_CR_DMAEN_Msk /*!< DMA enable */ #define PSSI_CR_OUTEN_Pos (31U) #define PSSI_CR_OUTEN_Msk (0x1UL << PSSI_CR_OUTEN_Pos) /*!< 0x80000000 */ #define PSSI_CR_OUTEN PSSI_CR_OUTEN_Msk /*!< Data direction selection */ /******************** Bit definition for PSSI_SR register *******************/ #define PSSI_SR_RTT4B_Pos (2U) #define PSSI_SR_RTT4B_Msk (0x1UL << PSSI_SR_RTT4B_Pos) /*!< 0x00000004 */ #define PSSI_SR_RTT4B PSSI_SR_RTT4B_Msk /*!< Ready to transfer four bytes */ #define PSSI_SR_RTT1B_Pos (3U) #define PSSI_SR_RTT1B_Msk (0x1UL << PSSI_SR_RTT1B_Pos) /*!< 0x00000008 */ #define PSSI_SR_RTT1B PSSI_SR_RTT1B_Msk /*!< Ready to transfer one byte */ /******************** Bit definition for PSSI_RIS register *******************/ #define PSSI_RIS_OVR_RIS_Pos (1U) #define PSSI_RIS_OVR_RIS_Msk (0x1UL << PSSI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */ #define PSSI_RIS_OVR_RIS PSSI_RIS_OVR_RIS_Msk /*!< Data buffer overrun/underrun raw interrupt status */ /******************** Bit definition for PSSI_IER register *******************/ #define PSSI_IER_OVR_IE_Pos (1U) #define PSSI_IER_OVR_IE_Msk (0x1UL << PSSI_IER_OVR_IE_Pos) /*!< 0x00000002 */ #define PSSI_IER_OVR_IE PSSI_IER_OVR_IE_Msk /*!< Data buffer overrun/underrun interrupt enable */ /******************** Bit definition for PSSI_MIS register *******************/ #define PSSI_MIS_OVR_MIS_Pos (1U) #define PSSI_MIS_OVR_MIS_Msk (0x1UL << PSSI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */ #define PSSI_MIS_OVR_MIS PSSI_MIS_OVR_MIS_Msk /*!< Data buffer overrun/underrun masked interrupt status */ /******************** Bit definition for PSSI_ICR register *******************/ #define PSSI_ICR_OVR_ISC_Pos (1U) #define PSSI_ICR_OVR_ISC_Msk (0x1UL << PSSI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */ #define PSSI_ICR_OVR_ISC PSSI_ICR_OVR_ISC_Msk /*!< Data buffer overrun/underrun interrupt status clear */ /******************** Bit definition for PSSI_DR register *******************/ #define PSSI_DR_DR_Pos (0U) #define PSSI_DR_DR_Msk (0xFFFFFFFFUL << PSSI_DR_DR_Pos) /*!< 0xFFFFFFF */ #define PSSI_DR_DR PSSI_DR_DR_Msk /*!< Data register */ /******************************************************************************/ /* */ /* Power Control */ /* */ /******************************************************************************/ /******************* Bit definition for PWR_CR1 register ********************/ #define PWR_CR1_SDEN_Pos (2U) #define PWR_CR1_SDEN_Msk (0x1UL << PWR_CR1_SDEN_Pos) /*!< 0x00000004 */ #define PWR_CR1_SDEN PWR_CR1_SDEN_Msk /*!< SMPS step-down converter enable */ #define PWR_CR1_MODE_PDN_Pos (4U) #define PWR_CR1_MODE_PDN_Msk (0x1UL << PWR_CR1_MODE_PDN_Pos) /*!< 0x00000010 */ #define PWR_CR1_MODE_PDN PWR_CR1_MODE_PDN_Msk /*!< Pull down on output voltage during power down mode */ #define PWR_CR1_LPDS08V_Pos (5U) #define PWR_CR1_LPDS08V_Msk (0x1UL << PWR_CR1_LPDS08V_Pos) /*!< 0x00000020 */ #define PWR_CR1_LPDS08V PWR_CR1_LPDS08V_Msk /*!< SMPS Low power mode enable (SVOS high only) */ #define PWR_CR1_VDD18SMPSVMEN_Pos (8U) #define PWR_CR1_VDD18SMPSVMEN_Msk (0x1UL << PWR_CR1_VDD18SMPSVMEN_Pos) /*!< 0x00000100 */ #define PWR_CR1_VDD18SMPSVMEN PWR_CR1_VDD18SMPSVMEN_Msk /*!< VDD18SMPS voltage monitor enable */ #define PWR_CR1_VDD18SMPSRDY_Pos (15U) #define PWR_CR1_VDD18SMPSRDY_Msk (0x1UL << PWR_CR1_VDD18SMPSRDY_Pos) /*!< 0x00008000 */ #define PWR_CR1_VDD18SMPSRDY PWR_CR1_VDD18SMPSRDY_Msk /*!< VDD18SMPS ready */ #define PWR_CR1_POPL_Pos (16U) #define PWR_CR1_POPL_Msk (0x1FUL << PWR_CR1_POPL_Pos) /*!< 0x001F0000 */ #define PWR_CR1_POPL PWR_CR1_POPL_Msk /*!< pwr_on pulse low configuration */ #define PWR_CR1_POPL_0 (0x1UL << PWR_CR1_POPL_Pos) /*!< 0x00010000 */ #define PWR_CR1_POPL_1 (0x2UL << PWR_CR1_POPL_Pos) /*!< 0x00020000 */ #define PWR_CR1_POPL_2 (0x4UL << PWR_CR1_POPL_Pos) /*!< 0x00040000 */ #define PWR_CR1_POPL_3 (0x8UL << PWR_CR1_POPL_Pos) /*!< 0x00080000 */ #define PWR_CR1_POPL_4 (0x10UL << PWR_CR1_POPL_Pos) /*!< 0x00100000 */ /******************* Bit definition for PWR_CR2 register ********************/ #define PWR_CR2_PVDEN_Pos (0U) #define PWR_CR2_PVDEN_Msk (0x1UL << PWR_CR2_PVDEN_Pos) /*!< 0x00000001 */ #define PWR_CR2_PVDEN PWR_CR2_PVDEN_Msk /*!< Programmable Voltage detector enable */ #define PWR_CR2_PVDO_Pos (8U) #define PWR_CR2_PVDO_Msk (0x1UL << PWR_CR2_PVDO_Pos) /*!< 0x00000100 */ #define PWR_CR2_PVDO PWR_CR2_PVDO_Msk /*!< Programmable Voltage Detect Output */ /******************* Bit definition for PWR_CR3 register ********************/ #define PWR_CR3_VCOREMONEN_Pos (0U) #define PWR_CR3_VCOREMONEN_Msk (0x1UL << PWR_CR3_VCOREMONEN_Pos) /*!< 0x00000001 */ #define PWR_CR3_VCOREMONEN PWR_CR3_VCOREMONEN_Msk /*!< VDDCORE monitoring enable */ #define PWR_CR3_VCORELLS_Pos (4U) #define PWR_CR3_VCORELLS_Msk (0x1UL << PWR_CR3_VCORELLS_Pos) /*!< 0x00000010 */ #define PWR_CR3_VCORELLS PWR_CR3_VCORELLS_Msk /*!< VDDCORE Voltage Detector low level selection */ #define PWR_CR3_VCOREL_Pos (8U) #define PWR_CR3_VCOREL_Msk (0x1UL << PWR_CR3_VCOREL_Pos) /*!< 0x00000100 */ #define PWR_CR3_VCOREL PWR_CR3_VCOREL_Msk /*!< Monitored VDDCORE level above low threshold */ #define PWR_CR3_VCOREH_Pos (9U) #define PWR_CR3_VCOREH_Msk (0x1UL << PWR_CR3_VCOREH_Pos) /*!< 0x00000200 */ #define PWR_CR3_VCOREH PWR_CR3_VCOREH_Msk /*!< Monitored VDDCORE level above high threshold */ /******************* Bit definition for PWR_CR4 register ********************/ #define PWR_CR4_TCMRBSEN_Pos (0U) #define PWR_CR4_TCMRBSEN_Msk (0x1UL << PWR_CR4_TCMRBSEN_Pos) /*!< 0x00000001 */ #define PWR_CR4_TCMRBSEN PWR_CR4_TCMRBSEN_Msk /*!< I-TCM and D-TCM RAMs backup supply enable (used to maintain TCM RAMs content in Standby mode) */ #define PWR_CR4_TCMFLXRBSEN_Pos (4U) #define PWR_CR4_TCMFLXRBSEN_Msk (0x1UL << PWR_CR4_TCMFLXRBSEN_Pos) /*!< 0x00000010 */ #define PWR_CR4_TCMFLXRBSEN PWR_CR4_TCMFLXRBSEN_Msk /*!< I-TCM FLEX MEM backup supply enable (used to maintain I-TCM FLEX MEM content in Standby mode) */ /****************** Bit definition for PWR_VOSCR register *******************/ #define PWR_VOSCR_VOS_Pos (0U) #define PWR_VOSCR_VOS_Msk (0x1UL << PWR_VOSCR_VOS_Pos) /*!< 0x00000001 */ #define PWR_VOSCR_VOS PWR_VOSCR_VOS_Msk /*!< Voltage scaling selection according to performance */ #define PWR_VOSCR_VOSRDY_Pos (1U) #define PWR_VOSCR_VOSRDY_Msk (0x1UL << PWR_VOSCR_VOSRDY_Pos) /*!< 0x00000002 */ #define PWR_VOSCR_VOSRDY PWR_VOSCR_VOSRDY_Msk /*!< VOS Ready bit for VCORE voltage scaling output selection */ #define PWR_VOSCR_ACTVOS_Pos (16U) #define PWR_VOSCR_ACTVOS_Msk (0x1UL << PWR_VOSCR_ACTVOS_Pos) /*!< 0x00010000 */ #define PWR_VOSCR_ACTVOS PWR_VOSCR_ACTVOS_Msk /*!< VOS currently applied for VCORE voltage scaling selection */ #define PWR_VOSCR_ACTVOSRDY_Pos (17U) #define PWR_VOSCR_ACTVOSRDY_Msk (0x1UL << PWR_VOSCR_ACTVOSRDY_Pos) /*!< 0x00020000 */ #define PWR_VOSCR_ACTVOSRDY PWR_VOSCR_ACTVOSRDY_Msk /*!< Voltage levels ready bit for currently used ACTVOS */ /****************** Bit definition for PWR_BDCR1 register *******************/ #define PWR_BDCR1_MONEN_Pos (0U) #define PWR_BDCR1_MONEN_Msk (0x1UL << PWR_BDCR1_MONEN_Pos) /*!< 0x00000001 */ #define PWR_BDCR1_MONEN PWR_BDCR1_MONEN_Msk /*!< VBAT and temperature monitoring enable */ #define PWR_BDCR1_VBATL_Pos (16U) #define PWR_BDCR1_VBATL_Msk (0x1UL << PWR_BDCR1_VBATL_Pos) /*!< 0x00010000 */ #define PWR_BDCR1_VBATL PWR_BDCR1_VBATL_Msk /*!< VBAT level monitoring versus low threshold */ #define PWR_BDCR1_VBATH_Pos (17U) #define PWR_BDCR1_VBATH_Msk (0x1UL << PWR_BDCR1_VBATH_Pos) /*!< 0x00020000 */ #define PWR_BDCR1_VBATH PWR_BDCR1_VBATH_Msk /*!< VBAT level monitoring versus high threshold */ #define PWR_BDCR1_TEMPL_Pos (18U) #define PWR_BDCR1_TEMPL_Msk (0x1UL << PWR_BDCR1_TEMPL_Pos) /*!< 0x00040000 */ #define PWR_BDCR1_TEMPL PWR_BDCR1_TEMPL_Msk /*!< Temperature level monitoring versus low threshold */ #define PWR_BDCR1_TEMPH_Pos (19U) #define PWR_BDCR1_TEMPH_Msk (0x1UL << PWR_BDCR1_TEMPH_Pos) /*!< 0x00080000 */ #define PWR_BDCR1_TEMPH PWR_BDCR1_TEMPH_Msk /*!< Temperature level monitoring versus high threshold */ /****************** Bit definition for PWR_BDCR2 register *******************/ #define PWR_BDCR2_BKPRBSEN_Pos (0U) #define PWR_BDCR2_BKPRBSEN_Msk (0x1UL << PWR_BDCR2_BKPRBSEN_Pos) /*!< 0x00000001 */ #define PWR_BDCR2_BKPRBSEN PWR_BDCR2_BKPRBSEN_Msk /*!< Backup RAM backup supply enable (used to maintain BKP RAM content in Standby and VBAT modes) */ /****************** Bit definition for PWR_DBPCR register *******************/ #define PWR_DBPCR_DBP_Pos (0U) #define PWR_DBPCR_DBP_Msk (0x1UL << PWR_DBPCR_DBP_Pos) /*!< 0x00000001 */ #define PWR_DBPCR_DBP PWR_DBPCR_DBP_Msk /*!< Disable backup domain write protection */ /****************** Bit definition for PWR_CPUCR register *******************/ #define PWR_CPUCR_PDDS_Pos (0U) #define PWR_CPUCR_PDDS_Msk (0x1UL << PWR_CPUCR_PDDS_Pos) /*!< 0x00000001 */ #define PWR_CPUCR_PDDS PWR_CPUCR_PDDS_Msk /*!< Power Down Deepsleep selection */ #define PWR_CPUCR_CSSF_Pos (1U) #define PWR_CPUCR_CSSF_Msk (0x1UL << PWR_CPUCR_CSSF_Pos) /*!< 0x00000002 */ #define PWR_CPUCR_CSSF PWR_CPUCR_CSSF_Msk /*!< Clear Standby and Stop flags (always read as 0) */ #define PWR_CPUCR_STOPF_Pos (8U) #define PWR_CPUCR_STOPF_Msk (0x1UL << PWR_CPUCR_STOPF_Pos) /*!< 0x00000100 */ #define PWR_CPUCR_STOPF PWR_CPUCR_STOPF_Msk /*!< STOP flag */ #define PWR_CPUCR_SBF_Pos (9U) #define PWR_CPUCR_SBF_Msk (0x1UL << PWR_CPUCR_SBF_Pos) /*!< 0x00000200 */ #define PWR_CPUCR_SBF PWR_CPUCR_SBF_Msk /*!< System Standby flag */ #define PWR_CPUCR_SVOS_Pos (16U) #define PWR_CPUCR_SVOS_Msk (0x1UL << PWR_CPUCR_SVOS_Pos) /*!< 0x00010000 */ #define PWR_CPUCR_SVOS PWR_CPUCR_SVOS_Msk /*!< System Stop mode voltage scaling selection */ /****************** Bit definition for PWR_SVMCR1 register ******************/ #define PWR_SVMCR1_VDDIO4VMEN_Pos (0U) #define PWR_SVMCR1_VDDIO4VMEN_Msk (0x1UL << PWR_SVMCR1_VDDIO4VMEN_Pos) /*!< 0x00000001 */ #define PWR_SVMCR1_VDDIO4VMEN PWR_SVMCR1_VDDIO4VMEN_Msk /*!< VDDOI4 Independent I/Os voltage monitor enable */ #define PWR_SVMCR1_VDDIO4SV_Pos (8U) #define PWR_SVMCR1_VDDIO4SV_Msk (0x1UL << PWR_SVMCR1_VDDIO4SV_Pos) /*!< 0x00000100 */ #define PWR_SVMCR1_VDDIO4SV PWR_SVMCR1_VDDIO4SV_Msk /*!< VDDIO4 Independent I/Os supply valid */ #define PWR_SVMCR1_VDDIO4RDY_Pos (16U) #define PWR_SVMCR1_VDDIO4RDY_Msk (0x1UL << PWR_SVMCR1_VDDIO4RDY_Pos) /*!< 0x00010000 */ #define PWR_SVMCR1_VDDIO4RDY PWR_SVMCR1_VDDIO4RDY_Msk /*!< VDDIO4 ready */ #define PWR_SVMCR1_VDDIO4VRSEL_Pos (24U) #define PWR_SVMCR1_VDDIO4VRSEL_Msk (0x1UL << PWR_SVMCR1_VDDIO4VRSEL_Pos) /*!< 0x01000000 */ #define PWR_SVMCR1_VDDIO4VRSEL PWR_SVMCR1_VDDIO4VRSEL_Msk /*!< VDDIO4 IO voltage range selection */ #define PWR_SVMCR1_VDDIO4VRSTBY_Pos (25U) #define PWR_SVMCR1_VDDIO4VRSTBY_Msk (0x1UL << PWR_SVMCR1_VDDIO4VRSTBY_Pos) /*!< 0x04000000 */ #define PWR_SVMCR1_VDDIO4VRSTBY PWR_SVMCR1_VDDIO4VRSTBY_Msk /*!< VDDIO4 IO voltage range standby mode */ /****************** Bit definition for PWR_SVMCR2 register ******************/ #define PWR_SVMCR2_VDDIO5VMEN_Pos (0U) #define PWR_SVMCR2_VDDIO5VMEN_Msk (0x1UL << PWR_SVMCR2_VDDIO5VMEN_Pos) /*!< 0x00000001 */ #define PWR_SVMCR2_VDDIO5VMEN PWR_SVMCR2_VDDIO5VMEN_Msk /*!< VDDIO5 Independent voltage monitor enable */ #define PWR_SVMCR2_VDDIO5SV_Pos (8U) #define PWR_SVMCR2_VDDIO5SV_Msk (0x1UL << PWR_SVMCR2_VDDIO5SV_Pos) /*!< 0x00000100 */ #define PWR_SVMCR2_VDDIO5SV PWR_SVMCR2_VDDIO5SV_Msk /*!< VDDIO5 Independent supply valid */ #define PWR_SVMCR2_VDDIO5RDY_Pos (16U) #define PWR_SVMCR2_VDDIO5RDY_Msk (0x1UL << PWR_SVMCR2_VDDIO5RDY_Pos) /*!< 0x00010000 */ #define PWR_SVMCR2_VDDIO5RDY PWR_SVMCR2_VDDIO5RDY_Msk /*!< VDDIO5 ready */ #define PWR_SVMCR2_VDDIO5VRSEL_Pos (24U) #define PWR_SVMCR2_VDDIO5VRSEL_Msk (0x1UL << PWR_SVMCR2_VDDIO5VRSEL_Pos) /*!< 0x01000000 */ #define PWR_SVMCR2_VDDIO5VRSEL PWR_SVMCR2_VDDIO5VRSEL_Msk /*!< VDDIO5 IO voltage range selection */ #define PWR_SVMCR2_VDDIO5VRSTBY_Pos (25U) #define PWR_SVMCR2_VDDIO5VRSTBY_Msk (0x1UL << PWR_SVMCR2_VDDIO5VRSTBY_Pos) /*!< 0x02000000 */ #define PWR_SVMCR2_VDDIO5VRSTBY PWR_SVMCR2_VDDIO5VRSTBY_Msk /*!< VDDIO5 IO voltage range standby mode */ /****************** Bit definition for PWR_SVMCR3 register ******************/ #define PWR_SVMCR3_VDDIO2VMEN_Pos (0U) #define PWR_SVMCR3_VDDIO2VMEN_Msk (0x1UL << PWR_SVMCR3_VDDIO2VMEN_Pos) /*!< 0x00000001 */ #define PWR_SVMCR3_VDDIO2VMEN PWR_SVMCR3_VDDIO2VMEN_Msk /*!< VDDIO2 Independent voltage monitor enable */ #define PWR_SVMCR3_VDDIO3VMEN_Pos (1U) #define PWR_SVMCR3_VDDIO3VMEN_Msk (0x1UL << PWR_SVMCR3_VDDIO3VMEN_Pos) /*!< 0x00000002 */ #define PWR_SVMCR3_VDDIO3VMEN PWR_SVMCR3_VDDIO3VMEN_Msk /*!< VDDIO3 Independent voltage monitor enable */ #define PWR_SVMCR3_USB33VMEN_Pos (2U) #define PWR_SVMCR3_USB33VMEN_Msk (0x1UL << PWR_SVMCR3_USB33VMEN_Pos) /*!< 0x00000004 */ #define PWR_SVMCR3_USB33VMEN PWR_SVMCR3_USB33VMEN_Msk /*!< VDD33USB Independent USB 33 voltage monitor enable */ #define PWR_SVMCR3_AVMEN_Pos (4U) #define PWR_SVMCR3_AVMEN_Msk (0x1UL << PWR_SVMCR3_AVMEN_Pos) /*!< 0x00000010 */ #define PWR_SVMCR3_AVMEN PWR_SVMCR3_AVMEN_Msk /*!< VDDA18ADC Independent ADC voltage monitor enable */ #define PWR_SVMCR3_VDDIO2SV_Pos (8U) #define PWR_SVMCR3_VDDIO2SV_Msk (0x1UL << PWR_SVMCR3_VDDIO2SV_Pos) /*!< 0x00000100 */ #define PWR_SVMCR3_VDDIO2SV PWR_SVMCR3_VDDIO2SV_Msk /*!< VDDIO2 Independent supply valid */ #define PWR_SVMCR3_VDDIO3SV_Pos (9U) #define PWR_SVMCR3_VDDIO3SV_Msk (0x1UL << PWR_SVMCR3_VDDIO3SV_Pos) /*!< 0x00000200 */ #define PWR_SVMCR3_VDDIO3SV PWR_SVMCR3_VDDIO3SV_Msk /*!< VDDIO3 Independent supply valid */ #define PWR_SVMCR3_USB33SV_Pos (10U) #define PWR_SVMCR3_USB33SV_Msk (0x1UL << PWR_SVMCR3_USB33SV_Pos) /*!< 0x00000400 */ #define PWR_SVMCR3_USB33SV PWR_SVMCR3_USB33SV_Msk /*!< VDD33USB Independent supply valid */ #define PWR_SVMCR3_ASV_Pos (12U) #define PWR_SVMCR3_ASV_Msk (0x1UL << PWR_SVMCR3_ASV_Pos) /*!< 0x00001000 */ #define PWR_SVMCR3_ASV PWR_SVMCR3_ASV_Msk /*!< VDDA18ADC Independent supply valid */ #define PWR_SVMCR3_VDDIO2RDY_Pos (16U) #define PWR_SVMCR3_VDDIO2RDY_Msk (0x1UL << PWR_SVMCR3_VDDIO2RDY_Pos) /*!< 0x00010000 */ #define PWR_SVMCR3_VDDIO2RDY PWR_SVMCR3_VDDIO2RDY_Msk /*!< VDDIO2 ready */ #define PWR_SVMCR3_VDDIO3RDY_Pos (17U) #define PWR_SVMCR3_VDDIO3RDY_Msk (0x1UL << PWR_SVMCR3_VDDIO3RDY_Pos) /*!< 0x00020000 */ #define PWR_SVMCR3_VDDIO3RDY PWR_SVMCR3_VDDIO3RDY_Msk /*!< VDDIO3 ready */ #define PWR_SVMCR3_USB33RDY_Pos (18U) #define PWR_SVMCR3_USB33RDY_Msk (0x1UL << PWR_SVMCR3_USB33RDY_Pos) /*!< 0x00040000 */ #define PWR_SVMCR3_USB33RDY PWR_SVMCR3_USB33RDY_Msk /*!< VDD33USB ready */ #define PWR_SVMCR3_ARDY_Pos (20U) #define PWR_SVMCR3_ARDY_Msk (0x1UL << PWR_SVMCR3_ARDY_Pos) /*!< 0x00100000 */ #define PWR_SVMCR3_ARDY PWR_SVMCR3_ARDY_Msk /*!< VDDA18ADC ready */ #define PWR_SVMCR3_VDDIOVRSEL_Pos (24U) #define PWR_SVMCR3_VDDIOVRSEL_Msk (0x1UL << PWR_SVMCR3_VDDIOVRSEL_Pos) /*!< 0x01000000 */ #define PWR_SVMCR3_VDDIOVRSEL PWR_SVMCR3_VDDIOVRSEL_Msk /*!< VDD IO voltage range selection */ #define PWR_SVMCR3_VDDIO2VRSEL_Pos (25U) #define PWR_SVMCR3_VDDIO2VRSEL_Msk (0x1UL << PWR_SVMCR3_VDDIO2VRSEL_Pos) /*!< 0x02000000 */ #define PWR_SVMCR3_VDDIO2VRSEL PWR_SVMCR3_VDDIO2VRSEL_Msk /*!< VDDIO2 IO voltage range selection */ #define PWR_SVMCR3_VDDIO3VRSEL_Pos (26U) #define PWR_SVMCR3_VDDIO3VRSEL_Msk (0x1UL << PWR_SVMCR3_VDDIO3VRSEL_Pos) /*!< 0x04000000 */ #define PWR_SVMCR3_VDDIO3VRSEL PWR_SVMCR3_VDDIO3VRSEL_Msk /*!< VDDIO3 IO voltage range selection */ /***************** Bit definition for PWR_WKUPCR register *******************/ #define PWR_WKUPCR_WKUPC1_Pos (0U) #define PWR_WKUPCR_WKUPC1_Msk (0x1UL << PWR_WKUPCR_WKUPC1_Pos) /*!< 0x00000001 */ #define PWR_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1_Msk /*!< Clear Wakeup Flag for WKUP1 pin */ #define PWR_WKUPCR_WKUPC2_Pos (1U) #define PWR_WKUPCR_WKUPC2_Msk (0x1UL << PWR_WKUPCR_WKUPC2_Pos) /*!< 0x00000002 */ #define PWR_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2_Msk /*!< Clear Wakeup Flag for WKUP2 pin */ #define PWR_WKUPCR_WKUPC3_Pos (2U) #define PWR_WKUPCR_WKUPC3_Msk (0x1UL << PWR_WKUPCR_WKUPC3_Pos) /*!< 0x00000004 */ #define PWR_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3_Msk /*!< Clear Wakeup Flag for WKUP3 pin */ #define PWR_WKUPCR_WKUPC4_Pos (3U) #define PWR_WKUPCR_WKUPC4_Msk (0x1UL << PWR_WKUPCR_WKUPC4_Pos) /*!< 0x00000008 */ #define PWR_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4_Msk /*!< Clear Wakeup Flag for WKUP4 pin */ #define PWR_WKUPCR_WKUPC_Pos (0U) #define PWR_WKUPCR_WKUPC_Msk (0xFUL << PWR_WKUPCR_WKUPC_Pos) /*!< 0x0000000F */ #define PWR_WKUPCR_WKUPC PWR_WKUPCR_WKUPC_Msk /*!< Clear Wakeup Flag 1 to 4 */ /***************** Bit definition for PWR_WKUPSR register *******************/ #define PWR_WKUPSR_WKUPF1_Pos (0U) #define PWR_WKUPSR_WKUPF1_Msk (0x1UL << PWR_WKUPSR_WKUPF1_Pos) /*!< 0x00000001 */ #define PWR_WKUPSR_WKUPF1 PWR_WKUPSR_WKUPF1_Msk /*!< Wakeup Flag for WKUP1 pin */ #define PWR_WKUPSR_WKUPF2_Pos (1U) #define PWR_WKUPSR_WKUPF2_Msk (0x1UL << PWR_WKUPSR_WKUPF2_Pos) /*!< 0x00000002 */ #define PWR_WKUPSR_WKUPF2 PWR_WKUPSR_WKUPF2_Msk /*!< Wakeup Flag for WKUP2 pin */ #define PWR_WKUPSR_WKUPF3_Pos (2U) #define PWR_WKUPSR_WKUPF3_Msk (0x1UL << PWR_WKUPSR_WKUPF3_Pos) /*!< 0x00000004 */ #define PWR_WKUPSR_WKUPF3 PWR_WKUPSR_WKUPF3_Msk /*!< Wakeup Flag for WKUP3 pin */ #define PWR_WKUPSR_WKUPF4_Pos (3U) #define PWR_WKUPSR_WKUPF4_Msk (0x1UL << PWR_WKUPSR_WKUPF4_Pos) /*!< 0x00000008 */ #define PWR_WKUPSR_WKUPF4 PWR_WKUPSR_WKUPF4_Msk /*!< Wakeup Flag for WKUP4 pin */ /***************** Bit definition for PWR_WKUPEPR register *******************/ #define PWR_WKUPEPR_WKUPEN1_Pos (0U) #define PWR_WKUPEPR_WKUPEN1_Msk (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos) /*!< 0x00000001 */ #define PWR_WKUPEPR_WKUPEN1 PWR_WKUPEPR_WKUPEN1_Msk /*!< Enable Wakeup pin WKUP1 */ #define PWR_WKUPEPR_WKUPEN2_Pos (1U) #define PWR_WKUPEPR_WKUPEN2_Msk (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos) /*!< 0x00000002 */ #define PWR_WKUPEPR_WKUPEN2 PWR_WKUPEPR_WKUPEN2_Msk /*!< Enable Wakeup pin WKUP2 */ #define PWR_WKUPEPR_WKUPEN3_Pos (2U) #define PWR_WKUPEPR_WKUPEN3_Msk (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos) /*!< 0x00000004 */ #define PWR_WKUPEPR_WKUPEN3 PWR_WKUPEPR_WKUPEN3_Msk /*!< Enable Wakeup pin WKUP3 */ #define PWR_WKUPEPR_WKUPEN4_Pos (3U) #define PWR_WKUPEPR_WKUPEN4_Msk (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos) /*!< 0x00000008 */ #define PWR_WKUPEPR_WKUPEN4 PWR_WKUPEPR_WKUPEN4_Msk /*!< Enable Wakeup pin WKUP4 */ #define PWR_WKUPEPR_WKUPP1_Pos (8U) #define PWR_WKUPEPR_WKUPP1_Msk (0x1UL << PWR_WKUPEPR_WKUPP1_Pos) /*!< 0x00000100 */ #define PWR_WKUPEPR_WKUPP1 PWR_WKUPEPR_WKUPP1_Msk /*!< Wakeup Polarity bit for WKUP1 pin */ #define PWR_WKUPEPR_WKUPP2_Pos (9U) #define PWR_WKUPEPR_WKUPP2_Msk (0x1UL << PWR_WKUPEPR_WKUPP2_Pos) /*!< 0x00000200 */ #define PWR_WKUPEPR_WKUPP2 PWR_WKUPEPR_WKUPP2_Msk /*!< Wakeup Polarity bit for WKUP2 pin */ #define PWR_WKUPEPR_WKUPP3_Pos (10U) #define PWR_WKUPEPR_WKUPP3_Msk (0x1UL << PWR_WKUPEPR_WKUPP3_Pos) /*!< 0x00000400 */ #define PWR_WKUPEPR_WKUPP3 PWR_WKUPEPR_WKUPP3_Msk /*!< Wakeup Polarity bit for WKUP3 pin */ #define PWR_WKUPEPR_WKUPP4_Pos (11U) #define PWR_WKUPEPR_WKUPP4_Msk (0x1UL << PWR_WKUPEPR_WKUPP4_Pos) /*!< 0x00000800 */ #define PWR_WKUPEPR_WKUPP4 PWR_WKUPEPR_WKUPP4_Msk /*!< Wakeup Polarity bit for WKUP4 pin */ #define PWR_WKUPEPR_WKUPP_Pos (8U) #define PWR_WKUPEPR_WKUPP_Msk (0x0FUL << PWR_WKUPEPR_WKUPP_Pos) /*!< 0x0000300F */ #define PWR_WKUPEPR_WKUPP PWR_WKUPEPR_WKUPP_Msk /*!< Wakeup Pin Polarity for WKUP1 to WKUP4 */ #define PWR_WKUPEPR_WKUPPUPD1_Pos (16U) #define PWR_WKUPEPR_WKUPPUPD1_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00030000 */ #define PWR_WKUPEPR_WKUPPUPD1 PWR_WKUPEPR_WKUPPUPD1_Msk /*!< Wakeup pull configuration for WKUP1 pin */ #define PWR_WKUPEPR_WKUPPUPD1_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00010000 */ #define PWR_WKUPEPR_WKUPPUPD1_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00020000 */ #define PWR_WKUPEPR_WKUPPUPD2_Pos (18U) #define PWR_WKUPEPR_WKUPPUPD2_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x000C0000 */ #define PWR_WKUPEPR_WKUPPUPD2 PWR_WKUPEPR_WKUPPUPD2_Msk /*!< Wakeup pull configuration for WKUP2 pin */ #define PWR_WKUPEPR_WKUPPUPD2_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x00040000 */ #define PWR_WKUPEPR_WKUPPUPD2_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x00080000 */ #define PWR_WKUPEPR_WKUPPUPD3_Pos (20U) #define PWR_WKUPEPR_WKUPPUPD3_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00300000 */ #define PWR_WKUPEPR_WKUPPUPD3 PWR_WKUPEPR_WKUPPUPD3_Msk /*!< Wakeup pull configuration for WKUP3 pin */ #define PWR_WKUPEPR_WKUPPUPD3_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00100000 */ #define PWR_WKUPEPR_WKUPPUPD3_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00200000 */ #define PWR_WKUPEPR_WKUPPUPD4_Pos (22U) #define PWR_WKUPEPR_WKUPPUPD4_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00C00000 */ #define PWR_WKUPEPR_WKUPPUPD4 PWR_WKUPEPR_WKUPPUPD4_Msk /*!< Wakeup pull configuration for WKUP4 pin */ #define PWR_WKUPEPR_WKUPPUPD4_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00400000 */ #define PWR_WKUPEPR_WKUPPUPD4_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00800000 */ #define PWR_WKUPEPR_WKUPEN_Pos (0U) #define PWR_WKUPEPR_WKUPEN_Msk (0x0FUL << PWR_WKUPEPR_WKUPEN_Pos) /*!< 0x0000003F */ #define PWR_WKUPEPR_WKUPEN PWR_WKUPEPR_WKUPEN_Msk /*!< Enable all Wakeup Pin */ /***************** Bit definition for PWR_SECCFGR register ******************/ #define PWR_SECCFGR_SEC0_Pos (0U) #define PWR_SECCFGR_SEC0_Msk (0x1UL << PWR_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ #define PWR_SECCFGR_SEC0 PWR_SECCFGR_SEC0_Msk /*!< System supply configuration secure protection */ #define PWR_SECCFGR_SEC1_Pos (1U) #define PWR_SECCFGR_SEC1_Msk (0x1UL << PWR_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ #define PWR_SECCFGR_SEC1 PWR_SECCFGR_SEC1_Msk /*!< Programmable voltage detector secure protection */ #define PWR_SECCFGR_SEC2_Pos (2U) #define PWR_SECCFGR_SEC2_Msk (0x1UL << PWR_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ #define PWR_SECCFGR_SEC2 PWR_SECCFGR_SEC2_Msk /*!< VDDCORE monitor secure protection */ #define PWR_SECCFGR_SEC3_Pos (3U) #define PWR_SECCFGR_SEC3_Msk (0x1UL << PWR_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ #define PWR_SECCFGR_SEC3 PWR_SECCFGR_SEC3_Msk /*!< I-TCM/D-TCM and I-TCM FLEX MEM low power control secure protection */ #define PWR_SECCFGR_SEC4_Pos (4U) #define PWR_SECCFGR_SEC4_Msk (0x1UL << PWR_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ #define PWR_SECCFGR_SEC4 PWR_SECCFGR_SEC4_Msk /*!< Voltage scaling selection secure protection */ #define PWR_SECCFGR_SEC5_Pos (5U) #define PWR_SECCFGR_SEC5_Msk (0x1UL << PWR_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ #define PWR_SECCFGR_SEC5 PWR_SECCFGR_SEC5_Msk /*!< Backup domain secure protection */ #define PWR_SECCFGR_SEC6_Pos (6U) #define PWR_SECCFGR_SEC6_Msk (0x1UL << PWR_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ #define PWR_SECCFGR_SEC6 PWR_SECCFGR_SEC6_Msk /*!< CPU power control secure protection */ #define PWR_SECCFGR_SEC7_Pos (7U) #define PWR_SECCFGR_SEC7_Msk (0x1UL << PWR_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ #define PWR_SECCFGR_SEC7 PWR_SECCFGR_SEC7_Msk /*!< Peripheral voltage monitor secure protection */ #define PWR_SECCFGR_WKUPSEC1_Pos (16U) #define PWR_SECCFGR_WKUPSEC1_Msk (0x1UL << PWR_SECCFGR_WKUPSEC1_Pos) /*!< 0x00010000 */ #define PWR_SECCFGR_WKUPSEC1 PWR_SECCFGR_WKUPSEC1_Msk /*!< WKUP1 secure protection */ #define PWR_SECCFGR_WKUPSEC2_Pos (17U) #define PWR_SECCFGR_WKUPSEC2_Msk (0x1UL << PWR_SECCFGR_WKUPSEC2_Pos) /*!< 0x00020000 */ #define PWR_SECCFGR_WKUPSEC2 PWR_SECCFGR_WKUPSEC2_Msk /*!< WKUP2 secure protection */ #define PWR_SECCFGR_WKUPSEC3_Pos (18U) #define PWR_SECCFGR_WKUPSEC3_Msk (0x1UL << PWR_SECCFGR_WKUPSEC3_Pos) /*!< 0x00040000 */ #define PWR_SECCFGR_WKUPSEC3 PWR_SECCFGR_WKUPSEC3_Msk /*!< WKUP3 secure protection */ #define PWR_SECCFGR_WKUPSEC4_Pos (19U) #define PWR_SECCFGR_WKUPSEC4_Msk (0x1UL << PWR_SECCFGR_WKUPSEC4_Pos) /*!< 0x00080000 */ #define PWR_SECCFGR_WKUPSEC4 PWR_SECCFGR_WKUPSEC4_Msk /*!< WKUP4 secure protection */ /***************** Bit definition for PWR_PRIVCFGR register *****************/ #define PWR_PRIVCFGR_PRIV0_Pos (0U) #define PWR_PRIVCFGR_PRIV0_Msk (0x1UL << PWR_PRIVCFGR_PRIV0_Pos) /*!< 0x00000001 */ #define PWR_PRIVCFGR_PRIV0 PWR_PRIVCFGR_PRIV0_Msk /*!< System supply configuration privileged protection */ #define PWR_PRIVCFGR_PRIV1_Pos (1U) #define PWR_PRIVCFGR_PRIV1_Msk (0x1UL << PWR_PRIVCFGR_PRIV1_Pos) /*!< 0x00000002 */ #define PWR_PRIVCFGR_PRIV1 PWR_PRIVCFGR_PRIV1_Msk /*!< Programmable voltage detector privileged protection */ #define PWR_PRIVCFGR_PRIV2_Pos (2U) #define PWR_PRIVCFGR_PRIV2_Msk (0x1UL << PWR_PRIVCFGR_PRIV2_Pos) /*!< 0x00000004 */ #define PWR_PRIVCFGR_PRIV2 PWR_PRIVCFGR_PRIV2_Msk /*!< VDDCORE monitor privileged protection */ #define PWR_PRIVCFGR_PRIV3_Pos (3U) #define PWR_PRIVCFGR_PRIV3_Msk (0x1UL << PWR_PRIVCFGR_PRIV3_Pos) /*!< 0x00000008 */ #define PWR_PRIVCFGR_PRIV3 PWR_PRIVCFGR_PRIV3_Msk /*!< I-TCM/D-TCM and I-TCM FLEX MEM low power control privileged protection */ #define PWR_PRIVCFGR_PRIV4_Pos (4U) #define PWR_PRIVCFGR_PRIV4_Msk (0x1UL << PWR_PRIVCFGR_PRIV4_Pos) /*!< 0x00000010 */ #define PWR_PRIVCFGR_PRIV4 PWR_PRIVCFGR_PRIV4_Msk /*!< Voltage scaling selection privileged protection */ #define PWR_PRIVCFGR_PRIV5_Pos (5U) #define PWR_PRIVCFGR_PRIV5_Msk (0x1UL << PWR_PRIVCFGR_PRIV5_Pos) /*!< 0x00000020 */ #define PWR_PRIVCFGR_PRIV5 PWR_PRIVCFGR_PRIV5_Msk /*!< Backup domain privileged protection */ #define PWR_PRIVCFGR_PRIV6_Pos (6U) #define PWR_PRIVCFGR_PRIV6_Msk (0x1UL << PWR_PRIVCFGR_PRIV6_Pos) /*!< 0x00000040 */ #define PWR_PRIVCFGR_PRIV6 PWR_PRIVCFGR_PRIV6_Msk /*!< CPU power control privileged protection */ #define PWR_PRIVCFGR_PRIV7_Pos (7U) #define PWR_PRIVCFGR_PRIV7_Msk (0x1UL << PWR_PRIVCFGR_PRIV7_Pos) /*!< 0x00000080 */ #define PWR_PRIVCFGR_PRIV7 PWR_PRIVCFGR_PRIV7_Msk /*!< Peripheral voltage monitor privileged protection */ #define PWR_PRIVCFGR_WKUPPRIV1_Pos (16U) #define PWR_PRIVCFGR_WKUPPRIV1_Msk (0x1UL << PWR_PRIVCFGR_WKUPPRIV1_Pos) /*!< 0x00010000 */ #define PWR_PRIVCFGR_WKUPPRIV1 PWR_PRIVCFGR_WKUPPRIV1_Msk /*!< WKUP1 privileged protection */ #define PWR_PRIVCFGR_WKUPPRIV2_Pos (17U) #define PWR_PRIVCFGR_WKUPPRIV2_Msk (0x1UL << PWR_PRIVCFGR_WKUPPRIV2_Pos) /*!< 0x00020000 */ #define PWR_PRIVCFGR_WKUPPRIV2 PWR_PRIVCFGR_WKUPPRIV2_Msk /*!< WKUP2 privileged protection */ #define PWR_PRIVCFGR_WKUPPRIV3_Pos (18U) #define PWR_PRIVCFGR_WKUPPRIV3_Msk (0x1UL << PWR_PRIVCFGR_WKUPPRIV3_Pos) /*!< 0x00040000 */ #define PWR_PRIVCFGR_WKUPPRIV3 PWR_PRIVCFGR_WKUPPRIV3_Msk /*!< WKUP3 privileged protection */ #define PWR_PRIVCFGR_WKUPPRIV4_Pos (19U) #define PWR_PRIVCFGR_WKUPPRIV4_Msk (0x1UL << PWR_PRIVCFGR_WKUPPRIV4_Pos) /*!< 0x00080000 */ #define PWR_PRIVCFGR_WKUPPRIV4 PWR_PRIVCFGR_WKUPPRIV4_Msk /*!< WKUP4 privileged protection */ /******************************************************************************/ /* */ /* RAMs configuration controller */ /* */ /******************************************************************************/ /******************* Bit definition for RAMCFG_CR register ******************/ #define RAMCFG_CR_ECCE_Pos (0U) #define RAMCFG_CR_ECCE_Msk (0x1UL << RAMCFG_CR_ECCE_Pos) /*!< 0x00000001 */ #define RAMCFG_CR_ECCE RAMCFG_CR_ECCE_Msk /*!< ECC Enable */ #define RAMCFG_CR_ALE_Pos (4U) #define RAMCFG_CR_ALE_Msk (0x1UL << RAMCFG_CR_ALE_Pos) /*!< 0x00000010 */ #define RAMCFG_CR_ALE RAMCFG_CR_ALE_Msk /*!< Address Latching Enable */ #define RAMCFG_CR_SRAMER_Pos (8U) #define RAMCFG_CR_SRAMER_Msk (0x1UL << RAMCFG_CR_SRAMER_Pos) /*!< 0x00000100 */ #define RAMCFG_CR_SRAMER RAMCFG_CR_SRAMER_Msk /*!< Start Erase */ #define RAMCFG_CR_SRAMHWERDIS_Pos (12U) #define RAMCFG_CR_SRAMHWERDIS_Msk (0x1UL << RAMCFG_CR_SRAMHWERDIS_Pos) /*!< 0x00001000 */ #define RAMCFG_CR_SRAMHWERDIS RAMCFG_CR_SRAMHWERDIS_Msk /*!< SRAM hardware erase disable */ #define RAMCFG_CR_ITCMCFG_Pos (16U) #define RAMCFG_CR_ITCMCFG_Msk (0x3UL << RAMCFG_CR_ITCMCFG_Pos) /*!< 0x00030000 */ #define RAMCFG_CR_ITCMCFG RAMCFG_CR_ITCMCFG_Msk /*!< Configuration of the FLEXMEM D-TCM extension */ #define RAMCFG_CR_ITCMCFG_0 (0x1UL << RAMCFG_CR_ITCMCFG_Pos) /*!< 0x00010000 */ #define RAMCFG_CR_ITCMCFG_1 (0x2UL << RAMCFG_CR_ITCMCFG_Pos) /*!< 0x00020000 */ #define RAMCFG_CR_SRAMSD_Pos (20U) #define RAMCFG_CR_SRAMSD_Msk (0x1UL << RAMCFG_CR_SRAMSD_Pos) /*!< 0x00100000 */ #define RAMCFG_CR_SRAMSD RAMCFG_CR_SRAMSD_Msk /*!< Shutdown AXISRAMx */ #define RAMCFG_CR_DTCMCFG_Pos (24U) #define RAMCFG_CR_DTCMCFG_Msk (0x1UL << RAMCFG_CR_DTCMCFG_Pos) /*!< 0x01000000 */ #define RAMCFG_CR_DTCMCFG RAMCFG_CR_DTCMCFG_Msk /*!< Configuration of the FLEXMEM D-TCM extension */ /******************* Bit definition for RAMCFG_IER register *****************/ #define RAMCFG_IER_SEIE_Pos (0U) #define RAMCFG_IER_SEIE_Msk (0x1UL << RAMCFG_IER_SEIE_Pos) /*!< 0x00000001 */ #define RAMCFG_IER_SEIE RAMCFG_IER_SEIE_Msk /*!< Single Error Interrupt Enable */ #define RAMCFG_IER_DEIE_Pos (1U) #define RAMCFG_IER_DEIE_Msk (0x1UL << RAMCFG_IER_DEIE_Pos) /*!< 0x00000002 */ #define RAMCFG_IER_DEIE RAMCFG_IER_DEIE_Msk /*!< Double Error Interrupt Enable */ /******************* Bit definition for RAMCFG_ISR register *****************/ #define RAMCFG_ISR_SEDC_Pos (0U) #define RAMCFG_ISR_SEDC_Msk (0x1UL << RAMCFG_ISR_SEDC_Pos) /*!< 0x00000001 */ #define RAMCFG_ISR_SEDC RAMCFG_ISR_SEDC_Msk /*!< Single Error Detected and Corrected flag */ #define RAMCFG_ISR_DED_Pos (1U) #define RAMCFG_ISR_DED_Msk (0x1UL << RAMCFG_ISR_DED_Pos) /*!< 0x00000002 */ #define RAMCFG_ISR_DED RAMCFG_ISR_DED_Msk /*!< Double Error Detected flag */ #define RAMCFG_ISR_SRAMBUSY_Pos (8U) #define RAMCFG_ISR_SRAMBUSY_Msk (0x1UL << RAMCFG_ISR_SRAMBUSY_Pos) /*!< 0x00000100 */ #define RAMCFG_ISR_SRAMBUSY RAMCFG_ISR_SRAMBUSY_Msk /*!< SRAM busy flag */ /******************* Bit definition for RAMCFG_ESEAR register ****************/ #define RAMCFG_ESEAR_ESEA_Pos (0U) #define RAMCFG_ESEAR_ESEA_Msk (0x7FFUL << RAMCFG_ESEAR_ESEA_Pos) /*!< 0x000007FF */ #define RAMCFG_ESEAR_ESEA RAMCFG_ESEAR_ESEA_Msk /*!< ECC Single Error Address */ /******************* Bit definition for RAMCFG_EDEAR register ****************/ #define RAMCFG_EDEAR_EDEA_Pos (0U) #define RAMCFG_EDEAR_EDEA_Msk (0x7FFUL << RAMCFG_EDEAR_EDEA_Pos) /*!< 0x000007FF */ #define RAMCFG_EDEAR_EDEA RAMCFG_EDEAR_EDEA_Msk /*!< ECC Double Error Address */ /******************* Bit definition for RAMCFG_ICR register *****************/ #define RAMCFG_ICR_CSEDC_Pos (0U) #define RAMCFG_ICR_CSEDC_Msk (0x1UL << RAMCFG_ICR_CSEDC_Pos) /*!< 0x00000001 */ #define RAMCFG_ICR_CSEDC RAMCFG_ICR_CSEDC_Msk /*!< Clear ECC Single Error Detected and Corrected Flag */ #define RAMCFG_ICR_CDED_Pos (1U) #define RAMCFG_ICR_CDED_Msk (0x1UL << RAMCFG_ICR_CDED_Pos) /*!< 0x00000002 */ #define RAMCFG_ICR_CDED RAMCFG_ICR_CDED_Msk /*!< Clear ECC Double Error Detected Flag*/ /***************** Bit definition for RAMCFG_ECCKEYR register ***************/ #define RAMCFG_ECCKEYR_ECCKEY_Pos (0U) #define RAMCFG_ECCKEYR_ECCKEY_Msk (0xFFUL << RAMCFG_ECCKEYR_ECCKEY_Pos) /*!< 0x000000FF */ #define RAMCFG_ECCKEYR_ECCKEY RAMCFG_ECCKEYR_ECCKEY_Msk /*!< ECC Write Protection Key */ /***************** Bit definition for RAMCFG_ERKEYR register ****************/ #define RAMCFG_ERKEYR_ERASEKEY_Pos (0U) #define RAMCFG_ERKEYR_ERASEKEY_Msk (0xFFUL << RAMCFG_ERKEYR_ERASEKEY_Pos) /*!< 0x000000FF */ #define RAMCFG_ERKEYR_ERASEKEY RAMCFG_ERKEYR_ERASEKEY_Msk /*!< Erase Write Protection Key */ /******************************************************************************/ /* */ /* (RCC) */ /* */ /******************************************************************************/ /******************** Bit definition for RCC_CR register ********************/ #define RCC_CR_LSION_Pos (0U) #define RCC_CR_LSION_Msk (0x1UL << RCC_CR_LSION_Pos) /*!< 0x00000001 */ #define RCC_CR_LSION RCC_CR_LSION_Msk /*!< LSI oscillator enable */ #define RCC_CR_LSEON_Pos (1U) #define RCC_CR_LSEON_Msk (0x1UL << RCC_CR_LSEON_Pos) /*!< 0x00000002 */ #define RCC_CR_LSEON RCC_CR_LSEON_Msk /*!< LSE oscillator enable */ #define RCC_CR_MSION_Pos (2U) #define RCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos) /*!< 0x00000004 */ #define RCC_CR_MSION RCC_CR_MSION_Msk /*!< MSI oscillator enable */ #define RCC_CR_HSION_Pos (3U) #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000008 */ #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< HSI oscillator enable */ #define RCC_CR_HSEON_Pos (4U) #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00000010 */ #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< HSE oscillator enable */ #define RCC_CR_PLL1ON_Pos (8U) #define RCC_CR_PLL1ON_Msk (0x1UL << RCC_CR_PLL1ON_Pos) /*!< 0x00000100 */ #define RCC_CR_PLL1ON RCC_CR_PLL1ON_Msk /*!< PLL1 enable */ #define RCC_CR_PLL2ON_Pos (9U) #define RCC_CR_PLL2ON_Msk (0x1UL << RCC_CR_PLL2ON_Pos) /*!< 0x00000200 */ #define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk /*!< PLL2 enable */ #define RCC_CR_PLL3ON_Pos (10U) #define RCC_CR_PLL3ON_Msk (0x1UL << RCC_CR_PLL3ON_Pos) /*!< 0x00000400 */ #define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk /*!< PLL3 enable */ #define RCC_CR_PLL4ON_Pos (11U) #define RCC_CR_PLL4ON_Msk (0x1UL << RCC_CR_PLL4ON_Pos) /*!< 0x00000800 */ #define RCC_CR_PLL4ON RCC_CR_PLL4ON_Msk /*!< PLL4 enable */ /******************** Bit definition for RCC_SR register ********************/ #define RCC_SR_LSIRDY_Pos (0U) #define RCC_SR_LSIRDY_Msk (0x1UL << RCC_SR_LSIRDY_Pos) /*!< 0x00000001 */ #define RCC_SR_LSIRDY RCC_SR_LSIRDY_Msk /*!< LSI clock ready flag */ #define RCC_SR_LSERDY_Pos (1U) #define RCC_SR_LSERDY_Msk (0x1UL << RCC_SR_LSERDY_Pos) /*!< 0x00000002 */ #define RCC_SR_LSERDY RCC_SR_LSERDY_Msk /*!< LSE clock ready flag */ #define RCC_SR_MSIRDY_Pos (2U) #define RCC_SR_MSIRDY_Msk (0x1UL << RCC_SR_MSIRDY_Pos) /*!< 0x00000004 */ #define RCC_SR_MSIRDY RCC_SR_MSIRDY_Msk /*!< MSI clock ready flag */ #define RCC_SR_HSIRDY_Pos (3U) #define RCC_SR_HSIRDY_Msk (0x1UL << RCC_SR_HSIRDY_Pos) /*!< 0x00000008 */ #define RCC_SR_HSIRDY RCC_SR_HSIRDY_Msk /*!< HSI clock ready flag */ #define RCC_SR_HSERDY_Pos (4U) #define RCC_SR_HSERDY_Msk (0x1UL << RCC_SR_HSERDY_Pos) /*!< 0x00000010 */ #define RCC_SR_HSERDY RCC_SR_HSERDY_Msk /*!< HSE clock ready flag */ #define RCC_SR_PLL1RDY_Pos (8U) #define RCC_SR_PLL1RDY_Msk (0x1UL << RCC_SR_PLL1RDY_Pos) /*!< 0x00000100 */ #define RCC_SR_PLL1RDY RCC_SR_PLL1RDY_Msk /*!< PLL1 clock ready flag */ #define RCC_SR_PLL2RDY_Pos (9U) #define RCC_SR_PLL2RDY_Msk (0x1UL << RCC_SR_PLL2RDY_Pos) /*!< 0x00000200 */ #define RCC_SR_PLL2RDY RCC_SR_PLL2RDY_Msk /*!< PLL2 clock ready flag */ #define RCC_SR_PLL3RDY_Pos (10U) #define RCC_SR_PLL3RDY_Msk (0x1UL << RCC_SR_PLL3RDY_Pos) /*!< 0x00000400 */ #define RCC_SR_PLL3RDY RCC_SR_PLL3RDY_Msk /*!< PLL3 clock ready flag */ #define RCC_SR_PLL4RDY_Pos (11U) #define RCC_SR_PLL4RDY_Msk (0x1UL << RCC_SR_PLL4RDY_Pos) /*!< 0x00000800 */ #define RCC_SR_PLL4RDY RCC_SR_PLL4RDY_Msk /*!< PLL4 clock ready flag */ /****************** Bit definition for RCC_STOPCR register ******************/ #define RCC_STOPCR_MSISTOPEN_Pos (0U) #define RCC_STOPCR_MSISTOPEN_Msk (0x1UL << RCC_STOPCR_MSISTOPEN_Pos) /*!< 0x00000001 */ #define RCC_STOPCR_MSISTOPEN RCC_STOPCR_MSISTOPEN_Msk /*!< MSI oscillator enable */ #define RCC_STOPCR_HSISTOPEN_Pos (1U) #define RCC_STOPCR_HSISTOPEN_Msk (0x1UL << RCC_STOPCR_HSISTOPEN_Pos) /*!< 0x00000002 */ #define RCC_STOPCR_HSISTOPEN RCC_STOPCR_HSISTOPEN_Msk /*!< HSI oscillator enable */ /****************** Bit definition for RCC_CFGR1 register *******************/ #define RCC_CFGR1_STOPWUCK_Pos (0U) #define RCC_CFGR1_STOPWUCK_Msk (0x1UL << RCC_CFGR1_STOPWUCK_Pos) /*!< 0x00000001 */ #define RCC_CFGR1_STOPWUCK RCC_CFGR1_STOPWUCK_Msk /*!< System clock selection after a wake up from system stop */ #define RCC_CFGR1_CPUSW_Pos (16U) #define RCC_CFGR1_CPUSW_Msk (0x3UL << RCC_CFGR1_CPUSW_Pos) /*!< 0x00030000 */ #define RCC_CFGR1_CPUSW RCC_CFGR1_CPUSW_Msk /*!< CPU clock switch selection */ #define RCC_CFGR1_CPUSW_0 (0x1UL << RCC_CFGR1_CPUSW_Pos) /*!< 0x00010000 */ #define RCC_CFGR1_CPUSW_1 (0x2UL << RCC_CFGR1_CPUSW_Pos) /*!< 0x00020000 */ #define RCC_CFGR1_CPUSWS_Pos (20U) #define RCC_CFGR1_CPUSWS_Msk (0x3UL << RCC_CFGR1_CPUSWS_Pos) /*!< 0x00300000 */ #define RCC_CFGR1_CPUSWS RCC_CFGR1_CPUSWS_Msk /*!< CPU clock switch status */ #define RCC_CFGR1_CPUSWS_0 (0x1UL << RCC_CFGR1_CPUSWS_Pos) /*!< 0x00100000 */ #define RCC_CFGR1_CPUSWS_1 (0x2UL << RCC_CFGR1_CPUSWS_Pos) /*!< 0x00200000 */ #define RCC_CFGR1_SYSSW_Pos (24U) #define RCC_CFGR1_SYSSW_Msk (0x3UL << RCC_CFGR1_SYSSW_Pos) /*!< 0x03000000 */ #define RCC_CFGR1_SYSSW RCC_CFGR1_SYSSW_Msk /*!< System clock switch selection */ #define RCC_CFGR1_SYSSW_0 (0x1UL << RCC_CFGR1_SYSSW_Pos) /*!< 0x01000000 */ #define RCC_CFGR1_SYSSW_1 (0x2UL << RCC_CFGR1_SYSSW_Pos) /*!< 0x02000000 */ #define RCC_CFGR1_SYSSWS_Pos (28U) #define RCC_CFGR1_SYSSWS_Msk (0x3UL << RCC_CFGR1_SYSSWS_Pos) /*!< 0x30000000 */ #define RCC_CFGR1_SYSSWS RCC_CFGR1_SYSSWS_Msk /*!< System clock switch status */ #define RCC_CFGR1_SYSSWS_0 (0x1UL << RCC_CFGR1_SYSSWS_Pos) /*!< 0x10000000 */ #define RCC_CFGR1_SYSSWS_1 (0x2UL << RCC_CFGR1_SYSSWS_Pos) /*!< 0x20000000 */ /****************** Bit definition for RCC_CFGR2 register *******************/ #define RCC_CFGR2_PPRE1_Pos (0U) #define RCC_CFGR2_PPRE1_Msk (0x7UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000007 */ #define RCC_CFGR2_PPRE1 RCC_CFGR2_PPRE1_Msk /*!< CPU domain APB1 prescaler */ #define RCC_CFGR2_PPRE1_0 (0x1UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000001 */ #define RCC_CFGR2_PPRE1_1 (0x2UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000002 */ #define RCC_CFGR2_PPRE1_2 (0x4UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000004 */ #define RCC_CFGR2_PPRE2_Pos (4U) #define RCC_CFGR2_PPRE2_Msk (0x7UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000070 */ #define RCC_CFGR2_PPRE2 RCC_CFGR2_PPRE2_Msk /*!< CPU domain APB2 prescaler */ #define RCC_CFGR2_PPRE2_0 (0x1UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000010 */ #define RCC_CFGR2_PPRE2_1 (0x2UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000020 */ #define RCC_CFGR2_PPRE2_2 (0x4UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000040 */ #define RCC_CFGR2_PPRE4_Pos (12U) #define RCC_CFGR2_PPRE4_Msk (0x7UL << RCC_CFGR2_PPRE4_Pos) /*!< 0x00007000 */ #define RCC_CFGR2_PPRE4 RCC_CFGR2_PPRE4_Msk /*!< CPU domain APB4 prescaler */ #define RCC_CFGR2_PPRE4_0 (0x1UL << RCC_CFGR2_PPRE4_Pos) /*!< 0x00001000 */ #define RCC_CFGR2_PPRE4_1 (0x2UL << RCC_CFGR2_PPRE4_Pos) /*!< 0x00002000 */ #define RCC_CFGR2_PPRE4_2 (0x4UL << RCC_CFGR2_PPRE4_Pos) /*!< 0x00004000 */ #define RCC_CFGR2_PPRE5_Pos (16U) #define RCC_CFGR2_PPRE5_Msk (0x7UL << RCC_CFGR2_PPRE5_Pos) /*!< 0x00070000 */ #define RCC_CFGR2_PPRE5 RCC_CFGR2_PPRE5_Msk /*!< CPU domain APB5 prescaler */ #define RCC_CFGR2_PPRE5_0 (0x1UL << RCC_CFGR2_PPRE5_Pos) /*!< 0x00010000 */ #define RCC_CFGR2_PPRE5_1 (0x2UL << RCC_CFGR2_PPRE5_Pos) /*!< 0x00020000 */ #define RCC_CFGR2_PPRE5_2 (0x4UL << RCC_CFGR2_PPRE5_Pos) /*!< 0x00040000 */ #define RCC_CFGR2_HPRE_Pos (20U) #define RCC_CFGR2_HPRE_Msk (0x7UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00700000 */ #define RCC_CFGR2_HPRE RCC_CFGR2_HPRE_Msk /*!< AHB clock prescaler */ #define RCC_CFGR2_HPRE_0 (0x1UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00100000 */ #define RCC_CFGR2_HPRE_1 (0x2UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00200000 */ #define RCC_CFGR2_HPRE_2 (0x4UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00400000 */ #define RCC_CFGR2_TIMPRE_Pos (24U) #define RCC_CFGR2_TIMPRE_Msk (0x3UL << RCC_CFGR2_TIMPRE_Pos) /*!< 0x03000000 */ #define RCC_CFGR2_TIMPRE RCC_CFGR2_TIMPRE_Msk /*!< Timer clock prescaler selection */ #define RCC_CFGR2_TIMPRE_0 (0x1UL << RCC_CFGR2_TIMPRE_Pos) /*!< 0x01000000 */ #define RCC_CFGR2_TIMPRE_1 (0x2UL << RCC_CFGR2_TIMPRE_Pos) /*!< 0x02000000 */ /******************* Bit definition for RCC_BDCR register *******************/ #define RCC_BDCR_VSWRST_Pos (31U) #define RCC_BDCR_VSWRST_Msk (0x1UL << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ #define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*!< Vswitch (VSW) domain software reset */ /****************** Bit definition for RCC_HWRSR register *******************/ #define RCC_HWRSR_RMVF_Pos (16U) #define RCC_HWRSR_RMVF_Msk (0x1UL << RCC_HWRSR_RMVF_Pos) /*!< 0x00010000 */ #define RCC_HWRSR_RMVF RCC_HWRSR_RMVF_Msk /*!< Remove reset flag */ #define RCC_HWRSR_LCKRSTF_Pos (17U) #define RCC_HWRSR_LCKRSTF_Msk (0x1UL << RCC_HWRSR_LCKRSTF_Pos) /*!< 0x00020000 */ #define RCC_HWRSR_LCKRSTF RCC_HWRSR_LCKRSTF_Msk /*!< CPU lockup reset flag */ #define RCC_HWRSR_BORRSTF_Pos (21U) #define RCC_HWRSR_BORRSTF_Msk (0x1UL << RCC_HWRSR_BORRSTF_Pos) /*!< 0x00200000 */ #define RCC_HWRSR_BORRSTF RCC_HWRSR_BORRSTF_Msk /*!< BOR reset flag */ #define RCC_HWRSR_PINRSTF_Pos (22U) #define RCC_HWRSR_PINRSTF_Msk (0x1UL << RCC_HWRSR_PINRSTF_Pos) /*!< 0x00400000 */ #define RCC_HWRSR_PINRSTF RCC_HWRSR_PINRSTF_Msk /*!< Pin reset flag (NRST) */ #define RCC_HWRSR_PORRSTF_Pos (23U) #define RCC_HWRSR_PORRSTF_Msk (0x1UL << RCC_HWRSR_PORRSTF_Pos) /*!< 0x00800000 */ #define RCC_HWRSR_PORRSTF RCC_HWRSR_PORRSTF_Msk /*!< POR/PDR reset flag */ #define RCC_HWRSR_SFTRSTF_Pos (24U) #define RCC_HWRSR_SFTRSTF_Msk (0x1UL << RCC_HWRSR_SFTRSTF_Pos) /*!< 0x01000000 */ #define RCC_HWRSR_SFTRSTF RCC_HWRSR_SFTRSTF_Msk /*!< Software system reset flag */ #define RCC_HWRSR_IWDGRSTF_Pos (26U) #define RCC_HWRSR_IWDGRSTF_Msk (0x1UL << RCC_HWRSR_IWDGRSTF_Pos) /*!< 0x04000000 */ #define RCC_HWRSR_IWDGRSTF RCC_HWRSR_IWDGRSTF_Msk /*!< Independent watchdog reset flag */ #define RCC_HWRSR_WWDGRSTF_Pos (28U) #define RCC_HWRSR_WWDGRSTF_Msk (0x1UL << RCC_HWRSR_WWDGRSTF_Pos) /*!< 0x10000000 */ #define RCC_HWRSR_WWDGRSTF RCC_HWRSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ #define RCC_HWRSR_LPWRRSTF_Pos (30U) #define RCC_HWRSR_LPWRRSTF_Msk (0x1UL << RCC_HWRSR_LPWRRSTF_Pos) /*!< 0x40000000 */ #define RCC_HWRSR_LPWRRSTF RCC_HWRSR_LPWRRSTF_Msk /*!< Illegal Stop or Standby flag */ /******************* Bit definition for RCC_RSR register ********************/ #define RCC_RSR_RMVF_Pos (16U) #define RCC_RSR_RMVF_Msk (0x1UL << RCC_RSR_RMVF_Pos) /*!< 0x00010000 */ #define RCC_RSR_RMVF RCC_RSR_RMVF_Msk /*!< Remove reset flag */ #define RCC_RSR_LCKRSTF_Pos (17U) #define RCC_RSR_LCKRSTF_Msk (0x1UL << RCC_RSR_LCKRSTF_Pos) /*!< 0x00020000 */ #define RCC_RSR_LCKRSTF RCC_RSR_LCKRSTF_Msk /*!< CPU lockup reset flag */ #define RCC_RSR_BORRSTF_Pos (21U) #define RCC_RSR_BORRSTF_Msk (0x1UL << RCC_RSR_BORRSTF_Pos) /*!< 0x00200000 */ #define RCC_RSR_BORRSTF RCC_RSR_BORRSTF_Msk /*!< BOR reset flag */ #define RCC_RSR_PINRSTF_Pos (22U) #define RCC_RSR_PINRSTF_Msk (0x1UL << RCC_RSR_PINRSTF_Pos) /*!< 0x00400000 */ #define RCC_RSR_PINRSTF RCC_RSR_PINRSTF_Msk /*!< Pin reset flag (NRST) */ #define RCC_RSR_PORRSTF_Pos (23U) #define RCC_RSR_PORRSTF_Msk (0x1UL << RCC_RSR_PORRSTF_Pos) /*!< 0x00800000 */ #define RCC_RSR_PORRSTF RCC_RSR_PORRSTF_Msk /*!< POR/PDR reset flag */ #define RCC_RSR_SFTRSTF_Pos (24U) #define RCC_RSR_SFTRSTF_Msk (0x1UL << RCC_RSR_SFTRSTF_Pos) /*!< 0x01000000 */ #define RCC_RSR_SFTRSTF RCC_RSR_SFTRSTF_Msk /*!< Software system reset flag */ #define RCC_RSR_IWDGRSTF_Pos (26U) #define RCC_RSR_IWDGRSTF_Msk (0x1UL << RCC_RSR_IWDGRSTF_Pos) /*!< 0x04000000 */ #define RCC_RSR_IWDGRSTF RCC_RSR_IWDGRSTF_Msk /*!< Independent watchdog reset flag */ #define RCC_RSR_WWDGRSTF_Pos (28U) #define RCC_RSR_WWDGRSTF_Msk (0x1UL << RCC_RSR_WWDGRSTF_Pos) /*!< 0x10000000 */ #define RCC_RSR_WWDGRSTF RCC_RSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ #define RCC_RSR_LPWRRSTF_Pos (30U) #define RCC_RSR_LPWRRSTF_Msk (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x40000000 */ #define RCC_RSR_LPWRRSTF RCC_RSR_LPWRRSTF_Msk /*!< Illegal Stop or Standby flag */ /***************** Bit definition for RCC_LSECFGR register ******************/ #define RCC_LSECFGR_LSECSSON_Pos (7U) #define RCC_LSECFGR_LSECSSON_Msk (0x1UL << RCC_LSECFGR_LSECSSON_Pos) /*!< 0x00000080 */ #define RCC_LSECFGR_LSECSSON RCC_LSECFGR_LSECSSON_Msk /*!< LSE clock security system (CSS) enable */ #define RCC_LSECFGR_LSECSSRA_Pos (8U) #define RCC_LSECFGR_LSECSSRA_Msk (0x1UL << RCC_LSECFGR_LSECSSRA_Pos) /*!< 0x00000100 */ #define RCC_LSECFGR_LSECSSRA RCC_LSECFGR_LSECSSRA_Msk /*!< LSE clock security system (CSS) rearm function */ #define RCC_LSECFGR_LSECSSD_Pos (9U) #define RCC_LSECFGR_LSECSSD_Msk (0x1UL << RCC_LSECFGR_LSECSSD_Pos) /*!< 0x00000200 */ #define RCC_LSECFGR_LSECSSD RCC_LSECFGR_LSECSSD_Msk /*!< LSE clock security system (CSS) failure detection */ #define RCC_LSECFGR_LSEBYP_Pos (15U) #define RCC_LSECFGR_LSEBYP_Msk (0x1UL << RCC_LSECFGR_LSEBYP_Pos) /*!< 0x00008000 */ #define RCC_LSECFGR_LSEBYP RCC_LSECFGR_LSEBYP_Msk /*!< LSE clock bypass */ #define RCC_LSECFGR_LSEEXT_Pos (16U) #define RCC_LSECFGR_LSEEXT_Msk (0x1UL << RCC_LSECFGR_LSEEXT_Pos) /*!< 0x00010000 */ #define RCC_LSECFGR_LSEEXT RCC_LSECFGR_LSEEXT_Msk /*!< LSE clock type in bypass mode */ #define RCC_LSECFGR_LSEGFON_Pos (17U) #define RCC_LSECFGR_LSEGFON_Msk (0x1UL << RCC_LSECFGR_LSEGFON_Pos) /*!< 0x00020000 */ #define RCC_LSECFGR_LSEGFON RCC_LSECFGR_LSEGFON_Msk /*!< LSE clock glitch filter enable */ #define RCC_LSECFGR_LSEDRV_Pos (18U) #define RCC_LSECFGR_LSEDRV_Msk (0x3UL << RCC_LSECFGR_LSEDRV_Pos) /*!< 0x000C0000 */ #define RCC_LSECFGR_LSEDRV RCC_LSECFGR_LSEDRV_Msk /*!< LSE oscillator driving capability */ #define RCC_LSECFGR_LSEDRV_0 (0x1UL << RCC_LSECFGR_LSEDRV_Pos) /*!< 0x00040000 */ #define RCC_LSECFGR_LSEDRV_1 (0x2UL << RCC_LSECFGR_LSEDRV_Pos) /*!< 0x00080000 */ /***************** Bit definition for RCC_MSICFGR register ******************/ #define RCC_MSICFGR_MSIFREQSEL_Pos (9U) #define RCC_MSICFGR_MSIFREQSEL_Msk (0x1UL << RCC_MSICFGR_MSIFREQSEL_Pos) /*!< 0x00000200 */ #define RCC_MSICFGR_MSIFREQSEL RCC_MSICFGR_MSIFREQSEL_Msk /*!< MSI oscillator frequency selection */ #define RCC_MSICFGR_MSITRIM_Pos (16U) #define RCC_MSICFGR_MSITRIM_Msk (0x1FUL << RCC_MSICFGR_MSITRIM_Pos) /*!< 0x001F0000 */ #define RCC_MSICFGR_MSITRIM RCC_MSICFGR_MSITRIM_Msk /*!< MSI clock trimming */ #define RCC_MSICFGR_MSICAL_Pos (23U) #define RCC_MSICFGR_MSICAL_Msk (0xFFUL << RCC_MSICFGR_MSICAL_Pos) /*!< 0x7F800000 */ #define RCC_MSICFGR_MSICAL RCC_MSICFGR_MSICAL_Msk /*!< MSI clock calibration */ /***************** Bit definition for RCC_HSICFGR register ******************/ #define RCC_HSICFGR_HSIDIV_Pos (7U) #define RCC_HSICFGR_HSIDIV_Msk (0x3UL << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000180 */ #define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /*!< HSI clock divider */ #define RCC_HSICFGR_HSIDIV_0 (0x1UL << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000080 */ #define RCC_HSICFGR_HSIDIV_1 (0x2UL << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000100 */ #define RCC_HSICFGR_HSITRIM_Pos (16U) #define RCC_HSICFGR_HSITRIM_Msk (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x007F0000 */ #define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSI clock trimming */ #define RCC_HSICFGR_HSICAL_Pos (23U) #define RCC_HSICFGR_HSICAL_Msk (0x1FFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0xFF800000 */ #define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSI clock calibration */ /****************** Bit definition for RCC_HSIMCR register ******************/ #define RCC_HSIMCR_HSIREF_Pos (0U) #define RCC_HSIMCR_HSIREF_Msk (0x7FFUL << RCC_HSIMCR_HSIREF_Pos) /*!< 0x000007FF */ #define RCC_HSIMCR_HSIREF RCC_HSIMCR_HSIREF_Msk /*!< HSI clock-cycle counter reference value */ #define RCC_HSIMCR_HSIDEV_Pos (16U) #define RCC_HSIMCR_HSIDEV_Msk (0x3FUL << RCC_HSIMCR_HSIDEV_Pos) /*!< 0x003F0000 */ #define RCC_HSIMCR_HSIDEV RCC_HSIMCR_HSIDEV_Msk /*!< HSI clock count deviation value */ #define RCC_HSIMCR_HSIMONEN_Pos (31U) #define RCC_HSIMCR_HSIMONEN_Msk (0x1UL << RCC_HSIMCR_HSIMONEN_Pos) /*!< 0x80000000 */ #define RCC_HSIMCR_HSIMONEN RCC_HSIMCR_HSIMONEN_Msk /*!< HSI clock period monitor enable */ /****************** Bit definition for RCC_HSIMSR register ******************/ #define RCC_HSIMSR_HSIVAL_Pos (0U) #define RCC_HSIMSR_HSIVAL_Msk (0x7FFUL << RCC_HSIMSR_HSIVAL_Pos) /*!< 0x000007FF */ #define RCC_HSIMSR_HSIVAL RCC_HSIMSR_HSIVAL_Msk /*!< HSI clock-cycle counter measured value */ /***************** Bit definition for RCC_HSECFGR register ******************/ #define RCC_HSECFGR_HSEDIV2SEL_Pos (6U) #define RCC_HSECFGR_HSEDIV2SEL_Msk (0x1UL << RCC_HSECFGR_HSEDIV2SEL_Pos) /*!< 0x00000040 */ #define RCC_HSECFGR_HSEDIV2SEL RCC_HSECFGR_HSEDIV2SEL_Msk /*!< HSE div2 clock source select */ #define RCC_HSECFGR_HSECSSON_Pos (7U) #define RCC_HSECFGR_HSECSSON_Msk (0x1UL << RCC_HSECFGR_HSECSSON_Pos) /*!< 0x00000080 */ #define RCC_HSECFGR_HSECSSON RCC_HSECFGR_HSECSSON_Msk /*!< HSE CSS enable */ #define RCC_HSECFGR_HSECSSD_Pos (9U) #define RCC_HSECFGR_HSECSSD_Msk (0x1UL << RCC_HSECFGR_HSECSSD_Pos) /*!< 0x00000200 */ #define RCC_HSECFGR_HSECSSD RCC_HSECFGR_HSECSSD_Msk /*!< HSE CSS failure detection */ #define RCC_HSECFGR_HSECSSBYP_Pos (10U) #define RCC_HSECFGR_HSECSSBYP_Msk (0x1UL << RCC_HSECFGR_HSECSSBYP_Pos) /*!< 0x00000400 */ #define RCC_HSECFGR_HSECSSBYP RCC_HSECFGR_HSECSSBYP_Msk /*!< HSE CSS bypass enable */ #define RCC_HSECFGR_HSECSSBPRE_Pos (11U) #define RCC_HSECFGR_HSECSSBPRE_Msk (0xFUL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00007800 */ #define RCC_HSECFGR_HSECSSBPRE RCC_HSECFGR_HSECSSBPRE_Msk /*!< HSE CSS bypass divider */ #define RCC_HSECFGR_HSECSSBPRE_0 (0x1UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00000800 */ #define RCC_HSECFGR_HSECSSBPRE_1 (0x2UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00001000 */ #define RCC_HSECFGR_HSECSSBPRE_2 (0x4UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00002000 */ #define RCC_HSECFGR_HSECSSBPRE_3 (0x8UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00004000 */ #define RCC_HSECFGR_HSEBYP_Pos (15U) #define RCC_HSECFGR_HSEBYP_Msk (0x1UL << RCC_HSECFGR_HSEBYP_Pos) /*!< 0x00008000 */ #define RCC_HSECFGR_HSEBYP RCC_HSECFGR_HSEBYP_Msk /*!< HSE clock bypass */ #define RCC_HSECFGR_HSEEXT_Pos (16U) #define RCC_HSECFGR_HSEEXT_Msk (0x1UL << RCC_HSECFGR_HSEEXT_Pos) /*!< 0x00010000 */ #define RCC_HSECFGR_HSEEXT RCC_HSECFGR_HSEEXT_Msk /*!< HSE clock type in bypass mode */ /**************** Bit definition for RCC_PLL1CFGR1 register *****************/ #define RCC_PLL1CFGR1_PLL1DIVN_Pos (8U) #define RCC_PLL1CFGR1_PLL1DIVN_Msk (0xFFFUL << RCC_PLL1CFGR1_PLL1DIVN_Pos) /*!< 0x000FFF00 */ #define RCC_PLL1CFGR1_PLL1DIVN RCC_PLL1CFGR1_PLL1DIVN_Msk /*!< PLL1 integer part for the VCO multiplication factor */ #define RCC_PLL1CFGR1_PLL1DIVM_Pos (20U) #define RCC_PLL1CFGR1_PLL1DIVM_Msk (0x3FUL << RCC_PLL1CFGR1_PLL1DIVM_Pos)/*!< 0x03F00000 */ #define RCC_PLL1CFGR1_PLL1DIVM RCC_PLL1CFGR1_PLL1DIVM_Msk /*!< PLL1 reference input clock divide frequency ratio */ #define RCC_PLL1CFGR1_PLL1BYP_Pos (27U) #define RCC_PLL1CFGR1_PLL1BYP_Msk (0x1UL << RCC_PLL1CFGR1_PLL1BYP_Pos) /*!< 0x08000000 */ #define RCC_PLL1CFGR1_PLL1BYP RCC_PLL1CFGR1_PLL1BYP_Msk /*!< PLL1 bypass */ #define RCC_PLL1CFGR1_PLL1SEL_Pos (28U) #define RCC_PLL1CFGR1_PLL1SEL_Msk (0x7UL << RCC_PLL1CFGR1_PLL1SEL_Pos) /*!< 0x70000000 */ #define RCC_PLL1CFGR1_PLL1SEL RCC_PLL1CFGR1_PLL1SEL_Msk /*!< PLL1 source selection of the reference clock */ #define RCC_PLL1CFGR1_PLL1SEL_0 (0x1UL << RCC_PLL1CFGR1_PLL1SEL_Pos) /*!< 0x10000000 */ #define RCC_PLL1CFGR1_PLL1SEL_1 (0x2UL << RCC_PLL1CFGR1_PLL1SEL_Pos) /*!< 0x20000000 */ #define RCC_PLL1CFGR1_PLL1SEL_2 (0x4UL << RCC_PLL1CFGR1_PLL1SEL_Pos) /*!< 0x40000000 */ /**************** Bit definition for RCC_PLL1CFGR2 register *****************/ #define RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos (0U) #define RCC_PLL1CFGR2_PLL1DIVNFRAC_Msk (0xFFFFFFUL << RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos) /*!< 0x00FFFFFF */ #define RCC_PLL1CFGR2_PLL1DIVNFRAC RCC_PLL1CFGR2_PLL1DIVNFRAC_Msk /*!< PLL1 fractional part of the VCO multiplication factor */ /**************** Bit definition for RCC_PLL1CFGR3 register *****************/ #define RCC_PLL1CFGR3_PLL1MODSSRST_Pos (0U) #define RCC_PLL1CFGR3_PLL1MODSSRST_Msk (0x1UL << RCC_PLL1CFGR3_PLL1MODSSRST_Pos) /*!< 0x00000001 */ #define RCC_PLL1CFGR3_PLL1MODSSRST RCC_PLL1CFGR3_PLL1MODSSRST_Msk /*!< PLL1 modulation spread spectrum reset */ #define RCC_PLL1CFGR3_PLL1DACEN_Pos (1U) #define RCC_PLL1CFGR3_PLL1DACEN_Msk (0x1UL << RCC_PLL1CFGR3_PLL1DACEN_Pos)/*!< 0x00000002 */ #define RCC_PLL1CFGR3_PLL1DACEN RCC_PLL1CFGR3_PLL1DACEN_Msk /*!< PLL1 noise canceling DAC enable in fractional mode */ #define RCC_PLL1CFGR3_PLL1MODSSDIS_Pos (2U) #define RCC_PLL1CFGR3_PLL1MODSSDIS_Msk (0x1UL << RCC_PLL1CFGR3_PLL1MODSSDIS_Pos) /*!< 0x00000004 */ #define RCC_PLL1CFGR3_PLL1MODSSDIS RCC_PLL1CFGR3_PLL1MODSSDIS_Msk /*!< PLL1 modulation spread spectrum disable */ #define RCC_PLL1CFGR3_PLL1MODDSEN_Pos (3U) #define RCC_PLL1CFGR3_PLL1MODDSEN_Msk (0x1UL << RCC_PLL1CFGR3_PLL1MODDSEN_Pos) /*!< 0x00000008 */ #define RCC_PLL1CFGR3_PLL1MODDSEN RCC_PLL1CFGR3_PLL1MODDSEN_Msk /*!< PLL1 modulation spread spectrum (and fractional divide) enable */ #define RCC_PLL1CFGR3_PLL1MODSPRDW_Pos (4U) #define RCC_PLL1CFGR3_PLL1MODSPRDW_Msk (0x1UL << RCC_PLL1CFGR3_PLL1MODSPRDW_Pos) /*!< 0x00000010 */ #define RCC_PLL1CFGR3_PLL1MODSPRDW RCC_PLL1CFGR3_PLL1MODSPRDW_Msk /*!< PLL1 modulation spread spectrum down */ #define RCC_PLL1CFGR3_PLL1MODDIV_Pos (8U) #define RCC_PLL1CFGR3_PLL1MODDIV_Msk (0xFUL << RCC_PLL1CFGR3_PLL1MODDIV_Pos) /*!< 0x00000F00 */ #define RCC_PLL1CFGR3_PLL1MODDIV RCC_PLL1CFGR3_PLL1MODDIV_Msk /*!< PLL1 modulation division frequency adjustment */ #define RCC_PLL1CFGR3_PLL1MODSPR_Pos (16U) #define RCC_PLL1CFGR3_PLL1MODSPR_Msk (0x1FUL << RCC_PLL1CFGR3_PLL1MODSPR_Pos) /*!< 0x001F0000 */ #define RCC_PLL1CFGR3_PLL1MODSPR RCC_PLL1CFGR3_PLL1MODSPR_Msk /*!< PLL1 modulation spread depth adjustment */ #define RCC_PLL1CFGR3_PLL1PDIV2_Pos (24U) #define RCC_PLL1CFGR3_PLL1PDIV2_Msk (0x7UL << RCC_PLL1CFGR3_PLL1PDIV2_Pos)/*!< 0x07000000 */ #define RCC_PLL1CFGR3_PLL1PDIV2 RCC_PLL1CFGR3_PLL1PDIV2_Msk /*!< PLL1 VCO frequency divider level 2 */ #define RCC_PLL1CFGR3_PLL1PDIV1_Pos (27U) #define RCC_PLL1CFGR3_PLL1PDIV1_Msk (0x7UL << RCC_PLL1CFGR3_PLL1PDIV1_Pos)/*!< 0x38000000 */ #define RCC_PLL1CFGR3_PLL1PDIV1 RCC_PLL1CFGR3_PLL1PDIV1_Msk /*!< PLL1 VCO frequency divider level 1 */ #define RCC_PLL1CFGR3_PLL1PDIVEN_Pos (30U) #define RCC_PLL1CFGR3_PLL1PDIVEN_Msk (0x1UL << RCC_PLL1CFGR3_PLL1PDIVEN_Pos) /*!< 0x40000000 */ #define RCC_PLL1CFGR3_PLL1PDIVEN RCC_PLL1CFGR3_PLL1PDIVEN_Msk /*!< PLL1 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */ /**************** Bit definition for RCC_PLL2CFGR1 register *****************/ #define RCC_PLL2CFGR1_PLL2DIVN_Pos (8U) #define RCC_PLL2CFGR1_PLL2DIVN_Msk (0xFFFUL << RCC_PLL2CFGR1_PLL2DIVN_Pos) /*!< 0x000FFF00 */ #define RCC_PLL2CFGR1_PLL2DIVN RCC_PLL2CFGR1_PLL2DIVN_Msk /*!< PLL2 integer part for the VCO multiplication factor */ #define RCC_PLL2CFGR1_PLL2DIVM_Pos (20U) #define RCC_PLL2CFGR1_PLL2DIVM_Msk (0x3FUL << RCC_PLL2CFGR1_PLL2DIVM_Pos)/*!< 0x03F00000 */ #define RCC_PLL2CFGR1_PLL2DIVM RCC_PLL2CFGR1_PLL2DIVM_Msk /*!< PLL2 reference input clock divide frequency ratio */ #define RCC_PLL2CFGR1_PLL2BYP_Pos (27U) #define RCC_PLL2CFGR1_PLL2BYP_Msk (0x1UL << RCC_PLL2CFGR1_PLL2BYP_Pos) /*!< 0x08000000 */ #define RCC_PLL2CFGR1_PLL2BYP RCC_PLL2CFGR1_PLL2BYP_Msk /*!< PLL2 bypass */ #define RCC_PLL2CFGR1_PLL2SEL_Pos (28U) #define RCC_PLL2CFGR1_PLL2SEL_Msk (0x7UL << RCC_PLL2CFGR1_PLL2SEL_Pos) /*!< 0x70000000 */ #define RCC_PLL2CFGR1_PLL2SEL RCC_PLL2CFGR1_PLL2SEL_Msk /*!< PLL2 source selection of the reference clock */ #define RCC_PLL2CFGR1_PLL2SEL_0 (0x1UL << RCC_PLL2CFGR1_PLL2SEL_Pos) /*!< 0x10000000 */ #define RCC_PLL2CFGR1_PLL2SEL_1 (0x2UL << RCC_PLL2CFGR1_PLL2SEL_Pos) /*!< 0x20000000 */ #define RCC_PLL2CFGR1_PLL2SEL_2 (0x4UL << RCC_PLL2CFGR1_PLL2SEL_Pos) /*!< 0x40000000 */ /**************** Bit definition for RCC_PLL2CFGR2 register *****************/ #define RCC_PLL2CFGR2_PLL2DIVNFRAC_Pos (0U) #define RCC_PLL2CFGR2_PLL2DIVNFRAC_Msk (0xFFFFFFUL << RCC_PLL2CFGR2_PLL2DIVNFRAC_Pos) /*!< 0x00FFFFFF */ #define RCC_PLL2CFGR2_PLL2DIVNFRAC RCC_PLL2CFGR2_PLL2DIVNFRAC_Msk /*!< PLL2 fractional part of the VCO multiplication factor */ /**************** Bit definition for RCC_PLL2CFGR3 register *****************/ #define RCC_PLL2CFGR3_PLL2MODSSRST_Pos (0U) #define RCC_PLL2CFGR3_PLL2MODSSRST_Msk (0x1UL << RCC_PLL2CFGR3_PLL2MODSSRST_Pos) /*!< 0x00000001 */ #define RCC_PLL2CFGR3_PLL2MODSSRST RCC_PLL2CFGR3_PLL2MODSSRST_Msk /*!< PLL2 modulation spread spectrum reset */ #define RCC_PLL2CFGR3_PLL2DACEN_Pos (1U) #define RCC_PLL2CFGR3_PLL2DACEN_Msk (0x1UL << RCC_PLL2CFGR3_PLL2DACEN_Pos)/*!< 0x00000002 */ #define RCC_PLL2CFGR3_PLL2DACEN RCC_PLL2CFGR3_PLL2DACEN_Msk /*!< PLL2 noise canceling DAC enable in fractional mode */ #define RCC_PLL2CFGR3_PLL2MODSSDIS_Pos (2U) #define RCC_PLL2CFGR3_PLL2MODSSDIS_Msk (0x1UL << RCC_PLL2CFGR3_PLL2MODSSDIS_Pos) /*!< 0x00000004 */ #define RCC_PLL2CFGR3_PLL2MODSSDIS RCC_PLL2CFGR3_PLL2MODSSDIS_Msk /*!< PLL2 modulation spread spectrum disable */ #define RCC_PLL2CFGR3_PLL2MODDSEN_Pos (3U) #define RCC_PLL2CFGR3_PLL2MODDSEN_Msk (0x1UL << RCC_PLL2CFGR3_PLL2MODDSEN_Pos) /*!< 0x00000008 */ #define RCC_PLL2CFGR3_PLL2MODDSEN RCC_PLL2CFGR3_PLL2MODDSEN_Msk /*!< PLL2 modulation spread spectrum (and fractional divide) enable */ #define RCC_PLL2CFGR3_PLL2MODSPRDW_Pos (4U) #define RCC_PLL2CFGR3_PLL2MODSPRDW_Msk (0x1UL << RCC_PLL2CFGR3_PLL2MODSPRDW_Pos) /*!< 0x00000010 */ #define RCC_PLL2CFGR3_PLL2MODSPRDW RCC_PLL2CFGR3_PLL2MODSPRDW_Msk /*!< PLL2 modulation down spread */ #define RCC_PLL2CFGR3_PLL2MODDIV_Pos (8U) #define RCC_PLL2CFGR3_PLL2MODDIV_Msk (0xFUL << RCC_PLL2CFGR3_PLL2MODDIV_Pos) /*!< 0x00000F00 */ #define RCC_PLL2CFGR3_PLL2MODDIV RCC_PLL2CFGR3_PLL2MODDIV_Msk /*!< PLL2 modulation division frequency adjustment */ #define RCC_PLL2CFGR3_PLL2MODSPR_Pos (16U) #define RCC_PLL2CFGR3_PLL2MODSPR_Msk (0x1FUL << RCC_PLL2CFGR3_PLL2MODSPR_Pos) /*!< 0x001F0000 */ #define RCC_PLL2CFGR3_PLL2MODSPR RCC_PLL2CFGR3_PLL2MODSPR_Msk /*!< PLL2 modulation spread depth adjustment */ #define RCC_PLL2CFGR3_PLL2PDIV2_Pos (24U) #define RCC_PLL2CFGR3_PLL2PDIV2_Msk (0x7UL << RCC_PLL2CFGR3_PLL2PDIV2_Pos)/*!< 0x07000000 */ #define RCC_PLL2CFGR3_PLL2PDIV2 RCC_PLL2CFGR3_PLL2PDIV2_Msk /*!< PLL2 VCO frequency divider level 2 */ #define RCC_PLL2CFGR3_PLL2PDIV1_Pos (27U) #define RCC_PLL2CFGR3_PLL2PDIV1_Msk (0x7UL << RCC_PLL2CFGR3_PLL2PDIV1_Pos)/*!< 0x38000000 */ #define RCC_PLL2CFGR3_PLL2PDIV1 RCC_PLL2CFGR3_PLL2PDIV1_Msk /*!< PLL2 VCO frequency divider level 1 */ #define RCC_PLL2CFGR3_PLL2PDIVEN_Pos (30U) #define RCC_PLL2CFGR3_PLL2PDIVEN_Msk (0x1UL << RCC_PLL2CFGR3_PLL2PDIVEN_Pos) /*!< 0x40000000 */ #define RCC_PLL2CFGR3_PLL2PDIVEN RCC_PLL2CFGR3_PLL2PDIVEN_Msk /*!< PLL2 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */ /**************** Bit definition for RCC_PLL3CFGR1 register *****************/ #define RCC_PLL3CFGR1_PLL3DIVN_Pos (8U) #define RCC_PLL3CFGR1_PLL3DIVN_Msk (0xFFFUL << RCC_PLL3CFGR1_PLL3DIVN_Pos) /*!< 0x000FFF00 */ #define RCC_PLL3CFGR1_PLL3DIVN RCC_PLL3CFGR1_PLL3DIVN_Msk /*!< PLL3 Integer part for the VCO multiplication factor */ #define RCC_PLL3CFGR1_PLL3DIVM_Pos (20U) #define RCC_PLL3CFGR1_PLL3DIVM_Msk (0x3FUL << RCC_PLL3CFGR1_PLL3DIVM_Pos)/*!< 0x03F00000 */ #define RCC_PLL3CFGR1_PLL3DIVM RCC_PLL3CFGR1_PLL3DIVM_Msk /*!< PLL3 reference input clock divide frequency ratio */ #define RCC_PLL3CFGR1_PLL3BYP_Pos (27U) #define RCC_PLL3CFGR1_PLL3BYP_Msk (0x1UL << RCC_PLL3CFGR1_PLL3BYP_Pos) /*!< 0x08000000 */ #define RCC_PLL3CFGR1_PLL3BYP RCC_PLL3CFGR1_PLL3BYP_Msk /*!< PLL3 bypass */ #define RCC_PLL3CFGR1_PLL3SEL_Pos (28U) #define RCC_PLL3CFGR1_PLL3SEL_Msk (0x7UL << RCC_PLL3CFGR1_PLL3SEL_Pos) /*!< 0x70000000 */ #define RCC_PLL3CFGR1_PLL3SEL RCC_PLL3CFGR1_PLL3SEL_Msk /*!< PLL3 source selection of the reference clock */ #define RCC_PLL3CFGR1_PLL3SEL_0 (0x1UL << RCC_PLL3CFGR1_PLL3SEL_Pos) /*!< 0x10000000 */ #define RCC_PLL3CFGR1_PLL3SEL_1 (0x2UL << RCC_PLL3CFGR1_PLL3SEL_Pos) /*!< 0x20000000 */ #define RCC_PLL3CFGR1_PLL3SEL_2 (0x4UL << RCC_PLL3CFGR1_PLL3SEL_Pos) /*!< 0x40000000 */ /**************** Bit definition for RCC_PLL3CFGR2 register *****************/ #define RCC_PLL3CFGR2_PLL3DIVNFRAC_Pos (0U) #define RCC_PLL3CFGR2_PLL3DIVNFRAC_Msk (0xFFFFFFUL << RCC_PLL3CFGR2_PLL3DIVNFRAC_Pos) /*!< 0x00FFFFFF */ #define RCC_PLL3CFGR2_PLL3DIVNFRAC RCC_PLL3CFGR2_PLL3DIVNFRAC_Msk /*!< PLL3 fractional part of the VCO multiplication factor */ /**************** Bit definition for RCC_PLL3CFGR3 register *****************/ #define RCC_PLL3CFGR3_PLL3MODSSRST_Pos (0U) #define RCC_PLL3CFGR3_PLL3MODSSRST_Msk (0x1UL << RCC_PLL3CFGR3_PLL3MODSSRST_Pos) /*!< 0x00000001 */ #define RCC_PLL3CFGR3_PLL3MODSSRST RCC_PLL3CFGR3_PLL3MODSSRST_Msk /*!< PLL3 modulation spread spectrum reset */ #define RCC_PLL3CFGR3_PLL3DACEN_Pos (1U) #define RCC_PLL3CFGR3_PLL3DACEN_Msk (0x1UL << RCC_PLL3CFGR3_PLL3DACEN_Pos)/*!< 0x00000002 */ #define RCC_PLL3CFGR3_PLL3DACEN RCC_PLL3CFGR3_PLL3DACEN_Msk /*!< PLL3 noise canceling DAC enable in fractional mode */ #define RCC_PLL3CFGR3_PLL3MODSSDIS_Pos (2U) #define RCC_PLL3CFGR3_PLL3MODSSDIS_Msk (0x1UL << RCC_PLL3CFGR3_PLL3MODSSDIS_Pos) /*!< 0x00000004 */ #define RCC_PLL3CFGR3_PLL3MODSSDIS RCC_PLL3CFGR3_PLL3MODSSDIS_Msk /*!< PLL3 modulation spread spectrum disable */ #define RCC_PLL3CFGR3_PLL3MODDSEN_Pos (3U) #define RCC_PLL3CFGR3_PLL3MODDSEN_Msk (0x1UL << RCC_PLL3CFGR3_PLL3MODDSEN_Pos) /*!< 0x00000008 */ #define RCC_PLL3CFGR3_PLL3MODDSEN RCC_PLL3CFGR3_PLL3MODDSEN_Msk /*!< PLL3 modulation spread spectrum (and fractional divide) enable */ #define RCC_PLL3CFGR3_PLL3MODSPRDW_Pos (4U) #define RCC_PLL3CFGR3_PLL3MODSPRDW_Msk (0x1UL << RCC_PLL3CFGR3_PLL3MODSPRDW_Pos) /*!< 0x00000010 */ #define RCC_PLL3CFGR3_PLL3MODSPRDW RCC_PLL3CFGR3_PLL3MODSPRDW_Msk /*!< PLL3 modulation down spread */ #define RCC_PLL3CFGR3_PLL3MODDIV_Pos (8U) #define RCC_PLL3CFGR3_PLL3MODDIV_Msk (0xFUL << RCC_PLL3CFGR3_PLL3MODDIV_Pos) /*!< 0x00000F00 */ #define RCC_PLL3CFGR3_PLL3MODDIV RCC_PLL3CFGR3_PLL3MODDIV_Msk /*!< PLL3 modulation division frequency adjustment */ #define RCC_PLL3CFGR3_PLL3MODSPR_Pos (16U) #define RCC_PLL3CFGR3_PLL3MODSPR_Msk (0x1FUL << RCC_PLL3CFGR3_PLL3MODSPR_Pos) /*!< 0x001F0000 */ #define RCC_PLL3CFGR3_PLL3MODSPR RCC_PLL3CFGR3_PLL3MODSPR_Msk /*!< PLL3 modulation spread depth adjustment */ #define RCC_PLL3CFGR3_PLL3PDIV2_Pos (24U) #define RCC_PLL3CFGR3_PLL3PDIV2_Msk (0x7UL << RCC_PLL3CFGR3_PLL3PDIV2_Pos)/*!< 0x07000000 */ #define RCC_PLL3CFGR3_PLL3PDIV2 RCC_PLL3CFGR3_PLL3PDIV2_Msk /*!< PLL3 VCO frequency divider level 2 */ #define RCC_PLL3CFGR3_PLL3PDIV1_Pos (27U) #define RCC_PLL3CFGR3_PLL3PDIV1_Msk (0x7UL << RCC_PLL3CFGR3_PLL3PDIV1_Pos)/*!< 0x38000000 */ #define RCC_PLL3CFGR3_PLL3PDIV1 RCC_PLL3CFGR3_PLL3PDIV1_Msk /*!< PLL3 VCO frequency divider level 1 */ #define RCC_PLL3CFGR3_PLL3PDIVEN_Pos (30U) #define RCC_PLL3CFGR3_PLL3PDIVEN_Msk (0x1UL << RCC_PLL3CFGR3_PLL3PDIVEN_Pos) /*!< 0x40000000 */ #define RCC_PLL3CFGR3_PLL3PDIVEN RCC_PLL3CFGR3_PLL3PDIVEN_Msk /*!< PLL3 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */ /**************** Bit definition for RCC_PLL4CFGR1 register *****************/ #define RCC_PLL4CFGR1_PLL4DIVN_Pos (8U) #define RCC_PLL4CFGR1_PLL4DIVN_Msk (0xFFFUL << RCC_PLL4CFGR1_PLL4DIVN_Pos) /*!< 0x000FFF00 */ #define RCC_PLL4CFGR1_PLL4DIVN RCC_PLL4CFGR1_PLL4DIVN_Msk /*!< PLL4 integer part for the VCO multiplication factor */ #define RCC_PLL4CFGR1_PLL4DIVM_Pos (20U) #define RCC_PLL4CFGR1_PLL4DIVM_Msk (0x3FUL << RCC_PLL4CFGR1_PLL4DIVM_Pos)/*!< 0x03F00000 */ #define RCC_PLL4CFGR1_PLL4DIVM RCC_PLL4CFGR1_PLL4DIVM_Msk /*!< PLL4 reference input clock divide frequency ratio */ #define RCC_PLL4CFGR1_PLL4BYP_Pos (27U) #define RCC_PLL4CFGR1_PLL4BYP_Msk (0x1UL << RCC_PLL4CFGR1_PLL4BYP_Pos) /*!< 0x08000000 */ #define RCC_PLL4CFGR1_PLL4BYP RCC_PLL4CFGR1_PLL4BYP_Msk /*!< PLL4 bypass */ #define RCC_PLL4CFGR1_PLL4SEL_Pos (28U) #define RCC_PLL4CFGR1_PLL4SEL_Msk (0x7UL << RCC_PLL4CFGR1_PLL4SEL_Pos) /*!< 0x70000000 */ #define RCC_PLL4CFGR1_PLL4SEL RCC_PLL4CFGR1_PLL4SEL_Msk /*!< PLL4 source selection of the reference clock */ #define RCC_PLL4CFGR1_PLL4SEL_0 (0x1UL << RCC_PLL4CFGR1_PLL4SEL_Pos) /*!< 0x10000000 */ #define RCC_PLL4CFGR1_PLL4SEL_1 (0x2UL << RCC_PLL4CFGR1_PLL4SEL_Pos) /*!< 0x20000000 */ #define RCC_PLL4CFGR1_PLL4SEL_2 (0x4UL << RCC_PLL4CFGR1_PLL4SEL_Pos) /*!< 0x40000000 */ /**************** Bit definition for RCC_PLL4CFGR2 register *****************/ #define RCC_PLL4CFGR2_PLL4DIVNFRAC_Pos (0U) #define RCC_PLL4CFGR2_PLL4DIVNFRAC_Msk (0xFFFFFFUL << RCC_PLL4CFGR2_PLL4DIVNFRAC_Pos) /*!< 0x00FFFFFF */ #define RCC_PLL4CFGR2_PLL4DIVNFRAC RCC_PLL4CFGR2_PLL4DIVNFRAC_Msk /*!< PLL4 fractional part of the VCO multiplication factor */ /**************** Bit definition for RCC_PLL4CFGR3 register *****************/ #define RCC_PLL4CFGR3_PLL4MODSSRST_Pos (0U) #define RCC_PLL4CFGR3_PLL4MODSSRST_Msk (0x1UL << RCC_PLL4CFGR3_PLL4MODSSRST_Pos) /*!< 0x00000001 */ #define RCC_PLL4CFGR3_PLL4MODSSRST RCC_PLL4CFGR3_PLL4MODSSRST_Msk /*!< PLL4 modulation spread spectrum reset */ #define RCC_PLL4CFGR3_PLL4DACEN_Pos (1U) #define RCC_PLL4CFGR3_PLL4DACEN_Msk (0x1UL << RCC_PLL4CFGR3_PLL4DACEN_Pos)/*!< 0x00000002 */ #define RCC_PLL4CFGR3_PLL4DACEN RCC_PLL4CFGR3_PLL4DACEN_Msk /*!< PLL4 noise canceling DAC enable in fractional mode */ #define RCC_PLL4CFGR3_PLL4MODSSDIS_Pos (2U) #define RCC_PLL4CFGR3_PLL4MODSSDIS_Msk (0x1UL << RCC_PLL4CFGR3_PLL4MODSSDIS_Pos) /*!< 0x00000004 */ #define RCC_PLL4CFGR3_PLL4MODSSDIS RCC_PLL4CFGR3_PLL4MODSSDIS_Msk /*!< PLL4 modulation spread spectrum disable */ #define RCC_PLL4CFGR3_PLL4MODDSEN_Pos (3U) #define RCC_PLL4CFGR3_PLL4MODDSEN_Msk (0x1UL << RCC_PLL4CFGR3_PLL4MODDSEN_Pos) /*!< 0x00000008 */ #define RCC_PLL4CFGR3_PLL4MODDSEN RCC_PLL4CFGR3_PLL4MODDSEN_Msk /*!< PLL4 modulation spread spectrum (and fractional divide) enable */ #define RCC_PLL4CFGR3_PLL4MODSPRDW_Pos (4U) #define RCC_PLL4CFGR3_PLL4MODSPRDW_Msk (0x1UL << RCC_PLL4CFGR3_PLL4MODSPRDW_Pos) /*!< 0x00000010 */ #define RCC_PLL4CFGR3_PLL4MODSPRDW RCC_PLL4CFGR3_PLL4MODSPRDW_Msk /*!< PLL4 modulation down spread */ #define RCC_PLL4CFGR3_PLL4MODDIV_Pos (8U) #define RCC_PLL4CFGR3_PLL4MODDIV_Msk (0xFUL << RCC_PLL4CFGR3_PLL4MODDIV_Pos) /*!< 0x00000F00 */ #define RCC_PLL4CFGR3_PLL4MODDIV RCC_PLL4CFGR3_PLL4MODDIV_Msk /*!< PLL4 modulation division frequency adjustment */ #define RCC_PLL4CFGR3_PLL4MODSPR_Pos (16U) #define RCC_PLL4CFGR3_PLL4MODSPR_Msk (0x1FUL << RCC_PLL4CFGR3_PLL4MODSPR_Pos) /*!< 0x001F0000 */ #define RCC_PLL4CFGR3_PLL4MODSPR RCC_PLL4CFGR3_PLL4MODSPR_Msk /*!< PLL4 modulation spread depth adjustment */ #define RCC_PLL4CFGR3_PLL4PDIV2_Pos (24U) #define RCC_PLL4CFGR3_PLL4PDIV2_Msk (0x7UL << RCC_PLL4CFGR3_PLL4PDIV2_Pos)/*!< 0x07000000 */ #define RCC_PLL4CFGR3_PLL4PDIV2 RCC_PLL4CFGR3_PLL4PDIV2_Msk /*!< PLL4 VCO frequency divider level 2 */ #define RCC_PLL4CFGR3_PLL4PDIV1_Pos (27U) #define RCC_PLL4CFGR3_PLL4PDIV1_Msk (0x7UL << RCC_PLL4CFGR3_PLL4PDIV1_Pos)/*!< 0x38000000 */ #define RCC_PLL4CFGR3_PLL4PDIV1 RCC_PLL4CFGR3_PLL4PDIV1_Msk /*!< PLL4 VCO frequency divider level 1 */ #define RCC_PLL4CFGR3_PLL4PDIVEN_Pos (30U) #define RCC_PLL4CFGR3_PLL4PDIVEN_Msk (0x1UL << RCC_PLL4CFGR3_PLL4PDIVEN_Pos) /*!< 0x40000000 */ #define RCC_PLL4CFGR3_PLL4PDIVEN RCC_PLL4CFGR3_PLL4PDIVEN_Msk /*!< PLL4 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */ /***************** Bit definition for RCC_IC1CFGR register ******************/ #define RCC_IC1CFGR_IC1INT_Pos (16U) #define RCC_IC1CFGR_IC1INT_Msk (0xFFUL << RCC_IC1CFGR_IC1INT_Pos) /*!< 0x00FF0000 */ #define RCC_IC1CFGR_IC1INT RCC_IC1CFGR_IC1INT_Msk /*!< Divider IC1 integer division factor */ #define RCC_IC1CFGR_IC1SEL_Pos (28U) #define RCC_IC1CFGR_IC1SEL_Msk (0x3UL << RCC_IC1CFGR_IC1SEL_Pos) /*!< 0x30000000 */ #define RCC_IC1CFGR_IC1SEL RCC_IC1CFGR_IC1SEL_Msk /*!< Divider IC1 source selection */ #define RCC_IC1CFGR_IC1SEL_0 (0x1UL << RCC_IC1CFGR_IC1SEL_Pos) /*!< 0x10000000 */ #define RCC_IC1CFGR_IC1SEL_1 (0x2UL << RCC_IC1CFGR_IC1SEL_Pos) /*!< 0x20000000 */ /***************** Bit definition for RCC_IC2CFGR register ******************/ #define RCC_IC2CFGR_IC2INT_Pos (16U) #define RCC_IC2CFGR_IC2INT_Msk (0xFFUL << RCC_IC2CFGR_IC2INT_Pos) /*!< 0x00FF0000 */ #define RCC_IC2CFGR_IC2INT RCC_IC2CFGR_IC2INT_Msk /*!< Divider IC2 integer division factor */ #define RCC_IC2CFGR_IC2SEL_Pos (28U) #define RCC_IC2CFGR_IC2SEL_Msk (0x3UL << RCC_IC2CFGR_IC2SEL_Pos) /*!< 0x30000000 */ #define RCC_IC2CFGR_IC2SEL RCC_IC2CFGR_IC2SEL_Msk /*!< Divider IC2 source selection */ #define RCC_IC2CFGR_IC2SEL_0 (0x1UL << RCC_IC2CFGR_IC2SEL_Pos) /*!< 0x10000000 */ #define RCC_IC2CFGR_IC2SEL_1 (0x2UL << RCC_IC2CFGR_IC2SEL_Pos) /*!< 0x20000000 */ /***************** Bit definition for RCC_IC3CFGR register ******************/ #define RCC_IC3CFGR_IC3INT_Pos (16U) #define RCC_IC3CFGR_IC3INT_Msk (0xFFUL << RCC_IC3CFGR_IC3INT_Pos) /*!< 0x00FF0000 */ #define RCC_IC3CFGR_IC3INT RCC_IC3CFGR_IC3INT_Msk /*!< Divider IC3 integer division factor */ #define RCC_IC3CFGR_IC3SEL_Pos (28U) #define RCC_IC3CFGR_IC3SEL_Msk (0x3UL << RCC_IC3CFGR_IC3SEL_Pos) /*!< 0x30000000 */ #define RCC_IC3CFGR_IC3SEL RCC_IC3CFGR_IC3SEL_Msk /*!< Divider IC3 source selection */ #define RCC_IC3CFGR_IC3SEL_0 (0x1UL << RCC_IC3CFGR_IC3SEL_Pos) /*!< 0x10000000 */ #define RCC_IC3CFGR_IC3SEL_1 (0x2UL << RCC_IC3CFGR_IC3SEL_Pos) /*!< 0x20000000 */ /***************** Bit definition for RCC_IC4CFGR register ******************/ #define RCC_IC4CFGR_IC4INT_Pos (16U) #define RCC_IC4CFGR_IC4INT_Msk (0xFFUL << RCC_IC4CFGR_IC4INT_Pos) /*!< 0x00FF0000 */ #define RCC_IC4CFGR_IC4INT RCC_IC4CFGR_IC4INT_Msk /*!< Divider IC4 integer division factor */ #define RCC_IC4CFGR_IC4SEL_Pos (28U) #define RCC_IC4CFGR_IC4SEL_Msk (0x3UL << RCC_IC4CFGR_IC4SEL_Pos) /*!< 0x30000000 */ #define RCC_IC4CFGR_IC4SEL RCC_IC4CFGR_IC4SEL_Msk /*!< Divider IC4 source selection */ #define RCC_IC4CFGR_IC4SEL_0 (0x1UL << RCC_IC4CFGR_IC4SEL_Pos) /*!< 0x10000000 */ #define RCC_IC4CFGR_IC4SEL_1 (0x2UL << RCC_IC4CFGR_IC4SEL_Pos) /*!< 0x20000000 */ /***************** Bit definition for RCC_IC5CFGR register ******************/ #define RCC_IC5CFGR_IC5INT_Pos (16U) #define RCC_IC5CFGR_IC5INT_Msk (0xFFUL << RCC_IC5CFGR_IC5INT_Pos) /*!< 0x00FF0000 */ #define RCC_IC5CFGR_IC5INT RCC_IC5CFGR_IC5INT_Msk /*!< Divider IC5 integer division factor */ #define RCC_IC5CFGR_IC5SEL_Pos (28U) #define RCC_IC5CFGR_IC5SEL_Msk (0x3UL << RCC_IC5CFGR_IC5SEL_Pos) /*!< 0x30000000 */ #define RCC_IC5CFGR_IC5SEL RCC_IC5CFGR_IC5SEL_Msk /*!< Divider IC5 source selection */ #define RCC_IC5CFGR_IC5SEL_0 (0x1UL << RCC_IC5CFGR_IC5SEL_Pos) /*!< 0x10000000 */ #define RCC_IC5CFGR_IC5SEL_1 (0x2UL << RCC_IC5CFGR_IC5SEL_Pos) /*!< 0x20000000 */ /***************** Bit definition for RCC_IC6CFGR register ******************/ #define RCC_IC6CFGR_IC6INT_Pos (16U) #define RCC_IC6CFGR_IC6INT_Msk (0xFFUL << RCC_IC6CFGR_IC6INT_Pos) /*!< 0x00FF0000 */ #define RCC_IC6CFGR_IC6INT RCC_IC6CFGR_IC6INT_Msk /*!< Divider IC6 integer division factor */ #define RCC_IC6CFGR_IC6SEL_Pos (28U) #define RCC_IC6CFGR_IC6SEL_Msk (0x3UL << RCC_IC6CFGR_IC6SEL_Pos) /*!< 0x30000000 */ #define RCC_IC6CFGR_IC6SEL RCC_IC6CFGR_IC6SEL_Msk /*!< Divider IC6 source selection */ #define RCC_IC6CFGR_IC6SEL_0 (0x1UL << RCC_IC6CFGR_IC6SEL_Pos) /*!< 0x10000000 */ #define RCC_IC6CFGR_IC6SEL_1 (0x2UL << RCC_IC6CFGR_IC6SEL_Pos) /*!< 0x20000000 */ /***************** Bit definition for RCC_IC7CFGR register ******************/ #define RCC_IC7CFGR_IC7INT_Pos (16U) #define RCC_IC7CFGR_IC7INT_Msk (0xFFUL << RCC_IC7CFGR_IC7INT_Pos) /*!< 0x00FF0000 */ #define RCC_IC7CFGR_IC7INT RCC_IC7CFGR_IC7INT_Msk /*!< Divider IC7 integer division factor */ #define RCC_IC7CFGR_IC7SEL_Pos (28U) #define RCC_IC7CFGR_IC7SEL_Msk (0x3UL << RCC_IC7CFGR_IC7SEL_Pos) /*!< 0x30000000 */ #define RCC_IC7CFGR_IC7SEL RCC_IC7CFGR_IC7SEL_Msk /*!< Divider IC7 source selection */ #define RCC_IC7CFGR_IC7SEL_0 (0x1UL << RCC_IC7CFGR_IC7SEL_Pos) /*!< 0x10000000 */ #define RCC_IC7CFGR_IC7SEL_1 (0x2UL << RCC_IC7CFGR_IC7SEL_Pos) /*!< 0x20000000 */ /***************** Bit definition for RCC_IC8CFGR register ******************/ #define RCC_IC8CFGR_IC8INT_Pos (16U) #define RCC_IC8CFGR_IC8INT_Msk (0xFFUL << RCC_IC8CFGR_IC8INT_Pos) /*!< 0x00FF0000 */ #define RCC_IC8CFGR_IC8INT RCC_IC8CFGR_IC8INT_Msk /*!< Divider IC8 integer division factor */ #define RCC_IC8CFGR_IC8SEL_Pos (28U) #define RCC_IC8CFGR_IC8SEL_Msk (0x3UL << RCC_IC8CFGR_IC8SEL_Pos) /*!< 0x30000000 */ #define RCC_IC8CFGR_IC8SEL RCC_IC8CFGR_IC8SEL_Msk /*!< Divider IC8 source selection */ #define RCC_IC8CFGR_IC8SEL_0 (0x1UL << RCC_IC8CFGR_IC8SEL_Pos) /*!< 0x10000000 */ #define RCC_IC8CFGR_IC8SEL_1 (0x2UL << RCC_IC8CFGR_IC8SEL_Pos) /*!< 0x20000000 */ /***************** Bit definition for RCC_IC9CFGR register ******************/ #define RCC_IC9CFGR_IC9INT_Pos (16U) #define RCC_IC9CFGR_IC9INT_Msk (0xFFUL << RCC_IC9CFGR_IC9INT_Pos) /*!< 0x00FF0000 */ #define RCC_IC9CFGR_IC9INT RCC_IC9CFGR_IC9INT_Msk /*!< Divider IC9 integer division factor */ #define RCC_IC9CFGR_IC9SEL_Pos (28U) #define RCC_IC9CFGR_IC9SEL_Msk (0x3UL << RCC_IC9CFGR_IC9SEL_Pos) /*!< 0x30000000 */ #define RCC_IC9CFGR_IC9SEL RCC_IC9CFGR_IC9SEL_Msk /*!< Divider IC9 source selection */ #define RCC_IC9CFGR_IC9SEL_0 (0x1UL << RCC_IC9CFGR_IC9SEL_Pos) /*!< 0x10000000 */ #define RCC_IC9CFGR_IC9SEL_1 (0x2UL << RCC_IC9CFGR_IC9SEL_Pos) /*!< 0x20000000 */ /***************** Bit definition for RCC_IC10CFGR register *****************/ #define RCC_IC10CFGR_IC10INT_Pos (16U) #define RCC_IC10CFGR_IC10INT_Msk (0xFFUL << RCC_IC10CFGR_IC10INT_Pos) /*!< 0x00FF0000 */ #define RCC_IC10CFGR_IC10INT RCC_IC10CFGR_IC10INT_Msk /*!< Divider IC10 integer division factor */ #define RCC_IC10CFGR_IC10SEL_Pos (28U) #define RCC_IC10CFGR_IC10SEL_Msk (0x3UL << RCC_IC10CFGR_IC10SEL_Pos) /*!< 0x30000000 */ #define RCC_IC10CFGR_IC10SEL RCC_IC10CFGR_IC10SEL_Msk /*!< Divider IC10 source selection */ #define RCC_IC10CFGR_IC10SEL_0 (0x1UL << RCC_IC10CFGR_IC10SEL_Pos) /*!< 0x10000000 */ #define RCC_IC10CFGR_IC10SEL_1 (0x2UL << RCC_IC10CFGR_IC10SEL_Pos) /*!< 0x20000000 */ /***************** Bit definition for RCC_IC11CFGR register *****************/ #define RCC_IC11CFGR_IC11INT_Pos (16U) #define RCC_IC11CFGR_IC11INT_Msk (0xFFUL << RCC_IC11CFGR_IC11INT_Pos) /*!< 0x00FF0000 */ #define RCC_IC11CFGR_IC11INT RCC_IC11CFGR_IC11INT_Msk /*!< Divider IC11 integer division factor */ #define RCC_IC11CFGR_IC11SEL_Pos (28U) #define RCC_IC11CFGR_IC11SEL_Msk (0x3UL << RCC_IC11CFGR_IC11SEL_Pos) /*!< 0x30000000 */ #define RCC_IC11CFGR_IC11SEL RCC_IC11CFGR_IC11SEL_Msk /*!< Divider IC11 source selection */ #define RCC_IC11CFGR_IC11SEL_0 (0x1UL << RCC_IC11CFGR_IC11SEL_Pos) /*!< 0x10000000 */ #define RCC_IC11CFGR_IC11SEL_1 (0x2UL << RCC_IC11CFGR_IC11SEL_Pos) /*!< 0x20000000 */ /***************** Bit definition for RCC_IC12CFGR register *****************/ #define RCC_IC12CFGR_IC12INT_Pos (16U) #define RCC_IC12CFGR_IC12INT_Msk (0xFFUL << RCC_IC12CFGR_IC12INT_Pos) /*!< 0x00FF0000 */ #define RCC_IC12CFGR_IC12INT RCC_IC12CFGR_IC12INT_Msk /*!< Divider IC12 integer division factor */ #define RCC_IC12CFGR_IC12SEL_Pos (28U) #define RCC_IC12CFGR_IC12SEL_Msk (0x3UL << RCC_IC12CFGR_IC12SEL_Pos) /*!< 0x30000000 */ #define RCC_IC12CFGR_IC12SEL RCC_IC12CFGR_IC12SEL_Msk /*!< Divider IC12 source selection */ #define RCC_IC12CFGR_IC12SEL_0 (0x1UL << RCC_IC12CFGR_IC12SEL_Pos) /*!< 0x10000000 */ #define RCC_IC12CFGR_IC12SEL_1 (0x2UL << RCC_IC12CFGR_IC12SEL_Pos) /*!< 0x20000000 */ /***************** Bit definition for RCC_IC13CFGR register *****************/ #define RCC_IC13CFGR_IC13INT_Pos (16U) #define RCC_IC13CFGR_IC13INT_Msk (0xFFUL << RCC_IC13CFGR_IC13INT_Pos) /*!< 0x00FF0000 */ #define RCC_IC13CFGR_IC13INT RCC_IC13CFGR_IC13INT_Msk /*!< Divider IC13 integer division factor */ #define RCC_IC13CFGR_IC13SEL_Pos (28U) #define RCC_IC13CFGR_IC13SEL_Msk (0x3UL << RCC_IC13CFGR_IC13SEL_Pos) /*!< 0x30000000 */ #define RCC_IC13CFGR_IC13SEL RCC_IC13CFGR_IC13SEL_Msk /*!< Divider IC13 source selection */ #define RCC_IC13CFGR_IC13SEL_0 (0x1UL << RCC_IC13CFGR_IC13SEL_Pos) /*!< 0x10000000 */ #define RCC_IC13CFGR_IC13SEL_1 (0x2UL << RCC_IC13CFGR_IC13SEL_Pos) /*!< 0x20000000 */ /***************** Bit definition for RCC_IC14CFGR register *****************/ #define RCC_IC14CFGR_IC14INT_Pos (16U) #define RCC_IC14CFGR_IC14INT_Msk (0xFFUL << RCC_IC14CFGR_IC14INT_Pos) /*!< 0x00FF0000 */ #define RCC_IC14CFGR_IC14INT RCC_IC14CFGR_IC14INT_Msk /*!< Divider IC14 integer division factor */ #define RCC_IC14CFGR_IC14SEL_Pos (28U) #define RCC_IC14CFGR_IC14SEL_Msk (0x3UL << RCC_IC14CFGR_IC14SEL_Pos) /*!< 0x30000000 */ #define RCC_IC14CFGR_IC14SEL RCC_IC14CFGR_IC14SEL_Msk /*!< Divider IC14 source selection */ #define RCC_IC14CFGR_IC14SEL_0 (0x1UL << RCC_IC14CFGR_IC14SEL_Pos) /*!< 0x10000000 */ #define RCC_IC14CFGR_IC14SEL_1 (0x2UL << RCC_IC14CFGR_IC14SEL_Pos) /*!< 0x20000000 */ /***************** Bit definition for RCC_IC15CFGR register *****************/ #define RCC_IC15CFGR_IC15INT_Pos (16U) #define RCC_IC15CFGR_IC15INT_Msk (0xFFUL << RCC_IC15CFGR_IC15INT_Pos) /*!< 0x00FF0000 */ #define RCC_IC15CFGR_IC15INT RCC_IC15CFGR_IC15INT_Msk /*!< Divider IC15 integer division factor */ #define RCC_IC15CFGR_IC15SEL_Pos (28U) #define RCC_IC15CFGR_IC15SEL_Msk (0x3UL << RCC_IC15CFGR_IC15SEL_Pos) /*!< 0x30000000 */ #define RCC_IC15CFGR_IC15SEL RCC_IC15CFGR_IC15SEL_Msk /*!< Divider IC15 source selection */ #define RCC_IC15CFGR_IC15SEL_0 (0x1UL << RCC_IC15CFGR_IC15SEL_Pos) /*!< 0x10000000 */ #define RCC_IC15CFGR_IC15SEL_1 (0x2UL << RCC_IC15CFGR_IC15SEL_Pos) /*!< 0x20000000 */ /***************** Bit definition for RCC_IC16CFGR register *****************/ #define RCC_IC16CFGR_IC16INT_Pos (16U) #define RCC_IC16CFGR_IC16INT_Msk (0xFFUL << RCC_IC16CFGR_IC16INT_Pos) /*!< 0x00FF0000 */ #define RCC_IC16CFGR_IC16INT RCC_IC16CFGR_IC16INT_Msk /*!< Divider IC16 integer division factor */ #define RCC_IC16CFGR_IC16SEL_Pos (28U) #define RCC_IC16CFGR_IC16SEL_Msk (0x3UL << RCC_IC16CFGR_IC16SEL_Pos) /*!< 0x30000000 */ #define RCC_IC16CFGR_IC16SEL RCC_IC16CFGR_IC16SEL_Msk /*!< Divider IC16 source selection */ #define RCC_IC16CFGR_IC16SEL_0 (0x1UL << RCC_IC16CFGR_IC16SEL_Pos) /*!< 0x10000000 */ #define RCC_IC16CFGR_IC16SEL_1 (0x2UL << RCC_IC16CFGR_IC16SEL_Pos) /*!< 0x20000000 */ /***************** Bit definition for RCC_IC17CFGR register *****************/ #define RCC_IC17CFGR_IC17INT_Pos (16U) #define RCC_IC17CFGR_IC17INT_Msk (0xFFUL << RCC_IC17CFGR_IC17INT_Pos) /*!< 0x00FF0000 */ #define RCC_IC17CFGR_IC17INT RCC_IC17CFGR_IC17INT_Msk /*!< Divider IC17 integer division factor */ #define RCC_IC17CFGR_IC17SEL_Pos (28U) #define RCC_IC17CFGR_IC17SEL_Msk (0x3UL << RCC_IC17CFGR_IC17SEL_Pos) /*!< 0x30000000 */ #define RCC_IC17CFGR_IC17SEL RCC_IC17CFGR_IC17SEL_Msk /*!< Divider IC17 source selection */ #define RCC_IC17CFGR_IC17SEL_0 (0x1UL << RCC_IC17CFGR_IC17SEL_Pos) /*!< 0x10000000 */ #define RCC_IC17CFGR_IC17SEL_1 (0x2UL << RCC_IC17CFGR_IC17SEL_Pos) /*!< 0x20000000 */ /***************** Bit definition for RCC_IC18CFGR register *****************/ #define RCC_IC18CFGR_IC18INT_Pos (16U) #define RCC_IC18CFGR_IC18INT_Msk (0xFFUL << RCC_IC18CFGR_IC18INT_Pos) /*!< 0x00FF0000 */ #define RCC_IC18CFGR_IC18INT RCC_IC18CFGR_IC18INT_Msk /*!< Divider IC18 integer division factor */ #define RCC_IC18CFGR_IC18SEL_Pos (28U) #define RCC_IC18CFGR_IC18SEL_Msk (0x3UL << RCC_IC18CFGR_IC18SEL_Pos) /*!< 0x30000000 */ #define RCC_IC18CFGR_IC18SEL RCC_IC18CFGR_IC18SEL_Msk /*!< Divider IC18 source selection */ #define RCC_IC18CFGR_IC18SEL_0 (0x1UL << RCC_IC18CFGR_IC18SEL_Pos) /*!< 0x10000000 */ #define RCC_IC18CFGR_IC18SEL_1 (0x2UL << RCC_IC18CFGR_IC18SEL_Pos) /*!< 0x20000000 */ /***************** Bit definition for RCC_IC19CFGR register *****************/ #define RCC_IC19CFGR_IC19INT_Pos (16U) #define RCC_IC19CFGR_IC19INT_Msk (0xFFUL << RCC_IC19CFGR_IC19INT_Pos) /*!< 0x00FF0000 */ #define RCC_IC19CFGR_IC19INT RCC_IC19CFGR_IC19INT_Msk /*!< Divider IC19 integer division factor */ #define RCC_IC19CFGR_IC19SEL_Pos (28U) #define RCC_IC19CFGR_IC19SEL_Msk (0x3UL << RCC_IC19CFGR_IC19SEL_Pos) /*!< 0x30000000 */ #define RCC_IC19CFGR_IC19SEL RCC_IC19CFGR_IC19SEL_Msk /*!< Divider IC19 source selection */ #define RCC_IC19CFGR_IC19SEL_0 (0x1UL << RCC_IC19CFGR_IC19SEL_Pos) /*!< 0x10000000 */ #define RCC_IC19CFGR_IC19SEL_1 (0x2UL << RCC_IC19CFGR_IC19SEL_Pos) /*!< 0x20000000 */ /***************** Bit definition for RCC_IC20CFGR register *****************/ #define RCC_IC20CFGR_IC20INT_Pos (16U) #define RCC_IC20CFGR_IC20INT_Msk (0xFFUL << RCC_IC20CFGR_IC20INT_Pos) /*!< 0x00FF0000 */ #define RCC_IC20CFGR_IC20INT RCC_IC20CFGR_IC20INT_Msk /*!< Divider IC20 integer division factor */ #define RCC_IC20CFGR_IC20SEL_Pos (28U) #define RCC_IC20CFGR_IC20SEL_Msk (0x3UL << RCC_IC20CFGR_IC20SEL_Pos) /*!< 0x30000000 */ #define RCC_IC20CFGR_IC20SEL RCC_IC20CFGR_IC20SEL_Msk /*!< Divider IC20 source selection */ #define RCC_IC20CFGR_IC20SEL_0 (0x1UL << RCC_IC20CFGR_IC20SEL_Pos) /*!< 0x10000000 */ #define RCC_IC20CFGR_IC20SEL_1 (0x2UL << RCC_IC20CFGR_IC20SEL_Pos) /*!< 0x20000000 */ /******************* Bit definition for RCC_CIER register *******************/ #define RCC_CIER_LSIRDYIE_Pos (0U) #define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ #define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI ready interrupt enable */ #define RCC_CIER_LSERDYIE_Pos (1U) #define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ #define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE ready interrupt enable */ #define RCC_CIER_MSIRDYIE_Pos (2U) #define RCC_CIER_MSIRDYIE_Msk (0x1UL << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000004 */ #define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk /*!< MSI ready interrupt enable */ #define RCC_CIER_HSIRDYIE_Pos (3U) #define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */ #define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk /*!< HSI ready interrupt enable */ #define RCC_CIER_HSERDYIE_Pos (4U) #define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */ #define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE ready interrupt enable */ #define RCC_CIER_PLL1RDYIE_Pos (8U) #define RCC_CIER_PLL1RDYIE_Msk (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000100 */ #define RCC_CIER_PLL1RDYIE RCC_CIER_PLL1RDYIE_Msk /*!< PLL1 ready interrupt enable */ #define RCC_CIER_PLL2RDYIE_Pos (9U) #define RCC_CIER_PLL2RDYIE_Msk (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000200 */ #define RCC_CIER_PLL2RDYIE RCC_CIER_PLL2RDYIE_Msk /*!< PLL2 ready interrupt enable */ #define RCC_CIER_PLL3RDYIE_Pos (10U) #define RCC_CIER_PLL3RDYIE_Msk (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000400 */ #define RCC_CIER_PLL3RDYIE RCC_CIER_PLL3RDYIE_Msk /*!< PLL3 ready interrupt enable */ #define RCC_CIER_PLL4RDYIE_Pos (11U) #define RCC_CIER_PLL4RDYIE_Msk (0x1UL << RCC_CIER_PLL4RDYIE_Pos) /*!< 0x00000800 */ #define RCC_CIER_PLL4RDYIE RCC_CIER_PLL4RDYIE_Msk /*!< PLL4 ready interrupt enable */ #define RCC_CIER_LSECSSIE_Pos (16U) #define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ #define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk /*!< LSE CSS interrupt enable */ #define RCC_CIER_HSECSSIE_Pos (17U) #define RCC_CIER_HSECSSIE_Msk (0x1UL << RCC_CIER_HSECSSIE_Pos) /*!< 0x00020000 */ #define RCC_CIER_HSECSSIE RCC_CIER_HSECSSIE_Msk /*!< HSE CSS interrupt enable */ #define RCC_CIER_WKUPIE_Pos (24U) #define RCC_CIER_WKUPIE_Msk (0x1UL << RCC_CIER_WKUPIE_Pos) /*!< 0x01000000 */ #define RCC_CIER_WKUPIE RCC_CIER_WKUPIE_Msk /*!< CPU wake-up from Stop interrupt enable */ /******************* Bit definition for RCC_CIFR register *******************/ #define RCC_CIFR_LSIRDYF_Pos (0U) #define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ #define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI ready interrupt flag */ #define RCC_CIFR_LSERDYF_Pos (1U) #define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ #define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE ready interrupt flag */ #define RCC_CIFR_MSIRDYF_Pos (2U) #define RCC_CIFR_MSIRDYF_Msk (0x1UL << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000004 */ #define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk /*!< MSI ready interrupt flag */ #define RCC_CIFR_HSIRDYF_Pos (3U) #define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */ #define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk /*!< HSI ready interrupt flag */ #define RCC_CIFR_HSERDYF_Pos (4U) #define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */ #define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE ready interrupt flag */ #define RCC_CIFR_PLL1RDYF_Pos (8U) #define RCC_CIFR_PLL1RDYF_Msk (0x1UL << RCC_CIFR_PLL1RDYF_Pos) /*!< 0x00000100 */ #define RCC_CIFR_PLL1RDYF RCC_CIFR_PLL1RDYF_Msk /*!< PLL1 ready interrupt flag */ #define RCC_CIFR_PLL2RDYF_Pos (9U) #define RCC_CIFR_PLL2RDYF_Msk (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000200 */ #define RCC_CIFR_PLL2RDYF RCC_CIFR_PLL2RDYF_Msk /*!< PLL2 ready interrupt flag */ #define RCC_CIFR_PLL3RDYF_Pos (10U) #define RCC_CIFR_PLL3RDYF_Msk (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000400 */ #define RCC_CIFR_PLL3RDYF RCC_CIFR_PLL3RDYF_Msk /*!< PLL3 ready interrupt flag */ #define RCC_CIFR_PLL4RDYF_Pos (11U) #define RCC_CIFR_PLL4RDYF_Msk (0x1UL << RCC_CIFR_PLL4RDYF_Pos) /*!< 0x00000800 */ #define RCC_CIFR_PLL4RDYF RCC_CIFR_PLL4RDYF_Msk /*!< PLL4 ready interrupt flag */ #define RCC_CIFR_LSECSSF_Pos (16U) #define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ #define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk /*!< LSE ready interrupt flag */ #define RCC_CIFR_HSECSSF_Pos (17U) #define RCC_CIFR_HSECSSF_Msk (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00020000 */ #define RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk /*!< HSE ready interrupt flag */ #define RCC_CIFR_WKUPF_Pos (24U) #define RCC_CIFR_WKUPF_Msk (0x1UL << RCC_CIFR_WKUPF_Pos) /*!< 0x01000000 */ #define RCC_CIFR_WKUPF RCC_CIFR_WKUPF_Msk /*!< CPU wake-up from Stop interrupt flag */ /******************* Bit definition for RCC_CICR register *******************/ #define RCC_CICR_LSIRDYC_Pos (0U) #define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */ #define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI ready interrupt clear */ #define RCC_CICR_LSERDYC_Pos (1U) #define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ #define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE ready interrupt clear */ #define RCC_CICR_MSIRDYC_Pos (2U) #define RCC_CICR_MSIRDYC_Msk (0x1UL << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000004 */ #define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk /*!< MSI ready interrupt clear */ #define RCC_CICR_HSIRDYC_Pos (3U) #define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */ #define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk /*!< HSI ready interrupt clear */ #define RCC_CICR_HSERDYC_Pos (4U) #define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */ #define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE ready interrupt clear */ #define RCC_CICR_PLL1RDYC_Pos (8U) #define RCC_CICR_PLL1RDYC_Msk (0x1UL << RCC_CICR_PLL1RDYC_Pos) /*!< 0x00000100 */ #define RCC_CICR_PLL1RDYC RCC_CICR_PLL1RDYC_Msk /*!< PLL1 ready interrupt clear */ #define RCC_CICR_PLL2RDYC_Pos (9U) #define RCC_CICR_PLL2RDYC_Msk (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000200 */ #define RCC_CICR_PLL2RDYC RCC_CICR_PLL2RDYC_Msk /*!< PLL2 ready interrupt clear */ #define RCC_CICR_PLL3RDYC_Pos (10U) #define RCC_CICR_PLL3RDYC_Msk (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000400 */ #define RCC_CICR_PLL3RDYC RCC_CICR_PLL3RDYC_Msk /*!< PLL3 ready interrupt clear */ #define RCC_CICR_PLL4RDYC_Pos (11U) #define RCC_CICR_PLL4RDYC_Msk (0x1UL << RCC_CICR_PLL4RDYC_Pos) /*!< 0x00000800 */ #define RCC_CICR_PLL4RDYC RCC_CICR_PLL4RDYC_Msk /*!< PLL4 ready interrupt clear */ #define RCC_CICR_LSECSSC_Pos (16U) #define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00010000 */ #define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk /*!< LSE ready interrupt clear */ #define RCC_CICR_HSECSSC_Pos (17U) #define RCC_CICR_HSECSSC_Msk (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00020000 */ #define RCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk /*!< HSE ready interrupt clear */ #define RCC_CICR_WKUPFC_Pos (24U) #define RCC_CICR_WKUPFC_Msk (0x1UL << RCC_CICR_WKUPFC_Pos) /*!< 0x01000000 */ #define RCC_CICR_WKUPFC RCC_CICR_WKUPFC_Msk /*!< CPU wake-up ready interrupt clear */ /****************** Bit definition for RCC_CCIPR1 register ******************/ #define RCC_CCIPR1_ADF1SEL_Pos (0U) #define RCC_CCIPR1_ADF1SEL_Msk (0x7UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00000007 */ #define RCC_CCIPR1_ADF1SEL RCC_CCIPR1_ADF1SEL_Msk /*!< Source selection for the ADF1 kernel clock */ #define RCC_CCIPR1_ADF1SEL_0 (0x1UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00000001 */ #define RCC_CCIPR1_ADF1SEL_1 (0x2UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00000002 */ #define RCC_CCIPR1_ADF1SEL_2 (0x4UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00000004 */ #define RCC_CCIPR1_ADC12SEL_Pos (4U) #define RCC_CCIPR1_ADC12SEL_Msk (0x7UL << RCC_CCIPR1_ADC12SEL_Pos) /*!< 0x00000070 */ #define RCC_CCIPR1_ADC12SEL RCC_CCIPR1_ADC12SEL_Msk /*!< Source selection for the ADC12 kernel clock */ #define RCC_CCIPR1_ADC12SEL_0 (0x1UL << RCC_CCIPR1_ADC12SEL_Pos) /*!< 0x00000010 */ #define RCC_CCIPR1_ADC12SEL_1 (0x2UL << RCC_CCIPR1_ADC12SEL_Pos) /*!< 0x00000020 */ #define RCC_CCIPR1_ADC12SEL_2 (0x4UL << RCC_CCIPR1_ADC12SEL_Pos) /*!< 0x00000040 */ #define RCC_CCIPR1_ADCPRE_Pos (8U) #define RCC_CCIPR1_ADCPRE_Msk (0xFFUL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x0000FF00 */ #define RCC_CCIPR1_ADCPRE RCC_CCIPR1_ADCPRE_Msk /*!< ADC12 Bus Slave clock divider selection (for clock ck_icn_s_vencram) */ #define RCC_CCIPR1_ADCPRE_0 (0x1UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00000100 */ #define RCC_CCIPR1_ADCPRE_1 (0x2UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00000200 */ #define RCC_CCIPR1_ADCPRE_2 (0x4UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00000400 */ #define RCC_CCIPR1_ADCPRE_3 (0x8UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00000800 */ #define RCC_CCIPR1_ADCPRE_4 (0x10UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00001000 */ #define RCC_CCIPR1_ADCPRE_5 (0x20UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00002000 */ #define RCC_CCIPR1_ADCPRE_6 (0x40UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00004000 */ #define RCC_CCIPR1_ADCPRE_7 (0x80UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00008000 */ #define RCC_CCIPR1_DCMIPPSEL_Pos (20U) #define RCC_CCIPR1_DCMIPPSEL_Msk (0x3UL << RCC_CCIPR1_DCMIPPSEL_Pos) /*!< 0x00300000 */ #define RCC_CCIPR1_DCMIPPSEL RCC_CCIPR1_DCMIPPSEL_Msk /*!< Source selection for the DCMIPP kernel clock */ #define RCC_CCIPR1_DCMIPPSEL_0 (0x1UL << RCC_CCIPR1_DCMIPPSEL_Pos) /*!< 0x00100000 */ #define RCC_CCIPR1_DCMIPPSEL_1 (0x2UL << RCC_CCIPR1_DCMIPPSEL_Pos) /*!< 0x00200000 */ /****************** Bit definition for RCC_CCIPR2 register ******************/ #define RCC_CCIPR2_ETH1PTPSEL_Pos (0U) #define RCC_CCIPR2_ETH1PTPSEL_Msk (0x3UL << RCC_CCIPR2_ETH1PTPSEL_Pos) /*!< 0x00000003 */ #define RCC_CCIPR2_ETH1PTPSEL RCC_CCIPR2_ETH1PTPSEL_Msk /*!< Source selection for the ETH1 kernel clock */ #define RCC_CCIPR2_ETH1PTPSEL_0 (0x1UL << RCC_CCIPR2_ETH1PTPSEL_Pos) /*!< 0x00000001 */ #define RCC_CCIPR2_ETH1PTPSEL_1 (0x2UL << RCC_CCIPR2_ETH1PTPSEL_Pos) /*!< 0x00000002 */ #define RCC_CCIPR2_ETH1PTPDIV_Pos (4U) #define RCC_CCIPR2_ETH1PTPDIV_Msk (0xFUL << RCC_CCIPR2_ETH1PTPDIV_Pos) /*!< 0x000000F0 */ #define RCC_CCIPR2_ETH1PTPDIV RCC_CCIPR2_ETH1PTPDIV_Msk /*!< ETH1 Kernel clock divider selection (for clock ck_ker_eth1ptp) */ #define RCC_CCIPR2_ETH1PTPDIV_0 (0x1UL << RCC_CCIPR2_ETH1PTPDIV_Pos) /*!< 0x00000010 */ #define RCC_CCIPR2_ETH1PTPDIV_1 (0x2UL << RCC_CCIPR2_ETH1PTPDIV_Pos) /*!< 0x00000020 */ #define RCC_CCIPR2_ETH1PTPDIV_2 (0x4UL << RCC_CCIPR2_ETH1PTPDIV_Pos) /*!< 0x00000040 */ #define RCC_CCIPR2_ETH1PTPDIV_3 (0x8UL << RCC_CCIPR2_ETH1PTPDIV_Pos) /*!< 0x00000080 */ #define RCC_CCIPR2_ETH1PWRDOWNACK_Pos (8U) #define RCC_CCIPR2_ETH1PWRDOWNACK_Msk (0x1UL << RCC_CCIPR2_ETH1PWRDOWNACK_Pos) /*!< 0x00000100 */ #define RCC_CCIPR2_ETH1PWRDOWNACK RCC_CCIPR2_ETH1PWRDOWNACK_Msk /*!< Set and reset by software */ #define RCC_CCIPR2_ETH1CLKSEL_Pos (12U) #define RCC_CCIPR2_ETH1CLKSEL_Msk (0x3UL << RCC_CCIPR2_ETH1CLKSEL_Pos) /*!< 0x00003000 */ #define RCC_CCIPR2_ETH1CLKSEL RCC_CCIPR2_ETH1CLKSEL_Msk /*!< Source selection for the ETH1 kernel clock */ #define RCC_CCIPR2_ETH1CLKSEL_0 (0x1UL << RCC_CCIPR2_ETH1CLKSEL_Pos) /*!< 0x00001000 */ #define RCC_CCIPR2_ETH1CLKSEL_1 (0x2UL << RCC_CCIPR2_ETH1CLKSEL_Pos) /*!< 0x00002000 */ #define RCC_CCIPR2_ETH1SEL_Pos (16U) #define RCC_CCIPR2_ETH1SEL_Msk (0x7UL << RCC_CCIPR2_ETH1SEL_Pos) /*!< 0x00070000 */ #define RCC_CCIPR2_ETH1SEL RCC_CCIPR2_ETH1SEL_Msk /*!< Set and reset by software */ #define RCC_CCIPR2_ETH1SEL_0 (0x1UL << RCC_CCIPR2_ETH1SEL_Pos) /*!< 0x00010000 */ #define RCC_CCIPR2_ETH1SEL_1 (0x2UL << RCC_CCIPR2_ETH1SEL_Pos) /*!< 0x00020000 */ #define RCC_CCIPR2_ETH1SEL_2 (0x4UL << RCC_CCIPR2_ETH1SEL_Pos) /*!< 0x00040000 */ #define RCC_CCIPR2_ETH1REFCLKSEL_Pos (20U) #define RCC_CCIPR2_ETH1REFCLKSEL_Msk (0x1UL << RCC_CCIPR2_ETH1REFCLKSEL_Pos) /*!< 0x00100000 */ #define RCC_CCIPR2_ETH1REFCLKSEL RCC_CCIPR2_ETH1REFCLKSEL_Msk /*!< Set and reset by software */ #define RCC_CCIPR2_ETH1GTXCLKSEL_Pos (24U) #define RCC_CCIPR2_ETH1GTXCLKSEL_Msk (0x1UL << RCC_CCIPR2_ETH1GTXCLKSEL_Pos) /*!< 0x01000000 */ #define RCC_CCIPR2_ETH1GTXCLKSEL RCC_CCIPR2_ETH1GTXCLKSEL_Msk /*!< Set and reset by software */ /****************** Bit definition for RCC_CCIPR3 register ******************/ #define RCC_CCIPR3_FDCANSEL_Pos (0U) #define RCC_CCIPR3_FDCANSEL_Msk (0x3UL << RCC_CCIPR3_FDCANSEL_Pos) /*!< 0x00000003 */ #define RCC_CCIPR3_FDCANSEL RCC_CCIPR3_FDCANSEL_Msk /*!< Source selection for the FDCAN kernel clock */ #define RCC_CCIPR3_FDCANSEL_0 (0x1UL << RCC_CCIPR3_FDCANSEL_Pos) /*!< 0x00000001 */ #define RCC_CCIPR3_FDCANSEL_1 (0x2UL << RCC_CCIPR3_FDCANSEL_Pos) /*!< 0x00000002 */ #define RCC_CCIPR3_FMCSEL_Pos (4U) #define RCC_CCIPR3_FMCSEL_Msk (0x3UL << RCC_CCIPR3_FMCSEL_Pos) /*!< 0x00000030 */ #define RCC_CCIPR3_FMCSEL RCC_CCIPR3_FMCSEL_Msk /*!< Source selection for the FMC kernel clock */ #define RCC_CCIPR3_FMCSEL_0 (0x1UL << RCC_CCIPR3_FMCSEL_Pos) /*!< 0x00000010 */ #define RCC_CCIPR3_FMCSEL_1 (0x2UL << RCC_CCIPR3_FMCSEL_Pos) /*!< 0x00000020 */ #define RCC_CCIPR3_DFTSEL_Pos (8U) #define RCC_CCIPR3_DFTSEL_Msk (0x1UL << RCC_CCIPR3_DFTSEL_Pos) /*!< 0x00000100 */ #define RCC_CCIPR3_DFTSEL RCC_CCIPR3_DFTSEL_Msk /*!< Source selection for the DFT kernel clock */ /****************** Bit definition for RCC_CCIPR4 register ******************/ #define RCC_CCIPR4_I2C1SEL_Pos (0U) #define RCC_CCIPR4_I2C1SEL_Msk (0x7UL << RCC_CCIPR4_I2C1SEL_Pos) /*!< 0x00000007 */ #define RCC_CCIPR4_I2C1SEL RCC_CCIPR4_I2C1SEL_Msk /*!< Source selection for the I2C1 kernel clock */ #define RCC_CCIPR4_I2C1SEL_0 (0x1UL << RCC_CCIPR4_I2C1SEL_Pos) /*!< 0x00000001 */ #define RCC_CCIPR4_I2C1SEL_1 (0x2UL << RCC_CCIPR4_I2C1SEL_Pos) /*!< 0x00000002 */ #define RCC_CCIPR4_I2C1SEL_2 (0x4UL << RCC_CCIPR4_I2C1SEL_Pos) /*!< 0x00000004 */ #define RCC_CCIPR4_I2C2SEL_Pos (4U) #define RCC_CCIPR4_I2C2SEL_Msk (0x7UL << RCC_CCIPR4_I2C2SEL_Pos) /*!< 0x00000070 */ #define RCC_CCIPR4_I2C2SEL RCC_CCIPR4_I2C2SEL_Msk /*!< Source selection for the I2C2 kernel clock */ #define RCC_CCIPR4_I2C2SEL_0 (0x1UL << RCC_CCIPR4_I2C2SEL_Pos) /*!< 0x00000010 */ #define RCC_CCIPR4_I2C2SEL_1 (0x2UL << RCC_CCIPR4_I2C2SEL_Pos) /*!< 0x00000020 */ #define RCC_CCIPR4_I2C2SEL_2 (0x4UL << RCC_CCIPR4_I2C2SEL_Pos) /*!< 0x00000040 */ #define RCC_CCIPR4_I2C3SEL_Pos (8U) #define RCC_CCIPR4_I2C3SEL_Msk (0x7UL << RCC_CCIPR4_I2C3SEL_Pos) /*!< 0x00000700 */ #define RCC_CCIPR4_I2C3SEL RCC_CCIPR4_I2C3SEL_Msk /*!< Source selection for the I2C3 kernel clock */ #define RCC_CCIPR4_I2C3SEL_0 (0x1UL << RCC_CCIPR4_I2C3SEL_Pos) /*!< 0x00000100 */ #define RCC_CCIPR4_I2C3SEL_1 (0x2UL << RCC_CCIPR4_I2C3SEL_Pos) /*!< 0x00000200 */ #define RCC_CCIPR4_I2C3SEL_2 (0x4UL << RCC_CCIPR4_I2C3SEL_Pos) /*!< 0x00000400 */ #define RCC_CCIPR4_I2C4SEL_Pos (12U) #define RCC_CCIPR4_I2C4SEL_Msk (0x7UL << RCC_CCIPR4_I2C4SEL_Pos) /*!< 0x00007000 */ #define RCC_CCIPR4_I2C4SEL RCC_CCIPR4_I2C4SEL_Msk /*!< Source selection for the I2C4 kernel clock */ #define RCC_CCIPR4_I2C4SEL_0 (0x1UL << RCC_CCIPR4_I2C4SEL_Pos) /*!< 0x00001000 */ #define RCC_CCIPR4_I2C4SEL_1 (0x2UL << RCC_CCIPR4_I2C4SEL_Pos) /*!< 0x00002000 */ #define RCC_CCIPR4_I2C4SEL_2 (0x4UL << RCC_CCIPR4_I2C4SEL_Pos) /*!< 0x00004000 */ #define RCC_CCIPR4_I3C1SEL_Pos (16U) #define RCC_CCIPR4_I3C1SEL_Msk (0x7UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x00070000 */ #define RCC_CCIPR4_I3C1SEL RCC_CCIPR4_I3C1SEL_Msk /*!< Source selection for the I3C1 kernel clock */ #define RCC_CCIPR4_I3C1SEL_0 (0x1UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x00010000 */ #define RCC_CCIPR4_I3C1SEL_1 (0x2UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x00020000 */ #define RCC_CCIPR4_I3C1SEL_2 (0x4UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x00040000 */ #define RCC_CCIPR4_I3C2SEL_Pos (20U) #define RCC_CCIPR4_I3C2SEL_Msk (0x7UL << RCC_CCIPR4_I3C2SEL_Pos) /*!< 0x00700000 */ #define RCC_CCIPR4_I3C2SEL RCC_CCIPR4_I3C2SEL_Msk /*!< Source selection for the I3C2 kernel clock */ #define RCC_CCIPR4_I3C2SEL_0 (0x1UL << RCC_CCIPR4_I3C2SEL_Pos) /*!< 0x00100000 */ #define RCC_CCIPR4_I3C2SEL_1 (0x2UL << RCC_CCIPR4_I3C2SEL_Pos) /*!< 0x00200000 */ #define RCC_CCIPR4_I3C2SEL_2 (0x4UL << RCC_CCIPR4_I3C2SEL_Pos) /*!< 0x00400000 */ #define RCC_CCIPR4_LTDCSEL_Pos (24U) #define RCC_CCIPR4_LTDCSEL_Msk (0x3UL << RCC_CCIPR4_LTDCSEL_Pos) /*!< 0x03000000 */ #define RCC_CCIPR4_LTDCSEL RCC_CCIPR4_LTDCSEL_Msk /*!< Source selection for the LTDC kernel clock */ #define RCC_CCIPR4_LTDCSEL_0 (0x1UL << RCC_CCIPR4_LTDCSEL_Pos) /*!< 0x01000000 */ #define RCC_CCIPR4_LTDCSEL_1 (0x2UL << RCC_CCIPR4_LTDCSEL_Pos) /*!< 0x02000000 */ /****************** Bit definition for RCC_CCIPR5 register ******************/ #define RCC_CCIPR5_MCO1SEL_Pos (0U) #define RCC_CCIPR5_MCO1SEL_Msk (0x7UL << RCC_CCIPR5_MCO1SEL_Pos) /*!< 0x00000007 */ #define RCC_CCIPR5_MCO1SEL RCC_CCIPR5_MCO1SEL_Msk /*!< Source selection for the MCO1 kernel clock */ #define RCC_CCIPR5_MCO1SEL_0 (0x1UL << RCC_CCIPR5_MCO1SEL_Pos) /*!< 0x00000001 */ #define RCC_CCIPR5_MCO1SEL_1 (0x2UL << RCC_CCIPR5_MCO1SEL_Pos) /*!< 0x00000002 */ #define RCC_CCIPR5_MCO1SEL_2 (0x4UL << RCC_CCIPR5_MCO1SEL_Pos) /*!< 0x00000004 */ #define RCC_CCIPR5_MCO1PRE_Pos (4U) #define RCC_CCIPR5_MCO1PRE_Msk (0xFUL << RCC_CCIPR5_MCO1PRE_Pos) /*!< 0x000000F0 */ #define RCC_CCIPR5_MCO1PRE RCC_CCIPR5_MCO1PRE_Msk /*!< MCO1 Kernel clock divider selection (for clock MCO1) */ #define RCC_CCIPR5_MCO1PRE_0 (0x1UL << RCC_CCIPR5_MCO1PRE_Pos) /*!< 0x00000010 */ #define RCC_CCIPR5_MCO1PRE_1 (0x2UL << RCC_CCIPR5_MCO1PRE_Pos) /*!< 0x00000020 */ #define RCC_CCIPR5_MCO1PRE_2 (0x4UL << RCC_CCIPR5_MCO1PRE_Pos) /*!< 0x00000040 */ #define RCC_CCIPR5_MCO1PRE_3 (0x8UL << RCC_CCIPR5_MCO1PRE_Pos) /*!< 0x00000080 */ #define RCC_CCIPR5_MCO2SEL_Pos (8U) #define RCC_CCIPR5_MCO2SEL_Msk (0x7UL << RCC_CCIPR5_MCO2SEL_Pos) /*!< 0x00000700 */ #define RCC_CCIPR5_MCO2SEL RCC_CCIPR5_MCO2SEL_Msk /*!< Source selection for the MCO2 kernel clock */ #define RCC_CCIPR5_MCO2SEL_0 (0x1UL << RCC_CCIPR5_MCO2SEL_Pos) /*!< 0x00000100 */ #define RCC_CCIPR5_MCO2SEL_1 (0x2UL << RCC_CCIPR5_MCO2SEL_Pos) /*!< 0x00000200 */ #define RCC_CCIPR5_MCO2SEL_2 (0x4UL << RCC_CCIPR5_MCO2SEL_Pos) /*!< 0x00000400 */ #define RCC_CCIPR5_MCO2PRE_Pos (12U) #define RCC_CCIPR5_MCO2PRE_Msk (0xFUL << RCC_CCIPR5_MCO2PRE_Pos) /*!< 0x0000F000 */ #define RCC_CCIPR5_MCO2PRE RCC_CCIPR5_MCO2PRE_Msk /*!< MCO2 Kernel clock divider selection (for clock MCO2) */ #define RCC_CCIPR5_MCO2PRE_0 (0x1UL << RCC_CCIPR5_MCO2PRE_Pos) /*!< 0x00001000 */ #define RCC_CCIPR5_MCO2PRE_1 (0x2UL << RCC_CCIPR5_MCO2PRE_Pos) /*!< 0x00002000 */ #define RCC_CCIPR5_MCO2PRE_2 (0x4UL << RCC_CCIPR5_MCO2PRE_Pos) /*!< 0x00004000 */ #define RCC_CCIPR5_MCO2PRE_3 (0x8UL << RCC_CCIPR5_MCO2PRE_Pos) /*!< 0x00008000 */ #define RCC_CCIPR5_MDF1SEL_Pos (16U) #define RCC_CCIPR5_MDF1SEL_Msk (0x7UL << RCC_CCIPR5_MDF1SEL_Pos) /*!< 0x00070000 */ #define RCC_CCIPR5_MDF1SEL RCC_CCIPR5_MDF1SEL_Msk /*!< Source selection for the MDF1 kernel clock */ #define RCC_CCIPR5_MDF1SEL_0 (0x1UL << RCC_CCIPR5_MDF1SEL_Pos) /*!< 0x00010000 */ #define RCC_CCIPR5_MDF1SEL_1 (0x2UL << RCC_CCIPR5_MDF1SEL_Pos) /*!< 0x00020000 */ #define RCC_CCIPR5_MDF1SEL_2 (0x4UL << RCC_CCIPR5_MDF1SEL_Pos) /*!< 0x00040000 */ /****************** Bit definition for RCC_CCIPR6 register ******************/ #define RCC_CCIPR6_XSPI1SEL_Pos (0U) #define RCC_CCIPR6_XSPI1SEL_Msk (0x3UL << RCC_CCIPR6_XSPI1SEL_Pos) /*!< 0x00000003 */ #define RCC_CCIPR6_XSPI1SEL RCC_CCIPR6_XSPI1SEL_Msk /*!< Source selection for the XSPI1 kernel clock */ #define RCC_CCIPR6_XSPI1SEL_0 (0x1UL << RCC_CCIPR6_XSPI1SEL_Pos) /*!< 0x00000001 */ #define RCC_CCIPR6_XSPI1SEL_1 (0x2UL << RCC_CCIPR6_XSPI1SEL_Pos) /*!< 0x00000002 */ #define RCC_CCIPR6_XSPI2SEL_Pos (4U) #define RCC_CCIPR6_XSPI2SEL_Msk (0x3UL << RCC_CCIPR6_XSPI2SEL_Pos) /*!< 0x00000030 */ #define RCC_CCIPR6_XSPI2SEL RCC_CCIPR6_XSPI2SEL_Msk /*!< Source selection for the XSPI2 kernel clock */ #define RCC_CCIPR6_XSPI2SEL_0 (0x1UL << RCC_CCIPR6_XSPI2SEL_Pos) /*!< 0x00000010 */ #define RCC_CCIPR6_XSPI2SEL_1 (0x2UL << RCC_CCIPR6_XSPI2SEL_Pos) /*!< 0x00000020 */ #define RCC_CCIPR6_XSPI3SEL_Pos (8U) #define RCC_CCIPR6_XSPI3SEL_Msk (0x3UL << RCC_CCIPR6_XSPI3SEL_Pos) /*!< 0x00000300 */ #define RCC_CCIPR6_XSPI3SEL RCC_CCIPR6_XSPI3SEL_Msk /*!< Source selection for the XSPI3 kernel clock */ #define RCC_CCIPR6_XSPI3SEL_0 (0x1UL << RCC_CCIPR6_XSPI3SEL_Pos) /*!< 0x00000100 */ #define RCC_CCIPR6_XSPI3SEL_1 (0x2UL << RCC_CCIPR6_XSPI3SEL_Pos) /*!< 0x00000200 */ #define RCC_CCIPR6_OTGPHY1SEL_Pos (12U) #define RCC_CCIPR6_OTGPHY1SEL_Msk (0x3UL << RCC_CCIPR6_OTGPHY1SEL_Pos) /*!< 0x00003000 */ #define RCC_CCIPR6_OTGPHY1SEL RCC_CCIPR6_OTGPHY1SEL_Msk /*!< Source selection for the OTGPHY1 kernel clock */ #define RCC_CCIPR6_OTGPHY1SEL_0 (0x1UL << RCC_CCIPR6_OTGPHY1SEL_Pos) /*!< 0x00001000 */ #define RCC_CCIPR6_OTGPHY1SEL_1 (0x2UL << RCC_CCIPR6_OTGPHY1SEL_Pos) /*!< 0x00002000 */ #define RCC_CCIPR6_OTGPHY1CKREFSEL_Pos (16U) #define RCC_CCIPR6_OTGPHY1CKREFSEL_Msk (0x1UL << RCC_CCIPR6_OTGPHY1CKREFSEL_Pos) /*!< 0x00010000 */ #define RCC_CCIPR6_OTGPHY1CKREFSEL RCC_CCIPR6_OTGPHY1CKREFSEL_Msk /*!< Set and reset by software */ #define RCC_CCIPR6_OTGPHY2SEL_Pos (20U) #define RCC_CCIPR6_OTGPHY2SEL_Msk (0x3UL << RCC_CCIPR6_OTGPHY2SEL_Pos) /*!< 0x00300000 */ #define RCC_CCIPR6_OTGPHY2SEL RCC_CCIPR6_OTGPHY2SEL_Msk /*!< Source selection for the OTGPHY2 kernel clock */ #define RCC_CCIPR6_OTGPHY2SEL_0 (0x1UL << RCC_CCIPR6_OTGPHY2SEL_Pos) /*!< 0x00100000 */ #define RCC_CCIPR6_OTGPHY2SEL_1 (0x2UL << RCC_CCIPR6_OTGPHY2SEL_Pos) /*!< 0x00200000 */ #define RCC_CCIPR6_OTGPHY2CKREFSEL_Pos (24U) #define RCC_CCIPR6_OTGPHY2CKREFSEL_Msk (0x1UL << RCC_CCIPR6_OTGPHY2CKREFSEL_Pos) /*!< 0x01000000 */ #define RCC_CCIPR6_OTGPHY2CKREFSEL RCC_CCIPR6_OTGPHY2CKREFSEL_Msk /*!< Set and reset by software */ /****************** Bit definition for RCC_CCIPR7 register ******************/ #define RCC_CCIPR7_PERSEL_Pos (0U) #define RCC_CCIPR7_PERSEL_Msk (0x7UL << RCC_CCIPR7_PERSEL_Pos) /*!< 0x00000007 */ #define RCC_CCIPR7_PERSEL RCC_CCIPR7_PERSEL_Msk /*!< Source selection for the PER kernel clock */ #define RCC_CCIPR7_PERSEL_0 (0x1UL << RCC_CCIPR7_PERSEL_Pos) /*!< 0x00000001 */ #define RCC_CCIPR7_PERSEL_1 (0x2UL << RCC_CCIPR7_PERSEL_Pos) /*!< 0x00000002 */ #define RCC_CCIPR7_PERSEL_2 (0x4UL << RCC_CCIPR7_PERSEL_Pos) /*!< 0x00000004 */ #define RCC_CCIPR7_PSSISEL_Pos (4U) #define RCC_CCIPR7_PSSISEL_Msk (0x3UL << RCC_CCIPR7_PSSISEL_Pos) /*!< 0x00000030 */ #define RCC_CCIPR7_PSSISEL RCC_CCIPR7_PSSISEL_Msk /*!< Source selection for the PSSI kernel clock */ #define RCC_CCIPR7_PSSISEL_0 (0x1UL << RCC_CCIPR7_PSSISEL_Pos) /*!< 0x00000010 */ #define RCC_CCIPR7_PSSISEL_1 (0x2UL << RCC_CCIPR7_PSSISEL_Pos) /*!< 0x00000020 */ #define RCC_CCIPR7_RTCSEL_Pos (8U) #define RCC_CCIPR7_RTCSEL_Msk (0x3UL << RCC_CCIPR7_RTCSEL_Pos) /*!< 0x00000300 */ #define RCC_CCIPR7_RTCSEL RCC_CCIPR7_RTCSEL_Msk /*!< Source selection for the RTC kernel clock */ #define RCC_CCIPR7_RTCSEL_0 (0x1UL << RCC_CCIPR7_RTCSEL_Pos) /*!< 0x00000100 */ #define RCC_CCIPR7_RTCSEL_1 (0x2UL << RCC_CCIPR7_RTCSEL_Pos) /*!< 0x00000200 */ #define RCC_CCIPR7_RTCPRE_Pos (12U) #define RCC_CCIPR7_RTCPRE_Msk (0x3FUL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x0003F000 */ #define RCC_CCIPR7_RTCPRE RCC_CCIPR7_RTCPRE_Msk /*!< RTC OSC clock divider selection (for clock hse_ck) */ #define RCC_CCIPR7_RTCPRE_0 (0x1UL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x00001000 */ #define RCC_CCIPR7_RTCPRE_1 (0x2UL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x00002000 */ #define RCC_CCIPR7_RTCPRE_2 (0x4UL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x00004000 */ #define RCC_CCIPR7_RTCPRE_3 (0x8UL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x00008000 */ #define RCC_CCIPR7_RTCPRE_4 (0x10UL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x00010000 */ #define RCC_CCIPR7_RTCPRE_5 (0x20UL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x00020000 */ #define RCC_CCIPR7_SAI1SEL_Pos (20U) #define RCC_CCIPR7_SAI1SEL_Msk (0x7UL << RCC_CCIPR7_SAI1SEL_Pos) /*!< 0x00700000 */ #define RCC_CCIPR7_SAI1SEL RCC_CCIPR7_SAI1SEL_Msk /*!< Source selection for the SAI1 kernel clock */ #define RCC_CCIPR7_SAI1SEL_0 (0x1UL << RCC_CCIPR7_SAI1SEL_Pos) /*!< 0x00100000 */ #define RCC_CCIPR7_SAI1SEL_1 (0x2UL << RCC_CCIPR7_SAI1SEL_Pos) /*!< 0x00200000 */ #define RCC_CCIPR7_SAI1SEL_2 (0x4UL << RCC_CCIPR7_SAI1SEL_Pos) /*!< 0x00400000 */ #define RCC_CCIPR7_SAI2SEL_Pos (24U) #define RCC_CCIPR7_SAI2SEL_Msk (0x7UL << RCC_CCIPR7_SAI2SEL_Pos) /*!< 0x07000000 */ #define RCC_CCIPR7_SAI2SEL RCC_CCIPR7_SAI2SEL_Msk /*!< Source selection for the SAI2 kernel clock */ #define RCC_CCIPR7_SAI2SEL_0 (0x1UL << RCC_CCIPR7_SAI2SEL_Pos) /*!< 0x01000000 */ #define RCC_CCIPR7_SAI2SEL_1 (0x2UL << RCC_CCIPR7_SAI2SEL_Pos) /*!< 0x02000000 */ #define RCC_CCIPR7_SAI2SEL_2 (0x4UL << RCC_CCIPR7_SAI2SEL_Pos) /*!< 0x04000000 */ /****************** Bit definition for RCC_CCIPR8 register ******************/ #define RCC_CCIPR8_SDMMC1SEL_Pos (0U) #define RCC_CCIPR8_SDMMC1SEL_Msk (0x3UL << RCC_CCIPR8_SDMMC1SEL_Pos) /*!< 0x00000003 */ #define RCC_CCIPR8_SDMMC1SEL RCC_CCIPR8_SDMMC1SEL_Msk /*!< Source selection for the SDMMC1 kernel clock */ #define RCC_CCIPR8_SDMMC1SEL_0 (0x1UL << RCC_CCIPR8_SDMMC1SEL_Pos) /*!< 0x00000001 */ #define RCC_CCIPR8_SDMMC1SEL_1 (0x2UL << RCC_CCIPR8_SDMMC1SEL_Pos) /*!< 0x00000002 */ #define RCC_CCIPR8_SDMMC2SEL_Pos (4U) #define RCC_CCIPR8_SDMMC2SEL_Msk (0x3UL << RCC_CCIPR8_SDMMC2SEL_Pos) /*!< 0x00000030 */ #define RCC_CCIPR8_SDMMC2SEL RCC_CCIPR8_SDMMC2SEL_Msk /*!< Source selection for the SDMMC2 kernel clock */ #define RCC_CCIPR8_SDMMC2SEL_0 (0x1UL << RCC_CCIPR8_SDMMC2SEL_Pos) /*!< 0x00000010 */ #define RCC_CCIPR8_SDMMC2SEL_1 (0x2UL << RCC_CCIPR8_SDMMC2SEL_Pos) /*!< 0x00000020 */ /****************** Bit definition for RCC_CCIPR9 register ******************/ #define RCC_CCIPR9_SPDIFRX1SEL_Pos (0U) #define RCC_CCIPR9_SPDIFRX1SEL_Msk (0x7UL << RCC_CCIPR9_SPDIFRX1SEL_Pos) /*!< 0x00000007 */ #define RCC_CCIPR9_SPDIFRX1SEL RCC_CCIPR9_SPDIFRX1SEL_Msk /*!< Source selection for the SPDIFRX1 kernel clock */ #define RCC_CCIPR9_SPDIFRX1SEL_0 (0x1UL << RCC_CCIPR9_SPDIFRX1SEL_Pos) /*!< 0x00000001 */ #define RCC_CCIPR9_SPDIFRX1SEL_1 (0x2UL << RCC_CCIPR9_SPDIFRX1SEL_Pos) /*!< 0x00000002 */ #define RCC_CCIPR9_SPDIFRX1SEL_2 (0x4UL << RCC_CCIPR9_SPDIFRX1SEL_Pos) /*!< 0x00000004 */ #define RCC_CCIPR9_SPI1SEL_Pos (4U) #define RCC_CCIPR9_SPI1SEL_Msk (0x7UL << RCC_CCIPR9_SPI1SEL_Pos) /*!< 0x00000070 */ #define RCC_CCIPR9_SPI1SEL RCC_CCIPR9_SPI1SEL_Msk /*!< Source selection for the SPI1 kernel clock */ #define RCC_CCIPR9_SPI1SEL_0 (0x1UL << RCC_CCIPR9_SPI1SEL_Pos) /*!< 0x00000010 */ #define RCC_CCIPR9_SPI1SEL_1 (0x2UL << RCC_CCIPR9_SPI1SEL_Pos) /*!< 0x00000020 */ #define RCC_CCIPR9_SPI1SEL_2 (0x4UL << RCC_CCIPR9_SPI1SEL_Pos) /*!< 0x00000040 */ #define RCC_CCIPR9_SPI2SEL_Pos (8U) #define RCC_CCIPR9_SPI2SEL_Msk (0x7UL << RCC_CCIPR9_SPI2SEL_Pos) /*!< 0x00000700 */ #define RCC_CCIPR9_SPI2SEL RCC_CCIPR9_SPI2SEL_Msk /*!< Source selection for the SPI2 kernel clock */ #define RCC_CCIPR9_SPI2SEL_0 (0x1UL << RCC_CCIPR9_SPI2SEL_Pos) /*!< 0x00000100 */ #define RCC_CCIPR9_SPI2SEL_1 (0x2UL << RCC_CCIPR9_SPI2SEL_Pos) /*!< 0x00000200 */ #define RCC_CCIPR9_SPI2SEL_2 (0x4UL << RCC_CCIPR9_SPI2SEL_Pos) /*!< 0x00000400 */ #define RCC_CCIPR9_SPI3SEL_Pos (12U) #define RCC_CCIPR9_SPI3SEL_Msk (0x7UL << RCC_CCIPR9_SPI3SEL_Pos) /*!< 0x00007000 */ #define RCC_CCIPR9_SPI3SEL RCC_CCIPR9_SPI3SEL_Msk /*!< Source selection for the SPI3 kernel clock */ #define RCC_CCIPR9_SPI3SEL_0 (0x1UL << RCC_CCIPR9_SPI3SEL_Pos) /*!< 0x00001000 */ #define RCC_CCIPR9_SPI3SEL_1 (0x2UL << RCC_CCIPR9_SPI3SEL_Pos) /*!< 0x00002000 */ #define RCC_CCIPR9_SPI3SEL_2 (0x4UL << RCC_CCIPR9_SPI3SEL_Pos) /*!< 0x00004000 */ #define RCC_CCIPR9_SPI4SEL_Pos (16U) #define RCC_CCIPR9_SPI4SEL_Msk (0x7UL << RCC_CCIPR9_SPI4SEL_Pos) /*!< 0x00070000 */ #define RCC_CCIPR9_SPI4SEL RCC_CCIPR9_SPI4SEL_Msk /*!< Source selection for the SPI4 kernel clock */ #define RCC_CCIPR9_SPI4SEL_0 (0x1UL << RCC_CCIPR9_SPI4SEL_Pos) /*!< 0x00010000 */ #define RCC_CCIPR9_SPI4SEL_1 (0x2UL << RCC_CCIPR9_SPI4SEL_Pos) /*!< 0x00020000 */ #define RCC_CCIPR9_SPI4SEL_2 (0x4UL << RCC_CCIPR9_SPI4SEL_Pos) /*!< 0x00040000 */ #define RCC_CCIPR9_SPI5SEL_Pos (20U) #define RCC_CCIPR9_SPI5SEL_Msk (0x7UL << RCC_CCIPR9_SPI5SEL_Pos) /*!< 0x00700000 */ #define RCC_CCIPR9_SPI5SEL RCC_CCIPR9_SPI5SEL_Msk /*!< Source selection for the SPI5 kernel clock */ #define RCC_CCIPR9_SPI5SEL_0 (0x1UL << RCC_CCIPR9_SPI5SEL_Pos) /*!< 0x00100000 */ #define RCC_CCIPR9_SPI5SEL_1 (0x2UL << RCC_CCIPR9_SPI5SEL_Pos) /*!< 0x00200000 */ #define RCC_CCIPR9_SPI5SEL_2 (0x4UL << RCC_CCIPR9_SPI5SEL_Pos) /*!< 0x00400000 */ #define RCC_CCIPR9_SPI6SEL_Pos (24U) #define RCC_CCIPR9_SPI6SEL_Msk (0x7UL << RCC_CCIPR9_SPI6SEL_Pos) /*!< 0x07000000 */ #define RCC_CCIPR9_SPI6SEL RCC_CCIPR9_SPI6SEL_Msk /*!< Source selection for the SPI6 kernel clock */ #define RCC_CCIPR9_SPI6SEL_0 (0x1UL << RCC_CCIPR9_SPI6SEL_Pos) /*!< 0x01000000 */ #define RCC_CCIPR9_SPI6SEL_1 (0x2UL << RCC_CCIPR9_SPI6SEL_Pos) /*!< 0x02000000 */ #define RCC_CCIPR9_SPI6SEL_2 (0x4UL << RCC_CCIPR9_SPI6SEL_Pos) /*!< 0x04000000 */ /***************** Bit definition for RCC_CCIPR12 register ******************/ #define RCC_CCIPR12_LPTIM1SEL_Pos (8U) #define RCC_CCIPR12_LPTIM1SEL_Msk (0x7UL << RCC_CCIPR12_LPTIM1SEL_Pos) /*!< 0x00000700 */ #define RCC_CCIPR12_LPTIM1SEL RCC_CCIPR12_LPTIM1SEL_Msk /*!< Source selection for the LPTIM1 kernel clock */ #define RCC_CCIPR12_LPTIM1SEL_0 (0x1UL << RCC_CCIPR12_LPTIM1SEL_Pos) /*!< 0x00000100 */ #define RCC_CCIPR12_LPTIM1SEL_1 (0x2UL << RCC_CCIPR12_LPTIM1SEL_Pos) /*!< 0x00000200 */ #define RCC_CCIPR12_LPTIM1SEL_2 (0x4UL << RCC_CCIPR12_LPTIM1SEL_Pos) /*!< 0x00000400 */ #define RCC_CCIPR12_LPTIM2SEL_Pos (12U) #define RCC_CCIPR12_LPTIM2SEL_Msk (0x7UL << RCC_CCIPR12_LPTIM2SEL_Pos) /*!< 0x00007000 */ #define RCC_CCIPR12_LPTIM2SEL RCC_CCIPR12_LPTIM2SEL_Msk /*!< Source selection for the LPTIM2 kernel clock */ #define RCC_CCIPR12_LPTIM2SEL_0 (0x1UL << RCC_CCIPR12_LPTIM2SEL_Pos) /*!< 0x00001000 */ #define RCC_CCIPR12_LPTIM2SEL_1 (0x2UL << RCC_CCIPR12_LPTIM2SEL_Pos) /*!< 0x00002000 */ #define RCC_CCIPR12_LPTIM2SEL_2 (0x4UL << RCC_CCIPR12_LPTIM2SEL_Pos) /*!< 0x00004000 */ #define RCC_CCIPR12_LPTIM3SEL_Pos (16U) #define RCC_CCIPR12_LPTIM3SEL_Msk (0x7UL << RCC_CCIPR12_LPTIM3SEL_Pos) /*!< 0x00070000 */ #define RCC_CCIPR12_LPTIM3SEL RCC_CCIPR12_LPTIM3SEL_Msk /*!< Source selection for the LPTIM3 kernel clock */ #define RCC_CCIPR12_LPTIM3SEL_0 (0x1UL << RCC_CCIPR12_LPTIM3SEL_Pos) /*!< 0x00010000 */ #define RCC_CCIPR12_LPTIM3SEL_1 (0x2UL << RCC_CCIPR12_LPTIM3SEL_Pos) /*!< 0x00020000 */ #define RCC_CCIPR12_LPTIM3SEL_2 (0x4UL << RCC_CCIPR12_LPTIM3SEL_Pos) /*!< 0x00040000 */ #define RCC_CCIPR12_LPTIM4SEL_Pos (20U) #define RCC_CCIPR12_LPTIM4SEL_Msk (0x7UL << RCC_CCIPR12_LPTIM4SEL_Pos) /*!< 0x00700000 */ #define RCC_CCIPR12_LPTIM4SEL RCC_CCIPR12_LPTIM4SEL_Msk /*!< Source selection for the LPTIM4 kernel clock */ #define RCC_CCIPR12_LPTIM4SEL_0 (0x1UL << RCC_CCIPR12_LPTIM4SEL_Pos) /*!< 0x00100000 */ #define RCC_CCIPR12_LPTIM4SEL_1 (0x2UL << RCC_CCIPR12_LPTIM4SEL_Pos) /*!< 0x00200000 */ #define RCC_CCIPR12_LPTIM4SEL_2 (0x4UL << RCC_CCIPR12_LPTIM4SEL_Pos) /*!< 0x00400000 */ #define RCC_CCIPR12_LPTIM5SEL_Pos (24U) #define RCC_CCIPR12_LPTIM5SEL_Msk (0x7UL << RCC_CCIPR12_LPTIM5SEL_Pos) /*!< 0x07000000 */ #define RCC_CCIPR12_LPTIM5SEL RCC_CCIPR12_LPTIM5SEL_Msk /*!< Source selection for the LPTIM5 kernel clock */ #define RCC_CCIPR12_LPTIM5SEL_0 (0x1UL << RCC_CCIPR12_LPTIM5SEL_Pos) /*!< 0x01000000 */ #define RCC_CCIPR12_LPTIM5SEL_1 (0x2UL << RCC_CCIPR12_LPTIM5SEL_Pos) /*!< 0x02000000 */ #define RCC_CCIPR12_LPTIM5SEL_2 (0x4UL << RCC_CCIPR12_LPTIM5SEL_Pos) /*!< 0x04000000 */ /***************** Bit definition for RCC_CCIPR13 register ******************/ #define RCC_CCIPR13_USART1SEL_Pos (0U) #define RCC_CCIPR13_USART1SEL_Msk (0x7UL << RCC_CCIPR13_USART1SEL_Pos) /*!< 0x00000007 */ #define RCC_CCIPR13_USART1SEL RCC_CCIPR13_USART1SEL_Msk /*!< Source selection for the USART1 kernel clock */ #define RCC_CCIPR13_USART1SEL_0 (0x1UL << RCC_CCIPR13_USART1SEL_Pos) /*!< 0x00000001 */ #define RCC_CCIPR13_USART1SEL_1 (0x2UL << RCC_CCIPR13_USART1SEL_Pos) /*!< 0x00000002 */ #define RCC_CCIPR13_USART1SEL_2 (0x4UL << RCC_CCIPR13_USART1SEL_Pos) /*!< 0x00000004 */ #define RCC_CCIPR13_USART2SEL_Pos (4U) #define RCC_CCIPR13_USART2SEL_Msk (0x7UL << RCC_CCIPR13_USART2SEL_Pos) /*!< 0x00000070 */ #define RCC_CCIPR13_USART2SEL RCC_CCIPR13_USART2SEL_Msk /*!< Source selection for the USART2 kernel clock */ #define RCC_CCIPR13_USART2SEL_0 (0x1UL << RCC_CCIPR13_USART2SEL_Pos) /*!< 0x00000010 */ #define RCC_CCIPR13_USART2SEL_1 (0x2UL << RCC_CCIPR13_USART2SEL_Pos) /*!< 0x00000020 */ #define RCC_CCIPR13_USART2SEL_2 (0x4UL << RCC_CCIPR13_USART2SEL_Pos) /*!< 0x00000040 */ #define RCC_CCIPR13_USART3SEL_Pos (8U) #define RCC_CCIPR13_USART3SEL_Msk (0x7UL << RCC_CCIPR13_USART3SEL_Pos) /*!< 0x00000700 */ #define RCC_CCIPR13_USART3SEL RCC_CCIPR13_USART3SEL_Msk /*!< Source selection for the USART3 kernel clock */ #define RCC_CCIPR13_USART3SEL_0 (0x1UL << RCC_CCIPR13_USART3SEL_Pos) /*!< 0x00000100 */ #define RCC_CCIPR13_USART3SEL_1 (0x2UL << RCC_CCIPR13_USART3SEL_Pos) /*!< 0x00000200 */ #define RCC_CCIPR13_USART3SEL_2 (0x4UL << RCC_CCIPR13_USART3SEL_Pos) /*!< 0x00000400 */ #define RCC_CCIPR13_UART4SEL_Pos (12U) #define RCC_CCIPR13_UART4SEL_Msk (0x7UL << RCC_CCIPR13_UART4SEL_Pos) /*!< 0x00007000 */ #define RCC_CCIPR13_UART4SEL RCC_CCIPR13_UART4SEL_Msk /*!< Source selection for the UART4 kernel clock */ #define RCC_CCIPR13_UART4SEL_0 (0x1UL << RCC_CCIPR13_UART4SEL_Pos) /*!< 0x00001000 */ #define RCC_CCIPR13_UART4SEL_1 (0x2UL << RCC_CCIPR13_UART4SEL_Pos) /*!< 0x00002000 */ #define RCC_CCIPR13_UART4SEL_2 (0x4UL << RCC_CCIPR13_UART4SEL_Pos) /*!< 0x00004000 */ #define RCC_CCIPR13_UART5SEL_Pos (16U) #define RCC_CCIPR13_UART5SEL_Msk (0x7UL << RCC_CCIPR13_UART5SEL_Pos) /*!< 0x00070000 */ #define RCC_CCIPR13_UART5SEL RCC_CCIPR13_UART5SEL_Msk /*!< Source selection for the UART5 kernel clock */ #define RCC_CCIPR13_UART5SEL_0 (0x1UL << RCC_CCIPR13_UART5SEL_Pos) /*!< 0x00010000 */ #define RCC_CCIPR13_UART5SEL_1 (0x2UL << RCC_CCIPR13_UART5SEL_Pos) /*!< 0x00020000 */ #define RCC_CCIPR13_UART5SEL_2 (0x4UL << RCC_CCIPR13_UART5SEL_Pos) /*!< 0x00040000 */ #define RCC_CCIPR13_USART6SEL_Pos (20U) #define RCC_CCIPR13_USART6SEL_Msk (0x7UL << RCC_CCIPR13_USART6SEL_Pos) /*!< 0x00700000 */ #define RCC_CCIPR13_USART6SEL RCC_CCIPR13_USART6SEL_Msk /*!< Source selection for the USART6 kernel clock */ #define RCC_CCIPR13_USART6SEL_0 (0x1UL << RCC_CCIPR13_USART6SEL_Pos) /*!< 0x00100000 */ #define RCC_CCIPR13_USART6SEL_1 (0x2UL << RCC_CCIPR13_USART6SEL_Pos) /*!< 0x00200000 */ #define RCC_CCIPR13_USART6SEL_2 (0x4UL << RCC_CCIPR13_USART6SEL_Pos) /*!< 0x00400000 */ #define RCC_CCIPR13_UART7SEL_Pos (24U) #define RCC_CCIPR13_UART7SEL_Msk (0x7UL << RCC_CCIPR13_UART7SEL_Pos) /*!< 0x07000000 */ #define RCC_CCIPR13_UART7SEL RCC_CCIPR13_UART7SEL_Msk /*!< Source selection for the UART7 kernel clock */ #define RCC_CCIPR13_UART7SEL_0 (0x1UL << RCC_CCIPR13_UART7SEL_Pos) /*!< 0x01000000 */ #define RCC_CCIPR13_UART7SEL_1 (0x2UL << RCC_CCIPR13_UART7SEL_Pos) /*!< 0x02000000 */ #define RCC_CCIPR13_UART7SEL_2 (0x4UL << RCC_CCIPR13_UART7SEL_Pos) /*!< 0x04000000 */ #define RCC_CCIPR13_UART8SEL_Pos (28U) #define RCC_CCIPR13_UART8SEL_Msk (0x7UL << RCC_CCIPR13_UART8SEL_Pos) /*!< 0x70000000 */ #define RCC_CCIPR13_UART8SEL RCC_CCIPR13_UART8SEL_Msk /*!< Source selection for the UART8 kernel clock */ #define RCC_CCIPR13_UART8SEL_0 (0x1UL << RCC_CCIPR13_UART8SEL_Pos) /*!< 0x10000000 */ #define RCC_CCIPR13_UART8SEL_1 (0x2UL << RCC_CCIPR13_UART8SEL_Pos) /*!< 0x20000000 */ #define RCC_CCIPR13_UART8SEL_2 (0x4UL << RCC_CCIPR13_UART8SEL_Pos) /*!< 0x40000000 */ /***************** Bit definition for RCC_CCIPR14 register ******************/ #define RCC_CCIPR14_UART9SEL_Pos (0U) #define RCC_CCIPR14_UART9SEL_Msk (0x7UL << RCC_CCIPR14_UART9SEL_Pos) /*!< 0x00000007 */ #define RCC_CCIPR14_UART9SEL RCC_CCIPR14_UART9SEL_Msk /*!< Source selection for the UART9 kernel clock */ #define RCC_CCIPR14_UART9SEL_0 (0x1UL << RCC_CCIPR14_UART9SEL_Pos) /*!< 0x00000001 */ #define RCC_CCIPR14_UART9SEL_1 (0x2UL << RCC_CCIPR14_UART9SEL_Pos) /*!< 0x00000002 */ #define RCC_CCIPR14_UART9SEL_2 (0x4UL << RCC_CCIPR14_UART9SEL_Pos) /*!< 0x00000004 */ #define RCC_CCIPR14_USART10SEL_Pos (4U) #define RCC_CCIPR14_USART10SEL_Msk (0x7UL << RCC_CCIPR14_USART10SEL_Pos) /*!< 0x00000070 */ #define RCC_CCIPR14_USART10SEL RCC_CCIPR14_USART10SEL_Msk /*!< Source selection for the USART10 kernel clock */ #define RCC_CCIPR14_USART10SEL_0 (0x1UL << RCC_CCIPR14_USART10SEL_Pos) /*!< 0x00000010 */ #define RCC_CCIPR14_USART10SEL_1 (0x2UL << RCC_CCIPR14_USART10SEL_Pos) /*!< 0x00000020 */ #define RCC_CCIPR14_USART10SEL_2 (0x4UL << RCC_CCIPR14_USART10SEL_Pos) /*!< 0x00000040 */ #define RCC_CCIPR14_LPUART1SEL_Pos (8U) #define RCC_CCIPR14_LPUART1SEL_Msk (0x7UL << RCC_CCIPR14_LPUART1SEL_Pos) /*!< 0x00000700 */ #define RCC_CCIPR14_LPUART1SEL RCC_CCIPR14_LPUART1SEL_Msk /*!< Source selection for the LPUART1 kernel clock */ #define RCC_CCIPR14_LPUART1SEL_0 (0x1UL << RCC_CCIPR14_LPUART1SEL_Pos) /*!< 0x00000100 */ #define RCC_CCIPR14_LPUART1SEL_1 (0x2UL << RCC_CCIPR14_LPUART1SEL_Pos) /*!< 0x00000200 */ #define RCC_CCIPR14_LPUART1SEL_2 (0x4UL << RCC_CCIPR14_LPUART1SEL_Pos) /*!< 0x00000400 */ /***************** Bit definition for RCC_MISCRSTR register *****************/ #define RCC_MISCRSTR_DBGRST_Pos (0U) #define RCC_MISCRSTR_DBGRST_Msk (0x1UL << RCC_MISCRSTR_DBGRST_Pos) /*!< 0x00000001 */ #define RCC_MISCRSTR_DBGRST RCC_MISCRSTR_DBGRST_Msk /*!< DBG reset */ #define RCC_MISCRSTR_XSPIPHY1RST_Pos (4U) #define RCC_MISCRSTR_XSPIPHY1RST_Msk (0x1UL << RCC_MISCRSTR_XSPIPHY1RST_Pos) /*!< 0x00000010 */ #define RCC_MISCRSTR_XSPIPHY1RST RCC_MISCRSTR_XSPIPHY1RST_Msk /*!< XSPIPHY1 reset */ #define RCC_MISCRSTR_XSPIPHY2RST_Pos (5U) #define RCC_MISCRSTR_XSPIPHY2RST_Msk (0x1UL << RCC_MISCRSTR_XSPIPHY2RST_Pos) /*!< 0x00000020 */ #define RCC_MISCRSTR_XSPIPHY2RST RCC_MISCRSTR_XSPIPHY2RST_Msk /*!< XSPIPHY2 reset */ #define RCC_MISCRSTR_SDMMC1DLLRST_Pos (7U) #define RCC_MISCRSTR_SDMMC1DLLRST_Msk (0x1UL << RCC_MISCRSTR_SDMMC1DLLRST_Pos) /*!< 0x00000080 */ #define RCC_MISCRSTR_SDMMC1DLLRST RCC_MISCRSTR_SDMMC1DLLRST_Msk /*!< SDMMC1DLL reset */ #define RCC_MISCRSTR_SDMMC2DLLRST_Pos (8U) #define RCC_MISCRSTR_SDMMC2DLLRST_Msk (0x1UL << RCC_MISCRSTR_SDMMC2DLLRST_Pos) /*!< 0x00000100 */ #define RCC_MISCRSTR_SDMMC2DLLRST RCC_MISCRSTR_SDMMC2DLLRST_Msk /*!< SDMMC2DLL reset */ /***************** Bit definition for RCC_MEMRSTR register ******************/ #define RCC_MEMRSTR_AXISRAM3RST_Pos (0U) #define RCC_MEMRSTR_AXISRAM3RST_Msk (0x1UL << RCC_MEMRSTR_AXISRAM3RST_Pos)/*!< 0x00000001 */ #define RCC_MEMRSTR_AXISRAM3RST RCC_MEMRSTR_AXISRAM3RST_Msk /*!< AXISRAM3 reset */ #define RCC_MEMRSTR_AXISRAM4RST_Pos (1U) #define RCC_MEMRSTR_AXISRAM4RST_Msk (0x1UL << RCC_MEMRSTR_AXISRAM4RST_Pos)/*!< 0x00000002 */ #define RCC_MEMRSTR_AXISRAM4RST RCC_MEMRSTR_AXISRAM4RST_Msk /*!< AXISRAM4 reset */ #define RCC_MEMRSTR_AXISRAM5RST_Pos (2U) #define RCC_MEMRSTR_AXISRAM5RST_Msk (0x1UL << RCC_MEMRSTR_AXISRAM5RST_Pos)/*!< 0x00000004 */ #define RCC_MEMRSTR_AXISRAM5RST RCC_MEMRSTR_AXISRAM5RST_Msk /*!< AXISRAM5 reset */ #define RCC_MEMRSTR_AXISRAM6RST_Pos (3U) #define RCC_MEMRSTR_AXISRAM6RST_Msk (0x1UL << RCC_MEMRSTR_AXISRAM6RST_Pos)/*!< 0x00000008 */ #define RCC_MEMRSTR_AXISRAM6RST RCC_MEMRSTR_AXISRAM6RST_Msk /*!< AXISRAM6 reset */ #define RCC_MEMRSTR_AHBSRAM1RST_Pos (4U) #define RCC_MEMRSTR_AHBSRAM1RST_Msk (0x1UL << RCC_MEMRSTR_AHBSRAM1RST_Pos)/*!< 0x00000010 */ #define RCC_MEMRSTR_AHBSRAM1RST RCC_MEMRSTR_AHBSRAM1RST_Msk /*!< AHBSRAM1 reset */ #define RCC_MEMRSTR_AHBSRAM2RST_Pos (5U) #define RCC_MEMRSTR_AHBSRAM2RST_Msk (0x1UL << RCC_MEMRSTR_AHBSRAM2RST_Pos)/*!< 0x00000020 */ #define RCC_MEMRSTR_AHBSRAM2RST RCC_MEMRSTR_AHBSRAM2RST_Msk /*!< AHBSRAM2 reset */ #define RCC_MEMRSTR_AXISRAM1RST_Pos (7U) #define RCC_MEMRSTR_AXISRAM1RST_Msk (0x1UL << RCC_MEMRSTR_AXISRAM1RST_Pos)/*!< 0x00000080 */ #define RCC_MEMRSTR_AXISRAM1RST RCC_MEMRSTR_AXISRAM1RST_Msk /*!< AXISRAM1 reset */ #define RCC_MEMRSTR_AXISRAM2RST_Pos (8U) #define RCC_MEMRSTR_AXISRAM2RST_Msk (0x1UL << RCC_MEMRSTR_AXISRAM2RST_Pos)/*!< 0x00000100 */ #define RCC_MEMRSTR_AXISRAM2RST RCC_MEMRSTR_AXISRAM2RST_Msk /*!< AXISRAM2 reset */ #define RCC_MEMRSTR_FLEXRAMRST_Pos (9U) #define RCC_MEMRSTR_FLEXRAMRST_Msk (0x1UL << RCC_MEMRSTR_FLEXRAMRST_Pos) /*!< 0x00000200 */ #define RCC_MEMRSTR_FLEXRAMRST RCC_MEMRSTR_FLEXRAMRST_Msk /*!< FLEXRAM reset */ #define RCC_MEMRSTR_CACHEAXIRAMRST_Pos (10U) #define RCC_MEMRSTR_CACHEAXIRAMRST_Msk (0x1UL << RCC_MEMRSTR_CACHEAXIRAMRST_Pos) /*!< 0x00000400 */ #define RCC_MEMRSTR_CACHEAXIRAMRST RCC_MEMRSTR_CACHEAXIRAMRST_Msk /*!< CACHEAXIRAM reset */ #define RCC_MEMRSTR_VENCRAMRST_Pos (11U) #define RCC_MEMRSTR_VENCRAMRST_Msk (0x1UL << RCC_MEMRSTR_VENCRAMRST_Pos) /*!< 0x00000800 */ #define RCC_MEMRSTR_VENCRAMRST RCC_MEMRSTR_VENCRAMRST_Msk /*!< VENCRAM reset */ #define RCC_MEMRSTR_BOOTROMRST_Pos (12U) #define RCC_MEMRSTR_BOOTROMRST_Msk (0x1UL << RCC_MEMRSTR_BOOTROMRST_Pos) /*!< 0x00001000 */ #define RCC_MEMRSTR_BOOTROMRST RCC_MEMRSTR_BOOTROMRST_Msk /*!< Boot ROM reset */ /***************** Bit definition for RCC_AHB1RSTR register *****************/ #define RCC_AHB1RSTR_GPDMA1RST_Pos (4U) #define RCC_AHB1RSTR_GPDMA1RST_Msk (0x1UL << RCC_AHB1RSTR_GPDMA1RST_Pos) /*!< 0x00000010 */ #define RCC_AHB1RSTR_GPDMA1RST RCC_AHB1RSTR_GPDMA1RST_Msk /*!< GPDMA1 reset */ #define RCC_AHB1RSTR_ADC12RST_Pos (5U) #define RCC_AHB1RSTR_ADC12RST_Msk (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos) /*!< 0x00000020 */ #define RCC_AHB1RSTR_ADC12RST RCC_AHB1RSTR_ADC12RST_Msk /*!< ADC12 reset */ /***************** Bit definition for RCC_AHB2RSTR register *****************/ #define RCC_AHB2RSTR_RAMCFGRST_Pos (12U) #define RCC_AHB2RSTR_RAMCFGRST_Msk (0x1UL << RCC_AHB2RSTR_RAMCFGRST_Pos) /*!< 0x00001000 */ #define RCC_AHB2RSTR_RAMCFGRST RCC_AHB2RSTR_RAMCFGRST_Msk /*!< RAMCFG reset */ #define RCC_AHB2RSTR_MDF1RST_Pos (16U) #define RCC_AHB2RSTR_MDF1RST_Msk (0x1UL << RCC_AHB2RSTR_MDF1RST_Pos) /*!< 0x00010000 */ #define RCC_AHB2RSTR_MDF1RST RCC_AHB2RSTR_MDF1RST_Msk /*!< MDF1 reset */ #define RCC_AHB2RSTR_ADF1RST_Pos (17U) #define RCC_AHB2RSTR_ADF1RST_Msk (0x1UL << RCC_AHB2RSTR_ADF1RST_Pos) /*!< 0x00020000 */ #define RCC_AHB2RSTR_ADF1RST RCC_AHB2RSTR_ADF1RST_Msk /*!< ADF1 reset */ /***************** Bit definition for RCC_AHB3RSTR register *****************/ #define RCC_AHB3RSTR_RNGRST_Pos (0U) #define RCC_AHB3RSTR_RNGRST_Msk (0x1UL << RCC_AHB3RSTR_RNGRST_Pos) /*!< 0x00000001 */ #define RCC_AHB3RSTR_RNGRST RCC_AHB3RSTR_RNGRST_Msk /*!< RNG reset */ #define RCC_AHB3RSTR_HASHRST_Pos (1U) #define RCC_AHB3RSTR_HASHRST_Msk (0x1UL << RCC_AHB3RSTR_HASHRST_Pos) /*!< 0x00000002 */ #define RCC_AHB3RSTR_HASHRST RCC_AHB3RSTR_HASHRST_Msk /*!< HASH reset */ #define RCC_AHB3RSTR_CRYPRST_Pos (2U) #define RCC_AHB3RSTR_CRYPRST_Msk (0x1UL << RCC_AHB3RSTR_CRYPRST_Pos) /*!< 0x00000004 */ #define RCC_AHB3RSTR_CRYPRST RCC_AHB3RSTR_CRYPRST_Msk /*!< CRYP reset */ #define RCC_AHB3RSTR_SAESRST_Pos (4U) #define RCC_AHB3RSTR_SAESRST_Msk (0x1UL << RCC_AHB3RSTR_SAESRST_Pos) /*!< 0x00000010 */ #define RCC_AHB3RSTR_SAESRST RCC_AHB3RSTR_SAESRST_Msk /*!< SAES reset */ #define RCC_AHB3RSTR_PKARST_Pos (8U) #define RCC_AHB3RSTR_PKARST_Msk (0x1UL << RCC_AHB3RSTR_PKARST_Pos) /*!< 0x00000100 */ #define RCC_AHB3RSTR_PKARST RCC_AHB3RSTR_PKARST_Msk /*!< PKA reset */ #define RCC_AHB3RSTR_IACRST_Pos (10U) #define RCC_AHB3RSTR_IACRST_Msk (0x1UL << RCC_AHB3RSTR_IACRST_Pos) /*!< 0x00000400 */ #define RCC_AHB3RSTR_IACRST RCC_AHB3RSTR_IACRST_Msk /*!< IAC reset */ /***************** Bit definition for RCC_AHB4RSTR register *****************/ #define RCC_AHB4RSTR_GPIOARST_Pos (0U) #define RCC_AHB4RSTR_GPIOARST_Msk (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos) /*!< 0x00000001 */ #define RCC_AHB4RSTR_GPIOARST RCC_AHB4RSTR_GPIOARST_Msk /*!< GPIO A reset */ #define RCC_AHB4RSTR_GPIOBRST_Pos (1U) #define RCC_AHB4RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos) /*!< 0x00000002 */ #define RCC_AHB4RSTR_GPIOBRST RCC_AHB4RSTR_GPIOBRST_Msk /*!< GPIO B reset */ #define RCC_AHB4RSTR_GPIOCRST_Pos (2U) #define RCC_AHB4RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos) /*!< 0x00000004 */ #define RCC_AHB4RSTR_GPIOCRST RCC_AHB4RSTR_GPIOCRST_Msk /*!< GPIO C reset */ #define RCC_AHB4RSTR_GPIODRST_Pos (3U) #define RCC_AHB4RSTR_GPIODRST_Msk (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos) /*!< 0x00000008 */ #define RCC_AHB4RSTR_GPIODRST RCC_AHB4RSTR_GPIODRST_Msk /*!< GPIO D reset */ #define RCC_AHB4RSTR_GPIOERST_Pos (4U) #define RCC_AHB4RSTR_GPIOERST_Msk (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos) /*!< 0x00000010 */ #define RCC_AHB4RSTR_GPIOERST RCC_AHB4RSTR_GPIOERST_Msk /*!< GPIO E reset */ #define RCC_AHB4RSTR_GPIOFRST_Pos (5U) #define RCC_AHB4RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos) /*!< 0x00000020 */ #define RCC_AHB4RSTR_GPIOFRST RCC_AHB4RSTR_GPIOFRST_Msk /*!< GPIO F reset */ #define RCC_AHB4RSTR_GPIOGRST_Pos (6U) #define RCC_AHB4RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos) /*!< 0x00000040 */ #define RCC_AHB4RSTR_GPIOGRST RCC_AHB4RSTR_GPIOGRST_Msk /*!< GPIO G reset */ #define RCC_AHB4RSTR_GPIOHRST_Pos (7U) #define RCC_AHB4RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos) /*!< 0x00000080 */ #define RCC_AHB4RSTR_GPIOHRST RCC_AHB4RSTR_GPIOHRST_Msk /*!< GPIO H reset */ #define RCC_AHB4RSTR_GPIONRST_Pos (13U) #define RCC_AHB4RSTR_GPIONRST_Msk (0x1UL << RCC_AHB4RSTR_GPIONRST_Pos) /*!< 0x00002000 */ #define RCC_AHB4RSTR_GPIONRST RCC_AHB4RSTR_GPIONRST_Msk /*!< GPIO N reset */ #define RCC_AHB4RSTR_GPIOORST_Pos (14U) #define RCC_AHB4RSTR_GPIOORST_Msk (0x1UL << RCC_AHB4RSTR_GPIOORST_Pos) /*!< 0x00004000 */ #define RCC_AHB4RSTR_GPIOORST RCC_AHB4RSTR_GPIOORST_Msk /*!< GPIO O reset */ #define RCC_AHB4RSTR_GPIOPRST_Pos (15U) #define RCC_AHB4RSTR_GPIOPRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOPRST_Pos) /*!< 0x00008000 */ #define RCC_AHB4RSTR_GPIOPRST RCC_AHB4RSTR_GPIOPRST_Msk /*!< GPIO P reset */ #define RCC_AHB4RSTR_GPIOQRST_Pos (16U) #define RCC_AHB4RSTR_GPIOQRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOQRST_Pos) /*!< 0x00010000 */ #define RCC_AHB4RSTR_GPIOQRST RCC_AHB4RSTR_GPIOQRST_Msk /*!< GPIO Q reset */ #define RCC_AHB4RSTR_PWRRST_Pos (18U) #define RCC_AHB4RSTR_PWRRST_Msk (0x1UL << RCC_AHB4RSTR_PWRRST_Pos) /*!< 0x00040000 */ #define RCC_AHB4RSTR_PWRRST RCC_AHB4RSTR_PWRRST_Msk /*!< PWR reset */ #define RCC_AHB4RSTR_CRCRST_Pos (19U) #define RCC_AHB4RSTR_CRCRST_Msk (0x1UL << RCC_AHB4RSTR_CRCRST_Pos) /*!< 0x00080000 */ #define RCC_AHB4RSTR_CRCRST RCC_AHB4RSTR_CRCRST_Msk /*!< CRC reset */ /***************** Bit definition for RCC_AHB5RSTR register *****************/ #define RCC_AHB5RSTR_HPDMA1RST_Pos (0U) #define RCC_AHB5RSTR_HPDMA1RST_Msk (0x1UL << RCC_AHB5RSTR_HPDMA1RST_Pos) /*!< 0x00000001 */ #define RCC_AHB5RSTR_HPDMA1RST RCC_AHB5RSTR_HPDMA1RST_Msk /*!< HPDMA1 reset */ #define RCC_AHB5RSTR_DMA2DRST_Pos (1U) #define RCC_AHB5RSTR_DMA2DRST_Msk (0x1UL << RCC_AHB5RSTR_DMA2DRST_Pos) /*!< 0x00000002 */ #define RCC_AHB5RSTR_DMA2DRST RCC_AHB5RSTR_DMA2DRST_Msk /*!< DMA2D reset */ #define RCC_AHB5RSTR_JPEGRST_Pos (3U) #define RCC_AHB5RSTR_JPEGRST_Msk (0x1UL << RCC_AHB5RSTR_JPEGRST_Pos) /*!< 0x00000008 */ #define RCC_AHB5RSTR_JPEGRST RCC_AHB5RSTR_JPEGRST_Msk /*!< JPEG reset */ #define RCC_AHB5RSTR_FMCRST_Pos (4U) #define RCC_AHB5RSTR_FMCRST_Msk (0x1UL << RCC_AHB5RSTR_FMCRST_Pos) /*!< 0x00000010 */ #define RCC_AHB5RSTR_FMCRST RCC_AHB5RSTR_FMCRST_Msk /*!< FMC reset */ #define RCC_AHB5RSTR_XSPI1RST_Pos (5U) #define RCC_AHB5RSTR_XSPI1RST_Msk (0x1UL << RCC_AHB5RSTR_XSPI1RST_Pos) /*!< 0x00000020 */ #define RCC_AHB5RSTR_XSPI1RST RCC_AHB5RSTR_XSPI1RST_Msk /*!< XSPI1 reset */ #define RCC_AHB5RSTR_PSSIRST_Pos (6U) #define RCC_AHB5RSTR_PSSIRST_Msk (0x1UL << RCC_AHB5RSTR_PSSIRST_Pos) /*!< 0x00000040 */ #define RCC_AHB5RSTR_PSSIRST RCC_AHB5RSTR_PSSIRST_Msk /*!< PSSI reset */ #define RCC_AHB5RSTR_SDMMC2RST_Pos (7U) #define RCC_AHB5RSTR_SDMMC2RST_Msk (0x1UL << RCC_AHB5RSTR_SDMMC2RST_Pos) /*!< 0x00000080 */ #define RCC_AHB5RSTR_SDMMC2RST RCC_AHB5RSTR_SDMMC2RST_Msk /*!< SDMMC2 reset */ #define RCC_AHB5RSTR_SDMMC1RST_Pos (8U) #define RCC_AHB5RSTR_SDMMC1RST_Msk (0x1UL << RCC_AHB5RSTR_SDMMC1RST_Pos) /*!< 0x00000100 */ #define RCC_AHB5RSTR_SDMMC1RST RCC_AHB5RSTR_SDMMC1RST_Msk /*!< SDMMC1 reset */ #define RCC_AHB5RSTR_XSPI2RST_Pos (12U) #define RCC_AHB5RSTR_XSPI2RST_Msk (0x1UL << RCC_AHB5RSTR_XSPI2RST_Pos) /*!< 0x00001000 */ #define RCC_AHB5RSTR_XSPI2RST RCC_AHB5RSTR_XSPI2RST_Msk /*!< XSPI2 reset */ #define RCC_AHB5RSTR_XSPIMRST_Pos (13U) #define RCC_AHB5RSTR_XSPIMRST_Msk (0x1UL << RCC_AHB5RSTR_XSPIMRST_Pos) /*!< 0x00002000 */ #define RCC_AHB5RSTR_XSPIMRST RCC_AHB5RSTR_XSPIMRST_Msk /*!< XSPIM reset */ #define RCC_AHB5RSTR_XSPI3RST_Pos (17U) #define RCC_AHB5RSTR_XSPI3RST_Msk (0x1UL << RCC_AHB5RSTR_XSPI3RST_Pos) /*!< 0x00020000 */ #define RCC_AHB5RSTR_XSPI3RST RCC_AHB5RSTR_XSPI3RST_Msk /*!< XSPI3 reset */ #define RCC_AHB5RSTR_GFXMMURST_Pos (19U) #define RCC_AHB5RSTR_GFXMMURST_Msk (0x1UL << RCC_AHB5RSTR_GFXMMURST_Pos) /*!< 0x00080000 */ #define RCC_AHB5RSTR_GFXMMURST RCC_AHB5RSTR_GFXMMURST_Msk /*!< GFXMMU reset */ #define RCC_AHB5RSTR_GPU2DRST_Pos (20U) #define RCC_AHB5RSTR_GPU2DRST_Msk (0x1UL << RCC_AHB5RSTR_GPU2DRST_Pos) /*!< 0x00100000 */ #define RCC_AHB5RSTR_GPU2DRST RCC_AHB5RSTR_GPU2DRST_Msk /*!< GPU2D reset */ #define RCC_AHB5RSTR_OTG1PHYCTLRST_Pos (23U) #define RCC_AHB5RSTR_OTG1PHYCTLRST_Msk (0x1UL << RCC_AHB5RSTR_OTG1PHYCTLRST_Pos) /*!< 0x00800000 */ #define RCC_AHB5RSTR_OTG1PHYCTLRST RCC_AHB5RSTR_OTG1PHYCTLRST_Msk /*!< OTG1PHYCTL reset */ #define RCC_AHB5RSTR_OTG2PHYCTLRST_Pos (24U) #define RCC_AHB5RSTR_OTG2PHYCTLRST_Msk (0x1UL << RCC_AHB5RSTR_OTG2PHYCTLRST_Pos) /*!< 0x01000000 */ #define RCC_AHB5RSTR_OTG2PHYCTLRST RCC_AHB5RSTR_OTG2PHYCTLRST_Msk /*!< OTG2PHYCTL reset */ #define RCC_AHB5RSTR_ETH1RST_Pos (25U) #define RCC_AHB5RSTR_ETH1RST_Msk (0x1UL << RCC_AHB5RSTR_ETH1RST_Pos) /*!< 0x02000000 */ #define RCC_AHB5RSTR_ETH1RST RCC_AHB5RSTR_ETH1RST_Msk /*!< ETH1 reset */ #define RCC_AHB5RSTR_OTG1RST_Pos (26U) #define RCC_AHB5RSTR_OTG1RST_Msk (0x1UL << RCC_AHB5RSTR_OTG1RST_Pos) /*!< 0x04000000 */ #define RCC_AHB5RSTR_OTG1RST RCC_AHB5RSTR_OTG1RST_Msk /*!< OTG1 reset */ #define RCC_AHB5RSTR_OTGPHY1RST_Pos (27U) #define RCC_AHB5RSTR_OTGPHY1RST_Msk (0x1UL << RCC_AHB5RSTR_OTGPHY1RST_Pos)/*!< 0x08000000 */ #define RCC_AHB5RSTR_OTGPHY1RST RCC_AHB5RSTR_OTGPHY1RST_Msk /*!< OTGPHY1 reset */ #define RCC_AHB5RSTR_OTGPHY2RST_Pos (28U) #define RCC_AHB5RSTR_OTGPHY2RST_Msk (0x1UL << RCC_AHB5RSTR_OTGPHY2RST_Pos)/*!< 0x10000000 */ #define RCC_AHB5RSTR_OTGPHY2RST RCC_AHB5RSTR_OTGPHY2RST_Msk /*!< OTGPHY2 reset */ #define RCC_AHB5RSTR_OTG2RST_Pos (29U) #define RCC_AHB5RSTR_OTG2RST_Msk (0x1UL << RCC_AHB5RSTR_OTG2RST_Pos) /*!< 0x20000000 */ #define RCC_AHB5RSTR_OTG2RST RCC_AHB5RSTR_OTG2RST_Msk /*!< OTG2 reset */ #define RCC_AHB5RSTR_CACHEAXIRST_Pos (30U) #define RCC_AHB5RSTR_CACHEAXIRST_Msk (0x1UL << RCC_AHB5RSTR_CACHEAXIRST_Pos) /*!< 0x40000000 */ #define RCC_AHB5RSTR_CACHEAXIRST RCC_AHB5RSTR_CACHEAXIRST_Msk /*!< CACHEAXI reset */ #define RCC_AHB5RSTR_NPURST_Pos (31U) #define RCC_AHB5RSTR_NPURST_Msk (0x1UL << RCC_AHB5RSTR_NPURST_Pos) /*!< 0x80000000 */ #define RCC_AHB5RSTR_NPURST RCC_AHB5RSTR_NPURST_Msk /*!< NPU reset */ /**************** Bit definition for RCC_APB1RSTR1 register *****************/ #define RCC_APB1RSTR1_TIM2RST_Pos (0U) #define RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */ #define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk /*!< TIM2 reset */ #define RCC_APB1RSTR1_TIM3RST_Pos (1U) #define RCC_APB1RSTR1_TIM3RST_Msk (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos) /*!< 0x00000002 */ #define RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk /*!< TIM3 reset */ #define RCC_APB1RSTR1_TIM4RST_Pos (2U) #define RCC_APB1RSTR1_TIM4RST_Msk (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos) /*!< 0x00000004 */ #define RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk /*!< TIM4 reset */ #define RCC_APB1RSTR1_TIM5RST_Pos (3U) #define RCC_APB1RSTR1_TIM5RST_Msk (0x1UL << RCC_APB1RSTR1_TIM5RST_Pos) /*!< 0x00000008 */ #define RCC_APB1RSTR1_TIM5RST RCC_APB1RSTR1_TIM5RST_Msk /*!< TIM5 reset */ #define RCC_APB1RSTR1_TIM6RST_Pos (4U) #define RCC_APB1RSTR1_TIM6RST_Msk (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos) /*!< 0x00000010 */ #define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk /*!< TIM6 reset */ #define RCC_APB1RSTR1_TIM7RST_Pos (5U) #define RCC_APB1RSTR1_TIM7RST_Msk (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos) /*!< 0x00000020 */ #define RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk /*!< TIM7 reset */ #define RCC_APB1RSTR1_TIM12RST_Pos (6U) #define RCC_APB1RSTR1_TIM12RST_Msk (0x1UL << RCC_APB1RSTR1_TIM12RST_Pos) /*!< 0x00000040 */ #define RCC_APB1RSTR1_TIM12RST RCC_APB1RSTR1_TIM12RST_Msk /*!< TIM12 reset */ #define RCC_APB1RSTR1_TIM13RST_Pos (7U) #define RCC_APB1RSTR1_TIM13RST_Msk (0x1UL << RCC_APB1RSTR1_TIM13RST_Pos) /*!< 0x00000080 */ #define RCC_APB1RSTR1_TIM13RST RCC_APB1RSTR1_TIM13RST_Msk /*!< TIM13 reset */ #define RCC_APB1RSTR1_TIM14RST_Pos (8U) #define RCC_APB1RSTR1_TIM14RST_Msk (0x1UL << RCC_APB1RSTR1_TIM14RST_Pos) /*!< 0x00000100 */ #define RCC_APB1RSTR1_TIM14RST RCC_APB1RSTR1_TIM14RST_Msk /*!< TIM14 reset */ #define RCC_APB1RSTR1_LPTIM1RST_Pos (9U) #define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)/*!< 0x00000200 */ #define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk /*!< LPTIM1 reset */ #define RCC_APB1RSTR1_WWDGRST_Pos (11U) #define RCC_APB1RSTR1_WWDGRST_Msk (0x1UL << RCC_APB1RSTR1_WWDGRST_Pos) /*!< 0x00000800 */ #define RCC_APB1RSTR1_WWDGRST RCC_APB1RSTR1_WWDGRST_Msk /*!< WWDG reset */ #define RCC_APB1RSTR1_TIM10RST_Pos (12U) #define RCC_APB1RSTR1_TIM10RST_Msk (0x1UL << RCC_APB1RSTR1_TIM10RST_Pos) /*!< 0x00001000 */ #define RCC_APB1RSTR1_TIM10RST RCC_APB1RSTR1_TIM10RST_Msk /*!< TIM10 reset */ #define RCC_APB1RSTR1_TIM11RST_Pos (13U) #define RCC_APB1RSTR1_TIM11RST_Msk (0x1UL << RCC_APB1RSTR1_TIM11RST_Pos) /*!< 0x00002000 */ #define RCC_APB1RSTR1_TIM11RST RCC_APB1RSTR1_TIM11RST_Msk /*!< TIM11 reset */ #define RCC_APB1RSTR1_SPI2RST_Pos (14U) #define RCC_APB1RSTR1_SPI2RST_Msk (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos) /*!< 0x00004000 */ #define RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk /*!< SPI2 reset */ #define RCC_APB1RSTR1_SPI3RST_Pos (15U) #define RCC_APB1RSTR1_SPI3RST_Msk (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos) /*!< 0x00008000 */ #define RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk /*!< SPI3 reset */ #define RCC_APB1RSTR1_SPDIFRX1RST_Pos (16U) #define RCC_APB1RSTR1_SPDIFRX1RST_Msk (0x1UL << RCC_APB1RSTR1_SPDIFRX1RST_Pos) /*!< 0x00010000 */ #define RCC_APB1RSTR1_SPDIFRX1RST RCC_APB1RSTR1_SPDIFRX1RST_Msk /*!< SPDIFRX1 reset */ #define RCC_APB1RSTR1_USART2RST_Pos (17U) #define RCC_APB1RSTR1_USART2RST_Msk (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)/*!< 0x00020000 */ #define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk /*!< USART2 reset */ #define RCC_APB1RSTR1_USART3RST_Pos (18U) #define RCC_APB1RSTR1_USART3RST_Msk (0x1UL << RCC_APB1RSTR1_USART3RST_Pos)/*!< 0x00040000 */ #define RCC_APB1RSTR1_USART3RST RCC_APB1RSTR1_USART3RST_Msk /*!< USART3 reset */ #define RCC_APB1RSTR1_UART4RST_Pos (19U) #define RCC_APB1RSTR1_UART4RST_Msk (0x1UL << RCC_APB1RSTR1_UART4RST_Pos) /*!< 0x00080000 */ #define RCC_APB1RSTR1_UART4RST RCC_APB1RSTR1_UART4RST_Msk /*!< UART4 reset */ #define RCC_APB1RSTR1_UART5RST_Pos (20U) #define RCC_APB1RSTR1_UART5RST_Msk (0x1UL << RCC_APB1RSTR1_UART5RST_Pos) /*!< 0x00100000 */ #define RCC_APB1RSTR1_UART5RST RCC_APB1RSTR1_UART5RST_Msk /*!< UART5 reset */ #define RCC_APB1RSTR1_I2C1RST_Pos (21U) #define RCC_APB1RSTR1_I2C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos) /*!< 0x00200000 */ #define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk /*!< I2C1 reset */ #define RCC_APB1RSTR1_I2C2RST_Pos (22U) #define RCC_APB1RSTR1_I2C2RST_Msk (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos) /*!< 0x00400000 */ #define RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk /*!< I2C2 reset */ #define RCC_APB1RSTR1_I2C3RST_Pos (23U) #define RCC_APB1RSTR1_I2C3RST_Msk (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos) /*!< 0x00800000 */ #define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk /*!< I2C3 reset */ #define RCC_APB1RSTR1_I3C1RST_Pos (24U) #define RCC_APB1RSTR1_I3C1RST_Msk (0x1UL << RCC_APB1RSTR1_I3C1RST_Pos) /*!< 0x01000000 */ #define RCC_APB1RSTR1_I3C1RST RCC_APB1RSTR1_I3C1RST_Msk /*!< I3C1 reset */ #define RCC_APB1RSTR1_I3C2RST_Pos (25U) #define RCC_APB1RSTR1_I3C2RST_Msk (0x1UL << RCC_APB1RSTR1_I3C2RST_Pos) /*!< 0x02000000 */ #define RCC_APB1RSTR1_I3C2RST RCC_APB1RSTR1_I3C2RST_Msk /*!< I3C2 reset */ #define RCC_APB1RSTR1_UART7RST_Pos (30U) #define RCC_APB1RSTR1_UART7RST_Msk (0x1UL << RCC_APB1RSTR1_UART7RST_Pos) /*!< 0x40000000 */ #define RCC_APB1RSTR1_UART7RST RCC_APB1RSTR1_UART7RST_Msk /*!< UART7 reset */ #define RCC_APB1RSTR1_UART8RST_Pos (31U) #define RCC_APB1RSTR1_UART8RST_Msk (0x1UL << RCC_APB1RSTR1_UART8RST_Pos) /*!< 0x80000000 */ #define RCC_APB1RSTR1_UART8RST RCC_APB1RSTR1_UART8RST_Msk /*!< UART8 reset */ /**************** Bit definition for RCC_APB1RSTR2 register *****************/ #define RCC_APB1RSTR2_MDIOSRST_Pos (5U) #define RCC_APB1RSTR2_MDIOSRST_Msk (0x1UL << RCC_APB1RSTR2_MDIOSRST_Pos) /*!< 0x00000020 */ #define RCC_APB1RSTR2_MDIOSRST RCC_APB1RSTR2_MDIOSRST_Msk /*!< MDIOS reset */ #define RCC_APB1RSTR2_FDCANRST_Pos (8U) #define RCC_APB1RSTR2_FDCANRST_Msk (0x1UL << RCC_APB1RSTR2_FDCANRST_Pos) /*!< 0x00000100 */ #define RCC_APB1RSTR2_FDCANRST RCC_APB1RSTR2_FDCANRST_Msk /*!< FDCAN reset */ #define RCC_APB1RSTR2_UCPD1RST_Pos (18U) #define RCC_APB1RSTR2_UCPD1RST_Msk (0x1UL << RCC_APB1RSTR2_UCPD1RST_Pos) /*!< 0x00040000 */ #define RCC_APB1RSTR2_UCPD1RST RCC_APB1RSTR2_UCPD1RST_Msk /*!< UCPD1 reset */ /***************** Bit definition for RCC_APB2RSTR register *****************/ #define RCC_APB2RSTR_TIM1RST_Pos (0U) #define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */ #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */ #define RCC_APB2RSTR_TIM8RST_Pos (1U) #define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */ #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk /*!< TIM8 reset */ #define RCC_APB2RSTR_USART1RST_Pos (4U) #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */ #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ #define RCC_APB2RSTR_USART6RST_Pos (5U) #define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */ #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk /*!< USART6 reset */ #define RCC_APB2RSTR_UART9RST_Pos (6U) #define RCC_APB2RSTR_UART9RST_Msk (0x1UL << RCC_APB2RSTR_UART9RST_Pos) /*!< 0x00000040 */ #define RCC_APB2RSTR_UART9RST RCC_APB2RSTR_UART9RST_Msk /*!< UART9 reset */ #define RCC_APB2RSTR_USART10RST_Pos (7U) #define RCC_APB2RSTR_USART10RST_Msk (0x1UL << RCC_APB2RSTR_USART10RST_Pos)/*!< 0x00000080 */ #define RCC_APB2RSTR_USART10RST RCC_APB2RSTR_USART10RST_Msk /*!< USART10 reset */ #define RCC_APB2RSTR_SPI1RST_Pos (12U) #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */ #define RCC_APB2RSTR_SPI4RST_Pos (13U) #define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */ #define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk /*!< SPI4 reset */ #define RCC_APB2RSTR_TIM18RST_Pos (15U) #define RCC_APB2RSTR_TIM18RST_Msk (0x1UL << RCC_APB2RSTR_TIM18RST_Pos) /*!< 0x00008000 */ #define RCC_APB2RSTR_TIM18RST RCC_APB2RSTR_TIM18RST_Msk /*!< TIM18 reset */ #define RCC_APB2RSTR_TIM15RST_Pos (16U) #define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ #define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 reset */ #define RCC_APB2RSTR_TIM16RST_Pos (17U) #define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */ #define RCC_APB2RSTR_TIM17RST_Pos (18U) #define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */ #define RCC_APB2RSTR_TIM9RST_Pos (19U) #define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00080000 */ #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk /*!< TIM9 reset */ #define RCC_APB2RSTR_SPI5RST_Pos (20U) #define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */ #define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk /*!< SPI5 reset */ #define RCC_APB2RSTR_SAI1RST_Pos (21U) #define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00200000 */ #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk /*!< SAI1 reset */ #define RCC_APB2RSTR_SAI2RST_Pos (22U) #define RCC_APB2RSTR_SAI2RST_Msk (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00400000 */ #define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk /*!< SAI2 reset */ /**************** Bit definition for RCC_APB4RSTR1 register *****************/ #define RCC_APB4RSTR1_HDPRST_Pos (2U) #define RCC_APB4RSTR1_HDPRST_Msk (0x1UL << RCC_APB4RSTR1_HDPRST_Pos) /*!< 0x00000004 */ #define RCC_APB4RSTR1_HDPRST RCC_APB4RSTR1_HDPRST_Msk /*!< HDP reset */ #define RCC_APB4RSTR1_LPUART1RST_Pos (3U) #define RCC_APB4RSTR1_LPUART1RST_Msk (0x1UL << RCC_APB4RSTR1_LPUART1RST_Pos) /*!< 0x00000008 */ #define RCC_APB4RSTR1_LPUART1RST RCC_APB4RSTR1_LPUART1RST_Msk /*!< LPUART1 reset */ #define RCC_APB4RSTR1_SPI6RST_Pos (5U) #define RCC_APB4RSTR1_SPI6RST_Msk (0x1UL << RCC_APB4RSTR1_SPI6RST_Pos) /*!< 0x00000020 */ #define RCC_APB4RSTR1_SPI6RST RCC_APB4RSTR1_SPI6RST_Msk /*!< SPI6 reset */ #define RCC_APB4RSTR1_I2C4RST_Pos (7U) #define RCC_APB4RSTR1_I2C4RST_Msk (0x1UL << RCC_APB4RSTR1_I2C4RST_Pos) /*!< 0x00000080 */ #define RCC_APB4RSTR1_I2C4RST RCC_APB4RSTR1_I2C4RST_Msk /*!< I2C4 reset */ #define RCC_APB4RSTR1_LPTIM2RST_Pos (9U) #define RCC_APB4RSTR1_LPTIM2RST_Msk (0x1UL << RCC_APB4RSTR1_LPTIM2RST_Pos)/*!< 0x00000200 */ #define RCC_APB4RSTR1_LPTIM2RST RCC_APB4RSTR1_LPTIM2RST_Msk /*!< LPTIM2 reset */ #define RCC_APB4RSTR1_LPTIM3RST_Pos (10U) #define RCC_APB4RSTR1_LPTIM3RST_Msk (0x1UL << RCC_APB4RSTR1_LPTIM3RST_Pos)/*!< 0x00000400 */ #define RCC_APB4RSTR1_LPTIM3RST RCC_APB4RSTR1_LPTIM3RST_Msk /*!< LPTIM3 reset */ #define RCC_APB4RSTR1_LPTIM4RST_Pos (11U) #define RCC_APB4RSTR1_LPTIM4RST_Msk (0x1UL << RCC_APB4RSTR1_LPTIM4RST_Pos)/*!< 0x00000800 */ #define RCC_APB4RSTR1_LPTIM4RST RCC_APB4RSTR1_LPTIM4RST_Msk /*!< LPTIM4 reset */ #define RCC_APB4RSTR1_LPTIM5RST_Pos (12U) #define RCC_APB4RSTR1_LPTIM5RST_Msk (0x1UL << RCC_APB4RSTR1_LPTIM5RST_Pos)/*!< 0x00001000 */ #define RCC_APB4RSTR1_LPTIM5RST RCC_APB4RSTR1_LPTIM5RST_Msk /*!< LPTIM5 reset */ #define RCC_APB4RSTR1_VREFBUFRST_Pos (15U) #define RCC_APB4RSTR1_VREFBUFRST_Msk (0x1UL << RCC_APB4RSTR1_VREFBUFRST_Pos) /*!< 0x00008000 */ #define RCC_APB4RSTR1_VREFBUFRST RCC_APB4RSTR1_VREFBUFRST_Msk /*!< VREFBUF reset */ #define RCC_APB4RSTR1_RTCRST_Pos (16U) #define RCC_APB4RSTR1_RTCRST_Msk (0x1UL << RCC_APB4RSTR1_RTCRST_Pos) /*!< 0x00010000 */ #define RCC_APB4RSTR1_RTCRST RCC_APB4RSTR1_RTCRST_Msk /*!< RTC reset */ /**************** Bit definition for RCC_APB4RSTR2 register *****************/ #define RCC_APB4RSTR2_SYSCFGRST_Pos (0U) #define RCC_APB4RSTR2_SYSCFGRST_Msk (0x1UL << RCC_APB4RSTR2_SYSCFGRST_Pos)/*!< 0x00000001 */ #define RCC_APB4RSTR2_SYSCFGRST RCC_APB4RSTR2_SYSCFGRST_Msk /*!< SYSCFG reset */ #define RCC_APB4RSTR2_DTSRST_Pos (2U) #define RCC_APB4RSTR2_DTSRST_Msk (0x1UL << RCC_APB4RSTR2_DTSRST_Pos) /*!< 0x00000004 */ #define RCC_APB4RSTR2_DTSRST RCC_APB4RSTR2_DTSRST_Msk /*!< DTS reset */ /***************** Bit definition for RCC_APB5RSTR register *****************/ #define RCC_APB5RSTR_LTDCRST_Pos (1U) #define RCC_APB5RSTR_LTDCRST_Msk (0x1UL << RCC_APB5RSTR_LTDCRST_Pos) /*!< 0x00000002 */ #define RCC_APB5RSTR_LTDCRST RCC_APB5RSTR_LTDCRST_Msk /*!< LTDC reset */ #define RCC_APB5RSTR_DCMIPPRST_Pos (2U) #define RCC_APB5RSTR_DCMIPPRST_Msk (0x1UL << RCC_APB5RSTR_DCMIPPRST_Pos) /*!< 0x00000004 */ #define RCC_APB5RSTR_DCMIPPRST RCC_APB5RSTR_DCMIPPRST_Msk /*!< DCMIPP reset */ #define RCC_APB5RSTR_GFXTIMRST_Pos (4U) #define RCC_APB5RSTR_GFXTIMRST_Msk (0x1UL << RCC_APB5RSTR_GFXTIMRST_Pos) /*!< 0x00000010 */ #define RCC_APB5RSTR_GFXTIMRST RCC_APB5RSTR_GFXTIMRST_Msk /*!< GFXTIM reset */ #define RCC_APB5RSTR_VENCRST_Pos (5U) #define RCC_APB5RSTR_VENCRST_Msk (0x1UL << RCC_APB5RSTR_VENCRST_Pos) /*!< 0x00000020 */ #define RCC_APB5RSTR_VENCRST RCC_APB5RSTR_VENCRST_Msk /*!< VENC reset */ #define RCC_APB5RSTR_CSIRST_Pos (6U) #define RCC_APB5RSTR_CSIRST_Msk (0x1UL << RCC_APB5RSTR_CSIRST_Pos) /*!< 0x00000040 */ #define RCC_APB5RSTR_CSIRST RCC_APB5RSTR_CSIRST_Msk /*!< CSI reset */ /****************** Bit definition for RCC_DIVENR register ******************/ #define RCC_DIVENR_IC1EN_Pos (0U) #define RCC_DIVENR_IC1EN_Msk (0x1UL << RCC_DIVENR_IC1EN_Pos) /*!< 0x00000001 */ #define RCC_DIVENR_IC1EN RCC_DIVENR_IC1EN_Msk /*!< IC1 enable */ #define RCC_DIVENR_IC2EN_Pos (1U) #define RCC_DIVENR_IC2EN_Msk (0x1UL << RCC_DIVENR_IC2EN_Pos) /*!< 0x00000002 */ #define RCC_DIVENR_IC2EN RCC_DIVENR_IC2EN_Msk /*!< IC2 enable */ #define RCC_DIVENR_IC3EN_Pos (2U) #define RCC_DIVENR_IC3EN_Msk (0x1UL << RCC_DIVENR_IC3EN_Pos) /*!< 0x00000004 */ #define RCC_DIVENR_IC3EN RCC_DIVENR_IC3EN_Msk /*!< IC3 enable */ #define RCC_DIVENR_IC4EN_Pos (3U) #define RCC_DIVENR_IC4EN_Msk (0x1UL << RCC_DIVENR_IC4EN_Pos) /*!< 0x00000008 */ #define RCC_DIVENR_IC4EN RCC_DIVENR_IC4EN_Msk /*!< IC4 enable */ #define RCC_DIVENR_IC5EN_Pos (4U) #define RCC_DIVENR_IC5EN_Msk (0x1UL << RCC_DIVENR_IC5EN_Pos) /*!< 0x00000010 */ #define RCC_DIVENR_IC5EN RCC_DIVENR_IC5EN_Msk /*!< IC5 enable */ #define RCC_DIVENR_IC6EN_Pos (5U) #define RCC_DIVENR_IC6EN_Msk (0x1UL << RCC_DIVENR_IC6EN_Pos) /*!< 0x00000020 */ #define RCC_DIVENR_IC6EN RCC_DIVENR_IC6EN_Msk /*!< IC6 enable */ #define RCC_DIVENR_IC7EN_Pos (6U) #define RCC_DIVENR_IC7EN_Msk (0x1UL << RCC_DIVENR_IC7EN_Pos) /*!< 0x00000040 */ #define RCC_DIVENR_IC7EN RCC_DIVENR_IC7EN_Msk /*!< IC7 enable */ #define RCC_DIVENR_IC8EN_Pos (7U) #define RCC_DIVENR_IC8EN_Msk (0x1UL << RCC_DIVENR_IC8EN_Pos) /*!< 0x00000080 */ #define RCC_DIVENR_IC8EN RCC_DIVENR_IC8EN_Msk /*!< IC8 enable */ #define RCC_DIVENR_IC9EN_Pos (8U) #define RCC_DIVENR_IC9EN_Msk (0x1UL << RCC_DIVENR_IC9EN_Pos) /*!< 0x00000100 */ #define RCC_DIVENR_IC9EN RCC_DIVENR_IC9EN_Msk /*!< IC9 enable */ #define RCC_DIVENR_IC10EN_Pos (9U) #define RCC_DIVENR_IC10EN_Msk (0x1UL << RCC_DIVENR_IC10EN_Pos) /*!< 0x00000200 */ #define RCC_DIVENR_IC10EN RCC_DIVENR_IC10EN_Msk /*!< IC10 enable */ #define RCC_DIVENR_IC11EN_Pos (10U) #define RCC_DIVENR_IC11EN_Msk (0x1UL << RCC_DIVENR_IC11EN_Pos) /*!< 0x00000400 */ #define RCC_DIVENR_IC11EN RCC_DIVENR_IC11EN_Msk /*!< IC11 enable */ #define RCC_DIVENR_IC12EN_Pos (11U) #define RCC_DIVENR_IC12EN_Msk (0x1UL << RCC_DIVENR_IC12EN_Pos) /*!< 0x00000800 */ #define RCC_DIVENR_IC12EN RCC_DIVENR_IC12EN_Msk /*!< IC12 enable */ #define RCC_DIVENR_IC13EN_Pos (12U) #define RCC_DIVENR_IC13EN_Msk (0x1UL << RCC_DIVENR_IC13EN_Pos) /*!< 0x00001000 */ #define RCC_DIVENR_IC13EN RCC_DIVENR_IC13EN_Msk /*!< IC13 enable */ #define RCC_DIVENR_IC14EN_Pos (13U) #define RCC_DIVENR_IC14EN_Msk (0x1UL << RCC_DIVENR_IC14EN_Pos) /*!< 0x00002000 */ #define RCC_DIVENR_IC14EN RCC_DIVENR_IC14EN_Msk /*!< IC14 enable */ #define RCC_DIVENR_IC15EN_Pos (14U) #define RCC_DIVENR_IC15EN_Msk (0x1UL << RCC_DIVENR_IC15EN_Pos) /*!< 0x00004000 */ #define RCC_DIVENR_IC15EN RCC_DIVENR_IC15EN_Msk /*!< IC15 enable */ #define RCC_DIVENR_IC16EN_Pos (15U) #define RCC_DIVENR_IC16EN_Msk (0x1UL << RCC_DIVENR_IC16EN_Pos) /*!< 0x00008000 */ #define RCC_DIVENR_IC16EN RCC_DIVENR_IC16EN_Msk /*!< IC16 enable */ #define RCC_DIVENR_IC17EN_Pos (16U) #define RCC_DIVENR_IC17EN_Msk (0x1UL << RCC_DIVENR_IC17EN_Pos) /*!< 0x00010000 */ #define RCC_DIVENR_IC17EN RCC_DIVENR_IC17EN_Msk /*!< IC17 enable */ #define RCC_DIVENR_IC18EN_Pos (17U) #define RCC_DIVENR_IC18EN_Msk (0x1UL << RCC_DIVENR_IC18EN_Pos) /*!< 0x00020000 */ #define RCC_DIVENR_IC18EN RCC_DIVENR_IC18EN_Msk /*!< IC18 enable */ #define RCC_DIVENR_IC19EN_Pos (18U) #define RCC_DIVENR_IC19EN_Msk (0x1UL << RCC_DIVENR_IC19EN_Pos) /*!< 0x00040000 */ #define RCC_DIVENR_IC19EN RCC_DIVENR_IC19EN_Msk /*!< IC19 enable */ #define RCC_DIVENR_IC20EN_Pos (19U) #define RCC_DIVENR_IC20EN_Msk (0x1UL << RCC_DIVENR_IC20EN_Pos) /*!< 0x00080000 */ #define RCC_DIVENR_IC20EN RCC_DIVENR_IC20EN_Msk /*!< IC20 enable */ /****************** Bit definition for RCC_BUSENR register ******************/ #define RCC_BUSENR_ACLKNEN_Pos (0U) #define RCC_BUSENR_ACLKNEN_Msk (0x1UL << RCC_BUSENR_ACLKNEN_Pos) /*!< 0x00000001 */ #define RCC_BUSENR_ACLKNEN RCC_BUSENR_ACLKNEN_Msk /*!< ACLKN enable */ #define RCC_BUSENR_ACLKNCEN_Pos (1U) #define RCC_BUSENR_ACLKNCEN_Msk (0x1UL << RCC_BUSENR_ACLKNCEN_Pos) /*!< 0x00000002 */ #define RCC_BUSENR_ACLKNCEN RCC_BUSENR_ACLKNCEN_Msk /*!< ACLKNC enable */ #define RCC_BUSENR_AHBMEN_Pos (2U) #define RCC_BUSENR_AHBMEN_Msk (0x1UL << RCC_BUSENR_AHBMEN_Pos) /*!< 0x00000004 */ #define RCC_BUSENR_AHBMEN RCC_BUSENR_AHBMEN_Msk /*!< AHBM enable */ #define RCC_BUSENR_AHB1EN_Pos (3U) #define RCC_BUSENR_AHB1EN_Msk (0x1UL << RCC_BUSENR_AHB1EN_Pos) /*!< 0x00000008 */ #define RCC_BUSENR_AHB1EN RCC_BUSENR_AHB1EN_Msk /*!< AHB1 enable */ #define RCC_BUSENR_AHB2EN_Pos (4U) #define RCC_BUSENR_AHB2EN_Msk (0x1UL << RCC_BUSENR_AHB2EN_Pos) /*!< 0x00000010 */ #define RCC_BUSENR_AHB2EN RCC_BUSENR_AHB2EN_Msk /*!< AHB2 enable */ #define RCC_BUSENR_AHB3EN_Pos (5U) #define RCC_BUSENR_AHB3EN_Msk (0x1UL << RCC_BUSENR_AHB3EN_Pos) /*!< 0x00000020 */ #define RCC_BUSENR_AHB3EN RCC_BUSENR_AHB3EN_Msk /*!< AHB3 enable */ #define RCC_BUSENR_AHB4EN_Pos (6U) #define RCC_BUSENR_AHB4EN_Msk (0x1UL << RCC_BUSENR_AHB4EN_Pos) /*!< 0x00000040 */ #define RCC_BUSENR_AHB4EN RCC_BUSENR_AHB4EN_Msk /*!< AHB4 enable */ #define RCC_BUSENR_AHB5EN_Pos (7U) #define RCC_BUSENR_AHB5EN_Msk (0x1UL << RCC_BUSENR_AHB5EN_Pos) /*!< 0x00000080 */ #define RCC_BUSENR_AHB5EN RCC_BUSENR_AHB5EN_Msk /*!< AHB5 enable */ #define RCC_BUSENR_APB1EN_Pos (8U) #define RCC_BUSENR_APB1EN_Msk (0x1UL << RCC_BUSENR_APB1EN_Pos) /*!< 0x00000100 */ #define RCC_BUSENR_APB1EN RCC_BUSENR_APB1EN_Msk /*!< APB1 enable */ #define RCC_BUSENR_APB2EN_Pos (9U) #define RCC_BUSENR_APB2EN_Msk (0x1UL << RCC_BUSENR_APB2EN_Pos) /*!< 0x00000200 */ #define RCC_BUSENR_APB2EN RCC_BUSENR_APB2EN_Msk /*!< APB2 enable */ #define RCC_BUSENR_APB3EN_Pos (10U) #define RCC_BUSENR_APB3EN_Msk (0x1UL << RCC_BUSENR_APB3EN_Pos) /*!< 0x00000400 */ #define RCC_BUSENR_APB3EN RCC_BUSENR_APB3EN_Msk /*!< APB3 enable */ #define RCC_BUSENR_APB4EN_Pos (11U) #define RCC_BUSENR_APB4EN_Msk (0x1UL << RCC_BUSENR_APB4EN_Pos) /*!< 0x00000800 */ #define RCC_BUSENR_APB4EN RCC_BUSENR_APB4EN_Msk /*!< APB4 enable */ #define RCC_BUSENR_APB5EN_Pos (12U) #define RCC_BUSENR_APB5EN_Msk (0x1UL << RCC_BUSENR_APB5EN_Pos) /*!< 0x00001000 */ #define RCC_BUSENR_APB5EN RCC_BUSENR_APB5EN_Msk /*!< APB5 enable */ /***************** Bit definition for RCC_MISCENR register ******************/ #define RCC_MISCENR_DBGEN_Pos (0U) #define RCC_MISCENR_DBGEN_Msk (0x1UL << RCC_MISCENR_DBGEN_Pos) /*!< 0x00000001 */ #define RCC_MISCENR_DBGEN RCC_MISCENR_DBGEN_Msk /*!< DBG enable */ #define RCC_MISCENR_MCO1EN_Pos (1U) #define RCC_MISCENR_MCO1EN_Msk (0x1UL << RCC_MISCENR_MCO1EN_Pos) /*!< 0x00000002 */ #define RCC_MISCENR_MCO1EN RCC_MISCENR_MCO1EN_Msk /*!< MCO1 enable */ #define RCC_MISCENR_MCO2EN_Pos (2U) #define RCC_MISCENR_MCO2EN_Msk (0x1UL << RCC_MISCENR_MCO2EN_Pos) /*!< 0x00000004 */ #define RCC_MISCENR_MCO2EN RCC_MISCENR_MCO2EN_Msk /*!< MCO2 enable */ #define RCC_MISCENR_XSPIPHYCOMPEN_Pos (3U) #define RCC_MISCENR_XSPIPHYCOMPEN_Msk (0x1UL << RCC_MISCENR_XSPIPHYCOMPEN_Pos) /*!< 0x00000008 */ #define RCC_MISCENR_XSPIPHYCOMPEN RCC_MISCENR_XSPIPHYCOMPEN_Msk /*!< XSPIPHYCOMP enable */ #define RCC_MISCENR_PEREN_Pos (6U) #define RCC_MISCENR_PEREN_Msk (0x1UL << RCC_MISCENR_PEREN_Pos) /*!< 0x00000040 */ #define RCC_MISCENR_PEREN RCC_MISCENR_PEREN_Msk /*!< PER enable */ /****************** Bit definition for RCC_MEMENR register ******************/ #define RCC_MEMENR_AXISRAM3EN_Pos (0U) #define RCC_MEMENR_AXISRAM3EN_Msk (0x1UL << RCC_MEMENR_AXISRAM3EN_Pos) /*!< 0x00000001 */ #define RCC_MEMENR_AXISRAM3EN RCC_MEMENR_AXISRAM3EN_Msk /*!< AXISRAM3 enable */ #define RCC_MEMENR_AXISRAM4EN_Pos (1U) #define RCC_MEMENR_AXISRAM4EN_Msk (0x1UL << RCC_MEMENR_AXISRAM4EN_Pos) /*!< 0x00000002 */ #define RCC_MEMENR_AXISRAM4EN RCC_MEMENR_AXISRAM4EN_Msk /*!< AXISRAM4 enable */ #define RCC_MEMENR_AXISRAM5EN_Pos (2U) #define RCC_MEMENR_AXISRAM5EN_Msk (0x1UL << RCC_MEMENR_AXISRAM5EN_Pos) /*!< 0x00000004 */ #define RCC_MEMENR_AXISRAM5EN RCC_MEMENR_AXISRAM5EN_Msk /*!< AXISRAM5 enable */ #define RCC_MEMENR_AXISRAM6EN_Pos (3U) #define RCC_MEMENR_AXISRAM6EN_Msk (0x1UL << RCC_MEMENR_AXISRAM6EN_Pos) /*!< 0x00000008 */ #define RCC_MEMENR_AXISRAM6EN RCC_MEMENR_AXISRAM6EN_Msk /*!< AXISRAM6 enable */ #define RCC_MEMENR_AHBSRAM1EN_Pos (4U) #define RCC_MEMENR_AHBSRAM1EN_Msk (0x1UL << RCC_MEMENR_AHBSRAM1EN_Pos) /*!< 0x00000010 */ #define RCC_MEMENR_AHBSRAM1EN RCC_MEMENR_AHBSRAM1EN_Msk /*!< AHBSRAM1 enable */ #define RCC_MEMENR_AHBSRAM2EN_Pos (5U) #define RCC_MEMENR_AHBSRAM2EN_Msk (0x1UL << RCC_MEMENR_AHBSRAM2EN_Pos) /*!< 0x00000020 */ #define RCC_MEMENR_AHBSRAM2EN RCC_MEMENR_AHBSRAM2EN_Msk /*!< AHBSRAM2 enable */ #define RCC_MEMENR_BKPSRAMEN_Pos (6U) #define RCC_MEMENR_BKPSRAMEN_Msk (0x1UL << RCC_MEMENR_BKPSRAMEN_Pos) /*!< 0x00000040 */ #define RCC_MEMENR_BKPSRAMEN RCC_MEMENR_BKPSRAMEN_Msk /*!< BKPSRAM enable */ #define RCC_MEMENR_AXISRAM1EN_Pos (7U) #define RCC_MEMENR_AXISRAM1EN_Msk (0x1UL << RCC_MEMENR_AXISRAM1EN_Pos) /*!< 0x00000080 */ #define RCC_MEMENR_AXISRAM1EN RCC_MEMENR_AXISRAM1EN_Msk /*!< AXISRAM1 enable */ #define RCC_MEMENR_AXISRAM2EN_Pos (8U) #define RCC_MEMENR_AXISRAM2EN_Msk (0x1UL << RCC_MEMENR_AXISRAM2EN_Pos) /*!< 0x00000100 */ #define RCC_MEMENR_AXISRAM2EN RCC_MEMENR_AXISRAM2EN_Msk /*!< AXISRAM2 enable */ #define RCC_MEMENR_FLEXRAMEN_Pos (9U) #define RCC_MEMENR_FLEXRAMEN_Msk (0x1UL << RCC_MEMENR_FLEXRAMEN_Pos) /*!< 0x00000200 */ #define RCC_MEMENR_FLEXRAMEN RCC_MEMENR_FLEXRAMEN_Msk /*!< FLEXRAM enable */ #define RCC_MEMENR_CACHEAXIRAMEN_Pos (10U) #define RCC_MEMENR_CACHEAXIRAMEN_Msk (0x1UL << RCC_MEMENR_CACHEAXIRAMEN_Pos) /*!< 0x00000400 */ #define RCC_MEMENR_CACHEAXIRAMEN RCC_MEMENR_CACHEAXIRAMEN_Msk /*!< CACHEAXIRAM enable */ #define RCC_MEMENR_VENCRAMEN_Pos (11U) #define RCC_MEMENR_VENCRAMEN_Msk (0x1UL << RCC_MEMENR_VENCRAMEN_Pos) /*!< 0x00000800 */ #define RCC_MEMENR_VENCRAMEN RCC_MEMENR_VENCRAMEN_Msk /*!< VENCRAM enable */ #define RCC_MEMENR_BOOTROMEN_Pos (12U) #define RCC_MEMENR_BOOTROMEN_Msk (0x1UL << RCC_MEMENR_BOOTROMEN_Pos) /*!< 0x00001000 */ #define RCC_MEMENR_BOOTROMEN RCC_MEMENR_BOOTROMEN_Msk /*!< Boot ROM enable */ /***************** Bit definition for RCC_AHB1ENR register ******************/ #define RCC_AHB1ENR_GPDMA1EN_Pos (4U) #define RCC_AHB1ENR_GPDMA1EN_Msk (0x1UL << RCC_AHB1ENR_GPDMA1EN_Pos) /*!< 0x00000010 */ #define RCC_AHB1ENR_GPDMA1EN RCC_AHB1ENR_GPDMA1EN_Msk /*!< GPDMA1 enable */ #define RCC_AHB1ENR_ADC12EN_Pos (5U) #define RCC_AHB1ENR_ADC12EN_Msk (0x1UL << RCC_AHB1ENR_ADC12EN_Pos) /*!< 0x00000020 */ #define RCC_AHB1ENR_ADC12EN RCC_AHB1ENR_ADC12EN_Msk /*!< ADC12 enable */ /***************** Bit definition for RCC_AHB2ENR register ******************/ #define RCC_AHB2ENR_RAMCFGEN_Pos (12U) #define RCC_AHB2ENR_RAMCFGEN_Msk (0x1UL << RCC_AHB2ENR_RAMCFGEN_Pos) /*!< 0x00001000 */ #define RCC_AHB2ENR_RAMCFGEN RCC_AHB2ENR_RAMCFGEN_Msk /*!< RAMCFG enable */ #define RCC_AHB2ENR_MDF1EN_Pos (16U) #define RCC_AHB2ENR_MDF1EN_Msk (0x1UL << RCC_AHB2ENR_MDF1EN_Pos) /*!< 0x00010000 */ #define RCC_AHB2ENR_MDF1EN RCC_AHB2ENR_MDF1EN_Msk /*!< MDF1 enable */ #define RCC_AHB2ENR_ADF1EN_Pos (17U) #define RCC_AHB2ENR_ADF1EN_Msk (0x1UL << RCC_AHB2ENR_ADF1EN_Pos) /*!< 0x00020000 */ #define RCC_AHB2ENR_ADF1EN RCC_AHB2ENR_ADF1EN_Msk /*!< ADF1 enable */ /***************** Bit definition for RCC_AHB3ENR register ******************/ #define RCC_AHB3ENR_RNGEN_Pos (0U) #define RCC_AHB3ENR_RNGEN_Msk (0x1UL << RCC_AHB3ENR_RNGEN_Pos) /*!< 0x00000001 */ #define RCC_AHB3ENR_RNGEN RCC_AHB3ENR_RNGEN_Msk /*!< RNG enable */ #define RCC_AHB3ENR_HASHEN_Pos (1U) #define RCC_AHB3ENR_HASHEN_Msk (0x1UL << RCC_AHB3ENR_HASHEN_Pos) /*!< 0x00000002 */ #define RCC_AHB3ENR_HASHEN RCC_AHB3ENR_HASHEN_Msk /*!< HASH enable */ #define RCC_AHB3ENR_CRYPEN_Pos (2U) #define RCC_AHB3ENR_CRYPEN_Msk (0x1UL << RCC_AHB3ENR_CRYPEN_Pos) /*!< 0x00000004 */ #define RCC_AHB3ENR_CRYPEN RCC_AHB3ENR_CRYPEN_Msk /*!< CRYP enable */ #define RCC_AHB3ENR_SAESEN_Pos (4U) #define RCC_AHB3ENR_SAESEN_Msk (0x1UL << RCC_AHB3ENR_SAESEN_Pos) /*!< 0x00000010 */ #define RCC_AHB3ENR_SAESEN RCC_AHB3ENR_SAESEN_Msk /*!< SAES enable */ #define RCC_AHB3ENR_PKAEN_Pos (8U) #define RCC_AHB3ENR_PKAEN_Msk (0x1UL << RCC_AHB3ENR_PKAEN_Pos) /*!< 0x00000100 */ #define RCC_AHB3ENR_PKAEN RCC_AHB3ENR_PKAEN_Msk /*!< PKA enable */ #define RCC_AHB3ENR_RIFSCEN_Pos (9U) #define RCC_AHB3ENR_RIFSCEN_Msk (0x1UL << RCC_AHB3ENR_RIFSCEN_Pos) /*!< 0x00000200 */ #define RCC_AHB3ENR_RIFSCEN RCC_AHB3ENR_RIFSCEN_Msk /*!< RIFSC enable */ #define RCC_AHB3ENR_IACEN_Pos (10U) #define RCC_AHB3ENR_IACEN_Msk (0x1UL << RCC_AHB3ENR_IACEN_Pos) /*!< 0x00000400 */ #define RCC_AHB3ENR_IACEN RCC_AHB3ENR_IACEN_Msk /*!< IAC enable */ #define RCC_AHB3ENR_RISAFEN_Pos (14U) #define RCC_AHB3ENR_RISAFEN_Msk (0x1UL << RCC_AHB3ENR_RISAFEN_Pos) /*!< 0x00004000 */ #define RCC_AHB3ENR_RISAFEN RCC_AHB3ENR_RISAFEN_Msk /*!< RISAF enable */ /***************** Bit definition for RCC_AHB4ENR register ******************/ #define RCC_AHB4ENR_GPIOAEN_Pos (0U) #define RCC_AHB4ENR_GPIOAEN_Msk (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos) /*!< 0x00000001 */ #define RCC_AHB4ENR_GPIOAEN RCC_AHB4ENR_GPIOAEN_Msk /*!< GPIO A enable */ #define RCC_AHB4ENR_GPIOBEN_Pos (1U) #define RCC_AHB4ENR_GPIOBEN_Msk (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos) /*!< 0x00000002 */ #define RCC_AHB4ENR_GPIOBEN RCC_AHB4ENR_GPIOBEN_Msk /*!< GPIO B enable */ #define RCC_AHB4ENR_GPIOCEN_Pos (2U) #define RCC_AHB4ENR_GPIOCEN_Msk (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos) /*!< 0x00000004 */ #define RCC_AHB4ENR_GPIOCEN RCC_AHB4ENR_GPIOCEN_Msk /*!< GPIO C enable */ #define RCC_AHB4ENR_GPIODEN_Pos (3U) #define RCC_AHB4ENR_GPIODEN_Msk (0x1UL << RCC_AHB4ENR_GPIODEN_Pos) /*!< 0x00000008 */ #define RCC_AHB4ENR_GPIODEN RCC_AHB4ENR_GPIODEN_Msk /*!< GPIO D enable */ #define RCC_AHB4ENR_GPIOEEN_Pos (4U) #define RCC_AHB4ENR_GPIOEEN_Msk (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos) /*!< 0x00000010 */ #define RCC_AHB4ENR_GPIOEEN RCC_AHB4ENR_GPIOEEN_Msk /*!< GPIO E enable */ #define RCC_AHB4ENR_GPIOFEN_Pos (5U) #define RCC_AHB4ENR_GPIOFEN_Msk (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos) /*!< 0x00000020 */ #define RCC_AHB4ENR_GPIOFEN RCC_AHB4ENR_GPIOFEN_Msk /*!< GPIO F enable */ #define RCC_AHB4ENR_GPIOGEN_Pos (6U) #define RCC_AHB4ENR_GPIOGEN_Msk (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos) /*!< 0x00000040 */ #define RCC_AHB4ENR_GPIOGEN RCC_AHB4ENR_GPIOGEN_Msk /*!< GPIO G enable */ #define RCC_AHB4ENR_GPIOHEN_Pos (7U) #define RCC_AHB4ENR_GPIOHEN_Msk (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos) /*!< 0x00000080 */ #define RCC_AHB4ENR_GPIOHEN RCC_AHB4ENR_GPIOHEN_Msk /*!< GPIO H enable */ #define RCC_AHB4ENR_GPIONEN_Pos (13U) #define RCC_AHB4ENR_GPIONEN_Msk (0x1UL << RCC_AHB4ENR_GPIONEN_Pos) /*!< 0x00002000 */ #define RCC_AHB4ENR_GPIONEN RCC_AHB4ENR_GPIONEN_Msk /*!< GPIO N enable */ #define RCC_AHB4ENR_GPIOOEN_Pos (14U) #define RCC_AHB4ENR_GPIOOEN_Msk (0x1UL << RCC_AHB4ENR_GPIOOEN_Pos) /*!< 0x00004000 */ #define RCC_AHB4ENR_GPIOOEN RCC_AHB4ENR_GPIOOEN_Msk /*!< GPIO O enable */ #define RCC_AHB4ENR_GPIOPEN_Pos (15U) #define RCC_AHB4ENR_GPIOPEN_Msk (0x1UL << RCC_AHB4ENR_GPIOPEN_Pos) /*!< 0x00008000 */ #define RCC_AHB4ENR_GPIOPEN RCC_AHB4ENR_GPIOPEN_Msk /*!< GPIO P enable */ #define RCC_AHB4ENR_GPIOQEN_Pos (16U) #define RCC_AHB4ENR_GPIOQEN_Msk (0x1UL << RCC_AHB4ENR_GPIOQEN_Pos) /*!< 0x00010000 */ #define RCC_AHB4ENR_GPIOQEN RCC_AHB4ENR_GPIOQEN_Msk /*!< GPIO Q enable */ #define RCC_AHB4ENR_PWREN_Pos (18U) #define RCC_AHB4ENR_PWREN_Msk (0x1UL << RCC_AHB4ENR_PWREN_Pos) /*!< 0x00040000 */ #define RCC_AHB4ENR_PWREN RCC_AHB4ENR_PWREN_Msk /*!< PWR enable */ #define RCC_AHB4ENR_CRCEN_Pos (19U) #define RCC_AHB4ENR_CRCEN_Msk (0x1UL << RCC_AHB4ENR_CRCEN_Pos) /*!< 0x00080000 */ #define RCC_AHB4ENR_CRCEN RCC_AHB4ENR_CRCEN_Msk /*!< CRC enable */ /***************** Bit definition for RCC_AHB5ENR register ******************/ #define RCC_AHB5ENR_HPDMA1EN_Pos (0U) #define RCC_AHB5ENR_HPDMA1EN_Msk (0x1UL << RCC_AHB5ENR_HPDMA1EN_Pos) /*!< 0x00000001 */ #define RCC_AHB5ENR_HPDMA1EN RCC_AHB5ENR_HPDMA1EN_Msk /*!< HPDMA1 enable */ #define RCC_AHB5ENR_DMA2DEN_Pos (1U) #define RCC_AHB5ENR_DMA2DEN_Msk (0x1UL << RCC_AHB5ENR_DMA2DEN_Pos) /*!< 0x00000002 */ #define RCC_AHB5ENR_DMA2DEN RCC_AHB5ENR_DMA2DEN_Msk /*!< DMA2D enable */ #define RCC_AHB5ENR_JPEGEN_Pos (3U) #define RCC_AHB5ENR_JPEGEN_Msk (0x1UL << RCC_AHB5ENR_JPEGEN_Pos) /*!< 0x00000008 */ #define RCC_AHB5ENR_JPEGEN RCC_AHB5ENR_JPEGEN_Msk /*!< JPEG enable */ #define RCC_AHB5ENR_FMCEN_Pos (4U) #define RCC_AHB5ENR_FMCEN_Msk (0x1UL << RCC_AHB5ENR_FMCEN_Pos) /*!< 0x00000010 */ #define RCC_AHB5ENR_FMCEN RCC_AHB5ENR_FMCEN_Msk /*!< FMC enable */ #define RCC_AHB5ENR_XSPI1EN_Pos (5U) #define RCC_AHB5ENR_XSPI1EN_Msk (0x1UL << RCC_AHB5ENR_XSPI1EN_Pos) /*!< 0x00000020 */ #define RCC_AHB5ENR_XSPI1EN RCC_AHB5ENR_XSPI1EN_Msk /*!< XSPI1 enable */ #define RCC_AHB5ENR_PSSIEN_Pos (6U) #define RCC_AHB5ENR_PSSIEN_Msk (0x1UL << RCC_AHB5ENR_PSSIEN_Pos) /*!< 0x00000040 */ #define RCC_AHB5ENR_PSSIEN RCC_AHB5ENR_PSSIEN_Msk /*!< PSSI enable */ #define RCC_AHB5ENR_SDMMC2EN_Pos (7U) #define RCC_AHB5ENR_SDMMC2EN_Msk (0x1UL << RCC_AHB5ENR_SDMMC2EN_Pos) /*!< 0x00000080 */ #define RCC_AHB5ENR_SDMMC2EN RCC_AHB5ENR_SDMMC2EN_Msk /*!< SDMMC2 enable */ #define RCC_AHB5ENR_SDMMC1EN_Pos (8U) #define RCC_AHB5ENR_SDMMC1EN_Msk (0x1UL << RCC_AHB5ENR_SDMMC1EN_Pos) /*!< 0x00000100 */ #define RCC_AHB5ENR_SDMMC1EN RCC_AHB5ENR_SDMMC1EN_Msk /*!< SDMMC1 enable */ #define RCC_AHB5ENR_XSPI2EN_Pos (12U) #define RCC_AHB5ENR_XSPI2EN_Msk (0x1UL << RCC_AHB5ENR_XSPI2EN_Pos) /*!< 0x00001000 */ #define RCC_AHB5ENR_XSPI2EN RCC_AHB5ENR_XSPI2EN_Msk /*!< XSPI2 enable */ #define RCC_AHB5ENR_XSPIMEN_Pos (13U) #define RCC_AHB5ENR_XSPIMEN_Msk (0x1UL << RCC_AHB5ENR_XSPIMEN_Pos) /*!< 0x00002000 */ #define RCC_AHB5ENR_XSPIMEN RCC_AHB5ENR_XSPIMEN_Msk /*!< XSPIM enable */ #define RCC_AHB5ENR_MCE1EN_Pos (14U) #define RCC_AHB5ENR_MCE1EN_Msk (0x1UL << RCC_AHB5ENR_MCE1EN_Pos) /*!< 0x00004000 */ #define RCC_AHB5ENR_MCE1EN RCC_AHB5ENR_MCE1EN_Msk /*!< MCE1 enable */ #define RCC_AHB5ENR_MCE2EN_Pos (15U) #define RCC_AHB5ENR_MCE2EN_Msk (0x1UL << RCC_AHB5ENR_MCE2EN_Pos) /*!< 0x00008000 */ #define RCC_AHB5ENR_MCE2EN RCC_AHB5ENR_MCE2EN_Msk /*!< MCE2 enable */ #define RCC_AHB5ENR_MCE3EN_Pos (16U) #define RCC_AHB5ENR_MCE3EN_Msk (0x1UL << RCC_AHB5ENR_MCE3EN_Pos) /*!< 0x00010000 */ #define RCC_AHB5ENR_MCE3EN RCC_AHB5ENR_MCE3EN_Msk /*!< MCE3 enable */ #define RCC_AHB5ENR_XSPI3EN_Pos (17U) #define RCC_AHB5ENR_XSPI3EN_Msk (0x1UL << RCC_AHB5ENR_XSPI3EN_Pos) /*!< 0x00020000 */ #define RCC_AHB5ENR_XSPI3EN RCC_AHB5ENR_XSPI3EN_Msk /*!< XSPI3 enable */ #define RCC_AHB5ENR_MCE4EN_Pos (18U) #define RCC_AHB5ENR_MCE4EN_Msk (0x1UL << RCC_AHB5ENR_MCE4EN_Pos) /*!< 0x00040000 */ #define RCC_AHB5ENR_MCE4EN RCC_AHB5ENR_MCE4EN_Msk /*!< MCE4 enable */ #define RCC_AHB5ENR_GFXMMUEN_Pos (19U) #define RCC_AHB5ENR_GFXMMUEN_Msk (0x1UL << RCC_AHB5ENR_GFXMMUEN_Pos) /*!< 0x00080000 */ #define RCC_AHB5ENR_GFXMMUEN RCC_AHB5ENR_GFXMMUEN_Msk /*!< GFXMMU enable */ #define RCC_AHB5ENR_GPU2DEN_Pos (20U) #define RCC_AHB5ENR_GPU2DEN_Msk (0x1UL << RCC_AHB5ENR_GPU2DEN_Pos) /*!< 0x00100000 */ #define RCC_AHB5ENR_GPU2DEN RCC_AHB5ENR_GPU2DEN_Msk /*!< GPU2D enable */ #define RCC_AHB5ENR_ETH1MACEN_Pos (22U) #define RCC_AHB5ENR_ETH1MACEN_Msk (0x1UL << RCC_AHB5ENR_ETH1MACEN_Pos) /*!< 0x00400000 */ #define RCC_AHB5ENR_ETH1MACEN RCC_AHB5ENR_ETH1MACEN_Msk /*!< ETH1MAC enable */ #define RCC_AHB5ENR_ETH1TXEN_Pos (23U) #define RCC_AHB5ENR_ETH1TXEN_Msk (0x1UL << RCC_AHB5ENR_ETH1TXEN_Pos) /*!< 0x00800000 */ #define RCC_AHB5ENR_ETH1TXEN RCC_AHB5ENR_ETH1TXEN_Msk /*!< ETH1TX enable */ #define RCC_AHB5ENR_ETH1RXEN_Pos (24U) #define RCC_AHB5ENR_ETH1RXEN_Msk (0x1UL << RCC_AHB5ENR_ETH1RXEN_Pos) /*!< 0x01000000 */ #define RCC_AHB5ENR_ETH1RXEN RCC_AHB5ENR_ETH1RXEN_Msk /*!< ETH1RX enable */ #define RCC_AHB5ENR_ETH1EN_Pos (25U) #define RCC_AHB5ENR_ETH1EN_Msk (0x1UL << RCC_AHB5ENR_ETH1EN_Pos) /*!< 0x02000000 */ #define RCC_AHB5ENR_ETH1EN RCC_AHB5ENR_ETH1EN_Msk /*!< ETH1 enable */ #define RCC_AHB5ENR_OTG1EN_Pos (26U) #define RCC_AHB5ENR_OTG1EN_Msk (0x1UL << RCC_AHB5ENR_OTG1EN_Pos) /*!< 0x04000000 */ #define RCC_AHB5ENR_OTG1EN RCC_AHB5ENR_OTG1EN_Msk /*!< OTG1 enable */ #define RCC_AHB5ENR_OTGPHY1EN_Pos (27U) #define RCC_AHB5ENR_OTGPHY1EN_Msk (0x1UL << RCC_AHB5ENR_OTGPHY1EN_Pos) /*!< 0x08000000 */ #define RCC_AHB5ENR_OTGPHY1EN RCC_AHB5ENR_OTGPHY1EN_Msk /*!< OTGPHY1 enable */ #define RCC_AHB5ENR_OTGPHY2EN_Pos (28U) #define RCC_AHB5ENR_OTGPHY2EN_Msk (0x1UL << RCC_AHB5ENR_OTGPHY2EN_Pos) /*!< 0x10000000 */ #define RCC_AHB5ENR_OTGPHY2EN RCC_AHB5ENR_OTGPHY2EN_Msk /*!< OTGPHY2 enable */ #define RCC_AHB5ENR_OTG2EN_Pos (29U) #define RCC_AHB5ENR_OTG2EN_Msk (0x1UL << RCC_AHB5ENR_OTG2EN_Pos) /*!< 0x20000000 */ #define RCC_AHB5ENR_OTG2EN RCC_AHB5ENR_OTG2EN_Msk /*!< OTG2 enable */ #define RCC_AHB5ENR_CACHEAXIEN_Pos (30U) #define RCC_AHB5ENR_CACHEAXIEN_Msk (0x1UL << RCC_AHB5ENR_CACHEAXIEN_Pos) /*!< 0x40000000 */ #define RCC_AHB5ENR_CACHEAXIEN RCC_AHB5ENR_CACHEAXIEN_Msk /*!< CACHEAXI enable */ #define RCC_AHB5ENR_NPUEN_Pos (31U) #define RCC_AHB5ENR_NPUEN_Msk (0x1UL << RCC_AHB5ENR_NPUEN_Pos) /*!< 0x80000000 */ #define RCC_AHB5ENR_NPUEN RCC_AHB5ENR_NPUEN_Msk /*!< NPU enable */ /***************** Bit definition for RCC_APB1ENR1 register *****************/ #define RCC_APB1ENR1_TIM2EN_Pos (0U) #define RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */ #define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk /*!< TIM2 enable */ #define RCC_APB1ENR1_TIM3EN_Pos (1U) #define RCC_APB1ENR1_TIM3EN_Msk (0x1UL << RCC_APB1ENR1_TIM3EN_Pos) /*!< 0x00000002 */ #define RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk /*!< TIM3 enable */ #define RCC_APB1ENR1_TIM4EN_Pos (2U) #define RCC_APB1ENR1_TIM4EN_Msk (0x1UL << RCC_APB1ENR1_TIM4EN_Pos) /*!< 0x00000004 */ #define RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk /*!< TIM4 enable */ #define RCC_APB1ENR1_TIM5EN_Pos (3U) #define RCC_APB1ENR1_TIM5EN_Msk (0x1UL << RCC_APB1ENR1_TIM5EN_Pos) /*!< 0x00000008 */ #define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk /*!< TIM5 enable */ #define RCC_APB1ENR1_TIM6EN_Pos (4U) #define RCC_APB1ENR1_TIM6EN_Msk (0x1UL << RCC_APB1ENR1_TIM6EN_Pos) /*!< 0x00000010 */ #define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk /*!< TIM6 enable */ #define RCC_APB1ENR1_TIM7EN_Pos (5U) #define RCC_APB1ENR1_TIM7EN_Msk (0x1UL << RCC_APB1ENR1_TIM7EN_Pos) /*!< 0x00000020 */ #define RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk /*!< TIM7 enable */ #define RCC_APB1ENR1_TIM12EN_Pos (6U) #define RCC_APB1ENR1_TIM12EN_Msk (0x1UL << RCC_APB1ENR1_TIM12EN_Pos) /*!< 0x00000040 */ #define RCC_APB1ENR1_TIM12EN RCC_APB1ENR1_TIM12EN_Msk /*!< TIM12 enable */ #define RCC_APB1ENR1_TIM13EN_Pos (7U) #define RCC_APB1ENR1_TIM13EN_Msk (0x1UL << RCC_APB1ENR1_TIM13EN_Pos) /*!< 0x00000080 */ #define RCC_APB1ENR1_TIM13EN RCC_APB1ENR1_TIM13EN_Msk /*!< TIM13 enable */ #define RCC_APB1ENR1_TIM14EN_Pos (8U) #define RCC_APB1ENR1_TIM14EN_Msk (0x1UL << RCC_APB1ENR1_TIM14EN_Pos) /*!< 0x00000100 */ #define RCC_APB1ENR1_TIM14EN RCC_APB1ENR1_TIM14EN_Msk /*!< TIM14 enable */ #define RCC_APB1ENR1_LPTIM1EN_Pos (9U) #define RCC_APB1ENR1_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos) /*!< 0x00000200 */ #define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk /*!< LPTIM1 enable */ #define RCC_APB1ENR1_WWDGEN_Pos (11U) #define RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */ #define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk /*!< WWDG enable */ #define RCC_APB1ENR1_TIM10EN_Pos (12U) #define RCC_APB1ENR1_TIM10EN_Msk (0x1UL << RCC_APB1ENR1_TIM10EN_Pos) /*!< 0x00001000 */ #define RCC_APB1ENR1_TIM10EN RCC_APB1ENR1_TIM10EN_Msk /*!< TIM10 enable */ #define RCC_APB1ENR1_TIM11EN_Pos (13U) #define RCC_APB1ENR1_TIM11EN_Msk (0x1UL << RCC_APB1ENR1_TIM11EN_Pos) /*!< 0x00002000 */ #define RCC_APB1ENR1_TIM11EN RCC_APB1ENR1_TIM11EN_Msk /*!< TIM11 enable */ #define RCC_APB1ENR1_SPI2EN_Pos (14U) #define RCC_APB1ENR1_SPI2EN_Msk (0x1UL << RCC_APB1ENR1_SPI2EN_Pos) /*!< 0x00004000 */ #define RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk /*!< SPI2 enable */ #define RCC_APB1ENR1_SPI3EN_Pos (15U) #define RCC_APB1ENR1_SPI3EN_Msk (0x1UL << RCC_APB1ENR1_SPI3EN_Pos) /*!< 0x00008000 */ #define RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk /*!< SPI3 enable */ #define RCC_APB1ENR1_SPDIFRX1EN_Pos (16U) #define RCC_APB1ENR1_SPDIFRX1EN_Msk (0x1UL << RCC_APB1ENR1_SPDIFRX1EN_Pos)/*!< 0x00010000 */ #define RCC_APB1ENR1_SPDIFRX1EN RCC_APB1ENR1_SPDIFRX1EN_Msk /*!< SPDIFRX1 enable */ #define RCC_APB1ENR1_USART2EN_Pos (17U) #define RCC_APB1ENR1_USART2EN_Msk (0x1UL << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */ #define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk /*!< USART2 enable */ #define RCC_APB1ENR1_USART3EN_Pos (18U) #define RCC_APB1ENR1_USART3EN_Msk (0x1UL << RCC_APB1ENR1_USART3EN_Pos) /*!< 0x00040000 */ #define RCC_APB1ENR1_USART3EN RCC_APB1ENR1_USART3EN_Msk /*!< USART3 enable */ #define RCC_APB1ENR1_UART4EN_Pos (19U) #define RCC_APB1ENR1_UART4EN_Msk (0x1UL << RCC_APB1ENR1_UART4EN_Pos) /*!< 0x00080000 */ #define RCC_APB1ENR1_UART4EN RCC_APB1ENR1_UART4EN_Msk /*!< UART4 enable */ #define RCC_APB1ENR1_UART5EN_Pos (20U) #define RCC_APB1ENR1_UART5EN_Msk (0x1UL << RCC_APB1ENR1_UART5EN_Pos) /*!< 0x00100000 */ #define RCC_APB1ENR1_UART5EN RCC_APB1ENR1_UART5EN_Msk /*!< UART5 enable */ #define RCC_APB1ENR1_I2C1EN_Pos (21U) #define RCC_APB1ENR1_I2C1EN_Msk (0x1UL << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */ #define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk /*!< I2C1 enable */ #define RCC_APB1ENR1_I2C2EN_Pos (22U) #define RCC_APB1ENR1_I2C2EN_Msk (0x1UL << RCC_APB1ENR1_I2C2EN_Pos) /*!< 0x00400000 */ #define RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk /*!< I2C2 enable */ #define RCC_APB1ENR1_I2C3EN_Pos (23U) #define RCC_APB1ENR1_I2C3EN_Msk (0x1UL << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */ #define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk /*!< I2C3 enable */ #define RCC_APB1ENR1_I3C1EN_Pos (24U) #define RCC_APB1ENR1_I3C1EN_Msk (0x1UL << RCC_APB1ENR1_I3C1EN_Pos) /*!< 0x01000000 */ #define RCC_APB1ENR1_I3C1EN RCC_APB1ENR1_I3C1EN_Msk /*!< I3C1 enable */ #define RCC_APB1ENR1_I3C2EN_Pos (25U) #define RCC_APB1ENR1_I3C2EN_Msk (0x1UL << RCC_APB1ENR1_I3C2EN_Pos) /*!< 0x02000000 */ #define RCC_APB1ENR1_I3C2EN RCC_APB1ENR1_I3C2EN_Msk /*!< I3C2 enable */ #define RCC_APB1ENR1_UART7EN_Pos (30U) #define RCC_APB1ENR1_UART7EN_Msk (0x1UL << RCC_APB1ENR1_UART7EN_Pos) /*!< 0x40000000 */ #define RCC_APB1ENR1_UART7EN RCC_APB1ENR1_UART7EN_Msk /*!< UART7 enable */ #define RCC_APB1ENR1_UART8EN_Pos (31U) #define RCC_APB1ENR1_UART8EN_Msk (0x1UL << RCC_APB1ENR1_UART8EN_Pos) /*!< 0x80000000 */ #define RCC_APB1ENR1_UART8EN RCC_APB1ENR1_UART8EN_Msk /*!< UART8 enable */ /***************** Bit definition for RCC_APB1ENR2 register *****************/ #define RCC_APB1ENR2_MDIOSEN_Pos (5U) #define RCC_APB1ENR2_MDIOSEN_Msk (0x1UL << RCC_APB1ENR2_MDIOSEN_Pos) /*!< 0x00000020 */ #define RCC_APB1ENR2_MDIOSEN RCC_APB1ENR2_MDIOSEN_Msk /*!< MDIOS enable */ #define RCC_APB1ENR2_FDCANEN_Pos (8U) #define RCC_APB1ENR2_FDCANEN_Msk (0x1UL << RCC_APB1ENR2_FDCANEN_Pos) /*!< 0x00000100 */ #define RCC_APB1ENR2_FDCANEN RCC_APB1ENR2_FDCANEN_Msk /*!< FDCAN enable */ #define RCC_APB1ENR2_UCPD1EN_Pos (18U) #define RCC_APB1ENR2_UCPD1EN_Msk (0x1UL << RCC_APB1ENR2_UCPD1EN_Pos) /*!< 0x00040000 */ #define RCC_APB1ENR2_UCPD1EN RCC_APB1ENR2_UCPD1EN_Msk /*!< UCPD1 enable */ /***************** Bit definition for RCC_APB2ENR register ******************/ #define RCC_APB2ENR_TIM1EN_Pos (0U) #define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */ #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 enable */ #define RCC_APB2ENR_TIM8EN_Pos (1U) #define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */ #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk /*!< TIM8 enable */ #define RCC_APB2ENR_USART1EN_Pos (4U) #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */ #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 enable */ #define RCC_APB2ENR_USART6EN_Pos (5U) #define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */ #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk /*!< USART6 enable */ #define RCC_APB2ENR_UART9EN_Pos (6U) #define RCC_APB2ENR_UART9EN_Msk (0x1UL << RCC_APB2ENR_UART9EN_Pos) /*!< 0x00000040 */ #define RCC_APB2ENR_UART9EN RCC_APB2ENR_UART9EN_Msk /*!< UART9 enable */ #define RCC_APB2ENR_USART10EN_Pos (7U) #define RCC_APB2ENR_USART10EN_Msk (0x1UL << RCC_APB2ENR_USART10EN_Pos) /*!< 0x00000080 */ #define RCC_APB2ENR_USART10EN RCC_APB2ENR_USART10EN_Msk /*!< USART10 enable */ #define RCC_APB2ENR_SPI1EN_Pos (12U) #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 enable */ #define RCC_APB2ENR_SPI4EN_Pos (13U) #define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */ #define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk /*!< SPI4 enable */ #define RCC_APB2ENR_TIM18EN_Pos (15U) #define RCC_APB2ENR_TIM18EN_Msk (0x1UL << RCC_APB2ENR_TIM18EN_Pos) /*!< 0x00008000 */ #define RCC_APB2ENR_TIM18EN RCC_APB2ENR_TIM18EN_Msk /*!< TIM18 enable */ #define RCC_APB2ENR_TIM15EN_Pos (16U) #define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */ #define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk /*!< TIM15 enable */ #define RCC_APB2ENR_TIM16EN_Pos (17U) #define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk /*!< TIM16 enable */ #define RCC_APB2ENR_TIM17EN_Pos (18U) #define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk /*!< TIM17 enable */ #define RCC_APB2ENR_TIM9EN_Pos (19U) #define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00080000 */ #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk /*!< TIM9 enable */ #define RCC_APB2ENR_SPI5EN_Pos (20U) #define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */ #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk /*!< SPI5 enable */ #define RCC_APB2ENR_SAI1EN_Pos (21U) #define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00200000 */ #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk /*!< SAI1 enable */ #define RCC_APB2ENR_SAI2EN_Pos (22U) #define RCC_APB2ENR_SAI2EN_Msk (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00400000 */ #define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk /*!< SAI2 enable */ /***************** Bit definition for RCC_APB3ENR register ******************/ #define RCC_APB3ENR_DFTEN_Pos (2U) #define RCC_APB3ENR_DFTEN_Msk (0x1UL << RCC_APB3ENR_DFTEN_Pos) /*!< 0x00000004 */ #define RCC_APB3ENR_DFTEN RCC_APB3ENR_DFTEN_Msk /*!< DFT enable */ /***************** Bit definition for RCC_APB4ENR1 register *****************/ #define RCC_APB4ENR1_HDPEN_Pos (2U) #define RCC_APB4ENR1_HDPEN_Msk (0x1UL << RCC_APB4ENR1_HDPEN_Pos) /*!< 0x00000004 */ #define RCC_APB4ENR1_HDPEN RCC_APB4ENR1_HDPEN_Msk /*!< HDP enable */ #define RCC_APB4ENR1_LPUART1EN_Pos (3U) #define RCC_APB4ENR1_LPUART1EN_Msk (0x1UL << RCC_APB4ENR1_LPUART1EN_Pos) /*!< 0x00000008 */ #define RCC_APB4ENR1_LPUART1EN RCC_APB4ENR1_LPUART1EN_Msk /*!< LPUART1 enable */ #define RCC_APB4ENR1_SPI6EN_Pos (5U) #define RCC_APB4ENR1_SPI6EN_Msk (0x1UL << RCC_APB4ENR1_SPI6EN_Pos) /*!< 0x00000020 */ #define RCC_APB4ENR1_SPI6EN RCC_APB4ENR1_SPI6EN_Msk /*!< SPI6 enable */ #define RCC_APB4ENR1_I2C4EN_Pos (7U) #define RCC_APB4ENR1_I2C4EN_Msk (0x1UL << RCC_APB4ENR1_I2C4EN_Pos) /*!< 0x00000080 */ #define RCC_APB4ENR1_I2C4EN RCC_APB4ENR1_I2C4EN_Msk /*!< I2C4 enable */ #define RCC_APB4ENR1_LPTIM2EN_Pos (9U) #define RCC_APB4ENR1_LPTIM2EN_Msk (0x1UL << RCC_APB4ENR1_LPTIM2EN_Pos) /*!< 0x00000200 */ #define RCC_APB4ENR1_LPTIM2EN RCC_APB4ENR1_LPTIM2EN_Msk /*!< LPTIM2 enable */ #define RCC_APB4ENR1_LPTIM3EN_Pos (10U) #define RCC_APB4ENR1_LPTIM3EN_Msk (0x1UL << RCC_APB4ENR1_LPTIM3EN_Pos) /*!< 0x00000400 */ #define RCC_APB4ENR1_LPTIM3EN RCC_APB4ENR1_LPTIM3EN_Msk /*!< LPTIM3 enable */ #define RCC_APB4ENR1_LPTIM4EN_Pos (11U) #define RCC_APB4ENR1_LPTIM4EN_Msk (0x1UL << RCC_APB4ENR1_LPTIM4EN_Pos) /*!< 0x00000800 */ #define RCC_APB4ENR1_LPTIM4EN RCC_APB4ENR1_LPTIM4EN_Msk /*!< LPTIM4 enable */ #define RCC_APB4ENR1_LPTIM5EN_Pos (12U) #define RCC_APB4ENR1_LPTIM5EN_Msk (0x1UL << RCC_APB4ENR1_LPTIM5EN_Pos) /*!< 0x00001000 */ #define RCC_APB4ENR1_LPTIM5EN RCC_APB4ENR1_LPTIM5EN_Msk /*!< LPTIM5 enable */ #define RCC_APB4ENR1_VREFBUFEN_Pos (15U) #define RCC_APB4ENR1_VREFBUFEN_Msk (0x1UL << RCC_APB4ENR1_VREFBUFEN_Pos) /*!< 0x00008000 */ #define RCC_APB4ENR1_VREFBUFEN RCC_APB4ENR1_VREFBUFEN_Msk /*!< VREFBUF enable */ #define RCC_APB4ENR1_RTCEN_Pos (16U) #define RCC_APB4ENR1_RTCEN_Msk (0x1UL << RCC_APB4ENR1_RTCEN_Pos) /*!< 0x00010000 */ #define RCC_APB4ENR1_RTCEN RCC_APB4ENR1_RTCEN_Msk /*!< RTC enable */ #define RCC_APB4ENR1_RTCAPBEN_Pos (17U) #define RCC_APB4ENR1_RTCAPBEN_Msk (0x1UL << RCC_APB4ENR1_RTCAPBEN_Pos) /*!< 0x00020000 */ #define RCC_APB4ENR1_RTCAPBEN RCC_APB4ENR1_RTCAPBEN_Msk /*!< RTCAPB enable */ /***************** Bit definition for RCC_APB4ENR2 register *****************/ #define RCC_APB4ENR2_SYSCFGEN_Pos (0U) #define RCC_APB4ENR2_SYSCFGEN_Msk (0x1UL << RCC_APB4ENR2_SYSCFGEN_Pos) /*!< 0x00000001 */ #define RCC_APB4ENR2_SYSCFGEN RCC_APB4ENR2_SYSCFGEN_Msk /*!< SYSCFG enable */ #define RCC_APB4ENR2_BSECEN_Pos (1U) #define RCC_APB4ENR2_BSECEN_Msk (0x1UL << RCC_APB4ENR2_BSECEN_Pos) /*!< 0x00000002 */ #define RCC_APB4ENR2_BSECEN RCC_APB4ENR2_BSECEN_Msk /*!< BSEC enable */ #define RCC_APB4ENR2_DTSEN_Pos (2U) #define RCC_APB4ENR2_DTSEN_Msk (0x1UL << RCC_APB4ENR2_DTSEN_Pos) /*!< 0x00000004 */ #define RCC_APB4ENR2_DTSEN RCC_APB4ENR2_DTSEN_Msk /*!< DTS enable */ /***************** Bit definition for RCC_APB5ENR register ******************/ #define RCC_APB5ENR_LTDCEN_Pos (1U) #define RCC_APB5ENR_LTDCEN_Msk (0x1UL << RCC_APB5ENR_LTDCEN_Pos) /*!< 0x00000002 */ #define RCC_APB5ENR_LTDCEN RCC_APB5ENR_LTDCEN_Msk /*!< LTDC enable */ #define RCC_APB5ENR_DCMIPPEN_Pos (2U) #define RCC_APB5ENR_DCMIPPEN_Msk (0x1UL << RCC_APB5ENR_DCMIPPEN_Pos) /*!< 0x00000004 */ #define RCC_APB5ENR_DCMIPPEN RCC_APB5ENR_DCMIPPEN_Msk /*!< DCMIPP enable */ #define RCC_APB5ENR_GFXTIMEN_Pos (4U) #define RCC_APB5ENR_GFXTIMEN_Msk (0x1UL << RCC_APB5ENR_GFXTIMEN_Pos) /*!< 0x00000010 */ #define RCC_APB5ENR_GFXTIMEN RCC_APB5ENR_GFXTIMEN_Msk /*!< GFXTIM enable */ #define RCC_APB5ENR_VENCEN_Pos (5U) #define RCC_APB5ENR_VENCEN_Msk (0x1UL << RCC_APB5ENR_VENCEN_Pos) /*!< 0x00000020 */ #define RCC_APB5ENR_VENCEN RCC_APB5ENR_VENCEN_Msk /*!< VENC enable */ #define RCC_APB5ENR_CSIEN_Pos (6U) #define RCC_APB5ENR_CSIEN_Msk (0x1UL << RCC_APB5ENR_CSIEN_Pos) /*!< 0x00000040 */ #define RCC_APB5ENR_CSIEN RCC_APB5ENR_CSIEN_Msk /*!< CSI enable */ /***************** Bit definition for RCC_BUSLPENR register *****************/ #define RCC_BUSLPENR_ACLKNLPEN_Pos (0U) #define RCC_BUSLPENR_ACLKNLPEN_Msk (0x1UL << RCC_BUSLPENR_ACLKNLPEN_Pos) /*!< 0x00000001 */ #define RCC_BUSLPENR_ACLKNLPEN RCC_BUSLPENR_ACLKNLPEN_Msk /*!< ACLKN enable */ #define RCC_BUSLPENR_ACLKNCLPEN_Pos (1U) #define RCC_BUSLPENR_ACLKNCLPEN_Msk (0x1UL << RCC_BUSLPENR_ACLKNCLPEN_Pos)/*!< 0x00000002 */ #define RCC_BUSLPENR_ACLKNCLPEN RCC_BUSLPENR_ACLKNCLPEN_Msk /*!< ACLKNC enable */ /**************** Bit definition for RCC_MISCLPENR register *****************/ #define RCC_MISCLPENR_DBGLPEN_Pos (0U) #define RCC_MISCLPENR_DBGLPEN_Msk (0x1UL << RCC_MISCLPENR_DBGLPEN_Pos) /*!< 0x00000001 */ #define RCC_MISCLPENR_DBGLPEN RCC_MISCLPENR_DBGLPEN_Msk /*!< DBG enable */ #define RCC_MISCLPENR_XSPIPHYCOMPLPEN_Pos (3U) #define RCC_MISCLPENR_XSPIPHYCOMPLPEN_Msk (0x1UL << RCC_MISCLPENR_XSPIPHYCOMPLPEN_Pos) /*!< 0x00000008 */ #define RCC_MISCLPENR_XSPIPHYCOMPLPEN RCC_MISCLPENR_XSPIPHYCOMPLPEN_Msk /*!< XSPIPHYCOMP enable */ #define RCC_MISCLPENR_PERLPEN_Pos (6U) #define RCC_MISCLPENR_PERLPEN_Msk (0x1UL << RCC_MISCLPENR_PERLPEN_Pos) /*!< 0x00000040 */ #define RCC_MISCLPENR_PERLPEN RCC_MISCLPENR_PERLPEN_Msk /*!< PER enable */ /***************** Bit definition for RCC_MEMLPENR register *****************/ #define RCC_MEMLPENR_AXISRAM3LPEN_Pos (0U) #define RCC_MEMLPENR_AXISRAM3LPEN_Msk (0x1UL << RCC_MEMLPENR_AXISRAM3LPEN_Pos) /*!< 0x00000001 */ #define RCC_MEMLPENR_AXISRAM3LPEN RCC_MEMLPENR_AXISRAM3LPEN_Msk /*!< AXISRAM3 enable */ #define RCC_MEMLPENR_AXISRAM4LPEN_Pos (1U) #define RCC_MEMLPENR_AXISRAM4LPEN_Msk (0x1UL << RCC_MEMLPENR_AXISRAM4LPEN_Pos) /*!< 0x00000002 */ #define RCC_MEMLPENR_AXISRAM4LPEN RCC_MEMLPENR_AXISRAM4LPEN_Msk /*!< AXISRAM4 enable */ #define RCC_MEMLPENR_AXISRAM5LPEN_Pos (2U) #define RCC_MEMLPENR_AXISRAM5LPEN_Msk (0x1UL << RCC_MEMLPENR_AXISRAM5LPEN_Pos) /*!< 0x00000004 */ #define RCC_MEMLPENR_AXISRAM5LPEN RCC_MEMLPENR_AXISRAM5LPEN_Msk /*!< AXISRAM5 enable */ #define RCC_MEMLPENR_AXISRAM6LPEN_Pos (3U) #define RCC_MEMLPENR_AXISRAM6LPEN_Msk (0x1UL << RCC_MEMLPENR_AXISRAM6LPEN_Pos) /*!< 0x00000008 */ #define RCC_MEMLPENR_AXISRAM6LPEN RCC_MEMLPENR_AXISRAM6LPEN_Msk /*!< AXISRAM6 enable */ #define RCC_MEMLPENR_AHBSRAM1LPEN_Pos (4U) #define RCC_MEMLPENR_AHBSRAM1LPEN_Msk (0x1UL << RCC_MEMLPENR_AHBSRAM1LPEN_Pos) /*!< 0x00000010 */ #define RCC_MEMLPENR_AHBSRAM1LPEN RCC_MEMLPENR_AHBSRAM1LPEN_Msk /*!< AHBSRAM1 enable */ #define RCC_MEMLPENR_AHBSRAM2LPEN_Pos (5U) #define RCC_MEMLPENR_AHBSRAM2LPEN_Msk (0x1UL << RCC_MEMLPENR_AHBSRAM2LPEN_Pos) /*!< 0x00000020 */ #define RCC_MEMLPENR_AHBSRAM2LPEN RCC_MEMLPENR_AHBSRAM2LPEN_Msk /*!< AHBSRAM2 enable */ #define RCC_MEMLPENR_BKPSRAMLPEN_Pos (6U) #define RCC_MEMLPENR_BKPSRAMLPEN_Msk (0x1UL << RCC_MEMLPENR_BKPSRAMLPEN_Pos) /*!< 0x00000040 */ #define RCC_MEMLPENR_BKPSRAMLPEN RCC_MEMLPENR_BKPSRAMLPEN_Msk /*!< BKPSRAM enable */ #define RCC_MEMLPENR_AXISRAM1LPEN_Pos (7U) #define RCC_MEMLPENR_AXISRAM1LPEN_Msk (0x1UL << RCC_MEMLPENR_AXISRAM1LPEN_Pos) /*!< 0x00000080 */ #define RCC_MEMLPENR_AXISRAM1LPEN RCC_MEMLPENR_AXISRAM1LPEN_Msk /*!< AXISRAM1 enable */ #define RCC_MEMLPENR_AXISRAM2LPEN_Pos (8U) #define RCC_MEMLPENR_AXISRAM2LPEN_Msk (0x1UL << RCC_MEMLPENR_AXISRAM2LPEN_Pos) /*!< 0x00000100 */ #define RCC_MEMLPENR_AXISRAM2LPEN RCC_MEMLPENR_AXISRAM2LPEN_Msk /*!< AXISRAM2 enable */ #define RCC_MEMLPENR_FLEXRAMLPEN_Pos (9U) #define RCC_MEMLPENR_FLEXRAMLPEN_Msk (0x1UL << RCC_MEMLPENR_FLEXRAMLPEN_Pos) /*!< 0x00000200 */ #define RCC_MEMLPENR_FLEXRAMLPEN RCC_MEMLPENR_FLEXRAMLPEN_Msk /*!< FLEXRAM enable */ #define RCC_MEMLPENR_CACHEAXIRAMLPEN_Pos (10U) #define RCC_MEMLPENR_CACHEAXIRAMLPEN_Msk (0x1UL << RCC_MEMLPENR_CACHEAXIRAMLPEN_Pos) /*!< 0x00000400 */ #define RCC_MEMLPENR_CACHEAXIRAMLPEN RCC_MEMLPENR_CACHEAXIRAMLPEN_Msk /*!< CACHEAXIRAM enable */ #define RCC_MEMLPENR_VENCRAMLPEN_Pos (11U) #define RCC_MEMLPENR_VENCRAMLPEN_Msk (0x1UL << RCC_MEMLPENR_VENCRAMLPEN_Pos) /*!< 0x00000800 */ #define RCC_MEMLPENR_VENCRAMLPEN RCC_MEMLPENR_VENCRAMLPEN_Msk /*!< VENCRAM enable */ #define RCC_MEMLPENR_BOOTROMLPEN_Pos (12U) #define RCC_MEMLPENR_BOOTROMLPEN_Msk (0x1UL << RCC_MEMLPENR_BOOTROMLPEN_Pos) /*!< 0x00001000 */ #define RCC_MEMLPENR_BOOTROMLPEN RCC_MEMLPENR_BOOTROMLPEN_Msk /*!< Boot ROM enable */ /**************** Bit definition for RCC_AHB1LPENR register *****************/ #define RCC_AHB1LPENR_GPDMA1LPEN_Pos (4U) #define RCC_AHB1LPENR_GPDMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_GPDMA1LPEN_Pos) /*!< 0x00000010 */ #define RCC_AHB1LPENR_GPDMA1LPEN RCC_AHB1LPENR_GPDMA1LPEN_Msk /*!< GPDMA1 enable */ #define RCC_AHB1LPENR_ADC12LPEN_Pos (5U) #define RCC_AHB1LPENR_ADC12LPEN_Msk (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos)/*!< 0x00000020 */ #define RCC_AHB1LPENR_ADC12LPEN RCC_AHB1LPENR_ADC12LPEN_Msk /*!< ADC12 enable */ /**************** Bit definition for RCC_AHB2LPENR register *****************/ #define RCC_AHB2LPENR_RAMCFGLPEN_Pos (12U) #define RCC_AHB2LPENR_RAMCFGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RAMCFGLPEN_Pos) /*!< 0x00001000 */ #define RCC_AHB2LPENR_RAMCFGLPEN RCC_AHB2LPENR_RAMCFGLPEN_Msk /*!< RAMCFG enable */ #define RCC_AHB2LPENR_MDF1LPEN_Pos (16U) #define RCC_AHB2LPENR_MDF1LPEN_Msk (0x1UL << RCC_AHB2LPENR_MDF1LPEN_Pos) /*!< 0x00010000 */ #define RCC_AHB2LPENR_MDF1LPEN RCC_AHB2LPENR_MDF1LPEN_Msk /*!< MDF1 enable */ #define RCC_AHB2LPENR_ADF1LPEN_Pos (17U) #define RCC_AHB2LPENR_ADF1LPEN_Msk (0x1UL << RCC_AHB2LPENR_ADF1LPEN_Pos) /*!< 0x00020000 */ #define RCC_AHB2LPENR_ADF1LPEN RCC_AHB2LPENR_ADF1LPEN_Msk /*!< ADF1 enable */ /**************** Bit definition for RCC_AHB3LPENR register *****************/ #define RCC_AHB3LPENR_RNGLPEN_Pos (0U) #define RCC_AHB3LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB3LPENR_RNGLPEN_Pos) /*!< 0x00000001 */ #define RCC_AHB3LPENR_RNGLPEN RCC_AHB3LPENR_RNGLPEN_Msk /*!< RNG enable */ #define RCC_AHB3LPENR_HASHLPEN_Pos (1U) #define RCC_AHB3LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB3LPENR_HASHLPEN_Pos) /*!< 0x00000002 */ #define RCC_AHB3LPENR_HASHLPEN RCC_AHB3LPENR_HASHLPEN_Msk /*!< HASH enable */ #define RCC_AHB3LPENR_CRYPLPEN_Pos (2U) #define RCC_AHB3LPENR_CRYPLPEN_Msk (0x1UL << RCC_AHB3LPENR_CRYPLPEN_Pos) /*!< 0x00000004 */ #define RCC_AHB3LPENR_CRYPLPEN RCC_AHB3LPENR_CRYPLPEN_Msk /*!< CRYP enable */ #define RCC_AHB3LPENR_SAESLPEN_Pos (4U) #define RCC_AHB3LPENR_SAESLPEN_Msk (0x1UL << RCC_AHB3LPENR_SAESLPEN_Pos) /*!< 0x00000010 */ #define RCC_AHB3LPENR_SAESLPEN RCC_AHB3LPENR_SAESLPEN_Msk /*!< SAES enable */ #define RCC_AHB3LPENR_PKALPEN_Pos (8U) #define RCC_AHB3LPENR_PKALPEN_Msk (0x1UL << RCC_AHB3LPENR_PKALPEN_Pos) /*!< 0x00000100 */ #define RCC_AHB3LPENR_PKALPEN RCC_AHB3LPENR_PKALPEN_Msk /*!< PKA enable */ #define RCC_AHB3LPENR_RIFSCLPEN_Pos (9U) #define RCC_AHB3LPENR_RIFSCLPEN_Msk (0x1UL << RCC_AHB3LPENR_RIFSCLPEN_Pos)/*!< 0x00000200 */ #define RCC_AHB3LPENR_RIFSCLPEN RCC_AHB3LPENR_RIFSCLPEN_Msk /*!< RIFSC enable */ #define RCC_AHB3LPENR_IACLPEN_Pos (10U) #define RCC_AHB3LPENR_IACLPEN_Msk (0x1UL << RCC_AHB3LPENR_IACLPEN_Pos) /*!< 0x00000400 */ #define RCC_AHB3LPENR_IACLPEN RCC_AHB3LPENR_IACLPEN_Msk /*!< IAC enable */ #define RCC_AHB3LPENR_RISAFLPEN_Pos (14U) #define RCC_AHB3LPENR_RISAFLPEN_Msk (0x1UL << RCC_AHB3LPENR_RISAFLPEN_Pos)/*!< 0x00004000 */ #define RCC_AHB3LPENR_RISAFLPEN RCC_AHB3LPENR_RISAFLPEN_Msk /*!< RISAF enable */ /**************** Bit definition for RCC_AHB4LPENR register *****************/ #define RCC_AHB4LPENR_GPIOALPEN_Pos (0U) #define RCC_AHB4LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos)/*!< 0x00000001 */ #define RCC_AHB4LPENR_GPIOALPEN RCC_AHB4LPENR_GPIOALPEN_Msk /*!< GPIO A enable */ #define RCC_AHB4LPENR_GPIOBLPEN_Pos (1U) #define RCC_AHB4LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos)/*!< 0x00000002 */ #define RCC_AHB4LPENR_GPIOBLPEN RCC_AHB4LPENR_GPIOBLPEN_Msk /*!< GPIO B enable */ #define RCC_AHB4LPENR_GPIOCLPEN_Pos (2U) #define RCC_AHB4LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos)/*!< 0x00000004 */ #define RCC_AHB4LPENR_GPIOCLPEN RCC_AHB4LPENR_GPIOCLPEN_Msk /*!< GPIO C enable */ #define RCC_AHB4LPENR_GPIODLPEN_Pos (3U) #define RCC_AHB4LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos)/*!< 0x00000008 */ #define RCC_AHB4LPENR_GPIODLPEN RCC_AHB4LPENR_GPIODLPEN_Msk /*!< GPIO D enable */ #define RCC_AHB4LPENR_GPIOELPEN_Pos (4U) #define RCC_AHB4LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos)/*!< 0x00000010 */ #define RCC_AHB4LPENR_GPIOELPEN RCC_AHB4LPENR_GPIOELPEN_Msk /*!< GPIO E enable */ #define RCC_AHB4LPENR_GPIOFLPEN_Pos (5U) #define RCC_AHB4LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos)/*!< 0x00000020 */ #define RCC_AHB4LPENR_GPIOFLPEN RCC_AHB4LPENR_GPIOFLPEN_Msk /*!< GPIO F enable */ #define RCC_AHB4LPENR_GPIOGLPEN_Pos (6U) #define RCC_AHB4LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos)/*!< 0x00000040 */ #define RCC_AHB4LPENR_GPIOGLPEN RCC_AHB4LPENR_GPIOGLPEN_Msk /*!< GPIO G enable */ #define RCC_AHB4LPENR_GPIOHLPEN_Pos (7U) #define RCC_AHB4LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos)/*!< 0x00000080 */ #define RCC_AHB4LPENR_GPIOHLPEN RCC_AHB4LPENR_GPIOHLPEN_Msk /*!< GPIO H enable */ #define RCC_AHB4LPENR_GPIONLPEN_Pos (13U) #define RCC_AHB4LPENR_GPIONLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIONLPEN_Pos)/*!< 0x00002000 */ #define RCC_AHB4LPENR_GPIONLPEN RCC_AHB4LPENR_GPIONLPEN_Msk /*!< GPIO N enable */ #define RCC_AHB4LPENR_GPIOOLPEN_Pos (14U) #define RCC_AHB4LPENR_GPIOOLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOOLPEN_Pos)/*!< 0x00004000 */ #define RCC_AHB4LPENR_GPIOOLPEN RCC_AHB4LPENR_GPIOOLPEN_Msk /*!< GPIO O enable */ #define RCC_AHB4LPENR_GPIOPLPEN_Pos (15U) #define RCC_AHB4LPENR_GPIOPLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOPLPEN_Pos)/*!< 0x00008000 */ #define RCC_AHB4LPENR_GPIOPLPEN RCC_AHB4LPENR_GPIOPLPEN_Msk /*!< GPIO P enable */ #define RCC_AHB4LPENR_GPIOQLPEN_Pos (16U) #define RCC_AHB4LPENR_GPIOQLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOQLPEN_Pos)/*!< 0x00010000 */ #define RCC_AHB4LPENR_GPIOQLPEN RCC_AHB4LPENR_GPIOQLPEN_Msk /*!< GPIO Q enable */ #define RCC_AHB4LPENR_PWRLPEN_Pos (18U) #define RCC_AHB4LPENR_PWRLPEN_Msk (0x1UL << RCC_AHB4LPENR_PWRLPEN_Pos) /*!< 0x00040000 */ #define RCC_AHB4LPENR_PWRLPEN RCC_AHB4LPENR_PWRLPEN_Msk /*!< PWR enable */ #define RCC_AHB4LPENR_CRCLPEN_Pos (19U) #define RCC_AHB4LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos) /*!< 0x00080000 */ #define RCC_AHB4LPENR_CRCLPEN RCC_AHB4LPENR_CRCLPEN_Msk /*!< CRC enable */ /**************** Bit definition for RCC_AHB5LPENR register *****************/ #define RCC_AHB5LPENR_HPDMA1LPEN_Pos (0U) #define RCC_AHB5LPENR_HPDMA1LPEN_Msk (0x1UL << RCC_AHB5LPENR_HPDMA1LPEN_Pos) /*!< 0x00000001 */ #define RCC_AHB5LPENR_HPDMA1LPEN RCC_AHB5LPENR_HPDMA1LPEN_Msk /*!< HPDMA1 enable */ #define RCC_AHB5LPENR_DMA2DLPEN_Pos (1U) #define RCC_AHB5LPENR_DMA2DLPEN_Msk (0x1UL << RCC_AHB5LPENR_DMA2DLPEN_Pos)/*!< 0x00000002 */ #define RCC_AHB5LPENR_DMA2DLPEN RCC_AHB5LPENR_DMA2DLPEN_Msk /*!< DMA2D enable */ #define RCC_AHB5LPENR_JPEGLPEN_Pos (3U) #define RCC_AHB5LPENR_JPEGLPEN_Msk (0x1UL << RCC_AHB5LPENR_JPEGLPEN_Pos) /*!< 0x00000008 */ #define RCC_AHB5LPENR_JPEGLPEN RCC_AHB5LPENR_JPEGLPEN_Msk /*!< JPEG enable */ #define RCC_AHB5LPENR_FMCLPEN_Pos (4U) #define RCC_AHB5LPENR_FMCLPEN_Msk (0x1UL << RCC_AHB5LPENR_FMCLPEN_Pos) /*!< 0x00000010 */ #define RCC_AHB5LPENR_FMCLPEN RCC_AHB5LPENR_FMCLPEN_Msk /*!< FMC enable */ #define RCC_AHB5LPENR_XSPI1LPEN_Pos (5U) #define RCC_AHB5LPENR_XSPI1LPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPI1LPEN_Pos)/*!< 0x00000020 */ #define RCC_AHB5LPENR_XSPI1LPEN RCC_AHB5LPENR_XSPI1LPEN_Msk /*!< XSPI1 enable */ #define RCC_AHB5LPENR_PSSILPEN_Pos (6U) #define RCC_AHB5LPENR_PSSILPEN_Msk (0x1UL << RCC_AHB5LPENR_PSSILPEN_Pos) /*!< 0x00000040 */ #define RCC_AHB5LPENR_PSSILPEN RCC_AHB5LPENR_PSSILPEN_Msk /*!< PSSI enable */ #define RCC_AHB5LPENR_SDMMC2LPEN_Pos (7U) #define RCC_AHB5LPENR_SDMMC2LPEN_Msk (0x1UL << RCC_AHB5LPENR_SDMMC2LPEN_Pos) /*!< 0x00000080 */ #define RCC_AHB5LPENR_SDMMC2LPEN RCC_AHB5LPENR_SDMMC2LPEN_Msk /*!< SDMMC2 enable */ #define RCC_AHB5LPENR_SDMMC1LPEN_Pos (8U) #define RCC_AHB5LPENR_SDMMC1LPEN_Msk (0x1UL << RCC_AHB5LPENR_SDMMC1LPEN_Pos) /*!< 0x00000100 */ #define RCC_AHB5LPENR_SDMMC1LPEN RCC_AHB5LPENR_SDMMC1LPEN_Msk /*!< SDMMC1 enable */ #define RCC_AHB5LPENR_XSPI2LPEN_Pos (12U) #define RCC_AHB5LPENR_XSPI2LPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPI2LPEN_Pos)/*!< 0x00001000 */ #define RCC_AHB5LPENR_XSPI2LPEN RCC_AHB5LPENR_XSPI2LPEN_Msk /*!< XSPI2 enable */ #define RCC_AHB5LPENR_XSPIMLPEN_Pos (13U) #define RCC_AHB5LPENR_XSPIMLPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPIMLPEN_Pos)/*!< 0x00002000 */ #define RCC_AHB5LPENR_XSPIMLPEN RCC_AHB5LPENR_XSPIMLPEN_Msk /*!< XSPIM enable */ #define RCC_AHB5LPENR_MCE1LPEN_Pos (14U) #define RCC_AHB5LPENR_MCE1LPEN_Msk (0x1UL << RCC_AHB5LPENR_MCE1LPEN_Pos) /*!< 0x00004000 */ #define RCC_AHB5LPENR_MCE1LPEN RCC_AHB5LPENR_MCE1LPEN_Msk /*!< MCE1 enable */ #define RCC_AHB5LPENR_MCE2LPEN_Pos (15U) #define RCC_AHB5LPENR_MCE2LPEN_Msk (0x1UL << RCC_AHB5LPENR_MCE2LPEN_Pos) /*!< 0x00008000 */ #define RCC_AHB5LPENR_MCE2LPEN RCC_AHB5LPENR_MCE2LPEN_Msk /*!< MCE2 enable */ #define RCC_AHB5LPENR_MCE3LPEN_Pos (16U) #define RCC_AHB5LPENR_MCE3LPEN_Msk (0x1UL << RCC_AHB5LPENR_MCE3LPEN_Pos) /*!< 0x00010000 */ #define RCC_AHB5LPENR_MCE3LPEN RCC_AHB5LPENR_MCE3LPEN_Msk /*!< MCE3 enable */ #define RCC_AHB5LPENR_XSPI3LPEN_Pos (17U) #define RCC_AHB5LPENR_XSPI3LPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPI3LPEN_Pos)/*!< 0x00020000 */ #define RCC_AHB5LPENR_XSPI3LPEN RCC_AHB5LPENR_XSPI3LPEN_Msk /*!< XSPI3 enable */ #define RCC_AHB5LPENR_MCE4LPEN_Pos (18U) #define RCC_AHB5LPENR_MCE4LPEN_Msk (0x1UL << RCC_AHB5LPENR_MCE4LPEN_Pos) /*!< 0x00040000 */ #define RCC_AHB5LPENR_MCE4LPEN RCC_AHB5LPENR_MCE4LPEN_Msk /*!< MCE4 enable */ #define RCC_AHB5LPENR_GFXMMULPEN_Pos (19U) #define RCC_AHB5LPENR_GFXMMULPEN_Msk (0x1UL << RCC_AHB5LPENR_GFXMMULPEN_Pos) /*!< 0x00080000 */ #define RCC_AHB5LPENR_GFXMMULPEN RCC_AHB5LPENR_GFXMMULPEN_Msk /*!< GFXMMU enable */ #define RCC_AHB5LPENR_GPU2DLPEN_Pos (20U) #define RCC_AHB5LPENR_GPU2DLPEN_Msk (0x1UL << RCC_AHB5LPENR_GPU2DLPEN_Pos)/*!< 0x00100000 */ #define RCC_AHB5LPENR_GPU2DLPEN RCC_AHB5LPENR_GPU2DLPEN_Msk /*!< GPU2D enable */ #define RCC_AHB5LPENR_ETH1MACLPEN_Pos (22U) #define RCC_AHB5LPENR_ETH1MACLPEN_Msk (0x1UL << RCC_AHB5LPENR_ETH1MACLPEN_Pos) /*!< 0x00400000 */ #define RCC_AHB5LPENR_ETH1MACLPEN RCC_AHB5LPENR_ETH1MACLPEN_Msk /*!< ETH1MAC enable */ #define RCC_AHB5LPENR_ETH1TXLPEN_Pos (23U) #define RCC_AHB5LPENR_ETH1TXLPEN_Msk (0x1UL << RCC_AHB5LPENR_ETH1TXLPEN_Pos) /*!< 0x00800000 */ #define RCC_AHB5LPENR_ETH1TXLPEN RCC_AHB5LPENR_ETH1TXLPEN_Msk /*!< ETH1TX enable */ #define RCC_AHB5LPENR_ETH1RXLPEN_Pos (24U) #define RCC_AHB5LPENR_ETH1RXLPEN_Msk (0x1UL << RCC_AHB5LPENR_ETH1RXLPEN_Pos) /*!< 0x01000000 */ #define RCC_AHB5LPENR_ETH1RXLPEN RCC_AHB5LPENR_ETH1RXLPEN_Msk /*!< ETH1RX enable */ #define RCC_AHB5LPENR_ETH1LPEN_Pos (25U) #define RCC_AHB5LPENR_ETH1LPEN_Msk (0x1UL << RCC_AHB5LPENR_ETH1LPEN_Pos) /*!< 0x02000000 */ #define RCC_AHB5LPENR_ETH1LPEN RCC_AHB5LPENR_ETH1LPEN_Msk /*!< ETH1 enable */ #define RCC_AHB5LPENR_OTG1LPEN_Pos (26U) #define RCC_AHB5LPENR_OTG1LPEN_Msk (0x1UL << RCC_AHB5LPENR_OTG1LPEN_Pos) /*!< 0x04000000 */ #define RCC_AHB5LPENR_OTG1LPEN RCC_AHB5LPENR_OTG1LPEN_Msk /*!< OTG1 enable */ #define RCC_AHB5LPENR_OTGPHY1LPEN_Pos (27U) #define RCC_AHB5LPENR_OTGPHY1LPEN_Msk (0x1UL << RCC_AHB5LPENR_OTGPHY1LPEN_Pos) /*!< 0x08000000 */ #define RCC_AHB5LPENR_OTGPHY1LPEN RCC_AHB5LPENR_OTGPHY1LPEN_Msk /*!< OTGPHY1 enable */ #define RCC_AHB5LPENR_OTGPHY2LPEN_Pos (28U) #define RCC_AHB5LPENR_OTGPHY2LPEN_Msk (0x1UL << RCC_AHB5LPENR_OTGPHY2LPEN_Pos) /*!< 0x10000000 */ #define RCC_AHB5LPENR_OTGPHY2LPEN RCC_AHB5LPENR_OTGPHY2LPEN_Msk /*!< OTGPHY2 enable */ #define RCC_AHB5LPENR_OTG2LPEN_Pos (29U) #define RCC_AHB5LPENR_OTG2LPEN_Msk (0x1UL << RCC_AHB5LPENR_OTG2LPEN_Pos) /*!< 0x20000000 */ #define RCC_AHB5LPENR_OTG2LPEN RCC_AHB5LPENR_OTG2LPEN_Msk /*!< OTG2 enable */ #define RCC_AHB5LPENR_CACHEAXILPEN_Pos (30U) #define RCC_AHB5LPENR_CACHEAXILPEN_Msk (0x1UL << RCC_AHB5LPENR_CACHEAXILPEN_Pos) /*!< 0x40000000 */ #define RCC_AHB5LPENR_CACHEAXILPEN RCC_AHB5LPENR_CACHEAXILPEN_Msk /*!< CACHEAXI enable */ #define RCC_AHB5LPENR_NPULPEN_Pos (31U) #define RCC_AHB5LPENR_NPULPEN_Msk (0x1UL << RCC_AHB5LPENR_NPULPEN_Pos) /*!< 0x80000000 */ #define RCC_AHB5LPENR_NPULPEN RCC_AHB5LPENR_NPULPEN_Msk /*!< NPU enable */ /**************** Bit definition for RCC_APB1LPENR1 register ****************/ #define RCC_APB1LPENR1_TIM2LPEN_Pos (0U) #define RCC_APB1LPENR1_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM2LPEN_Pos)/*!< 0x00000001 */ #define RCC_APB1LPENR1_TIM2LPEN RCC_APB1LPENR1_TIM2LPEN_Msk /*!< TIM2 enable */ #define RCC_APB1LPENR1_TIM3LPEN_Pos (1U) #define RCC_APB1LPENR1_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM3LPEN_Pos)/*!< 0x00000002 */ #define RCC_APB1LPENR1_TIM3LPEN RCC_APB1LPENR1_TIM3LPEN_Msk /*!< TIM3 enable */ #define RCC_APB1LPENR1_TIM4LPEN_Pos (2U) #define RCC_APB1LPENR1_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM4LPEN_Pos)/*!< 0x00000004 */ #define RCC_APB1LPENR1_TIM4LPEN RCC_APB1LPENR1_TIM4LPEN_Msk /*!< TIM4 enable */ #define RCC_APB1LPENR1_TIM5LPEN_Pos (3U) #define RCC_APB1LPENR1_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM5LPEN_Pos)/*!< 0x00000008 */ #define RCC_APB1LPENR1_TIM5LPEN RCC_APB1LPENR1_TIM5LPEN_Msk /*!< TIM5 enable */ #define RCC_APB1LPENR1_TIM6LPEN_Pos (4U) #define RCC_APB1LPENR1_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM6LPEN_Pos)/*!< 0x00000010 */ #define RCC_APB1LPENR1_TIM6LPEN RCC_APB1LPENR1_TIM6LPEN_Msk /*!< TIM6 enable */ #define RCC_APB1LPENR1_TIM7LPEN_Pos (5U) #define RCC_APB1LPENR1_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM7LPEN_Pos)/*!< 0x00000020 */ #define RCC_APB1LPENR1_TIM7LPEN RCC_APB1LPENR1_TIM7LPEN_Msk /*!< TIM7 enable */ #define RCC_APB1LPENR1_TIM12LPEN_Pos (6U) #define RCC_APB1LPENR1_TIM12LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM12LPEN_Pos) /*!< 0x00000040 */ #define RCC_APB1LPENR1_TIM12LPEN RCC_APB1LPENR1_TIM12LPEN_Msk /*!< TIM12 enable */ #define RCC_APB1LPENR1_TIM13LPEN_Pos (7U) #define RCC_APB1LPENR1_TIM13LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM13LPEN_Pos) /*!< 0x00000080 */ #define RCC_APB1LPENR1_TIM13LPEN RCC_APB1LPENR1_TIM13LPEN_Msk /*!< TIM13 enable */ #define RCC_APB1LPENR1_TIM14LPEN_Pos (8U) #define RCC_APB1LPENR1_TIM14LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM14LPEN_Pos) /*!< 0x00000100 */ #define RCC_APB1LPENR1_TIM14LPEN RCC_APB1LPENR1_TIM14LPEN_Msk /*!< TIM14 enable */ #define RCC_APB1LPENR1_LPTIM1LPEN_Pos (9U) #define RCC_APB1LPENR1_LPTIM1LPEN_Msk (0x1UL << RCC_APB1LPENR1_LPTIM1LPEN_Pos) /*!< 0x00000200 */ #define RCC_APB1LPENR1_LPTIM1LPEN RCC_APB1LPENR1_LPTIM1LPEN_Msk /*!< LPTIM1 enable */ #define RCC_APB1LPENR1_WWDGLPEN_Pos (11U) #define RCC_APB1LPENR1_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR1_WWDGLPEN_Pos)/*!< 0x00000800 */ #define RCC_APB1LPENR1_WWDGLPEN RCC_APB1LPENR1_WWDGLPEN_Msk /*!< WWDG enable */ #define RCC_APB1LPENR1_TIM10LPEN_Pos (12U) #define RCC_APB1LPENR1_TIM10LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM10LPEN_Pos) /*!< 0x00001000 */ #define RCC_APB1LPENR1_TIM10LPEN RCC_APB1LPENR1_TIM10LPEN_Msk /*!< TIM10 enable */ #define RCC_APB1LPENR1_TIM11LPEN_Pos (13U) #define RCC_APB1LPENR1_TIM11LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM11LPEN_Pos) /*!< 0x00002000 */ #define RCC_APB1LPENR1_TIM11LPEN RCC_APB1LPENR1_TIM11LPEN_Msk /*!< TIM11 enable */ #define RCC_APB1LPENR1_SPI2LPEN_Pos (14U) #define RCC_APB1LPENR1_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR1_SPI2LPEN_Pos)/*!< 0x00004000 */ #define RCC_APB1LPENR1_SPI2LPEN RCC_APB1LPENR1_SPI2LPEN_Msk /*!< SPI2 enable */ #define RCC_APB1LPENR1_SPI3LPEN_Pos (15U) #define RCC_APB1LPENR1_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR1_SPI3LPEN_Pos)/*!< 0x00008000 */ #define RCC_APB1LPENR1_SPI3LPEN RCC_APB1LPENR1_SPI3LPEN_Msk /*!< SPI3 enable */ #define RCC_APB1LPENR1_SPDIFRX1LPEN_Pos (16U) #define RCC_APB1LPENR1_SPDIFRX1LPEN_Msk (0x1UL << RCC_APB1LPENR1_SPDIFRX1LPEN_Pos) /*!< 0x00010000 */ #define RCC_APB1LPENR1_SPDIFRX1LPEN RCC_APB1LPENR1_SPDIFRX1LPEN_Msk /*!< SPDIFRX1 enable */ #define RCC_APB1LPENR1_USART2LPEN_Pos (17U) #define RCC_APB1LPENR1_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR1_USART2LPEN_Pos) /*!< 0x00020000 */ #define RCC_APB1LPENR1_USART2LPEN RCC_APB1LPENR1_USART2LPEN_Msk /*!< USART2 enable */ #define RCC_APB1LPENR1_USART3LPEN_Pos (18U) #define RCC_APB1LPENR1_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR1_USART3LPEN_Pos) /*!< 0x00040000 */ #define RCC_APB1LPENR1_USART3LPEN RCC_APB1LPENR1_USART3LPEN_Msk /*!< USART3 enable */ #define RCC_APB1LPENR1_UART4LPEN_Pos (19U) #define RCC_APB1LPENR1_UART4LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART4LPEN_Pos) /*!< 0x00080000 */ #define RCC_APB1LPENR1_UART4LPEN RCC_APB1LPENR1_UART4LPEN_Msk /*!< UART4 enable */ #define RCC_APB1LPENR1_UART5LPEN_Pos (20U) #define RCC_APB1LPENR1_UART5LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART5LPEN_Pos) /*!< 0x00100000 */ #define RCC_APB1LPENR1_UART5LPEN RCC_APB1LPENR1_UART5LPEN_Msk /*!< UART5 enable */ #define RCC_APB1LPENR1_I2C1LPEN_Pos (21U) #define RCC_APB1LPENR1_I2C1LPEN_Msk (0x1UL << RCC_APB1LPENR1_I2C1LPEN_Pos)/*!< 0x00200000 */ #define RCC_APB1LPENR1_I2C1LPEN RCC_APB1LPENR1_I2C1LPEN_Msk /*!< I2C1 enable */ #define RCC_APB1LPENR1_I2C2LPEN_Pos (22U) #define RCC_APB1LPENR1_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR1_I2C2LPEN_Pos)/*!< 0x00400000 */ #define RCC_APB1LPENR1_I2C2LPEN RCC_APB1LPENR1_I2C2LPEN_Msk /*!< I2C2 enable */ #define RCC_APB1LPENR1_I2C3LPEN_Pos (23U) #define RCC_APB1LPENR1_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR1_I2C3LPEN_Pos)/*!< 0x00800000 */ #define RCC_APB1LPENR1_I2C3LPEN RCC_APB1LPENR1_I2C3LPEN_Msk /*!< I2C3 enable */ #define RCC_APB1LPENR1_I3C1LPEN_Pos (24U) #define RCC_APB1LPENR1_I3C1LPEN_Msk (0x1UL << RCC_APB1LPENR1_I3C1LPEN_Pos)/*!< 0x01000000 */ #define RCC_APB1LPENR1_I3C1LPEN RCC_APB1LPENR1_I3C1LPEN_Msk /*!< I3C1 enable */ #define RCC_APB1LPENR1_I3C2LPEN_Pos (25U) #define RCC_APB1LPENR1_I3C2LPEN_Msk (0x1UL << RCC_APB1LPENR1_I3C2LPEN_Pos)/*!< 0x02000000 */ #define RCC_APB1LPENR1_I3C2LPEN RCC_APB1LPENR1_I3C2LPEN_Msk /*!< I3C2 enable */ #define RCC_APB1LPENR1_UART7LPEN_Pos (30U) #define RCC_APB1LPENR1_UART7LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART7LPEN_Pos) /*!< 0x40000000 */ #define RCC_APB1LPENR1_UART7LPEN RCC_APB1LPENR1_UART7LPEN_Msk /*!< UART7 enable */ #define RCC_APB1LPENR1_UART8LPEN_Pos (31U) #define RCC_APB1LPENR1_UART8LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART8LPEN_Pos) /*!< 0x80000000 */ #define RCC_APB1LPENR1_UART8LPEN RCC_APB1LPENR1_UART8LPEN_Msk /*!< UART8 enable */ /**************** Bit definition for RCC_APB1LPENR2 register ****************/ #define RCC_APB1LPENR2_MDIOSLPEN_Pos (5U) #define RCC_APB1LPENR2_MDIOSLPEN_Msk (0x1UL << RCC_APB1LPENR2_MDIOSLPEN_Pos) /*!< 0x00000020 */ #define RCC_APB1LPENR2_MDIOSLPEN RCC_APB1LPENR2_MDIOSLPEN_Msk /*!< MDIOS enable in Sleep mode */ #define RCC_APB1LPENR2_FDCANLPEN_Pos (8U) #define RCC_APB1LPENR2_FDCANLPEN_Msk (0x1UL << RCC_APB1LPENR2_FDCANLPEN_Pos) /*!< 0x00000100 */ #define RCC_APB1LPENR2_FDCANLPEN RCC_APB1LPENR2_FDCANLPEN_Msk /*!< FDCAN enablein Sleep mode */ #define RCC_APB1LPENR2_UCPD1LPEN_Pos (18U) #define RCC_APB1LPENR2_UCPD1LPEN_Msk (0x1UL << RCC_APB1LPENR2_UCPD1LPEN_Pos) /*!< 0x00040000 */ #define RCC_APB1LPENR2_UCPD1LPEN RCC_APB1LPENR2_UCPD1LPEN_Msk /*!< UCPD1 enable in Sleep mode */ /**************** Bit definition for RCC_APB2LPENR register *****************/ #define RCC_APB2LPENR_TIM1LPEN_Pos (0U) #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */ #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk /*!< TIM1 enable */ #define RCC_APB2LPENR_TIM8LPEN_Pos (1U) #define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */ #define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk /*!< TIM8 enable */ #define RCC_APB2LPENR_USART1LPEN_Pos (4U) #define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */ #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk /*!< USART1 enable */ #define RCC_APB2LPENR_USART6LPEN_Pos (5U) #define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */ #define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk /*!< USART6 enable */ #define RCC_APB2LPENR_UART9LPEN_Pos (6U) #define RCC_APB2LPENR_UART9LPEN_Msk (0x1UL << RCC_APB2LPENR_UART9LPEN_Pos)/*!< 0x00000040 */ #define RCC_APB2LPENR_UART9LPEN RCC_APB2LPENR_UART9LPEN_Msk /*!< UART9 enable */ #define RCC_APB2LPENR_USART10LPEN_Pos (7U) #define RCC_APB2LPENR_USART10LPEN_Msk (0x1UL << RCC_APB2LPENR_USART10LPEN_Pos) /*!< 0x00000080 */ #define RCC_APB2LPENR_USART10LPEN RCC_APB2LPENR_USART10LPEN_Msk /*!< USART10 enable */ #define RCC_APB2LPENR_SPI1LPEN_Pos (12U) #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */ #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk /*!< SPI1 enable */ #define RCC_APB2LPENR_SPI4LPEN_Pos (13U) #define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */ #define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk /*!< SPI4 enable */ #define RCC_APB2LPENR_TIM18LPEN_Pos (15U) #define RCC_APB2LPENR_TIM18LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM18LPEN_Pos)/*!< 0x00008000 */ #define RCC_APB2LPENR_TIM18LPEN RCC_APB2LPENR_TIM18LPEN_Msk /*!< TIM18 enable */ #define RCC_APB2LPENR_TIM15LPEN_Pos (16U) #define RCC_APB2LPENR_TIM15LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos)/*!< 0x00010000 */ #define RCC_APB2LPENR_TIM15LPEN RCC_APB2LPENR_TIM15LPEN_Msk /*!< TIM15 enable */ #define RCC_APB2LPENR_TIM16LPEN_Pos (17U) #define RCC_APB2LPENR_TIM16LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos)/*!< 0x00020000 */ #define RCC_APB2LPENR_TIM16LPEN RCC_APB2LPENR_TIM16LPEN_Msk /*!< TIM16 enable */ #define RCC_APB2LPENR_TIM17LPEN_Pos (18U) #define RCC_APB2LPENR_TIM17LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos)/*!< 0x00040000 */ #define RCC_APB2LPENR_TIM17LPEN RCC_APB2LPENR_TIM17LPEN_Msk /*!< TIM17 enable */ #define RCC_APB2LPENR_TIM9LPEN_Pos (19U) #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00080000 */ #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk /*!< TIM9 enable */ #define RCC_APB2LPENR_SPI5LPEN_Pos (20U) #define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */ #define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk /*!< SPI5 enable */ #define RCC_APB2LPENR_SAI1LPEN_Pos (21U) #define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00200000 */ #define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk /*!< SAI1 enable */ #define RCC_APB2LPENR_SAI2LPEN_Pos (22U) #define RCC_APB2LPENR_SAI2LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00400000 */ #define RCC_APB2LPENR_SAI2LPEN RCC_APB2LPENR_SAI2LPEN_Msk /*!< SAI2 enable */ /**************** Bit definition for RCC_APB3LPENR register *****************/ #define RCC_APB3LPENR_DFTLPEN_Pos (2U) #define RCC_APB3LPENR_DFTLPEN_Msk (0x1UL << RCC_APB3LPENR_DFTLPEN_Pos) /*!< 0x00000004 */ #define RCC_APB3LPENR_DFTLPEN RCC_APB3LPENR_DFTLPEN_Msk /*!< DFT enable */ /**************** Bit definition for RCC_APB4LPENR1 register ****************/ #define RCC_APB4LPENR1_HDPLPEN_Pos (2U) #define RCC_APB4LPENR1_HDPLPEN_Msk (0x1UL << RCC_APB4LPENR1_HDPLPEN_Pos) /*!< 0x00000004 */ #define RCC_APB4LPENR1_HDPLPEN RCC_APB4LPENR1_HDPLPEN_Msk /*!< HDP enable */ #define RCC_APB4LPENR1_LPUART1LPEN_Pos (3U) #define RCC_APB4LPENR1_LPUART1LPEN_Msk (0x1UL << RCC_APB4LPENR1_LPUART1LPEN_Pos) /*!< 0x00000008 */ #define RCC_APB4LPENR1_LPUART1LPEN RCC_APB4LPENR1_LPUART1LPEN_Msk /*!< LPUART1 enable */ #define RCC_APB4LPENR1_SPI6LPEN_Pos (5U) #define RCC_APB4LPENR1_SPI6LPEN_Msk (0x1UL << RCC_APB4LPENR1_SPI6LPEN_Pos)/*!< 0x00000020 */ #define RCC_APB4LPENR1_SPI6LPEN RCC_APB4LPENR1_SPI6LPEN_Msk /*!< SPI6 enable */ #define RCC_APB4LPENR1_I2C4LPEN_Pos (7U) #define RCC_APB4LPENR1_I2C4LPEN_Msk (0x1UL << RCC_APB4LPENR1_I2C4LPEN_Pos)/*!< 0x00000080 */ #define RCC_APB4LPENR1_I2C4LPEN RCC_APB4LPENR1_I2C4LPEN_Msk /*!< I2C4 enable */ #define RCC_APB4LPENR1_LPTIM2LPEN_Pos (9U) #define RCC_APB4LPENR1_LPTIM2LPEN_Msk (0x1UL << RCC_APB4LPENR1_LPTIM2LPEN_Pos) /*!< 0x00000200 */ #define RCC_APB4LPENR1_LPTIM2LPEN RCC_APB4LPENR1_LPTIM2LPEN_Msk /*!< LPTIM2 enable */ #define RCC_APB4LPENR1_LPTIM3LPEN_Pos (10U) #define RCC_APB4LPENR1_LPTIM3LPEN_Msk (0x1UL << RCC_APB4LPENR1_LPTIM3LPEN_Pos) /*!< 0x00000400 */ #define RCC_APB4LPENR1_LPTIM3LPEN RCC_APB4LPENR1_LPTIM3LPEN_Msk /*!< LPTIM3 enable */ #define RCC_APB4LPENR1_LPTIM4LPEN_Pos (11U) #define RCC_APB4LPENR1_LPTIM4LPEN_Msk (0x1UL << RCC_APB4LPENR1_LPTIM4LPEN_Pos) /*!< 0x00000800 */ #define RCC_APB4LPENR1_LPTIM4LPEN RCC_APB4LPENR1_LPTIM4LPEN_Msk /*!< LPTIM4 enable */ #define RCC_APB4LPENR1_LPTIM5LPEN_Pos (12U) #define RCC_APB4LPENR1_LPTIM5LPEN_Msk (0x1UL << RCC_APB4LPENR1_LPTIM5LPEN_Pos) /*!< 0x00001000 */ #define RCC_APB4LPENR1_LPTIM5LPEN RCC_APB4LPENR1_LPTIM5LPEN_Msk /*!< LPTIM5 enable */ #define RCC_APB4LPENR1_VREFBUFLPEN_Pos (15U) #define RCC_APB4LPENR1_VREFBUFLPEN_Msk (0x1UL << RCC_APB4LPENR1_VREFBUFLPEN_Pos) /*!< 0x00008000 */ #define RCC_APB4LPENR1_VREFBUFLPEN RCC_APB4LPENR1_VREFBUFLPEN_Msk /*!< VREFBUF enable */ #define RCC_APB4LPENR1_RTCLPEN_Pos (16U) #define RCC_APB4LPENR1_RTCLPEN_Msk (0x1UL << RCC_APB4LPENR1_RTCLPEN_Pos) /*!< 0x00010000 */ #define RCC_APB4LPENR1_RTCLPEN RCC_APB4LPENR1_RTCLPEN_Msk /*!< RTC enable */ #define RCC_APB4LPENR1_RTCAPBLPEN_Pos (17U) #define RCC_APB4LPENR1_RTCAPBLPEN_Msk (0x1UL << RCC_APB4LPENR1_RTCAPBLPEN_Pos) /*!< 0x00020000 */ #define RCC_APB4LPENR1_RTCAPBLPEN RCC_APB4LPENR1_RTCAPBLPEN_Msk /*!< RTCAPB enable */ /**************** Bit definition for RCC_APB4LPENR2 register ****************/ #define RCC_APB4LPENR2_SYSCFGLPEN_Pos (0U) #define RCC_APB4LPENR2_SYSCFGLPEN_Msk (0x1UL << RCC_APB4LPENR2_SYSCFGLPEN_Pos) /*!< 0x00000001 */ #define RCC_APB4LPENR2_SYSCFGLPEN RCC_APB4LPENR2_SYSCFGLPEN_Msk /*!< SYSCFG enable */ #define RCC_APB4LPENR2_BSECLPEN_Pos (1U) #define RCC_APB4LPENR2_BSECLPEN_Msk (0x1UL << RCC_APB4LPENR2_BSECLPEN_Pos)/*!< 0x00000002 */ #define RCC_APB4LPENR2_BSECLPEN RCC_APB4LPENR2_BSECLPEN_Msk /*!< BSEC enable */ #define RCC_APB4LPENR2_DTSLPEN_Pos (2U) #define RCC_APB4LPENR2_DTSLPEN_Msk (0x1UL << RCC_APB4LPENR2_DTSLPEN_Pos) /*!< 0x00000004 */ #define RCC_APB4LPENR2_DTSLPEN RCC_APB4LPENR2_DTSLPEN_Msk /*!< DTS enable */ /**************** Bit definition for RCC_APB5LPENR register *****************/ #define RCC_APB5LPENR_LTDCLPEN_Pos (1U) #define RCC_APB5LPENR_LTDCLPEN_Msk (0x1UL << RCC_APB5LPENR_LTDCLPEN_Pos) /*!< 0x00000002 */ #define RCC_APB5LPENR_LTDCLPEN RCC_APB5LPENR_LTDCLPEN_Msk /*!< LTDC enable */ #define RCC_APB5LPENR_DCMIPPLPEN_Pos (2U) #define RCC_APB5LPENR_DCMIPPLPEN_Msk (0x1UL << RCC_APB5LPENR_DCMIPPLPEN_Pos) /*!< 0x00000004 */ #define RCC_APB5LPENR_DCMIPPLPEN RCC_APB5LPENR_DCMIPPLPEN_Msk /*!< DCMIPP enable */ #define RCC_APB5LPENR_GFXTIMLPEN_Pos (4U) #define RCC_APB5LPENR_GFXTIMLPEN_Msk (0x1UL << RCC_APB5LPENR_GFXTIMLPEN_Pos) /*!< 0x00000010 */ #define RCC_APB5LPENR_GFXTIMLPEN RCC_APB5LPENR_GFXTIMLPEN_Msk /*!< GFXTIM enable */ #define RCC_APB5LPENR_VENCLPEN_Pos (5U) #define RCC_APB5LPENR_VENCLPEN_Msk (0x1UL << RCC_APB5LPENR_VENCLPEN_Pos) /*!< 0x00000020 */ #define RCC_APB5LPENR_VENCLPEN RCC_APB5LPENR_VENCLPEN_Msk /*!< VENC enable */ #define RCC_APB5LPENR_CSILPEN_Pos (6U) #define RCC_APB5LPENR_CSILPEN_Msk (0x1UL << RCC_APB5LPENR_CSILPEN_Pos) /*!< 0x00000040 */ #define RCC_APB5LPENR_CSILPEN RCC_APB5LPENR_CSILPEN_Msk /*!< CSI enable */ /******************* Bit definition for RCC_RDCR register *******************/ #define RCC_RDCR_MRD_Pos (16U) #define RCC_RDCR_MRD_Msk (0x1FUL << RCC_RDCR_MRD_Pos) /*!< 0x001F0000 */ #define RCC_RDCR_MRD RCC_RDCR_MRD_Msk /*!< Minimum reset duration */ /***************** Bit definition for RCC_SECCFGR0 register *****************/ #define RCC_SECCFGR0_LSISEC_Pos (0U) #define RCC_SECCFGR0_LSISEC_Msk (0x1UL << RCC_SECCFGR0_LSISEC_Pos) /*!< 0x00000001 */ #define RCC_SECCFGR0_LSISEC RCC_SECCFGR0_LSISEC_Msk /*!< Secure protection of LSI oscillator configuration bits */ #define RCC_SECCFGR0_LSESEC_Pos (1U) #define RCC_SECCFGR0_LSESEC_Msk (0x1UL << RCC_SECCFGR0_LSESEC_Pos) /*!< 0x00000002 */ #define RCC_SECCFGR0_LSESEC RCC_SECCFGR0_LSESEC_Msk /*!< Secure protection of LSE oscillator configuration bits */ #define RCC_SECCFGR0_MSISEC_Pos (2U) #define RCC_SECCFGR0_MSISEC_Msk (0x1UL << RCC_SECCFGR0_MSISEC_Pos) /*!< 0x00000004 */ #define RCC_SECCFGR0_MSISEC RCC_SECCFGR0_MSISEC_Msk /*!< Secure protection of MSI oscillator configuration bits */ #define RCC_SECCFGR0_HSISEC_Pos (3U) #define RCC_SECCFGR0_HSISEC_Msk (0x1UL << RCC_SECCFGR0_HSISEC_Pos) /*!< 0x00000008 */ #define RCC_SECCFGR0_HSISEC RCC_SECCFGR0_HSISEC_Msk /*!< Secure protection of HSI oscillator configuration bits */ #define RCC_SECCFGR0_HSESEC_Pos (4U) #define RCC_SECCFGR0_HSESEC_Msk (0x1UL << RCC_SECCFGR0_HSESEC_Pos) /*!< 0x00000010 */ #define RCC_SECCFGR0_HSESEC RCC_SECCFGR0_HSESEC_Msk /*!< Secure protection of HSE oscillator configuration bits */ /**************** Bit definition for RCC_PRIVCFGR0 register *****************/ #define RCC_PRIVCFGR0_LSIPRIV_Pos (0U) #define RCC_PRIVCFGR0_LSIPRIV_Msk (0x1UL << RCC_PRIVCFGR0_LSIPRIV_Pos) /*!< 0x00000001 */ #define RCC_PRIVCFGR0_LSIPRIV RCC_PRIVCFGR0_LSIPRIV_Msk /*!< Privileged protection of LSI oscillator configuration bits */ #define RCC_PRIVCFGR0_LSEPRIV_Pos (1U) #define RCC_PRIVCFGR0_LSEPRIV_Msk (0x1UL << RCC_PRIVCFGR0_LSEPRIV_Pos) /*!< 0x00000002 */ #define RCC_PRIVCFGR0_LSEPRIV RCC_PRIVCFGR0_LSEPRIV_Msk /*!< Privileged protection of LSE oscillator configuration bits */ #define RCC_PRIVCFGR0_MSIPRIV_Pos (2U) #define RCC_PRIVCFGR0_MSIPRIV_Msk (0x1UL << RCC_PRIVCFGR0_MSIPRIV_Pos) /*!< 0x00000004 */ #define RCC_PRIVCFGR0_MSIPRIV RCC_PRIVCFGR0_MSIPRIV_Msk /*!< Privileged protection of MSI oscillator configuration bits */ #define RCC_PRIVCFGR0_HSIPRIV_Pos (3U) #define RCC_PRIVCFGR0_HSIPRIV_Msk (0x1UL << RCC_PRIVCFGR0_HSIPRIV_Pos) /*!< 0x00000008 */ #define RCC_PRIVCFGR0_HSIPRIV RCC_PRIVCFGR0_HSIPRIV_Msk /*!< Privileged protection of HSI oscillator configuration bits */ #define RCC_PRIVCFGR0_HSEPRIV_Pos (4U) #define RCC_PRIVCFGR0_HSEPRIV_Msk (0x1UL << RCC_PRIVCFGR0_HSEPRIV_Pos) /*!< 0x00000010 */ #define RCC_PRIVCFGR0_HSEPRIV RCC_PRIVCFGR0_HSEPRIV_Msk /*!< Privileged protection of HSE oscillator configuration bits */ /**************** Bit definition for RCC_LOCKCFGR0 register *****************/ #define RCC_LOCKCFGR0_LSILOCK_Pos (0U) #define RCC_LOCKCFGR0_LSILOCK_Msk (0x1UL << RCC_LOCKCFGR0_LSILOCK_Pos) /*!< 0x00000001 */ #define RCC_LOCKCFGR0_LSILOCK RCC_LOCKCFGR0_LSILOCK_Msk /*!< Locked protection of LSI oscillator configuration bits */ #define RCC_LOCKCFGR0_LSELOCK_Pos (1U) #define RCC_LOCKCFGR0_LSELOCK_Msk (0x1UL << RCC_LOCKCFGR0_LSELOCK_Pos) /*!< 0x00000002 */ #define RCC_LOCKCFGR0_LSELOCK RCC_LOCKCFGR0_LSELOCK_Msk /*!< Locked protection of LSE oscillator configuration bits */ #define RCC_LOCKCFGR0_MSILOCK_Pos (2U) #define RCC_LOCKCFGR0_MSILOCK_Msk (0x1UL << RCC_LOCKCFGR0_MSILOCK_Pos) /*!< 0x00000004 */ #define RCC_LOCKCFGR0_MSILOCK RCC_LOCKCFGR0_MSILOCK_Msk /*!< Locked protection of MSI oscillator configuration bits */ #define RCC_LOCKCFGR0_HSILOCK_Pos (3U) #define RCC_LOCKCFGR0_HSILOCK_Msk (0x1UL << RCC_LOCKCFGR0_HSILOCK_Pos) /*!< 0x00000008 */ #define RCC_LOCKCFGR0_HSILOCK RCC_LOCKCFGR0_HSILOCK_Msk /*!< Locked protection of HSI oscillator configuration bits */ #define RCC_LOCKCFGR0_HSELOCK_Pos (4U) #define RCC_LOCKCFGR0_HSELOCK_Msk (0x1UL << RCC_LOCKCFGR0_HSELOCK_Pos) /*!< 0x00000010 */ #define RCC_LOCKCFGR0_HSELOCK RCC_LOCKCFGR0_HSELOCK_Msk /*!< Locked protection of HSE oscillator configuration bits */ /***************** Bit definition for RCC_PUBCFGR0 register *****************/ #define RCC_PUBCFGR0_LSIPUB_Pos (0U) #define RCC_PUBCFGR0_LSIPUB_Msk (0x1UL << RCC_PUBCFGR0_LSIPUB_Pos) /*!< 0x00000001 */ #define RCC_PUBCFGR0_LSIPUB RCC_PUBCFGR0_LSIPUB_Msk /*!< Public protection of LSI oscillator configuration bits */ #define RCC_PUBCFGR0_LSEPUB_Pos (1U) #define RCC_PUBCFGR0_LSEPUB_Msk (0x1UL << RCC_PUBCFGR0_LSEPUB_Pos) /*!< 0x00000002 */ #define RCC_PUBCFGR0_LSEPUB RCC_PUBCFGR0_LSEPUB_Msk /*!< Public protection of LSE oscillator configuration bits */ #define RCC_PUBCFGR0_MSIPUB_Pos (2U) #define RCC_PUBCFGR0_MSIPUB_Msk (0x1UL << RCC_PUBCFGR0_MSIPUB_Pos) /*!< 0x00000004 */ #define RCC_PUBCFGR0_MSIPUB RCC_PUBCFGR0_MSIPUB_Msk /*!< Public protection of MSI oscillator configuration bits */ #define RCC_PUBCFGR0_HSIPUB_Pos (3U) #define RCC_PUBCFGR0_HSIPUB_Msk (0x1UL << RCC_PUBCFGR0_HSIPUB_Pos) /*!< 0x00000008 */ #define RCC_PUBCFGR0_HSIPUB RCC_PUBCFGR0_HSIPUB_Msk /*!< Public protection of HSI oscillator configuration bits */ #define RCC_PUBCFGR0_HSEPUB_Pos (4U) #define RCC_PUBCFGR0_HSEPUB_Msk (0x1UL << RCC_PUBCFGR0_HSEPUB_Pos) /*!< 0x00000010 */ #define RCC_PUBCFGR0_HSEPUB RCC_PUBCFGR0_HSEPUB_Msk /*!< Public protection of HSE oscillator configuration bits */ /***************** Bit definition for RCC_SECCFGR1 register *****************/ #define RCC_SECCFGR1_PLL1SEC_Pos (0U) #define RCC_SECCFGR1_PLL1SEC_Msk (0x1UL << RCC_SECCFGR1_PLL1SEC_Pos) /*!< 0x00000001 */ #define RCC_SECCFGR1_PLL1SEC RCC_SECCFGR1_PLL1SEC_Msk /*!< Secure protection of PLL1 configuration bits */ #define RCC_SECCFGR1_PLL2SEC_Pos (1U) #define RCC_SECCFGR1_PLL2SEC_Msk (0x1UL << RCC_SECCFGR1_PLL2SEC_Pos) /*!< 0x00000002 */ #define RCC_SECCFGR1_PLL2SEC RCC_SECCFGR1_PLL2SEC_Msk /*!< Secure protection of PLL2 configuration bits */ #define RCC_SECCFGR1_PLL3SEC_Pos (2U) #define RCC_SECCFGR1_PLL3SEC_Msk (0x1UL << RCC_SECCFGR1_PLL3SEC_Pos) /*!< 0x00000004 */ #define RCC_SECCFGR1_PLL3SEC RCC_SECCFGR1_PLL3SEC_Msk /*!< Secure protection of PLL3 configuration bits */ #define RCC_SECCFGR1_PLL4SEC_Pos (3U) #define RCC_SECCFGR1_PLL4SEC_Msk (0x1UL << RCC_SECCFGR1_PLL4SEC_Pos) /*!< 0x00000008 */ #define RCC_SECCFGR1_PLL4SEC RCC_SECCFGR1_PLL4SEC_Msk /*!< Secure protection of PLL4 configuration bits */ /**************** Bit definition for RCC_PRIVCFGR1 register *****************/ #define RCC_PRIVCFGR1_PLL1PRIV_Pos (0U) #define RCC_PRIVCFGR1_PLL1PRIV_Msk (0x1UL << RCC_PRIVCFGR1_PLL1PRIV_Pos) /*!< 0x00000001 */ #define RCC_PRIVCFGR1_PLL1PRIV RCC_PRIVCFGR1_PLL1PRIV_Msk /*!< Privileged protection of PLL1 configuration bits */ #define RCC_PRIVCFGR1_PLL2PRIV_Pos (1U) #define RCC_PRIVCFGR1_PLL2PRIV_Msk (0x1UL << RCC_PRIVCFGR1_PLL2PRIV_Pos) /*!< 0x00000002 */ #define RCC_PRIVCFGR1_PLL2PRIV RCC_PRIVCFGR1_PLL2PRIV_Msk /*!< Privileged protection of PLL2 configuration bits */ #define RCC_PRIVCFGR1_PLL3PRIV_Pos (2U) #define RCC_PRIVCFGR1_PLL3PRIV_Msk (0x1UL << RCC_PRIVCFGR1_PLL3PRIV_Pos) /*!< 0x00000004 */ #define RCC_PRIVCFGR1_PLL3PRIV RCC_PRIVCFGR1_PLL3PRIV_Msk /*!< Privileged protection of PLL3 configuration bits */ #define RCC_PRIVCFGR1_PLL4PRIV_Pos (3U) #define RCC_PRIVCFGR1_PLL4PRIV_Msk (0x1UL << RCC_PRIVCFGR1_PLL4PRIV_Pos) /*!< 0x00000008 */ #define RCC_PRIVCFGR1_PLL4PRIV RCC_PRIVCFGR1_PLL4PRIV_Msk /*!< Privileged protection of PLL4 configuration bits */ /**************** Bit definition for RCC_LOCKCFGR1 register *****************/ #define RCC_LOCKCFGR1_PLL1LOCK_Pos (0U) #define RCC_LOCKCFGR1_PLL1LOCK_Msk (0x1UL << RCC_LOCKCFGR1_PLL1LOCK_Pos) /*!< 0x00000001 */ #define RCC_LOCKCFGR1_PLL1LOCK RCC_LOCKCFGR1_PLL1LOCK_Msk /*!< Locked protection of PLL1 configuration bits */ #define RCC_LOCKCFGR1_PLL2LOCK_Pos (1U) #define RCC_LOCKCFGR1_PLL2LOCK_Msk (0x1UL << RCC_LOCKCFGR1_PLL2LOCK_Pos) /*!< 0x00000002 */ #define RCC_LOCKCFGR1_PLL2LOCK RCC_LOCKCFGR1_PLL2LOCK_Msk /*!< Locked protection of PLL2 configuration bits */ #define RCC_LOCKCFGR1_PLL3LOCK_Pos (2U) #define RCC_LOCKCFGR1_PLL3LOCK_Msk (0x1UL << RCC_LOCKCFGR1_PLL3LOCK_Pos) /*!< 0x00000004 */ #define RCC_LOCKCFGR1_PLL3LOCK RCC_LOCKCFGR1_PLL3LOCK_Msk /*!< Locked protection of PLL3 configuration bits */ #define RCC_LOCKCFGR1_PLL4LOCK_Pos (3U) #define RCC_LOCKCFGR1_PLL4LOCK_Msk (0x1UL << RCC_LOCKCFGR1_PLL4LOCK_Pos) /*!< 0x00000008 */ #define RCC_LOCKCFGR1_PLL4LOCK RCC_LOCKCFGR1_PLL4LOCK_Msk /*!< Locked protection of PLL4 configuration bits */ /***************** Bit definition for RCC_PUBCFGR1 register *****************/ #define RCC_PUBCFGR1_PLL1PUB_Pos (0U) #define RCC_PUBCFGR1_PLL1PUB_Msk (0x1UL << RCC_PUBCFGR1_PLL1PUB_Pos) /*!< 0x00000001 */ #define RCC_PUBCFGR1_PLL1PUB RCC_PUBCFGR1_PLL1PUB_Msk /*!< Public protection of PLL1 configuration bits */ #define RCC_PUBCFGR1_PLL2PUB_Pos (1U) #define RCC_PUBCFGR1_PLL2PUB_Msk (0x1UL << RCC_PUBCFGR1_PLL2PUB_Pos) /*!< 0x00000002 */ #define RCC_PUBCFGR1_PLL2PUB RCC_PUBCFGR1_PLL2PUB_Msk /*!< Public protection of PLL2 configuration bits */ #define RCC_PUBCFGR1_PLL3PUB_Pos (2U) #define RCC_PUBCFGR1_PLL3PUB_Msk (0x1UL << RCC_PUBCFGR1_PLL3PUB_Pos) /*!< 0x00000004 */ #define RCC_PUBCFGR1_PLL3PUB RCC_PUBCFGR1_PLL3PUB_Msk /*!< Public protection of PLL3 configuration bits */ #define RCC_PUBCFGR1_PLL4PUB_Pos (3U) #define RCC_PUBCFGR1_PLL4PUB_Msk (0x1UL << RCC_PUBCFGR1_PLL4PUB_Pos) /*!< 0x00000008 */ #define RCC_PUBCFGR1_PLL4PUB RCC_PUBCFGR1_PLL4PUB_Msk /*!< Public protection of PLL4 configuration bits */ /***************** Bit definition for RCC_SECCFGR2 register *****************/ #define RCC_SECCFGR2_IC1SEC_Pos (0U) #define RCC_SECCFGR2_IC1SEC_Msk (0x1UL << RCC_SECCFGR2_IC1SEC_Pos) /*!< 0x00000001 */ #define RCC_SECCFGR2_IC1SEC RCC_SECCFGR2_IC1SEC_Msk /*!< Secure protection of IC1 divider configuration bits */ #define RCC_SECCFGR2_IC2SEC_Pos (1U) #define RCC_SECCFGR2_IC2SEC_Msk (0x1UL << RCC_SECCFGR2_IC2SEC_Pos) /*!< 0x00000002 */ #define RCC_SECCFGR2_IC2SEC RCC_SECCFGR2_IC2SEC_Msk /*!< Secure protection of IC2 divider configuration bits */ #define RCC_SECCFGR2_IC3SEC_Pos (2U) #define RCC_SECCFGR2_IC3SEC_Msk (0x1UL << RCC_SECCFGR2_IC3SEC_Pos) /*!< 0x00000004 */ #define RCC_SECCFGR2_IC3SEC RCC_SECCFGR2_IC3SEC_Msk /*!< Secure protection of IC3 divider configuration bits */ #define RCC_SECCFGR2_IC4SEC_Pos (3U) #define RCC_SECCFGR2_IC4SEC_Msk (0x1UL << RCC_SECCFGR2_IC4SEC_Pos) /*!< 0x00000008 */ #define RCC_SECCFGR2_IC4SEC RCC_SECCFGR2_IC4SEC_Msk /*!< Secure protection of IC4 divider configuration bits */ #define RCC_SECCFGR2_IC5SEC_Pos (4U) #define RCC_SECCFGR2_IC5SEC_Msk (0x1UL << RCC_SECCFGR2_IC5SEC_Pos) /*!< 0x00000010 */ #define RCC_SECCFGR2_IC5SEC RCC_SECCFGR2_IC5SEC_Msk /*!< Secure protection of IC5 divider configuration bits */ #define RCC_SECCFGR2_IC6SEC_Pos (5U) #define RCC_SECCFGR2_IC6SEC_Msk (0x1UL << RCC_SECCFGR2_IC6SEC_Pos) /*!< 0x00000020 */ #define RCC_SECCFGR2_IC6SEC RCC_SECCFGR2_IC6SEC_Msk /*!< Secure protection of IC6 divider configuration bits */ #define RCC_SECCFGR2_IC7SEC_Pos (6U) #define RCC_SECCFGR2_IC7SEC_Msk (0x1UL << RCC_SECCFGR2_IC7SEC_Pos) /*!< 0x00000040 */ #define RCC_SECCFGR2_IC7SEC RCC_SECCFGR2_IC7SEC_Msk /*!< Secure protection of IC7 divider configuration bits */ #define RCC_SECCFGR2_IC8SEC_Pos (7U) #define RCC_SECCFGR2_IC8SEC_Msk (0x1UL << RCC_SECCFGR2_IC8SEC_Pos) /*!< 0x00000080 */ #define RCC_SECCFGR2_IC8SEC RCC_SECCFGR2_IC8SEC_Msk /*!< Secure protection of IC8 divider configuration bits */ #define RCC_SECCFGR2_IC9SEC_Pos (8U) #define RCC_SECCFGR2_IC9SEC_Msk (0x1UL << RCC_SECCFGR2_IC9SEC_Pos) /*!< 0x00000100 */ #define RCC_SECCFGR2_IC9SEC RCC_SECCFGR2_IC9SEC_Msk /*!< Secure protection of IC9 divider configuration bits */ #define RCC_SECCFGR2_IC10SEC_Pos (9U) #define RCC_SECCFGR2_IC10SEC_Msk (0x1UL << RCC_SECCFGR2_IC10SEC_Pos) /*!< 0x00000200 */ #define RCC_SECCFGR2_IC10SEC RCC_SECCFGR2_IC10SEC_Msk /*!< Secure protection of IC10 divider configuration bits */ #define RCC_SECCFGR2_IC11SEC_Pos (10U) #define RCC_SECCFGR2_IC11SEC_Msk (0x1UL << RCC_SECCFGR2_IC11SEC_Pos) /*!< 0x00000400 */ #define RCC_SECCFGR2_IC11SEC RCC_SECCFGR2_IC11SEC_Msk /*!< Secure protection of IC11 divider configuration bits */ #define RCC_SECCFGR2_IC12SEC_Pos (11U) #define RCC_SECCFGR2_IC12SEC_Msk (0x1UL << RCC_SECCFGR2_IC12SEC_Pos) /*!< 0x00000800 */ #define RCC_SECCFGR2_IC12SEC RCC_SECCFGR2_IC12SEC_Msk /*!< Secure protection of IC12 divider configuration bits */ #define RCC_SECCFGR2_IC13SEC_Pos (12U) #define RCC_SECCFGR2_IC13SEC_Msk (0x1UL << RCC_SECCFGR2_IC13SEC_Pos) /*!< 0x00001000 */ #define RCC_SECCFGR2_IC13SEC RCC_SECCFGR2_IC13SEC_Msk /*!< Secure protection of IC13 divider configuration bits */ #define RCC_SECCFGR2_IC14SEC_Pos (13U) #define RCC_SECCFGR2_IC14SEC_Msk (0x1UL << RCC_SECCFGR2_IC14SEC_Pos) /*!< 0x00002000 */ #define RCC_SECCFGR2_IC14SEC RCC_SECCFGR2_IC14SEC_Msk /*!< Secure protection of IC14 divider configuration bits */ #define RCC_SECCFGR2_IC15SEC_Pos (14U) #define RCC_SECCFGR2_IC15SEC_Msk (0x1UL << RCC_SECCFGR2_IC15SEC_Pos) /*!< 0x00004000 */ #define RCC_SECCFGR2_IC15SEC RCC_SECCFGR2_IC15SEC_Msk /*!< Secure protection of IC15 divider configuration bits */ #define RCC_SECCFGR2_IC16SEC_Pos (15U) #define RCC_SECCFGR2_IC16SEC_Msk (0x1UL << RCC_SECCFGR2_IC16SEC_Pos) /*!< 0x00008000 */ #define RCC_SECCFGR2_IC16SEC RCC_SECCFGR2_IC16SEC_Msk /*!< Secure protection of IC16 divider configuration bits */ #define RCC_SECCFGR2_IC17SEC_Pos (16U) #define RCC_SECCFGR2_IC17SEC_Msk (0x1UL << RCC_SECCFGR2_IC17SEC_Pos) /*!< 0x00010000 */ #define RCC_SECCFGR2_IC17SEC RCC_SECCFGR2_IC17SEC_Msk /*!< Secure protection of IC17 divider configuration bits */ #define RCC_SECCFGR2_IC18SEC_Pos (17U) #define RCC_SECCFGR2_IC18SEC_Msk (0x1UL << RCC_SECCFGR2_IC18SEC_Pos) /*!< 0x00020000 */ #define RCC_SECCFGR2_IC18SEC RCC_SECCFGR2_IC18SEC_Msk /*!< Secure protection of IC18 divider configuration bits */ #define RCC_SECCFGR2_IC19SEC_Pos (18U) #define RCC_SECCFGR2_IC19SEC_Msk (0x1UL << RCC_SECCFGR2_IC19SEC_Pos) /*!< 0x00040000 */ #define RCC_SECCFGR2_IC19SEC RCC_SECCFGR2_IC19SEC_Msk /*!< Secure protection of IC19 divider configuration bits */ #define RCC_SECCFGR2_IC20SEC_Pos (19U) #define RCC_SECCFGR2_IC20SEC_Msk (0x1UL << RCC_SECCFGR2_IC20SEC_Pos) /*!< 0x00080000 */ #define RCC_SECCFGR2_IC20SEC RCC_SECCFGR2_IC20SEC_Msk /*!< Secure protection of IC20 divider configuration bits */ /**************** Bit definition for RCC_PRIVCFGR2 register *****************/ #define RCC_PRIVCFGR2_IC1PRIV_Pos (0U) #define RCC_PRIVCFGR2_IC1PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC1PRIV_Pos) /*!< 0x00000001 */ #define RCC_PRIVCFGR2_IC1PRIV RCC_PRIVCFGR2_IC1PRIV_Msk /*!< Privileged protection of IC1 divider configuration bits */ #define RCC_PRIVCFGR2_IC2PRIV_Pos (1U) #define RCC_PRIVCFGR2_IC2PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC2PRIV_Pos) /*!< 0x00000002 */ #define RCC_PRIVCFGR2_IC2PRIV RCC_PRIVCFGR2_IC2PRIV_Msk /*!< Privileged protection of IC2 divider configuration bits */ #define RCC_PRIVCFGR2_IC3PRIV_Pos (2U) #define RCC_PRIVCFGR2_IC3PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC3PRIV_Pos) /*!< 0x00000004 */ #define RCC_PRIVCFGR2_IC3PRIV RCC_PRIVCFGR2_IC3PRIV_Msk /*!< Privileged protection of IC3 divider configuration bits */ #define RCC_PRIVCFGR2_IC4PRIV_Pos (3U) #define RCC_PRIVCFGR2_IC4PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC4PRIV_Pos) /*!< 0x00000008 */ #define RCC_PRIVCFGR2_IC4PRIV RCC_PRIVCFGR2_IC4PRIV_Msk /*!< Privileged protection of IC4 divider configuration bits */ #define RCC_PRIVCFGR2_IC5PRIV_Pos (4U) #define RCC_PRIVCFGR2_IC5PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC5PRIV_Pos) /*!< 0x00000010 */ #define RCC_PRIVCFGR2_IC5PRIV RCC_PRIVCFGR2_IC5PRIV_Msk /*!< Privileged protection of IC5 divider configuration bits */ #define RCC_PRIVCFGR2_IC6PRIV_Pos (5U) #define RCC_PRIVCFGR2_IC6PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC6PRIV_Pos) /*!< 0x00000020 */ #define RCC_PRIVCFGR2_IC6PRIV RCC_PRIVCFGR2_IC6PRIV_Msk /*!< Privileged protection of IC6 divider configuration bits */ #define RCC_PRIVCFGR2_IC7PRIV_Pos (6U) #define RCC_PRIVCFGR2_IC7PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC7PRIV_Pos) /*!< 0x00000040 */ #define RCC_PRIVCFGR2_IC7PRIV RCC_PRIVCFGR2_IC7PRIV_Msk /*!< Privileged protection of IC7 divider configuration bits */ #define RCC_PRIVCFGR2_IC8PRIV_Pos (7U) #define RCC_PRIVCFGR2_IC8PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC8PRIV_Pos) /*!< 0x00000080 */ #define RCC_PRIVCFGR2_IC8PRIV RCC_PRIVCFGR2_IC8PRIV_Msk /*!< Privileged protection of IC8 divider configuration bits */ #define RCC_PRIVCFGR2_IC9PRIV_Pos (8U) #define RCC_PRIVCFGR2_IC9PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC9PRIV_Pos) /*!< 0x00000100 */ #define RCC_PRIVCFGR2_IC9PRIV RCC_PRIVCFGR2_IC9PRIV_Msk /*!< Privileged protection of IC9 divider configuration bits */ #define RCC_PRIVCFGR2_IC10PRIV_Pos (9U) #define RCC_PRIVCFGR2_IC10PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC10PRIV_Pos) /*!< 0x00000200 */ #define RCC_PRIVCFGR2_IC10PRIV RCC_PRIVCFGR2_IC10PRIV_Msk /*!< Privileged protection of IC10 divider configuration bits */ #define RCC_PRIVCFGR2_IC11PRIV_Pos (10U) #define RCC_PRIVCFGR2_IC11PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC11PRIV_Pos) /*!< 0x00000400 */ #define RCC_PRIVCFGR2_IC11PRIV RCC_PRIVCFGR2_IC11PRIV_Msk /*!< Privileged protection of IC11 divider configuration bits */ #define RCC_PRIVCFGR2_IC12PRIV_Pos (11U) #define RCC_PRIVCFGR2_IC12PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC12PRIV_Pos) /*!< 0x00000800 */ #define RCC_PRIVCFGR2_IC12PRIV RCC_PRIVCFGR2_IC12PRIV_Msk /*!< Privileged protection of IC12 divider configuration bits */ #define RCC_PRIVCFGR2_IC13PRIV_Pos (12U) #define RCC_PRIVCFGR2_IC13PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC13PRIV_Pos) /*!< 0x00001000 */ #define RCC_PRIVCFGR2_IC13PRIV RCC_PRIVCFGR2_IC13PRIV_Msk /*!< Privileged protection of IC13 divider configuration bits */ #define RCC_PRIVCFGR2_IC14PRIV_Pos (13U) #define RCC_PRIVCFGR2_IC14PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC14PRIV_Pos) /*!< 0x00002000 */ #define RCC_PRIVCFGR2_IC14PRIV RCC_PRIVCFGR2_IC14PRIV_Msk /*!< Privileged protection of IC14 divider configuration bits */ #define RCC_PRIVCFGR2_IC15PRIV_Pos (14U) #define RCC_PRIVCFGR2_IC15PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC15PRIV_Pos) /*!< 0x00004000 */ #define RCC_PRIVCFGR2_IC15PRIV RCC_PRIVCFGR2_IC15PRIV_Msk /*!< Privileged protection of IC15 divider configuration bits */ #define RCC_PRIVCFGR2_IC16PRIV_Pos (15U) #define RCC_PRIVCFGR2_IC16PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC16PRIV_Pos) /*!< 0x00008000 */ #define RCC_PRIVCFGR2_IC16PRIV RCC_PRIVCFGR2_IC16PRIV_Msk /*!< Privileged protection of IC16 divider configuration bits */ #define RCC_PRIVCFGR2_IC17PRIV_Pos (16U) #define RCC_PRIVCFGR2_IC17PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC17PRIV_Pos) /*!< 0x00010000 */ #define RCC_PRIVCFGR2_IC17PRIV RCC_PRIVCFGR2_IC17PRIV_Msk /*!< Privileges protection of IC17 divider configuration bits */ #define RCC_PRIVCFGR2_IC18PRIV_Pos (17U) #define RCC_PRIVCFGR2_IC18PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC18PRIV_Pos) /*!< 0x00020000 */ #define RCC_PRIVCFGR2_IC18PRIV RCC_PRIVCFGR2_IC18PRIV_Msk /*!< Privilege protection of IC18 divider configuration bits */ #define RCC_PRIVCFGR2_IC19PRIV_Pos (18U) #define RCC_PRIVCFGR2_IC19PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC19PRIV_Pos) /*!< 0x00040000 */ #define RCC_PRIVCFGR2_IC19PRIV RCC_PRIVCFGR2_IC19PRIV_Msk /*!< Privileged protection of IC19 divider configuration bits */ #define RCC_PRIVCFGR2_IC20PRIV_Pos (19U) #define RCC_PRIVCFGR2_IC20PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC20PRIV_Pos) /*!< 0x00080000 */ #define RCC_PRIVCFGR2_IC20PRIV RCC_PRIVCFGR2_IC20PRIV_Msk /*!< Privileged protection of IC20 divider configuration bits */ /**************** Bit definition for RCC_LOCKCFGR2 register *****************/ #define RCC_LOCKCFGR2_IC1LOCK_Pos (0U) #define RCC_LOCKCFGR2_IC1LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC1LOCK_Pos) /*!< 0x00000001 */ #define RCC_LOCKCFGR2_IC1LOCK RCC_LOCKCFGR2_IC1LOCK_Msk /*!< Locked protection of IC1 divider configuration bits */ #define RCC_LOCKCFGR2_IC2LOCK_Pos (1U) #define RCC_LOCKCFGR2_IC2LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC2LOCK_Pos) /*!< 0x00000002 */ #define RCC_LOCKCFGR2_IC2LOCK RCC_LOCKCFGR2_IC2LOCK_Msk /*!< Locked protection of IC2 divider configuration bits */ #define RCC_LOCKCFGR2_IC3LOCK_Pos (2U) #define RCC_LOCKCFGR2_IC3LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC3LOCK_Pos) /*!< 0x00000004 */ #define RCC_LOCKCFGR2_IC3LOCK RCC_LOCKCFGR2_IC3LOCK_Msk /*!< Locked protection of IC3 divider configuration bits */ #define RCC_LOCKCFGR2_IC4LOCK_Pos (3U) #define RCC_LOCKCFGR2_IC4LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC4LOCK_Pos) /*!< 0x00000008 */ #define RCC_LOCKCFGR2_IC4LOCK RCC_LOCKCFGR2_IC4LOCK_Msk /*!< Locked protection of IC4 divider configuration bits */ #define RCC_LOCKCFGR2_IC5LOCK_Pos (4U) #define RCC_LOCKCFGR2_IC5LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC5LOCK_Pos) /*!< 0x00000010 */ #define RCC_LOCKCFGR2_IC5LOCK RCC_LOCKCFGR2_IC5LOCK_Msk /*!< Locked protection of IC5 divider configuration bits */ #define RCC_LOCKCFGR2_IC6LOCK_Pos (5U) #define RCC_LOCKCFGR2_IC6LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC6LOCK_Pos) /*!< 0x00000020 */ #define RCC_LOCKCFGR2_IC6LOCK RCC_LOCKCFGR2_IC6LOCK_Msk /*!< Locked protection of IC6 divider configuration bits */ #define RCC_LOCKCFGR2_IC7LOCK_Pos (6U) #define RCC_LOCKCFGR2_IC7LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC7LOCK_Pos) /*!< 0x00000040 */ #define RCC_LOCKCFGR2_IC7LOCK RCC_LOCKCFGR2_IC7LOCK_Msk /*!< Locked protection of IC7 divider configuration bits */ #define RCC_LOCKCFGR2_IC8LOCK_Pos (7U) #define RCC_LOCKCFGR2_IC8LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC8LOCK_Pos) /*!< 0x00000080 */ #define RCC_LOCKCFGR2_IC8LOCK RCC_LOCKCFGR2_IC8LOCK_Msk /*!< Locked protection of IC8 divider configuration bits */ #define RCC_LOCKCFGR2_IC9LOCK_Pos (8U) #define RCC_LOCKCFGR2_IC9LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC9LOCK_Pos) /*!< 0x00000100 */ #define RCC_LOCKCFGR2_IC9LOCK RCC_LOCKCFGR2_IC9LOCK_Msk /*!< Locked protection of IC9 divider configuration bits */ #define RCC_LOCKCFGR2_IC10LOCK_Pos (9U) #define RCC_LOCKCFGR2_IC10LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC10LOCK_Pos) /*!< 0x00000200 */ #define RCC_LOCKCFGR2_IC10LOCK RCC_LOCKCFGR2_IC10LOCK_Msk /*!< Locked protection of IC10 divider configuration bits */ #define RCC_LOCKCFGR2_IC11LOCK_Pos (10U) #define RCC_LOCKCFGR2_IC11LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC11LOCK_Pos) /*!< 0x00000400 */ #define RCC_LOCKCFGR2_IC11LOCK RCC_LOCKCFGR2_IC11LOCK_Msk /*!< Locked protection of IC11 divider configuration bits */ #define RCC_LOCKCFGR2_IC12LOCK_Pos (11U) #define RCC_LOCKCFGR2_IC12LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC12LOCK_Pos) /*!< 0x00000800 */ #define RCC_LOCKCFGR2_IC12LOCK RCC_LOCKCFGR2_IC12LOCK_Msk /*!< Locked protection of IC12 divider configuration bits */ #define RCC_LOCKCFGR2_IC13LOCK_Pos (12U) #define RCC_LOCKCFGR2_IC13LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC13LOCK_Pos) /*!< 0x00001000 */ #define RCC_LOCKCFGR2_IC13LOCK RCC_LOCKCFGR2_IC13LOCK_Msk /*!< Locked protection of IC13 divider configuration bits */ #define RCC_LOCKCFGR2_IC14LOCK_Pos (13U) #define RCC_LOCKCFGR2_IC14LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC14LOCK_Pos) /*!< 0x00002000 */ #define RCC_LOCKCFGR2_IC14LOCK RCC_LOCKCFGR2_IC14LOCK_Msk /*!< Locked protection of IC14 divider configuration bits */ #define RCC_LOCKCFGR2_IC15LOCK_Pos (14U) #define RCC_LOCKCFGR2_IC15LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC15LOCK_Pos) /*!< 0x00004000 */ #define RCC_LOCKCFGR2_IC15LOCK RCC_LOCKCFGR2_IC15LOCK_Msk /*!< Locked protection of IC15 divider configuration bits */ #define RCC_LOCKCFGR2_IC16LOCK_Pos (15U) #define RCC_LOCKCFGR2_IC16LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC16LOCK_Pos) /*!< 0x00008000 */ #define RCC_LOCKCFGR2_IC16LOCK RCC_LOCKCFGR2_IC16LOCK_Msk /*!< Locked protection of IC16 divider configuration bits */ #define RCC_LOCKCFGR2_IC17LOCK_Pos (16U) #define RCC_LOCKCFGR2_IC17LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC17LOCK_Pos) /*!< 0x00010000 */ #define RCC_LOCKCFGR2_IC17LOCK RCC_LOCKCFGR2_IC17LOCK_Msk /*!< Locked protection of IC17 divider configuration bits */ #define RCC_LOCKCFGR2_IC18LOCK_Pos (17U) #define RCC_LOCKCFGR2_IC18LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC18LOCK_Pos) /*!< 0x00020000 */ #define RCC_LOCKCFGR2_IC18LOCK RCC_LOCKCFGR2_IC18LOCK_Msk /*!< Locked protection of IC18 divider configuration bits */ #define RCC_LOCKCFGR2_IC19LOCK_Pos (18U) #define RCC_LOCKCFGR2_IC19LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC19LOCK_Pos) /*!< 0x00040000 */ #define RCC_LOCKCFGR2_IC19LOCK RCC_LOCKCFGR2_IC19LOCK_Msk /*!< Locked protection of IC19 divider configuration bits */ #define RCC_LOCKCFGR2_IC20LOCK_Pos (19U) #define RCC_LOCKCFGR2_IC20LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC20LOCK_Pos) /*!< 0x00080000 */ #define RCC_LOCKCFGR2_IC20LOCK RCC_LOCKCFGR2_IC20LOCK_Msk /*!< Locked protection of IC20 divider configuration bits */ /***************** Bit definition for RCC_PUBCFGR2 register *****************/ #define RCC_PUBCFGR2_IC1PUB_Pos (0U) #define RCC_PUBCFGR2_IC1PUB_Msk (0x1UL << RCC_PUBCFGR2_IC1PUB_Pos) /*!< 0x00000001 */ #define RCC_PUBCFGR2_IC1PUB RCC_PUBCFGR2_IC1PUB_Msk /*!< Public protection of IC1 divider configuration bits */ #define RCC_PUBCFGR2_IC2PUB_Pos (1U) #define RCC_PUBCFGR2_IC2PUB_Msk (0x1UL << RCC_PUBCFGR2_IC2PUB_Pos) /*!< 0x00000002 */ #define RCC_PUBCFGR2_IC2PUB RCC_PUBCFGR2_IC2PUB_Msk /*!< Public protection of IC2 divider configuration bits */ #define RCC_PUBCFGR2_IC3PUB_Pos (2U) #define RCC_PUBCFGR2_IC3PUB_Msk (0x1UL << RCC_PUBCFGR2_IC3PUB_Pos) /*!< 0x00000004 */ #define RCC_PUBCFGR2_IC3PUB RCC_PUBCFGR2_IC3PUB_Msk /*!< Public protection of IC3 divider configuration bits */ #define RCC_PUBCFGR2_IC4PUB_Pos (3U) #define RCC_PUBCFGR2_IC4PUB_Msk (0x1UL << RCC_PUBCFGR2_IC4PUB_Pos) /*!< 0x00000008 */ #define RCC_PUBCFGR2_IC4PUB RCC_PUBCFGR2_IC4PUB_Msk /*!< Public protection of IC4 divider configuration bits */ #define RCC_PUBCFGR2_IC5PUB_Pos (4U) #define RCC_PUBCFGR2_IC5PUB_Msk (0x1UL << RCC_PUBCFGR2_IC5PUB_Pos) /*!< 0x00000010 */ #define RCC_PUBCFGR2_IC5PUB RCC_PUBCFGR2_IC5PUB_Msk /*!< Public protection of IC5 divider configuration bits */ #define RCC_PUBCFGR2_IC6PUB_Pos (5U) #define RCC_PUBCFGR2_IC6PUB_Msk (0x1UL << RCC_PUBCFGR2_IC6PUB_Pos) /*!< 0x00000020 */ #define RCC_PUBCFGR2_IC6PUB RCC_PUBCFGR2_IC6PUB_Msk /*!< Public protection of IC6 divider configuration bits */ #define RCC_PUBCFGR2_IC7PUB_Pos (6U) #define RCC_PUBCFGR2_IC7PUB_Msk (0x1UL << RCC_PUBCFGR2_IC7PUB_Pos) /*!< 0x00000040 */ #define RCC_PUBCFGR2_IC7PUB RCC_PUBCFGR2_IC7PUB_Msk /*!< Public protection of IC7 divider configuration bits */ #define RCC_PUBCFGR2_IC8PUB_Pos (7U) #define RCC_PUBCFGR2_IC8PUB_Msk (0x1UL << RCC_PUBCFGR2_IC8PUB_Pos) /*!< 0x00000080 */ #define RCC_PUBCFGR2_IC8PUB RCC_PUBCFGR2_IC8PUB_Msk /*!< Public protection of IC8 divider configuration bits */ #define RCC_PUBCFGR2_IC9PUB_Pos (8U) #define RCC_PUBCFGR2_IC9PUB_Msk (0x1UL << RCC_PUBCFGR2_IC9PUB_Pos) /*!< 0x00000100 */ #define RCC_PUBCFGR2_IC9PUB RCC_PUBCFGR2_IC9PUB_Msk /*!< Public protection of IC9 divider configuration bits */ #define RCC_PUBCFGR2_IC10PUB_Pos (9U) #define RCC_PUBCFGR2_IC10PUB_Msk (0x1UL << RCC_PUBCFGR2_IC10PUB_Pos) /*!< 0x00000200 */ #define RCC_PUBCFGR2_IC10PUB RCC_PUBCFGR2_IC10PUB_Msk /*!< Public protection of IC10 divider configuration bits */ #define RCC_PUBCFGR2_IC11PUB_Pos (10U) #define RCC_PUBCFGR2_IC11PUB_Msk (0x1UL << RCC_PUBCFGR2_IC11PUB_Pos) /*!< 0x00000400 */ #define RCC_PUBCFGR2_IC11PUB RCC_PUBCFGR2_IC11PUB_Msk /*!< Public protection of IC11 divider configuration bits */ #define RCC_PUBCFGR2_IC12PUB_Pos (11U) #define RCC_PUBCFGR2_IC12PUB_Msk (0x1UL << RCC_PUBCFGR2_IC12PUB_Pos) /*!< 0x00000800 */ #define RCC_PUBCFGR2_IC12PUB RCC_PUBCFGR2_IC12PUB_Msk /*!< Public protection of IC12 divider configuration bits */ #define RCC_PUBCFGR2_IC13PUB_Pos (12U) #define RCC_PUBCFGR2_IC13PUB_Msk (0x1UL << RCC_PUBCFGR2_IC13PUB_Pos) /*!< 0x00001000 */ #define RCC_PUBCFGR2_IC13PUB RCC_PUBCFGR2_IC13PUB_Msk /*!< Public protection of IC13 divider configuration bits */ #define RCC_PUBCFGR2_IC14PUB_Pos (13U) #define RCC_PUBCFGR2_IC14PUB_Msk (0x1UL << RCC_PUBCFGR2_IC14PUB_Pos) /*!< 0x00002000 */ #define RCC_PUBCFGR2_IC14PUB RCC_PUBCFGR2_IC14PUB_Msk /*!< Public protection of IC14 divider configuration bits */ #define RCC_PUBCFGR2_IC15PUB_Pos (14U) #define RCC_PUBCFGR2_IC15PUB_Msk (0x1UL << RCC_PUBCFGR2_IC15PUB_Pos) /*!< 0x00004000 */ #define RCC_PUBCFGR2_IC15PUB RCC_PUBCFGR2_IC15PUB_Msk /*!< Public protection of IC15 divider configuration bits */ #define RCC_PUBCFGR2_IC16PUB_Pos (15U) #define RCC_PUBCFGR2_IC16PUB_Msk (0x1UL << RCC_PUBCFGR2_IC16PUB_Pos) /*!< 0x00008000 */ #define RCC_PUBCFGR2_IC16PUB RCC_PUBCFGR2_IC16PUB_Msk /*!< Public protection of IC16 divider configuration bits */ #define RCC_PUBCFGR2_IC17PUB_Pos (16U) #define RCC_PUBCFGR2_IC17PUB_Msk (0x1UL << RCC_PUBCFGR2_IC17PUB_Pos) /*!< 0x00010000 */ #define RCC_PUBCFGR2_IC17PUB RCC_PUBCFGR2_IC17PUB_Msk /*!< Public protection of IC17 divider configuration bits */ #define RCC_PUBCFGR2_IC18PUB_Pos (17U) #define RCC_PUBCFGR2_IC18PUB_Msk (0x1UL << RCC_PUBCFGR2_IC18PUB_Pos) /*!< 0x00020000 */ #define RCC_PUBCFGR2_IC18PUB RCC_PUBCFGR2_IC18PUB_Msk /*!< Public protection of IC18 divider configuration bits */ #define RCC_PUBCFGR2_IC19PUB_Pos (18U) #define RCC_PUBCFGR2_IC19PUB_Msk (0x1UL << RCC_PUBCFGR2_IC19PUB_Pos) /*!< 0x00040000 */ #define RCC_PUBCFGR2_IC19PUB RCC_PUBCFGR2_IC19PUB_Msk /*!< Public protection of IC19 divider configuration bits */ #define RCC_PUBCFGR2_IC20PUB_Pos (19U) #define RCC_PUBCFGR2_IC20PUB_Msk (0x1UL << RCC_PUBCFGR2_IC20PUB_Pos) /*!< 0x00080000 */ #define RCC_PUBCFGR2_IC20PUB RCC_PUBCFGR2_IC20PUB_Msk /*!< Public protection of IC20 divider configuration bits */ /***************** Bit definition for RCC_SECCFGR3 register *****************/ #define RCC_SECCFGR3_MODSEC_Pos (0U) #define RCC_SECCFGR3_MODSEC_Msk (0x1UL << RCC_SECCFGR3_MODSEC_Pos) /*!< 0x00000001 */ #define RCC_SECCFGR3_MODSEC RCC_SECCFGR3_MODSEC_Msk /*!< Secure protection of MOD system configuration bits */ #define RCC_SECCFGR3_SYSSEC_Pos (1U) #define RCC_SECCFGR3_SYSSEC_Msk (0x1UL << RCC_SECCFGR3_SYSSEC_Pos) /*!< 0x00000002 */ #define RCC_SECCFGR3_SYSSEC RCC_SECCFGR3_SYSSEC_Msk /*!< Secure protection of SYS system configuration bit */ #define RCC_SECCFGR3_BUSSEC_Pos (2U) #define RCC_SECCFGR3_BUSSEC_Msk (0x1UL << RCC_SECCFGR3_BUSSEC_Pos) /*!< 0x00000004 */ #define RCC_SECCFGR3_BUSSEC RCC_SECCFGR3_BUSSEC_Msk /*!< Secure protection of BUS system configuration bits */ #define RCC_SECCFGR3_PERSEC_Pos (3U) #define RCC_SECCFGR3_PERSEC_Msk (0x1UL << RCC_SECCFGR3_PERSEC_Pos) /*!< 0x00000008 */ #define RCC_SECCFGR3_PERSEC RCC_SECCFGR3_PERSEC_Msk /*!< Secure protection of PER system configuration bits */ #define RCC_SECCFGR3_INTSEC_Pos (4U) #define RCC_SECCFGR3_INTSEC_Msk (0x1UL << RCC_SECCFGR3_INTSEC_Pos) /*!< 0x00000010 */ #define RCC_SECCFGR3_INTSEC RCC_SECCFGR3_INTSEC_Msk /*!< Secure protection of INT system configuration bits */ #define RCC_SECCFGR3_RSTSEC_Pos (5U) #define RCC_SECCFGR3_RSTSEC_Msk (0x1UL << RCC_SECCFGR3_RSTSEC_Pos) /*!< 0x00000020 */ #define RCC_SECCFGR3_RSTSEC RCC_SECCFGR3_RSTSEC_Msk /*!< Secure protection of RST system configuration bits */ /**************** Bit definition for RCC_PRIVCFGR3 register *****************/ #define RCC_PRIVCFGR3_MODPRIV_Pos (0U) #define RCC_PRIVCFGR3_MODPRIV_Msk (0x1UL << RCC_PRIVCFGR3_MODPRIV_Pos) /*!< 0x00000001 */ #define RCC_PRIVCFGR3_MODPRIV RCC_PRIVCFGR3_MODPRIV_Msk /*!< Privileged protection of MOD system configuration bits */ #define RCC_PRIVCFGR3_SYSPRIV_Pos (1U) #define RCC_PRIVCFGR3_SYSPRIV_Msk (0x1UL << RCC_PRIVCFGR3_SYSPRIV_Pos) /*!< 0x00000002 */ #define RCC_PRIVCFGR3_SYSPRIV RCC_PRIVCFGR3_SYSPRIV_Msk /*!< Privileged protection of SYS system configuration bits */ #define RCC_PRIVCFGR3_BUSPRIV_Pos (2U) #define RCC_PRIVCFGR3_BUSPRIV_Msk (0x1UL << RCC_PRIVCFGR3_BUSPRIV_Pos) /*!< 0x00000004 */ #define RCC_PRIVCFGR3_BUSPRIV RCC_PRIVCFGR3_BUSPRIV_Msk /*!< Privileged protection of BUS system configuration bits */ #define RCC_PRIVCFGR3_PERPRIV_Pos (3U) #define RCC_PRIVCFGR3_PERPRIV_Msk (0x1UL << RCC_PRIVCFGR3_PERPRIV_Pos) /*!< 0x00000008 */ #define RCC_PRIVCFGR3_PERPRIV RCC_PRIVCFGR3_PERPRIV_Msk /*!< Privileged protection of PER system configuration bits */ #define RCC_PRIVCFGR3_INTPRIV_Pos (4U) #define RCC_PRIVCFGR3_INTPRIV_Msk (0x1UL << RCC_PRIVCFGR3_INTPRIV_Pos) /*!< 0x00000010 */ #define RCC_PRIVCFGR3_INTPRIV RCC_PRIVCFGR3_INTPRIV_Msk /*!< Privileged protection of INT system configuration bits */ #define RCC_PRIVCFGR3_RSTPRIV_Pos (5U) #define RCC_PRIVCFGR3_RSTPRIV_Msk (0x1UL << RCC_PRIVCFGR3_RSTPRIV_Pos) /*!< 0x00000020 */ #define RCC_PRIVCFGR3_RSTPRIV RCC_PRIVCFGR3_RSTPRIV_Msk /*!< Privileged protection of RST system configuration bits */ /**************** Bit definition for RCC_LOCKCFGR3 register *****************/ #define RCC_LOCKCFGR3_MODLOCK_Pos (0U) #define RCC_LOCKCFGR3_MODLOCK_Msk (0x1UL << RCC_LOCKCFGR3_MODLOCK_Pos) /*!< 0x00000001 */ #define RCC_LOCKCFGR3_MODLOCK RCC_LOCKCFGR3_MODLOCK_Msk /*!< Locked protection of MOD system configuration bits */ #define RCC_LOCKCFGR3_SYSLOCK_Pos (1U) #define RCC_LOCKCFGR3_SYSLOCK_Msk (0x1UL << RCC_LOCKCFGR3_SYSLOCK_Pos) /*!< 0x00000002 */ #define RCC_LOCKCFGR3_SYSLOCK RCC_LOCKCFGR3_SYSLOCK_Msk /*!< Locked protection of SYS system configuration bits */ #define RCC_LOCKCFGR3_BUSLOCK_Pos (2U) #define RCC_LOCKCFGR3_BUSLOCK_Msk (0x1UL << RCC_LOCKCFGR3_BUSLOCK_Pos) /*!< 0x00000004 */ #define RCC_LOCKCFGR3_BUSLOCK RCC_LOCKCFGR3_BUSLOCK_Msk /*!< Locked protection of BUS system configuration bits */ #define RCC_LOCKCFGR3_PERLOCK_Pos (3U) #define RCC_LOCKCFGR3_PERLOCK_Msk (0x1UL << RCC_LOCKCFGR3_PERLOCK_Pos) /*!< 0x00000008 */ #define RCC_LOCKCFGR3_PERLOCK RCC_LOCKCFGR3_PERLOCK_Msk /*!< Locked protection of PER system configuration bits */ #define RCC_LOCKCFGR3_INTLOCK_Pos (4U) #define RCC_LOCKCFGR3_INTLOCK_Msk (0x1UL << RCC_LOCKCFGR3_INTLOCK_Pos) /*!< 0x00000010 */ #define RCC_LOCKCFGR3_INTLOCK RCC_LOCKCFGR3_INTLOCK_Msk /*!< Locked protection of INT system configuration bits */ #define RCC_LOCKCFGR3_RSTLOCK_Pos (5U) #define RCC_LOCKCFGR3_RSTLOCK_Msk (0x1UL << RCC_LOCKCFGR3_RSTLOCK_Pos) /*!< 0x00000020 */ #define RCC_LOCKCFGR3_RSTLOCK RCC_LOCKCFGR3_RSTLOCK_Msk /*!< Locked protection of RST system configuration bits */ /***************** Bit definition for RCC_PUBCFGR3 register *****************/ #define RCC_PUBCFGR3_MODPUB_Pos (0U) #define RCC_PUBCFGR3_MODPUB_Msk (0x1UL << RCC_PUBCFGR3_MODPUB_Pos) /*!< 0x00000001 */ #define RCC_PUBCFGR3_MODPUB RCC_PUBCFGR3_MODPUB_Msk /*!< Public protection of MOD system configuration bits */ #define RCC_PUBCFGR3_SYSPUB_Pos (1U) #define RCC_PUBCFGR3_SYSPUB_Msk (0x1UL << RCC_PUBCFGR3_SYSPUB_Pos) /*!< 0x00000002 */ #define RCC_PUBCFGR3_SYSPUB RCC_PUBCFGR3_SYSPUB_Msk /*!< Public protection of SYS system configuration bits */ #define RCC_PUBCFGR3_BUSPUB_Pos (2U) #define RCC_PUBCFGR3_BUSPUB_Msk (0x1UL << RCC_PUBCFGR3_BUSPUB_Pos) /*!< 0x00000004 */ #define RCC_PUBCFGR3_BUSPUB RCC_PUBCFGR3_BUSPUB_Msk /*!< Public protection of BUS system configuration bits */ #define RCC_PUBCFGR3_PERPUB_Pos (3U) #define RCC_PUBCFGR3_PERPUB_Msk (0x1UL << RCC_PUBCFGR3_PERPUB_Pos) /*!< 0x00000008 */ #define RCC_PUBCFGR3_PERPUB RCC_PUBCFGR3_PERPUB_Msk /*!< Public protection of PER system configuration bits */ #define RCC_PUBCFGR3_INTPUB_Pos (4U) #define RCC_PUBCFGR3_INTPUB_Msk (0x1UL << RCC_PUBCFGR3_INTPUB_Pos) /*!< 0x00000010 */ #define RCC_PUBCFGR3_INTPUB RCC_PUBCFGR3_INTPUB_Msk /*!< Public protection of INT system configuration bits */ #define RCC_PUBCFGR3_RSTPUB_Pos (5U) #define RCC_PUBCFGR3_RSTPUB_Msk (0x1UL << RCC_PUBCFGR3_RSTPUB_Pos) /*!< 0x00000020 */ #define RCC_PUBCFGR3_RSTPUB RCC_PUBCFGR3_RSTPUB_Msk /*!< Public protection of RST system configuration bits */ /***************** Bit definition for RCC_SECCFGR4 register *****************/ #define RCC_SECCFGR4_ACLKNSEC_Pos (0U) #define RCC_SECCFGR4_ACLKNSEC_Msk (0x1UL << RCC_SECCFGR4_ACLKNSEC_Pos) /*!< 0x00000001 */ #define RCC_SECCFGR4_ACLKNSEC RCC_SECCFGR4_ACLKNSEC_Msk /*!< Secure protection of ACLKN bus configuration bits */ #define RCC_SECCFGR4_ACLKNCSEC_Pos (1U) #define RCC_SECCFGR4_ACLKNCSEC_Msk (0x1UL << RCC_SECCFGR4_ACLKNCSEC_Pos) /*!< 0x00000002 */ #define RCC_SECCFGR4_ACLKNCSEC RCC_SECCFGR4_ACLKNCSEC_Msk /*!< Secure protection of ACLKNC bus configuration bits */ #define RCC_SECCFGR4_AHBMSEC_Pos (2U) #define RCC_SECCFGR4_AHBMSEC_Msk (0x1UL << RCC_SECCFGR4_AHBMSEC_Pos) /*!< 0x00000004 */ #define RCC_SECCFGR4_AHBMSEC RCC_SECCFGR4_AHBMSEC_Msk /*!< Secure protection of AHBM bus configuration bits */ #define RCC_SECCFGR4_AHB1SEC_Pos (3U) #define RCC_SECCFGR4_AHB1SEC_Msk (0x1UL << RCC_SECCFGR4_AHB1SEC_Pos) /*!< 0x00000008 */ #define RCC_SECCFGR4_AHB1SEC RCC_SECCFGR4_AHB1SEC_Msk /*!< Secure protection of AHB1 bus configuration bits */ #define RCC_SECCFGR4_AHB2SEC_Pos (4U) #define RCC_SECCFGR4_AHB2SEC_Msk (0x1UL << RCC_SECCFGR4_AHB2SEC_Pos) /*!< 0x00000010 */ #define RCC_SECCFGR4_AHB2SEC RCC_SECCFGR4_AHB2SEC_Msk /*!< Secure protection of AHB2 bus configuration bits */ #define RCC_SECCFGR4_AHB3SEC_Pos (5U) #define RCC_SECCFGR4_AHB3SEC_Msk (0x1UL << RCC_SECCFGR4_AHB3SEC_Pos) /*!< 0x00000020 */ #define RCC_SECCFGR4_AHB3SEC RCC_SECCFGR4_AHB3SEC_Msk /*!< Secure protection of AHB3 bus configuration bits */ #define RCC_SECCFGR4_AHB4SEC_Pos (6U) #define RCC_SECCFGR4_AHB4SEC_Msk (0x1UL << RCC_SECCFGR4_AHB4SEC_Pos) /*!< 0x00000040 */ #define RCC_SECCFGR4_AHB4SEC RCC_SECCFGR4_AHB4SEC_Msk /*!< Secure protection of AHB4 bus configuration bits */ #define RCC_SECCFGR4_AHB5SEC_Pos (7U) #define RCC_SECCFGR4_AHB5SEC_Msk (0x1UL << RCC_SECCFGR4_AHB5SEC_Pos) /*!< 0x00000080 */ #define RCC_SECCFGR4_AHB5SEC RCC_SECCFGR4_AHB5SEC_Msk /*!< Secure protection of AHB5 bus configuration bits */ #define RCC_SECCFGR4_APB1SEC_Pos (8U) #define RCC_SECCFGR4_APB1SEC_Msk (0x1UL << RCC_SECCFGR4_APB1SEC_Pos) /*!< 0x00000100 */ #define RCC_SECCFGR4_APB1SEC RCC_SECCFGR4_APB1SEC_Msk /*!< Secure protection of APB1 bus configuration bits */ #define RCC_SECCFGR4_APB2SEC_Pos (9U) #define RCC_SECCFGR4_APB2SEC_Msk (0x1UL << RCC_SECCFGR4_APB2SEC_Pos) /*!< 0x00000200 */ #define RCC_SECCFGR4_APB2SEC RCC_SECCFGR4_APB2SEC_Msk /*!< Secure protection of APB2 bus configuration bits */ #define RCC_SECCFGR4_APB3SEC_Pos (10U) #define RCC_SECCFGR4_APB3SEC_Msk (0x1UL << RCC_SECCFGR4_APB3SEC_Pos) /*!< 0x00000400 */ #define RCC_SECCFGR4_APB3SEC RCC_SECCFGR4_APB3SEC_Msk /*!< Secure protection of APB3 bus configuration bits */ #define RCC_SECCFGR4_APB4SEC_Pos (11U) #define RCC_SECCFGR4_APB4SEC_Msk (0x1UL << RCC_SECCFGR4_APB4SEC_Pos) /*!< 0x00000800 */ #define RCC_SECCFGR4_APB4SEC RCC_SECCFGR4_APB4SEC_Msk /*!< Secure protection of APB4 bus configuration bits */ #define RCC_SECCFGR4_APB5SEC_Pos (12U) #define RCC_SECCFGR4_APB5SEC_Msk (0x1UL << RCC_SECCFGR4_APB5SEC_Pos) /*!< 0x00001000 */ #define RCC_SECCFGR4_APB5SEC RCC_SECCFGR4_APB5SEC_Msk /*!< Secure protection of APB5 bus configuration bits */ #define RCC_SECCFGR4_NOCSEC_Pos (13U) #define RCC_SECCFGR4_NOCSEC_Msk (0x1UL << RCC_SECCFGR4_NOCSEC_Pos) /*!< 0x00002000 */ #define RCC_SECCFGR4_NOCSEC RCC_SECCFGR4_NOCSEC_Msk /*!< Secure protection of NOC bus configuration bits */ /**************** Bit definition for RCC_PRIVCFGR4 register *****************/ #define RCC_PRIVCFGR4_ACLKNPRIV_Pos (0U) #define RCC_PRIVCFGR4_ACLKNPRIV_Msk (0x1UL << RCC_PRIVCFGR4_ACLKNPRIV_Pos)/*!< 0x00000001 */ #define RCC_PRIVCFGR4_ACLKNPRIV RCC_PRIVCFGR4_ACLKNPRIV_Msk /*!< Privileged protection of ACLKN bus configuration bits */ #define RCC_PRIVCFGR4_ACLKNCPRIV_Pos (1U) #define RCC_PRIVCFGR4_ACLKNCPRIV_Msk (0x1UL << RCC_PRIVCFGR4_ACLKNCPRIV_Pos) /*!< 0x00000002 */ #define RCC_PRIVCFGR4_ACLKNCPRIV RCC_PRIVCFGR4_ACLKNCPRIV_Msk /*!< Privileged protection of ACLKNC bus configuration bits */ #define RCC_PRIVCFGR4_AHBMPRIV_Pos (2U) #define RCC_PRIVCFGR4_AHBMPRIV_Msk (0x1UL << RCC_PRIVCFGR4_AHBMPRIV_Pos) /*!< 0x00000004 */ #define RCC_PRIVCFGR4_AHBMPRIV RCC_PRIVCFGR4_AHBMPRIV_Msk /*!< Privileged protection of AHBM bus configuration bits */ #define RCC_PRIVCFGR4_AHB1PRIV_Pos (3U) #define RCC_PRIVCFGR4_AHB1PRIV_Msk (0x1UL << RCC_PRIVCFGR4_AHB1PRIV_Pos) /*!< 0x00000008 */ #define RCC_PRIVCFGR4_AHB1PRIV RCC_PRIVCFGR4_AHB1PRIV_Msk /*!< Privileged protection of AHB1 bus configuration bits */ #define RCC_PRIVCFGR4_AHB2PRIV_Pos (4U) #define RCC_PRIVCFGR4_AHB2PRIV_Msk (0x1UL << RCC_PRIVCFGR4_AHB2PRIV_Pos) /*!< 0x00000010 */ #define RCC_PRIVCFGR4_AHB2PRIV RCC_PRIVCFGR4_AHB2PRIV_Msk /*!< Privileged protection of AHB2 bus configuration bits */ #define RCC_PRIVCFGR4_AHB3PRIV_Pos (5U) #define RCC_PRIVCFGR4_AHB3PRIV_Msk (0x1UL << RCC_PRIVCFGR4_AHB3PRIV_Pos) /*!< 0x00000020 */ #define RCC_PRIVCFGR4_AHB3PRIV RCC_PRIVCFGR4_AHB3PRIV_Msk /*!< Privileged protection of AHB3 bus configuration bits */ #define RCC_PRIVCFGR4_AHB4PRIV_Pos (6U) #define RCC_PRIVCFGR4_AHB4PRIV_Msk (0x1UL << RCC_PRIVCFGR4_AHB4PRIV_Pos) /*!< 0x00000040 */ #define RCC_PRIVCFGR4_AHB4PRIV RCC_PRIVCFGR4_AHB4PRIV_Msk /*!< Privileged protection of AHB4 bus configuration bits */ #define RCC_PRIVCFGR4_AHB5PRIV_Pos (7U) #define RCC_PRIVCFGR4_AHB5PRIV_Msk (0x1UL << RCC_PRIVCFGR4_AHB5PRIV_Pos) /*!< 0x00000080 */ #define RCC_PRIVCFGR4_AHB5PRIV RCC_PRIVCFGR4_AHB5PRIV_Msk /*!< Privileged protection of AHB5 bus configuration bits */ #define RCC_PRIVCFGR4_APB1PRIV_Pos (8U) #define RCC_PRIVCFGR4_APB1PRIV_Msk (0x1UL << RCC_PRIVCFGR4_APB1PRIV_Pos) /*!< 0x00000100 */ #define RCC_PRIVCFGR4_APB1PRIV RCC_PRIVCFGR4_APB1PRIV_Msk /*!< Privileged protection of APB1 bus configuration bits */ #define RCC_PRIVCFGR4_APB2PRIV_Pos (9U) #define RCC_PRIVCFGR4_APB2PRIV_Msk (0x1UL << RCC_PRIVCFGR4_APB2PRIV_Pos) /*!< 0x00000200 */ #define RCC_PRIVCFGR4_APB2PRIV RCC_PRIVCFGR4_APB2PRIV_Msk /*!< Privileged protection of APB2 bus configuration bits */ #define RCC_PRIVCFGR4_APB3PRIV_Pos (10U) #define RCC_PRIVCFGR4_APB3PRIV_Msk (0x1UL << RCC_PRIVCFGR4_APB3PRIV_Pos) /*!< 0x00000400 */ #define RCC_PRIVCFGR4_APB3PRIV RCC_PRIVCFGR4_APB3PRIV_Msk /*!< Privileged protection of APB3 bus configuration bits */ #define RCC_PRIVCFGR4_APB4PRIV_Pos (11U) #define RCC_PRIVCFGR4_APB4PRIV_Msk (0x1UL << RCC_PRIVCFGR4_APB4PRIV_Pos) /*!< 0x00000800 */ #define RCC_PRIVCFGR4_APB4PRIV RCC_PRIVCFGR4_APB4PRIV_Msk /*!< Privileged protection of APB4 bus configuration bits */ #define RCC_PRIVCFGR4_APB5PRIV_Pos (12U) #define RCC_PRIVCFGR4_APB5PRIV_Msk (0x1UL << RCC_PRIVCFGR4_APB5PRIV_Pos) /*!< 0x00001000 */ #define RCC_PRIVCFGR4_APB5PRIV RCC_PRIVCFGR4_APB5PRIV_Msk /*!< Privileged protection of APB5 bus configuration bits */ #define RCC_PRIVCFGR4_NOCPRIV_Pos (13U) #define RCC_PRIVCFGR4_NOCPRIV_Msk (0x1UL << RCC_PRIVCFGR4_NOCPRIV_Pos) /*!< 0x00002000 */ #define RCC_PRIVCFGR4_NOCPRIV RCC_PRIVCFGR4_NOCPRIV_Msk /*!< Privileged protection of NOC bus configuration bits */ /**************** Bit definition for RCC_LOCKCFGR4 register *****************/ #define RCC_LOCKCFGR4_ACLKNLOCK_Pos (0U) #define RCC_LOCKCFGR4_ACLKNLOCK_Msk (0x1UL << RCC_LOCKCFGR4_ACLKNLOCK_Pos)/*!< 0x00000001 */ #define RCC_LOCKCFGR4_ACLKNLOCK RCC_LOCKCFGR4_ACLKNLOCK_Msk /*!< Locked protection of ACLKN bus configuration bits */ #define RCC_LOCKCFGR4_ACLKNCLOCK_Pos (1U) #define RCC_LOCKCFGR4_ACLKNCLOCK_Msk (0x1UL << RCC_LOCKCFGR4_ACLKNCLOCK_Pos) /*!< 0x00000002 */ #define RCC_LOCKCFGR4_ACLKNCLOCK RCC_LOCKCFGR4_ACLKNCLOCK_Msk /*!< Locked protection of ACLKNC bus configuration bits */ #define RCC_LOCKCFGR4_AHBMLOCK_Pos (2U) #define RCC_LOCKCFGR4_AHBMLOCK_Msk (0x1UL << RCC_LOCKCFGR4_AHBMLOCK_Pos) /*!< 0x00000004 */ #define RCC_LOCKCFGR4_AHBMLOCK RCC_LOCKCFGR4_AHBMLOCK_Msk /*!< Locked protection of AHBM bus configuration bits */ #define RCC_LOCKCFGR4_AHB1LOCK_Pos (3U) #define RCC_LOCKCFGR4_AHB1LOCK_Msk (0x1UL << RCC_LOCKCFGR4_AHB1LOCK_Pos) /*!< 0x00000008 */ #define RCC_LOCKCFGR4_AHB1LOCK RCC_LOCKCFGR4_AHB1LOCK_Msk /*!< Locked protection of AHB1 bus configuration bits */ #define RCC_LOCKCFGR4_AHB2LOCK_Pos (4U) #define RCC_LOCKCFGR4_AHB2LOCK_Msk (0x1UL << RCC_LOCKCFGR4_AHB2LOCK_Pos) /*!< 0x00000010 */ #define RCC_LOCKCFGR4_AHB2LOCK RCC_LOCKCFGR4_AHB2LOCK_Msk /*!< Locked protection of AHB2 bus configuration bits */ #define RCC_LOCKCFGR4_AHB3LOCK_Pos (5U) #define RCC_LOCKCFGR4_AHB3LOCK_Msk (0x1UL << RCC_LOCKCFGR4_AHB3LOCK_Pos) /*!< 0x00000020 */ #define RCC_LOCKCFGR4_AHB3LOCK RCC_LOCKCFGR4_AHB3LOCK_Msk /*!< Locked protection of AHB3 bus configuration bits */ #define RCC_LOCKCFGR4_AHB4LOCK_Pos (6U) #define RCC_LOCKCFGR4_AHB4LOCK_Msk (0x1UL << RCC_LOCKCFGR4_AHB4LOCK_Pos) /*!< 0x00000040 */ #define RCC_LOCKCFGR4_AHB4LOCK RCC_LOCKCFGR4_AHB4LOCK_Msk /*!< Locked protection of AHB4 bus configuration bits */ #define RCC_LOCKCFGR4_AHB5LOCK_Pos (7U) #define RCC_LOCKCFGR4_AHB5LOCK_Msk (0x1UL << RCC_LOCKCFGR4_AHB5LOCK_Pos) /*!< 0x00000080 */ #define RCC_LOCKCFGR4_AHB5LOCK RCC_LOCKCFGR4_AHB5LOCK_Msk /*!< Locked protection of AHB5 bus configuration bits */ #define RCC_LOCKCFGR4_APB1LOCK_Pos (8U) #define RCC_LOCKCFGR4_APB1LOCK_Msk (0x1UL << RCC_LOCKCFGR4_APB1LOCK_Pos) /*!< 0x00000100 */ #define RCC_LOCKCFGR4_APB1LOCK RCC_LOCKCFGR4_APB1LOCK_Msk /*!< Locked protection of APB1 bus configuration bits */ #define RCC_LOCKCFGR4_APB2LOCK_Pos (9U) #define RCC_LOCKCFGR4_APB2LOCK_Msk (0x1UL << RCC_LOCKCFGR4_APB2LOCK_Pos) /*!< 0x00000200 */ #define RCC_LOCKCFGR4_APB2LOCK RCC_LOCKCFGR4_APB2LOCK_Msk /*!< Locked protection of APB2 bus configuration bits */ #define RCC_LOCKCFGR4_APB3LOCK_Pos (10U) #define RCC_LOCKCFGR4_APB3LOCK_Msk (0x1UL << RCC_LOCKCFGR4_APB3LOCK_Pos) /*!< 0x00000400 */ #define RCC_LOCKCFGR4_APB3LOCK RCC_LOCKCFGR4_APB3LOCK_Msk /*!< Locked protection of APB3 bus configuration bits */ #define RCC_LOCKCFGR4_APB4LOCK_Pos (11U) #define RCC_LOCKCFGR4_APB4LOCK_Msk (0x1UL << RCC_LOCKCFGR4_APB4LOCK_Pos) /*!< 0x00000800 */ #define RCC_LOCKCFGR4_APB4LOCK RCC_LOCKCFGR4_APB4LOCK_Msk /*!< Locked protection of APB4 bus configuration bits */ #define RCC_LOCKCFGR4_APB5LOCK_Pos (12U) #define RCC_LOCKCFGR4_APB5LOCK_Msk (0x1UL << RCC_LOCKCFGR4_APB5LOCK_Pos) /*!< 0x00001000 */ #define RCC_LOCKCFGR4_APB5LOCK RCC_LOCKCFGR4_APB5LOCK_Msk /*!< Locked protection of APB5 bus configuration bits */ #define RCC_LOCKCFGR4_NOCLOCK_Pos (13U) #define RCC_LOCKCFGR4_NOCLOCK_Msk (0x1UL << RCC_LOCKCFGR4_NOCLOCK_Pos) /*!< 0x00002000 */ #define RCC_LOCKCFGR4_NOCLOCK RCC_LOCKCFGR4_NOCLOCK_Msk /*!< Locked protection of NOC bus configuration bits */ /***************** Bit definition for RCC_PUBCFGR4 register *****************/ #define RCC_PUBCFGR4_ACLKNPUB_Pos (0U) #define RCC_PUBCFGR4_ACLKNPUB_Msk (0x1UL << RCC_PUBCFGR4_ACLKNPUB_Pos) /*!< 0x00000001 */ #define RCC_PUBCFGR4_ACLKNPUB RCC_PUBCFGR4_ACLKNPUB_Msk /*!< Public protection of the ACLKN bus configuration bits */ #define RCC_PUBCFGR4_ACLKNCPUB_Pos (1U) #define RCC_PUBCFGR4_ACLKNCPUB_Msk (0x1UL << RCC_PUBCFGR4_ACLKNCPUB_Pos) /*!< 0x00000002 */ #define RCC_PUBCFGR4_ACLKNCPUB RCC_PUBCFGR4_ACLKNCPUB_Msk /*!< Public protection of ACLKNC bus configuration bits */ #define RCC_PUBCFGR4_AHBMPUB_Pos (2U) #define RCC_PUBCFGR4_AHBMPUB_Msk (0x1UL << RCC_PUBCFGR4_AHBMPUB_Pos) /*!< 0x00000004 */ #define RCC_PUBCFGR4_AHBMPUB RCC_PUBCFGR4_AHBMPUB_Msk /*!< Public protection of AHBM bus configuration bits */ #define RCC_PUBCFGR4_AHB1PUB_Pos (3U) #define RCC_PUBCFGR4_AHB1PUB_Msk (0x1UL << RCC_PUBCFGR4_AHB1PUB_Pos) /*!< 0x00000008 */ #define RCC_PUBCFGR4_AHB1PUB RCC_PUBCFGR4_AHB1PUB_Msk /*!< Public protection of AHB1 bus configuration bits */ #define RCC_PUBCFGR4_AHB2PUB_Pos (4U) #define RCC_PUBCFGR4_AHB2PUB_Msk (0x1UL << RCC_PUBCFGR4_AHB2PUB_Pos) /*!< 0x00000010 */ #define RCC_PUBCFGR4_AHB2PUB RCC_PUBCFGR4_AHB2PUB_Msk /*!< Public protection of AHB2 bus configuration bits */ #define RCC_PUBCFGR4_AHB3PUB_Pos (5U) #define RCC_PUBCFGR4_AHB3PUB_Msk (0x1UL << RCC_PUBCFGR4_AHB3PUB_Pos) /*!< 0x00000020 */ #define RCC_PUBCFGR4_AHB3PUB RCC_PUBCFGR4_AHB3PUB_Msk /*!< Public protection of AHB3 bus configuration bits */ #define RCC_PUBCFGR4_AHB4PUB_Pos (6U) #define RCC_PUBCFGR4_AHB4PUB_Msk (0x1UL << RCC_PUBCFGR4_AHB4PUB_Pos) /*!< 0x00000040 */ #define RCC_PUBCFGR4_AHB4PUB RCC_PUBCFGR4_AHB4PUB_Msk /*!< Public protection of AHB4 bus configuration bits */ #define RCC_PUBCFGR4_AHB5PUB_Pos (7U) #define RCC_PUBCFGR4_AHB5PUB_Msk (0x1UL << RCC_PUBCFGR4_AHB5PUB_Pos) /*!< 0x00000080 */ #define RCC_PUBCFGR4_AHB5PUB RCC_PUBCFGR4_AHB5PUB_Msk /*!< Public protection of AHB5 bus configuration bits */ #define RCC_PUBCFGR4_APB1PUB_Pos (8U) #define RCC_PUBCFGR4_APB1PUB_Msk (0x1UL << RCC_PUBCFGR4_APB1PUB_Pos) /*!< 0x00000100 */ #define RCC_PUBCFGR4_APB1PUB RCC_PUBCFGR4_APB1PUB_Msk /*!< Public protection of APB1 bus configuration bits */ #define RCC_PUBCFGR4_APB2PUB_Pos (9U) #define RCC_PUBCFGR4_APB2PUB_Msk (0x1UL << RCC_PUBCFGR4_APB2PUB_Pos) /*!< 0x00000200 */ #define RCC_PUBCFGR4_APB2PUB RCC_PUBCFGR4_APB2PUB_Msk /*!< Public protection of APB2 bus configuration bits */ #define RCC_PUBCFGR4_APB3PUB_Pos (10U) #define RCC_PUBCFGR4_APB3PUB_Msk (0x1UL << RCC_PUBCFGR4_APB3PUB_Pos) /*!< 0x00000400 */ #define RCC_PUBCFGR4_APB3PUB RCC_PUBCFGR4_APB3PUB_Msk /*!< Public protection of APB3 bus configuration bits */ #define RCC_PUBCFGR4_APB4PUB_Pos (11U) #define RCC_PUBCFGR4_APB4PUB_Msk (0x1UL << RCC_PUBCFGR4_APB4PUB_Pos) /*!< 0x00000800 */ #define RCC_PUBCFGR4_APB4PUB RCC_PUBCFGR4_APB4PUB_Msk /*!< Public protection of APB4 bus configuration bits */ #define RCC_PUBCFGR4_APB5PUB_Pos (12U) #define RCC_PUBCFGR4_APB5PUB_Msk (0x1UL << RCC_PUBCFGR4_APB5PUB_Pos) /*!< 0x00001000 */ #define RCC_PUBCFGR4_APB5PUB RCC_PUBCFGR4_APB5PUB_Msk /*!< Public protection of APB5 bus configuration bits */ #define RCC_PUBCFGR4_NOCPUB_Pos (13U) #define RCC_PUBCFGR4_NOCPUB_Msk (0x1UL << RCC_PUBCFGR4_NOCPUB_Pos) /*!< 0x00002000 */ #define RCC_PUBCFGR4_NOCPUB RCC_PUBCFGR4_NOCPUB_Msk /*!< Public protection of NOC bus configuration bits */ /***************** Bit definition for RCC_PUBCFGR5 register *****************/ #define RCC_PUBCFGR5_AXISRAM3PUB_Pos (0U) #define RCC_PUBCFGR5_AXISRAM3PUB_Msk (0x1UL << RCC_PUBCFGR5_AXISRAM3PUB_Pos) /*!< 0x00000001 */ #define RCC_PUBCFGR5_AXISRAM3PUB RCC_PUBCFGR5_AXISRAM3PUB_Msk /*!< Public protection of AXISRAM3 bus configuration bits */ #define RCC_PUBCFGR5_AXISRAM4PUB_Pos (1U) #define RCC_PUBCFGR5_AXISRAM4PUB_Msk (0x1UL << RCC_PUBCFGR5_AXISRAM4PUB_Pos) /*!< 0x00000002 */ #define RCC_PUBCFGR5_AXISRAM4PUB RCC_PUBCFGR5_AXISRAM4PUB_Msk /*!< Public protection of AXISRAM4 bus configuration bits */ #define RCC_PUBCFGR5_AXISRAM5PUB_Pos (2U) #define RCC_PUBCFGR5_AXISRAM5PUB_Msk (0x1UL << RCC_PUBCFGR5_AXISRAM5PUB_Pos) /*!< 0x00000004 */ #define RCC_PUBCFGR5_AXISRAM5PUB RCC_PUBCFGR5_AXISRAM5PUB_Msk /*!< Public protection of AXISRAM5 bus configuration bits */ #define RCC_PUBCFGR5_AXISRAM6PUB_Pos (3U) #define RCC_PUBCFGR5_AXISRAM6PUB_Msk (0x1UL << RCC_PUBCFGR5_AXISRAM6PUB_Pos) /*!< 0x00000008 */ #define RCC_PUBCFGR5_AXISRAM6PUB RCC_PUBCFGR5_AXISRAM6PUB_Msk /*!< Public protection of AXISRAM6 bus configuration bits */ #define RCC_PUBCFGR5_AHBSRAM1PUB_Pos (4U) #define RCC_PUBCFGR5_AHBSRAM1PUB_Msk (0x1UL << RCC_PUBCFGR5_AHBSRAM1PUB_Pos) /*!< 0x00000010 */ #define RCC_PUBCFGR5_AHBSRAM1PUB RCC_PUBCFGR5_AHBSRAM1PUB_Msk /*!< Public protection of AHBSRAM1 bus configuration bits */ #define RCC_PUBCFGR5_AHBSRAM2PUB_Pos (5U) #define RCC_PUBCFGR5_AHBSRAM2PUB_Msk (0x1UL << RCC_PUBCFGR5_AHBSRAM2PUB_Pos) /*!< 0x00000020 */ #define RCC_PUBCFGR5_AHBSRAM2PUB RCC_PUBCFGR5_AHBSRAM2PUB_Msk /*!< Public protection of AHBSRAM2 bus configuration bits */ #define RCC_PUBCFGR5_BKPSRAMPUB_Pos (6U) #define RCC_PUBCFGR5_BKPSRAMPUB_Msk (0x1UL << RCC_PUBCFGR5_BKPSRAMPUB_Pos)/*!< 0x00000040 */ #define RCC_PUBCFGR5_BKPSRAMPUB RCC_PUBCFGR5_BKPSRAMPUB_Msk /*!< Public protection of BKPSRAM bus configuration bits */ #define RCC_PUBCFGR5_AXISRAM1PUB_Pos (7U) #define RCC_PUBCFGR5_AXISRAM1PUB_Msk (0x1UL << RCC_PUBCFGR5_AXISRAM1PUB_Pos) /*!< 0x00000080 */ #define RCC_PUBCFGR5_AXISRAM1PUB RCC_PUBCFGR5_AXISRAM1PUB_Msk /*!< Public protection of AXISRAM1 bus configuration bits */ #define RCC_PUBCFGR5_AXISRAM2PUB_Pos (8U) #define RCC_PUBCFGR5_AXISRAM2PUB_Msk (0x1UL << RCC_PUBCFGR5_AXISRAM2PUB_Pos) /*!< 0x00000100 */ #define RCC_PUBCFGR5_AXISRAM2PUB RCC_PUBCFGR5_AXISRAM2PUB_Msk /*!< Public protection of AXISRAM2 bus configuration bits */ #define RCC_PUBCFGR5_FLEXRAMPUB_Pos (9U) #define RCC_PUBCFGR5_FLEXRAMPUB_Msk (0x1UL << RCC_PUBCFGR5_FLEXRAMPUB_Pos)/*!< 0x00000200 */ #define RCC_PUBCFGR5_FLEXRAMPUB RCC_PUBCFGR5_FLEXRAMPUB_Msk /*!< Public protection of FLEXRAM bus configuration bits */ #define RCC_PUBCFGR5_CACHEAXIRAMPUB_Pos (10U) #define RCC_PUBCFGR5_CACHEAXIRAMPUB_Msk (0x1UL << RCC_PUBCFGR5_CACHEAXIRAMPUB_Pos) /*!< 0x00000400 */ #define RCC_PUBCFGR5_CACHEAXIRAMPUB RCC_PUBCFGR5_CACHEAXIRAMPUB_Msk /*!< Public protection of CACHEAXIRAM bus configuration bits */ #define RCC_PUBCFGR5_VENCRAMPUB_Pos (11U) #define RCC_PUBCFGR5_VENCRAMPUB_Msk (0x1UL << RCC_PUBCFGR5_VENCRAMPUB_Pos)/*!< 0x00000800 */ #define RCC_PUBCFGR5_VENCRAMPUB RCC_PUBCFGR5_VENCRAMPUB_Msk /*!< Public protection of VENCRAM bus configuration bits */ /******************* Bit definition for RCC_CSR register ********************/ #define RCC_CSR_LSIONS_Pos (0U) #define RCC_CSR_LSIONS_Msk (0x1UL << RCC_CSR_LSIONS_Pos) /*!< 0x00000001 */ #define RCC_CSR_LSIONS RCC_CSR_LSIONS_Msk /*!< LSI oscillator enable */ #define RCC_CSR_LSEONS_Pos (1U) #define RCC_CSR_LSEONS_Msk (0x1UL << RCC_CSR_LSEONS_Pos) /*!< 0x00000002 */ #define RCC_CSR_LSEONS RCC_CSR_LSEONS_Msk /*!< LSE oscillator enable */ #define RCC_CSR_MSIONS_Pos (2U) #define RCC_CSR_MSIONS_Msk (0x1UL << RCC_CSR_MSIONS_Pos) /*!< 0x00000004 */ #define RCC_CSR_MSIONS RCC_CSR_MSIONS_Msk /*!< MSI oscillator enable */ #define RCC_CSR_HSIONS_Pos (3U) #define RCC_CSR_HSIONS_Msk (0x1UL << RCC_CSR_HSIONS_Pos) /*!< 0x00000008 */ #define RCC_CSR_HSIONS RCC_CSR_HSIONS_Msk /*!< HSI oscillator enable */ #define RCC_CSR_HSEONS_Pos (4U) #define RCC_CSR_HSEONS_Msk (0x1UL << RCC_CSR_HSEONS_Pos) /*!< 0x00000010 */ #define RCC_CSR_HSEONS RCC_CSR_HSEONS_Msk /*!< HSE oscillator enable */ #define RCC_CSR_PLL1ONS_Pos (8U) #define RCC_CSR_PLL1ONS_Msk (0x1UL << RCC_CSR_PLL1ONS_Pos) /*!< 0x00000100 */ #define RCC_CSR_PLL1ONS RCC_CSR_PLL1ONS_Msk /*!< PLL1 oscillator enable */ #define RCC_CSR_PLL2ONS_Pos (9U) #define RCC_CSR_PLL2ONS_Msk (0x1UL << RCC_CSR_PLL2ONS_Pos) /*!< 0x00000200 */ #define RCC_CSR_PLL2ONS RCC_CSR_PLL2ONS_Msk /*!< PLL2 oscillator enable */ #define RCC_CSR_PLL3ONS_Pos (10U) #define RCC_CSR_PLL3ONS_Msk (0x1UL << RCC_CSR_PLL3ONS_Pos) /*!< 0x00000400 */ #define RCC_CSR_PLL3ONS RCC_CSR_PLL3ONS_Msk /*!< PLL3 oscillator enable */ #define RCC_CSR_PLL4ONS_Pos (11U) #define RCC_CSR_PLL4ONS_Msk (0x1UL << RCC_CSR_PLL4ONS_Pos) /*!< 0x00000800 */ #define RCC_CSR_PLL4ONS RCC_CSR_PLL4ONS_Msk /*!< PLL4 oscillator enable */ /***************** Bit definition for RCC_STOPCSR register ******************/ #define RCC_STOPCSR_MSISTOPENS_Pos (0U) #define RCC_STOPCSR_MSISTOPENS_Msk (0x1UL << RCC_STOPCSR_MSISTOPENS_Pos) /*!< 0x00000001 */ #define RCC_STOPCSR_MSISTOPENS RCC_STOPCSR_MSISTOPENS_Msk /*!< MSI oscillator enable */ #define RCC_STOPCSR_HSISTOPENS_Pos (1U) #define RCC_STOPCSR_HSISTOPENS_Msk (0x1UL << RCC_STOPCSR_HSISTOPENS_Pos) /*!< 0x00000002 */ #define RCC_STOPCSR_HSISTOPENS RCC_STOPCSR_HSISTOPENS_Msk /*!< HSI oscillator enable */ /**************** Bit definition for RCC_MISCRSTSR register *****************/ #define RCC_MISCRSTSR_DBGRSTS_Pos (0U) #define RCC_MISCRSTSR_DBGRSTS_Msk (0x1UL << RCC_MISCRSTSR_DBGRSTS_Pos) /*!< 0x00000001 */ #define RCC_MISCRSTSR_DBGRSTS RCC_MISCRSTSR_DBGRSTS_Msk /*!< DBG reset */ #define RCC_MISCRSTSR_XSPIPHY1RSTS_Pos (4U) #define RCC_MISCRSTSR_XSPIPHY1RSTS_Msk (0x1UL << RCC_MISCRSTSR_XSPIPHY1RSTS_Pos) /*!< 0x00000010 */ #define RCC_MISCRSTSR_XSPIPHY1RSTS RCC_MISCRSTSR_XSPIPHY1RSTS_Msk /*!< XSPIPHY1 reset */ #define RCC_MISCRSTSR_XSPIPHY2RSTS_Pos (5U) #define RCC_MISCRSTSR_XSPIPHY2RSTS_Msk (0x1UL << RCC_MISCRSTSR_XSPIPHY2RSTS_Pos) /*!< 0x00000020 */ #define RCC_MISCRSTSR_XSPIPHY2RSTS RCC_MISCRSTSR_XSPIPHY2RSTS_Msk /*!< XSPIPHY2 reset */ #define RCC_MISCRSTSR_SDMMC1DLLRSTS_Pos (7U) #define RCC_MISCRSTSR_SDMMC1DLLRSTS_Msk (0x1UL << RCC_MISCRSTSR_SDMMC1DLLRSTS_Pos) /*!< 0x00000080 */ #define RCC_MISCRSTSR_SDMMC1DLLRSTS RCC_MISCRSTSR_SDMMC1DLLRSTS_Msk /*!< SDMMC1DLL reset */ #define RCC_MISCRSTSR_SDMMC2DLLRSTS_Pos (8U) #define RCC_MISCRSTSR_SDMMC2DLLRSTS_Msk (0x1UL << RCC_MISCRSTSR_SDMMC2DLLRSTS_Pos) /*!< 0x00000100 */ #define RCC_MISCRSTSR_SDMMC2DLLRSTS RCC_MISCRSTSR_SDMMC2DLLRSTS_Msk /*!< SDMMC2DLL reset */ /***************** Bit definition for RCC_MEMRSTSR register *****************/ #define RCC_MEMRSTSR_AXISRAM3RSTS_Pos (0U) #define RCC_MEMRSTSR_AXISRAM3RSTS_Msk (0x1UL << RCC_MEMRSTSR_AXISRAM3RSTS_Pos) /*!< 0x00000001 */ #define RCC_MEMRSTSR_AXISRAM3RSTS RCC_MEMRSTSR_AXISRAM3RSTS_Msk /*!< AXISRAM3 reset */ #define RCC_MEMRSTSR_AXISRAM4RSTS_Pos (1U) #define RCC_MEMRSTSR_AXISRAM4RSTS_Msk (0x1UL << RCC_MEMRSTSR_AXISRAM4RSTS_Pos) /*!< 0x00000002 */ #define RCC_MEMRSTSR_AXISRAM4RSTS RCC_MEMRSTSR_AXISRAM4RSTS_Msk /*!< AXISRAM4 reset */ #define RCC_MEMRSTSR_AXISRAM5RSTS_Pos (2U) #define RCC_MEMRSTSR_AXISRAM5RSTS_Msk (0x1UL << RCC_MEMRSTSR_AXISRAM5RSTS_Pos) /*!< 0x00000004 */ #define RCC_MEMRSTSR_AXISRAM5RSTS RCC_MEMRSTSR_AXISRAM5RSTS_Msk /*!< AXISRAM5 reset */ #define RCC_MEMRSTSR_AXISRAM6RSTS_Pos (3U) #define RCC_MEMRSTSR_AXISRAM6RSTS_Msk (0x1UL << RCC_MEMRSTSR_AXISRAM6RSTS_Pos) /*!< 0x00000008 */ #define RCC_MEMRSTSR_AXISRAM6RSTS RCC_MEMRSTSR_AXISRAM6RSTS_Msk /*!< AXISRAM6 reset */ #define RCC_MEMRSTSR_AHBSRAM1RSTS_Pos (4U) #define RCC_MEMRSTSR_AHBSRAM1RSTS_Msk (0x1UL << RCC_MEMRSTSR_AHBSRAM1RSTS_Pos) /*!< 0x00000010 */ #define RCC_MEMRSTSR_AHBSRAM1RSTS RCC_MEMRSTSR_AHBSRAM1RSTS_Msk /*!< AHBSRAM1 reset */ #define RCC_MEMRSTSR_AHBSRAM2RSTS_Pos (5U) #define RCC_MEMRSTSR_AHBSRAM2RSTS_Msk (0x1UL << RCC_MEMRSTSR_AHBSRAM2RSTS_Pos) /*!< 0x00000020 */ #define RCC_MEMRSTSR_AHBSRAM2RSTS RCC_MEMRSTSR_AHBSRAM2RSTS_Msk /*!< AHBSRAM2 reset */ #define RCC_MEMRSTSR_AXISRAM1RSTS_Pos (7U) #define RCC_MEMRSTSR_AXISRAM1RSTS_Msk (0x1UL << RCC_MEMRSTSR_AXISRAM1RSTS_Pos) /*!< 0x00000080 */ #define RCC_MEMRSTSR_AXISRAM1RSTS RCC_MEMRSTSR_AXISRAM1RSTS_Msk /*!< AXISRAM1 reset */ #define RCC_MEMRSTSR_AXISRAM2RSTS_Pos (8U) #define RCC_MEMRSTSR_AXISRAM2RSTS_Msk (0x1UL << RCC_MEMRSTSR_AXISRAM2RSTS_Pos) /*!< 0x00000100 */ #define RCC_MEMRSTSR_AXISRAM2RSTS RCC_MEMRSTSR_AXISRAM2RSTS_Msk /*!< AXISRAM2 reset */ #define RCC_MEMRSTSR_FLEXRAMRSTS_Pos (9U) #define RCC_MEMRSTSR_FLEXRAMRSTS_Msk (0x1UL << RCC_MEMRSTSR_FLEXRAMRSTS_Pos) /*!< 0x00000200 */ #define RCC_MEMRSTSR_FLEXRAMRSTS RCC_MEMRSTSR_FLEXRAMRSTS_Msk /*!< FLEXRAM reset */ #define RCC_MEMRSTSR_CACHEAXIRAMRSTS_Pos (10U) #define RCC_MEMRSTSR_CACHEAXIRAMRSTS_Msk (0x1UL << RCC_MEMRSTSR_CACHEAXIRAMRSTS_Pos) /*!< 0x00000400 */ #define RCC_MEMRSTSR_CACHEAXIRAMRSTS RCC_MEMRSTSR_CACHEAXIRAMRSTS_Msk /*!< CACHEAXIRAM reset */ #define RCC_MEMRSTSR_VENCRAMRSTS_Pos (11U) #define RCC_MEMRSTSR_VENCRAMRSTS_Msk (0x1UL << RCC_MEMRSTSR_VENCRAMRSTS_Pos) /*!< 0x00000800 */ #define RCC_MEMRSTSR_VENCRAMRSTS RCC_MEMRSTSR_VENCRAMRSTS_Msk /*!< VENCRAM reset */ #define RCC_MEMRSTSR_BOOTROMRSTS_Pos (12U) #define RCC_MEMRSTSR_BOOTROMRSTS_Msk (0x1UL << RCC_MEMRSTSR_BOOTROMRSTS_Pos) /*!< 0x00001000 */ #define RCC_MEMRSTSR_BOOTROMRSTS RCC_MEMRSTSR_BOOTROMRSTS_Msk /*!< Boot ROM reset */ /**************** Bit definition for RCC_AHB1RSTSR register *****************/ #define RCC_AHB1RSTSR_GPDMA1RSTS_Pos (4U) #define RCC_AHB1RSTSR_GPDMA1RSTS_Msk (0x1UL << RCC_AHB1RSTSR_GPDMA1RSTS_Pos) /*!< 0x00000010 */ #define RCC_AHB1RSTSR_GPDMA1RSTS RCC_AHB1RSTSR_GPDMA1RSTS_Msk /*!< GPDMA1 reset */ #define RCC_AHB1RSTSR_ADC12RSTS_Pos (5U) #define RCC_AHB1RSTSR_ADC12RSTS_Msk (0x1UL << RCC_AHB1RSTSR_ADC12RSTS_Pos)/*!< 0x00000020 */ #define RCC_AHB1RSTSR_ADC12RSTS RCC_AHB1RSTSR_ADC12RSTS_Msk /*!< ADC12 reset */ /**************** Bit definition for RCC_AHB2RSTSR register *****************/ #define RCC_AHB2RSTSR_RAMCFGRSTS_Pos (12U) #define RCC_AHB2RSTSR_RAMCFGRSTS_Msk (0x1UL << RCC_AHB2RSTSR_RAMCFGRSTS_Pos) /*!< 0x00001000 */ #define RCC_AHB2RSTSR_RAMCFGRSTS RCC_AHB2RSTSR_RAMCFGRSTS_Msk /*!< RAMCFG reset */ #define RCC_AHB2RSTSR_MDF1RSTS_Pos (16U) #define RCC_AHB2RSTSR_MDF1RSTS_Msk (0x1UL << RCC_AHB2RSTSR_MDF1RSTS_Pos) /*!< 0x00010000 */ #define RCC_AHB2RSTSR_MDF1RSTS RCC_AHB2RSTSR_MDF1RSTS_Msk /*!< MDF1 reset */ #define RCC_AHB2RSTSR_ADF1RSTS_Pos (17U) #define RCC_AHB2RSTSR_ADF1RSTS_Msk (0x1UL << RCC_AHB2RSTSR_ADF1RSTS_Pos) /*!< 0x00020000 */ #define RCC_AHB2RSTSR_ADF1RSTS RCC_AHB2RSTSR_ADF1RSTS_Msk /*!< ADF1 reset */ /**************** Bit definition for RCC_AHB3RSTSR register *****************/ #define RCC_AHB3RSTSR_RNGRSTS_Pos (0U) #define RCC_AHB3RSTSR_RNGRSTS_Msk (0x1UL << RCC_AHB3RSTSR_RNGRSTS_Pos) /*!< 0x00000001 */ #define RCC_AHB3RSTSR_RNGRSTS RCC_AHB3RSTSR_RNGRSTS_Msk /*!< RNG reset */ #define RCC_AHB3RSTSR_HASHRSTS_Pos (1U) #define RCC_AHB3RSTSR_HASHRSTS_Msk (0x1UL << RCC_AHB3RSTSR_HASHRSTS_Pos) /*!< 0x00000002 */ #define RCC_AHB3RSTSR_HASHRSTS RCC_AHB3RSTSR_HASHRSTS_Msk /*!< HASH reset */ #define RCC_AHB3RSTSR_CRYPRSTS_Pos (2U) #define RCC_AHB3RSTSR_CRYPRSTS_Msk (0x1UL << RCC_AHB3RSTSR_CRYPRSTS_Pos) /*!< 0x00000004 */ #define RCC_AHB3RSTSR_CRYPRSTS RCC_AHB3RSTSR_CRYPRSTS_Msk /*!< CRYP reset */ #define RCC_AHB3RSTSR_SAESRSTS_Pos (4U) #define RCC_AHB3RSTSR_SAESRSTS_Msk (0x1UL << RCC_AHB3RSTSR_SAESRSTS_Pos) /*!< 0x00000010 */ #define RCC_AHB3RSTSR_SAESRSTS RCC_AHB3RSTSR_SAESRSTS_Msk /*!< SAES reset */ #define RCC_AHB3RSTSR_PKARSTS_Pos (8U) #define RCC_AHB3RSTSR_PKARSTS_Msk (0x1UL << RCC_AHB3RSTSR_PKARSTS_Pos) /*!< 0x00000100 */ #define RCC_AHB3RSTSR_PKARSTS RCC_AHB3RSTSR_PKARSTS_Msk /*!< PKA reset */ #define RCC_AHB3RSTSR_IACRSTS_Pos (10U) #define RCC_AHB3RSTSR_IACRSTS_Msk (0x1UL << RCC_AHB3RSTSR_IACRSTS_Pos) /*!< 0x00000400 */ #define RCC_AHB3RSTSR_IACRSTS RCC_AHB3RSTSR_IACRSTS_Msk /*!< IAC reset */ /**************** Bit definition for RCC_AHB4RSTSR register *****************/ #define RCC_AHB4RSTSR_GPIOARSTS_Pos (0U) #define RCC_AHB4RSTSR_GPIOARSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOARSTS_Pos)/*!< 0x00000001 */ #define RCC_AHB4RSTSR_GPIOARSTS RCC_AHB4RSTSR_GPIOARSTS_Msk /*!< GPIO A reset */ #define RCC_AHB4RSTSR_GPIOBRSTS_Pos (1U) #define RCC_AHB4RSTSR_GPIOBRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOBRSTS_Pos)/*!< 0x00000002 */ #define RCC_AHB4RSTSR_GPIOBRSTS RCC_AHB4RSTSR_GPIOBRSTS_Msk /*!< GPIO B reset */ #define RCC_AHB4RSTSR_GPIOCRSTS_Pos (2U) #define RCC_AHB4RSTSR_GPIOCRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOCRSTS_Pos)/*!< 0x00000004 */ #define RCC_AHB4RSTSR_GPIOCRSTS RCC_AHB4RSTSR_GPIOCRSTS_Msk /*!< GPIO C reset */ #define RCC_AHB4RSTSR_GPIODRSTS_Pos (3U) #define RCC_AHB4RSTSR_GPIODRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIODRSTS_Pos)/*!< 0x00000008 */ #define RCC_AHB4RSTSR_GPIODRSTS RCC_AHB4RSTSR_GPIODRSTS_Msk /*!< GPIO D reset */ #define RCC_AHB4RSTSR_GPIOERSTS_Pos (4U) #define RCC_AHB4RSTSR_GPIOERSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOERSTS_Pos)/*!< 0x00000010 */ #define RCC_AHB4RSTSR_GPIOERSTS RCC_AHB4RSTSR_GPIOERSTS_Msk /*!< GPIO E reset */ #define RCC_AHB4RSTSR_GPIOFRSTS_Pos (5U) #define RCC_AHB4RSTSR_GPIOFRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOFRSTS_Pos)/*!< 0x00000020 */ #define RCC_AHB4RSTSR_GPIOFRSTS RCC_AHB4RSTSR_GPIOFRSTS_Msk /*!< GPIO F reset */ #define RCC_AHB4RSTSR_GPIOGRSTS_Pos (6U) #define RCC_AHB4RSTSR_GPIOGRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOGRSTS_Pos)/*!< 0x00000040 */ #define RCC_AHB4RSTSR_GPIOGRSTS RCC_AHB4RSTSR_GPIOGRSTS_Msk /*!< GPIO G reset */ #define RCC_AHB4RSTSR_GPIOHRSTS_Pos (7U) #define RCC_AHB4RSTSR_GPIOHRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOHRSTS_Pos)/*!< 0x00000080 */ #define RCC_AHB4RSTSR_GPIOHRSTS RCC_AHB4RSTSR_GPIOHRSTS_Msk /*!< GPIO H reset */ #define RCC_AHB4RSTSR_GPIONRSTS_Pos (13U) #define RCC_AHB4RSTSR_GPIONRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIONRSTS_Pos)/*!< 0x00002000 */ #define RCC_AHB4RSTSR_GPIONRSTS RCC_AHB4RSTSR_GPIONRSTS_Msk /*!< GPIO N reset */ #define RCC_AHB4RSTSR_GPIOORSTS_Pos (14U) #define RCC_AHB4RSTSR_GPIOORSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOORSTS_Pos)/*!< 0x00004000 */ #define RCC_AHB4RSTSR_GPIOORSTS RCC_AHB4RSTSR_GPIOORSTS_Msk /*!< GPIO O reset */ #define RCC_AHB4RSTSR_GPIOPRSTS_Pos (15U) #define RCC_AHB4RSTSR_GPIOPRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOPRSTS_Pos)/*!< 0x00008000 */ #define RCC_AHB4RSTSR_GPIOPRSTS RCC_AHB4RSTSR_GPIOPRSTS_Msk /*!< GPIO P reset */ #define RCC_AHB4RSTSR_GPIOQRSTS_Pos (16U) #define RCC_AHB4RSTSR_GPIOQRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOQRSTS_Pos)/*!< 0x00010000 */ #define RCC_AHB4RSTSR_GPIOQRSTS RCC_AHB4RSTSR_GPIOQRSTS_Msk /*!< GPIO Q reset */ #define RCC_AHB4RSTSR_PWRRSTS_Pos (18U) #define RCC_AHB4RSTSR_PWRRSTS_Msk (0x1UL << RCC_AHB4RSTSR_PWRRSTS_Pos) /*!< 0x00040000 */ #define RCC_AHB4RSTSR_PWRRSTS RCC_AHB4RSTSR_PWRRSTS_Msk /*!< PWR reset */ #define RCC_AHB4RSTSR_CRCRSTS_Pos (19U) #define RCC_AHB4RSTSR_CRCRSTS_Msk (0x1UL << RCC_AHB4RSTSR_CRCRSTS_Pos) /*!< 0x00080000 */ #define RCC_AHB4RSTSR_CRCRSTS RCC_AHB4RSTSR_CRCRSTS_Msk /*!< CRC reset */ /**************** Bit definition for RCC_AHB5RSTSR register *****************/ #define RCC_AHB5RSTSR_HPDMA1RSTS_Pos (0U) #define RCC_AHB5RSTSR_HPDMA1RSTS_Msk (0x1UL << RCC_AHB5RSTSR_HPDMA1RSTS_Pos) /*!< 0x00000001 */ #define RCC_AHB5RSTSR_HPDMA1RSTS RCC_AHB5RSTSR_HPDMA1RSTS_Msk /*!< HPDMA1 reset */ #define RCC_AHB5RSTSR_DMA2DRSTS_Pos (1U) #define RCC_AHB5RSTSR_DMA2DRSTS_Msk (0x1UL << RCC_AHB5RSTSR_DMA2DRSTS_Pos)/*!< 0x00000002 */ #define RCC_AHB5RSTSR_DMA2DRSTS RCC_AHB5RSTSR_DMA2DRSTS_Msk /*!< DMA2D reset */ #define RCC_AHB5RSTSR_JPEGRSTS_Pos (3U) #define RCC_AHB5RSTSR_JPEGRSTS_Msk (0x1UL << RCC_AHB5RSTSR_JPEGRSTS_Pos) /*!< 0x00000008 */ #define RCC_AHB5RSTSR_JPEGRSTS RCC_AHB5RSTSR_JPEGRSTS_Msk /*!< JPEG reset */ #define RCC_AHB5RSTSR_FMCRSTS_Pos (4U) #define RCC_AHB5RSTSR_FMCRSTS_Msk (0x1UL << RCC_AHB5RSTSR_FMCRSTS_Pos) /*!< 0x00000010 */ #define RCC_AHB5RSTSR_FMCRSTS RCC_AHB5RSTSR_FMCRSTS_Msk /*!< FMC reset */ #define RCC_AHB5RSTSR_XSPI1RSTS_Pos (5U) #define RCC_AHB5RSTSR_XSPI1RSTS_Msk (0x1UL << RCC_AHB5RSTSR_XSPI1RSTS_Pos)/*!< 0x00000020 */ #define RCC_AHB5RSTSR_XSPI1RSTS RCC_AHB5RSTSR_XSPI1RSTS_Msk /*!< XSPI1 reset */ #define RCC_AHB5RSTSR_PSSIRSTS_Pos (6U) #define RCC_AHB5RSTSR_PSSIRSTS_Msk (0x1UL << RCC_AHB5RSTSR_PSSIRSTS_Pos) /*!< 0x00000040 */ #define RCC_AHB5RSTSR_PSSIRSTS RCC_AHB5RSTSR_PSSIRSTS_Msk /*!< PSSI reset */ #define RCC_AHB5RSTSR_SDMMC2RSTS_Pos (7U) #define RCC_AHB5RSTSR_SDMMC2RSTS_Msk (0x1UL << RCC_AHB5RSTSR_SDMMC2RSTS_Pos) /*!< 0x00000080 */ #define RCC_AHB5RSTSR_SDMMC2RSTS RCC_AHB5RSTSR_SDMMC2RSTS_Msk /*!< SDMMC2 reset */ #define RCC_AHB5RSTSR_SDMMC1RSTS_Pos (8U) #define RCC_AHB5RSTSR_SDMMC1RSTS_Msk (0x1UL << RCC_AHB5RSTSR_SDMMC1RSTS_Pos) /*!< 0x00000100 */ #define RCC_AHB5RSTSR_SDMMC1RSTS RCC_AHB5RSTSR_SDMMC1RSTS_Msk /*!< SDMMC1 reset */ #define RCC_AHB5RSTSR_XSPI2RSTS_Pos (12U) #define RCC_AHB5RSTSR_XSPI2RSTS_Msk (0x1UL << RCC_AHB5RSTSR_XSPI2RSTS_Pos)/*!< 0x00001000 */ #define RCC_AHB5RSTSR_XSPI2RSTS RCC_AHB5RSTSR_XSPI2RSTS_Msk /*!< XSPI2 reset */ #define RCC_AHB5RSTSR_XSPIMRSTS_Pos (13U) #define RCC_AHB5RSTSR_XSPIMRSTS_Msk (0x1UL << RCC_AHB5RSTSR_XSPIMRSTS_Pos)/*!< 0x00002000 */ #define RCC_AHB5RSTSR_XSPIMRSTS RCC_AHB5RSTSR_XSPIMRSTS_Msk /*!< XSPIM reset */ #define RCC_AHB5RSTSR_XSPI3RSTS_Pos (17U) #define RCC_AHB5RSTSR_XSPI3RSTS_Msk (0x1UL << RCC_AHB5RSTSR_XSPI3RSTS_Pos)/*!< 0x00020000 */ #define RCC_AHB5RSTSR_XSPI3RSTS RCC_AHB5RSTSR_XSPI3RSTS_Msk /*!< XSPI3 reset */ #define RCC_AHB5RSTSR_GFXMMURSTS_Pos (19U) #define RCC_AHB5RSTSR_GFXMMURSTS_Msk (0x1UL << RCC_AHB5RSTSR_GFXMMURSTS_Pos) /*!< 0x00080000 */ #define RCC_AHB5RSTSR_GFXMMURSTS RCC_AHB5RSTSR_GFXMMURSTS_Msk /*!< GFXMMU reset */ #define RCC_AHB5RSTSR_GPU2DRSTS_Pos (20U) #define RCC_AHB5RSTSR_GPU2DRSTS_Msk (0x1UL << RCC_AHB5RSTSR_GPU2DRSTS_Pos)/*!< 0x00100000 */ #define RCC_AHB5RSTSR_GPU2DRSTS RCC_AHB5RSTSR_GPU2DRSTS_Msk /*!< GPU2D reset */ #define RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Pos (23U) #define RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Msk (0x1UL << RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Pos) /*!< 0x00800000 */ #define RCC_AHB5RSTSR_OTG1PHYCTLRSTS RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Msk /*!< OTG1PHYCTL reset */ #define RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Pos (24U) #define RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Msk (0x1UL << RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Pos) /*!< 0x01000000 */ #define RCC_AHB5RSTSR_OTG2PHYCTLRSTS RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Msk /*!< OTG2PHYCTL reset */ #define RCC_AHB5RSTSR_ETH1RSTS_Pos (25U) #define RCC_AHB5RSTSR_ETH1RSTS_Msk (0x1UL << RCC_AHB5RSTSR_ETH1RSTS_Pos) /*!< 0x02000000 */ #define RCC_AHB5RSTSR_ETH1RSTS RCC_AHB5RSTSR_ETH1RSTS_Msk /*!< ETH1 reset */ #define RCC_AHB5RSTSR_OTG1RSTS_Pos (26U) #define RCC_AHB5RSTSR_OTG1RSTS_Msk (0x1UL << RCC_AHB5RSTSR_OTG1RSTS_Pos) /*!< 0x04000000 */ #define RCC_AHB5RSTSR_OTG1RSTS RCC_AHB5RSTSR_OTG1RSTS_Msk /*!< OTG1 reset */ #define RCC_AHB5RSTSR_OTGPHY1RSTS_Pos (27U) #define RCC_AHB5RSTSR_OTGPHY1RSTS_Msk (0x1UL << RCC_AHB5RSTSR_OTGPHY1RSTS_Pos) /*!< 0x08000000 */ #define RCC_AHB5RSTSR_OTGPHY1RSTS RCC_AHB5RSTSR_OTGPHY1RSTS_Msk /*!< OTGPHY1 reset */ #define RCC_AHB5RSTSR_OTGPHY2RSTS_Pos (28U) #define RCC_AHB5RSTSR_OTGPHY2RSTS_Msk (0x1UL << RCC_AHB5RSTSR_OTGPHY2RSTS_Pos) /*!< 0x10000000 */ #define RCC_AHB5RSTSR_OTGPHY2RSTS RCC_AHB5RSTSR_OTGPHY2RSTS_Msk /*!< OTGPHY2 reset */ #define RCC_AHB5RSTSR_OTG2RSTS_Pos (29U) #define RCC_AHB5RSTSR_OTG2RSTS_Msk (0x1UL << RCC_AHB5RSTSR_OTG2RSTS_Pos) /*!< 0x20000000 */ #define RCC_AHB5RSTSR_OTG2RSTS RCC_AHB5RSTSR_OTG2RSTS_Msk /*!< OTG2 reset */ #define RCC_AHB5RSTSR_CACHEAXIRSTS_Pos (30U) #define RCC_AHB5RSTSR_CACHEAXIRSTS_Msk (0x1UL << RCC_AHB5RSTSR_CACHEAXIRSTS_Pos) /*!< 0x40000000 */ #define RCC_AHB5RSTSR_CACHEAXIRSTS RCC_AHB5RSTSR_CACHEAXIRSTS_Msk /*!< CACHEAXI reset */ #define RCC_AHB5RSTSR_NPURSTS_Pos (31U) #define RCC_AHB5RSTSR_NPURSTS_Msk (0x1UL << RCC_AHB5RSTSR_NPURSTS_Pos) /*!< 0x80000000 */ #define RCC_AHB5RSTSR_NPURSTS RCC_AHB5RSTSR_NPURSTS_Msk /*!< NPU reset */ /**************** Bit definition for RCC_APB1RSTSR1 register ****************/ #define RCC_APB1RSTSR1_TIM2RSTS_Pos (0U) #define RCC_APB1RSTSR1_TIM2RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM2RSTS_Pos)/*!< 0x00000001 */ #define RCC_APB1RSTSR1_TIM2RSTS RCC_APB1RSTSR1_TIM2RSTS_Msk /*!< TIM2 reset */ #define RCC_APB1RSTSR1_TIM3RSTS_Pos (1U) #define RCC_APB1RSTSR1_TIM3RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM3RSTS_Pos)/*!< 0x00000002 */ #define RCC_APB1RSTSR1_TIM3RSTS RCC_APB1RSTSR1_TIM3RSTS_Msk /*!< TIM3 reset */ #define RCC_APB1RSTSR1_TIM4RSTS_Pos (2U) #define RCC_APB1RSTSR1_TIM4RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM4RSTS_Pos)/*!< 0x00000004 */ #define RCC_APB1RSTSR1_TIM4RSTS RCC_APB1RSTSR1_TIM4RSTS_Msk /*!< TIM4 reset */ #define RCC_APB1RSTSR1_TIM5RSTS_Pos (3U) #define RCC_APB1RSTSR1_TIM5RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM5RSTS_Pos)/*!< 0x00000008 */ #define RCC_APB1RSTSR1_TIM5RSTS RCC_APB1RSTSR1_TIM5RSTS_Msk /*!< TIM5 reset */ #define RCC_APB1RSTSR1_TIM6RSTS_Pos (4U) #define RCC_APB1RSTSR1_TIM6RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM6RSTS_Pos)/*!< 0x00000010 */ #define RCC_APB1RSTSR1_TIM6RSTS RCC_APB1RSTSR1_TIM6RSTS_Msk /*!< TIM6 reset */ #define RCC_APB1RSTSR1_TIM7RSTS_Pos (5U) #define RCC_APB1RSTSR1_TIM7RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM7RSTS_Pos)/*!< 0x00000020 */ #define RCC_APB1RSTSR1_TIM7RSTS RCC_APB1RSTSR1_TIM7RSTS_Msk /*!< TIM7 reset */ #define RCC_APB1RSTSR1_TIM12RSTS_Pos (6U) #define RCC_APB1RSTSR1_TIM12RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM12RSTS_Pos) /*!< 0x00000040 */ #define RCC_APB1RSTSR1_TIM12RSTS RCC_APB1RSTSR1_TIM12RSTS_Msk /*!< TIM12 reset */ #define RCC_APB1RSTSR1_TIM13RSTS_Pos (7U) #define RCC_APB1RSTSR1_TIM13RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM13RSTS_Pos) /*!< 0x00000080 */ #define RCC_APB1RSTSR1_TIM13RSTS RCC_APB1RSTSR1_TIM13RSTS_Msk /*!< TIM13 reset */ #define RCC_APB1RSTSR1_TIM14RSTS_Pos (8U) #define RCC_APB1RSTSR1_TIM14RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM14RSTS_Pos) /*!< 0x00000100 */ #define RCC_APB1RSTSR1_TIM14RSTS RCC_APB1RSTSR1_TIM14RSTS_Msk /*!< TIM14 reset */ #define RCC_APB1RSTSR1_LPTIM1RSTS_Pos (9U) #define RCC_APB1RSTSR1_LPTIM1RSTS_Msk (0x1UL << RCC_APB1RSTSR1_LPTIM1RSTS_Pos) /*!< 0x00000200 */ #define RCC_APB1RSTSR1_LPTIM1RSTS RCC_APB1RSTSR1_LPTIM1RSTS_Msk /*!< LPTIM1 reset */ #define RCC_APB1RSTSR1_WWDGRSTS_Pos (11U) #define RCC_APB1RSTSR1_WWDGRSTS_Msk (0x1UL << RCC_APB1RSTSR1_WWDGRSTS_Pos)/*!< 0x00000800 */ #define RCC_APB1RSTSR1_WWDGRSTS RCC_APB1RSTSR1_WWDGRSTS_Msk /*!< WWDG reset */ #define RCC_APB1RSTSR1_TIM10RSTS_Pos (12U) #define RCC_APB1RSTSR1_TIM10RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM10RSTS_Pos) /*!< 0x00001000 */ #define RCC_APB1RSTSR1_TIM10RSTS RCC_APB1RSTSR1_TIM10RSTS_Msk /*!< TIM10 reset */ #define RCC_APB1RSTSR1_TIM11RSTS_Pos (13U) #define RCC_APB1RSTSR1_TIM11RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM11RSTS_Pos) /*!< 0x00002000 */ #define RCC_APB1RSTSR1_TIM11RSTS RCC_APB1RSTSR1_TIM11RSTS_Msk /*!< TIM11 reset */ #define RCC_APB1RSTSR1_SPI2RSTS_Pos (14U) #define RCC_APB1RSTSR1_SPI2RSTS_Msk (0x1UL << RCC_APB1RSTSR1_SPI2RSTS_Pos)/*!< 0x00004000 */ #define RCC_APB1RSTSR1_SPI2RSTS RCC_APB1RSTSR1_SPI2RSTS_Msk /*!< SPI2 reset */ #define RCC_APB1RSTSR1_SPI3RSTS_Pos (15U) #define RCC_APB1RSTSR1_SPI3RSTS_Msk (0x1UL << RCC_APB1RSTSR1_SPI3RSTS_Pos)/*!< 0x00008000 */ #define RCC_APB1RSTSR1_SPI3RSTS RCC_APB1RSTSR1_SPI3RSTS_Msk /*!< SPI3 reset */ #define RCC_APB1RSTSR1_SPDIFRX1RSTS_Pos (16U) #define RCC_APB1RSTSR1_SPDIFRX1RSTS_Msk (0x1UL << RCC_APB1RSTSR1_SPDIFRX1RSTS_Pos) /*!< 0x00010000 */ #define RCC_APB1RSTSR1_SPDIFRX1RSTS RCC_APB1RSTSR1_SPDIFRX1RSTS_Msk /*!< SPDIFRX1 reset */ #define RCC_APB1RSTSR1_USART2RSTS_Pos (17U) #define RCC_APB1RSTSR1_USART2RSTS_Msk (0x1UL << RCC_APB1RSTSR1_USART2RSTS_Pos) /*!< 0x00020000 */ #define RCC_APB1RSTSR1_USART2RSTS RCC_APB1RSTSR1_USART2RSTS_Msk /*!< USART2 reset */ #define RCC_APB1RSTSR1_USART3RSTS_Pos (18U) #define RCC_APB1RSTSR1_USART3RSTS_Msk (0x1UL << RCC_APB1RSTSR1_USART3RSTS_Pos) /*!< 0x00040000 */ #define RCC_APB1RSTSR1_USART3RSTS RCC_APB1RSTSR1_USART3RSTS_Msk /*!< USART3 reset */ #define RCC_APB1RSTSR1_UART4RSTS_Pos (19U) #define RCC_APB1RSTSR1_UART4RSTS_Msk (0x1UL << RCC_APB1RSTSR1_UART4RSTS_Pos) /*!< 0x00080000 */ #define RCC_APB1RSTSR1_UART4RSTS RCC_APB1RSTSR1_UART4RSTS_Msk /*!< UART4 reset */ #define RCC_APB1RSTSR1_UART5RSTS_Pos (20U) #define RCC_APB1RSTSR1_UART5RSTS_Msk (0x1UL << RCC_APB1RSTSR1_UART5RSTS_Pos) /*!< 0x00100000 */ #define RCC_APB1RSTSR1_UART5RSTS RCC_APB1RSTSR1_UART5RSTS_Msk /*!< UART5 reset */ #define RCC_APB1RSTSR1_I2C1RSTS_Pos (21U) #define RCC_APB1RSTSR1_I2C1RSTS_Msk (0x1UL << RCC_APB1RSTSR1_I2C1RSTS_Pos)/*!< 0x00200000 */ #define RCC_APB1RSTSR1_I2C1RSTS RCC_APB1RSTSR1_I2C1RSTS_Msk /*!< I2C1 reset */ #define RCC_APB1RSTSR1_I2C2RSTS_Pos (22U) #define RCC_APB1RSTSR1_I2C2RSTS_Msk (0x1UL << RCC_APB1RSTSR1_I2C2RSTS_Pos)/*!< 0x00400000 */ #define RCC_APB1RSTSR1_I2C2RSTS RCC_APB1RSTSR1_I2C2RSTS_Msk /*!< I2C2 reset */ #define RCC_APB1RSTSR1_I2C3RSTS_Pos (23U) #define RCC_APB1RSTSR1_I2C3RSTS_Msk (0x1UL << RCC_APB1RSTSR1_I2C3RSTS_Pos)/*!< 0x00800000 */ #define RCC_APB1RSTSR1_I2C3RSTS RCC_APB1RSTSR1_I2C3RSTS_Msk /*!< I2C3 reset */ #define RCC_APB1RSTSR1_I3C1RSTS_Pos (24U) #define RCC_APB1RSTSR1_I3C1RSTS_Msk (0x1UL << RCC_APB1RSTSR1_I3C1RSTS_Pos)/*!< 0x01000000 */ #define RCC_APB1RSTSR1_I3C1RSTS RCC_APB1RSTSR1_I3C1RSTS_Msk /*!< I3C1 reset */ #define RCC_APB1RSTSR1_I3C2RSTS_Pos (25U) #define RCC_APB1RSTSR1_I3C2RSTS_Msk (0x1UL << RCC_APB1RSTSR1_I3C2RSTS_Pos)/*!< 0x02000000 */ #define RCC_APB1RSTSR1_I3C2RSTS RCC_APB1RSTSR1_I3C2RSTS_Msk /*!< I3C2 reset */ #define RCC_APB1RSTSR1_UART7RSTS_Pos (30U) #define RCC_APB1RSTSR1_UART7RSTS_Msk (0x1UL << RCC_APB1RSTSR1_UART7RSTS_Pos) /*!< 0x40000000 */ #define RCC_APB1RSTSR1_UART7RSTS RCC_APB1RSTSR1_UART7RSTS_Msk /*!< UART7 reset */ #define RCC_APB1RSTSR1_UART8RSTS_Pos (31U) #define RCC_APB1RSTSR1_UART8RSTS_Msk (0x1UL << RCC_APB1RSTSR1_UART8RSTS_Pos) /*!< 0x80000000 */ #define RCC_APB1RSTSR1_UART8RSTS RCC_APB1RSTSR1_UART8RSTS_Msk /*!< UART8 reset */ /**************** Bit definition for RCC_APB1RSTSR2 register ****************/ #define RCC_APB1RSTSR2_MDIOSRSTS_Pos (5U) #define RCC_APB1RSTSR2_MDIOSRSTS_Msk (0x1UL << RCC_APB1RSTSR2_MDIOSRSTS_Pos) /*!< 0x00000020 */ #define RCC_APB1RSTSR2_MDIOSRSTS RCC_APB1RSTSR2_MDIOSRSTS_Msk /*!< MDIOS reset */ #define RCC_APB1RSTSR2_FDCANRSTS_Pos (8U) #define RCC_APB1RSTSR2_FDCANRSTS_Msk (0x1UL << RCC_APB1RSTSR2_FDCANRSTS_Pos) /*!< 0x00000100 */ #define RCC_APB1RSTSR2_FDCANRSTS RCC_APB1RSTSR2_FDCANRSTS_Msk /*!< FDCAN reset */ #define RCC_APB1RSTSR2_UCPD1RSTS_Pos (18U) #define RCC_APB1RSTSR2_UCPD1RSTS_Msk (0x1UL << RCC_APB1RSTSR2_UCPD1RSTS_Pos) /*!< 0x00040000 */ #define RCC_APB1RSTSR2_UCPD1RSTS RCC_APB1RSTSR2_UCPD1RSTS_Msk /*!< UCPD1 reset */ /**************** Bit definition for RCC_APB2RSTSR register *****************/ #define RCC_APB2RSTSR_TIM1RSTS_Pos (0U) #define RCC_APB2RSTSR_TIM1RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM1RSTS_Pos) /*!< 0x00000001 */ #define RCC_APB2RSTSR_TIM1RSTS RCC_APB2RSTSR_TIM1RSTS_Msk /*!< TIM1 reset */ #define RCC_APB2RSTSR_TIM8RSTS_Pos (1U) #define RCC_APB2RSTSR_TIM8RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM8RSTS_Pos) /*!< 0x00000002 */ #define RCC_APB2RSTSR_TIM8RSTS RCC_APB2RSTSR_TIM8RSTS_Msk /*!< TIM8 reset */ #define RCC_APB2RSTSR_USART1RSTS_Pos (4U) #define RCC_APB2RSTSR_USART1RSTS_Msk (0x1UL << RCC_APB2RSTSR_USART1RSTS_Pos) /*!< 0x00000010 */ #define RCC_APB2RSTSR_USART1RSTS RCC_APB2RSTSR_USART1RSTS_Msk /*!< USART1 reset */ #define RCC_APB2RSTSR_USART6RSTS_Pos (5U) #define RCC_APB2RSTSR_USART6RSTS_Msk (0x1UL << RCC_APB2RSTSR_USART6RSTS_Pos) /*!< 0x00000020 */ #define RCC_APB2RSTSR_USART6RSTS RCC_APB2RSTSR_USART6RSTS_Msk /*!< USART6 reset */ #define RCC_APB2RSTSR_UART9RSTS_Pos (6U) #define RCC_APB2RSTSR_UART9RSTS_Msk (0x1UL << RCC_APB2RSTSR_UART9RSTS_Pos)/*!< 0x00000040 */ #define RCC_APB2RSTSR_UART9RSTS RCC_APB2RSTSR_UART9RSTS_Msk /*!< UART9 reset */ #define RCC_APB2RSTSR_USART10RSTS_Pos (7U) #define RCC_APB2RSTSR_USART10RSTS_Msk (0x1UL << RCC_APB2RSTSR_USART10RSTS_Pos) /*!< 0x00000080 */ #define RCC_APB2RSTSR_USART10RSTS RCC_APB2RSTSR_USART10RSTS_Msk /*!< USART10 reset */ #define RCC_APB2RSTSR_SPI1RSTS_Pos (12U) #define RCC_APB2RSTSR_SPI1RSTS_Msk (0x1UL << RCC_APB2RSTSR_SPI1RSTS_Pos) /*!< 0x00001000 */ #define RCC_APB2RSTSR_SPI1RSTS RCC_APB2RSTSR_SPI1RSTS_Msk /*!< SPI1 reset */ #define RCC_APB2RSTSR_SPI4RSTS_Pos (13U) #define RCC_APB2RSTSR_SPI4RSTS_Msk (0x1UL << RCC_APB2RSTSR_SPI4RSTS_Pos) /*!< 0x00002000 */ #define RCC_APB2RSTSR_SPI4RSTS RCC_APB2RSTSR_SPI4RSTS_Msk /*!< SPI4 reset */ #define RCC_APB2RSTSR_TIM18RSTS_Pos (15U) #define RCC_APB2RSTSR_TIM18RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM18RSTS_Pos)/*!< 0x00008000 */ #define RCC_APB2RSTSR_TIM18RSTS RCC_APB2RSTSR_TIM18RSTS_Msk /*!< TIM18 reset */ #define RCC_APB2RSTSR_TIM15RSTS_Pos (16U) #define RCC_APB2RSTSR_TIM15RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM15RSTS_Pos)/*!< 0x00010000 */ #define RCC_APB2RSTSR_TIM15RSTS RCC_APB2RSTSR_TIM15RSTS_Msk /*!< TIM15 reset */ #define RCC_APB2RSTSR_TIM16RSTS_Pos (17U) #define RCC_APB2RSTSR_TIM16RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM16RSTS_Pos)/*!< 0x00020000 */ #define RCC_APB2RSTSR_TIM16RSTS RCC_APB2RSTSR_TIM16RSTS_Msk /*!< TIM16 reset */ #define RCC_APB2RSTSR_TIM17RSTS_Pos (18U) #define RCC_APB2RSTSR_TIM17RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM17RSTS_Pos)/*!< 0x00040000 */ #define RCC_APB2RSTSR_TIM17RSTS RCC_APB2RSTSR_TIM17RSTS_Msk /*!< TIM17 reset */ #define RCC_APB2RSTSR_TIM9RSTS_Pos (19U) #define RCC_APB2RSTSR_TIM9RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM9RSTS_Pos) /*!< 0x00080000 */ #define RCC_APB2RSTSR_TIM9RSTS RCC_APB2RSTSR_TIM9RSTS_Msk /*!< TIM9 reset */ #define RCC_APB2RSTSR_SPI5RSTS_Pos (20U) #define RCC_APB2RSTSR_SPI5RSTS_Msk (0x1UL << RCC_APB2RSTSR_SPI5RSTS_Pos) /*!< 0x00100000 */ #define RCC_APB2RSTSR_SPI5RSTS RCC_APB2RSTSR_SPI5RSTS_Msk /*!< SPI5 reset */ #define RCC_APB2RSTSR_SAI1RSTS_Pos (21U) #define RCC_APB2RSTSR_SAI1RSTS_Msk (0x1UL << RCC_APB2RSTSR_SAI1RSTS_Pos) /*!< 0x00200000 */ #define RCC_APB2RSTSR_SAI1RSTS RCC_APB2RSTSR_SAI1RSTS_Msk /*!< SAI1 reset */ #define RCC_APB2RSTSR_SAI2RSTS_Pos (22U) #define RCC_APB2RSTSR_SAI2RSTS_Msk (0x1UL << RCC_APB2RSTSR_SAI2RSTS_Pos) /*!< 0x00400000 */ #define RCC_APB2RSTSR_SAI2RSTS RCC_APB2RSTSR_SAI2RSTS_Msk /*!< SAI2 reset */ /**************** Bit definition for RCC_APB4RSTSR1 register ****************/ #define RCC_APB4RSTSR1_HDPRSTS_Pos (2U) #define RCC_APB4RSTSR1_HDPRSTS_Msk (0x1UL << RCC_APB4RSTSR1_HDPRSTS_Pos) /*!< 0x00000004 */ #define RCC_APB4RSTSR1_HDPRSTS RCC_APB4RSTSR1_HDPRSTS_Msk /*!< HDP reset */ #define RCC_APB4RSTSR1_LPUART1RSTS_Pos (3U) #define RCC_APB4RSTSR1_LPUART1RSTS_Msk (0x1UL << RCC_APB4RSTSR1_LPUART1RSTS_Pos) /*!< 0x00000008 */ #define RCC_APB4RSTSR1_LPUART1RSTS RCC_APB4RSTSR1_LPUART1RSTS_Msk /*!< LPUART1 reset */ #define RCC_APB4RSTSR1_SPI6RSTS_Pos (5U) #define RCC_APB4RSTSR1_SPI6RSTS_Msk (0x1UL << RCC_APB4RSTSR1_SPI6RSTS_Pos)/*!< 0x00000020 */ #define RCC_APB4RSTSR1_SPI6RSTS RCC_APB4RSTSR1_SPI6RSTS_Msk /*!< SPI6 reset */ #define RCC_APB4RSTSR1_I2C4RSTS_Pos (7U) #define RCC_APB4RSTSR1_I2C4RSTS_Msk (0x1UL << RCC_APB4RSTSR1_I2C4RSTS_Pos)/*!< 0x00000080 */ #define RCC_APB4RSTSR1_I2C4RSTS RCC_APB4RSTSR1_I2C4RSTS_Msk /*!< I2C4 reset */ #define RCC_APB4RSTSR1_LPTIM2RSTS_Pos (9U) #define RCC_APB4RSTSR1_LPTIM2RSTS_Msk (0x1UL << RCC_APB4RSTSR1_LPTIM2RSTS_Pos) /*!< 0x00000200 */ #define RCC_APB4RSTSR1_LPTIM2RSTS RCC_APB4RSTSR1_LPTIM2RSTS_Msk /*!< LPTIM2 reset */ #define RCC_APB4RSTSR1_LPTIM3RSTS_Pos (10U) #define RCC_APB4RSTSR1_LPTIM3RSTS_Msk (0x1UL << RCC_APB4RSTSR1_LPTIM3RSTS_Pos) /*!< 0x00000400 */ #define RCC_APB4RSTSR1_LPTIM3RSTS RCC_APB4RSTSR1_LPTIM3RSTS_Msk /*!< LPTIM3 reset */ #define RCC_APB4RSTSR1_LPTIM4RSTS_Pos (11U) #define RCC_APB4RSTSR1_LPTIM4RSTS_Msk (0x1UL << RCC_APB4RSTSR1_LPTIM4RSTS_Pos) /*!< 0x00000800 */ #define RCC_APB4RSTSR1_LPTIM4RSTS RCC_APB4RSTSR1_LPTIM4RSTS_Msk /*!< LPTIM4 reset */ #define RCC_APB4RSTSR1_LPTIM5RSTS_Pos (12U) #define RCC_APB4RSTSR1_LPTIM5RSTS_Msk (0x1UL << RCC_APB4RSTSR1_LPTIM5RSTS_Pos) /*!< 0x00001000 */ #define RCC_APB4RSTSR1_LPTIM5RSTS RCC_APB4RSTSR1_LPTIM5RSTS_Msk /*!< LPTIM5 reset */ #define RCC_APB4RSTSR1_VREFBUFRSTS_Pos (15U) #define RCC_APB4RSTSR1_VREFBUFRSTS_Msk (0x1UL << RCC_APB4RSTSR1_VREFBUFRSTS_Pos) /*!< 0x00008000 */ #define RCC_APB4RSTSR1_VREFBUFRSTS RCC_APB4RSTSR1_VREFBUFRSTS_Msk /*!< VREFBUF reset */ #define RCC_APB4RSTSR1_RTCRSTS_Pos (16U) #define RCC_APB4RSTSR1_RTCRSTS_Msk (0x1UL << RCC_APB4RSTSR1_RTCRSTS_Pos) /*!< 0x00010000 */ #define RCC_APB4RSTSR1_RTCRSTS RCC_APB4RSTSR1_RTCRSTS_Msk /*!< RTC reset */ /**************** Bit definition for RCC_APB4RSTSR2 register ****************/ #define RCC_APB4RSTSR2_SYSCFGRSTS_Pos (0U) #define RCC_APB4RSTSR2_SYSCFGRSTS_Msk (0x1UL << RCC_APB4RSTSR2_SYSCFGRSTS_Pos) /*!< 0x00000001 */ #define RCC_APB4RSTSR2_SYSCFGRSTS RCC_APB4RSTSR2_SYSCFGRSTS_Msk /*!< SYSCFG reset */ #define RCC_APB4RSTSR2_DTSRSTS_Pos (2U) #define RCC_APB4RSTSR2_DTSRSTS_Msk (0x1UL << RCC_APB4RSTSR2_DTSRSTS_Pos) /*!< 0x00000004 */ #define RCC_APB4RSTSR2_DTSRSTS RCC_APB4RSTSR2_DTSRSTS_Msk /*!< DTS reset */ /**************** Bit definition for RCC_APB5RSTSR register *****************/ #define RCC_APB5RSTSR_LTDCRSTS_Pos (1U) #define RCC_APB5RSTSR_LTDCRSTS_Msk (0x1UL << RCC_APB5RSTSR_LTDCRSTS_Pos) /*!< 0x00000002 */ #define RCC_APB5RSTSR_LTDCRSTS RCC_APB5RSTSR_LTDCRSTS_Msk /*!< LTDC reset */ #define RCC_APB5RSTSR_DCMIPPRSTS_Pos (2U) #define RCC_APB5RSTSR_DCMIPPRSTS_Msk (0x1UL << RCC_APB5RSTSR_DCMIPPRSTS_Pos) /*!< 0x00000004 */ #define RCC_APB5RSTSR_DCMIPPRSTS RCC_APB5RSTSR_DCMIPPRSTS_Msk /*!< DCMIPP reset */ #define RCC_APB5RSTSR_GFXTIMRSTS_Pos (4U) #define RCC_APB5RSTSR_GFXTIMRSTS_Msk (0x1UL << RCC_APB5RSTSR_GFXTIMRSTS_Pos) /*!< 0x00000010 */ #define RCC_APB5RSTSR_GFXTIMRSTS RCC_APB5RSTSR_GFXTIMRSTS_Msk /*!< GFXTIM reset */ #define RCC_APB5RSTSR_VENCRSTS_Pos (5U) #define RCC_APB5RSTSR_VENCRSTS_Msk (0x1UL << RCC_APB5RSTSR_VENCRSTS_Pos) /*!< 0x00000020 */ #define RCC_APB5RSTSR_VENCRSTS RCC_APB5RSTSR_VENCRSTS_Msk /*!< VENC reset */ #define RCC_APB5RSTSR_CSIRSTS_Pos (6U) #define RCC_APB5RSTSR_CSIRSTS_Msk (0x1UL << RCC_APB5RSTSR_CSIRSTS_Pos) /*!< 0x00000040 */ #define RCC_APB5RSTSR_CSIRSTS RCC_APB5RSTSR_CSIRSTS_Msk /*!< CSI reset */ /***************** Bit definition for RCC_DIVENSR register ******************/ #define RCC_DIVENSR_IC1ENS_Pos (0U) #define RCC_DIVENSR_IC1ENS_Msk (0x1UL << RCC_DIVENSR_IC1ENS_Pos) /*!< 0x00000001 */ #define RCC_DIVENSR_IC1ENS RCC_DIVENSR_IC1ENS_Msk /*!< IC1 enable */ #define RCC_DIVENSR_IC2ENS_Pos (1U) #define RCC_DIVENSR_IC2ENS_Msk (0x1UL << RCC_DIVENSR_IC2ENS_Pos) /*!< 0x00000002 */ #define RCC_DIVENSR_IC2ENS RCC_DIVENSR_IC2ENS_Msk /*!< IC2 enable */ #define RCC_DIVENSR_IC3ENS_Pos (2U) #define RCC_DIVENSR_IC3ENS_Msk (0x1UL << RCC_DIVENSR_IC3ENS_Pos) /*!< 0x00000004 */ #define RCC_DIVENSR_IC3ENS RCC_DIVENSR_IC3ENS_Msk /*!< IC3 enable */ #define RCC_DIVENSR_IC4ENS_Pos (3U) #define RCC_DIVENSR_IC4ENS_Msk (0x1UL << RCC_DIVENSR_IC4ENS_Pos) /*!< 0x00000008 */ #define RCC_DIVENSR_IC4ENS RCC_DIVENSR_IC4ENS_Msk /*!< IC4 enable */ #define RCC_DIVENSR_IC5ENS_Pos (4U) #define RCC_DIVENSR_IC5ENS_Msk (0x1UL << RCC_DIVENSR_IC5ENS_Pos) /*!< 0x00000010 */ #define RCC_DIVENSR_IC5ENS RCC_DIVENSR_IC5ENS_Msk /*!< IC5 enable */ #define RCC_DIVENSR_IC6ENS_Pos (5U) #define RCC_DIVENSR_IC6ENS_Msk (0x1UL << RCC_DIVENSR_IC6ENS_Pos) /*!< 0x00000020 */ #define RCC_DIVENSR_IC6ENS RCC_DIVENSR_IC6ENS_Msk /*!< IC6 enable */ #define RCC_DIVENSR_IC7ENS_Pos (6U) #define RCC_DIVENSR_IC7ENS_Msk (0x1UL << RCC_DIVENSR_IC7ENS_Pos) /*!< 0x00000040 */ #define RCC_DIVENSR_IC7ENS RCC_DIVENSR_IC7ENS_Msk /*!< IC7 enable */ #define RCC_DIVENSR_IC8ENS_Pos (7U) #define RCC_DIVENSR_IC8ENS_Msk (0x1UL << RCC_DIVENSR_IC8ENS_Pos) /*!< 0x00000080 */ #define RCC_DIVENSR_IC8ENS RCC_DIVENSR_IC8ENS_Msk /*!< IC8 enable */ #define RCC_DIVENSR_IC9ENS_Pos (8U) #define RCC_DIVENSR_IC9ENS_Msk (0x1UL << RCC_DIVENSR_IC9ENS_Pos) /*!< 0x00000100 */ #define RCC_DIVENSR_IC9ENS RCC_DIVENSR_IC9ENS_Msk /*!< IC9 enable */ #define RCC_DIVENSR_IC10ENS_Pos (9U) #define RCC_DIVENSR_IC10ENS_Msk (0x1UL << RCC_DIVENSR_IC10ENS_Pos) /*!< 0x00000200 */ #define RCC_DIVENSR_IC10ENS RCC_DIVENSR_IC10ENS_Msk /*!< IC10 enable */ #define RCC_DIVENSR_IC11ENS_Pos (10U) #define RCC_DIVENSR_IC11ENS_Msk (0x1UL << RCC_DIVENSR_IC11ENS_Pos) /*!< 0x00000400 */ #define RCC_DIVENSR_IC11ENS RCC_DIVENSR_IC11ENS_Msk /*!< IC11 enable */ #define RCC_DIVENSR_IC12ENS_Pos (11U) #define RCC_DIVENSR_IC12ENS_Msk (0x1UL << RCC_DIVENSR_IC12ENS_Pos) /*!< 0x00000800 */ #define RCC_DIVENSR_IC12ENS RCC_DIVENSR_IC12ENS_Msk /*!< IC12 enable */ #define RCC_DIVENSR_IC13ENS_Pos (12U) #define RCC_DIVENSR_IC13ENS_Msk (0x1UL << RCC_DIVENSR_IC13ENS_Pos) /*!< 0x00001000 */ #define RCC_DIVENSR_IC13ENS RCC_DIVENSR_IC13ENS_Msk /*!< IC13 enable */ #define RCC_DIVENSR_IC14ENS_Pos (13U) #define RCC_DIVENSR_IC14ENS_Msk (0x1UL << RCC_DIVENSR_IC14ENS_Pos) /*!< 0x00002000 */ #define RCC_DIVENSR_IC14ENS RCC_DIVENSR_IC14ENS_Msk /*!< IC14 enable */ #define RCC_DIVENSR_IC15ENS_Pos (14U) #define RCC_DIVENSR_IC15ENS_Msk (0x1UL << RCC_DIVENSR_IC15ENS_Pos) /*!< 0x00004000 */ #define RCC_DIVENSR_IC15ENS RCC_DIVENSR_IC15ENS_Msk /*!< IC15 enable */ #define RCC_DIVENSR_IC16ENS_Pos (15U) #define RCC_DIVENSR_IC16ENS_Msk (0x1UL << RCC_DIVENSR_IC16ENS_Pos) /*!< 0x00008000 */ #define RCC_DIVENSR_IC16ENS RCC_DIVENSR_IC16ENS_Msk /*!< IC16 enable */ #define RCC_DIVENSR_IC17ENS_Pos (16U) #define RCC_DIVENSR_IC17ENS_Msk (0x1UL << RCC_DIVENSR_IC17ENS_Pos) /*!< 0x00010000 */ #define RCC_DIVENSR_IC17ENS RCC_DIVENSR_IC17ENS_Msk /*!< IC17 enable */ #define RCC_DIVENSR_IC18ENS_Pos (17U) #define RCC_DIVENSR_IC18ENS_Msk (0x1UL << RCC_DIVENSR_IC18ENS_Pos) /*!< 0x00020000 */ #define RCC_DIVENSR_IC18ENS RCC_DIVENSR_IC18ENS_Msk /*!< IC18 enable */ #define RCC_DIVENSR_IC19ENS_Pos (18U) #define RCC_DIVENSR_IC19ENS_Msk (0x1UL << RCC_DIVENSR_IC19ENS_Pos) /*!< 0x00040000 */ #define RCC_DIVENSR_IC19ENS RCC_DIVENSR_IC19ENS_Msk /*!< IC19 enable */ #define RCC_DIVENSR_IC20ENS_Pos (19U) #define RCC_DIVENSR_IC20ENS_Msk (0x1UL << RCC_DIVENSR_IC20ENS_Pos) /*!< 0x00080000 */ #define RCC_DIVENSR_IC20ENS RCC_DIVENSR_IC20ENS_Msk /*!< IC20 enable */ /***************** Bit definition for RCC_BUSENSR register ******************/ #define RCC_BUSENSR_ACLKNENS_Pos (0U) #define RCC_BUSENSR_ACLKNENS_Msk (0x1UL << RCC_BUSENSR_ACLKNENS_Pos) /*!< 0x00000001 */ #define RCC_BUSENSR_ACLKNENS RCC_BUSENSR_ACLKNENS_Msk /*!< ACLKN enable */ #define RCC_BUSENSR_ACLKNCENS_Pos (1U) #define RCC_BUSENSR_ACLKNCENS_Msk (0x1UL << RCC_BUSENSR_ACLKNCENS_Pos) /*!< 0x00000002 */ #define RCC_BUSENSR_ACLKNCENS RCC_BUSENSR_ACLKNCENS_Msk /*!< ACLKNC enable */ #define RCC_BUSENSR_AHBMENS_Pos (2U) #define RCC_BUSENSR_AHBMENS_Msk (0x1UL << RCC_BUSENSR_AHBMENS_Pos) /*!< 0x00000004 */ #define RCC_BUSENSR_AHBMENS RCC_BUSENSR_AHBMENS_Msk /*!< AHBM enable */ #define RCC_BUSENSR_AHB1ENS_Pos (3U) #define RCC_BUSENSR_AHB1ENS_Msk (0x1UL << RCC_BUSENSR_AHB1ENS_Pos) /*!< 0x00000008 */ #define RCC_BUSENSR_AHB1ENS RCC_BUSENSR_AHB1ENS_Msk /*!< AHB1 enable */ #define RCC_BUSENSR_AHB2ENS_Pos (4U) #define RCC_BUSENSR_AHB2ENS_Msk (0x1UL << RCC_BUSENSR_AHB2ENS_Pos) /*!< 0x00000010 */ #define RCC_BUSENSR_AHB2ENS RCC_BUSENSR_AHB2ENS_Msk /*!< AHB2 enable */ #define RCC_BUSENSR_AHB3ENS_Pos (5U) #define RCC_BUSENSR_AHB3ENS_Msk (0x1UL << RCC_BUSENSR_AHB3ENS_Pos) /*!< 0x00000020 */ #define RCC_BUSENSR_AHB3ENS RCC_BUSENSR_AHB3ENS_Msk /*!< AHB3 enable */ #define RCC_BUSENSR_AHB4ENS_Pos (6U) #define RCC_BUSENSR_AHB4ENS_Msk (0x1UL << RCC_BUSENSR_AHB4ENS_Pos) /*!< 0x00000040 */ #define RCC_BUSENSR_AHB4ENS RCC_BUSENSR_AHB4ENS_Msk /*!< AHB4 enable */ #define RCC_BUSENSR_AHB5ENS_Pos (7U) #define RCC_BUSENSR_AHB5ENS_Msk (0x1UL << RCC_BUSENSR_AHB5ENS_Pos) /*!< 0x00000080 */ #define RCC_BUSENSR_AHB5ENS RCC_BUSENSR_AHB5ENS_Msk /*!< AHB5 enable */ #define RCC_BUSENSR_APB1ENS_Pos (8U) #define RCC_BUSENSR_APB1ENS_Msk (0x1UL << RCC_BUSENSR_APB1ENS_Pos) /*!< 0x00000100 */ #define RCC_BUSENSR_APB1ENS RCC_BUSENSR_APB1ENS_Msk /*!< APB1 enable */ #define RCC_BUSENSR_APB2ENS_Pos (9U) #define RCC_BUSENSR_APB2ENS_Msk (0x1UL << RCC_BUSENSR_APB2ENS_Pos) /*!< 0x00000200 */ #define RCC_BUSENSR_APB2ENS RCC_BUSENSR_APB2ENS_Msk /*!< APB2 enable */ #define RCC_BUSENSR_APB3ENS_Pos (10U) #define RCC_BUSENSR_APB3ENS_Msk (0x1UL << RCC_BUSENSR_APB3ENS_Pos) /*!< 0x00000400 */ #define RCC_BUSENSR_APB3ENS RCC_BUSENSR_APB3ENS_Msk /*!< APB3 enable */ #define RCC_BUSENSR_APB4ENS_Pos (11U) #define RCC_BUSENSR_APB4ENS_Msk (0x1UL << RCC_BUSENSR_APB4ENS_Pos) /*!< 0x00000800 */ #define RCC_BUSENSR_APB4ENS RCC_BUSENSR_APB4ENS_Msk /*!< APB4 enable */ #define RCC_BUSENSR_APB5ENS_Pos (12U) #define RCC_BUSENSR_APB5ENS_Msk (0x1UL << RCC_BUSENSR_APB5ENS_Pos) /*!< 0x00001000 */ #define RCC_BUSENSR_APB5ENS RCC_BUSENSR_APB5ENS_Msk /*!< APB5 enable */ /***************** Bit definition for RCC_MISCENSR register *****************/ #define RCC_MISCENSR_DBGENS_Pos (0U) #define RCC_MISCENSR_DBGENS_Msk (0x1UL << RCC_MISCENSR_DBGENS_Pos) /*!< 0x00000001 */ #define RCC_MISCENSR_DBGENS RCC_MISCENSR_DBGENS_Msk /*!< DBG enable */ #define RCC_MISCENSR_MCO1ENS_Pos (1U) #define RCC_MISCENSR_MCO1ENS_Msk (0x1UL << RCC_MISCENSR_MCO1ENS_Pos) /*!< 0x00000002 */ #define RCC_MISCENSR_MCO1ENS RCC_MISCENSR_MCO1ENS_Msk /*!< MCO1 enable */ #define RCC_MISCENSR_MCO2ENS_Pos (2U) #define RCC_MISCENSR_MCO2ENS_Msk (0x1UL << RCC_MISCENSR_MCO2ENS_Pos) /*!< 0x00000004 */ #define RCC_MISCENSR_MCO2ENS RCC_MISCENSR_MCO2ENS_Msk /*!< MCO2 enable */ #define RCC_MISCENSR_XSPIPHYCOMPENS_Pos (3U) #define RCC_MISCENSR_XSPIPHYCOMPENS_Msk (0x1UL << RCC_MISCENSR_XSPIPHYCOMPENS_Pos) /*!< 0x00000008 */ #define RCC_MISCENSR_XSPIPHYCOMPENS RCC_MISCENSR_XSPIPHYCOMPENS_Msk /*!< XSPIPHYCOMP enable */ #define RCC_MISCENSR_PERENS_Pos (6U) #define RCC_MISCENSR_PERENS_Msk (0x1UL << RCC_MISCENSR_PERENS_Pos) /*!< 0x00000040 */ #define RCC_MISCENSR_PERENS RCC_MISCENSR_PERENS_Msk /*!< PER enable */ /***************** Bit definition for RCC_MEMENSR register ******************/ #define RCC_MEMENSR_AXISRAM3ENS_Pos (0U) #define RCC_MEMENSR_AXISRAM3ENS_Msk (0x1UL << RCC_MEMENSR_AXISRAM3ENS_Pos)/*!< 0x00000001 */ #define RCC_MEMENSR_AXISRAM3ENS RCC_MEMENSR_AXISRAM3ENS_Msk /*!< AXISRAM3 enable */ #define RCC_MEMENSR_AXISRAM4ENS_Pos (1U) #define RCC_MEMENSR_AXISRAM4ENS_Msk (0x1UL << RCC_MEMENSR_AXISRAM4ENS_Pos)/*!< 0x00000002 */ #define RCC_MEMENSR_AXISRAM4ENS RCC_MEMENSR_AXISRAM4ENS_Msk /*!< AXISRAM4 enable */ #define RCC_MEMENSR_AXISRAM5ENS_Pos (2U) #define RCC_MEMENSR_AXISRAM5ENS_Msk (0x1UL << RCC_MEMENSR_AXISRAM5ENS_Pos)/*!< 0x00000004 */ #define RCC_MEMENSR_AXISRAM5ENS RCC_MEMENSR_AXISRAM5ENS_Msk /*!< AXISRAM5 enable */ #define RCC_MEMENSR_AXISRAM6ENS_Pos (3U) #define RCC_MEMENSR_AXISRAM6ENS_Msk (0x1UL << RCC_MEMENSR_AXISRAM6ENS_Pos)/*!< 0x00000008 */ #define RCC_MEMENSR_AXISRAM6ENS RCC_MEMENSR_AXISRAM6ENS_Msk /*!< AXISRAM6 enable */ #define RCC_MEMENSR_AHBSRAM1ENS_Pos (4U) #define RCC_MEMENSR_AHBSRAM1ENS_Msk (0x1UL << RCC_MEMENSR_AHBSRAM1ENS_Pos)/*!< 0x00000010 */ #define RCC_MEMENSR_AHBSRAM1ENS RCC_MEMENSR_AHBSRAM1ENS_Msk /*!< AHBSRAM1 enable */ #define RCC_MEMENSR_AHBSRAM2ENS_Pos (5U) #define RCC_MEMENSR_AHBSRAM2ENS_Msk (0x1UL << RCC_MEMENSR_AHBSRAM2ENS_Pos)/*!< 0x00000020 */ #define RCC_MEMENSR_AHBSRAM2ENS RCC_MEMENSR_AHBSRAM2ENS_Msk /*!< AHBSRAM2 enable */ #define RCC_MEMENSR_BKPSRAMENS_Pos (6U) #define RCC_MEMENSR_BKPSRAMENS_Msk (0x1UL << RCC_MEMENSR_BKPSRAMENS_Pos) /*!< 0x00000040 */ #define RCC_MEMENSR_BKPSRAMENS RCC_MEMENSR_BKPSRAMENS_Msk /*!< BKPSRAM enable */ #define RCC_MEMENSR_AXISRAM1ENS_Pos (7U) #define RCC_MEMENSR_AXISRAM1ENS_Msk (0x1UL << RCC_MEMENSR_AXISRAM1ENS_Pos)/*!< 0x00000080 */ #define RCC_MEMENSR_AXISRAM1ENS RCC_MEMENSR_AXISRAM1ENS_Msk /*!< AXISRAM1 enable */ #define RCC_MEMENSR_AXISRAM2ENS_Pos (8U) #define RCC_MEMENSR_AXISRAM2ENS_Msk (0x1UL << RCC_MEMENSR_AXISRAM2ENS_Pos)/*!< 0x00000100 */ #define RCC_MEMENSR_AXISRAM2ENS RCC_MEMENSR_AXISRAM2ENS_Msk /*!< AXISRAM2 enable */ #define RCC_MEMENSR_FLEXRAMENS_Pos (9U) #define RCC_MEMENSR_FLEXRAMENS_Msk (0x1UL << RCC_MEMENSR_FLEXRAMENS_Pos) /*!< 0x00000200 */ #define RCC_MEMENSR_FLEXRAMENS RCC_MEMENSR_FLEXRAMENS_Msk /*!< FLEXRAM enable */ #define RCC_MEMENSR_CACHEAXIRAMENS_Pos (10U) #define RCC_MEMENSR_CACHEAXIRAMENS_Msk (0x1UL << RCC_MEMENSR_CACHEAXIRAMENS_Pos) /*!< 0x00000400 */ #define RCC_MEMENSR_CACHEAXIRAMENS RCC_MEMENSR_CACHEAXIRAMENS_Msk /*!< CACHEAXIRAM enable */ #define RCC_MEMENSR_VENCRAMENS_Pos (11U) #define RCC_MEMENSR_VENCRAMENS_Msk (0x1UL << RCC_MEMENSR_VENCRAMENS_Pos) /*!< 0x00000800 */ #define RCC_MEMENSR_VENCRAMENS RCC_MEMENSR_VENCRAMENS_Msk /*!< VENCRAM enable */ #define RCC_MEMENSR_BOOTROMENS_Pos (12U) #define RCC_MEMENSR_BOOTROMENS_Msk (0x1UL << RCC_MEMENSR_BOOTROMENS_Pos) /*!< 0x00001000 */ #define RCC_MEMENSR_BOOTROMENS RCC_MEMENSR_BOOTROMENS_Msk /*!< Boot ROM enable */ /***************** Bit definition for RCC_AHB1ENSR register *****************/ #define RCC_AHB1ENSR_GPDMA1ENS_Pos (4U) #define RCC_AHB1ENSR_GPDMA1ENS_Msk (0x1UL << RCC_AHB1ENSR_GPDMA1ENS_Pos) /*!< 0x00000010 */ #define RCC_AHB1ENSR_GPDMA1ENS RCC_AHB1ENSR_GPDMA1ENS_Msk /*!< GPDMA1 enable */ #define RCC_AHB1ENSR_ADC12ENS_Pos (5U) #define RCC_AHB1ENSR_ADC12ENS_Msk (0x1UL << RCC_AHB1ENSR_ADC12ENS_Pos) /*!< 0x00000020 */ #define RCC_AHB1ENSR_ADC12ENS RCC_AHB1ENSR_ADC12ENS_Msk /*!< ADC12 enable */ /***************** Bit definition for RCC_AHB2ENSR register *****************/ #define RCC_AHB2ENSR_RAMCFGENS_Pos (12U) #define RCC_AHB2ENSR_RAMCFGENS_Msk (0x1UL << RCC_AHB2ENSR_RAMCFGENS_Pos) /*!< 0x00001000 */ #define RCC_AHB2ENSR_RAMCFGENS RCC_AHB2ENSR_RAMCFGENS_Msk /*!< RAMCFG enable */ #define RCC_AHB2ENSR_MDF1ENS_Pos (16U) #define RCC_AHB2ENSR_MDF1ENS_Msk (0x1UL << RCC_AHB2ENSR_MDF1ENS_Pos) /*!< 0x00010000 */ #define RCC_AHB2ENSR_MDF1ENS RCC_AHB2ENSR_MDF1ENS_Msk /*!< MDF1 enable */ #define RCC_AHB2ENSR_ADF1ENS_Pos (17U) #define RCC_AHB2ENSR_ADF1ENS_Msk (0x1UL << RCC_AHB2ENSR_ADF1ENS_Pos) /*!< 0x00020000 */ #define RCC_AHB2ENSR_ADF1ENS RCC_AHB2ENSR_ADF1ENS_Msk /*!< ADF1 enable */ /***************** Bit definition for RCC_AHB3ENSR register *****************/ #define RCC_AHB3ENSR_RNGENS_Pos (0U) #define RCC_AHB3ENSR_RNGENS_Msk (0x1UL << RCC_AHB3ENSR_RNGENS_Pos) /*!< 0x00000001 */ #define RCC_AHB3ENSR_RNGENS RCC_AHB3ENSR_RNGENS_Msk /*!< RNG enable */ #define RCC_AHB3ENSR_HASHENS_Pos (1U) #define RCC_AHB3ENSR_HASHENS_Msk (0x1UL << RCC_AHB3ENSR_HASHENS_Pos) /*!< 0x00000002 */ #define RCC_AHB3ENSR_HASHENS RCC_AHB3ENSR_HASHENS_Msk /*!< HASH enable */ #define RCC_AHB3ENSR_CRYPENS_Pos (2U) #define RCC_AHB3ENSR_CRYPENS_Msk (0x1UL << RCC_AHB3ENSR_CRYPENS_Pos) /*!< 0x00000004 */ #define RCC_AHB3ENSR_CRYPENS RCC_AHB3ENSR_CRYPENS_Msk /*!< CRYP enable */ #define RCC_AHB3ENSR_SAESENS_Pos (4U) #define RCC_AHB3ENSR_SAESENS_Msk (0x1UL << RCC_AHB3ENSR_SAESENS_Pos) /*!< 0x00000010 */ #define RCC_AHB3ENSR_SAESENS RCC_AHB3ENSR_SAESENS_Msk /*!< SAES enable */ #define RCC_AHB3ENSR_PKAENS_Pos (8U) #define RCC_AHB3ENSR_PKAENS_Msk (0x1UL << RCC_AHB3ENSR_PKAENS_Pos) /*!< 0x00000100 */ #define RCC_AHB3ENSR_PKAENS RCC_AHB3ENSR_PKAENS_Msk /*!< PKA enable */ #define RCC_AHB3ENSR_RIFSCENS_Pos (9U) #define RCC_AHB3ENSR_RIFSCENS_Msk (0x1UL << RCC_AHB3ENSR_RIFSCENS_Pos) /*!< 0x00000200 */ #define RCC_AHB3ENSR_RIFSCENS RCC_AHB3ENSR_RIFSCENS_Msk /*!< RIFSC enable */ #define RCC_AHB3ENSR_IACENS_Pos (10U) #define RCC_AHB3ENSR_IACENS_Msk (0x1UL << RCC_AHB3ENSR_IACENS_Pos) /*!< 0x00000400 */ #define RCC_AHB3ENSR_IACENS RCC_AHB3ENSR_IACENS_Msk /*!< IAC enable */ #define RCC_AHB3ENSR_RISAFENS_Pos (14U) #define RCC_AHB3ENSR_RISAFENS_Msk (0x1UL << RCC_AHB3ENSR_RISAFENS_Pos) /*!< 0x00004000 */ #define RCC_AHB3ENSR_RISAFENS RCC_AHB3ENSR_RISAFENS_Msk /*!< RISAF enable */ /***************** Bit definition for RCC_AHB4ENSR register *****************/ #define RCC_AHB4ENSR_GPIOAENS_Pos (0U) #define RCC_AHB4ENSR_GPIOAENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOAENS_Pos) /*!< 0x00000001 */ #define RCC_AHB4ENSR_GPIOAENS RCC_AHB4ENSR_GPIOAENS_Msk /*!< GPIO A enable */ #define RCC_AHB4ENSR_GPIOBENS_Pos (1U) #define RCC_AHB4ENSR_GPIOBENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOBENS_Pos) /*!< 0x00000002 */ #define RCC_AHB4ENSR_GPIOBENS RCC_AHB4ENSR_GPIOBENS_Msk /*!< GPIO B enable */ #define RCC_AHB4ENSR_GPIOCENS_Pos (2U) #define RCC_AHB4ENSR_GPIOCENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOCENS_Pos) /*!< 0x00000004 */ #define RCC_AHB4ENSR_GPIOCENS RCC_AHB4ENSR_GPIOCENS_Msk /*!< GPIO C enable */ #define RCC_AHB4ENSR_GPIODENS_Pos (3U) #define RCC_AHB4ENSR_GPIODENS_Msk (0x1UL << RCC_AHB4ENSR_GPIODENS_Pos) /*!< 0x00000008 */ #define RCC_AHB4ENSR_GPIODENS RCC_AHB4ENSR_GPIODENS_Msk /*!< GPIO D enable */ #define RCC_AHB4ENSR_GPIOEENS_Pos (4U) #define RCC_AHB4ENSR_GPIOEENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOEENS_Pos) /*!< 0x00000010 */ #define RCC_AHB4ENSR_GPIOEENS RCC_AHB4ENSR_GPIOEENS_Msk /*!< GPIO E enable */ #define RCC_AHB4ENSR_GPIOFENS_Pos (5U) #define RCC_AHB4ENSR_GPIOFENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOFENS_Pos) /*!< 0x00000020 */ #define RCC_AHB4ENSR_GPIOFENS RCC_AHB4ENSR_GPIOFENS_Msk /*!< GPIO F enable */ #define RCC_AHB4ENSR_GPIOGENS_Pos (6U) #define RCC_AHB4ENSR_GPIOGENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOGENS_Pos) /*!< 0x00000040 */ #define RCC_AHB4ENSR_GPIOGENS RCC_AHB4ENSR_GPIOGENS_Msk /*!< GPIO G enable */ #define RCC_AHB4ENSR_GPIOHENS_Pos (7U) #define RCC_AHB4ENSR_GPIOHENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOHENS_Pos) /*!< 0x00000080 */ #define RCC_AHB4ENSR_GPIOHENS RCC_AHB4ENSR_GPIOHENS_Msk /*!< GPIO H enable */ #define RCC_AHB4ENSR_GPIONENS_Pos (13U) #define RCC_AHB4ENSR_GPIONENS_Msk (0x1UL << RCC_AHB4ENSR_GPIONENS_Pos) /*!< 0x00002000 */ #define RCC_AHB4ENSR_GPIONENS RCC_AHB4ENSR_GPIONENS_Msk /*!< GPIO N enable */ #define RCC_AHB4ENSR_GPIOOENS_Pos (14U) #define RCC_AHB4ENSR_GPIOOENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOOENS_Pos) /*!< 0x00004000 */ #define RCC_AHB4ENSR_GPIOOENS RCC_AHB4ENSR_GPIOOENS_Msk /*!< GPIO O enable */ #define RCC_AHB4ENSR_GPIOPENS_Pos (15U) #define RCC_AHB4ENSR_GPIOPENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOPENS_Pos) /*!< 0x00008000 */ #define RCC_AHB4ENSR_GPIOPENS RCC_AHB4ENSR_GPIOPENS_Msk /*!< GPIO P enable */ #define RCC_AHB4ENSR_GPIOQENS_Pos (16U) #define RCC_AHB4ENSR_GPIOQENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOQENS_Pos) /*!< 0x00010000 */ #define RCC_AHB4ENSR_GPIOQENS RCC_AHB4ENSR_GPIOQENS_Msk /*!< GPIO Q enable */ #define RCC_AHB4ENSR_PWRENS_Pos (18U) #define RCC_AHB4ENSR_PWRENS_Msk (0x1UL << RCC_AHB4ENSR_PWRENS_Pos) /*!< 0x00040000 */ #define RCC_AHB4ENSR_PWRENS RCC_AHB4ENSR_PWRENS_Msk /*!< PWR enable */ #define RCC_AHB4ENSR_CRCENS_Pos (19U) #define RCC_AHB4ENSR_CRCENS_Msk (0x1UL << RCC_AHB4ENSR_CRCENS_Pos) /*!< 0x00080000 */ #define RCC_AHB4ENSR_CRCENS RCC_AHB4ENSR_CRCENS_Msk /*!< CRC enable */ /***************** Bit definition for RCC_AHB5ENSR register *****************/ #define RCC_AHB5ENSR_HPDMA1ENS_Pos (0U) #define RCC_AHB5ENSR_HPDMA1ENS_Msk (0x1UL << RCC_AHB5ENSR_HPDMA1ENS_Pos) /*!< 0x00000001 */ #define RCC_AHB5ENSR_HPDMA1ENS RCC_AHB5ENSR_HPDMA1ENS_Msk /*!< HPDMA1 enable */ #define RCC_AHB5ENSR_DMA2DENS_Pos (1U) #define RCC_AHB5ENSR_DMA2DENS_Msk (0x1UL << RCC_AHB5ENSR_DMA2DENS_Pos) /*!< 0x00000002 */ #define RCC_AHB5ENSR_DMA2DENS RCC_AHB5ENSR_DMA2DENS_Msk /*!< DMA2D enable */ #define RCC_AHB5ENSR_JPEGENS_Pos (3U) #define RCC_AHB5ENSR_JPEGENS_Msk (0x1UL << RCC_AHB5ENSR_JPEGENS_Pos) /*!< 0x00000008 */ #define RCC_AHB5ENSR_JPEGENS RCC_AHB5ENSR_JPEGENS_Msk /*!< JPEG enable */ #define RCC_AHB5ENSR_FMCENS_Pos (4U) #define RCC_AHB5ENSR_FMCENS_Msk (0x1UL << RCC_AHB5ENSR_FMCENS_Pos) /*!< 0x00000010 */ #define RCC_AHB5ENSR_FMCENS RCC_AHB5ENSR_FMCENS_Msk /*!< FMC enable */ #define RCC_AHB5ENSR_XSPI1ENS_Pos (5U) #define RCC_AHB5ENSR_XSPI1ENS_Msk (0x1UL << RCC_AHB5ENSR_XSPI1ENS_Pos) /*!< 0x00000020 */ #define RCC_AHB5ENSR_XSPI1ENS RCC_AHB5ENSR_XSPI1ENS_Msk /*!< XSPI1 enable */ #define RCC_AHB5ENSR_PSSIENS_Pos (6U) #define RCC_AHB5ENSR_PSSIENS_Msk (0x1UL << RCC_AHB5ENSR_PSSIENS_Pos) /*!< 0x00000040 */ #define RCC_AHB5ENSR_PSSIENS RCC_AHB5ENSR_PSSIENS_Msk /*!< PSSI enable */ #define RCC_AHB5ENSR_SDMMC2ENS_Pos (7U) #define RCC_AHB5ENSR_SDMMC2ENS_Msk (0x1UL << RCC_AHB5ENSR_SDMMC2ENS_Pos) /*!< 0x00000080 */ #define RCC_AHB5ENSR_SDMMC2ENS RCC_AHB5ENSR_SDMMC2ENS_Msk /*!< SDMMC2 enable */ #define RCC_AHB5ENSR_SDMMC1ENS_Pos (8U) #define RCC_AHB5ENSR_SDMMC1ENS_Msk (0x1UL << RCC_AHB5ENSR_SDMMC1ENS_Pos) /*!< 0x00000100 */ #define RCC_AHB5ENSR_SDMMC1ENS RCC_AHB5ENSR_SDMMC1ENS_Msk /*!< SDMMC1 enable */ #define RCC_AHB5ENSR_XSPI2ENS_Pos (12U) #define RCC_AHB5ENSR_XSPI2ENS_Msk (0x1UL << RCC_AHB5ENSR_XSPI2ENS_Pos) /*!< 0x00001000 */ #define RCC_AHB5ENSR_XSPI2ENS RCC_AHB5ENSR_XSPI2ENS_Msk /*!< XSPI2 enable */ #define RCC_AHB5ENSR_XSPIMENS_Pos (13U) #define RCC_AHB5ENSR_XSPIMENS_Msk (0x1UL << RCC_AHB5ENSR_XSPIMENS_Pos) /*!< 0x00002000 */ #define RCC_AHB5ENSR_XSPIMENS RCC_AHB5ENSR_XSPIMENS_Msk /*!< XSPIM enable */ #define RCC_AHB5ENSR_MCE1ENS_Pos (14U) #define RCC_AHB5ENSR_MCE1ENS_Msk (0x1UL << RCC_AHB5ENSR_MCE1ENS_Pos) /*!< 0x00004000 */ #define RCC_AHB5ENSR_MCE1ENS RCC_AHB5ENSR_MCE1ENS_Msk /*!< MCE1 enable */ #define RCC_AHB5ENSR_MCE2ENS_Pos (15U) #define RCC_AHB5ENSR_MCE2ENS_Msk (0x1UL << RCC_AHB5ENSR_MCE2ENS_Pos) /*!< 0x00008000 */ #define RCC_AHB5ENSR_MCE2ENS RCC_AHB5ENSR_MCE2ENS_Msk /*!< MCE2 enable */ #define RCC_AHB5ENSR_MCE3ENS_Pos (16U) #define RCC_AHB5ENSR_MCE3ENS_Msk (0x1UL << RCC_AHB5ENSR_MCE3ENS_Pos) /*!< 0x00010000 */ #define RCC_AHB5ENSR_MCE3ENS RCC_AHB5ENSR_MCE3ENS_Msk /*!< MCE3 enable */ #define RCC_AHB5ENSR_XSPI3ENS_Pos (17U) #define RCC_AHB5ENSR_XSPI3ENS_Msk (0x1UL << RCC_AHB5ENSR_XSPI3ENS_Pos) /*!< 0x00020000 */ #define RCC_AHB5ENSR_XSPI3ENS RCC_AHB5ENSR_XSPI3ENS_Msk /*!< XSPI3 enable */ #define RCC_AHB5ENSR_MCE4ENS_Pos (18U) #define RCC_AHB5ENSR_MCE4ENS_Msk (0x1UL << RCC_AHB5ENSR_MCE4ENS_Pos) /*!< 0x00040000 */ #define RCC_AHB5ENSR_MCE4ENS RCC_AHB5ENSR_MCE4ENS_Msk /*!< MCE4 enable */ #define RCC_AHB5ENSR_GFXMMUENS_Pos (19U) #define RCC_AHB5ENSR_GFXMMUENS_Msk (0x1UL << RCC_AHB5ENSR_GFXMMUENS_Pos) /*!< 0x00080000 */ #define RCC_AHB5ENSR_GFXMMUENS RCC_AHB5ENSR_GFXMMUENS_Msk /*!< GFXMMU enable */ #define RCC_AHB5ENSR_GPU2DENS_Pos (20U) #define RCC_AHB5ENSR_GPU2DENS_Msk (0x1UL << RCC_AHB5ENSR_GPU2DENS_Pos) /*!< 0x00100000 */ #define RCC_AHB5ENSR_GPU2DENS RCC_AHB5ENSR_GPU2DENS_Msk /*!< GPU2D enable */ #define RCC_AHB5ENSR_ETH1MACENS_Pos (22U) #define RCC_AHB5ENSR_ETH1MACENS_Msk (0x1UL << RCC_AHB5ENSR_ETH1MACENS_Pos)/*!< 0x00400000 */ #define RCC_AHB5ENSR_ETH1MACENS RCC_AHB5ENSR_ETH1MACENS_Msk /*!< ETH1MAC enable */ #define RCC_AHB5ENSR_ETH1TXENS_Pos (23U) #define RCC_AHB5ENSR_ETH1TXENS_Msk (0x1UL << RCC_AHB5ENSR_ETH1TXENS_Pos) /*!< 0x00800000 */ #define RCC_AHB5ENSR_ETH1TXENS RCC_AHB5ENSR_ETH1TXENS_Msk /*!< ETH1TX enable */ #define RCC_AHB5ENSR_ETH1RXENS_Pos (24U) #define RCC_AHB5ENSR_ETH1RXENS_Msk (0x1UL << RCC_AHB5ENSR_ETH1RXENS_Pos) /*!< 0x01000000 */ #define RCC_AHB5ENSR_ETH1RXENS RCC_AHB5ENSR_ETH1RXENS_Msk /*!< ETH1RX enable */ #define RCC_AHB5ENSR_ETH1ENS_Pos (25U) #define RCC_AHB5ENSR_ETH1ENS_Msk (0x1UL << RCC_AHB5ENSR_ETH1ENS_Pos) /*!< 0x02000000 */ #define RCC_AHB5ENSR_ETH1ENS RCC_AHB5ENSR_ETH1ENS_Msk /*!< ETH1 enable */ #define RCC_AHB5ENSR_OTG1ENS_Pos (26U) #define RCC_AHB5ENSR_OTG1ENS_Msk (0x1UL << RCC_AHB5ENSR_OTG1ENS_Pos) /*!< 0x04000000 */ #define RCC_AHB5ENSR_OTG1ENS RCC_AHB5ENSR_OTG1ENS_Msk /*!< OTG1 enable */ #define RCC_AHB5ENSR_OTGPHY1ENS_Pos (27U) #define RCC_AHB5ENSR_OTGPHY1ENS_Msk (0x1UL << RCC_AHB5ENSR_OTGPHY1ENS_Pos)/*!< 0x08000000 */ #define RCC_AHB5ENSR_OTGPHY1ENS RCC_AHB5ENSR_OTGPHY1ENS_Msk /*!< OTGPHY1 enable */ #define RCC_AHB5ENSR_OTGPHY2ENS_Pos (28U) #define RCC_AHB5ENSR_OTGPHY2ENS_Msk (0x1UL << RCC_AHB5ENSR_OTGPHY2ENS_Pos)/*!< 0x10000000 */ #define RCC_AHB5ENSR_OTGPHY2ENS RCC_AHB5ENSR_OTGPHY2ENS_Msk /*!< OTGPHY2 enable */ #define RCC_AHB5ENSR_OTG2ENS_Pos (29U) #define RCC_AHB5ENSR_OTG2ENS_Msk (0x1UL << RCC_AHB5ENSR_OTG2ENS_Pos) /*!< 0x20000000 */ #define RCC_AHB5ENSR_OTG2ENS RCC_AHB5ENSR_OTG2ENS_Msk /*!< OTG2 enable */ #define RCC_AHB5ENSR_CACHEAXIENS_Pos (30U) #define RCC_AHB5ENSR_CACHEAXIENS_Msk (0x1UL << RCC_AHB5ENSR_CACHEAXIENS_Pos) /*!< 0x40000000 */ #define RCC_AHB5ENSR_CACHEAXIENS RCC_AHB5ENSR_CACHEAXIENS_Msk /*!< CACHEAXI enable */ #define RCC_AHB5ENSR_NPUENS_Pos (31U) #define RCC_AHB5ENSR_NPUENS_Msk (0x1UL << RCC_AHB5ENSR_NPUENS_Pos) /*!< 0x80000000 */ #define RCC_AHB5ENSR_NPUENS RCC_AHB5ENSR_NPUENS_Msk /*!< NPU enable */ /**************** Bit definition for RCC_APB1ENSR1 register *****************/ #define RCC_APB1ENSR1_TIM2ENS_Pos (0U) #define RCC_APB1ENSR1_TIM2ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM2ENS_Pos) /*!< 0x00000001 */ #define RCC_APB1ENSR1_TIM2ENS RCC_APB1ENSR1_TIM2ENS_Msk /*!< TIM2 enable */ #define RCC_APB1ENSR1_TIM3ENS_Pos (1U) #define RCC_APB1ENSR1_TIM3ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM3ENS_Pos) /*!< 0x00000002 */ #define RCC_APB1ENSR1_TIM3ENS RCC_APB1ENSR1_TIM3ENS_Msk /*!< TIM3 enable */ #define RCC_APB1ENSR1_TIM4ENS_Pos (2U) #define RCC_APB1ENSR1_TIM4ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM4ENS_Pos) /*!< 0x00000004 */ #define RCC_APB1ENSR1_TIM4ENS RCC_APB1ENSR1_TIM4ENS_Msk /*!< TIM4 enable */ #define RCC_APB1ENSR1_TIM5ENS_Pos (3U) #define RCC_APB1ENSR1_TIM5ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM5ENS_Pos) /*!< 0x00000008 */ #define RCC_APB1ENSR1_TIM5ENS RCC_APB1ENSR1_TIM5ENS_Msk /*!< TIM5 enable */ #define RCC_APB1ENSR1_TIM6ENS_Pos (4U) #define RCC_APB1ENSR1_TIM6ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM6ENS_Pos) /*!< 0x00000010 */ #define RCC_APB1ENSR1_TIM6ENS RCC_APB1ENSR1_TIM6ENS_Msk /*!< TIM6 enable */ #define RCC_APB1ENSR1_TIM7ENS_Pos (5U) #define RCC_APB1ENSR1_TIM7ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM7ENS_Pos) /*!< 0x00000020 */ #define RCC_APB1ENSR1_TIM7ENS RCC_APB1ENSR1_TIM7ENS_Msk /*!< TIM7 enable */ #define RCC_APB1ENSR1_TIM12ENS_Pos (6U) #define RCC_APB1ENSR1_TIM12ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM12ENS_Pos) /*!< 0x00000040 */ #define RCC_APB1ENSR1_TIM12ENS RCC_APB1ENSR1_TIM12ENS_Msk /*!< TIM12 enable */ #define RCC_APB1ENSR1_TIM13ENS_Pos (7U) #define RCC_APB1ENSR1_TIM13ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM13ENS_Pos) /*!< 0x00000080 */ #define RCC_APB1ENSR1_TIM13ENS RCC_APB1ENSR1_TIM13ENS_Msk /*!< TIM13 enable */ #define RCC_APB1ENSR1_TIM14ENS_Pos (8U) #define RCC_APB1ENSR1_TIM14ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM14ENS_Pos) /*!< 0x00000100 */ #define RCC_APB1ENSR1_TIM14ENS RCC_APB1ENSR1_TIM14ENS_Msk /*!< TIM14 enable */ #define RCC_APB1ENSR1_LPTIM1ENS_Pos (9U) #define RCC_APB1ENSR1_LPTIM1ENS_Msk (0x1UL << RCC_APB1ENSR1_LPTIM1ENS_Pos)/*!< 0x00000200 */ #define RCC_APB1ENSR1_LPTIM1ENS RCC_APB1ENSR1_LPTIM1ENS_Msk /*!< LPTIM1 enable */ #define RCC_APB1ENSR1_WWDGENS_Pos (11U) #define RCC_APB1ENSR1_WWDGENS_Msk (0x1UL << RCC_APB1ENSR1_WWDGENS_Pos) /*!< 0x00000800 */ #define RCC_APB1ENSR1_WWDGENS RCC_APB1ENSR1_WWDGENS_Msk /*!< WWDG enable */ #define RCC_APB1ENSR1_TIM10ENS_Pos (12U) #define RCC_APB1ENSR1_TIM10ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM10ENS_Pos) /*!< 0x00001000 */ #define RCC_APB1ENSR1_TIM10ENS RCC_APB1ENSR1_TIM10ENS_Msk /*!< TIM10 enable */ #define RCC_APB1ENSR1_TIM11ENS_Pos (13U) #define RCC_APB1ENSR1_TIM11ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM11ENS_Pos) /*!< 0x00002000 */ #define RCC_APB1ENSR1_TIM11ENS RCC_APB1ENSR1_TIM11ENS_Msk /*!< TIM11 enable */ #define RCC_APB1ENSR1_SPI2ENS_Pos (14U) #define RCC_APB1ENSR1_SPI2ENS_Msk (0x1UL << RCC_APB1ENSR1_SPI2ENS_Pos) /*!< 0x00004000 */ #define RCC_APB1ENSR1_SPI2ENS RCC_APB1ENSR1_SPI2ENS_Msk /*!< SPI2 enable */ #define RCC_APB1ENSR1_SPI3ENS_Pos (15U) #define RCC_APB1ENSR1_SPI3ENS_Msk (0x1UL << RCC_APB1ENSR1_SPI3ENS_Pos) /*!< 0x00008000 */ #define RCC_APB1ENSR1_SPI3ENS RCC_APB1ENSR1_SPI3ENS_Msk /*!< SPI3 enable */ #define RCC_APB1ENSR1_SPDIFRX1ENS_Pos (16U) #define RCC_APB1ENSR1_SPDIFRX1ENS_Msk (0x1UL << RCC_APB1ENSR1_SPDIFRX1ENS_Pos) /*!< 0x00010000 */ #define RCC_APB1ENSR1_SPDIFRX1ENS RCC_APB1ENSR1_SPDIFRX1ENS_Msk /*!< SPDIFRX1 enable */ #define RCC_APB1ENSR1_USART2ENS_Pos (17U) #define RCC_APB1ENSR1_USART2ENS_Msk (0x1UL << RCC_APB1ENSR1_USART2ENS_Pos)/*!< 0x00020000 */ #define RCC_APB1ENSR1_USART2ENS RCC_APB1ENSR1_USART2ENS_Msk /*!< USART2 enable */ #define RCC_APB1ENSR1_USART3ENS_Pos (18U) #define RCC_APB1ENSR1_USART3ENS_Msk (0x1UL << RCC_APB1ENSR1_USART3ENS_Pos)/*!< 0x00040000 */ #define RCC_APB1ENSR1_USART3ENS RCC_APB1ENSR1_USART3ENS_Msk /*!< USART3 enable */ #define RCC_APB1ENSR1_UART4ENS_Pos (19U) #define RCC_APB1ENSR1_UART4ENS_Msk (0x1UL << RCC_APB1ENSR1_UART4ENS_Pos) /*!< 0x00080000 */ #define RCC_APB1ENSR1_UART4ENS RCC_APB1ENSR1_UART4ENS_Msk /*!< UART4 enable */ #define RCC_APB1ENSR1_UART5ENS_Pos (20U) #define RCC_APB1ENSR1_UART5ENS_Msk (0x1UL << RCC_APB1ENSR1_UART5ENS_Pos) /*!< 0x00100000 */ #define RCC_APB1ENSR1_UART5ENS RCC_APB1ENSR1_UART5ENS_Msk /*!< UART5 enable */ #define RCC_APB1ENSR1_I2C1ENS_Pos (21U) #define RCC_APB1ENSR1_I2C1ENS_Msk (0x1UL << RCC_APB1ENSR1_I2C1ENS_Pos) /*!< 0x00200000 */ #define RCC_APB1ENSR1_I2C1ENS RCC_APB1ENSR1_I2C1ENS_Msk /*!< I2C1 enable */ #define RCC_APB1ENSR1_I2C2ENS_Pos (22U) #define RCC_APB1ENSR1_I2C2ENS_Msk (0x1UL << RCC_APB1ENSR1_I2C2ENS_Pos) /*!< 0x00400000 */ #define RCC_APB1ENSR1_I2C2ENS RCC_APB1ENSR1_I2C2ENS_Msk /*!< I2C2 enable */ #define RCC_APB1ENSR1_I2C3ENS_Pos (23U) #define RCC_APB1ENSR1_I2C3ENS_Msk (0x1UL << RCC_APB1ENSR1_I2C3ENS_Pos) /*!< 0x00800000 */ #define RCC_APB1ENSR1_I2C3ENS RCC_APB1ENSR1_I2C3ENS_Msk /*!< I2C3 enable */ #define RCC_APB1ENSR1_I3C1ENS_Pos (24U) #define RCC_APB1ENSR1_I3C1ENS_Msk (0x1UL << RCC_APB1ENSR1_I3C1ENS_Pos) /*!< 0x01000000 */ #define RCC_APB1ENSR1_I3C1ENS RCC_APB1ENSR1_I3C1ENS_Msk /*!< I3C1 enable */ #define RCC_APB1ENSR1_I3C2ENS_Pos (25U) #define RCC_APB1ENSR1_I3C2ENS_Msk (0x1UL << RCC_APB1ENSR1_I3C2ENS_Pos) /*!< 0x02000000 */ #define RCC_APB1ENSR1_I3C2ENS RCC_APB1ENSR1_I3C2ENS_Msk /*!< I3C2 enable */ #define RCC_APB1ENSR1_UART7ENS_Pos (30U) #define RCC_APB1ENSR1_UART7ENS_Msk (0x1UL << RCC_APB1ENSR1_UART7ENS_Pos) /*!< 0x40000000 */ #define RCC_APB1ENSR1_UART7ENS RCC_APB1ENSR1_UART7ENS_Msk /*!< UART7 enable */ #define RCC_APB1ENSR1_UART8ENS_Pos (31U) #define RCC_APB1ENSR1_UART8ENS_Msk (0x1UL << RCC_APB1ENSR1_UART8ENS_Pos) /*!< 0x80000000 */ #define RCC_APB1ENSR1_UART8ENS RCC_APB1ENSR1_UART8ENS_Msk /*!< UART8 enable */ /**************** Bit definition for RCC_APB1ENSR2 register *****************/ #define RCC_APB1ENSR2_MDIOSENS_Pos (5U) #define RCC_APB1ENSR2_MDIOSENS_Msk (0x1UL << RCC_APB1ENSR2_MDIOSENS_Pos) /*!< 0x00000020 */ #define RCC_APB1ENSR2_MDIOSENS RCC_APB1ENSR2_MDIOSENS_Msk /*!< MDIOS enable */ #define RCC_APB1ENSR2_FDCANENS_Pos (8U) #define RCC_APB1ENSR2_FDCANENS_Msk (0x1UL << RCC_APB1ENSR2_FDCANENS_Pos) /*!< 0x00000100 */ #define RCC_APB1ENSR2_FDCANENS RCC_APB1ENSR2_FDCANENS_Msk /*!< FDCAN enable */ #define RCC_APB1ENSR2_UCPD1ENS_Pos (18U) #define RCC_APB1ENSR2_UCPD1ENS_Msk (0x1UL << RCC_APB1ENSR2_UCPD1ENS_Pos) /*!< 0x00040000 */ #define RCC_APB1ENSR2_UCPD1ENS RCC_APB1ENSR2_UCPD1ENS_Msk /*!< UCPD1 enable */ /***************** Bit definition for RCC_APB2ENSR register *****************/ #define RCC_APB2ENSR_TIM1ENS_Pos (0U) #define RCC_APB2ENSR_TIM1ENS_Msk (0x1UL << RCC_APB2ENSR_TIM1ENS_Pos) /*!< 0x00000001 */ #define RCC_APB2ENSR_TIM1ENS RCC_APB2ENSR_TIM1ENS_Msk /*!< TIM1 enable */ #define RCC_APB2ENSR_TIM8ENS_Pos (1U) #define RCC_APB2ENSR_TIM8ENS_Msk (0x1UL << RCC_APB2ENSR_TIM8ENS_Pos) /*!< 0x00000002 */ #define RCC_APB2ENSR_TIM8ENS RCC_APB2ENSR_TIM8ENS_Msk /*!< TIM8 enable */ #define RCC_APB2ENSR_USART1ENS_Pos (4U) #define RCC_APB2ENSR_USART1ENS_Msk (0x1UL << RCC_APB2ENSR_USART1ENS_Pos) /*!< 0x00000010 */ #define RCC_APB2ENSR_USART1ENS RCC_APB2ENSR_USART1ENS_Msk /*!< USART1 enable */ #define RCC_APB2ENSR_USART6ENS_Pos (5U) #define RCC_APB2ENSR_USART6ENS_Msk (0x1UL << RCC_APB2ENSR_USART6ENS_Pos) /*!< 0x00000020 */ #define RCC_APB2ENSR_USART6ENS RCC_APB2ENSR_USART6ENS_Msk /*!< USART6 enable */ #define RCC_APB2ENSR_UART9ENS_Pos (6U) #define RCC_APB2ENSR_UART9ENS_Msk (0x1UL << RCC_APB2ENSR_UART9ENS_Pos) /*!< 0x00000040 */ #define RCC_APB2ENSR_UART9ENS RCC_APB2ENSR_UART9ENS_Msk /*!< UART9 enable */ #define RCC_APB2ENSR_USART10ENS_Pos (7U) #define RCC_APB2ENSR_USART10ENS_Msk (0x1UL << RCC_APB2ENSR_USART10ENS_Pos)/*!< 0x00000080 */ #define RCC_APB2ENSR_USART10ENS RCC_APB2ENSR_USART10ENS_Msk /*!< USART10 enable */ #define RCC_APB2ENSR_SPI1ENS_Pos (12U) #define RCC_APB2ENSR_SPI1ENS_Msk (0x1UL << RCC_APB2ENSR_SPI1ENS_Pos) /*!< 0x00001000 */ #define RCC_APB2ENSR_SPI1ENS RCC_APB2ENSR_SPI1ENS_Msk /*!< SPI1 enable */ #define RCC_APB2ENSR_SPI4ENS_Pos (13U) #define RCC_APB2ENSR_SPI4ENS_Msk (0x1UL << RCC_APB2ENSR_SPI4ENS_Pos) /*!< 0x00002000 */ #define RCC_APB2ENSR_SPI4ENS RCC_APB2ENSR_SPI4ENS_Msk /*!< SPI4 enable */ #define RCC_APB2ENSR_TIM18ENS_Pos (15U) #define RCC_APB2ENSR_TIM18ENS_Msk (0x1UL << RCC_APB2ENSR_TIM18ENS_Pos) /*!< 0x00008000 */ #define RCC_APB2ENSR_TIM18ENS RCC_APB2ENSR_TIM18ENS_Msk /*!< TIM18 enable */ #define RCC_APB2ENSR_TIM15ENS_Pos (16U) #define RCC_APB2ENSR_TIM15ENS_Msk (0x1UL << RCC_APB2ENSR_TIM15ENS_Pos) /*!< 0x00010000 */ #define RCC_APB2ENSR_TIM15ENS RCC_APB2ENSR_TIM15ENS_Msk /*!< TIM15 enable */ #define RCC_APB2ENSR_TIM16ENS_Pos (17U) #define RCC_APB2ENSR_TIM16ENS_Msk (0x1UL << RCC_APB2ENSR_TIM16ENS_Pos) /*!< 0x00020000 */ #define RCC_APB2ENSR_TIM16ENS RCC_APB2ENSR_TIM16ENS_Msk /*!< TIM16 enable */ #define RCC_APB2ENSR_TIM17ENS_Pos (18U) #define RCC_APB2ENSR_TIM17ENS_Msk (0x1UL << RCC_APB2ENSR_TIM17ENS_Pos) /*!< 0x00040000 */ #define RCC_APB2ENSR_TIM17ENS RCC_APB2ENSR_TIM17ENS_Msk /*!< TIM17 enable */ #define RCC_APB2ENSR_TIM9ENS_Pos (19U) #define RCC_APB2ENSR_TIM9ENS_Msk (0x1UL << RCC_APB2ENSR_TIM9ENS_Pos) /*!< 0x00080000 */ #define RCC_APB2ENSR_TIM9ENS RCC_APB2ENSR_TIM9ENS_Msk /*!< TIM9 enable */ #define RCC_APB2ENSR_SPI5ENS_Pos (20U) #define RCC_APB2ENSR_SPI5ENS_Msk (0x1UL << RCC_APB2ENSR_SPI5ENS_Pos) /*!< 0x00100000 */ #define RCC_APB2ENSR_SPI5ENS RCC_APB2ENSR_SPI5ENS_Msk /*!< SPI5 enable */ #define RCC_APB2ENSR_SAI1ENS_Pos (21U) #define RCC_APB2ENSR_SAI1ENS_Msk (0x1UL << RCC_APB2ENSR_SAI1ENS_Pos) /*!< 0x00200000 */ #define RCC_APB2ENSR_SAI1ENS RCC_APB2ENSR_SAI1ENS_Msk /*!< SAI1 enable */ #define RCC_APB2ENSR_SAI2ENS_Pos (22U) #define RCC_APB2ENSR_SAI2ENS_Msk (0x1UL << RCC_APB2ENSR_SAI2ENS_Pos) /*!< 0x00400000 */ #define RCC_APB2ENSR_SAI2ENS RCC_APB2ENSR_SAI2ENS_Msk /*!< SAI2 enable */ /***************** Bit definition for RCC_APB3ENSR register *****************/ #define RCC_APB3ENSR_DFTENS_Pos (2U) #define RCC_APB3ENSR_DFTENS_Msk (0x1UL << RCC_APB3ENSR_DFTENS_Pos) /*!< 0x00000004 */ #define RCC_APB3ENSR_DFTENS RCC_APB3ENSR_DFTENS_Msk /*!< DFT enable */ /**************** Bit definition for RCC_APB4ENSR1 register *****************/ #define RCC_APB4ENSR1_HDPENS_Pos (2U) #define RCC_APB4ENSR1_HDPENS_Msk (0x1UL << RCC_APB4ENSR1_HDPENS_Pos) /*!< 0x00000004 */ #define RCC_APB4ENSR1_HDPENS RCC_APB4ENSR1_HDPENS_Msk /*!< HDP enable */ #define RCC_APB4ENSR1_LPUART1ENS_Pos (3U) #define RCC_APB4ENSR1_LPUART1ENS_Msk (0x1UL << RCC_APB4ENSR1_LPUART1ENS_Pos) /*!< 0x00000008 */ #define RCC_APB4ENSR1_LPUART1ENS RCC_APB4ENSR1_LPUART1ENS_Msk /*!< LPUART1 enable */ #define RCC_APB4ENSR1_SPI6ENS_Pos (5U) #define RCC_APB4ENSR1_SPI6ENS_Msk (0x1UL << RCC_APB4ENSR1_SPI6ENS_Pos) /*!< 0x00000020 */ #define RCC_APB4ENSR1_SPI6ENS RCC_APB4ENSR1_SPI6ENS_Msk /*!< SPI6 enable */ #define RCC_APB4ENSR1_I2C4ENS_Pos (7U) #define RCC_APB4ENSR1_I2C4ENS_Msk (0x1UL << RCC_APB4ENSR1_I2C4ENS_Pos) /*!< 0x00000080 */ #define RCC_APB4ENSR1_I2C4ENS RCC_APB4ENSR1_I2C4ENS_Msk /*!< I2C4 enable */ #define RCC_APB4ENSR1_LPTIM2ENS_Pos (9U) #define RCC_APB4ENSR1_LPTIM2ENS_Msk (0x1UL << RCC_APB4ENSR1_LPTIM2ENS_Pos)/*!< 0x00000200 */ #define RCC_APB4ENSR1_LPTIM2ENS RCC_APB4ENSR1_LPTIM2ENS_Msk /*!< LPTIM2 enable */ #define RCC_APB4ENSR1_LPTIM3ENS_Pos (10U) #define RCC_APB4ENSR1_LPTIM3ENS_Msk (0x1UL << RCC_APB4ENSR1_LPTIM3ENS_Pos)/*!< 0x00000400 */ #define RCC_APB4ENSR1_LPTIM3ENS RCC_APB4ENSR1_LPTIM3ENS_Msk /*!< LPTIM3 enable */ #define RCC_APB4ENSR1_LPTIM4ENS_Pos (11U) #define RCC_APB4ENSR1_LPTIM4ENS_Msk (0x1UL << RCC_APB4ENSR1_LPTIM4ENS_Pos)/*!< 0x00000800 */ #define RCC_APB4ENSR1_LPTIM4ENS RCC_APB4ENSR1_LPTIM4ENS_Msk /*!< LPTIM4 enable */ #define RCC_APB4ENSR1_LPTIM5ENS_Pos (12U) #define RCC_APB4ENSR1_LPTIM5ENS_Msk (0x1UL << RCC_APB4ENSR1_LPTIM5ENS_Pos)/*!< 0x00001000 */ #define RCC_APB4ENSR1_LPTIM5ENS RCC_APB4ENSR1_LPTIM5ENS_Msk /*!< LPTIM5 enable */ #define RCC_APB4ENSR1_VREFBUFENS_Pos (15U) #define RCC_APB4ENSR1_VREFBUFENS_Msk (0x1UL << RCC_APB4ENSR1_VREFBUFENS_Pos) /*!< 0x00008000 */ #define RCC_APB4ENSR1_VREFBUFENS RCC_APB4ENSR1_VREFBUFENS_Msk /*!< VREFBUF enable */ #define RCC_APB4ENSR1_RTCENS_Pos (16U) #define RCC_APB4ENSR1_RTCENS_Msk (0x1UL << RCC_APB4ENSR1_RTCENS_Pos) /*!< 0x00010000 */ #define RCC_APB4ENSR1_RTCENS RCC_APB4ENSR1_RTCENS_Msk /*!< RTC enable */ #define RCC_APB4ENSR1_RTCAPBENS_Pos (17U) #define RCC_APB4ENSR1_RTCAPBENS_Msk (0x1UL << RCC_APB4ENSR1_RTCAPBENS_Pos)/*!< 0x00020000 */ #define RCC_APB4ENSR1_RTCAPBENS RCC_APB4ENSR1_RTCAPBENS_Msk /*!< RTCAPB enable */ /**************** Bit definition for RCC_APB4ENSR2 register *****************/ #define RCC_APB4ENSR2_SYSCFGENS_Pos (0U) #define RCC_APB4ENSR2_SYSCFGENS_Msk (0x1UL << RCC_APB4ENSR2_SYSCFGENS_Pos)/*!< 0x00000001 */ #define RCC_APB4ENSR2_SYSCFGENS RCC_APB4ENSR2_SYSCFGENS_Msk /*!< SYSCFG enable */ #define RCC_APB4ENSR2_BSECENS_Pos (1U) #define RCC_APB4ENSR2_BSECENS_Msk (0x1UL << RCC_APB4ENSR2_BSECENS_Pos) /*!< 0x00000002 */ #define RCC_APB4ENSR2_BSECENS RCC_APB4ENSR2_BSECENS_Msk /*!< BSEC enable */ #define RCC_APB4ENSR2_DTSENS_Pos (2U) #define RCC_APB4ENSR2_DTSENS_Msk (0x1UL << RCC_APB4ENSR2_DTSENS_Pos) /*!< 0x00000004 */ #define RCC_APB4ENSR2_DTSENS RCC_APB4ENSR2_DTSENS_Msk /*!< DTS enable */ /***************** Bit definition for RCC_APB5ENSR register *****************/ #define RCC_APB5ENSR_LTDCENS_Pos (1U) #define RCC_APB5ENSR_LTDCENS_Msk (0x1UL << RCC_APB5ENSR_LTDCENS_Pos) /*!< 0x00000002 */ #define RCC_APB5ENSR_LTDCENS RCC_APB5ENSR_LTDCENS_Msk /*!< LTDC enable */ #define RCC_APB5ENSR_DCMIPPENS_Pos (2U) #define RCC_APB5ENSR_DCMIPPENS_Msk (0x1UL << RCC_APB5ENSR_DCMIPPENS_Pos) /*!< 0x00000004 */ #define RCC_APB5ENSR_DCMIPPENS RCC_APB5ENSR_DCMIPPENS_Msk /*!< DCMIPP enable */ #define RCC_APB5ENSR_GFXTIMENS_Pos (4U) #define RCC_APB5ENSR_GFXTIMENS_Msk (0x1UL << RCC_APB5ENSR_GFXTIMENS_Pos) /*!< 0x00000010 */ #define RCC_APB5ENSR_GFXTIMENS RCC_APB5ENSR_GFXTIMENS_Msk /*!< GFXTIM enable */ #define RCC_APB5ENSR_VENCENS_Pos (5U) #define RCC_APB5ENSR_VENCENS_Msk (0x1UL << RCC_APB5ENSR_VENCENS_Pos) /*!< 0x00000020 */ #define RCC_APB5ENSR_VENCENS RCC_APB5ENSR_VENCENS_Msk /*!< VENC enable */ #define RCC_APB5ENSR_CSIENS_Pos (6U) #define RCC_APB5ENSR_CSIENS_Msk (0x1UL << RCC_APB5ENSR_CSIENS_Pos) /*!< 0x00000040 */ #define RCC_APB5ENSR_CSIENS RCC_APB5ENSR_CSIENS_Msk /*!< CSI enable */ /**************** Bit definition for RCC_BUSLPENSR register *****************/ #define RCC_BUSLPENSR_ACLKNLPENS_Pos (0U) #define RCC_BUSLPENSR_ACLKNLPENS_Msk (0x1UL << RCC_BUSLPENSR_ACLKNLPENS_Pos) /*!< 0x00000001 */ #define RCC_BUSLPENSR_ACLKNLPENS RCC_BUSLPENSR_ACLKNLPENS_Msk /*!< ACLKN enable */ #define RCC_BUSLPENSR_ACLKNCLPENS_Pos (1U) #define RCC_BUSLPENSR_ACLKNCLPENS_Msk (0x1UL << RCC_BUSLPENSR_ACLKNCLPENS_Pos) /*!< 0x00000002 */ #define RCC_BUSLPENSR_ACLKNCLPENS RCC_BUSLPENSR_ACLKNCLPENS_Msk /*!< ACLKNC enable */ /**************** Bit definition for RCC_MISCLPENSR register ****************/ #define RCC_MISCLPENSR_DBGLPENS_Pos (0U) #define RCC_MISCLPENSR_DBGLPENS_Msk (0x1UL << RCC_MISCLPENSR_DBGLPENS_Pos)/*!< 0x00000001 */ #define RCC_MISCLPENSR_DBGLPENS RCC_MISCLPENSR_DBGLPENS_Msk /*!< DBG enable */ #define RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Pos (3U) #define RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Msk (0x1UL << RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Pos) /*!< 0x00000008 */ #define RCC_MISCLPENSR_XSPIPHYCOMPLPENS RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Msk /*!< XSPIPHYCOMP enable */ #define RCC_MISCLPENSR_PERLPENS_Pos (6U) #define RCC_MISCLPENSR_PERLPENS_Msk (0x1UL << RCC_MISCLPENSR_PERLPENS_Pos)/*!< 0x00000040 */ #define RCC_MISCLPENSR_PERLPENS RCC_MISCLPENSR_PERLPENS_Msk /*!< PER enable */ /**************** Bit definition for RCC_MEMLPENSR register *****************/ #define RCC_MEMLPENSR_AXISRAM3LPENS_Pos (0U) #define RCC_MEMLPENSR_AXISRAM3LPENS_Msk (0x1UL << RCC_MEMLPENSR_AXISRAM3LPENS_Pos) /*!< 0x00000001 */ #define RCC_MEMLPENSR_AXISRAM3LPENS RCC_MEMLPENSR_AXISRAM3LPENS_Msk /*!< AXISRAM3 enable */ #define RCC_MEMLPENSR_AXISRAM4LPENS_Pos (1U) #define RCC_MEMLPENSR_AXISRAM4LPENS_Msk (0x1UL << RCC_MEMLPENSR_AXISRAM4LPENS_Pos) /*!< 0x00000002 */ #define RCC_MEMLPENSR_AXISRAM4LPENS RCC_MEMLPENSR_AXISRAM4LPENS_Msk /*!< AXISRAM4 enable */ #define RCC_MEMLPENSR_AXISRAM5LPENS_Pos (2U) #define RCC_MEMLPENSR_AXISRAM5LPENS_Msk (0x1UL << RCC_MEMLPENSR_AXISRAM5LPENS_Pos) /*!< 0x00000004 */ #define RCC_MEMLPENSR_AXISRAM5LPENS RCC_MEMLPENSR_AXISRAM5LPENS_Msk /*!< AXISRAM5 enable */ #define RCC_MEMLPENSR_AXISRAM6LPENS_Pos (3U) #define RCC_MEMLPENSR_AXISRAM6LPENS_Msk (0x1UL << RCC_MEMLPENSR_AXISRAM6LPENS_Pos) /*!< 0x00000008 */ #define RCC_MEMLPENSR_AXISRAM6LPENS RCC_MEMLPENSR_AXISRAM6LPENS_Msk /*!< AXISRAM6 enable */ #define RCC_MEMLPENSR_AHBSRAM1LPENS_Pos (4U) #define RCC_MEMLPENSR_AHBSRAM1LPENS_Msk (0x1UL << RCC_MEMLPENSR_AHBSRAM1LPENS_Pos) /*!< 0x00000010 */ #define RCC_MEMLPENSR_AHBSRAM1LPENS RCC_MEMLPENSR_AHBSRAM1LPENS_Msk /*!< AHBSRAM1 enable */ #define RCC_MEMLPENSR_AHBSRAM2LPENS_Pos (5U) #define RCC_MEMLPENSR_AHBSRAM2LPENS_Msk (0x1UL << RCC_MEMLPENSR_AHBSRAM2LPENS_Pos) /*!< 0x00000020 */ #define RCC_MEMLPENSR_AHBSRAM2LPENS RCC_MEMLPENSR_AHBSRAM2LPENS_Msk /*!< AHBSRAM2 enable */ #define RCC_MEMLPENSR_BKPSRAMLPENS_Pos (6U) #define RCC_MEMLPENSR_BKPSRAMLPENS_Msk (0x1UL << RCC_MEMLPENSR_BKPSRAMLPENS_Pos) /*!< 0x00000040 */ #define RCC_MEMLPENSR_BKPSRAMLPENS RCC_MEMLPENSR_BKPSRAMLPENS_Msk /*!< BKPSRAM enable */ #define RCC_MEMLPENSR_AXISRAM1LPENS_Pos (7U) #define RCC_MEMLPENSR_AXISRAM1LPENS_Msk (0x1UL << RCC_MEMLPENSR_AXISRAM1LPENS_Pos) /*!< 0x00000080 */ #define RCC_MEMLPENSR_AXISRAM1LPENS RCC_MEMLPENSR_AXISRAM1LPENS_Msk /*!< AXISRAM1 enable */ #define RCC_MEMLPENSR_AXISRAM2LPENS_Pos (8U) #define RCC_MEMLPENSR_AXISRAM2LPENS_Msk (0x1UL << RCC_MEMLPENSR_AXISRAM2LPENS_Pos) /*!< 0x00000100 */ #define RCC_MEMLPENSR_AXISRAM2LPENS RCC_MEMLPENSR_AXISRAM2LPENS_Msk /*!< AXISRAM2 enable */ #define RCC_MEMLPENSR_FLEXRAMLPENS_Pos (9U) #define RCC_MEMLPENSR_FLEXRAMLPENS_Msk (0x1UL << RCC_MEMLPENSR_FLEXRAMLPENS_Pos) /*!< 0x00000200 */ #define RCC_MEMLPENSR_FLEXRAMLPENS RCC_MEMLPENSR_FLEXRAMLPENS_Msk /*!< FLEXRAM enable */ #define RCC_MEMLPENSR_CACHEAXIRAMLPENS_Pos (10U) #define RCC_MEMLPENSR_CACHEAXIRAMLPENS_Msk (0x1UL << RCC_MEMLPENSR_CACHEAXIRAMLPENS_Pos) /*!< 0x00000400 */ #define RCC_MEMLPENSR_CACHEAXIRAMLPENS RCC_MEMLPENSR_CACHEAXIRAMLPENS_Msk /*!< CACHEAXIRAM enable */ #define RCC_MEMLPENSR_VENCRAMLPENS_Pos (11U) #define RCC_MEMLPENSR_VENCRAMLPENS_Msk (0x1UL << RCC_MEMLPENSR_VENCRAMLPENS_Pos) /*!< 0x00000800 */ #define RCC_MEMLPENSR_VENCRAMLPENS RCC_MEMLPENSR_VENCRAMLPENS_Msk /*!< VENCRAM enable */ #define RCC_MEMLPENSR_BOOTROMLPENS_Pos (12U) #define RCC_MEMLPENSR_BOOTROMLPENS_Msk (0x1UL << RCC_MEMLPENSR_BOOTROMLPENS_Pos) /*!< 0x00001000 */ #define RCC_MEMLPENSR_BOOTROMLPENS RCC_MEMLPENSR_BOOTROMLPENS_Msk /*!< Boot ROM enable */ /**************** Bit definition for RCC_AHB1LPENSR register ****************/ #define RCC_AHB1LPENSR_GPDMA1LPENS_Pos (4U) #define RCC_AHB1LPENSR_GPDMA1LPENS_Msk (0x1UL << RCC_AHB1LPENSR_GPDMA1LPENS_Pos) /*!< 0x00000010 */ #define RCC_AHB1LPENSR_GPDMA1LPENS RCC_AHB1LPENSR_GPDMA1LPENS_Msk /*!< GPDMA1 enable */ #define RCC_AHB1LPENSR_ADC12LPENS_Pos (5U) #define RCC_AHB1LPENSR_ADC12LPENS_Msk (0x1UL << RCC_AHB1LPENSR_ADC12LPENS_Pos) /*!< 0x00000020 */ #define RCC_AHB1LPENSR_ADC12LPENS RCC_AHB1LPENSR_ADC12LPENS_Msk /*!< ADC12 enable */ /**************** Bit definition for RCC_AHB2LPENSR register ****************/ #define RCC_AHB2LPENSR_RAMCFGLPENS_Pos (12U) #define RCC_AHB2LPENSR_RAMCFGLPENS_Msk (0x1UL << RCC_AHB2LPENSR_RAMCFGLPENS_Pos) /*!< 0x00001000 */ #define RCC_AHB2LPENSR_RAMCFGLPENS RCC_AHB2LPENSR_RAMCFGLPENS_Msk /*!< RAMCFG enable */ #define RCC_AHB2LPENSR_MDF1LPENS_Pos (16U) #define RCC_AHB2LPENSR_MDF1LPENS_Msk (0x1UL << RCC_AHB2LPENSR_MDF1LPENS_Pos) /*!< 0x00010000 */ #define RCC_AHB2LPENSR_MDF1LPENS RCC_AHB2LPENSR_MDF1LPENS_Msk /*!< MDF1 enable */ #define RCC_AHB2LPENSR_ADF1LPENS_Pos (17U) #define RCC_AHB2LPENSR_ADF1LPENS_Msk (0x1UL << RCC_AHB2LPENSR_ADF1LPENS_Pos) /*!< 0x00020000 */ #define RCC_AHB2LPENSR_ADF1LPENS RCC_AHB2LPENSR_ADF1LPENS_Msk /*!< ADF1 enable */ /**************** Bit definition for RCC_AHB3LPENSR register ****************/ #define RCC_AHB3LPENSR_RNGLPENS_Pos (0U) #define RCC_AHB3LPENSR_RNGLPENS_Msk (0x1UL << RCC_AHB3LPENSR_RNGLPENS_Pos)/*!< 0x00000001 */ #define RCC_AHB3LPENSR_RNGLPENS RCC_AHB3LPENSR_RNGLPENS_Msk /*!< RNG enable */ #define RCC_AHB3LPENSR_HASHLPENS_Pos (1U) #define RCC_AHB3LPENSR_HASHLPENS_Msk (0x1UL << RCC_AHB3LPENSR_HASHLPENS_Pos) /*!< 0x00000002 */ #define RCC_AHB3LPENSR_HASHLPENS RCC_AHB3LPENSR_HASHLPENS_Msk /*!< HASH enable */ #define RCC_AHB3LPENSR_CRYPLPENS_Pos (2U) #define RCC_AHB3LPENSR_CRYPLPENS_Msk (0x1UL << RCC_AHB3LPENSR_CRYPLPENS_Pos) /*!< 0x00000004 */ #define RCC_AHB3LPENSR_CRYPLPENS RCC_AHB3LPENSR_CRYPLPENS_Msk /*!< CRYP enable */ #define RCC_AHB3LPENSR_SAESLPENS_Pos (4U) #define RCC_AHB3LPENSR_SAESLPENS_Msk (0x1UL << RCC_AHB3LPENSR_SAESLPENS_Pos) /*!< 0x00000010 */ #define RCC_AHB3LPENSR_SAESLPENS RCC_AHB3LPENSR_SAESLPENS_Msk /*!< SAES enable */ #define RCC_AHB3LPENSR_PKALPENS_Pos (8U) #define RCC_AHB3LPENSR_PKALPENS_Msk (0x1UL << RCC_AHB3LPENSR_PKALPENS_Pos)/*!< 0x00000100 */ #define RCC_AHB3LPENSR_PKALPENS RCC_AHB3LPENSR_PKALPENS_Msk /*!< PKA enable */ #define RCC_AHB3LPENSR_RIFSCLPENS_Pos (9U) #define RCC_AHB3LPENSR_RIFSCLPENS_Msk (0x1UL << RCC_AHB3LPENSR_RIFSCLPENS_Pos) /*!< 0x00000200 */ #define RCC_AHB3LPENSR_RIFSCLPENS RCC_AHB3LPENSR_RIFSCLPENS_Msk /*!< RIFSC enable */ #define RCC_AHB3LPENSR_IACLPENS_Pos (10U) #define RCC_AHB3LPENSR_IACLPENS_Msk (0x1UL << RCC_AHB3LPENSR_IACLPENS_Pos)/*!< 0x00000400 */ #define RCC_AHB3LPENSR_IACLPENS RCC_AHB3LPENSR_IACLPENS_Msk /*!< IAC enable in Sleep mode */ #define RCC_AHB3LPENSR_RISAFLPENS_Pos (14U) #define RCC_AHB3LPENSR_RISAFLPENS_Msk (0x1UL << RCC_AHB3LPENSR_RISAFLPENS_Pos) /*!< 0x00004000 */ #define RCC_AHB3LPENSR_RISAFLPENS RCC_AHB3LPENSR_RISAFLPENS_Msk /*!< RISAF enable */ /**************** Bit definition for RCC_AHB4LPENSR register ****************/ #define RCC_AHB4LPENSR_GPIOALPENS_Pos (0U) #define RCC_AHB4LPENSR_GPIOALPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOALPENS_Pos) /*!< 0x00000001 */ #define RCC_AHB4LPENSR_GPIOALPENS RCC_AHB4LPENSR_GPIOALPENS_Msk /*!< GPIO A enable */ #define RCC_AHB4LPENSR_GPIOBLPENS_Pos (1U) #define RCC_AHB4LPENSR_GPIOBLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOBLPENS_Pos) /*!< 0x00000002 */ #define RCC_AHB4LPENSR_GPIOBLPENS RCC_AHB4LPENSR_GPIOBLPENS_Msk /*!< GPIO B enable */ #define RCC_AHB4LPENSR_GPIOCLPENS_Pos (2U) #define RCC_AHB4LPENSR_GPIOCLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOCLPENS_Pos) /*!< 0x00000004 */ #define RCC_AHB4LPENSR_GPIOCLPENS RCC_AHB4LPENSR_GPIOCLPENS_Msk /*!< GPIO C enable */ #define RCC_AHB4LPENSR_GPIODLPENS_Pos (3U) #define RCC_AHB4LPENSR_GPIODLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIODLPENS_Pos) /*!< 0x00000008 */ #define RCC_AHB4LPENSR_GPIODLPENS RCC_AHB4LPENSR_GPIODLPENS_Msk /*!< GPIO D enable */ #define RCC_AHB4LPENSR_GPIOELPENS_Pos (4U) #define RCC_AHB4LPENSR_GPIOELPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOELPENS_Pos) /*!< 0x00000010 */ #define RCC_AHB4LPENSR_GPIOELPENS RCC_AHB4LPENSR_GPIOELPENS_Msk /*!< GPIO E enable */ #define RCC_AHB4LPENSR_GPIOFLPENS_Pos (5U) #define RCC_AHB4LPENSR_GPIOFLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOFLPENS_Pos) /*!< 0x00000020 */ #define RCC_AHB4LPENSR_GPIOFLPENS RCC_AHB4LPENSR_GPIOFLPENS_Msk /*!< GPIO F enable */ #define RCC_AHB4LPENSR_GPIOGLPENS_Pos (6U) #define RCC_AHB4LPENSR_GPIOGLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOGLPENS_Pos) /*!< 0x00000040 */ #define RCC_AHB4LPENSR_GPIOGLPENS RCC_AHB4LPENSR_GPIOGLPENS_Msk /*!< GPIO G enable */ #define RCC_AHB4LPENSR_GPIOHLPENS_Pos (7U) #define RCC_AHB4LPENSR_GPIOHLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOHLPENS_Pos) /*!< 0x00000080 */ #define RCC_AHB4LPENSR_GPIOHLPENS RCC_AHB4LPENSR_GPIOHLPENS_Msk /*!< GPIO H enable */ #define RCC_AHB4LPENSR_GPIONLPENS_Pos (13U) #define RCC_AHB4LPENSR_GPIONLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIONLPENS_Pos) /*!< 0x00002000 */ #define RCC_AHB4LPENSR_GPIONLPENS RCC_AHB4LPENSR_GPIONLPENS_Msk /*!< GPIO N enable */ #define RCC_AHB4LPENSR_GPIOOLPENS_Pos (14U) #define RCC_AHB4LPENSR_GPIOOLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOOLPENS_Pos) /*!< 0x00004000 */ #define RCC_AHB4LPENSR_GPIOOLPENS RCC_AHB4LPENSR_GPIOOLPENS_Msk /*!< GPIO O enable */ #define RCC_AHB4LPENSR_GPIOPLPENS_Pos (15U) #define RCC_AHB4LPENSR_GPIOPLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOPLPENS_Pos) /*!< 0x00008000 */ #define RCC_AHB4LPENSR_GPIOPLPENS RCC_AHB4LPENSR_GPIOPLPENS_Msk /*!< GPIO P enable */ #define RCC_AHB4LPENSR_GPIOQLPENS_Pos (16U) #define RCC_AHB4LPENSR_GPIOQLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOQLPENS_Pos) /*!< 0x00010000 */ #define RCC_AHB4LPENSR_GPIOQLPENS RCC_AHB4LPENSR_GPIOQLPENS_Msk /*!< GPIO Q enable */ #define RCC_AHB4LPENSR_PWRLPENS_Pos (18U) #define RCC_AHB4LPENSR_PWRLPENS_Msk (0x1UL << RCC_AHB4LPENSR_PWRLPENS_Pos)/*!< 0x00040000 */ #define RCC_AHB4LPENSR_PWRLPENS RCC_AHB4LPENSR_PWRLPENS_Msk /*!< PWR enable */ #define RCC_AHB4LPENSR_CRCLPENS_Pos (19U) #define RCC_AHB4LPENSR_CRCLPENS_Msk (0x1UL << RCC_AHB4LPENSR_CRCLPENS_Pos)/*!< 0x00080000 */ #define RCC_AHB4LPENSR_CRCLPENS RCC_AHB4LPENSR_CRCLPENS_Msk /*!< CRC enable */ /**************** Bit definition for RCC_AHB5LPENSR register ****************/ #define RCC_AHB5LPENSR_HPDMA1LPENS_Pos (0U) #define RCC_AHB5LPENSR_HPDMA1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_HPDMA1LPENS_Pos) /*!< 0x00000001 */ #define RCC_AHB5LPENSR_HPDMA1LPENS RCC_AHB5LPENSR_HPDMA1LPENS_Msk /*!< HPDMA1 enable */ #define RCC_AHB5LPENSR_DMA2DLPENS_Pos (1U) #define RCC_AHB5LPENSR_DMA2DLPENS_Msk (0x1UL << RCC_AHB5LPENSR_DMA2DLPENS_Pos) /*!< 0x00000002 */ #define RCC_AHB5LPENSR_DMA2DLPENS RCC_AHB5LPENSR_DMA2DLPENS_Msk /*!< DMA2D enable */ #define RCC_AHB5LPENSR_JPEGLPENS_Pos (3U) #define RCC_AHB5LPENSR_JPEGLPENS_Msk (0x1UL << RCC_AHB5LPENSR_JPEGLPENS_Pos) /*!< 0x00000008 */ #define RCC_AHB5LPENSR_JPEGLPENS RCC_AHB5LPENSR_JPEGLPENS_Msk /*!< JPEG enable */ #define RCC_AHB5LPENSR_FMCLPENS_Pos (4U) #define RCC_AHB5LPENSR_FMCLPENS_Msk (0x1UL << RCC_AHB5LPENSR_FMCLPENS_Pos)/*!< 0x00000010 */ #define RCC_AHB5LPENSR_FMCLPENS RCC_AHB5LPENSR_FMCLPENS_Msk /*!< FMC enable */ #define RCC_AHB5LPENSR_XSPI1LPENS_Pos (5U) #define RCC_AHB5LPENSR_XSPI1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_XSPI1LPENS_Pos) /*!< 0x00000020 */ #define RCC_AHB5LPENSR_XSPI1LPENS RCC_AHB5LPENSR_XSPI1LPENS_Msk /*!< XSPI1 enable */ #define RCC_AHB5LPENSR_PSSILPENS_Pos (6U) #define RCC_AHB5LPENSR_PSSILPENS_Msk (0x1UL << RCC_AHB5LPENSR_PSSILPENS_Pos) /*!< 0x00000040 */ #define RCC_AHB5LPENSR_PSSILPENS RCC_AHB5LPENSR_PSSILPENS_Msk /*!< PSSI enable */ #define RCC_AHB5LPENSR_SDMMC2LPENS_Pos (7U) #define RCC_AHB5LPENSR_SDMMC2LPENS_Msk (0x1UL << RCC_AHB5LPENSR_SDMMC2LPENS_Pos) /*!< 0x00000080 */ #define RCC_AHB5LPENSR_SDMMC2LPENS RCC_AHB5LPENSR_SDMMC2LPENS_Msk /*!< SDMMC2 enable */ #define RCC_AHB5LPENSR_SDMMC1LPENS_Pos (8U) #define RCC_AHB5LPENSR_SDMMC1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_SDMMC1LPENS_Pos) /*!< 0x00000100 */ #define RCC_AHB5LPENSR_SDMMC1LPENS RCC_AHB5LPENSR_SDMMC1LPENS_Msk /*!< SDMMC1 enable */ #define RCC_AHB5LPENSR_XSPI2LPENS_Pos (12U) #define RCC_AHB5LPENSR_XSPI2LPENS_Msk (0x1UL << RCC_AHB5LPENSR_XSPI2LPENS_Pos) /*!< 0x00001000 */ #define RCC_AHB5LPENSR_XSPI2LPENS RCC_AHB5LPENSR_XSPI2LPENS_Msk /*!< XSPI2 enable */ #define RCC_AHB5LPENSR_XSPIMLPENS_Pos (13U) #define RCC_AHB5LPENSR_XSPIMLPENS_Msk (0x1UL << RCC_AHB5LPENSR_XSPIMLPENS_Pos) /*!< 0x00002000 */ #define RCC_AHB5LPENSR_XSPIMLPENS RCC_AHB5LPENSR_XSPIMLPENS_Msk /*!< XSPIM enable */ #define RCC_AHB5LPENSR_MCE1LPENS_Pos (14U) #define RCC_AHB5LPENSR_MCE1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_MCE1LPENS_Pos) /*!< 0x00004000 */ #define RCC_AHB5LPENSR_MCE1LPENS RCC_AHB5LPENSR_MCE1LPENS_Msk /*!< MCE1 enable */ #define RCC_AHB5LPENSR_MCE2LPENS_Pos (15U) #define RCC_AHB5LPENSR_MCE2LPENS_Msk (0x1UL << RCC_AHB5LPENSR_MCE2LPENS_Pos) /*!< 0x00008000 */ #define RCC_AHB5LPENSR_MCE2LPENS RCC_AHB5LPENSR_MCE2LPENS_Msk /*!< MCE2 enable */ #define RCC_AHB5LPENSR_MCE3LPENS_Pos (16U) #define RCC_AHB5LPENSR_MCE3LPENS_Msk (0x1UL << RCC_AHB5LPENSR_MCE3LPENS_Pos) /*!< 0x00010000 */ #define RCC_AHB5LPENSR_MCE3LPENS RCC_AHB5LPENSR_MCE3LPENS_Msk /*!< MCE3 enable */ #define RCC_AHB5LPENSR_XSPI3LPENS_Pos (17U) #define RCC_AHB5LPENSR_XSPI3LPENS_Msk (0x1UL << RCC_AHB5LPENSR_XSPI3LPENS_Pos) /*!< 0x00020000 */ #define RCC_AHB5LPENSR_XSPI3LPENS RCC_AHB5LPENSR_XSPI3LPENS_Msk /*!< XSPI3 enable */ #define RCC_AHB5LPENSR_MCE4LPENS_Pos (18U) #define RCC_AHB5LPENSR_MCE4LPENS_Msk (0x1UL << RCC_AHB5LPENSR_MCE4LPENS_Pos) /*!< 0x00040000 */ #define RCC_AHB5LPENSR_MCE4LPENS RCC_AHB5LPENSR_MCE4LPENS_Msk /*!< MCE4 enable */ #define RCC_AHB5LPENSR_GFXMMULPENS_Pos (19U) #define RCC_AHB5LPENSR_GFXMMULPENS_Msk (0x1UL << RCC_AHB5LPENSR_GFXMMULPENS_Pos) /*!< 0x00080000 */ #define RCC_AHB5LPENSR_GFXMMULPENS RCC_AHB5LPENSR_GFXMMULPENS_Msk /*!< GFXMMU enable */ #define RCC_AHB5LPENSR_GPU2DLPENS_Pos (20U) #define RCC_AHB5LPENSR_GPU2DLPENS_Msk (0x1UL << RCC_AHB5LPENSR_GPU2DLPENS_Pos) /*!< 0x00100000 */ #define RCC_AHB5LPENSR_GPU2DLPENS RCC_AHB5LPENSR_GPU2DLPENS_Msk /*!< GPU2D enable */ #define RCC_AHB5LPENSR_ETH1MACLPENS_Pos (22U) #define RCC_AHB5LPENSR_ETH1MACLPENS_Msk (0x1UL << RCC_AHB5LPENSR_ETH1MACLPENS_Pos) /*!< 0x00400000 */ #define RCC_AHB5LPENSR_ETH1MACLPENS RCC_AHB5LPENSR_ETH1MACLPENS_Msk /*!< ETH1MAC enable */ #define RCC_AHB5LPENSR_ETH1TXLPENS_Pos (23U) #define RCC_AHB5LPENSR_ETH1TXLPENS_Msk (0x1UL << RCC_AHB5LPENSR_ETH1TXLPENS_Pos) /*!< 0x00800000 */ #define RCC_AHB5LPENSR_ETH1TXLPENS RCC_AHB5LPENSR_ETH1TXLPENS_Msk /*!< ETH1TX enable */ #define RCC_AHB5LPENSR_ETH1RXLPENS_Pos (24U) #define RCC_AHB5LPENSR_ETH1RXLPENS_Msk (0x1UL << RCC_AHB5LPENSR_ETH1RXLPENS_Pos) /*!< 0x01000000 */ #define RCC_AHB5LPENSR_ETH1RXLPENS RCC_AHB5LPENSR_ETH1RXLPENS_Msk /*!< ETH1RX enable */ #define RCC_AHB5LPENSR_ETH1LPENS_Pos (25U) #define RCC_AHB5LPENSR_ETH1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_ETH1LPENS_Pos) /*!< 0x02000000 */ #define RCC_AHB5LPENSR_ETH1LPENS RCC_AHB5LPENSR_ETH1LPENS_Msk /*!< ETH1 enable */ #define RCC_AHB5LPENSR_OTG1LPENS_Pos (26U) #define RCC_AHB5LPENSR_OTG1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_OTG1LPENS_Pos) /*!< 0x04000000 */ #define RCC_AHB5LPENSR_OTG1LPENS RCC_AHB5LPENSR_OTG1LPENS_Msk /*!< OTG1 enable */ #define RCC_AHB5LPENSR_OTGPHY1LPENS_Pos (27U) #define RCC_AHB5LPENSR_OTGPHY1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_OTGPHY1LPENS_Pos) /*!< 0x08000000 */ #define RCC_AHB5LPENSR_OTGPHY1LPENS RCC_AHB5LPENSR_OTGPHY1LPENS_Msk /*!< OTGPHY1 enable */ #define RCC_AHB5LPENSR_OTGPHY2LPENS_Pos (28U) #define RCC_AHB5LPENSR_OTGPHY2LPENS_Msk (0x1UL << RCC_AHB5LPENSR_OTGPHY2LPENS_Pos) /*!< 0x10000000 */ #define RCC_AHB5LPENSR_OTGPHY2LPENS RCC_AHB5LPENSR_OTGPHY2LPENS_Msk /*!< OTGPHY2 enable */ #define RCC_AHB5LPENSR_OTG2LPENS_Pos (29U) #define RCC_AHB5LPENSR_OTG2LPENS_Msk (0x1UL << RCC_AHB5LPENSR_OTG2LPENS_Pos) /*!< 0x20000000 */ #define RCC_AHB5LPENSR_OTG2LPENS RCC_AHB5LPENSR_OTG2LPENS_Msk /*!< OTG2 enable */ #define RCC_AHB5LPENSR_CACHEAXILPENS_Pos (30U) #define RCC_AHB5LPENSR_CACHEAXILPENS_Msk (0x1UL << RCC_AHB5LPENSR_CACHEAXILPENS_Pos) /*!< 0x40000000 */ #define RCC_AHB5LPENSR_CACHEAXILPENS RCC_AHB5LPENSR_CACHEAXILPENS_Msk /*!< CACHEAXI enable */ #define RCC_AHB5LPENSR_NPULPENS_Pos (31U) #define RCC_AHB5LPENSR_NPULPENS_Msk (0x1UL << RCC_AHB5LPENSR_NPULPENS_Pos)/*!< 0x80000000 */ #define RCC_AHB5LPENSR_NPULPENS RCC_AHB5LPENSR_NPULPENS_Msk /*!< NPU enable */ /*************** Bit definition for RCC_APB1LPENSR1 register ****************/ #define RCC_APB1LPENSR1_TIM2LPENS_Pos (0U) #define RCC_APB1LPENSR1_TIM2LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM2LPENS_Pos) /*!< 0x00000001 */ #define RCC_APB1LPENSR1_TIM2LPENS RCC_APB1LPENSR1_TIM2LPENS_Msk /*!< TIM2 enable */ #define RCC_APB1LPENSR1_TIM3LPENS_Pos (1U) #define RCC_APB1LPENSR1_TIM3LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM3LPENS_Pos) /*!< 0x00000002 */ #define RCC_APB1LPENSR1_TIM3LPENS RCC_APB1LPENSR1_TIM3LPENS_Msk /*!< TIM3 enable */ #define RCC_APB1LPENSR1_TIM4LPENS_Pos (2U) #define RCC_APB1LPENSR1_TIM4LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM4LPENS_Pos) /*!< 0x00000004 */ #define RCC_APB1LPENSR1_TIM4LPENS RCC_APB1LPENSR1_TIM4LPENS_Msk /*!< TIM4 enable */ #define RCC_APB1LPENSR1_TIM5LPENS_Pos (3U) #define RCC_APB1LPENSR1_TIM5LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM5LPENS_Pos) /*!< 0x00000008 */ #define RCC_APB1LPENSR1_TIM5LPENS RCC_APB1LPENSR1_TIM5LPENS_Msk /*!< TIM5 enable */ #define RCC_APB1LPENSR1_TIM6LPENS_Pos (4U) #define RCC_APB1LPENSR1_TIM6LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM6LPENS_Pos) /*!< 0x00000010 */ #define RCC_APB1LPENSR1_TIM6LPENS RCC_APB1LPENSR1_TIM6LPENS_Msk /*!< TIM6 enable */ #define RCC_APB1LPENSR1_TIM7LPENS_Pos (5U) #define RCC_APB1LPENSR1_TIM7LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM7LPENS_Pos) /*!< 0x00000020 */ #define RCC_APB1LPENSR1_TIM7LPENS RCC_APB1LPENSR1_TIM7LPENS_Msk /*!< TIM7 enable */ #define RCC_APB1LPENSR1_TIM12LPENS_Pos (6U) #define RCC_APB1LPENSR1_TIM12LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM12LPENS_Pos) /*!< 0x00000040 */ #define RCC_APB1LPENSR1_TIM12LPENS RCC_APB1LPENSR1_TIM12LPENS_Msk /*!< TIM12 enable */ #define RCC_APB1LPENSR1_TIM13LPENS_Pos (7U) #define RCC_APB1LPENSR1_TIM13LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM13LPENS_Pos) /*!< 0x00000080 */ #define RCC_APB1LPENSR1_TIM13LPENS RCC_APB1LPENSR1_TIM13LPENS_Msk /*!< TIM13 enable */ #define RCC_APB1LPENSR1_TIM14LPENS_Pos (8U) #define RCC_APB1LPENSR1_TIM14LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM14LPENS_Pos) /*!< 0x00000100 */ #define RCC_APB1LPENSR1_TIM14LPENS RCC_APB1LPENSR1_TIM14LPENS_Msk /*!< TIM14 enable */ #define RCC_APB1LPENSR1_LPTIM1LPENS_Pos (9U) #define RCC_APB1LPENSR1_LPTIM1LPENS_Msk (0x1UL << RCC_APB1LPENSR1_LPTIM1LPENS_Pos) /*!< 0x00000200 */ #define RCC_APB1LPENSR1_LPTIM1LPENS RCC_APB1LPENSR1_LPTIM1LPENS_Msk /*!< LPTIM1 enable */ #define RCC_APB1LPENSR1_WWDGLPENS_Pos (11U) #define RCC_APB1LPENSR1_WWDGLPENS_Msk (0x1UL << RCC_APB1LPENSR1_WWDGLPENS_Pos) /*!< 0x00000800 */ #define RCC_APB1LPENSR1_WWDGLPENS RCC_APB1LPENSR1_WWDGLPENS_Msk /*!< WWDG enable */ #define RCC_APB1LPENSR1_TIM10LPENS_Pos (12U) #define RCC_APB1LPENSR1_TIM10LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM10LPENS_Pos) /*!< 0x00001000 */ #define RCC_APB1LPENSR1_TIM10LPENS RCC_APB1LPENSR1_TIM10LPENS_Msk /*!< TIM10 enable */ #define RCC_APB1LPENSR1_TIM11LPENS_Pos (13U) #define RCC_APB1LPENSR1_TIM11LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM11LPENS_Pos) /*!< 0x00002000 */ #define RCC_APB1LPENSR1_TIM11LPENS RCC_APB1LPENSR1_TIM11LPENS_Msk /*!< TIM11 enable */ #define RCC_APB1LPENSR1_SPI2LPENS_Pos (14U) #define RCC_APB1LPENSR1_SPI2LPENS_Msk (0x1UL << RCC_APB1LPENSR1_SPI2LPENS_Pos) /*!< 0x00004000 */ #define RCC_APB1LPENSR1_SPI2LPENS RCC_APB1LPENSR1_SPI2LPENS_Msk /*!< SPI2 enable */ #define RCC_APB1LPENSR1_SPI3LPENS_Pos (15U) #define RCC_APB1LPENSR1_SPI3LPENS_Msk (0x1UL << RCC_APB1LPENSR1_SPI3LPENS_Pos) /*!< 0x00008000 */ #define RCC_APB1LPENSR1_SPI3LPENS RCC_APB1LPENSR1_SPI3LPENS_Msk /*!< SPI3 enable */ #define RCC_APB1LPENSR1_SPDIFRX1LPENS_Pos (16U) #define RCC_APB1LPENSR1_SPDIFRX1LPENS_Msk (0x1UL << RCC_APB1LPENSR1_SPDIFRX1LPENS_Pos) /*!< 0x00010000 */ #define RCC_APB1LPENSR1_SPDIFRX1LPENS RCC_APB1LPENSR1_SPDIFRX1LPENS_Msk /*!< SPDIFRX1 enable */ #define RCC_APB1LPENSR1_USART2LPENS_Pos (17U) #define RCC_APB1LPENSR1_USART2LPENS_Msk (0x1UL << RCC_APB1LPENSR1_USART2LPENS_Pos) /*!< 0x00020000 */ #define RCC_APB1LPENSR1_USART2LPENS RCC_APB1LPENSR1_USART2LPENS_Msk /*!< USART2 enable */ #define RCC_APB1LPENSR1_USART3LPENS_Pos (18U) #define RCC_APB1LPENSR1_USART3LPENS_Msk (0x1UL << RCC_APB1LPENSR1_USART3LPENS_Pos) /*!< 0x00040000 */ #define RCC_APB1LPENSR1_USART3LPENS RCC_APB1LPENSR1_USART3LPENS_Msk /*!< USART3 enable */ #define RCC_APB1LPENSR1_UART4LPENS_Pos (19U) #define RCC_APB1LPENSR1_UART4LPENS_Msk (0x1UL << RCC_APB1LPENSR1_UART4LPENS_Pos) /*!< 0x00080000 */ #define RCC_APB1LPENSR1_UART4LPENS RCC_APB1LPENSR1_UART4LPENS_Msk /*!< UART4 enable */ #define RCC_APB1LPENSR1_UART5LPENS_Pos (20U) #define RCC_APB1LPENSR1_UART5LPENS_Msk (0x1UL << RCC_APB1LPENSR1_UART5LPENS_Pos) /*!< 0x00100000 */ #define RCC_APB1LPENSR1_UART5LPENS RCC_APB1LPENSR1_UART5LPENS_Msk /*!< UART5 enable */ #define RCC_APB1LPENSR1_I2C1LPENS_Pos (21U) #define RCC_APB1LPENSR1_I2C1LPENS_Msk (0x1UL << RCC_APB1LPENSR1_I2C1LPENS_Pos) /*!< 0x00200000 */ #define RCC_APB1LPENSR1_I2C1LPENS RCC_APB1LPENSR1_I2C1LPENS_Msk /*!< I2C1 enable */ #define RCC_APB1LPENSR1_I2C2LPENS_Pos (22U) #define RCC_APB1LPENSR1_I2C2LPENS_Msk (0x1UL << RCC_APB1LPENSR1_I2C2LPENS_Pos) /*!< 0x00400000 */ #define RCC_APB1LPENSR1_I2C2LPENS RCC_APB1LPENSR1_I2C2LPENS_Msk /*!< I2C2 enable */ #define RCC_APB1LPENSR1_I2C3LPENS_Pos (23U) #define RCC_APB1LPENSR1_I2C3LPENS_Msk (0x1UL << RCC_APB1LPENSR1_I2C3LPENS_Pos) /*!< 0x00800000 */ #define RCC_APB1LPENSR1_I2C3LPENS RCC_APB1LPENSR1_I2C3LPENS_Msk /*!< I2C3 enable */ #define RCC_APB1LPENSR1_I3C1LPENS_Pos (24U) #define RCC_APB1LPENSR1_I3C1LPENS_Msk (0x1UL << RCC_APB1LPENSR1_I3C1LPENS_Pos) /*!< 0x01000000 */ #define RCC_APB1LPENSR1_I3C1LPENS RCC_APB1LPENSR1_I3C1LPENS_Msk /*!< I3C1 enable */ #define RCC_APB1LPENSR1_I3C2LPENS_Pos (25U) #define RCC_APB1LPENSR1_I3C2LPENS_Msk (0x1UL << RCC_APB1LPENSR1_I3C2LPENS_Pos) /*!< 0x02000000 */ #define RCC_APB1LPENSR1_I3C2LPENS RCC_APB1LPENSR1_I3C2LPENS_Msk /*!< I3C2 enable */ #define RCC_APB1LPENSR1_UART7LPENS_Pos (30U) #define RCC_APB1LPENSR1_UART7LPENS_Msk (0x1UL << RCC_APB1LPENSR1_UART7LPENS_Pos) /*!< 0x40000000 */ #define RCC_APB1LPENSR1_UART7LPENS RCC_APB1LPENSR1_UART7LPENS_Msk /*!< UART7 enable */ #define RCC_APB1LPENSR1_UART8LPENS_Pos (31U) #define RCC_APB1LPENSR1_UART8LPENS_Msk (0x1UL << RCC_APB1LPENSR1_UART8LPENS_Pos) /*!< 0x80000000 */ #define RCC_APB1LPENSR1_UART8LPENS RCC_APB1LPENSR1_UART8LPENS_Msk /*!< UART8 enable */ /*************** Bit definition for RCC_APB1LPENSR2 register ****************/ #define RCC_APB1LPENSR2_MDIOSLPENS_Pos (5U) #define RCC_APB1LPENSR2_MDIOSLPENS_Msk (0x1UL << RCC_APB1LPENSR2_MDIOSLPENS_Pos) /*!< 0x00000020 */ #define RCC_APB1LPENSR2_MDIOSLPENS RCC_APB1LPENSR2_MDIOSLPENS_Msk /*!< MDIOS enable */ #define RCC_APB1LPENSR2_FDCANLPENS_Pos (8U) #define RCC_APB1LPENSR2_FDCANLPENS_Msk (0x1UL << RCC_APB1LPENSR2_FDCANLPENS_Pos) /*!< 0x00000100 */ #define RCC_APB1LPENSR2_FDCANLPENS RCC_APB1LPENSR2_FDCANLPENS_Msk /*!< FDCAN enable */ #define RCC_APB1LPENSR2_UCPD1LPENS_Pos (18U) #define RCC_APB1LPENSR2_UCPD1LPENS_Msk (0x1UL << RCC_APB1LPENSR2_UCPD1LPENS_Pos) /*!< 0x00040000 */ #define RCC_APB1LPENSR2_UCPD1LPENS RCC_APB1LPENSR2_UCPD1LPENS_Msk /*!< UCPD1 enable */ /**************** Bit definition for RCC_APB2LPENSR register ****************/ #define RCC_APB2LPENSR_TIM1LPENS_Pos (0U) #define RCC_APB2LPENSR_TIM1LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM1LPENS_Pos) /*!< 0x00000001 */ #define RCC_APB2LPENSR_TIM1LPENS RCC_APB2LPENSR_TIM1LPENS_Msk /*!< TIM1 enable */ #define RCC_APB2LPENSR_TIM8LPENS_Pos (1U) #define RCC_APB2LPENSR_TIM8LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM8LPENS_Pos) /*!< 0x00000002 */ #define RCC_APB2LPENSR_TIM8LPENS RCC_APB2LPENSR_TIM8LPENS_Msk /*!< TIM8 enable */ #define RCC_APB2LPENSR_USART1LPENS_Pos (4U) #define RCC_APB2LPENSR_USART1LPENS_Msk (0x1UL << RCC_APB2LPENSR_USART1LPENS_Pos) /*!< 0x00000010 */ #define RCC_APB2LPENSR_USART1LPENS RCC_APB2LPENSR_USART1LPENS_Msk /*!< USART1 enable */ #define RCC_APB2LPENSR_USART6LPENS_Pos (5U) #define RCC_APB2LPENSR_USART6LPENS_Msk (0x1UL << RCC_APB2LPENSR_USART6LPENS_Pos) /*!< 0x00000020 */ #define RCC_APB2LPENSR_USART6LPENS RCC_APB2LPENSR_USART6LPENS_Msk /*!< USART6 enable */ #define RCC_APB2LPENSR_UART9LPENS_Pos (6U) #define RCC_APB2LPENSR_UART9LPENS_Msk (0x1UL << RCC_APB2LPENSR_UART9LPENS_Pos) /*!< 0x00000040 */ #define RCC_APB2LPENSR_UART9LPENS RCC_APB2LPENSR_UART9LPENS_Msk /*!< UART9 enable */ #define RCC_APB2LPENSR_USART10LPENS_Pos (7U) #define RCC_APB2LPENSR_USART10LPENS_Msk (0x1UL << RCC_APB2LPENSR_USART10LPENS_Pos) /*!< 0x00000080 */ #define RCC_APB2LPENSR_USART10LPENS RCC_APB2LPENSR_USART10LPENS_Msk /*!< USART10 enable */ #define RCC_APB2LPENSR_SPI1LPENS_Pos (12U) #define RCC_APB2LPENSR_SPI1LPENS_Msk (0x1UL << RCC_APB2LPENSR_SPI1LPENS_Pos) /*!< 0x00001000 */ #define RCC_APB2LPENSR_SPI1LPENS RCC_APB2LPENSR_SPI1LPENS_Msk /*!< SPI1 enable */ #define RCC_APB2LPENSR_SPI4LPENS_Pos (13U) #define RCC_APB2LPENSR_SPI4LPENS_Msk (0x1UL << RCC_APB2LPENSR_SPI4LPENS_Pos) /*!< 0x00002000 */ #define RCC_APB2LPENSR_SPI4LPENS RCC_APB2LPENSR_SPI4LPENS_Msk /*!< SPI4 enable */ #define RCC_APB2LPENSR_TIM18LPENS_Pos (15U) #define RCC_APB2LPENSR_TIM18LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM18LPENS_Pos) /*!< 0x00008000 */ #define RCC_APB2LPENSR_TIM18LPENS RCC_APB2LPENSR_TIM18LPENS_Msk /*!< TIM18 enable */ #define RCC_APB2LPENSR_TIM15LPENS_Pos (16U) #define RCC_APB2LPENSR_TIM15LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM15LPENS_Pos) /*!< 0x00010000 */ #define RCC_APB2LPENSR_TIM15LPENS RCC_APB2LPENSR_TIM15LPENS_Msk /*!< TIM15 enable */ #define RCC_APB2LPENSR_TIM16LPENS_Pos (17U) #define RCC_APB2LPENSR_TIM16LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM16LPENS_Pos) /*!< 0x00020000 */ #define RCC_APB2LPENSR_TIM16LPENS RCC_APB2LPENSR_TIM16LPENS_Msk /*!< TIM16 enable */ #define RCC_APB2LPENSR_TIM17LPENS_Pos (18U) #define RCC_APB2LPENSR_TIM17LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM17LPENS_Pos) /*!< 0x00040000 */ #define RCC_APB2LPENSR_TIM17LPENS RCC_APB2LPENSR_TIM17LPENS_Msk /*!< TIM17 enable */ #define RCC_APB2LPENSR_TIM9LPENS_Pos (19U) #define RCC_APB2LPENSR_TIM9LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM9LPENS_Pos) /*!< 0x00080000 */ #define RCC_APB2LPENSR_TIM9LPENS RCC_APB2LPENSR_TIM9LPENS_Msk /*!< TIM9 enable */ #define RCC_APB2LPENSR_SPI5LPENS_Pos (20U) #define RCC_APB2LPENSR_SPI5LPENS_Msk (0x1UL << RCC_APB2LPENSR_SPI5LPENS_Pos) /*!< 0x00100000 */ #define RCC_APB2LPENSR_SPI5LPENS RCC_APB2LPENSR_SPI5LPENS_Msk /*!< SPI5 enable */ #define RCC_APB2LPENSR_SAI1LPENS_Pos (21U) #define RCC_APB2LPENSR_SAI1LPENS_Msk (0x1UL << RCC_APB2LPENSR_SAI1LPENS_Pos) /*!< 0x00200000 */ #define RCC_APB2LPENSR_SAI1LPENS RCC_APB2LPENSR_SAI1LPENS_Msk /*!< SAI1 enable */ #define RCC_APB2LPENSR_SAI2LPENS_Pos (22U) #define RCC_APB2LPENSR_SAI2LPENS_Msk (0x1UL << RCC_APB2LPENSR_SAI2LPENS_Pos) /*!< 0x00400000 */ #define RCC_APB2LPENSR_SAI2LPENS RCC_APB2LPENSR_SAI2LPENS_Msk /*!< SAI2 enable */ /**************** Bit definition for RCC_APB3LPENSR register ****************/ #define RCC_APB3LPENSR_DFTLPENS_Pos (2U) #define RCC_APB3LPENSR_DFTLPENS_Msk (0x1UL << RCC_APB3LPENSR_DFTLPENS_Pos)/*!< 0x00000004 */ #define RCC_APB3LPENSR_DFTLPENS RCC_APB3LPENSR_DFTLPENS_Msk /*!< DFT enable */ /*************** Bit definition for RCC_APB4LPENSR1 register ****************/ #define RCC_APB4LPENSR1_HDPLPENS_Pos (2U) #define RCC_APB4LPENSR1_HDPLPENS_Msk (0x1UL << RCC_APB4LPENSR1_HDPLPENS_Pos) /*!< 0x00000004 */ #define RCC_APB4LPENSR1_HDPLPENS RCC_APB4LPENSR1_HDPLPENS_Msk /*!< HDP enable */ #define RCC_APB4LPENSR1_LPUART1LPENS_Pos (3U) #define RCC_APB4LPENSR1_LPUART1LPENS_Msk (0x1UL << RCC_APB4LPENSR1_LPUART1LPENS_Pos) /*!< 0x00000008 */ #define RCC_APB4LPENSR1_LPUART1LPENS RCC_APB4LPENSR1_LPUART1LPENS_Msk /*!< LPUART1 enable */ #define RCC_APB4LPENSR1_SPI6LPENS_Pos (5U) #define RCC_APB4LPENSR1_SPI6LPENS_Msk (0x1UL << RCC_APB4LPENSR1_SPI6LPENS_Pos) /*!< 0x00000020 */ #define RCC_APB4LPENSR1_SPI6LPENS RCC_APB4LPENSR1_SPI6LPENS_Msk /*!< SPI6 enable */ #define RCC_APB4LPENSR1_I2C4LPENS_Pos (7U) #define RCC_APB4LPENSR1_I2C4LPENS_Msk (0x1UL << RCC_APB4LPENSR1_I2C4LPENS_Pos) /*!< 0x00000080 */ #define RCC_APB4LPENSR1_I2C4LPENS RCC_APB4LPENSR1_I2C4LPENS_Msk /*!< I2C4 enable */ #define RCC_APB4LPENSR1_LPTIM2LPENS_Pos (9U) #define RCC_APB4LPENSR1_LPTIM2LPENS_Msk (0x1UL << RCC_APB4LPENSR1_LPTIM2LPENS_Pos) /*!< 0x00000200 */ #define RCC_APB4LPENSR1_LPTIM2LPENS RCC_APB4LPENSR1_LPTIM2LPENS_Msk /*!< LPTIM2 enable */ #define RCC_APB4LPENSR1_LPTIM3LPENS_Pos (10U) #define RCC_APB4LPENSR1_LPTIM3LPENS_Msk (0x1UL << RCC_APB4LPENSR1_LPTIM3LPENS_Pos) /*!< 0x00000400 */ #define RCC_APB4LPENSR1_LPTIM3LPENS RCC_APB4LPENSR1_LPTIM3LPENS_Msk /*!< LPTIM3 enable */ #define RCC_APB4LPENSR1_LPTIM4LPENS_Pos (11U) #define RCC_APB4LPENSR1_LPTIM4LPENS_Msk (0x1UL << RCC_APB4LPENSR1_LPTIM4LPENS_Pos) /*!< 0x00000800 */ #define RCC_APB4LPENSR1_LPTIM4LPENS RCC_APB4LPENSR1_LPTIM4LPENS_Msk /*!< LPTIM4 enable */ #define RCC_APB4LPENSR1_LPTIM5LPENS_Pos (12U) #define RCC_APB4LPENSR1_LPTIM5LPENS_Msk (0x1UL << RCC_APB4LPENSR1_LPTIM5LPENS_Pos) /*!< 0x00001000 */ #define RCC_APB4LPENSR1_LPTIM5LPENS RCC_APB4LPENSR1_LPTIM5LPENS_Msk /*!< LPTIM5 enable */ #define RCC_APB4LPENSR1_VREFBUFLPENS_Pos (15U) #define RCC_APB4LPENSR1_VREFBUFLPENS_Msk (0x1UL << RCC_APB4LPENSR1_VREFBUFLPENS_Pos) /*!< 0x00008000 */ #define RCC_APB4LPENSR1_VREFBUFLPENS RCC_APB4LPENSR1_VREFBUFLPENS_Msk /*!< VREFBUF enable */ #define RCC_APB4LPENSR1_RTCLPENS_Pos (16U) #define RCC_APB4LPENSR1_RTCLPENS_Msk (0x1UL << RCC_APB4LPENSR1_RTCLPENS_Pos) /*!< 0x00010000 */ #define RCC_APB4LPENSR1_RTCLPENS RCC_APB4LPENSR1_RTCLPENS_Msk /*!< RTC enable */ #define RCC_APB4LPENSR1_RTCAPBLPENS_Pos (17U) #define RCC_APB4LPENSR1_RTCAPBLPENS_Msk (0x1UL << RCC_APB4LPENSR1_RTCAPBLPENS_Pos) /*!< 0x00020000 */ #define RCC_APB4LPENSR1_RTCAPBLPENS RCC_APB4LPENSR1_RTCAPBLPENS_Msk /*!< RTCAPB enable */ /*************** Bit definition for RCC_APB4LPENSR2 register ****************/ #define RCC_APB4LPENSR2_SYSCFGLPENS_Pos (0U) #define RCC_APB4LPENSR2_SYSCFGLPENS_Msk (0x1UL << RCC_APB4LPENSR2_SYSCFGLPENS_Pos) /*!< 0x00000001 */ #define RCC_APB4LPENSR2_SYSCFGLPENS RCC_APB4LPENSR2_SYSCFGLPENS_Msk /*!< SYSCFG enable */ #define RCC_APB4LPENSR2_BSECLPENS_Pos (1U) #define RCC_APB4LPENSR2_BSECLPENS_Msk (0x1UL << RCC_APB4LPENSR2_BSECLPENS_Pos) /*!< 0x00000002 */ #define RCC_APB4LPENSR2_BSECLPENS RCC_APB4LPENSR2_BSECLPENS_Msk /*!< BSEC enable */ #define RCC_APB4LPENSR2_DTSLPENS_Pos (2U) #define RCC_APB4LPENSR2_DTSLPENS_Msk (0x1UL << RCC_APB4LPENSR2_DTSLPENS_Pos) /*!< 0x00000004 */ #define RCC_APB4LPENSR2_DTSLPENS RCC_APB4LPENSR2_DTSLPENS_Msk /*!< DTS enable */ /**************** Bit definition for RCC_APB5LPENSR register ****************/ #define RCC_APB5LPENSR_LTDCLPENS_Pos (1U) #define RCC_APB5LPENSR_LTDCLPENS_Msk (0x1UL << RCC_APB5LPENSR_LTDCLPENS_Pos) /*!< 0x00000002 */ #define RCC_APB5LPENSR_LTDCLPENS RCC_APB5LPENSR_LTDCLPENS_Msk /*!< LTDC enable */ #define RCC_APB5LPENSR_DCMIPPLPENS_Pos (2U) #define RCC_APB5LPENSR_DCMIPPLPENS_Msk (0x1UL << RCC_APB5LPENSR_DCMIPPLPENS_Pos) /*!< 0x00000004 */ #define RCC_APB5LPENSR_DCMIPPLPENS RCC_APB5LPENSR_DCMIPPLPENS_Msk /*!< DCMIPP enable */ #define RCC_APB5LPENSR_GFXTIMLPENS_Pos (4U) #define RCC_APB5LPENSR_GFXTIMLPENS_Msk (0x1UL << RCC_APB5LPENSR_GFXTIMLPENS_Pos) /*!< 0x00000010 */ #define RCC_APB5LPENSR_GFXTIMLPENS RCC_APB5LPENSR_GFXTIMLPENS_Msk /*!< GFXTIM enable */ #define RCC_APB5LPENSR_VENCLPENS_Pos (5U) #define RCC_APB5LPENSR_VENCLPENS_Msk (0x1UL << RCC_APB5LPENSR_VENCLPENS_Pos) /*!< 0x00000020 */ #define RCC_APB5LPENSR_VENCLPENS RCC_APB5LPENSR_VENCLPENS_Msk /*!< VENC enable */ #define RCC_APB5LPENSR_CSILPENS_Pos (6U) #define RCC_APB5LPENSR_CSILPENS_Msk (0x1UL << RCC_APB5LPENSR_CSILPENS_Pos)/*!< 0x00000040 */ #define RCC_APB5LPENSR_CSILPENS RCC_APB5LPENSR_CSILPENS_Msk /*!< CSI enable */ /**************** Bit definition for RCC_PRIVCFGSR0 register ****************/ #define RCC_PRIVCFGSR0_LSIPRIVS_Pos (0U) #define RCC_PRIVCFGSR0_LSIPRIVS_Msk (0x1UL << RCC_PRIVCFGSR0_LSIPRIVS_Pos)/*!< 0x00000001 */ #define RCC_PRIVCFGSR0_LSIPRIVS RCC_PRIVCFGSR0_LSIPRIVS_Msk /*!< Privileged protection of the LSI configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGSR0_LSEPRIVS_Pos (1U) #define RCC_PRIVCFGSR0_LSEPRIVS_Msk (0x1UL << RCC_PRIVCFGSR0_LSEPRIVS_Pos)/*!< 0x00000002 */ #define RCC_PRIVCFGSR0_LSEPRIVS RCC_PRIVCFGSR0_LSEPRIVS_Msk /*!< Privileged protection of LSE configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGSR0_MSIPRIVS_Pos (2U) #define RCC_PRIVCFGSR0_MSIPRIVS_Msk (0x1UL << RCC_PRIVCFGSR0_MSIPRIVS_Pos)/*!< 0x00000004 */ #define RCC_PRIVCFGSR0_MSIPRIVS RCC_PRIVCFGSR0_MSIPRIVS_Msk /*!< Privileged protection of MSI configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGSR0_HSIPRIVS_Pos (3U) #define RCC_PRIVCFGSR0_HSIPRIVS_Msk (0x1UL << RCC_PRIVCFGSR0_HSIPRIVS_Pos)/*!< 0x00000008 */ #define RCC_PRIVCFGSR0_HSIPRIVS RCC_PRIVCFGSR0_HSIPRIVS_Msk /*!< Privileged protection of HSI configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGSR0_HSEPRIVS_Pos (4U) #define RCC_PRIVCFGSR0_HSEPRIVS_Msk (0x1UL << RCC_PRIVCFGSR0_HSEPRIVS_Pos)/*!< 0x00000010 */ #define RCC_PRIVCFGSR0_HSEPRIVS RCC_PRIVCFGSR0_HSEPRIVS_Msk /*!< Privileged protection of HSE configuration bits (enable, ready, divider) */ /**************** Bit definition for RCC_PUBCFGSR0 register *****************/ #define RCC_PUBCFGSR0_LSIPUBS_Pos (0U) #define RCC_PUBCFGSR0_LSIPUBS_Msk (0x1UL << RCC_PUBCFGSR0_LSIPUBS_Pos) /*!< 0x00000001 */ #define RCC_PUBCFGSR0_LSIPUBS RCC_PUBCFGSR0_LSIPUBS_Msk /*!< Public protection of LSI configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR0_LSEPUBS_Pos (1U) #define RCC_PUBCFGSR0_LSEPUBS_Msk (0x1UL << RCC_PUBCFGSR0_LSEPUBS_Pos) /*!< 0x00000002 */ #define RCC_PUBCFGSR0_LSEPUBS RCC_PUBCFGSR0_LSEPUBS_Msk /*!< Public protection of LSE configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR0_MSIPUBS_Pos (2U) #define RCC_PUBCFGSR0_MSIPUBS_Msk (0x1UL << RCC_PUBCFGSR0_MSIPUBS_Pos) /*!< 0x00000004 */ #define RCC_PUBCFGSR0_MSIPUBS RCC_PUBCFGSR0_MSIPUBS_Msk /*!< Public protection of MSI configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR0_HSIPUBS_Pos (3U) #define RCC_PUBCFGSR0_HSIPUBS_Msk (0x1UL << RCC_PUBCFGSR0_HSIPUBS_Pos) /*!< 0x00000008 */ #define RCC_PUBCFGSR0_HSIPUBS RCC_PUBCFGSR0_HSIPUBS_Msk /*!< Public protection of HSI configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR0_HSEPUBS_Pos (4U) #define RCC_PUBCFGSR0_HSEPUBS_Msk (0x1UL << RCC_PUBCFGSR0_HSEPUBS_Pos) /*!< 0x00000010 */ #define RCC_PUBCFGSR0_HSEPUBS RCC_PUBCFGSR0_HSEPUBS_Msk /*!< Public protection of he HSE configuration bits (enable, ready, divider) */ /**************** Bit definition for RCC_PRIVCFGSR1 register ****************/ #define RCC_PRIVCFGSR1_PLL1PRIVS_Pos (0U) #define RCC_PRIVCFGSR1_PLL1PRIVS_Msk (0x1UL << RCC_PRIVCFGSR1_PLL1PRIVS_Pos) /*!< 0x00000001 */ #define RCC_PRIVCFGSR1_PLL1PRIVS RCC_PRIVCFGSR1_PLL1PRIVS_Msk /*!< Privileged protection of PLL1 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGSR1_PLL2PRIVS_Pos (1U) #define RCC_PRIVCFGSR1_PLL2PRIVS_Msk (0x1UL << RCC_PRIVCFGSR1_PLL2PRIVS_Pos) /*!< 0x00000002 */ #define RCC_PRIVCFGSR1_PLL2PRIVS RCC_PRIVCFGSR1_PLL2PRIVS_Msk /*!< Privileged protection of PLL2 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGSR1_PLL3PRIVS_Pos (2U) #define RCC_PRIVCFGSR1_PLL3PRIVS_Msk (0x1UL << RCC_PRIVCFGSR1_PLL3PRIVS_Pos) /*!< 0x00000004 */ #define RCC_PRIVCFGSR1_PLL3PRIVS RCC_PRIVCFGSR1_PLL3PRIVS_Msk /*!< Privileged protection of PLL3 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGSR1_PLL4PRIVS_Pos (3U) #define RCC_PRIVCFGSR1_PLL4PRIVS_Msk (0x1UL << RCC_PRIVCFGSR1_PLL4PRIVS_Pos) /*!< 0x00000008 */ #define RCC_PRIVCFGSR1_PLL4PRIVS RCC_PRIVCFGSR1_PLL4PRIVS_Msk /*!< Privileged protection of PLL4 configuration bits (enable, ready, divider) */ /**************** Bit definition for RCC_PUBCFGSR1 register *****************/ #define RCC_PUBCFGSR1_PLL1PUBS_Pos (0U) #define RCC_PUBCFGSR1_PLL1PUBS_Msk (0x1UL << RCC_PUBCFGSR1_PLL1PUBS_Pos) /*!< 0x00000001 */ #define RCC_PUBCFGSR1_PLL1PUBS RCC_PUBCFGSR1_PLL1PUBS_Msk /*!< Public protection of PLL1 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR1_PLL2PUBS_Pos (1U) #define RCC_PUBCFGSR1_PLL2PUBS_Msk (0x1UL << RCC_PUBCFGSR1_PLL2PUBS_Pos) /*!< 0x00000002 */ #define RCC_PUBCFGSR1_PLL2PUBS RCC_PUBCFGSR1_PLL2PUBS_Msk /*!< Public protection of PLL2 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR1_PLL3PUBS_Pos (2U) #define RCC_PUBCFGSR1_PLL3PUBS_Msk (0x1UL << RCC_PUBCFGSR1_PLL3PUBS_Pos) /*!< 0x00000004 */ #define RCC_PUBCFGSR1_PLL3PUBS RCC_PUBCFGSR1_PLL3PUBS_Msk /*!< Public protection of PLL3 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR1_PLL4PUBS_Pos (3U) #define RCC_PUBCFGSR1_PLL4PUBS_Msk (0x1UL << RCC_PUBCFGSR1_PLL4PUBS_Pos) /*!< 0x00000008 */ #define RCC_PUBCFGSR1_PLL4PUBS RCC_PUBCFGSR1_PLL4PUBS_Msk /*!< Public protection of PLL4 configuration bits (enable, ready, divider) */ /**************** Bit definition for RCC_PRIVCFGSR2 register ****************/ #define RCC_PRIVCFGSR2_IC1PRIVS_Pos (0U) #define RCC_PRIVCFGSR2_IC1PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC1PRIVS_Pos)/*!< 0x00000001 */ #define RCC_PRIVCFGSR2_IC1PRIVS RCC_PRIVCFGSR2_IC1PRIVS_Msk /*!< Privileged protection of IC1 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGSR2_IC2PRIVS_Pos (1U) #define RCC_PRIVCFGSR2_IC2PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC2PRIVS_Pos)/*!< 0x00000002 */ #define RCC_PRIVCFGSR2_IC2PRIVS RCC_PRIVCFGSR2_IC2PRIVS_Msk /*!< Privileged protection of IC2 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGSR2_IC3PRIVS_Pos (2U) #define RCC_PRIVCFGSR2_IC3PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC3PRIVS_Pos)/*!< 0x00000004 */ #define RCC_PRIVCFGSR2_IC3PRIVS RCC_PRIVCFGSR2_IC3PRIVS_Msk /*!< Privileged protection of IC3 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGSR2_IC4PRIVS_Pos (3U) #define RCC_PRIVCFGSR2_IC4PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC4PRIVS_Pos)/*!< 0x00000008 */ #define RCC_PRIVCFGSR2_IC4PRIVS RCC_PRIVCFGSR2_IC4PRIVS_Msk /*!< Privileged protection of IC4 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGSR2_IC5PRIVS_Pos (4U) #define RCC_PRIVCFGSR2_IC5PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC5PRIVS_Pos)/*!< 0x00000010 */ #define RCC_PRIVCFGSR2_IC5PRIVS RCC_PRIVCFGSR2_IC5PRIVS_Msk /*!< Privileged protection of IC5 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGSR2_IC6PRIVS_Pos (5U) #define RCC_PRIVCFGSR2_IC6PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC6PRIVS_Pos)/*!< 0x00000020 */ #define RCC_PRIVCFGSR2_IC6PRIVS RCC_PRIVCFGSR2_IC6PRIVS_Msk /*!< Privileged protection of IC6 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGSR2_IC7PRIVS_Pos (6U) #define RCC_PRIVCFGSR2_IC7PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC7PRIVS_Pos)/*!< 0x00000040 */ #define RCC_PRIVCFGSR2_IC7PRIVS RCC_PRIVCFGSR2_IC7PRIVS_Msk /*!< Privileged protection of IC7 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGSR2_IC8PRIVS_Pos (7U) #define RCC_PRIVCFGSR2_IC8PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC8PRIVS_Pos)/*!< 0x00000080 */ #define RCC_PRIVCFGSR2_IC8PRIVS RCC_PRIVCFGSR2_IC8PRIVS_Msk /*!< Privileged protection of IC8 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGSR2_IC9PRIVS_Pos (8U) #define RCC_PRIVCFGSR2_IC9PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC9PRIVS_Pos)/*!< 0x00000100 */ #define RCC_PRIVCFGSR2_IC9PRIVS RCC_PRIVCFGSR2_IC9PRIVS_Msk /*!< Privileged protection of IC9 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGSR2_IC10PRIVS_Pos (9U) #define RCC_PRIVCFGSR2_IC10PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC10PRIVS_Pos) /*!< 0x00000200 */ #define RCC_PRIVCFGSR2_IC10PRIVS RCC_PRIVCFGSR2_IC10PRIVS_Msk /*!< Privileged protection of IC10 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGSR2_IC11PRIVS_Pos (10U) #define RCC_PRIVCFGSR2_IC11PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC11PRIVS_Pos) /*!< 0x00000400 */ #define RCC_PRIVCFGSR2_IC11PRIVS RCC_PRIVCFGSR2_IC11PRIVS_Msk /*!< Privileged protection of IC11 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGSR2_IC12PRIVS_Pos (11U) #define RCC_PRIVCFGSR2_IC12PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC12PRIVS_Pos) /*!< 0x00000800 */ #define RCC_PRIVCFGSR2_IC12PRIVS RCC_PRIVCFGSR2_IC12PRIVS_Msk /*!< Privileged protection of IC12 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGSR2_IC13PRIVS_Pos (12U) #define RCC_PRIVCFGSR2_IC13PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC13PRIVS_Pos) /*!< 0x00001000 */ #define RCC_PRIVCFGSR2_IC13PRIVS RCC_PRIVCFGSR2_IC13PRIVS_Msk /*!< Privileged protection of IC13 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGSR2_IC14PRIVS_Pos (13U) #define RCC_PRIVCFGSR2_IC14PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC14PRIVS_Pos) /*!< 0x00002000 */ #define RCC_PRIVCFGSR2_IC14PRIVS RCC_PRIVCFGSR2_IC14PRIVS_Msk /*!< Privileged protection of IC14 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGSR2_IC15PRIVS_Pos (14U) #define RCC_PRIVCFGSR2_IC15PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC15PRIVS_Pos) /*!< 0x00004000 */ #define RCC_PRIVCFGSR2_IC15PRIVS RCC_PRIVCFGSR2_IC15PRIVS_Msk /*!< Privileged protection of IC15 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGSR2_IC16PRIVS_Pos (15U) #define RCC_PRIVCFGSR2_IC16PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC16PRIVS_Pos) /*!< 0x00008000 */ #define RCC_PRIVCFGSR2_IC16PRIVS RCC_PRIVCFGSR2_IC16PRIVS_Msk /*!< Privileged protection of IC16 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGSR2_IC17PRIVS_Pos (16U) #define RCC_PRIVCFGSR2_IC17PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC17PRIVS_Pos) /*!< 0x00010000 */ #define RCC_PRIVCFGSR2_IC17PRIVS RCC_PRIVCFGSR2_IC17PRIVS_Msk /*!< Privileged protection of IC17 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGSR2_IC18PRIVS_Pos (17U) #define RCC_PRIVCFGSR2_IC18PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC18PRIVS_Pos) /*!< 0x00020000 */ #define RCC_PRIVCFGSR2_IC18PRIVS RCC_PRIVCFGSR2_IC18PRIVS_Msk /*!< Privileged protection of IC18 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGSR2_IC19PRIVS_Pos (18U) #define RCC_PRIVCFGSR2_IC19PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC19PRIVS_Pos) /*!< 0x00040000 */ #define RCC_PRIVCFGSR2_IC19PRIVS RCC_PRIVCFGSR2_IC19PRIVS_Msk /*!< Privileged protection of IC19 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGSR2_IC20PRIVS_Pos (19U) #define RCC_PRIVCFGSR2_IC20PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC20PRIVS_Pos) /*!< 0x00080000 */ #define RCC_PRIVCFGSR2_IC20PRIVS RCC_PRIVCFGSR2_IC20PRIVS_Msk /*!< Privileged protection of IC20 configuration bits (enable, ready, divider) */ /**************** Bit definition for RCC_PUBCFGSR2 register *****************/ #define RCC_PUBCFGSR2_IC1PUBS_Pos (0U) #define RCC_PUBCFGSR2_IC1PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC1PUBS_Pos) /*!< 0x00000001 */ #define RCC_PUBCFGSR2_IC1PUBS RCC_PUBCFGSR2_IC1PUBS_Msk /*!< Public protection of IC1 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR2_IC2PUBS_Pos (1U) #define RCC_PUBCFGSR2_IC2PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC2PUBS_Pos) /*!< 0x00000002 */ #define RCC_PUBCFGSR2_IC2PUBS RCC_PUBCFGSR2_IC2PUBS_Msk /*!< Public protection of IC2 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR2_IC3PUBS_Pos (2U) #define RCC_PUBCFGSR2_IC3PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC3PUBS_Pos) /*!< 0x00000004 */ #define RCC_PUBCFGSR2_IC3PUBS RCC_PUBCFGSR2_IC3PUBS_Msk /*!< Public protection of IC3 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR2_IC4PUBS_Pos (3U) #define RCC_PUBCFGSR2_IC4PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC4PUBS_Pos) /*!< 0x00000008 */ #define RCC_PUBCFGSR2_IC4PUBS RCC_PUBCFGSR2_IC4PUBS_Msk /*!< Public protection of IC4 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR2_IC5PUBS_Pos (4U) #define RCC_PUBCFGSR2_IC5PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC5PUBS_Pos) /*!< 0x00000010 */ #define RCC_PUBCFGSR2_IC5PUBS RCC_PUBCFGSR2_IC5PUBS_Msk /*!< Public protection of IC5 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR2_IC6PUBS_Pos (5U) #define RCC_PUBCFGSR2_IC6PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC6PUBS_Pos) /*!< 0x00000020 */ #define RCC_PUBCFGSR2_IC6PUBS RCC_PUBCFGSR2_IC6PUBS_Msk /*!< Public protection of IC6 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR2_IC7PUBS_Pos (6U) #define RCC_PUBCFGSR2_IC7PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC7PUBS_Pos) /*!< 0x00000040 */ #define RCC_PUBCFGSR2_IC7PUBS RCC_PUBCFGSR2_IC7PUBS_Msk /*!< Public protection of IC7 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR2_IC8PUBS_Pos (7U) #define RCC_PUBCFGSR2_IC8PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC8PUBS_Pos) /*!< 0x00000080 */ #define RCC_PUBCFGSR2_IC8PUBS RCC_PUBCFGSR2_IC8PUBS_Msk /*!< Public protection of IC8 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR2_IC9PUBS_Pos (8U) #define RCC_PUBCFGSR2_IC9PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC9PUBS_Pos) /*!< 0x00000100 */ #define RCC_PUBCFGSR2_IC9PUBS RCC_PUBCFGSR2_IC9PUBS_Msk /*!< Public protection of IC9 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR2_IC10PUBS_Pos (9U) #define RCC_PUBCFGSR2_IC10PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC10PUBS_Pos) /*!< 0x00000200 */ #define RCC_PUBCFGSR2_IC10PUBS RCC_PUBCFGSR2_IC10PUBS_Msk /*!< Public protection of IC10 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR2_IC11PUBS_Pos (10U) #define RCC_PUBCFGSR2_IC11PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC11PUBS_Pos) /*!< 0x00000400 */ #define RCC_PUBCFGSR2_IC11PUBS RCC_PUBCFGSR2_IC11PUBS_Msk /*!< Public protection of IC11 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR2_IC12PUBS_Pos (11U) #define RCC_PUBCFGSR2_IC12PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC12PUBS_Pos) /*!< 0x00000800 */ #define RCC_PUBCFGSR2_IC12PUBS RCC_PUBCFGSR2_IC12PUBS_Msk /*!< Public protection of IC12 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR2_IC13PUBS_Pos (12U) #define RCC_PUBCFGSR2_IC13PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC13PUBS_Pos) /*!< 0x00001000 */ #define RCC_PUBCFGSR2_IC13PUBS RCC_PUBCFGSR2_IC13PUBS_Msk /*!< Public protection of IC13 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR2_IC14PUBS_Pos (13U) #define RCC_PUBCFGSR2_IC14PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC14PUBS_Pos) /*!< 0x00002000 */ #define RCC_PUBCFGSR2_IC14PUBS RCC_PUBCFGSR2_IC14PUBS_Msk /*!< Public protection of IC14 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR2_IC15PUBS_Pos (14U) #define RCC_PUBCFGSR2_IC15PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC15PUBS_Pos) /*!< 0x00004000 */ #define RCC_PUBCFGSR2_IC15PUBS RCC_PUBCFGSR2_IC15PUBS_Msk /*!< Public protection of IC15 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR2_IC16PUBS_Pos (15U) #define RCC_PUBCFGSR2_IC16PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC16PUBS_Pos) /*!< 0x00008000 */ #define RCC_PUBCFGSR2_IC16PUBS RCC_PUBCFGSR2_IC16PUBS_Msk /*!< Public protection of th IC16 configuration bits (enable, ready, divider */ #define RCC_PUBCFGSR2_IC17PUBS_Pos (16U) #define RCC_PUBCFGSR2_IC17PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC17PUBS_Pos) /*!< 0x00010000 */ #define RCC_PUBCFGSR2_IC17PUBS RCC_PUBCFGSR2_IC17PUBS_Msk /*!< Public protection of IC17 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR2_IC18PUBS_Pos (17U) #define RCC_PUBCFGSR2_IC18PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC18PUBS_Pos) /*!< 0x00020000 */ #define RCC_PUBCFGSR2_IC18PUBS RCC_PUBCFGSR2_IC18PUBS_Msk /*!< Public protection of IC18 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR2_IC19PUBS_Pos (18U) #define RCC_PUBCFGSR2_IC19PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC19PUBS_Pos) /*!< 0x00040000 */ #define RCC_PUBCFGSR2_IC19PUBS RCC_PUBCFGSR2_IC19PUBS_Msk /*!< Public protection of IC19 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR2_IC20PUBS_Pos (19U) #define RCC_PUBCFGSR2_IC20PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC20PUBS_Pos) /*!< 0x00080000 */ #define RCC_PUBCFGSR2_IC20PUBS RCC_PUBCFGSR2_IC20PUBS_Msk /*!< Public protection of IC20 configuration bits (enable, ready, divider) */ /**************** Bit definition for RCC_PRIVCFGSR3 register ****************/ #define RCC_PRIVCFGSR3_MODPRIVS_Pos (0U) #define RCC_PRIVCFGSR3_MODPRIVS_Msk (0x1UL << RCC_PRIVCFGSR3_MODPRIVS_Pos)/*!< 0x00000001 */ #define RCC_PRIVCFGSR3_MODPRIVS RCC_PRIVCFGSR3_MODPRIVS_Msk /*!< Privileged protection of MOD configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGSR3_SYSPRIVS_Pos (1U) #define RCC_PRIVCFGSR3_SYSPRIVS_Msk (0x1UL << RCC_PRIVCFGSR3_SYSPRIVS_Pos)/*!< 0x00000002 */ #define RCC_PRIVCFGSR3_SYSPRIVS RCC_PRIVCFGSR3_SYSPRIVS_Msk /*!< Privileged protection of SYS configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGSR3_BUSPRIVS_Pos (2U) #define RCC_PRIVCFGSR3_BUSPRIVS_Msk (0x1UL << RCC_PRIVCFGSR3_BUSPRIVS_Pos)/*!< 0x00000004 */ #define RCC_PRIVCFGSR3_BUSPRIVS RCC_PRIVCFGSR3_BUSPRIVS_Msk /*!< Privileged protection of BUS configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGSR3_PERPRIVS_Pos (3U) #define RCC_PRIVCFGSR3_PERPRIVS_Msk (0x1UL << RCC_PRIVCFGSR3_PERPRIVS_Pos)/*!< 0x00000008 */ #define RCC_PRIVCFGSR3_PERPRIVS RCC_PRIVCFGSR3_PERPRIVS_Msk /*!< Privileged protection of PER configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGSR3_INTPRIVS_Pos (4U) #define RCC_PRIVCFGSR3_INTPRIVS_Msk (0x1UL << RCC_PRIVCFGSR3_INTPRIVS_Pos)/*!< 0x00000010 */ #define RCC_PRIVCFGSR3_INTPRIVS RCC_PRIVCFGSR3_INTPRIVS_Msk /*!< Privileged protection of INT configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGSR3_RSTPRIVS_Pos (5U) #define RCC_PRIVCFGSR3_RSTPRIVS_Msk (0x1UL << RCC_PRIVCFGSR3_RSTPRIVS_Pos)/*!< 0x00000020 */ #define RCC_PRIVCFGSR3_RSTPRIVS RCC_PRIVCFGSR3_RSTPRIVS_Msk /*!< Privileged protection of RST configuration bits (enable, ready, divider) */ /**************** Bit definition for RCC_PUBCFGSR3 register *****************/ #define RCC_PUBCFGSR3_MODPUBS_Pos (0U) #define RCC_PUBCFGSR3_MODPUBS_Msk (0x1UL << RCC_PUBCFGSR3_MODPUBS_Pos) /*!< 0x00000001 */ #define RCC_PUBCFGSR3_MODPUBS RCC_PUBCFGSR3_MODPUBS_Msk /*!< Public protection of MOD configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR3_SYSPUBS_Pos (1U) #define RCC_PUBCFGSR3_SYSPUBS_Msk (0x1UL << RCC_PUBCFGSR3_SYSPUBS_Pos) /*!< 0x00000002 */ #define RCC_PUBCFGSR3_SYSPUBS RCC_PUBCFGSR3_SYSPUBS_Msk /*!< Public protection of SYS configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR3_BUSPUBS_Pos (2U) #define RCC_PUBCFGSR3_BUSPUBS_Msk (0x1UL << RCC_PUBCFGSR3_BUSPUBS_Pos) /*!< 0x00000004 */ #define RCC_PUBCFGSR3_BUSPUBS RCC_PUBCFGSR3_BUSPUBS_Msk /*!< Public protection of BUS configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR3_PERPUBS_Pos (3U) #define RCC_PUBCFGSR3_PERPUBS_Msk (0x1UL << RCC_PUBCFGSR3_PERPUBS_Pos) /*!< 0x00000008 */ #define RCC_PUBCFGSR3_PERPUBS RCC_PUBCFGSR3_PERPUBS_Msk /*!< Public protection of PER configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR3_INTPUBS_Pos (4U) #define RCC_PUBCFGSR3_INTPUBS_Msk (0x1UL << RCC_PUBCFGSR3_INTPUBS_Pos) /*!< 0x00000010 */ #define RCC_PUBCFGSR3_INTPUBS RCC_PUBCFGSR3_INTPUBS_Msk /*!< Public protection of INT configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR3_RSTPUBS_Pos (5U) #define RCC_PUBCFGSR3_RSTPUBS_Msk (0x1UL << RCC_PUBCFGSR3_RSTPUBS_Pos) /*!< 0x00000020 */ #define RCC_PUBCFGSR3_RSTPUBS RCC_PUBCFGSR3_RSTPUBS_Msk /*!< Public protection of RST configuration bits (enable, ready, divider) */ /**************** Bit definition for RCC_PRIVCFGSR4 register ****************/ #define RCC_PRIVCFGSR4_ACLKNPRIVS_Pos (0U) #define RCC_PRIVCFGSR4_ACLKNPRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_ACLKNPRIVS_Pos) /*!< 0x00000001 */ #define RCC_PRIVCFGSR4_ACLKNPRIVS RCC_PRIVCFGSR4_ACLKNPRIVS_Msk /*!< Privileged protection of ACLKN configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGSR4_ACLKNCPRIVS_Pos (1U) #define RCC_PRIVCFGSR4_ACLKNCPRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_ACLKNCPRIVS_Pos) /*!< 0x00000002 */ #define RCC_PRIVCFGSR4_ACLKNCPRIVS RCC_PRIVCFGSR4_ACLKNCPRIVS_Msk /*!< Privileged protection of th ACLKNC configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGSR4_AHBMPRIVS_Pos (2U) #define RCC_PRIVCFGSR4_AHBMPRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_AHBMPRIVS_Pos) /*!< 0x00000004 */ #define RCC_PRIVCFGSR4_AHBMPRIVS RCC_PRIVCFGSR4_AHBMPRIVS_Msk /*!< Privileged protection of AHBM configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGSR4_AHB1PRIVS_Pos (3U) #define RCC_PRIVCFGSR4_AHB1PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_AHB1PRIVS_Pos) /*!< 0x00000008 */ #define RCC_PRIVCFGSR4_AHB1PRIVS RCC_PRIVCFGSR4_AHB1PRIVS_Msk /*!< Privileged protection of AHB1 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGSR4_AHB2PRIVS_Pos (4U) #define RCC_PRIVCFGSR4_AHB2PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_AHB2PRIVS_Pos) /*!< 0x00000010 */ #define RCC_PRIVCFGSR4_AHB2PRIVS RCC_PRIVCFGSR4_AHB2PRIVS_Msk /*!< Privileged protection of AHB2 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGSR4_AHB3PRIVS_Pos (5U) #define RCC_PRIVCFGSR4_AHB3PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_AHB3PRIVS_Pos) /*!< 0x00000020 */ #define RCC_PRIVCFGSR4_AHB3PRIVS RCC_PRIVCFGSR4_AHB3PRIVS_Msk /*!< Privileged protection of AHB3 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGSR4_AHB4PRIVS_Pos (6U) #define RCC_PRIVCFGSR4_AHB4PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_AHB4PRIVS_Pos) /*!< 0x00000040 */ #define RCC_PRIVCFGSR4_AHB4PRIVS RCC_PRIVCFGSR4_AHB4PRIVS_Msk /*!< Privileged protection of AHB4 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGSR4_AHB5PRIVS_Pos (7U) #define RCC_PRIVCFGSR4_AHB5PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_AHB5PRIVS_Pos) /*!< 0x00000080 */ #define RCC_PRIVCFGSR4_AHB5PRIVS RCC_PRIVCFGSR4_AHB5PRIVS_Msk /*!< Privileged protection of AHB5 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGSR4_APB1PRIVS_Pos (8U) #define RCC_PRIVCFGSR4_APB1PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_APB1PRIVS_Pos) /*!< 0x00000100 */ #define RCC_PRIVCFGSR4_APB1PRIVS RCC_PRIVCFGSR4_APB1PRIVS_Msk /*!< Privileged protection of APB1 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGSR4_APB2PRIVS_Pos (9U) #define RCC_PRIVCFGSR4_APB2PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_APB2PRIVS_Pos) /*!< 0x00000200 */ #define RCC_PRIVCFGSR4_APB2PRIVS RCC_PRIVCFGSR4_APB2PRIVS_Msk /*!< Privileged protection of APB2 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGSR4_APB3PRIVS_Pos (10U) #define RCC_PRIVCFGSR4_APB3PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_APB3PRIVS_Pos) /*!< 0x00000400 */ #define RCC_PRIVCFGSR4_APB3PRIVS RCC_PRIVCFGSR4_APB3PRIVS_Msk /*!< Privileged protection of APB3 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGSR4_APB4PRIVS_Pos (11U) #define RCC_PRIVCFGSR4_APB4PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_APB4PRIVS_Pos) /*!< 0x00000800 */ #define RCC_PRIVCFGSR4_APB4PRIVS RCC_PRIVCFGSR4_APB4PRIVS_Msk /*!< Privileged protection of APB4 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGSR4_APB5PRIVS_Pos (12U) #define RCC_PRIVCFGSR4_APB5PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_APB5PRIVS_Pos) /*!< 0x00001000 */ #define RCC_PRIVCFGSR4_APB5PRIVS RCC_PRIVCFGSR4_APB5PRIVS_Msk /*!< Privileged protection of APB5 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGSR4_NOCPRIVS_Pos (13U) #define RCC_PRIVCFGSR4_NOCPRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_NOCPRIVS_Pos)/*!< 0x00002000 */ #define RCC_PRIVCFGSR4_NOCPRIVS RCC_PRIVCFGSR4_NOCPRIVS_Msk /*!< Privileged protection of NOC configuration bits (enable, ready, divider) */ /**************** Bit definition for RCC_PUBCFGSR4 register *****************/ #define RCC_PUBCFGSR4_ACLKNPUBS_Pos (0U) #define RCC_PUBCFGSR4_ACLKNPUBS_Msk (0x1UL << RCC_PUBCFGSR4_ACLKNPUBS_Pos)/*!< 0x00000001 */ #define RCC_PUBCFGSR4_ACLKNPUBS RCC_PUBCFGSR4_ACLKNPUBS_Msk /*!< Public protection of ACLKN configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR4_ACLKNCPUBS_Pos (1U) #define RCC_PUBCFGSR4_ACLKNCPUBS_Msk (0x1UL << RCC_PUBCFGSR4_ACLKNCPUBS_Pos) /*!< 0x00000002 */ #define RCC_PUBCFGSR4_ACLKNCPUBS RCC_PUBCFGSR4_ACLKNCPUBS_Msk /*!< Public protection of ACLKNC configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR4_AHBMPUBS_Pos (2U) #define RCC_PUBCFGSR4_AHBMPUBS_Msk (0x1UL << RCC_PUBCFGSR4_AHBMPUBS_Pos) /*!< 0x00000004 */ #define RCC_PUBCFGSR4_AHBMPUBS RCC_PUBCFGSR4_AHBMPUBS_Msk /*!< Public protection of AHBM configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR4_AHB1PUBS_Pos (3U) #define RCC_PUBCFGSR4_AHB1PUBS_Msk (0x1UL << RCC_PUBCFGSR4_AHB1PUBS_Pos) /*!< 0x00000008 */ #define RCC_PUBCFGSR4_AHB1PUBS RCC_PUBCFGSR4_AHB1PUBS_Msk /*!< Public protection of AHB1 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR4_AHB2PUBS_Pos (4U) #define RCC_PUBCFGSR4_AHB2PUBS_Msk (0x1UL << RCC_PUBCFGSR4_AHB2PUBS_Pos) /*!< 0x00000010 */ #define RCC_PUBCFGSR4_AHB2PUBS RCC_PUBCFGSR4_AHB2PUBS_Msk /*!< Public protection of AHB2 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR4_AHB3PUBS_Pos (5U) #define RCC_PUBCFGSR4_AHB3PUBS_Msk (0x1UL << RCC_PUBCFGSR4_AHB3PUBS_Pos) /*!< 0x00000020 */ #define RCC_PUBCFGSR4_AHB3PUBS RCC_PUBCFGSR4_AHB3PUBS_Msk /*!< Public protection of AHB3 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR4_AHB4PUBS_Pos (6U) #define RCC_PUBCFGSR4_AHB4PUBS_Msk (0x1UL << RCC_PUBCFGSR4_AHB4PUBS_Pos) /*!< 0x00000040 */ #define RCC_PUBCFGSR4_AHB4PUBS RCC_PUBCFGSR4_AHB4PUBS_Msk /*!< Public protection of AHB4 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR4_AHB5PUBS_Pos (7U) #define RCC_PUBCFGSR4_AHB5PUBS_Msk (0x1UL << RCC_PUBCFGSR4_AHB5PUBS_Pos) /*!< 0x00000080 */ #define RCC_PUBCFGSR4_AHB5PUBS RCC_PUBCFGSR4_AHB5PUBS_Msk /*!< Public protection of AHB5 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR4_APB1PUBS_Pos (8U) #define RCC_PUBCFGSR4_APB1PUBS_Msk (0x1UL << RCC_PUBCFGSR4_APB1PUBS_Pos) /*!< 0x00000100 */ #define RCC_PUBCFGSR4_APB1PUBS RCC_PUBCFGSR4_APB1PUBS_Msk /*!< Public protection of APB1 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR4_APB2PUBS_Pos (9U) #define RCC_PUBCFGSR4_APB2PUBS_Msk (0x1UL << RCC_PUBCFGSR4_APB2PUBS_Pos) /*!< 0x00000200 */ #define RCC_PUBCFGSR4_APB2PUBS RCC_PUBCFGSR4_APB2PUBS_Msk /*!< Public protection of APB2 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR4_APB3PUBS_Pos (10U) #define RCC_PUBCFGSR4_APB3PUBS_Msk (0x1UL << RCC_PUBCFGSR4_APB3PUBS_Pos) /*!< 0x00000400 */ #define RCC_PUBCFGSR4_APB3PUBS RCC_PUBCFGSR4_APB3PUBS_Msk /*!< Public protection of APB3 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR4_APB4PUBS_Pos (11U) #define RCC_PUBCFGSR4_APB4PUBS_Msk (0x1UL << RCC_PUBCFGSR4_APB4PUBS_Pos) /*!< 0x00000800 */ #define RCC_PUBCFGSR4_APB4PUBS RCC_PUBCFGSR4_APB4PUBS_Msk /*!< Public protection of APB4 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR4_APB5PUBS_Pos (12U) #define RCC_PUBCFGSR4_APB5PUBS_Msk (0x1UL << RCC_PUBCFGSR4_APB5PUBS_Pos) /*!< 0x00001000 */ #define RCC_PUBCFGSR4_APB5PUBS RCC_PUBCFGSR4_APB5PUBS_Msk /*!< Public protection of APB5 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR4_NOCPUBS_Pos (13U) #define RCC_PUBCFGSR4_NOCPUBS_Msk (0x1UL << RCC_PUBCFGSR4_NOCPUBS_Pos) /*!< 0x00002000 */ #define RCC_PUBCFGSR4_NOCPUBS RCC_PUBCFGSR4_NOCPUBS_Msk /*!< Public protection of NOC configuration bits (enable, ready, divider) */ /**************** Bit definition for RCC_PUBCFGSR5 register *****************/ #define RCC_PUBCFGSR5_AXISRAM3PUBS_Pos (0U) #define RCC_PUBCFGSR5_AXISRAM3PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AXISRAM3PUBS_Pos) /*!< 0x00000001 */ #define RCC_PUBCFGSR5_AXISRAM3PUBS RCC_PUBCFGSR5_AXISRAM3PUBS_Msk /*!< Public protection of AXISRAM3 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR5_AXISRAM4PUBS_Pos (1U) #define RCC_PUBCFGSR5_AXISRAM4PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AXISRAM4PUBS_Pos) /*!< 0x00000002 */ #define RCC_PUBCFGSR5_AXISRAM4PUBS RCC_PUBCFGSR5_AXISRAM4PUBS_Msk /*!< Public protection of AXISRAM4 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR5_AXISRAM5PUBS_Pos (2U) #define RCC_PUBCFGSR5_AXISRAM5PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AXISRAM5PUBS_Pos) /*!< 0x00000004 */ #define RCC_PUBCFGSR5_AXISRAM5PUBS RCC_PUBCFGSR5_AXISRAM5PUBS_Msk /*!< Public protection of AXISRAM5 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR5_AXISRAM6PUBS_Pos (3U) #define RCC_PUBCFGSR5_AXISRAM6PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AXISRAM6PUBS_Pos) /*!< 0x00000008 */ #define RCC_PUBCFGSR5_AXISRAM6PUBS RCC_PUBCFGSR5_AXISRAM6PUBS_Msk /*!< Public protection of AXISRAM6 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR5_AHBSRAM1PUBS_Pos (4U) #define RCC_PUBCFGSR5_AHBSRAM1PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AHBSRAM1PUBS_Pos) /*!< 0x00000010 */ #define RCC_PUBCFGSR5_AHBSRAM1PUBS RCC_PUBCFGSR5_AHBSRAM1PUBS_Msk /*!< Public protection of AHBSRAM1 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR5_AHBSRAM2PUBS_Pos (5U) #define RCC_PUBCFGSR5_AHBSRAM2PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AHBSRAM2PUBS_Pos) /*!< 0x00000020 */ #define RCC_PUBCFGSR5_AHBSRAM2PUBS RCC_PUBCFGSR5_AHBSRAM2PUBS_Msk /*!< Public protection of AHBSRAM2 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR5_BKPSRAMPUBS_Pos (6U) #define RCC_PUBCFGSR5_BKPSRAMPUBS_Msk (0x1UL << RCC_PUBCFGSR5_BKPSRAMPUBS_Pos) /*!< 0x00000040 */ #define RCC_PUBCFGSR5_BKPSRAMPUBS RCC_PUBCFGSR5_BKPSRAMPUBS_Msk /*!< Public protection of BKPSRAM configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR5_AXISRAM1PUBS_Pos (7U) #define RCC_PUBCFGSR5_AXISRAM1PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AXISRAM1PUBS_Pos) /*!< 0x00000080 */ #define RCC_PUBCFGSR5_AXISRAM1PUBS RCC_PUBCFGSR5_AXISRAM1PUBS_Msk /*!< Public protection of AXISRAM1 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR5_AXISRAM2PUBS_Pos (8U) #define RCC_PUBCFGSR5_AXISRAM2PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AXISRAM2PUBS_Pos) /*!< 0x00000100 */ #define RCC_PUBCFGSR5_AXISRAM2PUBS RCC_PUBCFGSR5_AXISRAM2PUBS_Msk /*!< Public protection of AXISRAM2 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR5_FLEXRAMPUBS_Pos (9U) #define RCC_PUBCFGSR5_FLEXRAMPUBS_Msk (0x1UL << RCC_PUBCFGSR5_FLEXRAMPUBS_Pos) /*!< 0x00000200 */ #define RCC_PUBCFGSR5_FLEXRAMPUBS RCC_PUBCFGSR5_FLEXRAMPUBS_Msk /*!< Public protection of FLEXRAM configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR5_CACHEAXIRAMPUBS_Pos (10U) #define RCC_PUBCFGSR5_CACHEAXIRAMPUBS_Msk (0x1UL << RCC_PUBCFGSR5_CACHEAXIRAMPUBS_Pos) /*!< 0x00000400 */ #define RCC_PUBCFGSR5_CACHEAXIRAMPUBS RCC_PUBCFGSR5_CACHEAXIRAMPUBS_Msk /*!< Public protection of CACHEAXIRAM configuration bits (enable, ready, divider) */ #define RCC_PUBCFGSR5_VENCRAMPUBS_Pos (11U) #define RCC_PUBCFGSR5_VENCRAMPUBS_Msk (0x1UL << RCC_PUBCFGSR5_VENCRAMPUBS_Pos) /*!< 0x00000800 */ #define RCC_PUBCFGSR5_VENCRAMPUBS RCC_PUBCFGSR5_VENCRAMPUBS_Msk /*!< Public protection of VENCRAM configuration bits (enable, ready, divider) */ /******************* Bit definition for RCC_CCR register ********************/ #define RCC_CCR_LSIONC_Pos (0U) #define RCC_CCR_LSIONC_Msk (0x1UL << RCC_CCR_LSIONC_Pos) /*!< 0x00000001 */ #define RCC_CCR_LSIONC RCC_CCR_LSIONC_Msk /*!< LSI oscillator enable */ #define RCC_CCR_LSEONC_Pos (1U) #define RCC_CCR_LSEONC_Msk (0x1UL << RCC_CCR_LSEONC_Pos) /*!< 0x00000002 */ #define RCC_CCR_LSEONC RCC_CCR_LSEONC_Msk /*!< LSE oscillator enable */ #define RCC_CCR_MSIONC_Pos (2U) #define RCC_CCR_MSIONC_Msk (0x1UL << RCC_CCR_MSIONC_Pos) /*!< 0x00000004 */ #define RCC_CCR_MSIONC RCC_CCR_MSIONC_Msk /*!< MSI oscillator enable */ #define RCC_CCR_HSIONC_Pos (3U) #define RCC_CCR_HSIONC_Msk (0x1UL << RCC_CCR_HSIONC_Pos) /*!< 0x00000008 */ #define RCC_CCR_HSIONC RCC_CCR_HSIONC_Msk /*!< HSI oscillator enable */ #define RCC_CCR_HSEONC_Pos (4U) #define RCC_CCR_HSEONC_Msk (0x1UL << RCC_CCR_HSEONC_Pos) /*!< 0x00000010 */ #define RCC_CCR_HSEONC RCC_CCR_HSEONC_Msk /*!< HSE oscillator enable */ #define RCC_CCR_PLL1ONC_Pos (8U) #define RCC_CCR_PLL1ONC_Msk (0x1UL << RCC_CCR_PLL1ONC_Pos) /*!< 0x00000100 */ #define RCC_CCR_PLL1ONC RCC_CCR_PLL1ONC_Msk /*!< PLL1 oscillator enable */ #define RCC_CCR_PLL2ONC_Pos (9U) #define RCC_CCR_PLL2ONC_Msk (0x1UL << RCC_CCR_PLL2ONC_Pos) /*!< 0x00000200 */ #define RCC_CCR_PLL2ONC RCC_CCR_PLL2ONC_Msk /*!< PLL2 oscillator enable */ #define RCC_CCR_PLL3ONC_Pos (10U) #define RCC_CCR_PLL3ONC_Msk (0x1UL << RCC_CCR_PLL3ONC_Pos) /*!< 0x00000400 */ #define RCC_CCR_PLL3ONC RCC_CCR_PLL3ONC_Msk /*!< PLL3 oscillator enable */ #define RCC_CCR_PLL4ONC_Pos (11U) #define RCC_CCR_PLL4ONC_Msk (0x1UL << RCC_CCR_PLL4ONC_Pos) /*!< 0x00000800 */ #define RCC_CCR_PLL4ONC RCC_CCR_PLL4ONC_Msk /*!< PLL4 oscillator enable */ /***************** Bit definition for RCC_STOPCCR register ******************/ #define RCC_STOPCCR_MSISTOPENC_Pos (0U) #define RCC_STOPCCR_MSISTOPENC_Msk (0x1UL << RCC_STOPCCR_MSISTOPENC_Pos) /*!< 0x00000001 */ #define RCC_STOPCCR_MSISTOPENC RCC_STOPCCR_MSISTOPENC_Msk /*!< MSI oscillator enable */ #define RCC_STOPCCR_HSISTOPENC_Pos (1U) #define RCC_STOPCCR_HSISTOPENC_Msk (0x1UL << RCC_STOPCCR_HSISTOPENC_Pos) /*!< 0x00000002 */ #define RCC_STOPCCR_HSISTOPENC RCC_STOPCCR_HSISTOPENC_Msk /*!< HSI oscillator enable */ /**************** Bit definition for RCC_MISCRSTCR register *****************/ #define RCC_MISCRSTCR_DBGRSTC_Pos (0U) #define RCC_MISCRSTCR_DBGRSTC_Msk (0x1UL << RCC_MISCRSTCR_DBGRSTC_Pos) /*!< 0x00000001 */ #define RCC_MISCRSTCR_DBGRSTC RCC_MISCRSTCR_DBGRSTC_Msk /*!< DBG reset */ #define RCC_MISCRSTCR_XSPIPHY1RSTC_Pos (4U) #define RCC_MISCRSTCR_XSPIPHY1RSTC_Msk (0x1UL << RCC_MISCRSTCR_XSPIPHY1RSTC_Pos) /*!< 0x00000010 */ #define RCC_MISCRSTCR_XSPIPHY1RSTC RCC_MISCRSTCR_XSPIPHY1RSTC_Msk /*!< XSPIPHY1 reset */ #define RCC_MISCRSTCR_XSPIPHY2RSTC_Pos (5U) #define RCC_MISCRSTCR_XSPIPHY2RSTC_Msk (0x1UL << RCC_MISCRSTCR_XSPIPHY2RSTC_Pos) /*!< 0x00000020 */ #define RCC_MISCRSTCR_XSPIPHY2RSTC RCC_MISCRSTCR_XSPIPHY2RSTC_Msk /*!< XSPIPHY2 reset */ #define RCC_MISCRSTCR_SDMMC1DLLRSTC_Pos (7U) #define RCC_MISCRSTCR_SDMMC1DLLRSTC_Msk (0x1UL << RCC_MISCRSTCR_SDMMC1DLLRSTC_Pos) /*!< 0x00000080 */ #define RCC_MISCRSTCR_SDMMC1DLLRSTC RCC_MISCRSTCR_SDMMC1DLLRSTC_Msk /*!< SDMMC1DLL reset */ #define RCC_MISCRSTCR_SDMMC2DLLRSTC_Pos (8U) #define RCC_MISCRSTCR_SDMMC2DLLRSTC_Msk (0x1UL << RCC_MISCRSTCR_SDMMC2DLLRSTC_Pos) /*!< 0x00000100 */ #define RCC_MISCRSTCR_SDMMC2DLLRSTC RCC_MISCRSTCR_SDMMC2DLLRSTC_Msk /*!< SDMMC2DLL reset */ /***************** Bit definition for RCC_MEMRSTCR register *****************/ #define RCC_MEMRSTCR_AXISRAM3RSTC_Pos (0U) #define RCC_MEMRSTCR_AXISRAM3RSTC_Msk (0x1UL << RCC_MEMRSTCR_AXISRAM3RSTC_Pos) /*!< 0x00000001 */ #define RCC_MEMRSTCR_AXISRAM3RSTC RCC_MEMRSTCR_AXISRAM3RSTC_Msk /*!< AXISRAM3 reset */ #define RCC_MEMRSTCR_AXISRAM4RSTC_Pos (1U) #define RCC_MEMRSTCR_AXISRAM4RSTC_Msk (0x1UL << RCC_MEMRSTCR_AXISRAM4RSTC_Pos) /*!< 0x00000002 */ #define RCC_MEMRSTCR_AXISRAM4RSTC RCC_MEMRSTCR_AXISRAM4RSTC_Msk /*!< AXISRAM4 reset */ #define RCC_MEMRSTCR_AXISRAM5RSTC_Pos (2U) #define RCC_MEMRSTCR_AXISRAM5RSTC_Msk (0x1UL << RCC_MEMRSTCR_AXISRAM5RSTC_Pos) /*!< 0x00000004 */ #define RCC_MEMRSTCR_AXISRAM5RSTC RCC_MEMRSTCR_AXISRAM5RSTC_Msk /*!< AXISRAM5 reset */ #define RCC_MEMRSTCR_AXISRAM6RSTC_Pos (3U) #define RCC_MEMRSTCR_AXISRAM6RSTC_Msk (0x1UL << RCC_MEMRSTCR_AXISRAM6RSTC_Pos) /*!< 0x00000008 */ #define RCC_MEMRSTCR_AXISRAM6RSTC RCC_MEMRSTCR_AXISRAM6RSTC_Msk /*!< AXISRAM6 reset */ #define RCC_MEMRSTCR_AHBSRAM1RSTC_Pos (4U) #define RCC_MEMRSTCR_AHBSRAM1RSTC_Msk (0x1UL << RCC_MEMRSTCR_AHBSRAM1RSTC_Pos) /*!< 0x00000010 */ #define RCC_MEMRSTCR_AHBSRAM1RSTC RCC_MEMRSTCR_AHBSRAM1RSTC_Msk /*!< AHBSRAM1 reset */ #define RCC_MEMRSTCR_AHBSRAM2RSTC_Pos (5U) #define RCC_MEMRSTCR_AHBSRAM2RSTC_Msk (0x1UL << RCC_MEMRSTCR_AHBSRAM2RSTC_Pos) /*!< 0x00000020 */ #define RCC_MEMRSTCR_AHBSRAM2RSTC RCC_MEMRSTCR_AHBSRAM2RSTC_Msk /*!< AHBSRAM2 reset */ #define RCC_MEMRSTCR_AXISRAM1RSTC_Pos (7U) #define RCC_MEMRSTCR_AXISRAM1RSTC_Msk (0x1UL << RCC_MEMRSTCR_AXISRAM1RSTC_Pos) /*!< 0x00000080 */ #define RCC_MEMRSTCR_AXISRAM1RSTC RCC_MEMRSTCR_AXISRAM1RSTC_Msk /*!< AXISRAM1 reset */ #define RCC_MEMRSTCR_AXISRAM2RSTC_Pos (8U) #define RCC_MEMRSTCR_AXISRAM2RSTC_Msk (0x1UL << RCC_MEMRSTCR_AXISRAM2RSTC_Pos) /*!< 0x00000100 */ #define RCC_MEMRSTCR_AXISRAM2RSTC RCC_MEMRSTCR_AXISRAM2RSTC_Msk /*!< AXISRAM2 reset */ #define RCC_MEMRSTCR_FLEXRAMRSTC_Pos (9U) #define RCC_MEMRSTCR_FLEXRAMRSTC_Msk (0x1UL << RCC_MEMRSTCR_FLEXRAMRSTC_Pos) /*!< 0x00000200 */ #define RCC_MEMRSTCR_FLEXRAMRSTC RCC_MEMRSTCR_FLEXRAMRSTC_Msk /*!< FLEXRAM reset */ #define RCC_MEMRSTCR_CACHEAXIRAMRSTC_Pos (10U) #define RCC_MEMRSTCR_CACHEAXIRAMRSTC_Msk (0x1UL << RCC_MEMRSTCR_CACHEAXIRAMRSTC_Pos) /*!< 0x00000400 */ #define RCC_MEMRSTCR_CACHEAXIRAMRSTC RCC_MEMRSTCR_CACHEAXIRAMRSTC_Msk /*!< CACHEAXIRAM reset */ #define RCC_MEMRSTCR_VENCRAMRSTC_Pos (11U) #define RCC_MEMRSTCR_VENCRAMRSTC_Msk (0x1UL << RCC_MEMRSTCR_VENCRAMRSTC_Pos) /*!< 0x00000800 */ #define RCC_MEMRSTCR_VENCRAMRSTC RCC_MEMRSTCR_VENCRAMRSTC_Msk /*!< VENCRAM reset */ #define RCC_MEMRSTCR_BOOTROMRSTC_Pos (12U) #define RCC_MEMRSTCR_BOOTROMRSTC_Msk (0x1UL << RCC_MEMRSTCR_BOOTROMRSTC_Pos) /*!< 0x00001000 */ #define RCC_MEMRSTCR_BOOTROMRSTC RCC_MEMRSTCR_BOOTROMRSTC_Msk /*!< Boot ROM reset */ /**************** Bit definition for RCC_AHB1RSTCR register *****************/ #define RCC_AHB1RSTCR_GPDMA1RSTC_Pos (4U) #define RCC_AHB1RSTCR_GPDMA1RSTC_Msk (0x1UL << RCC_AHB1RSTCR_GPDMA1RSTC_Pos) /*!< 0x00000010 */ #define RCC_AHB1RSTCR_GPDMA1RSTC RCC_AHB1RSTCR_GPDMA1RSTC_Msk /*!< GPDMA1 reset */ #define RCC_AHB1RSTCR_ADC12RSTC_Pos (5U) #define RCC_AHB1RSTCR_ADC12RSTC_Msk (0x1UL << RCC_AHB1RSTCR_ADC12RSTC_Pos)/*!< 0x00000020 */ #define RCC_AHB1RSTCR_ADC12RSTC RCC_AHB1RSTCR_ADC12RSTC_Msk /*!< ADC12 reset */ /**************** Bit definition for RCC_AHB2RSTCR register *****************/ #define RCC_AHB2RSTCR_RAMCFGRSTC_Pos (12U) #define RCC_AHB2RSTCR_RAMCFGRSTC_Msk (0x1UL << RCC_AHB2RSTCR_RAMCFGRSTC_Pos) /*!< 0x00001000 */ #define RCC_AHB2RSTCR_RAMCFGRSTC RCC_AHB2RSTCR_RAMCFGRSTC_Msk /*!< RAMCFG reset */ #define RCC_AHB2RSTCR_MDF1RSTC_Pos (16U) #define RCC_AHB2RSTCR_MDF1RSTC_Msk (0x1UL << RCC_AHB2RSTCR_MDF1RSTC_Pos) /*!< 0x00010000 */ #define RCC_AHB2RSTCR_MDF1RSTC RCC_AHB2RSTCR_MDF1RSTC_Msk /*!< MDF1 reset */ #define RCC_AHB2RSTCR_ADF1RSTC_Pos (17U) #define RCC_AHB2RSTCR_ADF1RSTC_Msk (0x1UL << RCC_AHB2RSTCR_ADF1RSTC_Pos) /*!< 0x00020000 */ #define RCC_AHB2RSTCR_ADF1RSTC RCC_AHB2RSTCR_ADF1RSTC_Msk /*!< ADF1 reset */ /**************** Bit definition for RCC_AHB3RSTCR register *****************/ #define RCC_AHB3RSTCR_RNGRSTC_Pos (0U) #define RCC_AHB3RSTCR_RNGRSTC_Msk (0x1UL << RCC_AHB3RSTCR_RNGRSTC_Pos) /*!< 0x00000001 */ #define RCC_AHB3RSTCR_RNGRSTC RCC_AHB3RSTCR_RNGRSTC_Msk /*!< RNG reset */ #define RCC_AHB3RSTCR_HASHRSTC_Pos (1U) #define RCC_AHB3RSTCR_HASHRSTC_Msk (0x1UL << RCC_AHB3RSTCR_HASHRSTC_Pos) /*!< 0x00000002 */ #define RCC_AHB3RSTCR_HASHRSTC RCC_AHB3RSTCR_HASHRSTC_Msk /*!< HASH reset */ #define RCC_AHB3RSTCR_CRYPRSTC_Pos (2U) #define RCC_AHB3RSTCR_CRYPRSTC_Msk (0x1UL << RCC_AHB3RSTCR_CRYPRSTC_Pos) /*!< 0x00000004 */ #define RCC_AHB3RSTCR_CRYPRSTC RCC_AHB3RSTCR_CRYPRSTC_Msk /*!< CRYP reset */ #define RCC_AHB3RSTCR_SAESRSTC_Pos (4U) #define RCC_AHB3RSTCR_SAESRSTC_Msk (0x1UL << RCC_AHB3RSTCR_SAESRSTC_Pos) /*!< 0x00000010 */ #define RCC_AHB3RSTCR_SAESRSTC RCC_AHB3RSTCR_SAESRSTC_Msk /*!< SAES reset */ #define RCC_AHB3RSTCR_PKARSTC_Pos (8U) #define RCC_AHB3RSTCR_PKARSTC_Msk (0x1UL << RCC_AHB3RSTCR_PKARSTC_Pos) /*!< 0x00000100 */ #define RCC_AHB3RSTCR_PKARSTC RCC_AHB3RSTCR_PKARSTC_Msk /*!< PKA reset */ #define RCC_AHB3RSTCR_IACRSTC_Pos (10U) #define RCC_AHB3RSTCR_IACRSTC_Msk (0x1UL << RCC_AHB3RSTCR_IACRSTC_Pos) /*!< 0x00000400 */ #define RCC_AHB3RSTCR_IACRSTC RCC_AHB3RSTCR_IACRSTC_Msk /*!< IAC reset */ /**************** Bit definition for RCC_AHB4RSTCR register *****************/ #define RCC_AHB4RSTCR_GPIOARSTC_Pos (0U) #define RCC_AHB4RSTCR_GPIOARSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOARSTC_Pos)/*!< 0x00000001 */ #define RCC_AHB4RSTCR_GPIOARSTC RCC_AHB4RSTCR_GPIOARSTC_Msk /*!< GPIO A reset */ #define RCC_AHB4RSTCR_GPIOBRSTC_Pos (1U) #define RCC_AHB4RSTCR_GPIOBRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOBRSTC_Pos)/*!< 0x00000002 */ #define RCC_AHB4RSTCR_GPIOBRSTC RCC_AHB4RSTCR_GPIOBRSTC_Msk /*!< GPIO B reset */ #define RCC_AHB4RSTCR_GPIOCRSTC_Pos (2U) #define RCC_AHB4RSTCR_GPIOCRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOCRSTC_Pos)/*!< 0x00000004 */ #define RCC_AHB4RSTCR_GPIOCRSTC RCC_AHB4RSTCR_GPIOCRSTC_Msk /*!< GPIO C reset */ #define RCC_AHB4RSTCR_GPIODRSTC_Pos (3U) #define RCC_AHB4RSTCR_GPIODRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIODRSTC_Pos)/*!< 0x00000008 */ #define RCC_AHB4RSTCR_GPIODRSTC RCC_AHB4RSTCR_GPIODRSTC_Msk /*!< GPIO D reset */ #define RCC_AHB4RSTCR_GPIOERSTC_Pos (4U) #define RCC_AHB4RSTCR_GPIOERSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOERSTC_Pos)/*!< 0x00000010 */ #define RCC_AHB4RSTCR_GPIOERSTC RCC_AHB4RSTCR_GPIOERSTC_Msk /*!< GPIO E reset */ #define RCC_AHB4RSTCR_GPIOFRSTC_Pos (5U) #define RCC_AHB4RSTCR_GPIOFRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOFRSTC_Pos)/*!< 0x00000020 */ #define RCC_AHB4RSTCR_GPIOFRSTC RCC_AHB4RSTCR_GPIOFRSTC_Msk /*!< GPIO F reset */ #define RCC_AHB4RSTCR_GPIOGRSTC_Pos (6U) #define RCC_AHB4RSTCR_GPIOGRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOGRSTC_Pos)/*!< 0x00000040 */ #define RCC_AHB4RSTCR_GPIOGRSTC RCC_AHB4RSTCR_GPIOGRSTC_Msk /*!< GPIO G reset */ #define RCC_AHB4RSTCR_GPIOHRSTC_Pos (7U) #define RCC_AHB4RSTCR_GPIOHRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOHRSTC_Pos)/*!< 0x00000080 */ #define RCC_AHB4RSTCR_GPIOHRSTC RCC_AHB4RSTCR_GPIOHRSTC_Msk /*!< GPIO H reset */ #define RCC_AHB4RSTCR_GPIONRSTC_Pos (13U) #define RCC_AHB4RSTCR_GPIONRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIONRSTC_Pos)/*!< 0x00002000 */ #define RCC_AHB4RSTCR_GPIONRSTC RCC_AHB4RSTCR_GPIONRSTC_Msk /*!< GPIO N reset */ #define RCC_AHB4RSTCR_GPIOORSTC_Pos (14U) #define RCC_AHB4RSTCR_GPIOORSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOORSTC_Pos)/*!< 0x00004000 */ #define RCC_AHB4RSTCR_GPIOORSTC RCC_AHB4RSTCR_GPIOORSTC_Msk /*!< GPIO O reset */ #define RCC_AHB4RSTCR_GPIOPRSTC_Pos (15U) #define RCC_AHB4RSTCR_GPIOPRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOPRSTC_Pos)/*!< 0x00008000 */ #define RCC_AHB4RSTCR_GPIOPRSTC RCC_AHB4RSTCR_GPIOPRSTC_Msk /*!< GPIO P reset */ #define RCC_AHB4RSTCR_GPIOQRSTC_Pos (16U) #define RCC_AHB4RSTCR_GPIOQRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOQRSTC_Pos)/*!< 0x00010000 */ #define RCC_AHB4RSTCR_GPIOQRSTC RCC_AHB4RSTCR_GPIOQRSTC_Msk /*!< GPIO Q reset */ #define RCC_AHB4RSTCR_PWRRSTC_Pos (18U) #define RCC_AHB4RSTCR_PWRRSTC_Msk (0x1UL << RCC_AHB4RSTCR_PWRRSTC_Pos) /*!< 0x00040000 */ #define RCC_AHB4RSTCR_PWRRSTC RCC_AHB4RSTCR_PWRRSTC_Msk /*!< PWR reset */ #define RCC_AHB4RSTCR_CRCRSTC_Pos (19U) #define RCC_AHB4RSTCR_CRCRSTC_Msk (0x1UL << RCC_AHB4RSTCR_CRCRSTC_Pos) /*!< 0x00080000 */ #define RCC_AHB4RSTCR_CRCRSTC RCC_AHB4RSTCR_CRCRSTC_Msk /*!< CRC reset */ /**************** Bit definition for RCC_AHB5RSTCR register *****************/ #define RCC_AHB5RSTCR_HPDMA1RSTC_Pos (0U) #define RCC_AHB5RSTCR_HPDMA1RSTC_Msk (0x1UL << RCC_AHB5RSTCR_HPDMA1RSTC_Pos) /*!< 0x00000001 */ #define RCC_AHB5RSTCR_HPDMA1RSTC RCC_AHB5RSTCR_HPDMA1RSTC_Msk /*!< HPDMA1 reset */ #define RCC_AHB5RSTCR_DMA2DRSTC_Pos (1U) #define RCC_AHB5RSTCR_DMA2DRSTC_Msk (0x1UL << RCC_AHB5RSTCR_DMA2DRSTC_Pos)/*!< 0x00000002 */ #define RCC_AHB5RSTCR_DMA2DRSTC RCC_AHB5RSTCR_DMA2DRSTC_Msk /*!< DMA2D reset */ #define RCC_AHB5RSTCR_JPEGRSTC_Pos (3U) #define RCC_AHB5RSTCR_JPEGRSTC_Msk (0x1UL << RCC_AHB5RSTCR_JPEGRSTC_Pos) /*!< 0x00000008 */ #define RCC_AHB5RSTCR_JPEGRSTC RCC_AHB5RSTCR_JPEGRSTC_Msk /*!< JPEG reset */ #define RCC_AHB5RSTCR_FMCRSTC_Pos (4U) #define RCC_AHB5RSTCR_FMCRSTC_Msk (0x1UL << RCC_AHB5RSTCR_FMCRSTC_Pos) /*!< 0x00000010 */ #define RCC_AHB5RSTCR_FMCRSTC RCC_AHB5RSTCR_FMCRSTC_Msk /*!< FMC reset */ #define RCC_AHB5RSTCR_XSPI1RSTC_Pos (5U) #define RCC_AHB5RSTCR_XSPI1RSTC_Msk (0x1UL << RCC_AHB5RSTCR_XSPI1RSTC_Pos)/*!< 0x00000020 */ #define RCC_AHB5RSTCR_XSPI1RSTC RCC_AHB5RSTCR_XSPI1RSTC_Msk /*!< XSPI1 reset */ #define RCC_AHB5RSTCR_PSSIRSTC_Pos (6U) #define RCC_AHB5RSTCR_PSSIRSTC_Msk (0x1UL << RCC_AHB5RSTCR_PSSIRSTC_Pos) /*!< 0x00000040 */ #define RCC_AHB5RSTCR_PSSIRSTC RCC_AHB5RSTCR_PSSIRSTC_Msk /*!< PSSI reset */ #define RCC_AHB5RSTCR_SDMMC2RSTC_Pos (7U) #define RCC_AHB5RSTCR_SDMMC2RSTC_Msk (0x1UL << RCC_AHB5RSTCR_SDMMC2RSTC_Pos) /*!< 0x00000080 */ #define RCC_AHB5RSTCR_SDMMC2RSTC RCC_AHB5RSTCR_SDMMC2RSTC_Msk /*!< SDMMC2 reset */ #define RCC_AHB5RSTCR_SDMMC1RSTC_Pos (8U) #define RCC_AHB5RSTCR_SDMMC1RSTC_Msk (0x1UL << RCC_AHB5RSTCR_SDMMC1RSTC_Pos) /*!< 0x00000100 */ #define RCC_AHB5RSTCR_SDMMC1RSTC RCC_AHB5RSTCR_SDMMC1RSTC_Msk /*!< SDMMC1 reset */ #define RCC_AHB5RSTCR_XSPI2RSTC_Pos (12U) #define RCC_AHB5RSTCR_XSPI2RSTC_Msk (0x1UL << RCC_AHB5RSTCR_XSPI2RSTC_Pos)/*!< 0x00001000 */ #define RCC_AHB5RSTCR_XSPI2RSTC RCC_AHB5RSTCR_XSPI2RSTC_Msk /*!< XSPI2 reset */ #define RCC_AHB5RSTCR_XSPIMRSTC_Pos (13U) #define RCC_AHB5RSTCR_XSPIMRSTC_Msk (0x1UL << RCC_AHB5RSTCR_XSPIMRSTC_Pos)/*!< 0x00002000 */ #define RCC_AHB5RSTCR_XSPIMRSTC RCC_AHB5RSTCR_XSPIMRSTC_Msk /*!< XSPIM reset */ #define RCC_AHB5RSTCR_XSPI3RSTC_Pos (17U) #define RCC_AHB5RSTCR_XSPI3RSTC_Msk (0x1UL << RCC_AHB5RSTCR_XSPI3RSTC_Pos)/*!< 0x00020000 */ #define RCC_AHB5RSTCR_XSPI3RSTC RCC_AHB5RSTCR_XSPI3RSTC_Msk /*!< XSPI3 reset */ #define RCC_AHB5RSTCR_GFXMMURSTC_Pos (19U) #define RCC_AHB5RSTCR_GFXMMURSTC_Msk (0x1UL << RCC_AHB5RSTCR_GFXMMURSTC_Pos) /*!< 0x00080000 */ #define RCC_AHB5RSTCR_GFXMMURSTC RCC_AHB5RSTCR_GFXMMURSTC_Msk /*!< GFXMMU reset */ #define RCC_AHB5RSTCR_GPU2DRSTC_Pos (20U) #define RCC_AHB5RSTCR_GPU2DRSTC_Msk (0x1UL << RCC_AHB5RSTCR_GPU2DRSTC_Pos)/*!< 0x00100000 */ #define RCC_AHB5RSTCR_GPU2DRSTC RCC_AHB5RSTCR_GPU2DRSTC_Msk /*!< GPU2D reset */ #define RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Pos (23U) #define RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Msk (0x1UL << RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Pos) /*!< 0x00800000 */ #define RCC_AHB5RSTCR_OTG1PHYCTLRSTC RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Msk /*!< OTG1PHYCTL reset */ #define RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Pos (24U) #define RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Msk (0x1UL << RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Pos) /*!< 0x01000000 */ #define RCC_AHB5RSTCR_OTG2PHYCTLRSTC RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Msk /*!< OTG2PHYCTL reset */ #define RCC_AHB5RSTCR_ETH1RSTC_Pos (25U) #define RCC_AHB5RSTCR_ETH1RSTC_Msk (0x1UL << RCC_AHB5RSTCR_ETH1RSTC_Pos) /*!< 0x02000000 */ #define RCC_AHB5RSTCR_ETH1RSTC RCC_AHB5RSTCR_ETH1RSTC_Msk /*!< ETH1 reset */ #define RCC_AHB5RSTCR_OTG1RSTC_Pos (26U) #define RCC_AHB5RSTCR_OTG1RSTC_Msk (0x1UL << RCC_AHB5RSTCR_OTG1RSTC_Pos) /*!< 0x04000000 */ #define RCC_AHB5RSTCR_OTG1RSTC RCC_AHB5RSTCR_OTG1RSTC_Msk /*!< OTG1 reset */ #define RCC_AHB5RSTCR_OTGPHY1RSTC_Pos (27U) #define RCC_AHB5RSTCR_OTGPHY1RSTC_Msk (0x1UL << RCC_AHB5RSTCR_OTGPHY1RSTC_Pos) /*!< 0x08000000 */ #define RCC_AHB5RSTCR_OTGPHY1RSTC RCC_AHB5RSTCR_OTGPHY1RSTC_Msk /*!< OTGPHY1 reset */ #define RCC_AHB5RSTCR_OTGPHY2RSTC_Pos (28U) #define RCC_AHB5RSTCR_OTGPHY2RSTC_Msk (0x1UL << RCC_AHB5RSTCR_OTGPHY2RSTC_Pos) /*!< 0x10000000 */ #define RCC_AHB5RSTCR_OTGPHY2RSTC RCC_AHB5RSTCR_OTGPHY2RSTC_Msk /*!< OTGPHY2 reset */ #define RCC_AHB5RSTCR_OTG2RSTC_Pos (29U) #define RCC_AHB5RSTCR_OTG2RSTC_Msk (0x1UL << RCC_AHB5RSTCR_OTG2RSTC_Pos) /*!< 0x20000000 */ #define RCC_AHB5RSTCR_OTG2RSTC RCC_AHB5RSTCR_OTG2RSTC_Msk /*!< OTG2 reset */ #define RCC_AHB5RSTCR_CACHEAXIRSTC_Pos (30U) #define RCC_AHB5RSTCR_CACHEAXIRSTC_Msk (0x1UL << RCC_AHB5RSTCR_CACHEAXIRSTC_Pos) /*!< 0x40000000 */ #define RCC_AHB5RSTCR_CACHEAXIRSTC RCC_AHB5RSTCR_CACHEAXIRSTC_Msk /*!< CACHEAXI reset */ #define RCC_AHB5RSTCR_NPURSTC_Pos (31U) #define RCC_AHB5RSTCR_NPURSTC_Msk (0x1UL << RCC_AHB5RSTCR_NPURSTC_Pos) /*!< 0x80000000 */ #define RCC_AHB5RSTCR_NPURSTC RCC_AHB5RSTCR_NPURSTC_Msk /*!< NPU reset */ /**************** Bit definition for RCC_APB1RSTCR1 register ****************/ #define RCC_APB1RSTCR1_TIM2RSTC_Pos (0U) #define RCC_APB1RSTCR1_TIM2RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM2RSTC_Pos)/*!< 0x00000001 */ #define RCC_APB1RSTCR1_TIM2RSTC RCC_APB1RSTCR1_TIM2RSTC_Msk /*!< TIM2 reset */ #define RCC_APB1RSTCR1_TIM3RSTC_Pos (1U) #define RCC_APB1RSTCR1_TIM3RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM3RSTC_Pos)/*!< 0x00000002 */ #define RCC_APB1RSTCR1_TIM3RSTC RCC_APB1RSTCR1_TIM3RSTC_Msk /*!< TIM3 reset */ #define RCC_APB1RSTCR1_TIM4RSTC_Pos (2U) #define RCC_APB1RSTCR1_TIM4RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM4RSTC_Pos)/*!< 0x00000004 */ #define RCC_APB1RSTCR1_TIM4RSTC RCC_APB1RSTCR1_TIM4RSTC_Msk /*!< TIM4 reset */ #define RCC_APB1RSTCR1_TIM5RSTC_Pos (3U) #define RCC_APB1RSTCR1_TIM5RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM5RSTC_Pos)/*!< 0x00000008 */ #define RCC_APB1RSTCR1_TIM5RSTC RCC_APB1RSTCR1_TIM5RSTC_Msk /*!< TIM5 reset */ #define RCC_APB1RSTCR1_TIM6RSTC_Pos (4U) #define RCC_APB1RSTCR1_TIM6RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM6RSTC_Pos)/*!< 0x00000010 */ #define RCC_APB1RSTCR1_TIM6RSTC RCC_APB1RSTCR1_TIM6RSTC_Msk /*!< TIM6 reset */ #define RCC_APB1RSTCR1_TIM7RSTC_Pos (5U) #define RCC_APB1RSTCR1_TIM7RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM7RSTC_Pos)/*!< 0x00000020 */ #define RCC_APB1RSTCR1_TIM7RSTC RCC_APB1RSTCR1_TIM7RSTC_Msk /*!< TIM7 reset */ #define RCC_APB1RSTCR1_TIM12RSTC_Pos (6U) #define RCC_APB1RSTCR1_TIM12RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM12RSTC_Pos) /*!< 0x00000040 */ #define RCC_APB1RSTCR1_TIM12RSTC RCC_APB1RSTCR1_TIM12RSTC_Msk /*!< TIM12 reset */ #define RCC_APB1RSTCR1_TIM13RSTC_Pos (7U) #define RCC_APB1RSTCR1_TIM13RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM13RSTC_Pos) /*!< 0x00000080 */ #define RCC_APB1RSTCR1_TIM13RSTC RCC_APB1RSTCR1_TIM13RSTC_Msk /*!< TIM13 reset */ #define RCC_APB1RSTCR1_TIM14RSTC_Pos (8U) #define RCC_APB1RSTCR1_TIM14RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM14RSTC_Pos) /*!< 0x00000100 */ #define RCC_APB1RSTCR1_TIM14RSTC RCC_APB1RSTCR1_TIM14RSTC_Msk /*!< TIM14 reset */ #define RCC_APB1RSTCR1_LPTIM1RSTC_Pos (9U) #define RCC_APB1RSTCR1_LPTIM1RSTC_Msk (0x1UL << RCC_APB1RSTCR1_LPTIM1RSTC_Pos) /*!< 0x00000200 */ #define RCC_APB1RSTCR1_LPTIM1RSTC RCC_APB1RSTCR1_LPTIM1RSTC_Msk /*!< LPTIM1 reset */ #define RCC_APB1RSTCR1_WWDGRSTC_Pos (11U) #define RCC_APB1RSTCR1_WWDGRSTC_Msk (0x1UL << RCC_APB1RSTCR1_WWDGRSTC_Pos)/*!< 0x00000800 */ #define RCC_APB1RSTCR1_WWDGRSTC RCC_APB1RSTCR1_WWDGRSTC_Msk /*!< WWDG reset */ #define RCC_APB1RSTCR1_TIM10RSTC_Pos (12U) #define RCC_APB1RSTCR1_TIM10RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM10RSTC_Pos) /*!< 0x00001000 */ #define RCC_APB1RSTCR1_TIM10RSTC RCC_APB1RSTCR1_TIM10RSTC_Msk /*!< TIM10 reset */ #define RCC_APB1RSTCR1_TIM11RSTC_Pos (13U) #define RCC_APB1RSTCR1_TIM11RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM11RSTC_Pos) /*!< 0x00002000 */ #define RCC_APB1RSTCR1_TIM11RSTC RCC_APB1RSTCR1_TIM11RSTC_Msk /*!< TIM11 reset */ #define RCC_APB1RSTCR1_SPI2RSTC_Pos (14U) #define RCC_APB1RSTCR1_SPI2RSTC_Msk (0x1UL << RCC_APB1RSTCR1_SPI2RSTC_Pos)/*!< 0x00004000 */ #define RCC_APB1RSTCR1_SPI2RSTC RCC_APB1RSTCR1_SPI2RSTC_Msk /*!< SPI2 reset */ #define RCC_APB1RSTCR1_SPI3RSTC_Pos (15U) #define RCC_APB1RSTCR1_SPI3RSTC_Msk (0x1UL << RCC_APB1RSTCR1_SPI3RSTC_Pos)/*!< 0x00008000 */ #define RCC_APB1RSTCR1_SPI3RSTC RCC_APB1RSTCR1_SPI3RSTC_Msk /*!< SPI3 reset */ #define RCC_APB1RSTCR1_SPDIFRX1RSTC_Pos (16U) #define RCC_APB1RSTCR1_SPDIFRX1RSTC_Msk (0x1UL << RCC_APB1RSTCR1_SPDIFRX1RSTC_Pos) /*!< 0x00010000 */ #define RCC_APB1RSTCR1_SPDIFRX1RSTC RCC_APB1RSTCR1_SPDIFRX1RSTC_Msk /*!< SPDIFRX1 reset */ #define RCC_APB1RSTCR1_USART2RSTC_Pos (17U) #define RCC_APB1RSTCR1_USART2RSTC_Msk (0x1UL << RCC_APB1RSTCR1_USART2RSTC_Pos) /*!< 0x00020000 */ #define RCC_APB1RSTCR1_USART2RSTC RCC_APB1RSTCR1_USART2RSTC_Msk /*!< USART2 reset */ #define RCC_APB1RSTCR1_USART3RSTC_Pos (18U) #define RCC_APB1RSTCR1_USART3RSTC_Msk (0x1UL << RCC_APB1RSTCR1_USART3RSTC_Pos) /*!< 0x00040000 */ #define RCC_APB1RSTCR1_USART3RSTC RCC_APB1RSTCR1_USART3RSTC_Msk /*!< USART3 reset */ #define RCC_APB1RSTCR1_UART4RSTC_Pos (19U) #define RCC_APB1RSTCR1_UART4RSTC_Msk (0x1UL << RCC_APB1RSTCR1_UART4RSTC_Pos) /*!< 0x00080000 */ #define RCC_APB1RSTCR1_UART4RSTC RCC_APB1RSTCR1_UART4RSTC_Msk /*!< UART4 reset */ #define RCC_APB1RSTCR1_UART5RSTC_Pos (20U) #define RCC_APB1RSTCR1_UART5RSTC_Msk (0x1UL << RCC_APB1RSTCR1_UART5RSTC_Pos) /*!< 0x00100000 */ #define RCC_APB1RSTCR1_UART5RSTC RCC_APB1RSTCR1_UART5RSTC_Msk /*!< UART5 reset */ #define RCC_APB1RSTCR1_I2C1RSTC_Pos (21U) #define RCC_APB1RSTCR1_I2C1RSTC_Msk (0x1UL << RCC_APB1RSTCR1_I2C1RSTC_Pos)/*!< 0x00200000 */ #define RCC_APB1RSTCR1_I2C1RSTC RCC_APB1RSTCR1_I2C1RSTC_Msk /*!< I2C1 reset */ #define RCC_APB1RSTCR1_I2C2RSTC_Pos (22U) #define RCC_APB1RSTCR1_I2C2RSTC_Msk (0x1UL << RCC_APB1RSTCR1_I2C2RSTC_Pos)/*!< 0x00400000 */ #define RCC_APB1RSTCR1_I2C2RSTC RCC_APB1RSTCR1_I2C2RSTC_Msk /*!< I2C2 reset */ #define RCC_APB1RSTCR1_I2C3RSTC_Pos (23U) #define RCC_APB1RSTCR1_I2C3RSTC_Msk (0x1UL << RCC_APB1RSTCR1_I2C3RSTC_Pos)/*!< 0x00800000 */ #define RCC_APB1RSTCR1_I2C3RSTC RCC_APB1RSTCR1_I2C3RSTC_Msk /*!< I2C3 reset */ #define RCC_APB1RSTCR1_I3C1RSTC_Pos (24U) #define RCC_APB1RSTCR1_I3C1RSTC_Msk (0x1UL << RCC_APB1RSTCR1_I3C1RSTC_Pos)/*!< 0x01000000 */ #define RCC_APB1RSTCR1_I3C1RSTC RCC_APB1RSTCR1_I3C1RSTC_Msk /*!< I3C1 reset */ #define RCC_APB1RSTCR1_I3C2RSTC_Pos (25U) #define RCC_APB1RSTCR1_I3C2RSTC_Msk (0x1UL << RCC_APB1RSTCR1_I3C2RSTC_Pos)/*!< 0x02000000 */ #define RCC_APB1RSTCR1_I3C2RSTC RCC_APB1RSTCR1_I3C2RSTC_Msk /*!< I3C2 reset */ #define RCC_APB1RSTCR1_UART7RSTC_Pos (30U) #define RCC_APB1RSTCR1_UART7RSTC_Msk (0x1UL << RCC_APB1RSTCR1_UART7RSTC_Pos) /*!< 0x40000000 */ #define RCC_APB1RSTCR1_UART7RSTC RCC_APB1RSTCR1_UART7RSTC_Msk /*!< UART7 reset */ #define RCC_APB1RSTCR1_UART8RSTC_Pos (31U) #define RCC_APB1RSTCR1_UART8RSTC_Msk (0x1UL << RCC_APB1RSTCR1_UART8RSTC_Pos) /*!< 0x80000000 */ #define RCC_APB1RSTCR1_UART8RSTC RCC_APB1RSTCR1_UART8RSTC_Msk /*!< UART8 reset */ /**************** Bit definition for RCC_APB1RSTCR2 register ****************/ #define RCC_APB1RSTCR2_MDIOSRSTC_Pos (5U) #define RCC_APB1RSTCR2_MDIOSRSTC_Msk (0x1UL << RCC_APB1RSTCR2_MDIOSRSTC_Pos) /*!< 0x00000020 */ #define RCC_APB1RSTCR2_MDIOSRSTC RCC_APB1RSTCR2_MDIOSRSTC_Msk /*!< MDIOS reset */ #define RCC_APB1RSTCR2_FDCANRSTC_Pos (8U) #define RCC_APB1RSTCR2_FDCANRSTC_Msk (0x1UL << RCC_APB1RSTCR2_FDCANRSTC_Pos) /*!< 0x00000100 */ #define RCC_APB1RSTCR2_FDCANRSTC RCC_APB1RSTCR2_FDCANRSTC_Msk /*!< FDCAN reset */ #define RCC_APB1RSTCR2_UCPD1RSTC_Pos (18U) #define RCC_APB1RSTCR2_UCPD1RSTC_Msk (0x1UL << RCC_APB1RSTCR2_UCPD1RSTC_Pos) /*!< 0x00040000 */ #define RCC_APB1RSTCR2_UCPD1RSTC RCC_APB1RSTCR2_UCPD1RSTC_Msk /*!< UCPD1 reset */ /**************** Bit definition for RCC_APB2RSTCR register *****************/ #define RCC_APB2RSTCR_TIM1RSTC_Pos (0U) #define RCC_APB2RSTCR_TIM1RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM1RSTC_Pos) /*!< 0x00000001 */ #define RCC_APB2RSTCR_TIM1RSTC RCC_APB2RSTCR_TIM1RSTC_Msk /*!< TIM1 reset */ #define RCC_APB2RSTCR_TIM8RSTC_Pos (1U) #define RCC_APB2RSTCR_TIM8RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM8RSTC_Pos) /*!< 0x00000002 */ #define RCC_APB2RSTCR_TIM8RSTC RCC_APB2RSTCR_TIM8RSTC_Msk /*!< TIM8 reset */ #define RCC_APB2RSTCR_USART1RSTC_Pos (4U) #define RCC_APB2RSTCR_USART1RSTC_Msk (0x1UL << RCC_APB2RSTCR_USART1RSTC_Pos) /*!< 0x00000010 */ #define RCC_APB2RSTCR_USART1RSTC RCC_APB2RSTCR_USART1RSTC_Msk /*!< USART1 reset */ #define RCC_APB2RSTCR_USART6RSTC_Pos (5U) #define RCC_APB2RSTCR_USART6RSTC_Msk (0x1UL << RCC_APB2RSTCR_USART6RSTC_Pos) /*!< 0x00000020 */ #define RCC_APB2RSTCR_USART6RSTC RCC_APB2RSTCR_USART6RSTC_Msk /*!< USART6 reset */ #define RCC_APB2RSTCR_UART9RSTC_Pos (6U) #define RCC_APB2RSTCR_UART9RSTC_Msk (0x1UL << RCC_APB2RSTCR_UART9RSTC_Pos)/*!< 0x00000040 */ #define RCC_APB2RSTCR_UART9RSTC RCC_APB2RSTCR_UART9RSTC_Msk /*!< UART9 reset */ #define RCC_APB2RSTCR_USART10RSTC_Pos (7U) #define RCC_APB2RSTCR_USART10RSTC_Msk (0x1UL << RCC_APB2RSTCR_USART10RSTC_Pos) /*!< 0x00000080 */ #define RCC_APB2RSTCR_USART10RSTC RCC_APB2RSTCR_USART10RSTC_Msk /*!< USART10 reset */ #define RCC_APB2RSTCR_SPI1RSTC_Pos (12U) #define RCC_APB2RSTCR_SPI1RSTC_Msk (0x1UL << RCC_APB2RSTCR_SPI1RSTC_Pos) /*!< 0x00001000 */ #define RCC_APB2RSTCR_SPI1RSTC RCC_APB2RSTCR_SPI1RSTC_Msk /*!< SPI1 reset */ #define RCC_APB2RSTCR_SPI4RSTC_Pos (13U) #define RCC_APB2RSTCR_SPI4RSTC_Msk (0x1UL << RCC_APB2RSTCR_SPI4RSTC_Pos) /*!< 0x00002000 */ #define RCC_APB2RSTCR_SPI4RSTC RCC_APB2RSTCR_SPI4RSTC_Msk /*!< SPI4 reset */ #define RCC_APB2RSTCR_TIM18RSTC_Pos (15U) #define RCC_APB2RSTCR_TIM18RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM18RSTC_Pos)/*!< 0x00008000 */ #define RCC_APB2RSTCR_TIM18RSTC RCC_APB2RSTCR_TIM18RSTC_Msk /*!< TIM18 reset */ #define RCC_APB2RSTCR_TIM15RSTC_Pos (16U) #define RCC_APB2RSTCR_TIM15RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM15RSTC_Pos)/*!< 0x00010000 */ #define RCC_APB2RSTCR_TIM15RSTC RCC_APB2RSTCR_TIM15RSTC_Msk /*!< TIM15 reset */ #define RCC_APB2RSTCR_TIM16RSTC_Pos (17U) #define RCC_APB2RSTCR_TIM16RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM16RSTC_Pos)/*!< 0x00020000 */ #define RCC_APB2RSTCR_TIM16RSTC RCC_APB2RSTCR_TIM16RSTC_Msk /*!< TIM16 reset */ #define RCC_APB2RSTCR_TIM17RSTC_Pos (18U) #define RCC_APB2RSTCR_TIM17RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM17RSTC_Pos)/*!< 0x00040000 */ #define RCC_APB2RSTCR_TIM17RSTC RCC_APB2RSTCR_TIM17RSTC_Msk /*!< TIM17 reset */ #define RCC_APB2RSTCR_TIM9RSTC_Pos (19U) #define RCC_APB2RSTCR_TIM9RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM9RSTC_Pos) /*!< 0x00080000 */ #define RCC_APB2RSTCR_TIM9RSTC RCC_APB2RSTCR_TIM9RSTC_Msk /*!< TIM9 reset */ #define RCC_APB2RSTCR_SPI5RSTC_Pos (20U) #define RCC_APB2RSTCR_SPI5RSTC_Msk (0x1UL << RCC_APB2RSTCR_SPI5RSTC_Pos) /*!< 0x00100000 */ #define RCC_APB2RSTCR_SPI5RSTC RCC_APB2RSTCR_SPI5RSTC_Msk /*!< SPI5 reset */ #define RCC_APB2RSTCR_SAI1RSTC_Pos (21U) #define RCC_APB2RSTCR_SAI1RSTC_Msk (0x1UL << RCC_APB2RSTCR_SAI1RSTC_Pos) /*!< 0x00200000 */ #define RCC_APB2RSTCR_SAI1RSTC RCC_APB2RSTCR_SAI1RSTC_Msk /*!< SAI1 reset */ #define RCC_APB2RSTCR_SAI2RSTC_Pos (22U) #define RCC_APB2RSTCR_SAI2RSTC_Msk (0x1UL << RCC_APB2RSTCR_SAI2RSTC_Pos) /*!< 0x00400000 */ #define RCC_APB2RSTCR_SAI2RSTC RCC_APB2RSTCR_SAI2RSTC_Msk /*!< SAI2 reset */ /**************** Bit definition for RCC_APB4RSTCR1 register ****************/ #define RCC_APB4RSTCR1_HDPRSTC_Pos (2U) #define RCC_APB4RSTCR1_HDPRSTC_Msk (0x1UL << RCC_APB4RSTCR1_HDPRSTC_Pos) /*!< 0x00000004 */ #define RCC_APB4RSTCR1_HDPRSTC RCC_APB4RSTCR1_HDPRSTC_Msk /*!< HDP reset */ #define RCC_APB4RSTCR1_LPUART1RSTC_Pos (3U) #define RCC_APB4RSTCR1_LPUART1RSTC_Msk (0x1UL << RCC_APB4RSTCR1_LPUART1RSTC_Pos) /*!< 0x00000008 */ #define RCC_APB4RSTCR1_LPUART1RSTC RCC_APB4RSTCR1_LPUART1RSTC_Msk /*!< LPUART1 reset */ #define RCC_APB4RSTCR1_SPI6RSTC_Pos (5U) #define RCC_APB4RSTCR1_SPI6RSTC_Msk (0x1UL << RCC_APB4RSTCR1_SPI6RSTC_Pos)/*!< 0x00000020 */ #define RCC_APB4RSTCR1_SPI6RSTC RCC_APB4RSTCR1_SPI6RSTC_Msk /*!< SPI6 reset */ #define RCC_APB4RSTCR1_I2C4RSTC_Pos (7U) #define RCC_APB4RSTCR1_I2C4RSTC_Msk (0x1UL << RCC_APB4RSTCR1_I2C4RSTC_Pos)/*!< 0x00000080 */ #define RCC_APB4RSTCR1_I2C4RSTC RCC_APB4RSTCR1_I2C4RSTC_Msk /*!< I2C4 reset */ #define RCC_APB4RSTCR1_LPTIM2RSTC_Pos (9U) #define RCC_APB4RSTCR1_LPTIM2RSTC_Msk (0x1UL << RCC_APB4RSTCR1_LPTIM2RSTC_Pos) /*!< 0x00000200 */ #define RCC_APB4RSTCR1_LPTIM2RSTC RCC_APB4RSTCR1_LPTIM2RSTC_Msk /*!< LPTIM2 reset */ #define RCC_APB4RSTCR1_LPTIM3RSTC_Pos (10U) #define RCC_APB4RSTCR1_LPTIM3RSTC_Msk (0x1UL << RCC_APB4RSTCR1_LPTIM3RSTC_Pos) /*!< 0x00000400 */ #define RCC_APB4RSTCR1_LPTIM3RSTC RCC_APB4RSTCR1_LPTIM3RSTC_Msk /*!< LPTIM3 reset */ #define RCC_APB4RSTCR1_LPTIM4RSTC_Pos (11U) #define RCC_APB4RSTCR1_LPTIM4RSTC_Msk (0x1UL << RCC_APB4RSTCR1_LPTIM4RSTC_Pos) /*!< 0x00000800 */ #define RCC_APB4RSTCR1_LPTIM4RSTC RCC_APB4RSTCR1_LPTIM4RSTC_Msk /*!< LPTIM4 reset */ #define RCC_APB4RSTCR1_LPTIM5RSTC_Pos (12U) #define RCC_APB4RSTCR1_LPTIM5RSTC_Msk (0x1UL << RCC_APB4RSTCR1_LPTIM5RSTC_Pos) /*!< 0x00001000 */ #define RCC_APB4RSTCR1_LPTIM5RSTC RCC_APB4RSTCR1_LPTIM5RSTC_Msk /*!< LPTIM5 reset */ #define RCC_APB4RSTCR1_VREFBUFRSTC_Pos (15U) #define RCC_APB4RSTCR1_VREFBUFRSTC_Msk (0x1UL << RCC_APB4RSTCR1_VREFBUFRSTC_Pos) /*!< 0x00008000 */ #define RCC_APB4RSTCR1_VREFBUFRSTC RCC_APB4RSTCR1_VREFBUFRSTC_Msk /*!< VREFBUF reset */ #define RCC_APB4RSTCR1_RTCRSTC_Pos (16U) #define RCC_APB4RSTCR1_RTCRSTC_Msk (0x1UL << RCC_APB4RSTCR1_RTCRSTC_Pos) /*!< 0x00010000 */ #define RCC_APB4RSTCR1_RTCRSTC RCC_APB4RSTCR1_RTCRSTC_Msk /*!< RTC reset */ /**************** Bit definition for RCC_APB4RSTCR2 register ****************/ #define RCC_APB4RSTCR2_SYSCFGRSTC_Pos (0U) #define RCC_APB4RSTCR2_SYSCFGRSTC_Msk (0x1UL << RCC_APB4RSTCR2_SYSCFGRSTC_Pos) /*!< 0x00000001 */ #define RCC_APB4RSTCR2_SYSCFGRSTC RCC_APB4RSTCR2_SYSCFGRSTC_Msk /*!< SYSCFG reset */ #define RCC_APB4RSTCR2_DTSRSTC_Pos (2U) #define RCC_APB4RSTCR2_DTSRSTC_Msk (0x1UL << RCC_APB4RSTCR2_DTSRSTC_Pos) /*!< 0x00000004 */ #define RCC_APB4RSTCR2_DTSRSTC RCC_APB4RSTCR2_DTSRSTC_Msk /*!< DTS reset */ /**************** Bit definition for RCC_APB5RSTCR register *****************/ #define RCC_APB5RSTCR_LTDCRSTC_Pos (1U) #define RCC_APB5RSTCR_LTDCRSTC_Msk (0x1UL << RCC_APB5RSTCR_LTDCRSTC_Pos) /*!< 0x00000002 */ #define RCC_APB5RSTCR_LTDCRSTC RCC_APB5RSTCR_LTDCRSTC_Msk /*!< LTDC reset */ #define RCC_APB5RSTCR_DCMIPPRSTC_Pos (2U) #define RCC_APB5RSTCR_DCMIPPRSTC_Msk (0x1UL << RCC_APB5RSTCR_DCMIPPRSTC_Pos) /*!< 0x00000004 */ #define RCC_APB5RSTCR_DCMIPPRSTC RCC_APB5RSTCR_DCMIPPRSTC_Msk /*!< DCMIPP reset */ #define RCC_APB5RSTCR_GFXTIMRSTC_Pos (4U) #define RCC_APB5RSTCR_GFXTIMRSTC_Msk (0x1UL << RCC_APB5RSTCR_GFXTIMRSTC_Pos) /*!< 0x00000010 */ #define RCC_APB5RSTCR_GFXTIMRSTC RCC_APB5RSTCR_GFXTIMRSTC_Msk /*!< GFXTIM reset */ #define RCC_APB5RSTCR_VENCRSTC_Pos (5U) #define RCC_APB5RSTCR_VENCRSTC_Msk (0x1UL << RCC_APB5RSTCR_VENCRSTC_Pos) /*!< 0x00000020 */ #define RCC_APB5RSTCR_VENCRSTC RCC_APB5RSTCR_VENCRSTC_Msk /*!< VENC reset */ #define RCC_APB5RSTCR_CSIRSTC_Pos (6U) #define RCC_APB5RSTCR_CSIRSTC_Msk (0x1UL << RCC_APB5RSTCR_CSIRSTC_Pos) /*!< 0x00000040 */ #define RCC_APB5RSTCR_CSIRSTC RCC_APB5RSTCR_CSIRSTC_Msk /*!< CSI reset */ /***************** Bit definition for RCC_DIVENCR register ******************/ #define RCC_DIVENCR_IC1ENC_Pos (0U) #define RCC_DIVENCR_IC1ENC_Msk (0x1UL << RCC_DIVENCR_IC1ENC_Pos) /*!< 0x00000001 */ #define RCC_DIVENCR_IC1ENC RCC_DIVENCR_IC1ENC_Msk /*!< IC1 enable */ #define RCC_DIVENCR_IC2ENC_Pos (1U) #define RCC_DIVENCR_IC2ENC_Msk (0x1UL << RCC_DIVENCR_IC2ENC_Pos) /*!< 0x00000002 */ #define RCC_DIVENCR_IC2ENC RCC_DIVENCR_IC2ENC_Msk /*!< IC2 enable */ #define RCC_DIVENCR_IC3ENC_Pos (2U) #define RCC_DIVENCR_IC3ENC_Msk (0x1UL << RCC_DIVENCR_IC3ENC_Pos) /*!< 0x00000004 */ #define RCC_DIVENCR_IC3ENC RCC_DIVENCR_IC3ENC_Msk /*!< IC3 enable */ #define RCC_DIVENCR_IC4ENC_Pos (3U) #define RCC_DIVENCR_IC4ENC_Msk (0x1UL << RCC_DIVENCR_IC4ENC_Pos) /*!< 0x00000008 */ #define RCC_DIVENCR_IC4ENC RCC_DIVENCR_IC4ENC_Msk /*!< IC4 enable */ #define RCC_DIVENCR_IC5ENC_Pos (4U) #define RCC_DIVENCR_IC5ENC_Msk (0x1UL << RCC_DIVENCR_IC5ENC_Pos) /*!< 0x00000010 */ #define RCC_DIVENCR_IC5ENC RCC_DIVENCR_IC5ENC_Msk /*!< IC5 enable */ #define RCC_DIVENCR_IC6ENC_Pos (5U) #define RCC_DIVENCR_IC6ENC_Msk (0x1UL << RCC_DIVENCR_IC6ENC_Pos) /*!< 0x00000020 */ #define RCC_DIVENCR_IC6ENC RCC_DIVENCR_IC6ENC_Msk /*!< IC6 enable */ #define RCC_DIVENCR_IC7ENC_Pos (6U) #define RCC_DIVENCR_IC7ENC_Msk (0x1UL << RCC_DIVENCR_IC7ENC_Pos) /*!< 0x00000040 */ #define RCC_DIVENCR_IC7ENC RCC_DIVENCR_IC7ENC_Msk /*!< IC7 enable */ #define RCC_DIVENCR_IC8ENC_Pos (7U) #define RCC_DIVENCR_IC8ENC_Msk (0x1UL << RCC_DIVENCR_IC8ENC_Pos) /*!< 0x00000080 */ #define RCC_DIVENCR_IC8ENC RCC_DIVENCR_IC8ENC_Msk /*!< IC8 enable */ #define RCC_DIVENCR_IC9ENC_Pos (8U) #define RCC_DIVENCR_IC9ENC_Msk (0x1UL << RCC_DIVENCR_IC9ENC_Pos) /*!< 0x00000100 */ #define RCC_DIVENCR_IC9ENC RCC_DIVENCR_IC9ENC_Msk /*!< IC9 enable */ #define RCC_DIVENCR_IC10ENC_Pos (9U) #define RCC_DIVENCR_IC10ENC_Msk (0x1UL << RCC_DIVENCR_IC10ENC_Pos) /*!< 0x00000200 */ #define RCC_DIVENCR_IC10ENC RCC_DIVENCR_IC10ENC_Msk /*!< IC10 enable */ #define RCC_DIVENCR_IC11ENC_Pos (10U) #define RCC_DIVENCR_IC11ENC_Msk (0x1UL << RCC_DIVENCR_IC11ENC_Pos) /*!< 0x00000400 */ #define RCC_DIVENCR_IC11ENC RCC_DIVENCR_IC11ENC_Msk /*!< IC11 enable */ #define RCC_DIVENCR_IC12ENC_Pos (11U) #define RCC_DIVENCR_IC12ENC_Msk (0x1UL << RCC_DIVENCR_IC12ENC_Pos) /*!< 0x00000800 */ #define RCC_DIVENCR_IC12ENC RCC_DIVENCR_IC12ENC_Msk /*!< IC12 enable */ #define RCC_DIVENCR_IC13ENC_Pos (12U) #define RCC_DIVENCR_IC13ENC_Msk (0x1UL << RCC_DIVENCR_IC13ENC_Pos) /*!< 0x00001000 */ #define RCC_DIVENCR_IC13ENC RCC_DIVENCR_IC13ENC_Msk /*!< IC13 enable */ #define RCC_DIVENCR_IC14ENC_Pos (13U) #define RCC_DIVENCR_IC14ENC_Msk (0x1UL << RCC_DIVENCR_IC14ENC_Pos) /*!< 0x00002000 */ #define RCC_DIVENCR_IC14ENC RCC_DIVENCR_IC14ENC_Msk /*!< IC14 enable */ #define RCC_DIVENCR_IC15ENC_Pos (14U) #define RCC_DIVENCR_IC15ENC_Msk (0x1UL << RCC_DIVENCR_IC15ENC_Pos) /*!< 0x00004000 */ #define RCC_DIVENCR_IC15ENC RCC_DIVENCR_IC15ENC_Msk /*!< IC15 enable */ #define RCC_DIVENCR_IC16ENC_Pos (15U) #define RCC_DIVENCR_IC16ENC_Msk (0x1UL << RCC_DIVENCR_IC16ENC_Pos) /*!< 0x00008000 */ #define RCC_DIVENCR_IC16ENC RCC_DIVENCR_IC16ENC_Msk /*!< IC16 enable */ #define RCC_DIVENCR_IC17ENC_Pos (16U) #define RCC_DIVENCR_IC17ENC_Msk (0x1UL << RCC_DIVENCR_IC17ENC_Pos) /*!< 0x00010000 */ #define RCC_DIVENCR_IC17ENC RCC_DIVENCR_IC17ENC_Msk /*!< IC17 enable */ #define RCC_DIVENCR_IC18ENC_Pos (17U) #define RCC_DIVENCR_IC18ENC_Msk (0x1UL << RCC_DIVENCR_IC18ENC_Pos) /*!< 0x00020000 */ #define RCC_DIVENCR_IC18ENC RCC_DIVENCR_IC18ENC_Msk /*!< IC18 enable */ #define RCC_DIVENCR_IC19ENC_Pos (18U) #define RCC_DIVENCR_IC19ENC_Msk (0x1UL << RCC_DIVENCR_IC19ENC_Pos) /*!< 0x00040000 */ #define RCC_DIVENCR_IC19ENC RCC_DIVENCR_IC19ENC_Msk /*!< IC19 enable */ #define RCC_DIVENCR_IC20ENC_Pos (19U) #define RCC_DIVENCR_IC20ENC_Msk (0x1UL << RCC_DIVENCR_IC20ENC_Pos) /*!< 0x00080000 */ #define RCC_DIVENCR_IC20ENC RCC_DIVENCR_IC20ENC_Msk /*!< IC20 enable */ /***************** Bit definition for RCC_BUSENCR register ******************/ #define RCC_BUSENCR_ACLKNENC_Pos (0U) #define RCC_BUSENCR_ACLKNENC_Msk (0x1UL << RCC_BUSENCR_ACLKNENC_Pos) /*!< 0x00000001 */ #define RCC_BUSENCR_ACLKNENC RCC_BUSENCR_ACLKNENC_Msk /*!< ACLKN enable */ #define RCC_BUSENCR_ACLKNCENC_Pos (1U) #define RCC_BUSENCR_ACLKNCENC_Msk (0x1UL << RCC_BUSENCR_ACLKNCENC_Pos) /*!< 0x00000002 */ #define RCC_BUSENCR_ACLKNCENC RCC_BUSENCR_ACLKNCENC_Msk /*!< ACLKNC enable */ #define RCC_BUSENCR_AHBMENC_Pos (2U) #define RCC_BUSENCR_AHBMENC_Msk (0x1UL << RCC_BUSENCR_AHBMENC_Pos) /*!< 0x00000004 */ #define RCC_BUSENCR_AHBMENC RCC_BUSENCR_AHBMENC_Msk /*!< AHBM enable */ #define RCC_BUSENCR_AHB1ENC_Pos (3U) #define RCC_BUSENCR_AHB1ENC_Msk (0x1UL << RCC_BUSENCR_AHB1ENC_Pos) /*!< 0x00000008 */ #define RCC_BUSENCR_AHB1ENC RCC_BUSENCR_AHB1ENC_Msk /*!< AHB1 enable */ #define RCC_BUSENCR_AHB2ENC_Pos (4U) #define RCC_BUSENCR_AHB2ENC_Msk (0x1UL << RCC_BUSENCR_AHB2ENC_Pos) /*!< 0x00000010 */ #define RCC_BUSENCR_AHB2ENC RCC_BUSENCR_AHB2ENC_Msk /*!< AHB2 enable */ #define RCC_BUSENCR_AHB3ENC_Pos (5U) #define RCC_BUSENCR_AHB3ENC_Msk (0x1UL << RCC_BUSENCR_AHB3ENC_Pos) /*!< 0x00000020 */ #define RCC_BUSENCR_AHB3ENC RCC_BUSENCR_AHB3ENC_Msk /*!< AHB3 enable */ #define RCC_BUSENCR_AHB4ENC_Pos (6U) #define RCC_BUSENCR_AHB4ENC_Msk (0x1UL << RCC_BUSENCR_AHB4ENC_Pos) /*!< 0x00000040 */ #define RCC_BUSENCR_AHB4ENC RCC_BUSENCR_AHB4ENC_Msk /*!< AHB4 enable */ #define RCC_BUSENCR_AHB5ENC_Pos (7U) #define RCC_BUSENCR_AHB5ENC_Msk (0x1UL << RCC_BUSENCR_AHB5ENC_Pos) /*!< 0x00000080 */ #define RCC_BUSENCR_AHB5ENC RCC_BUSENCR_AHB5ENC_Msk /*!< AHB5 enable */ #define RCC_BUSENCR_APB1ENC_Pos (8U) #define RCC_BUSENCR_APB1ENC_Msk (0x1UL << RCC_BUSENCR_APB1ENC_Pos) /*!< 0x00000100 */ #define RCC_BUSENCR_APB1ENC RCC_BUSENCR_APB1ENC_Msk /*!< APB1 enable */ #define RCC_BUSENCR_APB2ENC_Pos (9U) #define RCC_BUSENCR_APB2ENC_Msk (0x1UL << RCC_BUSENCR_APB2ENC_Pos) /*!< 0x00000200 */ #define RCC_BUSENCR_APB2ENC RCC_BUSENCR_APB2ENC_Msk /*!< APB2 enable */ #define RCC_BUSENCR_APB3ENC_Pos (10U) #define RCC_BUSENCR_APB3ENC_Msk (0x1UL << RCC_BUSENCR_APB3ENC_Pos) /*!< 0x00000400 */ #define RCC_BUSENCR_APB3ENC RCC_BUSENCR_APB3ENC_Msk /*!< APB3 enable */ #define RCC_BUSENCR_APB4ENC_Pos (11U) #define RCC_BUSENCR_APB4ENC_Msk (0x1UL << RCC_BUSENCR_APB4ENC_Pos) /*!< 0x00000800 */ #define RCC_BUSENCR_APB4ENC RCC_BUSENCR_APB4ENC_Msk /*!< APB4 enable */ #define RCC_BUSENCR_APB5ENC_Pos (12U) #define RCC_BUSENCR_APB5ENC_Msk (0x1UL << RCC_BUSENCR_APB5ENC_Pos) /*!< 0x00001000 */ #define RCC_BUSENCR_APB5ENC RCC_BUSENCR_APB5ENC_Msk /*!< APB5 enable */ /***************** Bit definition for RCC_MISCENCR register *****************/ #define RCC_MISCENCR_DBGENC_Pos (0U) #define RCC_MISCENCR_DBGENC_Msk (0x1UL << RCC_MISCENCR_DBGENC_Pos) /*!< 0x00000001 */ #define RCC_MISCENCR_DBGENC RCC_MISCENCR_DBGENC_Msk /*!< DBG enable */ #define RCC_MISCENCR_MCO1ENC_Pos (1U) #define RCC_MISCENCR_MCO1ENC_Msk (0x1UL << RCC_MISCENCR_MCO1ENC_Pos) /*!< 0x00000002 */ #define RCC_MISCENCR_MCO1ENC RCC_MISCENCR_MCO1ENC_Msk /*!< MCO1 enable */ #define RCC_MISCENCR_MCO2ENC_Pos (2U) #define RCC_MISCENCR_MCO2ENC_Msk (0x1UL << RCC_MISCENCR_MCO2ENC_Pos) /*!< 0x00000004 */ #define RCC_MISCENCR_MCO2ENC RCC_MISCENCR_MCO2ENC_Msk /*!< MCO2 enable */ #define RCC_MISCENCR_XSPIPHYCOMPENC_Pos (3U) #define RCC_MISCENCR_XSPIPHYCOMPENC_Msk (0x1UL << RCC_MISCENCR_XSPIPHYCOMPENC_Pos) /*!< 0x00000008 */ #define RCC_MISCENCR_XSPIPHYCOMPENC RCC_MISCENCR_XSPIPHYCOMPENC_Msk /*!< XSPIPHYCOMP enable */ #define RCC_MISCENCR_PERENC_Pos (6U) #define RCC_MISCENCR_PERENC_Msk (0x1UL << RCC_MISCENCR_PERENC_Pos) /*!< 0x00000040 */ #define RCC_MISCENCR_PERENC RCC_MISCENCR_PERENC_Msk /*!< PER enable */ /***************** Bit definition for RCC_MEMENCR register ******************/ #define RCC_MEMENCR_AXISRAM3ENC_Pos (0U) #define RCC_MEMENCR_AXISRAM3ENC_Msk (0x1UL << RCC_MEMENCR_AXISRAM3ENC_Pos)/*!< 0x00000001 */ #define RCC_MEMENCR_AXISRAM3ENC RCC_MEMENCR_AXISRAM3ENC_Msk /*!< AXISRAM3 enable */ #define RCC_MEMENCR_AXISRAM4ENC_Pos (1U) #define RCC_MEMENCR_AXISRAM4ENC_Msk (0x1UL << RCC_MEMENCR_AXISRAM4ENC_Pos)/*!< 0x00000002 */ #define RCC_MEMENCR_AXISRAM4ENC RCC_MEMENCR_AXISRAM4ENC_Msk /*!< AXISRAM4 enable */ #define RCC_MEMENCR_AXISRAM5ENC_Pos (2U) #define RCC_MEMENCR_AXISRAM5ENC_Msk (0x1UL << RCC_MEMENCR_AXISRAM5ENC_Pos)/*!< 0x00000004 */ #define RCC_MEMENCR_AXISRAM5ENC RCC_MEMENCR_AXISRAM5ENC_Msk /*!< AXISRAM5 enable */ #define RCC_MEMENCR_AXISRAM6ENC_Pos (3U) #define RCC_MEMENCR_AXISRAM6ENC_Msk (0x1UL << RCC_MEMENCR_AXISRAM6ENC_Pos)/*!< 0x00000008 */ #define RCC_MEMENCR_AXISRAM6ENC RCC_MEMENCR_AXISRAM6ENC_Msk /*!< AXISRAM6 enable */ #define RCC_MEMENCR_AHBSRAM1ENC_Pos (4U) #define RCC_MEMENCR_AHBSRAM1ENC_Msk (0x1UL << RCC_MEMENCR_AHBSRAM1ENC_Pos)/*!< 0x00000010 */ #define RCC_MEMENCR_AHBSRAM1ENC RCC_MEMENCR_AHBSRAM1ENC_Msk /*!< AHBSRAM1 enable */ #define RCC_MEMENCR_AHBSRAM2ENC_Pos (5U) #define RCC_MEMENCR_AHBSRAM2ENC_Msk (0x1UL << RCC_MEMENCR_AHBSRAM2ENC_Pos)/*!< 0x00000020 */ #define RCC_MEMENCR_AHBSRAM2ENC RCC_MEMENCR_AHBSRAM2ENC_Msk /*!< AHBSRAM2 enable */ #define RCC_MEMENCR_BKPSRAMENC_Pos (6U) #define RCC_MEMENCR_BKPSRAMENC_Msk (0x1UL << RCC_MEMENCR_BKPSRAMENC_Pos) /*!< 0x00000040 */ #define RCC_MEMENCR_BKPSRAMENC RCC_MEMENCR_BKPSRAMENC_Msk /*!< BKPSRAM enable */ #define RCC_MEMENCR_AXISRAM1ENC_Pos (7U) #define RCC_MEMENCR_AXISRAM1ENC_Msk (0x1UL << RCC_MEMENCR_AXISRAM1ENC_Pos)/*!< 0x00000080 */ #define RCC_MEMENCR_AXISRAM1ENC RCC_MEMENCR_AXISRAM1ENC_Msk /*!< AXISRAM1 enable */ #define RCC_MEMENCR_AXISRAM2ENC_Pos (8U) #define RCC_MEMENCR_AXISRAM2ENC_Msk (0x1UL << RCC_MEMENCR_AXISRAM2ENC_Pos)/*!< 0x00000100 */ #define RCC_MEMENCR_AXISRAM2ENC RCC_MEMENCR_AXISRAM2ENC_Msk /*!< AXISRAM2 enable */ #define RCC_MEMENCR_FLEXRAMENC_Pos (9U) #define RCC_MEMENCR_FLEXRAMENC_Msk (0x1UL << RCC_MEMENCR_FLEXRAMENC_Pos) /*!< 0x00000200 */ #define RCC_MEMENCR_FLEXRAMENC RCC_MEMENCR_FLEXRAMENC_Msk /*!< FLEXRAM enable */ #define RCC_MEMENCR_CACHEAXIRAMENC_Pos (10U) #define RCC_MEMENCR_CACHEAXIRAMENC_Msk (0x1UL << RCC_MEMENCR_CACHEAXIRAMENC_Pos) /*!< 0x00000400 */ #define RCC_MEMENCR_CACHEAXIRAMENC RCC_MEMENCR_CACHEAXIRAMENC_Msk /*!< CACHEAXIRAM enable */ #define RCC_MEMENCR_VENCRAMENC_Pos (11U) #define RCC_MEMENCR_VENCRAMENC_Msk (0x1UL << RCC_MEMENCR_VENCRAMENC_Pos) /*!< 0x00000800 */ #define RCC_MEMENCR_VENCRAMENC RCC_MEMENCR_VENCRAMENC_Msk /*!< VENCRAM enable */ #define RCC_MEMENCR_BOOTROMENC_Pos (12U) #define RCC_MEMENCR_BOOTROMENC_Msk (0x1UL << RCC_MEMENCR_BOOTROMENC_Pos) /*!< 0x00001000 */ #define RCC_MEMENCR_BOOTROMENC RCC_MEMENCR_BOOTROMENC_Msk /*!< Boot ROM enable */ /***************** Bit definition for RCC_AHB1ENCR register *****************/ #define RCC_AHB1ENCR_GPDMA1ENC_Pos (4U) #define RCC_AHB1ENCR_GPDMA1ENC_Msk (0x1UL << RCC_AHB1ENCR_GPDMA1ENC_Pos) /*!< 0x00000010 */ #define RCC_AHB1ENCR_GPDMA1ENC RCC_AHB1ENCR_GPDMA1ENC_Msk /*!< GPDMA1 enable */ #define RCC_AHB1ENCR_ADC12ENC_Pos (5U) #define RCC_AHB1ENCR_ADC12ENC_Msk (0x1UL << RCC_AHB1ENCR_ADC12ENC_Pos) /*!< 0x00000020 */ #define RCC_AHB1ENCR_ADC12ENC RCC_AHB1ENCR_ADC12ENC_Msk /*!< ADC12 enable */ /***************** Bit definition for RCC_AHB2ENCR register *****************/ #define RCC_AHB2ENCR_RAMCFGENC_Pos (12U) #define RCC_AHB2ENCR_RAMCFGENC_Msk (0x1UL << RCC_AHB2ENCR_RAMCFGENC_Pos) /*!< 0x00001000 */ #define RCC_AHB2ENCR_RAMCFGENC RCC_AHB2ENCR_RAMCFGENC_Msk /*!< RAMCFG enable */ #define RCC_AHB2ENCR_MDF1ENC_Pos (16U) #define RCC_AHB2ENCR_MDF1ENC_Msk (0x1UL << RCC_AHB2ENCR_MDF1ENC_Pos) /*!< 0x00010000 */ #define RCC_AHB2ENCR_MDF1ENC RCC_AHB2ENCR_MDF1ENC_Msk /*!< MDF1 enable */ #define RCC_AHB2ENCR_ADF1ENC_Pos (17U) #define RCC_AHB2ENCR_ADF1ENC_Msk (0x1UL << RCC_AHB2ENCR_ADF1ENC_Pos) /*!< 0x00020000 */ #define RCC_AHB2ENCR_ADF1ENC RCC_AHB2ENCR_ADF1ENC_Msk /*!< ADF1 enable */ /***************** Bit definition for RCC_AHB3ENCR register *****************/ #define RCC_AHB3ENCR_RNGENC_Pos (0U) #define RCC_AHB3ENCR_RNGENC_Msk (0x1UL << RCC_AHB3ENCR_RNGENC_Pos) /*!< 0x00000001 */ #define RCC_AHB3ENCR_RNGENC RCC_AHB3ENCR_RNGENC_Msk /*!< RNG enable */ #define RCC_AHB3ENCR_HASHENC_Pos (1U) #define RCC_AHB3ENCR_HASHENC_Msk (0x1UL << RCC_AHB3ENCR_HASHENC_Pos) /*!< 0x00000002 */ #define RCC_AHB3ENCR_HASHENC RCC_AHB3ENCR_HASHENC_Msk /*!< HASH enable */ #define RCC_AHB3ENCR_CRYPENC_Pos (2U) #define RCC_AHB3ENCR_CRYPENC_Msk (0x1UL << RCC_AHB3ENCR_CRYPENC_Pos) /*!< 0x00000004 */ #define RCC_AHB3ENCR_CRYPENC RCC_AHB3ENCR_CRYPENC_Msk /*!< CRYP enable */ #define RCC_AHB3ENCR_SAESENC_Pos (4U) #define RCC_AHB3ENCR_SAESENC_Msk (0x1UL << RCC_AHB3ENCR_SAESENC_Pos) /*!< 0x00000010 */ #define RCC_AHB3ENCR_SAESENC RCC_AHB3ENCR_SAESENC_Msk /*!< SAES enable */ #define RCC_AHB3ENCR_PKAENC_Pos (8U) #define RCC_AHB3ENCR_PKAENC_Msk (0x1UL << RCC_AHB3ENCR_PKAENC_Pos) /*!< 0x00000100 */ #define RCC_AHB3ENCR_PKAENC RCC_AHB3ENCR_PKAENC_Msk /*!< PKA enable */ #define RCC_AHB3ENCR_RIFSCENC_Pos (9U) #define RCC_AHB3ENCR_RIFSCENC_Msk (0x1UL << RCC_AHB3ENCR_RIFSCENC_Pos) /*!< 0x00000200 */ #define RCC_AHB3ENCR_RIFSCENC RCC_AHB3ENCR_RIFSCENC_Msk /*!< RIFSC enable */ #define RCC_AHB3ENCR_IACENC_Pos (10U) #define RCC_AHB3ENCR_IACENC_Msk (0x1UL << RCC_AHB3ENCR_IACENC_Pos) /*!< 0x00000400 */ #define RCC_AHB3ENCR_IACENC RCC_AHB3ENCR_IACENC_Msk /*!< IAC enable */ #define RCC_AHB3ENCR_RISAFENC_Pos (14U) #define RCC_AHB3ENCR_RISAFENC_Msk (0x1UL << RCC_AHB3ENCR_RISAFENC_Pos) /*!< 0x00004000 */ #define RCC_AHB3ENCR_RISAFENC RCC_AHB3ENCR_RISAFENC_Msk /*!< RISAF enable */ /***************** Bit definition for RCC_AHB4ENCR register *****************/ #define RCC_AHB4ENCR_GPIOAENC_Pos (0U) #define RCC_AHB4ENCR_GPIOAENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOAENC_Pos) /*!< 0x00000001 */ #define RCC_AHB4ENCR_GPIOAENC RCC_AHB4ENCR_GPIOAENC_Msk /*!< GPIO A enable */ #define RCC_AHB4ENCR_GPIOBENC_Pos (1U) #define RCC_AHB4ENCR_GPIOBENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOBENC_Pos) /*!< 0x00000002 */ #define RCC_AHB4ENCR_GPIOBENC RCC_AHB4ENCR_GPIOBENC_Msk /*!< GPIO B enable */ #define RCC_AHB4ENCR_GPIOCENC_Pos (2U) #define RCC_AHB4ENCR_GPIOCENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOCENC_Pos) /*!< 0x00000004 */ #define RCC_AHB4ENCR_GPIOCENC RCC_AHB4ENCR_GPIOCENC_Msk /*!< GPIO C enable */ #define RCC_AHB4ENCR_GPIODENC_Pos (3U) #define RCC_AHB4ENCR_GPIODENC_Msk (0x1UL << RCC_AHB4ENCR_GPIODENC_Pos) /*!< 0x00000008 */ #define RCC_AHB4ENCR_GPIODENC RCC_AHB4ENCR_GPIODENC_Msk /*!< GPIO D enable */ #define RCC_AHB4ENCR_GPIOEENC_Pos (4U) #define RCC_AHB4ENCR_GPIOEENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOEENC_Pos) /*!< 0x00000010 */ #define RCC_AHB4ENCR_GPIOEENC RCC_AHB4ENCR_GPIOEENC_Msk /*!< GPIO E enable */ #define RCC_AHB4ENCR_GPIOFENC_Pos (5U) #define RCC_AHB4ENCR_GPIOFENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOFENC_Pos) /*!< 0x00000020 */ #define RCC_AHB4ENCR_GPIOFENC RCC_AHB4ENCR_GPIOFENC_Msk /*!< GPIO F enable */ #define RCC_AHB4ENCR_GPIOGENC_Pos (6U) #define RCC_AHB4ENCR_GPIOGENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOGENC_Pos) /*!< 0x00000040 */ #define RCC_AHB4ENCR_GPIOGENC RCC_AHB4ENCR_GPIOGENC_Msk /*!< GPIO G enable */ #define RCC_AHB4ENCR_GPIOHENC_Pos (7U) #define RCC_AHB4ENCR_GPIOHENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOHENC_Pos) /*!< 0x00000080 */ #define RCC_AHB4ENCR_GPIOHENC RCC_AHB4ENCR_GPIOHENC_Msk /*!< GPIO H enable */ #define RCC_AHB4ENCR_GPIONENC_Pos (13U) #define RCC_AHB4ENCR_GPIONENC_Msk (0x1UL << RCC_AHB4ENCR_GPIONENC_Pos) /*!< 0x00002000 */ #define RCC_AHB4ENCR_GPIONENC RCC_AHB4ENCR_GPIONENC_Msk /*!< GPIO N enable */ #define RCC_AHB4ENCR_GPIOOENC_Pos (14U) #define RCC_AHB4ENCR_GPIOOENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOOENC_Pos) /*!< 0x00004000 */ #define RCC_AHB4ENCR_GPIOOENC RCC_AHB4ENCR_GPIOOENC_Msk /*!< GPIO O enable */ #define RCC_AHB4ENCR_GPIOPENC_Pos (15U) #define RCC_AHB4ENCR_GPIOPENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOPENC_Pos) /*!< 0x00008000 */ #define RCC_AHB4ENCR_GPIOPENC RCC_AHB4ENCR_GPIOPENC_Msk /*!< GPIO P enable */ #define RCC_AHB4ENCR_GPIOQENC_Pos (16U) #define RCC_AHB4ENCR_GPIOQENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOQENC_Pos) /*!< 0x00010000 */ #define RCC_AHB4ENCR_GPIOQENC RCC_AHB4ENCR_GPIOQENC_Msk /*!< GPIO Q enable */ #define RCC_AHB4ENCR_PWRENC_Pos (18U) #define RCC_AHB4ENCR_PWRENC_Msk (0x1UL << RCC_AHB4ENCR_PWRENC_Pos) /*!< 0x00040000 */ #define RCC_AHB4ENCR_PWRENC RCC_AHB4ENCR_PWRENC_Msk /*!< PWR enable */ #define RCC_AHB4ENCR_CRCENC_Pos (19U) #define RCC_AHB4ENCR_CRCENC_Msk (0x1UL << RCC_AHB4ENCR_CRCENC_Pos) /*!< 0x00080000 */ #define RCC_AHB4ENCR_CRCENC RCC_AHB4ENCR_CRCENC_Msk /*!< CRC enable */ /***************** Bit definition for RCC_AHB5ENCR register *****************/ #define RCC_AHB5ENCR_HPDMA1ENC_Pos (0U) #define RCC_AHB5ENCR_HPDMA1ENC_Msk (0x1UL << RCC_AHB5ENCR_HPDMA1ENC_Pos) /*!< 0x00000001 */ #define RCC_AHB5ENCR_HPDMA1ENC RCC_AHB5ENCR_HPDMA1ENC_Msk /*!< HPDMA1 enable */ #define RCC_AHB5ENCR_DMA2DENC_Pos (1U) #define RCC_AHB5ENCR_DMA2DENC_Msk (0x1UL << RCC_AHB5ENCR_DMA2DENC_Pos) /*!< 0x00000002 */ #define RCC_AHB5ENCR_DMA2DENC RCC_AHB5ENCR_DMA2DENC_Msk /*!< DMA2D enable */ #define RCC_AHB5ENCR_JPEGENC_Pos (3U) #define RCC_AHB5ENCR_JPEGENC_Msk (0x1UL << RCC_AHB5ENCR_JPEGENC_Pos) /*!< 0x00000008 */ #define RCC_AHB5ENCR_JPEGENC RCC_AHB5ENCR_JPEGENC_Msk /*!< JPEG enable */ #define RCC_AHB5ENCR_FMCENC_Pos (4U) #define RCC_AHB5ENCR_FMCENC_Msk (0x1UL << RCC_AHB5ENCR_FMCENC_Pos) /*!< 0x00000010 */ #define RCC_AHB5ENCR_FMCENC RCC_AHB5ENCR_FMCENC_Msk /*!< FMC enable */ #define RCC_AHB5ENCR_XSPI1ENC_Pos (5U) #define RCC_AHB5ENCR_XSPI1ENC_Msk (0x1UL << RCC_AHB5ENCR_XSPI1ENC_Pos) /*!< 0x00000020 */ #define RCC_AHB5ENCR_XSPI1ENC RCC_AHB5ENCR_XSPI1ENC_Msk /*!< XSPI1 enable */ #define RCC_AHB5ENCR_PSSIENC_Pos (6U) #define RCC_AHB5ENCR_PSSIENC_Msk (0x1UL << RCC_AHB5ENCR_PSSIENC_Pos) /*!< 0x00000040 */ #define RCC_AHB5ENCR_PSSIENC RCC_AHB5ENCR_PSSIENC_Msk /*!< PSSI enable */ #define RCC_AHB5ENCR_SDMMC2ENC_Pos (7U) #define RCC_AHB5ENCR_SDMMC2ENC_Msk (0x1UL << RCC_AHB5ENCR_SDMMC2ENC_Pos) /*!< 0x00000080 */ #define RCC_AHB5ENCR_SDMMC2ENC RCC_AHB5ENCR_SDMMC2ENC_Msk /*!< SDMMC2 enable */ #define RCC_AHB5ENCR_SDMMC1ENC_Pos (8U) #define RCC_AHB5ENCR_SDMMC1ENC_Msk (0x1UL << RCC_AHB5ENCR_SDMMC1ENC_Pos) /*!< 0x00000100 */ #define RCC_AHB5ENCR_SDMMC1ENC RCC_AHB5ENCR_SDMMC1ENC_Msk /*!< SDMMC1 enable */ #define RCC_AHB5ENCR_XSPI2ENC_Pos (12U) #define RCC_AHB5ENCR_XSPI2ENC_Msk (0x1UL << RCC_AHB5ENCR_XSPI2ENC_Pos) /*!< 0x00001000 */ #define RCC_AHB5ENCR_XSPI2ENC RCC_AHB5ENCR_XSPI2ENC_Msk /*!< XSPI2 enable */ #define RCC_AHB5ENCR_XSPIMENC_Pos (13U) #define RCC_AHB5ENCR_XSPIMENC_Msk (0x1UL << RCC_AHB5ENCR_XSPIMENC_Pos) /*!< 0x00002000 */ #define RCC_AHB5ENCR_XSPIMENC RCC_AHB5ENCR_XSPIMENC_Msk /*!< XSPIM enable */ #define RCC_AHB5ENCR_MCE1ENC_Pos (14U) #define RCC_AHB5ENCR_MCE1ENC_Msk (0x1UL << RCC_AHB5ENCR_MCE1ENC_Pos) /*!< 0x00004000 */ #define RCC_AHB5ENCR_MCE1ENC RCC_AHB5ENCR_MCE1ENC_Msk /*!< MCE1 enable */ #define RCC_AHB5ENCR_MCE2ENC_Pos (15U) #define RCC_AHB5ENCR_MCE2ENC_Msk (0x1UL << RCC_AHB5ENCR_MCE2ENC_Pos) /*!< 0x00008000 */ #define RCC_AHB5ENCR_MCE2ENC RCC_AHB5ENCR_MCE2ENC_Msk /*!< MCE2 enable */ #define RCC_AHB5ENCR_MCE3ENC_Pos (16U) #define RCC_AHB5ENCR_MCE3ENC_Msk (0x1UL << RCC_AHB5ENCR_MCE3ENC_Pos) /*!< 0x00010000 */ #define RCC_AHB5ENCR_MCE3ENC RCC_AHB5ENCR_MCE3ENC_Msk /*!< MCE3 enable */ #define RCC_AHB5ENCR_XSPI3ENC_Pos (17U) #define RCC_AHB5ENCR_XSPI3ENC_Msk (0x1UL << RCC_AHB5ENCR_XSPI3ENC_Pos) /*!< 0x00020000 */ #define RCC_AHB5ENCR_XSPI3ENC RCC_AHB5ENCR_XSPI3ENC_Msk /*!< XSPI3 enable */ #define RCC_AHB5ENCR_MCE4ENC_Pos (18U) #define RCC_AHB5ENCR_MCE4ENC_Msk (0x1UL << RCC_AHB5ENCR_MCE4ENC_Pos) /*!< 0x00040000 */ #define RCC_AHB5ENCR_MCE4ENC RCC_AHB5ENCR_MCE4ENC_Msk /*!< MCE4 enable */ #define RCC_AHB5ENCR_GFXMMUENC_Pos (19U) #define RCC_AHB5ENCR_GFXMMUENC_Msk (0x1UL << RCC_AHB5ENCR_GFXMMUENC_Pos) /*!< 0x00080000 */ #define RCC_AHB5ENCR_GFXMMUENC RCC_AHB5ENCR_GFXMMUENC_Msk /*!< GFXMMU enable */ #define RCC_AHB5ENCR_GPU2DENC_Pos (20U) #define RCC_AHB5ENCR_GPU2DENC_Msk (0x1UL << RCC_AHB5ENCR_GPU2DENC_Pos) /*!< 0x00100000 */ #define RCC_AHB5ENCR_GPU2DENC RCC_AHB5ENCR_GPU2DENC_Msk /*!< GPU2D enable */ #define RCC_AHB5ENCR_ETH1MACENC_Pos (22U) #define RCC_AHB5ENCR_ETH1MACENC_Msk (0x1UL << RCC_AHB5ENCR_ETH1MACENC_Pos)/*!< 0x00400000 */ #define RCC_AHB5ENCR_ETH1MACENC RCC_AHB5ENCR_ETH1MACENC_Msk /*!< ETH1MAC enable */ #define RCC_AHB5ENCR_ETH1TXENC_Pos (23U) #define RCC_AHB5ENCR_ETH1TXENC_Msk (0x1UL << RCC_AHB5ENCR_ETH1TXENC_Pos) /*!< 0x00800000 */ #define RCC_AHB5ENCR_ETH1TXENC RCC_AHB5ENCR_ETH1TXENC_Msk /*!< ETH1TX enable */ #define RCC_AHB5ENCR_ETH1RXENC_Pos (24U) #define RCC_AHB5ENCR_ETH1RXENC_Msk (0x1UL << RCC_AHB5ENCR_ETH1RXENC_Pos) /*!< 0x01000000 */ #define RCC_AHB5ENCR_ETH1RXENC RCC_AHB5ENCR_ETH1RXENC_Msk /*!< ETH1RX enable */ #define RCC_AHB5ENCR_ETH1ENC_Pos (25U) #define RCC_AHB5ENCR_ETH1ENC_Msk (0x1UL << RCC_AHB5ENCR_ETH1ENC_Pos) /*!< 0x02000000 */ #define RCC_AHB5ENCR_ETH1ENC RCC_AHB5ENCR_ETH1ENC_Msk /*!< ETH1 enable */ #define RCC_AHB5ENCR_OTG1ENC_Pos (26U) #define RCC_AHB5ENCR_OTG1ENC_Msk (0x1UL << RCC_AHB5ENCR_OTG1ENC_Pos) /*!< 0x04000000 */ #define RCC_AHB5ENCR_OTG1ENC RCC_AHB5ENCR_OTG1ENC_Msk /*!< OTG1 enable */ #define RCC_AHB5ENCR_OTGPHY1ENC_Pos (27U) #define RCC_AHB5ENCR_OTGPHY1ENC_Msk (0x1UL << RCC_AHB5ENCR_OTGPHY1ENC_Pos)/*!< 0x08000000 */ #define RCC_AHB5ENCR_OTGPHY1ENC RCC_AHB5ENCR_OTGPHY1ENC_Msk /*!< OTGPHY1 enable */ #define RCC_AHB5ENCR_OTGPHY2ENC_Pos (28U) #define RCC_AHB5ENCR_OTGPHY2ENC_Msk (0x1UL << RCC_AHB5ENCR_OTGPHY2ENC_Pos)/*!< 0x10000000 */ #define RCC_AHB5ENCR_OTGPHY2ENC RCC_AHB5ENCR_OTGPHY2ENC_Msk /*!< OTGPHY2 enable */ #define RCC_AHB5ENCR_OTG2ENC_Pos (29U) #define RCC_AHB5ENCR_OTG2ENC_Msk (0x1UL << RCC_AHB5ENCR_OTG2ENC_Pos) /*!< 0x20000000 */ #define RCC_AHB5ENCR_OTG2ENC RCC_AHB5ENCR_OTG2ENC_Msk /*!< OTG2 enable */ #define RCC_AHB5ENCR_CACHEAXIENC_Pos (30U) #define RCC_AHB5ENCR_CACHEAXIENC_Msk (0x1UL << RCC_AHB5ENCR_CACHEAXIENC_Pos) /*!< 0x40000000 */ #define RCC_AHB5ENCR_CACHEAXIENC RCC_AHB5ENCR_CACHEAXIENC_Msk /*!< CACHEAXI enable */ #define RCC_AHB5ENCR_NPUENC_Pos (31U) #define RCC_AHB5ENCR_NPUENC_Msk (0x1UL << RCC_AHB5ENCR_NPUENC_Pos) /*!< 0x80000000 */ #define RCC_AHB5ENCR_NPUENC RCC_AHB5ENCR_NPUENC_Msk /*!< NPU enable */ /**************** Bit definition for RCC_APB1ENCR1 register *****************/ #define RCC_APB1ENCR1_TIM2ENC_Pos (0U) #define RCC_APB1ENCR1_TIM2ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM2ENC_Pos) /*!< 0x00000001 */ #define RCC_APB1ENCR1_TIM2ENC RCC_APB1ENCR1_TIM2ENC_Msk /*!< TIM2 enable */ #define RCC_APB1ENCR1_TIM3ENC_Pos (1U) #define RCC_APB1ENCR1_TIM3ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM3ENC_Pos) /*!< 0x00000002 */ #define RCC_APB1ENCR1_TIM3ENC RCC_APB1ENCR1_TIM3ENC_Msk /*!< TIM3 enable */ #define RCC_APB1ENCR1_TIM4ENC_Pos (2U) #define RCC_APB1ENCR1_TIM4ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM4ENC_Pos) /*!< 0x00000004 */ #define RCC_APB1ENCR1_TIM4ENC RCC_APB1ENCR1_TIM4ENC_Msk /*!< TIM4 enable */ #define RCC_APB1ENCR1_TIM5ENC_Pos (3U) #define RCC_APB1ENCR1_TIM5ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM5ENC_Pos) /*!< 0x00000008 */ #define RCC_APB1ENCR1_TIM5ENC RCC_APB1ENCR1_TIM5ENC_Msk /*!< TIM5 enable */ #define RCC_APB1ENCR1_TIM6ENC_Pos (4U) #define RCC_APB1ENCR1_TIM6ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM6ENC_Pos) /*!< 0x00000010 */ #define RCC_APB1ENCR1_TIM6ENC RCC_APB1ENCR1_TIM6ENC_Msk /*!< TIM6 enable */ #define RCC_APB1ENCR1_TIM7ENC_Pos (5U) #define RCC_APB1ENCR1_TIM7ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM7ENC_Pos) /*!< 0x00000020 */ #define RCC_APB1ENCR1_TIM7ENC RCC_APB1ENCR1_TIM7ENC_Msk /*!< TIM7 enable */ #define RCC_APB1ENCR1_TIM12ENC_Pos (6U) #define RCC_APB1ENCR1_TIM12ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM12ENC_Pos) /*!< 0x00000040 */ #define RCC_APB1ENCR1_TIM12ENC RCC_APB1ENCR1_TIM12ENC_Msk /*!< TIM12 enable */ #define RCC_APB1ENCR1_TIM13ENC_Pos (7U) #define RCC_APB1ENCR1_TIM13ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM13ENC_Pos) /*!< 0x00000080 */ #define RCC_APB1ENCR1_TIM13ENC RCC_APB1ENCR1_TIM13ENC_Msk /*!< TIM13 enable */ #define RCC_APB1ENCR1_TIM14ENC_Pos (8U) #define RCC_APB1ENCR1_TIM14ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM14ENC_Pos) /*!< 0x00000100 */ #define RCC_APB1ENCR1_TIM14ENC RCC_APB1ENCR1_TIM14ENC_Msk /*!< TIM14 enable */ #define RCC_APB1ENCR1_LPTIM1ENC_Pos (9U) #define RCC_APB1ENCR1_LPTIM1ENC_Msk (0x1UL << RCC_APB1ENCR1_LPTIM1ENC_Pos)/*!< 0x00000200 */ #define RCC_APB1ENCR1_LPTIM1ENC RCC_APB1ENCR1_LPTIM1ENC_Msk /*!< LPTIM1 enable */ #define RCC_APB1ENCR1_TIM10ENC_Pos (12U) #define RCC_APB1ENCR1_TIM10ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM10ENC_Pos) /*!< 0x00001000 */ #define RCC_APB1ENCR1_TIM10ENC RCC_APB1ENCR1_TIM10ENC_Msk /*!< TIM10 enable */ #define RCC_APB1ENCR1_TIM11ENC_Pos (13U) #define RCC_APB1ENCR1_TIM11ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM11ENC_Pos) /*!< 0x00002000 */ #define RCC_APB1ENCR1_TIM11ENC RCC_APB1ENCR1_TIM11ENC_Msk /*!< TIM11 enable */ #define RCC_APB1ENCR1_SPI2ENC_Pos (14U) #define RCC_APB1ENCR1_SPI2ENC_Msk (0x1UL << RCC_APB1ENCR1_SPI2ENC_Pos) /*!< 0x00004000 */ #define RCC_APB1ENCR1_SPI2ENC RCC_APB1ENCR1_SPI2ENC_Msk /*!< SPI2 enable */ #define RCC_APB1ENCR1_SPI3ENC_Pos (15U) #define RCC_APB1ENCR1_SPI3ENC_Msk (0x1UL << RCC_APB1ENCR1_SPI3ENC_Pos) /*!< 0x00008000 */ #define RCC_APB1ENCR1_SPI3ENC RCC_APB1ENCR1_SPI3ENC_Msk /*!< SPI3 enable */ #define RCC_APB1ENCR1_SPDIFRX1ENC_Pos (16U) #define RCC_APB1ENCR1_SPDIFRX1ENC_Msk (0x1UL << RCC_APB1ENCR1_SPDIFRX1ENC_Pos) /*!< 0x00010000 */ #define RCC_APB1ENCR1_SPDIFRX1ENC RCC_APB1ENCR1_SPDIFRX1ENC_Msk /*!< SPDIFRX1 enable */ #define RCC_APB1ENCR1_USART2ENC_Pos (17U) #define RCC_APB1ENCR1_USART2ENC_Msk (0x1UL << RCC_APB1ENCR1_USART2ENC_Pos)/*!< 0x00020000 */ #define RCC_APB1ENCR1_USART2ENC RCC_APB1ENCR1_USART2ENC_Msk /*!< USART2 enable */ #define RCC_APB1ENCR1_USART3ENC_Pos (18U) #define RCC_APB1ENCR1_USART3ENC_Msk (0x1UL << RCC_APB1ENCR1_USART3ENC_Pos)/*!< 0x00040000 */ #define RCC_APB1ENCR1_USART3ENC RCC_APB1ENCR1_USART3ENC_Msk /*!< USART3 enable */ #define RCC_APB1ENCR1_UART4ENC_Pos (19U) #define RCC_APB1ENCR1_UART4ENC_Msk (0x1UL << RCC_APB1ENCR1_UART4ENC_Pos) /*!< 0x00080000 */ #define RCC_APB1ENCR1_UART4ENC RCC_APB1ENCR1_UART4ENC_Msk /*!< UART4 enable */ #define RCC_APB1ENCR1_UART5ENC_Pos (20U) #define RCC_APB1ENCR1_UART5ENC_Msk (0x1UL << RCC_APB1ENCR1_UART5ENC_Pos) /*!< 0x00100000 */ #define RCC_APB1ENCR1_UART5ENC RCC_APB1ENCR1_UART5ENC_Msk /*!< UART5 enable */ #define RCC_APB1ENCR1_I2C1ENC_Pos (21U) #define RCC_APB1ENCR1_I2C1ENC_Msk (0x1UL << RCC_APB1ENCR1_I2C1ENC_Pos) /*!< 0x00200000 */ #define RCC_APB1ENCR1_I2C1ENC RCC_APB1ENCR1_I2C1ENC_Msk /*!< I2C1 enable */ #define RCC_APB1ENCR1_I2C2ENC_Pos (22U) #define RCC_APB1ENCR1_I2C2ENC_Msk (0x1UL << RCC_APB1ENCR1_I2C2ENC_Pos) /*!< 0x00400000 */ #define RCC_APB1ENCR1_I2C2ENC RCC_APB1ENCR1_I2C2ENC_Msk /*!< I2C2 enable */ #define RCC_APB1ENCR1_I2C3ENC_Pos (23U) #define RCC_APB1ENCR1_I2C3ENC_Msk (0x1UL << RCC_APB1ENCR1_I2C3ENC_Pos) /*!< 0x00800000 */ #define RCC_APB1ENCR1_I2C3ENC RCC_APB1ENCR1_I2C3ENC_Msk /*!< I2C3 enable */ #define RCC_APB1ENCR1_I3C1ENC_Pos (24U) #define RCC_APB1ENCR1_I3C1ENC_Msk (0x1UL << RCC_APB1ENCR1_I3C1ENC_Pos) /*!< 0x01000000 */ #define RCC_APB1ENCR1_I3C1ENC RCC_APB1ENCR1_I3C1ENC_Msk /*!< I3C1 enable */ #define RCC_APB1ENCR1_I3C2ENC_Pos (25U) #define RCC_APB1ENCR1_I3C2ENC_Msk (0x1UL << RCC_APB1ENCR1_I3C2ENC_Pos) /*!< 0x02000000 */ #define RCC_APB1ENCR1_I3C2ENC RCC_APB1ENCR1_I3C2ENC_Msk /*!< I3C2 enable */ #define RCC_APB1ENCR1_UART7ENC_Pos (30U) #define RCC_APB1ENCR1_UART7ENC_Msk (0x1UL << RCC_APB1ENCR1_UART7ENC_Pos) /*!< 0x40000000 */ #define RCC_APB1ENCR1_UART7ENC RCC_APB1ENCR1_UART7ENC_Msk /*!< UART7 enable */ #define RCC_APB1ENCR1_UART8ENC_Pos (31U) #define RCC_APB1ENCR1_UART8ENC_Msk (0x1UL << RCC_APB1ENCR1_UART8ENC_Pos) /*!< 0x80000000 */ #define RCC_APB1ENCR1_UART8ENC RCC_APB1ENCR1_UART8ENC_Msk /*!< UART8 enable */ /**************** Bit definition for RCC_APB1ENCR2 register *****************/ #define RCC_APB1ENCR2_MDIOSENC_Pos (5U) #define RCC_APB1ENCR2_MDIOSENC_Msk (0x1UL << RCC_APB1ENCR2_MDIOSENC_Pos) /*!< 0x00000020 */ #define RCC_APB1ENCR2_MDIOSENC RCC_APB1ENCR2_MDIOSENC_Msk /*!< MDIOS enable */ #define RCC_APB1ENCR2_FDCANENC_Pos (8U) #define RCC_APB1ENCR2_FDCANENC_Msk (0x1UL << RCC_APB1ENCR2_FDCANENC_Pos) /*!< 0x00000100 */ #define RCC_APB1ENCR2_FDCANENC RCC_APB1ENCR2_FDCANENC_Msk /*!< FDCAN enable */ #define RCC_APB1ENCR2_UCPD1ENC_Pos (18U) #define RCC_APB1ENCR2_UCPD1ENC_Msk (0x1UL << RCC_APB1ENCR2_UCPD1ENC_Pos) /*!< 0x00040000 */ #define RCC_APB1ENCR2_UCPD1ENC RCC_APB1ENCR2_UCPD1ENC_Msk /*!< UCPD1 enable */ /***************** Bit definition for RCC_APB2ENCR register *****************/ #define RCC_APB2ENCR_TIM1ENC_Pos (0U) #define RCC_APB2ENCR_TIM1ENC_Msk (0x1UL << RCC_APB2ENCR_TIM1ENC_Pos) /*!< 0x00000001 */ #define RCC_APB2ENCR_TIM1ENC RCC_APB2ENCR_TIM1ENC_Msk /*!< TIM1 enable */ #define RCC_APB2ENCR_TIM8ENC_Pos (1U) #define RCC_APB2ENCR_TIM8ENC_Msk (0x1UL << RCC_APB2ENCR_TIM8ENC_Pos) /*!< 0x00000002 */ #define RCC_APB2ENCR_TIM8ENC RCC_APB2ENCR_TIM8ENC_Msk /*!< TIM8 enable */ #define RCC_APB2ENCR_USART1ENC_Pos (4U) #define RCC_APB2ENCR_USART1ENC_Msk (0x1UL << RCC_APB2ENCR_USART1ENC_Pos) /*!< 0x00000010 */ #define RCC_APB2ENCR_USART1ENC RCC_APB2ENCR_USART1ENC_Msk /*!< USART1 enable */ #define RCC_APB2ENCR_USART6ENC_Pos (5U) #define RCC_APB2ENCR_USART6ENC_Msk (0x1UL << RCC_APB2ENCR_USART6ENC_Pos) /*!< 0x00000020 */ #define RCC_APB2ENCR_USART6ENC RCC_APB2ENCR_USART6ENC_Msk /*!< USART6 enable */ #define RCC_APB2ENCR_UART9ENC_Pos (6U) #define RCC_APB2ENCR_UART9ENC_Msk (0x1UL << RCC_APB2ENCR_UART9ENC_Pos) /*!< 0x00000040 */ #define RCC_APB2ENCR_UART9ENC RCC_APB2ENCR_UART9ENC_Msk /*!< UART9 enable */ #define RCC_APB2ENCR_USART10ENC_Pos (7U) #define RCC_APB2ENCR_USART10ENC_Msk (0x1UL << RCC_APB2ENCR_USART10ENC_Pos)/*!< 0x00000080 */ #define RCC_APB2ENCR_USART10ENC RCC_APB2ENCR_USART10ENC_Msk /*!< USART10 enable */ #define RCC_APB2ENCR_SPI1ENC_Pos (12U) #define RCC_APB2ENCR_SPI1ENC_Msk (0x1UL << RCC_APB2ENCR_SPI1ENC_Pos) /*!< 0x00001000 */ #define RCC_APB2ENCR_SPI1ENC RCC_APB2ENCR_SPI1ENC_Msk /*!< SPI1 enable */ #define RCC_APB2ENCR_SPI4ENC_Pos (13U) #define RCC_APB2ENCR_SPI4ENC_Msk (0x1UL << RCC_APB2ENCR_SPI4ENC_Pos) /*!< 0x00002000 */ #define RCC_APB2ENCR_SPI4ENC RCC_APB2ENCR_SPI4ENC_Msk /*!< SPI4 enable */ #define RCC_APB2ENCR_TIM18ENC_Pos (15U) #define RCC_APB2ENCR_TIM18ENC_Msk (0x1UL << RCC_APB2ENCR_TIM18ENC_Pos) /*!< 0x00008000 */ #define RCC_APB2ENCR_TIM18ENC RCC_APB2ENCR_TIM18ENC_Msk /*!< TIM18 enable */ #define RCC_APB2ENCR_TIM15ENC_Pos (16U) #define RCC_APB2ENCR_TIM15ENC_Msk (0x1UL << RCC_APB2ENCR_TIM15ENC_Pos) /*!< 0x00010000 */ #define RCC_APB2ENCR_TIM15ENC RCC_APB2ENCR_TIM15ENC_Msk /*!< TIM15 enable */ #define RCC_APB2ENCR_TIM16ENC_Pos (17U) #define RCC_APB2ENCR_TIM16ENC_Msk (0x1UL << RCC_APB2ENCR_TIM16ENC_Pos) /*!< 0x00020000 */ #define RCC_APB2ENCR_TIM16ENC RCC_APB2ENCR_TIM16ENC_Msk /*!< TIM16 enable */ #define RCC_APB2ENCR_TIM17ENC_Pos (18U) #define RCC_APB2ENCR_TIM17ENC_Msk (0x1UL << RCC_APB2ENCR_TIM17ENC_Pos) /*!< 0x00040000 */ #define RCC_APB2ENCR_TIM17ENC RCC_APB2ENCR_TIM17ENC_Msk /*!< TIM17 enable */ #define RCC_APB2ENCR_TIM9ENC_Pos (19U) #define RCC_APB2ENCR_TIM9ENC_Msk (0x1UL << RCC_APB2ENCR_TIM9ENC_Pos) /*!< 0x00080000 */ #define RCC_APB2ENCR_TIM9ENC RCC_APB2ENCR_TIM9ENC_Msk /*!< TIM9 enable */ #define RCC_APB2ENCR_SPI5ENC_Pos (20U) #define RCC_APB2ENCR_SPI5ENC_Msk (0x1UL << RCC_APB2ENCR_SPI5ENC_Pos) /*!< 0x00100000 */ #define RCC_APB2ENCR_SPI5ENC RCC_APB2ENCR_SPI5ENC_Msk /*!< SPI5 enable */ #define RCC_APB2ENCR_SAI1ENC_Pos (21U) #define RCC_APB2ENCR_SAI1ENC_Msk (0x1UL << RCC_APB2ENCR_SAI1ENC_Pos) /*!< 0x00200000 */ #define RCC_APB2ENCR_SAI1ENC RCC_APB2ENCR_SAI1ENC_Msk /*!< SAI1 enable */ #define RCC_APB2ENCR_SAI2ENC_Pos (22U) #define RCC_APB2ENCR_SAI2ENC_Msk (0x1UL << RCC_APB2ENCR_SAI2ENC_Pos) /*!< 0x00400000 */ #define RCC_APB2ENCR_SAI2ENC RCC_APB2ENCR_SAI2ENC_Msk /*!< SAI2 enable */ /***************** Bit definition for RCC_APB3ENCR register *****************/ #define RCC_APB3ENCR_DFTENC_Pos (2U) #define RCC_APB3ENCR_DFTENC_Msk (0x1UL << RCC_APB3ENCR_DFTENC_Pos) /*!< 0x00000004 */ #define RCC_APB3ENCR_DFTENC RCC_APB3ENCR_DFTENC_Msk /*!< DFT enable */ /**************** Bit definition for RCC_APB4ENCR1 register *****************/ #define RCC_APB4ENCR1_HDPENC_Pos (2U) #define RCC_APB4ENCR1_HDPENC_Msk (0x1UL << RCC_APB4ENCR1_HDPENC_Pos) /*!< 0x00000004 */ #define RCC_APB4ENCR1_HDPENC RCC_APB4ENCR1_HDPENC_Msk /*!< HDP enable */ #define RCC_APB4ENCR1_LPUART1ENC_Pos (3U) #define RCC_APB4ENCR1_LPUART1ENC_Msk (0x1UL << RCC_APB4ENCR1_LPUART1ENC_Pos) /*!< 0x00000008 */ #define RCC_APB4ENCR1_LPUART1ENC RCC_APB4ENCR1_LPUART1ENC_Msk /*!< LPUART1 enable */ #define RCC_APB4ENCR1_SPI6ENC_Pos (5U) #define RCC_APB4ENCR1_SPI6ENC_Msk (0x1UL << RCC_APB4ENCR1_SPI6ENC_Pos) /*!< 0x00000020 */ #define RCC_APB4ENCR1_SPI6ENC RCC_APB4ENCR1_SPI6ENC_Msk /*!< SPI6 enable */ #define RCC_APB4ENCR1_I2C4ENC_Pos (7U) #define RCC_APB4ENCR1_I2C4ENC_Msk (0x1UL << RCC_APB4ENCR1_I2C4ENC_Pos) /*!< 0x00000080 */ #define RCC_APB4ENCR1_I2C4ENC RCC_APB4ENCR1_I2C4ENC_Msk /*!< I2C4 enable */ #define RCC_APB4ENCR1_LPTIM2ENC_Pos (9U) #define RCC_APB4ENCR1_LPTIM2ENC_Msk (0x1UL << RCC_APB4ENCR1_LPTIM2ENC_Pos)/*!< 0x00000200 */ #define RCC_APB4ENCR1_LPTIM2ENC RCC_APB4ENCR1_LPTIM2ENC_Msk /*!< LPTIM2 enable */ #define RCC_APB4ENCR1_LPTIM3ENC_Pos (10U) #define RCC_APB4ENCR1_LPTIM3ENC_Msk (0x1UL << RCC_APB4ENCR1_LPTIM3ENC_Pos)/*!< 0x00000400 */ #define RCC_APB4ENCR1_LPTIM3ENC RCC_APB4ENCR1_LPTIM3ENC_Msk /*!< LPTIM3 enable */ #define RCC_APB4ENCR1_LPTIM4ENC_Pos (11U) #define RCC_APB4ENCR1_LPTIM4ENC_Msk (0x1UL << RCC_APB4ENCR1_LPTIM4ENC_Pos)/*!< 0x00000800 */ #define RCC_APB4ENCR1_LPTIM4ENC RCC_APB4ENCR1_LPTIM4ENC_Msk /*!< LPTIM4 enable */ #define RCC_APB4ENCR1_LPTIM5ENC_Pos (12U) #define RCC_APB4ENCR1_LPTIM5ENC_Msk (0x1UL << RCC_APB4ENCR1_LPTIM5ENC_Pos)/*!< 0x00001000 */ #define RCC_APB4ENCR1_LPTIM5ENC RCC_APB4ENCR1_LPTIM5ENC_Msk /*!< LPTIM5 enable */ #define RCC_APB4ENCR1_VREFBUFENC_Pos (15U) #define RCC_APB4ENCR1_VREFBUFENC_Msk (0x1UL << RCC_APB4ENCR1_VREFBUFENC_Pos) /*!< 0x00008000 */ #define RCC_APB4ENCR1_VREFBUFENC RCC_APB4ENCR1_VREFBUFENC_Msk /*!< VREFBUF enable */ #define RCC_APB4ENCR1_RTCENC_Pos (16U) #define RCC_APB4ENCR1_RTCENC_Msk (0x1UL << RCC_APB4ENCR1_RTCENC_Pos) /*!< 0x00010000 */ #define RCC_APB4ENCR1_RTCENC RCC_APB4ENCR1_RTCENC_Msk /*!< RTC enable */ #define RCC_APB4ENCR1_RTCAPBENC_Pos (17U) #define RCC_APB4ENCR1_RTCAPBENC_Msk (0x1UL << RCC_APB4ENCR1_RTCAPBENC_Pos)/*!< 0x00020000 */ #define RCC_APB4ENCR1_RTCAPBENC RCC_APB4ENCR1_RTCAPBENC_Msk /*!< RTCAPB enable */ /**************** Bit definition for RCC_APB4ENCR2 register *****************/ #define RCC_APB4ENCR2_SYSCFGENC_Pos (0U) #define RCC_APB4ENCR2_SYSCFGENC_Msk (0x1UL << RCC_APB4ENCR2_SYSCFGENC_Pos)/*!< 0x00000001 */ #define RCC_APB4ENCR2_SYSCFGENC RCC_APB4ENCR2_SYSCFGENC_Msk /*!< SYSCFG enable */ #define RCC_APB4ENCR2_BSECENC_Pos (1U) #define RCC_APB4ENCR2_BSECENC_Msk (0x1UL << RCC_APB4ENCR2_BSECENC_Pos) /*!< 0x00000002 */ #define RCC_APB4ENCR2_BSECENC RCC_APB4ENCR2_BSECENC_Msk /*!< BSEC enable */ #define RCC_APB4ENCR2_DTSENC_Pos (2U) #define RCC_APB4ENCR2_DTSENC_Msk (0x1UL << RCC_APB4ENCR2_DTSENC_Pos) /*!< 0x00000004 */ #define RCC_APB4ENCR2_DTSENC RCC_APB4ENCR2_DTSENC_Msk /*!< DTS enable */ /***************** Bit definition for RCC_APB5ENCR register *****************/ #define RCC_APB5ENCR_LTDCENC_Pos (1U) #define RCC_APB5ENCR_LTDCENC_Msk (0x1UL << RCC_APB5ENCR_LTDCENC_Pos) /*!< 0x00000002 */ #define RCC_APB5ENCR_LTDCENC RCC_APB5ENCR_LTDCENC_Msk /*!< LTDC enable */ #define RCC_APB5ENCR_DCMIPPENC_Pos (2U) #define RCC_APB5ENCR_DCMIPPENC_Msk (0x1UL << RCC_APB5ENCR_DCMIPPENC_Pos) /*!< 0x00000004 */ #define RCC_APB5ENCR_DCMIPPENC RCC_APB5ENCR_DCMIPPENC_Msk /*!< DCMIPP enable */ #define RCC_APB5ENCR_GFXTIMENC_Pos (4U) #define RCC_APB5ENCR_GFXTIMENC_Msk (0x1UL << RCC_APB5ENCR_GFXTIMENC_Pos) /*!< 0x00000010 */ #define RCC_APB5ENCR_GFXTIMENC RCC_APB5ENCR_GFXTIMENC_Msk /*!< GFXTIM enable */ #define RCC_APB5ENCR_VENCENC_Pos (5U) #define RCC_APB5ENCR_VENCENC_Msk (0x1UL << RCC_APB5ENCR_VENCENC_Pos) /*!< 0x00000020 */ #define RCC_APB5ENCR_VENCENC RCC_APB5ENCR_VENCENC_Msk /*!< VENC enable */ #define RCC_APB5ENCR_CSIENC_Pos (6U) #define RCC_APB5ENCR_CSIENC_Msk (0x1UL << RCC_APB5ENCR_CSIENC_Pos) /*!< 0x00000040 */ #define RCC_APB5ENCR_CSIENC RCC_APB5ENCR_CSIENC_Msk /*!< CSI enable */ /**************** Bit definition for RCC_BUSLPENCR register *****************/ #define RCC_BUSLPENCR_ACLKNLPENC_Pos (0U) #define RCC_BUSLPENCR_ACLKNLPENC_Msk (0x1UL << RCC_BUSLPENCR_ACLKNLPENC_Pos) /*!< 0x00000001 */ #define RCC_BUSLPENCR_ACLKNLPENC RCC_BUSLPENCR_ACLKNLPENC_Msk /*!< ACLKN enable in Sleep mode */ #define RCC_BUSLPENCR_ACLKNCLPENC_Pos (1U) #define RCC_BUSLPENCR_ACLKNCLPENC_Msk (0x1UL << RCC_BUSLPENCR_ACLKNCLPENC_Pos) /*!< 0x00000002 */ #define RCC_BUSLPENCR_ACLKNCLPENC RCC_BUSLPENCR_ACLKNCLPENC_Msk /*!< ACLKNC enable in Sleep mode */ /**************** Bit definition for RCC_MISCLPENCR register ****************/ #define RCC_MISCLPENCR_DBGLPENC_Pos (0U) #define RCC_MISCLPENCR_DBGLPENC_Msk (0x1UL << RCC_MISCLPENCR_DBGLPENC_Pos)/*!< 0x00000001 */ #define RCC_MISCLPENCR_DBGLPENC RCC_MISCLPENCR_DBGLPENC_Msk /*!< DBG enable in Sleep mode */ #define RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Pos (3U) #define RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Msk (0x1UL << RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Pos) /*!< 0x00000008 */ #define RCC_MISCLPENCR_XSPIPHYCOMPLPENC RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Msk /*!< XSPIPHYCOMP enable in Sleep mode */ #define RCC_MISCLPENCR_PERLPENC_Pos (6U) #define RCC_MISCLPENCR_PERLPENC_Msk (0x1UL << RCC_MISCLPENCR_PERLPENC_Pos)/*!< 0x00000040 */ #define RCC_MISCLPENCR_PERLPENC RCC_MISCLPENCR_PERLPENC_Msk /*!< PER enable in Sleep mode */ /**************** Bit definition for RCC_MEMLPENCR register *****************/ #define RCC_MEMLPENCR_AXISRAM3LPENC_Pos (0U) #define RCC_MEMLPENCR_AXISRAM3LPENC_Msk (0x1UL << RCC_MEMLPENCR_AXISRAM3LPENC_Pos) /*!< 0x00000001 */ #define RCC_MEMLPENCR_AXISRAM3LPENC RCC_MEMLPENCR_AXISRAM3LPENC_Msk /*!< AXISRAM3 enable in Sleep mode */ #define RCC_MEMLPENCR_AXISRAM4LPENC_Pos (1U) #define RCC_MEMLPENCR_AXISRAM4LPENC_Msk (0x1UL << RCC_MEMLPENCR_AXISRAM4LPENC_Pos) /*!< 0x00000002 */ #define RCC_MEMLPENCR_AXISRAM4LPENC RCC_MEMLPENCR_AXISRAM4LPENC_Msk /*!< AXISRAM4 enable in Sleep mode */ #define RCC_MEMLPENCR_AXISRAM5LPENC_Pos (2U) #define RCC_MEMLPENCR_AXISRAM5LPENC_Msk (0x1UL << RCC_MEMLPENCR_AXISRAM5LPENC_Pos) /*!< 0x00000004 */ #define RCC_MEMLPENCR_AXISRAM5LPENC RCC_MEMLPENCR_AXISRAM5LPENC_Msk /*!< AXISRAM5 enable in Sleep mode */ #define RCC_MEMLPENCR_AXISRAM6LPENC_Pos (3U) #define RCC_MEMLPENCR_AXISRAM6LPENC_Msk (0x1UL << RCC_MEMLPENCR_AXISRAM6LPENC_Pos) /*!< 0x00000008 */ #define RCC_MEMLPENCR_AXISRAM6LPENC RCC_MEMLPENCR_AXISRAM6LPENC_Msk /*!< AXISRAM6 enable in Sleep mode */ #define RCC_MEMLPENCR_AHBSRAM1LPENC_Pos (4U) #define RCC_MEMLPENCR_AHBSRAM1LPENC_Msk (0x1UL << RCC_MEMLPENCR_AHBSRAM1LPENC_Pos) /*!< 0x00000010 */ #define RCC_MEMLPENCR_AHBSRAM1LPENC RCC_MEMLPENCR_AHBSRAM1LPENC_Msk /*!< AHBSRAM1 enable in Sleep mode */ #define RCC_MEMLPENCR_AHBSRAM2LPENC_Pos (5U) #define RCC_MEMLPENCR_AHBSRAM2LPENC_Msk (0x1UL << RCC_MEMLPENCR_AHBSRAM2LPENC_Pos) /*!< 0x00000020 */ #define RCC_MEMLPENCR_AHBSRAM2LPENC RCC_MEMLPENCR_AHBSRAM2LPENC_Msk /*!< AHBSRAM2 enable in Sleep mode */ #define RCC_MEMLPENCR_BKPSRAMLPENC_Pos (6U) #define RCC_MEMLPENCR_BKPSRAMLPENC_Msk (0x1UL << RCC_MEMLPENCR_BKPSRAMLPENC_Pos) /*!< 0x00000040 */ #define RCC_MEMLPENCR_BKPSRAMLPENC RCC_MEMLPENCR_BKPSRAMLPENC_Msk /*!< BKPSRAM enable in Sleep mode */ #define RCC_MEMLPENCR_AXISRAM1LPENC_Pos (7U) #define RCC_MEMLPENCR_AXISRAM1LPENC_Msk (0x1UL << RCC_MEMLPENCR_AXISRAM1LPENC_Pos) /*!< 0x00000080 */ #define RCC_MEMLPENCR_AXISRAM1LPENC RCC_MEMLPENCR_AXISRAM1LPENC_Msk /*!< AXISRAM1 enable in Sleep mode */ #define RCC_MEMLPENCR_AXISRAM2LPENC_Pos (8U) #define RCC_MEMLPENCR_AXISRAM2LPENC_Msk (0x1UL << RCC_MEMLPENCR_AXISRAM2LPENC_Pos) /*!< 0x00000100 */ #define RCC_MEMLPENCR_AXISRAM2LPENC RCC_MEMLPENCR_AXISRAM2LPENC_Msk /*!< AXISRAM2 enable in Sleep mode */ #define RCC_MEMLPENCR_FLEXRAMLPENC_Pos (9U) #define RCC_MEMLPENCR_FLEXRAMLPENC_Msk (0x1UL << RCC_MEMLPENCR_FLEXRAMLPENC_Pos) /*!< 0x00000200 */ #define RCC_MEMLPENCR_FLEXRAMLPENC RCC_MEMLPENCR_FLEXRAMLPENC_Msk /*!< FLEXRAM enable in Sleep mode */ #define RCC_MEMLPENCR_CACHEAXIRAMLPENC_Pos (10U) #define RCC_MEMLPENCR_CACHEAXIRAMLPENC_Msk (0x1UL << RCC_MEMLPENCR_CACHEAXIRAMLPENC_Pos) /*!< 0x00000400 */ #define RCC_MEMLPENCR_CACHEAXIRAMLPENC RCC_MEMLPENCR_CACHEAXIRAMLPENC_Msk /*!< CACHEAXIRAM enable in Sleep mode */ #define RCC_MEMLPENCR_VENCRAMLPENC_Pos (11U) #define RCC_MEMLPENCR_VENCRAMLPENC_Msk (0x1UL << RCC_MEMLPENCR_VENCRAMLPENC_Pos) /*!< 0x00000800 */ #define RCC_MEMLPENCR_VENCRAMLPENC RCC_MEMLPENCR_VENCRAMLPENC_Msk /*!< VENCRAM enable in Sleep mode */ #define RCC_MEMLPENCR_BOOTROMLPENC_Pos (12U) #define RCC_MEMLPENCR_BOOTROMLPENC_Msk (0x1UL << RCC_MEMLPENCR_BOOTROMLPENC_Pos) /*!< 0x00001000 */ #define RCC_MEMLPENCR_BOOTROMLPENC RCC_MEMLPENCR_BOOTROMLPENC_Msk /*!< Boot ROM enable in Sleep mode */ /**************** Bit definition for RCC_AHB1LPENCR register ****************/ #define RCC_AHB1LPENCR_GPDMA1LPENC_Pos (4U) #define RCC_AHB1LPENCR_GPDMA1LPENC_Msk (0x1UL << RCC_AHB1LPENCR_GPDMA1LPENC_Pos) /*!< 0x00000010 */ #define RCC_AHB1LPENCR_GPDMA1LPENC RCC_AHB1LPENCR_GPDMA1LPENC_Msk /*!< GPDMA1 enable in Sleep mode */ #define RCC_AHB1LPENCR_ADC12LPENC_Pos (5U) #define RCC_AHB1LPENCR_ADC12LPENC_Msk (0x1UL << RCC_AHB1LPENCR_ADC12LPENC_Pos) /*!< 0x00000020 */ #define RCC_AHB1LPENCR_ADC12LPENC RCC_AHB1LPENCR_ADC12LPENC_Msk /*!< ADC12 enable in Sleep mode */ /**************** Bit definition for RCC_AHB2LPENCR register ****************/ #define RCC_AHB2LPENCR_RAMCFGLPENC_Pos (12U) #define RCC_AHB2LPENCR_RAMCFGLPENC_Msk (0x1UL << RCC_AHB2LPENCR_RAMCFGLPENC_Pos) /*!< 0x00001000 */ #define RCC_AHB2LPENCR_RAMCFGLPENC RCC_AHB2LPENCR_RAMCFGLPENC_Msk /*!< RAMCFG enable in Sleep mode */ #define RCC_AHB2LPENCR_MDF1LPENC_Pos (16U) #define RCC_AHB2LPENCR_MDF1LPENC_Msk (0x1UL << RCC_AHB2LPENCR_MDF1LPENC_Pos) /*!< 0x00010000 */ #define RCC_AHB2LPENCR_MDF1LPENC RCC_AHB2LPENCR_MDF1LPENC_Msk /*!< MDF1 enable in Sleep mode */ #define RCC_AHB2LPENCR_ADF1LPENC_Pos (17U) #define RCC_AHB2LPENCR_ADF1LPENC_Msk (0x1UL << RCC_AHB2LPENCR_ADF1LPENC_Pos) /*!< 0x00020000 */ #define RCC_AHB2LPENCR_ADF1LPENC RCC_AHB2LPENCR_ADF1LPENC_Msk /*!< ADF1 enable in Sleep mode */ /**************** Bit definition for RCC_AHB3LPENCR register ****************/ #define RCC_AHB3LPENCR_RNGLPENC_Pos (0U) #define RCC_AHB3LPENCR_RNGLPENC_Msk (0x1UL << RCC_AHB3LPENCR_RNGLPENC_Pos)/*!< 0x00000001 */ #define RCC_AHB3LPENCR_RNGLPENC RCC_AHB3LPENCR_RNGLPENC_Msk /*!< RNG enable in Sleep mode */ #define RCC_AHB3LPENCR_HASHLPENC_Pos (1U) #define RCC_AHB3LPENCR_HASHLPENC_Msk (0x1UL << RCC_AHB3LPENCR_HASHLPENC_Pos) /*!< 0x00000002 */ #define RCC_AHB3LPENCR_HASHLPENC RCC_AHB3LPENCR_HASHLPENC_Msk /*!< HASH enable in Sleep mode */ #define RCC_AHB3LPENCR_CRYPLPENC_Pos (2U) #define RCC_AHB3LPENCR_CRYPLPENC_Msk (0x1UL << RCC_AHB3LPENCR_CRYPLPENC_Pos) /*!< 0x00000004 */ #define RCC_AHB3LPENCR_CRYPLPENC RCC_AHB3LPENCR_CRYPLPENC_Msk /*!< CRYP enable in Sleep mode */ #define RCC_AHB3LPENCR_SAESLPENC_Pos (4U) #define RCC_AHB3LPENCR_SAESLPENC_Msk (0x1UL << RCC_AHB3LPENCR_SAESLPENC_Pos) /*!< 0x00000010 */ #define RCC_AHB3LPENCR_SAESLPENC RCC_AHB3LPENCR_SAESLPENC_Msk /*!< SAES enable in Sleep mode */ #define RCC_AHB3LPENCR_PKALPENC_Pos (8U) #define RCC_AHB3LPENCR_PKALPENC_Msk (0x1UL << RCC_AHB3LPENCR_PKALPENC_Pos)/*!< 0x00000100 */ #define RCC_AHB3LPENCR_PKALPENC RCC_AHB3LPENCR_PKALPENC_Msk /*!< PKA enable in Sleep mode */ #define RCC_AHB3LPENCR_RIFSCLPENC_Pos (9U) #define RCC_AHB3LPENCR_RIFSCLPENC_Msk (0x1UL << RCC_AHB3LPENCR_RIFSCLPENC_Pos) /*!< 0x00000200 */ #define RCC_AHB3LPENCR_RIFSCLPENC RCC_AHB3LPENCR_RIFSCLPENC_Msk /*!< RIFSC enable in Sleep mode */ #define RCC_AHB3LPENCR_IACLPENC_Pos (10U) #define RCC_AHB3LPENCR_IACLPENC_Msk (0x1UL << RCC_AHB3LPENCR_IACLPENC_Pos)/*!< 0x00000400 */ #define RCC_AHB3LPENCR_IACLPENC RCC_AHB3LPENCR_IACLPENC_Msk /*!< IAC enable in Sleep mode */ #define RCC_AHB3LPENCR_RISAFLPENC_Pos (14U) #define RCC_AHB3LPENCR_RISAFLPENC_Msk (0x1UL << RCC_AHB3LPENCR_RISAFLPENC_Pos) /*!< 0x00004000 */ #define RCC_AHB3LPENCR_RISAFLPENC RCC_AHB3LPENCR_RISAFLPENC_Msk /*!< RISAF enable in Sleep mode */ /**************** Bit definition for RCC_AHB4LPENCR register ****************/ #define RCC_AHB4LPENCR_GPIOALPENC_Pos (0U) #define RCC_AHB4LPENCR_GPIOALPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOALPENC_Pos) /*!< 0x00000001 */ #define RCC_AHB4LPENCR_GPIOALPENC RCC_AHB4LPENCR_GPIOALPENC_Msk /*!< GPIO A enable in Sleep mode */ #define RCC_AHB4LPENCR_GPIOBLPENC_Pos (1U) #define RCC_AHB4LPENCR_GPIOBLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOBLPENC_Pos) /*!< 0x00000002 */ #define RCC_AHB4LPENCR_GPIOBLPENC RCC_AHB4LPENCR_GPIOBLPENC_Msk /*!< GPIO B enable in Sleep mode */ #define RCC_AHB4LPENCR_GPIOCLPENC_Pos (2U) #define RCC_AHB4LPENCR_GPIOCLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOCLPENC_Pos) /*!< 0x00000004 */ #define RCC_AHB4LPENCR_GPIOCLPENC RCC_AHB4LPENCR_GPIOCLPENC_Msk /*!< GPIO C enable in Sleep mode */ #define RCC_AHB4LPENCR_GPIODLPENC_Pos (3U) #define RCC_AHB4LPENCR_GPIODLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIODLPENC_Pos) /*!< 0x00000008 */ #define RCC_AHB4LPENCR_GPIODLPENC RCC_AHB4LPENCR_GPIODLPENC_Msk /*!< GPIO D enable in Sleep mode */ #define RCC_AHB4LPENCR_GPIOELPENC_Pos (4U) #define RCC_AHB4LPENCR_GPIOELPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOELPENC_Pos) /*!< 0x00000010 */ #define RCC_AHB4LPENCR_GPIOELPENC RCC_AHB4LPENCR_GPIOELPENC_Msk /*!< GPIO E enable in Sleep mode */ #define RCC_AHB4LPENCR_GPIOFLPENC_Pos (5U) #define RCC_AHB4LPENCR_GPIOFLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOFLPENC_Pos) /*!< 0x00000020 */ #define RCC_AHB4LPENCR_GPIOFLPENC RCC_AHB4LPENCR_GPIOFLPENC_Msk /*!< GPIO F enable in Sleep mode */ #define RCC_AHB4LPENCR_GPIOGLPENC_Pos (6U) #define RCC_AHB4LPENCR_GPIOGLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOGLPENC_Pos) /*!< 0x00000040 */ #define RCC_AHB4LPENCR_GPIOGLPENC RCC_AHB4LPENCR_GPIOGLPENC_Msk /*!< GPIO G enable in Sleep mode */ #define RCC_AHB4LPENCR_GPIOHLPENC_Pos (7U) #define RCC_AHB4LPENCR_GPIOHLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOHLPENC_Pos) /*!< 0x00000080 */ #define RCC_AHB4LPENCR_GPIOHLPENC RCC_AHB4LPENCR_GPIOHLPENC_Msk /*!< GPIO H enable in Sleep mode */ #define RCC_AHB4LPENCR_GPIONLPENC_Pos (13U) #define RCC_AHB4LPENCR_GPIONLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIONLPENC_Pos) /*!< 0x00002000 */ #define RCC_AHB4LPENCR_GPIONLPENC RCC_AHB4LPENCR_GPIONLPENC_Msk /*!< GPIO N enable in Sleep mode */ #define RCC_AHB4LPENCR_GPIOOLPENC_Pos (14U) #define RCC_AHB4LPENCR_GPIOOLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOOLPENC_Pos) /*!< 0x00004000 */ #define RCC_AHB4LPENCR_GPIOOLPENC RCC_AHB4LPENCR_GPIOOLPENC_Msk /*!< GPIO O enable in Sleep mode */ #define RCC_AHB4LPENCR_GPIOPLPENC_Pos (15U) #define RCC_AHB4LPENCR_GPIOPLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOPLPENC_Pos) /*!< 0x00008000 */ #define RCC_AHB4LPENCR_GPIOPLPENC RCC_AHB4LPENCR_GPIOPLPENC_Msk /*!< GPIO P enable in Sleep mode */ #define RCC_AHB4LPENCR_GPIOQLPENC_Pos (16U) #define RCC_AHB4LPENCR_GPIOQLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOQLPENC_Pos) /*!< 0x00010000 */ #define RCC_AHB4LPENCR_GPIOQLPENC RCC_AHB4LPENCR_GPIOQLPENC_Msk /*!< GPIO Q enable in Sleep mode */ #define RCC_AHB4LPENCR_PWRLPENC_Pos (18U) #define RCC_AHB4LPENCR_PWRLPENC_Msk (0x1UL << RCC_AHB4LPENCR_PWRLPENC_Pos)/*!< 0x00040000 */ #define RCC_AHB4LPENCR_PWRLPENC RCC_AHB4LPENCR_PWRLPENC_Msk /*!< PWR enable in Sleep mode */ #define RCC_AHB4LPENCR_CRCLPENC_Pos (19U) #define RCC_AHB4LPENCR_CRCLPENC_Msk (0x1UL << RCC_AHB4LPENCR_CRCLPENC_Pos)/*!< 0x00080000 */ #define RCC_AHB4LPENCR_CRCLPENC RCC_AHB4LPENCR_CRCLPENC_Msk /*!< CRC enable in Sleep mode */ /**************** Bit definition for RCC_AHB5LPENCR register ****************/ #define RCC_AHB5LPENCR_HPDMA1LPENC_Pos (0U) #define RCC_AHB5LPENCR_HPDMA1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_HPDMA1LPENC_Pos) /*!< 0x00000001 */ #define RCC_AHB5LPENCR_HPDMA1LPENC RCC_AHB5LPENCR_HPDMA1LPENC_Msk /*!< HPDMA1 enable in Sleep mode */ #define RCC_AHB5LPENCR_DMA2DLPENC_Pos (1U) #define RCC_AHB5LPENCR_DMA2DLPENC_Msk (0x1UL << RCC_AHB5LPENCR_DMA2DLPENC_Pos) /*!< 0x00000002 */ #define RCC_AHB5LPENCR_DMA2DLPENC RCC_AHB5LPENCR_DMA2DLPENC_Msk /*!< DMA2D enable in Sleep mode */ #define RCC_AHB5LPENCR_JPEGLPENC_Pos (3U) #define RCC_AHB5LPENCR_JPEGLPENC_Msk (0x1UL << RCC_AHB5LPENCR_JPEGLPENC_Pos) /*!< 0x00000008 */ #define RCC_AHB5LPENCR_JPEGLPENC RCC_AHB5LPENCR_JPEGLPENC_Msk /*!< JPEG enable in Sleep mode */ #define RCC_AHB5LPENCR_FMCLPENC_Pos (4U) #define RCC_AHB5LPENCR_FMCLPENC_Msk (0x1UL << RCC_AHB5LPENCR_FMCLPENC_Pos)/*!< 0x00000010 */ #define RCC_AHB5LPENCR_FMCLPENC RCC_AHB5LPENCR_FMCLPENC_Msk /*!< FMC enable in Sleep mode */ #define RCC_AHB5LPENCR_XSPI1LPENC_Pos (5U) #define RCC_AHB5LPENCR_XSPI1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_XSPI1LPENC_Pos) /*!< 0x00000020 */ #define RCC_AHB5LPENCR_XSPI1LPENC RCC_AHB5LPENCR_XSPI1LPENC_Msk /*!< XSPI1 enable in Sleep mode */ #define RCC_AHB5LPENCR_PSSILPENC_Pos (6U) #define RCC_AHB5LPENCR_PSSILPENC_Msk (0x1UL << RCC_AHB5LPENCR_PSSILPENC_Pos) /*!< 0x00000040 */ #define RCC_AHB5LPENCR_PSSILPENC RCC_AHB5LPENCR_PSSILPENC_Msk /*!< PSSI enable in Sleep mode */ #define RCC_AHB5LPENCR_SDMMC2LPENC_Pos (7U) #define RCC_AHB5LPENCR_SDMMC2LPENC_Msk (0x1UL << RCC_AHB5LPENCR_SDMMC2LPENC_Pos) /*!< 0x00000080 */ #define RCC_AHB5LPENCR_SDMMC2LPENC RCC_AHB5LPENCR_SDMMC2LPENC_Msk /*!< SDMMC2 enable in Sleep mode */ #define RCC_AHB5LPENCR_SDMMC1LPENC_Pos (8U) #define RCC_AHB5LPENCR_SDMMC1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_SDMMC1LPENC_Pos) /*!< 0x00000100 */ #define RCC_AHB5LPENCR_SDMMC1LPENC RCC_AHB5LPENCR_SDMMC1LPENC_Msk /*!< SDMMC1 enable in Sleep mode */ #define RCC_AHB5LPENCR_XSPI2LPENC_Pos (12U) #define RCC_AHB5LPENCR_XSPI2LPENC_Msk (0x1UL << RCC_AHB5LPENCR_XSPI2LPENC_Pos) /*!< 0x00001000 */ #define RCC_AHB5LPENCR_XSPI2LPENC RCC_AHB5LPENCR_XSPI2LPENC_Msk /*!< XSPI2 enable in Sleep mode */ #define RCC_AHB5LPENCR_XSPIMLPENC_Pos (13U) #define RCC_AHB5LPENCR_XSPIMLPENC_Msk (0x1UL << RCC_AHB5LPENCR_XSPIMLPENC_Pos) /*!< 0x00002000 */ #define RCC_AHB5LPENCR_XSPIMLPENC RCC_AHB5LPENCR_XSPIMLPENC_Msk /*!< XSPIM enable in Sleep mode */ #define RCC_AHB5LPENCR_MCE1LPENC_Pos (14U) #define RCC_AHB5LPENCR_MCE1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_MCE1LPENC_Pos) /*!< 0x00004000 */ #define RCC_AHB5LPENCR_MCE1LPENC RCC_AHB5LPENCR_MCE1LPENC_Msk /*!< MCE1 enable in Sleep mode */ #define RCC_AHB5LPENCR_MCE2LPENC_Pos (15U) #define RCC_AHB5LPENCR_MCE2LPENC_Msk (0x1UL << RCC_AHB5LPENCR_MCE2LPENC_Pos) /*!< 0x00008000 */ #define RCC_AHB5LPENCR_MCE2LPENC RCC_AHB5LPENCR_MCE2LPENC_Msk /*!< MCE2 enable in Sleep mode */ #define RCC_AHB5LPENCR_MCE3LPENC_Pos (16U) #define RCC_AHB5LPENCR_MCE3LPENC_Msk (0x1UL << RCC_AHB5LPENCR_MCE3LPENC_Pos) /*!< 0x00010000 */ #define RCC_AHB5LPENCR_MCE3LPENC RCC_AHB5LPENCR_MCE3LPENC_Msk /*!< MCE3 enable in Sleep mode */ #define RCC_AHB5LPENCR_XSPI3LPENC_Pos (17U) #define RCC_AHB5LPENCR_XSPI3LPENC_Msk (0x1UL << RCC_AHB5LPENCR_XSPI3LPENC_Pos) /*!< 0x00020000 */ #define RCC_AHB5LPENCR_XSPI3LPENC RCC_AHB5LPENCR_XSPI3LPENC_Msk /*!< XSPI3 enable in Sleep mode */ #define RCC_AHB5LPENCR_MCE4LPENC_Pos (18U) #define RCC_AHB5LPENCR_MCE4LPENC_Msk (0x1UL << RCC_AHB5LPENCR_MCE4LPENC_Pos) /*!< 0x00040000 */ #define RCC_AHB5LPENCR_MCE4LPENC RCC_AHB5LPENCR_MCE4LPENC_Msk /*!< MCE4 enable in Sleep mode */ #define RCC_AHB5LPENCR_GFXMMULPENC_Pos (19U) #define RCC_AHB5LPENCR_GFXMMULPENC_Msk (0x1UL << RCC_AHB5LPENCR_GFXMMULPENC_Pos) /*!< 0x00080000 */ #define RCC_AHB5LPENCR_GFXMMULPENC RCC_AHB5LPENCR_GFXMMULPENC_Msk /*!< GFXMMU enable in Sleep mode */ #define RCC_AHB5LPENCR_GPU2DLPENC_Pos (20U) #define RCC_AHB5LPENCR_GPU2DLPENC_Msk (0x1UL << RCC_AHB5LPENCR_GPU2DLPENC_Pos) /*!< 0x00100000 */ #define RCC_AHB5LPENCR_GPU2DLPENC RCC_AHB5LPENCR_GPU2DLPENC_Msk /*!< GPU2D enable in Sleep mode */ #define RCC_AHB5LPENCR_ETH1MACLPENC_Pos (22U) #define RCC_AHB5LPENCR_ETH1MACLPENC_Msk (0x1UL << RCC_AHB5LPENCR_ETH1MACLPENC_Pos) /*!< 0x00400000 */ #define RCC_AHB5LPENCR_ETH1MACLPENC RCC_AHB5LPENCR_ETH1MACLPENC_Msk /*!< ETH1MAC enable in Sleep mode */ #define RCC_AHB5LPENCR_ETH1TXLPENC_Pos (23U) #define RCC_AHB5LPENCR_ETH1TXLPENC_Msk (0x1UL << RCC_AHB5LPENCR_ETH1TXLPENC_Pos) /*!< 0x00800000 */ #define RCC_AHB5LPENCR_ETH1TXLPENC RCC_AHB5LPENCR_ETH1TXLPENC_Msk /*!< ETH1TX enable in Sleep mode */ #define RCC_AHB5LPENCR_ETH1RXLPENC_Pos (24U) #define RCC_AHB5LPENCR_ETH1RXLPENC_Msk (0x1UL << RCC_AHB5LPENCR_ETH1RXLPENC_Pos) /*!< 0x01000000 */ #define RCC_AHB5LPENCR_ETH1RXLPENC RCC_AHB5LPENCR_ETH1RXLPENC_Msk /*!< ETH1RX enable in Sleep mode */ #define RCC_AHB5LPENCR_ETH1LPENC_Pos (25U) #define RCC_AHB5LPENCR_ETH1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_ETH1LPENC_Pos) /*!< 0x02000000 */ #define RCC_AHB5LPENCR_ETH1LPENC RCC_AHB5LPENCR_ETH1LPENC_Msk /*!< ETH1 enable in Sleep mode */ #define RCC_AHB5LPENCR_OTG1LPENC_Pos (26U) #define RCC_AHB5LPENCR_OTG1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_OTG1LPENC_Pos) /*!< 0x04000000 */ #define RCC_AHB5LPENCR_OTG1LPENC RCC_AHB5LPENCR_OTG1LPENC_Msk /*!< OTG1 enable in Sleep mode */ #define RCC_AHB5LPENCR_OTGPHY1LPENC_Pos (27U) #define RCC_AHB5LPENCR_OTGPHY1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_OTGPHY1LPENC_Pos) /*!< 0x08000000 */ #define RCC_AHB5LPENCR_OTGPHY1LPENC RCC_AHB5LPENCR_OTGPHY1LPENC_Msk /*!< OTGPHY1 enable in Sleep mode */ #define RCC_AHB5LPENCR_OTGPHY2LPENC_Pos (28U) #define RCC_AHB5LPENCR_OTGPHY2LPENC_Msk (0x1UL << RCC_AHB5LPENCR_OTGPHY2LPENC_Pos) /*!< 0x10000000 */ #define RCC_AHB5LPENCR_OTGPHY2LPENC RCC_AHB5LPENCR_OTGPHY2LPENC_Msk /*!< OTGPHY2 enable in Sleep mode */ #define RCC_AHB5LPENCR_OTG2LPENC_Pos (29U) #define RCC_AHB5LPENCR_OTG2LPENC_Msk (0x1UL << RCC_AHB5LPENCR_OTG2LPENC_Pos) /*!< 0x20000000 */ #define RCC_AHB5LPENCR_OTG2LPENC RCC_AHB5LPENCR_OTG2LPENC_Msk /*!< OTG2 enable in Sleep mode */ #define RCC_AHB5LPENCR_CACHEAXILPENC_Pos (30U) #define RCC_AHB5LPENCR_CACHEAXILPENC_Msk (0x1UL << RCC_AHB5LPENCR_CACHEAXILPENC_Pos) /*!< 0x40000000 */ #define RCC_AHB5LPENCR_CACHEAXILPENC RCC_AHB5LPENCR_CACHEAXILPENC_Msk /*!< CACHEAXI enable in Sleep mode */ #define RCC_AHB5LPENCR_NPULPENC_Pos (31U) #define RCC_AHB5LPENCR_NPULPENC_Msk (0x1UL << RCC_AHB5LPENCR_NPULPENC_Pos)/*!< 0x80000000 */ #define RCC_AHB5LPENCR_NPULPENC RCC_AHB5LPENCR_NPULPENC_Msk /*!< NPU enable in Sleep mode */ /*************** Bit definition for RCC_APB1LPENCR1 register ****************/ #define RCC_APB1LPENCR1_TIM2LPENC_Pos (0U) #define RCC_APB1LPENCR1_TIM2LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM2LPENC_Pos) /*!< 0x00000001 */ #define RCC_APB1LPENCR1_TIM2LPENC RCC_APB1LPENCR1_TIM2LPENC_Msk /*!< TIM2 enable */ #define RCC_APB1LPENCR1_TIM3LPENC_Pos (1U) #define RCC_APB1LPENCR1_TIM3LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM3LPENC_Pos) /*!< 0x00000002 */ #define RCC_APB1LPENCR1_TIM3LPENC RCC_APB1LPENCR1_TIM3LPENC_Msk /*!< TIM3 enable */ #define RCC_APB1LPENCR1_TIM4LPENC_Pos (2U) #define RCC_APB1LPENCR1_TIM4LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM4LPENC_Pos) /*!< 0x00000004 */ #define RCC_APB1LPENCR1_TIM4LPENC RCC_APB1LPENCR1_TIM4LPENC_Msk /*!< TIM4 enable */ #define RCC_APB1LPENCR1_TIM5LPENC_Pos (3U) #define RCC_APB1LPENCR1_TIM5LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM5LPENC_Pos) /*!< 0x00000008 */ #define RCC_APB1LPENCR1_TIM5LPENC RCC_APB1LPENCR1_TIM5LPENC_Msk /*!< TIM5 enable */ #define RCC_APB1LPENCR1_TIM6LPENC_Pos (4U) #define RCC_APB1LPENCR1_TIM6LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM6LPENC_Pos) /*!< 0x00000010 */ #define RCC_APB1LPENCR1_TIM6LPENC RCC_APB1LPENCR1_TIM6LPENC_Msk /*!< TIM6 enable */ #define RCC_APB1LPENCR1_TIM7LPENC_Pos (5U) #define RCC_APB1LPENCR1_TIM7LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM7LPENC_Pos) /*!< 0x00000020 */ #define RCC_APB1LPENCR1_TIM7LPENC RCC_APB1LPENCR1_TIM7LPENC_Msk /*!< TIM7 enable */ #define RCC_APB1LPENCR1_TIM12LPENC_Pos (6U) #define RCC_APB1LPENCR1_TIM12LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM12LPENC_Pos) /*!< 0x00000040 */ #define RCC_APB1LPENCR1_TIM12LPENC RCC_APB1LPENCR1_TIM12LPENC_Msk /*!< TIM12 enable */ #define RCC_APB1LPENCR1_TIM13LPENC_Pos (7U) #define RCC_APB1LPENCR1_TIM13LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM13LPENC_Pos) /*!< 0x00000080 */ #define RCC_APB1LPENCR1_TIM13LPENC RCC_APB1LPENCR1_TIM13LPENC_Msk /*!< TIM13 enable */ #define RCC_APB1LPENCR1_TIM14LPENC_Pos (8U) #define RCC_APB1LPENCR1_TIM14LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM14LPENC_Pos) /*!< 0x00000100 */ #define RCC_APB1LPENCR1_TIM14LPENC RCC_APB1LPENCR1_TIM14LPENC_Msk /*!< TIM14 enable */ #define RCC_APB1LPENCR1_LPTIM1LPENC_Pos (9U) #define RCC_APB1LPENCR1_LPTIM1LPENC_Msk (0x1UL << RCC_APB1LPENCR1_LPTIM1LPENC_Pos) /*!< 0x00000200 */ #define RCC_APB1LPENCR1_LPTIM1LPENC RCC_APB1LPENCR1_LPTIM1LPENC_Msk /*!< LPTIM1 enable */ #define RCC_APB1LPENCR1_WWDGLPENC_Pos (11U) #define RCC_APB1LPENCR1_WWDGLPENC_Msk (0x1UL << RCC_APB1LPENCR1_WWDGLPENC_Pos) /*!< 0x00000800 */ #define RCC_APB1LPENCR1_WWDGLPENC RCC_APB1LPENCR1_WWDGLPENC_Msk /*!< WWDG enable */ #define RCC_APB1LPENCR1_TIM10LPENC_Pos (12U) #define RCC_APB1LPENCR1_TIM10LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM10LPENC_Pos) /*!< 0x00001000 */ #define RCC_APB1LPENCR1_TIM10LPENC RCC_APB1LPENCR1_TIM10LPENC_Msk /*!< TIM10 enable */ #define RCC_APB1LPENCR1_TIM11LPENC_Pos (13U) #define RCC_APB1LPENCR1_TIM11LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM11LPENC_Pos) /*!< 0x00002000 */ #define RCC_APB1LPENCR1_TIM11LPENC RCC_APB1LPENCR1_TIM11LPENC_Msk /*!< TIM11 enable */ #define RCC_APB1LPENCR1_SPI2LPENC_Pos (14U) #define RCC_APB1LPENCR1_SPI2LPENC_Msk (0x1UL << RCC_APB1LPENCR1_SPI2LPENC_Pos) /*!< 0x00004000 */ #define RCC_APB1LPENCR1_SPI2LPENC RCC_APB1LPENCR1_SPI2LPENC_Msk /*!< SPI2 enable */ #define RCC_APB1LPENCR1_SPI3LPENC_Pos (15U) #define RCC_APB1LPENCR1_SPI3LPENC_Msk (0x1UL << RCC_APB1LPENCR1_SPI3LPENC_Pos) /*!< 0x00008000 */ #define RCC_APB1LPENCR1_SPI3LPENC RCC_APB1LPENCR1_SPI3LPENC_Msk /*!< SPI3 enable */ #define RCC_APB1LPENCR1_SPDIFRX1LPENC_Pos (16U) #define RCC_APB1LPENCR1_SPDIFRX1LPENC_Msk (0x1UL << RCC_APB1LPENCR1_SPDIFRX1LPENC_Pos) /*!< 0x00010000 */ #define RCC_APB1LPENCR1_SPDIFRX1LPENC RCC_APB1LPENCR1_SPDIFRX1LPENC_Msk /*!< SPDIFRX1 enable */ #define RCC_APB1LPENCR1_USART2LPENC_Pos (17U) #define RCC_APB1LPENCR1_USART2LPENC_Msk (0x1UL << RCC_APB1LPENCR1_USART2LPENC_Pos) /*!< 0x00020000 */ #define RCC_APB1LPENCR1_USART2LPENC RCC_APB1LPENCR1_USART2LPENC_Msk /*!< USART2 enable */ #define RCC_APB1LPENCR1_USART3LPENC_Pos (18U) #define RCC_APB1LPENCR1_USART3LPENC_Msk (0x1UL << RCC_APB1LPENCR1_USART3LPENC_Pos) /*!< 0x00040000 */ #define RCC_APB1LPENCR1_USART3LPENC RCC_APB1LPENCR1_USART3LPENC_Msk /*!< USART3 enable */ #define RCC_APB1LPENCR1_UART4LPENC_Pos (19U) #define RCC_APB1LPENCR1_UART4LPENC_Msk (0x1UL << RCC_APB1LPENCR1_UART4LPENC_Pos) /*!< 0x00080000 */ #define RCC_APB1LPENCR1_UART4LPENC RCC_APB1LPENCR1_UART4LPENC_Msk /*!< UART4 enable */ #define RCC_APB1LPENCR1_UART5LPENC_Pos (20U) #define RCC_APB1LPENCR1_UART5LPENC_Msk (0x1UL << RCC_APB1LPENCR1_UART5LPENC_Pos) /*!< 0x00100000 */ #define RCC_APB1LPENCR1_UART5LPENC RCC_APB1LPENCR1_UART5LPENC_Msk /*!< UART5 enable */ #define RCC_APB1LPENCR1_I2C1LPENC_Pos (21U) #define RCC_APB1LPENCR1_I2C1LPENC_Msk (0x1UL << RCC_APB1LPENCR1_I2C1LPENC_Pos) /*!< 0x00200000 */ #define RCC_APB1LPENCR1_I2C1LPENC RCC_APB1LPENCR1_I2C1LPENC_Msk /*!< I2C1 enable */ #define RCC_APB1LPENCR1_I2C2LPENC_Pos (22U) #define RCC_APB1LPENCR1_I2C2LPENC_Msk (0x1UL << RCC_APB1LPENCR1_I2C2LPENC_Pos) /*!< 0x00400000 */ #define RCC_APB1LPENCR1_I2C2LPENC RCC_APB1LPENCR1_I2C2LPENC_Msk /*!< I2C2 enable */ #define RCC_APB1LPENCR1_I2C3LPENC_Pos (23U) #define RCC_APB1LPENCR1_I2C3LPENC_Msk (0x1UL << RCC_APB1LPENCR1_I2C3LPENC_Pos) /*!< 0x00800000 */ #define RCC_APB1LPENCR1_I2C3LPENC RCC_APB1LPENCR1_I2C3LPENC_Msk /*!< I2C3 enable */ #define RCC_APB1LPENCR1_I3C1LPENC_Pos (24U) #define RCC_APB1LPENCR1_I3C1LPENC_Msk (0x1UL << RCC_APB1LPENCR1_I3C1LPENC_Pos) /*!< 0x01000000 */ #define RCC_APB1LPENCR1_I3C1LPENC RCC_APB1LPENCR1_I3C1LPENC_Msk /*!< I3C1 enable */ #define RCC_APB1LPENCR1_I3C2LPENC_Pos (25U) #define RCC_APB1LPENCR1_I3C2LPENC_Msk (0x1UL << RCC_APB1LPENCR1_I3C2LPENC_Pos) /*!< 0x02000000 */ #define RCC_APB1LPENCR1_I3C2LPENC RCC_APB1LPENCR1_I3C2LPENC_Msk /*!< I3C2 enable */ #define RCC_APB1LPENCR1_UART7LPENC_Pos (30U) #define RCC_APB1LPENCR1_UART7LPENC_Msk (0x1UL << RCC_APB1LPENCR1_UART7LPENC_Pos) /*!< 0x40000000 */ #define RCC_APB1LPENCR1_UART7LPENC RCC_APB1LPENCR1_UART7LPENC_Msk /*!< UART7 enable */ #define RCC_APB1LPENCR1_UART8LPENC_Pos (31U) #define RCC_APB1LPENCR1_UART8LPENC_Msk (0x1UL << RCC_APB1LPENCR1_UART8LPENC_Pos) /*!< 0x80000000 */ #define RCC_APB1LPENCR1_UART8LPENC RCC_APB1LPENCR1_UART8LPENC_Msk /*!< UART8 enable */ /*************** Bit definition for RCC_APB1LPENCR2 register ****************/ #define RCC_APB1LPENCR2_MDIOSLPENC_Pos (5U) #define RCC_APB1LPENCR2_MDIOSLPENC_Msk (0x1UL << RCC_APB1LPENCR2_MDIOSLPENC_Pos) /*!< 0x00000020 */ #define RCC_APB1LPENCR2_MDIOSLPENC RCC_APB1LPENCR2_MDIOSLPENC_Msk /*!< MDIOS enable */ #define RCC_APB1LPENCR2_FDCANLPENC_Pos (8U) #define RCC_APB1LPENCR2_FDCANLPENC_Msk (0x1UL << RCC_APB1LPENCR2_FDCANLPENC_Pos) /*!< 0x00000100 */ #define RCC_APB1LPENCR2_FDCANLPENC RCC_APB1LPENCR2_FDCANLPENC_Msk /*!< FDCAN enable */ #define RCC_APB1LPENCR2_UCPD1LPENC_Pos (18U) #define RCC_APB1LPENCR2_UCPD1LPENC_Msk (0x1UL << RCC_APB1LPENCR2_UCPD1LPENC_Pos) /*!< 0x00040000 */ #define RCC_APB1LPENCR2_UCPD1LPENC RCC_APB1LPENCR2_UCPD1LPENC_Msk /*!< UCPD1 enable */ /**************** Bit definition for RCC_APB2LPENCR register ****************/ #define RCC_APB2LPENCR_TIM1LPENC_Pos (0U) #define RCC_APB2LPENCR_TIM1LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM1LPENC_Pos) /*!< 0x00000001 */ #define RCC_APB2LPENCR_TIM1LPENC RCC_APB2LPENCR_TIM1LPENC_Msk /*!< TIM1 enable */ #define RCC_APB2LPENCR_TIM8LPENC_Pos (1U) #define RCC_APB2LPENCR_TIM8LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM8LPENC_Pos) /*!< 0x00000002 */ #define RCC_APB2LPENCR_TIM8LPENC RCC_APB2LPENCR_TIM8LPENC_Msk /*!< TIM8 enable */ #define RCC_APB2LPENCR_USART1LPENC_Pos (4U) #define RCC_APB2LPENCR_USART1LPENC_Msk (0x1UL << RCC_APB2LPENCR_USART1LPENC_Pos) /*!< 0x00000010 */ #define RCC_APB2LPENCR_USART1LPENC RCC_APB2LPENCR_USART1LPENC_Msk /*!< USART1 enable */ #define RCC_APB2LPENCR_USART6LPENC_Pos (5U) #define RCC_APB2LPENCR_USART6LPENC_Msk (0x1UL << RCC_APB2LPENCR_USART6LPENC_Pos) /*!< 0x00000020 */ #define RCC_APB2LPENCR_USART6LPENC RCC_APB2LPENCR_USART6LPENC_Msk /*!< USART6 enable */ #define RCC_APB2LPENCR_UART9LPENC_Pos (6U) #define RCC_APB2LPENCR_UART9LPENC_Msk (0x1UL << RCC_APB2LPENCR_UART9LPENC_Pos) /*!< 0x00000040 */ #define RCC_APB2LPENCR_UART9LPENC RCC_APB2LPENCR_UART9LPENC_Msk /*!< UART9 enable */ #define RCC_APB2LPENCR_USART10LPENC_Pos (7U) #define RCC_APB2LPENCR_USART10LPENC_Msk (0x1UL << RCC_APB2LPENCR_USART10LPENC_Pos) /*!< 0x00000080 */ #define RCC_APB2LPENCR_USART10LPENC RCC_APB2LPENCR_USART10LPENC_Msk /*!< USART10 enable */ #define RCC_APB2LPENCR_SPI1LPENC_Pos (12U) #define RCC_APB2LPENCR_SPI1LPENC_Msk (0x1UL << RCC_APB2LPENCR_SPI1LPENC_Pos) /*!< 0x00001000 */ #define RCC_APB2LPENCR_SPI1LPENC RCC_APB2LPENCR_SPI1LPENC_Msk /*!< SPI1 enable */ #define RCC_APB2LPENCR_SPI4LPENC_Pos (13U) #define RCC_APB2LPENCR_SPI4LPENC_Msk (0x1UL << RCC_APB2LPENCR_SPI4LPENC_Pos) /*!< 0x00002000 */ #define RCC_APB2LPENCR_SPI4LPENC RCC_APB2LPENCR_SPI4LPENC_Msk /*!< SPI4 enable */ #define RCC_APB2LPENCR_TIM18LPENC_Pos (15U) #define RCC_APB2LPENCR_TIM18LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM18LPENC_Pos) /*!< 0x00008000 */ #define RCC_APB2LPENCR_TIM18LPENC RCC_APB2LPENCR_TIM18LPENC_Msk /*!< TIM18 enable */ #define RCC_APB2LPENCR_TIM15LPENC_Pos (16U) #define RCC_APB2LPENCR_TIM15LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM15LPENC_Pos) /*!< 0x00010000 */ #define RCC_APB2LPENCR_TIM15LPENC RCC_APB2LPENCR_TIM15LPENC_Msk /*!< TIM15 enable */ #define RCC_APB2LPENCR_TIM16LPENC_Pos (17U) #define RCC_APB2LPENCR_TIM16LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM16LPENC_Pos) /*!< 0x00020000 */ #define RCC_APB2LPENCR_TIM16LPENC RCC_APB2LPENCR_TIM16LPENC_Msk /*!< TIM16 enable */ #define RCC_APB2LPENCR_TIM17LPENC_Pos (18U) #define RCC_APB2LPENCR_TIM17LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM17LPENC_Pos) /*!< 0x00040000 */ #define RCC_APB2LPENCR_TIM17LPENC RCC_APB2LPENCR_TIM17LPENC_Msk /*!< TIM17 enable */ #define RCC_APB2LPENCR_TIM9LPENC_Pos (19U) #define RCC_APB2LPENCR_TIM9LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM9LPENC_Pos) /*!< 0x00080000 */ #define RCC_APB2LPENCR_TIM9LPENC RCC_APB2LPENCR_TIM9LPENC_Msk /*!< TIM9 enable */ #define RCC_APB2LPENCR_SPI5LPENC_Pos (20U) #define RCC_APB2LPENCR_SPI5LPENC_Msk (0x1UL << RCC_APB2LPENCR_SPI5LPENC_Pos) /*!< 0x00100000 */ #define RCC_APB2LPENCR_SPI5LPENC RCC_APB2LPENCR_SPI5LPENC_Msk /*!< SPI5 enable */ #define RCC_APB2LPENCR_SAI1LPENC_Pos (21U) #define RCC_APB2LPENCR_SAI1LPENC_Msk (0x1UL << RCC_APB2LPENCR_SAI1LPENC_Pos) /*!< 0x00200000 */ #define RCC_APB2LPENCR_SAI1LPENC RCC_APB2LPENCR_SAI1LPENC_Msk /*!< SAI1 enable */ #define RCC_APB2LPENCR_SAI2LPENC_Pos (22U) #define RCC_APB2LPENCR_SAI2LPENC_Msk (0x1UL << RCC_APB2LPENCR_SAI2LPENC_Pos) /*!< 0x00400000 */ #define RCC_APB2LPENCR_SAI2LPENC RCC_APB2LPENCR_SAI2LPENC_Msk /*!< SAI2 enable */ /**************** Bit definition for RCC_APB3LPENCR register ****************/ #define RCC_APB3LPENCR_DFTLPENC_Pos (2U) #define RCC_APB3LPENCR_DFTLPENC_Msk (0x1UL << RCC_APB3LPENCR_DFTLPENC_Pos)/*!< 0x00000004 */ #define RCC_APB3LPENCR_DFTLPENC RCC_APB3LPENCR_DFTLPENC_Msk /*!< DFT enable */ /*************** Bit definition for RCC_APB4LPENCR1 register ****************/ #define RCC_APB4LPENCR1_HDPLPENC_Pos (2U) #define RCC_APB4LPENCR1_HDPLPENC_Msk (0x1UL << RCC_APB4LPENCR1_HDPLPENC_Pos) /*!< 0x00000004 */ #define RCC_APB4LPENCR1_HDPLPENC RCC_APB4LPENCR1_HDPLPENC_Msk /*!< HDP enable */ #define RCC_APB4LPENCR1_LPUART1LPENC_Pos (3U) #define RCC_APB4LPENCR1_LPUART1LPENC_Msk (0x1UL << RCC_APB4LPENCR1_LPUART1LPENC_Pos) /*!< 0x00000008 */ #define RCC_APB4LPENCR1_LPUART1LPENC RCC_APB4LPENCR1_LPUART1LPENC_Msk /*!< LPUART1 enable */ #define RCC_APB4LPENCR1_SPI6LPENC_Pos (5U) #define RCC_APB4LPENCR1_SPI6LPENC_Msk (0x1UL << RCC_APB4LPENCR1_SPI6LPENC_Pos) /*!< 0x00000020 */ #define RCC_APB4LPENCR1_SPI6LPENC RCC_APB4LPENCR1_SPI6LPENC_Msk /*!< SPI6 enable */ #define RCC_APB4LPENCR1_I2C4LPENC_Pos (7U) #define RCC_APB4LPENCR1_I2C4LPENC_Msk (0x1UL << RCC_APB4LPENCR1_I2C4LPENC_Pos) /*!< 0x00000080 */ #define RCC_APB4LPENCR1_I2C4LPENC RCC_APB4LPENCR1_I2C4LPENC_Msk /*!< I2C4 enable */ #define RCC_APB4LPENCR1_LPTIM2LPENC_Pos (9U) #define RCC_APB4LPENCR1_LPTIM2LPENC_Msk (0x1UL << RCC_APB4LPENCR1_LPTIM2LPENC_Pos) /*!< 0x00000200 */ #define RCC_APB4LPENCR1_LPTIM2LPENC RCC_APB4LPENCR1_LPTIM2LPENC_Msk /*!< LPTIM2 enable */ #define RCC_APB4LPENCR1_LPTIM3LPENC_Pos (10U) #define RCC_APB4LPENCR1_LPTIM3LPENC_Msk (0x1UL << RCC_APB4LPENCR1_LPTIM3LPENC_Pos) /*!< 0x00000400 */ #define RCC_APB4LPENCR1_LPTIM3LPENC RCC_APB4LPENCR1_LPTIM3LPENC_Msk /*!< LPTIM3 enable */ #define RCC_APB4LPENCR1_LPTIM4LPENC_Pos (11U) #define RCC_APB4LPENCR1_LPTIM4LPENC_Msk (0x1UL << RCC_APB4LPENCR1_LPTIM4LPENC_Pos) /*!< 0x00000800 */ #define RCC_APB4LPENCR1_LPTIM4LPENC RCC_APB4LPENCR1_LPTIM4LPENC_Msk /*!< LPTIM4 enable */ #define RCC_APB4LPENCR1_LPTIM5LPENC_Pos (12U) #define RCC_APB4LPENCR1_LPTIM5LPENC_Msk (0x1UL << RCC_APB4LPENCR1_LPTIM5LPENC_Pos) /*!< 0x00001000 */ #define RCC_APB4LPENCR1_LPTIM5LPENC RCC_APB4LPENCR1_LPTIM5LPENC_Msk /*!< LPTIM5 enable */ #define RCC_APB4LPENCR1_VREFBUFLPENC_Pos (15U) #define RCC_APB4LPENCR1_VREFBUFLPENC_Msk (0x1UL << RCC_APB4LPENCR1_VREFBUFLPENC_Pos) /*!< 0x00008000 */ #define RCC_APB4LPENCR1_VREFBUFLPENC RCC_APB4LPENCR1_VREFBUFLPENC_Msk /*!< VREFBUF enable */ #define RCC_APB4LPENCR1_RTCLPENC_Pos (16U) #define RCC_APB4LPENCR1_RTCLPENC_Msk (0x1UL << RCC_APB4LPENCR1_RTCLPENC_Pos) /*!< 0x00010000 */ #define RCC_APB4LPENCR1_RTCLPENC RCC_APB4LPENCR1_RTCLPENC_Msk /*!< RTC enable */ #define RCC_APB4LPENCR1_RTCAPBLPENC_Pos (17U) #define RCC_APB4LPENCR1_RTCAPBLPENC_Msk (0x1UL << RCC_APB4LPENCR1_RTCAPBLPENC_Pos) /*!< 0x00020000 */ #define RCC_APB4LPENCR1_RTCAPBLPENC RCC_APB4LPENCR1_RTCAPBLPENC_Msk /*!< RTCAPB enable */ /*************** Bit definition for RCC_APB4LPENCR2 register ****************/ #define RCC_APB4LPENCR2_SYSCFGLPENC_Pos (0U) #define RCC_APB4LPENCR2_SYSCFGLPENC_Msk (0x1UL << RCC_APB4LPENCR2_SYSCFGLPENC_Pos) /*!< 0x00000001 */ #define RCC_APB4LPENCR2_SYSCFGLPENC RCC_APB4LPENCR2_SYSCFGLPENC_Msk /*!< SYSCFG enable */ #define RCC_APB4LPENCR2_BSECLPENC_Pos (1U) #define RCC_APB4LPENCR2_BSECLPENC_Msk (0x1UL << RCC_APB4LPENCR2_BSECLPENC_Pos) /*!< 0x00000002 */ #define RCC_APB4LPENCR2_BSECLPENC RCC_APB4LPENCR2_BSECLPENC_Msk /*!< BSEC enable */ #define RCC_APB4LPENCR2_DTSLPENC_Pos (2U) #define RCC_APB4LPENCR2_DTSLPENC_Msk (0x1UL << RCC_APB4LPENCR2_DTSLPENC_Pos) /*!< 0x00000004 */ #define RCC_APB4LPENCR2_DTSLPENC RCC_APB4LPENCR2_DTSLPENC_Msk /*!< DTS enable */ /**************** Bit definition for RCC_APB5LPENCR register ****************/ #define RCC_APB5LPENCR_LTDCLPENC_Pos (1U) #define RCC_APB5LPENCR_LTDCLPENC_Msk (0x1UL << RCC_APB5LPENCR_LTDCLPENC_Pos) /*!< 0x00000002 */ #define RCC_APB5LPENCR_LTDCLPENC RCC_APB5LPENCR_LTDCLPENC_Msk /*!< LTDC sleep enable */ #define RCC_APB5LPENCR_DCMIPPLPENC_Pos (2U) #define RCC_APB5LPENCR_DCMIPPLPENC_Msk (0x1UL << RCC_APB5LPENCR_DCMIPPLPENC_Pos) /*!< 0x00000004 */ #define RCC_APB5LPENCR_DCMIPPLPENC RCC_APB5LPENCR_DCMIPPLPENC_Msk /*!< DCMIPP sleep enable */ #define RCC_APB5LPENCR_GFXTIMLPENC_Pos (4U) #define RCC_APB5LPENCR_GFXTIMLPENC_Msk (0x1UL << RCC_APB5LPENCR_GFXTIMLPENC_Pos) /*!< 0x00000010 */ #define RCC_APB5LPENCR_GFXTIMLPENC RCC_APB5LPENCR_GFXTIMLPENC_Msk /*!< GFXTIM sleep enable */ #define RCC_APB5LPENCR_VENCLPENC_Pos (5U) #define RCC_APB5LPENCR_VENCLPENC_Msk (0x1UL << RCC_APB5LPENCR_VENCLPENC_Pos) /*!< 0x00000020 */ #define RCC_APB5LPENCR_VENCLPENC RCC_APB5LPENCR_VENCLPENC_Msk /*!< VENC sleep enable */ #define RCC_APB5LPENCR_CSILPENC_Pos (6U) #define RCC_APB5LPENCR_CSILPENC_Msk (0x1UL << RCC_APB5LPENCR_CSILPENC_Pos)/*!< 0x00000040 */ #define RCC_APB5LPENCR_CSILPENC RCC_APB5LPENCR_CSILPENC_Msk /*!< CSI sleep enable */ /**************** Bit definition for RCC_PRIVCFGCR0 register ****************/ #define RCC_PRIVCFGCR0_LSIPRIVC_Pos (0U) #define RCC_PRIVCFGCR0_LSIPRIVC_Msk (0x1UL << RCC_PRIVCFGCR0_LSIPRIVC_Pos)/*!< 0x00000001 */ #define RCC_PRIVCFGCR0_LSIPRIVC RCC_PRIVCFGCR0_LSIPRIVC_Msk /*!< Privileged protection of LSI configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGCR0_LSEPRIVC_Pos (1U) #define RCC_PRIVCFGCR0_LSEPRIVC_Msk (0x1UL << RCC_PRIVCFGCR0_LSEPRIVC_Pos)/*!< 0x00000002 */ #define RCC_PRIVCFGCR0_LSEPRIVC RCC_PRIVCFGCR0_LSEPRIVC_Msk /*!< Privileged protection of LSE configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGCR0_MSIPRIVC_Pos (2U) #define RCC_PRIVCFGCR0_MSIPRIVC_Msk (0x1UL << RCC_PRIVCFGCR0_MSIPRIVC_Pos)/*!< 0x00000004 */ #define RCC_PRIVCFGCR0_MSIPRIVC RCC_PRIVCFGCR0_MSIPRIVC_Msk /*!< Privileged protection of MSI configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGCR0_HSIPRIVC_Pos (3U) #define RCC_PRIVCFGCR0_HSIPRIVC_Msk (0x1UL << RCC_PRIVCFGCR0_HSIPRIVC_Pos)/*!< 0x00000008 */ #define RCC_PRIVCFGCR0_HSIPRIVC RCC_PRIVCFGCR0_HSIPRIVC_Msk /*!< Privileged protection of HSI configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGCR0_HSEPRIVC_Pos (4U) #define RCC_PRIVCFGCR0_HSEPRIVC_Msk (0x1UL << RCC_PRIVCFGCR0_HSEPRIVC_Pos)/*!< 0x00000010 */ #define RCC_PRIVCFGCR0_HSEPRIVC RCC_PRIVCFGCR0_HSEPRIVC_Msk /*!< Privileged protection of HSE configuration bits (enable, ready, divider) */ /**************** Bit definition for RCC_PUBCFGCR0 register *****************/ #define RCC_PUBCFGCR0_LSIPUBC_Pos (0U) #define RCC_PUBCFGCR0_LSIPUBC_Msk (0x1UL << RCC_PUBCFGCR0_LSIPUBC_Pos) /*!< 0x00000001 */ #define RCC_PUBCFGCR0_LSIPUBC RCC_PUBCFGCR0_LSIPUBC_Msk /*!< Public protection of LSI configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR0_LSEPUBC_Pos (1U) #define RCC_PUBCFGCR0_LSEPUBC_Msk (0x1UL << RCC_PUBCFGCR0_LSEPUBC_Pos) /*!< 0x00000002 */ #define RCC_PUBCFGCR0_LSEPUBC RCC_PUBCFGCR0_LSEPUBC_Msk /*!< Public protection of LSE configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR0_MSIPUBC_Pos (2U) #define RCC_PUBCFGCR0_MSIPUBC_Msk (0x1UL << RCC_PUBCFGCR0_MSIPUBC_Pos) /*!< 0x00000004 */ #define RCC_PUBCFGCR0_MSIPUBC RCC_PUBCFGCR0_MSIPUBC_Msk /*!< Public protection of MSI configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR0_HSIPUBC_Pos (3U) #define RCC_PUBCFGCR0_HSIPUBC_Msk (0x1UL << RCC_PUBCFGCR0_HSIPUBC_Pos) /*!< 0x00000008 */ #define RCC_PUBCFGCR0_HSIPUBC RCC_PUBCFGCR0_HSIPUBC_Msk /*!< Public protection of HSI configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR0_HSEPUBC_Pos (4U) #define RCC_PUBCFGCR0_HSEPUBC_Msk (0x1UL << RCC_PUBCFGCR0_HSEPUBC_Pos) /*!< 0x00000010 */ #define RCC_PUBCFGCR0_HSEPUBC RCC_PUBCFGCR0_HSEPUBC_Msk /*!< Public protection of HSE configuration bits (enable, ready, divider) */ /**************** Bit definition for RCC_PRIVCFGCR1 register ****************/ #define RCC_PRIVCFGCR1_PLL1PRIVC_Pos (0U) #define RCC_PRIVCFGCR1_PLL1PRIVC_Msk (0x1UL << RCC_PRIVCFGCR1_PLL1PRIVC_Pos) /*!< 0x00000001 */ #define RCC_PRIVCFGCR1_PLL1PRIVC RCC_PRIVCFGCR1_PLL1PRIVC_Msk /*!< Privileged protection of PLL1 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGCR1_PLL2PRIVC_Pos (1U) #define RCC_PRIVCFGCR1_PLL2PRIVC_Msk (0x1UL << RCC_PRIVCFGCR1_PLL2PRIVC_Pos) /*!< 0x00000002 */ #define RCC_PRIVCFGCR1_PLL2PRIVC RCC_PRIVCFGCR1_PLL2PRIVC_Msk /*!< Privileged protection of PLL2 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGCR1_PLL3PRIVC_Pos (2U) #define RCC_PRIVCFGCR1_PLL3PRIVC_Msk (0x1UL << RCC_PRIVCFGCR1_PLL3PRIVC_Pos) /*!< 0x00000004 */ #define RCC_PRIVCFGCR1_PLL3PRIVC RCC_PRIVCFGCR1_PLL3PRIVC_Msk /*!< Privileged protection of PLL3 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGCR1_PLL4PRIVC_Pos (3U) #define RCC_PRIVCFGCR1_PLL4PRIVC_Msk (0x1UL << RCC_PRIVCFGCR1_PLL4PRIVC_Pos) /*!< 0x00000008 */ #define RCC_PRIVCFGCR1_PLL4PRIVC RCC_PRIVCFGCR1_PLL4PRIVC_Msk /*!< Privileged protection of PLL4 configuration bits (enable, ready, divider) */ /**************** Bit definition for RCC_PUBCFGCR1 register *****************/ #define RCC_PUBCFGCR1_PLL1PUBC_Pos (0U) #define RCC_PUBCFGCR1_PLL1PUBC_Msk (0x1UL << RCC_PUBCFGCR1_PLL1PUBC_Pos) /*!< 0x00000001 */ #define RCC_PUBCFGCR1_PLL1PUBC RCC_PUBCFGCR1_PLL1PUBC_Msk /*!< Public protection of th PLL1 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR1_PLL2PUBC_Pos (1U) #define RCC_PUBCFGCR1_PLL2PUBC_Msk (0x1UL << RCC_PUBCFGCR1_PLL2PUBC_Pos) /*!< 0x00000002 */ #define RCC_PUBCFGCR1_PLL2PUBC RCC_PUBCFGCR1_PLL2PUBC_Msk /*!< Public protection of te PLL2 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR1_PLL3PUBC_Pos (2U) #define RCC_PUBCFGCR1_PLL3PUBC_Msk (0x1UL << RCC_PUBCFGCR1_PLL3PUBC_Pos) /*!< 0x00000004 */ #define RCC_PUBCFGCR1_PLL3PUBC RCC_PUBCFGCR1_PLL3PUBC_Msk /*!< Public protection of PLL3 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR1_PLL4PUBC_Pos (3U) #define RCC_PUBCFGCR1_PLL4PUBC_Msk (0x1UL << RCC_PUBCFGCR1_PLL4PUBC_Pos) /*!< 0x00000008 */ #define RCC_PUBCFGCR1_PLL4PUBC RCC_PUBCFGCR1_PLL4PUBC_Msk /*!< Public protection of PLL4 configuration bits (enable, ready, divider) */ /**************** Bit definition for RCC_PRIVCFGCR2 register ****************/ #define RCC_PRIVCFGCR2_IC1PRIVC_Pos (0U) #define RCC_PRIVCFGCR2_IC1PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC1PRIVC_Pos)/*!< 0x00000001 */ #define RCC_PRIVCFGCR2_IC1PRIVC RCC_PRIVCFGCR2_IC1PRIVC_Msk /*!< Privileged protection of the IC1 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGCR2_IC2PRIVC_Pos (1U) #define RCC_PRIVCFGCR2_IC2PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC2PRIVC_Pos)/*!< 0x00000002 */ #define RCC_PRIVCFGCR2_IC2PRIVC RCC_PRIVCFGCR2_IC2PRIVC_Msk /*!< Privileged protection of the IC2 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGCR2_IC3PRIVC_Pos (2U) #define RCC_PRIVCFGCR2_IC3PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC3PRIVC_Pos)/*!< 0x00000004 */ #define RCC_PRIVCFGCR2_IC3PRIVC RCC_PRIVCFGCR2_IC3PRIVC_Msk /*!< Privileged protection of the IC3 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGCR2_IC4PRIVC_Pos (3U) #define RCC_PRIVCFGCR2_IC4PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC4PRIVC_Pos)/*!< 0x00000008 */ #define RCC_PRIVCFGCR2_IC4PRIVC RCC_PRIVCFGCR2_IC4PRIVC_Msk /*!< Privileged protection of the IC4 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGCR2_IC5PRIVC_Pos (4U) #define RCC_PRIVCFGCR2_IC5PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC5PRIVC_Pos)/*!< 0x00000010 */ #define RCC_PRIVCFGCR2_IC5PRIVC RCC_PRIVCFGCR2_IC5PRIVC_Msk /*!< Privileged protection of the IC5 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGCR2_IC6PRIVC_Pos (5U) #define RCC_PRIVCFGCR2_IC6PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC6PRIVC_Pos)/*!< 0x00000020 */ #define RCC_PRIVCFGCR2_IC6PRIVC RCC_PRIVCFGCR2_IC6PRIVC_Msk /*!< Privileged protection of IC6 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGCR2_IC7PRIVC_Pos (6U) #define RCC_PRIVCFGCR2_IC7PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC7PRIVC_Pos)/*!< 0x00000040 */ #define RCC_PRIVCFGCR2_IC7PRIVC RCC_PRIVCFGCR2_IC7PRIVC_Msk /*!< Privileged protection of IC7 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGCR2_IC8PRIVC_Pos (7U) #define RCC_PRIVCFGCR2_IC8PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC8PRIVC_Pos)/*!< 0x00000080 */ #define RCC_PRIVCFGCR2_IC8PRIVC RCC_PRIVCFGCR2_IC8PRIVC_Msk /*!< Privileged protection of IC8 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGCR2_IC9PRIVC_Pos (8U) #define RCC_PRIVCFGCR2_IC9PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC9PRIVC_Pos)/*!< 0x00000100 */ #define RCC_PRIVCFGCR2_IC9PRIVC RCC_PRIVCFGCR2_IC9PRIVC_Msk /*!< Privileged protection of IC9 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGCR2_IC10PRIVC_Pos (9U) #define RCC_PRIVCFGCR2_IC10PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC10PRIVC_Pos) /*!< 0x00000200 */ #define RCC_PRIVCFGCR2_IC10PRIVC RCC_PRIVCFGCR2_IC10PRIVC_Msk /*!< Privileged protection of IC10 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGCR2_IC11PRIVC_Pos (10U) #define RCC_PRIVCFGCR2_IC11PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC11PRIVC_Pos) /*!< 0x00000400 */ #define RCC_PRIVCFGCR2_IC11PRIVC RCC_PRIVCFGCR2_IC11PRIVC_Msk /*!< Privileged protection of IC11 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGCR2_IC12PRIVC_Pos (11U) #define RCC_PRIVCFGCR2_IC12PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC12PRIVC_Pos) /*!< 0x00000800 */ #define RCC_PRIVCFGCR2_IC12PRIVC RCC_PRIVCFGCR2_IC12PRIVC_Msk /*!< Privileged protection of IC12 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGCR2_IC13PRIVC_Pos (12U) #define RCC_PRIVCFGCR2_IC13PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC13PRIVC_Pos) /*!< 0x00001000 */ #define RCC_PRIVCFGCR2_IC13PRIVC RCC_PRIVCFGCR2_IC13PRIVC_Msk /*!< Privileged protection of IC13 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGCR2_IC14PRIVC_Pos (13U) #define RCC_PRIVCFGCR2_IC14PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC14PRIVC_Pos) /*!< 0x00002000 */ #define RCC_PRIVCFGCR2_IC14PRIVC RCC_PRIVCFGCR2_IC14PRIVC_Msk /*!< Privileged protection of IC14 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGCR2_IC15PRIVC_Pos (14U) #define RCC_PRIVCFGCR2_IC15PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC15PRIVC_Pos) /*!< 0x00004000 */ #define RCC_PRIVCFGCR2_IC15PRIVC RCC_PRIVCFGCR2_IC15PRIVC_Msk /*!< Privileged protection of IC15 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGCR2_IC16PRIVC_Pos (15U) #define RCC_PRIVCFGCR2_IC16PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC16PRIVC_Pos) /*!< 0x00008000 */ #define RCC_PRIVCFGCR2_IC16PRIVC RCC_PRIVCFGCR2_IC16PRIVC_Msk /*!< Privileged protection of IC16 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGCR2_IC17PRIVC_Pos (16U) #define RCC_PRIVCFGCR2_IC17PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC17PRIVC_Pos) /*!< 0x00010000 */ #define RCC_PRIVCFGCR2_IC17PRIVC RCC_PRIVCFGCR2_IC17PRIVC_Msk /*!< Privileged protection of IC17 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGCR2_IC18PRIVC_Pos (17U) #define RCC_PRIVCFGCR2_IC18PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC18PRIVC_Pos) /*!< 0x00020000 */ #define RCC_PRIVCFGCR2_IC18PRIVC RCC_PRIVCFGCR2_IC18PRIVC_Msk /*!< Privileged protection of IC18 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGCR2_IC19PRIVC_Pos (18U) #define RCC_PRIVCFGCR2_IC19PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC19PRIVC_Pos) /*!< 0x00040000 */ #define RCC_PRIVCFGCR2_IC19PRIVC RCC_PRIVCFGCR2_IC19PRIVC_Msk /*!< Privileged protection of IC19 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGCR2_IC20PRIVC_Pos (19U) #define RCC_PRIVCFGCR2_IC20PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC20PRIVC_Pos) /*!< 0x00080000 */ #define RCC_PRIVCFGCR2_IC20PRIVC RCC_PRIVCFGCR2_IC20PRIVC_Msk /*!< Privileged protection of IC20 configuration bits (enable, ready, divider) */ /**************** Bit definition for RCC_PUBCFGCR2 register *****************/ #define RCC_PUBCFGCR2_IC1PUBC_Pos (0U) #define RCC_PUBCFGCR2_IC1PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC1PUBC_Pos) /*!< 0x00000001 */ #define RCC_PUBCFGCR2_IC1PUBC RCC_PUBCFGCR2_IC1PUBC_Msk /*!< Public protection of IC1 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR2_IC2PUBC_Pos (1U) #define RCC_PUBCFGCR2_IC2PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC2PUBC_Pos) /*!< 0x00000002 */ #define RCC_PUBCFGCR2_IC2PUBC RCC_PUBCFGCR2_IC2PUBC_Msk /*!< Public protection of IC2 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR2_IC3PUBC_Pos (2U) #define RCC_PUBCFGCR2_IC3PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC3PUBC_Pos) /*!< 0x00000004 */ #define RCC_PUBCFGCR2_IC3PUBC RCC_PUBCFGCR2_IC3PUBC_Msk /*!< Public protection of IC3 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR2_IC4PUBC_Pos (3U) #define RCC_PUBCFGCR2_IC4PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC4PUBC_Pos) /*!< 0x00000008 */ #define RCC_PUBCFGCR2_IC4PUBC RCC_PUBCFGCR2_IC4PUBC_Msk /*!< Public protection of IC4 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR2_IC5PUBC_Pos (4U) #define RCC_PUBCFGCR2_IC5PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC5PUBC_Pos) /*!< 0x00000010 */ #define RCC_PUBCFGCR2_IC5PUBC RCC_PUBCFGCR2_IC5PUBC_Msk /*!< Public protection of IC5 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR2_IC6PUBC_Pos (5U) #define RCC_PUBCFGCR2_IC6PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC6PUBC_Pos) /*!< 0x00000020 */ #define RCC_PUBCFGCR2_IC6PUBC RCC_PUBCFGCR2_IC6PUBC_Msk /*!< Public protection of IC6 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR2_IC7PUBC_Pos (6U) #define RCC_PUBCFGCR2_IC7PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC7PUBC_Pos) /*!< 0x00000040 */ #define RCC_PUBCFGCR2_IC7PUBC RCC_PUBCFGCR2_IC7PUBC_Msk /*!< Public protection of IC7 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR2_IC8PUBC_Pos (7U) #define RCC_PUBCFGCR2_IC8PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC8PUBC_Pos) /*!< 0x00000080 */ #define RCC_PUBCFGCR2_IC8PUBC RCC_PUBCFGCR2_IC8PUBC_Msk /*!< Public protection of IC8 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR2_IC9PUBC_Pos (8U) #define RCC_PUBCFGCR2_IC9PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC9PUBC_Pos) /*!< 0x00000100 */ #define RCC_PUBCFGCR2_IC9PUBC RCC_PUBCFGCR2_IC9PUBC_Msk /*!< Public protection of IC9 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR2_IC10PUBC_Pos (9U) #define RCC_PUBCFGCR2_IC10PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC10PUBC_Pos) /*!< 0x00000200 */ #define RCC_PUBCFGCR2_IC10PUBC RCC_PUBCFGCR2_IC10PUBC_Msk /*!< Public protection of IC10 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR2_IC11PUBC_Pos (10U) #define RCC_PUBCFGCR2_IC11PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC11PUBC_Pos) /*!< 0x00000400 */ #define RCC_PUBCFGCR2_IC11PUBC RCC_PUBCFGCR2_IC11PUBC_Msk /*!< Public protection of IC11 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR2_IC12PUBC_Pos (11U) #define RCC_PUBCFGCR2_IC12PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC12PUBC_Pos) /*!< 0x00000800 */ #define RCC_PUBCFGCR2_IC12PUBC RCC_PUBCFGCR2_IC12PUBC_Msk /*!< Public protection of IC12 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR2_IC13PUBC_Pos (12U) #define RCC_PUBCFGCR2_IC13PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC13PUBC_Pos) /*!< 0x00001000 */ #define RCC_PUBCFGCR2_IC13PUBC RCC_PUBCFGCR2_IC13PUBC_Msk /*!< Public protection of IC13 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR2_IC14PUBC_Pos (13U) #define RCC_PUBCFGCR2_IC14PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC14PUBC_Pos) /*!< 0x00002000 */ #define RCC_PUBCFGCR2_IC14PUBC RCC_PUBCFGCR2_IC14PUBC_Msk /*!< Public protection of IC14 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR2_IC15PUBC_Pos (14U) #define RCC_PUBCFGCR2_IC15PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC15PUBC_Pos) /*!< 0x00004000 */ #define RCC_PUBCFGCR2_IC15PUBC RCC_PUBCFGCR2_IC15PUBC_Msk /*!< Public protection of IC15 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR2_IC16PUBC_Pos (15U) #define RCC_PUBCFGCR2_IC16PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC16PUBC_Pos) /*!< 0x00008000 */ #define RCC_PUBCFGCR2_IC16PUBC RCC_PUBCFGCR2_IC16PUBC_Msk /*!< Public protection of IC16 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR2_IC17PUBC_Pos (16U) #define RCC_PUBCFGCR2_IC17PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC17PUBC_Pos) /*!< 0x00010000 */ #define RCC_PUBCFGCR2_IC17PUBC RCC_PUBCFGCR2_IC17PUBC_Msk /*!< Public protection of IC17 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR2_IC18PUBC_Pos (17U) #define RCC_PUBCFGCR2_IC18PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC18PUBC_Pos) /*!< 0x00020000 */ #define RCC_PUBCFGCR2_IC18PUBC RCC_PUBCFGCR2_IC18PUBC_Msk /*!< Public protection of IC18 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR2_IC19PUBC_Pos (18U) #define RCC_PUBCFGCR2_IC19PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC19PUBC_Pos) /*!< 0x00040000 */ #define RCC_PUBCFGCR2_IC19PUBC RCC_PUBCFGCR2_IC19PUBC_Msk /*!< Public protection of IC19 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR2_IC20PUBC_Pos (19U) #define RCC_PUBCFGCR2_IC20PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC20PUBC_Pos) /*!< 0x00080000 */ #define RCC_PUBCFGCR2_IC20PUBC RCC_PUBCFGCR2_IC20PUBC_Msk /*!< Public protection of IC20 configuration bits (enable, ready, divider) */ /**************** Bit definition for RCC_PRIVCFGCR3 register ****************/ #define RCC_PRIVCFGCR3_MODPRIVC_Pos (0U) #define RCC_PRIVCFGCR3_MODPRIVC_Msk (0x1UL << RCC_PRIVCFGCR3_MODPRIVC_Pos)/*!< 0x00000001 */ #define RCC_PRIVCFGCR3_MODPRIVC RCC_PRIVCFGCR3_MODPRIVC_Msk /*!< Privileged protection of MOD configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGCR3_SYSPRIVC_Pos (1U) #define RCC_PRIVCFGCR3_SYSPRIVC_Msk (0x1UL << RCC_PRIVCFGCR3_SYSPRIVC_Pos)/*!< 0x00000002 */ #define RCC_PRIVCFGCR3_SYSPRIVC RCC_PRIVCFGCR3_SYSPRIVC_Msk /*!< Privileged protection of SYS configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGCR3_BUSPRIVC_Pos (2U) #define RCC_PRIVCFGCR3_BUSPRIVC_Msk (0x1UL << RCC_PRIVCFGCR3_BUSPRIVC_Pos)/*!< 0x00000004 */ #define RCC_PRIVCFGCR3_BUSPRIVC RCC_PRIVCFGCR3_BUSPRIVC_Msk /*!< Privileged protection of BUS configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGCR3_PERPRIVC_Pos (3U) #define RCC_PRIVCFGCR3_PERPRIVC_Msk (0x1UL << RCC_PRIVCFGCR3_PERPRIVC_Pos)/*!< 0x00000008 */ #define RCC_PRIVCFGCR3_PERPRIVC RCC_PRIVCFGCR3_PERPRIVC_Msk /*!< Privileged protection of PER configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGCR3_INTPRIVC_Pos (4U) #define RCC_PRIVCFGCR3_INTPRIVC_Msk (0x1UL << RCC_PRIVCFGCR3_INTPRIVC_Pos)/*!< 0x00000010 */ #define RCC_PRIVCFGCR3_INTPRIVC RCC_PRIVCFGCR3_INTPRIVC_Msk /*!< Privileged protection of INT configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGCR3_RSTPRIVC_Pos (5U) #define RCC_PRIVCFGCR3_RSTPRIVC_Msk (0x1UL << RCC_PRIVCFGCR3_RSTPRIVC_Pos)/*!< 0x00000020 */ #define RCC_PRIVCFGCR3_RSTPRIVC RCC_PRIVCFGCR3_RSTPRIVC_Msk /*!< Privileged protection of RST configuration bits (enable, ready, divider) */ /**************** Bit definition for RCC_PUBCFGCR3 register *****************/ #define RCC_PUBCFGCR3_MODPUBC_Pos (0U) #define RCC_PUBCFGCR3_MODPUBC_Msk (0x1UL << RCC_PUBCFGCR3_MODPUBC_Pos) /*!< 0x00000001 */ #define RCC_PUBCFGCR3_MODPUBC RCC_PUBCFGCR3_MODPUBC_Msk /*!< Public protection of MOD configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR3_SYSPUBC_Pos (1U) #define RCC_PUBCFGCR3_SYSPUBC_Msk (0x1UL << RCC_PUBCFGCR3_SYSPUBC_Pos) /*!< 0x00000002 */ #define RCC_PUBCFGCR3_SYSPUBC RCC_PUBCFGCR3_SYSPUBC_Msk /*!< Public protection of SYS configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR3_BUSPUBC_Pos (2U) #define RCC_PUBCFGCR3_BUSPUBC_Msk (0x1UL << RCC_PUBCFGCR3_BUSPUBC_Pos) /*!< 0x00000004 */ #define RCC_PUBCFGCR3_BUSPUBC RCC_PUBCFGCR3_BUSPUBC_Msk /*!< Public protection of BUS configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR3_PERPUBC_Pos (3U) #define RCC_PUBCFGCR3_PERPUBC_Msk (0x1UL << RCC_PUBCFGCR3_PERPUBC_Pos) /*!< 0x00000008 */ #define RCC_PUBCFGCR3_PERPUBC RCC_PUBCFGCR3_PERPUBC_Msk /*!< Public protection of PER configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR3_INTPUBC_Pos (4U) #define RCC_PUBCFGCR3_INTPUBC_Msk (0x1UL << RCC_PUBCFGCR3_INTPUBC_Pos) /*!< 0x00000010 */ #define RCC_PUBCFGCR3_INTPUBC RCC_PUBCFGCR3_INTPUBC_Msk /*!< Public protection of INT configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR3_RSTPUBC_Pos (5U) #define RCC_PUBCFGCR3_RSTPUBC_Msk (0x1UL << RCC_PUBCFGCR3_RSTPUBC_Pos) /*!< 0x00000020 */ #define RCC_PUBCFGCR3_RSTPUBC RCC_PUBCFGCR3_RSTPUBC_Msk /*!< Public protection of RST configuration bits (enable, ready, divider) */ /**************** Bit definition for RCC_PRIVCFGCR4 register ****************/ #define RCC_PRIVCFGCR4_ACLKNPRIVC_Pos (0U) #define RCC_PRIVCFGCR4_ACLKNPRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_ACLKNPRIVC_Pos) /*!< 0x00000001 */ #define RCC_PRIVCFGCR4_ACLKNPRIVC RCC_PRIVCFGCR4_ACLKNPRIVC_Msk /*!< Privileged protection of ACLKN configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGCR4_ACLKNCPRIVC_Pos (1U) #define RCC_PRIVCFGCR4_ACLKNCPRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_ACLKNCPRIVC_Pos) /*!< 0x00000002 */ #define RCC_PRIVCFGCR4_ACLKNCPRIVC RCC_PRIVCFGCR4_ACLKNCPRIVC_Msk /*!< Privileged protection of ACLKNC configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGCR4_AHBMPRIVC_Pos (2U) #define RCC_PRIVCFGCR4_AHBMPRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_AHBMPRIVC_Pos) /*!< 0x00000004 */ #define RCC_PRIVCFGCR4_AHBMPRIVC RCC_PRIVCFGCR4_AHBMPRIVC_Msk /*!< Privileged protection of AHBM configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGCR4_AHB1PRIVC_Pos (3U) #define RCC_PRIVCFGCR4_AHB1PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_AHB1PRIVC_Pos) /*!< 0x00000008 */ #define RCC_PRIVCFGCR4_AHB1PRIVC RCC_PRIVCFGCR4_AHB1PRIVC_Msk /*!< Privileged protection of AHB1 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGCR4_AHB2PRIVC_Pos (4U) #define RCC_PRIVCFGCR4_AHB2PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_AHB2PRIVC_Pos) /*!< 0x00000010 */ #define RCC_PRIVCFGCR4_AHB2PRIVC RCC_PRIVCFGCR4_AHB2PRIVC_Msk /*!< Privileged protection of AHB2 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGCR4_AHB3PRIVC_Pos (5U) #define RCC_PRIVCFGCR4_AHB3PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_AHB3PRIVC_Pos) /*!< 0x00000020 */ #define RCC_PRIVCFGCR4_AHB3PRIVC RCC_PRIVCFGCR4_AHB3PRIVC_Msk /*!< Privileged protection of AHB3 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGCR4_AHB4PRIVC_Pos (6U) #define RCC_PRIVCFGCR4_AHB4PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_AHB4PRIVC_Pos) /*!< 0x00000040 */ #define RCC_PRIVCFGCR4_AHB4PRIVC RCC_PRIVCFGCR4_AHB4PRIVC_Msk /*!< Privileged protection of AHB4 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGCR4_AHB5PRIVC_Pos (7U) #define RCC_PRIVCFGCR4_AHB5PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_AHB5PRIVC_Pos) /*!< 0x00000080 */ #define RCC_PRIVCFGCR4_AHB5PRIVC RCC_PRIVCFGCR4_AHB5PRIVC_Msk /*!< Privileged protection of AHB5 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGCR4_APB1PRIVC_Pos (8U) #define RCC_PRIVCFGCR4_APB1PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_APB1PRIVC_Pos) /*!< 0x00000100 */ #define RCC_PRIVCFGCR4_APB1PRIVC RCC_PRIVCFGCR4_APB1PRIVC_Msk /*!< Privileged protection of APB1 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGCR4_APB2PRIVC_Pos (9U) #define RCC_PRIVCFGCR4_APB2PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_APB2PRIVC_Pos) /*!< 0x00000200 */ #define RCC_PRIVCFGCR4_APB2PRIVC RCC_PRIVCFGCR4_APB2PRIVC_Msk /*!< Privileged protection of APB2 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGCR4_APB3PRIVC_Pos (10U) #define RCC_PRIVCFGCR4_APB3PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_APB3PRIVC_Pos) /*!< 0x00000400 */ #define RCC_PRIVCFGCR4_APB3PRIVC RCC_PRIVCFGCR4_APB3PRIVC_Msk /*!< Privileged protection of APB3 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGCR4_APB4PRIVC_Pos (11U) #define RCC_PRIVCFGCR4_APB4PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_APB4PRIVC_Pos) /*!< 0x00000800 */ #define RCC_PRIVCFGCR4_APB4PRIVC RCC_PRIVCFGCR4_APB4PRIVC_Msk /*!< Privileged protection of APB4 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGCR4_APB5PRIVC_Pos (12U) #define RCC_PRIVCFGCR4_APB5PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_APB5PRIVC_Pos) /*!< 0x00001000 */ #define RCC_PRIVCFGCR4_APB5PRIVC RCC_PRIVCFGCR4_APB5PRIVC_Msk /*!< Privileged protection of APB5 configuration bits (enable, ready, divider) */ #define RCC_PRIVCFGCR4_NOCPRIVC_Pos (13U) #define RCC_PRIVCFGCR4_NOCPRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_NOCPRIVC_Pos)/*!< 0x00002000 */ #define RCC_PRIVCFGCR4_NOCPRIVC RCC_PRIVCFGCR4_NOCPRIVC_Msk /*!< Privileged protection of NOC configuration bits (enable, ready, divider) */ /**************** Bit definition for RCC_PUBCFGCR4 register *****************/ #define RCC_PUBCFGCR4_ACLKNPUBC_Pos (0U) #define RCC_PUBCFGCR4_ACLKNPUBC_Msk (0x1UL << RCC_PUBCFGCR4_ACLKNPUBC_Pos)/*!< 0x00000001 */ #define RCC_PUBCFGCR4_ACLKNPUBC RCC_PUBCFGCR4_ACLKNPUBC_Msk /*!< Public protection of ACLKN configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR4_ACLKNCPUBC_Pos (1U) #define RCC_PUBCFGCR4_ACLKNCPUBC_Msk (0x1UL << RCC_PUBCFGCR4_ACLKNCPUBC_Pos) /*!< 0x00000002 */ #define RCC_PUBCFGCR4_ACLKNCPUBC RCC_PUBCFGCR4_ACLKNCPUBC_Msk /*!< Public protection of ACLKNC configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR4_AHBMPUBC_Pos (2U) #define RCC_PUBCFGCR4_AHBMPUBC_Msk (0x1UL << RCC_PUBCFGCR4_AHBMPUBC_Pos) /*!< 0x00000004 */ #define RCC_PUBCFGCR4_AHBMPUBC RCC_PUBCFGCR4_AHBMPUBC_Msk /*!< Public protection of AHBM configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR4_AHB1PUBC_Pos (3U) #define RCC_PUBCFGCR4_AHB1PUBC_Msk (0x1UL << RCC_PUBCFGCR4_AHB1PUBC_Pos) /*!< 0x00000008 */ #define RCC_PUBCFGCR4_AHB1PUBC RCC_PUBCFGCR4_AHB1PUBC_Msk /*!< Public protection of AHB1 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR4_AHB2PUBC_Pos (4U) #define RCC_PUBCFGCR4_AHB2PUBC_Msk (0x1UL << RCC_PUBCFGCR4_AHB2PUBC_Pos) /*!< 0x00000010 */ #define RCC_PUBCFGCR4_AHB2PUBC RCC_PUBCFGCR4_AHB2PUBC_Msk /*!< Public protection of AHB2 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR4_AHB3PUBC_Pos (5U) #define RCC_PUBCFGCR4_AHB3PUBC_Msk (0x1UL << RCC_PUBCFGCR4_AHB3PUBC_Pos) /*!< 0x00000020 */ #define RCC_PUBCFGCR4_AHB3PUBC RCC_PUBCFGCR4_AHB3PUBC_Msk /*!< Public protection of AHB3 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR4_AHB4PUBC_Pos (6U) #define RCC_PUBCFGCR4_AHB4PUBC_Msk (0x1UL << RCC_PUBCFGCR4_AHB4PUBC_Pos) /*!< 0x00000040 */ #define RCC_PUBCFGCR4_AHB4PUBC RCC_PUBCFGCR4_AHB4PUBC_Msk /*!< Public protection of AHB4 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR4_AHB5PUBC_Pos (7U) #define RCC_PUBCFGCR4_AHB5PUBC_Msk (0x1UL << RCC_PUBCFGCR4_AHB5PUBC_Pos) /*!< 0x00000080 */ #define RCC_PUBCFGCR4_AHB5PUBC RCC_PUBCFGCR4_AHB5PUBC_Msk /*!< Public protection of AHB5 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR4_APB1PUBC_Pos (8U) #define RCC_PUBCFGCR4_APB1PUBC_Msk (0x1UL << RCC_PUBCFGCR4_APB1PUBC_Pos) /*!< 0x00000100 */ #define RCC_PUBCFGCR4_APB1PUBC RCC_PUBCFGCR4_APB1PUBC_Msk /*!< Public protection of APB1 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR4_APB2PUBC_Pos (9U) #define RCC_PUBCFGCR4_APB2PUBC_Msk (0x1UL << RCC_PUBCFGCR4_APB2PUBC_Pos) /*!< 0x00000200 */ #define RCC_PUBCFGCR4_APB2PUBC RCC_PUBCFGCR4_APB2PUBC_Msk /*!< Public protection of APB2 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR4_APB3PUBC_Pos (10U) #define RCC_PUBCFGCR4_APB3PUBC_Msk (0x1UL << RCC_PUBCFGCR4_APB3PUBC_Pos) /*!< 0x00000400 */ #define RCC_PUBCFGCR4_APB3PUBC RCC_PUBCFGCR4_APB3PUBC_Msk /*!< Public protection of APB3 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR4_APB4PUBC_Pos (11U) #define RCC_PUBCFGCR4_APB4PUBC_Msk (0x1UL << RCC_PUBCFGCR4_APB4PUBC_Pos) /*!< 0x00000800 */ #define RCC_PUBCFGCR4_APB4PUBC RCC_PUBCFGCR4_APB4PUBC_Msk /*!< Public protection of APB4 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR4_APB5PUBC_Pos (12U) #define RCC_PUBCFGCR4_APB5PUBC_Msk (0x1UL << RCC_PUBCFGCR4_APB5PUBC_Pos) /*!< 0x00001000 */ #define RCC_PUBCFGCR4_APB5PUBC RCC_PUBCFGCR4_APB5PUBC_Msk /*!< Public protection of APB5 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR4_NOCPUBC_Pos (13U) #define RCC_PUBCFGCR4_NOCPUBC_Msk (0x1UL << RCC_PUBCFGCR4_NOCPUBC_Pos) /*!< 0x00002000 */ #define RCC_PUBCFGCR4_NOCPUBC RCC_PUBCFGCR4_NOCPUBC_Msk /*!< Public protection of NOC configuration bits (enable, ready, divider) */ /**************** Bit definition for RCC_PUBCFGCR5 register *****************/ #define RCC_PUBCFGCR5_AXISRAM3PUBC_Pos (0U) #define RCC_PUBCFGCR5_AXISRAM3PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AXISRAM3PUBC_Pos) /*!< 0x00000001 */ #define RCC_PUBCFGCR5_AXISRAM3PUBC RCC_PUBCFGCR5_AXISRAM3PUBC_Msk /*!< Public protection of AXISRAM3 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR5_AXISRAM4PUBC_Pos (1U) #define RCC_PUBCFGCR5_AXISRAM4PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AXISRAM4PUBC_Pos) /*!< 0x00000002 */ #define RCC_PUBCFGCR5_AXISRAM4PUBC RCC_PUBCFGCR5_AXISRAM4PUBC_Msk /*!< Public protection of AXISRAM4 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR5_AXISRAM5PUBC_Pos (2U) #define RCC_PUBCFGCR5_AXISRAM5PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AXISRAM5PUBC_Pos) /*!< 0x00000004 */ #define RCC_PUBCFGCR5_AXISRAM5PUBC RCC_PUBCFGCR5_AXISRAM5PUBC_Msk /*!< Public protection of AXISRAM5 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR5_AXISRAM6PUBC_Pos (3U) #define RCC_PUBCFGCR5_AXISRAM6PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AXISRAM6PUBC_Pos) /*!< 0x00000008 */ #define RCC_PUBCFGCR5_AXISRAM6PUBC RCC_PUBCFGCR5_AXISRAM6PUBC_Msk /*!< Public protection of AXISRAM6 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR5_AHBSRAM1PUBC_Pos (4U) #define RCC_PUBCFGCR5_AHBSRAM1PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AHBSRAM1PUBC_Pos) /*!< 0x00000010 */ #define RCC_PUBCFGCR5_AHBSRAM1PUBC RCC_PUBCFGCR5_AHBSRAM1PUBC_Msk /*!< Public protection of AHBSRAM1 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR5_AHBSRAM2PUBC_Pos (5U) #define RCC_PUBCFGCR5_AHBSRAM2PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AHBSRAM2PUBC_Pos) /*!< 0x00000020 */ #define RCC_PUBCFGCR5_AHBSRAM2PUBC RCC_PUBCFGCR5_AHBSRAM2PUBC_Msk /*!< Public protection of AHBSRAM2 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR5_BKPSRAMPUBC_Pos (6U) #define RCC_PUBCFGCR5_BKPSRAMPUBC_Msk (0x1UL << RCC_PUBCFGCR5_BKPSRAMPUBC_Pos) /*!< 0x00000040 */ #define RCC_PUBCFGCR5_BKPSRAMPUBC RCC_PUBCFGCR5_BKPSRAMPUBC_Msk /*!< Public protection of BKPSRAM configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR5_AXISRAM1PUBC_Pos (7U) #define RCC_PUBCFGCR5_AXISRAM1PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AXISRAM1PUBC_Pos) /*!< 0x00000080 */ #define RCC_PUBCFGCR5_AXISRAM1PUBC RCC_PUBCFGCR5_AXISRAM1PUBC_Msk /*!< Public protection of AXISRAM1 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR5_AXISRAM2PUBC_Pos (8U) #define RCC_PUBCFGCR5_AXISRAM2PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AXISRAM2PUBC_Pos) /*!< 0x00000100 */ #define RCC_PUBCFGCR5_AXISRAM2PUBC RCC_PUBCFGCR5_AXISRAM2PUBC_Msk /*!< Public protection of AXISRAM2 configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR5_FLEXRAMPUBC_Pos (9U) #define RCC_PUBCFGCR5_FLEXRAMPUBC_Msk (0x1UL << RCC_PUBCFGCR5_FLEXRAMPUBC_Pos) /*!< 0x00000200 */ #define RCC_PUBCFGCR5_FLEXRAMPUBC RCC_PUBCFGCR5_FLEXRAMPUBC_Msk /*!< Public protection of FLEXRAM configuration bits (enable, ready, divider) */ #define RCC_PUBCFGCR5_CACHEAXIRAMPUBC_Pos (10U) #define RCC_PUBCFGCR5_CACHEAXIRAMPUBC_Msk (0x1UL << RCC_PUBCFGCR5_CACHEAXIRAMPUBC_Pos) /*!< 0x00000400 */ #define RCC_PUBCFGCR5_CACHEAXIRAMPUBC RCC_PUBCFGCR5_CACHEAXIRAMPUBC_Msk /*!< Public protection of CACHEAXIRAM configuration bits */ #define RCC_PUBCFGCR5_VENCRAMPUBC_Pos (11U) #define RCC_PUBCFGCR5_VENCRAMPUBC_Msk (0x1UL << RCC_PUBCFGCR5_VENCRAMPUBC_Pos) /*!< 0x00000800 */ #define RCC_PUBCFGCR5_VENCRAMPUBC RCC_PUBCFGCR5_VENCRAMPUBC_Msk /*!< Public protection of VENCRAM configuration bits (enable, ready, divider) */ /******************************************************************************/ /* */ /* Resource Isolation Framework Security Controller (RIFSC) */ /* */ /******************************************************************************/ /**************** Bit definition for RIFSC_RISC_CR register *****************/ #define RIFSC_RISC_CR_GLOCK_Pos (0UL) #define RIFSC_RISC_CR_GLOCK_Msk (0x1UL << RIFSC_RISC_CR_GLOCK_Pos) /*!< 0x00000001 */ #define RIFSC_RISC_CR_GLOCK RIFSC_RISC_CR_GLOCK_Msk /*!< Global lock */ /************* Bit definition for RIFSC_RISC_SECCFGRx register **************/ #define RIFSC_RISC_SECCFGRx_SEC0_Pos (0U) #define RIFSC_RISC_SECCFGRx_SEC0_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC0_Pos) /*!< 0x00000001 */ #define RIFSC_RISC_SECCFGRx_SEC0 RIFSC_RISC_SECCFGRx_SEC0_Msk /*!< Security configuration for peripheral 0 */ #define RIFSC_RISC_SECCFGRx_SEC1_Pos (1U) #define RIFSC_RISC_SECCFGRx_SEC1_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC1_Pos) /*!< 0x00000002 */ #define RIFSC_RISC_SECCFGRx_SEC1 RIFSC_RISC_SECCFGRx_SEC1_Msk /*!< Security configuration for peripheral 1 */ #define RIFSC_RISC_SECCFGRx_SEC2_Pos (2U) #define RIFSC_RISC_SECCFGRx_SEC2_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC2_Pos) /*!< 0x00000004 */ #define RIFSC_RISC_SECCFGRx_SEC2 RIFSC_RISC_SECCFGRx_SEC2_Msk /*!< Security configuration for peripheral 2 */ #define RIFSC_RISC_SECCFGRx_SEC3_Pos (3U) #define RIFSC_RISC_SECCFGRx_SEC3_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC3_Pos) /*!< 0x00000008 */ #define RIFSC_RISC_SECCFGRx_SEC3 RIFSC_RISC_SECCFGRx_SEC3_Msk /*!< Security configuration for peripheral 3 */ #define RIFSC_RISC_SECCFGRx_SEC4_Pos (4U) #define RIFSC_RISC_SECCFGRx_SEC4_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC4_Pos) /*!< 0x00000010 */ #define RIFSC_RISC_SECCFGRx_SEC4 RIFSC_RISC_SECCFGRx_SEC4_Msk /*!< Security configuration for peripheral 4 */ #define RIFSC_RISC_SECCFGRx_SEC5_Pos (5U) #define RIFSC_RISC_SECCFGRx_SEC5_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC5_Pos) /*!< 0x00000020 */ #define RIFSC_RISC_SECCFGRx_SEC5 RIFSC_RISC_SECCFGRx_SEC5_Msk /*!< Security configuration for peripheral 5 */ #define RIFSC_RISC_SECCFGRx_SEC6_Pos (6U) #define RIFSC_RISC_SECCFGRx_SEC6_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC6_Pos) /*!< 0x00000040 */ #define RIFSC_RISC_SECCFGRx_SEC6 RIFSC_RISC_SECCFGRx_SEC6_Msk /*!< Security configuration for peripheral 6 */ #define RIFSC_RISC_SECCFGRx_SEC7_Pos (7U) #define RIFSC_RISC_SECCFGRx_SEC7_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC7_Pos) /*!< 0x00000080 */ #define RIFSC_RISC_SECCFGRx_SEC7 RIFSC_RISC_SECCFGRx_SEC7_Msk /*!< Security configuration for peripheral 7 */ #define RIFSC_RISC_SECCFGRx_SEC8_Pos (8U) #define RIFSC_RISC_SECCFGRx_SEC8_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC8_Pos) /*!< 0x00000100 */ #define RIFSC_RISC_SECCFGRx_SEC8 RIFSC_RISC_SECCFGRx_SEC8_Msk /*!< Security configuration for peripheral 8 */ #define RIFSC_RISC_SECCFGRx_SEC9_Pos (9U) #define RIFSC_RISC_SECCFGRx_SEC9_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC9_Pos) /*!< 0x00000200 */ #define RIFSC_RISC_SECCFGRx_SEC9 RIFSC_RISC_SECCFGRx_SEC9_Msk /*!< Security configuration for peripheral 9 */ #define RIFSC_RISC_SECCFGRx_SEC10_Pos (10U) #define RIFSC_RISC_SECCFGRx_SEC10_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC10_Pos) /*!< 0x00000400 */ #define RIFSC_RISC_SECCFGRx_SEC10 RIFSC_RISC_SECCFGRx_SEC10_Msk /*!< Security configuration for peripheral 10 */ #define RIFSC_RISC_SECCFGRx_SEC11_Pos (11U) #define RIFSC_RISC_SECCFGRx_SEC11_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC11_Pos) /*!< 0x00000800 */ #define RIFSC_RISC_SECCFGRx_SEC11 RIFSC_RISC_SECCFGRx_SEC11_Msk /*!< Security configuration for peripheral 11 */ #define RIFSC_RISC_SECCFGRx_SEC12_Pos (12U) #define RIFSC_RISC_SECCFGRx_SEC12_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC12_Pos) /*!< 0x00001000 */ #define RIFSC_RISC_SECCFGRx_SEC12 RIFSC_RISC_SECCFGRx_SEC12_Msk /*!< Security configuration for peripheral 12 */ #define RIFSC_RISC_SECCFGRx_SEC13_Pos (13U) #define RIFSC_RISC_SECCFGRx_SEC13_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC13_Pos) /*!< 0x00002000 */ #define RIFSC_RISC_SECCFGRx_SEC13 RIFSC_RISC_SECCFGRx_SEC13_Msk /*!< Security configuration for peripheral 13 */ #define RIFSC_RISC_SECCFGRx_SEC14_Pos (14U) #define RIFSC_RISC_SECCFGRx_SEC14_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC14_Pos) /*!< 0x00004000 */ #define RIFSC_RISC_SECCFGRx_SEC14 RIFSC_RISC_SECCFGRx_SEC14_Msk /*!< Security configuration for peripheral 14 */ #define RIFSC_RISC_SECCFGRx_SEC15_Pos (15U) #define RIFSC_RISC_SECCFGRx_SEC15_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC15_Pos) /*!< 0x00008000 */ #define RIFSC_RISC_SECCFGRx_SEC15 RIFSC_RISC_SECCFGRx_SEC15_Msk /*!< Security configuration for peripheral 15 */ #define RIFSC_RISC_SECCFGRx_SEC16_Pos (16U) #define RIFSC_RISC_SECCFGRx_SEC16_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC16_Pos) /*!< 0x00010000 */ #define RIFSC_RISC_SECCFGRx_SEC16 RIFSC_RISC_SECCFGRx_SEC16_Msk /*!< Security configuration for peripheral 16 */ #define RIFSC_RISC_SECCFGRx_SEC17_Pos (17U) #define RIFSC_RISC_SECCFGRx_SEC17_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC17_Pos) /*!< 0x00020000 */ #define RIFSC_RISC_SECCFGRx_SEC17 RIFSC_RISC_SECCFGRx_SEC17_Msk /*!< Security configuration for peripheral 17 */ #define RIFSC_RISC_SECCFGRx_SEC18_Pos (18U) #define RIFSC_RISC_SECCFGRx_SEC18_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC18_Pos) /*!< 0x00040000 */ #define RIFSC_RISC_SECCFGRx_SEC18 RIFSC_RISC_SECCFGRx_SEC18_Msk /*!< Security configuration for peripheral 18 */ #define RIFSC_RISC_SECCFGRx_SEC19_Pos (19U) #define RIFSC_RISC_SECCFGRx_SEC19_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC19_Pos) /*!< 0x00080000 */ #define RIFSC_RISC_SECCFGRx_SEC19 RIFSC_RISC_SECCFGRx_SEC19_Msk /*!< Security configuration for peripheral 19 */ #define RIFSC_RISC_SECCFGRx_SEC20_Pos (20U) #define RIFSC_RISC_SECCFGRx_SEC20_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC20_Pos) /*!< 0x00100000 */ #define RIFSC_RISC_SECCFGRx_SEC20 RIFSC_RISC_SECCFGRx_SEC20_Msk /*!< Security configuration for peripheral 20 */ #define RIFSC_RISC_SECCFGRx_SEC21_Pos (21U) #define RIFSC_RISC_SECCFGRx_SEC21_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC21_Pos) /*!< 0x00200000 */ #define RIFSC_RISC_SECCFGRx_SEC21 RIFSC_RISC_SECCFGRx_SEC21_Msk /*!< Security configuration for peripheral 21 */ #define RIFSC_RISC_SECCFGRx_SEC22_Pos (22U) #define RIFSC_RISC_SECCFGRx_SEC22_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC22_Pos) /*!< 0x00400000 */ #define RIFSC_RISC_SECCFGRx_SEC22 RIFSC_RISC_SECCFGRx_SEC22_Msk /*!< Security configuration for peripheral 22 */ #define RIFSC_RISC_SECCFGRx_SEC23_Pos (23U) #define RIFSC_RISC_SECCFGRx_SEC23_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC23_Pos) /*!< 0x00800000 */ #define RIFSC_RISC_SECCFGRx_SEC23 RIFSC_RISC_SECCFGRx_SEC23_Msk /*!< Security configuration for peripheral 23 */ #define RIFSC_RISC_SECCFGRx_SEC24_Pos (24U) #define RIFSC_RISC_SECCFGRx_SEC24_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC24_Pos) /*!< 0x01000000 */ #define RIFSC_RISC_SECCFGRx_SEC24 RIFSC_RISC_SECCFGRx_SEC24_Msk /*!< Security configuration for peripheral 24 */ #define RIFSC_RISC_SECCFGRx_SEC25_Pos (25U) #define RIFSC_RISC_SECCFGRx_SEC25_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC25_Pos) /*!< 0x02000000 */ #define RIFSC_RISC_SECCFGRx_SEC25 RIFSC_RISC_SECCFGRx_SEC25_Msk /*!< Security configuration for peripheral 25 */ #define RIFSC_RISC_SECCFGRx_SEC26_Pos (26U) #define RIFSC_RISC_SECCFGRx_SEC26_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC26_Pos) /*!< 0x04000000 */ #define RIFSC_RISC_SECCFGRx_SEC26 RIFSC_RISC_SECCFGRx_SEC26_Msk /*!< Security configuration for peripheral 26 */ #define RIFSC_RISC_SECCFGRx_SEC27_Pos (27U) #define RIFSC_RISC_SECCFGRx_SEC27_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC27_Pos) /*!< 0x08000000 */ #define RIFSC_RISC_SECCFGRx_SEC27 RIFSC_RISC_SECCFGRx_SEC27_Msk /*!< Security configuration for peripheral 27 */ #define RIFSC_RISC_SECCFGRx_SEC28_Pos (28U) #define RIFSC_RISC_SECCFGRx_SEC28_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC28_Pos) /*!< 0x10000000 */ #define RIFSC_RISC_SECCFGRx_SEC28 RIFSC_RISC_SECCFGRx_SEC28_Msk /*!< Security configuration for peripheral 28 */ #define RIFSC_RISC_SECCFGRx_SEC29_Pos (29U) #define RIFSC_RISC_SECCFGRx_SEC29_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC29_Pos) /*!< 0x20000000 */ #define RIFSC_RISC_SECCFGRx_SEC29 RIFSC_RISC_SECCFGRx_SEC29_Msk /*!< Security configuration for peripheral 29 */ #define RIFSC_RISC_SECCFGRx_SEC30_Pos (30U) #define RIFSC_RISC_SECCFGRx_SEC30_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC30_Pos) /*!< 0x40000000 */ #define RIFSC_RISC_SECCFGRx_SEC30 RIFSC_RISC_SECCFGRx_SEC30_Msk /*!< Security configuration for peripheral 30 */ #define RIFSC_RISC_SECCFGRx_SEC31_Pos (31U) #define RIFSC_RISC_SECCFGRx_SEC31_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC31_Pos) /*!< 0x80000000 */ #define RIFSC_RISC_SECCFGRx_SEC31 RIFSC_RISC_SECCFGRx_SEC31_Msk /*!< Security configuration for peripheral 31 */ /************* Bit definition for RIFSC_RISC_PRIVCFGRx register *************/ #define RIFSC_RISC_PRIVCFGRx_PRIV0_Pos (0U) #define RIFSC_RISC_PRIVCFGRx_PRIV0_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV0_Pos) /*!< 0x00000001 */ #define RIFSC_RISC_PRIVCFGRx_PRIV0 RIFSC_RISC_PRIVCFGRx_PRIV0_Msk /*!< privileged-only access permission for peripheral 0 */ #define RIFSC_RISC_PRIVCFGRx_PRIV1_Pos (1U) #define RIFSC_RISC_PRIVCFGRx_PRIV1_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV1_Pos) /*!< 0x00000002 */ #define RIFSC_RISC_PRIVCFGRx_PRIV1 RIFSC_RISC_PRIVCFGRx_PRIV1_Msk /*!< privileged-only access permission for peripheral 1 */ #define RIFSC_RISC_PRIVCFGRx_PRIV2_Pos (2U) #define RIFSC_RISC_PRIVCFGRx_PRIV2_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV2_Pos) /*!< 0x00000004 */ #define RIFSC_RISC_PRIVCFGRx_PRIV2 RIFSC_RISC_PRIVCFGRx_PRIV2_Msk /*!< privileged-only access permission for peripheral 2 */ #define RIFSC_RISC_PRIVCFGRx_PRIV3_Pos (3U) #define RIFSC_RISC_PRIVCFGRx_PRIV3_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV3_Pos) /*!< 0x00000008 */ #define RIFSC_RISC_PRIVCFGRx_PRIV3 RIFSC_RISC_PRIVCFGRx_PRIV3_Msk /*!< privileged-only access permission for peripheral 3 */ #define RIFSC_RISC_PRIVCFGRx_PRIV4_Pos (4U) #define RIFSC_RISC_PRIVCFGRx_PRIV4_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV4_Pos) /*!< 0x00000010 */ #define RIFSC_RISC_PRIVCFGRx_PRIV4 RIFSC_RISC_PRIVCFGRx_PRIV4_Msk /*!< privileged-only access permission for peripheral 4 */ #define RIFSC_RISC_PRIVCFGRx_PRIV5_Pos (5U) #define RIFSC_RISC_PRIVCFGRx_PRIV5_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV5_Pos) /*!< 0x00000020 */ #define RIFSC_RISC_PRIVCFGRx_PRIV5 RIFSC_RISC_PRIVCFGRx_PRIV5_Msk /*!< privileged-only access permission for peripheral 5 */ #define RIFSC_RISC_PRIVCFGRx_PRIV6_Pos (6U) #define RIFSC_RISC_PRIVCFGRx_PRIV6_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV6_Pos) /*!< 0x00000040 */ #define RIFSC_RISC_PRIVCFGRx_PRIV6 RIFSC_RISC_PRIVCFGRx_PRIV6_Msk /*!< privileged-only access permission for peripheral 6 */ #define RIFSC_RISC_PRIVCFGRx_PRIV7_Pos (7U) #define RIFSC_RISC_PRIVCFGRx_PRIV7_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV7_Pos) /*!< 0x00000080 */ #define RIFSC_RISC_PRIVCFGRx_PRIV7 RIFSC_RISC_PRIVCFGRx_PRIV7_Msk /*!< privileged-only access permission for peripheral 7 */ #define RIFSC_RISC_PRIVCFGRx_PRIV8_Pos (8U) #define RIFSC_RISC_PRIVCFGRx_PRIV8_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV8_Pos) /*!< 0x00000100 */ #define RIFSC_RISC_PRIVCFGRx_PRIV8 RIFSC_RISC_PRIVCFGRx_PRIV8_Msk /*!< privileged-only access permission for peripheral 8 */ #define RIFSC_RISC_PRIVCFGRx_PRIV9_Pos (9U) #define RIFSC_RISC_PRIVCFGRx_PRIV9_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV9_Pos) /*!< 0x00000200 */ #define RIFSC_RISC_PRIVCFGRx_PRIV9 RIFSC_RISC_PRIVCFGRx_PRIV9_Msk /*!< privileged-only access permission for peripheral 9 */ #define RIFSC_RISC_PRIVCFGRx_PRIV10_Pos (10U) #define RIFSC_RISC_PRIVCFGRx_PRIV10_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV10_Pos) /*!< 0x00000400 */ #define RIFSC_RISC_PRIVCFGRx_PRIV10 RIFSC_RISC_PRIVCFGRx_PRIV10_Msk /*!< privileged-only access permission for peripheral 10 */ #define RIFSC_RISC_PRIVCFGRx_PRIV11_Pos (11U) #define RIFSC_RISC_PRIVCFGRx_PRIV11_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV11_Pos) /*!< 0x00000800 */ #define RIFSC_RISC_PRIVCFGRx_PRIV11 RIFSC_RISC_PRIVCFGRx_PRIV11_Msk /*!< privileged-only access permission for peripheral 11 */ #define RIFSC_RISC_PRIVCFGRx_PRIV12_Pos (12U) #define RIFSC_RISC_PRIVCFGRx_PRIV12_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV12_Pos) /*!< 0x00001000 */ #define RIFSC_RISC_PRIVCFGRx_PRIV12 RIFSC_RISC_PRIVCFGRx_PRIV12_Msk /*!< privileged-only access permission for peripheral 12 */ #define RIFSC_RISC_PRIVCFGRx_PRIV13_Pos (13U) #define RIFSC_RISC_PRIVCFGRx_PRIV13_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV13_Pos) /*!< 0x00002000 */ #define RIFSC_RISC_PRIVCFGRx_PRIV13 RIFSC_RISC_PRIVCFGRx_PRIV13_Msk /*!< privileged-only access permission for peripheral 13 */ #define RIFSC_RISC_PRIVCFGRx_PRIV14_Pos (14U) #define RIFSC_RISC_PRIVCFGRx_PRIV14_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV14_Pos) /*!< 0x00004000 */ #define RIFSC_RISC_PRIVCFGRx_PRIV14 RIFSC_RISC_PRIVCFGRx_PRIV14_Msk /*!< privileged-only access permission for peripheral 14 */ #define RIFSC_RISC_PRIVCFGRx_PRIV15_Pos (15U) #define RIFSC_RISC_PRIVCFGRx_PRIV15_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV15_Pos) /*!< 0x00008000 */ #define RIFSC_RISC_PRIVCFGRx_PRIV15 RIFSC_RISC_PRIVCFGRx_PRIV15_Msk /*!< privileged-only access permission for peripheral 15 */ #define RIFSC_RISC_PRIVCFGRx_PRIV16_Pos (16U) #define RIFSC_RISC_PRIVCFGRx_PRIV16_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV16_Pos) /*!< 0x00010000 */ #define RIFSC_RISC_PRIVCFGRx_PRIV16 RIFSC_RISC_PRIVCFGRx_PRIV16_Msk /*!< privileged-only access permission for peripheral 16 */ #define RIFSC_RISC_PRIVCFGRx_PRIV17_Pos (17U) #define RIFSC_RISC_PRIVCFGRx_PRIV17_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV17_Pos) /*!< 0x00020000 */ #define RIFSC_RISC_PRIVCFGRx_PRIV17 RIFSC_RISC_PRIVCFGRx_PRIV17_Msk /*!< privileged-only access permission for peripheral 17 */ #define RIFSC_RISC_PRIVCFGRx_PRIV18_Pos (18U) #define RIFSC_RISC_PRIVCFGRx_PRIV18_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV18_Pos) /*!< 0x00040000 */ #define RIFSC_RISC_PRIVCFGRx_PRIV18 RIFSC_RISC_PRIVCFGRx_PRIV18_Msk /*!< privileged-only access permission for peripheral 18 */ #define RIFSC_RISC_PRIVCFGRx_PRIV19_Pos (19U) #define RIFSC_RISC_PRIVCFGRx_PRIV19_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV19_Pos) /*!< 0x00080000 */ #define RIFSC_RISC_PRIVCFGRx_PRIV19 RIFSC_RISC_PRIVCFGRx_PRIV19_Msk /*!< privileged-only access permission for peripheral 19 */ #define RIFSC_RISC_PRIVCFGRx_PRIV20_Pos (20U) #define RIFSC_RISC_PRIVCFGRx_PRIV20_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV20_Pos) /*!< 0x00100000 */ #define RIFSC_RISC_PRIVCFGRx_PRIV20 RIFSC_RISC_PRIVCFGRx_PRIV20_Msk /*!< privileged-only access permission for peripheral 20 */ #define RIFSC_RISC_PRIVCFGRx_PRIV21_Pos (21U) #define RIFSC_RISC_PRIVCFGRx_PRIV21_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV21_Pos) /*!< 0x00200000 */ #define RIFSC_RISC_PRIVCFGRx_PRIV21 RIFSC_RISC_PRIVCFGRx_PRIV21_Msk /*!< privileged-only access permission for peripheral 21 */ #define RIFSC_RISC_PRIVCFGRx_PRIV22_Pos (22U) #define RIFSC_RISC_PRIVCFGRx_PRIV22_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV22_Pos) /*!< 0x00400000 */ #define RIFSC_RISC_PRIVCFGRx_PRIV22 RIFSC_RISC_PRIVCFGRx_PRIV22_Msk /*!< privileged-only access permission for peripheral 22 */ #define RIFSC_RISC_PRIVCFGRx_PRIV23_Pos (23U) #define RIFSC_RISC_PRIVCFGRx_PRIV23_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV23_Pos) /*!< 0x00800000 */ #define RIFSC_RISC_PRIVCFGRx_PRIV23 RIFSC_RISC_PRIVCFGRx_PRIV23_Msk /*!< privileged-only access permission for peripheral 23 */ #define RIFSC_RISC_PRIVCFGRx_PRIV24_Pos (24U) #define RIFSC_RISC_PRIVCFGRx_PRIV24_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV24_Pos) /*!< 0x01000000 */ #define RIFSC_RISC_PRIVCFGRx_PRIV24 RIFSC_RISC_PRIVCFGRx_PRIV24_Msk /*!< privileged-only access permission for peripheral 24 */ #define RIFSC_RISC_PRIVCFGRx_PRIV25_Pos (25U) #define RIFSC_RISC_PRIVCFGRx_PRIV25_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV25_Pos) /*!< 0x02000000 */ #define RIFSC_RISC_PRIVCFGRx_PRIV25 RIFSC_RISC_PRIVCFGRx_PRIV25_Msk /*!< privileged-only access permission for peripheral 25 */ #define RIFSC_RISC_PRIVCFGRx_PRIV26_Pos (26U) #define RIFSC_RISC_PRIVCFGRx_PRIV26_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV26_Pos) /*!< 0x04000000 */ #define RIFSC_RISC_PRIVCFGRx_PRIV26 RIFSC_RISC_PRIVCFGRx_PRIV26_Msk /*!< privileged-only access permission for peripheral 26 */ #define RIFSC_RISC_PRIVCFGRx_PRIV27_Pos (27U) #define RIFSC_RISC_PRIVCFGRx_PRIV27_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV27_Pos) /*!< 0x08000000 */ #define RIFSC_RISC_PRIVCFGRx_PRIV27 RIFSC_RISC_PRIVCFGRx_PRIV27_Msk /*!< privileged-only access permission for peripheral 27 */ #define RIFSC_RISC_PRIVCFGRx_PRIV28_Pos (28U) #define RIFSC_RISC_PRIVCFGRx_PRIV28_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV28_Pos) /*!< 0x10000000 */ #define RIFSC_RISC_PRIVCFGRx_PRIV28 RIFSC_RISC_PRIVCFGRx_PRIV28_Msk /*!< privileged-only access permission for peripheral 28 */ #define RIFSC_RISC_PRIVCFGRx_PRIV29_Pos (29U) #define RIFSC_RISC_PRIVCFGRx_PRIV29_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV29_Pos) /*!< 0x20000000 */ #define RIFSC_RISC_PRIVCFGRx_PRIV29 RIFSC_RISC_PRIVCFGRx_PRIV29_Msk /*!< privileged-only access permission for peripheral 29 */ #define RIFSC_RISC_PRIVCFGRx_PRIV30_Pos (30U) #define RIFSC_RISC_PRIVCFGRx_PRIV30_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV30_Pos) /*!< 0x40000000 */ #define RIFSC_RISC_PRIVCFGRx_PRIV30 RIFSC_RISC_PRIVCFGRx_PRIV30_Msk /*!< privileged-only access permission for peripheral 30 */ #define RIFSC_RISC_PRIVCFGRx_PRIV31_Pos (31U) #define RIFSC_RISC_PRIVCFGRx_PRIV31_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV31_Pos) /*!< 0x80000000 */ #define RIFSC_RISC_PRIVCFGRx_PRIV31 RIFSC_RISC_PRIVCFGRx_PRIV31_Msk /*!< privileged-only access permission for peripheral 31 */ /************* Bit definition for RIFSC_RISC_RCFGLOCKRx register *************/ #define RIFSC_RISC_RCFGLOCKRx_RLOCK0_Pos (0U) #define RIFSC_RISC_RCFGLOCKRx_RLOCK0_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK0_Pos) /*!< 0x00000001 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK0 RIFSC_RISC_RCFGLOCKRx_RLOCK0_Msk /*!< Resource lock for peripheral 0 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK1_Pos (1U) #define RIFSC_RISC_RCFGLOCKRx_RLOCK1_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK1_Pos) /*!< 0x00000002 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK1 RIFSC_RISC_RCFGLOCKRx_RLOCK1_Msk /*!< Resource lock for peripheral 1 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK2_Pos (2U) #define RIFSC_RISC_RCFGLOCKRx_RLOCK2_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK2_Pos) /*!< 0x00000004 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK2 RIFSC_RISC_RCFGLOCKRx_RLOCK2_Msk /*!< Resource lock for peripheral 2 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK3_Pos (3U) #define RIFSC_RISC_RCFGLOCKRx_RLOCK3_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK3_Pos) /*!< 0x00000008 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK3 RIFSC_RISC_RCFGLOCKRx_RLOCK3_Msk /*!< Resource lock for peripheral 3 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK4_Pos (4U) #define RIFSC_RISC_RCFGLOCKRx_RLOCK4_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK4_Pos) /*!< 0x00000010 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK4 RIFSC_RISC_RCFGLOCKRx_RLOCK4_Msk /*!< Resource lock for peripheral 4 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK5_Pos (5U) #define RIFSC_RISC_RCFGLOCKRx_RLOCK5_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK5_Pos) /*!< 0x00000020 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK5 RIFSC_RISC_RCFGLOCKRx_RLOCK5_Msk /*!< Resource lock for peripheral 5 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK6_Pos (6U) #define RIFSC_RISC_RCFGLOCKRx_RLOCK6_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK6_Pos) /*!< 0x00000040 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK6 RIFSC_RISC_RCFGLOCKRx_RLOCK6_Msk /*!< Resource lock for peripheral 6 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK7_Pos (7U) #define RIFSC_RISC_RCFGLOCKRx_RLOCK7_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK7_Pos) /*!< 0x00000080 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK7 RIFSC_RISC_RCFGLOCKRx_RLOCK7_Msk /*!< Resource lock for peripheral 7 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK8_Pos (8U) #define RIFSC_RISC_RCFGLOCKRx_RLOCK8_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK8_Pos) /*!< 0x00000100 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK8 RIFSC_RISC_RCFGLOCKRx_RLOCK8_Msk /*!< Resource lock for peripheral 8 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK9_Pos (9U) #define RIFSC_RISC_RCFGLOCKRx_RLOCK9_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK9_Pos) /*!< 0x00000200 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK9 RIFSC_RISC_RCFGLOCKRx_RLOCK9_Msk /*!< Resource lock for peripheral 9 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK10_Pos (10U) #define RIFSC_RISC_RCFGLOCKRx_RLOCK10_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK10_Pos) /*!< 0x00000400 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK10 RIFSC_RISC_RCFGLOCKRx_RLOCK10_Msk /*!< Resource lock for peripheral 10 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK11_Pos (11U) #define RIFSC_RISC_RCFGLOCKRx_RLOCK11_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK11_Pos) /*!< 0x00000800 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK11 RIFSC_RISC_RCFGLOCKRx_RLOCK11_Msk /*!< Resource lock for peripheral 11 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK12_Pos (12U) #define RIFSC_RISC_RCFGLOCKRx_RLOCK12_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK12_Pos) /*!< 0x00001000 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK12 RIFSC_RISC_RCFGLOCKRx_RLOCK12_Msk /*!< Resource lock for peripheral 12 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK13_Pos (13U) #define RIFSC_RISC_RCFGLOCKRx_RLOCK13_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK13_Pos) /*!< 0x00002000 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK13 RIFSC_RISC_RCFGLOCKRx_RLOCK13_Msk /*!< Resource lock for peripheral 13 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK14_Pos (14U) #define RIFSC_RISC_RCFGLOCKRx_RLOCK14_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK14_Pos) /*!< 0x00004000 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK14 RIFSC_RISC_RCFGLOCKRx_RLOCK14_Msk /*!< Resource lock for peripheral 14 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK15_Pos (15U) #define RIFSC_RISC_RCFGLOCKRx_RLOCK15_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK15_Pos) /*!< 0x00008000 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK15 RIFSC_RISC_RCFGLOCKRx_RLOCK15_Msk /*!< Resource lock for peripheral 15 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK16_Pos (16U) #define RIFSC_RISC_RCFGLOCKRx_RLOCK16_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK16_Pos) /*!< 0x00010000 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK16 RIFSC_RISC_RCFGLOCKRx_RLOCK16_Msk /*!< Resource lock for peripheral 16 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK17_Pos (17U) #define RIFSC_RISC_RCFGLOCKRx_RLOCK17_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK17_Pos) /*!< 0x00020000 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK17 RIFSC_RISC_RCFGLOCKRx_RLOCK17_Msk /*!< Resource lock for peripheral 17 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK18_Pos (18U) #define RIFSC_RISC_RCFGLOCKRx_RLOCK18_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK18_Pos) /*!< 0x00040000 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK18 RIFSC_RISC_RCFGLOCKRx_RLOCK18_Msk /*!< Resource lock for peripheral 18 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK19_Pos (19U) #define RIFSC_RISC_RCFGLOCKRx_RLOCK19_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK19_Pos) /*!< 0x00080000 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK19 RIFSC_RISC_RCFGLOCKRx_RLOCK19_Msk /*!< Resource lock for peripheral 19 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK20_Pos (20U) #define RIFSC_RISC_RCFGLOCKRx_RLOCK20_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK20_Pos) /*!< 0x00100000 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK20 RIFSC_RISC_RCFGLOCKRx_RLOCK20_Msk /*!< Resource lock for peripheral 20 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK21_Pos (21U) #define RIFSC_RISC_RCFGLOCKRx_RLOCK21_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK21_Pos) /*!< 0x00200000 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK21 RIFSC_RISC_RCFGLOCKRx_RLOCK21_Msk /*!< Resource lock for peripheral 21 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK22_Pos (22U) #define RIFSC_RISC_RCFGLOCKRx_RLOCK22_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK22_Pos) /*!< 0x00400000 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK22 RIFSC_RISC_RCFGLOCKRx_RLOCK22_Msk /*!< Resource lock for peripheral 22 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK23_Pos (23U) #define RIFSC_RISC_RCFGLOCKRx_RLOCK23_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK23_Pos) /*!< 0x00800000 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK23 RIFSC_RISC_RCFGLOCKRx_RLOCK23_Msk /*!< Resource lock for peripheral 23 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK24_Pos (24U) #define RIFSC_RISC_RCFGLOCKRx_RLOCK24_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK24_Pos) /*!< 0x01000000 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK24 RIFSC_RISC_RCFGLOCKRx_RLOCK24_Msk /*!< Resource lock for peripheral 24 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK25_Pos (25U) #define RIFSC_RISC_RCFGLOCKRx_RLOCK25_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK25_Pos) /*!< 0x02000000 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK25 RIFSC_RISC_RCFGLOCKRx_RLOCK25_Msk /*!< Resource lock for peripheral 25 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK26_Pos (26U) #define RIFSC_RISC_RCFGLOCKRx_RLOCK26_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK26_Pos) /*!< 0x04000000 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK26 RIFSC_RISC_RCFGLOCKRx_RLOCK26_Msk /*!< Resource lock for peripheral 26 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK27_Pos (27U) #define RIFSC_RISC_RCFGLOCKRx_RLOCK27_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK27_Pos) /*!< 0x08000000 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK27 RIFSC_RISC_RCFGLOCKRx_RLOCK27_Msk /*!< Resource lock for peripheral 27 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK28_Pos (28U) #define RIFSC_RISC_RCFGLOCKRx_RLOCK28_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK28_Pos) /*!< 0x10000000 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK28 RIFSC_RISC_RCFGLOCKRx_RLOCK28_Msk /*!< Resource lock for peripheral 28 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK29_Pos (29U) #define RIFSC_RISC_RCFGLOCKRx_RLOCK29_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK29_Pos) /*!< 0x20000000 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK29 RIFSC_RISC_RCFGLOCKRx_RLOCK29_Msk /*!< Resource lock for peripheral 29 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK30_Pos (30U) #define RIFSC_RISC_RCFGLOCKRx_RLOCK30_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK30_Pos) /*!< 0x40000000 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK30 RIFSC_RISC_RCFGLOCKRx_RLOCK30_Msk /*!< Resource lock for peripheral 30 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK31_Pos (31U) #define RIFSC_RISC_RCFGLOCKRx_RLOCK31_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK31_Pos) /*!< 0x80000000 */ #define RIFSC_RISC_RCFGLOCKRx_RLOCK31 RIFSC_RISC_RCFGLOCKRx_RLOCK31_Msk /*!< Resource lock for peripheral 31 */ /**************** Bit definition for RIFSC_RIMC_CR register *****************/ #define RIFSC_RIMC_CR_GLOCK_Pos (0U) #define RIFSC_RIMC_CR_GLOCK_Msk (0x1UL << RIFSC_RIMC_CR_GLOCK_Pos) /*!< 0x00000001 */ #define RIFSC_RIMC_CR_GLOCK RIFSC_RIMC_CR_GLOCK_Msk /*!< Global lock */ #define RIFSC_RIMC_CR_DAPCID_Pos (8U) #define RIFSC_RIMC_CR_DAPCID_Msk (0x7UL << RIFSC_RIMC_CR_DAPCID_Pos) /*!< 0x00000700 */ #define RIFSC_RIMC_CR_DAPCID RIFSC_RIMC_CR_DAPCID_Msk /*!< Debug access port compartment ID */ #define RIFSC_RIMC_CR_DAPCID_0 (0x1UL << RIFSC_RIMC_CR_DAPCID_Pos) /*!< 0x00000100 */ #define RIFSC_RIMC_CR_DAPCID_1 (0x2UL << RIFSC_RIMC_CR_DAPCID_Pos) /*!< 0x00000200 */ #define RIFSC_RIMC_CR_DAPCID_2 (0x4UL << RIFSC_RIMC_CR_DAPCID_Pos) /*!< 0x00000400 */ /*************** Bit definition for RIFSC_RIMC_ATTRx register ***************/ #define RIFSC_RIMC_ATTRx_MCID_Pos (4U) #define RIFSC_RIMC_ATTRx_MCID_Msk (0x7UL << RIFSC_RIMC_ATTRx_MCID_Pos) /*!< 0x00000070 */ #define RIFSC_RIMC_ATTRx_MCID RIFSC_RIMC_ATTRx_MCID_Msk /*!< Master CID */ #define RIFSC_RIMC_ATTRx_MCID_0 (0x1UL << RIFSC_RIMC_ATTRx_MCID_Pos) /*!< 0x00000010 */ #define RIFSC_RIMC_ATTRx_MCID_1 (0x2UL << RIFSC_RIMC_ATTRx_MCID_Pos) /*!< 0x00000020 */ #define RIFSC_RIMC_ATTRx_MCID_2 (0x4UL << RIFSC_RIMC_ATTRx_MCID_Pos) /*!< 0x00000040 */ #define RIFSC_RIMC_ATTRx_MSEC_Pos (8U) #define RIFSC_RIMC_ATTRx_MSEC_Msk (0x1UL << RIFSC_RIMC_ATTRx_MSEC_Pos) /*!< 0x00000100 */ #define RIFSC_RIMC_ATTRx_MSEC RIFSC_RIMC_ATTRx_MSEC_Msk /*!< Master secure */ #define RIFSC_RIMC_ATTRx_MPRIV_Pos (9U) #define RIFSC_RIMC_ATTRx_MPRIV_Msk (0x1UL << RIFSC_RIMC_ATTRx_MPRIV_Pos) /*!< 0x00000200 */ #define RIFSC_RIMC_ATTRx_MPRIV RIFSC_RIMC_ATTRx_MPRIV_Msk /*!< Master privileged */ /******************************************************************************/ /* */ /* Resource Isolation Slave unit for Address space protection (RISAF) */ /* */ /******************************************************************************/ /******************* Bit definition for RISAF_CR register *******************/ #define RISAF_CR_GLOCK_Pos (0U) #define RISAF_CR_GLOCK_Msk (0x1UL << RISAF_CR_GLOCK_Pos) /*!< 0x00000001 */ #define RISAF_CR_GLOCK RISAF_CR_GLOCK_Msk /*!< Global lock */ /****************** Bit definition for RISAF_IASR register ******************/ #define RISAF_IASR_CAEF_Pos (0U) #define RISAF_IASR_CAEF_Msk (0x1UL << RISAF_IASR_CAEF_Pos) /*!< 0x00000001 */ #define RISAF_IASR_CAEF RISAF_IASR_CAEF_Msk /*!< Configuration access error flag */ #define RISAF_IASR_IAEF_Pos (1U) #define RISAF_IASR_IAEF_Msk (0x1UL << RISAF_IASR_IAEF_Pos) /*!< 0x00000002 */ #define RISAF_IASR_IAEF RISAF_IASR_IAEF_Msk /*!< Illegal access error flag */ /****************** Bit definition for RISAF_IACR register ******************/ #define RISAF_IACR_CAEF_Pos (0U) #define RISAF_IACR_CAEF_Msk (0x1UL << RISAF_IACR_CAEF_Pos) /*!< 0x00000001 */ #define RISAF_IACR_CAEF RISAF_IACR_CAEF_Msk /*!< Configuration access error flag */ #define RISAF_IACR_IAEF_Pos (1U) #define RISAF_IACR_IAEF_Msk (0x1UL << RISAF_IACR_IAEF_Pos) /*!< 0x00000002 */ #define RISAF_IACR_IAEF RISAF_IACR_IAEF_Msk /*!< Illegal access error flag */ /***************** Bit definition for RISAF_IAESR register *****************/ #define RISAF_IAESR_IACID_Pos (0U) #define RISAF_IAESR_IACID_Msk (0x7UL << RISAF_IAESR_IACID_Pos) /*!< 0x00000007 */ #define RISAF_IAESR_IACID RISAF_IAESR_IACID_Msk /*!< Illegal access compartment ID */ #define RISAF_IAESR_IACID_0 (0x1UL << RISAF_IAESR_IACID_Pos) /*!< 0x00000001 */ #define RISAF_IAESR_IACID_1 (0x2UL << RISAF_IAESR_IACID_Pos) /*!< 0x00000002 */ #define RISAF_IAESR_IACID_2 (0x4UL << RISAF_IAESR_IACID_Pos) /*!< 0x00000004 */ #define RISAF_IAESR_IAPRIV_Pos (4U) #define RISAF_IAESR_IAPRIV_Msk (0x1UL << RISAF_IAESR_IAPRIV_Pos) /*!< 0x00000010 */ #define RISAF_IAESR_IAPRIV RISAF_IAESR_IAPRIV_Msk /*!< Illegal access privileged */ #define RISAF_IAESR_IASEC_Pos (5U) #define RISAF_IAESR_IASEC_Msk (0x1UL << RISAF_IAESR_IASEC_Pos) /*!< 0x00000020 */ #define RISAF_IAESR_IASEC RISAF_IAESR_IASEC_Msk /*!< Illegal access security */ #define RISAF_IAESR_IANRW_Pos (7U) #define RISAF_IAESR_IANRW_Msk (0x1UL << RISAF_IAESR_IANRW_Pos) /*!< 0x00000080 */ #define RISAF_IAESR_IANRW RISAF_IAESR_IANRW_Msk /*!< Illegal access read/write */ /***************** Bit definition for RISAF_IADDR register *****************/ #define RISAF_IADDR_IADD_Pos (0U) #define RISAF_IADDR_IADD_Msk (0xFFFFFFFFUL << RISAF_IADDR_IADD_Pos) /*!< 0xFFFFFFFF */ #define RISAF_IADDR_IADD RISAF_IADDR_IADD_Msk /*!< Illegal address */ #define RISAF_IADDR_IADD_0 (0x1UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000001 */ #define RISAF_IADDR_IADD_1 (0x2UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000002 */ #define RISAF_IADDR_IADD_2 (0x4UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000004 */ #define RISAF_IADDR_IADD_3 (0x8UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000008 */ #define RISAF_IADDR_IADD_4 (0x10UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000010 */ #define RISAF_IADDR_IADD_5 (0x20UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000020 */ #define RISAF_IADDR_IADD_6 (0x40UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000040 */ #define RISAF_IADDR_IADD_7 (0x80UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000080 */ #define RISAF_IADDR_IADD_8 (0x100UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000100 */ #define RISAF_IADDR_IADD_9 (0x200UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000200 */ #define RISAF_IADDR_IADD_10 (0x400UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000400 */ #define RISAF_IADDR_IADD_11 (0x800UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000800 */ #define RISAF_IADDR_IADD_12 (0x1000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00001000 */ #define RISAF_IADDR_IADD_13 (0x2000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00002000 */ #define RISAF_IADDR_IADD_14 (0x4000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00004000 */ #define RISAF_IADDR_IADD_15 (0x8000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00008000 */ #define RISAF_IADDR_IADD_16 (0x10000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00010000 */ #define RISAF_IADDR_IADD_17 (0x20000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00020000 */ #define RISAF_IADDR_IADD_18 (0x40000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00040000 */ #define RISAF_IADDR_IADD_19 (0x80000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00080000 */ #define RISAF_IADDR_IADD_20 (0x100000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00100000 */ #define RISAF_IADDR_IADD_21 (0x200000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00200000 */ #define RISAF_IADDR_IADD_22 (0x400000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00400000 */ #define RISAF_IADDR_IADD_23 (0x800000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00800000 */ #define RISAF_IADDR_IADD_24 (0x1000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x01000000 */ #define RISAF_IADDR_IADD_25 (0x2000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x02000000 */ #define RISAF_IADDR_IADD_26 (0x4000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x04000000 */ #define RISAF_IADDR_IADD_27 (0x8000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x08000000 */ #define RISAF_IADDR_IADD_28 (0x10000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x10000000 */ #define RISAF_IADDR_IADD_29 (0x20000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x20000000 */ #define RISAF_IADDR_IADD_30 (0x40000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x40000000 */ #define RISAF_IADDR_IADD_31 (0x80000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x80000000 */ /*************** Bit definition for RISAF_REGx_CFGR register ****************/ #define RISAF_REGx_CFGR_BREN_Pos (0U) #define RISAF_REGx_CFGR_BREN_Msk (0x1UL << RISAF_REGx_CFGR_BREN_Pos) /*!< 0x00000001 */ #define RISAF_REGx_CFGR_BREN RISAF_REGx_CFGR_BREN_Msk /*!< Base region enable */ #define RISAF_REGx_CFGR_SEC_Pos (8U) #define RISAF_REGx_CFGR_SEC_Msk (0x1UL << RISAF_REGx_CFGR_SEC_Pos) /*!< 0x00000100 */ #define RISAF_REGx_CFGR_SEC RISAF_REGx_CFGR_SEC_Msk /*!< Secure region */ #define RISAF_REGx_CFGR_PRIVC0_Pos (16U) #define RISAF_REGx_CFGR_PRIVC0_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC0_Pos) /*!< 0x00010000 */ #define RISAF_REGx_CFGR_PRIVC0 RISAF_REGx_CFGR_PRIVC0_Msk /*!< Privileged access for compartment 0 */ #define RISAF_REGx_CFGR_PRIVC1_Pos (17U) #define RISAF_REGx_CFGR_PRIVC1_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC1_Pos) /*!< 0x00020000 */ #define RISAF_REGx_CFGR_PRIVC1 RISAF_REGx_CFGR_PRIVC1_Msk /*!< Privileged access for compartment 1 */ #define RISAF_REGx_CFGR_PRIVC2_Pos (18U) #define RISAF_REGx_CFGR_PRIVC2_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC2_Pos) /*!< 0x00040000 */ #define RISAF_REGx_CFGR_PRIVC2 RISAF_REGx_CFGR_PRIVC2_Msk /*!< Privileged access for compartment 2 */ #define RISAF_REGx_CFGR_PRIVC3_Pos (19U) #define RISAF_REGx_CFGR_PRIVC3_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC3_Pos) /*!< 0x00080000 */ #define RISAF_REGx_CFGR_PRIVC3 RISAF_REGx_CFGR_PRIVC3_Msk /*!< Privileged access for compartment 3 */ #define RISAF_REGx_CFGR_PRIVC4_Pos (20U) #define RISAF_REGx_CFGR_PRIVC4_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC4_Pos) /*!< 0x00100000 */ #define RISAF_REGx_CFGR_PRIVC4 RISAF_REGx_CFGR_PRIVC4_Msk /*!< Privileged access for compartment 4 */ #define RISAF_REGx_CFGR_PRIVC5_Pos (21U) #define RISAF_REGx_CFGR_PRIVC5_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC5_Pos) /*!< 0x00200000 */ #define RISAF_REGx_CFGR_PRIVC5 RISAF_REGx_CFGR_PRIVC5_Msk /*!< Privileged access for compartment 5 */ #define RISAF_REGx_CFGR_PRIVC6_Pos (22U) #define RISAF_REGx_CFGR_PRIVC6_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC6_Pos) /*!< 0x00400000 */ #define RISAF_REGx_CFGR_PRIVC6 RISAF_REGx_CFGR_PRIVC6_Msk /*!< Privileged access for compartment 6 */ #define RISAF_REGx_CFGR_PRIVC7_Pos (23U) #define RISAF_REGx_CFGR_PRIVC7_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC7_Pos) /*!< 0x00800000 */ #define RISAF_REGx_CFGR_PRIVC7 RISAF_REGx_CFGR_PRIVC7_Msk /*!< Privileged access for compartment 7 */ /************** Bit definition for RISAF_REGx_STARTR register ***************/ #define RISAF_REGx_STARTR_BADDSTART_Pos (0U) #define RISAF_REGx_STARTR_BADDSTART_Msk (0xFFFFFFFFUL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0xFFFFFFFF */ #define RISAF_REGx_STARTR_BADDSTART RISAF_REGx_STARTR_BADDSTART_Msk /*!< Base region address start */ #define RISAF_REGx_STARTR_BADDSTART_0 (0x1UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000001 */ #define RISAF_REGx_STARTR_BADDSTART_1 (0x2UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000002 */ #define RISAF_REGx_STARTR_BADDSTART_2 (0x4UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000004 */ #define RISAF_REGx_STARTR_BADDSTART_3 (0x8UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000008 */ #define RISAF_REGx_STARTR_BADDSTART_4 (0x10UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000010 */ #define RISAF_REGx_STARTR_BADDSTART_5 (0x20UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000020 */ #define RISAF_REGx_STARTR_BADDSTART_6 (0x40UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000040 */ #define RISAF_REGx_STARTR_BADDSTART_7 (0x80UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000080 */ #define RISAF_REGx_STARTR_BADDSTART_8 (0x100UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000100 */ #define RISAF_REGx_STARTR_BADDSTART_9 (0x200UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000200 */ #define RISAF_REGx_STARTR_BADDSTART_10 (0x400UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000400 */ #define RISAF_REGx_STARTR_BADDSTART_11 (0x800UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000800 */ #define RISAF_REGx_STARTR_BADDSTART_12 (0x1000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00001000 */ #define RISAF_REGx_STARTR_BADDSTART_13 (0x2000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00002000 */ #define RISAF_REGx_STARTR_BADDSTART_14 (0x4000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00004000 */ #define RISAF_REGx_STARTR_BADDSTART_15 (0x8000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00008000 */ #define RISAF_REGx_STARTR_BADDSTART_16 (0x10000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00010000 */ #define RISAF_REGx_STARTR_BADDSTART_17 (0x20000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00020000 */ #define RISAF_REGx_STARTR_BADDSTART_18 (0x40000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00040000 */ #define RISAF_REGx_STARTR_BADDSTART_19 (0x80000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00080000 */ #define RISAF_REGx_STARTR_BADDSTART_20 (0x100000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00100000 */ #define RISAF_REGx_STARTR_BADDSTART_21 (0x200000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00200000 */ #define RISAF_REGx_STARTR_BADDSTART_22 (0x400000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00400000 */ #define RISAF_REGx_STARTR_BADDSTART_23 (0x800000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00800000 */ #define RISAF_REGx_STARTR_BADDSTART_24 (0x1000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x01000000 */ #define RISAF_REGx_STARTR_BADDSTART_25 (0x2000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x02000000 */ #define RISAF_REGx_STARTR_BADDSTART_26 (0x4000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x04000000 */ #define RISAF_REGx_STARTR_BADDSTART_27 (0x8000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x08000000 */ #define RISAF_REGx_STARTR_BADDSTART_28 (0x10000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x10000000 */ #define RISAF_REGx_STARTR_BADDSTART_29 (0x20000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x20000000 */ #define RISAF_REGx_STARTR_BADDSTART_30 (0x40000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x40000000 */ #define RISAF_REGx_STARTR_BADDSTART_31 (0x80000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x80000000 */ /*************** Bit definition for RISAF_REGx_ENDR register ****************/ #define RISAF_REGx_ENDR_BADDEND_Pos (0U) #define RISAF_REGx_ENDR_BADDEND_Msk (0xFFFFFFFFUL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0xFFFFFFFF */ #define RISAF_REGx_ENDR_BADDEND RISAF_REGx_ENDR_BADDEND_Msk /*!< Base region address end */ #define RISAF_REGx_ENDR_BADDEND_0 (0x1UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000001 */ #define RISAF_REGx_ENDR_BADDEND_1 (0x2UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000002 */ #define RISAF_REGx_ENDR_BADDEND_2 (0x4UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000004 */ #define RISAF_REGx_ENDR_BADDEND_3 (0x8UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000008 */ #define RISAF_REGx_ENDR_BADDEND_4 (0x10UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000010 */ #define RISAF_REGx_ENDR_BADDEND_5 (0x20UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000020 */ #define RISAF_REGx_ENDR_BADDEND_6 (0x40UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000040 */ #define RISAF_REGx_ENDR_BADDEND_7 (0x80UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000080 */ #define RISAF_REGx_ENDR_BADDEND_8 (0x100UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000100 */ #define RISAF_REGx_ENDR_BADDEND_9 (0x200UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000200 */ #define RISAF_REGx_ENDR_BADDEND_10 (0x400UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000400 */ #define RISAF_REGx_ENDR_BADDEND_11 (0x800UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000800 */ #define RISAF_REGx_ENDR_BADDEND_12 (0x1000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00001000 */ #define RISAF_REGx_ENDR_BADDEND_13 (0x2000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00002000 */ #define RISAF_REGx_ENDR_BADDEND_14 (0x4000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00004000 */ #define RISAF_REGx_ENDR_BADDEND_15 (0x8000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00008000 */ #define RISAF_REGx_ENDR_BADDEND_16 (0x10000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00010000 */ #define RISAF_REGx_ENDR_BADDEND_17 (0x20000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00020000 */ #define RISAF_REGx_ENDR_BADDEND_18 (0x40000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00040000 */ #define RISAF_REGx_ENDR_BADDEND_19 (0x80000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00080000 */ #define RISAF_REGx_ENDR_BADDEND_20 (0x100000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00100000 */ #define RISAF_REGx_ENDR_BADDEND_21 (0x200000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00200000 */ #define RISAF_REGx_ENDR_BADDEND_22 (0x400000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00400000 */ #define RISAF_REGx_ENDR_BADDEND_23 (0x800000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00800000 */ #define RISAF_REGx_ENDR_BADDEND_24 (0x1000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x01000000 */ #define RISAF_REGx_ENDR_BADDEND_25 (0x2000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x02000000 */ #define RISAF_REGx_ENDR_BADDEND_26 (0x4000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x04000000 */ #define RISAF_REGx_ENDR_BADDEND_27 (0x8000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x08000000 */ #define RISAF_REGx_ENDR_BADDEND_28 (0x10000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x10000000 */ #define RISAF_REGx_ENDR_BADDEND_29 (0x20000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x20000000 */ #define RISAF_REGx_ENDR_BADDEND_30 (0x40000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x40000000 */ #define RISAF_REGx_ENDR_BADDEND_31 (0x80000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x80000000 */ /************** Bit definition for RISAF_REGx_CIDCFGR register **************/ #define RISAF_REGx_CIDCFGR_RDENC0_Pos (0U) #define RISAF_REGx_CIDCFGR_RDENC0_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC0_Pos) /*!< 0x00000001 */ #define RISAF_REGx_CIDCFGR_RDENC0 RISAF_REGx_CIDCFGR_RDENC0_Msk /*!< Read enable for compartment 0 */ #define RISAF_REGx_CIDCFGR_RDENC1_Pos (1U) #define RISAF_REGx_CIDCFGR_RDENC1_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC1_Pos) /*!< 0x00000002 */ #define RISAF_REGx_CIDCFGR_RDENC1 RISAF_REGx_CIDCFGR_RDENC1_Msk /*!< Read enable for compartment 1 */ #define RISAF_REGx_CIDCFGR_RDENC2_Pos (2U) #define RISAF_REGx_CIDCFGR_RDENC2_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC2_Pos) /*!< 0x00000004 */ #define RISAF_REGx_CIDCFGR_RDENC2 RISAF_REGx_CIDCFGR_RDENC2_Msk /*!< Read enable for compartment 2 */ #define RISAF_REGx_CIDCFGR_RDENC3_Pos (3U) #define RISAF_REGx_CIDCFGR_RDENC3_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC3_Pos) /*!< 0x00000008 */ #define RISAF_REGx_CIDCFGR_RDENC3 RISAF_REGx_CIDCFGR_RDENC3_Msk /*!< Read enable for compartment 3 */ #define RISAF_REGx_CIDCFGR_RDENC4_Pos (4U) #define RISAF_REGx_CIDCFGR_RDENC4_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC4_Pos) /*!< 0x00000010 */ #define RISAF_REGx_CIDCFGR_RDENC4 RISAF_REGx_CIDCFGR_RDENC4_Msk /*!< Read enable for compartment 4 */ #define RISAF_REGx_CIDCFGR_RDENC5_Pos (5U) #define RISAF_REGx_CIDCFGR_RDENC5_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC5_Pos) /*!< 0x00000020 */ #define RISAF_REGx_CIDCFGR_RDENC5 RISAF_REGx_CIDCFGR_RDENC5_Msk /*!< Read enable for compartment 5 */ #define RISAF_REGx_CIDCFGR_RDENC6_Pos (6U) #define RISAF_REGx_CIDCFGR_RDENC6_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC6_Pos) /*!< 0x00000040 */ #define RISAF_REGx_CIDCFGR_RDENC6 RISAF_REGx_CIDCFGR_RDENC6_Msk /*!< Read enable for compartment 6 */ #define RISAF_REGx_CIDCFGR_RDENC7_Pos (7U) #define RISAF_REGx_CIDCFGR_RDENC7_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC7_Pos) /*!< 0x00000080 */ #define RISAF_REGx_CIDCFGR_RDENC7 RISAF_REGx_CIDCFGR_RDENC7_Msk /*!< Read enable for compartment 7 */ #define RISAF_REGx_CIDCFGR_WRENC0_Pos (16U) #define RISAF_REGx_CIDCFGR_WRENC0_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC0_Pos) /*!< 0x00010000 */ #define RISAF_REGx_CIDCFGR_WRENC0 RISAF_REGx_CIDCFGR_WRENC0_Msk /*!< Write enable for compartment 0 */ #define RISAF_REGx_CIDCFGR_WRENC1_Pos (17U) #define RISAF_REGx_CIDCFGR_WRENC1_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC1_Pos) /*!< 0x00020000 */ #define RISAF_REGx_CIDCFGR_WRENC1 RISAF_REGx_CIDCFGR_WRENC1_Msk /*!< Write enable for compartment 1 */ #define RISAF_REGx_CIDCFGR_WRENC2_Pos (18U) #define RISAF_REGx_CIDCFGR_WRENC2_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC2_Pos) /*!< 0x00040000 */ #define RISAF_REGx_CIDCFGR_WRENC2 RISAF_REGx_CIDCFGR_WRENC2_Msk /*!< Write enable for compartment 2 */ #define RISAF_REGx_CIDCFGR_WRENC3_Pos (19U) #define RISAF_REGx_CIDCFGR_WRENC3_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC3_Pos) /*!< 0x00080000 */ #define RISAF_REGx_CIDCFGR_WRENC3 RISAF_REGx_CIDCFGR_WRENC3_Msk /*!< Write enable for compartment 3 */ #define RISAF_REGx_CIDCFGR_WRENC4_Pos (20U) #define RISAF_REGx_CIDCFGR_WRENC4_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC4_Pos) /*!< 0x00100000 */ #define RISAF_REGx_CIDCFGR_WRENC4 RISAF_REGx_CIDCFGR_WRENC4_Msk /*!< Write enable for compartment 4 */ #define RISAF_REGx_CIDCFGR_WRENC5_Pos (21U) #define RISAF_REGx_CIDCFGR_WRENC5_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC5_Pos) /*!< 0x00200000 */ #define RISAF_REGx_CIDCFGR_WRENC5 RISAF_REGx_CIDCFGR_WRENC5_Msk /*!< Write enable for compartment 5 */ #define RISAF_REGx_CIDCFGR_WRENC6_Pos (22U) #define RISAF_REGx_CIDCFGR_WRENC6_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC6_Pos) /*!< 0x00400000 */ #define RISAF_REGx_CIDCFGR_WRENC6 RISAF_REGx_CIDCFGR_WRENC6_Msk /*!< Write enable for compartment 6 */ #define RISAF_REGx_CIDCFGR_WRENC7_Pos (23U) #define RISAF_REGx_CIDCFGR_WRENC7_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC7_Pos) /*!< 0x00800000 */ #define RISAF_REGx_CIDCFGR_WRENC7 RISAF_REGx_CIDCFGR_WRENC7_Msk /*!< Write enable for compartment 7 */ /*************** Bit definition for RISAF_REGx_zCFGR register ***************/ #define RISAF_REGx_zCFGR_SREN_Pos (0U) #define RISAF_REGx_zCFGR_SREN_Msk (0x1UL << RISAF_REGx_zCFGR_SREN_Pos) /*!< 0x00000001 */ #define RISAF_REGx_zCFGR_SREN RISAF_REGx_zCFGR_SREN_Msk /*!< Subregion enable */ #define RISAF_REGx_zCFGR_RLOCK_Pos (1U) #define RISAF_REGx_zCFGR_RLOCK_Msk (0x1UL << RISAF_REGx_zCFGR_RLOCK_Pos) /*!< 0x00000002 */ #define RISAF_REGx_zCFGR_RLOCK RISAF_REGx_zCFGR_RLOCK_Msk /*!< Resource lock */ #define RISAF_REGx_zCFGR_SRCID_Pos (4U) #define RISAF_REGx_zCFGR_SRCID_Msk (0x7UL << RISAF_REGx_zCFGR_SRCID_Pos) /*!< 0x00000070 */ #define RISAF_REGx_zCFGR_SRCID RISAF_REGx_zCFGR_SRCID_Msk /*!< Subregion CID */ #define RISAF_REGx_zCFGR_SRCID_0 (0x1UL << RISAF_REGx_zCFGR_SRCID_Pos) /*!< 0x00000010 */ #define RISAF_REGx_zCFGR_SRCID_1 (0x2UL << RISAF_REGx_zCFGR_SRCID_Pos) /*!< 0x00000020 */ #define RISAF_REGx_zCFGR_SRCID_2 (0x4UL << RISAF_REGx_zCFGR_SRCID_Pos) /*!< 0x00000040 */ #define RISAF_REGx_zCFGR_SEC_Pos (8U) #define RISAF_REGx_zCFGR_SEC_Msk (0x1UL << RISAF_REGx_zCFGR_SEC_Pos) /*!< 0x00000100 */ #define RISAF_REGx_zCFGR_SEC RISAF_REGx_zCFGR_SEC_Msk /*!< Secure subregion */ #define RISAF_REGx_zCFGR_PRIV_Pos (9U) #define RISAF_REGx_zCFGR_PRIV_Msk (0x1UL << RISAF_REGx_zCFGR_PRIV_Pos) /*!< 0x00000200 */ #define RISAF_REGx_zCFGR_PRIV RISAF_REGx_zCFGR_PRIV_Msk /*!< Privileged subregion */ #define RISAF_REGx_zCFGR_RDEN_Pos (12U) #define RISAF_REGx_zCFGR_RDEN_Msk (0x1UL << RISAF_REGx_zCFGR_RDEN_Pos) /*!< 0x00001000 */ #define RISAF_REGx_zCFGR_RDEN RISAF_REGx_zCFGR_RDEN_Msk /*!< Read enable */ #define RISAF_REGx_zCFGR_WREN_Pos (13U) #define RISAF_REGx_zCFGR_WREN_Msk (0x1UL << RISAF_REGx_zCFGR_WREN_Pos) /*!< 0x00002000 */ #define RISAF_REGx_zCFGR_WREN RISAF_REGx_zCFGR_WREN_Msk /*!< Write enable */ /************** Bit definition for RISAF_REGx_zSTARTR register **************/ #define RISAF_REGx_zSTARTR_SADDSTART_Pos (0U) #define RISAF_REGx_zSTARTR_SADDSTART_Msk (0xFFFFFFFFUL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0xFFFFFFFF */ #define RISAF_REGx_zSTARTR_SADDSTART RISAF_REGx_zSTARTR_SADDSTART_Msk /*!< Subregion address start */ #define RISAF_REGx_zSTARTR_SADDSTART_0 (0x1UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000001 */ #define RISAF_REGx_zSTARTR_SADDSTART_1 (0x2UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000002 */ #define RISAF_REGx_zSTARTR_SADDSTART_2 (0x4UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000004 */ #define RISAF_REGx_zSTARTR_SADDSTART_3 (0x8UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000008 */ #define RISAF_REGx_zSTARTR_SADDSTART_4 (0x10UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000010 */ #define RISAF_REGx_zSTARTR_SADDSTART_5 (0x20UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000020 */ #define RISAF_REGx_zSTARTR_SADDSTART_6 (0x40UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000040 */ #define RISAF_REGx_zSTARTR_SADDSTART_7 (0x80UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000080 */ #define RISAF_REGx_zSTARTR_SADDSTART_8 (0x100UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000100 */ #define RISAF_REGx_zSTARTR_SADDSTART_9 (0x200UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000200 */ #define RISAF_REGx_zSTARTR_SADDSTART_10 (0x400UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000400 */ #define RISAF_REGx_zSTARTR_SADDSTART_11 (0x800UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000800 */ #define RISAF_REGx_zSTARTR_SADDSTART_12 (0x1000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00001000 */ #define RISAF_REGx_zSTARTR_SADDSTART_13 (0x2000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00002000 */ #define RISAF_REGx_zSTARTR_SADDSTART_14 (0x4000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00004000 */ #define RISAF_REGx_zSTARTR_SADDSTART_15 (0x8000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00008000 */ #define RISAF_REGx_zSTARTR_SADDSTART_16 (0x10000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00010000 */ #define RISAF_REGx_zSTARTR_SADDSTART_17 (0x20000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00020000 */ #define RISAF_REGx_zSTARTR_SADDSTART_18 (0x40000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00040000 */ #define RISAF_REGx_zSTARTR_SADDSTART_19 (0x80000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00080000 */ #define RISAF_REGx_zSTARTR_SADDSTART_20 (0x100000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00100000 */ #define RISAF_REGx_zSTARTR_SADDSTART_21 (0x200000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00200000 */ #define RISAF_REGx_zSTARTR_SADDSTART_22 (0x400000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00400000 */ #define RISAF_REGx_zSTARTR_SADDSTART_23 (0x800000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00800000 */ #define RISAF_REGx_zSTARTR_SADDSTART_24 (0x1000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x01000000 */ #define RISAF_REGx_zSTARTR_SADDSTART_25 (0x2000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x02000000 */ #define RISAF_REGx_zSTARTR_SADDSTART_26 (0x4000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x04000000 */ #define RISAF_REGx_zSTARTR_SADDSTART_27 (0x8000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x08000000 */ #define RISAF_REGx_zSTARTR_SADDSTART_28 (0x10000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x10000000 */ #define RISAF_REGx_zSTARTR_SADDSTART_29 (0x20000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x20000000 */ #define RISAF_REGx_zSTARTR_SADDSTART_30 (0x40000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x40000000 */ #define RISAF_REGx_zSTARTR_SADDSTART_31 (0x80000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x80000000 */ /*************** Bit definition for RISAF_REGx_zENDR register ***************/ #define RISAF_REGx_zENDR_SADDEND_Pos (0U) #define RISAF_REGx_zENDR_SADDEND_Msk (0xFFFFFFFFUL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0xFFFFFFFF */ #define RISAF_REGx_zENDR_SADDEND RISAF_REGx_zENDR_SADDEND_Msk /*!< Subregion address end */ #define RISAF_REGx_zENDR_SADDEND_0 (0x1UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000001 */ #define RISAF_REGx_zENDR_SADDEND_1 (0x2UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000002 */ #define RISAF_REGx_zENDR_SADDEND_2 (0x4UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000004 */ #define RISAF_REGx_zENDR_SADDEND_3 (0x8UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000008 */ #define RISAF_REGx_zENDR_SADDEND_4 (0x10UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000010 */ #define RISAF_REGx_zENDR_SADDEND_5 (0x20UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000020 */ #define RISAF_REGx_zENDR_SADDEND_6 (0x40UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000040 */ #define RISAF_REGx_zENDR_SADDEND_7 (0x80UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000080 */ #define RISAF_REGx_zENDR_SADDEND_8 (0x100UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000100 */ #define RISAF_REGx_zENDR_SADDEND_9 (0x200UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000200 */ #define RISAF_REGx_zENDR_SADDEND_10 (0x400UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000400 */ #define RISAF_REGx_zENDR_SADDEND_11 (0x800UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000800 */ #define RISAF_REGx_zENDR_SADDEND_12 (0x1000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00001000 */ #define RISAF_REGx_zENDR_SADDEND_13 (0x2000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00002000 */ #define RISAF_REGx_zENDR_SADDEND_14 (0x4000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00004000 */ #define RISAF_REGx_zENDR_SADDEND_15 (0x8000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00008000 */ #define RISAF_REGx_zENDR_SADDEND_16 (0x10000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00010000 */ #define RISAF_REGx_zENDR_SADDEND_17 (0x20000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00020000 */ #define RISAF_REGx_zENDR_SADDEND_18 (0x40000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00040000 */ #define RISAF_REGx_zENDR_SADDEND_19 (0x80000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00080000 */ #define RISAF_REGx_zENDR_SADDEND_20 (0x100000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00100000 */ #define RISAF_REGx_zENDR_SADDEND_21 (0x200000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00200000 */ #define RISAF_REGx_zENDR_SADDEND_22 (0x400000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00400000 */ #define RISAF_REGx_zENDR_SADDEND_23 (0x800000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00800000 */ #define RISAF_REGx_zENDR_SADDEND_24 (0x1000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x01000000 */ #define RISAF_REGx_zENDR_SADDEND_25 (0x2000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x02000000 */ #define RISAF_REGx_zENDR_SADDEND_26 (0x4000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x04000000 */ #define RISAF_REGx_zENDR_SADDEND_27 (0x8000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x08000000 */ #define RISAF_REGx_zENDR_SADDEND_28 (0x10000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x10000000 */ #define RISAF_REGx_zENDR_SADDEND_29 (0x20000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x20000000 */ #define RISAF_REGx_zENDR_SADDEND_30 (0x40000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x40000000 */ #define RISAF_REGx_zENDR_SADDEND_31 (0x80000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x80000000 */ /************** Bit definition for RISAF_REGx_zNESTR register ***************/ #define RISAF_REGx_zNESTR_DCEN_Pos (2U) #define RISAF_REGx_zNESTR_DCEN_Msk (0x1UL << RISAF_REGx_zNESTR_DCEN_Pos) /*!< 0x00000004 */ #define RISAF_REGx_zNESTR_DCEN RISAF_REGx_zNESTR_DCEN_Msk /*!< Delegated configuration enable */ #define RISAF_REGx_zNESTR_DCCID_Pos (4U) #define RISAF_REGx_zNESTR_DCCID_Msk (0x7UL << RISAF_REGx_zNESTR_DCCID_Pos) /*!< 0x00000070 */ #define RISAF_REGx_zNESTR_DCCID RISAF_REGx_zNESTR_DCCID_Msk /*!< Delegated configuration CID */ #define RISAF_REGx_zNESTR_DCCID_0 (0x1UL << RISAF_REGx_zNESTR_DCCID_Pos) /*!< 0x00000010 */ #define RISAF_REGx_zNESTR_DCCID_1 (0x2UL << RISAF_REGx_zNESTR_DCCID_Pos) /*!< 0x00000020 */ #define RISAF_REGx_zNESTR_DCCID_2 (0x4UL << RISAF_REGx_zNESTR_DCCID_Pos) /*!< 0x00000040 */ /******************************************************************************/ /* */ /* (IAC) */ /* */ /******************************************************************************/ /******************* Bit definition for IAC_IER0 register *******************/ #define IAC_IERx_IAIE0_Pos (0U) #define IAC_IERx_IAIE0_Msk (0x1UL << IAC_IERx_IAIE0_Pos) /*!< 0x00000001 */ #define IAC_IERx_IAIE0 IAC_IERx_IAIE0_Msk /*!< illegal access interrupt enable for peripheral 0 (i = 0 to 31) */ #define IAC_IERx_IAIE1_Pos (1U) #define IAC_IERx_IAIE1_Msk (0x1UL << IAC_IERx_IAIE1_Pos) /*!< 0x00000002 */ #define IAC_IERx_IAIE1 IAC_IERx_IAIE1_Msk /*!< illegal access interrupt enable for peripheral 1 (i = 0 to 31) */ #define IAC_IERx_IAIE2_Pos (2U) #define IAC_IERx_IAIE2_Msk (0x1UL << IAC_IERx_IAIE2_Pos) /*!< 0x00000004 */ #define IAC_IERx_IAIE2 IAC_IERx_IAIE2_Msk /*!< illegal access interrupt enable for peripheral 2 (i = 0 to 31) */ #define IAC_IERx_IAIE3_Pos (3U) #define IAC_IERx_IAIE3_Msk (0x1UL << IAC_IERx_IAIE3_Pos) /*!< 0x00000008 */ #define IAC_IERx_IAIE3 IAC_IERx_IAIE3_Msk /*!< illegal access interrupt enable for peripheral 3 (i = 0 to 31) */ #define IAC_IERx_IAIE4_Pos (4U) #define IAC_IERx_IAIE4_Msk (0x1UL << IAC_IERx_IAIE4_Pos) /*!< 0x00000010 */ #define IAC_IERx_IAIE4 IAC_IERx_IAIE4_Msk /*!< illegal access interrupt enable for peripheral 4 (i = 0 to 31) */ #define IAC_IERx_IAIE5_Pos (5U) #define IAC_IERx_IAIE5_Msk (0x1UL << IAC_IERx_IAIE5_Pos) /*!< 0x00000020 */ #define IAC_IERx_IAIE5 IAC_IERx_IAIE5_Msk /*!< illegal access interrupt enable for peripheral 5 (i = 0 to 31) */ #define IAC_IERx_IAIE6_Pos (6U) #define IAC_IERx_IAIE6_Msk (0x1UL << IAC_IERx_IAIE6_Pos) /*!< 0x00000040 */ #define IAC_IERx_IAIE6 IAC_IERx_IAIE6_Msk /*!< illegal access interrupt enable for peripheral 6 (i = 0 to 31) */ #define IAC_IERx_IAIE7_Pos (7U) #define IAC_IERx_IAIE7_Msk (0x1UL << IAC_IERx_IAIE7_Pos) /*!< 0x00000080 */ #define IAC_IERx_IAIE7 IAC_IERx_IAIE7_Msk /*!< illegal access interrupt enable for peripheral 7 (i = 0 to 31) */ #define IAC_IERx_IAIE8_Pos (8U) #define IAC_IERx_IAIE8_Msk (0x1UL << IAC_IERx_IAIE8_Pos) /*!< 0x00000100 */ #define IAC_IERx_IAIE8 IAC_IERx_IAIE8_Msk /*!< illegal access interrupt enable for peripheral 8 (i = 0 to 31) */ #define IAC_IERx_IAIE9_Pos (9U) #define IAC_IERx_IAIE9_Msk (0x1UL << IAC_IERx_IAIE9_Pos) /*!< 0x00000200 */ #define IAC_IERx_IAIE9 IAC_IERx_IAIE9_Msk /*!< illegal access interrupt enable for peripheral 9 (i = 0 to 31) */ #define IAC_IERx_IAIE10_Pos (10U) #define IAC_IERx_IAIE10_Msk (0x1UL << IAC_IERx_IAIE10_Pos) /*!< 0x00000400 */ #define IAC_IERx_IAIE10 IAC_IERx_IAIE10_Msk /*!< illegal access interrupt enable for peripheral 10 (i = 0 to 31) */ #define IAC_IERx_IAIE11_Pos (11U) #define IAC_IERx_IAIE11_Msk (0x1UL << IAC_IERx_IAIE11_Pos) /*!< 0x00000800 */ #define IAC_IERx_IAIE11 IAC_IERx_IAIE11_Msk /*!< illegal access interrupt enable for peripheral 11 (i = 0 to 31) */ #define IAC_IERx_IAIE12_Pos (12U) #define IAC_IERx_IAIE12_Msk (0x1UL << IAC_IERx_IAIE12_Pos) /*!< 0x00001000 */ #define IAC_IERx_IAIE12 IAC_IERx_IAIE12_Msk /*!< illegal access interrupt enable for peripheral 12 (i = 0 to 31) */ #define IAC_IERx_IAIE13_Pos (13U) #define IAC_IERx_IAIE13_Msk (0x1UL << IAC_IERx_IAIE13_Pos) /*!< 0x00002000 */ #define IAC_IERx_IAIE13 IAC_IERx_IAIE13_Msk /*!< illegal access interrupt enable for peripheral 13 (i = 0 to 31) */ #define IAC_IERx_IAIE14_Pos (14U) #define IAC_IERx_IAIE14_Msk (0x1UL << IAC_IERx_IAIE14_Pos) /*!< 0x00004000 */ #define IAC_IERx_IAIE14 IAC_IERx_IAIE14_Msk /*!< illegal access interrupt enable for peripheral 14 (i = 0 to 31) */ #define IAC_IERx_IAIE15_Pos (15U) #define IAC_IERx_IAIE15_Msk (0x1UL << IAC_IERx_IAIE15_Pos) /*!< 0x00008000 */ #define IAC_IERx_IAIE15 IAC_IERx_IAIE15_Msk /*!< illegal access interrupt enable for peripheral 15 (i = 0 to 31) */ #define IAC_IERx_IAIE16_Pos (16U) #define IAC_IERx_IAIE16_Msk (0x1UL << IAC_IERx_IAIE16_Pos) /*!< 0x00010000 */ #define IAC_IERx_IAIE16 IAC_IERx_IAIE16_Msk /*!< illegal access interrupt enable for peripheral 16 (i = 0 to 31) */ #define IAC_IERx_IAIE17_Pos (17U) #define IAC_IERx_IAIE17_Msk (0x1UL << IAC_IERx_IAIE17_Pos) /*!< 0x00020000 */ #define IAC_IERx_IAIE17 IAC_IERx_IAIE17_Msk /*!< illegal access interrupt enable for peripheral 17 (i = 0 to 31) */ #define IAC_IERx_IAIE18_Pos (18U) #define IAC_IERx_IAIE18_Msk (0x1UL << IAC_IERx_IAIE18_Pos) /*!< 0x00040000 */ #define IAC_IERx_IAIE18 IAC_IERx_IAIE18_Msk /*!< illegal access interrupt enable for peripheral 18 (i = 0 to 31) */ #define IAC_IERx_IAIE19_Pos (19U) #define IAC_IERx_IAIE19_Msk (0x1UL << IAC_IERx_IAIE19_Pos) /*!< 0x00080000 */ #define IAC_IERx_IAIE19 IAC_IERx_IAIE19_Msk /*!< illegal access interrupt enable for peripheral 19 (i = 0 to 31) */ #define IAC_IERx_IAIE20_Pos (20U) #define IAC_IERx_IAIE20_Msk (0x1UL << IAC_IERx_IAIE20_Pos) /*!< 0x00100000 */ #define IAC_IERx_IAIE20 IAC_IERx_IAIE20_Msk /*!< illegal access interrupt enable for peripheral 20 (i = 0 to 31) */ #define IAC_IERx_IAIE21_Pos (21U) #define IAC_IERx_IAIE21_Msk (0x1UL << IAC_IERx_IAIE21_Pos) /*!< 0x00200000 */ #define IAC_IERx_IAIE21 IAC_IERx_IAIE21_Msk /*!< illegal access interrupt enable for peripheral 21 (i = 0 to 31) */ #define IAC_IERx_IAIE22_Pos (22U) #define IAC_IERx_IAIE22_Msk (0x1UL << IAC_IERx_IAIE22_Pos) /*!< 0x00400000 */ #define IAC_IERx_IAIE22 IAC_IERx_IAIE22_Msk /*!< illegal access interrupt enable for peripheral 22 (i = 0 to 31) */ #define IAC_IERx_IAIE23_Pos (23U) #define IAC_IERx_IAIE23_Msk (0x1UL << IAC_IERx_IAIE23_Pos) /*!< 0x00800000 */ #define IAC_IERx_IAIE23 IAC_IERx_IAIE23_Msk /*!< illegal access interrupt enable for peripheral 23 (i = 0 to 31) */ #define IAC_IERx_IAIE24_Pos (24U) #define IAC_IERx_IAIE24_Msk (0x1UL << IAC_IERx_IAIE24_Pos) /*!< 0x01000000 */ #define IAC_IERx_IAIE24 IAC_IERx_IAIE24_Msk /*!< illegal access interrupt enable for peripheral 24 (i = 0 to 31) */ #define IAC_IERx_IAIE25_Pos (25U) #define IAC_IERx_IAIE25_Msk (0x1UL << IAC_IERx_IAIE25_Pos) /*!< 0x02000000 */ #define IAC_IERx_IAIE25 IAC_IERx_IAIE25_Msk /*!< illegal access interrupt enable for peripheral 25 (i = 0 to 31) */ #define IAC_IERx_IAIE26_Pos (26U) #define IAC_IERx_IAIE26_Msk (0x1UL << IAC_IERx_IAIE26_Pos) /*!< 0x04000000 */ #define IAC_IERx_IAIE26 IAC_IERx_IAIE26_Msk /*!< illegal access interrupt enable for peripheral 26 (i = 0 to 31) */ #define IAC_IERx_IAIE27_Pos (27U) #define IAC_IERx_IAIE27_Msk (0x1UL << IAC_IERx_IAIE27_Pos) /*!< 0x08000000 */ #define IAC_IERx_IAIE27 IAC_IERx_IAIE27_Msk /*!< illegal access interrupt enable for peripheral 27 (i = 0 to 31) */ #define IAC_IERx_IAIE28_Pos (28U) #define IAC_IERx_IAIE28_Msk (0x1UL << IAC_IERx_IAIE28_Pos) /*!< 0x10000000 */ #define IAC_IERx_IAIE28 IAC_IERx_IAIE28_Msk /*!< illegal access interrupt enable for peripheral 28 (i = 0 to 31) */ #define IAC_IERx_IAIE29_Pos (29U) #define IAC_IERx_IAIE29_Msk (0x1UL << IAC_IERx_IAIE29_Pos) /*!< 0x20000000 */ #define IAC_IERx_IAIE29 IAC_IERx_IAIE29_Msk /*!< illegal access interrupt enable for peripheral 29 (i = 0 to 31) */ #define IAC_IERx_IAIE30_Pos (30U) #define IAC_IERx_IAIE30_Msk (0x1UL << IAC_IERx_IAIE30_Pos) /*!< 0x40000000 */ #define IAC_IERx_IAIE30 IAC_IERx_IAIE30_Msk /*!< illegal access interrupt enable for peripheral 30 (i = 0 to 31) */ #define IAC_IERx_IAIE31_Pos (31U) #define IAC_IERx_IAIE31_Msk (0x1UL << IAC_IERx_IAIE31_Pos) /*!< 0x80000000 */ #define IAC_IERx_IAIE31 IAC_IERx_IAIE31_Msk /*!< illegal access interrupt enable for peripheral 31 (i = 0 to 31) */ /******************* Bit definition for IAC_ISRx register *******************/ #define IAC_ISRx_IAF0_Pos (0U) #define IAC_ISRx_IAF0_Msk (0x1UL << IAC_ISRx_IAF0_Pos) /*!< 0x00000001 */ #define IAC_ISRx_IAF0 IAC_ISRx_IAF0_Msk /*!< illegal access interrupt enable for peripheral 0 (i = 0 to 31) */ #define IAC_ISRx_IAF1_Pos (1U) #define IAC_ISRx_IAF1_Msk (0x1UL << IAC_ISRx_IAF1_Pos) /*!< 0x00000002 */ #define IAC_ISRx_IAF1 IAC_ISRx_IAF1_Msk /*!< illegal access interrupt enable for peripheral 1 (i = 0 to 31) */ #define IAC_ISRx_IAF2_Pos (2U) #define IAC_ISRx_IAF2_Msk (0x1UL << IAC_ISRx_IAF2_Pos) /*!< 0x00000004 */ #define IAC_ISRx_IAF2 IAC_ISRx_IAF2_Msk /*!< illegal access interrupt enable for peripheral 2 (i = 0 to 31) */ #define IAC_ISRx_IAF3_Pos (3U) #define IAC_ISRx_IAF3_Msk (0x1UL << IAC_ISRx_IAF3_Pos) /*!< 0x00000008 */ #define IAC_ISRx_IAF3 IAC_ISRx_IAF3_Msk /*!< illegal access interrupt enable for peripheral 3 (i = 0 to 31) */ #define IAC_ISRx_IAF4_Pos (4U) #define IAC_ISRx_IAF4_Msk (0x1UL << IAC_ISRx_IAF4_Pos) /*!< 0x00000010 */ #define IAC_ISRx_IAF4 IAC_ISRx_IAF4_Msk /*!< illegal access interrupt enable for peripheral 4 (i = 0 to 31) */ #define IAC_ISRx_IAF5_Pos (5U) #define IAC_ISRx_IAF5_Msk (0x1UL << IAC_ISRx_IAF5_Pos) /*!< 0x00000020 */ #define IAC_ISRx_IAF5 IAC_ISRx_IAF5_Msk /*!< illegal access interrupt enable for peripheral 5 (i = 0 to 31) */ #define IAC_ISRx_IAF6_Pos (6U) #define IAC_ISRx_IAF6_Msk (0x1UL << IAC_ISRx_IAF6_Pos) /*!< 0x00000040 */ #define IAC_ISRx_IAF6 IAC_ISRx_IAF6_Msk /*!< illegal access interrupt enable for peripheral 6 (i = 0 to 31) */ #define IAC_ISRx_IAF7_Pos (7U) #define IAC_ISRx_IAF7_Msk (0x1UL << IAC_ISRx_IAF7_Pos) /*!< 0x00000080 */ #define IAC_ISRx_IAF7 IAC_ISRx_IAF7_Msk /*!< illegal access interrupt enable for peripheral 7 (i = 0 to 31) */ #define IAC_ISRx_IAF8_Pos (8U) #define IAC_ISRx_IAF8_Msk (0x1UL << IAC_ISRx_IAF8_Pos) /*!< 0x00000100 */ #define IAC_ISRx_IAF8 IAC_ISRx_IAF8_Msk /*!< illegal access interrupt enable for peripheral 8 (i = 0 to 31) */ #define IAC_ISRx_IAF9_Pos (9U) #define IAC_ISRx_IAF9_Msk (0x1UL << IAC_ISRx_IAF9_Pos) /*!< 0x00000200 */ #define IAC_ISRx_IAF9 IAC_ISRx_IAF9_Msk /*!< illegal access interrupt enable for peripheral 9 (i = 0 to 31) */ #define IAC_ISRx_IAF10_Pos (10U) #define IAC_ISRx_IAF10_Msk (0x1UL << IAC_ISRx_IAF10_Pos) /*!< 0x00000400 */ #define IAC_ISRx_IAF10 IAC_ISRx_IAF10_Msk /*!< illegal access interrupt enable for peripheral 10 (i = 0 to 31) */ #define IAC_ISRx_IAF11_Pos (11U) #define IAC_ISRx_IAF11_Msk (0x1UL << IAC_ISRx_IAF11_Pos) /*!< 0x00000800 */ #define IAC_ISRx_IAF11 IAC_ISRx_IAF11_Msk /*!< illegal access interrupt enable for peripheral 11 (i = 0 to 31) */ #define IAC_ISRx_IAF12_Pos (12U) #define IAC_ISRx_IAF12_Msk (0x1UL << IAC_ISRx_IAF12_Pos) /*!< 0x00001000 */ #define IAC_ISRx_IAF12 IAC_ISRx_IAF12_Msk /*!< illegal access interrupt enable for peripheral 12 (i = 0 to 31) */ #define IAC_ISRx_IAF13_Pos (13U) #define IAC_ISRx_IAF13_Msk (0x1UL << IAC_ISRx_IAF13_Pos) /*!< 0x00002000 */ #define IAC_ISRx_IAF13 IAC_ISRx_IAF13_Msk /*!< illegal access interrupt enable for peripheral 13 (i = 0 to 31) */ #define IAC_ISRx_IAF14_Pos (14U) #define IAC_ISRx_IAF14_Msk (0x1UL << IAC_ISRx_IAF14_Pos) /*!< 0x00004000 */ #define IAC_ISRx_IAF14 IAC_ISRx_IAF14_Msk /*!< illegal access interrupt enable for peripheral 14 (i = 0 to 31) */ #define IAC_ISRx_IAF15_Pos (15U) #define IAC_ISRx_IAF15_Msk (0x1UL << IAC_ISRx_IAF15_Pos) /*!< 0x00008000 */ #define IAC_ISRx_IAF15 IAC_ISRx_IAF15_Msk /*!< illegal access interrupt enable for peripheral 15 (i = 0 to 31) */ #define IAC_ISRx_IAF16_Pos (16U) #define IAC_ISRx_IAF16_Msk (0x1UL << IAC_ISRx_IAF16_Pos) /*!< 0x00010000 */ #define IAC_ISRx_IAF16 IAC_ISRx_IAF16_Msk /*!< illegal access interrupt enable for peripheral 16 (i = 0 to 31) */ #define IAC_ISRx_IAF17_Pos (17U) #define IAC_ISRx_IAF17_Msk (0x1UL << IAC_ISRx_IAF17_Pos) /*!< 0x00020000 */ #define IAC_ISRx_IAF17 IAC_ISRx_IAF17_Msk /*!< illegal access interrupt enable for peripheral 17 (i = 0 to 31) */ #define IAC_ISRx_IAF18_Pos (18U) #define IAC_ISRx_IAF18_Msk (0x1UL << IAC_ISRx_IAF18_Pos) /*!< 0x00040000 */ #define IAC_ISRx_IAF18 IAC_ISRx_IAF18_Msk /*!< illegal access interrupt enable for peripheral 18 (i = 0 to 31) */ #define IAC_ISRx_IAF19_Pos (19U) #define IAC_ISRx_IAF19_Msk (0x1UL << IAC_ISRx_IAF19_Pos) /*!< 0x00080000 */ #define IAC_ISRx_IAF19 IAC_ISRx_IAF19_Msk /*!< illegal access interrupt enable for peripheral 19 (i = 0 to 31) */ #define IAC_ISRx_IAF20_Pos (20U) #define IAC_ISRx_IAF20_Msk (0x1UL << IAC_ISRx_IAF20_Pos) /*!< 0x00100000 */ #define IAC_ISRx_IAF20 IAC_ISRx_IAF20_Msk /*!< illegal access interrupt enable for peripheral 20 (i = 0 to 31) */ #define IAC_ISRx_IAF21_Pos (21U) #define IAC_ISRx_IAF21_Msk (0x1UL << IAC_ISRx_IAF21_Pos) /*!< 0x00200000 */ #define IAC_ISRx_IAF21 IAC_ISRx_IAF21_Msk /*!< illegal access interrupt enable for peripheral 21 (i = 0 to 31) */ #define IAC_ISRx_IAF22_Pos (22U) #define IAC_ISRx_IAF22_Msk (0x1UL << IAC_ISRx_IAF22_Pos) /*!< 0x00400000 */ #define IAC_ISRx_IAF22 IAC_ISRx_IAF22_Msk /*!< illegal access interrupt enable for peripheral 22 (i = 0 to 31) */ #define IAC_ISRx_IAF23_Pos (23U) #define IAC_ISRx_IAF23_Msk (0x1UL << IAC_ISRx_IAF23_Pos) /*!< 0x00800000 */ #define IAC_ISRx_IAF23 IAC_ISRx_IAF23_Msk /*!< illegal access interrupt enable for peripheral 23 (i = 0 to 31) */ #define IAC_ISRx_IAF24_Pos (24U) #define IAC_ISRx_IAF24_Msk (0x1UL << IAC_ISRx_IAF24_Pos) /*!< 0x01000000 */ #define IAC_ISRx_IAF24 IAC_ISRx_IAF24_Msk /*!< illegal access interrupt enable for peripheral 24 (i = 0 to 31) */ #define IAC_ISRx_IAF25_Pos (25U) #define IAC_ISRx_IAF25_Msk (0x1UL << IAC_ISRx_IAF25_Pos) /*!< 0x02000000 */ #define IAC_ISRx_IAF25 IAC_ISRx_IAF25_Msk /*!< illegal access interrupt enable for peripheral 25 (i = 0 to 31) */ #define IAC_ISRx_IAF26_Pos (26U) #define IAC_ISRx_IAF26_Msk (0x1UL << IAC_ISRx_IAF26_Pos) /*!< 0x04000000 */ #define IAC_ISRx_IAF26 IAC_ISRx_IAF26_Msk /*!< illegal access interrupt enable for peripheral 26 (i = 0 to 31) */ #define IAC_ISRx_IAF27_Pos (27U) #define IAC_ISRx_IAF27_Msk (0x1UL << IAC_ISRx_IAF27_Pos) /*!< 0x08000000 */ #define IAC_ISRx_IAF27 IAC_ISRx_IAF27_Msk /*!< illegal access interrupt enable for peripheral 27 (i = 0 to 31) */ #define IAC_ISRx_IAF28_Pos (28U) #define IAC_ISRx_IAF28_Msk (0x1UL << IAC_ISRx_IAF28_Pos) /*!< 0x10000000 */ #define IAC_ISRx_IAF28 IAC_ISRx_IAF28_Msk /*!< illegal access interrupt enable for peripheral 28 (i = 0 to 31) */ #define IAC_ISRx_IAF29_Pos (29U) #define IAC_ISRx_IAF29_Msk (0x1UL << IAC_ISRx_IAF29_Pos) /*!< 0x20000000 */ #define IAC_ISRx_IAF29 IAC_ISRx_IAF29_Msk /*!< illegal access interrupt enable for peripheral 29 (i = 0 to 31) */ #define IAC_ISRx_IAF30_Pos (30U) #define IAC_ISRx_IAF30_Msk (0x1UL << IAC_ISRx_IAF30_Pos) /*!< 0x40000000 */ #define IAC_ISRx_IAF30 IAC_ISRx_IAF30_Msk /*!< illegal access interrupt enable for peripheral 30 (i = 0 to 31) */ #define IAC_ISRx_IAF31_Pos (31U) #define IAC_ISRx_IAF31_Msk (0x1UL << IAC_ISRx_IAF31_Pos) /*!< 0x80000000 */ #define IAC_ISRx_IAF31 IAC_ISRx_IAF31_Msk /*!< illegal access interrupt enable for peripheral 31 (i = 0 to 31) */ /******************* Bit definition for IAC_ICRx register *******************/ #define IAC_ICRx_IAF0_Pos (0U) #define IAC_ICRx_IAF0_Msk (0x1UL << IAC_ICRx_IAF0_Pos) /*!< 0x00000001 */ #define IAC_ICRx_IAF0 IAC_ICRx_IAF0_Msk /*!< illegal access flag clear for peripheral 0 (i = 0 to 31) */ #define IAC_ICRx_IAF1_Pos (1U) #define IAC_ICRx_IAF1_Msk (0x1UL << IAC_ICRx_IAF1_Pos) /*!< 0x00000002 */ #define IAC_ICRx_IAF1 IAC_ICRx_IAF1_Msk /*!< illegal access flag clear for peripheral 1 (i = 0 to 31) */ #define IAC_ICRx_IAF2_Pos (2U) #define IAC_ICRx_IAF2_Msk (0x1UL << IAC_ICRx_IAF2_Pos) /*!< 0x00000004 */ #define IAC_ICRx_IAF2 IAC_ICRx_IAF2_Msk /*!< illegal access flag clear for peripheral 2 (i = 0 to 31) */ #define IAC_ICRx_IAF3_Pos (3U) #define IAC_ICRx_IAF3_Msk (0x1UL << IAC_ICRx_IAF3_Pos) /*!< 0x00000008 */ #define IAC_ICRx_IAF3 IAC_ICRx_IAF3_Msk /*!< illegal access flag clear for peripheral 3 (i = 0 to 31) */ #define IAC_ICRx_IAF4_Pos (4U) #define IAC_ICRx_IAF4_Msk (0x1UL << IAC_ICRx_IAF4_Pos) /*!< 0x00000010 */ #define IAC_ICRx_IAF4 IAC_ICRx_IAF4_Msk /*!< illegal access flag clear for peripheral 4 (i = 0 to 31) */ #define IAC_ICRx_IAF5_Pos (5U) #define IAC_ICRx_IAF5_Msk (0x1UL << IAC_ICRx_IAF5_Pos) /*!< 0x00000020 */ #define IAC_ICRx_IAF5 IAC_ICRx_IAF5_Msk /*!< illegal access flag clear for peripheral 5 (i = 0 to 31) */ #define IAC_ICRx_IAF6_Pos (6U) #define IAC_ICRx_IAF6_Msk (0x1UL << IAC_ICRx_IAF6_Pos) /*!< 0x00000040 */ #define IAC_ICRx_IAF6 IAC_ICRx_IAF6_Msk /*!< illegal access flag clear for peripheral 6 (i = 0 to 31) */ #define IAC_ICRx_IAF7_Pos (7U) #define IAC_ICRx_IAF7_Msk (0x1UL << IAC_ICRx_IAF7_Pos) /*!< 0x00000080 */ #define IAC_ICRx_IAF7 IAC_ICRx_IAF7_Msk /*!< illegal access flag clear for peripheral 7 (i = 0 to 31) */ #define IAC_ICRx_IAF8_Pos (8U) #define IAC_ICRx_IAF8_Msk (0x1UL << IAC_ICRx_IAF8_Pos) /*!< 0x00000100 */ #define IAC_ICRx_IAF8 IAC_ICRx_IAF8_Msk /*!< illegal access flag clear for peripheral 8 (i = 0 to 31) */ #define IAC_ICRx_IAF9_Pos (9U) #define IAC_ICRx_IAF9_Msk (0x1UL << IAC_ICRx_IAF9_Pos) /*!< 0x00000200 */ #define IAC_ICRx_IAF9 IAC_ICRx_IAF9_Msk /*!< illegal access flag clear for peripheral 9 (i = 0 to 31) */ #define IAC_ICRx_IAF10_Pos (10U) #define IAC_ICRx_IAF10_Msk (0x1UL << IAC_ICRx_IAF10_Pos) /*!< 0x00000400 */ #define IAC_ICRx_IAF10 IAC_ICRx_IAF10_Msk /*!< illegal access flag clear for peripheral 10 (i = 0 to 31) */ #define IAC_ICRx_IAF11_Pos (11U) #define IAC_ICRx_IAF11_Msk (0x1UL << IAC_ICRx_IAF11_Pos) /*!< 0x00000800 */ #define IAC_ICRx_IAF11 IAC_ICRx_IAF11_Msk /*!< illegal access flag clear for peripheral 11 (i = 0 to 31) */ #define IAC_ICRx_IAF12_Pos (12U) #define IAC_ICRx_IAF12_Msk (0x1UL << IAC_ICRx_IAF12_Pos) /*!< 0x00001000 */ #define IAC_ICRx_IAF12 IAC_ICRx_IAF12_Msk /*!< illegal access flag clear for peripheral 12 (i = 0 to 31) */ #define IAC_ICRx_IAF13_Pos (13U) #define IAC_ICRx_IAF13_Msk (0x1UL << IAC_ICRx_IAF13_Pos) /*!< 0x00002000 */ #define IAC_ICRx_IAF13 IAC_ICRx_IAF13_Msk /*!< illegal access flag clear for peripheral 13 (i = 0 to 31) */ #define IAC_ICRx_IAF14_Pos (14U) #define IAC_ICRx_IAF14_Msk (0x1UL << IAC_ICRx_IAF14_Pos) /*!< 0x00004000 */ #define IAC_ICRx_IAF14 IAC_ICRx_IAF14_Msk /*!< illegal access flag clear for peripheral 14 (i = 0 to 31) */ #define IAC_ICRx_IAF15_Pos (15U) #define IAC_ICRx_IAF15_Msk (0x1UL << IAC_ICRx_IAF15_Pos) /*!< 0x00008000 */ #define IAC_ICRx_IAF15 IAC_ICRx_IAF15_Msk /*!< illegal access flag clear for peripheral 15 (i = 0 to 31) */ #define IAC_ICRx_IAF16_Pos (16U) #define IAC_ICRx_IAF16_Msk (0x1UL << IAC_ICRx_IAF16_Pos) /*!< 0x00010000 */ #define IAC_ICRx_IAF16 IAC_ICRx_IAF16_Msk /*!< illegal access flag clear for peripheral 16 (i = 0 to 31) */ #define IAC_ICRx_IAF17_Pos (17U) #define IAC_ICRx_IAF17_Msk (0x1UL << IAC_ICRx_IAF17_Pos) /*!< 0x00020000 */ #define IAC_ICRx_IAF17 IAC_ICRx_IAF17_Msk /*!< illegal access flag clear for peripheral 17 (i = 0 to 31) */ #define IAC_ICRx_IAF18_Pos (18U) #define IAC_ICRx_IAF18_Msk (0x1UL << IAC_ICRx_IAF18_Pos) /*!< 0x00040000 */ #define IAC_ICRx_IAF18 IAC_ICRx_IAF18_Msk /*!< illegal access flag clear for peripheral 18 (i = 0 to 31) */ #define IAC_ICRx_IAF19_Pos (19U) #define IAC_ICRx_IAF19_Msk (0x1UL << IAC_ICRx_IAF19_Pos) /*!< 0x00080000 */ #define IAC_ICRx_IAF19 IAC_ICRx_IAF19_Msk /*!< illegal access flag clear for peripheral 19 (i = 0 to 31) */ #define IAC_ICRx_IAF20_Pos (20U) #define IAC_ICRx_IAF20_Msk (0x1UL << IAC_ICRx_IAF20_Pos) /*!< 0x00100000 */ #define IAC_ICRx_IAF20 IAC_ICRx_IAF20_Msk /*!< illegal access flag clear for peripheral 20 (i = 0 to 31) */ #define IAC_ICRx_IAF21_Pos (21U) #define IAC_ICRx_IAF21_Msk (0x1UL << IAC_ICRx_IAF21_Pos) /*!< 0x00200000 */ #define IAC_ICRx_IAF21 IAC_ICRx_IAF21_Msk /*!< illegal access flag clear for peripheral 21 (i = 0 to 31) */ #define IAC_ICRx_IAF22_Pos (22U) #define IAC_ICRx_IAF22_Msk (0x1UL << IAC_ICRx_IAF22_Pos) /*!< 0x00400000 */ #define IAC_ICRx_IAF22 IAC_ICRx_IAF22_Msk /*!< illegal access flag clear for peripheral 22 (i = 0 to 31) */ #define IAC_ICRx_IAF23_Pos (23U) #define IAC_ICRx_IAF23_Msk (0x1UL << IAC_ICRx_IAF23_Pos) /*!< 0x00800000 */ #define IAC_ICRx_IAF23 IAC_ICRx_IAF23_Msk /*!< illegal access flag clear for peripheral 23 (i = 0 to 31) */ #define IAC_ICRx_IAF24_Pos (24U) #define IAC_ICRx_IAF24_Msk (0x1UL << IAC_ICRx_IAF24_Pos) /*!< 0x01000000 */ #define IAC_ICRx_IAF24 IAC_ICRx_IAF24_Msk /*!< illegal access flag clear for peripheral 24 (i = 0 to 31) */ #define IAC_ICRx_IAF25_Pos (25U) #define IAC_ICRx_IAF25_Msk (0x1UL << IAC_ICRx_IAF25_Pos) /*!< 0x02000000 */ #define IAC_ICRx_IAF25 IAC_ICRx_IAF25_Msk /*!< illegal access flag clear for peripheral 25 (i = 0 to 31) */ #define IAC_ICRx_IAF26_Pos (26U) #define IAC_ICRx_IAF26_Msk (0x1UL << IAC_ICRx_IAF26_Pos) /*!< 0x04000000 */ #define IAC_ICRx_IAF26 IAC_ICRx_IAF26_Msk /*!< illegal access flag clear for peripheral 26 (i = 0 to 31) */ #define IAC_ICRx_IAF27_Pos (27U) #define IAC_ICRx_IAF27_Msk (0x1UL << IAC_ICRx_IAF27_Pos) /*!< 0x08000000 */ #define IAC_ICRx_IAF27 IAC_ICRx_IAF27_Msk /*!< illegal access flag clear for peripheral 27 (i = 0 to 31) */ #define IAC_ICRx_IAF28_Pos (28U) #define IAC_ICRx_IAF28_Msk (0x1UL << IAC_ICRx_IAF28_Pos) /*!< 0x10000000 */ #define IAC_ICRx_IAF28 IAC_ICRx_IAF28_Msk /*!< illegal access flag clear for peripheral 28 (i = 0 to 31) */ #define IAC_ICRx_IAF29_Pos (29U) #define IAC_ICRx_IAF29_Msk (0x1UL << IAC_ICRx_IAF29_Pos) /*!< 0x20000000 */ #define IAC_ICRx_IAF29 IAC_ICRx_IAF29_Msk /*!< illegal access flag clear for peripheral 29 (i = 0 to 31) */ #define IAC_ICRx_IAF30_Pos (30U) #define IAC_ICRx_IAF30_Msk (0x1UL << IAC_ICRx_IAF30_Pos) /*!< 0x40000000 */ #define IAC_ICRx_IAF30 IAC_ICRx_IAF30_Msk /*!< illegal access flag clear for peripheral 30 (i = 0 to 31) */ #define IAC_ICRx_IAF31_Pos (31U) #define IAC_ICRx_IAF31_Msk (0x1UL << IAC_ICRx_IAF31_Pos) /*!< 0x80000000 */ #define IAC_ICRx_IAF31 IAC_ICRx_IAF31_Msk /*!< illegal access flag clear for peripheral 31 (i = 0 to 31) */ /****************** Bit definition for IAC_IISRx register *******************/ #define IAC_IISRx_ILACIN0_Pos (0U) #define IAC_IISRx_ILACIN0_Msk (0x1UL << IAC_IISRx_ILACIN0_Pos) /*!< 0x00000001 */ #define IAC_IISRx_ILACIN0 IAC_IISRx_ILACIN0_Msk /*!< illegal access input 0 (i = 0 to 31) */ #define IAC_IISRx_ILACIN1_Pos (1U) #define IAC_IISRx_ILACIN1_Msk (0x1UL << IAC_IISRx_ILACIN1_Pos) /*!< 0x00000002 */ #define IAC_IISRx_ILACIN1 IAC_IISRx_ILACIN1_Msk /*!< illegal access input 1 (i = 0 to 31) */ #define IAC_IISRx_ILACIN2_Pos (2U) #define IAC_IISRx_ILACIN2_Msk (0x1UL << IAC_IISRx_ILACIN2_Pos) /*!< 0x00000004 */ #define IAC_IISRx_ILACIN2 IAC_IISRx_ILACIN2_Msk /*!< illegal access input 2 (i = 0 to 31) */ #define IAC_IISRx_ILACIN3_Pos (3U) #define IAC_IISRx_ILACIN3_Msk (0x1UL << IAC_IISRx_ILACIN3_Pos) /*!< 0x00000008 */ #define IAC_IISRx_ILACIN3 IAC_IISRx_ILACIN3_Msk /*!< illegal access input 3 (i = 0 to 31) */ #define IAC_IISRx_ILACIN4_Pos (4U) #define IAC_IISRx_ILACIN4_Msk (0x1UL << IAC_IISRx_ILACIN4_Pos) /*!< 0x00000010 */ #define IAC_IISRx_ILACIN4 IAC_IISRx_ILACIN4_Msk /*!< illegal access input 4 (i = 0 to 31) */ #define IAC_IISRx_ILACIN5_Pos (5U) #define IAC_IISRx_ILACIN5_Msk (0x1UL << IAC_IISRx_ILACIN5_Pos) /*!< 0x00000020 */ #define IAC_IISRx_ILACIN5 IAC_IISRx_ILACIN5_Msk /*!< illegal access input 5 (i = 0 to 31) */ #define IAC_IISRx_ILACIN6_Pos (6U) #define IAC_IISRx_ILACIN6_Msk (0x1UL << IAC_IISRx_ILACIN6_Pos) /*!< 0x00000040 */ #define IAC_IISRx_ILACIN6 IAC_IISRx_ILACIN6_Msk /*!< illegal access input 6 (i = 0 to 31) */ #define IAC_IISRx_ILACIN7_Pos (7U) #define IAC_IISRx_ILACIN7_Msk (0x1UL << IAC_IISRx_ILACIN7_Pos) /*!< 0x00000080 */ #define IAC_IISRx_ILACIN7 IAC_IISRx_ILACIN7_Msk /*!< illegal access input 7 (i = 0 to 31) */ #define IAC_IISRx_ILACIN8_Pos (8U) #define IAC_IISRx_ILACIN8_Msk (0x1UL << IAC_IISRx_ILACIN8_Pos) /*!< 0x00000100 */ #define IAC_IISRx_ILACIN8 IAC_IISRx_ILACIN8_Msk /*!< illegal access input 8 (i = 0 to 31) */ #define IAC_IISRx_ILACIN9_Pos (9U) #define IAC_IISRx_ILACIN9_Msk (0x1UL << IAC_IISRx_ILACIN9_Pos) /*!< 0x00000200 */ #define IAC_IISRx_ILACIN9 IAC_IISRx_ILACIN9_Msk /*!< illegal access input 9 (i = 0 to 31) */ #define IAC_IISRx_ILACIN10_Pos (10U) #define IAC_IISRx_ILACIN10_Msk (0x1UL << IAC_IISRx_ILACIN10_Pos) /*!< 0x00000400 */ #define IAC_IISRx_ILACIN10 IAC_IISRx_ILACIN10_Msk /*!< illegal access input 10 (i = 0 to 31) */ #define IAC_IISRx_ILACIN11_Pos (11U) #define IAC_IISRx_ILACIN11_Msk (0x1UL << IAC_IISRx_ILACIN11_Pos) /*!< 0x00000800 */ #define IAC_IISRx_ILACIN11 IAC_IISRx_ILACIN11_Msk /*!< illegal access input 11 (i = 0 to 31) */ #define IAC_IISRx_ILACIN12_Pos (12U) #define IAC_IISRx_ILACIN12_Msk (0x1UL << IAC_IISRx_ILACIN12_Pos) /*!< 0x00001000 */ #define IAC_IISRx_ILACIN12 IAC_IISRx_ILACIN12_Msk /*!< illegal access input 12 (i = 0 to 31) */ #define IAC_IISRx_ILACIN13_Pos (13U) #define IAC_IISRx_ILACIN13_Msk (0x1UL << IAC_IISRx_ILACIN13_Pos) /*!< 0x00002000 */ #define IAC_IISRx_ILACIN13 IAC_IISRx_ILACIN13_Msk /*!< illegal access input 13 (i = 0 to 31) */ #define IAC_IISRx_ILACIN14_Pos (14U) #define IAC_IISRx_ILACIN14_Msk (0x1UL << IAC_IISRx_ILACIN14_Pos) /*!< 0x00004000 */ #define IAC_IISRx_ILACIN14 IAC_IISRx_ILACIN14_Msk /*!< illegal access input 14 (i = 0 to 31) */ #define IAC_IISRx_ILACIN15_Pos (15U) #define IAC_IISRx_ILACIN15_Msk (0x1UL << IAC_IISRx_ILACIN15_Pos) /*!< 0x00008000 */ #define IAC_IISRx_ILACIN15 IAC_IISRx_ILACIN15_Msk /*!< illegal access input 15 (i = 0 to 31) */ #define IAC_IISRx_ILACIN16_Pos (16U) #define IAC_IISRx_ILACIN16_Msk (0x1UL << IAC_IISRx_ILACIN16_Pos) /*!< 0x00010000 */ #define IAC_IISRx_ILACIN16 IAC_IISRx_ILACIN16_Msk /*!< illegal access input 16 (i = 0 to 31) */ #define IAC_IISRx_ILACIN17_Pos (17U) #define IAC_IISRx_ILACIN17_Msk (0x1UL << IAC_IISRx_ILACIN17_Pos) /*!< 0x00020000 */ #define IAC_IISRx_ILACIN17 IAC_IISRx_ILACIN17_Msk /*!< illegal access input 17 (i = 0 to 31) */ #define IAC_IISRx_ILACIN18_Pos (18U) #define IAC_IISRx_ILACIN18_Msk (0x1UL << IAC_IISRx_ILACIN18_Pos) /*!< 0x00040000 */ #define IAC_IISRx_ILACIN18 IAC_IISRx_ILACIN18_Msk /*!< illegal access input 18 (i = 0 to 31) */ #define IAC_IISRx_ILACIN19_Pos (19U) #define IAC_IISRx_ILACIN19_Msk (0x1UL << IAC_IISRx_ILACIN19_Pos) /*!< 0x00080000 */ #define IAC_IISRx_ILACIN19 IAC_IISRx_ILACIN19_Msk /*!< illegal access input 19 (i = 0 to 31) */ #define IAC_IISRx_ILACIN20_Pos (20U) #define IAC_IISRx_ILACIN20_Msk (0x1UL << IAC_IISRx_ILACIN20_Pos) /*!< 0x00100000 */ #define IAC_IISRx_ILACIN20 IAC_IISRx_ILACIN20_Msk /*!< illegal access input 20 (i = 0 to 31) */ #define IAC_IISRx_ILACIN21_Pos (21U) #define IAC_IISRx_ILACIN21_Msk (0x1UL << IAC_IISRx_ILACIN21_Pos) /*!< 0x00200000 */ #define IAC_IISRx_ILACIN21 IAC_IISRx_ILACIN21_Msk /*!< illegal access input 21 (i = 0 to 31) */ #define IAC_IISRx_ILACIN22_Pos (22U) #define IAC_IISRx_ILACIN22_Msk (0x1UL << IAC_IISRx_ILACIN22_Pos) /*!< 0x00400000 */ #define IAC_IISRx_ILACIN22 IAC_IISRx_ILACIN22_Msk /*!< illegal access input 22 (i = 0 to 31) */ #define IAC_IISRx_ILACIN23_Pos (23U) #define IAC_IISRx_ILACIN23_Msk (0x1UL << IAC_IISRx_ILACIN23_Pos) /*!< 0x00800000 */ #define IAC_IISRx_ILACIN23 IAC_IISRx_ILACIN23_Msk /*!< illegal access input 23 (i = 0 to 31) */ #define IAC_IISRx_ILACIN24_Pos (24U) #define IAC_IISRx_ILACIN24_Msk (0x1UL << IAC_IISRx_ILACIN24_Pos) /*!< 0x01000000 */ #define IAC_IISRx_ILACIN24 IAC_IISRx_ILACIN24_Msk /*!< illegal access input 24 (i = 0 to 31) */ #define IAC_IISRx_ILACIN25_Pos (25U) #define IAC_IISRx_ILACIN25_Msk (0x1UL << IAC_IISRx_ILACIN25_Pos) /*!< 0x02000000 */ #define IAC_IISRx_ILACIN25 IAC_IISRx_ILACIN25_Msk /*!< illegal access input 25 (i = 0 to 31) */ #define IAC_IISRx_ILACIN26_Pos (26U) #define IAC_IISRx_ILACIN26_Msk (0x1UL << IAC_IISRx_ILACIN26_Pos) /*!< 0x04000000 */ #define IAC_IISRx_ILACIN26 IAC_IISRx_ILACIN26_Msk /*!< illegal access input 26 (i = 0 to 31) */ #define IAC_IISRx_ILACIN27_Pos (27U) #define IAC_IISRx_ILACIN27_Msk (0x1UL << IAC_IISRx_ILACIN27_Pos) /*!< 0x08000000 */ #define IAC_IISRx_ILACIN27 IAC_IISRx_ILACIN27_Msk /*!< illegal access input 27 (i = 0 to 31) */ #define IAC_IISRx_ILACIN28_Pos (28U) #define IAC_IISRx_ILACIN28_Msk (0x1UL << IAC_IISRx_ILACIN28_Pos) /*!< 0x10000000 */ #define IAC_IISRx_ILACIN28 IAC_IISRx_ILACIN28_Msk /*!< illegal access input 28 (i = 0 to 31) */ #define IAC_IISRx_ILACIN29_Pos (29U) #define IAC_IISRx_ILACIN29_Msk (0x1UL << IAC_IISRx_ILACIN29_Pos) /*!< 0x20000000 */ #define IAC_IISRx_ILACIN29 IAC_IISRx_ILACIN29_Msk /*!< illegal access input 29 (i = 0 to 31) */ #define IAC_IISRx_ILACIN30_Pos (30U) #define IAC_IISRx_ILACIN30_Msk (0x1UL << IAC_IISRx_ILACIN30_Pos) /*!< 0x40000000 */ #define IAC_IISRx_ILACIN30 IAC_IISRx_ILACIN30_Msk /*!< illegal access input 30 (i = 0 to 31) */ #define IAC_IISRx_ILACIN31_Pos (31U) #define IAC_IISRx_ILACIN31_Msk (0x1UL << IAC_IISRx_ILACIN31_Pos) /*!< 0x80000000 */ #define IAC_IISRx_ILACIN31 IAC_IISRx_ILACIN31_Msk /*!< illegal access input 31 (i = 0 to 31) */ /******************************************************************************/ /* */ /* RNG */ /* */ /******************************************************************************/ /******************** Bits definition for RNG_CR register *******************/ #define RNG_CR_RNGEN_Pos (2U) #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk #define RNG_CR_IE_Pos (3U) #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ #define RNG_CR_IE RNG_CR_IE_Msk #define RNG_CR_CED_Pos (5U) #define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ #define RNG_CR_CED RNG_CR_CED_Msk #define RNG_CR_ARDIS_Pos (7U) #define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) #define RNG_CR_ARDIS RNG_CR_ARDIS_Msk #define RNG_CR_RNG_CONFIG3_Pos (8U) #define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) #define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk #define RNG_CR_NISTC_Pos (12U) #define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) #define RNG_CR_NISTC RNG_CR_NISTC_Msk #define RNG_CR_RNG_CONFIG2_Pos (13U) #define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) #define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk #define RNG_CR_CLKDIV_Pos (16U) #define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) #define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk #define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ #define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ #define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ #define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20U) #define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) #define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk #define RNG_CR_CONDRST_Pos (30U) #define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) #define RNG_CR_CONDRST RNG_CR_CONDRST_Msk #define RNG_CR_CONFIGLOCK_Pos (31U) #define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) #define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /******************** Bits definition for RNG_SR register *******************/ #define RNG_SR_DRDY_Pos (0U) #define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ #define RNG_SR_DRDY RNG_SR_DRDY_Msk #define RNG_SR_CECS_Pos (1U) #define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ #define RNG_SR_CECS RNG_SR_CECS_Msk #define RNG_SR_SECS_Pos (2U) #define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ #define RNG_SR_SECS RNG_SR_SECS_Msk #define RNG_SR_CEIS_Pos (5U) #define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ #define RNG_SR_CEIS RNG_SR_CEIS_Msk #define RNG_SR_SEIS_Pos (6U) #define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ #define RNG_SR_SEIS RNG_SR_SEIS_Msk /******************** Bits definition for RNG_HTCR register *******************/ #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk /******************************************************************************/ /* */ /* Real-Time Clock (RTC) */ /* */ /******************************************************************************/ /******************** Bits definition for RTC_TR register *******************/ #define RTC_TR_SU_Pos (0U) #define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ #define RTC_TR_SU RTC_TR_SU_Msk #define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ #define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ #define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ #define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ #define RTC_TR_ST_Pos (4U) #define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ #define RTC_TR_ST RTC_TR_ST_Msk #define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ #define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ #define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ #define RTC_TR_MNU_Pos (8U) #define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_TR_MNU RTC_TR_MNU_Msk #define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ #define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ #define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ #define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ #define RTC_TR_MNT_Pos (12U) #define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ #define RTC_TR_MNT RTC_TR_MNT_Msk #define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ #define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ #define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ #define RTC_TR_HU_Pos (16U) #define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ #define RTC_TR_HU RTC_TR_HU_Msk #define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ #define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ #define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ #define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ #define RTC_TR_HT_Pos (20U) #define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ #define RTC_TR_HT RTC_TR_HT_Msk #define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ #define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ #define RTC_TR_PM_Pos (22U) #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ #define RTC_TR_PM RTC_TR_PM_Msk /******************** Bits definition for RTC_DR register *******************/ #define RTC_DR_DU_Pos (0U) #define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ #define RTC_DR_DU RTC_DR_DU_Msk #define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ #define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ #define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ #define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ #define RTC_DR_DT_Pos (4U) #define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ #define RTC_DR_DT RTC_DR_DT_Msk #define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ #define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ #define RTC_DR_MU_Pos (8U) #define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ #define RTC_DR_MU RTC_DR_MU_Msk #define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ #define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ #define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ #define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ #define RTC_DR_MT_Pos (12U) #define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ #define RTC_DR_MT RTC_DR_MT_Msk #define RTC_DR_WDU_Pos (13U) #define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ #define RTC_DR_WDU RTC_DR_WDU_Msk #define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ #define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ #define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ #define RTC_DR_YU_Pos (16U) #define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ #define RTC_DR_YU RTC_DR_YU_Msk #define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ #define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ #define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ #define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ #define RTC_DR_YT_Pos (20U) #define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ #define RTC_DR_YT RTC_DR_YT_Msk #define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ #define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ #define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ #define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ /******************** Bits definition for RTC_SSR register ******************/ #define RTC_SSR_SS_Pos (0U) #define RTC_SSR_SS_Msk (0xFFFFFFFFUL << RTC_SSR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_SSR_SS RTC_SSR_SS_Msk /******************** Bits definition for RTC_ICSR register ******************/ #define RTC_ICSR_WUTWF_Pos (2U) #define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ #define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk #define RTC_ICSR_SHPF_Pos (3U) #define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ #define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk #define RTC_ICSR_INITS_Pos (4U) #define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ #define RTC_ICSR_INITS RTC_ICSR_INITS_Msk #define RTC_ICSR_RSF_Pos (5U) #define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ #define RTC_ICSR_RSF RTC_ICSR_RSF_Msk #define RTC_ICSR_INITF_Pos (6U) #define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ #define RTC_ICSR_INITF RTC_ICSR_INITF_Msk #define RTC_ICSR_INIT_Pos (7U) #define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ #define RTC_ICSR_INIT RTC_ICSR_INIT_Msk #define RTC_ICSR_BIN_Pos (8U) #define RTC_ICSR_BIN_Msk (0x3UL << RTC_ICSR_BIN_Pos) /*!< 0x00000300 */ #define RTC_ICSR_BIN RTC_ICSR_BIN_Msk #define RTC_ICSR_BIN_0 (0x1UL << RTC_ICSR_BIN_Pos) /*!< 0x00000100 */ #define RTC_ICSR_BIN_1 (0x2UL << RTC_ICSR_BIN_Pos) /*!< 0x00000200 */ #define RTC_ICSR_BCDU_Pos (10U) #define RTC_ICSR_BCDU_Msk (0x7UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001C00 */ #define RTC_ICSR_BCDU RTC_ICSR_BCDU_Msk #define RTC_ICSR_BCDU_0 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000400 */ #define RTC_ICSR_BCDU_1 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000800 */ #define RTC_ICSR_BCDU_2 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001000 */ #define RTC_ICSR_RECALPF_Pos (16U) #define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ #define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk /******************** Bits definition for RTC_PRER register *****************/ #define RTC_PRER_PREDIV_S_Pos (0U) #define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk #define RTC_PRER_PREDIV_A_Pos (16U) #define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk /******************** Bits definition for RTC_WUTR register *****************/ #define RTC_WUTR_WUT_Pos (0U) #define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk #define RTC_WUTR_WUTOCLR_Pos (16U) #define RTC_WUTR_WUTOCLR_Msk (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos) /*!< 0x0000FFFF */ #define RTC_WUTR_WUTOCLR RTC_WUTR_WUTOCLR_Msk /******************** Bits definition for RTC_CR register *******************/ #define RTC_CR_WUCKSEL_Pos (0U) #define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk #define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ #define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ #define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ #define RTC_CR_TSEDGE_Pos (3U) #define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk #define RTC_CR_REFCKON_Pos (4U) #define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk #define RTC_CR_BYPSHAD_Pos (5U) #define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk #define RTC_CR_FMT_Pos (6U) #define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ #define RTC_CR_FMT RTC_CR_FMT_Msk #define RTC_CR_SSRUIE_Pos (7U) #define RTC_CR_SSRUIE_Msk (0x1UL << RTC_CR_SSRUIE_Pos) /*!< 0x00000080 */ #define RTC_CR_SSRUIE RTC_CR_SSRUIE_Msk #define RTC_CR_ALRAE_Pos (8U) #define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk #define RTC_CR_ALRBE_Pos (9U) #define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk #define RTC_CR_WUTE_Pos (10U) #define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ #define RTC_CR_WUTE RTC_CR_WUTE_Msk #define RTC_CR_TSE_Pos (11U) #define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ #define RTC_CR_TSE RTC_CR_TSE_Msk #define RTC_CR_ALRAIE_Pos (12U) #define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk #define RTC_CR_ALRBIE_Pos (13U) #define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk #define RTC_CR_WUTIE_Pos (14U) #define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk #define RTC_CR_TSIE_Pos (15U) #define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ #define RTC_CR_TSIE RTC_CR_TSIE_Msk #define RTC_CR_ADD1H_Pos (16U) #define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk #define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk #define RTC_CR_BKP_Pos (18U) #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ #define RTC_CR_BKP RTC_CR_BKP_Msk #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL RTC_CR_COSEL_Msk #define RTC_CR_POL_Pos (20U) #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ #define RTC_CR_POL RTC_CR_POL_Msk #define RTC_CR_OSEL_Pos (21U) #define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ #define RTC_CR_OSEL RTC_CR_OSEL_Msk #define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ #define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ #define RTC_CR_COE_Pos (23U) #define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ #define RTC_CR_COE RTC_CR_COE_Msk #define RTC_CR_ITSE_Pos (24U) #define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */ #define RTC_CR_ITSE RTC_CR_ITSE_Msk /*! */ /******************** Bits definition for RTC_ALRMAR register ***************/ #define RTC_ALRMAR_SU_Pos (0U) #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ #define RTC_ALRMAR_ST_Pos (4U) #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ #define RTC_ALRMAR_MSK1_Pos (7U) #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk #define RTC_ALRMAR_MNU_Pos (8U) #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ #define RTC_ALRMAR_MNT_Pos (12U) #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ #define RTC_ALRMAR_MSK2_Pos (15U) #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk #define RTC_ALRMAR_HU_Pos (16U) #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ #define RTC_ALRMAR_HT_Pos (20U) #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ #define RTC_ALRMAR_PM_Pos (22U) #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk #define RTC_ALRMAR_MSK3_Pos (23U) #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk #define RTC_ALRMAR_DU_Pos (24U) #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ #define RTC_ALRMAR_DT_Pos (28U) #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ #define RTC_ALRMAR_WDSEL_Pos (30U) #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk #define RTC_ALRMAR_MSK4_Pos (31U) #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ #define RTC_ALRMASSR_SS_Pos (0U) #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk #define RTC_ALRMASSR_MASKSS_Pos (24U) #define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ #define RTC_ALRMASSR_SSCLR_Pos (31U) #define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk /******************** Bits definition for RTC_ALRMBR register ***************/ #define RTC_ALRMBR_SU_Pos (0U) #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ #define RTC_ALRMBR_ST_Pos (4U) #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ #define RTC_ALRMBR_MSK1_Pos (7U) #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk #define RTC_ALRMBR_MNU_Pos (8U) #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ #define RTC_ALRMBR_MNT_Pos (12U) #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ #define RTC_ALRMBR_MSK2_Pos (15U) #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk #define RTC_ALRMBR_HU_Pos (16U) #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ #define RTC_ALRMBR_HT_Pos (20U) #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ #define RTC_ALRMBR_PM_Pos (22U) #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk #define RTC_ALRMBR_MSK3_Pos (23U) #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk #define RTC_ALRMBR_DU_Pos (24U) #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ #define RTC_ALRMBR_DT_Pos (28U) #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ #define RTC_ALRMBR_WDSEL_Pos (30U) #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk #define RTC_ALRMBR_MSK4_Pos (31U) #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ #define RTC_ALRMBSSR_SS_Pos (0U) #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk #define RTC_ALRMBSSR_MASKSS_Pos (24U) #define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ #define RTC_ALRMBSSR_SSCLR_Pos (31U) #define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk /******************** Bits definition for RTC_SR register *******************/ #define RTC_SR_ALRAF_Pos (0U) #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk #define RTC_SR_ALRBF_Pos (1U) #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk #define RTC_SR_WUTF_Pos (2U) #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ #define RTC_SR_WUTF RTC_SR_WUTF_Msk #define RTC_SR_TSF_Pos (3U) #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ #define RTC_SR_TSF RTC_SR_TSF_Msk #define RTC_SR_TSOVF_Pos (4U) #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk #define RTC_SR_ITSF_Pos (5U) #define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk #define RTC_SR_SSRUF_Pos (6U) #define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ #define RTC_SR_SSRUF RTC_SR_SSRUF_Msk /******************** Bits definition for RTC_MISR register *****************/ #define RTC_MISR_ALRAMF_Pos (0U) #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk #define RTC_MISR_ALRBMF_Pos (1U) #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk #define RTC_MISR_WUTMF_Pos (2U) #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk #define RTC_MISR_TSMF_Pos (3U) #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk #define RTC_MISR_TSOVMF_Pos (4U) #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk #define RTC_MISR_ITSMF_Pos (5U) #define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk #define RTC_MISR_SSRUMF_Pos (6U) #define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk /******************** Bits definition for RTC_SMISR register *****************/ #define RTC_SMISR_ALRAMF_Pos (0U) #define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk #define RTC_SMISR_ALRBMF_Pos (1U) #define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk #define RTC_SMISR_WUTMF_Pos (2U) #define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk #define RTC_SMISR_TSMF_Pos (3U) #define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk #define RTC_SMISR_TSOVMF_Pos (4U) #define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk #define RTC_SMISR_ITSMF_Pos (5U) #define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk #define RTC_SMISR_SSRUMF_Pos (6U) #define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk /******************** Bits definition for RTC_SCR register ******************/ #define RTC_SCR_CALRAF_Pos (0U) #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk #define RTC_SCR_CALRBF_Pos (1U) #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk #define RTC_SCR_CWUTF_Pos (2U) #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk #define RTC_SCR_CTSF_Pos (3U) #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk #define RTC_SCR_CTSOVF_Pos (4U) #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk #define RTC_SCR_CITSF_Pos (5U) #define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk #define RTC_SCR_CSSRUF_Pos (6U) #define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ #define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk /******************** Bits definition for RTC_ALRABINR register ******************/ #define RTC_ALRABINR_SS_Pos (0U) #define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk /******************** Bits definition for RTC_ALRBBINR register ******************/ #define RTC_ALRBBINR_SS_Pos (0U) #define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk /******************************************************************************/ /* */ /* Secure Advanced Encryption Standard (SAES) */ /* */ /******************************************************************************/ /******************* Bits definition for SAES_CR register *********************/ #define SAES_CR_EN_Pos (0U) #define SAES_CR_EN_Msk (0x1UL << SAES_CR_EN_Pos) /*!< 0x00000001 */ #define SAES_CR_EN SAES_CR_EN_Msk /*!< SAES Enable */ #define SAES_CR_DATATYPE_Pos (1U) #define SAES_CR_DATATYPE_Msk (0x3UL << SAES_CR_DATATYPE_Pos) /*!< 0x00000006 */ #define SAES_CR_DATATYPE SAES_CR_DATATYPE_Msk /*!< Data type selection */ #define SAES_CR_DATATYPE_0 (0x1UL << SAES_CR_DATATYPE_Pos) /*!< 0x00000002 */ #define SAES_CR_DATATYPE_1 (0x2UL << SAES_CR_DATATYPE_Pos) /*!< 0x00000004 */ #define SAES_CR_MODE_Pos (3U) #define SAES_CR_MODE_Msk (0x3UL << SAES_CR_MODE_Pos) /*!< 0x00000018 */ #define SAES_CR_MODE SAES_CR_MODE_Msk /*!< SAES Mode Of Operation */ #define SAES_CR_MODE_0 (0x1UL << SAES_CR_MODE_Pos) /*!< 0x00000008 */ #define SAES_CR_MODE_1 (0x2UL << SAES_CR_MODE_Pos) /*!< 0x00000010 */ #define SAES_CR_CHMOD_Pos (5U) #define SAES_CR_CHMOD_Msk (0x803UL << SAES_CR_CHMOD_Pos) /*!< 0x00010060 */ #define SAES_CR_CHMOD SAES_CR_CHMOD_Msk /*!< SAES Chaining Mode */ #define SAES_CR_CHMOD_0 (0x1UL << SAES_CR_CHMOD_Pos) /*!< 0x00000020*/ #define SAES_CR_CHMOD_1 (0x2UL << SAES_CR_CHMOD_Pos) /*!< 0x00000040 */ #define SAES_CR_CHMOD_2 (0x800UL << SAES_CR_CHMOD_Pos) /*!< 0x00010000 */ #define SAES_CR_DMAINEN_Pos (11U) #define SAES_CR_DMAINEN_Msk (0x1UL << SAES_CR_DMAINEN_Pos) /*!< 0x00000800 */ #define SAES_CR_DMAINEN SAES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */ #define SAES_CR_DMAOUTEN_Pos (12U) #define SAES_CR_DMAOUTEN_Msk (0x1UL << SAES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */ #define SAES_CR_DMAOUTEN SAES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */ #define SAES_CR_GCMPH_Pos (13U) #define SAES_CR_GCMPH_Msk (0x3UL << SAES_CR_GCMPH_Pos) /*!< 0x0006000 */ #define SAES_CR_GCMPH SAES_CR_GCMPH_Msk /*!< GCM or CCM phase selection */ #define SAES_CR_GCMPH_0 (0x1UL << SAES_CR_GCMPH_Pos) /*!< 0x00020000 */ #define SAES_CR_GCMPH_1 (0x2UL << SAES_CR_GCMPH_Pos) /*!< 0x00040000 */ #define SAES_CR_KEYSIZE_Pos (18U) #define SAES_CR_KEYSIZE_Msk (0x1UL << SAES_CR_KEYSIZE_Pos) /*!< 0x00040000 */ #define SAES_CR_KEYSIZE SAES_CR_KEYSIZE_Msk /*!< Key size selection */ #define SAES_CR_KEYPROT_Pos (19U) #define SAES_CR_KEYPROT_Msk (0x1UL << SAES_CR_KEYPROT_Pos) /*!< 0x00080000 */ #define SAES_CR_KEYPROT SAES_CR_KEYPROT_Msk /*!< Key protection */ #define SAES_CR_NPBLB_Pos (20U) #define SAES_CR_NPBLB_Msk (0xFUL << SAES_CR_NPBLB_Pos) /*!< 0x00F00000 */ #define SAES_CR_NPBLB SAES_CR_NPBLB_Msk /*!< Number of padding bytes in last block */ #define SAES_CR_NPBLB_0 (0x1UL << SAES_CR_NPBLB_Pos) /*!< 0x00100000 */ #define SAES_CR_NPBLB_1 (0x2UL << SAES_CR_NPBLB_Pos) /*!< 0x00200000 */ #define SAES_CR_NPBLB_2 (0x4UL << SAES_CR_NPBLB_Pos) /*!< 0x00400000 */ #define SAES_CR_NPBLB_3 (0x8UL << SAES_CR_NPBLB_Pos) /*!< 0x00800000 */ #define SAES_CR_KMOD_Pos (24U) #define SAES_CR_KMOD_Msk (0x3UL << SAES_CR_KMOD_Pos) /*!< 0x03000000 */ #define SAES_CR_KMOD SAES_CR_KMOD_Msk /*!< Key mode selection */ #define SAES_CR_KMOD_0 (0x1UL << SAES_CR_KMOD_Pos) /*!< 0x01000000 */ #define SAES_CR_KMOD_1 (0x2UL << SAES_CR_KMOD_Pos) /*!< 0x02000000 */ #define SAES_CR_KSHAREID_Pos (26U) #define SAES_CR_KSHAREID_Msk (0x3UL << SAES_CR_KSHAREID_Pos) /*!< 0x0C000000 */ #define SAES_CR_KSHAREID SAES_CR_KSHAREID_Msk /*!< Key Shared ID */ #define SAES_CR_KSHAREID_0 (0x1UL << SAES_CR_KSHAREID_Pos) /*!< 0x04000000 */ #define SAES_CR_KSHAREID_1 (0x2UL << SAES_CR_KSHAREID_Pos) /*!< 0x08000000 */ #define SAES_CR_KEYSEL_Pos (28U) #define SAES_CR_KEYSEL_Msk (0x7UL << SAES_CR_KEYSEL_Pos) /*!< 0x70000000 */ #define SAES_CR_KEYSEL SAES_CR_KEYSEL_Msk /*!< Key Selection */ #define SAES_CR_KEYSEL_0 (0x1UL << SAES_CR_KEYSEL_Pos) /*!< 0x10000000 */ #define SAES_CR_KEYSEL_1 (0x2UL << SAES_CR_KEYSEL_Pos) /*!< 0x20000000 */ #define SAES_CR_KEYSEL_2 (0x4UL << SAES_CR_KEYSEL_Pos) /*!< 0x40000000 */ #define SAES_CR_IPRST_Pos (31U) #define SAES_CR_IPRST_Msk (0x1UL << SAES_CR_IPRST_Pos) /*!< 0x80000000 */ #define SAES_CR_IPRST SAES_CR_IPRST_Msk /*!< SAES IP software reset */ /******************* Bits definition for SAES_SR register *********************/ #define SAES_SR_CCF_Pos (0U) #define SAES_SR_CCF_Msk (0x1UL << SAES_SR_CCF_Pos) /*!< 0x00000001 */ #define SAES_SR_CCF SAES_SR_CCF_Msk /*!< Computation Complete Flag */ #define SAES_SR_RDERR_Pos (1U) #define SAES_SR_RDERR_Msk (0x1UL << SAES_SR_RDERR_Pos) /*!< 0x00000002 */ #define SAES_SR_RDERR SAES_SR_RDERR_Msk /*!< Read Error Flag */ #define SAES_SR_WRERR_Pos (2U) #define SAES_SR_WRERR_Msk (0x1UL << SAES_SR_WRERR_Pos) /*!< 0x00000004 */ #define SAES_SR_WRERR SAES_SR_WRERR_Msk /*!< Write Error Flag */ #define SAES_SR_BUSY_Pos (3U) #define SAES_SR_BUSY_Msk (0x1UL << SAES_SR_BUSY_Pos) /*!< 0x00000008 */ #define SAES_SR_BUSY SAES_SR_BUSY_Msk /*!< Busy Flag */ #define SAES_SR_KEYVALID_Pos (7U) #define SAES_SR_KEYVALID_Msk (0x1UL << SAES_SR_KEYVALID_Pos) /*!< 0x00000080 */ #define SAES_SR_KEYVALID SAES_SR_KEYVALID_Msk /*!< Key valid Flag */ /******************* Bits definition for SAES_DINR register *******************/ #define SAES_DINR_Pos (0U) #define SAES_DINR_Msk (0xFFFFFFFFUL << SAES_DINR_Pos) /*!< 0xFFFFFFFF */ #define SAES_DINR SAES_DINR_Msk /*!< SAES Data Input Register */ /******************* Bits definition for SAES_DOUTR register ******************/ #define SAES_DOUTR_Pos (0U) #define SAES_DOUTR_Msk (0xFFFFFFFFUL << SAES_DOUTR_Pos) /*!< 0xFFFFFFFF */ #define SAES_DOUTR SAES_DOUTR_Msk /*!< SAES Data Output Register */ /******************* Bits definition for SAES_KEYR0 register ******************/ #define SAES_KEYR0_Pos (0U) #define SAES_KEYR0_Msk (0xFFFFFFFFUL << SAES_KEYR0_Pos) /*!< 0xFFFFFFFF */ #define SAES_KEYR0 SAES_KEYR0_Msk /*!< SAES cryptographic key, bits [31:0] */ /******************* Bits definition for SAES_KEYR1 register ******************/ #define SAES_KEYR1_Pos (0U) #define SAES_KEYR1_Msk (0xFFFFFFFFUL << SAES_KEYR1_Pos) /*!< 0xFFFFFFFF */ #define SAES_KEYR1 SAES_KEYR1_Msk /*!< SAES cryptographic key, bits [63:32] */ /******************* Bits definition for SAES_KEYR2 register ******************/ #define SAES_KEYR2_Pos (0U) #define SAES_KEYR2_Msk (0xFFFFFFFFUL << SAES_KEYR2_Pos) /*!< 0xFFFFFFFF */ #define SAES_KEYR2 SAES_KEYR2_Msk /*!< SAES cryptographic key, bits [95:64] */ /******************* Bits definition for SAES_KEYR3 register ******************/ #define SAES_KEYR3_Pos (0U) #define SAES_KEYR3_Msk (0xFFFFFFFFUL << SAES_KEYR3_Pos) /*!< 0xFFFFFFFF */ #define SAES_KEYR3 SAES_KEYR3_Msk /*!< SAES cryptographic key, bits [127:96] */ /******************* Bits definition for SAES_KEYR4 register ******************/ #define SAES_KEYR4_Pos (0U) #define SAES_KEYR4_Msk (0xFFFFFFFFUL << SAES_KEYR4_Pos) /*!< 0xFFFFFFFF */ #define SAES_KEYR4 SAES_KEYR4_Msk /*!< SAES cryptographic key, bits [127:96] */ /******************* Bits definition for SAES_KEYR5 register ******************/ #define SAES_KEYR5_Pos (0U) #define SAES_KEYR5_Msk (0xFFFFFFFFUL << SAES_KEYR5_Pos) /*!< 0xFFFFFFFF */ #define SAES_KEYR5 SAES_KEYR5_Msk /*!< SAES cryptographic key, bits [127:96] */ /******************* Bits definition for SAES_KEYR6 register ******************/ #define SAES_KEYR6_Pos (0U) #define SAES_KEYR6_Msk (0xFFFFFFFFUL << SAES_KEYR6_Pos) /*!< 0xFFFFFFFF */ #define SAES_KEYR6 SAES_KEYR6_Msk /*!< SAES cryptographic key, bits [127:96] */ /******************* Bits definition for SAES_KEYR7 register ******************/ #define SAES_KEYR7_Pos (0U) #define SAES_KEYR7_Msk (0xFFFFFFFFUL << SAES_KEYR7_Pos) /*!< 0xFFFFFFFF */ #define SAES_KEYR7 SAES_KEYR7_Msk /*!< SAES cryptographic key, bits [127:96] */ /******************* Bits definition for SAES_IVR0 register ******************/ #define SAES_IVR0_Pos (0U) #define SAES_IVR0_Msk (0xFFFFFFFFUL << SAES_IVR0_Pos) /*!< 0xFFFFFFFF */ #define SAES_IVR0 SAES_IVR0_Msk /*!< SAES initialization vector input, bits [31:0] */ /******************* Bits definition for SAES_IVR1 register ******************/ #define SAES_IVR1_Pos (0U) #define SAES_IVR1_Msk (0xFFFFFFFFUL << SAES_IVR1_Pos) /*!< 0xFFFFFFFF */ #define SAES_IVR1 SAES_IVR1_Msk /*!< SAES initialization vector input, bits [63:32] */ /******************* Bits definition for SAES_IVR2 register ******************/ #define SAES_IVR2_Pos (0U) #define SAES_IVR2_Msk (0xFFFFFFFFUL << SAES_IVR2_Pos) /*!< 0xFFFFFFFF */ #define SAES_IVR2 SAES_IVR2_Msk /*!< SAES initialization vector input, bits [95:64] */ /******************* Bits definition for SAES_IVR3 register ******************/ #define SAES_IVR3_Pos (0U) #define SAES_IVR3_Msk (0xFFFFFFFFUL << SAES_IVR3_Pos) /*!< 0xFFFFFFFF */ #define SAES_IVR3 SAES_IVR3_Msk /*!< SAES initialization vector input, bits [127:96] */ /******************* Bits definition for SAES_DPACFGR register ******************/ #define SAES_DPACFGR_REDCFG_Pos (0U) #define SAES_DPACFGR_REDCFG_Msk (0x3UL << SAES_DPACFGR_REDCFG_Pos) /*!< 0x00000003 */ #define SAES_DPACFGR_REDCFG SAES_DPACFGR_REDCFG_Msk /*!< Redundancy configuration*/ #define SAES_DPACFGR_REDCFG_0 (0x1UL << SAES_DPACFGR_REDCFG_Pos) /*!< 0x00000001 */ #define SAES_DPACFGR_REDCFG_1 (0x2UL << SAES_DPACFGR_REDCFG_Pos) /*!< 0x00000002 */ #define SAES_DPACFGR_RESEED_Pos (2U) #define SAES_DPACFGR_RESEED_Msk (0x1UL << SAES_DPACFGR_RESEED_Pos) /*!< 0x00000004 */ #define SAES_DPACFGR_RESEED SAES_DPACFGR_RESEED_Msk /*!< Automatic reseed enable */ #define SAES_DPACFGR_TRIMCFG_Pos (3U) #define SAES_DPACFGR_TRIMCFG_Msk (0x3UL << SAES_DPACFGR_TRIMCFG_Pos) /*!< 0x00000018 */ #define SAES_DPACFGR_TRIMCFG SAES_DPACFGR_TRIMCFG_Msk /*!< Clock trimming */ #define SAES_DPACFGR_TRIMCFG_0 (0x1UL << SAES_DPACFGR_TRIMCFG_Pos) /*!< 0x00000008 */ #define SAES_DPACFGR_TRIMCFG_1 (0x2UL << SAES_DPACFGR_TRIMCFG_Pos) /*!< 0x00000010 */ #define SAES_DPACFGR_CONFIGLOCK_Pos (31U) #define SAES_DPACFGR_CONFIGLOCK_Msk (0x1UL << SAES_DPACFGR_CONFIGLOCK_Pos) /*!< 0x80000000 */ #define SAES_DPACFGR_CONFIGLOCK SAES_DPACFGR_CONFIGLOCK_Msk /*!< DPA configuration lock */ /******************* Bits definition for SAES_IER register ******************/ #define SAES_IER_CCFIE_Pos (0U) #define SAES_IER_CCFIE_Msk (0x1UL << SAES_IER_CCFIE_Pos) /*!< 0x00000001 */ #define SAES_IER_CCFIE SAES_IER_CCFIE_Msk /*!< Computation complete flag interrupt enable */ #define SAES_IER_RWEIE_Pos (1U) #define SAES_IER_RWEIE_Msk (0x1UL << SAES_IER_RWEIE_Pos) /*!< 0x00000002 */ #define SAES_IER_RWEIE SAES_IER_RWEIE_Msk /*!< Read or write error Interrupt Enable */ #define SAES_IER_KEIE_Pos (2U) #define SAES_IER_KEIE_Msk (0x1UL << SAES_IER_KEIE_Pos) /*!< 0x00000004 */ #define SAES_IER_KEIE SAES_IER_KEIE_Msk /*!< Key error interrupt enable */ #define SAES_IER_RNGEIE_Pos (3U) #define SAES_IER_RNGEIE_Msk (0x1UL << SAES_IER_RNGEIE_Pos) /*!< 0x00000008 */ #define SAES_IER_RNGEIE SAES_IER_RNGEIE_Msk /*!< RNG error interrupt enable */ /******************* Bits definition for SAES_ISR register ******************/ #define SAES_ISR_CCF_Pos (0U) #define SAES_ISR_CCF_Msk (0x1UL << SAES_ISR_CCF_Pos) /*!< 0x00000001 */ #define SAES_ISR_CCF SAES_ISR_CCF_Msk /*!< Computation complete flag */ #define SAES_ISR_RWEIF_Pos (1U) #define SAES_ISR_RWEIF_Msk (0x1UL << SAES_ISR_RWEIF_Pos) /*!< 0x00000002 */ #define SAES_ISR_RWEIF SAES_ISR_RWEIF_Msk /*!< Read or write error Interrupt flag */ #define SAES_ISR_KEIF_Pos (2U) #define SAES_ISR_KEIF_Msk (0x1UL << SAES_ISR_KEIF_Pos) /*!< 0x00000004 */ #define SAES_ISR_KEIF SAES_ISR_KEIF_Msk /*!< Key error interrupt flag */ #define SAES_ISR_RNGEIF_Pos (3U) #define SAES_ISR_RNGEIF_Msk (0x1UL << SAES_ISR_RNGEIF_Pos) /*!< 0x00000008 */ #define SAES_ISR_RNGEIF SAES_ISR_RNGEIF_Msk /*!< RNG error interrupt flag */ /******************* Bits definition for SAES_ICR register ******************/ #define SAES_ICR_CCF_Pos (0U) #define SAES_ICR_CCF_Msk (0x1UL << SAES_ICR_CCF_Pos) /*!< 0x00000001 */ #define SAES_ICR_CCF SAES_ICR_CCF_Msk /*!< Computation complete flag clear */ #define SAES_ICR_RWEIF_Pos (1U) #define SAES_ICR_RWEIF_Msk (0x1UL << SAES_ICR_RWEIF_Pos) /*!< 0x00000002 */ #define SAES_ICR_RWEIF SAES_ICR_RWEIF_Msk /*!< Read or write error Interrupt flag clear */ #define SAES_ICR_KEIF_Pos (2U) #define SAES_ICR_KEIF_Msk (0x1UL << SAES_ICR_KEIF_Pos) /*!< 0x00000004 */ #define SAES_ICR_KEIF SAES_ICR_KEIF_Msk /*!< Key error interrupt flag clear */ #define SAES_ICR_RNGEIF_Pos (3U) #define SAES_ICR_RNGEIF_Msk (0x1UL << SAES_ICR_RNGEIF_Pos) /*!< 0x00000008 */ #define SAES_ICR_RNGEIF SAES_ICR_RNGEIF_Msk /*!< RNG error interrupt flag clear */ /******************************************************************************/ /* */ /* Serial Audio Interface */ /* */ /******************************************************************************/ /******************** Bit definition for SAI_GCR register *******************/ #define SAI_GCR_SYNCIN_Pos (0U) #define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */ #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!