1 /**
2 ******************************************************************************
3 * @file stm32f3xx_hal_tim.c
4 * @author MCD Application Team
5 * @brief TIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Timer (TIM) peripheral:
8 * + TIM Time Base Initialization
9 * + TIM Time Base Start
10 * + TIM Time Base Start Interruption
11 * + TIM Time Base Start DMA
12 * + TIM Output Compare/PWM Initialization
13 * + TIM Output Compare/PWM Channel Configuration
14 * + TIM Output Compare/PWM Start
15 * + TIM Output Compare/PWM Start Interruption
16 * + TIM Output Compare/PWM Start DMA
17 * + TIM Input Capture Initialization
18 * + TIM Input Capture Channel Configuration
19 * + TIM Input Capture Start
20 * + TIM Input Capture Start Interruption
21 * + TIM Input Capture Start DMA
22 * + TIM One Pulse Initialization
23 * + TIM One Pulse Channel Configuration
24 * + TIM One Pulse Start
25 * + TIM Encoder Interface Initialization
26 * + TIM Encoder Interface Start
27 * + TIM Encoder Interface Start Interruption
28 * + TIM Encoder Interface Start DMA
29 * + Commutation Event configuration with Interruption and DMA
30 * + TIM OCRef clear configuration
31 * + TIM External Clock configuration
32 ******************************************************************************
33 * @attention
34 *
35 * Copyright (c) 2016 STMicroelectronics.
36 * All rights reserved.
37 *
38 * This software is licensed under terms that can be found in the LICENSE file
39 * in the root directory of this software component.
40 * If no LICENSE file comes with this software, it is provided AS-IS.
41 *
42 ******************************************************************************
43 @verbatim
44 ==============================================================================
45 ##### TIMER Generic features #####
46 ==============================================================================
47 [..] The Timer features include:
48 (#) 16-bit up, down, up/down auto-reload counter.
49 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
50 counter clock frequency either by any factor between 1 and 65536.
51 (#) Up to 4 independent channels for:
52 (++) Input Capture
53 (++) Output Compare
54 (++) PWM generation (Edge and Center-aligned Mode)
55 (++) One-pulse mode output
56 (#) Synchronization circuit to control the timer with external signals and to interconnect
57 several timers together.
58 (#) Supports incremental encoder for positioning purposes
59
60 ##### How to use this driver #####
61 ==============================================================================
62 [..]
63 (#) Initialize the TIM low level resources by implementing the following functions
64 depending on the selected feature:
65 (++) Time Base : HAL_TIM_Base_MspInit()
66 (++) Input Capture : HAL_TIM_IC_MspInit()
67 (++) Output Compare : HAL_TIM_OC_MspInit()
68 (++) PWM generation : HAL_TIM_PWM_MspInit()
69 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
70 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
71
72 (#) Initialize the TIM low level resources :
73 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
74 (##) TIM pins configuration
75 (+++) Enable the clock for the TIM GPIOs using the following function:
76 __HAL_RCC_GPIOx_CLK_ENABLE();
77 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
78
79 (#) The external Clock can be configured, if needed (the default clock is the
80 internal clock from the APBx), using the following function:
81 HAL_TIM_ConfigClockSource, the clock configuration should be done before
82 any start function.
83
84 (#) Configure the TIM in the desired functioning mode using one of the
85 Initialization function of this driver:
86 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
87 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
88 Output Compare signal.
89 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
90 PWM signal.
91 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
92 external signal.
93 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
94 in One Pulse Mode.
95 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
96
97 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
98 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
99 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
100 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
101 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
102 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
103 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
104
105 (#) The DMA Burst is managed with the two following functions:
106 HAL_TIM_DMABurst_WriteStart()
107 HAL_TIM_DMABurst_ReadStart()
108
109 *** Callback registration ***
110 =============================================
111
112 [..]
113 The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
114 allows the user to configure dynamically the driver callbacks.
115
116 [..]
117 Use Function HAL_TIM_RegisterCallback() to register a callback.
118 HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
119 the Callback ID and a pointer to the user callback function.
120
121 [..]
122 Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default
123 weak function.
124 HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
125 and the Callback ID.
126
127 [..]
128 These functions allow to register/unregister following callbacks:
129 (+) Base_MspInitCallback : TIM Base Msp Init Callback.
130 (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.
131 (+) IC_MspInitCallback : TIM IC Msp Init Callback.
132 (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback.
133 (+) OC_MspInitCallback : TIM OC Msp Init Callback.
134 (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback.
135 (+) PWM_MspInitCallback : TIM PWM Msp Init Callback.
136 (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback.
137 (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback.
138 (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback.
139 (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback.
140 (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback.
141 (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback.
142 (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback.
143 (+) PeriodElapsedCallback : TIM Period Elapsed Callback.
144 (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback.
145 (+) TriggerCallback : TIM Trigger Callback.
146 (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback.
147 (+) IC_CaptureCallback : TIM Input Capture Callback.
148 (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback.
149 (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback.
150 (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback.
151 (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
152 (+) ErrorCallback : TIM Error Callback.
153 (+) CommutationCallback : TIM Commutation Callback.
154 (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback.
155 (+) BreakCallback : TIM Break Callback.
156 (+) Break2Callback : TIM Break2 Callback (when supported).
157
158 [..]
159 By default, after the Init and when the state is HAL_TIM_STATE_RESET
160 all interrupt callbacks are set to the corresponding weak functions:
161 examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback().
162
163 [..]
164 Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
165 functionalities in the Init / DeInit only when these callbacks are null
166 (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
167 keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
168
169 [..]
170 Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
171 Exception done MspInit / MspDeInit that can be registered / unregistered
172 in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
173 thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
174 In that case first register the MspInit/MspDeInit user callbacks
175 using HAL_TIM_RegisterCallback() before calling DeInit or Init function.
176
177 [..]
178 When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
179 not defined, the callback registration feature is not available and all callbacks
180 are set to the corresponding weak functions.
181
182 @endverbatim
183 ******************************************************************************
184 */
185
186 /* Includes ------------------------------------------------------------------*/
187 #include "stm32f3xx_hal.h"
188
189 /** @addtogroup STM32F3xx_HAL_Driver
190 * @{
191 */
192
193 /** @defgroup TIM TIM
194 * @brief TIM HAL module driver
195 * @{
196 */
197
198 #ifdef HAL_TIM_MODULE_ENABLED
199
200 /* Private typedef -----------------------------------------------------------*/
201 /* Private define ------------------------------------------------------------*/
202 /* Private macros ------------------------------------------------------------*/
203 /* Private variables ---------------------------------------------------------*/
204 /* Private function prototypes -----------------------------------------------*/
205 /** @addtogroup TIM_Private_Functions
206 * @{
207 */
208 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
209 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
210 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
211 #if defined(TIM_CCER_CC5E)
212 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
213 #endif /* TIM_CCER_CC5E */
214 #if defined(TIM_CCER_CC6E)
215 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
216 #endif /* TIM_CCER_CC6E */
217 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
218 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
219 uint32_t TIM_ICFilter);
220 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
221 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
222 uint32_t TIM_ICFilter);
223 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
224 uint32_t TIM_ICFilter);
225 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
226 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
227 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
228 static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
229 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
230 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
231 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
232 const TIM_SlaveConfigTypeDef *sSlaveConfig);
233 /**
234 * @}
235 */
236 /* Exported functions --------------------------------------------------------*/
237
238 /** @defgroup TIM_Exported_Functions TIM Exported Functions
239 * @{
240 */
241
242 /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
243 * @brief Time Base functions
244 *
245 @verbatim
246 ==============================================================================
247 ##### Time Base functions #####
248 ==============================================================================
249 [..]
250 This section provides functions allowing to:
251 (+) Initialize and configure the TIM base.
252 (+) De-initialize the TIM base.
253 (+) Start the Time Base.
254 (+) Stop the Time Base.
255 (+) Start the Time Base and enable interrupt.
256 (+) Stop the Time Base and disable interrupt.
257 (+) Start the Time Base and enable DMA transfer.
258 (+) Stop the Time Base and disable DMA transfer.
259
260 @endverbatim
261 * @{
262 */
263 /**
264 * @brief Initializes the TIM Time base Unit according to the specified
265 * parameters in the TIM_HandleTypeDef and initialize the associated handle.
266 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
267 * requires a timer reset to avoid unexpected direction
268 * due to DIR bit readonly in center aligned mode.
269 * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
270 * @param htim TIM Base handle
271 * @retval HAL status
272 */
HAL_TIM_Base_Init(TIM_HandleTypeDef * htim)273 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
274 {
275 /* Check the TIM handle allocation */
276 if (htim == NULL)
277 {
278 return HAL_ERROR;
279 }
280
281 /* Check the parameters */
282 assert_param(IS_TIM_INSTANCE(htim->Instance));
283 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
284 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
285 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
286 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
287
288 if (htim->State == HAL_TIM_STATE_RESET)
289 {
290 /* Allocate lock resource and initialize it */
291 htim->Lock = HAL_UNLOCKED;
292
293 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
294 /* Reset interrupt callbacks to legacy weak callbacks */
295 TIM_ResetCallback(htim);
296
297 if (htim->Base_MspInitCallback == NULL)
298 {
299 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
300 }
301 /* Init the low level hardware : GPIO, CLOCK, NVIC */
302 htim->Base_MspInitCallback(htim);
303 #else
304 /* Init the low level hardware : GPIO, CLOCK, NVIC */
305 HAL_TIM_Base_MspInit(htim);
306 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
307 }
308
309 /* Set the TIM state */
310 htim->State = HAL_TIM_STATE_BUSY;
311
312 /* Set the Time Base configuration */
313 TIM_Base_SetConfig(htim->Instance, &htim->Init);
314
315 /* Initialize the DMA burst operation state */
316 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
317
318 /* Initialize the TIM channels state */
319 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
320 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
321
322 /* Initialize the TIM state*/
323 htim->State = HAL_TIM_STATE_READY;
324
325 return HAL_OK;
326 }
327
328 /**
329 * @brief DeInitializes the TIM Base peripheral
330 * @param htim TIM Base handle
331 * @retval HAL status
332 */
HAL_TIM_Base_DeInit(TIM_HandleTypeDef * htim)333 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
334 {
335 /* Check the parameters */
336 assert_param(IS_TIM_INSTANCE(htim->Instance));
337
338 htim->State = HAL_TIM_STATE_BUSY;
339
340 /* Disable the TIM Peripheral Clock */
341 __HAL_TIM_DISABLE(htim);
342
343 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
344 if (htim->Base_MspDeInitCallback == NULL)
345 {
346 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
347 }
348 /* DeInit the low level hardware */
349 htim->Base_MspDeInitCallback(htim);
350 #else
351 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
352 HAL_TIM_Base_MspDeInit(htim);
353 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
354
355 /* Change the DMA burst operation state */
356 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
357
358 /* Change the TIM channels state */
359 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
360 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
361
362 /* Change TIM state */
363 htim->State = HAL_TIM_STATE_RESET;
364
365 /* Release Lock */
366 __HAL_UNLOCK(htim);
367
368 return HAL_OK;
369 }
370
371 /**
372 * @brief Initializes the TIM Base MSP.
373 * @param htim TIM Base handle
374 * @retval None
375 */
HAL_TIM_Base_MspInit(TIM_HandleTypeDef * htim)376 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
377 {
378 /* Prevent unused argument(s) compilation warning */
379 UNUSED(htim);
380
381 /* NOTE : This function should not be modified, when the callback is needed,
382 the HAL_TIM_Base_MspInit could be implemented in the user file
383 */
384 }
385
386 /**
387 * @brief DeInitializes TIM Base MSP.
388 * @param htim TIM Base handle
389 * @retval None
390 */
HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef * htim)391 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
392 {
393 /* Prevent unused argument(s) compilation warning */
394 UNUSED(htim);
395
396 /* NOTE : This function should not be modified, when the callback is needed,
397 the HAL_TIM_Base_MspDeInit could be implemented in the user file
398 */
399 }
400
401
402 /**
403 * @brief Starts the TIM Base generation.
404 * @param htim TIM Base handle
405 * @retval HAL status
406 */
HAL_TIM_Base_Start(TIM_HandleTypeDef * htim)407 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
408 {
409 uint32_t tmpsmcr;
410
411 /* Check the parameters */
412 assert_param(IS_TIM_INSTANCE(htim->Instance));
413
414 /* Check the TIM state */
415 if (htim->State != HAL_TIM_STATE_READY)
416 {
417 return HAL_ERROR;
418 }
419
420 /* Set the TIM state */
421 htim->State = HAL_TIM_STATE_BUSY;
422
423 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
424 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
425 {
426 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
427 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
428 {
429 __HAL_TIM_ENABLE(htim);
430 }
431 }
432 else
433 {
434 __HAL_TIM_ENABLE(htim);
435 }
436
437 /* Return function status */
438 return HAL_OK;
439 }
440
441 /**
442 * @brief Stops the TIM Base generation.
443 * @param htim TIM Base handle
444 * @retval HAL status
445 */
HAL_TIM_Base_Stop(TIM_HandleTypeDef * htim)446 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
447 {
448 /* Check the parameters */
449 assert_param(IS_TIM_INSTANCE(htim->Instance));
450
451 /* Disable the Peripheral */
452 __HAL_TIM_DISABLE(htim);
453
454 /* Set the TIM state */
455 htim->State = HAL_TIM_STATE_READY;
456
457 /* Return function status */
458 return HAL_OK;
459 }
460
461 /**
462 * @brief Starts the TIM Base generation in interrupt mode.
463 * @param htim TIM Base handle
464 * @retval HAL status
465 */
HAL_TIM_Base_Start_IT(TIM_HandleTypeDef * htim)466 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
467 {
468 uint32_t tmpsmcr;
469
470 /* Check the parameters */
471 assert_param(IS_TIM_INSTANCE(htim->Instance));
472
473 /* Check the TIM state */
474 if (htim->State != HAL_TIM_STATE_READY)
475 {
476 return HAL_ERROR;
477 }
478
479 /* Set the TIM state */
480 htim->State = HAL_TIM_STATE_BUSY;
481
482 /* Enable the TIM Update interrupt */
483 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
484
485 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
486 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
487 {
488 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
489 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
490 {
491 __HAL_TIM_ENABLE(htim);
492 }
493 }
494 else
495 {
496 __HAL_TIM_ENABLE(htim);
497 }
498
499 /* Return function status */
500 return HAL_OK;
501 }
502
503 /**
504 * @brief Stops the TIM Base generation in interrupt mode.
505 * @param htim TIM Base handle
506 * @retval HAL status
507 */
HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef * htim)508 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
509 {
510 /* Check the parameters */
511 assert_param(IS_TIM_INSTANCE(htim->Instance));
512
513 /* Disable the TIM Update interrupt */
514 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
515
516 /* Disable the Peripheral */
517 __HAL_TIM_DISABLE(htim);
518
519 /* Set the TIM state */
520 htim->State = HAL_TIM_STATE_READY;
521
522 /* Return function status */
523 return HAL_OK;
524 }
525
526 /**
527 * @brief Starts the TIM Base generation in DMA mode.
528 * @param htim TIM Base handle
529 * @param pData The source Buffer address.
530 * @param Length The length of data to be transferred from memory to peripheral.
531 * @retval HAL status
532 */
HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef * htim,const uint32_t * pData,uint16_t Length)533 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length)
534 {
535 uint32_t tmpsmcr;
536
537 /* Check the parameters */
538 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
539
540 /* Set the TIM state */
541 if (htim->State == HAL_TIM_STATE_BUSY)
542 {
543 return HAL_BUSY;
544 }
545 else if (htim->State == HAL_TIM_STATE_READY)
546 {
547 if ((pData == NULL) || (Length == 0U))
548 {
549 return HAL_ERROR;
550 }
551 else
552 {
553 htim->State = HAL_TIM_STATE_BUSY;
554 }
555 }
556 else
557 {
558 return HAL_ERROR;
559 }
560
561 /* Set the DMA Period elapsed callbacks */
562 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
563 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
564
565 /* Set the DMA error callback */
566 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
567
568 /* Enable the DMA channel */
569 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR,
570 Length) != HAL_OK)
571 {
572 /* Return error status */
573 return HAL_ERROR;
574 }
575
576 /* Enable the TIM Update DMA request */
577 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
578
579 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
580 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
581 {
582 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
583 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
584 {
585 __HAL_TIM_ENABLE(htim);
586 }
587 }
588 else
589 {
590 __HAL_TIM_ENABLE(htim);
591 }
592
593 /* Return function status */
594 return HAL_OK;
595 }
596
597 /**
598 * @brief Stops the TIM Base generation in DMA mode.
599 * @param htim TIM Base handle
600 * @retval HAL status
601 */
HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef * htim)602 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
603 {
604 /* Check the parameters */
605 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
606
607 /* Disable the TIM Update DMA request */
608 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
609
610 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
611
612 /* Disable the Peripheral */
613 __HAL_TIM_DISABLE(htim);
614
615 /* Set the TIM state */
616 htim->State = HAL_TIM_STATE_READY;
617
618 /* Return function status */
619 return HAL_OK;
620 }
621
622 /**
623 * @}
624 */
625
626 /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
627 * @brief TIM Output Compare functions
628 *
629 @verbatim
630 ==============================================================================
631 ##### TIM Output Compare functions #####
632 ==============================================================================
633 [..]
634 This section provides functions allowing to:
635 (+) Initialize and configure the TIM Output Compare.
636 (+) De-initialize the TIM Output Compare.
637 (+) Start the TIM Output Compare.
638 (+) Stop the TIM Output Compare.
639 (+) Start the TIM Output Compare and enable interrupt.
640 (+) Stop the TIM Output Compare and disable interrupt.
641 (+) Start the TIM Output Compare and enable DMA transfer.
642 (+) Stop the TIM Output Compare and disable DMA transfer.
643
644 @endverbatim
645 * @{
646 */
647 /**
648 * @brief Initializes the TIM Output Compare according to the specified
649 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
650 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
651 * requires a timer reset to avoid unexpected direction
652 * due to DIR bit readonly in center aligned mode.
653 * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
654 * @param htim TIM Output Compare handle
655 * @retval HAL status
656 */
HAL_TIM_OC_Init(TIM_HandleTypeDef * htim)657 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
658 {
659 /* Check the TIM handle allocation */
660 if (htim == NULL)
661 {
662 return HAL_ERROR;
663 }
664
665 /* Check the parameters */
666 assert_param(IS_TIM_INSTANCE(htim->Instance));
667 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
668 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
669 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
670 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
671
672 if (htim->State == HAL_TIM_STATE_RESET)
673 {
674 /* Allocate lock resource and initialize it */
675 htim->Lock = HAL_UNLOCKED;
676
677 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
678 /* Reset interrupt callbacks to legacy weak callbacks */
679 TIM_ResetCallback(htim);
680
681 if (htim->OC_MspInitCallback == NULL)
682 {
683 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
684 }
685 /* Init the low level hardware : GPIO, CLOCK, NVIC */
686 htim->OC_MspInitCallback(htim);
687 #else
688 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
689 HAL_TIM_OC_MspInit(htim);
690 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
691 }
692
693 /* Set the TIM state */
694 htim->State = HAL_TIM_STATE_BUSY;
695
696 /* Init the base time for the Output Compare */
697 TIM_Base_SetConfig(htim->Instance, &htim->Init);
698
699 /* Initialize the DMA burst operation state */
700 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
701
702 /* Initialize the TIM channels state */
703 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
704 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
705
706 /* Initialize the TIM state*/
707 htim->State = HAL_TIM_STATE_READY;
708
709 return HAL_OK;
710 }
711
712 /**
713 * @brief DeInitializes the TIM peripheral
714 * @param htim TIM Output Compare handle
715 * @retval HAL status
716 */
HAL_TIM_OC_DeInit(TIM_HandleTypeDef * htim)717 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
718 {
719 /* Check the parameters */
720 assert_param(IS_TIM_INSTANCE(htim->Instance));
721
722 htim->State = HAL_TIM_STATE_BUSY;
723
724 /* Disable the TIM Peripheral Clock */
725 __HAL_TIM_DISABLE(htim);
726
727 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
728 if (htim->OC_MspDeInitCallback == NULL)
729 {
730 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
731 }
732 /* DeInit the low level hardware */
733 htim->OC_MspDeInitCallback(htim);
734 #else
735 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
736 HAL_TIM_OC_MspDeInit(htim);
737 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
738
739 /* Change the DMA burst operation state */
740 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
741
742 /* Change the TIM channels state */
743 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
744 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
745
746 /* Change TIM state */
747 htim->State = HAL_TIM_STATE_RESET;
748
749 /* Release Lock */
750 __HAL_UNLOCK(htim);
751
752 return HAL_OK;
753 }
754
755 /**
756 * @brief Initializes the TIM Output Compare MSP.
757 * @param htim TIM Output Compare handle
758 * @retval None
759 */
HAL_TIM_OC_MspInit(TIM_HandleTypeDef * htim)760 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
761 {
762 /* Prevent unused argument(s) compilation warning */
763 UNUSED(htim);
764
765 /* NOTE : This function should not be modified, when the callback is needed,
766 the HAL_TIM_OC_MspInit could be implemented in the user file
767 */
768 }
769
770 /**
771 * @brief DeInitializes TIM Output Compare MSP.
772 * @param htim TIM Output Compare handle
773 * @retval None
774 */
HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef * htim)775 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
776 {
777 /* Prevent unused argument(s) compilation warning */
778 UNUSED(htim);
779
780 /* NOTE : This function should not be modified, when the callback is needed,
781 the HAL_TIM_OC_MspDeInit could be implemented in the user file
782 */
783 }
784
785 /**
786 * @brief Starts the TIM Output Compare signal generation.
787 * @param htim TIM Output Compare handle
788 * @param Channel TIM Channel to be enabled
789 * This parameter can be one of the following values:
790 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
791 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
792 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
793 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
794 * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*)
795 * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*)
796 * (*) Value not defined for all devices
797 * @retval HAL status
798 */
HAL_TIM_OC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)799 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
800 {
801 uint32_t tmpsmcr;
802
803 /* Check the parameters */
804 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
805
806 /* Check the TIM channel state */
807 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
808 {
809 return HAL_ERROR;
810 }
811
812 /* Set the TIM channel state */
813 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
814
815 /* Enable the Output compare channel */
816 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
817
818 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
819 {
820 /* Enable the main output */
821 __HAL_TIM_MOE_ENABLE(htim);
822 }
823
824 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
825 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
826 {
827 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
828 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
829 {
830 __HAL_TIM_ENABLE(htim);
831 }
832 }
833 else
834 {
835 __HAL_TIM_ENABLE(htim);
836 }
837
838 /* Return function status */
839 return HAL_OK;
840 }
841
842 /**
843 * @brief Stops the TIM Output Compare signal generation.
844 * @param htim TIM Output Compare handle
845 * @param Channel TIM Channel to be disabled
846 * This parameter can be one of the following values:
847 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
848 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
849 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
850 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
851 * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*)
852 * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*)
853 * (*) Value not defined for all devices
854 * @retval HAL status
855 */
HAL_TIM_OC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)856 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
857 {
858 /* Check the parameters */
859 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
860
861 /* Disable the Output compare channel */
862 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
863
864 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
865 {
866 /* Disable the Main Output */
867 __HAL_TIM_MOE_DISABLE(htim);
868 }
869
870 /* Disable the Peripheral */
871 __HAL_TIM_DISABLE(htim);
872
873 /* Set the TIM channel state */
874 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
875
876 /* Return function status */
877 return HAL_OK;
878 }
879
880 /**
881 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
882 * @param htim TIM Output Compare handle
883 * @param Channel TIM Channel to be enabled
884 * This parameter can be one of the following values:
885 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
886 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
887 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
888 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
889 * @retval HAL status
890 */
HAL_TIM_OC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)891 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
892 {
893 HAL_StatusTypeDef status = HAL_OK;
894 uint32_t tmpsmcr;
895
896 /* Check the parameters */
897 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
898
899 /* Check the TIM channel state */
900 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
901 {
902 return HAL_ERROR;
903 }
904
905 /* Set the TIM channel state */
906 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
907
908 switch (Channel)
909 {
910 case TIM_CHANNEL_1:
911 {
912 /* Enable the TIM Capture/Compare 1 interrupt */
913 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
914 break;
915 }
916
917 case TIM_CHANNEL_2:
918 {
919 /* Enable the TIM Capture/Compare 2 interrupt */
920 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
921 break;
922 }
923
924 case TIM_CHANNEL_3:
925 {
926 /* Enable the TIM Capture/Compare 3 interrupt */
927 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
928 break;
929 }
930
931 case TIM_CHANNEL_4:
932 {
933 /* Enable the TIM Capture/Compare 4 interrupt */
934 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
935 break;
936 }
937
938 default:
939 status = HAL_ERROR;
940 break;
941 }
942
943 if (status == HAL_OK)
944 {
945 /* Enable the Output compare channel */
946 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
947
948 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
949 {
950 /* Enable the main output */
951 __HAL_TIM_MOE_ENABLE(htim);
952 }
953
954 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
955 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
956 {
957 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
958 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
959 {
960 __HAL_TIM_ENABLE(htim);
961 }
962 }
963 else
964 {
965 __HAL_TIM_ENABLE(htim);
966 }
967 }
968
969 /* Return function status */
970 return status;
971 }
972
973 /**
974 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
975 * @param htim TIM Output Compare handle
976 * @param Channel TIM Channel to be disabled
977 * This parameter can be one of the following values:
978 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
979 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
980 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
981 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
982 * @retval HAL status
983 */
HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)984 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
985 {
986 HAL_StatusTypeDef status = HAL_OK;
987
988 /* Check the parameters */
989 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
990
991 switch (Channel)
992 {
993 case TIM_CHANNEL_1:
994 {
995 /* Disable the TIM Capture/Compare 1 interrupt */
996 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
997 break;
998 }
999
1000 case TIM_CHANNEL_2:
1001 {
1002 /* Disable the TIM Capture/Compare 2 interrupt */
1003 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1004 break;
1005 }
1006
1007 case TIM_CHANNEL_3:
1008 {
1009 /* Disable the TIM Capture/Compare 3 interrupt */
1010 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1011 break;
1012 }
1013
1014 case TIM_CHANNEL_4:
1015 {
1016 /* Disable the TIM Capture/Compare 4 interrupt */
1017 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1018 break;
1019 }
1020
1021 default:
1022 status = HAL_ERROR;
1023 break;
1024 }
1025
1026 if (status == HAL_OK)
1027 {
1028 /* Disable the Output compare channel */
1029 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1030
1031 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1032 {
1033 /* Disable the Main Output */
1034 __HAL_TIM_MOE_DISABLE(htim);
1035 }
1036
1037 /* Disable the Peripheral */
1038 __HAL_TIM_DISABLE(htim);
1039
1040 /* Set the TIM channel state */
1041 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1042 }
1043
1044 /* Return function status */
1045 return status;
1046 }
1047
1048 /**
1049 * @brief Starts the TIM Output Compare signal generation in DMA mode.
1050 * @param htim TIM Output Compare handle
1051 * @param Channel TIM Channel to be enabled
1052 * This parameter can be one of the following values:
1053 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1054 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1055 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1056 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1057 * @param pData The source Buffer address.
1058 * @param Length The length of data to be transferred from memory to TIM peripheral
1059 * @retval HAL status
1060 */
HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)1061 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
1062 uint16_t Length)
1063 {
1064 HAL_StatusTypeDef status = HAL_OK;
1065 uint32_t tmpsmcr;
1066
1067 /* Check the parameters */
1068 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1069
1070 /* Set the TIM channel state */
1071 if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1072 {
1073 return HAL_BUSY;
1074 }
1075 else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1076 {
1077 if ((pData == NULL) || (Length == 0U))
1078 {
1079 return HAL_ERROR;
1080 }
1081 else
1082 {
1083 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1084 }
1085 }
1086 else
1087 {
1088 return HAL_ERROR;
1089 }
1090
1091 switch (Channel)
1092 {
1093 case TIM_CHANNEL_1:
1094 {
1095 /* Set the DMA compare callbacks */
1096 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1097 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1098
1099 /* Set the DMA error callback */
1100 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1101
1102 /* Enable the DMA channel */
1103 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
1104 Length) != HAL_OK)
1105 {
1106 /* Return error status */
1107 return HAL_ERROR;
1108 }
1109
1110 /* Enable the TIM Capture/Compare 1 DMA request */
1111 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1112 break;
1113 }
1114
1115 case TIM_CHANNEL_2:
1116 {
1117 /* Set the DMA compare callbacks */
1118 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1119 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1120
1121 /* Set the DMA error callback */
1122 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1123
1124 /* Enable the DMA channel */
1125 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
1126 Length) != HAL_OK)
1127 {
1128 /* Return error status */
1129 return HAL_ERROR;
1130 }
1131
1132 /* Enable the TIM Capture/Compare 2 DMA request */
1133 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1134 break;
1135 }
1136
1137 case TIM_CHANNEL_3:
1138 {
1139 /* Set the DMA compare callbacks */
1140 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1141 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1142
1143 /* Set the DMA error callback */
1144 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1145
1146 /* Enable the DMA channel */
1147 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
1148 Length) != HAL_OK)
1149 {
1150 /* Return error status */
1151 return HAL_ERROR;
1152 }
1153 /* Enable the TIM Capture/Compare 3 DMA request */
1154 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1155 break;
1156 }
1157
1158 case TIM_CHANNEL_4:
1159 {
1160 /* Set the DMA compare callbacks */
1161 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1162 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1163
1164 /* Set the DMA error callback */
1165 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1166
1167 /* Enable the DMA channel */
1168 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1169 Length) != HAL_OK)
1170 {
1171 /* Return error status */
1172 return HAL_ERROR;
1173 }
1174 /* Enable the TIM Capture/Compare 4 DMA request */
1175 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1176 break;
1177 }
1178
1179 default:
1180 status = HAL_ERROR;
1181 break;
1182 }
1183
1184 if (status == HAL_OK)
1185 {
1186 /* Enable the Output compare channel */
1187 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1188
1189 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1190 {
1191 /* Enable the main output */
1192 __HAL_TIM_MOE_ENABLE(htim);
1193 }
1194
1195 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1196 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1197 {
1198 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1199 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1200 {
1201 __HAL_TIM_ENABLE(htim);
1202 }
1203 }
1204 else
1205 {
1206 __HAL_TIM_ENABLE(htim);
1207 }
1208 }
1209
1210 /* Return function status */
1211 return status;
1212 }
1213
1214 /**
1215 * @brief Stops the TIM Output Compare signal generation in DMA mode.
1216 * @param htim TIM Output Compare handle
1217 * @param Channel TIM Channel to be disabled
1218 * This parameter can be one of the following values:
1219 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1220 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1221 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1222 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1223 * @retval HAL status
1224 */
HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1225 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1226 {
1227 HAL_StatusTypeDef status = HAL_OK;
1228
1229 /* Check the parameters */
1230 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1231
1232 switch (Channel)
1233 {
1234 case TIM_CHANNEL_1:
1235 {
1236 /* Disable the TIM Capture/Compare 1 DMA request */
1237 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1238 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1239 break;
1240 }
1241
1242 case TIM_CHANNEL_2:
1243 {
1244 /* Disable the TIM Capture/Compare 2 DMA request */
1245 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1246 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1247 break;
1248 }
1249
1250 case TIM_CHANNEL_3:
1251 {
1252 /* Disable the TIM Capture/Compare 3 DMA request */
1253 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1254 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1255 break;
1256 }
1257
1258 case TIM_CHANNEL_4:
1259 {
1260 /* Disable the TIM Capture/Compare 4 interrupt */
1261 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1262 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1263 break;
1264 }
1265
1266 default:
1267 status = HAL_ERROR;
1268 break;
1269 }
1270
1271 if (status == HAL_OK)
1272 {
1273 /* Disable the Output compare channel */
1274 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1275
1276 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1277 {
1278 /* Disable the Main Output */
1279 __HAL_TIM_MOE_DISABLE(htim);
1280 }
1281
1282 /* Disable the Peripheral */
1283 __HAL_TIM_DISABLE(htim);
1284
1285 /* Set the TIM channel state */
1286 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1287 }
1288
1289 /* Return function status */
1290 return status;
1291 }
1292
1293 /**
1294 * @}
1295 */
1296
1297 /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
1298 * @brief TIM PWM functions
1299 *
1300 @verbatim
1301 ==============================================================================
1302 ##### TIM PWM functions #####
1303 ==============================================================================
1304 [..]
1305 This section provides functions allowing to:
1306 (+) Initialize and configure the TIM PWM.
1307 (+) De-initialize the TIM PWM.
1308 (+) Start the TIM PWM.
1309 (+) Stop the TIM PWM.
1310 (+) Start the TIM PWM and enable interrupt.
1311 (+) Stop the TIM PWM and disable interrupt.
1312 (+) Start the TIM PWM and enable DMA transfer.
1313 (+) Stop the TIM PWM and disable DMA transfer.
1314
1315 @endverbatim
1316 * @{
1317 */
1318 /**
1319 * @brief Initializes the TIM PWM Time Base according to the specified
1320 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1321 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1322 * requires a timer reset to avoid unexpected direction
1323 * due to DIR bit readonly in center aligned mode.
1324 * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
1325 * @param htim TIM PWM handle
1326 * @retval HAL status
1327 */
HAL_TIM_PWM_Init(TIM_HandleTypeDef * htim)1328 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
1329 {
1330 /* Check the TIM handle allocation */
1331 if (htim == NULL)
1332 {
1333 return HAL_ERROR;
1334 }
1335
1336 /* Check the parameters */
1337 assert_param(IS_TIM_INSTANCE(htim->Instance));
1338 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1339 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1340 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
1341 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
1342
1343 if (htim->State == HAL_TIM_STATE_RESET)
1344 {
1345 /* Allocate lock resource and initialize it */
1346 htim->Lock = HAL_UNLOCKED;
1347
1348 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1349 /* Reset interrupt callbacks to legacy weak callbacks */
1350 TIM_ResetCallback(htim);
1351
1352 if (htim->PWM_MspInitCallback == NULL)
1353 {
1354 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
1355 }
1356 /* Init the low level hardware : GPIO, CLOCK, NVIC */
1357 htim->PWM_MspInitCallback(htim);
1358 #else
1359 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1360 HAL_TIM_PWM_MspInit(htim);
1361 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1362 }
1363
1364 /* Set the TIM state */
1365 htim->State = HAL_TIM_STATE_BUSY;
1366
1367 /* Init the base time for the PWM */
1368 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1369
1370 /* Initialize the DMA burst operation state */
1371 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
1372
1373 /* Initialize the TIM channels state */
1374 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1375 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1376
1377 /* Initialize the TIM state*/
1378 htim->State = HAL_TIM_STATE_READY;
1379
1380 return HAL_OK;
1381 }
1382
1383 /**
1384 * @brief DeInitializes the TIM peripheral
1385 * @param htim TIM PWM handle
1386 * @retval HAL status
1387 */
HAL_TIM_PWM_DeInit(TIM_HandleTypeDef * htim)1388 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
1389 {
1390 /* Check the parameters */
1391 assert_param(IS_TIM_INSTANCE(htim->Instance));
1392
1393 htim->State = HAL_TIM_STATE_BUSY;
1394
1395 /* Disable the TIM Peripheral Clock */
1396 __HAL_TIM_DISABLE(htim);
1397
1398 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1399 if (htim->PWM_MspDeInitCallback == NULL)
1400 {
1401 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
1402 }
1403 /* DeInit the low level hardware */
1404 htim->PWM_MspDeInitCallback(htim);
1405 #else
1406 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1407 HAL_TIM_PWM_MspDeInit(htim);
1408 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1409
1410 /* Change the DMA burst operation state */
1411 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
1412
1413 /* Change the TIM channels state */
1414 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
1415 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
1416
1417 /* Change TIM state */
1418 htim->State = HAL_TIM_STATE_RESET;
1419
1420 /* Release Lock */
1421 __HAL_UNLOCK(htim);
1422
1423 return HAL_OK;
1424 }
1425
1426 /**
1427 * @brief Initializes the TIM PWM MSP.
1428 * @param htim TIM PWM handle
1429 * @retval None
1430 */
HAL_TIM_PWM_MspInit(TIM_HandleTypeDef * htim)1431 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
1432 {
1433 /* Prevent unused argument(s) compilation warning */
1434 UNUSED(htim);
1435
1436 /* NOTE : This function should not be modified, when the callback is needed,
1437 the HAL_TIM_PWM_MspInit could be implemented in the user file
1438 */
1439 }
1440
1441 /**
1442 * @brief DeInitializes TIM PWM MSP.
1443 * @param htim TIM PWM handle
1444 * @retval None
1445 */
HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef * htim)1446 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
1447 {
1448 /* Prevent unused argument(s) compilation warning */
1449 UNUSED(htim);
1450
1451 /* NOTE : This function should not be modified, when the callback is needed,
1452 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
1453 */
1454 }
1455
1456 /**
1457 * @brief Starts the PWM signal generation.
1458 * @param htim TIM handle
1459 * @param Channel TIM Channels to be enabled
1460 * This parameter can be one of the following values:
1461 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1462 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1463 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1464 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1465 * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*)
1466 * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*)
1467 * (*) Value not defined for all devices
1468 * @retval HAL status
1469 */
HAL_TIM_PWM_Start(TIM_HandleTypeDef * htim,uint32_t Channel)1470 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1471 {
1472 uint32_t tmpsmcr;
1473
1474 /* Check the parameters */
1475 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1476
1477 /* Check the TIM channel state */
1478 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1479 {
1480 return HAL_ERROR;
1481 }
1482
1483 /* Set the TIM channel state */
1484 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1485
1486 /* Enable the Capture compare channel */
1487 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1488
1489 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1490 {
1491 /* Enable the main output */
1492 __HAL_TIM_MOE_ENABLE(htim);
1493 }
1494
1495 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1496 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1497 {
1498 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1499 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1500 {
1501 __HAL_TIM_ENABLE(htim);
1502 }
1503 }
1504 else
1505 {
1506 __HAL_TIM_ENABLE(htim);
1507 }
1508
1509 /* Return function status */
1510 return HAL_OK;
1511 }
1512
1513 /**
1514 * @brief Stops the PWM signal generation.
1515 * @param htim TIM PWM handle
1516 * @param Channel TIM Channels to be disabled
1517 * This parameter can be one of the following values:
1518 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1519 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1520 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1521 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1522 * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*)
1523 * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*)
1524 * (*) Value not defined for all devices
1525 * @retval HAL status
1526 */
HAL_TIM_PWM_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)1527 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1528 {
1529 /* Check the parameters */
1530 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1531
1532 /* Disable the Capture compare channel */
1533 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1534
1535 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1536 {
1537 /* Disable the Main Output */
1538 __HAL_TIM_MOE_DISABLE(htim);
1539 }
1540
1541 /* Disable the Peripheral */
1542 __HAL_TIM_DISABLE(htim);
1543
1544 /* Set the TIM channel state */
1545 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1546
1547 /* Return function status */
1548 return HAL_OK;
1549 }
1550
1551 /**
1552 * @brief Starts the PWM signal generation in interrupt mode.
1553 * @param htim TIM PWM handle
1554 * @param Channel TIM Channel to be enabled
1555 * This parameter can be one of the following values:
1556 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1557 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1558 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1559 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1560 * @retval HAL status
1561 */
HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1562 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1563 {
1564 HAL_StatusTypeDef status = HAL_OK;
1565 uint32_t tmpsmcr;
1566
1567 /* Check the parameters */
1568 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1569
1570 /* Check the TIM channel state */
1571 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1572 {
1573 return HAL_ERROR;
1574 }
1575
1576 /* Set the TIM channel state */
1577 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1578
1579 switch (Channel)
1580 {
1581 case TIM_CHANNEL_1:
1582 {
1583 /* Enable the TIM Capture/Compare 1 interrupt */
1584 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1585 break;
1586 }
1587
1588 case TIM_CHANNEL_2:
1589 {
1590 /* Enable the TIM Capture/Compare 2 interrupt */
1591 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1592 break;
1593 }
1594
1595 case TIM_CHANNEL_3:
1596 {
1597 /* Enable the TIM Capture/Compare 3 interrupt */
1598 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1599 break;
1600 }
1601
1602 case TIM_CHANNEL_4:
1603 {
1604 /* Enable the TIM Capture/Compare 4 interrupt */
1605 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1606 break;
1607 }
1608
1609 default:
1610 status = HAL_ERROR;
1611 break;
1612 }
1613
1614 if (status == HAL_OK)
1615 {
1616 /* Enable the Capture compare channel */
1617 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1618
1619 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1620 {
1621 /* Enable the main output */
1622 __HAL_TIM_MOE_ENABLE(htim);
1623 }
1624
1625 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1626 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1627 {
1628 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1629 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1630 {
1631 __HAL_TIM_ENABLE(htim);
1632 }
1633 }
1634 else
1635 {
1636 __HAL_TIM_ENABLE(htim);
1637 }
1638 }
1639
1640 /* Return function status */
1641 return status;
1642 }
1643
1644 /**
1645 * @brief Stops the PWM signal generation in interrupt mode.
1646 * @param htim TIM PWM handle
1647 * @param Channel TIM Channels to be disabled
1648 * This parameter can be one of the following values:
1649 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1650 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1651 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1652 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1653 * @retval HAL status
1654 */
HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1655 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1656 {
1657 HAL_StatusTypeDef status = HAL_OK;
1658
1659 /* Check the parameters */
1660 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1661
1662 switch (Channel)
1663 {
1664 case TIM_CHANNEL_1:
1665 {
1666 /* Disable the TIM Capture/Compare 1 interrupt */
1667 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1668 break;
1669 }
1670
1671 case TIM_CHANNEL_2:
1672 {
1673 /* Disable the TIM Capture/Compare 2 interrupt */
1674 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1675 break;
1676 }
1677
1678 case TIM_CHANNEL_3:
1679 {
1680 /* Disable the TIM Capture/Compare 3 interrupt */
1681 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1682 break;
1683 }
1684
1685 case TIM_CHANNEL_4:
1686 {
1687 /* Disable the TIM Capture/Compare 4 interrupt */
1688 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1689 break;
1690 }
1691
1692 default:
1693 status = HAL_ERROR;
1694 break;
1695 }
1696
1697 if (status == HAL_OK)
1698 {
1699 /* Disable the Capture compare channel */
1700 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1701
1702 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1703 {
1704 /* Disable the Main Output */
1705 __HAL_TIM_MOE_DISABLE(htim);
1706 }
1707
1708 /* Disable the Peripheral */
1709 __HAL_TIM_DISABLE(htim);
1710
1711 /* Set the TIM channel state */
1712 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1713 }
1714
1715 /* Return function status */
1716 return status;
1717 }
1718
1719 /**
1720 * @brief Starts the TIM PWM signal generation in DMA mode.
1721 * @param htim TIM PWM handle
1722 * @param Channel TIM Channels to be enabled
1723 * This parameter can be one of the following values:
1724 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1725 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1726 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1727 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1728 * @param pData The source Buffer address.
1729 * @param Length The length of data to be transferred from memory to TIM peripheral
1730 * @retval HAL status
1731 */
HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)1732 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
1733 uint16_t Length)
1734 {
1735 HAL_StatusTypeDef status = HAL_OK;
1736 uint32_t tmpsmcr;
1737
1738 /* Check the parameters */
1739 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1740
1741 /* Set the TIM channel state */
1742 if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1743 {
1744 return HAL_BUSY;
1745 }
1746 else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1747 {
1748 if ((pData == NULL) || (Length == 0U))
1749 {
1750 return HAL_ERROR;
1751 }
1752 else
1753 {
1754 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1755 }
1756 }
1757 else
1758 {
1759 return HAL_ERROR;
1760 }
1761
1762 switch (Channel)
1763 {
1764 case TIM_CHANNEL_1:
1765 {
1766 /* Set the DMA compare callbacks */
1767 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1768 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1769
1770 /* Set the DMA error callback */
1771 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1772
1773 /* Enable the DMA channel */
1774 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
1775 Length) != HAL_OK)
1776 {
1777 /* Return error status */
1778 return HAL_ERROR;
1779 }
1780
1781 /* Enable the TIM Capture/Compare 1 DMA request */
1782 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1783 break;
1784 }
1785
1786 case TIM_CHANNEL_2:
1787 {
1788 /* Set the DMA compare callbacks */
1789 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1790 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1791
1792 /* Set the DMA error callback */
1793 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1794
1795 /* Enable the DMA channel */
1796 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
1797 Length) != HAL_OK)
1798 {
1799 /* Return error status */
1800 return HAL_ERROR;
1801 }
1802 /* Enable the TIM Capture/Compare 2 DMA request */
1803 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1804 break;
1805 }
1806
1807 case TIM_CHANNEL_3:
1808 {
1809 /* Set the DMA compare callbacks */
1810 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1811 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1812
1813 /* Set the DMA error callback */
1814 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1815
1816 /* Enable the DMA channel */
1817 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
1818 Length) != HAL_OK)
1819 {
1820 /* Return error status */
1821 return HAL_ERROR;
1822 }
1823 /* Enable the TIM Output Capture/Compare 3 request */
1824 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1825 break;
1826 }
1827
1828 case TIM_CHANNEL_4:
1829 {
1830 /* Set the DMA compare callbacks */
1831 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1832 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1833
1834 /* Set the DMA error callback */
1835 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1836
1837 /* Enable the DMA channel */
1838 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1839 Length) != HAL_OK)
1840 {
1841 /* Return error status */
1842 return HAL_ERROR;
1843 }
1844 /* Enable the TIM Capture/Compare 4 DMA request */
1845 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1846 break;
1847 }
1848
1849 default:
1850 status = HAL_ERROR;
1851 break;
1852 }
1853
1854 if (status == HAL_OK)
1855 {
1856 /* Enable the Capture compare channel */
1857 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1858
1859 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1860 {
1861 /* Enable the main output */
1862 __HAL_TIM_MOE_ENABLE(htim);
1863 }
1864
1865 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1866 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1867 {
1868 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1869 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1870 {
1871 __HAL_TIM_ENABLE(htim);
1872 }
1873 }
1874 else
1875 {
1876 __HAL_TIM_ENABLE(htim);
1877 }
1878 }
1879
1880 /* Return function status */
1881 return status;
1882 }
1883
1884 /**
1885 * @brief Stops the TIM PWM signal generation in DMA mode.
1886 * @param htim TIM PWM handle
1887 * @param Channel TIM Channels to be disabled
1888 * This parameter can be one of the following values:
1889 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1890 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1891 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1892 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1893 * @retval HAL status
1894 */
HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1895 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1896 {
1897 HAL_StatusTypeDef status = HAL_OK;
1898
1899 /* Check the parameters */
1900 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1901
1902 switch (Channel)
1903 {
1904 case TIM_CHANNEL_1:
1905 {
1906 /* Disable the TIM Capture/Compare 1 DMA request */
1907 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1908 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1909 break;
1910 }
1911
1912 case TIM_CHANNEL_2:
1913 {
1914 /* Disable the TIM Capture/Compare 2 DMA request */
1915 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1916 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1917 break;
1918 }
1919
1920 case TIM_CHANNEL_3:
1921 {
1922 /* Disable the TIM Capture/Compare 3 DMA request */
1923 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1924 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1925 break;
1926 }
1927
1928 case TIM_CHANNEL_4:
1929 {
1930 /* Disable the TIM Capture/Compare 4 interrupt */
1931 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1932 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1933 break;
1934 }
1935
1936 default:
1937 status = HAL_ERROR;
1938 break;
1939 }
1940
1941 if (status == HAL_OK)
1942 {
1943 /* Disable the Capture compare channel */
1944 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1945
1946 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1947 {
1948 /* Disable the Main Output */
1949 __HAL_TIM_MOE_DISABLE(htim);
1950 }
1951
1952 /* Disable the Peripheral */
1953 __HAL_TIM_DISABLE(htim);
1954
1955 /* Set the TIM channel state */
1956 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1957 }
1958
1959 /* Return function status */
1960 return status;
1961 }
1962
1963 /**
1964 * @}
1965 */
1966
1967 /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
1968 * @brief TIM Input Capture functions
1969 *
1970 @verbatim
1971 ==============================================================================
1972 ##### TIM Input Capture functions #####
1973 ==============================================================================
1974 [..]
1975 This section provides functions allowing to:
1976 (+) Initialize and configure the TIM Input Capture.
1977 (+) De-initialize the TIM Input Capture.
1978 (+) Start the TIM Input Capture.
1979 (+) Stop the TIM Input Capture.
1980 (+) Start the TIM Input Capture and enable interrupt.
1981 (+) Stop the TIM Input Capture and disable interrupt.
1982 (+) Start the TIM Input Capture and enable DMA transfer.
1983 (+) Stop the TIM Input Capture and disable DMA transfer.
1984
1985 @endverbatim
1986 * @{
1987 */
1988 /**
1989 * @brief Initializes the TIM Input Capture Time base according to the specified
1990 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1991 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1992 * requires a timer reset to avoid unexpected direction
1993 * due to DIR bit readonly in center aligned mode.
1994 * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
1995 * @param htim TIM Input Capture handle
1996 * @retval HAL status
1997 */
HAL_TIM_IC_Init(TIM_HandleTypeDef * htim)1998 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
1999 {
2000 /* Check the TIM handle allocation */
2001 if (htim == NULL)
2002 {
2003 return HAL_ERROR;
2004 }
2005
2006 /* Check the parameters */
2007 assert_param(IS_TIM_INSTANCE(htim->Instance));
2008 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2009 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2010 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
2011 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2012
2013 if (htim->State == HAL_TIM_STATE_RESET)
2014 {
2015 /* Allocate lock resource and initialize it */
2016 htim->Lock = HAL_UNLOCKED;
2017
2018 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2019 /* Reset interrupt callbacks to legacy weak callbacks */
2020 TIM_ResetCallback(htim);
2021
2022 if (htim->IC_MspInitCallback == NULL)
2023 {
2024 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
2025 }
2026 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2027 htim->IC_MspInitCallback(htim);
2028 #else
2029 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2030 HAL_TIM_IC_MspInit(htim);
2031 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2032 }
2033
2034 /* Set the TIM state */
2035 htim->State = HAL_TIM_STATE_BUSY;
2036
2037 /* Init the base time for the input capture */
2038 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2039
2040 /* Initialize the DMA burst operation state */
2041 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
2042
2043 /* Initialize the TIM channels state */
2044 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
2045 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
2046
2047 /* Initialize the TIM state*/
2048 htim->State = HAL_TIM_STATE_READY;
2049
2050 return HAL_OK;
2051 }
2052
2053 /**
2054 * @brief DeInitializes the TIM peripheral
2055 * @param htim TIM Input Capture handle
2056 * @retval HAL status
2057 */
HAL_TIM_IC_DeInit(TIM_HandleTypeDef * htim)2058 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
2059 {
2060 /* Check the parameters */
2061 assert_param(IS_TIM_INSTANCE(htim->Instance));
2062
2063 htim->State = HAL_TIM_STATE_BUSY;
2064
2065 /* Disable the TIM Peripheral Clock */
2066 __HAL_TIM_DISABLE(htim);
2067
2068 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2069 if (htim->IC_MspDeInitCallback == NULL)
2070 {
2071 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
2072 }
2073 /* DeInit the low level hardware */
2074 htim->IC_MspDeInitCallback(htim);
2075 #else
2076 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
2077 HAL_TIM_IC_MspDeInit(htim);
2078 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2079
2080 /* Change the DMA burst operation state */
2081 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
2082
2083 /* Change the TIM channels state */
2084 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
2085 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
2086
2087 /* Change TIM state */
2088 htim->State = HAL_TIM_STATE_RESET;
2089
2090 /* Release Lock */
2091 __HAL_UNLOCK(htim);
2092
2093 return HAL_OK;
2094 }
2095
2096 /**
2097 * @brief Initializes the TIM Input Capture MSP.
2098 * @param htim TIM Input Capture handle
2099 * @retval None
2100 */
HAL_TIM_IC_MspInit(TIM_HandleTypeDef * htim)2101 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
2102 {
2103 /* Prevent unused argument(s) compilation warning */
2104 UNUSED(htim);
2105
2106 /* NOTE : This function should not be modified, when the callback is needed,
2107 the HAL_TIM_IC_MspInit could be implemented in the user file
2108 */
2109 }
2110
2111 /**
2112 * @brief DeInitializes TIM Input Capture MSP.
2113 * @param htim TIM handle
2114 * @retval None
2115 */
HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef * htim)2116 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
2117 {
2118 /* Prevent unused argument(s) compilation warning */
2119 UNUSED(htim);
2120
2121 /* NOTE : This function should not be modified, when the callback is needed,
2122 the HAL_TIM_IC_MspDeInit could be implemented in the user file
2123 */
2124 }
2125
2126 /**
2127 * @brief Starts the TIM Input Capture measurement.
2128 * @param htim TIM Input Capture handle
2129 * @param Channel TIM Channels to be enabled
2130 * This parameter can be one of the following values:
2131 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2132 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2133 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2134 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2135 * @retval HAL status
2136 */
HAL_TIM_IC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)2137 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
2138 {
2139 uint32_t tmpsmcr;
2140 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2141 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2142
2143 /* Check the parameters */
2144 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2145
2146 /* Check the TIM channel state */
2147 if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
2148 || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
2149 {
2150 return HAL_ERROR;
2151 }
2152
2153 /* Set the TIM channel state */
2154 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2155 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2156
2157 /* Enable the Input Capture channel */
2158 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2159
2160 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2161 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2162 {
2163 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2164 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2165 {
2166 __HAL_TIM_ENABLE(htim);
2167 }
2168 }
2169 else
2170 {
2171 __HAL_TIM_ENABLE(htim);
2172 }
2173
2174 /* Return function status */
2175 return HAL_OK;
2176 }
2177
2178 /**
2179 * @brief Stops the TIM Input Capture measurement.
2180 * @param htim TIM Input Capture handle
2181 * @param Channel TIM Channels to be disabled
2182 * This parameter can be one of the following values:
2183 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2184 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2185 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2186 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2187 * @retval HAL status
2188 */
HAL_TIM_IC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)2189 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
2190 {
2191 /* Check the parameters */
2192 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2193
2194 /* Disable the Input Capture channel */
2195 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2196
2197 /* Disable the Peripheral */
2198 __HAL_TIM_DISABLE(htim);
2199
2200 /* Set the TIM channel state */
2201 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2202 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2203
2204 /* Return function status */
2205 return HAL_OK;
2206 }
2207
2208 /**
2209 * @brief Starts the TIM Input Capture measurement in interrupt mode.
2210 * @param htim TIM Input Capture handle
2211 * @param Channel TIM Channels to be enabled
2212 * This parameter can be one of the following values:
2213 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2214 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2215 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2216 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2217 * @retval HAL status
2218 */
HAL_TIM_IC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2219 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2220 {
2221 HAL_StatusTypeDef status = HAL_OK;
2222 uint32_t tmpsmcr;
2223
2224 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2225 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2226
2227 /* Check the parameters */
2228 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2229
2230 /* Check the TIM channel state */
2231 if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
2232 || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
2233 {
2234 return HAL_ERROR;
2235 }
2236
2237 /* Set the TIM channel state */
2238 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2239 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2240
2241 switch (Channel)
2242 {
2243 case TIM_CHANNEL_1:
2244 {
2245 /* Enable the TIM Capture/Compare 1 interrupt */
2246 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2247 break;
2248 }
2249
2250 case TIM_CHANNEL_2:
2251 {
2252 /* Enable the TIM Capture/Compare 2 interrupt */
2253 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2254 break;
2255 }
2256
2257 case TIM_CHANNEL_3:
2258 {
2259 /* Enable the TIM Capture/Compare 3 interrupt */
2260 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
2261 break;
2262 }
2263
2264 case TIM_CHANNEL_4:
2265 {
2266 /* Enable the TIM Capture/Compare 4 interrupt */
2267 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
2268 break;
2269 }
2270
2271 default:
2272 status = HAL_ERROR;
2273 break;
2274 }
2275
2276 if (status == HAL_OK)
2277 {
2278 /* Enable the Input Capture channel */
2279 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2280
2281 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2282 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2283 {
2284 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2285 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2286 {
2287 __HAL_TIM_ENABLE(htim);
2288 }
2289 }
2290 else
2291 {
2292 __HAL_TIM_ENABLE(htim);
2293 }
2294 }
2295
2296 /* Return function status */
2297 return status;
2298 }
2299
2300 /**
2301 * @brief Stops the TIM Input Capture measurement in interrupt mode.
2302 * @param htim TIM Input Capture handle
2303 * @param Channel TIM Channels to be disabled
2304 * This parameter can be one of the following values:
2305 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2306 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2307 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2308 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2309 * @retval HAL status
2310 */
HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2311 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2312 {
2313 HAL_StatusTypeDef status = HAL_OK;
2314
2315 /* Check the parameters */
2316 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2317
2318 switch (Channel)
2319 {
2320 case TIM_CHANNEL_1:
2321 {
2322 /* Disable the TIM Capture/Compare 1 interrupt */
2323 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2324 break;
2325 }
2326
2327 case TIM_CHANNEL_2:
2328 {
2329 /* Disable the TIM Capture/Compare 2 interrupt */
2330 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2331 break;
2332 }
2333
2334 case TIM_CHANNEL_3:
2335 {
2336 /* Disable the TIM Capture/Compare 3 interrupt */
2337 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
2338 break;
2339 }
2340
2341 case TIM_CHANNEL_4:
2342 {
2343 /* Disable the TIM Capture/Compare 4 interrupt */
2344 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
2345 break;
2346 }
2347
2348 default:
2349 status = HAL_ERROR;
2350 break;
2351 }
2352
2353 if (status == HAL_OK)
2354 {
2355 /* Disable the Input Capture channel */
2356 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2357
2358 /* Disable the Peripheral */
2359 __HAL_TIM_DISABLE(htim);
2360
2361 /* Set the TIM channel state */
2362 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2363 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2364 }
2365
2366 /* Return function status */
2367 return status;
2368 }
2369
2370 /**
2371 * @brief Starts the TIM Input Capture measurement in DMA mode.
2372 * @param htim TIM Input Capture handle
2373 * @param Channel TIM Channels to be enabled
2374 * This parameter can be one of the following values:
2375 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2376 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2377 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2378 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2379 * @param pData The destination Buffer address.
2380 * @param Length The length of data to be transferred from TIM peripheral to memory.
2381 * @retval HAL status
2382 */
HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)2383 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
2384 {
2385 HAL_StatusTypeDef status = HAL_OK;
2386 uint32_t tmpsmcr;
2387
2388 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2389 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2390
2391 /* Check the parameters */
2392 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2393 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2394
2395 /* Set the TIM channel state */
2396 if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
2397 || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
2398 {
2399 return HAL_BUSY;
2400 }
2401 else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
2402 && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
2403 {
2404 if ((pData == NULL) || (Length == 0U))
2405 {
2406 return HAL_ERROR;
2407 }
2408 else
2409 {
2410 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2411 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2412 }
2413 }
2414 else
2415 {
2416 return HAL_ERROR;
2417 }
2418
2419 /* Enable the Input Capture channel */
2420 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2421
2422 switch (Channel)
2423 {
2424 case TIM_CHANNEL_1:
2425 {
2426 /* Set the DMA capture callbacks */
2427 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
2428 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2429
2430 /* Set the DMA error callback */
2431 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
2432
2433 /* Enable the DMA channel */
2434 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData,
2435 Length) != HAL_OK)
2436 {
2437 /* Return error status */
2438 return HAL_ERROR;
2439 }
2440 /* Enable the TIM Capture/Compare 1 DMA request */
2441 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
2442 break;
2443 }
2444
2445 case TIM_CHANNEL_2:
2446 {
2447 /* Set the DMA capture callbacks */
2448 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
2449 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2450
2451 /* Set the DMA error callback */
2452 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
2453
2454 /* Enable the DMA channel */
2455 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData,
2456 Length) != HAL_OK)
2457 {
2458 /* Return error status */
2459 return HAL_ERROR;
2460 }
2461 /* Enable the TIM Capture/Compare 2 DMA request */
2462 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
2463 break;
2464 }
2465
2466 case TIM_CHANNEL_3:
2467 {
2468 /* Set the DMA capture callbacks */
2469 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
2470 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2471
2472 /* Set the DMA error callback */
2473 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
2474
2475 /* Enable the DMA channel */
2476 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData,
2477 Length) != HAL_OK)
2478 {
2479 /* Return error status */
2480 return HAL_ERROR;
2481 }
2482 /* Enable the TIM Capture/Compare 3 DMA request */
2483 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
2484 break;
2485 }
2486
2487 case TIM_CHANNEL_4:
2488 {
2489 /* Set the DMA capture callbacks */
2490 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
2491 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2492
2493 /* Set the DMA error callback */
2494 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
2495
2496 /* Enable the DMA channel */
2497 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData,
2498 Length) != HAL_OK)
2499 {
2500 /* Return error status */
2501 return HAL_ERROR;
2502 }
2503 /* Enable the TIM Capture/Compare 4 DMA request */
2504 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
2505 break;
2506 }
2507
2508 default:
2509 status = HAL_ERROR;
2510 break;
2511 }
2512
2513 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2514 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2515 {
2516 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2517 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2518 {
2519 __HAL_TIM_ENABLE(htim);
2520 }
2521 }
2522 else
2523 {
2524 __HAL_TIM_ENABLE(htim);
2525 }
2526
2527 /* Return function status */
2528 return status;
2529 }
2530
2531 /**
2532 * @brief Stops the TIM Input Capture measurement in DMA mode.
2533 * @param htim TIM Input Capture handle
2534 * @param Channel TIM Channels to be disabled
2535 * This parameter can be one of the following values:
2536 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2537 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2538 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2539 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2540 * @retval HAL status
2541 */
HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)2542 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
2543 {
2544 HAL_StatusTypeDef status = HAL_OK;
2545
2546 /* Check the parameters */
2547 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2548 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2549
2550 /* Disable the Input Capture channel */
2551 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2552
2553 switch (Channel)
2554 {
2555 case TIM_CHANNEL_1:
2556 {
2557 /* Disable the TIM Capture/Compare 1 DMA request */
2558 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
2559 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
2560 break;
2561 }
2562
2563 case TIM_CHANNEL_2:
2564 {
2565 /* Disable the TIM Capture/Compare 2 DMA request */
2566 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
2567 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
2568 break;
2569 }
2570
2571 case TIM_CHANNEL_3:
2572 {
2573 /* Disable the TIM Capture/Compare 3 DMA request */
2574 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
2575 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
2576 break;
2577 }
2578
2579 case TIM_CHANNEL_4:
2580 {
2581 /* Disable the TIM Capture/Compare 4 DMA request */
2582 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
2583 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
2584 break;
2585 }
2586
2587 default:
2588 status = HAL_ERROR;
2589 break;
2590 }
2591
2592 if (status == HAL_OK)
2593 {
2594 /* Disable the Peripheral */
2595 __HAL_TIM_DISABLE(htim);
2596
2597 /* Set the TIM channel state */
2598 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2599 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2600 }
2601
2602 /* Return function status */
2603 return status;
2604 }
2605 /**
2606 * @}
2607 */
2608
2609 /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
2610 * @brief TIM One Pulse functions
2611 *
2612 @verbatim
2613 ==============================================================================
2614 ##### TIM One Pulse functions #####
2615 ==============================================================================
2616 [..]
2617 This section provides functions allowing to:
2618 (+) Initialize and configure the TIM One Pulse.
2619 (+) De-initialize the TIM One Pulse.
2620 (+) Start the TIM One Pulse.
2621 (+) Stop the TIM One Pulse.
2622 (+) Start the TIM One Pulse and enable interrupt.
2623 (+) Stop the TIM One Pulse and disable interrupt.
2624 (+) Start the TIM One Pulse and enable DMA transfer.
2625 (+) Stop the TIM One Pulse and disable DMA transfer.
2626
2627 @endverbatim
2628 * @{
2629 */
2630 /**
2631 * @brief Initializes the TIM One Pulse Time Base according to the specified
2632 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
2633 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
2634 * requires a timer reset to avoid unexpected direction
2635 * due to DIR bit readonly in center aligned mode.
2636 * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
2637 * @note When the timer instance is initialized in One Pulse mode, timer
2638 * channels 1 and channel 2 are reserved and cannot be used for other
2639 * purpose.
2640 * @param htim TIM One Pulse handle
2641 * @param OnePulseMode Select the One pulse mode.
2642 * This parameter can be one of the following values:
2643 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
2644 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
2645 * @retval HAL status
2646 */
HAL_TIM_OnePulse_Init(TIM_HandleTypeDef * htim,uint32_t OnePulseMode)2647 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
2648 {
2649 /* Check the TIM handle allocation */
2650 if (htim == NULL)
2651 {
2652 return HAL_ERROR;
2653 }
2654
2655 /* Check the parameters */
2656 assert_param(IS_TIM_INSTANCE(htim->Instance));
2657 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2658 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2659 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
2660 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
2661 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2662
2663 if (htim->State == HAL_TIM_STATE_RESET)
2664 {
2665 /* Allocate lock resource and initialize it */
2666 htim->Lock = HAL_UNLOCKED;
2667
2668 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2669 /* Reset interrupt callbacks to legacy weak callbacks */
2670 TIM_ResetCallback(htim);
2671
2672 if (htim->OnePulse_MspInitCallback == NULL)
2673 {
2674 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
2675 }
2676 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2677 htim->OnePulse_MspInitCallback(htim);
2678 #else
2679 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2680 HAL_TIM_OnePulse_MspInit(htim);
2681 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2682 }
2683
2684 /* Set the TIM state */
2685 htim->State = HAL_TIM_STATE_BUSY;
2686
2687 /* Configure the Time base in the One Pulse Mode */
2688 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2689
2690 /* Reset the OPM Bit */
2691 htim->Instance->CR1 &= ~TIM_CR1_OPM;
2692
2693 /* Configure the OPM Mode */
2694 htim->Instance->CR1 |= OnePulseMode;
2695
2696 /* Initialize the DMA burst operation state */
2697 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
2698
2699 /* Initialize the TIM channels state */
2700 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2701 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2702 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2703 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2704
2705 /* Initialize the TIM state*/
2706 htim->State = HAL_TIM_STATE_READY;
2707
2708 return HAL_OK;
2709 }
2710
2711 /**
2712 * @brief DeInitializes the TIM One Pulse
2713 * @param htim TIM One Pulse handle
2714 * @retval HAL status
2715 */
HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef * htim)2716 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
2717 {
2718 /* Check the parameters */
2719 assert_param(IS_TIM_INSTANCE(htim->Instance));
2720
2721 htim->State = HAL_TIM_STATE_BUSY;
2722
2723 /* Disable the TIM Peripheral Clock */
2724 __HAL_TIM_DISABLE(htim);
2725
2726 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2727 if (htim->OnePulse_MspDeInitCallback == NULL)
2728 {
2729 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
2730 }
2731 /* DeInit the low level hardware */
2732 htim->OnePulse_MspDeInitCallback(htim);
2733 #else
2734 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2735 HAL_TIM_OnePulse_MspDeInit(htim);
2736 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2737
2738 /* Change the DMA burst operation state */
2739 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
2740
2741 /* Set the TIM channel state */
2742 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
2743 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
2744 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
2745 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
2746
2747 /* Change TIM state */
2748 htim->State = HAL_TIM_STATE_RESET;
2749
2750 /* Release Lock */
2751 __HAL_UNLOCK(htim);
2752
2753 return HAL_OK;
2754 }
2755
2756 /**
2757 * @brief Initializes the TIM One Pulse MSP.
2758 * @param htim TIM One Pulse handle
2759 * @retval None
2760 */
HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef * htim)2761 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
2762 {
2763 /* Prevent unused argument(s) compilation warning */
2764 UNUSED(htim);
2765
2766 /* NOTE : This function should not be modified, when the callback is needed,
2767 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
2768 */
2769 }
2770
2771 /**
2772 * @brief DeInitializes TIM One Pulse MSP.
2773 * @param htim TIM One Pulse handle
2774 * @retval None
2775 */
HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef * htim)2776 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
2777 {
2778 /* Prevent unused argument(s) compilation warning */
2779 UNUSED(htim);
2780
2781 /* NOTE : This function should not be modified, when the callback is needed,
2782 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
2783 */
2784 }
2785
2786 /**
2787 * @brief Starts the TIM One Pulse signal generation.
2788 * @note Though OutputChannel parameter is deprecated and ignored by the function
2789 * it has been kept to avoid HAL_TIM API compatibility break.
2790 * @note The pulse output channel is determined when calling
2791 * @ref HAL_TIM_OnePulse_ConfigChannel().
2792 * @param htim TIM One Pulse handle
2793 * @param OutputChannel See note above
2794 * @retval HAL status
2795 */
HAL_TIM_OnePulse_Start(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2796 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2797 {
2798 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
2799 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
2800 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
2801 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
2802
2803 /* Prevent unused argument(s) compilation warning */
2804 UNUSED(OutputChannel);
2805
2806 /* Check the TIM channels state */
2807 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2808 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
2809 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2810 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
2811 {
2812 return HAL_ERROR;
2813 }
2814
2815 /* Set the TIM channels state */
2816 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2817 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2818 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2819 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2820
2821 /* Enable the Capture compare and the Input Capture channels
2822 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2823 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2824 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2825 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2826
2827 No need to enable the counter, it's enabled automatically by hardware
2828 (the counter starts in response to a stimulus and generate a pulse */
2829
2830 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2831 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2832
2833 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2834 {
2835 /* Enable the main output */
2836 __HAL_TIM_MOE_ENABLE(htim);
2837 }
2838
2839 /* Return function status */
2840 return HAL_OK;
2841 }
2842
2843 /**
2844 * @brief Stops the TIM One Pulse signal generation.
2845 * @note Though OutputChannel parameter is deprecated and ignored by the function
2846 * it has been kept to avoid HAL_TIM API compatibility break.
2847 * @note The pulse output channel is determined when calling
2848 * @ref HAL_TIM_OnePulse_ConfigChannel().
2849 * @param htim TIM One Pulse handle
2850 * @param OutputChannel See note above
2851 * @retval HAL status
2852 */
HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2853 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2854 {
2855 /* Prevent unused argument(s) compilation warning */
2856 UNUSED(OutputChannel);
2857
2858 /* Disable the Capture compare and the Input Capture channels
2859 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2860 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2861 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2862 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2863
2864 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2865 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2866
2867 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2868 {
2869 /* Disable the Main Output */
2870 __HAL_TIM_MOE_DISABLE(htim);
2871 }
2872
2873 /* Disable the Peripheral */
2874 __HAL_TIM_DISABLE(htim);
2875
2876 /* Set the TIM channels state */
2877 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2878 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2879 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2880 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2881
2882 /* Return function status */
2883 return HAL_OK;
2884 }
2885
2886 /**
2887 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
2888 * @note Though OutputChannel parameter is deprecated and ignored by the function
2889 * it has been kept to avoid HAL_TIM API compatibility break.
2890 * @note The pulse output channel is determined when calling
2891 * @ref HAL_TIM_OnePulse_ConfigChannel().
2892 * @param htim TIM One Pulse handle
2893 * @param OutputChannel See note above
2894 * @retval HAL status
2895 */
HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2896 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2897 {
2898 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
2899 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
2900 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
2901 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
2902
2903 /* Prevent unused argument(s) compilation warning */
2904 UNUSED(OutputChannel);
2905
2906 /* Check the TIM channels state */
2907 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2908 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
2909 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2910 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
2911 {
2912 return HAL_ERROR;
2913 }
2914
2915 /* Set the TIM channels state */
2916 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2917 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2918 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2919 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2920
2921 /* Enable the Capture compare and the Input Capture channels
2922 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2923 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2924 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2925 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2926
2927 No need to enable the counter, it's enabled automatically by hardware
2928 (the counter starts in response to a stimulus and generate a pulse */
2929
2930 /* Enable the TIM Capture/Compare 1 interrupt */
2931 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2932
2933 /* Enable the TIM Capture/Compare 2 interrupt */
2934 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2935
2936 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2937 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2938
2939 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2940 {
2941 /* Enable the main output */
2942 __HAL_TIM_MOE_ENABLE(htim);
2943 }
2944
2945 /* Return function status */
2946 return HAL_OK;
2947 }
2948
2949 /**
2950 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
2951 * @note Though OutputChannel parameter is deprecated and ignored by the function
2952 * it has been kept to avoid HAL_TIM API compatibility break.
2953 * @note The pulse output channel is determined when calling
2954 * @ref HAL_TIM_OnePulse_ConfigChannel().
2955 * @param htim TIM One Pulse handle
2956 * @param OutputChannel See note above
2957 * @retval HAL status
2958 */
HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2959 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2960 {
2961 /* Prevent unused argument(s) compilation warning */
2962 UNUSED(OutputChannel);
2963
2964 /* Disable the TIM Capture/Compare 1 interrupt */
2965 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2966
2967 /* Disable the TIM Capture/Compare 2 interrupt */
2968 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2969
2970 /* Disable the Capture compare and the Input Capture channels
2971 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2972 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2973 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2974 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2975 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2976 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2977
2978 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2979 {
2980 /* Disable the Main Output */
2981 __HAL_TIM_MOE_DISABLE(htim);
2982 }
2983
2984 /* Disable the Peripheral */
2985 __HAL_TIM_DISABLE(htim);
2986
2987 /* Set the TIM channels state */
2988 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2989 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2990 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2991 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2992
2993 /* Return function status */
2994 return HAL_OK;
2995 }
2996
2997 /**
2998 * @}
2999 */
3000
3001 /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
3002 * @brief TIM Encoder functions
3003 *
3004 @verbatim
3005 ==============================================================================
3006 ##### TIM Encoder functions #####
3007 ==============================================================================
3008 [..]
3009 This section provides functions allowing to:
3010 (+) Initialize and configure the TIM Encoder.
3011 (+) De-initialize the TIM Encoder.
3012 (+) Start the TIM Encoder.
3013 (+) Stop the TIM Encoder.
3014 (+) Start the TIM Encoder and enable interrupt.
3015 (+) Stop the TIM Encoder and disable interrupt.
3016 (+) Start the TIM Encoder and enable DMA transfer.
3017 (+) Stop the TIM Encoder and disable DMA transfer.
3018
3019 @endverbatim
3020 * @{
3021 */
3022 /**
3023 * @brief Initializes the TIM Encoder Interface and initialize the associated handle.
3024 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
3025 * requires a timer reset to avoid unexpected direction
3026 * due to DIR bit readonly in center aligned mode.
3027 * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
3028 * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together
3029 * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
3030 * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
3031 * @note When the timer instance is initialized in Encoder mode, timer
3032 * channels 1 and channel 2 are reserved and cannot be used for other
3033 * purpose.
3034 * @param htim TIM Encoder Interface handle
3035 * @param sConfig TIM Encoder Interface configuration structure
3036 * @retval HAL status
3037 */
HAL_TIM_Encoder_Init(TIM_HandleTypeDef * htim,const TIM_Encoder_InitTypeDef * sConfig)3038 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig)
3039 {
3040 uint32_t tmpsmcr;
3041 uint32_t tmpccmr1;
3042 uint32_t tmpccer;
3043
3044 /* Check the TIM handle allocation */
3045 if (htim == NULL)
3046 {
3047 return HAL_ERROR;
3048 }
3049
3050 /* Check the parameters */
3051 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3052 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
3053 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
3054 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
3055 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
3056 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
3057 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
3058 assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
3059 assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
3060 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
3061 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
3062 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
3063 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
3064 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
3065
3066 if (htim->State == HAL_TIM_STATE_RESET)
3067 {
3068 /* Allocate lock resource and initialize it */
3069 htim->Lock = HAL_UNLOCKED;
3070
3071 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3072 /* Reset interrupt callbacks to legacy weak callbacks */
3073 TIM_ResetCallback(htim);
3074
3075 if (htim->Encoder_MspInitCallback == NULL)
3076 {
3077 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
3078 }
3079 /* Init the low level hardware : GPIO, CLOCK, NVIC */
3080 htim->Encoder_MspInitCallback(htim);
3081 #else
3082 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
3083 HAL_TIM_Encoder_MspInit(htim);
3084 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3085 }
3086
3087 /* Set the TIM state */
3088 htim->State = HAL_TIM_STATE_BUSY;
3089
3090 /* Reset the SMS and ECE bits */
3091 htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
3092
3093 /* Configure the Time base in the Encoder Mode */
3094 TIM_Base_SetConfig(htim->Instance, &htim->Init);
3095
3096 /* Get the TIMx SMCR register value */
3097 tmpsmcr = htim->Instance->SMCR;
3098
3099 /* Get the TIMx CCMR1 register value */
3100 tmpccmr1 = htim->Instance->CCMR1;
3101
3102 /* Get the TIMx CCER register value */
3103 tmpccer = htim->Instance->CCER;
3104
3105 /* Set the encoder Mode */
3106 tmpsmcr |= sConfig->EncoderMode;
3107
3108 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
3109 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
3110 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
3111
3112 /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
3113 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
3114 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
3115 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
3116 tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
3117
3118 /* Set the TI1 and the TI2 Polarities */
3119 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
3120 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
3121 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
3122
3123 /* Write to TIMx SMCR */
3124 htim->Instance->SMCR = tmpsmcr;
3125
3126 /* Write to TIMx CCMR1 */
3127 htim->Instance->CCMR1 = tmpccmr1;
3128
3129 /* Write to TIMx CCER */
3130 htim->Instance->CCER = tmpccer;
3131
3132 /* Initialize the DMA burst operation state */
3133 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
3134
3135 /* Set the TIM channels state */
3136 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3137 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3138 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3139 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3140
3141 /* Initialize the TIM state*/
3142 htim->State = HAL_TIM_STATE_READY;
3143
3144 return HAL_OK;
3145 }
3146
3147
3148 /**
3149 * @brief DeInitializes the TIM Encoder interface
3150 * @param htim TIM Encoder Interface handle
3151 * @retval HAL status
3152 */
HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef * htim)3153 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
3154 {
3155 /* Check the parameters */
3156 assert_param(IS_TIM_INSTANCE(htim->Instance));
3157
3158 htim->State = HAL_TIM_STATE_BUSY;
3159
3160 /* Disable the TIM Peripheral Clock */
3161 __HAL_TIM_DISABLE(htim);
3162
3163 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3164 if (htim->Encoder_MspDeInitCallback == NULL)
3165 {
3166 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
3167 }
3168 /* DeInit the low level hardware */
3169 htim->Encoder_MspDeInitCallback(htim);
3170 #else
3171 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
3172 HAL_TIM_Encoder_MspDeInit(htim);
3173 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3174
3175 /* Change the DMA burst operation state */
3176 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
3177
3178 /* Set the TIM channels state */
3179 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
3180 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
3181 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
3182 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
3183
3184 /* Change TIM state */
3185 htim->State = HAL_TIM_STATE_RESET;
3186
3187 /* Release Lock */
3188 __HAL_UNLOCK(htim);
3189
3190 return HAL_OK;
3191 }
3192
3193 /**
3194 * @brief Initializes the TIM Encoder Interface MSP.
3195 * @param htim TIM Encoder Interface handle
3196 * @retval None
3197 */
HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef * htim)3198 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
3199 {
3200 /* Prevent unused argument(s) compilation warning */
3201 UNUSED(htim);
3202
3203 /* NOTE : This function should not be modified, when the callback is needed,
3204 the HAL_TIM_Encoder_MspInit could be implemented in the user file
3205 */
3206 }
3207
3208 /**
3209 * @brief DeInitializes TIM Encoder Interface MSP.
3210 * @param htim TIM Encoder Interface handle
3211 * @retval None
3212 */
HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef * htim)3213 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
3214 {
3215 /* Prevent unused argument(s) compilation warning */
3216 UNUSED(htim);
3217
3218 /* NOTE : This function should not be modified, when the callback is needed,
3219 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
3220 */
3221 }
3222
3223 /**
3224 * @brief Starts the TIM Encoder Interface.
3225 * @param htim TIM Encoder Interface handle
3226 * @param Channel TIM Channels to be enabled
3227 * This parameter can be one of the following values:
3228 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3229 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3230 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3231 * @retval HAL status
3232 */
HAL_TIM_Encoder_Start(TIM_HandleTypeDef * htim,uint32_t Channel)3233 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
3234 {
3235 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3236 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3237 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3238 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3239
3240 /* Check the parameters */
3241 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3242
3243 /* Set the TIM channel(s) state */
3244 if (Channel == TIM_CHANNEL_1)
3245 {
3246 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3247 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
3248 {
3249 return HAL_ERROR;
3250 }
3251 else
3252 {
3253 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3254 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3255 }
3256 }
3257 else if (Channel == TIM_CHANNEL_2)
3258 {
3259 if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3260 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3261 {
3262 return HAL_ERROR;
3263 }
3264 else
3265 {
3266 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3267 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3268 }
3269 }
3270 else
3271 {
3272 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3273 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3274 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3275 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3276 {
3277 return HAL_ERROR;
3278 }
3279 else
3280 {
3281 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3282 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3283 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3284 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3285 }
3286 }
3287
3288 /* Enable the encoder interface channels */
3289 switch (Channel)
3290 {
3291 case TIM_CHANNEL_1:
3292 {
3293 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3294 break;
3295 }
3296
3297 case TIM_CHANNEL_2:
3298 {
3299 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3300 break;
3301 }
3302
3303 default :
3304 {
3305 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3306 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3307 break;
3308 }
3309 }
3310 /* Enable the Peripheral */
3311 __HAL_TIM_ENABLE(htim);
3312
3313 /* Return function status */
3314 return HAL_OK;
3315 }
3316
3317 /**
3318 * @brief Stops the TIM Encoder Interface.
3319 * @param htim TIM Encoder Interface handle
3320 * @param Channel TIM Channels to be disabled
3321 * This parameter can be one of the following values:
3322 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3323 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3324 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3325 * @retval HAL status
3326 */
HAL_TIM_Encoder_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)3327 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
3328 {
3329 /* Check the parameters */
3330 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3331
3332 /* Disable the Input Capture channels 1 and 2
3333 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3334 switch (Channel)
3335 {
3336 case TIM_CHANNEL_1:
3337 {
3338 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3339 break;
3340 }
3341
3342 case TIM_CHANNEL_2:
3343 {
3344 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3345 break;
3346 }
3347
3348 default :
3349 {
3350 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3351 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3352 break;
3353 }
3354 }
3355
3356 /* Disable the Peripheral */
3357 __HAL_TIM_DISABLE(htim);
3358
3359 /* Set the TIM channel(s) state */
3360 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3361 {
3362 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3363 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3364 }
3365 else
3366 {
3367 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3368 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3369 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3370 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3371 }
3372
3373 /* Return function status */
3374 return HAL_OK;
3375 }
3376
3377 /**
3378 * @brief Starts the TIM Encoder Interface in interrupt mode.
3379 * @param htim TIM Encoder Interface handle
3380 * @param Channel TIM Channels to be enabled
3381 * This parameter can be one of the following values:
3382 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3383 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3384 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3385 * @retval HAL status
3386 */
HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)3387 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
3388 {
3389 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3390 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3391 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3392 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3393
3394 /* Check the parameters */
3395 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3396
3397 /* Set the TIM channel(s) state */
3398 if (Channel == TIM_CHANNEL_1)
3399 {
3400 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3401 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
3402 {
3403 return HAL_ERROR;
3404 }
3405 else
3406 {
3407 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3408 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3409 }
3410 }
3411 else if (Channel == TIM_CHANNEL_2)
3412 {
3413 if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3414 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3415 {
3416 return HAL_ERROR;
3417 }
3418 else
3419 {
3420 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3421 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3422 }
3423 }
3424 else
3425 {
3426 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3427 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3428 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3429 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3430 {
3431 return HAL_ERROR;
3432 }
3433 else
3434 {
3435 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3436 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3437 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3438 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3439 }
3440 }
3441
3442 /* Enable the encoder interface channels */
3443 /* Enable the capture compare Interrupts 1 and/or 2 */
3444 switch (Channel)
3445 {
3446 case TIM_CHANNEL_1:
3447 {
3448 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3449 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
3450 break;
3451 }
3452
3453 case TIM_CHANNEL_2:
3454 {
3455 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3456 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
3457 break;
3458 }
3459
3460 default :
3461 {
3462 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3463 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3464 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
3465 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
3466 break;
3467 }
3468 }
3469
3470 /* Enable the Peripheral */
3471 __HAL_TIM_ENABLE(htim);
3472
3473 /* Return function status */
3474 return HAL_OK;
3475 }
3476
3477 /**
3478 * @brief Stops the TIM Encoder Interface in interrupt mode.
3479 * @param htim TIM Encoder Interface handle
3480 * @param Channel TIM Channels to be disabled
3481 * This parameter can be one of the following values:
3482 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3483 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3484 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3485 * @retval HAL status
3486 */
HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)3487 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
3488 {
3489 /* Check the parameters */
3490 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3491
3492 /* Disable the Input Capture channels 1 and 2
3493 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3494 if (Channel == TIM_CHANNEL_1)
3495 {
3496 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3497
3498 /* Disable the capture compare Interrupts 1 */
3499 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
3500 }
3501 else if (Channel == TIM_CHANNEL_2)
3502 {
3503 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3504
3505 /* Disable the capture compare Interrupts 2 */
3506 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
3507 }
3508 else
3509 {
3510 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3511 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3512
3513 /* Disable the capture compare Interrupts 1 and 2 */
3514 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
3515 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
3516 }
3517
3518 /* Disable the Peripheral */
3519 __HAL_TIM_DISABLE(htim);
3520
3521 /* Set the TIM channel(s) state */
3522 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3523 {
3524 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3525 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3526 }
3527 else
3528 {
3529 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3530 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3531 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3532 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3533 }
3534
3535 /* Return function status */
3536 return HAL_OK;
3537 }
3538
3539 /**
3540 * @brief Starts the TIM Encoder Interface in DMA mode.
3541 * @param htim TIM Encoder Interface handle
3542 * @param Channel TIM Channels to be enabled
3543 * This parameter can be one of the following values:
3544 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3545 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3546 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3547 * @param pData1 The destination Buffer address for IC1.
3548 * @param pData2 The destination Buffer address for IC2.
3549 * @param Length The length of data to be transferred from TIM peripheral to memory.
3550 * @retval HAL status
3551 */
HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData1,uint32_t * pData2,uint16_t Length)3552 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
3553 uint32_t *pData2, uint16_t Length)
3554 {
3555 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3556 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3557 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3558 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3559
3560 /* Check the parameters */
3561 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3562
3563 /* Set the TIM channel(s) state */
3564 if (Channel == TIM_CHANNEL_1)
3565 {
3566 if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3567 || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
3568 {
3569 return HAL_BUSY;
3570 }
3571 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3572 && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
3573 {
3574 if ((pData1 == NULL) || (Length == 0U))
3575 {
3576 return HAL_ERROR;
3577 }
3578 else
3579 {
3580 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3581 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3582 }
3583 }
3584 else
3585 {
3586 return HAL_ERROR;
3587 }
3588 }
3589 else if (Channel == TIM_CHANNEL_2)
3590 {
3591 if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
3592 || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
3593 {
3594 return HAL_BUSY;
3595 }
3596 else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
3597 && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
3598 {
3599 if ((pData2 == NULL) || (Length == 0U))
3600 {
3601 return HAL_ERROR;
3602 }
3603 else
3604 {
3605 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3606 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3607 }
3608 }
3609 else
3610 {
3611 return HAL_ERROR;
3612 }
3613 }
3614 else
3615 {
3616 if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3617 || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
3618 || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3619 || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
3620 {
3621 return HAL_BUSY;
3622 }
3623 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3624 && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
3625 && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3626 && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
3627 {
3628 if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U))
3629 {
3630 return HAL_ERROR;
3631 }
3632 else
3633 {
3634 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3635 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3636 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3637 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3638 }
3639 }
3640 else
3641 {
3642 return HAL_ERROR;
3643 }
3644 }
3645
3646 switch (Channel)
3647 {
3648 case TIM_CHANNEL_1:
3649 {
3650 /* Set the DMA capture callbacks */
3651 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3652 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3653
3654 /* Set the DMA error callback */
3655 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3656
3657 /* Enable the DMA channel */
3658 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
3659 Length) != HAL_OK)
3660 {
3661 /* Return error status */
3662 return HAL_ERROR;
3663 }
3664 /* Enable the TIM Input Capture DMA request */
3665 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3666
3667 /* Enable the Capture compare channel */
3668 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3669
3670 /* Enable the Peripheral */
3671 __HAL_TIM_ENABLE(htim);
3672
3673 break;
3674 }
3675
3676 case TIM_CHANNEL_2:
3677 {
3678 /* Set the DMA capture callbacks */
3679 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3680 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3681
3682 /* Set the DMA error callback */
3683 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
3684 /* Enable the DMA channel */
3685 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
3686 Length) != HAL_OK)
3687 {
3688 /* Return error status */
3689 return HAL_ERROR;
3690 }
3691 /* Enable the TIM Input Capture DMA request */
3692 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3693
3694 /* Enable the Capture compare channel */
3695 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3696
3697 /* Enable the Peripheral */
3698 __HAL_TIM_ENABLE(htim);
3699
3700 break;
3701 }
3702
3703 default:
3704 {
3705 /* Set the DMA capture callbacks */
3706 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3707 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3708
3709 /* Set the DMA error callback */
3710 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3711
3712 /* Enable the DMA channel */
3713 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
3714 Length) != HAL_OK)
3715 {
3716 /* Return error status */
3717 return HAL_ERROR;
3718 }
3719
3720 /* Set the DMA capture callbacks */
3721 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3722 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3723
3724 /* Set the DMA error callback */
3725 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
3726
3727 /* Enable the DMA channel */
3728 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
3729 Length) != HAL_OK)
3730 {
3731 /* Return error status */
3732 return HAL_ERROR;
3733 }
3734
3735 /* Enable the TIM Input Capture DMA request */
3736 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3737 /* Enable the TIM Input Capture DMA request */
3738 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3739
3740 /* Enable the Capture compare channel */
3741 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3742 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3743
3744 /* Enable the Peripheral */
3745 __HAL_TIM_ENABLE(htim);
3746
3747 break;
3748 }
3749 }
3750
3751 /* Return function status */
3752 return HAL_OK;
3753 }
3754
3755 /**
3756 * @brief Stops the TIM Encoder Interface in DMA mode.
3757 * @param htim TIM Encoder Interface handle
3758 * @param Channel TIM Channels to be enabled
3759 * This parameter can be one of the following values:
3760 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3761 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3762 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3763 * @retval HAL status
3764 */
HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)3765 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
3766 {
3767 /* Check the parameters */
3768 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3769
3770 /* Disable the Input Capture channels 1 and 2
3771 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3772 if (Channel == TIM_CHANNEL_1)
3773 {
3774 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3775
3776 /* Disable the capture compare DMA Request 1 */
3777 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3778 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3779 }
3780 else if (Channel == TIM_CHANNEL_2)
3781 {
3782 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3783
3784 /* Disable the capture compare DMA Request 2 */
3785 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3786 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3787 }
3788 else
3789 {
3790 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3791 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3792
3793 /* Disable the capture compare DMA Request 1 and 2 */
3794 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3795 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3796 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3797 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3798 }
3799
3800 /* Disable the Peripheral */
3801 __HAL_TIM_DISABLE(htim);
3802
3803 /* Set the TIM channel(s) state */
3804 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3805 {
3806 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3807 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3808 }
3809 else
3810 {
3811 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3812 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3813 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3814 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3815 }
3816
3817 /* Return function status */
3818 return HAL_OK;
3819 }
3820
3821 /**
3822 * @}
3823 */
3824 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
3825 * @brief TIM IRQ handler management
3826 *
3827 @verbatim
3828 ==============================================================================
3829 ##### IRQ handler management #####
3830 ==============================================================================
3831 [..]
3832 This section provides Timer IRQ handler function.
3833
3834 @endverbatim
3835 * @{
3836 */
3837 /**
3838 * @brief This function handles TIM interrupts requests.
3839 * @param htim TIM handle
3840 * @retval None
3841 */
HAL_TIM_IRQHandler(TIM_HandleTypeDef * htim)3842 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
3843 {
3844 /* Capture compare 1 event */
3845 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
3846 {
3847 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
3848 {
3849 {
3850 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
3851 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
3852
3853 /* Input capture event */
3854 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
3855 {
3856 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3857 htim->IC_CaptureCallback(htim);
3858 #else
3859 HAL_TIM_IC_CaptureCallback(htim);
3860 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3861 }
3862 /* Output compare event */
3863 else
3864 {
3865 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3866 htim->OC_DelayElapsedCallback(htim);
3867 htim->PWM_PulseFinishedCallback(htim);
3868 #else
3869 HAL_TIM_OC_DelayElapsedCallback(htim);
3870 HAL_TIM_PWM_PulseFinishedCallback(htim);
3871 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3872 }
3873 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3874 }
3875 }
3876 }
3877 /* Capture compare 2 event */
3878 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
3879 {
3880 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
3881 {
3882 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
3883 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
3884 /* Input capture event */
3885 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
3886 {
3887 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3888 htim->IC_CaptureCallback(htim);
3889 #else
3890 HAL_TIM_IC_CaptureCallback(htim);
3891 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3892 }
3893 /* Output compare event */
3894 else
3895 {
3896 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3897 htim->OC_DelayElapsedCallback(htim);
3898 htim->PWM_PulseFinishedCallback(htim);
3899 #else
3900 HAL_TIM_OC_DelayElapsedCallback(htim);
3901 HAL_TIM_PWM_PulseFinishedCallback(htim);
3902 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3903 }
3904 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3905 }
3906 }
3907 /* Capture compare 3 event */
3908 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
3909 {
3910 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
3911 {
3912 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
3913 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
3914 /* Input capture event */
3915 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
3916 {
3917 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3918 htim->IC_CaptureCallback(htim);
3919 #else
3920 HAL_TIM_IC_CaptureCallback(htim);
3921 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3922 }
3923 /* Output compare event */
3924 else
3925 {
3926 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3927 htim->OC_DelayElapsedCallback(htim);
3928 htim->PWM_PulseFinishedCallback(htim);
3929 #else
3930 HAL_TIM_OC_DelayElapsedCallback(htim);
3931 HAL_TIM_PWM_PulseFinishedCallback(htim);
3932 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3933 }
3934 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3935 }
3936 }
3937 /* Capture compare 4 event */
3938 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
3939 {
3940 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
3941 {
3942 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
3943 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
3944 /* Input capture event */
3945 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
3946 {
3947 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3948 htim->IC_CaptureCallback(htim);
3949 #else
3950 HAL_TIM_IC_CaptureCallback(htim);
3951 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3952 }
3953 /* Output compare event */
3954 else
3955 {
3956 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3957 htim->OC_DelayElapsedCallback(htim);
3958 htim->PWM_PulseFinishedCallback(htim);
3959 #else
3960 HAL_TIM_OC_DelayElapsedCallback(htim);
3961 HAL_TIM_PWM_PulseFinishedCallback(htim);
3962 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3963 }
3964 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3965 }
3966 }
3967 /* TIM Update event */
3968 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
3969 {
3970 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
3971 {
3972 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
3973 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3974 htim->PeriodElapsedCallback(htim);
3975 #else
3976 HAL_TIM_PeriodElapsedCallback(htim);
3977 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3978 }
3979 }
3980 /* TIM Break input event */
3981 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
3982 {
3983 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
3984 {
3985 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
3986 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3987 htim->BreakCallback(htim);
3988 #else
3989 HAL_TIMEx_BreakCallback(htim);
3990 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3991 }
3992 }
3993 #if defined(TIM_BDTR_BK2E)
3994 /* TIM Break2 input event */
3995 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
3996 {
3997 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
3998 {
3999 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
4000 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4001 htim->Break2Callback(htim);
4002 #else
4003 HAL_TIMEx_Break2Callback(htim);
4004 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4005 }
4006 }
4007 #endif /* TIM_BDTR_BK2E */
4008 /* TIM Trigger detection event */
4009 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
4010 {
4011 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
4012 {
4013 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
4014 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4015 htim->TriggerCallback(htim);
4016 #else
4017 HAL_TIM_TriggerCallback(htim);
4018 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4019 }
4020 }
4021 /* TIM commutation event */
4022 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
4023 {
4024 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
4025 {
4026 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
4027 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4028 htim->CommutationCallback(htim);
4029 #else
4030 HAL_TIMEx_CommutCallback(htim);
4031 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4032 }
4033 }
4034 }
4035
4036 /**
4037 * @}
4038 */
4039
4040 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
4041 * @brief TIM Peripheral Control functions
4042 *
4043 @verbatim
4044 ==============================================================================
4045 ##### Peripheral Control functions #####
4046 ==============================================================================
4047 [..]
4048 This section provides functions allowing to:
4049 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
4050 (+) Configure External Clock source.
4051 (+) Configure Complementary channels, break features and dead time.
4052 (+) Configure Master and the Slave synchronization.
4053 (+) Configure the DMA Burst Mode.
4054
4055 @endverbatim
4056 * @{
4057 */
4058
4059 /**
4060 * @brief Initializes the TIM Output Compare Channels according to the specified
4061 * parameters in the TIM_OC_InitTypeDef.
4062 * @param htim TIM Output Compare handle
4063 * @param sConfig TIM Output Compare configuration structure
4064 * @param Channel TIM Channels to configure
4065 * This parameter can be one of the following values:
4066 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4067 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4068 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4069 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4070 * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*)
4071 * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*)
4072 * (*) Value not defined for all devices
4073 * @retval HAL status
4074 */
HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef * htim,const TIM_OC_InitTypeDef * sConfig,uint32_t Channel)4075 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
4076 const TIM_OC_InitTypeDef *sConfig,
4077 uint32_t Channel)
4078 {
4079 HAL_StatusTypeDef status = HAL_OK;
4080
4081 /* Check the parameters */
4082 assert_param(IS_TIM_CHANNELS(Channel));
4083 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
4084 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
4085
4086 /* Process Locked */
4087 __HAL_LOCK(htim);
4088
4089 switch (Channel)
4090 {
4091 case TIM_CHANNEL_1:
4092 {
4093 /* Check the parameters */
4094 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4095
4096 /* Configure the TIM Channel 1 in Output Compare */
4097 TIM_OC1_SetConfig(htim->Instance, sConfig);
4098 break;
4099 }
4100
4101 case TIM_CHANNEL_2:
4102 {
4103 /* Check the parameters */
4104 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4105
4106 /* Configure the TIM Channel 2 in Output Compare */
4107 TIM_OC2_SetConfig(htim->Instance, sConfig);
4108 break;
4109 }
4110
4111 case TIM_CHANNEL_3:
4112 {
4113 /* Check the parameters */
4114 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4115
4116 /* Configure the TIM Channel 3 in Output Compare */
4117 TIM_OC3_SetConfig(htim->Instance, sConfig);
4118 break;
4119 }
4120
4121 case TIM_CHANNEL_4:
4122 {
4123 /* Check the parameters */
4124 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4125
4126 /* Configure the TIM Channel 4 in Output Compare */
4127 TIM_OC4_SetConfig(htim->Instance, sConfig);
4128 break;
4129 }
4130
4131 #if defined(TIM_CCER_CC5E)
4132 case TIM_CHANNEL_5:
4133 {
4134 /* Check the parameters */
4135 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
4136
4137 /* Configure the TIM Channel 5 in Output Compare */
4138 TIM_OC5_SetConfig(htim->Instance, sConfig);
4139 break;
4140 }
4141 #endif /* TIM_CCER_CC5E */
4142
4143 #if defined(TIM_CCER_CC6E)
4144 case TIM_CHANNEL_6:
4145 {
4146 /* Check the parameters */
4147 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
4148
4149 /* Configure the TIM Channel 6 in Output Compare */
4150 TIM_OC6_SetConfig(htim->Instance, sConfig);
4151 break;
4152 }
4153 #endif /* TIM_CCER_CC6E */
4154
4155 default:
4156 status = HAL_ERROR;
4157 break;
4158 }
4159
4160 __HAL_UNLOCK(htim);
4161
4162 return status;
4163 }
4164
4165 /**
4166 * @brief Initializes the TIM Input Capture Channels according to the specified
4167 * parameters in the TIM_IC_InitTypeDef.
4168 * @param htim TIM IC handle
4169 * @param sConfig TIM Input Capture configuration structure
4170 * @param Channel TIM Channel to configure
4171 * This parameter can be one of the following values:
4172 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4173 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4174 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4175 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4176 * @retval HAL status
4177 */
HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef * htim,const TIM_IC_InitTypeDef * sConfig,uint32_t Channel)4178 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
4179 {
4180 HAL_StatusTypeDef status = HAL_OK;
4181
4182 /* Check the parameters */
4183 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4184 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
4185 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
4186 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
4187 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
4188
4189 /* Process Locked */
4190 __HAL_LOCK(htim);
4191
4192 if (Channel == TIM_CHANNEL_1)
4193 {
4194 /* TI1 Configuration */
4195 TIM_TI1_SetConfig(htim->Instance,
4196 sConfig->ICPolarity,
4197 sConfig->ICSelection,
4198 sConfig->ICFilter);
4199
4200 /* Reset the IC1PSC Bits */
4201 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
4202
4203 /* Set the IC1PSC value */
4204 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
4205 }
4206 else if (Channel == TIM_CHANNEL_2)
4207 {
4208 /* TI2 Configuration */
4209 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4210
4211 TIM_TI2_SetConfig(htim->Instance,
4212 sConfig->ICPolarity,
4213 sConfig->ICSelection,
4214 sConfig->ICFilter);
4215
4216 /* Reset the IC2PSC Bits */
4217 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
4218
4219 /* Set the IC2PSC value */
4220 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
4221 }
4222 else if (Channel == TIM_CHANNEL_3)
4223 {
4224 /* TI3 Configuration */
4225 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4226
4227 TIM_TI3_SetConfig(htim->Instance,
4228 sConfig->ICPolarity,
4229 sConfig->ICSelection,
4230 sConfig->ICFilter);
4231
4232 /* Reset the IC3PSC Bits */
4233 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
4234
4235 /* Set the IC3PSC value */
4236 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
4237 }
4238 else if (Channel == TIM_CHANNEL_4)
4239 {
4240 /* TI4 Configuration */
4241 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4242
4243 TIM_TI4_SetConfig(htim->Instance,
4244 sConfig->ICPolarity,
4245 sConfig->ICSelection,
4246 sConfig->ICFilter);
4247
4248 /* Reset the IC4PSC Bits */
4249 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
4250
4251 /* Set the IC4PSC value */
4252 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
4253 }
4254 else
4255 {
4256 status = HAL_ERROR;
4257 }
4258
4259 __HAL_UNLOCK(htim);
4260
4261 return status;
4262 }
4263
4264 /**
4265 * @brief Initializes the TIM PWM channels according to the specified
4266 * parameters in the TIM_OC_InitTypeDef.
4267 * @param htim TIM PWM handle
4268 * @param sConfig TIM PWM configuration structure
4269 * @param Channel TIM Channels to be configured
4270 * This parameter can be one of the following values:
4271 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4272 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4273 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4274 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4275 * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*)
4276 * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*)
4277 * (*) Value not defined for all devices
4278 * @retval HAL status
4279 */
HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef * htim,const TIM_OC_InitTypeDef * sConfig,uint32_t Channel)4280 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
4281 const TIM_OC_InitTypeDef *sConfig,
4282 uint32_t Channel)
4283 {
4284 HAL_StatusTypeDef status = HAL_OK;
4285
4286 /* Check the parameters */
4287 assert_param(IS_TIM_CHANNELS(Channel));
4288 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
4289 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
4290 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
4291
4292 /* Process Locked */
4293 __HAL_LOCK(htim);
4294
4295 switch (Channel)
4296 {
4297 case TIM_CHANNEL_1:
4298 {
4299 /* Check the parameters */
4300 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4301
4302 /* Configure the Channel 1 in PWM mode */
4303 TIM_OC1_SetConfig(htim->Instance, sConfig);
4304
4305 /* Set the Preload enable bit for channel1 */
4306 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
4307
4308 /* Configure the Output Fast mode */
4309 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
4310 htim->Instance->CCMR1 |= sConfig->OCFastMode;
4311 break;
4312 }
4313
4314 case TIM_CHANNEL_2:
4315 {
4316 /* Check the parameters */
4317 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4318
4319 /* Configure the Channel 2 in PWM mode */
4320 TIM_OC2_SetConfig(htim->Instance, sConfig);
4321
4322 /* Set the Preload enable bit for channel2 */
4323 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
4324
4325 /* Configure the Output Fast mode */
4326 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
4327 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
4328 break;
4329 }
4330
4331 case TIM_CHANNEL_3:
4332 {
4333 /* Check the parameters */
4334 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4335
4336 /* Configure the Channel 3 in PWM mode */
4337 TIM_OC3_SetConfig(htim->Instance, sConfig);
4338
4339 /* Set the Preload enable bit for channel3 */
4340 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
4341
4342 /* Configure the Output Fast mode */
4343 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
4344 htim->Instance->CCMR2 |= sConfig->OCFastMode;
4345 break;
4346 }
4347
4348 case TIM_CHANNEL_4:
4349 {
4350 /* Check the parameters */
4351 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4352
4353 /* Configure the Channel 4 in PWM mode */
4354 TIM_OC4_SetConfig(htim->Instance, sConfig);
4355
4356 /* Set the Preload enable bit for channel4 */
4357 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
4358
4359 /* Configure the Output Fast mode */
4360 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
4361 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
4362 break;
4363 }
4364
4365 #if defined(TIM_CCER_CC5E)
4366 case TIM_CHANNEL_5:
4367 {
4368 /* Check the parameters */
4369 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
4370
4371 /* Configure the Channel 5 in PWM mode */
4372 TIM_OC5_SetConfig(htim->Instance, sConfig);
4373
4374 /* Set the Preload enable bit for channel5*/
4375 htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
4376
4377 /* Configure the Output Fast mode */
4378 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
4379 htim->Instance->CCMR3 |= sConfig->OCFastMode;
4380 break;
4381 }
4382 #endif /* TIM_CCER_CC5E */
4383
4384 #if defined(TIM_CCER_CC6E)
4385 case TIM_CHANNEL_6:
4386 {
4387 /* Check the parameters */
4388 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
4389
4390 /* Configure the Channel 6 in PWM mode */
4391 TIM_OC6_SetConfig(htim->Instance, sConfig);
4392
4393 /* Set the Preload enable bit for channel6 */
4394 htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
4395
4396 /* Configure the Output Fast mode */
4397 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
4398 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
4399 break;
4400 }
4401 #endif /* TIM_CCER_CC6E */
4402
4403 default:
4404 status = HAL_ERROR;
4405 break;
4406 }
4407
4408 __HAL_UNLOCK(htim);
4409
4410 return status;
4411 }
4412
4413 /**
4414 * @brief Initializes the TIM One Pulse Channels according to the specified
4415 * parameters in the TIM_OnePulse_InitTypeDef.
4416 * @param htim TIM One Pulse handle
4417 * @param sConfig TIM One Pulse configuration structure
4418 * @param OutputChannel TIM output channel to configure
4419 * This parameter can be one of the following values:
4420 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4421 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4422 * @param InputChannel TIM input Channel to configure
4423 * This parameter can be one of the following values:
4424 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4425 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4426 * @note To output a waveform with a minimum delay user can enable the fast
4427 * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
4428 * output is forced in response to the edge detection on TIx input,
4429 * without taking in account the comparison.
4430 * @retval HAL status
4431 */
HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef * htim,TIM_OnePulse_InitTypeDef * sConfig,uint32_t OutputChannel,uint32_t InputChannel)4432 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
4433 uint32_t OutputChannel, uint32_t InputChannel)
4434 {
4435 HAL_StatusTypeDef status = HAL_OK;
4436 TIM_OC_InitTypeDef temp1;
4437
4438 /* Check the parameters */
4439 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
4440 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
4441
4442 if (OutputChannel != InputChannel)
4443 {
4444 /* Process Locked */
4445 __HAL_LOCK(htim);
4446
4447 htim->State = HAL_TIM_STATE_BUSY;
4448
4449 /* Extract the Output compare configuration from sConfig structure */
4450 temp1.OCMode = sConfig->OCMode;
4451 temp1.Pulse = sConfig->Pulse;
4452 temp1.OCPolarity = sConfig->OCPolarity;
4453 temp1.OCNPolarity = sConfig->OCNPolarity;
4454 temp1.OCIdleState = sConfig->OCIdleState;
4455 temp1.OCNIdleState = sConfig->OCNIdleState;
4456
4457 switch (OutputChannel)
4458 {
4459 case TIM_CHANNEL_1:
4460 {
4461 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4462
4463 TIM_OC1_SetConfig(htim->Instance, &temp1);
4464 break;
4465 }
4466
4467 case TIM_CHANNEL_2:
4468 {
4469 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4470
4471 TIM_OC2_SetConfig(htim->Instance, &temp1);
4472 break;
4473 }
4474
4475 default:
4476 status = HAL_ERROR;
4477 break;
4478 }
4479
4480 if (status == HAL_OK)
4481 {
4482 switch (InputChannel)
4483 {
4484 case TIM_CHANNEL_1:
4485 {
4486 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4487
4488 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
4489 sConfig->ICSelection, sConfig->ICFilter);
4490
4491 /* Reset the IC1PSC Bits */
4492 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
4493
4494 /* Select the Trigger source */
4495 htim->Instance->SMCR &= ~TIM_SMCR_TS;
4496 htim->Instance->SMCR |= TIM_TS_TI1FP1;
4497
4498 /* Select the Slave Mode */
4499 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
4500 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
4501 break;
4502 }
4503
4504 case TIM_CHANNEL_2:
4505 {
4506 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4507
4508 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
4509 sConfig->ICSelection, sConfig->ICFilter);
4510
4511 /* Reset the IC2PSC Bits */
4512 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
4513
4514 /* Select the Trigger source */
4515 htim->Instance->SMCR &= ~TIM_SMCR_TS;
4516 htim->Instance->SMCR |= TIM_TS_TI2FP2;
4517
4518 /* Select the Slave Mode */
4519 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
4520 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
4521 break;
4522 }
4523
4524 default:
4525 status = HAL_ERROR;
4526 break;
4527 }
4528 }
4529
4530 htim->State = HAL_TIM_STATE_READY;
4531
4532 __HAL_UNLOCK(htim);
4533
4534 return status;
4535 }
4536 else
4537 {
4538 return HAL_ERROR;
4539 }
4540 }
4541
4542 /**
4543 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
4544 * @param htim TIM handle
4545 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
4546 * This parameter can be one of the following values:
4547 * @arg TIM_DMABASE_CR1
4548 * @arg TIM_DMABASE_CR2
4549 * @arg TIM_DMABASE_SMCR
4550 * @arg TIM_DMABASE_DIER
4551 * @arg TIM_DMABASE_SR
4552 * @arg TIM_DMABASE_EGR
4553 * @arg TIM_DMABASE_CCMR1
4554 * @arg TIM_DMABASE_CCMR2
4555 * @arg TIM_DMABASE_CCER
4556 * @arg TIM_DMABASE_CNT
4557 * @arg TIM_DMABASE_PSC
4558 * @arg TIM_DMABASE_ARR
4559 * @arg TIM_DMABASE_RCR
4560 * @arg TIM_DMABASE_CCR1
4561 * @arg TIM_DMABASE_CCR2
4562 * @arg TIM_DMABASE_CCR3
4563 * @arg TIM_DMABASE_CCR4
4564 * @arg TIM_DMABASE_BDTR
4565 * @arg TIM_DMABASE_OR
4566 * @arg TIM_DMABASE_CCMR3 (*)
4567 * @arg TIM_DMABASE_CCR5 (*)
4568 * @arg TIM_DMABASE_CCR6 (*)
4569 * (*) value not defined in all devices
4570 * @param BurstRequestSrc TIM DMA Request sources
4571 * This parameter can be one of the following values:
4572 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4573 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4574 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4575 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4576 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4577 * @arg TIM_DMA_COM: TIM Commutation DMA source
4578 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4579 * @param BurstBuffer The Buffer address.
4580 * @param BurstLength DMA Burst length. This parameter can be one value
4581 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4582 * @note This function should be used only when BurstLength is equal to DMA data transfer length.
4583 * @retval HAL status
4584 */
HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,const uint32_t * BurstBuffer,uint32_t BurstLength)4585 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4586 uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength)
4587 {
4588 HAL_StatusTypeDef status;
4589
4590 status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
4591 ((BurstLength) >> 8U) + 1U);
4592
4593
4594
4595 return status;
4596 }
4597
4598 /**
4599 * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
4600 * @param htim TIM handle
4601 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
4602 * This parameter can be one of the following values:
4603 * @arg TIM_DMABASE_CR1
4604 * @arg TIM_DMABASE_CR2
4605 * @arg TIM_DMABASE_SMCR
4606 * @arg TIM_DMABASE_DIER
4607 * @arg TIM_DMABASE_SR
4608 * @arg TIM_DMABASE_EGR
4609 * @arg TIM_DMABASE_CCMR1
4610 * @arg TIM_DMABASE_CCMR2
4611 * @arg TIM_DMABASE_CCER
4612 * @arg TIM_DMABASE_CNT
4613 * @arg TIM_DMABASE_PSC
4614 * @arg TIM_DMABASE_ARR
4615 * @arg TIM_DMABASE_RCR
4616 * @arg TIM_DMABASE_CCR1
4617 * @arg TIM_DMABASE_CCR2
4618 * @arg TIM_DMABASE_CCR3
4619 * @arg TIM_DMABASE_CCR4
4620 * @arg TIM_DMABASE_BDTR
4621 * @arg TIM_DMABASE_OR
4622 * @arg TIM_DMABASE_CCMR3 (*)
4623 * @arg TIM_DMABASE_CCR5 (*)
4624 * @arg TIM_DMABASE_CCR6 (*)
4625 * (*) value not defined in all devices
4626 * @param BurstRequestSrc TIM DMA Request sources
4627 * This parameter can be one of the following values:
4628 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4629 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4630 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4631 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4632 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4633 * @arg TIM_DMA_COM: TIM Commutation DMA source
4634 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4635 * @param BurstBuffer The Buffer address.
4636 * @param BurstLength DMA Burst length. This parameter can be one value
4637 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4638 * @param DataLength Data length. This parameter can be one value
4639 * between 1 and 0xFFFF.
4640 * @retval HAL status
4641 */
HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,const uint32_t * BurstBuffer,uint32_t BurstLength,uint32_t DataLength)4642 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4643 uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
4644 uint32_t BurstLength, uint32_t DataLength)
4645 {
4646 HAL_StatusTypeDef status = HAL_OK;
4647
4648 /* Check the parameters */
4649 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
4650 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
4651 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4652 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
4653 assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
4654
4655 if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
4656 {
4657 return HAL_BUSY;
4658 }
4659 else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
4660 {
4661 if ((BurstBuffer == NULL) && (BurstLength > 0U))
4662 {
4663 return HAL_ERROR;
4664 }
4665 else
4666 {
4667 htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
4668 }
4669 }
4670 else
4671 {
4672 /* nothing to do */
4673 }
4674
4675 switch (BurstRequestSrc)
4676 {
4677 case TIM_DMA_UPDATE:
4678 {
4679 /* Set the DMA Period elapsed callbacks */
4680 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
4681 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
4682
4683 /* Set the DMA error callback */
4684 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
4685
4686 /* Enable the DMA channel */
4687 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
4688 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4689 {
4690 /* Return error status */
4691 return HAL_ERROR;
4692 }
4693 break;
4694 }
4695 case TIM_DMA_CC1:
4696 {
4697 /* Set the DMA compare callbacks */
4698 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
4699 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4700
4701 /* Set the DMA error callback */
4702 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
4703
4704 /* Enable the DMA channel */
4705 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
4706 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4707 {
4708 /* Return error status */
4709 return HAL_ERROR;
4710 }
4711 break;
4712 }
4713 case TIM_DMA_CC2:
4714 {
4715 /* Set the DMA compare callbacks */
4716 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
4717 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4718
4719 /* Set the DMA error callback */
4720 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
4721
4722 /* Enable the DMA channel */
4723 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
4724 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4725 {
4726 /* Return error status */
4727 return HAL_ERROR;
4728 }
4729 break;
4730 }
4731 case TIM_DMA_CC3:
4732 {
4733 /* Set the DMA compare callbacks */
4734 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
4735 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4736
4737 /* Set the DMA error callback */
4738 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
4739
4740 /* Enable the DMA channel */
4741 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
4742 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4743 {
4744 /* Return error status */
4745 return HAL_ERROR;
4746 }
4747 break;
4748 }
4749 case TIM_DMA_CC4:
4750 {
4751 /* Set the DMA compare callbacks */
4752 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
4753 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4754
4755 /* Set the DMA error callback */
4756 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
4757
4758 /* Enable the DMA channel */
4759 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
4760 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4761 {
4762 /* Return error status */
4763 return HAL_ERROR;
4764 }
4765 break;
4766 }
4767 case TIM_DMA_COM:
4768 {
4769 /* Set the DMA commutation callbacks */
4770 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
4771 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
4772
4773 /* Set the DMA error callback */
4774 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
4775
4776 /* Enable the DMA channel */
4777 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
4778 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4779 {
4780 /* Return error status */
4781 return HAL_ERROR;
4782 }
4783 break;
4784 }
4785 case TIM_DMA_TRIGGER:
4786 {
4787 /* Set the DMA trigger callbacks */
4788 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
4789 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
4790
4791 /* Set the DMA error callback */
4792 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
4793
4794 /* Enable the DMA channel */
4795 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
4796 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4797 {
4798 /* Return error status */
4799 return HAL_ERROR;
4800 }
4801 break;
4802 }
4803 default:
4804 status = HAL_ERROR;
4805 break;
4806 }
4807
4808 if (status == HAL_OK)
4809 {
4810 /* Configure the DMA Burst Mode */
4811 htim->Instance->DCR = (BurstBaseAddress | BurstLength);
4812 /* Enable the TIM DMA Request */
4813 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
4814 }
4815
4816 /* Return function status */
4817 return status;
4818 }
4819
4820 /**
4821 * @brief Stops the TIM DMA Burst mode
4822 * @param htim TIM handle
4823 * @param BurstRequestSrc TIM DMA Request sources to disable
4824 * @retval HAL status
4825 */
HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)4826 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
4827 {
4828 HAL_StatusTypeDef status = HAL_OK;
4829
4830 /* Check the parameters */
4831 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4832
4833 /* Abort the DMA transfer (at least disable the DMA channel) */
4834 switch (BurstRequestSrc)
4835 {
4836 case TIM_DMA_UPDATE:
4837 {
4838 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
4839 break;
4840 }
4841 case TIM_DMA_CC1:
4842 {
4843 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
4844 break;
4845 }
4846 case TIM_DMA_CC2:
4847 {
4848 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
4849 break;
4850 }
4851 case TIM_DMA_CC3:
4852 {
4853 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
4854 break;
4855 }
4856 case TIM_DMA_CC4:
4857 {
4858 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
4859 break;
4860 }
4861 case TIM_DMA_COM:
4862 {
4863 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
4864 break;
4865 }
4866 case TIM_DMA_TRIGGER:
4867 {
4868 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
4869 break;
4870 }
4871 default:
4872 status = HAL_ERROR;
4873 break;
4874 }
4875
4876 if (status == HAL_OK)
4877 {
4878 /* Disable the TIM Update DMA request */
4879 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
4880
4881 /* Change the DMA burst operation state */
4882 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
4883 }
4884
4885 /* Return function status */
4886 return status;
4887 }
4888
4889 /**
4890 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
4891 * @param htim TIM handle
4892 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
4893 * This parameter can be one of the following values:
4894 * @arg TIM_DMABASE_CR1
4895 * @arg TIM_DMABASE_CR2
4896 * @arg TIM_DMABASE_SMCR
4897 * @arg TIM_DMABASE_DIER
4898 * @arg TIM_DMABASE_SR
4899 * @arg TIM_DMABASE_EGR
4900 * @arg TIM_DMABASE_CCMR1
4901 * @arg TIM_DMABASE_CCMR2
4902 * @arg TIM_DMABASE_CCER
4903 * @arg TIM_DMABASE_CNT
4904 * @arg TIM_DMABASE_PSC
4905 * @arg TIM_DMABASE_ARR
4906 * @arg TIM_DMABASE_RCR
4907 * @arg TIM_DMABASE_CCR1
4908 * @arg TIM_DMABASE_CCR2
4909 * @arg TIM_DMABASE_CCR3
4910 * @arg TIM_DMABASE_CCR4
4911 * @arg TIM_DMABASE_BDTR
4912 * @arg TIM_DMABASE_OR
4913 * @arg TIM_DMABASE_CCMR3 (*)
4914 * @arg TIM_DMABASE_CCR5 (*)
4915 * @arg TIM_DMABASE_CCR6 (*)
4916 * (*) value not defined in all devices
4917 * @param BurstRequestSrc TIM DMA Request sources
4918 * This parameter can be one of the following values:
4919 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4920 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4921 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4922 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4923 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4924 * @arg TIM_DMA_COM: TIM Commutation DMA source
4925 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4926 * @param BurstBuffer The Buffer address.
4927 * @param BurstLength DMA Burst length. This parameter can be one value
4928 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4929 * @note This function should be used only when BurstLength is equal to DMA data transfer length.
4930 * @retval HAL status
4931 */
HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength)4932 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4933 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
4934 {
4935 HAL_StatusTypeDef status;
4936
4937 status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
4938 ((BurstLength) >> 8U) + 1U);
4939
4940
4941 return status;
4942 }
4943
4944 /**
4945 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
4946 * @param htim TIM handle
4947 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
4948 * This parameter can be one of the following values:
4949 * @arg TIM_DMABASE_CR1
4950 * @arg TIM_DMABASE_CR2
4951 * @arg TIM_DMABASE_SMCR
4952 * @arg TIM_DMABASE_DIER
4953 * @arg TIM_DMABASE_SR
4954 * @arg TIM_DMABASE_EGR
4955 * @arg TIM_DMABASE_CCMR1
4956 * @arg TIM_DMABASE_CCMR2
4957 * @arg TIM_DMABASE_CCER
4958 * @arg TIM_DMABASE_CNT
4959 * @arg TIM_DMABASE_PSC
4960 * @arg TIM_DMABASE_ARR
4961 * @arg TIM_DMABASE_RCR
4962 * @arg TIM_DMABASE_CCR1
4963 * @arg TIM_DMABASE_CCR2
4964 * @arg TIM_DMABASE_CCR3
4965 * @arg TIM_DMABASE_CCR4
4966 * @arg TIM_DMABASE_BDTR
4967 * @arg TIM_DMABASE_OR
4968 * @arg TIM_DMABASE_CCMR3 (*)
4969 * @arg TIM_DMABASE_CCR5 (*)
4970 * @arg TIM_DMABASE_CCR6 (*)
4971 * (*) value not defined in all devices
4972 * @param BurstRequestSrc TIM DMA Request sources
4973 * This parameter can be one of the following values:
4974 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4975 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4976 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4977 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4978 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4979 * @arg TIM_DMA_COM: TIM Commutation DMA source
4980 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4981 * @param BurstBuffer The Buffer address.
4982 * @param BurstLength DMA Burst length. This parameter can be one value
4983 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4984 * @param DataLength Data length. This parameter can be one value
4985 * between 1 and 0xFFFF.
4986 * @retval HAL status
4987 */
HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength,uint32_t DataLength)4988 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4989 uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
4990 uint32_t BurstLength, uint32_t DataLength)
4991 {
4992 HAL_StatusTypeDef status = HAL_OK;
4993
4994 /* Check the parameters */
4995 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
4996 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
4997 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4998 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
4999 assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
5000
5001 if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
5002 {
5003 return HAL_BUSY;
5004 }
5005 else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
5006 {
5007 if ((BurstBuffer == NULL) && (BurstLength > 0U))
5008 {
5009 return HAL_ERROR;
5010 }
5011 else
5012 {
5013 htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
5014 }
5015 }
5016 else
5017 {
5018 /* nothing to do */
5019 }
5020 switch (BurstRequestSrc)
5021 {
5022 case TIM_DMA_UPDATE:
5023 {
5024 /* Set the DMA Period elapsed callbacks */
5025 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
5026 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
5027
5028 /* Set the DMA error callback */
5029 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
5030
5031 /* Enable the DMA channel */
5032 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5033 DataLength) != HAL_OK)
5034 {
5035 /* Return error status */
5036 return HAL_ERROR;
5037 }
5038 break;
5039 }
5040 case TIM_DMA_CC1:
5041 {
5042 /* Set the DMA capture callbacks */
5043 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
5044 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
5045
5046 /* Set the DMA error callback */
5047 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
5048
5049 /* Enable the DMA channel */
5050 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5051 DataLength) != HAL_OK)
5052 {
5053 /* Return error status */
5054 return HAL_ERROR;
5055 }
5056 break;
5057 }
5058 case TIM_DMA_CC2:
5059 {
5060 /* Set the DMA capture callbacks */
5061 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
5062 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
5063
5064 /* Set the DMA error callback */
5065 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
5066
5067 /* Enable the DMA channel */
5068 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5069 DataLength) != HAL_OK)
5070 {
5071 /* Return error status */
5072 return HAL_ERROR;
5073 }
5074 break;
5075 }
5076 case TIM_DMA_CC3:
5077 {
5078 /* Set the DMA capture callbacks */
5079 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
5080 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
5081
5082 /* Set the DMA error callback */
5083 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
5084
5085 /* Enable the DMA channel */
5086 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5087 DataLength) != HAL_OK)
5088 {
5089 /* Return error status */
5090 return HAL_ERROR;
5091 }
5092 break;
5093 }
5094 case TIM_DMA_CC4:
5095 {
5096 /* Set the DMA capture callbacks */
5097 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
5098 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
5099
5100 /* Set the DMA error callback */
5101 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
5102
5103 /* Enable the DMA channel */
5104 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5105 DataLength) != HAL_OK)
5106 {
5107 /* Return error status */
5108 return HAL_ERROR;
5109 }
5110 break;
5111 }
5112 case TIM_DMA_COM:
5113 {
5114 /* Set the DMA commutation callbacks */
5115 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
5116 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
5117
5118 /* Set the DMA error callback */
5119 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
5120
5121 /* Enable the DMA channel */
5122 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5123 DataLength) != HAL_OK)
5124 {
5125 /* Return error status */
5126 return HAL_ERROR;
5127 }
5128 break;
5129 }
5130 case TIM_DMA_TRIGGER:
5131 {
5132 /* Set the DMA trigger callbacks */
5133 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
5134 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
5135
5136 /* Set the DMA error callback */
5137 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
5138
5139 /* Enable the DMA channel */
5140 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5141 DataLength) != HAL_OK)
5142 {
5143 /* Return error status */
5144 return HAL_ERROR;
5145 }
5146 break;
5147 }
5148 default:
5149 status = HAL_ERROR;
5150 break;
5151 }
5152
5153 if (status == HAL_OK)
5154 {
5155 /* Configure the DMA Burst Mode */
5156 htim->Instance->DCR = (BurstBaseAddress | BurstLength);
5157
5158 /* Enable the TIM DMA Request */
5159 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
5160 }
5161
5162 /* Return function status */
5163 return status;
5164 }
5165
5166 /**
5167 * @brief Stop the DMA burst reading
5168 * @param htim TIM handle
5169 * @param BurstRequestSrc TIM DMA Request sources to disable.
5170 * @retval HAL status
5171 */
HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)5172 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
5173 {
5174 HAL_StatusTypeDef status = HAL_OK;
5175
5176 /* Check the parameters */
5177 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
5178
5179 /* Abort the DMA transfer (at least disable the DMA channel) */
5180 switch (BurstRequestSrc)
5181 {
5182 case TIM_DMA_UPDATE:
5183 {
5184 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
5185 break;
5186 }
5187 case TIM_DMA_CC1:
5188 {
5189 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
5190 break;
5191 }
5192 case TIM_DMA_CC2:
5193 {
5194 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
5195 break;
5196 }
5197 case TIM_DMA_CC3:
5198 {
5199 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
5200 break;
5201 }
5202 case TIM_DMA_CC4:
5203 {
5204 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
5205 break;
5206 }
5207 case TIM_DMA_COM:
5208 {
5209 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
5210 break;
5211 }
5212 case TIM_DMA_TRIGGER:
5213 {
5214 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
5215 break;
5216 }
5217 default:
5218 status = HAL_ERROR;
5219 break;
5220 }
5221
5222 if (status == HAL_OK)
5223 {
5224 /* Disable the TIM Update DMA request */
5225 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
5226
5227 /* Change the DMA burst operation state */
5228 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
5229 }
5230
5231 /* Return function status */
5232 return status;
5233 }
5234
5235 /**
5236 * @brief Generate a software event
5237 * @param htim TIM handle
5238 * @param EventSource specifies the event source.
5239 * This parameter can be one of the following values:
5240 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
5241 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
5242 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
5243 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
5244 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
5245 * @arg TIM_EVENTSOURCE_COM: Timer COM event source
5246 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
5247 * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
5248 * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
5249 * @note Basic timers can only generate an update event.
5250 * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
5251 * @note TIM_EVENTSOURCE_BREAK are relevant only for timer instances
5252 * supporting a break input.
5253 * @retval HAL status
5254 */
5255
HAL_TIM_GenerateEvent(TIM_HandleTypeDef * htim,uint32_t EventSource)5256 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
5257 {
5258 /* Check the parameters */
5259 assert_param(IS_TIM_INSTANCE(htim->Instance));
5260 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
5261
5262 /* Process Locked */
5263 __HAL_LOCK(htim);
5264
5265 /* Change the TIM state */
5266 htim->State = HAL_TIM_STATE_BUSY;
5267
5268 /* Set the event sources */
5269 htim->Instance->EGR = EventSource;
5270
5271 /* Change the TIM state */
5272 htim->State = HAL_TIM_STATE_READY;
5273
5274 __HAL_UNLOCK(htim);
5275
5276 /* Return function status */
5277 return HAL_OK;
5278 }
5279
5280 /**
5281 * @brief Configures the OCRef clear feature
5282 * @param htim TIM handle
5283 * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
5284 * contains the OCREF clear feature and parameters for the TIM peripheral.
5285 * @param Channel specifies the TIM Channel
5286 * This parameter can be one of the following values:
5287 * @arg TIM_CHANNEL_1: TIM Channel 1
5288 * @arg TIM_CHANNEL_2: TIM Channel 2
5289 * @arg TIM_CHANNEL_3: TIM Channel 3
5290 * @arg TIM_CHANNEL_4: TIM Channel 4
5291 * @arg TIM_CHANNEL_5: TIM Channel 5 (*)
5292 * @arg TIM_CHANNEL_6: TIM Channel 6 (*)
5293 * (*) Value not defined for all devices
5294 * @retval HAL status
5295 */
HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef * htim,const TIM_ClearInputConfigTypeDef * sClearInputConfig,uint32_t Channel)5296 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
5297 const TIM_ClearInputConfigTypeDef *sClearInputConfig,
5298 uint32_t Channel)
5299 {
5300 HAL_StatusTypeDef status = HAL_OK;
5301
5302 /* Check the parameters */
5303 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
5304 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
5305
5306 /* Process Locked */
5307 __HAL_LOCK(htim);
5308
5309 htim->State = HAL_TIM_STATE_BUSY;
5310
5311 switch (sClearInputConfig->ClearInputSource)
5312 {
5313 case TIM_CLEARINPUTSOURCE_NONE:
5314 {
5315 /* Clear the OCREF clear selection bit and the the ETR Bits */
5316 #if defined(TIM_SMCR_OCCS)
5317 CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
5318 #else
5319 CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
5320 #endif /* TIM_SMCR_OCCS */
5321 break;
5322 }
5323 #if defined(TIM_SMCR_OCCS)
5324 case TIM_CLEARINPUTSOURCE_OCREFCLR:
5325 {
5326 /* Clear the OCREF clear selection bit */
5327 CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
5328 break;
5329 }
5330 #endif /* TIM_SMCR_OCCS */
5331
5332 case TIM_CLEARINPUTSOURCE_ETR:
5333 {
5334 /* Check the parameters */
5335 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
5336 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
5337 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
5338
5339 /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
5340 if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
5341 {
5342 htim->State = HAL_TIM_STATE_READY;
5343 __HAL_UNLOCK(htim);
5344 return HAL_ERROR;
5345 }
5346
5347 TIM_ETR_SetConfig(htim->Instance,
5348 sClearInputConfig->ClearInputPrescaler,
5349 sClearInputConfig->ClearInputPolarity,
5350 sClearInputConfig->ClearInputFilter);
5351 #if defined(TIM_SMCR_OCCS)
5352
5353 /* Set the OCREF clear selection bit */
5354 SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
5355 #endif /* TIM_SMCR_OCCS */
5356 break;
5357 }
5358
5359 default:
5360 status = HAL_ERROR;
5361 break;
5362 }
5363
5364 if (status == HAL_OK)
5365 {
5366 switch (Channel)
5367 {
5368 case TIM_CHANNEL_1:
5369 {
5370 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5371 {
5372 /* Enable the OCREF clear feature for Channel 1 */
5373 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
5374 }
5375 else
5376 {
5377 /* Disable the OCREF clear feature for Channel 1 */
5378 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
5379 }
5380 break;
5381 }
5382 case TIM_CHANNEL_2:
5383 {
5384 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5385 {
5386 /* Enable the OCREF clear feature for Channel 2 */
5387 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
5388 }
5389 else
5390 {
5391 /* Disable the OCREF clear feature for Channel 2 */
5392 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
5393 }
5394 break;
5395 }
5396 case TIM_CHANNEL_3:
5397 {
5398 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5399 {
5400 /* Enable the OCREF clear feature for Channel 3 */
5401 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
5402 }
5403 else
5404 {
5405 /* Disable the OCREF clear feature for Channel 3 */
5406 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
5407 }
5408 break;
5409 }
5410 case TIM_CHANNEL_4:
5411 {
5412 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5413 {
5414 /* Enable the OCREF clear feature for Channel 4 */
5415 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
5416 }
5417 else
5418 {
5419 /* Disable the OCREF clear feature for Channel 4 */
5420 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
5421 }
5422 break;
5423 }
5424 #if defined(TIM_CCER_CC5E)
5425 case TIM_CHANNEL_5:
5426 {
5427 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5428 {
5429 /* Enable the OCREF clear feature for Channel 5 */
5430 SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
5431 }
5432 else
5433 {
5434 /* Disable the OCREF clear feature for Channel 5 */
5435 CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
5436 }
5437 break;
5438 }
5439 #endif /* TIM_CCER_CC5E */
5440 #if defined(TIM_CCER_CC6E)
5441 case TIM_CHANNEL_6:
5442 {
5443 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5444 {
5445 /* Enable the OCREF clear feature for Channel 6 */
5446 SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
5447 }
5448 else
5449 {
5450 /* Disable the OCREF clear feature for Channel 6 */
5451 CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
5452 }
5453 break;
5454 }
5455 #endif /* TIM_CCER_CC6E */
5456 default:
5457 break;
5458 }
5459 }
5460
5461 htim->State = HAL_TIM_STATE_READY;
5462
5463 __HAL_UNLOCK(htim);
5464
5465 return status;
5466 }
5467
5468 /**
5469 * @brief Configures the clock source to be used
5470 * @param htim TIM handle
5471 * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
5472 * contains the clock source information for the TIM peripheral.
5473 * @retval HAL status
5474 */
HAL_TIM_ConfigClockSource(TIM_HandleTypeDef * htim,const TIM_ClockConfigTypeDef * sClockSourceConfig)5475 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
5476 {
5477 HAL_StatusTypeDef status = HAL_OK;
5478 uint32_t tmpsmcr;
5479
5480 /* Process Locked */
5481 __HAL_LOCK(htim);
5482
5483 htim->State = HAL_TIM_STATE_BUSY;
5484
5485 /* Check the parameters */
5486 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
5487
5488 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
5489 tmpsmcr = htim->Instance->SMCR;
5490 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
5491 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
5492 htim->Instance->SMCR = tmpsmcr;
5493
5494 switch (sClockSourceConfig->ClockSource)
5495 {
5496 case TIM_CLOCKSOURCE_INTERNAL:
5497 {
5498 assert_param(IS_TIM_INSTANCE(htim->Instance));
5499 break;
5500 }
5501
5502 case TIM_CLOCKSOURCE_ETRMODE1:
5503 {
5504 /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
5505 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
5506
5507 /* Check ETR input conditioning related parameters */
5508 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
5509 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5510 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5511
5512 /* Configure the ETR Clock source */
5513 TIM_ETR_SetConfig(htim->Instance,
5514 sClockSourceConfig->ClockPrescaler,
5515 sClockSourceConfig->ClockPolarity,
5516 sClockSourceConfig->ClockFilter);
5517
5518 /* Select the External clock mode1 and the ETRF trigger */
5519 tmpsmcr = htim->Instance->SMCR;
5520 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
5521 /* Write to TIMx SMCR */
5522 htim->Instance->SMCR = tmpsmcr;
5523 break;
5524 }
5525
5526 case TIM_CLOCKSOURCE_ETRMODE2:
5527 {
5528 /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
5529 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
5530
5531 /* Check ETR input conditioning related parameters */
5532 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
5533 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5534 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5535
5536 /* Configure the ETR Clock source */
5537 TIM_ETR_SetConfig(htim->Instance,
5538 sClockSourceConfig->ClockPrescaler,
5539 sClockSourceConfig->ClockPolarity,
5540 sClockSourceConfig->ClockFilter);
5541 /* Enable the External clock mode2 */
5542 htim->Instance->SMCR |= TIM_SMCR_ECE;
5543 break;
5544 }
5545
5546 case TIM_CLOCKSOURCE_TI1:
5547 {
5548 /* Check whether or not the timer instance supports external clock mode 1 */
5549 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5550
5551 /* Check TI1 input conditioning related parameters */
5552 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5553 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5554
5555 TIM_TI1_ConfigInputStage(htim->Instance,
5556 sClockSourceConfig->ClockPolarity,
5557 sClockSourceConfig->ClockFilter);
5558 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
5559 break;
5560 }
5561
5562 case TIM_CLOCKSOURCE_TI2:
5563 {
5564 /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
5565 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5566
5567 /* Check TI2 input conditioning related parameters */
5568 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5569 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5570
5571 TIM_TI2_ConfigInputStage(htim->Instance,
5572 sClockSourceConfig->ClockPolarity,
5573 sClockSourceConfig->ClockFilter);
5574 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
5575 break;
5576 }
5577
5578 case TIM_CLOCKSOURCE_TI1ED:
5579 {
5580 /* Check whether or not the timer instance supports external clock mode 1 */
5581 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5582
5583 /* Check TI1 input conditioning related parameters */
5584 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5585 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5586
5587 TIM_TI1_ConfigInputStage(htim->Instance,
5588 sClockSourceConfig->ClockPolarity,
5589 sClockSourceConfig->ClockFilter);
5590 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
5591 break;
5592 }
5593
5594 case TIM_CLOCKSOURCE_ITR0:
5595 case TIM_CLOCKSOURCE_ITR1:
5596 case TIM_CLOCKSOURCE_ITR2:
5597 case TIM_CLOCKSOURCE_ITR3:
5598 {
5599 /* Check whether or not the timer instance supports internal trigger input */
5600 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
5601
5602 TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
5603 break;
5604 }
5605
5606 default:
5607 status = HAL_ERROR;
5608 break;
5609 }
5610 htim->State = HAL_TIM_STATE_READY;
5611
5612 __HAL_UNLOCK(htim);
5613
5614 return status;
5615 }
5616
5617 /**
5618 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
5619 * or a XOR combination between CH1_input, CH2_input & CH3_input
5620 * @param htim TIM handle.
5621 * @param TI1_Selection Indicate whether or not channel 1 is connected to the
5622 * output of a XOR gate.
5623 * This parameter can be one of the following values:
5624 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
5625 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
5626 * pins are connected to the TI1 input (XOR combination)
5627 * @retval HAL status
5628 */
HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef * htim,uint32_t TI1_Selection)5629 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
5630 {
5631 uint32_t tmpcr2;
5632
5633 /* Check the parameters */
5634 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
5635 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
5636
5637 /* Get the TIMx CR2 register value */
5638 tmpcr2 = htim->Instance->CR2;
5639
5640 /* Reset the TI1 selection */
5641 tmpcr2 &= ~TIM_CR2_TI1S;
5642
5643 /* Set the TI1 selection */
5644 tmpcr2 |= TI1_Selection;
5645
5646 /* Write to TIMxCR2 */
5647 htim->Instance->CR2 = tmpcr2;
5648
5649 return HAL_OK;
5650 }
5651
5652 /**
5653 * @brief Configures the TIM in Slave mode
5654 * @param htim TIM handle.
5655 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
5656 * contains the selected trigger (internal trigger input, filtered
5657 * timer input or external trigger input) and the Slave mode
5658 * (Disable, Reset, Gated, Trigger, External clock mode 1).
5659 * @retval HAL status
5660 */
HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef * htim,const TIM_SlaveConfigTypeDef * sSlaveConfig)5661 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig)
5662 {
5663 /* Check the parameters */
5664 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
5665 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
5666 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
5667
5668 __HAL_LOCK(htim);
5669
5670 htim->State = HAL_TIM_STATE_BUSY;
5671
5672 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
5673 {
5674 htim->State = HAL_TIM_STATE_READY;
5675 __HAL_UNLOCK(htim);
5676 return HAL_ERROR;
5677 }
5678
5679 /* Disable Trigger Interrupt */
5680 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
5681
5682 /* Disable Trigger DMA request */
5683 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
5684
5685 htim->State = HAL_TIM_STATE_READY;
5686
5687 __HAL_UNLOCK(htim);
5688
5689 return HAL_OK;
5690 }
5691
5692 /**
5693 * @brief Configures the TIM in Slave mode in interrupt mode
5694 * @param htim TIM handle.
5695 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
5696 * contains the selected trigger (internal trigger input, filtered
5697 * timer input or external trigger input) and the Slave mode
5698 * (Disable, Reset, Gated, Trigger, External clock mode 1).
5699 * @retval HAL status
5700 */
HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef * htim,const TIM_SlaveConfigTypeDef * sSlaveConfig)5701 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
5702 const TIM_SlaveConfigTypeDef *sSlaveConfig)
5703 {
5704 /* Check the parameters */
5705 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
5706 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
5707 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
5708
5709 __HAL_LOCK(htim);
5710
5711 htim->State = HAL_TIM_STATE_BUSY;
5712
5713 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
5714 {
5715 htim->State = HAL_TIM_STATE_READY;
5716 __HAL_UNLOCK(htim);
5717 return HAL_ERROR;
5718 }
5719
5720 /* Enable Trigger Interrupt */
5721 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
5722
5723 /* Disable Trigger DMA request */
5724 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
5725
5726 htim->State = HAL_TIM_STATE_READY;
5727
5728 __HAL_UNLOCK(htim);
5729
5730 return HAL_OK;
5731 }
5732
5733 /**
5734 * @brief Read the captured value from Capture Compare unit
5735 * @param htim TIM handle.
5736 * @param Channel TIM Channels to be enabled
5737 * This parameter can be one of the following values:
5738 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
5739 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
5740 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
5741 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
5742 * @retval Captured value
5743 */
HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef * htim,uint32_t Channel)5744 uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel)
5745 {
5746 uint32_t tmpreg = 0U;
5747
5748 switch (Channel)
5749 {
5750 case TIM_CHANNEL_1:
5751 {
5752 /* Check the parameters */
5753 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
5754
5755 /* Return the capture 1 value */
5756 tmpreg = htim->Instance->CCR1;
5757
5758 break;
5759 }
5760 case TIM_CHANNEL_2:
5761 {
5762 /* Check the parameters */
5763 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
5764
5765 /* Return the capture 2 value */
5766 tmpreg = htim->Instance->CCR2;
5767
5768 break;
5769 }
5770
5771 case TIM_CHANNEL_3:
5772 {
5773 /* Check the parameters */
5774 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
5775
5776 /* Return the capture 3 value */
5777 tmpreg = htim->Instance->CCR3;
5778
5779 break;
5780 }
5781
5782 case TIM_CHANNEL_4:
5783 {
5784 /* Check the parameters */
5785 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
5786
5787 /* Return the capture 4 value */
5788 tmpreg = htim->Instance->CCR4;
5789
5790 break;
5791 }
5792
5793 default:
5794 break;
5795 }
5796
5797 return tmpreg;
5798 }
5799
5800 /**
5801 * @}
5802 */
5803
5804 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
5805 * @brief TIM Callbacks functions
5806 *
5807 @verbatim
5808 ==============================================================================
5809 ##### TIM Callbacks functions #####
5810 ==============================================================================
5811 [..]
5812 This section provides TIM callback functions:
5813 (+) TIM Period elapsed callback
5814 (+) TIM Output Compare callback
5815 (+) TIM Input capture callback
5816 (+) TIM Trigger callback
5817 (+) TIM Error callback
5818
5819 @endverbatim
5820 * @{
5821 */
5822
5823 /**
5824 * @brief Period elapsed callback in non-blocking mode
5825 * @param htim TIM handle
5826 * @retval None
5827 */
HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef * htim)5828 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
5829 {
5830 /* Prevent unused argument(s) compilation warning */
5831 UNUSED(htim);
5832
5833 /* NOTE : This function should not be modified, when the callback is needed,
5834 the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
5835 */
5836 }
5837
5838 /**
5839 * @brief Period elapsed half complete callback in non-blocking mode
5840 * @param htim TIM handle
5841 * @retval None
5842 */
HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef * htim)5843 __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
5844 {
5845 /* Prevent unused argument(s) compilation warning */
5846 UNUSED(htim);
5847
5848 /* NOTE : This function should not be modified, when the callback is needed,
5849 the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
5850 */
5851 }
5852
5853 /**
5854 * @brief Output Compare callback in non-blocking mode
5855 * @param htim TIM OC handle
5856 * @retval None
5857 */
HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef * htim)5858 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
5859 {
5860 /* Prevent unused argument(s) compilation warning */
5861 UNUSED(htim);
5862
5863 /* NOTE : This function should not be modified, when the callback is needed,
5864 the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
5865 */
5866 }
5867
5868 /**
5869 * @brief Input Capture callback in non-blocking mode
5870 * @param htim TIM IC handle
5871 * @retval None
5872 */
HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef * htim)5873 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
5874 {
5875 /* Prevent unused argument(s) compilation warning */
5876 UNUSED(htim);
5877
5878 /* NOTE : This function should not be modified, when the callback is needed,
5879 the HAL_TIM_IC_CaptureCallback could be implemented in the user file
5880 */
5881 }
5882
5883 /**
5884 * @brief Input Capture half complete callback in non-blocking mode
5885 * @param htim TIM IC handle
5886 * @retval None
5887 */
HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef * htim)5888 __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
5889 {
5890 /* Prevent unused argument(s) compilation warning */
5891 UNUSED(htim);
5892
5893 /* NOTE : This function should not be modified, when the callback is needed,
5894 the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
5895 */
5896 }
5897
5898 /**
5899 * @brief PWM Pulse finished callback in non-blocking mode
5900 * @param htim TIM handle
5901 * @retval None
5902 */
HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef * htim)5903 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
5904 {
5905 /* Prevent unused argument(s) compilation warning */
5906 UNUSED(htim);
5907
5908 /* NOTE : This function should not be modified, when the callback is needed,
5909 the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
5910 */
5911 }
5912
5913 /**
5914 * @brief PWM Pulse finished half complete callback in non-blocking mode
5915 * @param htim TIM handle
5916 * @retval None
5917 */
HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef * htim)5918 __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
5919 {
5920 /* Prevent unused argument(s) compilation warning */
5921 UNUSED(htim);
5922
5923 /* NOTE : This function should not be modified, when the callback is needed,
5924 the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
5925 */
5926 }
5927
5928 /**
5929 * @brief Hall Trigger detection callback in non-blocking mode
5930 * @param htim TIM handle
5931 * @retval None
5932 */
HAL_TIM_TriggerCallback(TIM_HandleTypeDef * htim)5933 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
5934 {
5935 /* Prevent unused argument(s) compilation warning */
5936 UNUSED(htim);
5937
5938 /* NOTE : This function should not be modified, when the callback is needed,
5939 the HAL_TIM_TriggerCallback could be implemented in the user file
5940 */
5941 }
5942
5943 /**
5944 * @brief Hall Trigger detection half complete callback in non-blocking mode
5945 * @param htim TIM handle
5946 * @retval None
5947 */
HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef * htim)5948 __weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
5949 {
5950 /* Prevent unused argument(s) compilation warning */
5951 UNUSED(htim);
5952
5953 /* NOTE : This function should not be modified, when the callback is needed,
5954 the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
5955 */
5956 }
5957
5958 /**
5959 * @brief Timer error callback in non-blocking mode
5960 * @param htim TIM handle
5961 * @retval None
5962 */
HAL_TIM_ErrorCallback(TIM_HandleTypeDef * htim)5963 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
5964 {
5965 /* Prevent unused argument(s) compilation warning */
5966 UNUSED(htim);
5967
5968 /* NOTE : This function should not be modified, when the callback is needed,
5969 the HAL_TIM_ErrorCallback could be implemented in the user file
5970 */
5971 }
5972
5973 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5974 /**
5975 * @brief Register a User TIM callback to be used instead of the weak predefined callback
5976 * @param htim tim handle
5977 * @param CallbackID ID of the callback to be registered
5978 * This parameter can be one of the following values:
5979 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
5980 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
5981 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
5982 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
5983 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
5984 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
5985 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
5986 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
5987 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
5988 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
5989 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
5990 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
5991 * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
5992 * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
5993 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
5994 * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
5995 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
5996 * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
5997 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
5998 * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
5999 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
6000 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
6001 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
6002 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
6003 * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
6004 * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
6005 * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
6006 #if defined(TIM_BDTR_BK2E)
6007 * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
6008 #endif
6009 * @param pCallback pointer to the callback function
6010 * @retval status
6011 */
HAL_TIM_RegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID,pTIM_CallbackTypeDef pCallback)6012 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
6013 pTIM_CallbackTypeDef pCallback)
6014 {
6015 HAL_StatusTypeDef status = HAL_OK;
6016
6017 if (pCallback == NULL)
6018 {
6019 return HAL_ERROR;
6020 }
6021
6022 if (htim->State == HAL_TIM_STATE_READY)
6023 {
6024 switch (CallbackID)
6025 {
6026 case HAL_TIM_BASE_MSPINIT_CB_ID :
6027 htim->Base_MspInitCallback = pCallback;
6028 break;
6029
6030 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6031 htim->Base_MspDeInitCallback = pCallback;
6032 break;
6033
6034 case HAL_TIM_IC_MSPINIT_CB_ID :
6035 htim->IC_MspInitCallback = pCallback;
6036 break;
6037
6038 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6039 htim->IC_MspDeInitCallback = pCallback;
6040 break;
6041
6042 case HAL_TIM_OC_MSPINIT_CB_ID :
6043 htim->OC_MspInitCallback = pCallback;
6044 break;
6045
6046 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6047 htim->OC_MspDeInitCallback = pCallback;
6048 break;
6049
6050 case HAL_TIM_PWM_MSPINIT_CB_ID :
6051 htim->PWM_MspInitCallback = pCallback;
6052 break;
6053
6054 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6055 htim->PWM_MspDeInitCallback = pCallback;
6056 break;
6057
6058 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6059 htim->OnePulse_MspInitCallback = pCallback;
6060 break;
6061
6062 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6063 htim->OnePulse_MspDeInitCallback = pCallback;
6064 break;
6065
6066 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6067 htim->Encoder_MspInitCallback = pCallback;
6068 break;
6069
6070 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6071 htim->Encoder_MspDeInitCallback = pCallback;
6072 break;
6073
6074 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6075 htim->HallSensor_MspInitCallback = pCallback;
6076 break;
6077
6078 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6079 htim->HallSensor_MspDeInitCallback = pCallback;
6080 break;
6081
6082 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
6083 htim->PeriodElapsedCallback = pCallback;
6084 break;
6085
6086 case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
6087 htim->PeriodElapsedHalfCpltCallback = pCallback;
6088 break;
6089
6090 case HAL_TIM_TRIGGER_CB_ID :
6091 htim->TriggerCallback = pCallback;
6092 break;
6093
6094 case HAL_TIM_TRIGGER_HALF_CB_ID :
6095 htim->TriggerHalfCpltCallback = pCallback;
6096 break;
6097
6098 case HAL_TIM_IC_CAPTURE_CB_ID :
6099 htim->IC_CaptureCallback = pCallback;
6100 break;
6101
6102 case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
6103 htim->IC_CaptureHalfCpltCallback = pCallback;
6104 break;
6105
6106 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
6107 htim->OC_DelayElapsedCallback = pCallback;
6108 break;
6109
6110 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
6111 htim->PWM_PulseFinishedCallback = pCallback;
6112 break;
6113
6114 case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
6115 htim->PWM_PulseFinishedHalfCpltCallback = pCallback;
6116 break;
6117
6118 case HAL_TIM_ERROR_CB_ID :
6119 htim->ErrorCallback = pCallback;
6120 break;
6121
6122 case HAL_TIM_COMMUTATION_CB_ID :
6123 htim->CommutationCallback = pCallback;
6124 break;
6125
6126 case HAL_TIM_COMMUTATION_HALF_CB_ID :
6127 htim->CommutationHalfCpltCallback = pCallback;
6128 break;
6129
6130 case HAL_TIM_BREAK_CB_ID :
6131 htim->BreakCallback = pCallback;
6132 break;
6133 #if defined(TIM_BDTR_BK2E)
6134
6135 case HAL_TIM_BREAK2_CB_ID :
6136 htim->Break2Callback = pCallback;
6137 break;
6138 #endif /* TIM_BDTR_BK2E */
6139
6140 default :
6141 /* Return error status */
6142 status = HAL_ERROR;
6143 break;
6144 }
6145 }
6146 else if (htim->State == HAL_TIM_STATE_RESET)
6147 {
6148 switch (CallbackID)
6149 {
6150 case HAL_TIM_BASE_MSPINIT_CB_ID :
6151 htim->Base_MspInitCallback = pCallback;
6152 break;
6153
6154 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6155 htim->Base_MspDeInitCallback = pCallback;
6156 break;
6157
6158 case HAL_TIM_IC_MSPINIT_CB_ID :
6159 htim->IC_MspInitCallback = pCallback;
6160 break;
6161
6162 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6163 htim->IC_MspDeInitCallback = pCallback;
6164 break;
6165
6166 case HAL_TIM_OC_MSPINIT_CB_ID :
6167 htim->OC_MspInitCallback = pCallback;
6168 break;
6169
6170 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6171 htim->OC_MspDeInitCallback = pCallback;
6172 break;
6173
6174 case HAL_TIM_PWM_MSPINIT_CB_ID :
6175 htim->PWM_MspInitCallback = pCallback;
6176 break;
6177
6178 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6179 htim->PWM_MspDeInitCallback = pCallback;
6180 break;
6181
6182 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6183 htim->OnePulse_MspInitCallback = pCallback;
6184 break;
6185
6186 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6187 htim->OnePulse_MspDeInitCallback = pCallback;
6188 break;
6189
6190 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6191 htim->Encoder_MspInitCallback = pCallback;
6192 break;
6193
6194 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6195 htim->Encoder_MspDeInitCallback = pCallback;
6196 break;
6197
6198 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6199 htim->HallSensor_MspInitCallback = pCallback;
6200 break;
6201
6202 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6203 htim->HallSensor_MspDeInitCallback = pCallback;
6204 break;
6205
6206 default :
6207 /* Return error status */
6208 status = HAL_ERROR;
6209 break;
6210 }
6211 }
6212 else
6213 {
6214 /* Return error status */
6215 status = HAL_ERROR;
6216 }
6217
6218 return status;
6219 }
6220
6221 /**
6222 * @brief Unregister a TIM callback
6223 * TIM callback is redirected to the weak predefined callback
6224 * @param htim tim handle
6225 * @param CallbackID ID of the callback to be unregistered
6226 * This parameter can be one of the following values:
6227 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
6228 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
6229 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
6230 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
6231 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
6232 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
6233 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
6234 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
6235 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
6236 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
6237 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
6238 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
6239 * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
6240 * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
6241 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
6242 * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
6243 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
6244 * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
6245 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
6246 * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
6247 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
6248 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
6249 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
6250 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
6251 * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
6252 * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
6253 * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
6254 #if defined(TIM_BDTR_BK2E)
6255 * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
6256 #endif
6257 * @retval status
6258 */
HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID)6259 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
6260 {
6261 HAL_StatusTypeDef status = HAL_OK;
6262
6263 if (htim->State == HAL_TIM_STATE_READY)
6264 {
6265 switch (CallbackID)
6266 {
6267 case HAL_TIM_BASE_MSPINIT_CB_ID :
6268 /* Legacy weak Base MspInit Callback */
6269 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
6270 break;
6271
6272 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6273 /* Legacy weak Base Msp DeInit Callback */
6274 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
6275 break;
6276
6277 case HAL_TIM_IC_MSPINIT_CB_ID :
6278 /* Legacy weak IC Msp Init Callback */
6279 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
6280 break;
6281
6282 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6283 /* Legacy weak IC Msp DeInit Callback */
6284 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
6285 break;
6286
6287 case HAL_TIM_OC_MSPINIT_CB_ID :
6288 /* Legacy weak OC Msp Init Callback */
6289 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
6290 break;
6291
6292 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6293 /* Legacy weak OC Msp DeInit Callback */
6294 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
6295 break;
6296
6297 case HAL_TIM_PWM_MSPINIT_CB_ID :
6298 /* Legacy weak PWM Msp Init Callback */
6299 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
6300 break;
6301
6302 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6303 /* Legacy weak PWM Msp DeInit Callback */
6304 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
6305 break;
6306
6307 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6308 /* Legacy weak One Pulse Msp Init Callback */
6309 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
6310 break;
6311
6312 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6313 /* Legacy weak One Pulse Msp DeInit Callback */
6314 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
6315 break;
6316
6317 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6318 /* Legacy weak Encoder Msp Init Callback */
6319 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
6320 break;
6321
6322 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6323 /* Legacy weak Encoder Msp DeInit Callback */
6324 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
6325 break;
6326
6327 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6328 /* Legacy weak Hall Sensor Msp Init Callback */
6329 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
6330 break;
6331
6332 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6333 /* Legacy weak Hall Sensor Msp DeInit Callback */
6334 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
6335 break;
6336
6337 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
6338 /* Legacy weak Period Elapsed Callback */
6339 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
6340 break;
6341
6342 case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
6343 /* Legacy weak Period Elapsed half complete Callback */
6344 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
6345 break;
6346
6347 case HAL_TIM_TRIGGER_CB_ID :
6348 /* Legacy weak Trigger Callback */
6349 htim->TriggerCallback = HAL_TIM_TriggerCallback;
6350 break;
6351
6352 case HAL_TIM_TRIGGER_HALF_CB_ID :
6353 /* Legacy weak Trigger half complete Callback */
6354 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
6355 break;
6356
6357 case HAL_TIM_IC_CAPTURE_CB_ID :
6358 /* Legacy weak IC Capture Callback */
6359 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
6360 break;
6361
6362 case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
6363 /* Legacy weak IC Capture half complete Callback */
6364 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
6365 break;
6366
6367 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
6368 /* Legacy weak OC Delay Elapsed Callback */
6369 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
6370 break;
6371
6372 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
6373 /* Legacy weak PWM Pulse Finished Callback */
6374 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
6375 break;
6376
6377 case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
6378 /* Legacy weak PWM Pulse Finished half complete Callback */
6379 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
6380 break;
6381
6382 case HAL_TIM_ERROR_CB_ID :
6383 /* Legacy weak Error Callback */
6384 htim->ErrorCallback = HAL_TIM_ErrorCallback;
6385 break;
6386
6387 case HAL_TIM_COMMUTATION_CB_ID :
6388 /* Legacy weak Commutation Callback */
6389 htim->CommutationCallback = HAL_TIMEx_CommutCallback;
6390 break;
6391
6392 case HAL_TIM_COMMUTATION_HALF_CB_ID :
6393 /* Legacy weak Commutation half complete Callback */
6394 htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback;
6395 break;
6396
6397 case HAL_TIM_BREAK_CB_ID :
6398 /* Legacy weak Break Callback */
6399 htim->BreakCallback = HAL_TIMEx_BreakCallback;
6400 break;
6401 #if defined(TIM_BDTR_BK2E)
6402
6403 case HAL_TIM_BREAK2_CB_ID :
6404 /* Legacy weak Break2 Callback */
6405 htim->Break2Callback = HAL_TIMEx_Break2Callback;
6406 break;
6407 #endif /* TIM_BDTR_BK2E */
6408
6409 default :
6410 /* Return error status */
6411 status = HAL_ERROR;
6412 break;
6413 }
6414 }
6415 else if (htim->State == HAL_TIM_STATE_RESET)
6416 {
6417 switch (CallbackID)
6418 {
6419 case HAL_TIM_BASE_MSPINIT_CB_ID :
6420 /* Legacy weak Base MspInit Callback */
6421 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
6422 break;
6423
6424 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6425 /* Legacy weak Base Msp DeInit Callback */
6426 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
6427 break;
6428
6429 case HAL_TIM_IC_MSPINIT_CB_ID :
6430 /* Legacy weak IC Msp Init Callback */
6431 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
6432 break;
6433
6434 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6435 /* Legacy weak IC Msp DeInit Callback */
6436 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
6437 break;
6438
6439 case HAL_TIM_OC_MSPINIT_CB_ID :
6440 /* Legacy weak OC Msp Init Callback */
6441 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
6442 break;
6443
6444 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6445 /* Legacy weak OC Msp DeInit Callback */
6446 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
6447 break;
6448
6449 case HAL_TIM_PWM_MSPINIT_CB_ID :
6450 /* Legacy weak PWM Msp Init Callback */
6451 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
6452 break;
6453
6454 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6455 /* Legacy weak PWM Msp DeInit Callback */
6456 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
6457 break;
6458
6459 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6460 /* Legacy weak One Pulse Msp Init Callback */
6461 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
6462 break;
6463
6464 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6465 /* Legacy weak One Pulse Msp DeInit Callback */
6466 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
6467 break;
6468
6469 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6470 /* Legacy weak Encoder Msp Init Callback */
6471 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
6472 break;
6473
6474 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6475 /* Legacy weak Encoder Msp DeInit Callback */
6476 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
6477 break;
6478
6479 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6480 /* Legacy weak Hall Sensor Msp Init Callback */
6481 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
6482 break;
6483
6484 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6485 /* Legacy weak Hall Sensor Msp DeInit Callback */
6486 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
6487 break;
6488
6489 default :
6490 /* Return error status */
6491 status = HAL_ERROR;
6492 break;
6493 }
6494 }
6495 else
6496 {
6497 /* Return error status */
6498 status = HAL_ERROR;
6499 }
6500
6501 return status;
6502 }
6503 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6504
6505 /**
6506 * @}
6507 */
6508
6509 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
6510 * @brief TIM Peripheral State functions
6511 *
6512 @verbatim
6513 ==============================================================================
6514 ##### Peripheral State functions #####
6515 ==============================================================================
6516 [..]
6517 This subsection permits to get in run-time the status of the peripheral
6518 and the data flow.
6519
6520 @endverbatim
6521 * @{
6522 */
6523
6524 /**
6525 * @brief Return the TIM Base handle state.
6526 * @param htim TIM Base handle
6527 * @retval HAL state
6528 */
HAL_TIM_Base_GetState(const TIM_HandleTypeDef * htim)6529 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim)
6530 {
6531 return htim->State;
6532 }
6533
6534 /**
6535 * @brief Return the TIM OC handle state.
6536 * @param htim TIM Output Compare handle
6537 * @retval HAL state
6538 */
HAL_TIM_OC_GetState(const TIM_HandleTypeDef * htim)6539 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim)
6540 {
6541 return htim->State;
6542 }
6543
6544 /**
6545 * @brief Return the TIM PWM handle state.
6546 * @param htim TIM handle
6547 * @retval HAL state
6548 */
HAL_TIM_PWM_GetState(const TIM_HandleTypeDef * htim)6549 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim)
6550 {
6551 return htim->State;
6552 }
6553
6554 /**
6555 * @brief Return the TIM Input Capture handle state.
6556 * @param htim TIM IC handle
6557 * @retval HAL state
6558 */
HAL_TIM_IC_GetState(const TIM_HandleTypeDef * htim)6559 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim)
6560 {
6561 return htim->State;
6562 }
6563
6564 /**
6565 * @brief Return the TIM One Pulse Mode handle state.
6566 * @param htim TIM OPM handle
6567 * @retval HAL state
6568 */
HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef * htim)6569 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim)
6570 {
6571 return htim->State;
6572 }
6573
6574 /**
6575 * @brief Return the TIM Encoder Mode handle state.
6576 * @param htim TIM Encoder Interface handle
6577 * @retval HAL state
6578 */
HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef * htim)6579 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim)
6580 {
6581 return htim->State;
6582 }
6583
6584 /**
6585 * @brief Return the TIM Encoder Mode handle state.
6586 * @param htim TIM handle
6587 * @retval Active channel
6588 */
HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef * htim)6589 HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim)
6590 {
6591 return htim->Channel;
6592 }
6593
6594 /**
6595 * @brief Return actual state of the TIM channel.
6596 * @param htim TIM handle
6597 * @param Channel TIM Channel
6598 * This parameter can be one of the following values:
6599 * @arg TIM_CHANNEL_1: TIM Channel 1
6600 * @arg TIM_CHANNEL_2: TIM Channel 2
6601 * @arg TIM_CHANNEL_3: TIM Channel 3
6602 * @arg TIM_CHANNEL_4: TIM Channel 4
6603 * @arg TIM_CHANNEL_5: TIM Channel 5
6604 * @arg TIM_CHANNEL_6: TIM Channel 6
6605 * @retval TIM Channel state
6606 */
HAL_TIM_GetChannelState(const TIM_HandleTypeDef * htim,uint32_t Channel)6607 HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel)
6608 {
6609 HAL_TIM_ChannelStateTypeDef channel_state;
6610
6611 /* Check the parameters */
6612 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
6613
6614 channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
6615
6616 return channel_state;
6617 }
6618
6619 /**
6620 * @brief Return actual state of a DMA burst operation.
6621 * @param htim TIM handle
6622 * @retval DMA burst state
6623 */
HAL_TIM_DMABurstState(const TIM_HandleTypeDef * htim)6624 HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim)
6625 {
6626 /* Check the parameters */
6627 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
6628
6629 return htim->DMABurstState;
6630 }
6631
6632 /**
6633 * @}
6634 */
6635
6636 /**
6637 * @}
6638 */
6639
6640 /** @defgroup TIM_Private_Functions TIM Private Functions
6641 * @{
6642 */
6643
6644 /**
6645 * @brief TIM DMA error callback
6646 * @param hdma pointer to DMA handle.
6647 * @retval None
6648 */
TIM_DMAError(DMA_HandleTypeDef * hdma)6649 void TIM_DMAError(DMA_HandleTypeDef *hdma)
6650 {
6651 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6652
6653 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6654 {
6655 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6656 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6657 }
6658 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6659 {
6660 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6661 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6662 }
6663 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6664 {
6665 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6666 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6667 }
6668 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6669 {
6670 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6671 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6672 }
6673 else
6674 {
6675 htim->State = HAL_TIM_STATE_READY;
6676 }
6677
6678 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6679 htim->ErrorCallback(htim);
6680 #else
6681 HAL_TIM_ErrorCallback(htim);
6682 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6683
6684 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6685 }
6686
6687 /**
6688 * @brief TIM DMA Delay Pulse complete callback.
6689 * @param hdma pointer to DMA handle.
6690 * @retval None
6691 */
TIM_DMADelayPulseCplt(DMA_HandleTypeDef * hdma)6692 static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
6693 {
6694 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6695
6696 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6697 {
6698 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6699
6700 if (hdma->Init.Mode == DMA_NORMAL)
6701 {
6702 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6703 }
6704 }
6705 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6706 {
6707 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6708
6709 if (hdma->Init.Mode == DMA_NORMAL)
6710 {
6711 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6712 }
6713 }
6714 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6715 {
6716 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6717
6718 if (hdma->Init.Mode == DMA_NORMAL)
6719 {
6720 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6721 }
6722 }
6723 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6724 {
6725 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6726
6727 if (hdma->Init.Mode == DMA_NORMAL)
6728 {
6729 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6730 }
6731 }
6732 else
6733 {
6734 /* nothing to do */
6735 }
6736
6737 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6738 htim->PWM_PulseFinishedCallback(htim);
6739 #else
6740 HAL_TIM_PWM_PulseFinishedCallback(htim);
6741 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6742
6743 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6744 }
6745
6746 /**
6747 * @brief TIM DMA Delay Pulse half complete callback.
6748 * @param hdma pointer to DMA handle.
6749 * @retval None
6750 */
TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef * hdma)6751 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
6752 {
6753 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6754
6755 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6756 {
6757 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6758 }
6759 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6760 {
6761 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6762 }
6763 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6764 {
6765 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6766 }
6767 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6768 {
6769 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6770 }
6771 else
6772 {
6773 /* nothing to do */
6774 }
6775
6776 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6777 htim->PWM_PulseFinishedHalfCpltCallback(htim);
6778 #else
6779 HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
6780 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6781
6782 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6783 }
6784
6785 /**
6786 * @brief TIM DMA Capture complete callback.
6787 * @param hdma pointer to DMA handle.
6788 * @retval None
6789 */
TIM_DMACaptureCplt(DMA_HandleTypeDef * hdma)6790 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
6791 {
6792 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6793
6794 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6795 {
6796 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6797
6798 if (hdma->Init.Mode == DMA_NORMAL)
6799 {
6800 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6801 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6802 }
6803 }
6804 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6805 {
6806 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6807
6808 if (hdma->Init.Mode == DMA_NORMAL)
6809 {
6810 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6811 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6812 }
6813 }
6814 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6815 {
6816 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6817
6818 if (hdma->Init.Mode == DMA_NORMAL)
6819 {
6820 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6821 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6822 }
6823 }
6824 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6825 {
6826 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6827
6828 if (hdma->Init.Mode == DMA_NORMAL)
6829 {
6830 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6831 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6832 }
6833 }
6834 else
6835 {
6836 /* nothing to do */
6837 }
6838
6839 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6840 htim->IC_CaptureCallback(htim);
6841 #else
6842 HAL_TIM_IC_CaptureCallback(htim);
6843 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6844
6845 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6846 }
6847
6848 /**
6849 * @brief TIM DMA Capture half complete callback.
6850 * @param hdma pointer to DMA handle.
6851 * @retval None
6852 */
TIM_DMACaptureHalfCplt(DMA_HandleTypeDef * hdma)6853 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
6854 {
6855 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6856
6857 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6858 {
6859 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6860 }
6861 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6862 {
6863 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6864 }
6865 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6866 {
6867 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6868 }
6869 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6870 {
6871 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6872 }
6873 else
6874 {
6875 /* nothing to do */
6876 }
6877
6878 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6879 htim->IC_CaptureHalfCpltCallback(htim);
6880 #else
6881 HAL_TIM_IC_CaptureHalfCpltCallback(htim);
6882 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6883
6884 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6885 }
6886
6887 /**
6888 * @brief TIM DMA Period Elapse complete callback.
6889 * @param hdma pointer to DMA handle.
6890 * @retval None
6891 */
TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef * hdma)6892 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
6893 {
6894 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6895
6896 if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL)
6897 {
6898 htim->State = HAL_TIM_STATE_READY;
6899 }
6900
6901 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6902 htim->PeriodElapsedCallback(htim);
6903 #else
6904 HAL_TIM_PeriodElapsedCallback(htim);
6905 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6906 }
6907
6908 /**
6909 * @brief TIM DMA Period Elapse half complete callback.
6910 * @param hdma pointer to DMA handle.
6911 * @retval None
6912 */
TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef * hdma)6913 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
6914 {
6915 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6916
6917 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6918 htim->PeriodElapsedHalfCpltCallback(htim);
6919 #else
6920 HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
6921 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6922 }
6923
6924 /**
6925 * @brief TIM DMA Trigger callback.
6926 * @param hdma pointer to DMA handle.
6927 * @retval None
6928 */
TIM_DMATriggerCplt(DMA_HandleTypeDef * hdma)6929 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
6930 {
6931 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6932
6933 if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL)
6934 {
6935 htim->State = HAL_TIM_STATE_READY;
6936 }
6937
6938 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6939 htim->TriggerCallback(htim);
6940 #else
6941 HAL_TIM_TriggerCallback(htim);
6942 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6943 }
6944
6945 /**
6946 * @brief TIM DMA Trigger half complete callback.
6947 * @param hdma pointer to DMA handle.
6948 * @retval None
6949 */
TIM_DMATriggerHalfCplt(DMA_HandleTypeDef * hdma)6950 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
6951 {
6952 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6953
6954 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6955 htim->TriggerHalfCpltCallback(htim);
6956 #else
6957 HAL_TIM_TriggerHalfCpltCallback(htim);
6958 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6959 }
6960
6961 /**
6962 * @brief Time Base configuration
6963 * @param TIMx TIM peripheral
6964 * @param Structure TIM Base configuration structure
6965 * @retval None
6966 */
TIM_Base_SetConfig(TIM_TypeDef * TIMx,const TIM_Base_InitTypeDef * Structure)6967 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
6968 {
6969 uint32_t tmpcr1;
6970 tmpcr1 = TIMx->CR1;
6971
6972 /* Set TIM Time Base Unit parameters ---------------------------------------*/
6973 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
6974 {
6975 /* Select the Counter Mode */
6976 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
6977 tmpcr1 |= Structure->CounterMode;
6978 }
6979
6980 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
6981 {
6982 /* Set the clock division */
6983 tmpcr1 &= ~TIM_CR1_CKD;
6984 tmpcr1 |= (uint32_t)Structure->ClockDivision;
6985 }
6986
6987 /* Set the auto-reload preload */
6988 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
6989
6990 TIMx->CR1 = tmpcr1;
6991
6992 /* Set the Autoreload value */
6993 TIMx->ARR = (uint32_t)Structure->Period ;
6994
6995 /* Set the Prescaler value */
6996 TIMx->PSC = Structure->Prescaler;
6997
6998 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
6999 {
7000 /* Set the Repetition Counter value */
7001 TIMx->RCR = Structure->RepetitionCounter;
7002 }
7003
7004 /* Generate an update event to reload the Prescaler
7005 and the repetition counter (only for advanced timer) value immediately */
7006 TIMx->EGR = TIM_EGR_UG;
7007 }
7008
7009 /**
7010 * @brief Timer Output Compare 1 configuration
7011 * @param TIMx to select the TIM peripheral
7012 * @param OC_Config The output configuration structure
7013 * @retval None
7014 */
TIM_OC1_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7015 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
7016 {
7017 uint32_t tmpccmrx;
7018 uint32_t tmpccer;
7019 uint32_t tmpcr2;
7020
7021 /* Disable the Channel 1: Reset the CC1E Bit */
7022 TIMx->CCER &= ~TIM_CCER_CC1E;
7023
7024 /* Get the TIMx CCER register value */
7025 tmpccer = TIMx->CCER;
7026 /* Get the TIMx CR2 register value */
7027 tmpcr2 = TIMx->CR2;
7028
7029 /* Get the TIMx CCMR1 register value */
7030 tmpccmrx = TIMx->CCMR1;
7031
7032 /* Reset the Output Compare Mode Bits */
7033 tmpccmrx &= ~TIM_CCMR1_OC1M;
7034 tmpccmrx &= ~TIM_CCMR1_CC1S;
7035 /* Select the Output Compare Mode */
7036 tmpccmrx |= OC_Config->OCMode;
7037
7038 /* Reset the Output Polarity level */
7039 tmpccer &= ~TIM_CCER_CC1P;
7040 /* Set the Output Compare Polarity */
7041 tmpccer |= OC_Config->OCPolarity;
7042
7043 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
7044 {
7045 /* Check parameters */
7046 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
7047
7048 /* Reset the Output N Polarity level */
7049 tmpccer &= ~TIM_CCER_CC1NP;
7050 /* Set the Output N Polarity */
7051 tmpccer |= OC_Config->OCNPolarity;
7052 /* Reset the Output N State */
7053 tmpccer &= ~TIM_CCER_CC1NE;
7054 }
7055
7056 if (IS_TIM_BREAK_INSTANCE(TIMx))
7057 {
7058 /* Check parameters */
7059 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
7060 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7061
7062 /* Reset the Output Compare and Output Compare N IDLE State */
7063 tmpcr2 &= ~TIM_CR2_OIS1;
7064 tmpcr2 &= ~TIM_CR2_OIS1N;
7065 /* Set the Output Idle state */
7066 tmpcr2 |= OC_Config->OCIdleState;
7067 /* Set the Output N Idle state */
7068 tmpcr2 |= OC_Config->OCNIdleState;
7069 }
7070
7071 /* Write to TIMx CR2 */
7072 TIMx->CR2 = tmpcr2;
7073
7074 /* Write to TIMx CCMR1 */
7075 TIMx->CCMR1 = tmpccmrx;
7076
7077 /* Set the Capture Compare Register value */
7078 TIMx->CCR1 = OC_Config->Pulse;
7079
7080 /* Write to TIMx CCER */
7081 TIMx->CCER = tmpccer;
7082 }
7083
7084 /**
7085 * @brief Timer Output Compare 2 configuration
7086 * @param TIMx to select the TIM peripheral
7087 * @param OC_Config The output configuration structure
7088 * @retval None
7089 */
TIM_OC2_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7090 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
7091 {
7092 uint32_t tmpccmrx;
7093 uint32_t tmpccer;
7094 uint32_t tmpcr2;
7095
7096 /* Disable the Channel 2: Reset the CC2E Bit */
7097 TIMx->CCER &= ~TIM_CCER_CC2E;
7098
7099 /* Get the TIMx CCER register value */
7100 tmpccer = TIMx->CCER;
7101 /* Get the TIMx CR2 register value */
7102 tmpcr2 = TIMx->CR2;
7103
7104 /* Get the TIMx CCMR1 register value */
7105 tmpccmrx = TIMx->CCMR1;
7106
7107 /* Reset the Output Compare mode and Capture/Compare selection Bits */
7108 tmpccmrx &= ~TIM_CCMR1_OC2M;
7109 tmpccmrx &= ~TIM_CCMR1_CC2S;
7110
7111 /* Select the Output Compare Mode */
7112 tmpccmrx |= (OC_Config->OCMode << 8U);
7113
7114 /* Reset the Output Polarity level */
7115 tmpccer &= ~TIM_CCER_CC2P;
7116 /* Set the Output Compare Polarity */
7117 tmpccer |= (OC_Config->OCPolarity << 4U);
7118
7119 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
7120 {
7121 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
7122
7123 /* Reset the Output N Polarity level */
7124 tmpccer &= ~TIM_CCER_CC2NP;
7125 /* Set the Output N Polarity */
7126 tmpccer |= (OC_Config->OCNPolarity << 4U);
7127 /* Reset the Output N State */
7128 tmpccer &= ~TIM_CCER_CC2NE;
7129
7130 }
7131
7132 if (IS_TIM_BREAK_INSTANCE(TIMx))
7133 {
7134 /* Check parameters */
7135 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
7136 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7137
7138 /* Reset the Output Compare and Output Compare N IDLE State */
7139 tmpcr2 &= ~TIM_CR2_OIS2;
7140 #if defined(TIM_CR2_OIS2N)
7141 tmpcr2 &= ~TIM_CR2_OIS2N;
7142 #endif /* TIM_CR2_OIS2N */
7143 /* Set the Output Idle state */
7144 tmpcr2 |= (OC_Config->OCIdleState << 2U);
7145 /* Set the Output N Idle state */
7146 tmpcr2 |= (OC_Config->OCNIdleState << 2U);
7147 }
7148
7149 /* Write to TIMx CR2 */
7150 TIMx->CR2 = tmpcr2;
7151
7152 /* Write to TIMx CCMR1 */
7153 TIMx->CCMR1 = tmpccmrx;
7154
7155 /* Set the Capture Compare Register value */
7156 TIMx->CCR2 = OC_Config->Pulse;
7157
7158 /* Write to TIMx CCER */
7159 TIMx->CCER = tmpccer;
7160 }
7161
7162 /**
7163 * @brief Timer Output Compare 3 configuration
7164 * @param TIMx to select the TIM peripheral
7165 * @param OC_Config The output configuration structure
7166 * @retval None
7167 */
TIM_OC3_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7168 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
7169 {
7170 uint32_t tmpccmrx;
7171 uint32_t tmpccer;
7172 uint32_t tmpcr2;
7173
7174 /* Disable the Channel 3: Reset the CC2E Bit */
7175 TIMx->CCER &= ~TIM_CCER_CC3E;
7176
7177 /* Get the TIMx CCER register value */
7178 tmpccer = TIMx->CCER;
7179 /* Get the TIMx CR2 register value */
7180 tmpcr2 = TIMx->CR2;
7181
7182 /* Get the TIMx CCMR2 register value */
7183 tmpccmrx = TIMx->CCMR2;
7184
7185 /* Reset the Output Compare mode and Capture/Compare selection Bits */
7186 tmpccmrx &= ~TIM_CCMR2_OC3M;
7187 tmpccmrx &= ~TIM_CCMR2_CC3S;
7188 /* Select the Output Compare Mode */
7189 tmpccmrx |= OC_Config->OCMode;
7190
7191 /* Reset the Output Polarity level */
7192 tmpccer &= ~TIM_CCER_CC3P;
7193 /* Set the Output Compare Polarity */
7194 tmpccer |= (OC_Config->OCPolarity << 8U);
7195
7196 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
7197 {
7198 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
7199
7200 /* Reset the Output N Polarity level */
7201 tmpccer &= ~TIM_CCER_CC3NP;
7202 /* Set the Output N Polarity */
7203 tmpccer |= (OC_Config->OCNPolarity << 8U);
7204 /* Reset the Output N State */
7205 tmpccer &= ~TIM_CCER_CC3NE;
7206 }
7207
7208 #if defined(TIM_CR2_OIS3)
7209 if (IS_TIM_BREAK_INSTANCE(TIMx))
7210 {
7211 /* Check parameters */
7212 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
7213 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7214
7215 /* Reset the Output Compare and Output Compare N IDLE State */
7216 tmpcr2 &= ~TIM_CR2_OIS3;
7217 tmpcr2 &= ~TIM_CR2_OIS3N;
7218 /* Set the Output Idle state */
7219 tmpcr2 |= (OC_Config->OCIdleState << 4U);
7220 /* Set the Output N Idle state */
7221 tmpcr2 |= (OC_Config->OCNIdleState << 4U);
7222 }
7223 #endif /* TIM_CR2_OIS3 */
7224
7225 /* Write to TIMx CR2 */
7226 TIMx->CR2 = tmpcr2;
7227
7228 /* Write to TIMx CCMR2 */
7229 TIMx->CCMR2 = tmpccmrx;
7230
7231 /* Set the Capture Compare Register value */
7232 TIMx->CCR3 = OC_Config->Pulse;
7233
7234 /* Write to TIMx CCER */
7235 TIMx->CCER = tmpccer;
7236 }
7237
7238 /**
7239 * @brief Timer Output Compare 4 configuration
7240 * @param TIMx to select the TIM peripheral
7241 * @param OC_Config The output configuration structure
7242 * @retval None
7243 */
TIM_OC4_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7244 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
7245 {
7246 uint32_t tmpccmrx;
7247 uint32_t tmpccer;
7248 uint32_t tmpcr2;
7249
7250 /* Disable the Channel 4: Reset the CC4E Bit */
7251 TIMx->CCER &= ~TIM_CCER_CC4E;
7252
7253 /* Get the TIMx CCER register value */
7254 tmpccer = TIMx->CCER;
7255 /* Get the TIMx CR2 register value */
7256 tmpcr2 = TIMx->CR2;
7257
7258 /* Get the TIMx CCMR2 register value */
7259 tmpccmrx = TIMx->CCMR2;
7260
7261 /* Reset the Output Compare mode and Capture/Compare selection Bits */
7262 tmpccmrx &= ~TIM_CCMR2_OC4M;
7263 tmpccmrx &= ~TIM_CCMR2_CC4S;
7264
7265 /* Select the Output Compare Mode */
7266 tmpccmrx |= (OC_Config->OCMode << 8U);
7267
7268 /* Reset the Output Polarity level */
7269 tmpccer &= ~TIM_CCER_CC4P;
7270 /* Set the Output Compare Polarity */
7271 tmpccer |= (OC_Config->OCPolarity << 12U);
7272
7273 #if defined(TIM_CR2_OIS4)
7274 if (IS_TIM_BREAK_INSTANCE(TIMx))
7275 {
7276 /* Check parameters */
7277 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7278
7279 /* Reset the Output Compare IDLE State */
7280 tmpcr2 &= ~TIM_CR2_OIS4;
7281
7282 /* Set the Output Idle state */
7283 tmpcr2 |= (OC_Config->OCIdleState << 6U);
7284 }
7285 #endif /* TIM_CR2_OIS4 */
7286
7287 /* Write to TIMx CR2 */
7288 TIMx->CR2 = tmpcr2;
7289
7290 /* Write to TIMx CCMR2 */
7291 TIMx->CCMR2 = tmpccmrx;
7292
7293 /* Set the Capture Compare Register value */
7294 TIMx->CCR4 = OC_Config->Pulse;
7295
7296 /* Write to TIMx CCER */
7297 TIMx->CCER = tmpccer;
7298 }
7299
7300 #if defined(TIM_CCER_CC5E)
7301 /**
7302 * @brief Timer Output Compare 5 configuration
7303 * @param TIMx to select the TIM peripheral
7304 * @param OC_Config The output configuration structure
7305 * @retval None
7306 */
TIM_OC5_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7307 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
7308 const TIM_OC_InitTypeDef *OC_Config)
7309 {
7310 uint32_t tmpccmrx;
7311 uint32_t tmpccer;
7312 uint32_t tmpcr2;
7313
7314 /* Disable the output: Reset the CCxE Bit */
7315 TIMx->CCER &= ~TIM_CCER_CC5E;
7316
7317 /* Get the TIMx CCER register value */
7318 tmpccer = TIMx->CCER;
7319 /* Get the TIMx CR2 register value */
7320 tmpcr2 = TIMx->CR2;
7321 /* Get the TIMx CCMR1 register value */
7322 tmpccmrx = TIMx->CCMR3;
7323
7324 /* Reset the Output Compare Mode Bits */
7325 tmpccmrx &= ~(TIM_CCMR3_OC5M);
7326 /* Select the Output Compare Mode */
7327 tmpccmrx |= OC_Config->OCMode;
7328
7329 /* Reset the Output Polarity level */
7330 tmpccer &= ~TIM_CCER_CC5P;
7331 /* Set the Output Compare Polarity */
7332 tmpccer |= (OC_Config->OCPolarity << 16U);
7333
7334 if (IS_TIM_BREAK_INSTANCE(TIMx))
7335 {
7336 /* Reset the Output Compare IDLE State */
7337 tmpcr2 &= ~TIM_CR2_OIS5;
7338 /* Set the Output Idle state */
7339 tmpcr2 |= (OC_Config->OCIdleState << 8U);
7340 }
7341 /* Write to TIMx CR2 */
7342 TIMx->CR2 = tmpcr2;
7343
7344 /* Write to TIMx CCMR3 */
7345 TIMx->CCMR3 = tmpccmrx;
7346
7347 /* Set the Capture Compare Register value */
7348 TIMx->CCR5 = OC_Config->Pulse;
7349
7350 /* Write to TIMx CCER */
7351 TIMx->CCER = tmpccer;
7352 }
7353 #endif /* TIM_CCER_CC5E */
7354
7355 #if defined(TIM_CCER_CC6E)
7356 /**
7357 * @brief Timer Output Compare 6 configuration
7358 * @param TIMx to select the TIM peripheral
7359 * @param OC_Config The output configuration structure
7360 * @retval None
7361 */
TIM_OC6_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7362 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
7363 const TIM_OC_InitTypeDef *OC_Config)
7364 {
7365 uint32_t tmpccmrx;
7366 uint32_t tmpccer;
7367 uint32_t tmpcr2;
7368
7369 /* Disable the output: Reset the CCxE Bit */
7370 TIMx->CCER &= ~TIM_CCER_CC6E;
7371
7372 /* Get the TIMx CCER register value */
7373 tmpccer = TIMx->CCER;
7374 /* Get the TIMx CR2 register value */
7375 tmpcr2 = TIMx->CR2;
7376 /* Get the TIMx CCMR1 register value */
7377 tmpccmrx = TIMx->CCMR3;
7378
7379 /* Reset the Output Compare Mode Bits */
7380 tmpccmrx &= ~(TIM_CCMR3_OC6M);
7381 /* Select the Output Compare Mode */
7382 tmpccmrx |= (OC_Config->OCMode << 8U);
7383
7384 /* Reset the Output Polarity level */
7385 tmpccer &= (uint32_t)~TIM_CCER_CC6P;
7386 /* Set the Output Compare Polarity */
7387 tmpccer |= (OC_Config->OCPolarity << 20U);
7388
7389 if (IS_TIM_BREAK_INSTANCE(TIMx))
7390 {
7391 /* Reset the Output Compare IDLE State */
7392 tmpcr2 &= ~TIM_CR2_OIS6;
7393 /* Set the Output Idle state */
7394 tmpcr2 |= (OC_Config->OCIdleState << 10U);
7395 }
7396
7397 /* Write to TIMx CR2 */
7398 TIMx->CR2 = tmpcr2;
7399
7400 /* Write to TIMx CCMR3 */
7401 TIMx->CCMR3 = tmpccmrx;
7402
7403 /* Set the Capture Compare Register value */
7404 TIMx->CCR6 = OC_Config->Pulse;
7405
7406 /* Write to TIMx CCER */
7407 TIMx->CCER = tmpccer;
7408 }
7409 #endif /* TIM_CCER_CC6E */
7410
7411 /**
7412 * @brief Slave Timer configuration function
7413 * @param htim TIM handle
7414 * @param sSlaveConfig Slave timer configuration
7415 * @retval None
7416 */
TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef * htim,const TIM_SlaveConfigTypeDef * sSlaveConfig)7417 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
7418 const TIM_SlaveConfigTypeDef *sSlaveConfig)
7419 {
7420 HAL_StatusTypeDef status = HAL_OK;
7421 uint32_t tmpsmcr;
7422 uint32_t tmpccmr1;
7423 uint32_t tmpccer;
7424
7425 /* Get the TIMx SMCR register value */
7426 tmpsmcr = htim->Instance->SMCR;
7427
7428 /* Reset the Trigger Selection Bits */
7429 tmpsmcr &= ~TIM_SMCR_TS;
7430 /* Set the Input Trigger source */
7431 tmpsmcr |= sSlaveConfig->InputTrigger;
7432
7433 /* Reset the slave mode Bits */
7434 tmpsmcr &= ~TIM_SMCR_SMS;
7435 /* Set the slave mode */
7436 tmpsmcr |= sSlaveConfig->SlaveMode;
7437
7438 /* Write to TIMx SMCR */
7439 htim->Instance->SMCR = tmpsmcr;
7440
7441 /* Configure the trigger prescaler, filter, and polarity */
7442 switch (sSlaveConfig->InputTrigger)
7443 {
7444 case TIM_TS_ETRF:
7445 {
7446 /* Check the parameters */
7447 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
7448 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
7449 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7450 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7451 /* Configure the ETR Trigger source */
7452 TIM_ETR_SetConfig(htim->Instance,
7453 sSlaveConfig->TriggerPrescaler,
7454 sSlaveConfig->TriggerPolarity,
7455 sSlaveConfig->TriggerFilter);
7456 break;
7457 }
7458
7459 case TIM_TS_TI1F_ED:
7460 {
7461 /* Check the parameters */
7462 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
7463 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7464
7465 if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
7466 {
7467 return HAL_ERROR;
7468 }
7469
7470 /* Disable the Channel 1: Reset the CC1E Bit */
7471 tmpccer = htim->Instance->CCER;
7472 htim->Instance->CCER &= ~TIM_CCER_CC1E;
7473 tmpccmr1 = htim->Instance->CCMR1;
7474
7475 /* Set the filter */
7476 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7477 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
7478
7479 /* Write to TIMx CCMR1 and CCER registers */
7480 htim->Instance->CCMR1 = tmpccmr1;
7481 htim->Instance->CCER = tmpccer;
7482 break;
7483 }
7484
7485 case TIM_TS_TI1FP1:
7486 {
7487 /* Check the parameters */
7488 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
7489 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7490 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7491
7492 /* Configure TI1 Filter and Polarity */
7493 TIM_TI1_ConfigInputStage(htim->Instance,
7494 sSlaveConfig->TriggerPolarity,
7495 sSlaveConfig->TriggerFilter);
7496 break;
7497 }
7498
7499 case TIM_TS_TI2FP2:
7500 {
7501 /* Check the parameters */
7502 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
7503 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7504 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7505
7506 /* Configure TI2 Filter and Polarity */
7507 TIM_TI2_ConfigInputStage(htim->Instance,
7508 sSlaveConfig->TriggerPolarity,
7509 sSlaveConfig->TriggerFilter);
7510 break;
7511 }
7512
7513 case TIM_TS_ITR0:
7514 case TIM_TS_ITR1:
7515 case TIM_TS_ITR2:
7516 case TIM_TS_ITR3:
7517 {
7518 /* Check the parameter */
7519 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
7520 break;
7521 }
7522
7523 default:
7524 status = HAL_ERROR;
7525 break;
7526 }
7527
7528 return status;
7529 }
7530
7531 /**
7532 * @brief Configure the TI1 as Input.
7533 * @param TIMx to select the TIM peripheral.
7534 * @param TIM_ICPolarity The Input Polarity.
7535 * This parameter can be one of the following values:
7536 * @arg TIM_ICPOLARITY_RISING
7537 * @arg TIM_ICPOLARITY_FALLING
7538 * @arg TIM_ICPOLARITY_BOTHEDGE
7539 * @param TIM_ICSelection specifies the input to be used.
7540 * This parameter can be one of the following values:
7541 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
7542 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
7543 * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
7544 * @param TIM_ICFilter Specifies the Input Capture Filter.
7545 * This parameter must be a value between 0x00 and 0x0F.
7546 * @retval None
7547 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
7548 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
7549 * protected against un-initialized filter and polarity values.
7550 */
TIM_TI1_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7551 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7552 uint32_t TIM_ICFilter)
7553 {
7554 uint32_t tmpccmr1;
7555 uint32_t tmpccer;
7556
7557 /* Disable the Channel 1: Reset the CC1E Bit */
7558 TIMx->CCER &= ~TIM_CCER_CC1E;
7559 tmpccmr1 = TIMx->CCMR1;
7560 tmpccer = TIMx->CCER;
7561
7562 /* Select the Input */
7563 if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
7564 {
7565 tmpccmr1 &= ~TIM_CCMR1_CC1S;
7566 tmpccmr1 |= TIM_ICSelection;
7567 }
7568 else
7569 {
7570 tmpccmr1 |= TIM_CCMR1_CC1S_0;
7571 }
7572
7573 /* Set the filter */
7574 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7575 tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
7576
7577 /* Select the Polarity and set the CC1E Bit */
7578 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
7579 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
7580
7581 /* Write to TIMx CCMR1 and CCER registers */
7582 TIMx->CCMR1 = tmpccmr1;
7583 TIMx->CCER = tmpccer;
7584 }
7585
7586 /**
7587 * @brief Configure the Polarity and Filter for TI1.
7588 * @param TIMx to select the TIM peripheral.
7589 * @param TIM_ICPolarity The Input Polarity.
7590 * This parameter can be one of the following values:
7591 * @arg TIM_ICPOLARITY_RISING
7592 * @arg TIM_ICPOLARITY_FALLING
7593 * @arg TIM_ICPOLARITY_BOTHEDGE
7594 * @param TIM_ICFilter Specifies the Input Capture Filter.
7595 * This parameter must be a value between 0x00 and 0x0F.
7596 * @retval None
7597 */
TIM_TI1_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)7598 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
7599 {
7600 uint32_t tmpccmr1;
7601 uint32_t tmpccer;
7602
7603 /* Disable the Channel 1: Reset the CC1E Bit */
7604 tmpccer = TIMx->CCER;
7605 TIMx->CCER &= ~TIM_CCER_CC1E;
7606 tmpccmr1 = TIMx->CCMR1;
7607
7608 /* Set the filter */
7609 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7610 tmpccmr1 |= (TIM_ICFilter << 4U);
7611
7612 /* Select the Polarity and set the CC1E Bit */
7613 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
7614 tmpccer |= TIM_ICPolarity;
7615
7616 /* Write to TIMx CCMR1 and CCER registers */
7617 TIMx->CCMR1 = tmpccmr1;
7618 TIMx->CCER = tmpccer;
7619 }
7620
7621 /**
7622 * @brief Configure the TI2 as Input.
7623 * @param TIMx to select the TIM peripheral
7624 * @param TIM_ICPolarity The Input Polarity.
7625 * This parameter can be one of the following values:
7626 * @arg TIM_ICPOLARITY_RISING
7627 * @arg TIM_ICPOLARITY_FALLING
7628 * @arg TIM_ICPOLARITY_BOTHEDGE
7629 * @param TIM_ICSelection specifies the input to be used.
7630 * This parameter can be one of the following values:
7631 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
7632 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
7633 * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
7634 * @param TIM_ICFilter Specifies the Input Capture Filter.
7635 * This parameter must be a value between 0x00 and 0x0F.
7636 * @retval None
7637 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
7638 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
7639 * protected against un-initialized filter and polarity values.
7640 */
TIM_TI2_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7641 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7642 uint32_t TIM_ICFilter)
7643 {
7644 uint32_t tmpccmr1;
7645 uint32_t tmpccer;
7646
7647 /* Disable the Channel 2: Reset the CC2E Bit */
7648 TIMx->CCER &= ~TIM_CCER_CC2E;
7649 tmpccmr1 = TIMx->CCMR1;
7650 tmpccer = TIMx->CCER;
7651
7652 /* Select the Input */
7653 tmpccmr1 &= ~TIM_CCMR1_CC2S;
7654 tmpccmr1 |= (TIM_ICSelection << 8U);
7655
7656 /* Set the filter */
7657 tmpccmr1 &= ~TIM_CCMR1_IC2F;
7658 tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
7659
7660 /* Select the Polarity and set the CC2E Bit */
7661 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
7662 tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
7663
7664 /* Write to TIMx CCMR1 and CCER registers */
7665 TIMx->CCMR1 = tmpccmr1 ;
7666 TIMx->CCER = tmpccer;
7667 }
7668
7669 /**
7670 * @brief Configure the Polarity and Filter for TI2.
7671 * @param TIMx to select the TIM peripheral.
7672 * @param TIM_ICPolarity The Input Polarity.
7673 * This parameter can be one of the following values:
7674 * @arg TIM_ICPOLARITY_RISING
7675 * @arg TIM_ICPOLARITY_FALLING
7676 * @arg TIM_ICPOLARITY_BOTHEDGE
7677 * @param TIM_ICFilter Specifies the Input Capture Filter.
7678 * This parameter must be a value between 0x00 and 0x0F.
7679 * @retval None
7680 */
TIM_TI2_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)7681 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
7682 {
7683 uint32_t tmpccmr1;
7684 uint32_t tmpccer;
7685
7686 /* Disable the Channel 2: Reset the CC2E Bit */
7687 TIMx->CCER &= ~TIM_CCER_CC2E;
7688 tmpccmr1 = TIMx->CCMR1;
7689 tmpccer = TIMx->CCER;
7690
7691 /* Set the filter */
7692 tmpccmr1 &= ~TIM_CCMR1_IC2F;
7693 tmpccmr1 |= (TIM_ICFilter << 12U);
7694
7695 /* Select the Polarity and set the CC2E Bit */
7696 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
7697 tmpccer |= (TIM_ICPolarity << 4U);
7698
7699 /* Write to TIMx CCMR1 and CCER registers */
7700 TIMx->CCMR1 = tmpccmr1 ;
7701 TIMx->CCER = tmpccer;
7702 }
7703
7704 /**
7705 * @brief Configure the TI3 as Input.
7706 * @param TIMx to select the TIM peripheral
7707 * @param TIM_ICPolarity The Input Polarity.
7708 * This parameter can be one of the following values:
7709 * @arg TIM_ICPOLARITY_RISING
7710 * @arg TIM_ICPOLARITY_FALLING
7711 * @arg TIM_ICPOLARITY_BOTHEDGE
7712 * @param TIM_ICSelection specifies the input to be used.
7713 * This parameter can be one of the following values:
7714 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
7715 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
7716 * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
7717 * @param TIM_ICFilter Specifies the Input Capture Filter.
7718 * This parameter must be a value between 0x00 and 0x0F.
7719 * @retval None
7720 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
7721 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
7722 * protected against un-initialized filter and polarity values.
7723 */
TIM_TI3_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7724 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7725 uint32_t TIM_ICFilter)
7726 {
7727 uint32_t tmpccmr2;
7728 uint32_t tmpccer;
7729
7730 /* Disable the Channel 3: Reset the CC3E Bit */
7731 TIMx->CCER &= ~TIM_CCER_CC3E;
7732 tmpccmr2 = TIMx->CCMR2;
7733 tmpccer = TIMx->CCER;
7734
7735 /* Select the Input */
7736 tmpccmr2 &= ~TIM_CCMR2_CC3S;
7737 tmpccmr2 |= TIM_ICSelection;
7738
7739 /* Set the filter */
7740 tmpccmr2 &= ~TIM_CCMR2_IC3F;
7741 tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
7742
7743 /* Select the Polarity and set the CC3E Bit */
7744 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
7745 tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
7746
7747 /* Write to TIMx CCMR2 and CCER registers */
7748 TIMx->CCMR2 = tmpccmr2;
7749 TIMx->CCER = tmpccer;
7750 }
7751
7752 /**
7753 * @brief Configure the TI4 as Input.
7754 * @param TIMx to select the TIM peripheral
7755 * @param TIM_ICPolarity The Input Polarity.
7756 * This parameter can be one of the following values:
7757 * @arg TIM_ICPOLARITY_RISING
7758 * @arg TIM_ICPOLARITY_FALLING
7759 * @arg TIM_ICPOLARITY_BOTHEDGE
7760 * @param TIM_ICSelection specifies the input to be used.
7761 * This parameter can be one of the following values:
7762 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
7763 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
7764 * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
7765 * @param TIM_ICFilter Specifies the Input Capture Filter.
7766 * This parameter must be a value between 0x00 and 0x0F.
7767 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
7768 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
7769 * protected against un-initialized filter and polarity values.
7770 * @retval None
7771 */
TIM_TI4_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7772 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7773 uint32_t TIM_ICFilter)
7774 {
7775 uint32_t tmpccmr2;
7776 uint32_t tmpccer;
7777
7778 /* Disable the Channel 4: Reset the CC4E Bit */
7779 TIMx->CCER &= ~TIM_CCER_CC4E;
7780 tmpccmr2 = TIMx->CCMR2;
7781 tmpccer = TIMx->CCER;
7782
7783 /* Select the Input */
7784 tmpccmr2 &= ~TIM_CCMR2_CC4S;
7785 tmpccmr2 |= (TIM_ICSelection << 8U);
7786
7787 /* Set the filter */
7788 tmpccmr2 &= ~TIM_CCMR2_IC4F;
7789 tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
7790
7791 /* Select the Polarity and set the CC4E Bit */
7792 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
7793 tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
7794
7795 /* Write to TIMx CCMR2 and CCER registers */
7796 TIMx->CCMR2 = tmpccmr2;
7797 TIMx->CCER = tmpccer ;
7798 }
7799
7800 /**
7801 * @brief Selects the Input Trigger source
7802 * @param TIMx to select the TIM peripheral
7803 * @param InputTriggerSource The Input Trigger source.
7804 * This parameter can be one of the following values:
7805 * @arg TIM_TS_ITR0: Internal Trigger 0
7806 * @arg TIM_TS_ITR1: Internal Trigger 1
7807 * @arg TIM_TS_ITR2: Internal Trigger 2
7808 * @arg TIM_TS_ITR3: Internal Trigger 3
7809 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
7810 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
7811 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
7812 * @arg TIM_TS_ETRF: External Trigger input
7813 * @retval None
7814 */
TIM_ITRx_SetConfig(TIM_TypeDef * TIMx,uint32_t InputTriggerSource)7815 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
7816 {
7817 uint32_t tmpsmcr;
7818
7819 /* Get the TIMx SMCR register value */
7820 tmpsmcr = TIMx->SMCR;
7821 /* Reset the TS Bits */
7822 tmpsmcr &= ~TIM_SMCR_TS;
7823 /* Set the Input Trigger source and the slave mode*/
7824 tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
7825 /* Write to TIMx SMCR */
7826 TIMx->SMCR = tmpsmcr;
7827 }
7828 /**
7829 * @brief Configures the TIMx External Trigger (ETR).
7830 * @param TIMx to select the TIM peripheral
7831 * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
7832 * This parameter can be one of the following values:
7833 * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
7834 * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
7835 * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
7836 * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
7837 * @param TIM_ExtTRGPolarity The external Trigger Polarity.
7838 * This parameter can be one of the following values:
7839 * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
7840 * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
7841 * @param ExtTRGFilter External Trigger Filter.
7842 * This parameter must be a value between 0x00 and 0x0F
7843 * @retval None
7844 */
TIM_ETR_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ExtTRGPrescaler,uint32_t TIM_ExtTRGPolarity,uint32_t ExtTRGFilter)7845 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
7846 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
7847 {
7848 uint32_t tmpsmcr;
7849
7850 tmpsmcr = TIMx->SMCR;
7851
7852 /* Reset the ETR Bits */
7853 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
7854
7855 /* Set the Prescaler, the Filter value and the Polarity */
7856 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
7857
7858 /* Write to TIMx SMCR */
7859 TIMx->SMCR = tmpsmcr;
7860 }
7861
7862 /**
7863 * @brief Enables or disables the TIM Capture Compare Channel x.
7864 * @param TIMx to select the TIM peripheral
7865 * @param Channel specifies the TIM Channel
7866 * This parameter can be one of the following values:
7867 * @arg TIM_CHANNEL_1: TIM Channel 1
7868 * @arg TIM_CHANNEL_2: TIM Channel 2
7869 * @arg TIM_CHANNEL_3: TIM Channel 3
7870 * @arg TIM_CHANNEL_4: TIM Channel 4
7871 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
7872 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
7873 * @param ChannelState specifies the TIM Channel CCxE bit new state.
7874 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
7875 * @retval None
7876 */
TIM_CCxChannelCmd(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ChannelState)7877 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
7878 {
7879 uint32_t tmp;
7880
7881 /* Check the parameters */
7882 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
7883 assert_param(IS_TIM_CHANNELS(Channel));
7884
7885 tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
7886
7887 /* Reset the CCxE Bit */
7888 TIMx->CCER &= ~tmp;
7889
7890 /* Set or reset the CCxE Bit */
7891 TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
7892 }
7893
7894 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7895 /**
7896 * @brief Reset interrupt callbacks to the legacy weak callbacks.
7897 * @param htim pointer to a TIM_HandleTypeDef structure that contains
7898 * the configuration information for TIM module.
7899 * @retval None
7900 */
TIM_ResetCallback(TIM_HandleTypeDef * htim)7901 void TIM_ResetCallback(TIM_HandleTypeDef *htim)
7902 {
7903 /* Reset the TIM callback to the legacy weak callbacks */
7904 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
7905 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
7906 htim->TriggerCallback = HAL_TIM_TriggerCallback;
7907 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
7908 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
7909 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
7910 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
7911 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
7912 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
7913 htim->ErrorCallback = HAL_TIM_ErrorCallback;
7914 htim->CommutationCallback = HAL_TIMEx_CommutCallback;
7915 htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback;
7916 htim->BreakCallback = HAL_TIMEx_BreakCallback;
7917 #if defined(TIM_BDTR_BK2E)
7918 htim->Break2Callback = HAL_TIMEx_Break2Callback;
7919 #endif /* TIM_BDTR_BK2E */
7920 }
7921 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7922
7923 /**
7924 * @}
7925 */
7926
7927 #endif /* HAL_TIM_MODULE_ENABLED */
7928 /**
7929 * @}
7930 */
7931
7932 /**
7933 * @}
7934 */
7935
