1 /**
2 ******************************************************************************
3 * @file stm32f0xx_ll_i2c.h
4 * @author MCD Application Team
5 * @brief Header file of I2C LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32F0xx_LL_I2C_H
21 #define STM32F0xx_LL_I2C_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f0xx.h"
29
30 /** @addtogroup STM32F0xx_LL_Driver
31 * @{
32 */
33
34 #if defined (I2C1) || defined (I2C2)
35
36 /** @defgroup I2C_LL I2C
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup I2C_LL_Private_Constants I2C Private Constants
45 * @{
46 */
47 /**
48 * @}
49 */
50
51 /* Private macros ------------------------------------------------------------*/
52 #if defined(USE_FULL_LL_DRIVER)
53 /** @defgroup I2C_LL_Private_Macros I2C Private Macros
54 * @{
55 */
56 /**
57 * @}
58 */
59 #endif /*USE_FULL_LL_DRIVER*/
60
61 /* Exported types ------------------------------------------------------------*/
62 #if defined(USE_FULL_LL_DRIVER)
63 /** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
64 * @{
65 */
66 typedef struct
67 {
68 uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
69 This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE.
70
71 This feature can be modified afterwards using unitary function
72 @ref LL_I2C_SetMode(). */
73
74 uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
75 This parameter must be set by referring to the STM32CubeMX Tool and
76 the helper macro @ref __LL_I2C_CONVERT_TIMINGS().
77
78 This feature can be modified afterwards using unitary function
79 @ref LL_I2C_SetTiming(). */
80
81 uint32_t AnalogFilter; /*!< Enables or disables analog noise filter.
82 This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION.
83
84 This feature can be modified afterwards using unitary functions
85 @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
86
87 uint32_t DigitalFilter; /*!< Configures the digital noise filter.
88 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F.
89
90 This feature can be modified afterwards using unitary function
91 @ref LL_I2C_SetDigitalFilter(). */
92
93 uint32_t OwnAddress1; /*!< Specifies the device own address 1.
94 This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF.
95
96 This feature can be modified afterwards using unitary function
97 @ref LL_I2C_SetOwnAddress1(). */
98
99 uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive
100 match code or next received byte.
101 This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE.
102
103 This feature can be modified afterwards using unitary function
104 @ref LL_I2C_AcknowledgeNextData(). */
105
106 uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
107 This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1.
108
109 This feature can be modified afterwards using unitary function
110 @ref LL_I2C_SetOwnAddress1(). */
111 } LL_I2C_InitTypeDef;
112 /**
113 * @}
114 */
115 #endif /*USE_FULL_LL_DRIVER*/
116
117 /* Exported constants --------------------------------------------------------*/
118 /** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
119 * @{
120 */
121
122 /** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines
123 * @brief Flags defines which can be used with LL_I2C_WriteReg function
124 * @{
125 */
126 #define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF /*!< Address Matched flag */
127 #define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF /*!< Not Acknowledge flag */
128 #define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF /*!< Stop detection flag */
129 #define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF /*!< Bus error flag */
130 #define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF /*!< Arbitration Lost flag */
131 #define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF /*!< Overrun/Underrun flag */
132 #define LL_I2C_ICR_PECCF I2C_ICR_PECCF /*!< PEC error flag */
133 #define LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF /*!< Timeout detection flag */
134 #define LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF /*!< Alert flag */
135 /**
136 * @}
137 */
138
139 /** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
140 * @brief Flags defines which can be used with LL_I2C_ReadReg function
141 * @{
142 */
143 #define LL_I2C_ISR_TXE I2C_ISR_TXE /*!< Transmit data register empty */
144 #define LL_I2C_ISR_TXIS I2C_ISR_TXIS /*!< Transmit interrupt status */
145 #define LL_I2C_ISR_RXNE I2C_ISR_RXNE /*!< Receive data register not empty */
146 #define LL_I2C_ISR_ADDR I2C_ISR_ADDR /*!< Address matched (slave mode) */
147 #define LL_I2C_ISR_NACKF I2C_ISR_NACKF /*!< Not Acknowledge received flag */
148 #define LL_I2C_ISR_STOPF I2C_ISR_STOPF /*!< Stop detection flag */
149 #define LL_I2C_ISR_TC I2C_ISR_TC /*!< Transfer Complete (master mode) */
150 #define LL_I2C_ISR_TCR I2C_ISR_TCR /*!< Transfer Complete Reload */
151 #define LL_I2C_ISR_BERR I2C_ISR_BERR /*!< Bus error */
152 #define LL_I2C_ISR_ARLO I2C_ISR_ARLO /*!< Arbitration lost */
153 #define LL_I2C_ISR_OVR I2C_ISR_OVR /*!< Overrun/Underrun (slave mode) */
154 #define LL_I2C_ISR_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */
155 #define LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */
156 #define LL_I2C_ISR_ALERT I2C_ISR_ALERT /*!< SMBus alert (SMBus mode) */
157 #define LL_I2C_ISR_BUSY I2C_ISR_BUSY /*!< Bus busy */
158 /**
159 * @}
160 */
161
162 /** @defgroup I2C_LL_EC_IT IT Defines
163 * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
164 * @{
165 */
166 #define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable */
167 #define LL_I2C_CR1_RXIE I2C_CR1_RXIE /*!< RX Interrupt enable */
168 #define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE /*!< Address match Interrupt enable (slave only) */
169 #define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE /*!< Not acknowledge received Interrupt enable */
170 #define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE /*!< STOP detection Interrupt enable */
171 #define LL_I2C_CR1_TCIE I2C_CR1_TCIE /*!< Transfer Complete interrupt enable */
172 #define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable */
173 /**
174 * @}
175 */
176
177 /** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
178 * @{
179 */
180 #define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */
181 #define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */
182 #define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode
183 (Default address not acknowledge) */
184 #define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */
185 /**
186 * @}
187 */
188
189 /** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
190 * @{
191 */
192 #define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */
193 #define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /*!< Analog filter is disabled. */
194 /**
195 * @}
196 */
197
198 /** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
199 * @{
200 */
201 #define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U /*!< Master operates in 7-bit addressing mode. */
202 #define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10 /*!< Master operates in 10-bit addressing mode.*/
203 /**
204 * @}
205 */
206
207 /** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
208 * @{
209 */
210 #define LL_I2C_OWNADDRESS1_7BIT 0x00000000U /*!< Own address 1 is a 7-bit address. */
211 #define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE /*!< Own address 1 is a 10-bit address.*/
212 /**
213 * @}
214 */
215
216 /** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
217 * @{
218 */
219 #define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */
220 #define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */
221 #define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */
222 #define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */
223 #define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */
224 #define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */
225 #define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */
226 #define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /*!< No comparison is done.
227 All Address2 are acknowledged. */
228 /**
229 * @}
230 */
231
232 /** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
233 * @{
234 */
235 #define LL_I2C_ACK 0x00000000U /*!< ACK is sent after current received byte. */
236 #define LL_I2C_NACK I2C_CR2_NACK /*!< NACK is sent after current received byte.*/
237 /**
238 * @}
239 */
240
241 /** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length
242 * @{
243 */
244 #define LL_I2C_ADDRSLAVE_7BIT 0x00000000U /*!< Slave Address in 7-bit. */
245 #define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10 /*!< Slave Address in 10-bit.*/
246 /**
247 * @}
248 */
249
250 /** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction
251 * @{
252 */
253 #define LL_I2C_REQUEST_WRITE 0x00000000U /*!< Master request a write transfer. */
254 #define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN /*!< Master request a read transfer. */
255 /**
256 * @}
257 */
258
259 /** @defgroup I2C_LL_EC_MODE Transfer End Mode
260 * @{
261 */
262 #define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */
263 #define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode
264 with no HW PEC comparison. */
265 #define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode
266 with no HW PEC comparison. */
267 #define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode
268 with HW PEC comparison. */
269 #define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode
270 with HW PEC comparison. */
271 #define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode
272 with HW PEC comparison. */
273 #define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)
274 /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
275 #define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)
276 /*!< Enable SMBUS Software end mode with HW PEC comparison. */
277 /**
278 * @}
279 */
280
281 /** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
282 * @{
283 */
284 #define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U
285 /*!< Don't Generate Stop and Start condition. */
286 #define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
287 /*!< Generate Stop condition (Size should be set to 0). */
288 #define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
289 /*!< Generate Start for read request. */
290 #define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
291 /*!< Generate Start for write request. */
292 #define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
293 /*!< Generate Restart for read request, slave 7Bit address. */
294 #define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
295 /*!< Generate Restart for write request, slave 7Bit address. */
296 #define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | \
297 I2C_CR2_RD_WRN | I2C_CR2_HEAD10R)
298 /*!< Generate Restart for read request, slave 10Bit address. */
299 #define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
300 /*!< Generate Restart for write request, slave 10Bit address.*/
301 /**
302 * @}
303 */
304
305 /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
306 * @{
307 */
308 #define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master,
309 slave enters receiver mode. */
310 #define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master,
311 slave enters transmitter mode.*/
312 /**
313 * @}
314 */
315
316 /** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
317 * @{
318 */
319 #define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for
320 transmission */
321 #define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for
322 reception */
323 /**
324 * @}
325 */
326
327 /** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
328 * @{
329 */
330 #define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect
331 SCL low level timeout. */
332 #define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect
333 both SCL and SDA high level timeout.*/
334 /**
335 * @}
336 */
337
338 /** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
339 * @{
340 */
341 #define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */
342 #define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock)
343 enable bit */
344 #define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | \
345 I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB
346 (extended clock) enable bits */
347 /**
348 * @}
349 */
350
351 /**
352 * @}
353 */
354
355 /* Exported macro ------------------------------------------------------------*/
356 /** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
357 * @{
358 */
359
360 /** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
361 * @{
362 */
363
364 /**
365 * @brief Write a value in I2C register
366 * @param __INSTANCE__ I2C Instance
367 * @param __REG__ Register to be written
368 * @param __VALUE__ Value to be written in the register
369 * @retval None
370 */
371 #define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
372
373 /**
374 * @brief Read a value in I2C register
375 * @param __INSTANCE__ I2C Instance
376 * @param __REG__ Register to be read
377 * @retval Register value
378 */
379 #define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
380 /**
381 * @}
382 */
383
384 /** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
385 * @{
386 */
387 /**
388 * @brief Configure the SDA setup, hold time and the SCL high, low period.
389 * @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
390 * @param __SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
391 (tscldel = (SCLDEL+1)xtpresc)
392 * @param __HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
393 (tsdadel = SDADELxtpresc)
394 * @param __SCLH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
395 (tsclh = (SCLH+1)xtpresc)
396 * @param __SCLL_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
397 (tscll = (SCLL+1)xtpresc)
398 * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
399 */
400 #define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCLH_PERIOD__, __SCLL_PERIOD__) \
401 ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \
402 (((uint32_t)(__SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \
403 (((uint32_t)(__HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \
404 (((uint32_t)(__SCLH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \
405 (((uint32_t)(__SCLL_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL))
406 /**
407 * @}
408 */
409
410 /**
411 * @}
412 */
413
414 /* Exported functions --------------------------------------------------------*/
415 /** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
416 * @{
417 */
418
419 /** @defgroup I2C_LL_EF_Configuration Configuration
420 * @{
421 */
422
423 /**
424 * @brief Enable I2C peripheral (PE = 1).
425 * @rmtoll CR1 PE LL_I2C_Enable
426 * @param I2Cx I2C Instance.
427 * @retval None
428 */
LL_I2C_Enable(I2C_TypeDef * I2Cx)429 __STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
430 {
431 SET_BIT(I2Cx->CR1, I2C_CR1_PE);
432 }
433
434 /**
435 * @brief Disable I2C peripheral (PE = 0).
436 * @note When PE = 0, the I2C SCL and SDA lines are released.
437 * Internal state machines and status bits are put back to their reset value.
438 * When cleared, PE must be kept low for at least 3 APB clock cycles.
439 * @rmtoll CR1 PE LL_I2C_Disable
440 * @param I2Cx I2C Instance.
441 * @retval None
442 */
LL_I2C_Disable(I2C_TypeDef * I2Cx)443 __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
444 {
445 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
446 }
447
448 /**
449 * @brief Check if the I2C peripheral is enabled or disabled.
450 * @rmtoll CR1 PE LL_I2C_IsEnabled
451 * @param I2Cx I2C Instance.
452 * @retval State of bit (1 or 0).
453 */
LL_I2C_IsEnabled(const I2C_TypeDef * I2Cx)454 __STATIC_INLINE uint32_t LL_I2C_IsEnabled(const I2C_TypeDef *I2Cx)
455 {
456 return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL);
457 }
458
459 /**
460 * @brief Configure Noise Filters (Analog and Digital).
461 * @note If the analog filter is also enabled, the digital filter is added to analog filter.
462 * The filters can only be programmed when the I2C is disabled (PE = 0).
463 * @rmtoll CR1 ANFOFF LL_I2C_ConfigFilters\n
464 * CR1 DNF LL_I2C_ConfigFilters
465 * @param I2Cx I2C Instance.
466 * @param AnalogFilter This parameter can be one of the following values:
467 * @arg @ref LL_I2C_ANALOGFILTER_ENABLE
468 * @arg @ref LL_I2C_ANALOGFILTER_DISABLE
469 * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
470 and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
471 * This parameter is used to configure the digital noise filter on SDA and SCL input.
472 * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
473 * @retval None
474 */
LL_I2C_ConfigFilters(I2C_TypeDef * I2Cx,uint32_t AnalogFilter,uint32_t DigitalFilter)475 __STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
476 {
477 MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos));
478 }
479
480 /**
481 * @brief Configure Digital Noise Filter.
482 * @note If the analog filter is also enabled, the digital filter is added to analog filter.
483 * This filter can only be programmed when the I2C is disabled (PE = 0).
484 * @rmtoll CR1 DNF LL_I2C_SetDigitalFilter
485 * @param I2Cx I2C Instance.
486 * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
487 and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
488 * This parameter is used to configure the digital noise filter on SDA and SCL input.
489 * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
490 * @retval None
491 */
LL_I2C_SetDigitalFilter(I2C_TypeDef * I2Cx,uint32_t DigitalFilter)492 __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
493 {
494 MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos);
495 }
496
497 /**
498 * @brief Get the current Digital Noise Filter configuration.
499 * @rmtoll CR1 DNF LL_I2C_GetDigitalFilter
500 * @param I2Cx I2C Instance.
501 * @retval Value between Min_Data=0x0 and Max_Data=0xF
502 */
LL_I2C_GetDigitalFilter(const I2C_TypeDef * I2Cx)503 __STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(const I2C_TypeDef *I2Cx)
504 {
505 return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
506 }
507
508 /**
509 * @brief Enable Analog Noise Filter.
510 * @note This filter can only be programmed when the I2C is disabled (PE = 0).
511 * @rmtoll CR1 ANFOFF LL_I2C_EnableAnalogFilter
512 * @param I2Cx I2C Instance.
513 * @retval None
514 */
LL_I2C_EnableAnalogFilter(I2C_TypeDef * I2Cx)515 __STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
516 {
517 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
518 }
519
520 /**
521 * @brief Disable Analog Noise Filter.
522 * @note This filter can only be programmed when the I2C is disabled (PE = 0).
523 * @rmtoll CR1 ANFOFF LL_I2C_DisableAnalogFilter
524 * @param I2Cx I2C Instance.
525 * @retval None
526 */
LL_I2C_DisableAnalogFilter(I2C_TypeDef * I2Cx)527 __STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
528 {
529 SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
530 }
531
532 /**
533 * @brief Check if Analog Noise Filter is enabled or disabled.
534 * @rmtoll CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter
535 * @param I2Cx I2C Instance.
536 * @retval State of bit (1 or 0).
537 */
LL_I2C_IsEnabledAnalogFilter(const I2C_TypeDef * I2Cx)538 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(const I2C_TypeDef *I2Cx)
539 {
540 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL);
541 }
542
543 /**
544 * @brief Enable DMA transmission requests.
545 * @rmtoll CR1 TXDMAEN LL_I2C_EnableDMAReq_TX
546 * @param I2Cx I2C Instance.
547 * @retval None
548 */
LL_I2C_EnableDMAReq_TX(I2C_TypeDef * I2Cx)549 __STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
550 {
551 SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
552 }
553
554 /**
555 * @brief Disable DMA transmission requests.
556 * @rmtoll CR1 TXDMAEN LL_I2C_DisableDMAReq_TX
557 * @param I2Cx I2C Instance.
558 * @retval None
559 */
LL_I2C_DisableDMAReq_TX(I2C_TypeDef * I2Cx)560 __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
561 {
562 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
563 }
564
565 /**
566 * @brief Check if DMA transmission requests are enabled or disabled.
567 * @rmtoll CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX
568 * @param I2Cx I2C Instance.
569 * @retval State of bit (1 or 0).
570 */
LL_I2C_IsEnabledDMAReq_TX(const I2C_TypeDef * I2Cx)571 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(const I2C_TypeDef *I2Cx)
572 {
573 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL);
574 }
575
576 /**
577 * @brief Enable DMA reception requests.
578 * @rmtoll CR1 RXDMAEN LL_I2C_EnableDMAReq_RX
579 * @param I2Cx I2C Instance.
580 * @retval None
581 */
LL_I2C_EnableDMAReq_RX(I2C_TypeDef * I2Cx)582 __STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
583 {
584 SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
585 }
586
587 /**
588 * @brief Disable DMA reception requests.
589 * @rmtoll CR1 RXDMAEN LL_I2C_DisableDMAReq_RX
590 * @param I2Cx I2C Instance.
591 * @retval None
592 */
LL_I2C_DisableDMAReq_RX(I2C_TypeDef * I2Cx)593 __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
594 {
595 CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
596 }
597
598 /**
599 * @brief Check if DMA reception requests are enabled or disabled.
600 * @rmtoll CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX
601 * @param I2Cx I2C Instance.
602 * @retval State of bit (1 or 0).
603 */
LL_I2C_IsEnabledDMAReq_RX(const I2C_TypeDef * I2Cx)604 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(const I2C_TypeDef *I2Cx)
605 {
606 return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL);
607 }
608
609 /**
610 * @brief Get the data register address used for DMA transfer
611 * @rmtoll TXDR TXDATA LL_I2C_DMA_GetRegAddr\n
612 * RXDR RXDATA LL_I2C_DMA_GetRegAddr
613 * @param I2Cx I2C Instance
614 * @param Direction This parameter can be one of the following values:
615 * @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT
616 * @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
617 * @retval Address of data register
618 */
LL_I2C_DMA_GetRegAddr(const I2C_TypeDef * I2Cx,uint32_t Direction)619 __STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(const I2C_TypeDef *I2Cx, uint32_t Direction)
620 {
621 uint32_t data_reg_addr;
622
623 if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
624 {
625 /* return address of TXDR register */
626 data_reg_addr = (uint32_t) &(I2Cx->TXDR);
627 }
628 else
629 {
630 /* return address of RXDR register */
631 data_reg_addr = (uint32_t) &(I2Cx->RXDR);
632 }
633
634 return data_reg_addr;
635 }
636
637 /**
638 * @brief Enable Clock stretching.
639 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
640 * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
641 * @param I2Cx I2C Instance.
642 * @retval None
643 */
LL_I2C_EnableClockStretching(I2C_TypeDef * I2Cx)644 __STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
645 {
646 CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
647 }
648
649 /**
650 * @brief Disable Clock stretching.
651 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
652 * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
653 * @param I2Cx I2C Instance.
654 * @retval None
655 */
LL_I2C_DisableClockStretching(I2C_TypeDef * I2Cx)656 __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
657 {
658 SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
659 }
660
661 /**
662 * @brief Check if Clock stretching is enabled or disabled.
663 * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
664 * @param I2Cx I2C Instance.
665 * @retval State of bit (1 or 0).
666 */
LL_I2C_IsEnabledClockStretching(const I2C_TypeDef * I2Cx)667 __STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(const I2C_TypeDef *I2Cx)
668 {
669 return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL);
670 }
671
672 /**
673 * @brief Enable hardware byte control in slave mode.
674 * @rmtoll CR1 SBC LL_I2C_EnableSlaveByteControl
675 * @param I2Cx I2C Instance.
676 * @retval None
677 */
LL_I2C_EnableSlaveByteControl(I2C_TypeDef * I2Cx)678 __STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx)
679 {
680 SET_BIT(I2Cx->CR1, I2C_CR1_SBC);
681 }
682
683 /**
684 * @brief Disable hardware byte control in slave mode.
685 * @rmtoll CR1 SBC LL_I2C_DisableSlaveByteControl
686 * @param I2Cx I2C Instance.
687 * @retval None
688 */
LL_I2C_DisableSlaveByteControl(I2C_TypeDef * I2Cx)689 __STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
690 {
691 CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC);
692 }
693
694 /**
695 * @brief Check if hardware byte control in slave mode is enabled or disabled.
696 * @rmtoll CR1 SBC LL_I2C_IsEnabledSlaveByteControl
697 * @param I2Cx I2C Instance.
698 * @retval State of bit (1 or 0).
699 */
LL_I2C_IsEnabledSlaveByteControl(const I2C_TypeDef * I2Cx)700 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(const I2C_TypeDef *I2Cx)
701 {
702 return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL);
703 }
704
705 #if defined(I2C_CR1_WUPEN)
706 /**
707 * @brief Enable Wakeup from STOP.
708 * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
709 * WakeUpFromStop feature is supported by the I2Cx Instance.
710 * @note This bit can only be programmed when Digital Filter is disabled.
711 * @rmtoll CR1 WUPEN LL_I2C_EnableWakeUpFromStop
712 * @param I2Cx I2C Instance.
713 * @retval None
714 */
LL_I2C_EnableWakeUpFromStop(I2C_TypeDef * I2Cx)715 __STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx)
716 {
717 SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
718 }
719
720 /**
721 * @brief Disable Wakeup from STOP.
722 * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
723 * WakeUpFromStop feature is supported by the I2Cx Instance.
724 * @rmtoll CR1 WUPEN LL_I2C_DisableWakeUpFromStop
725 * @param I2Cx I2C Instance.
726 * @retval None
727 */
LL_I2C_DisableWakeUpFromStop(I2C_TypeDef * I2Cx)728 __STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
729 {
730 CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
731 }
732
733 /**
734 * @brief Check if Wakeup from STOP is enabled or disabled.
735 * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
736 * WakeUpFromStop feature is supported by the I2Cx Instance.
737 * @rmtoll CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop
738 * @param I2Cx I2C Instance.
739 * @retval State of bit (1 or 0).
740 */
LL_I2C_IsEnabledWakeUpFromStop(const I2C_TypeDef * I2Cx)741 __STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(const I2C_TypeDef *I2Cx)
742 {
743 return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL);
744 }
745
746 #endif /* I2C_CR1_WUPEN */
747 /**
748 * @brief Enable General Call.
749 * @note When enabled the Address 0x00 is ACKed.
750 * @rmtoll CR1 GCEN LL_I2C_EnableGeneralCall
751 * @param I2Cx I2C Instance.
752 * @retval None
753 */
LL_I2C_EnableGeneralCall(I2C_TypeDef * I2Cx)754 __STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
755 {
756 SET_BIT(I2Cx->CR1, I2C_CR1_GCEN);
757 }
758
759 /**
760 * @brief Disable General Call.
761 * @note When disabled the Address 0x00 is NACKed.
762 * @rmtoll CR1 GCEN LL_I2C_DisableGeneralCall
763 * @param I2Cx I2C Instance.
764 * @retval None
765 */
LL_I2C_DisableGeneralCall(I2C_TypeDef * I2Cx)766 __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
767 {
768 CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
769 }
770
771 /**
772 * @brief Check if General Call is enabled or disabled.
773 * @rmtoll CR1 GCEN LL_I2C_IsEnabledGeneralCall
774 * @param I2Cx I2C Instance.
775 * @retval State of bit (1 or 0).
776 */
LL_I2C_IsEnabledGeneralCall(const I2C_TypeDef * I2Cx)777 __STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(const I2C_TypeDef *I2Cx)
778 {
779 return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL);
780 }
781
782 /**
783 * @brief Configure the Master to operate in 7-bit or 10-bit addressing mode.
784 * @note Changing this bit is not allowed, when the START bit is set.
785 * @rmtoll CR2 ADD10 LL_I2C_SetMasterAddressingMode
786 * @param I2Cx I2C Instance.
787 * @param AddressingMode This parameter can be one of the following values:
788 * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
789 * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
790 * @retval None
791 */
LL_I2C_SetMasterAddressingMode(I2C_TypeDef * I2Cx,uint32_t AddressingMode)792 __STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode)
793 {
794 MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode);
795 }
796
797 /**
798 * @brief Get the Master addressing mode.
799 * @rmtoll CR2 ADD10 LL_I2C_GetMasterAddressingMode
800 * @param I2Cx I2C Instance.
801 * @retval Returned value can be one of the following values:
802 * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
803 * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
804 */
LL_I2C_GetMasterAddressingMode(const I2C_TypeDef * I2Cx)805 __STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(const I2C_TypeDef *I2Cx)
806 {
807 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
808 }
809
810 /**
811 * @brief Set the Own Address1.
812 * @rmtoll OAR1 OA1 LL_I2C_SetOwnAddress1\n
813 * OAR1 OA1MODE LL_I2C_SetOwnAddress1
814 * @param I2Cx I2C Instance.
815 * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
816 * @param OwnAddrSize This parameter can be one of the following values:
817 * @arg @ref LL_I2C_OWNADDRESS1_7BIT
818 * @arg @ref LL_I2C_OWNADDRESS1_10BIT
819 * @retval None
820 */
LL_I2C_SetOwnAddress1(I2C_TypeDef * I2Cx,uint32_t OwnAddress1,uint32_t OwnAddrSize)821 __STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
822 {
823 MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize);
824 }
825
826 /**
827 * @brief Enable acknowledge on Own Address1 match address.
828 * @rmtoll OAR1 OA1EN LL_I2C_EnableOwnAddress1
829 * @param I2Cx I2C Instance.
830 * @retval None
831 */
LL_I2C_EnableOwnAddress1(I2C_TypeDef * I2Cx)832 __STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx)
833 {
834 SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
835 }
836
837 /**
838 * @brief Disable acknowledge on Own Address1 match address.
839 * @rmtoll OAR1 OA1EN LL_I2C_DisableOwnAddress1
840 * @param I2Cx I2C Instance.
841 * @retval None
842 */
LL_I2C_DisableOwnAddress1(I2C_TypeDef * I2Cx)843 __STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
844 {
845 CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
846 }
847
848 /**
849 * @brief Check if Own Address1 acknowledge is enabled or disabled.
850 * @rmtoll OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1
851 * @param I2Cx I2C Instance.
852 * @retval State of bit (1 or 0).
853 */
LL_I2C_IsEnabledOwnAddress1(const I2C_TypeDef * I2Cx)854 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(const I2C_TypeDef *I2Cx)
855 {
856 return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL);
857 }
858
859 /**
860 * @brief Set the 7bits Own Address2.
861 * @note This action has no effect if own address2 is enabled.
862 * @rmtoll OAR2 OA2 LL_I2C_SetOwnAddress2\n
863 * OAR2 OA2MSK LL_I2C_SetOwnAddress2
864 * @param I2Cx I2C Instance.
865 * @param OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
866 * @param OwnAddrMask This parameter can be one of the following values:
867 * @arg @ref LL_I2C_OWNADDRESS2_NOMASK
868 * @arg @ref LL_I2C_OWNADDRESS2_MASK01
869 * @arg @ref LL_I2C_OWNADDRESS2_MASK02
870 * @arg @ref LL_I2C_OWNADDRESS2_MASK03
871 * @arg @ref LL_I2C_OWNADDRESS2_MASK04
872 * @arg @ref LL_I2C_OWNADDRESS2_MASK05
873 * @arg @ref LL_I2C_OWNADDRESS2_MASK06
874 * @arg @ref LL_I2C_OWNADDRESS2_MASK07
875 * @retval None
876 */
LL_I2C_SetOwnAddress2(I2C_TypeDef * I2Cx,uint32_t OwnAddress2,uint32_t OwnAddrMask)877 __STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
878 {
879 MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask);
880 }
881
882 /**
883 * @brief Enable acknowledge on Own Address2 match address.
884 * @rmtoll OAR2 OA2EN LL_I2C_EnableOwnAddress2
885 * @param I2Cx I2C Instance.
886 * @retval None
887 */
LL_I2C_EnableOwnAddress2(I2C_TypeDef * I2Cx)888 __STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
889 {
890 SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
891 }
892
893 /**
894 * @brief Disable acknowledge on Own Address2 match address.
895 * @rmtoll OAR2 OA2EN LL_I2C_DisableOwnAddress2
896 * @param I2Cx I2C Instance.
897 * @retval None
898 */
LL_I2C_DisableOwnAddress2(I2C_TypeDef * I2Cx)899 __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
900 {
901 CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
902 }
903
904 /**
905 * @brief Check if Own Address1 acknowledge is enabled or disabled.
906 * @rmtoll OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2
907 * @param I2Cx I2C Instance.
908 * @retval State of bit (1 or 0).
909 */
LL_I2C_IsEnabledOwnAddress2(const I2C_TypeDef * I2Cx)910 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(const I2C_TypeDef *I2Cx)
911 {
912 return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL);
913 }
914
915 /**
916 * @brief Configure the SDA setup, hold time and the SCL high, low period.
917 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
918 * @rmtoll TIMINGR TIMINGR LL_I2C_SetTiming
919 * @param I2Cx I2C Instance.
920 * @param Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
921 * @note This parameter is computed with the STM32CubeMX Tool.
922 * @retval None
923 */
LL_I2C_SetTiming(I2C_TypeDef * I2Cx,uint32_t Timing)924 __STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
925 {
926 WRITE_REG(I2Cx->TIMINGR, Timing);
927 }
928
929 /**
930 * @brief Get the Timing Prescaler setting.
931 * @rmtoll TIMINGR PRESC LL_I2C_GetTimingPrescaler
932 * @param I2Cx I2C Instance.
933 * @retval Value between Min_Data=0x0 and Max_Data=0xF
934 */
LL_I2C_GetTimingPrescaler(const I2C_TypeDef * I2Cx)935 __STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(const I2C_TypeDef *I2Cx)
936 {
937 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
938 }
939
940 /**
941 * @brief Get the SCL low period setting.
942 * @rmtoll TIMINGR SCLL LL_I2C_GetClockLowPeriod
943 * @param I2Cx I2C Instance.
944 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
945 */
LL_I2C_GetClockLowPeriod(const I2C_TypeDef * I2Cx)946 __STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(const I2C_TypeDef *I2Cx)
947 {
948 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
949 }
950
951 /**
952 * @brief Get the SCL high period setting.
953 * @rmtoll TIMINGR SCLH LL_I2C_GetClockHighPeriod
954 * @param I2Cx I2C Instance.
955 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
956 */
LL_I2C_GetClockHighPeriod(const I2C_TypeDef * I2Cx)957 __STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(const I2C_TypeDef *I2Cx)
958 {
959 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
960 }
961
962 /**
963 * @brief Get the SDA hold time.
964 * @rmtoll TIMINGR SDADEL LL_I2C_GetDataHoldTime
965 * @param I2Cx I2C Instance.
966 * @retval Value between Min_Data=0x0 and Max_Data=0xF
967 */
LL_I2C_GetDataHoldTime(const I2C_TypeDef * I2Cx)968 __STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(const I2C_TypeDef *I2Cx)
969 {
970 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
971 }
972
973 /**
974 * @brief Get the SDA setup time.
975 * @rmtoll TIMINGR SCLDEL LL_I2C_GetDataSetupTime
976 * @param I2Cx I2C Instance.
977 * @retval Value between Min_Data=0x0 and Max_Data=0xF
978 */
LL_I2C_GetDataSetupTime(const I2C_TypeDef * I2Cx)979 __STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(const I2C_TypeDef *I2Cx)
980 {
981 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
982 }
983
984 /**
985 * @brief Configure peripheral mode.
986 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
987 * SMBus feature is supported by the I2Cx Instance.
988 * @rmtoll CR1 SMBHEN LL_I2C_SetMode\n
989 * CR1 SMBDEN LL_I2C_SetMode
990 * @param I2Cx I2C Instance.
991 * @param PeripheralMode This parameter can be one of the following values:
992 * @arg @ref LL_I2C_MODE_I2C
993 * @arg @ref LL_I2C_MODE_SMBUS_HOST
994 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
995 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
996 * @retval None
997 */
LL_I2C_SetMode(I2C_TypeDef * I2Cx,uint32_t PeripheralMode)998 __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
999 {
1000 MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode);
1001 }
1002
1003 /**
1004 * @brief Get peripheral mode.
1005 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1006 * SMBus feature is supported by the I2Cx Instance.
1007 * @rmtoll CR1 SMBHEN LL_I2C_GetMode\n
1008 * CR1 SMBDEN LL_I2C_GetMode
1009 * @param I2Cx I2C Instance.
1010 * @retval Returned value can be one of the following values:
1011 * @arg @ref LL_I2C_MODE_I2C
1012 * @arg @ref LL_I2C_MODE_SMBUS_HOST
1013 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
1014 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
1015 */
LL_I2C_GetMode(const I2C_TypeDef * I2Cx)1016 __STATIC_INLINE uint32_t LL_I2C_GetMode(const I2C_TypeDef *I2Cx)
1017 {
1018 return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN));
1019 }
1020
1021 /**
1022 * @brief Enable SMBus alert (Host or Device mode)
1023 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1024 * SMBus feature is supported by the I2Cx Instance.
1025 * @note SMBus Device mode:
1026 * - SMBus Alert pin is drived low and
1027 * Alert Response Address Header acknowledge is enabled.
1028 * SMBus Host mode:
1029 * - SMBus Alert pin management is supported.
1030 * @rmtoll CR1 ALERTEN LL_I2C_EnableSMBusAlert
1031 * @param I2Cx I2C Instance.
1032 * @retval None
1033 */
LL_I2C_EnableSMBusAlert(I2C_TypeDef * I2Cx)1034 __STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
1035 {
1036 SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
1037 }
1038
1039 /**
1040 * @brief Disable SMBus alert (Host or Device mode)
1041 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1042 * SMBus feature is supported by the I2Cx Instance.
1043 * @note SMBus Device mode:
1044 * - SMBus Alert pin is not drived (can be used as a standard GPIO) and
1045 * Alert Response Address Header acknowledge is disabled.
1046 * SMBus Host mode:
1047 * - SMBus Alert pin management is not supported.
1048 * @rmtoll CR1 ALERTEN LL_I2C_DisableSMBusAlert
1049 * @param I2Cx I2C Instance.
1050 * @retval None
1051 */
LL_I2C_DisableSMBusAlert(I2C_TypeDef * I2Cx)1052 __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
1053 {
1054 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
1055 }
1056
1057 /**
1058 * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
1059 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1060 * SMBus feature is supported by the I2Cx Instance.
1061 * @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert
1062 * @param I2Cx I2C Instance.
1063 * @retval State of bit (1 or 0).
1064 */
LL_I2C_IsEnabledSMBusAlert(const I2C_TypeDef * I2Cx)1065 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(const I2C_TypeDef *I2Cx)
1066 {
1067 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL);
1068 }
1069
1070 /**
1071 * @brief Enable SMBus Packet Error Calculation (PEC).
1072 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1073 * SMBus feature is supported by the I2Cx Instance.
1074 * @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC
1075 * @param I2Cx I2C Instance.
1076 * @retval None
1077 */
LL_I2C_EnableSMBusPEC(I2C_TypeDef * I2Cx)1078 __STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
1079 {
1080 SET_BIT(I2Cx->CR1, I2C_CR1_PECEN);
1081 }
1082
1083 /**
1084 * @brief Disable SMBus Packet Error Calculation (PEC).
1085 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1086 * SMBus feature is supported by the I2Cx Instance.
1087 * @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC
1088 * @param I2Cx I2C Instance.
1089 * @retval None
1090 */
LL_I2C_DisableSMBusPEC(I2C_TypeDef * I2Cx)1091 __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
1092 {
1093 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN);
1094 }
1095
1096 /**
1097 * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
1098 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1099 * SMBus feature is supported by the I2Cx Instance.
1100 * @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC
1101 * @param I2Cx I2C Instance.
1102 * @retval State of bit (1 or 0).
1103 */
LL_I2C_IsEnabledSMBusPEC(const I2C_TypeDef * I2Cx)1104 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(const I2C_TypeDef *I2Cx)
1105 {
1106 return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL);
1107 }
1108
1109 /**
1110 * @brief Configure the SMBus Clock Timeout.
1111 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1112 * SMBus feature is supported by the I2Cx Instance.
1113 * @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
1114 * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n
1115 * TIMEOUTR TIDLE LL_I2C_ConfigSMBusTimeout\n
1116 * TIMEOUTR TIMEOUTB LL_I2C_ConfigSMBusTimeout
1117 * @param I2Cx I2C Instance.
1118 * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
1119 * @param TimeoutAMode This parameter can be one of the following values:
1120 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
1121 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
1122 * @param TimeoutB
1123 * @retval None
1124 */
LL_I2C_ConfigSMBusTimeout(I2C_TypeDef * I2Cx,uint32_t TimeoutA,uint32_t TimeoutAMode,uint32_t TimeoutB)1125 __STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
1126 uint32_t TimeoutB)
1127 {
1128 MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB,
1129 TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos));
1130 }
1131
1132 /**
1133 * @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
1134 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1135 * SMBus feature is supported by the I2Cx Instance.
1136 * @note These bits can only be programmed when TimeoutA is disabled.
1137 * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA
1138 * @param I2Cx I2C Instance.
1139 * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
1140 * @retval None
1141 */
LL_I2C_SetSMBusTimeoutA(I2C_TypeDef * I2Cx,uint32_t TimeoutA)1142 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA)
1143 {
1144 WRITE_REG(I2Cx->TIMEOUTR, TimeoutA);
1145 }
1146
1147 /**
1148 * @brief Get the SMBus Clock TimeoutA setting.
1149 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1150 * SMBus feature is supported by the I2Cx Instance.
1151 * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA
1152 * @param I2Cx I2C Instance.
1153 * @retval Value between Min_Data=0 and Max_Data=0xFFF
1154 */
LL_I2C_GetSMBusTimeoutA(const I2C_TypeDef * I2Cx)1155 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(const I2C_TypeDef *I2Cx)
1156 {
1157 return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
1158 }
1159
1160 /**
1161 * @brief Set the SMBus Clock TimeoutA mode.
1162 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1163 * SMBus feature is supported by the I2Cx Instance.
1164 * @note This bit can only be programmed when TimeoutA is disabled.
1165 * @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode
1166 * @param I2Cx I2C Instance.
1167 * @param TimeoutAMode This parameter can be one of the following values:
1168 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
1169 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
1170 * @retval None
1171 */
LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef * I2Cx,uint32_t TimeoutAMode)1172 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
1173 {
1174 WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode);
1175 }
1176
1177 /**
1178 * @brief Get the SMBus Clock TimeoutA mode.
1179 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1180 * SMBus feature is supported by the I2Cx Instance.
1181 * @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode
1182 * @param I2Cx I2C Instance.
1183 * @retval Returned value can be one of the following values:
1184 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
1185 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
1186 */
LL_I2C_GetSMBusTimeoutAMode(const I2C_TypeDef * I2Cx)1187 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(const I2C_TypeDef *I2Cx)
1188 {
1189 return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
1190 }
1191
1192 /**
1193 * @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
1194 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1195 * SMBus feature is supported by the I2Cx Instance.
1196 * @note These bits can only be programmed when TimeoutB is disabled.
1197 * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB
1198 * @param I2Cx I2C Instance.
1199 * @param TimeoutB This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
1200 * @retval None
1201 */
LL_I2C_SetSMBusTimeoutB(I2C_TypeDef * I2Cx,uint32_t TimeoutB)1202 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB)
1203 {
1204 WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos);
1205 }
1206
1207 /**
1208 * @brief Get the SMBus Extended Cumulative Clock TimeoutB setting.
1209 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1210 * SMBus feature is supported by the I2Cx Instance.
1211 * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB
1212 * @param I2Cx I2C Instance.
1213 * @retval Value between Min_Data=0 and Max_Data=0xFFF
1214 */
LL_I2C_GetSMBusTimeoutB(const I2C_TypeDef * I2Cx)1215 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(const I2C_TypeDef *I2Cx)
1216 {
1217 return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
1218 }
1219
1220 /**
1221 * @brief Enable the SMBus Clock Timeout.
1222 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1223 * SMBus feature is supported by the I2Cx Instance.
1224 * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n
1225 * TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout
1226 * @param I2Cx I2C Instance.
1227 * @param ClockTimeout This parameter can be one of the following values:
1228 * @arg @ref LL_I2C_SMBUS_TIMEOUTA
1229 * @arg @ref LL_I2C_SMBUS_TIMEOUTB
1230 * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
1231 * @retval None
1232 */
LL_I2C_EnableSMBusTimeout(I2C_TypeDef * I2Cx,uint32_t ClockTimeout)1233 __STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
1234 {
1235 SET_BIT(I2Cx->TIMEOUTR, ClockTimeout);
1236 }
1237
1238 /**
1239 * @brief Disable the SMBus Clock Timeout.
1240 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1241 * SMBus feature is supported by the I2Cx Instance.
1242 * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n
1243 * TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout
1244 * @param I2Cx I2C Instance.
1245 * @param ClockTimeout This parameter can be one of the following values:
1246 * @arg @ref LL_I2C_SMBUS_TIMEOUTA
1247 * @arg @ref LL_I2C_SMBUS_TIMEOUTB
1248 * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
1249 * @retval None
1250 */
LL_I2C_DisableSMBusTimeout(I2C_TypeDef * I2Cx,uint32_t ClockTimeout)1251 __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
1252 {
1253 CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout);
1254 }
1255
1256 /**
1257 * @brief Check if the SMBus Clock Timeout is enabled or disabled.
1258 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1259 * SMBus feature is supported by the I2Cx Instance.
1260 * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n
1261 * TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout
1262 * @param I2Cx I2C Instance.
1263 * @param ClockTimeout This parameter can be one of the following values:
1264 * @arg @ref LL_I2C_SMBUS_TIMEOUTA
1265 * @arg @ref LL_I2C_SMBUS_TIMEOUTB
1266 * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
1267 * @retval State of bit (1 or 0).
1268 */
LL_I2C_IsEnabledSMBusTimeout(const I2C_TypeDef * I2Cx,uint32_t ClockTimeout)1269 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(const I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
1270 {
1271 return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \
1272 (ClockTimeout)) ? 1UL : 0UL);
1273 }
1274
1275 /**
1276 * @}
1277 */
1278
1279 /** @defgroup I2C_LL_EF_IT_Management IT_Management
1280 * @{
1281 */
1282
1283 /**
1284 * @brief Enable TXIS interrupt.
1285 * @rmtoll CR1 TXIE LL_I2C_EnableIT_TX
1286 * @param I2Cx I2C Instance.
1287 * @retval None
1288 */
LL_I2C_EnableIT_TX(I2C_TypeDef * I2Cx)1289 __STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
1290 {
1291 SET_BIT(I2Cx->CR1, I2C_CR1_TXIE);
1292 }
1293
1294 /**
1295 * @brief Disable TXIS interrupt.
1296 * @rmtoll CR1 TXIE LL_I2C_DisableIT_TX
1297 * @param I2Cx I2C Instance.
1298 * @retval None
1299 */
LL_I2C_DisableIT_TX(I2C_TypeDef * I2Cx)1300 __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
1301 {
1302 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE);
1303 }
1304
1305 /**
1306 * @brief Check if the TXIS Interrupt is enabled or disabled.
1307 * @rmtoll CR1 TXIE LL_I2C_IsEnabledIT_TX
1308 * @param I2Cx I2C Instance.
1309 * @retval State of bit (1 or 0).
1310 */
LL_I2C_IsEnabledIT_TX(const I2C_TypeDef * I2Cx)1311 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(const I2C_TypeDef *I2Cx)
1312 {
1313 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL);
1314 }
1315
1316 /**
1317 * @brief Enable RXNE interrupt.
1318 * @rmtoll CR1 RXIE LL_I2C_EnableIT_RX
1319 * @param I2Cx I2C Instance.
1320 * @retval None
1321 */
LL_I2C_EnableIT_RX(I2C_TypeDef * I2Cx)1322 __STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
1323 {
1324 SET_BIT(I2Cx->CR1, I2C_CR1_RXIE);
1325 }
1326
1327 /**
1328 * @brief Disable RXNE interrupt.
1329 * @rmtoll CR1 RXIE LL_I2C_DisableIT_RX
1330 * @param I2Cx I2C Instance.
1331 * @retval None
1332 */
LL_I2C_DisableIT_RX(I2C_TypeDef * I2Cx)1333 __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
1334 {
1335 CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE);
1336 }
1337
1338 /**
1339 * @brief Check if the RXNE Interrupt is enabled or disabled.
1340 * @rmtoll CR1 RXIE LL_I2C_IsEnabledIT_RX
1341 * @param I2Cx I2C Instance.
1342 * @retval State of bit (1 or 0).
1343 */
LL_I2C_IsEnabledIT_RX(const I2C_TypeDef * I2Cx)1344 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(const I2C_TypeDef *I2Cx)
1345 {
1346 return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL);
1347 }
1348
1349 /**
1350 * @brief Enable Address match interrupt (slave mode only).
1351 * @rmtoll CR1 ADDRIE LL_I2C_EnableIT_ADDR
1352 * @param I2Cx I2C Instance.
1353 * @retval None
1354 */
LL_I2C_EnableIT_ADDR(I2C_TypeDef * I2Cx)1355 __STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx)
1356 {
1357 SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
1358 }
1359
1360 /**
1361 * @brief Disable Address match interrupt (slave mode only).
1362 * @rmtoll CR1 ADDRIE LL_I2C_DisableIT_ADDR
1363 * @param I2Cx I2C Instance.
1364 * @retval None
1365 */
LL_I2C_DisableIT_ADDR(I2C_TypeDef * I2Cx)1366 __STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
1367 {
1368 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
1369 }
1370
1371 /**
1372 * @brief Check if Address match interrupt is enabled or disabled.
1373 * @rmtoll CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR
1374 * @param I2Cx I2C Instance.
1375 * @retval State of bit (1 or 0).
1376 */
LL_I2C_IsEnabledIT_ADDR(const I2C_TypeDef * I2Cx)1377 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(const I2C_TypeDef *I2Cx)
1378 {
1379 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL);
1380 }
1381
1382 /**
1383 * @brief Enable Not acknowledge received interrupt.
1384 * @rmtoll CR1 NACKIE LL_I2C_EnableIT_NACK
1385 * @param I2Cx I2C Instance.
1386 * @retval None
1387 */
LL_I2C_EnableIT_NACK(I2C_TypeDef * I2Cx)1388 __STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx)
1389 {
1390 SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
1391 }
1392
1393 /**
1394 * @brief Disable Not acknowledge received interrupt.
1395 * @rmtoll CR1 NACKIE LL_I2C_DisableIT_NACK
1396 * @param I2Cx I2C Instance.
1397 * @retval None
1398 */
LL_I2C_DisableIT_NACK(I2C_TypeDef * I2Cx)1399 __STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
1400 {
1401 CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
1402 }
1403
1404 /**
1405 * @brief Check if Not acknowledge received interrupt is enabled or disabled.
1406 * @rmtoll CR1 NACKIE LL_I2C_IsEnabledIT_NACK
1407 * @param I2Cx I2C Instance.
1408 * @retval State of bit (1 or 0).
1409 */
LL_I2C_IsEnabledIT_NACK(const I2C_TypeDef * I2Cx)1410 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(const I2C_TypeDef *I2Cx)
1411 {
1412 return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL);
1413 }
1414
1415 /**
1416 * @brief Enable STOP detection interrupt.
1417 * @rmtoll CR1 STOPIE LL_I2C_EnableIT_STOP
1418 * @param I2Cx I2C Instance.
1419 * @retval None
1420 */
LL_I2C_EnableIT_STOP(I2C_TypeDef * I2Cx)1421 __STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx)
1422 {
1423 SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
1424 }
1425
1426 /**
1427 * @brief Disable STOP detection interrupt.
1428 * @rmtoll CR1 STOPIE LL_I2C_DisableIT_STOP
1429 * @param I2Cx I2C Instance.
1430 * @retval None
1431 */
LL_I2C_DisableIT_STOP(I2C_TypeDef * I2Cx)1432 __STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
1433 {
1434 CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
1435 }
1436
1437 /**
1438 * @brief Check if STOP detection interrupt is enabled or disabled.
1439 * @rmtoll CR1 STOPIE LL_I2C_IsEnabledIT_STOP
1440 * @param I2Cx I2C Instance.
1441 * @retval State of bit (1 or 0).
1442 */
LL_I2C_IsEnabledIT_STOP(const I2C_TypeDef * I2Cx)1443 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(const I2C_TypeDef *I2Cx)
1444 {
1445 return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL);
1446 }
1447
1448 /**
1449 * @brief Enable Transfer Complete interrupt.
1450 * @note Any of these events will generate interrupt :
1451 * Transfer Complete (TC)
1452 * Transfer Complete Reload (TCR)
1453 * @rmtoll CR1 TCIE LL_I2C_EnableIT_TC
1454 * @param I2Cx I2C Instance.
1455 * @retval None
1456 */
LL_I2C_EnableIT_TC(I2C_TypeDef * I2Cx)1457 __STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx)
1458 {
1459 SET_BIT(I2Cx->CR1, I2C_CR1_TCIE);
1460 }
1461
1462 /**
1463 * @brief Disable Transfer Complete interrupt.
1464 * @note Any of these events will generate interrupt :
1465 * Transfer Complete (TC)
1466 * Transfer Complete Reload (TCR)
1467 * @rmtoll CR1 TCIE LL_I2C_DisableIT_TC
1468 * @param I2Cx I2C Instance.
1469 * @retval None
1470 */
LL_I2C_DisableIT_TC(I2C_TypeDef * I2Cx)1471 __STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
1472 {
1473 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE);
1474 }
1475
1476 /**
1477 * @brief Check if Transfer Complete interrupt is enabled or disabled.
1478 * @rmtoll CR1 TCIE LL_I2C_IsEnabledIT_TC
1479 * @param I2Cx I2C Instance.
1480 * @retval State of bit (1 or 0).
1481 */
LL_I2C_IsEnabledIT_TC(const I2C_TypeDef * I2Cx)1482 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(const I2C_TypeDef *I2Cx)
1483 {
1484 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL);
1485 }
1486
1487 /**
1488 * @brief Enable Error interrupts.
1489 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1490 * SMBus feature is supported by the I2Cx Instance.
1491 * @note Any of these errors will generate interrupt :
1492 * Arbitration Loss (ARLO)
1493 * Bus Error detection (BERR)
1494 * Overrun/Underrun (OVR)
1495 * SMBus Timeout detection (TIMEOUT)
1496 * SMBus PEC error detection (PECERR)
1497 * SMBus Alert pin event detection (ALERT)
1498 * @rmtoll CR1 ERRIE LL_I2C_EnableIT_ERR
1499 * @param I2Cx I2C Instance.
1500 * @retval None
1501 */
LL_I2C_EnableIT_ERR(I2C_TypeDef * I2Cx)1502 __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
1503 {
1504 SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
1505 }
1506
1507 /**
1508 * @brief Disable Error interrupts.
1509 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1510 * SMBus feature is supported by the I2Cx Instance.
1511 * @note Any of these errors will generate interrupt :
1512 * Arbitration Loss (ARLO)
1513 * Bus Error detection (BERR)
1514 * Overrun/Underrun (OVR)
1515 * SMBus Timeout detection (TIMEOUT)
1516 * SMBus PEC error detection (PECERR)
1517 * SMBus Alert pin event detection (ALERT)
1518 * @rmtoll CR1 ERRIE LL_I2C_DisableIT_ERR
1519 * @param I2Cx I2C Instance.
1520 * @retval None
1521 */
LL_I2C_DisableIT_ERR(I2C_TypeDef * I2Cx)1522 __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
1523 {
1524 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
1525 }
1526
1527 /**
1528 * @brief Check if Error interrupts are enabled or disabled.
1529 * @rmtoll CR1 ERRIE LL_I2C_IsEnabledIT_ERR
1530 * @param I2Cx I2C Instance.
1531 * @retval State of bit (1 or 0).
1532 */
LL_I2C_IsEnabledIT_ERR(const I2C_TypeDef * I2Cx)1533 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(const I2C_TypeDef *I2Cx)
1534 {
1535 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL);
1536 }
1537
1538 /**
1539 * @}
1540 */
1541
1542 /** @defgroup I2C_LL_EF_FLAG_management FLAG_management
1543 * @{
1544 */
1545
1546 /**
1547 * @brief Indicate the status of Transmit data register empty flag.
1548 * @note RESET: When next data is written in Transmit data register.
1549 * SET: When Transmit data register is empty.
1550 * @rmtoll ISR TXE LL_I2C_IsActiveFlag_TXE
1551 * @param I2Cx I2C Instance.
1552 * @retval State of bit (1 or 0).
1553 */
LL_I2C_IsActiveFlag_TXE(const I2C_TypeDef * I2Cx)1554 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(const I2C_TypeDef *I2Cx)
1555 {
1556 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL);
1557 }
1558
1559 /**
1560 * @brief Indicate the status of Transmit interrupt flag.
1561 * @note RESET: When next data is written in Transmit data register.
1562 * SET: When Transmit data register is empty.
1563 * @rmtoll ISR TXIS LL_I2C_IsActiveFlag_TXIS
1564 * @param I2Cx I2C Instance.
1565 * @retval State of bit (1 or 0).
1566 */
LL_I2C_IsActiveFlag_TXIS(const I2C_TypeDef * I2Cx)1567 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(const I2C_TypeDef *I2Cx)
1568 {
1569 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL);
1570 }
1571
1572 /**
1573 * @brief Indicate the status of Receive data register not empty flag.
1574 * @note RESET: When Receive data register is read.
1575 * SET: When the received data is copied in Receive data register.
1576 * @rmtoll ISR RXNE LL_I2C_IsActiveFlag_RXNE
1577 * @param I2Cx I2C Instance.
1578 * @retval State of bit (1 or 0).
1579 */
LL_I2C_IsActiveFlag_RXNE(const I2C_TypeDef * I2Cx)1580 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(const I2C_TypeDef *I2Cx)
1581 {
1582 return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL);
1583 }
1584
1585 /**
1586 * @brief Indicate the status of Address matched flag (slave mode).
1587 * @note RESET: Clear default value.
1588 * SET: When the received slave address matched with one of the enabled slave address.
1589 * @rmtoll ISR ADDR LL_I2C_IsActiveFlag_ADDR
1590 * @param I2Cx I2C Instance.
1591 * @retval State of bit (1 or 0).
1592 */
LL_I2C_IsActiveFlag_ADDR(const I2C_TypeDef * I2Cx)1593 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(const I2C_TypeDef *I2Cx)
1594 {
1595 return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL);
1596 }
1597
1598 /**
1599 * @brief Indicate the status of Not Acknowledge received flag.
1600 * @note RESET: Clear default value.
1601 * SET: When a NACK is received after a byte transmission.
1602 * @rmtoll ISR NACKF LL_I2C_IsActiveFlag_NACK
1603 * @param I2Cx I2C Instance.
1604 * @retval State of bit (1 or 0).
1605 */
LL_I2C_IsActiveFlag_NACK(const I2C_TypeDef * I2Cx)1606 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(const I2C_TypeDef *I2Cx)
1607 {
1608 return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL);
1609 }
1610
1611 /**
1612 * @brief Indicate the status of Stop detection flag.
1613 * @note RESET: Clear default value.
1614 * SET: When a Stop condition is detected.
1615 * @rmtoll ISR STOPF LL_I2C_IsActiveFlag_STOP
1616 * @param I2Cx I2C Instance.
1617 * @retval State of bit (1 or 0).
1618 */
LL_I2C_IsActiveFlag_STOP(const I2C_TypeDef * I2Cx)1619 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(const I2C_TypeDef *I2Cx)
1620 {
1621 return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL);
1622 }
1623
1624 /**
1625 * @brief Indicate the status of Transfer complete flag (master mode).
1626 * @note RESET: Clear default value.
1627 * SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
1628 * @rmtoll ISR TC LL_I2C_IsActiveFlag_TC
1629 * @param I2Cx I2C Instance.
1630 * @retval State of bit (1 or 0).
1631 */
LL_I2C_IsActiveFlag_TC(const I2C_TypeDef * I2Cx)1632 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(const I2C_TypeDef *I2Cx)
1633 {
1634 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL);
1635 }
1636
1637 /**
1638 * @brief Indicate the status of Transfer complete flag (master mode).
1639 * @note RESET: Clear default value.
1640 * SET: When RELOAD=1 and NBYTES date have been transferred.
1641 * @rmtoll ISR TCR LL_I2C_IsActiveFlag_TCR
1642 * @param I2Cx I2C Instance.
1643 * @retval State of bit (1 or 0).
1644 */
LL_I2C_IsActiveFlag_TCR(const I2C_TypeDef * I2Cx)1645 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(const I2C_TypeDef *I2Cx)
1646 {
1647 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL);
1648 }
1649
1650 /**
1651 * @brief Indicate the status of Bus error flag.
1652 * @note RESET: Clear default value.
1653 * SET: When a misplaced Start or Stop condition is detected.
1654 * @rmtoll ISR BERR LL_I2C_IsActiveFlag_BERR
1655 * @param I2Cx I2C Instance.
1656 * @retval State of bit (1 or 0).
1657 */
LL_I2C_IsActiveFlag_BERR(const I2C_TypeDef * I2Cx)1658 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(const I2C_TypeDef *I2Cx)
1659 {
1660 return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL);
1661 }
1662
1663 /**
1664 * @brief Indicate the status of Arbitration lost flag.
1665 * @note RESET: Clear default value.
1666 * SET: When arbitration lost.
1667 * @rmtoll ISR ARLO LL_I2C_IsActiveFlag_ARLO
1668 * @param I2Cx I2C Instance.
1669 * @retval State of bit (1 or 0).
1670 */
LL_I2C_IsActiveFlag_ARLO(const I2C_TypeDef * I2Cx)1671 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(const I2C_TypeDef *I2Cx)
1672 {
1673 return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL);
1674 }
1675
1676 /**
1677 * @brief Indicate the status of Overrun/Underrun flag (slave mode).
1678 * @note RESET: Clear default value.
1679 * SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
1680 * @rmtoll ISR OVR LL_I2C_IsActiveFlag_OVR
1681 * @param I2Cx I2C Instance.
1682 * @retval State of bit (1 or 0).
1683 */
LL_I2C_IsActiveFlag_OVR(const I2C_TypeDef * I2Cx)1684 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(const I2C_TypeDef *I2Cx)
1685 {
1686 return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL);
1687 }
1688
1689 /**
1690 * @brief Indicate the status of SMBus PEC error flag in reception.
1691 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1692 * SMBus feature is supported by the I2Cx Instance.
1693 * @note RESET: Clear default value.
1694 * SET: When the received PEC does not match with the PEC register content.
1695 * @rmtoll ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR
1696 * @param I2Cx I2C Instance.
1697 * @retval State of bit (1 or 0).
1698 */
LL_I2C_IsActiveSMBusFlag_PECERR(const I2C_TypeDef * I2Cx)1699 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(const I2C_TypeDef *I2Cx)
1700 {
1701 return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL);
1702 }
1703
1704 /**
1705 * @brief Indicate the status of SMBus Timeout detection flag.
1706 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1707 * SMBus feature is supported by the I2Cx Instance.
1708 * @note RESET: Clear default value.
1709 * SET: When a timeout or extended clock timeout occurs.
1710 * @rmtoll ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
1711 * @param I2Cx I2C Instance.
1712 * @retval State of bit (1 or 0).
1713 */
LL_I2C_IsActiveSMBusFlag_TIMEOUT(const I2C_TypeDef * I2Cx)1714 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(const I2C_TypeDef *I2Cx)
1715 {
1716 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL);
1717 }
1718
1719 /**
1720 * @brief Indicate the status of SMBus alert flag.
1721 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1722 * SMBus feature is supported by the I2Cx Instance.
1723 * @note RESET: Clear default value.
1724 * SET: When SMBus host configuration, SMBus alert enabled and
1725 * a falling edge event occurs on SMBA pin.
1726 * @rmtoll ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT
1727 * @param I2Cx I2C Instance.
1728 * @retval State of bit (1 or 0).
1729 */
LL_I2C_IsActiveSMBusFlag_ALERT(const I2C_TypeDef * I2Cx)1730 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(const I2C_TypeDef *I2Cx)
1731 {
1732 return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL);
1733 }
1734
1735 /**
1736 * @brief Indicate the status of Bus Busy flag.
1737 * @note RESET: Clear default value.
1738 * SET: When a Start condition is detected.
1739 * @rmtoll ISR BUSY LL_I2C_IsActiveFlag_BUSY
1740 * @param I2Cx I2C Instance.
1741 * @retval State of bit (1 or 0).
1742 */
LL_I2C_IsActiveFlag_BUSY(const I2C_TypeDef * I2Cx)1743 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(const I2C_TypeDef *I2Cx)
1744 {
1745 return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL);
1746 }
1747
1748 /**
1749 * @brief Clear Address Matched flag.
1750 * @rmtoll ICR ADDRCF LL_I2C_ClearFlag_ADDR
1751 * @param I2Cx I2C Instance.
1752 * @retval None
1753 */
LL_I2C_ClearFlag_ADDR(I2C_TypeDef * I2Cx)1754 __STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
1755 {
1756 SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF);
1757 }
1758
1759 /**
1760 * @brief Clear Not Acknowledge flag.
1761 * @rmtoll ICR NACKCF LL_I2C_ClearFlag_NACK
1762 * @param I2Cx I2C Instance.
1763 * @retval None
1764 */
LL_I2C_ClearFlag_NACK(I2C_TypeDef * I2Cx)1765 __STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx)
1766 {
1767 SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF);
1768 }
1769
1770 /**
1771 * @brief Clear Stop detection flag.
1772 * @rmtoll ICR STOPCF LL_I2C_ClearFlag_STOP
1773 * @param I2Cx I2C Instance.
1774 * @retval None
1775 */
LL_I2C_ClearFlag_STOP(I2C_TypeDef * I2Cx)1776 __STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
1777 {
1778 SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
1779 }
1780
1781 /**
1782 * @brief Clear Transmit data register empty flag (TXE).
1783 * @note This bit can be clear by software in order to flush the transmit data register (TXDR).
1784 * @rmtoll ISR TXE LL_I2C_ClearFlag_TXE
1785 * @param I2Cx I2C Instance.
1786 * @retval None
1787 */
LL_I2C_ClearFlag_TXE(I2C_TypeDef * I2Cx)1788 __STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx)
1789 {
1790 WRITE_REG(I2Cx->ISR, I2C_ISR_TXE);
1791 }
1792
1793 /**
1794 * @brief Clear Bus error flag.
1795 * @rmtoll ICR BERRCF LL_I2C_ClearFlag_BERR
1796 * @param I2Cx I2C Instance.
1797 * @retval None
1798 */
LL_I2C_ClearFlag_BERR(I2C_TypeDef * I2Cx)1799 __STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
1800 {
1801 SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF);
1802 }
1803
1804 /**
1805 * @brief Clear Arbitration lost flag.
1806 * @rmtoll ICR ARLOCF LL_I2C_ClearFlag_ARLO
1807 * @param I2Cx I2C Instance.
1808 * @retval None
1809 */
LL_I2C_ClearFlag_ARLO(I2C_TypeDef * I2Cx)1810 __STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
1811 {
1812 SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF);
1813 }
1814
1815 /**
1816 * @brief Clear Overrun/Underrun flag.
1817 * @rmtoll ICR OVRCF LL_I2C_ClearFlag_OVR
1818 * @param I2Cx I2C Instance.
1819 * @retval None
1820 */
LL_I2C_ClearFlag_OVR(I2C_TypeDef * I2Cx)1821 __STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
1822 {
1823 SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF);
1824 }
1825
1826 /**
1827 * @brief Clear SMBus PEC error flag.
1828 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1829 * SMBus feature is supported by the I2Cx Instance.
1830 * @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR
1831 * @param I2Cx I2C Instance.
1832 * @retval None
1833 */
LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef * I2Cx)1834 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
1835 {
1836 SET_BIT(I2Cx->ICR, I2C_ICR_PECCF);
1837 }
1838
1839 /**
1840 * @brief Clear SMBus Timeout detection flag.
1841 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1842 * SMBus feature is supported by the I2Cx Instance.
1843 * @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT
1844 * @param I2Cx I2C Instance.
1845 * @retval None
1846 */
LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef * I2Cx)1847 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
1848 {
1849 SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF);
1850 }
1851
1852 /**
1853 * @brief Clear SMBus Alert flag.
1854 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1855 * SMBus feature is supported by the I2Cx Instance.
1856 * @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT
1857 * @param I2Cx I2C Instance.
1858 * @retval None
1859 */
LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef * I2Cx)1860 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
1861 {
1862 SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF);
1863 }
1864
1865 /**
1866 * @}
1867 */
1868
1869 /** @defgroup I2C_LL_EF_Data_Management Data_Management
1870 * @{
1871 */
1872
1873 /**
1874 * @brief Enable automatic STOP condition generation (master mode).
1875 * @note Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
1876 * This bit has no effect in slave mode or when RELOAD bit is set.
1877 * @rmtoll CR2 AUTOEND LL_I2C_EnableAutoEndMode
1878 * @param I2Cx I2C Instance.
1879 * @retval None
1880 */
LL_I2C_EnableAutoEndMode(I2C_TypeDef * I2Cx)1881 __STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx)
1882 {
1883 SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
1884 }
1885
1886 /**
1887 * @brief Disable automatic STOP condition generation (master mode).
1888 * @note Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
1889 * @rmtoll CR2 AUTOEND LL_I2C_DisableAutoEndMode
1890 * @param I2Cx I2C Instance.
1891 * @retval None
1892 */
LL_I2C_DisableAutoEndMode(I2C_TypeDef * I2Cx)1893 __STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
1894 {
1895 CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
1896 }
1897
1898 /**
1899 * @brief Check if automatic STOP condition is enabled or disabled.
1900 * @rmtoll CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode
1901 * @param I2Cx I2C Instance.
1902 * @retval State of bit (1 or 0).
1903 */
LL_I2C_IsEnabledAutoEndMode(const I2C_TypeDef * I2Cx)1904 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(const I2C_TypeDef *I2Cx)
1905 {
1906 return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL);
1907 }
1908
1909 /**
1910 * @brief Enable reload mode (master mode).
1911 * @note The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
1912 * @rmtoll CR2 RELOAD LL_I2C_EnableReloadMode
1913 * @param I2Cx I2C Instance.
1914 * @retval None
1915 */
LL_I2C_EnableReloadMode(I2C_TypeDef * I2Cx)1916 __STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx)
1917 {
1918 SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
1919 }
1920
1921 /**
1922 * @brief Disable reload mode (master mode).
1923 * @note The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
1924 * @rmtoll CR2 RELOAD LL_I2C_DisableReloadMode
1925 * @param I2Cx I2C Instance.
1926 * @retval None
1927 */
LL_I2C_DisableReloadMode(I2C_TypeDef * I2Cx)1928 __STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
1929 {
1930 CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
1931 }
1932
1933 /**
1934 * @brief Check if reload mode is enabled or disabled.
1935 * @rmtoll CR2 RELOAD LL_I2C_IsEnabledReloadMode
1936 * @param I2Cx I2C Instance.
1937 * @retval State of bit (1 or 0).
1938 */
LL_I2C_IsEnabledReloadMode(const I2C_TypeDef * I2Cx)1939 __STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(const I2C_TypeDef *I2Cx)
1940 {
1941 return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL);
1942 }
1943
1944 /**
1945 * @brief Configure the number of bytes for transfer.
1946 * @note Changing these bits when START bit is set is not allowed.
1947 * @rmtoll CR2 NBYTES LL_I2C_SetTransferSize
1948 * @param I2Cx I2C Instance.
1949 * @param TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
1950 * @retval None
1951 */
LL_I2C_SetTransferSize(I2C_TypeDef * I2Cx,uint32_t TransferSize)1952 __STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)
1953 {
1954 MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos);
1955 }
1956
1957 /**
1958 * @brief Get the number of bytes configured for transfer.
1959 * @rmtoll CR2 NBYTES LL_I2C_GetTransferSize
1960 * @param I2Cx I2C Instance.
1961 * @retval Value between Min_Data=0x0 and Max_Data=0xFF
1962 */
LL_I2C_GetTransferSize(const I2C_TypeDef * I2Cx)1963 __STATIC_INLINE uint32_t LL_I2C_GetTransferSize(const I2C_TypeDef *I2Cx)
1964 {
1965 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
1966 }
1967
1968 /**
1969 * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code
1970 or next received byte.
1971 * @note Usage in Slave mode only.
1972 * @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData
1973 * @param I2Cx I2C Instance.
1974 * @param TypeAcknowledge This parameter can be one of the following values:
1975 * @arg @ref LL_I2C_ACK
1976 * @arg @ref LL_I2C_NACK
1977 * @retval None
1978 */
LL_I2C_AcknowledgeNextData(I2C_TypeDef * I2Cx,uint32_t TypeAcknowledge)1979 __STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
1980 {
1981 MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
1982 }
1983
1984 /**
1985 * @brief Generate a START or RESTART condition
1986 * @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
1987 * This action has no effect when RELOAD is set.
1988 * @rmtoll CR2 START LL_I2C_GenerateStartCondition
1989 * @param I2Cx I2C Instance.
1990 * @retval None
1991 */
LL_I2C_GenerateStartCondition(I2C_TypeDef * I2Cx)1992 __STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
1993 {
1994 SET_BIT(I2Cx->CR2, I2C_CR2_START);
1995 }
1996
1997 /**
1998 * @brief Generate a STOP condition after the current byte transfer (master mode).
1999 * @rmtoll CR2 STOP LL_I2C_GenerateStopCondition
2000 * @param I2Cx I2C Instance.
2001 * @retval None
2002 */
LL_I2C_GenerateStopCondition(I2C_TypeDef * I2Cx)2003 __STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
2004 {
2005 SET_BIT(I2Cx->CR2, I2C_CR2_STOP);
2006 }
2007
2008 /**
2009 * @brief Enable automatic RESTART Read request condition for 10bit address header (master mode).
2010 * @note The master sends the complete 10bit slave address read sequence :
2011 * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address
2012 in Read direction.
2013 * @rmtoll CR2 HEAD10R LL_I2C_EnableAuto10BitRead
2014 * @param I2Cx I2C Instance.
2015 * @retval None
2016 */
LL_I2C_EnableAuto10BitRead(I2C_TypeDef * I2Cx)2017 __STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx)
2018 {
2019 CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
2020 }
2021
2022 /**
2023 * @brief Disable automatic RESTART Read request condition for 10bit address header (master mode).
2024 * @note The master only sends the first 7 bits of 10bit address in Read direction.
2025 * @rmtoll CR2 HEAD10R LL_I2C_DisableAuto10BitRead
2026 * @param I2Cx I2C Instance.
2027 * @retval None
2028 */
LL_I2C_DisableAuto10BitRead(I2C_TypeDef * I2Cx)2029 __STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
2030 {
2031 SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
2032 }
2033
2034 /**
2035 * @brief Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
2036 * @rmtoll CR2 HEAD10R LL_I2C_IsEnabledAuto10BitRead
2037 * @param I2Cx I2C Instance.
2038 * @retval State of bit (1 or 0).
2039 */
LL_I2C_IsEnabledAuto10BitRead(const I2C_TypeDef * I2Cx)2040 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(const I2C_TypeDef *I2Cx)
2041 {
2042 return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL);
2043 }
2044
2045 /**
2046 * @brief Configure the transfer direction (master mode).
2047 * @note Changing these bits when START bit is set is not allowed.
2048 * @rmtoll CR2 RD_WRN LL_I2C_SetTransferRequest
2049 * @param I2Cx I2C Instance.
2050 * @param TransferRequest This parameter can be one of the following values:
2051 * @arg @ref LL_I2C_REQUEST_WRITE
2052 * @arg @ref LL_I2C_REQUEST_READ
2053 * @retval None
2054 */
LL_I2C_SetTransferRequest(I2C_TypeDef * I2Cx,uint32_t TransferRequest)2055 __STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest)
2056 {
2057 MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest);
2058 }
2059
2060 /**
2061 * @brief Get the transfer direction requested (master mode).
2062 * @rmtoll CR2 RD_WRN LL_I2C_GetTransferRequest
2063 * @param I2Cx I2C Instance.
2064 * @retval Returned value can be one of the following values:
2065 * @arg @ref LL_I2C_REQUEST_WRITE
2066 * @arg @ref LL_I2C_REQUEST_READ
2067 */
LL_I2C_GetTransferRequest(const I2C_TypeDef * I2Cx)2068 __STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(const I2C_TypeDef *I2Cx)
2069 {
2070 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
2071 }
2072
2073 /**
2074 * @brief Configure the slave address for transfer (master mode).
2075 * @note Changing these bits when START bit is set is not allowed.
2076 * @rmtoll CR2 SADD LL_I2C_SetSlaveAddr
2077 * @param I2Cx I2C Instance.
2078 * @param SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
2079 * @retval None
2080 */
LL_I2C_SetSlaveAddr(I2C_TypeDef * I2Cx,uint32_t SlaveAddr)2081 __STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
2082 {
2083 MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr);
2084 }
2085
2086 /**
2087 * @brief Get the slave address programmed for transfer.
2088 * @rmtoll CR2 SADD LL_I2C_GetSlaveAddr
2089 * @param I2Cx I2C Instance.
2090 * @retval Value between Min_Data=0x0 and Max_Data=0x3F
2091 */
LL_I2C_GetSlaveAddr(const I2C_TypeDef * I2Cx)2092 __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(const I2C_TypeDef *I2Cx)
2093 {
2094 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
2095 }
2096
2097 /**
2098 * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
2099 * @rmtoll CR2 SADD LL_I2C_HandleTransfer\n
2100 * CR2 ADD10 LL_I2C_HandleTransfer\n
2101 * CR2 RD_WRN LL_I2C_HandleTransfer\n
2102 * CR2 START LL_I2C_HandleTransfer\n
2103 * CR2 STOP LL_I2C_HandleTransfer\n
2104 * CR2 RELOAD LL_I2C_HandleTransfer\n
2105 * CR2 NBYTES LL_I2C_HandleTransfer\n
2106 * CR2 AUTOEND LL_I2C_HandleTransfer\n
2107 * CR2 HEAD10R LL_I2C_HandleTransfer
2108 * @param I2Cx I2C Instance.
2109 * @param SlaveAddr Specifies the slave address to be programmed.
2110 * @param SlaveAddrSize This parameter can be one of the following values:
2111 * @arg @ref LL_I2C_ADDRSLAVE_7BIT
2112 * @arg @ref LL_I2C_ADDRSLAVE_10BIT
2113 * @param TransferSize Specifies the number of bytes to be programmed.
2114 * This parameter must be a value between Min_Data=0 and Max_Data=255.
2115 * @param EndMode This parameter can be one of the following values:
2116 * @arg @ref LL_I2C_MODE_RELOAD
2117 * @arg @ref LL_I2C_MODE_AUTOEND
2118 * @arg @ref LL_I2C_MODE_SOFTEND
2119 * @arg @ref LL_I2C_MODE_SMBUS_RELOAD
2120 * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
2121 * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
2122 * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
2123 * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
2124 * @param Request This parameter can be one of the following values:
2125 * @arg @ref LL_I2C_GENERATE_NOSTARTSTOP
2126 * @arg @ref LL_I2C_GENERATE_STOP
2127 * @arg @ref LL_I2C_GENERATE_START_READ
2128 * @arg @ref LL_I2C_GENERATE_START_WRITE
2129 * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ
2130 * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE
2131 * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ
2132 * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE
2133 * @retval None
2134 */
LL_I2C_HandleTransfer(I2C_TypeDef * I2Cx,uint32_t SlaveAddr,uint32_t SlaveAddrSize,uint32_t TransferSize,uint32_t EndMode,uint32_t Request)2135 __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
2136 uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
2137 {
2138 MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 |
2139 (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) |
2140 I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
2141 I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
2142 SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request);
2143 }
2144
2145 /**
2146 * @brief Indicate the value of transfer direction (slave mode).
2147 * @note RESET: Write transfer, Slave enters in receiver mode.
2148 * SET: Read transfer, Slave enters in transmitter mode.
2149 * @rmtoll ISR DIR LL_I2C_GetTransferDirection
2150 * @param I2Cx I2C Instance.
2151 * @retval Returned value can be one of the following values:
2152 * @arg @ref LL_I2C_DIRECTION_WRITE
2153 * @arg @ref LL_I2C_DIRECTION_READ
2154 */
LL_I2C_GetTransferDirection(const I2C_TypeDef * I2Cx)2155 __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(const I2C_TypeDef *I2Cx)
2156 {
2157 return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
2158 }
2159
2160 /**
2161 * @brief Return the slave matched address.
2162 * @rmtoll ISR ADDCODE LL_I2C_GetAddressMatchCode
2163 * @param I2Cx I2C Instance.
2164 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
2165 */
LL_I2C_GetAddressMatchCode(const I2C_TypeDef * I2Cx)2166 __STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(const I2C_TypeDef *I2Cx)
2167 {
2168 return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
2169 }
2170
2171 /**
2172 * @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
2173 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
2174 * SMBus feature is supported by the I2Cx Instance.
2175 * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition
2176 or an Address Matched is received.
2177 * This bit has no effect when RELOAD bit is set.
2178 * This bit has no effect in device mode when SBC bit is not set.
2179 * @rmtoll CR2 PECBYTE LL_I2C_EnableSMBusPECCompare
2180 * @param I2Cx I2C Instance.
2181 * @retval None
2182 */
LL_I2C_EnableSMBusPECCompare(I2C_TypeDef * I2Cx)2183 __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
2184 {
2185 SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE);
2186 }
2187
2188 /**
2189 * @brief Check if the SMBus Packet Error byte internal comparison is requested or not.
2190 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
2191 * SMBus feature is supported by the I2Cx Instance.
2192 * @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare
2193 * @param I2Cx I2C Instance.
2194 * @retval State of bit (1 or 0).
2195 */
LL_I2C_IsEnabledSMBusPECCompare(const I2C_TypeDef * I2Cx)2196 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(const I2C_TypeDef *I2Cx)
2197 {
2198 return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL);
2199 }
2200
2201 /**
2202 * @brief Get the SMBus Packet Error byte calculated.
2203 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
2204 * SMBus feature is supported by the I2Cx Instance.
2205 * @rmtoll PECR PEC LL_I2C_GetSMBusPEC
2206 * @param I2Cx I2C Instance.
2207 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
2208 */
LL_I2C_GetSMBusPEC(const I2C_TypeDef * I2Cx)2209 __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(const I2C_TypeDef *I2Cx)
2210 {
2211 return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
2212 }
2213
2214 /**
2215 * @brief Read Receive Data register.
2216 * @rmtoll RXDR RXDATA LL_I2C_ReceiveData8
2217 * @param I2Cx I2C Instance.
2218 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
2219 */
LL_I2C_ReceiveData8(const I2C_TypeDef * I2Cx)2220 __STATIC_INLINE uint8_t LL_I2C_ReceiveData8(const I2C_TypeDef *I2Cx)
2221 {
2222 return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
2223 }
2224
2225 /**
2226 * @brief Write in Transmit Data Register .
2227 * @rmtoll TXDR TXDATA LL_I2C_TransmitData8
2228 * @param I2Cx I2C Instance.
2229 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
2230 * @retval None
2231 */
LL_I2C_TransmitData8(I2C_TypeDef * I2Cx,uint8_t Data)2232 __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
2233 {
2234 WRITE_REG(I2Cx->TXDR, Data);
2235 }
2236
2237 /**
2238 * @}
2239 */
2240
2241 #if defined(USE_FULL_LL_DRIVER)
2242 /** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
2243 * @{
2244 */
2245
2246 ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct);
2247 ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx);
2248 void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
2249
2250
2251 /**
2252 * @}
2253 */
2254 #endif /* USE_FULL_LL_DRIVER */
2255
2256 /**
2257 * @}
2258 */
2259
2260 /**
2261 * @}
2262 */
2263
2264 #endif /* I2C1 || I2C2 */
2265
2266 /**
2267 * @}
2268 */
2269
2270 #ifdef __cplusplus
2271 }
2272 #endif
2273
2274 #endif /* STM32F0xx_LL_I2C_H */
2275
