1 /**
2 ******************************************************************************
3 * @file stm32c0xx_ll_pwr.h
4 * @author MCD Application Team
5 * @brief Header file of PWR LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32C0xx_LL_PWR_H
21 #define STM32C0xx_LL_PWR_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32c0xx.h"
29
30 /** @addtogroup STM32C0xx_LL_Driver
31 * @{
32 */
33
34 #if defined(PWR)
35
36 /** @defgroup PWR_LL PWR
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44
45 /* Private macros ------------------------------------------------------------*/
46
47 /* Exported types ------------------------------------------------------------*/
48 /* Exported constants --------------------------------------------------------*/
49 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
50 * @{
51 */
52
53 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
54 * @brief Flags defines which can be used with LL_PWR_WriteReg function
55 * @{
56 */
57 #define LL_PWR_SCR_CSBF PWR_SCR_CSBF
58 #define LL_PWR_SCR_CWUF PWR_SCR_CWUF
59 #define LL_PWR_SCR_CWUF6 PWR_SCR_CWUF6
60 #if defined(PWR_SCR_CWUF5)
61 #define LL_PWR_SCR_CWUF5 PWR_SCR_CWUF5
62 #endif /* PWR_SCR_CWUF5 */
63 #define LL_PWR_SCR_CWUF4 PWR_SCR_CWUF4
64 #define LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3
65 #define LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2
66 #define LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1
67 /**
68 * @}
69 */
70
71 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
72 * @brief Flags defines which can be used with LL_PWR_ReadReg function
73 * @{
74 */
75 #define LL_PWR_SR1_WUFI PWR_SR1_WUFI
76 #define LL_PWR_SR1_SBF PWR_SR1_SBF
77 #define LL_PWR_SR1_WUF6 PWR_SR1_WUF6
78 #if defined(PWR_SR1_WUF5)
79 #define LL_PWR_SR1_WUF5 PWR_SR1_WUF5
80 #endif /* PWR_SR1_WUF5 */
81 #define LL_PWR_SR1_WUF4 PWR_SR1_WUF4
82 #define LL_PWR_SR1_WUF3 PWR_SR1_WUF3
83 #define LL_PWR_SR1_WUF2 PWR_SR1_WUF2
84 #define LL_PWR_SR1_WUF1 PWR_SR1_WUF1
85 /**
86 * @}
87 */
88
89
90 /** @defgroup PWR_LL_EC_MODE_PWR MODE PWR
91 * @{
92 */
93 #define LL_PWR_MODE_STOP0 (0x00000000UL)
94 #define LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_1 | PWR_CR1_LPMS_0)
95 #define LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_2)
96 /**
97 * @}
98 */
99
100 #if defined(PWR_PVM_SUPPORT)
101 /** @defgroup PWR_LL_EC_PVM_IP PVM_IP
102 * @{
103 */
104 #define LL_PWR_PVM_USB PWR_CR2_PVMEN_USB /*!< Peripheral Voltage Monitoring enable for USB peripheral:
105 Enable to keep the USB peripheral voltage monitoring
106 under control (power domain Vddio2) */
107 /**
108 * @}
109 */
110 #endif /* PWR_PVM_SUPPORT */
111
112 /** @defgroup PWR_LL_EC_WAKEUP WAKEUP
113 * @{
114 */
115 #define LL_PWR_WAKEUP_PIN1 (PWR_CR3_EWUP1)
116 #define LL_PWR_WAKEUP_PIN2 (PWR_CR3_EWUP2)
117 #define LL_PWR_WAKEUP_PIN3 (PWR_CR3_EWUP3)
118 #define LL_PWR_WAKEUP_PIN4 (PWR_CR3_EWUP4)
119 #if defined(PWR_CR3_EWUP5)
120 #define LL_PWR_WAKEUP_PIN5 (PWR_CR3_EWUP5)
121 #endif /* PWR_CR3_EWUP5 */
122 #define LL_PWR_WAKEUP_PIN6 (PWR_CR3_EWUP6)
123 /**
124 * @}
125 */
126
127 /** @defgroup PWR_LL_EC_GPIO GPIO
128 * @{
129 */
130 #define LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA)))
131 #define LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB)))
132 #define LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC)))
133 #if defined(GPIOD)
134 #define LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD)))
135 #endif /* GPIOD */
136 #define LL_PWR_GPIO_F ((uint32_t)(&(PWR->PUCRF)))
137 /**
138 * @}
139 */
140
141 /** @defgroup PWR_LL_EC_GPIO_BIT GPIO BIT
142 * @{
143 */
144 #define LL_PWR_GPIO_BIT_0 0x00000001U
145 #define LL_PWR_GPIO_BIT_1 0x00000002U
146 #define LL_PWR_GPIO_BIT_2 0x00000004U
147 #define LL_PWR_GPIO_BIT_3 0x00000008U
148 #define LL_PWR_GPIO_BIT_4 0x00000010U
149 #define LL_PWR_GPIO_BIT_5 0x00000020U
150 #define LL_PWR_GPIO_BIT_6 0x00000040U
151 #define LL_PWR_GPIO_BIT_7 0x00000080U
152 #define LL_PWR_GPIO_BIT_8 0x00000100U
153 #define LL_PWR_GPIO_BIT_9 0x00000200U
154 #define LL_PWR_GPIO_BIT_10 0x00000400U
155 #define LL_PWR_GPIO_BIT_11 0x00000800U
156 #define LL_PWR_GPIO_BIT_12 0x00001000U
157 #define LL_PWR_GPIO_BIT_13 0x00002000U
158 #define LL_PWR_GPIO_BIT_14 0x00004000U
159 #define LL_PWR_GPIO_BIT_15 0x00008000U
160 /**
161 * @}
162 */
163
164 /** @defgroup PWR_LL_EC_BKP BACKUP
165 * @{
166 */
167 #define LL_PWR_BKP_NUMBER 4U
168 #define LL_PWR_BKP_DR0 0U
169 #define LL_PWR_BKP_DR1 1U
170 #define LL_PWR_BKP_DR2 2U
171 #define LL_PWR_BKP_DR3 3U
172
173 /**
174 * @}
175 */
176
177 /**
178 * @}
179 */
180
181 /* Exported macro ------------------------------------------------------------*/
182 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
183 * @{
184 */
185
186 /** @defgroup PWR_LL_EM_WRITE_READ Common Write and read registers Macros
187 * @{
188 */
189
190 /**
191 * @brief Write a value in PWR register
192 * @param __REG__ Register to be written
193 * @param __VALUE__ Value to be written in the register
194 * @retval None
195 */
196 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
197
198 /**
199 * @brief Read a value in PWR register
200 * @param __REG__ Register to be read
201 * @retval Register value
202 */
203 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
204 /**
205 * @}
206 */
207
208 /**
209 * @}
210 */
211
212
213 /* Exported functions --------------------------------------------------------*/
214 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
215 * @{
216 */
217
218 /** @defgroup PWR_LL_EF_Configuration Configuration
219 * @{
220 */
221
222 /**
223 * @brief Enable Flash Power-down mode during sleep mode
224 * @rmtoll CR1 FPD_SLP LL_PWR_EnableFlashPowerDownInSleep
225 * @retval None
226 */
LL_PWR_EnableFlashPowerDownInSleep(void)227 __STATIC_INLINE void LL_PWR_EnableFlashPowerDownInSleep(void)
228 {
229 SET_BIT(PWR->CR1, PWR_CR1_FPD_SLP);
230 }
231
232 /**
233 * @brief Disable Flash Power-down mode during sleep mode
234 * @rmtoll CR1 FPD_SLP LL_PWR_DisableFlashPowerDownInSleep
235 * @retval None
236 */
LL_PWR_DisableFlashPowerDownInSleep(void)237 __STATIC_INLINE void LL_PWR_DisableFlashPowerDownInSleep(void)
238 {
239 CLEAR_BIT(PWR->CR1, PWR_CR1_FPD_SLP);
240 }
241
242 /**
243 * @brief Check if flash power-down mode during sleep mode domain is enabled
244 * @rmtoll CR1 FPD_SLP LL_PWR_IsEnableFlashPowerDownInSleep
245 * @retval State of bit (1 or 0).
246 */
LL_PWR_IsEnableFlashPowerDownInSleep(void)247 __STATIC_INLINE uint32_t LL_PWR_IsEnableFlashPowerDownInSleep(void)
248 {
249 return ((READ_BIT(PWR->CR1, PWR_CR1_FPD_SLP) == (PWR_CR1_FPD_SLP)) ? 1UL : 0UL);
250 }
251
252 /**
253 * @brief Enable Flash Power-down mode during stop mode
254 * @rmtoll CR1 FPD_STOP LL_PWR_EnableFlashPowerDownInStop
255 * @retval None
256 */
LL_PWR_EnableFlashPowerDownInStop(void)257 __STATIC_INLINE void LL_PWR_EnableFlashPowerDownInStop(void)
258 {
259 SET_BIT(PWR->CR1, PWR_CR1_FPD_STOP);
260 }
261
262 /**
263 * @brief Disable Flash Power-down mode during stop mode
264 * @rmtoll CR1 FPD_STOP LL_PWR_DisableFlashPowerDownInStop
265 * @retval None
266 */
LL_PWR_DisableFlashPowerDownInStop(void)267 __STATIC_INLINE void LL_PWR_DisableFlashPowerDownInStop(void)
268 {
269 CLEAR_BIT(PWR->CR1, PWR_CR1_FPD_STOP);
270 }
271
272 /**
273 * @brief Check if flash power-down mode during stop mode domain is enabled
274 * @rmtoll CR1 FPD_STOP LL_PWR_IsEnableFlashPowerDownInStop
275 * @retval State of bit (1 or 0).
276 */
LL_PWR_IsEnableFlashPowerDownInStop(void)277 __STATIC_INLINE uint32_t LL_PWR_IsEnableFlashPowerDownInStop(void)
278 {
279 return ((READ_BIT(PWR->CR1, PWR_CR1_FPD_STOP) == (PWR_CR1_FPD_STOP)) ? 1UL : 0UL);
280 }
281
282 #if defined(PWR_PVM_SUPPORT)
283 /**
284 * @brief Enable VDDIO2 supply
285 * @rmtoll CR2 PVM_VDDIO2 LL_PWR_EnableVddIO2
286 * @retval None
287 */
LL_PWR_EnableVddIO2(void)288 __STATIC_INLINE void LL_PWR_EnableVddIO2(void)
289 {
290 SET_BIT(PWR->CR2, PWR_CR2_PVM_VDDIO2_1);
291 }
292
293 /**
294 * @brief Disable VDDIO2 supply
295 * @rmtoll CR2 PVM_VDDIO2 LL_PWR_DisableVddIO2
296 * @retval None
297 */
LL_PWR_DisableVddIO2(void)298 __STATIC_INLINE void LL_PWR_DisableVddIO2(void)
299 {
300 CLEAR_BIT(PWR->CR2, PWR_CR2_PVM_VDDIO2_1);
301 }
302
303 /**
304 * @brief Check if VDDIO2 supply is enabled
305 * @rmtoll CR2 PVM_VDDIO2 LL_PWR_IsEnabledVddIO2
306 * @retval State of bit (1 or 0).
307 */
LL_PWR_IsEnabledVddIO2(void)308 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void)
309 {
310 return ((READ_BIT(PWR->CR2, PWR_CR2_PVM_VDDIO2_1) == (PWR_CR2_PVM_VDDIO2_1)) ? 1UL : 0UL);
311 }
312
313 /**
314 * @brief Enable the Power Voltage Monitoring on a peripheral
315 * @rmtoll CR2 PVMUSB LL_PWR_EnablePVM
316 * @param PeriphVoltage This parameter can be one of the following values:
317 * @arg @ref LL_PWR_PVM_USB (*)
318 *
319 * @note (*) Availability depends on devices
320 * @retval None
321 */
LL_PWR_EnablePVM(uint32_t PeriphVoltage)322 __STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage)
323 {
324 SET_BIT(PWR->CR2, PeriphVoltage);
325 }
326
327 /**
328 * @brief Disable the Power Voltage Monitoring on a peripheral
329 * @rmtoll CR2 PVMUSB LL_PWR_DisablePVM
330 * @param PeriphVoltage This parameter can be one of the following values:
331 * @arg @ref LL_PWR_PVM_USB (*)
332 *
333 * @note (*) Availability depends on devices
334 * @retval None
335 */
LL_PWR_DisablePVM(uint32_t PeriphVoltage)336 __STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage)
337 {
338 CLEAR_BIT(PWR->CR2, PeriphVoltage);
339 }
340
341 /**
342 * @brief Check if Power Voltage Monitoring is enabled on a peripheral
343 * @rmtoll CR2 PVMUSB LL_PWR_IsEnabledPVM
344 * @param PeriphVoltage This parameter can be one of the following values:
345 * @arg @ref LL_PWR_PVM_USB (*)
346
347 * @note (*) Availability depends on devices
348 * @retval State of bit (1 or 0).
349 */
LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage)350 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage)
351 {
352 return ((READ_BIT(PWR->CR2, PeriphVoltage) == (PeriphVoltage)) ? 1UL : 0UL);
353 }
354 #endif /* PWR_PVM_SUPPORT */
355
356 /**
357 * @brief Set Low-Power mode
358 * @rmtoll CR1 LPMS LL_PWR_SetPowerMode
359 * @param LowPowerMode This parameter can be one of the following values:
360 * @arg @ref LL_PWR_MODE_STOP0
361 * @arg @ref LL_PWR_MODE_STANDBY
362 * @arg @ref LL_PWR_MODE_SHUTDOWN
363 * @retval None
364 */
LL_PWR_SetPowerMode(uint32_t LowPowerMode)365 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode)
366 {
367 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode);
368 }
369
370 /**
371 * @brief Get Low-Power mode
372 * @rmtoll CR1 LPMS LL_PWR_GetPowerMode
373 * @retval Returned value can be one of the following values:
374 * @arg @ref LL_PWR_MODE_STOP0
375 * @arg @ref LL_PWR_MODE_STANDBY
376 * @arg @ref LL_PWR_MODE_SHUTDOWN
377 */
LL_PWR_GetPowerMode(void)378 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
379 {
380 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS));
381 }
382
383 /**
384 * @brief Enable Internal Wake-up line
385 * @rmtoll CR3 EIWF LL_PWR_EnableInternWU
386 * @retval None
387 */
LL_PWR_EnableInternWU(void)388 __STATIC_INLINE void LL_PWR_EnableInternWU(void)
389 {
390 SET_BIT(PWR->CR3, PWR_CR3_EIWUL);
391 }
392
393 /**
394 * @brief Disable Internal Wake-up line
395 * @rmtoll CR3 EIWF LL_PWR_DisableInternWU
396 * @retval None
397 */
LL_PWR_DisableInternWU(void)398 __STATIC_INLINE void LL_PWR_DisableInternWU(void)
399 {
400 CLEAR_BIT(PWR->CR3, PWR_CR3_EIWUL);
401 }
402
403 /**
404 * @brief Check if Internal Wake-up line is enabled
405 * @rmtoll CR3 EIWF LL_PWR_IsEnabledInternWU
406 * @retval State of bit (1 or 0).
407 */
LL_PWR_IsEnabledInternWU(void)408 __STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU(void)
409 {
410 return ((READ_BIT(PWR->CR3, PWR_CR3_EIWUL) == (PWR_CR3_EIWUL)) ? 1UL : 0UL);
411 }
412
413 /**
414 * @brief Enable pull-up and pull-down configuration
415 * @rmtoll CR3 APC LL_PWR_EnablePUPDCfg
416 * @retval None
417 */
LL_PWR_EnablePUPDCfg(void)418 __STATIC_INLINE void LL_PWR_EnablePUPDCfg(void)
419 {
420 SET_BIT(PWR->CR3, PWR_CR3_APC);
421 }
422
423 /**
424 * @brief Disable pull-up and pull-down configuration
425 * @rmtoll CR3 APC LL_PWR_DisablePUPDCfg
426 * @retval None
427 */
LL_PWR_DisablePUPDCfg(void)428 __STATIC_INLINE void LL_PWR_DisablePUPDCfg(void)
429 {
430 CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
431 }
432
433 /**
434 * @brief Check if pull-up and pull-down configuration is enabled
435 * @rmtoll CR3 APC LL_PWR_IsEnabledPUPDCfg
436 * @retval State of bit (1 or 0).
437 */
LL_PWR_IsEnabledPUPDCfg(void)438 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void)
439 {
440 return ((READ_BIT(PWR->CR3, PWR_CR3_APC) == (PWR_CR3_APC)) ? 1UL : 0UL);
441 }
442
443 /**
444 * @brief Enable the WakeUp PINx functionality
445 * @rmtoll CR3 EWUP1 LL_PWR_EnableWakeUpPin\n
446 * CR3 EWUP2 LL_PWR_EnableWakeUpPin\n
447 * CR3 EWUP3 LL_PWR_EnableWakeUpPin\n
448 * CR3 EWUP4 LL_PWR_EnableWakeUpPin\n
449 * CR3 EWUP5 LL_PWR_EnableWakeUpPin (*)\n
450 * CR3 EWUP6 LL_PWR_EnableWakeUpPin
451 * @param WakeUpPin This parameter can be one of the following values:
452 * @arg @ref LL_PWR_WAKEUP_PIN1
453 * @arg @ref LL_PWR_WAKEUP_PIN2
454 * @arg @ref LL_PWR_WAKEUP_PIN3
455 * @arg @ref LL_PWR_WAKEUP_PIN4
456 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
457 * @arg @ref LL_PWR_WAKEUP_PIN6
458 * @note (*) Availability depends on devices
459 * @retval None
460 */
LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)461 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
462 {
463 SET_BIT(PWR->CR3, WakeUpPin);
464 }
465
466 /**
467 * @brief Disable the WakeUp PINx functionality
468 * @rmtoll CR3 EWUP1 LL_PWR_DisableWakeUpPin\n
469 * CR3 EWUP2 LL_PWR_DisableWakeUpPin\n
470 * CR3 EWUP3 LL_PWR_DisableWakeUpPin\n
471 * CR3 EWUP4 LL_PWR_DisableWakeUpPin\n
472 * CR3 EWUP5 LL_PWR_DisableWakeUpPin (*)\n
473 * CR3 EWUP6 LL_PWR_DisableWakeUpPin
474 * @param WakeUpPin This parameter can be one of the following values:
475 * @arg @ref LL_PWR_WAKEUP_PIN1
476 * @arg @ref LL_PWR_WAKEUP_PIN2
477 * @arg @ref LL_PWR_WAKEUP_PIN3
478 * @arg @ref LL_PWR_WAKEUP_PIN4
479 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
480 * @arg @ref LL_PWR_WAKEUP_PIN6
481 * @note (*) Availability depends on devices
482 * @retval None
483 */
LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)484 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
485 {
486 CLEAR_BIT(PWR->CR3, WakeUpPin);
487 }
488
489 /**
490 * @brief Check if the WakeUp PINx functionality is enabled
491 * @rmtoll CR3 EWUP1 LL_PWR_IsEnabledWakeUpPin\n
492 * CR3 EWUP2 LL_PWR_IsEnabledWakeUpPin\n
493 * CR3 EWUP3 LL_PWR_IsEnabledWakeUpPin\n
494 * CR3 EWUP4 LL_PWR_IsEnabledWakeUpPin\n
495 * CR3 EWUP5 LL_PWR_IsEnabledWakeUpPin (*)\n
496 * CR3 EWUP6 LL_PWR_IsEnabledWakeUpPin
497 * @param WakeUpPin This parameter can be one of the following values:
498 * @arg @ref LL_PWR_WAKEUP_PIN1
499 * @arg @ref LL_PWR_WAKEUP_PIN2
500 * @arg @ref LL_PWR_WAKEUP_PIN3
501 * @arg @ref LL_PWR_WAKEUP_PIN4
502 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
503 * @arg @ref LL_PWR_WAKEUP_PIN6
504 * @note (*) Availability depends on devices
505 * @retval State of bit (1 or 0).
506 */
LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)507 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
508 {
509 return ((READ_BIT(PWR->CR3, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
510 }
511
512 /**
513 * @brief Set the Wake-Up pin polarity low for the event detection
514 * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityLow\n
515 * CR4 WP2 LL_PWR_SetWakeUpPinPolarityLow\n
516 * CR4 WP3 LL_PWR_SetWakeUpPinPolarityLow\n
517 * CR4 WP4 LL_PWR_SetWakeUpPinPolarityLow\n
518 * CR4 WP5 LL_PWR_SetWakeUpPinPolarityLow (*)\n
519 * CR4 WP6 LL_PWR_SetWakeUpPinPolarityLow\n
520 * @param WakeUpPin This parameter can be one of the following values:
521 * @arg @ref LL_PWR_WAKEUP_PIN1
522 * @arg @ref LL_PWR_WAKEUP_PIN2
523 * @arg @ref LL_PWR_WAKEUP_PIN3
524 * @arg @ref LL_PWR_WAKEUP_PIN4
525 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
526 * @arg @ref LL_PWR_WAKEUP_PIN6
527 * @note (*) Availability depends on devices
528 * @retval None
529 */
LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)530 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
531 {
532 SET_BIT(PWR->CR4, WakeUpPin);
533 }
534
535 /**
536 * @brief Set the Wake-Up pin polarity high for the event detection
537 * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityHigh\n
538 * CR4 WP2 LL_PWR_SetWakeUpPinPolarityHigh\n
539 * CR4 WP3 LL_PWR_SetWakeUpPinPolarityHigh\n
540 * CR4 WP4 LL_PWR_SetWakeUpPinPolarityHigh\n
541 * CR4 WP5 LL_PWR_SetWakeUpPinPolarityHigh (*)\n
542 * CR4 WP6 LL_PWR_SetWakeUpPinPolarityHigh
543 * @param WakeUpPin This parameter can be one of the following values:
544 * @arg @ref LL_PWR_WAKEUP_PIN1
545 * @arg @ref LL_PWR_WAKEUP_PIN2
546 * @arg @ref LL_PWR_WAKEUP_PIN3
547 * @arg @ref LL_PWR_WAKEUP_PIN4
548 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
549 * @arg @ref LL_PWR_WAKEUP_PIN6
550 * @note (*) Availability depends on devices
551 * @retval None
552 */
LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)553 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
554 {
555 CLEAR_BIT(PWR->CR4, WakeUpPin);
556 }
557
558 /**
559 * @brief Get the Wake-Up pin polarity for the event detection
560 * @rmtoll CR4 WP1 LL_PWR_IsWakeUpPinPolarityLow\n
561 * CR4 WP2 LL_PWR_IsWakeUpPinPolarityLow\n
562 * CR4 WP3 LL_PWR_IsWakeUpPinPolarityLow\n
563 * CR4 WP4 LL_PWR_IsWakeUpPinPolarityLow\n
564 * CR4 WP5 LL_PWR_IsWakeUpPinPolarityLow (*)\n
565 * CR4 WP6 LL_PWR_IsWakeUpPinPolarityLow
566 * @param WakeUpPin This parameter can be one of the following values:
567 * @arg @ref LL_PWR_WAKEUP_PIN1
568 * @arg @ref LL_PWR_WAKEUP_PIN2
569 * @arg @ref LL_PWR_WAKEUP_PIN3
570 * @arg @ref LL_PWR_WAKEUP_PIN4
571 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
572 * @arg @ref LL_PWR_WAKEUP_PIN6
573 * @note (*) Availability depends on devices
574 * @retval State of bit (1 or 0).
575 */
LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)576 __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
577 {
578 return ((READ_BIT(PWR->CR4, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
579 }
580
581 /**
582 * @brief Enable GPIO pull-up state in Standby and Shutdown modes
583 * @rmtoll PUCRA PU0-15 LL_PWR_EnableGPIOPullUp\n
584 * PUCRB PU0-15 LL_PWR_EnableGPIOPullUp\n
585 * PUCRC PU0-15 LL_PWR_EnableGPIOPullUp\n
586 * PUCRD PU0-15 LL_PWR_EnableGPIOPullUp (*)\n
587 * PUCRF PU0-15 LL_PWR_EnableGPIOPullUp
588 * @note (*) Port D availability depends on devices
589 * @param GPIO This parameter can be one of the following values:
590 * @arg @ref LL_PWR_GPIO_A
591 * @arg @ref LL_PWR_GPIO_B
592 * @arg @ref LL_PWR_GPIO_C
593 * @arg @ref LL_PWR_GPIO_D (*)
594 * @arg @ref LL_PWR_GPIO_F
595 * @note (*) Port D availability depends on devices
596 * @param GPIONumber This parameter can be one of the following values:
597 * @arg @ref LL_PWR_GPIO_BIT_0
598 * @arg @ref LL_PWR_GPIO_BIT_1
599 * @arg @ref LL_PWR_GPIO_BIT_2
600 * @arg @ref LL_PWR_GPIO_BIT_3
601 * @arg @ref LL_PWR_GPIO_BIT_4
602 * @arg @ref LL_PWR_GPIO_BIT_5
603 * @arg @ref LL_PWR_GPIO_BIT_6
604 * @arg @ref LL_PWR_GPIO_BIT_7
605 * @arg @ref LL_PWR_GPIO_BIT_8
606 * @arg @ref LL_PWR_GPIO_BIT_9
607 * @arg @ref LL_PWR_GPIO_BIT_10
608 * @arg @ref LL_PWR_GPIO_BIT_11
609 * @arg @ref LL_PWR_GPIO_BIT_12
610 * @arg @ref LL_PWR_GPIO_BIT_13
611 * @arg @ref LL_PWR_GPIO_BIT_14
612 * @arg @ref LL_PWR_GPIO_BIT_15
613 * @retval None
614 */
LL_PWR_EnableGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)615 __STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
616 {
617 SET_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
618 }
619
620 /**
621 * @brief Disable GPIO pull-up state in Standby and Shutdown modes
622 * @rmtoll PUCRA PU0-15 LL_PWR_DisableGPIOPullUp\n
623 * PUCRB PU0-15 LL_PWR_DisableGPIOPullUp\n
624 * PUCRC PU0-15 LL_PWR_DisableGPIOPullUp\n
625 * PUCRD PU0-15 LL_PWR_DisableGPIOPullUp (*)\n
626 * PUCRF PU0-15 LL_PWR_DisableGPIOPullUp
627 * @note (*) Port D availability depends on devices
628 * @param GPIO This parameter can be one of the following values:
629 * @arg @ref LL_PWR_GPIO_A
630 * @arg @ref LL_PWR_GPIO_B
631 * @arg @ref LL_PWR_GPIO_C
632 * @arg @ref LL_PWR_GPIO_D (*)
633 * @arg @ref LL_PWR_GPIO_F
634 * @param GPIONumber This parameter can be one of the following values:
635 * @arg @ref LL_PWR_GPIO_BIT_0
636 * @arg @ref LL_PWR_GPIO_BIT_1
637 * @arg @ref LL_PWR_GPIO_BIT_2
638 * @arg @ref LL_PWR_GPIO_BIT_3
639 * @arg @ref LL_PWR_GPIO_BIT_4
640 * @arg @ref LL_PWR_GPIO_BIT_5
641 * @arg @ref LL_PWR_GPIO_BIT_6
642 * @arg @ref LL_PWR_GPIO_BIT_7
643 * @arg @ref LL_PWR_GPIO_BIT_8
644 * @arg @ref LL_PWR_GPIO_BIT_9
645 * @arg @ref LL_PWR_GPIO_BIT_10
646 * @arg @ref LL_PWR_GPIO_BIT_11
647 * @arg @ref LL_PWR_GPIO_BIT_12
648 * @arg @ref LL_PWR_GPIO_BIT_13
649 * @arg @ref LL_PWR_GPIO_BIT_14
650 * @arg @ref LL_PWR_GPIO_BIT_15
651 * @retval None
652 */
LL_PWR_DisableGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)653 __STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
654 {
655 CLEAR_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
656 }
657
658 /**
659 * @brief Check if GPIO pull-up state is enabled
660 * @rmtoll PUCRA PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
661 * PUCRB PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
662 * PUCRC PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
663 * PUCRD PU0-15 LL_PWR_IsEnabledGPIOPullUp (*)\n
664 * PUCRF PU0-15 LL_PWR_IsEnabledGPIOPullUp
665 * @note (*) Port D availability depends on devices
666 * @param GPIO This parameter can be one of the following values:
667 * @arg @ref LL_PWR_GPIO_A
668 * @arg @ref LL_PWR_GPIO_B
669 * @arg @ref LL_PWR_GPIO_C
670 * @arg @ref LL_PWR_GPIO_D (*)
671 * @arg @ref LL_PWR_GPIO_F
672 * @note (*) Port D availability depends on devices
673 * @param GPIONumber This parameter can be one of the following values:
674 * @arg @ref LL_PWR_GPIO_BIT_0
675 * @arg @ref LL_PWR_GPIO_BIT_1
676 * @arg @ref LL_PWR_GPIO_BIT_2
677 * @arg @ref LL_PWR_GPIO_BIT_3
678 * @arg @ref LL_PWR_GPIO_BIT_4
679 * @arg @ref LL_PWR_GPIO_BIT_5
680 * @arg @ref LL_PWR_GPIO_BIT_6
681 * @arg @ref LL_PWR_GPIO_BIT_7
682 * @arg @ref LL_PWR_GPIO_BIT_8
683 * @arg @ref LL_PWR_GPIO_BIT_9
684 * @arg @ref LL_PWR_GPIO_BIT_10
685 * @arg @ref LL_PWR_GPIO_BIT_11
686 * @arg @ref LL_PWR_GPIO_BIT_12
687 * @arg @ref LL_PWR_GPIO_BIT_13
688 * @arg @ref LL_PWR_GPIO_BIT_14
689 * @arg @ref LL_PWR_GPIO_BIT_15
690 * @retval State of bit (1 or 0).
691 */
LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)692 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
693 {
694 return ((READ_BIT(*((__IO uint32_t *)GPIO), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
695 }
696
697 /**
698 * @brief Enable GPIO pull-down state in Standby and Shutdown modes
699 * @rmtoll PDCRA PD0-15 LL_PWR_EnableGPIOPullDown\n
700 * PDCRB PD0-15 LL_PWR_EnableGPIOPullDown\n
701 * PDCRC PD0-15 LL_PWR_EnableGPIOPullDown\n
702 * PDCRD PD0-15 LL_PWR_EnableGPIOPullDown (*)\n
703 * PDCRF PD0-15 LL_PWR_EnableGPIOPullDown
704 * @note (*) Port D availability depends on devices
705 * @param GPIO This parameter can be one of the following values:
706 * @arg @ref LL_PWR_GPIO_A
707 * @arg @ref LL_PWR_GPIO_B
708 * @arg @ref LL_PWR_GPIO_C
709 * @arg @ref LL_PWR_GPIO_D (*)
710 * @arg @ref LL_PWR_GPIO_F
711 * @param GPIONumber This parameter can be one of the following values:
712 * @arg @ref LL_PWR_GPIO_BIT_0
713 * @arg @ref LL_PWR_GPIO_BIT_1
714 * @arg @ref LL_PWR_GPIO_BIT_2
715 * @arg @ref LL_PWR_GPIO_BIT_3
716 * @arg @ref LL_PWR_GPIO_BIT_4
717 * @arg @ref LL_PWR_GPIO_BIT_5
718 * @arg @ref LL_PWR_GPIO_BIT_6
719 * @arg @ref LL_PWR_GPIO_BIT_7
720 * @arg @ref LL_PWR_GPIO_BIT_8
721 * @arg @ref LL_PWR_GPIO_BIT_9
722 * @arg @ref LL_PWR_GPIO_BIT_10
723 * @arg @ref LL_PWR_GPIO_BIT_11
724 * @arg @ref LL_PWR_GPIO_BIT_12
725 * @arg @ref LL_PWR_GPIO_BIT_13
726 * @arg @ref LL_PWR_GPIO_BIT_14
727 * @arg @ref LL_PWR_GPIO_BIT_15
728 * @retval None
729 */
LL_PWR_EnableGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)730 __STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
731 {
732 SET_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
733 }
734
735 /**
736 * @brief Disable GPIO pull-down state in Standby and Shutdown modes
737 * @rmtoll PDCRA PD0-15 LL_PWR_DisableGPIOPullDown\n
738 * PDCRB PD0-15 LL_PWR_DisableGPIOPullDown\n
739 * PDCRC PD0-15 LL_PWR_DisableGPIOPullDown\n
740 * PDCRD PD0-15 LL_PWR_DisableGPIOPullDown (*)\n
741 * PDCRF PD0-15 LL_PWR_DisableGPIOPullDown
742 * @note (*) Port D availability depends on devices
743 * @param GPIO This parameter can be one of the following values:
744 * @arg @ref LL_PWR_GPIO_A
745 * @arg @ref LL_PWR_GPIO_B
746 * @arg @ref LL_PWR_GPIO_C
747 * @arg @ref LL_PWR_GPIO_D (*)
748 * @note (*) Port D availability depends on devices
749 * @arg @ref LL_PWR_GPIO_F
750 * @param GPIONumber This parameter can be one of the following values:
751 * @arg @ref LL_PWR_GPIO_BIT_0
752 * @arg @ref LL_PWR_GPIO_BIT_1
753 * @arg @ref LL_PWR_GPIO_BIT_2
754 * @arg @ref LL_PWR_GPIO_BIT_3
755 * @arg @ref LL_PWR_GPIO_BIT_4
756 * @arg @ref LL_PWR_GPIO_BIT_5
757 * @arg @ref LL_PWR_GPIO_BIT_6
758 * @arg @ref LL_PWR_GPIO_BIT_7
759 * @arg @ref LL_PWR_GPIO_BIT_8
760 * @arg @ref LL_PWR_GPIO_BIT_9
761 * @arg @ref LL_PWR_GPIO_BIT_10
762 * @arg @ref LL_PWR_GPIO_BIT_11
763 * @arg @ref LL_PWR_GPIO_BIT_12
764 * @arg @ref LL_PWR_GPIO_BIT_13
765 * @arg @ref LL_PWR_GPIO_BIT_14
766 * @arg @ref LL_PWR_GPIO_BIT_15
767 * @retval None
768 */
LL_PWR_DisableGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)769 __STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
770 {
771 CLEAR_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
772 }
773
774 /**
775 * @brief Check if GPIO pull-down state is enabled
776 * @rmtoll PDCRA PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
777 * PDCRB PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
778 * PDCRC PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
779 * PDCRD PD0-15 LL_PWR_IsEnabledGPIOPullDown (*)\n
780 * @note (*) Port D availability depends on devices
781 * PDCRF PD0-15 LL_PWR_IsEnabledGPIOPullDown
782 * @param GPIO This parameter can be one of the following values:
783 * @arg @ref LL_PWR_GPIO_A
784 * @arg @ref LL_PWR_GPIO_B
785 * @arg @ref LL_PWR_GPIO_C
786 * @arg @ref LL_PWR_GPIO_D (*)
787 * @arg @ref LL_PWR_GPIO_F
788 * @note (*) Port D availability depends on devices
789 * @param GPIONumber This parameter can be one of the following values:
790 * @arg @ref LL_PWR_GPIO_BIT_0
791 * @arg @ref LL_PWR_GPIO_BIT_1
792 * @arg @ref LL_PWR_GPIO_BIT_2
793 * @arg @ref LL_PWR_GPIO_BIT_3
794 * @arg @ref LL_PWR_GPIO_BIT_4
795 * @arg @ref LL_PWR_GPIO_BIT_5
796 * @arg @ref LL_PWR_GPIO_BIT_6
797 * @arg @ref LL_PWR_GPIO_BIT_7
798 * @arg @ref LL_PWR_GPIO_BIT_8
799 * @arg @ref LL_PWR_GPIO_BIT_9
800 * @arg @ref LL_PWR_GPIO_BIT_10
801 * @arg @ref LL_PWR_GPIO_BIT_11
802 * @arg @ref LL_PWR_GPIO_BIT_12
803 * @arg @ref LL_PWR_GPIO_BIT_13
804 * @arg @ref LL_PWR_GPIO_BIT_14
805 * @arg @ref LL_PWR_GPIO_BIT_15
806 * @retval State of bit (1 or 0).
807 */
LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)808 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
809 {
810 return ((READ_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
811 }
812
813 /**
814 * @}
815 */
816
817 /** @defgroup PWR_LL_EF_Backup_Registers Backup_Registers
818 * @{
819 */
820
821 /**
822 * @brief Writes a data in a specified Backup data register.
823 * @rmtoll PWR_BKPREGx BKP LL_PWR_BKP_SetRegister
824 * @param BackupRegister This parameter can be one of the following values:
825 * @arg @ref LL_PWR_BKP_DR0
826 * @arg @ref LL_PWR_BKP_DR1
827 * @arg @ref LL_PWR_BKP_DR2
828 * @arg @ref LL_PWR_BKP_DR3
829 * @param Data Value between Min_Data=0x00 and Max_Data=0xFFFF
830 * @retval None
831 */
LL_PWR_BKP_SetRegister(uint32_t BackupRegister,uint16_t Data)832 __STATIC_INLINE void LL_PWR_BKP_SetRegister(uint32_t BackupRegister, uint16_t Data)
833 {
834 __IO uint32_t tmp;
835
836 tmp = (uint32_t)(&(PWR->BKP0R));
837 tmp += (BackupRegister * 4U);
838
839 /* Write the specified register */
840 *(__IO uint32_t *)tmp = (uint16_t)Data;
841 }
842
843 /**
844 * @brief Reads data from the specified Backup data Register.
845 * @rmtoll PWR_BKPREGx BKP LL_PWR_BKP_GetRegister
846 * @param BackupRegister This parameter can be one of the following values:
847 * @arg @ref LL_PWR_BKP_DR0
848 * @arg @ref LL_PWR_BKP_DR1
849 * @arg @ref LL_PWR_BKP_DR2
850 * @arg @ref LL_PWR_BKP_DR3
851 * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
852 */
LL_PWR_BKP_GetRegister(uint32_t BackupRegister)853 __STATIC_INLINE uint32_t LL_PWR_BKP_GetRegister(uint32_t BackupRegister)
854 {
855 uint32_t tmp;
856
857 tmp = (uint32_t)(&(PWR->BKP0R));
858 tmp += (BackupRegister * 4U);
859
860 /* Read the specified register */
861 return (*(__IO uint32_t *)tmp);
862 }
863
864 /**
865 * @}
866 */
867
868 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
869 * @{
870 */
871
872 /**
873 * @brief Get Internal Wake-up line Flag
874 * @rmtoll SR1 WUFI LL_PWR_IsActiveFlag_InternWU
875 * @retval State of bit (1 or 0).
876 */
LL_PWR_IsActiveFlag_InternWU(void)877 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU(void)
878 {
879 return ((READ_BIT(PWR->SR1, PWR_SR1_WUFI) == (PWR_SR1_WUFI)) ? 1UL : 0UL);
880 }
881
882 /**
883 * @brief Get Standby Flag
884 * @rmtoll SR1 SBF LL_PWR_IsActiveFlag_SB
885 * @retval State of bit (1 or 0).
886 */
LL_PWR_IsActiveFlag_SB(void)887 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
888 {
889 return ((READ_BIT(PWR->SR1, PWR_SR1_SBF) == (PWR_SR1_SBF)) ? 1UL : 0UL);
890 }
891
892 /**
893 * @brief Get Wake-up Flag 6
894 * @rmtoll SR1 WUF6 LL_PWR_IsActiveFlag_WU6
895 * @retval State of bit (1 or 0).
896 */
LL_PWR_IsActiveFlag_WU6(void)897 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void)
898 {
899 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF6) == (PWR_SR1_WUF6)) ? 1UL : 0UL);
900 }
901
902 #if defined(PWR_CR3_EWUP5)
903 /**
904 * @brief Get Wake-up Flag 5
905 * @rmtoll SR1 WUF5 LL_PWR_IsActiveFlag_WU5
906 * @retval State of bit (1 or 0).
907 */
LL_PWR_IsActiveFlag_WU5(void)908 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
909 {
910 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF5) == (PWR_SR1_WUF5)) ? 1UL : 0UL);
911 }
912 #endif /* PWR_CR3_EWUP5 */
913
914 /**
915 * @brief Get Wake-up Flag 4
916 * @rmtoll SR1 WUF4 LL_PWR_IsActiveFlag_WU4
917 * @retval State of bit (1 or 0).
918 */
LL_PWR_IsActiveFlag_WU4(void)919 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
920 {
921 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF4) == (PWR_SR1_WUF4)) ? 1UL : 0UL);
922 }
923
924 /**
925 * @brief Get Wake-up Flag 3
926 * @rmtoll SR1 WUF3 LL_PWR_IsActiveFlag_WU3
927 * @retval State of bit (1 or 0).
928 */
LL_PWR_IsActiveFlag_WU3(void)929 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
930 {
931 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF3) == (PWR_SR1_WUF3)) ? 1UL : 0UL);
932 }
933
934 /**
935 * @brief Get Wake-up Flag 2
936 * @rmtoll SR1 WUF2 LL_PWR_IsActiveFlag_WU2
937 * @retval State of bit (1 or 0).
938 */
LL_PWR_IsActiveFlag_WU2(void)939 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
940 {
941 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF2) == (PWR_SR1_WUF2)) ? 1UL : 0UL);
942 }
943
944 /**
945 * @brief Get Wake-up Flag 1
946 * @rmtoll SR1 WUF1 LL_PWR_IsActiveFlag_WU1
947 * @retval State of bit (1 or 0).
948 */
LL_PWR_IsActiveFlag_WU1(void)949 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
950 {
951 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF1) == (PWR_SR1_WUF1)) ? 1UL : 0UL);
952 }
953
954 /**
955 * @brief Clear Standby Flag
956 * @rmtoll SCR CSBF LL_PWR_ClearFlag_SB
957 * @retval None
958 */
LL_PWR_ClearFlag_SB(void)959 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
960 {
961 WRITE_REG(PWR->SCR, PWR_SCR_CSBF);
962 }
963
964 /**
965 * @brief Clear Wake-up Flags
966 * @rmtoll SCR CWUF LL_PWR_ClearFlag_WU
967 * @retval None
968 */
LL_PWR_ClearFlag_WU(void)969 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
970 {
971 WRITE_REG(PWR->SCR, PWR_SCR_CWUF);
972 }
973
974 /**
975 * @brief Clear Wake-up Flag 6
976 * @rmtoll SCR CWUF6 LL_PWR_ClearFlag_WU6
977 * @retval None
978 */
LL_PWR_ClearFlag_WU6(void)979 __STATIC_INLINE void LL_PWR_ClearFlag_WU6(void)
980 {
981 WRITE_REG(PWR->SCR, PWR_SCR_CWUF6);
982 }
983
984 #if defined(PWR_CR3_EWUP5)
985 /**
986 * @brief Clear Wake-up Flag 5
987 * @rmtoll SCR CWUF5 LL_PWR_ClearFlag_WU5
988 * @retval None
989 */
LL_PWR_ClearFlag_WU5(void)990 __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
991 {
992 WRITE_REG(PWR->SCR, PWR_SCR_CWUF5);
993 }
994 #endif /* PWR_CR3_EWUP5 */
995
996 /**
997 * @brief Clear Wake-up Flag 4
998 * @rmtoll SCR CWUF4 LL_PWR_ClearFlag_WU4
999 * @retval None
1000 */
LL_PWR_ClearFlag_WU4(void)1001 __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
1002 {
1003 WRITE_REG(PWR->SCR, PWR_SCR_CWUF4);
1004 }
1005
1006 /**
1007 * @brief Clear Wake-up Flag 3
1008 * @rmtoll SCR CWUF3 LL_PWR_ClearFlag_WU3
1009 * @retval None
1010 */
LL_PWR_ClearFlag_WU3(void)1011 __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
1012 {
1013 WRITE_REG(PWR->SCR, PWR_SCR_CWUF3);
1014 }
1015
1016 /**
1017 * @brief Clear Wake-up Flag 2
1018 * @rmtoll SCR CWUF2 LL_PWR_ClearFlag_WU2
1019 * @retval None
1020 */
LL_PWR_ClearFlag_WU2(void)1021 __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
1022 {
1023 WRITE_REG(PWR->SCR, PWR_SCR_CWUF2);
1024 }
1025
1026 /**
1027 * @brief Clear Wake-up Flag 1
1028 * @rmtoll SCR CWUF1 LL_PWR_ClearFlag_WU1
1029 * @retval None
1030 */
LL_PWR_ClearFlag_WU1(void)1031 __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
1032 {
1033 WRITE_REG(PWR->SCR, PWR_SCR_CWUF1);
1034 }
1035
1036 #if defined (PWR_PVM_SUPPORT)
1037 /**
1038 * @brief Indicate whether VDD voltage is below or above the selected PVD
1039 * threshold
1040 * @rmtoll SR2 PVDMO_USB LL_PWR_IsActiveFlag_PVMOUSB
1041 * @retval State of bit (1 or 0).
1042 */
LL_PWR_IsActiveFlag_PVMOUSB(void)1043 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMOUSB(void)
1044 {
1045 return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO_VDDIO2) == (PWR_SR2_PVMO_VDDIO2)) ? 1UL : 0UL);
1046 }
1047 #endif /* PWR_PVM_SUPPORT */
1048
1049 /**
1050 * @brief Indicate whether or not the flash is ready to be accessed
1051 * @rmtoll SR2 FLASH_RDY LL_PWR_IsActiveFlag_FLASH_RDY
1052 * @retval State of bit (1 or 0).
1053 */
LL_PWR_IsActiveFlag_FLASH_RDY(void)1054 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_FLASH_RDY(void)
1055 {
1056 return ((READ_BIT(PWR->SR2, PWR_SR2_FLASH_RDY) == (PWR_SR2_FLASH_RDY)) ? 1UL : 0UL);
1057 }
1058 /**
1059 * @}
1060 */
1061
1062 #if defined(USE_FULL_LL_DRIVER)
1063 /** @defgroup PWR_LL_EF_Init De-initialization function
1064 * @{
1065 */
1066 ErrorStatus LL_PWR_DeInit(void);
1067 /**
1068 * @}
1069 */
1070 #endif /* USE_FULL_LL_DRIVER */
1071
1072 /**
1073 * @}
1074 */
1075
1076 /**
1077 * @}
1078 */
1079
1080 #endif /* defined(PWR) */
1081
1082 /**
1083 * @}
1084 */
1085
1086 #ifdef __cplusplus
1087 }
1088 #endif
1089
1090 #endif /* STM32C0xx_LL_PWR_H */
1091
