/** ****************************************************************************** * @file stm32c0xx_ll_pwr.h * @author MCD Application Team * @brief Header file of PWR LL module. ****************************************************************************** * @attention * * Copyright (c) 2022 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32C0xx_LL_PWR_H #define STM32C0xx_LL_PWR_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32c0xx.h" /** @addtogroup STM32C0xx_LL_Driver * @{ */ #if defined(PWR) /** @defgroup PWR_LL PWR * @{ */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants * @{ */ /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines * @brief Flags defines which can be used with LL_PWR_WriteReg function * @{ */ #define LL_PWR_SCR_CSBF PWR_SCR_CSBF #define LL_PWR_SCR_CWUF PWR_SCR_CWUF #define LL_PWR_SCR_CWUF6 PWR_SCR_CWUF6 #if defined(PWR_SCR_CWUF5) #define LL_PWR_SCR_CWUF5 PWR_SCR_CWUF5 #endif /* PWR_SCR_CWUF5 */ #define LL_PWR_SCR_CWUF4 PWR_SCR_CWUF4 #define LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3 #define LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2 #define LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1 /** * @} */ /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines * @brief Flags defines which can be used with LL_PWR_ReadReg function * @{ */ #define LL_PWR_SR1_WUFI PWR_SR1_WUFI #define LL_PWR_SR1_SBF PWR_SR1_SBF #define LL_PWR_SR1_WUF6 PWR_SR1_WUF6 #if defined(PWR_SR1_WUF5) #define LL_PWR_SR1_WUF5 PWR_SR1_WUF5 #endif /* PWR_SR1_WUF5 */ #define LL_PWR_SR1_WUF4 PWR_SR1_WUF4 #define LL_PWR_SR1_WUF3 PWR_SR1_WUF3 #define LL_PWR_SR1_WUF2 PWR_SR1_WUF2 #define LL_PWR_SR1_WUF1 PWR_SR1_WUF1 /** * @} */ /** @defgroup PWR_LL_EC_MODE_PWR MODE PWR * @{ */ #define LL_PWR_MODE_STOP0 (0x00000000UL) #define LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_1 | PWR_CR1_LPMS_0) #define LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_2) /** * @} */ #if defined(PWR_PVM_SUPPORT) /** @defgroup PWR_LL_EC_PVM_IP PVM_IP * @{ */ #define LL_PWR_PVM_USB PWR_CR2_PVMEN_USB /*!< Peripheral Voltage Monitoring enable for USB peripheral: Enable to keep the USB peripheral voltage monitoring under control (power domain Vddio2) */ /** * @} */ #endif /* PWR_PVM_SUPPORT */ /** @defgroup PWR_LL_EC_WAKEUP WAKEUP * @{ */ #define LL_PWR_WAKEUP_PIN1 (PWR_CR3_EWUP1) #define LL_PWR_WAKEUP_PIN2 (PWR_CR3_EWUP2) #define LL_PWR_WAKEUP_PIN3 (PWR_CR3_EWUP3) #define LL_PWR_WAKEUP_PIN4 (PWR_CR3_EWUP4) #if defined(PWR_CR3_EWUP5) #define LL_PWR_WAKEUP_PIN5 (PWR_CR3_EWUP5) #endif /* PWR_CR3_EWUP5 */ #define LL_PWR_WAKEUP_PIN6 (PWR_CR3_EWUP6) /** * @} */ /** @defgroup PWR_LL_EC_GPIO GPIO * @{ */ #define LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA))) #define LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB))) #define LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC))) #if defined(GPIOD) #define LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD))) #endif /* GPIOD */ #define LL_PWR_GPIO_F ((uint32_t)(&(PWR->PUCRF))) /** * @} */ /** @defgroup PWR_LL_EC_GPIO_BIT GPIO BIT * @{ */ #define LL_PWR_GPIO_BIT_0 0x00000001U #define LL_PWR_GPIO_BIT_1 0x00000002U #define LL_PWR_GPIO_BIT_2 0x00000004U #define LL_PWR_GPIO_BIT_3 0x00000008U #define LL_PWR_GPIO_BIT_4 0x00000010U #define LL_PWR_GPIO_BIT_5 0x00000020U #define LL_PWR_GPIO_BIT_6 0x00000040U #define LL_PWR_GPIO_BIT_7 0x00000080U #define LL_PWR_GPIO_BIT_8 0x00000100U #define LL_PWR_GPIO_BIT_9 0x00000200U #define LL_PWR_GPIO_BIT_10 0x00000400U #define LL_PWR_GPIO_BIT_11 0x00000800U #define LL_PWR_GPIO_BIT_12 0x00001000U #define LL_PWR_GPIO_BIT_13 0x00002000U #define LL_PWR_GPIO_BIT_14 0x00004000U #define LL_PWR_GPIO_BIT_15 0x00008000U /** * @} */ /** @defgroup PWR_LL_EC_BKP BACKUP * @{ */ #define LL_PWR_BKP_NUMBER 4U #define LL_PWR_BKP_DR0 0U #define LL_PWR_BKP_DR1 1U #define LL_PWR_BKP_DR2 2U #define LL_PWR_BKP_DR3 3U /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros * @{ */ /** @defgroup PWR_LL_EM_WRITE_READ Common Write and read registers Macros * @{ */ /** * @brief Write a value in PWR register * @param __REG__ Register to be written * @param __VALUE__ Value to be written in the register * @retval None */ #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) /** * @brief Read a value in PWR register * @param __REG__ Register to be read * @retval Register value */ #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) /** * @} */ /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions * @{ */ /** @defgroup PWR_LL_EF_Configuration Configuration * @{ */ /** * @brief Enable Flash Power-down mode during sleep mode * @rmtoll CR1 FPD_SLP LL_PWR_EnableFlashPowerDownInSleep * @retval None */ __STATIC_INLINE void LL_PWR_EnableFlashPowerDownInSleep(void) { SET_BIT(PWR->CR1, PWR_CR1_FPD_SLP); } /** * @brief Disable Flash Power-down mode during sleep mode * @rmtoll CR1 FPD_SLP LL_PWR_DisableFlashPowerDownInSleep * @retval None */ __STATIC_INLINE void LL_PWR_DisableFlashPowerDownInSleep(void) { CLEAR_BIT(PWR->CR1, PWR_CR1_FPD_SLP); } /** * @brief Check if flash power-down mode during sleep mode domain is enabled * @rmtoll CR1 FPD_SLP LL_PWR_IsEnableFlashPowerDownInSleep * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsEnableFlashPowerDownInSleep(void) { return ((READ_BIT(PWR->CR1, PWR_CR1_FPD_SLP) == (PWR_CR1_FPD_SLP)) ? 1UL : 0UL); } /** * @brief Enable Flash Power-down mode during stop mode * @rmtoll CR1 FPD_STOP LL_PWR_EnableFlashPowerDownInStop * @retval None */ __STATIC_INLINE void LL_PWR_EnableFlashPowerDownInStop(void) { SET_BIT(PWR->CR1, PWR_CR1_FPD_STOP); } /** * @brief Disable Flash Power-down mode during stop mode * @rmtoll CR1 FPD_STOP LL_PWR_DisableFlashPowerDownInStop * @retval None */ __STATIC_INLINE void LL_PWR_DisableFlashPowerDownInStop(void) { CLEAR_BIT(PWR->CR1, PWR_CR1_FPD_STOP); } /** * @brief Check if flash power-down mode during stop mode domain is enabled * @rmtoll CR1 FPD_STOP LL_PWR_IsEnableFlashPowerDownInStop * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsEnableFlashPowerDownInStop(void) { return ((READ_BIT(PWR->CR1, PWR_CR1_FPD_STOP) == (PWR_CR1_FPD_STOP)) ? 1UL : 0UL); } #if defined(PWR_PVM_SUPPORT) /** * @brief Enable VDDIO2 supply * @rmtoll CR2 PVM_VDDIO2 LL_PWR_EnableVddIO2 * @retval None */ __STATIC_INLINE void LL_PWR_EnableVddIO2(void) { SET_BIT(PWR->CR2, PWR_CR2_PVM_VDDIO2_1); } /** * @brief Disable VDDIO2 supply * @rmtoll CR2 PVM_VDDIO2 LL_PWR_DisableVddIO2 * @retval None */ __STATIC_INLINE void LL_PWR_DisableVddIO2(void) { CLEAR_BIT(PWR->CR2, PWR_CR2_PVM_VDDIO2_1); } /** * @brief Check if VDDIO2 supply is enabled * @rmtoll CR2 PVM_VDDIO2 LL_PWR_IsEnabledVddIO2 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void) { return ((READ_BIT(PWR->CR2, PWR_CR2_PVM_VDDIO2_1) == (PWR_CR2_PVM_VDDIO2_1)) ? 1UL : 0UL); } /** * @brief Enable the Power Voltage Monitoring on a peripheral * @rmtoll CR2 PVMUSB LL_PWR_EnablePVM * @param PeriphVoltage This parameter can be one of the following values: * @arg @ref LL_PWR_PVM_USB (*) * * @note (*) Availability depends on devices * @retval None */ __STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage) { SET_BIT(PWR->CR2, PeriphVoltage); } /** * @brief Disable the Power Voltage Monitoring on a peripheral * @rmtoll CR2 PVMUSB LL_PWR_DisablePVM * @param PeriphVoltage This parameter can be one of the following values: * @arg @ref LL_PWR_PVM_USB (*) * * @note (*) Availability depends on devices * @retval None */ __STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage) { CLEAR_BIT(PWR->CR2, PeriphVoltage); } /** * @brief Check if Power Voltage Monitoring is enabled on a peripheral * @rmtoll CR2 PVMUSB LL_PWR_IsEnabledPVM * @param PeriphVoltage This parameter can be one of the following values: * @arg @ref LL_PWR_PVM_USB (*) * @note (*) Availability depends on devices * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage) { return ((READ_BIT(PWR->CR2, PeriphVoltage) == (PeriphVoltage)) ? 1UL : 0UL); } #endif /* PWR_PVM_SUPPORT */ /** * @brief Set Low-Power mode * @rmtoll CR1 LPMS LL_PWR_SetPowerMode * @param LowPowerMode This parameter can be one of the following values: * @arg @ref LL_PWR_MODE_STOP0 * @arg @ref LL_PWR_MODE_STANDBY * @arg @ref LL_PWR_MODE_SHUTDOWN * @retval None */ __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode) { MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode); } /** * @brief Get Low-Power mode * @rmtoll CR1 LPMS LL_PWR_GetPowerMode * @retval Returned value can be one of the following values: * @arg @ref LL_PWR_MODE_STOP0 * @arg @ref LL_PWR_MODE_STANDBY * @arg @ref LL_PWR_MODE_SHUTDOWN */ __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) { return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS)); } /** * @brief Enable Internal Wake-up line * @rmtoll CR3 EIWF LL_PWR_EnableInternWU * @retval None */ __STATIC_INLINE void LL_PWR_EnableInternWU(void) { SET_BIT(PWR->CR3, PWR_CR3_EIWUL); } /** * @brief Disable Internal Wake-up line * @rmtoll CR3 EIWF LL_PWR_DisableInternWU * @retval None */ __STATIC_INLINE void LL_PWR_DisableInternWU(void) { CLEAR_BIT(PWR->CR3, PWR_CR3_EIWUL); } /** * @brief Check if Internal Wake-up line is enabled * @rmtoll CR3 EIWF LL_PWR_IsEnabledInternWU * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU(void) { return ((READ_BIT(PWR->CR3, PWR_CR3_EIWUL) == (PWR_CR3_EIWUL)) ? 1UL : 0UL); } /** * @brief Enable pull-up and pull-down configuration * @rmtoll CR3 APC LL_PWR_EnablePUPDCfg * @retval None */ __STATIC_INLINE void LL_PWR_EnablePUPDCfg(void) { SET_BIT(PWR->CR3, PWR_CR3_APC); } /** * @brief Disable pull-up and pull-down configuration * @rmtoll CR3 APC LL_PWR_DisablePUPDCfg * @retval None */ __STATIC_INLINE void LL_PWR_DisablePUPDCfg(void) { CLEAR_BIT(PWR->CR3, PWR_CR3_APC); } /** * @brief Check if pull-up and pull-down configuration is enabled * @rmtoll CR3 APC LL_PWR_IsEnabledPUPDCfg * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void) { return ((READ_BIT(PWR->CR3, PWR_CR3_APC) == (PWR_CR3_APC)) ? 1UL : 0UL); } /** * @brief Enable the WakeUp PINx functionality * @rmtoll CR3 EWUP1 LL_PWR_EnableWakeUpPin\n * CR3 EWUP2 LL_PWR_EnableWakeUpPin\n * CR3 EWUP3 LL_PWR_EnableWakeUpPin\n * CR3 EWUP4 LL_PWR_EnableWakeUpPin\n * CR3 EWUP5 LL_PWR_EnableWakeUpPin (*)\n * CR3 EWUP6 LL_PWR_EnableWakeUpPin * @param WakeUpPin This parameter can be one of the following values: * @arg @ref LL_PWR_WAKEUP_PIN1 * @arg @ref LL_PWR_WAKEUP_PIN2 * @arg @ref LL_PWR_WAKEUP_PIN3 * @arg @ref LL_PWR_WAKEUP_PIN4 * @arg @ref LL_PWR_WAKEUP_PIN5 (*) * @arg @ref LL_PWR_WAKEUP_PIN6 * @note (*) Availability depends on devices * @retval None */ __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) { SET_BIT(PWR->CR3, WakeUpPin); } /** * @brief Disable the WakeUp PINx functionality * @rmtoll CR3 EWUP1 LL_PWR_DisableWakeUpPin\n * CR3 EWUP2 LL_PWR_DisableWakeUpPin\n * CR3 EWUP3 LL_PWR_DisableWakeUpPin\n * CR3 EWUP4 LL_PWR_DisableWakeUpPin\n * CR3 EWUP5 LL_PWR_DisableWakeUpPin (*)\n * CR3 EWUP6 LL_PWR_DisableWakeUpPin * @param WakeUpPin This parameter can be one of the following values: * @arg @ref LL_PWR_WAKEUP_PIN1 * @arg @ref LL_PWR_WAKEUP_PIN2 * @arg @ref LL_PWR_WAKEUP_PIN3 * @arg @ref LL_PWR_WAKEUP_PIN4 * @arg @ref LL_PWR_WAKEUP_PIN5 (*) * @arg @ref LL_PWR_WAKEUP_PIN6 * @note (*) Availability depends on devices * @retval None */ __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) { CLEAR_BIT(PWR->CR3, WakeUpPin); } /** * @brief Check if the WakeUp PINx functionality is enabled * @rmtoll CR3 EWUP1 LL_PWR_IsEnabledWakeUpPin\n * CR3 EWUP2 LL_PWR_IsEnabledWakeUpPin\n * CR3 EWUP3 LL_PWR_IsEnabledWakeUpPin\n * CR3 EWUP4 LL_PWR_IsEnabledWakeUpPin\n * CR3 EWUP5 LL_PWR_IsEnabledWakeUpPin (*)\n * CR3 EWUP6 LL_PWR_IsEnabledWakeUpPin * @param WakeUpPin This parameter can be one of the following values: * @arg @ref LL_PWR_WAKEUP_PIN1 * @arg @ref LL_PWR_WAKEUP_PIN2 * @arg @ref LL_PWR_WAKEUP_PIN3 * @arg @ref LL_PWR_WAKEUP_PIN4 * @arg @ref LL_PWR_WAKEUP_PIN5 (*) * @arg @ref LL_PWR_WAKEUP_PIN6 * @note (*) Availability depends on devices * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) { return ((READ_BIT(PWR->CR3, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); } /** * @brief Set the Wake-Up pin polarity low for the event detection * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityLow\n * CR4 WP2 LL_PWR_SetWakeUpPinPolarityLow\n * CR4 WP3 LL_PWR_SetWakeUpPinPolarityLow\n * CR4 WP4 LL_PWR_SetWakeUpPinPolarityLow\n * CR4 WP5 LL_PWR_SetWakeUpPinPolarityLow (*)\n * CR4 WP6 LL_PWR_SetWakeUpPinPolarityLow\n * @param WakeUpPin This parameter can be one of the following values: * @arg @ref LL_PWR_WAKEUP_PIN1 * @arg @ref LL_PWR_WAKEUP_PIN2 * @arg @ref LL_PWR_WAKEUP_PIN3 * @arg @ref LL_PWR_WAKEUP_PIN4 * @arg @ref LL_PWR_WAKEUP_PIN5 (*) * @arg @ref LL_PWR_WAKEUP_PIN6 * @note (*) Availability depends on devices * @retval None */ __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin) { SET_BIT(PWR->CR4, WakeUpPin); } /** * @brief Set the Wake-Up pin polarity high for the event detection * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityHigh\n * CR4 WP2 LL_PWR_SetWakeUpPinPolarityHigh\n * CR4 WP3 LL_PWR_SetWakeUpPinPolarityHigh\n * CR4 WP4 LL_PWR_SetWakeUpPinPolarityHigh\n * CR4 WP5 LL_PWR_SetWakeUpPinPolarityHigh (*)\n * CR4 WP6 LL_PWR_SetWakeUpPinPolarityHigh * @param WakeUpPin This parameter can be one of the following values: * @arg @ref LL_PWR_WAKEUP_PIN1 * @arg @ref LL_PWR_WAKEUP_PIN2 * @arg @ref LL_PWR_WAKEUP_PIN3 * @arg @ref LL_PWR_WAKEUP_PIN4 * @arg @ref LL_PWR_WAKEUP_PIN5 (*) * @arg @ref LL_PWR_WAKEUP_PIN6 * @note (*) Availability depends on devices * @retval None */ __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin) { CLEAR_BIT(PWR->CR4, WakeUpPin); } /** * @brief Get the Wake-Up pin polarity for the event detection * @rmtoll CR4 WP1 LL_PWR_IsWakeUpPinPolarityLow\n * CR4 WP2 LL_PWR_IsWakeUpPinPolarityLow\n * CR4 WP3 LL_PWR_IsWakeUpPinPolarityLow\n * CR4 WP4 LL_PWR_IsWakeUpPinPolarityLow\n * CR4 WP5 LL_PWR_IsWakeUpPinPolarityLow (*)\n * CR4 WP6 LL_PWR_IsWakeUpPinPolarityLow * @param WakeUpPin This parameter can be one of the following values: * @arg @ref LL_PWR_WAKEUP_PIN1 * @arg @ref LL_PWR_WAKEUP_PIN2 * @arg @ref LL_PWR_WAKEUP_PIN3 * @arg @ref LL_PWR_WAKEUP_PIN4 * @arg @ref LL_PWR_WAKEUP_PIN5 (*) * @arg @ref LL_PWR_WAKEUP_PIN6 * @note (*) Availability depends on devices * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin) { return ((READ_BIT(PWR->CR4, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); } /** * @brief Enable GPIO pull-up state in Standby and Shutdown modes * @rmtoll PUCRA PU0-15 LL_PWR_EnableGPIOPullUp\n * PUCRB PU0-15 LL_PWR_EnableGPIOPullUp\n * PUCRC PU0-15 LL_PWR_EnableGPIOPullUp\n * PUCRD PU0-15 LL_PWR_EnableGPIOPullUp (*)\n * PUCRF PU0-15 LL_PWR_EnableGPIOPullUp * @note (*) Port D availability depends on devices * @param GPIO This parameter can be one of the following values: * @arg @ref LL_PWR_GPIO_A * @arg @ref LL_PWR_GPIO_B * @arg @ref LL_PWR_GPIO_C * @arg @ref LL_PWR_GPIO_D (*) * @arg @ref LL_PWR_GPIO_F * @note (*) Port D availability depends on devices * @param GPIONumber This parameter can be one of the following values: * @arg @ref LL_PWR_GPIO_BIT_0 * @arg @ref LL_PWR_GPIO_BIT_1 * @arg @ref LL_PWR_GPIO_BIT_2 * @arg @ref LL_PWR_GPIO_BIT_3 * @arg @ref LL_PWR_GPIO_BIT_4 * @arg @ref LL_PWR_GPIO_BIT_5 * @arg @ref LL_PWR_GPIO_BIT_6 * @arg @ref LL_PWR_GPIO_BIT_7 * @arg @ref LL_PWR_GPIO_BIT_8 * @arg @ref LL_PWR_GPIO_BIT_9 * @arg @ref LL_PWR_GPIO_BIT_10 * @arg @ref LL_PWR_GPIO_BIT_11 * @arg @ref LL_PWR_GPIO_BIT_12 * @arg @ref LL_PWR_GPIO_BIT_13 * @arg @ref LL_PWR_GPIO_BIT_14 * @arg @ref LL_PWR_GPIO_BIT_15 * @retval None */ __STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) { SET_BIT(*((__IO uint32_t *)GPIO), GPIONumber); } /** * @brief Disable GPIO pull-up state in Standby and Shutdown modes * @rmtoll PUCRA PU0-15 LL_PWR_DisableGPIOPullUp\n * PUCRB PU0-15 LL_PWR_DisableGPIOPullUp\n * PUCRC PU0-15 LL_PWR_DisableGPIOPullUp\n * PUCRD PU0-15 LL_PWR_DisableGPIOPullUp (*)\n * PUCRF PU0-15 LL_PWR_DisableGPIOPullUp * @note (*) Port D availability depends on devices * @param GPIO This parameter can be one of the following values: * @arg @ref LL_PWR_GPIO_A * @arg @ref LL_PWR_GPIO_B * @arg @ref LL_PWR_GPIO_C * @arg @ref LL_PWR_GPIO_D (*) * @arg @ref LL_PWR_GPIO_F * @param GPIONumber This parameter can be one of the following values: * @arg @ref LL_PWR_GPIO_BIT_0 * @arg @ref LL_PWR_GPIO_BIT_1 * @arg @ref LL_PWR_GPIO_BIT_2 * @arg @ref LL_PWR_GPIO_BIT_3 * @arg @ref LL_PWR_GPIO_BIT_4 * @arg @ref LL_PWR_GPIO_BIT_5 * @arg @ref LL_PWR_GPIO_BIT_6 * @arg @ref LL_PWR_GPIO_BIT_7 * @arg @ref LL_PWR_GPIO_BIT_8 * @arg @ref LL_PWR_GPIO_BIT_9 * @arg @ref LL_PWR_GPIO_BIT_10 * @arg @ref LL_PWR_GPIO_BIT_11 * @arg @ref LL_PWR_GPIO_BIT_12 * @arg @ref LL_PWR_GPIO_BIT_13 * @arg @ref LL_PWR_GPIO_BIT_14 * @arg @ref LL_PWR_GPIO_BIT_15 * @retval None */ __STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) { CLEAR_BIT(*((__IO uint32_t *)GPIO), GPIONumber); } /** * @brief Check if GPIO pull-up state is enabled * @rmtoll PUCRA PU0-15 LL_PWR_IsEnabledGPIOPullUp\n * PUCRB PU0-15 LL_PWR_IsEnabledGPIOPullUp\n * PUCRC PU0-15 LL_PWR_IsEnabledGPIOPullUp\n * PUCRD PU0-15 LL_PWR_IsEnabledGPIOPullUp (*)\n * PUCRF PU0-15 LL_PWR_IsEnabledGPIOPullUp * @note (*) Port D availability depends on devices * @param GPIO This parameter can be one of the following values: * @arg @ref LL_PWR_GPIO_A * @arg @ref LL_PWR_GPIO_B * @arg @ref LL_PWR_GPIO_C * @arg @ref LL_PWR_GPIO_D (*) * @arg @ref LL_PWR_GPIO_F * @note (*) Port D availability depends on devices * @param GPIONumber This parameter can be one of the following values: * @arg @ref LL_PWR_GPIO_BIT_0 * @arg @ref LL_PWR_GPIO_BIT_1 * @arg @ref LL_PWR_GPIO_BIT_2 * @arg @ref LL_PWR_GPIO_BIT_3 * @arg @ref LL_PWR_GPIO_BIT_4 * @arg @ref LL_PWR_GPIO_BIT_5 * @arg @ref LL_PWR_GPIO_BIT_6 * @arg @ref LL_PWR_GPIO_BIT_7 * @arg @ref LL_PWR_GPIO_BIT_8 * @arg @ref LL_PWR_GPIO_BIT_9 * @arg @ref LL_PWR_GPIO_BIT_10 * @arg @ref LL_PWR_GPIO_BIT_11 * @arg @ref LL_PWR_GPIO_BIT_12 * @arg @ref LL_PWR_GPIO_BIT_13 * @arg @ref LL_PWR_GPIO_BIT_14 * @arg @ref LL_PWR_GPIO_BIT_15 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) { return ((READ_BIT(*((__IO uint32_t *)GPIO), GPIONumber) == (GPIONumber)) ? 1UL : 0UL); } /** * @brief Enable GPIO pull-down state in Standby and Shutdown modes * @rmtoll PDCRA PD0-15 LL_PWR_EnableGPIOPullDown\n * PDCRB PD0-15 LL_PWR_EnableGPIOPullDown\n * PDCRC PD0-15 LL_PWR_EnableGPIOPullDown\n * PDCRD PD0-15 LL_PWR_EnableGPIOPullDown (*)\n * PDCRF PD0-15 LL_PWR_EnableGPIOPullDown * @note (*) Port D availability depends on devices * @param GPIO This parameter can be one of the following values: * @arg @ref LL_PWR_GPIO_A * @arg @ref LL_PWR_GPIO_B * @arg @ref LL_PWR_GPIO_C * @arg @ref LL_PWR_GPIO_D (*) * @arg @ref LL_PWR_GPIO_F * @param GPIONumber This parameter can be one of the following values: * @arg @ref LL_PWR_GPIO_BIT_0 * @arg @ref LL_PWR_GPIO_BIT_1 * @arg @ref LL_PWR_GPIO_BIT_2 * @arg @ref LL_PWR_GPIO_BIT_3 * @arg @ref LL_PWR_GPIO_BIT_4 * @arg @ref LL_PWR_GPIO_BIT_5 * @arg @ref LL_PWR_GPIO_BIT_6 * @arg @ref LL_PWR_GPIO_BIT_7 * @arg @ref LL_PWR_GPIO_BIT_8 * @arg @ref LL_PWR_GPIO_BIT_9 * @arg @ref LL_PWR_GPIO_BIT_10 * @arg @ref LL_PWR_GPIO_BIT_11 * @arg @ref LL_PWR_GPIO_BIT_12 * @arg @ref LL_PWR_GPIO_BIT_13 * @arg @ref LL_PWR_GPIO_BIT_14 * @arg @ref LL_PWR_GPIO_BIT_15 * @retval None */ __STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) { SET_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber); } /** * @brief Disable GPIO pull-down state in Standby and Shutdown modes * @rmtoll PDCRA PD0-15 LL_PWR_DisableGPIOPullDown\n * PDCRB PD0-15 LL_PWR_DisableGPIOPullDown\n * PDCRC PD0-15 LL_PWR_DisableGPIOPullDown\n * PDCRD PD0-15 LL_PWR_DisableGPIOPullDown (*)\n * PDCRF PD0-15 LL_PWR_DisableGPIOPullDown * @note (*) Port D availability depends on devices * @param GPIO This parameter can be one of the following values: * @arg @ref LL_PWR_GPIO_A * @arg @ref LL_PWR_GPIO_B * @arg @ref LL_PWR_GPIO_C * @arg @ref LL_PWR_GPIO_D (*) * @note (*) Port D availability depends on devices * @arg @ref LL_PWR_GPIO_F * @param GPIONumber This parameter can be one of the following values: * @arg @ref LL_PWR_GPIO_BIT_0 * @arg @ref LL_PWR_GPIO_BIT_1 * @arg @ref LL_PWR_GPIO_BIT_2 * @arg @ref LL_PWR_GPIO_BIT_3 * @arg @ref LL_PWR_GPIO_BIT_4 * @arg @ref LL_PWR_GPIO_BIT_5 * @arg @ref LL_PWR_GPIO_BIT_6 * @arg @ref LL_PWR_GPIO_BIT_7 * @arg @ref LL_PWR_GPIO_BIT_8 * @arg @ref LL_PWR_GPIO_BIT_9 * @arg @ref LL_PWR_GPIO_BIT_10 * @arg @ref LL_PWR_GPIO_BIT_11 * @arg @ref LL_PWR_GPIO_BIT_12 * @arg @ref LL_PWR_GPIO_BIT_13 * @arg @ref LL_PWR_GPIO_BIT_14 * @arg @ref LL_PWR_GPIO_BIT_15 * @retval None */ __STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) { CLEAR_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber); } /** * @brief Check if GPIO pull-down state is enabled * @rmtoll PDCRA PD0-15 LL_PWR_IsEnabledGPIOPullDown\n * PDCRB PD0-15 LL_PWR_IsEnabledGPIOPullDown\n * PDCRC PD0-15 LL_PWR_IsEnabledGPIOPullDown\n * PDCRD PD0-15 LL_PWR_IsEnabledGPIOPullDown (*)\n * @note (*) Port D availability depends on devices * PDCRF PD0-15 LL_PWR_IsEnabledGPIOPullDown * @param GPIO This parameter can be one of the following values: * @arg @ref LL_PWR_GPIO_A * @arg @ref LL_PWR_GPIO_B * @arg @ref LL_PWR_GPIO_C * @arg @ref LL_PWR_GPIO_D (*) * @arg @ref LL_PWR_GPIO_F * @note (*) Port D availability depends on devices * @param GPIONumber This parameter can be one of the following values: * @arg @ref LL_PWR_GPIO_BIT_0 * @arg @ref LL_PWR_GPIO_BIT_1 * @arg @ref LL_PWR_GPIO_BIT_2 * @arg @ref LL_PWR_GPIO_BIT_3 * @arg @ref LL_PWR_GPIO_BIT_4 * @arg @ref LL_PWR_GPIO_BIT_5 * @arg @ref LL_PWR_GPIO_BIT_6 * @arg @ref LL_PWR_GPIO_BIT_7 * @arg @ref LL_PWR_GPIO_BIT_8 * @arg @ref LL_PWR_GPIO_BIT_9 * @arg @ref LL_PWR_GPIO_BIT_10 * @arg @ref LL_PWR_GPIO_BIT_11 * @arg @ref LL_PWR_GPIO_BIT_12 * @arg @ref LL_PWR_GPIO_BIT_13 * @arg @ref LL_PWR_GPIO_BIT_14 * @arg @ref LL_PWR_GPIO_BIT_15 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) { return ((READ_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL); } /** * @} */ /** @defgroup PWR_LL_EF_Backup_Registers Backup_Registers * @{ */ /** * @brief Writes a data in a specified Backup data register. * @rmtoll PWR_BKPREGx BKP LL_PWR_BKP_SetRegister * @param BackupRegister This parameter can be one of the following values: * @arg @ref LL_PWR_BKP_DR0 * @arg @ref LL_PWR_BKP_DR1 * @arg @ref LL_PWR_BKP_DR2 * @arg @ref LL_PWR_BKP_DR3 * @param Data Value between Min_Data=0x00 and Max_Data=0xFFFF * @retval None */ __STATIC_INLINE void LL_PWR_BKP_SetRegister(uint32_t BackupRegister, uint16_t Data) { __IO uint32_t tmp; tmp = (uint32_t)(&(PWR->BKP0R)); tmp += (BackupRegister * 4U); /* Write the specified register */ *(__IO uint32_t *)tmp = (uint16_t)Data; } /** * @brief Reads data from the specified Backup data Register. * @rmtoll PWR_BKPREGx BKP LL_PWR_BKP_GetRegister * @param BackupRegister This parameter can be one of the following values: * @arg @ref LL_PWR_BKP_DR0 * @arg @ref LL_PWR_BKP_DR1 * @arg @ref LL_PWR_BKP_DR2 * @arg @ref LL_PWR_BKP_DR3 * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF */ __STATIC_INLINE uint32_t LL_PWR_BKP_GetRegister(uint32_t BackupRegister) { uint32_t tmp; tmp = (uint32_t)(&(PWR->BKP0R)); tmp += (BackupRegister * 4U); /* Read the specified register */ return (*(__IO uint32_t *)tmp); } /** * @} */ /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management * @{ */ /** * @brief Get Internal Wake-up line Flag * @rmtoll SR1 WUFI LL_PWR_IsActiveFlag_InternWU * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU(void) { return ((READ_BIT(PWR->SR1, PWR_SR1_WUFI) == (PWR_SR1_WUFI)) ? 1UL : 0UL); } /** * @brief Get Standby Flag * @rmtoll SR1 SBF LL_PWR_IsActiveFlag_SB * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) { return ((READ_BIT(PWR->SR1, PWR_SR1_SBF) == (PWR_SR1_SBF)) ? 1UL : 0UL); } /** * @brief Get Wake-up Flag 6 * @rmtoll SR1 WUF6 LL_PWR_IsActiveFlag_WU6 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void) { return ((READ_BIT(PWR->SR1, PWR_SR1_WUF6) == (PWR_SR1_WUF6)) ? 1UL : 0UL); } #if defined(PWR_CR3_EWUP5) /** * @brief Get Wake-up Flag 5 * @rmtoll SR1 WUF5 LL_PWR_IsActiveFlag_WU5 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void) { return ((READ_BIT(PWR->SR1, PWR_SR1_WUF5) == (PWR_SR1_WUF5)) ? 1UL : 0UL); } #endif /* PWR_CR3_EWUP5 */ /** * @brief Get Wake-up Flag 4 * @rmtoll SR1 WUF4 LL_PWR_IsActiveFlag_WU4 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void) { return ((READ_BIT(PWR->SR1, PWR_SR1_WUF4) == (PWR_SR1_WUF4)) ? 1UL : 0UL); } /** * @brief Get Wake-up Flag 3 * @rmtoll SR1 WUF3 LL_PWR_IsActiveFlag_WU3 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void) { return ((READ_BIT(PWR->SR1, PWR_SR1_WUF3) == (PWR_SR1_WUF3)) ? 1UL : 0UL); } /** * @brief Get Wake-up Flag 2 * @rmtoll SR1 WUF2 LL_PWR_IsActiveFlag_WU2 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void) { return ((READ_BIT(PWR->SR1, PWR_SR1_WUF2) == (PWR_SR1_WUF2)) ? 1UL : 0UL); } /** * @brief Get Wake-up Flag 1 * @rmtoll SR1 WUF1 LL_PWR_IsActiveFlag_WU1 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void) { return ((READ_BIT(PWR->SR1, PWR_SR1_WUF1) == (PWR_SR1_WUF1)) ? 1UL : 0UL); } /** * @brief Clear Standby Flag * @rmtoll SCR CSBF LL_PWR_ClearFlag_SB * @retval None */ __STATIC_INLINE void LL_PWR_ClearFlag_SB(void) { WRITE_REG(PWR->SCR, PWR_SCR_CSBF); } /** * @brief Clear Wake-up Flags * @rmtoll SCR CWUF LL_PWR_ClearFlag_WU * @retval None */ __STATIC_INLINE void LL_PWR_ClearFlag_WU(void) { WRITE_REG(PWR->SCR, PWR_SCR_CWUF); } /** * @brief Clear Wake-up Flag 6 * @rmtoll SCR CWUF6 LL_PWR_ClearFlag_WU6 * @retval None */ __STATIC_INLINE void LL_PWR_ClearFlag_WU6(void) { WRITE_REG(PWR->SCR, PWR_SCR_CWUF6); } #if defined(PWR_CR3_EWUP5) /** * @brief Clear Wake-up Flag 5 * @rmtoll SCR CWUF5 LL_PWR_ClearFlag_WU5 * @retval None */ __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void) { WRITE_REG(PWR->SCR, PWR_SCR_CWUF5); } #endif /* PWR_CR3_EWUP5 */ /** * @brief Clear Wake-up Flag 4 * @rmtoll SCR CWUF4 LL_PWR_ClearFlag_WU4 * @retval None */ __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void) { WRITE_REG(PWR->SCR, PWR_SCR_CWUF4); } /** * @brief Clear Wake-up Flag 3 * @rmtoll SCR CWUF3 LL_PWR_ClearFlag_WU3 * @retval None */ __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void) { WRITE_REG(PWR->SCR, PWR_SCR_CWUF3); } /** * @brief Clear Wake-up Flag 2 * @rmtoll SCR CWUF2 LL_PWR_ClearFlag_WU2 * @retval None */ __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void) { WRITE_REG(PWR->SCR, PWR_SCR_CWUF2); } /** * @brief Clear Wake-up Flag 1 * @rmtoll SCR CWUF1 LL_PWR_ClearFlag_WU1 * @retval None */ __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void) { WRITE_REG(PWR->SCR, PWR_SCR_CWUF1); } #if defined (PWR_PVM_SUPPORT) /** * @brief Indicate whether VDD voltage is below or above the selected PVD * threshold * @rmtoll SR2 PVDMO_USB LL_PWR_IsActiveFlag_PVMOUSB * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMOUSB(void) { return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO_VDDIO2) == (PWR_SR2_PVMO_VDDIO2)) ? 1UL : 0UL); } #endif /* PWR_PVM_SUPPORT */ /** * @brief Indicate whether or not the flash is ready to be accessed * @rmtoll SR2 FLASH_RDY LL_PWR_IsActiveFlag_FLASH_RDY * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_FLASH_RDY(void) { return ((READ_BIT(PWR->SR2, PWR_SR2_FLASH_RDY) == (PWR_SR2_FLASH_RDY)) ? 1UL : 0UL); } /** * @} */ #if defined(USE_FULL_LL_DRIVER) /** @defgroup PWR_LL_EF_Init De-initialization function * @{ */ ErrorStatus LL_PWR_DeInit(void); /** * @} */ #endif /* USE_FULL_LL_DRIVER */ /** * @} */ /** * @} */ #endif /* defined(PWR) */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32C0xx_LL_PWR_H */