1/* 2 * Copyright (c) 2024 STMicroelectronics 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 8#include <arm/armv6-m.dtsi> 9#include <zephyr/dt-bindings/clock/stm32u0_clock.h> 10#include <zephyr/dt-bindings/gpio/gpio.h> 11#include <zephyr/dt-bindings/adc/adc.h> 12#include <zephyr/dt-bindings/adc/stm32l4_adc.h> 13#include <zephyr/dt-bindings/pwm/pwm.h> 14#include <zephyr/dt-bindings/pwm/stm32_pwm.h> 15#include <zephyr/dt-bindings/dma/stm32_dma.h> 16#include <zephyr/dt-bindings/i2c/i2c.h> 17#include <zephyr/dt-bindings/reset/stm32u0_reset.h> 18#include <freq.h> 19 20/ { 21 chosen { 22 zephyr,flash-controller = &flash; 23 zephyr,entropy = &rng; 24 }; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 cpu0: cpu@0 { 31 device_type = "cpu"; 32 compatible = "arm,cortex-m0+"; 33 reg = <0>; 34 #address-cells = <1>; 35 #size-cells = <1>; 36 }; 37 }; 38 39 sram0: memory@20000000 { 40 compatible = "mmio-sram"; 41 }; 42 43 clocks { 44 clk_hse: clk-hse { 45 #clock-cells = <0>; 46 compatible = "st,stm32-hse-clock"; 47 status = "disabled"; 48 }; 49 50 clk_hsi: clk-hsi { 51 #clock-cells = <0>; 52 compatible = "fixed-clock"; 53 clock-frequency = <DT_FREQ_M(16)>; 54 status = "disabled"; 55 }; 56 57 clk_hsi48: clk-hsi48 { 58 #clock-cells = <0>; 59 compatible = "fixed-clock"; 60 clock-frequency = <DT_FREQ_M(48)>; 61 status = "disabled"; 62 }; 63 64 clk_msi: clk-msi { 65 #clock-cells = <0>; 66 compatible = "st,stm32-msi-clock"; 67 msi-range = <4>; /* 4MHz (reset value) */ 68 status = "disabled"; 69 }; 70 71 clk_lse: clk-lse { 72 #clock-cells = <0>; 73 compatible = "st,stm32-lse-clock"; 74 clock-frequency = <32768>; 75 driving-capability = <2>; 76 status = "disabled"; 77 }; 78 79 clk_lsi: clk-lsi { 80 #clock-cells = <0>; 81 compatible = "fixed-clock"; 82 clock-frequency = <DT_FREQ_K(32)>; 83 status = "disabled"; 84 }; 85 86 pll: pll { 87 #clock-cells = <0>; 88 compatible = "st,stm32u0-pll-clock"; 89 status = "disabled"; 90 }; 91 }; 92 93 soc { 94 flash: flash-controller@40022000 { 95 compatible = "st,stm32-flash-controller", "st,stm32g0-flash-controller"; 96 reg = <0x40022000 0x400>; 97 interrupts = <3 0>; 98 99 #address-cells = <1>; 100 #size-cells = <1>; 101 102 flash0: flash@8000000 { 103 compatible = "st,stm32-nv-flash", "soc-nv-flash"; 104 105 write-block-size = <8>; 106 erase-block-size = <2048>; 107 /* maximum erase time(ms) for a 2K sector */ 108 max-erase-time = <40>; 109 }; 110 }; 111 112 rcc: rcc@40021000 { 113 compatible = "st,stm32f0-rcc"; 114 clocks-controller; 115 #clock-cells = <2>; 116 reg = <0x40021000 0x400>; 117 118 rctl: reset-controller { 119 compatible = "st,stm32-rcc-rctl"; 120 #reset-cells = <1>; 121 }; 122 }; 123 124 exti: interrupt-controller@40021800 { 125 compatible = "st,stm32g0-exti","st,stm32-exti"; 126 interrupt-controller; 127 #interrupt-cells = <1>; 128 #address-cells = <1>; 129 reg = <0x40021800 0x400>; 130 num-lines = <16>; 131 interrupts = <5 0>, <6 0>, <7 0>; 132 interrupt-names = "line0-1", "line2-3", "line4-15"; 133 line-ranges = <0 2>, <2 2>, <4 12>; 134 }; 135 136 pinctrl: pin-controller@50000000 { 137 compatible = "st,stm32-pinctrl"; 138 #address-cells = <1>; 139 #size-cells = <1>; 140 reg = <0x50000000 0x2000>; 141 142 gpioa: gpio@50000000 { 143 compatible = "st,stm32-gpio"; 144 gpio-controller; 145 #gpio-cells = <2>; 146 reg = <0x50000000 0x400>; 147 clocks = <&rcc STM32_CLOCK(IOP, 0U)>; 148 }; 149 150 gpiob: gpio@50000400 { 151 compatible = "st,stm32-gpio"; 152 gpio-controller; 153 #gpio-cells = <2>; 154 reg = <0x50000400 0x400>; 155 clocks = <&rcc STM32_CLOCK(IOP, 1U)>; 156 }; 157 158 gpioc: gpio@50000800 { 159 compatible = "st,stm32-gpio"; 160 gpio-controller; 161 #gpio-cells = <2>; 162 reg = <0x50000800 0x400>; 163 clocks = <&rcc STM32_CLOCK(IOP, 2U)>; 164 }; 165 166 gpiod: gpio@50000C00 { 167 compatible = "st,stm32-gpio"; 168 gpio-controller; 169 #gpio-cells = <2>; 170 reg = <0x50000C00 0x400>; 171 clocks = <&rcc STM32_CLOCK(IOP, 3U)>; 172 }; 173 174 gpioe: gpio@50001000 { 175 compatible = "st,stm32-gpio"; 176 gpio-controller; 177 #gpio-cells = <2>; 178 reg = <0x50001000 0x400>; 179 clocks = <&rcc STM32_CLOCK(IOP, 4U)>; 180 }; 181 182 gpiof: gpio@50001400 { 183 compatible = "st,stm32-gpio"; 184 gpio-controller; 185 #gpio-cells = <2>; 186 reg = <0x50001400 0x400>; 187 clocks = <&rcc STM32_CLOCK(IOP, 5U)>; 188 }; 189 }; 190 191 usart1: serial@40013800 { 192 compatible = "st,stm32-usart", "st,stm32-uart"; 193 reg = <0x40013800 0x400>; 194 clocks = <&rcc STM32_CLOCK(APB1_2, 14U)>; 195 resets = <&rctl STM32_RESET(APB1H, 14U)>; 196 interrupts = <27 0>; 197 status = "disabled"; 198 }; 199 200 usart2: serial@40004400 { 201 compatible = "st,stm32-usart", "st,stm32-uart"; 202 reg = <0x40004400 0x400>; 203 clocks = <&rcc STM32_CLOCK(APB1, 17U)>; 204 resets = <&rctl STM32_RESET(APB1L, 17U)>; 205 interrupts = <28 0>; 206 status = "disabled"; 207 }; 208 209 usart3: serial@40004800 { 210 compatible = "st,stm32-usart", "st,stm32-uart"; 211 reg = <0x40004800 0x400>; 212 clocks = <&rcc STM32_CLOCK(APB1, 18U)>; 213 resets = <&rctl STM32_RESET(APB1L, 18U)>; 214 interrupts = <29 0>; 215 status = "disabled"; 216 }; 217 218 lpuart1: serial@40008000 { 219 compatible = "st,stm32-lpuart", "st,stm32-uart"; 220 reg = <0x40008000 0x400>; 221 clocks = <&rcc STM32_CLOCK(APB1, 20U)>; 222 resets = <&rctl STM32_RESET(APB1L, 20U)>; 223 interrupts = <28 0>; 224 status = "disabled"; 225 }; 226 227 lpuart2: serial@40008400 { 228 compatible = "st,stm32-lpuart", "st,stm32-uart"; 229 reg = <0x40008400 0x400>; 230 clocks = <&rcc STM32_CLOCK(APB1, 7U)>; 231 resets = <&rctl STM32_RESET(APB1L, 7U)>; 232 interrupts = <29 0>; 233 status = "disabled"; 234 }; 235 236 iwdg: watchdog@40003000 { 237 compatible = "st,stm32-watchdog"; 238 reg = <0x40003000 0x400>; 239 status = "disabled"; 240 }; 241 242 wwdg: watchdog@40002c00 { 243 compatible = "st,stm32-window-watchdog"; 244 reg = <0x40002c00 0x400>; 245 clocks = <&rcc STM32_CLOCK(APB1, 11U)>; 246 interrupts = <0 7>; 247 status = "disabled"; 248 }; 249 250 adc1: adc@40012400 { 251 compatible = "st,stm32-adc"; 252 reg = <0x40012400 0x400>; 253 clocks = <&rcc STM32_CLOCK(APB1_2, 20U)>; 254 interrupts = <12 0>; 255 status = "disabled"; 256 #io-channel-cells = <1>; 257 resolutions = <STM32_ADC_RES(12, 0x00) 258 STM32_ADC_RES(10, 0x01) 259 STM32_ADC_RES(8, 0x02) 260 STM32_ADC_RES(6, 0x03)>; 261 sampling-times = <2 4 8 13 20 40 80 161>; 262 num-sampling-time-common-channels = <2>; 263 st,adc-sequencer = "NOT_FULLY_CONFIGURABLE"; 264 st,adc-oversampler = "OVERSAMPLER_MINIMAL"; 265 }; 266 267 dac1: dac@40007400 { 268 compatible = "st,stm32-dac"; 269 reg = <0x40007400 0x400>; 270 clocks = <&rcc STM32_CLOCK(APB1, 29U)>; 271 status = "disabled"; 272 #io-channel-cells = <1>; 273 }; 274 275 i2c1: i2c@40005400 { 276 compatible = "st,stm32-i2c-v2"; 277 clock-frequency = <I2C_BITRATE_STANDARD>; 278 #address-cells = <1>; 279 #size-cells = <0>; 280 reg = <0x40005400 0x400>; 281 clocks = <&rcc STM32_CLOCK(APB1, 21U)>; 282 interrupts = <23 0>; 283 interrupt-names = "combined"; 284 status = "disabled"; 285 }; 286 287 i2c2: i2c@40005800 { 288 compatible = "st,stm32-i2c-v2"; 289 clock-frequency = <I2C_BITRATE_STANDARD>; 290 #address-cells = <1>; 291 #size-cells = <0>; 292 reg = <0x40005800 0x400>; 293 clocks = <&rcc STM32_CLOCK(APB1, 22U)>; 294 interrupts = <24 0>; 295 interrupt-names = "combined"; 296 status = "disabled"; 297 }; 298 299 i2c3: i2c@40008800 { 300 compatible = "st,stm32-i2c-v2"; 301 clock-frequency = <I2C_BITRATE_STANDARD>; 302 #address-cells = <1>; 303 #size-cells = <0>; 304 reg = <0x40008800 0x400>; 305 clocks = <&rcc STM32_CLOCK(APB1, 23U)>; 306 interrupts = <24 0>; 307 interrupt-names = "combined"; 308 status = "disabled"; 309 }; 310 311 dma1: dma@40020000 { 312 compatible = "st,stm32-dma-v2"; 313 #dma-cells = <3>; 314 reg = <0x40020000 0x400>; 315 interrupts = <9 0 10 0 10 0 11 0 11 0 11 0 11 0>; 316 clocks = <&rcc STM32_CLOCK(AHB1, 0U)>; 317 dma-requests = <7>; 318 dma-offset = <0>; 319 status = "disabled"; 320 }; 321 322 dmamux1: dmamux@40020800 { 323 compatible = "st,stm32-dmamux"; 324 #dma-cells = <3>; 325 reg = <0x40020800 0x400>; 326 interrupts = <11 0>; 327 dma-channels = <7>; 328 dma-generators = <4>; 329 dma-requests= <76>; 330 status = "disabled"; 331 }; 332 333 spi1: spi@40013000 { 334 compatible = "st,stm32-spi-fifo", "st,stm32-spi"; 335 #address-cells = <1>; 336 #size-cells = <0>; 337 reg = <0x40013000 0x400>; 338 clocks = <&rcc STM32_CLOCK(APB1_2, 12U)>; 339 interrupts = <25 0>; 340 status = "disabled"; 341 }; 342 343 spi2: spi@40003800 { 344 compatible = "st,stm32-spi-fifo", "st,stm32-spi"; 345 #address-cells = <1>; 346 #size-cells = <0>; 347 reg = <0x40003800 0x400>; 348 clocks = <&rcc STM32_CLOCK(APB1, 14U)>; 349 interrupts = <26 0>; 350 status = "disabled"; 351 }; 352 353 spi3: spi@40003c00 { 354 compatible = "st,stm32-spi-fifo", "st,stm32-spi"; 355 #address-cells = <1>; 356 #size-cells = <0>; 357 reg = <0x40003c00 0x400>; 358 clocks = <&rcc STM32_CLOCK(APB1, 15U)>; 359 interrupts = <26 0>; 360 status = "disabled"; 361 }; 362 363 rng: rng@40025000 { 364 compatible = "st,stm32-rng"; 365 reg = <0x40025000 0x400>; 366 clocks = <&rcc STM32_CLOCK(AHB1, 18U)>; 367 interrupts = <31 0>; 368 status = "disabled"; 369 }; 370 371 aes: aes@40026000 { 372 compatible = "st,stm32-aes"; 373 reg = <0x40026000 0x400>; 374 clocks = <&rcc STM32_CLOCK(AHB1, 16U)>; 375 resets = <&rctl STM32_RESET(AHB1, 16U)>; 376 interrupts = <31 0>; 377 interrupt-names = "aes"; 378 status = "disabled"; 379 }; 380 381 rtc: rtc@40002800 { 382 compatible = "st,stm32-rtc"; 383 reg = <0x40002800 0x400>; 384 interrupts = <2 0>; 385 clocks = <&rcc STM32_CLOCK(APB1, 10U)>; 386 prescaler = <32768>; 387 alarms-count = <2>; 388 alrm-exti-line = <28>; 389 status = "disabled"; 390 }; 391 392 timers1: timers@40012c00 { 393 compatible = "st,stm32-timers"; 394 reg = <0x40012C00 0x400>; 395 clocks = <&rcc STM32_CLOCK(APB1_2, 11U)>; 396 resets = <&rctl STM32_RESET(APB1H, 11U)>; 397 interrupts = <13 0>, <14 0>; 398 interrupt-names = "brk_up_trg_com", "cc"; 399 st,prescaler = <0>; 400 status = "disabled"; 401 402 pwm { 403 compatible = "st,stm32-pwm"; 404 status = "disabled"; 405 #pwm-cells = <3>; 406 }; 407 408 counter { 409 compatible = "st,stm32-counter"; 410 status = "disabled"; 411 }; 412 }; 413 414 timers2: timers@40000000 { 415 compatible = "st,stm32-timers"; 416 reg = <0x40000000 0x400>; 417 clocks = <&rcc STM32_CLOCK(APB1, 0U)>; 418 resets = <&rctl STM32_RESET(APB1L, 0U)>; 419 interrupts = <15 0>; 420 interrupt-names = "global"; 421 st,prescaler = <0>; 422 status = "disabled"; 423 424 pwm { 425 compatible = "st,stm32-pwm"; 426 status = "disabled"; 427 #pwm-cells = <3>; 428 }; 429 430 counter { 431 compatible = "st,stm32-counter"; 432 status = "disabled"; 433 }; 434 }; 435 436 timers3: timers@40000400 { 437 compatible = "st,stm32-timers"; 438 reg = <0x40000400 0x400>; 439 clocks = <&rcc STM32_CLOCK(APB1, 1U)>; 440 resets = <&rctl STM32_RESET(APB1L, 1U)>; 441 interrupts = <16 0>; 442 interrupt-names = "global"; 443 st,prescaler = <0>; 444 status = "disabled"; 445 446 pwm { 447 compatible = "st,stm32-pwm"; 448 status = "disabled"; 449 #pwm-cells = <3>; 450 }; 451 452 counter { 453 compatible = "st,stm32-counter"; 454 status = "disabled"; 455 }; 456 }; 457 458 timers6: timers@40001000 { 459 compatible = "st,stm32-timers"; 460 reg = <0x40001000 0x400>; 461 clocks = <&rcc STM32_CLOCK(APB1, 4U)>; 462 resets = <&rctl STM32_RESET(APB1L, 4U)>; 463 interrupts = <17 0>; 464 interrupt-names = "combined"; 465 st,prescaler = <0>; 466 status = "disabled"; 467 }; 468 469 timers7: timers@40001400 { 470 compatible = "st,stm32-timers"; 471 reg = <0x40001400 0x400>; 472 clocks = <&rcc STM32_CLOCK(APB1, 5U)>; 473 resets = <&rctl STM32_RESET(APB1L, 5U)>; 474 interrupts = <18 0>; 475 interrupt-names = "combined"; 476 st,prescaler = <0>; 477 status = "disabled"; 478 }; 479 480 timers15: timers@40014000 { 481 compatible = "st,stm32-timers"; 482 reg = <0x40014000 0x400>; 483 clocks = <&rcc STM32_CLOCK(APB1_2, 16U)>; 484 resets = <&rctl STM32_RESET(APB1H, 16U)>; 485 interrupts = <19 0>; 486 interrupt-names = "combined"; 487 st,prescaler = <0>; 488 status = "disabled"; 489 490 pwm { 491 compatible = "st,stm32-pwm"; 492 status = "disabled"; 493 #pwm-cells = <3>; 494 }; 495 496 counter { 497 compatible = "st,stm32-counter"; 498 status = "disabled"; 499 }; 500 }; 501 502 timers16: timers@40014400 { 503 compatible = "st,stm32-timers"; 504 reg = <0x40014400 0x400>; 505 clocks = <&rcc STM32_CLOCK(APB1_2, 17U)>; 506 resets = <&rctl STM32_RESET(APB1H, 17U)>; 507 interrupts = <20 0>; 508 interrupt-names = "global"; 509 st,prescaler = <0>; 510 status = "disabled"; 511 512 pwm { 513 compatible = "st,stm32-pwm"; 514 status = "disabled"; 515 #pwm-cells = <3>; 516 }; 517 518 counter { 519 compatible = "st,stm32-counter"; 520 status = "disabled"; 521 }; 522 }; 523 524 lptim1: timers@40007c00 { 525 compatible = "st,stm32-lptim"; 526 clocks = <&rcc STM32_CLOCK(APB1, 31U)>; 527 #address-cells = <1>; 528 #size-cells = <0>; 529 reg = <0x40007c00 0x400>; 530 interrupts = <17 1>; 531 interrupt-names = "combined"; 532 status = "disabled"; 533 534 }; 535 536 lptim2: timers@40009400 { 537 compatible = "st,stm32-lptim"; 538 clocks = <&rcc STM32_CLOCK(APB1, 30U)>; 539 #address-cells = <1>; 540 #size-cells = <0>; 541 reg = <0x40009400 0x400>; 542 interrupts = <18 1>; 543 interrupt-names = "combined"; 544 status = "disabled"; 545 }; 546 }; 547}; 548 549&nvic { 550 arm,num-irq-priority-bits = <2>; 551}; 552
