/*
 * Copyright (c) 2024 STMicroelectronics
 *
 * SPDX-License-Identifier: Apache-2.0
 */


#include <arm/armv6-m.dtsi>
#include <zephyr/dt-bindings/clock/stm32u0_clock.h>
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/adc/adc.h>
#include <zephyr/dt-bindings/adc/stm32l4_adc.h>
#include <zephyr/dt-bindings/pwm/pwm.h>
#include <zephyr/dt-bindings/pwm/stm32_pwm.h>
#include <zephyr/dt-bindings/dma/stm32_dma.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/reset/stm32u0_reset.h>
#include <freq.h>

/ {
	chosen {
		zephyr,flash-controller = &flash;
		zephyr,entropy = &rng;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-m0+";
			reg = <0>;
			#address-cells = <1>;
			#size-cells = <1>;
		};
	};

	sram0: memory@20000000 {
		compatible = "mmio-sram";
	};

	clocks {
		clk_hse: clk-hse {
			#clock-cells = <0>;
			compatible = "st,stm32-hse-clock";
			status = "disabled";
		};

		clk_hsi: clk-hsi {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <DT_FREQ_M(16)>;
			status = "disabled";
		};

		clk_hsi48: clk-hsi48 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <DT_FREQ_M(48)>;
			status = "disabled";
		};

		clk_msi: clk-msi {
			#clock-cells = <0>;
			compatible = "st,stm32-msi-clock";
			msi-range = <4>; /* 4MHz (reset value) */
			status = "disabled";
		};

		clk_lse: clk-lse {
			#clock-cells = <0>;
			compatible = "st,stm32-lse-clock";
			clock-frequency = <32768>;
			driving-capability = <2>;
			status = "disabled";
		};

		clk_lsi: clk-lsi {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <DT_FREQ_K(32)>;
			status = "disabled";
		};

		pll: pll {
			#clock-cells = <0>;
			compatible = "st,stm32u0-pll-clock";
			status = "disabled";
		};
	};

	soc {
		flash: flash-controller@40022000 {
			compatible = "st,stm32-flash-controller", "st,stm32g0-flash-controller";
			reg = <0x40022000 0x400>;
			interrupts = <3 0>;

			#address-cells = <1>;
			#size-cells = <1>;

			flash0: flash@8000000 {
				compatible = "st,stm32-nv-flash", "soc-nv-flash";

				write-block-size = <8>;
				erase-block-size = <2048>;
				/* maximum erase time(ms) for a 2K sector */
				max-erase-time = <40>;
			};
		};

		rcc: rcc@40021000 {
			compatible = "st,stm32f0-rcc";
			clocks-controller;
			#clock-cells = <2>;
			reg = <0x40021000 0x400>;

			rctl: reset-controller {
				compatible = "st,stm32-rcc-rctl";
				#reset-cells = <1>;
			};
		};

		exti: interrupt-controller@40021800 {
			compatible = "st,stm32g0-exti","st,stm32-exti";
			interrupt-controller;
			#interrupt-cells = <1>;
			#address-cells = <1>;
			reg = <0x40021800 0x400>;
			num-lines = <16>;
			interrupts = <5 0>, <6 0>, <7 0>;
			interrupt-names = "line0-1", "line2-3", "line4-15";
			line-ranges = <0 2>, <2 2>, <4 12>;
		};

		pinctrl: pin-controller@50000000 {
			compatible = "st,stm32-pinctrl";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x50000000 0x2000>;

			gpioa: gpio@50000000 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x50000000 0x400>;
				clocks = <&rcc STM32_CLOCK(IOP, 0U)>;
			};

			gpiob: gpio@50000400 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x50000400 0x400>;
				clocks = <&rcc STM32_CLOCK(IOP, 1U)>;
			};

			gpioc: gpio@50000800 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x50000800 0x400>;
				clocks = <&rcc STM32_CLOCK(IOP, 2U)>;
			};

			gpiod: gpio@50000C00 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x50000C00 0x400>;
				clocks = <&rcc STM32_CLOCK(IOP, 3U)>;
			};

			gpioe: gpio@50001000 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x50001000 0x400>;
				clocks = <&rcc STM32_CLOCK(IOP, 4U)>;
			};

			gpiof: gpio@50001400 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x50001400 0x400>;
				clocks = <&rcc STM32_CLOCK(IOP, 5U)>;
			};
		};

		usart1: serial@40013800 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40013800 0x400>;
			clocks = <&rcc STM32_CLOCK(APB1_2, 14U)>;
			resets = <&rctl STM32_RESET(APB1H, 14U)>;
			interrupts = <27 0>;
			status = "disabled";
		};

		usart2: serial@40004400 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40004400 0x400>;
			clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
			resets = <&rctl STM32_RESET(APB1L, 17U)>;
			interrupts = <28 0>;
			status = "disabled";
		};

		usart3: serial@40004800 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40004800 0x400>;
			clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
			resets = <&rctl STM32_RESET(APB1L, 18U)>;
			interrupts = <29 0>;
			status = "disabled";
		};

		lpuart1: serial@40008000 {
			compatible = "st,stm32-lpuart", "st,stm32-uart";
			reg = <0x40008000 0x400>;
			clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
			resets = <&rctl STM32_RESET(APB1L, 20U)>;
			interrupts = <28 0>;
			status = "disabled";
		};

		lpuart2: serial@40008400 {
			compatible = "st,stm32-lpuart", "st,stm32-uart";
			reg = <0x40008400 0x400>;
			clocks = <&rcc STM32_CLOCK(APB1, 7U)>;
			resets = <&rctl STM32_RESET(APB1L, 7U)>;
			interrupts = <29 0>;
			status = "disabled";
		};

		iwdg: watchdog@40003000 {
			compatible = "st,stm32-watchdog";
			reg = <0x40003000 0x400>;
			status = "disabled";
		};

		wwdg: watchdog@40002c00 {
			compatible = "st,stm32-window-watchdog";
			reg = <0x40002c00 0x400>;
			clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
			interrupts = <0 7>;
			status = "disabled";
		};

		adc1: adc@40012400 {
			compatible = "st,stm32-adc";
			reg = <0x40012400 0x400>;
			clocks = <&rcc STM32_CLOCK(APB1_2, 20U)>;
			interrupts = <12 0>;
			status = "disabled";
			#io-channel-cells = <1>;
			resolutions = <STM32_ADC_RES(12, 0x00)
				       STM32_ADC_RES(10, 0x01)
				       STM32_ADC_RES(8, 0x02)
				       STM32_ADC_RES(6, 0x03)>;
			sampling-times = <2 4 8 13 20 40 80 161>;
			num-sampling-time-common-channels = <2>;
			st,adc-sequencer = "NOT_FULLY_CONFIGURABLE";
			st,adc-oversampler = "OVERSAMPLER_MINIMAL";
		};

		dac1: dac@40007400 {
			compatible = "st,stm32-dac";
			reg = <0x40007400 0x400>;
			clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
			status = "disabled";
			#io-channel-cells = <1>;
		};

		i2c1: i2c@40005400 {
			compatible = "st,stm32-i2c-v2";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40005400 0x400>;
			clocks = <&rcc STM32_CLOCK(APB1, 21U)>;
			interrupts = <23 0>;
			interrupt-names = "combined";
			status = "disabled";
		};

		i2c2: i2c@40005800 {
			compatible = "st,stm32-i2c-v2";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40005800 0x400>;
			clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
			interrupts = <24 0>;
			interrupt-names = "combined";
			status = "disabled";
		};

		i2c3: i2c@40008800 {
			compatible = "st,stm32-i2c-v2";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40008800 0x400>;
			clocks = <&rcc STM32_CLOCK(APB1, 23U)>;
			interrupts = <24 0>;
			interrupt-names = "combined";
			status = "disabled";
		};

		dma1: dma@40020000 {
			compatible = "st,stm32-dma-v2";
			#dma-cells = <3>;
			reg = <0x40020000 0x400>;
			interrupts = <9 0 10 0 10 0 11 0 11 0 11 0 11 0>;
			clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;
			dma-requests = <7>;
			dma-offset = <0>;
			status = "disabled";
		};

		dmamux1: dmamux@40020800 {
			compatible = "st,stm32-dmamux";
			#dma-cells = <3>;
			reg = <0x40020800 0x400>;
			interrupts = <11 0>;
			dma-channels = <7>;
			dma-generators = <4>;
			dma-requests= <76>;
			status = "disabled";
		};

		spi1: spi@40013000 {
			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40013000 0x400>;
			clocks = <&rcc STM32_CLOCK(APB1_2, 12U)>;
			interrupts = <25 0>;
			status = "disabled";
		};

		spi2: spi@40003800 {
			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40003800 0x400>;
			clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
			interrupts = <26 0>;
			status = "disabled";
		};

		spi3: spi@40003c00 {
			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40003c00 0x400>;
			clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
			interrupts = <26 0>;
			status = "disabled";
		};

		rng: rng@40025000 {
			compatible = "st,stm32-rng";
			reg = <0x40025000 0x400>;
			clocks = <&rcc STM32_CLOCK(AHB1, 18U)>;
			interrupts = <31 0>;
			status = "disabled";
		};

		aes: aes@40026000 {
			compatible = "st,stm32-aes";
			reg = <0x40026000 0x400>;
			clocks = <&rcc STM32_CLOCK(AHB1, 16U)>;
			resets = <&rctl STM32_RESET(AHB1, 16U)>;
			interrupts = <31 0>;
			interrupt-names = "aes";
			status = "disabled";
		};

		rtc: rtc@40002800 {
			compatible = "st,stm32-rtc";
			reg = <0x40002800 0x400>;
			interrupts = <2 0>;
			clocks = <&rcc STM32_CLOCK(APB1, 10U)>;
			prescaler = <32768>;
			alarms-count = <2>;
			alrm-exti-line = <28>;
			status = "disabled";
		};

		timers1: timers@40012c00 {
			compatible = "st,stm32-timers";
			reg = <0x40012C00 0x400>;
			clocks = <&rcc STM32_CLOCK(APB1_2, 11U)>;
			resets = <&rctl STM32_RESET(APB1H, 11U)>;
			interrupts = <13 0>, <14 0>;
			interrupt-names = "brk_up_trg_com", "cc";
			st,prescaler = <0>;
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};

			counter {
				compatible = "st,stm32-counter";
				status = "disabled";
			};
		};

		timers2: timers@40000000 {
			compatible = "st,stm32-timers";
			reg = <0x40000000 0x400>;
			clocks = <&rcc STM32_CLOCK(APB1, 0U)>;
			resets = <&rctl STM32_RESET(APB1L, 0U)>;
			interrupts = <15 0>;
			interrupt-names = "global";
			st,prescaler = <0>;
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};

			counter {
				compatible = "st,stm32-counter";
				status = "disabled";
			};
		};

		timers3: timers@40000400 {
			compatible = "st,stm32-timers";
			reg = <0x40000400 0x400>;
			clocks = <&rcc STM32_CLOCK(APB1, 1U)>;
			resets = <&rctl STM32_RESET(APB1L, 1U)>;
			interrupts = <16 0>;
			interrupt-names = "global";
			st,prescaler = <0>;
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};

			counter {
				compatible = "st,stm32-counter";
				status = "disabled";
			};
		};

		timers6: timers@40001000 {
			compatible = "st,stm32-timers";
			reg = <0x40001000 0x400>;
			clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
			resets = <&rctl STM32_RESET(APB1L, 4U)>;
			interrupts = <17 0>;
			interrupt-names = "combined";
			st,prescaler = <0>;
			status = "disabled";
		};

		timers7: timers@40001400 {
			compatible = "st,stm32-timers";
			reg = <0x40001400 0x400>;
			clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
			resets = <&rctl STM32_RESET(APB1L, 5U)>;
			interrupts = <18 0>;
			interrupt-names = "combined";
			st,prescaler = <0>;
			status = "disabled";
		};

		timers15: timers@40014000 {
			compatible = "st,stm32-timers";
			reg = <0x40014000 0x400>;
			clocks = <&rcc STM32_CLOCK(APB1_2, 16U)>;
			resets = <&rctl STM32_RESET(APB1H, 16U)>;
			interrupts = <19 0>;
			interrupt-names = "combined";
			st,prescaler = <0>;
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};

			counter {
				compatible = "st,stm32-counter";
				status = "disabled";
			};
		};

		timers16: timers@40014400 {
			compatible = "st,stm32-timers";
			reg = <0x40014400 0x400>;
			clocks = <&rcc STM32_CLOCK(APB1_2, 17U)>;
			resets = <&rctl STM32_RESET(APB1H, 17U)>;
			interrupts = <20 0>;
			interrupt-names = "global";
			st,prescaler = <0>;
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};

			counter {
				compatible = "st,stm32-counter";
				status = "disabled";
			};
		};

		lptim1: timers@40007c00 {
			compatible = "st,stm32-lptim";
			clocks = <&rcc STM32_CLOCK(APB1, 31U)>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40007c00 0x400>;
			interrupts = <17 1>;
			interrupt-names = "combined";
			status = "disabled";

		};

		lptim2: timers@40009400 {
			compatible = "st,stm32-lptim";
			clocks = <&rcc STM32_CLOCK(APB1, 30U)>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40009400 0x400>;
			interrupts = <18 1>;
			interrupt-names = "combined";
			status = "disabled";
		};
	};
};

&nvic {
	arm,num-irq-priority-bits = <2>;
};