1/*
2 * Copyright (c) 2021 Argentum Systems Ltd.
3 * Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#include <atmel/saml2x.dtsi>
9
10/ {
11	aliases {
12		tcc-0 = &tcc0;
13		tcc-1 = &tcc1;
14		tcc-2 = &tcc2;
15	};
16
17	soc {
18		tcc0: tcc@42001400 {
19			compatible = "atmel,sam0-tcc";
20			reg = <0x42001400 0x80>;
21			interrupts = <14 0>;
22			clocks = <&gclk 25>, <&mclk 0x1c 5>;
23			clock-names = "GCLK", "MCLK";
24			atmel,assigned-clocks = <&gclk 0>;
25			atmel,assigned-clock-names = "GCLK";
26			status = "disabled";
27
28			channels = <4>;
29			counter-size = <24>;
30		};
31
32		tcc1: tcc@42001800 {
33			compatible = "atmel,sam0-tcc";
34			reg = <0x42001800 0x80>;
35			interrupts = <15 0>;
36			clocks = <&gclk 25>, <&mclk 0x1c 6>;
37			clock-names = "GCLK", "MCLK";
38			atmel,assigned-clocks = <&gclk 0>;
39			atmel,assigned-clock-names = "GCLK";
40			status = "disabled";
41
42			channels = <4>;
43			counter-size = <24>;
44		};
45
46		tcc2: tcc@42001c00 {
47			compatible = "atmel,sam0-tcc";
48			reg = <0x42001C00 0x80>;
49			interrupts = <16 0>;
50			clocks = <&gclk 26>, <&mclk 0x1c 7>;
51			clock-names = "GCLK", "MCLK";
52			atmel,assigned-clocks = <&gclk 0>;
53			atmel,assigned-clock-names = "GCLK";
54			status = "disabled";
55
56			channels = <2>;
57			counter-size = <16>;
58		};
59	};
60};
61
62&dac {
63	interrupts = <24 0>;
64	clocks = <&gclk 32>, <&mclk 0x1c 12>;
65	clock-names = "GCLK", "MCLK";
66	atmel,assigned-clocks = <&gclk 0>;
67	atmel,assigned-clock-names = "GCLK";
68};
69
70&sercom0 {
71	interrupts = <8 0>;
72	clocks = <&gclk 18>, <&mclk 0x1c 0>;
73	clock-names = "GCLK", "MCLK";
74	atmel,assigned-clocks = <&gclk 0>;
75	atmel,assigned-clock-names = "GCLK";
76};
77
78&sercom1 {
79	interrupts = <9 0>;
80	clocks = <&gclk 19>, <&mclk 0x1c 1>;
81	clock-names = "GCLK", "MCLK";
82	atmel,assigned-clocks = <&gclk 0>;
83	atmel,assigned-clock-names = "GCLK";
84};
85
86&sercom2 {
87	interrupts = <10 0>;
88	clocks = <&gclk 20>, <&mclk 0x1c 2>;
89	clock-names = "GCLK", "MCLK";
90	atmel,assigned-clocks = <&gclk 0>;
91	atmel,assigned-clock-names = "GCLK";
92};
93
94&sercom3 {
95	interrupts = <11 0>;
96	clocks = <&gclk 21>, <&mclk 0x1c 3>;
97	clock-names = "GCLK", "MCLK";
98	atmel,assigned-clocks = <&gclk 0>;
99	atmel,assigned-clock-names = "GCLK";
100};
101
102&sercom4 {
103	interrupts = <12 0>;
104	clocks = <&gclk 22>, <&mclk 0x1c 4>;
105	clock-names = "GCLK", "MCLK";
106	atmel,assigned-clocks = <&gclk 0>;
107	atmel,assigned-clock-names = "GCLK";
108};
109
110&sercom5 {
111	interrupts = <13 0>;
112	clocks = <&gclk 24>, <&mclk 0x20 1>;
113	clock-names = "GCLK", "MCLK";
114	atmel,assigned-clocks = <&gclk 0>;
115	atmel,assigned-clock-names = "GCLK";
116};
117
118&tc4 {
119	interrupts = <21 0>;
120	clocks = <&gclk 29>, <&mclk 0x20 2>;
121	clock-names = "GCLK", "MCLK";
122	atmel,assigned-clocks = <&gclk 0>;
123	atmel,assigned-clock-names = "GCLK";
124};
125
126&adc {
127	interrupts = <22 0>;
128	interrupt-names = "resrdy";
129	clocks = <&gclk 30>, <&mclk 0x20 3>;
130	clock-names = "GCLK", "MCLK";
131	/*
132	 * 16 MHz is ADC max clock
133	 * 48 MHz DFLL / 2 / 2 = 12 MHz
134	 * Generator 3: 48MHz
135	 */
136	atmel,assigned-clocks = <&gclk 3>;
137	atmel,assigned-clock-names = "GCLK";
138};
139