1/* 2 * Copyright 2020, 2024 NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <mem.h> 8#include <arm/armv8-m.dtsi> 9#include <zephyr/dt-bindings/adc/adc.h> 10#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h> 11#include <zephyr/dt-bindings/gpio/gpio.h> 12#include <zephyr/dt-bindings/i2c/i2c.h> 13#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h> 14#include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h> 15 16/ { 17 chosen { 18 zephyr,entropy = &trng; 19 }; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpu0: cpu@0 { 26 compatible = "arm,cortex-m33f"; 27 reg = <0>; 28 cpu-power-states = <&idle &suspend>; 29 #address-cells = <1>; 30 #size-cells = <1>; 31 32 mpu: mpu@e000ed90 { 33 compatible = "arm,armv8m-mpu"; 34 reg = <0xe000ed90 0x40>; 35 }; 36 }; 37 38 power-states { 39 idle: idle { 40 compatible = "zephyr,power-state"; 41 power-state-name = "runtime-idle"; 42 min-residency-us = <10>; 43 }; 44 suspend: suspend { 45 compatible = "zephyr,power-state"; 46 power-state-name = "suspend-to-idle"; 47 min-residency-us = <1000>; 48 }; 49 }; 50 }; 51}; 52 53&sram { 54 #address-cells = <1>; 55 #size-cells = <1>; 56 57 /* RT6XX SRAM partitions are shared 58 * between code and data. Boards can 59 * override the reg properties of either sram0 or sram_code nodes to 60 * change the balance of SRAM allocation. 61 * 62 * Note that the sram code region starts at an offset of 0x1B000, 63 * as the boot ROM will not load code before 0x1C000. The first 64 * 0x1000 of the image will contain the boot header. 65 */ 66 sram_code: memory@1b000 { 67 compatible = "mmio-sram"; 68 reg = <0x1b000 DT_SIZE_K(1428)>; 69 }; 70 71 sram0: memory@180000 { 72 compatible = "mmio-sram"; 73 reg = <0x180000 DT_SIZE_K(3072)>; 74 }; 75 76 sram1: memory@40140000 { 77 compatible = "zephyr,memory-region", "mmio-sram"; 78 reg = <0x40140000 DT_SIZE_K(16)>; 79 zephyr,memory-region = "SRAM1"; 80 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; 81 }; 82}; 83 84&systick { 85 /* 86 * RT600 relies by default on the OS Timer for system clock 87 * implementation, so the SysTick node is not to be enabled. 88 */ 89 status = "disabled"; 90}; 91 92&peripheral { 93 #address-cells = <1>; 94 #size-cells = <1>; 95 /* 96 * Note that the offsets here are relative to the base address 97 * defined in either nxp_rt6xx_ns.dtsi or nxp_rt6xx.dtsi. The base 98 * addresses differ between non-secure (0x40000000) and secure 99 * modes (0x50000000). 100 */ 101 102 flexspi: spi@134000 { 103 reg = <0x134000 0x1000>, <0x18000000 DT_SIZE_M(128)>; 104 }; 105 106 clkctl0: clkctl@1000 { 107 /* FIXME This chip does NOT have a syscon */ 108 compatible = "nxp,lpc-syscon"; 109 reg = <0x1000 0x1000>; 110 #clock-cells = <1>; 111 }; 112 113 iocon: iocon@4000 { 114 compatible = "nxp,lpc-iocon"; 115 reg = <0x4000 0x1000>; 116 pinctrl: pinctrl { 117 compatible = "nxp,rt-iocon-pinctrl"; 118 }; 119 }; 120 121 clkctl1: clkctl@21000 { 122 /* FIXME This chip does NOT have a syscon */ 123 compatible = "nxp,lpc-syscon"; 124 reg = <0x21000 0x1000>; 125 #clock-cells = <1>; 126 }; 127 128 rstctl0: reset@0 { 129 compatible = "nxp,rstctl"; 130 reg = <0x0 0x80>; 131 #reset-cells = <1>; 132 }; 133 134 rstctl1: reset@20000 { 135 compatible = "nxp,rstctl"; 136 reg = <0x20000 0x80>; 137 #reset-cells = <1>; 138 }; 139 140 uuid: uuid@2f50 { 141 compatible = "nxp,lpc-uid"; 142 reg = <0x2f50 0x10>; 143 }; 144 145 gpio: gpio@100000 { 146 compatible = "nxp,lpc-gpio"; 147 reg = <0x100000 0x2784>; 148 #address-cells = <1>; 149 #size-cells = <0>; 150 151 gpio0: gpio@0 { 152 compatible = "nxp,lpc-gpio-port"; 153 int-source = "pint"; 154 gpio-controller; 155 #gpio-cells = <2>; 156 reg = <0>; 157 }; 158 159 gpio1: gpio@1 { 160 compatible = "nxp,lpc-gpio-port"; 161 int-source = "pint"; 162 gpio-controller; 163 #gpio-cells = <2>; 164 reg = <1>; 165 }; 166 167 gpio2: gpio@2 { 168 compatible = "nxp,lpc-gpio-port"; 169 gpio-controller; 170 #gpio-cells = <2>; 171 reg = <2>; 172 }; 173 174 gpio3: gpio@3 { 175 compatible = "nxp,lpc-gpio-port"; 176 gpio-controller; 177 #gpio-cells = <2>; 178 reg = <3>; 179 }; 180 181 gpio4: gpio@4 { 182 compatible = "nxp,lpc-gpio-port"; 183 gpio-controller; 184 #gpio-cells = <2>; 185 reg = <4>; 186 }; 187 188 gpio7: gpio@7 { 189 compatible = "nxp,lpc-gpio-port"; 190 gpio-controller; 191 #gpio-cells = <2>; 192 reg = <7>; 193 }; 194 }; 195 196 pint: pint@25000 { 197 compatible = "nxp,pint"; 198 reg = <0x25000 0x1000>; 199 interrupt-controller; 200 #interrupt-cells = <1>; 201 #address-cells = <0>; 202 interrupts = <4 2>, <5 2>, <6 2>, <7 2>, 203 <35 2>, <36 2>, <37 2>, <38 2>; 204 num-lines = <8>; 205 num-inputs = <64>; 206 }; 207 208 flexcomm0: flexcomm@106000 { 209 compatible = "nxp,lpc-flexcomm"; 210 reg = <0x106000 0x1000>; 211 interrupts = <14 0>; 212 clocks = <&clkctl1 MCUX_FLEXCOMM0_CLK>; 213 resets = <&rstctl1 NXP_SYSCON_RESET(0, 8)>; 214 status = "disabled"; 215 }; 216 217 flexcomm1: flexcomm@107000 { 218 compatible = "nxp,lpc-flexcomm"; 219 reg = <0x107000 0x1000>; 220 interrupts = <15 0>; 221 clocks = <&clkctl1 MCUX_FLEXCOMM1_CLK>; 222 resets = <&rstctl1 NXP_SYSCON_RESET(0, 9)>; 223 status = "disabled"; 224 }; 225 226 flexcomm2: flexcomm@108000 { 227 compatible = "nxp,lpc-flexcomm"; 228 reg = <0x108000 0x1000>; 229 interrupts = <16 0>; 230 clocks = <&clkctl1 MCUX_FLEXCOMM2_CLK>; 231 resets = <&rstctl1 NXP_SYSCON_RESET(0, 10)>; 232 status = "disabled"; 233 }; 234 235 flexcomm3: flexcomm@109000 { 236 compatible = "nxp,lpc-flexcomm"; 237 reg = <0x109000 0x1000>; 238 interrupts = <17 0>; 239 clocks = <&clkctl1 MCUX_FLEXCOMM3_CLK>; 240 resets = <&rstctl1 NXP_SYSCON_RESET(0, 11)>; 241 status = "disabled"; 242 }; 243 244 flexcomm4: flexcomm@122000 { 245 compatible = "nxp,lpc-flexcomm"; 246 reg = <0x122000 0x1000>; 247 interrupts = <18 0>; 248 clocks = <&clkctl1 MCUX_FLEXCOMM4_CLK>; 249 resets = <&rstctl1 NXP_SYSCON_RESET(0, 12)>; 250 status = "disabled"; 251 }; 252 253 flexcomm5: flexcomm@123000 { 254 compatible = "nxp,lpc-flexcomm"; 255 reg = <0x123000 0x1000>; 256 interrupts = <19 0>; 257 clocks = <&clkctl1 MCUX_FLEXCOMM5_CLK>; 258 resets = <&rstctl1 NXP_SYSCON_RESET(0, 13)>; 259 status = "disabled"; 260 }; 261 262 flexcomm6: flexcomm@124000 { 263 compatible = "nxp,lpc-flexcomm"; 264 reg = <0x124000 0x1000>; 265 interrupts = <43 0>; 266 clocks = <&clkctl1 MCUX_FLEXCOMM6_CLK>; 267 resets = <&rstctl1 NXP_SYSCON_RESET(0, 14)>; 268 status = "disabled"; 269 }; 270 271 flexcomm7: flexcomm@125000 { 272 compatible = "nxp,lpc-flexcomm"; 273 reg = <0x125000 0x1000>; 274 interrupts = <44 0>; 275 clocks = <&clkctl1 MCUX_FLEXCOMM7_CLK>; 276 resets = <&rstctl1 NXP_SYSCON_RESET(0, 15)>; 277 status = "disabled"; 278 }; 279 280 pmic_i2c: i2c@127000 { 281 compatible = "nxp,lpc-i2c"; 282 reg = <0x127000 0x1000>; 283 interrupts = <21 0>; 284 clocks = <&clkctl1 MCUX_PMIC_I2C_CLK>; 285 resets = <&rstctl1 NXP_SYSCON_RESET(0, 23)>; 286 status = "disabled"; 287 }; 288 289 usbhs: usbhs@144000 { 290 compatible = "nxp,lpcip3511"; 291 reg = <0x144000 0x1000>; 292 interrupts = <50 1>; 293 num-bidir-endpoints = <6>; 294 status = "disabled"; 295 }; 296 297 usbphy: usbphy@13b000 { 298 compatible = "nxp,usbphy"; 299 reg = <0x13b000 0x1000>; 300 status = "disabled"; 301 }; 302 303 hs_lspi: spi@126000 { 304 compatible = "nxp,lpc-spi"; 305 /* Enabling cs-gpios below will allow using GPIO CS, 306 rather than Flexcomm SS */ 307 /* cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>, 308 <&gpio1 15 GPIO_ACTIVE_LOW>, 309 <&gpio1 16 GPIO_ACTIVE_LOW>, 310 <&gpio1 17 GPIO_ACTIVE_LOW>; */ 311 reg = <0x126000 0x1000>; 312 interrupts = <20 0>; 313 clocks = <&clkctl1 MCUX_HS_SPI_CLK>; 314 resets = <&rstctl1 NXP_SYSCON_RESET(0, 22)>; 315 status = "disabled"; 316 #address-cells = <1>; 317 #size-cells = <0>; 318 }; 319 320 dma0: dma-controller@104000 { 321 compatible = "nxp,lpc-dma"; 322 reg = <0x104000 0x1000>; 323 interrupts = <1 0>; 324 dma-channels = <33>; 325 status = "disabled"; 326 #dma-cells = <1>; 327 }; 328 329 dma1: dma-controller@105000 { 330 compatible = "nxp,lpc-dma"; 331 reg = <0x105000 0x1000>; 332 interrupts = <54 0>; 333 dma-channels = <33>; 334 status = "disabled"; 335 #dma-cells = <1>; 336 }; 337 338 dmic0: dmic@121000 { 339 #address-cells = <1>; 340 #size-cells = <0>; 341 compatible = "nxp,dmic"; 342 reg = <0x121000 0x1000>; 343 interrupts = <25 0>; 344 status = "disabled"; 345 clocks = <&clkctl0 MCUX_DMIC_CLK>; 346 347 pdmc0: dmic-channel@0 { 348 reg = <0>; 349 dmas = <&dma0 16>; 350 status = "disabled"; 351 }; 352 353 pdmc1: dmic-channel@1 { 354 reg = <1>; 355 dmas = <&dma0 17>; 356 status = "disabled"; 357 }; 358 359 pdmc2: dmic-channel@2 { 360 reg = <2>; 361 dmas = <&dma0 18>; 362 status = "disabled"; 363 }; 364 365 pdmc3: dmic-channel@3 { 366 reg = <3>; 367 dmas = <&dma0 19>; 368 status = "disabled"; 369 }; 370 371 pdmc4: dmic-channel@4 { 372 reg = <4>; 373 dmas = <&dma0 20>; 374 status = "disabled"; 375 }; 376 377 pdmc5: dmic-channel@5 { 378 reg = <5>; 379 dmas = <&dma0 21>; 380 status = "disabled"; 381 }; 382 383 pdmc6: dmic-channel@6 { 384 reg = <6>; 385 dmas = <&dma0 22>; 386 status = "disabled"; 387 }; 388 389 pdmc7: dmic-channel@7 { 390 reg = <7>; 391 dmas = <&dma0 23>; 392 status = "disabled"; 393 }; 394 }; 395 396 os_timer: timers@113000 { 397 compatible = "nxp,os-timer"; 398 reg = <0x113000 0x1000>; 399 interrupts = <41 0>; 400 status = "disabled"; 401 }; 402 403 rtc: rtc@30000 { 404 compatible = "nxp,lpc-rtc"; 405 reg = <0x30000 0x1000>; 406 interrupts = <32 0>; 407 status = "disabled"; 408 rtc_highres: rtc_highres { 409 compatible = "nxp,lpc-rtc-highres"; 410 status = "disabled"; 411 }; 412 }; 413 414 trng: random@138000 { 415 compatible = "nxp,kinetis-trng"; 416 reg = <0x138000 0x1000>; 417 status = "okay"; 418 interrupts = <31 0>; 419 }; 420 421 sc_timer: pwm@146000 { 422 compatible = "nxp,sctimer-pwm"; 423 reg = <0x146000 0x1000>; 424 interrupts = <12 0>; 425 status = "disabled"; 426 clocks = <&clkctl1 MCUX_SCTIMER_CLK>; 427 prescaler = <8>; 428 #pwm-cells = <3>; 429 }; 430 431 wwdt0: watchdog@e000 { 432 compatible = "nxp,lpc-wwdt"; 433 reg = <0xe000 0x1000>; 434 interrupts = <0 0>; 435 status = "disabled"; 436 clk-divider = <1>; 437 }; 438 439 wwdt1: watchdog@2e000 { 440 compatible = "nxp,lpc-wwdt"; 441 reg = <0x2e000 0x1000>; 442 interrupts = <52 0>; 443 status = "disabled"; 444 clk-divider = <1>; 445 }; 446 447 usdhc0: usdhc@136000 { 448 compatible = "nxp,imx-usdhc"; 449 reg = <0x136000 0x1000>; 450 status = "disabled"; 451 interrupts = <45 0>; 452 clocks = <&clkctl1 MCUX_USDHC1_CLK>; 453 max-current-330 = <1020>; 454 max-current-180 = <1020>; 455 max-bus-freq = <208000000>; 456 min-bus-freq = <400000>; 457 }; 458 459 usdhc1: usdhc@137000 { 460 compatible = "nxp,imx-usdhc"; 461 reg = <0x137000 0x1000>; 462 status = "disabled"; 463 interrupts = <46 0>; 464 clocks = <&clkctl1 MCUX_USDHC2_CLK>; 465 max-current-330 = <1020>; 466 max-current-180 = <1020>; 467 max-bus-freq = <208000000>; 468 min-bus-freq = <400000>; 469 }; 470 471 lpadc0: adc@13a000 { 472 compatible = "nxp,lpc-lpadc"; 473 reg = <0x13a000 0x304>; 474 interrupts = <22 0>; 475 status = "disabled"; 476 clk-divider = <1>; 477 clk-source = <0>; 478 voltage-ref= <1>; 479 calibration-average = <128>; 480 power-level = <0>; 481 offset-value-a = <10>; 482 offset-value-b = <10>; 483 #io-channel-cells = <1>; 484 clocks = <&clkctl1 MCUX_LPADC1_CLK>; 485 }; 486 487 ctimer0: ctimer@28000 { 488 compatible = "nxp,lpc-ctimer"; 489 reg = <0x28000 0x1000>; 490 interrupts = <10 0>; 491 status = "disabled"; 492 clk-source = <1>; 493 clocks = <&clkctl1 MCUX_CTIMER0_CLK>; 494 mode = <0>; 495 input = <0>; 496 prescale = <0>; 497 }; 498 499 ctimer1: ctimer@29000 { 500 compatible = "nxp,lpc-ctimer"; 501 reg = <0x29000 0x1000>; 502 interrupts = <11 0>; 503 status = "disabled"; 504 clk-source = <1>; 505 clocks = <&clkctl1 MCUX_CTIMER1_CLK>; 506 mode = <0>; 507 input = <0>; 508 prescale = <0>; 509 }; 510 511 ctimer2: ctimer@2a000 { 512 compatible = "nxp,lpc-ctimer"; 513 reg = <0x2a000 0x1000>; 514 interrupts = <39 0>; 515 status = "disabled"; 516 clk-source = <1>; 517 clocks = <&clkctl1 MCUX_CTIMER2_CLK>; 518 mode = <0>; 519 input = <0>; 520 prescale = <0>; 521 }; 522 523 ctimer3: ctimer@2b000 { 524 compatible = "nxp,lpc-ctimer"; 525 reg = <0x2b000 0x1000>; 526 interrupts = <13 0>; 527 status = "disabled"; 528 clk-source = <1>; 529 clocks = <&clkctl1 MCUX_CTIMER3_CLK>; 530 mode = <0>; 531 input = <0>; 532 prescale = <0>; 533 }; 534 535 ctimer4: ctimer@2c000 { 536 compatible = "nxp,lpc-ctimer"; 537 reg = <0x2c000 0x1000>; 538 interrupts = <40 0>; 539 status = "disabled"; 540 clk-source = <1>; 541 clocks = <&clkctl1 MCUX_CTIMER4_CLK>; 542 mode = <0>; 543 input = <0>; 544 prescale = <0>; 545 }; 546 547 i3c0: i3c@36000 { 548 compatible = "nxp,mcux-i3c"; 549 reg = <0x36000 0x1000>; 550 interrupts = <49 0>; 551 clocks = <&clkctl1 MCUX_I3C_CLK>; 552 clk-divider = <2>; 553 clk-divider-slow = <1>; 554 clk-divider-tc = <1>; 555 status = "disabled"; 556 #address-cells = <3>; 557 #size-cells = <0>; 558 }; 559 560 mrt: mrt@2d000 { 561 compatible = "nxp,mrt"; 562 reg = <0x2d000 0x100>; 563 interrupts = <9 0>; 564 num-channels = <4>; 565 num-bits = <24>; 566 clocks = <&clkctl1 MCUX_MRT_CLK>; 567 resets = <&rstctl1 NXP_SYSCON_RESET(2, 8)>; 568 #address-cells = <1>; 569 #size-cells = <0>; 570 571 mrt_channel0: mrt_channel@0 { 572 compatible = "nxp,mrt-channel"; 573 reg = <0>; 574 status = "disabled"; 575 }; 576 mrt_channel1: mrt_channel@1 { 577 compatible = "nxp,mrt-channel"; 578 reg = <1>; 579 status = "disabled"; 580 }; 581 mrt_channel2: mrt_channel@2 { 582 compatible = "nxp,mrt-channel"; 583 reg = <2>; 584 status = "disabled"; 585 }; 586 mrt_channel3: mrt_channel@3 { 587 compatible = "nxp,mrt-channel"; 588 reg = <3>; 589 status = "disabled"; 590 }; 591 }; 592}; 593 594&flexspi { 595 compatible = "nxp,imx-flexspi"; 596 interrupts = <42 0>; 597 #address-cells = <1>; 598 #size-cells = <0>; 599 status = "disabled"; 600 clocks = <&clkctl1 MCUX_FLEXSPI_CLK>; 601}; 602 603&nvic { 604 arm,num-irq-priority-bits = <3>; 605}; 606
