1/*
2 * Copyright 2024 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
9#include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
10#include <zephyr/dt-bindings/gpio/gpio.h>
11#include <arm/armv8-m.dtsi>
12#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
13
14/ {
15	cpus: cpus {
16		#address-cells = <1>;
17		#size-cells = <0>;
18
19		cpu@0 {
20			compatible = "arm,cortex-m33f";
21			reg = <0>;
22			#address-cells = <1>;
23			#size-cells = <1>;
24
25			mpu: mpu@e000ed90 {
26				compatible = "arm,armv8m-mpu";
27				reg = <0xe000ed90 0x40>;
28			};
29		};
30		cpu@1 {
31			compatible = "arm,cortex-m33";
32			reg = <1>;
33		};
34	};
35
36	/* Dummy pinctrl node, filled with pin mux options at board level */
37	pinctrl: pinctrl {
38		compatible = "nxp,port-pinctrl";
39		status = "okay";
40	};
41};
42
43&sram {
44	#address-cells = <1>;
45	#size-cells = <1>;
46
47	sramx: memory@4000000 {
48		compatible =  "zephyr,memory-region", "mmio-sram";
49		reg = <0x4000000 DT_SIZE_K(96)>;
50		zephyr,memory-region = "SRAM1";
51		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
52	};
53
54	/* mcxn94x Memory configurations:
55	 *
56	 * RAM blocks RAMA through SRAM4 are contiguous address ranges
57	 *
58	 * MCXN94X: 512KB RAM, RAMX: 96K, RAMA: 32K, RAMB: 32K,
59	 *                     RAMC: 64K, RAMD: 64K, RAME: 64K
60	 *                     RAMF: 64K, RAMG: 64K, RAMH: 32K
61	 */
62	sram0: memory@20000000 {
63		compatible = "mmio-sram";
64		reg = <0x20000000 DT_SIZE_K(416)>;
65	};
66};
67
68&peripheral {
69	#address-cells = <1>;
70	#size-cells = <1>;
71
72	syscon: syscon@0 {
73		compatible = "nxp,lpc-syscon";
74		reg = <0x0 0x4000>;
75		#clock-cells = <1>;
76		reset: reset {
77			compatible = "nxp,lpc-syscon-reset";
78			#reset-cells = <1>;
79		};
80	};
81
82	porta: pinmux@116000 {
83		compatible = "nxp,port-pinmux";
84		reg = <0x116000 0x1000>;
85		clocks = <&syscon MCUX_PORT0_CLK>;
86	};
87
88	portb: pinmux@117000 {
89		compatible = "nxp,port-pinmux";
90		reg = <0x117000 0x1000>;
91		clocks = <&syscon MCUX_PORT1_CLK>;
92	};
93
94	portc: pinmux@118000 {
95		compatible = "nxp,port-pinmux";
96		reg = <0x118000 0x1000>;
97		clocks = <&syscon MCUX_PORT2_CLK>;
98	};
99
100	portd: pinmux@119000 {
101		compatible = "nxp,port-pinmux";
102		reg = <0x119000 0x1000>;
103		clocks = <&syscon MCUX_PORT3_CLK>;
104	};
105
106	porte: pinmux@11a000 {
107		compatible = "nxp,port-pinmux";
108		reg = <0x11a000 0x1000>;
109		clocks = <&syscon MCUX_PORT4_CLK>;
110	};
111
112	portf: pinmux@42000 {
113		compatible = "nxp,port-pinmux";
114		reg = <0x42000 0x1000>;
115		clocks = <&syscon MCUX_PORT5_CLK>;
116	};
117
118	gpio0: gpio@96000 {
119		compatible = "nxp,kinetis-gpio";
120		status = "disabled";
121		reg = <0x96000 0x1000>;
122		interrupts = <17 0>,<18 0>;
123		gpio-controller;
124		#gpio-cells = <2>;
125		nxp,kinetis-port = <&porta>;
126	};
127
128	gpio1: gpio@98000 {
129		compatible = "nxp,kinetis-gpio";
130		status = "disabled";
131		reg = <0x98000 0x1000>;
132		interrupts = <19 0>,<20 0>;
133		gpio-controller;
134		#gpio-cells = <2>;
135		nxp,kinetis-port = <&portb>;
136	};
137
138	gpio2: gpio@9a000 {
139		compatible = "nxp,kinetis-gpio";
140		status = "disabled";
141		reg = <0x9a000 0x1000>;
142		interrupts = <21 0>,<22 0>;
143		gpio-controller;
144		#gpio-cells = <2>;
145		nxp,kinetis-port = <&portc>;
146	};
147
148	gpio3: gpio@9c000 {
149		compatible = "nxp,kinetis-gpio";
150		status = "disabled";
151		reg = <0x9c000 0x1000>;
152		interrupts = <23 0>,<24 0>;
153		gpio-controller;
154		#gpio-cells = <2>;
155		nxp,kinetis-port = <&portd>;
156	};
157
158	gpio4: gpio@9e000 {
159		compatible = "nxp,kinetis-gpio";
160		status = "disabled";
161		reg = <0x9e000 0x1000>;
162		interrupts = <25 0>,<26 0>;
163		gpio-controller;
164		#gpio-cells = <2>;
165		nxp,kinetis-port = <&porte>;
166	};
167
168	gpio5: gpio@40000 {
169		compatible = "nxp,kinetis-gpio";
170		status = "disabled";
171		reg = <0x40000 0x1000>;
172		interrupts = <27 0>,<28 0>;
173		gpio-controller;
174		#gpio-cells = <2>;
175		nxp,kinetis-port = <&portf>;
176	};
177
178	flexcomm0: flexcomm@92000 {
179		compatible = "nxp,lp-flexcomm";
180		reg = <0x92000 0x1000>;
181		interrupts = <35 0>;
182		status = "disabled";
183
184		/* Empty ranges property implies parent and child address space is identical */
185		ranges = <>;
186		#address-cells = <1>;
187		#size-cells = <1>;
188
189		flexcomm0_lpuart0: lpuart@92000 {
190			compatible = "nxp,lpuart";
191			reg = <0x92000 0x1000>;
192			clocks = <&syscon MCUX_FLEXCOMM0_CLK>;
193			status = "disabled";
194		};
195		flexcomm0_lpspi0: spi@92000 {
196			compatible = "nxp,lpspi";
197			reg = <0x92000 0x1000>;
198			clocks = <&syscon MCUX_FLEXCOMM0_CLK>;
199			#address-cells = <1>;
200			#size-cells = <0>;
201			tx-fifo-size = <8>;
202			rx-fifo-size = <8>;
203			status = "disabled";
204		};
205		flexcomm0_lpi2c0: lpi2c@92800 {
206			compatible = "nxp,lpi2c";
207			reg = <0x92800 0x1000>;
208			clocks = <&syscon MCUX_FLEXCOMM0_CLK>;
209			#address-cells = <1>;
210			#size-cells = <0>;
211			status = "disabled";
212		};
213	};
214
215	flexcomm1: flexcomm@93000 {
216		compatible = "nxp,lp-flexcomm";
217		reg = <0x93000 0x1000>;
218		interrupts = <36 0>;
219		status = "disabled";
220
221		ranges = <>;
222		#address-cells = <1>;
223		#size-cells = <1>;
224
225		flexcomm1_lpuart1: lpuart@93000 {
226			compatible = "nxp,lpuart";
227			reg = <0x93000 0x1000>;
228			clocks = <&syscon MCUX_FLEXCOMM1_CLK>;
229			/* DMA channels 0 and 1, muxed to LPUART1 RX and TX */
230			dmas = <&edma0 0 71>, <&edma0 1 72>;
231			dma-names = "rx", "tx";
232			status = "disabled";
233		};
234		flexcomm1_lpspi1: spi@93000 {
235			compatible = "nxp,lpspi";
236			reg = <0x93000 0x1000>;
237			clocks = <&syscon MCUX_FLEXCOMM1_CLK>;
238			#address-cells = <1>;
239			#size-cells = <0>;
240			/* DMA channels 0 and 1, muxed to LPSPI1 RX and TX */
241			dmas = <&edma0 0 71>, <&edma0 1 72>;
242			dma-names = "rx", "tx";
243			tx-fifo-size = <8>;
244			rx-fifo-size = <8>;
245			status = "disabled";
246		};
247		flexcomm1_lpi2c1: lpi2c@93800 {
248			compatible = "nxp,lpi2c";
249			reg = <0x93800 0x1000>;
250			clocks = <&syscon MCUX_FLEXCOMM1_CLK>;
251			#address-cells = <1>;
252			#size-cells = <0>;
253			status = "disabled";
254		};
255	};
256
257	flexcomm2: flexcomm@94000 {
258		compatible = "nxp,lp-flexcomm";
259		reg = <0x94000 0x1000>;
260		interrupts = <37 0>;
261		status = "disabled";
262
263		ranges = <>;
264		#address-cells = <1>;
265		#size-cells = <1>;
266
267		flexcomm2_lpuart2: lpuart@94000 {
268			compatible = "nxp,lpuart";
269			reg = <0x94000 0x1000>;
270			clocks = <&syscon MCUX_FLEXCOMM2_CLK>;
271			/* DMA channels 4 and 5, muxed to LPUART2 RX and TX */
272			dmas = <&edma0 4 73>, <&edma0 5 74>;
273			dma-names = "rx", "tx";
274			status = "disabled";
275		};
276		flexcomm2_lpspi2: spi@94000 {
277			compatible = "nxp,lpspi";
278			reg = <0x94000 0x1000>;
279			clocks = <&syscon MCUX_FLEXCOMM2_CLK>;
280			#address-cells = <1>;
281			#size-cells = <0>;
282			/* DMA channels 4 and 5, muxed to LPSPI2 RX and TX */
283			dmas = <&edma0 4 73>, <&edma0 5 74>;
284			dma-names = "rx", "tx";
285			tx-fifo-size = <8>;
286			rx-fifo-size = <8>;
287			status = "disabled";
288		};
289		flexcomm2_lpi2c2: lpi2c@94800 {
290			compatible = "nxp,lpi2c";
291			reg = <0x94800 0x1000>;
292			clocks = <&syscon MCUX_FLEXCOMM2_CLK>;
293			#address-cells = <1>;
294			#size-cells = <0>;
295			status = "disabled";
296		};
297	};
298
299	flexcomm3: flexcomm@95000 {
300		compatible = "nxp,lp-flexcomm";
301		reg = <0x95000 0x1000>;
302		interrupts = <38 0>;
303		status = "disabled";
304
305		ranges = <>;
306		#address-cells = <1>;
307		#size-cells = <1>;
308
309		flexcomm3_lpuart3: lpuart@95000 {
310			compatible = "nxp,lpuart";
311			reg = <0x95000 0x1000>;
312			clocks = <&syscon MCUX_FLEXCOMM3_CLK>;
313			status = "disabled";
314		};
315		flexcomm3_lpspi3: spi@95000 {
316			compatible = "nxp,lpspi";
317			reg = <0x95000 0x1000>;
318			clocks = <&syscon MCUX_FLEXCOMM3_CLK>;
319			#address-cells = <1>;
320			#size-cells = <0>;
321			tx-fifo-size = <8>;
322			rx-fifo-size = <8>;
323			status = "disabled";
324		};
325		flexcomm3_lpi2c3: lpi2c@95800 {
326			compatible = "nxp,lpi2c";
327			reg = <0x95800 0x1000>;
328			clocks = <&syscon MCUX_FLEXCOMM3_CLK>;
329			#address-cells = <1>;
330			#size-cells = <0>;
331			status = "disabled";
332		};
333	};
334
335	flexcomm4: flexcomm@b4000 {
336		compatible = "nxp,lp-flexcomm";
337		reg = <0xb4000 0x1000>;
338		interrupts = <39 0>;
339		status = "disabled";
340
341		ranges = <>;
342		#address-cells = <1>;
343		#size-cells = <1>;
344
345		flexcomm4_lpuart4: lpuart@b4000 {
346			compatible = "nxp,lpuart";
347			reg = <0xb4000 0x1000>;
348			clocks = <&syscon MCUX_FLEXCOMM4_CLK>;
349			/* DMA channels 2 and 3, muxed to LPUART4 RX and TX */
350			dmas = <&edma0 2 77>, <&edma0 3 78>;
351			dma-names = "rx", "tx";
352			status = "disabled";
353		};
354		flexcomm4_lpspi4: spi@b4000 {
355			compatible = "nxp,lpspi";
356			reg = <0xb4000 0x1000>;
357			clocks = <&syscon MCUX_FLEXCOMM4_CLK>;
358			#address-cells = <1>;
359			#size-cells = <0>;
360			/* DMA channels 2 and 3, muxed to LPSPI4 RX and TX */
361			dmas = <&edma0 2 77>, <&edma0 3 78>;
362			dma-names = "rx", "tx";
363			tx-fifo-size = <8>;
364			rx-fifo-size = <8>;
365			status = "disabled";
366		};
367		flexcomm4_lpi2c4: lpi2c@b4800 {
368			compatible = "nxp,lpi2c";
369			reg = <0xb4800 0x1000>;
370			clocks = <&syscon MCUX_FLEXCOMM4_CLK>;
371			#address-cells = <1>;
372			#size-cells = <0>;
373			status = "disabled";
374		};
375	};
376
377	flexcomm5: flexcomm@b5000 {
378		compatible = "nxp,lp-flexcomm";
379		reg = <0xb5000 0x1000>;
380		interrupts = <40 0>;
381		status = "disabled";
382
383		ranges = <>;
384		#address-cells = <1>;
385		#size-cells = <1>;
386
387		flexcomm5_lpuart5: lpuart@b5000 {
388			compatible = "nxp,lpuart";
389			reg = <0xb5000 0x1000>;
390			clocks = <&syscon MCUX_FLEXCOMM5_CLK>;
391			status = "disabled";
392		};
393		flexcomm5_lpspi5: spi@b5000 {
394			compatible = "nxp,lpspi";
395			reg = <0xb5000 0x1000>;
396			clocks = <&syscon MCUX_FLEXCOMM5_CLK>;
397			#address-cells = <1>;
398			#size-cells = <0>;
399			tx-fifo-size = <8>;
400			rx-fifo-size = <8>;
401			status = "disabled";
402		};
403		flexcomm5_lpi2c5: lpi2c@b5800 {
404			compatible = "nxp,lpi2c";
405			reg = <0xb5800 0x1000>;
406			clocks = <&syscon MCUX_FLEXCOMM5_CLK>;
407			#address-cells = <1>;
408			#size-cells = <0>;
409			status = "disabled";
410		};
411	};
412
413	flexcomm6: flexcomm@b6000 {
414		compatible = "nxp,lp-flexcomm";
415		reg = <0xb6000 0x1000>;
416		interrupts = <41 0>;
417		status = "disabled";
418
419		ranges = <>;
420		#address-cells = <1>;
421		#size-cells = <1>;
422
423		flexcomm6_lpuart6: lpuart@b6000 {
424			compatible = "nxp,lpuart";
425			reg = <0xb6000 0x1000>;
426			clocks = <&syscon MCUX_FLEXCOMM6_CLK>;
427			status = "disabled";
428		};
429		flexcomm6_lpspi6: spi@b6000 {
430			compatible = "nxp,lpspi";
431			reg = <0xb6000 0x1000>;
432			clocks = <&syscon MCUX_FLEXCOMM6_CLK>;
433			#address-cells = <1>;
434			#size-cells = <0>;
435			tx-fifo-size = <8>;
436			rx-fifo-size = <8>;
437			status = "disabled";
438		};
439		flexcomm6_lpi2c6: lpi2c@b6800 {
440			compatible = "nxp,lpi2c";
441			reg = <0xb6800 0x1000>;
442			clocks = <&syscon MCUX_FLEXCOMM6_CLK>;
443			#address-cells = <1>;
444			#size-cells = <0>;
445			status = "disabled";
446		};
447	};
448
449	flexcomm7: flexcomm@b7000 {
450		compatible = "nxp,lp-flexcomm";
451		reg = <0xb7000 0x1000>;
452		interrupts = <42 0>;
453		status = "disabled";
454
455		ranges = <>;
456		#address-cells = <1>;
457		#size-cells = <1>;
458
459		flexcomm7_lpuart7: lpuart@b7000 {
460			compatible = "nxp,lpuart";
461			reg = <0xb7000 0x1000>;
462			clocks = <&syscon MCUX_FLEXCOMM7_CLK>;
463			status = "disabled";
464		};
465		flexcomm7_lpspi7: spi@b7000 {
466			compatible = "nxp,lpspi";
467			reg = <0xb7000 0x1000>;
468			clocks = <&syscon MCUX_FLEXCOMM7_CLK>;
469			#address-cells = <1>;
470			#size-cells = <0>;
471			tx-fifo-size = <8>;
472			rx-fifo-size = <8>;
473			status = "disabled";
474		};
475		flexcomm7_lpi2c7: lpi2c@b7800 {
476			compatible = "nxp,lpi2c";
477			reg = <0xb7800 0x1000>;
478			clocks = <&syscon MCUX_FLEXCOMM7_CLK>;
479			#address-cells = <1>;
480			#size-cells = <0>;
481			status = "disabled";
482		};
483	};
484
485	flexcomm8: flexcomm@b8000 {
486		compatible = "nxp,lp-flexcomm";
487		reg = <0xb8000 0x1000>;
488		interrupts = <43 0>;
489		status = "disabled";
490
491		ranges = <>;
492		#address-cells = <1>;
493		#size-cells = <1>;
494
495		flexcomm8_lpuart8: lpuart@b8000 {
496			compatible = "nxp,lpuart";
497			reg = <0xb8000 0x1000>;
498			clocks = <&syscon MCUX_FLEXCOMM8_CLK>;
499			status = "disabled";
500		};
501		flexcomm8_lpspi8: spi@b8000 {
502			compatible = "nxp,lpspi";
503			reg = <0xb8000 0x1000>;
504			clocks = <&syscon MCUX_FLEXCOMM8_CLK>;
505			#address-cells = <1>;
506			#size-cells = <0>;
507			tx-fifo-size = <8>;
508			rx-fifo-size = <8>;
509			status = "disabled";
510		};
511		flexcomm8_lpi2c8: lpi2c@b8800 {
512			compatible = "nxp,lpi2c";
513			reg = <0xb8800 0x1000>;
514			clocks = <&syscon MCUX_FLEXCOMM8_CLK>;
515			#address-cells = <1>;
516			#size-cells = <0>;
517			status = "disabled";
518		};
519	};
520
521	flexcomm9: flexcomm@b9000 {
522		compatible = "nxp,lp-flexcomm";
523		reg = <0xb9000 0x1000>;
524		interrupts = <44 0>;
525		status = "disabled";
526
527		ranges = <>;
528		#address-cells = <1>;
529		#size-cells = <1>;
530
531		flexcomm9_lpuart9: lpuart@b9000 {
532			compatible = "nxp,lpuart";
533			reg = <0xb9000 0x1000>;
534			clocks = <&syscon MCUX_FLEXCOMM9_CLK>;
535			status = "disabled";
536		};
537		flexcomm9_lpspi9: spi@b9000 {
538			compatible = "nxp,lpspi";
539			reg = <0xb9000 0x1000>;
540			clocks = <&syscon MCUX_FLEXCOMM9_CLK>;
541			#address-cells = <1>;
542			#size-cells = <0>;
543			tx-fifo-size = <8>;
544			rx-fifo-size = <8>;
545			status = "disabled";
546		};
547		flexcomm9_lpi2c9: lpi2c@b9800 {
548			compatible = "nxp,lpi2c";
549			reg = <0xb9800 0x1000>;
550			clocks = <&syscon MCUX_FLEXCOMM9_CLK>;
551			#address-cells = <1>;
552			#size-cells = <0>;
553			status = "disabled";
554		};
555	};
556
557	mbox: mbox@b2000 {
558		compatible = "nxp,mbox-mailbox";
559		reg = <0xb2000 0xec>;
560		interrupts = <54 0>;
561		rx-channels = <4>;
562		#mbox-cells = <1>;
563		status = "disabled";
564	};
565
566	edma0: dma-controller@80000 {
567		#dma-cells = <2>;
568		compatible = "nxp,mcux-edma";
569		nxp,version = <4>;
570		dma-channels = <16>;
571		dma-requests = <120>;
572
573		reg = <0x80000 0x1000>;
574		interrupts = <1 0>, <2 0>, <3 0>, <4 0>,
575			<5 0>, <6 0>, <7 0>, <8 0>,
576			<9 0>, <10 0>, <11 0>, <12 0>,
577			<13 0>, <14 0>, <15 0>, <16 0>;
578		no-error-irq;
579		status = "disabled";
580	};
581
582	edma1: dma-controller@a0000 {
583		#dma-cells = <2>;
584		compatible = "nxp,mcux-edma";
585		nxp,version = <4>;
586		dma-channels = <16>;
587		dma-requests = <120>;
588
589		reg = <0xa0000 0x1000>;
590		interrupts = <77 0>, <78 0>, <79 0>, <80 0>,
591			<81 0>, <82 0>, <83 0>, <84 0>,
592			<85 0>, <86 0>, <87 0>, <88 0>,
593			<89 0>, <90 0>, <91 0>, <92 0>;
594		no-error-irq;
595		status = "disabled";
596	};
597
598	fmu: flash-controller@43000 {
599		compatible = "nxp,msf1";
600		reg = <0x43000 0x1000>;
601		interrupts = <138 0>;
602		status = "disabled";
603
604		#address-cells = <1>;
605		#size-cells = <1>;
606
607		flash: flash@0 {
608			compatible = "soc-nv-flash";
609			reg = <0 DT_SIZE_M(2)>;
610			erase-block-size = <8192>;
611			/* MCXN94x ROM Flash API supports writing of 128B pages. */
612			write-block-size = <128>;
613		};
614
615		uuid: uuid@1100000 {
616			compatible = "nxp,lpc-uid";
617			reg = <0x1100000 0x10>;
618		};
619	};
620
621	os_timer: timers@49000 {
622		compatible = "nxp,os-timer";
623		reg = <0x49000 0x1000>;
624		interrupts = <57 0>;
625		status = "disabled";
626	};
627
628	dac0: dac@10f000 {
629		compatible = "nxp,lpdac";
630		reg = < 0x10f000 0x1000>;
631		interrupts = <106 0>;
632		status = "disabled";
633		voltage-reference = <0>;
634		#io-channel-cells = <1>;
635	};
636
637	dac1: dac@112000 {
638		compatible = "nxp,lpdac";
639		reg = < 0x112000 0x1000>;
640		interrupts = <107 0>;
641		status = "disabled";
642		voltage-reference = <0>;
643		#io-channel-cells = <1>;
644	};
645
646	enet: ethernet@40100000 {
647		compatible = "nxp,enet-qos";
648		reg = <0x40100000 0x1200>;
649		clocks = <&syscon MCUX_ENET_QOS_CLK>;
650		enet_mac: ethernet {
651			compatible = "nxp,enet-qos-mac";
652			status = "disabled";
653			interrupts = <139 0>, <140 0>, <141 0>;
654			interrupt-names = "mac", "power", "lpi";
655		};
656		enet_mdio: mdio {
657			#address-cells = <1>;
658			#size-cells = <0>;
659			compatible = "nxp,enet-qos-mdio";
660			status = "disabled";
661		};
662	};
663
664	wwdt0: watchdog@16000 {
665		compatible = "nxp,lpc-wwdt";
666		reg = <0x16000 0x1000>;
667		interrupts = <152 0>;
668		status = "disabled";
669		clk-divider = <1>;
670	};
671
672	flexpwm0: flexpwm@ce000 {
673		compatible = "nxp,flexpwm";
674		reg = <0xce000 0x1000>;
675		interrupt-names = "RELOAD-ERROR", "FAULT";
676		interrupts = <112 0>, <113 0>;
677		flexpwm0_pwm0: pwm0 {
678			compatible = "nxp,imx-pwm";
679			index = <0>;
680			interrupts = <114 0>;
681			#pwm-cells = <3>;
682			clocks = <&syscon MCUX_BUS_CLK>;
683			nxp,prescaler = <128>;
684			status = "disabled";
685			run-in-wait;
686		};
687
688		flexpwm0_pwm1: pwm1 {
689			compatible = "nxp,imx-pwm";
690			index = <1>;
691			interrupts = <115 0>;
692			#pwm-cells = <3>;
693			clocks = <&syscon MCUX_BUS_CLK>;
694			nxp,prescaler = <128>;
695			status = "disabled";
696			run-in-wait;
697		};
698
699		flexpwm0_pwm2: pwm2 {
700			compatible = "nxp,imx-pwm";
701			index = <2>;
702			interrupts = <116 0>;
703			#pwm-cells = <3>;
704			clocks = <&syscon MCUX_BUS_CLK>;
705			nxp,prescaler = <128>;
706			status = "disabled";
707			run-in-wait;
708		};
709
710		flexpwm0_pwm3: pwm3 {
711			compatible = "nxp,imx-pwm";
712			index = <3>;
713			interrupts = <117 0>;
714			#pwm-cells = <3>;
715			clocks = <&syscon MCUX_BUS_CLK>;
716			nxp,prescaler = <128>;
717			status = "disabled";
718			run-in-wait;
719		};
720	};
721
722	flexpwm1: flexpwm@d0000 {
723		compatible = "nxp,flexpwm";
724		reg = <0xd0000 0x1000>;
725		interrupt-names = "RELOAD-ERROR", "FAULT";
726		interrupts = <118 0>, <119 0>;
727		flexpwm1_pwm0: pwm0 {
728			compatible = "nxp,imx-pwm";
729			index = <0>;
730			interrupts = <120 0>;
731			#pwm-cells = <3>;
732			clocks = <&syscon MCUX_BUS_CLK>;
733			nxp,prescaler = <128>;
734			status = "disabled";
735			run-in-wait;
736		};
737
738		flexpwm1_pwm1: pwm1 {
739			compatible = "nxp,imx-pwm";
740			index = <1>;
741			interrupts = <121 0>;
742			#pwm-cells = <3>;
743			clocks = <&syscon MCUX_BUS_CLK>;
744			nxp,prescaler = <128>;
745			status = "disabled";
746			run-in-wait;
747		};
748
749		flexpwm1_pwm2: pwm2 {
750			compatible = "nxp,imx-pwm";
751			index = <2>;
752			interrupts = <122 0>;
753			#pwm-cells = <3>;
754			clocks = <&syscon MCUX_BUS_CLK>;
755			nxp,prescaler = <128>;
756			status = "disabled";
757			run-in-wait;
758		};
759
760		flexpwm1_pwm3: pwm3 {
761			compatible = "nxp,imx-pwm";
762			index = <3>;
763			interrupts = <123 0>;
764			#pwm-cells = <3>;
765			clocks = <&syscon MCUX_BUS_CLK>;
766			nxp,prescaler = <128>;
767			status = "disabled";
768			run-in-wait;
769		};
770	};
771
772	ctimer0: ctimer@c000 {
773		compatible = "nxp,lpc-ctimer";
774		reg = <0xc000 0x1000>;
775		interrupts = <31 0>;
776		status = "disabled";
777		clk-source = <1>;
778		clocks = <&syscon MCUX_CTIMER0_CLK>;
779		mode = <0>;
780		input = <0>;
781		prescale = <0>;
782	};
783
784	ctimer1: ctimer@d000 {
785		compatible = "nxp,lpc-ctimer";
786		reg = <0xd000 0x1000>;
787		interrupts = <32 0>;
788		status = "disabled";
789		clk-source = <1>;
790		clocks = <&syscon MCUX_CTIMER1_CLK>;
791		mode = <0>;
792		input = <0>;
793		prescale = <0>;
794	};
795
796	ctimer2: ctimer@e000 {
797		compatible = "nxp,lpc-ctimer";
798		reg = <0xe000 0x1000>;
799		interrupts = <34 0>;
800		status = "disabled";
801		clk-source = <1>;
802		clocks = <&syscon MCUX_CTIMER2_CLK>;
803		mode = <0>;
804		input = <0>;
805		prescale = <0>;
806	};
807
808	ctimer3: ctimer@f000 {
809		compatible = "nxp,lpc-ctimer";
810		reg = <0xf000 0x1000>;
811		interrupts = <55 0>;
812		status = "disabled";
813		clk-source = <1>;
814		clocks = <&syscon MCUX_CTIMER3_CLK>;
815		mode = <0>;
816		input = <0>;
817		prescale = <0>;
818	};
819
820	ctimer4: ctimer@10000 {
821		compatible = "nxp,lpc-ctimer";
822		reg = <0x10000 0x1000>;
823		interrupts = <56 0>;
824		status = "disabled";
825		clk-source = <1>;
826		clocks = <&syscon MCUX_CTIMER4_CLK>;
827		mode = <0>;
828		input = <0>;
829		prescale = <0>;
830	};
831
832	sc_timer: pwm@91000 {
833		compatible = "nxp,sctimer-pwm";
834		reg = <0x91000 0x1000>;
835		interrupts = <33 0>;
836		clocks = <&syscon MCUX_SCTIMER_CLK>;
837		status = "disabled";
838		prescaler = <1>;
839		#pwm-cells = <3>;
840	};
841
842	smartdma: smartdma@33000 {
843		compatible = "nxp,smartdma";
844		reg = <0x33000 0x1000>;
845		status = "disabled";
846		interrupts = <53 0>;
847		program-mem = <0x4000000>;
848		#dma-cells = <0>;
849	};
850
851	usdhc0: usdhc@109000 {
852		compatible = "nxp,imx-usdhc";
853		reg = <0x109000 0x1000>;
854		interrupts = <61 0>;
855		status = "disabled";
856		clocks = <&syscon MCUX_USDHC1_CLK>;
857		max-bus-freq = <52000000>;
858		min-bus-freq = <400000>;
859	};
860
861	vref: vref@111000 {
862		compatible = "nxp,vref";
863		regulator-name = "mcxn94x-vref";
864		reg = <0x111000 0x14>;
865		status = "disabled";
866		#nxp,reference-cells = <1>;
867		nxp,buffer-startup-delay-us = <400>;
868		nxp,bandgap-startup-time-us = <20>;
869		regulator-min-microvolt = <1000000>;
870		regulator-max-microvolt = <2100000>;
871
872	};
873
874	lpadc0: adc@10d000 {
875		compatible = "nxp,lpc-lpadc";
876		reg = <0x10d000 0x1000>;
877		interrupts = <45 0>;
878		status = "disabled";
879		voltage-ref= <1>;
880		calibration-average = <128>;
881		power-level = <0>;
882		offset-value-a = <0>;
883		offset-value-b = <0>;
884		#io-channel-cells = <1>;
885		clocks = <&syscon MCUX_LPADC1_CLK>;
886		nxp,references = <&vref 1800>;
887	};
888
889	lpadc1: adc@10e000 {
890		compatible = "nxp,lpc-lpadc";
891		reg = <0x10e000 0x1000>;
892		interrupts = <46 0>;
893		status = "disabled";
894		voltage-ref= <0>;
895		calibration-average = <128>;
896		power-level = <1>;
897		offset-value-a = <0>;
898		offset-value-b = <0>;
899		#io-channel-cells = <1>;
900		clocks = <&syscon MCUX_LPADC2_CLK>;
901	};
902
903	usb0: usbd@dd000 {
904		compatible = "nxp,kinetis-usbd";
905		reg = <0xdd000 0x1000>;
906		interrupts = <50 1>;
907		interrupt-names = "usbfs0";
908		num-bidir-endpoints = <16>;
909		no-voltage-regulator;
910		status = "disabled";
911	};
912
913	usb1: usbd@10b000 {
914		compatible = "nxp,ehci";
915		reg = <0x10b000 0x1000>;
916		interrupts = <67 0>;
917		interrupt-names = "usb_otg";
918		num-bidir-endpoints = <8>;
919		status = "disabled";
920	};
921
922	usbphy1: usbphy@10a000 {
923		compatible = "nxp,usbphy";
924		reg = <0x10a000 0x1000>;
925		status = "disabled";
926	};
927
928	lpcmp0: lpcmp@51000 {
929		compatible = "nxp,lpcmp";
930		reg = <0x51000 0x1000>;
931		interrupts = <109 0>;
932		status = "disabled";
933		#io-channel-cells = <2>;
934	};
935
936	lpcmp1: lpcmp@52000 {
937		compatible = "nxp,lpcmp";
938		reg = <0x52000 0x1000>;
939		interrupts = <110 0>;
940		status = "disabled";
941		#io-channel-cells = <2>;
942	};
943
944	lpcmp2: lpcmp@53000 {
945		compatible = "nxp,lpcmp";
946		reg = <0x53000 0x1000>;
947		interrupts = <111 0>;
948		status = "disabled";
949		#io-channel-cells = <2>;
950	};
951
952	flexcan0: can@d4000 {
953		compatible = "nxp,flexcan";
954		reg = <0xd4000 0x4000>;
955		interrupts = <62 0>;
956		interrupt-names = "common";
957		clocks = <&syscon MCUX_FLEXCAN0_CLK>;
958		clk-source = <0>;
959		status = "disabled";
960	};
961
962	flexcan1: can@d8000 {
963		compatible = "nxp,flexcan";
964		reg = <0xd8000 0x4000>;
965		interrupts = <63 0>;
966		interrupt-names = "common";
967		clocks = <&syscon MCUX_FLEXCAN1_CLK>;
968		clk-source = <0>;
969		status = "disabled";
970	};
971
972	lptmr0: lptmr@4a000 {
973		compatible = "nxp,lptmr";
974		reg = <0x4a000 0x1000>;
975		interrupts = <143 0>;
976		clock-frequency = <16000>;
977		prescaler = <1>;
978		clk-source = <1>;
979		resolution = <32>;
980	};
981
982	lptmr1: lptmr@4b000 {
983		compatible = "nxp,lptmr";
984		reg = <0x4b000 0x1000>;
985		interrupts = <144 0>;
986		clock-frequency = <16000>;
987		prescaler = <1>;
988		clk-source = <1>;
989		resolution = <32>;
990	};
991
992	i3c0: i3c@21000 {
993		compatible = "nxp,mcux-i3c";
994		reg = <0x21000 0x1000>;
995		interrupts = <95 0>;
996		clocks = <&syscon MCUX_I3C_CLK>;
997		clk-divider = <6>;
998		clk-divider-slow = <1>;
999		clk-divider-tc = <1>;
1000		status = "disabled";
1001		#address-cells = <3>;
1002		#size-cells = <0>;
1003	};
1004
1005	i3c1: i3c@22000 {
1006		compatible = "nxp,mcux-i3c";
1007		reg = <0x22000 0x1000>;
1008		interrupts = <96 0>;
1009		clocks = <&syscon MCUX_I3C2_CLK>;
1010		clk-divider = <6>;
1011		clk-divider-slow = <1>;
1012		clk-divider-tc = <1>;
1013		status = "disabled";
1014		#address-cells = <3>;
1015		#size-cells = <0>;
1016	};
1017
1018	flexio0: flexio@105000 {
1019		compatible = "nxp,flexio";
1020		reg = <0x105000 0x1000>;
1021		status = "disabled";
1022		interrupts = <105 0>;
1023		clocks = <&syscon MCUX_FLEXIO0_CLK>;
1024		flexio0_lcd: flexio0-lcd {
1025			compatible = "nxp,mipi-dbi-flexio-lcdif";
1026			status = "disabled";
1027		};
1028	};
1029
1030	mrt0: mrt@13000 {
1031		compatible = "nxp,mrt";
1032		reg = <0x13000 0x1000>;
1033		interrupts = <30 0>;
1034		num-channels = <4>;
1035		num-bits = <24>;
1036		clocks = <&syscon MCUX_MRT_CLK>;
1037		resets = <&reset NXP_SYSCON_RESET(1, 0)>;
1038		#address-cells = <1>;
1039		#size-cells = <0>;
1040
1041		mrt0_channel0: mrt0_channel@0 {
1042			compatible = "nxp,mrt-channel";
1043			reg = <0>;
1044			status = "disabled";
1045		};
1046		mrt0_channel1: mrt0_channel@1 {
1047			compatible = "nxp,mrt-channel";
1048			reg = <1>;
1049			status = "disabled";
1050		};
1051		mrt0_channel2: mrt0_channel@2 {
1052			compatible = "nxp,mrt-channel";
1053			reg = <2>;
1054			status = "disabled";
1055		};
1056		mrt0_channel3: mrt0_channel@3 {
1057			compatible = "nxp,mrt-channel";
1058			reg = <3>;
1059			status = "disabled";
1060		};
1061	};
1062
1063	rtc: rtc@4c000 {
1064		compatible = "nxp,irtc";
1065		reg = <0x4c000 0x1000>;
1066		status = "disabled";
1067		interrupts = <52 0>;
1068		prescaler = <1>;
1069		clock-frequency = <16384>;
1070		clock-src = <0>;
1071		alarms-count = <1>;
1072	};
1073
1074	sai0: sai@106000 {
1075		compatible = "nxp,mcux-i2s";
1076		#address-cells = <1>;
1077		#size-cells = <0>;
1078		#pinmux-cells = <2>;
1079		reg = < 0x106000 0x1000>;
1080		clocks = <&syscon MCUX_SAI0_CLK>;
1081		pinmuxes = <&sai0 0x100 0x40000000>;
1082		interrupts = <59 0>;
1083		dmas = <&edma0 0 99>, <&edma0 0 100>;
1084		dma-names = "rx", "tx";
1085		nxp,tx-channel = <1>;
1086		nxp,tx-dma-channel = <0>;
1087		nxp,rx-dma-channel = <1>;
1088		status = "disabled";
1089	};
1090	sai1: sai@107000 {
1091		compatible = "nxp,mcux-i2s";
1092		#address-cells = <1>;
1093		#size-cells = <0>;
1094		#pinmux-cells = <2>;
1095		reg = < 0x107000 0x1000>;
1096		clocks = <&syscon MCUX_SAI1_CLK>;
1097		pinmuxes = <&sai1 0x100 0x40000000>;
1098		interrupts = <60 0>;
1099		dmas = <&edma0 0 101>, <&edma0 0 102>;
1100		dma-names = "rx", "tx";
1101		nxp,tx-channel = <1>;
1102		nxp,tx-dma-channel = <2>;
1103		nxp,rx-dma-channel = <3>;
1104		status = "disabled";
1105	};
1106};
1107
1108&systick {
1109	/*
1110	 * MCXN94X relies by default on the OS Timer for system clock
1111	 * implementation, so the SysTick node is not to be enabled.
1112	 */
1113	status = "disabled";
1114};
1115
1116&flexspi {
1117	compatible = "nxp,imx-flexspi";
1118	interrupts = <58 0>;
1119	#address-cells = <1>;
1120	#size-cells = <0>;
1121	status = "disabled";
1122	clocks = <&syscon MCUX_FLEXSPI_CLK>;
1123};
1124
1125&nvic {
1126	arm,num-irq-priority-bits = <3>;
1127};
1128