1/* 2 * Copyright 2024 NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <mem.h> 8#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h> 9#include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h> 10#include <zephyr/dt-bindings/gpio/gpio.h> 11#include <arm/armv8-m.dtsi> 12#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h> 13 14/ { 15 cpus: cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu@0 { 20 compatible = "arm,cortex-m33f"; 21 reg = <0>; 22 #address-cells = <1>; 23 #size-cells = <1>; 24 25 mpu: mpu@e000ed90 { 26 compatible = "arm,armv8m-mpu"; 27 reg = <0xe000ed90 0x40>; 28 }; 29 }; 30 }; 31 32 pinctrl: pinctrl { 33 compatible = "nxp,port-pinctrl"; 34 status = "okay"; 35 }; 36}; 37 38&sram { 39 #address-cells = <1>; 40 #size-cells = <1>; 41 42 sramx: memory@4000000 { 43 compatible = "zephyr,memory-region", "mmio-sram"; 44 reg = <0x4000000 DT_SIZE_K(96)>; 45 zephyr,memory-region = "SRAM1"; 46 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; 47 }; 48 49 /* mcxn23x Memory configurations: 50 * 51 * RAM blocks RAMA through SRAM4 are contiguous address ranges 52 * 53 * MCXN23X: 352KB RAM, RAMX: 96K, RAMA: 32K, RAMB: 32K, 54 * RAMC: 64K, RAMD: 64K, RAME: 64K 55 */ 56 sram0: memory@20000000 { 57 compatible = "mmio-sram"; 58 reg = <0x20000000 DT_SIZE_K(256)>; 59 }; 60}; 61 62&peripheral { 63 #address-cells = <1>; 64 #size-cells = <1>; 65 66 syscon: syscon@0 { 67 compatible = "nxp,lpc-syscon"; 68 reg = <0x0 0x4000>; 69 #clock-cells = <1>; 70 reset: reset { 71 compatible = "nxp,lpc-syscon-reset"; 72 #reset-cells = <1>; 73 }; 74 }; 75 76 porta: pinmux@116000 { 77 compatible = "nxp,port-pinmux"; 78 reg = <0x116000 0x1000>; 79 clocks = <&syscon MCUX_PORT0_CLK>; 80 }; 81 82 portb: pinmux@117000 { 83 compatible = "nxp,port-pinmux"; 84 reg = <0x117000 0x1000>; 85 clocks = <&syscon MCUX_PORT1_CLK>; 86 }; 87 88 portc: pinmux@118000 { 89 compatible = "nxp,port-pinmux"; 90 reg = <0x118000 0x1000>; 91 clocks = <&syscon MCUX_PORT2_CLK>; 92 }; 93 94 portd: pinmux@119000 { 95 compatible = "nxp,port-pinmux"; 96 reg = <0x119000 0x1000>; 97 clocks = <&syscon MCUX_PORT3_CLK>; 98 }; 99 100 porte: pinmux@11a000 { 101 compatible = "nxp,port-pinmux"; 102 reg = <0x11a000 0x1000>; 103 clocks = <&syscon MCUX_PORT4_CLK>; 104 }; 105 106 portf: pinmux@42000 { 107 compatible = "nxp,port-pinmux"; 108 reg = <0x42000 0x1000>; 109 clocks = <&syscon MCUX_PORT5_CLK>; 110 }; 111 112 gpio0: gpio@96000 { 113 compatible = "nxp,kinetis-gpio"; 114 status = "disabled"; 115 reg = <0x96000 0x1000>; 116 interrupts = <17 0>,<18 0>; 117 gpio-controller; 118 #gpio-cells = <2>; 119 nxp,kinetis-port = <&porta>; 120 }; 121 122 gpio1: gpio@98000 { 123 compatible = "nxp,kinetis-gpio"; 124 status = "disabled"; 125 reg = <0x98000 0x1000>; 126 interrupts = <19 0>,<20 0>; 127 gpio-controller; 128 #gpio-cells = <2>; 129 nxp,kinetis-port = <&portb>; 130 }; 131 132 gpio2: gpio@9a000 { 133 compatible = "nxp,kinetis-gpio"; 134 status = "disabled"; 135 reg = <0x9a000 0x1000>; 136 interrupts = <21 0>,<22 0>; 137 gpio-controller; 138 #gpio-cells = <2>; 139 nxp,kinetis-port = <&portc>; 140 }; 141 142 gpio3: gpio@9c000 { 143 compatible = "nxp,kinetis-gpio"; 144 status = "disabled"; 145 reg = <0x9c000 0x1000>; 146 interrupts = <23 0>,<24 0>; 147 gpio-controller; 148 #gpio-cells = <2>; 149 nxp,kinetis-port = <&portd>; 150 }; 151 152 gpio4: gpio@9e000 { 153 compatible = "nxp,kinetis-gpio"; 154 status = "disabled"; 155 reg = <0x9e000 0x1000>; 156 interrupts = <25 0>,<26 0>; 157 gpio-controller; 158 #gpio-cells = <2>; 159 nxp,kinetis-port = <&porte>; 160 }; 161 162 gpio5: gpio@40000 { 163 compatible = "nxp,kinetis-gpio"; 164 status = "disabled"; 165 reg = <0x40000 0x1000>; 166 interrupts = <27 0>,<28 0>; 167 gpio-controller; 168 #gpio-cells = <2>; 169 nxp,kinetis-port = <&portf>; 170 }; 171 172 flexcomm0: flexcomm@92000 { 173 compatible = "nxp,lp-flexcomm"; 174 reg = <0x92000 0x1000>; 175 interrupts = <35 0>; 176 status = "disabled"; 177 178 ranges = <>; 179 #address-cells = <1>; 180 #size-cells = <1>; 181 182 flexcomm0_lpuart0: lpuart@92000 { 183 compatible = "nxp,lpuart"; 184 reg = <0x92000 0x1000>; 185 clocks = <&syscon MCUX_FLEXCOMM0_CLK>; 186 status = "disabled"; 187 }; 188 flexcomm0_lpspi0: spi@92000 { 189 compatible = "nxp,lpspi"; 190 reg = <0x92000 0x1000>; 191 clocks = <&syscon MCUX_FLEXCOMM0_CLK>; 192 #address-cells = <1>; 193 #size-cells = <0>; 194 status = "disabled"; 195 }; 196 flexcomm0_lpi2c0: lpi2c@92800 { 197 compatible = "nxp,lpi2c"; 198 reg = <0x92800 0x1000>; 199 clocks = <&syscon MCUX_FLEXCOMM0_CLK>; 200 #address-cells = <1>; 201 #size-cells = <0>; 202 status = "disabled"; 203 }; 204 }; 205 206 flexcomm1: flexcomm@93000 { 207 compatible = "nxp,lp-flexcomm"; 208 reg = <0x93000 0x1000>; 209 interrupts = <36 0>; 210 status = "disabled"; 211 212 ranges = <>; 213 #address-cells = <1>; 214 #size-cells = <1>; 215 216 flexcomm1_lpuart1: lpuart@93000 { 217 compatible = "nxp,lpuart"; 218 reg = <0x93000 0x1000>; 219 clocks = <&syscon MCUX_FLEXCOMM1_CLK>; 220 /* DMA channels 0 and 1, muxed to LPUART1 RX and TX */ 221 dmas = <&edma0 0 71>, <&edma0 1 72>; 222 dma-names = "rx", "tx"; 223 status = "disabled"; 224 }; 225 flexcomm1_lpspi1: spi@93000 { 226 compatible = "nxp,lpspi"; 227 reg = <0x93000 0x1000>; 228 clocks = <&syscon MCUX_FLEXCOMM1_CLK>; 229 #address-cells = <1>; 230 #size-cells = <0>; 231 /* DMA channels 0 and 1, muxed to LPSPI1 RX and TX */ 232 dmas = <&edma0 0 71>, <&edma0 1 72>; 233 dma-names = "rx", "tx"; 234 status = "disabled"; 235 }; 236 flexcomm1_lpi2c1: lpi2c@93800 { 237 compatible = "nxp,lpi2c"; 238 reg = <0x93800 0x1000>; 239 clocks = <&syscon MCUX_FLEXCOMM1_CLK>; 240 #address-cells = <1>; 241 #size-cells = <0>; 242 status = "disabled"; 243 }; 244 }; 245 246 flexcomm2: flexcomm@94000 { 247 compatible = "nxp,lp-flexcomm"; 248 reg = <0x94000 0x1000>; 249 interrupts = <37 0>; 250 status = "disabled"; 251 252 ranges = <>; 253 #address-cells = <1>; 254 #size-cells = <1>; 255 256 flexcomm2_lpuart2: lpuart@94000 { 257 compatible = "nxp,lpuart"; 258 reg = <0x94000 0x1000>; 259 clocks = <&syscon MCUX_FLEXCOMM2_CLK>; 260 /* DMA channels 4 and 5, muxed to LPUART2 RX and TX */ 261 dmas = <&edma0 4 73>, <&edma0 5 74>; 262 dma-names = "rx", "tx"; 263 status = "disabled"; 264 }; 265 flexcomm2_lpspi2: spi@94000 { 266 compatible = "nxp,lpspi"; 267 reg = <0x94000 0x1000>; 268 clocks = <&syscon MCUX_FLEXCOMM2_CLK>; 269 #address-cells = <1>; 270 #size-cells = <0>; 271 /* DMA channels 4 and 5, muxed to LPSPI2 RX and TX */ 272 dmas = <&edma0 4 73>, <&edma0 5 74>; 273 dma-names = "rx", "tx"; 274 status = "disabled"; 275 }; 276 flexcomm2_lpi2c2: lpi2c@94800 { 277 compatible = "nxp,lpi2c"; 278 reg = <0x94800 0x1000>; 279 clocks = <&syscon MCUX_FLEXCOMM2_CLK>; 280 #address-cells = <1>; 281 #size-cells = <0>; 282 status = "disabled"; 283 }; 284 }; 285 286 flexcomm3: flexcomm@95000 { 287 compatible = "nxp,lp-flexcomm"; 288 reg = <0x95000 0x1000>; 289 interrupts = <38 0>; 290 status = "disabled"; 291 292 ranges = <>; 293 #address-cells = <1>; 294 #size-cells = <1>; 295 296 flexcomm3_lpuart3: lpuart@95000 { 297 compatible = "nxp,lpuart"; 298 reg = <0x95000 0x1000>; 299 clocks = <&syscon MCUX_FLEXCOMM3_CLK>; 300 status = "disabled"; 301 }; 302 flexcomm3_lpspi3: spi@95000 { 303 compatible = "nxp,lpspi"; 304 reg = <0x95000 0x1000>; 305 clocks = <&syscon MCUX_FLEXCOMM3_CLK>; 306 #address-cells = <1>; 307 #size-cells = <0>; 308 status = "disabled"; 309 }; 310 flexcomm3_lpi2c3: lpi2c@95800 { 311 compatible = "nxp,lpi2c"; 312 reg = <0x95800 0x1000>; 313 clocks = <&syscon MCUX_FLEXCOMM3_CLK>; 314 #address-cells = <1>; 315 #size-cells = <0>; 316 status = "disabled"; 317 }; 318 }; 319 320 flexcomm4: flexcomm@b4000 { 321 compatible = "nxp,lp-flexcomm"; 322 reg = <0xb4000 0x1000>; 323 interrupts = <39 0>; 324 status = "disabled"; 325 326 ranges = <>; 327 #address-cells = <1>; 328 #size-cells = <1>; 329 330 flexcomm4_lpuart4: lpuart@b4000 { 331 compatible = "nxp,lpuart"; 332 reg = <0xb4000 0x1000>; 333 clocks = <&syscon MCUX_FLEXCOMM4_CLK>; 334 /* DMA channels 2 and 3, muxed to LPUART4 RX and TX */ 335 dmas = <&edma0 2 77>, <&edma0 3 78>; 336 dma-names = "rx", "tx"; 337 status = "disabled"; 338 }; 339 flexcomm4_lpspi4: spi@b4000 { 340 compatible = "nxp,lpspi"; 341 reg = <0xb4000 0x1000>; 342 clocks = <&syscon MCUX_FLEXCOMM4_CLK>; 343 #address-cells = <1>; 344 #size-cells = <0>; 345 /* DMA channels 2 and 3, muxed to LPSPI4 RX and TX */ 346 dmas = <&edma0 2 77>, <&edma0 3 78>; 347 dma-names = "rx", "tx"; 348 status = "disabled"; 349 }; 350 flexcomm4_lpi2c4: lpi2c@b4800 { 351 compatible = "nxp,lpi2c"; 352 reg = <0xb4800 0x1000>; 353 clocks = <&syscon MCUX_FLEXCOMM4_CLK>; 354 #address-cells = <1>; 355 #size-cells = <0>; 356 status = "disabled"; 357 }; 358 }; 359 360 flexcomm5: flexcomm@b5000 { 361 compatible = "nxp,lp-flexcomm"; 362 reg = <0xb5000 0x1000>; 363 interrupts = <40 0>; 364 status = "disabled"; 365 366 ranges = <>; 367 #address-cells = <1>; 368 #size-cells = <1>; 369 370 flexcomm5_lpuart5: lpuart@b5000 { 371 compatible = "nxp,lpuart"; 372 reg = <0xb5000 0x1000>; 373 clocks = <&syscon MCUX_FLEXCOMM5_CLK>; 374 status = "disabled"; 375 }; 376 flexcomm5_lpspi5: spi@b5000 { 377 compatible = "nxp,lpspi"; 378 reg = <0xb5000 0x1000>; 379 clocks = <&syscon MCUX_FLEXCOMM5_CLK>; 380 #address-cells = <1>; 381 #size-cells = <0>; 382 status = "disabled"; 383 }; 384 flexcomm5_lpi2c5: lpi2c@b5800 { 385 compatible = "nxp,lpi2c"; 386 reg = <0xb5800 0x1000>; 387 clocks = <&syscon MCUX_FLEXCOMM5_CLK>; 388 #address-cells = <1>; 389 #size-cells = <0>; 390 status = "disabled"; 391 }; 392 }; 393 394 flexcomm6: flexcomm@b6000 { 395 compatible = "nxp,lp-flexcomm"; 396 reg = <0xb6000 0x1000>; 397 interrupts = <41 0>; 398 status = "disabled"; 399 400 ranges = <>; 401 #address-cells = <1>; 402 #size-cells = <1>; 403 404 flexcomm6_lpuart6: lpuart@b6000 { 405 compatible = "nxp,lpuart"; 406 reg = <0xb6000 0x1000>; 407 clocks = <&syscon MCUX_FLEXCOMM6_CLK>; 408 status = "disabled"; 409 }; 410 flexcomm6_lpspi6: spi@b6000 { 411 compatible = "nxp,lpspi"; 412 reg = <0xb6000 0x1000>; 413 clocks = <&syscon MCUX_FLEXCOMM6_CLK>; 414 #address-cells = <1>; 415 #size-cells = <0>; 416 status = "disabled"; 417 }; 418 flexcomm6_lpi2c6: lpi2c@b6800 { 419 compatible = "nxp,lpi2c"; 420 reg = <0xb6800 0x1000>; 421 clocks = <&syscon MCUX_FLEXCOMM6_CLK>; 422 #address-cells = <1>; 423 #size-cells = <0>; 424 status = "disabled"; 425 }; 426 }; 427 428 flexcomm7: flexcomm@b7000 { 429 compatible = "nxp,lp-flexcomm"; 430 reg = <0xb7000 0x1000>; 431 interrupts = <42 0>; 432 status = "disabled"; 433 434 ranges = <>; 435 #address-cells = <1>; 436 #size-cells = <1>; 437 438 flexcomm7_lpuart7: lpuart@b7000 { 439 compatible = "nxp,lpuart"; 440 reg = <0xb7000 0x1000>; 441 clocks = <&syscon MCUX_FLEXCOMM7_CLK>; 442 status = "disabled"; 443 }; 444 flexcomm7_lpspi7: spi@b7000 { 445 compatible = "nxp,lpspi"; 446 reg = <0xb7000 0x1000>; 447 clocks = <&syscon MCUX_FLEXCOMM7_CLK>; 448 #address-cells = <1>; 449 #size-cells = <0>; 450 status = "disabled"; 451 }; 452 flexcomm7_lpi2c7: lpi2c@b7800 { 453 compatible = "nxp,lpi2c"; 454 reg = <0xb7800 0x1000>; 455 clocks = <&syscon MCUX_FLEXCOMM7_CLK>; 456 #address-cells = <1>; 457 #size-cells = <0>; 458 status = "disabled"; 459 }; 460 }; 461 462 edma0: dma-controller@80000 { 463 #dma-cells = <2>; 464 compatible = "nxp,mcux-edma"; 465 nxp,version = <4>; 466 dma-channels = <16>; 467 dma-requests = <120>; 468 469 reg = <0x80000 0x1000>; 470 interrupts = <1 0>, <2 0>, <3 0>, <4 0>, 471 <5 0>, <6 0>, <7 0>, <8 0>, 472 <9 0>, <10 0>, <11 0>, <12 0>, 473 <13 0>, <14 0>, <15 0>, <16 0>; 474 no-error-irq; 475 status = "disabled"; 476 }; 477 478 edma1: dma-controller@a0000 { 479 #dma-cells = <2>; 480 compatible = "nxp,mcux-edma"; 481 nxp,version = <4>; 482 dma-channels = <16>; 483 dma-requests = <120>; 484 485 reg = <0xa0000 0x1000>; 486 interrupts = <77 0>, <78 0>, <79 0>, <80 0>, 487 <81 0>, <82 0>, <83 0>, <84 0>, 488 <85 0>, <86 0>, <87 0>, <88 0>, 489 <89 0>, <90 0>, <91 0>, <92 0>; 490 no-error-irq; 491 status = "disabled"; 492 }; 493 494 fmu: flash-controller@43000 { 495 compatible = "nxp,msf1"; 496 reg = <0x43000 0x1000>; 497 interrupts = <138 0>; 498 status = "disabled"; 499 500 #address-cells = <1>; 501 #size-cells = <1>; 502 503 flash: flash@0 { 504 compatible = "soc-nv-flash"; 505 reg = <0 DT_SIZE_M(1)>; 506 erase-block-size = <8192>; 507 /* MCXN23x ROM Flash API supports writing of 128B pages. */ 508 write-block-size = <128>; 509 }; 510 }; 511 512 os_timer: timers@49000 { 513 compatible = "nxp,os-timer"; 514 reg = <0x49000 0x1000>; 515 interrupts = <57 0>; 516 status = "disabled"; 517 }; 518 519 wwdt0: watchdog@16000 { 520 compatible = "nxp,lpc-wwdt"; 521 reg = <0x16000 0x1000>; 522 interrupts = <152 0>; 523 status = "disabled"; 524 clk-divider = <1>; 525 }; 526 527 flexpwm0: flexpwm@ce000 { 528 compatible = "nxp,flexpwm"; 529 reg = <0xce000 0x1000>; 530 interrupt-names = "RELOAD-ERROR", "FAULT"; 531 interrupts = <112 0>, <113 0>; 532 flexpwm0_pwm0: pwm0 { 533 compatible = "nxp,imx-pwm"; 534 index = <0>; 535 interrupts = <114 0>; 536 #pwm-cells = <3>; 537 clocks = <&syscon MCUX_BUS_CLK>; 538 nxp,prescaler = <128>; 539 status = "disabled"; 540 run-in-wait; 541 }; 542 543 flexpwm0_pwm1: pwm1 { 544 compatible = "nxp,imx-pwm"; 545 index = <1>; 546 interrupts = <115 0>; 547 #pwm-cells = <3>; 548 clocks = <&syscon MCUX_BUS_CLK>; 549 nxp,prescaler = <128>; 550 status = "disabled"; 551 run-in-wait; 552 }; 553 554 flexpwm0_pwm2: pwm2 { 555 compatible = "nxp,imx-pwm"; 556 index = <2>; 557 interrupts = <116 0>; 558 #pwm-cells = <3>; 559 clocks = <&syscon MCUX_BUS_CLK>; 560 nxp,prescaler = <128>; 561 status = "disabled"; 562 run-in-wait; 563 }; 564 565 flexpwm0_pwm3: pwm3 { 566 compatible = "nxp,imx-pwm"; 567 index = <3>; 568 interrupts = <117 0>; 569 #pwm-cells = <3>; 570 clocks = <&syscon MCUX_BUS_CLK>; 571 nxp,prescaler = <128>; 572 status = "disabled"; 573 run-in-wait; 574 }; 575 }; 576 577 flexpwm1: flexpwm@d0000 { 578 compatible = "nxp,flexpwm"; 579 reg = <0xd0000 0x1000>; 580 interrupt-names = "RELOAD-ERROR", "FAULT"; 581 interrupts = <118 0>, <119 0>; 582 flexpwm1_pwm0: pwm0 { 583 compatible = "nxp,imx-pwm"; 584 index = <0>; 585 interrupts = <120 0>; 586 #pwm-cells = <3>; 587 clocks = <&syscon MCUX_BUS_CLK>; 588 nxp,prescaler = <128>; 589 status = "disabled"; 590 run-in-wait; 591 }; 592 593 flexpwm1_pwm1: pwm1 { 594 compatible = "nxp,imx-pwm"; 595 index = <1>; 596 interrupts = <121 0>; 597 #pwm-cells = <3>; 598 clocks = <&syscon MCUX_BUS_CLK>; 599 nxp,prescaler = <128>; 600 status = "disabled"; 601 run-in-wait; 602 }; 603 604 flexpwm1_pwm2: pwm2 { 605 compatible = "nxp,imx-pwm"; 606 index = <2>; 607 interrupts = <122 0>; 608 #pwm-cells = <3>; 609 clocks = <&syscon MCUX_BUS_CLK>; 610 nxp,prescaler = <128>; 611 status = "disabled"; 612 run-in-wait; 613 }; 614 615 flexpwm1_pwm3: pwm3 { 616 compatible = "nxp,imx-pwm"; 617 index = <3>; 618 interrupts = <123 0>; 619 #pwm-cells = <3>; 620 clocks = <&syscon MCUX_BUS_CLK>; 621 nxp,prescaler = <128>; 622 status = "disabled"; 623 run-in-wait; 624 }; 625 }; 626 627 ctimer0: ctimer@c000 { 628 compatible = "nxp,lpc-ctimer"; 629 reg = <0xc000 0x1000>; 630 interrupts = <31 0>; 631 status = "disabled"; 632 clk-source = <1>; 633 clocks = <&syscon MCUX_CTIMER0_CLK>; 634 mode = <0>; 635 input = <0>; 636 prescale = <0>; 637 }; 638 639 ctimer1: ctimer@d000 { 640 compatible = "nxp,lpc-ctimer"; 641 reg = <0xd000 0x1000>; 642 interrupts = <32 0>; 643 status = "disabled"; 644 clk-source = <1>; 645 clocks = <&syscon MCUX_CTIMER1_CLK>; 646 mode = <0>; 647 input = <0>; 648 prescale = <0>; 649 }; 650 651 ctimer2: ctimer@e000 { 652 compatible = "nxp,lpc-ctimer"; 653 reg = <0xe000 0x1000>; 654 interrupts = <34 0>; 655 status = "disabled"; 656 clk-source = <1>; 657 clocks = <&syscon MCUX_CTIMER2_CLK>; 658 mode = <0>; 659 input = <0>; 660 prescale = <0>; 661 }; 662 663 ctimer3: ctimer@f000 { 664 compatible = "nxp,lpc-ctimer"; 665 reg = <0xf000 0x1000>; 666 interrupts = <55 0>; 667 status = "disabled"; 668 clk-source = <1>; 669 clocks = <&syscon MCUX_CTIMER3_CLK>; 670 mode = <0>; 671 input = <0>; 672 prescale = <0>; 673 }; 674 675 ctimer4: ctimer@10000 { 676 compatible = "nxp,lpc-ctimer"; 677 reg = <0x10000 0x1000>; 678 interrupts = <56 0>; 679 status = "disabled"; 680 clk-source = <1>; 681 clocks = <&syscon MCUX_CTIMER4_CLK>; 682 mode = <0>; 683 input = <0>; 684 prescale = <0>; 685 }; 686 687 vref: vref@111000 { 688 compatible = "nxp,vref"; 689 regulator-name = "mcxn23x-vref"; 690 reg = <0x111000 0x14>; 691 status = "disabled"; 692 #nxp,reference-cells = <1>; 693 nxp,buffer-startup-delay-us = <400>; 694 nxp,bandgap-startup-time-us = <20>; 695 regulator-min-microvolt = <1000000>; 696 regulator-max-microvolt = <2100000>; 697 }; 698 699 lpadc0: lpadc@10d000 { 700 compatible = "nxp,lpc-lpadc"; 701 reg = <0x10d000 0x1000>; 702 interrupts = <45 0>; 703 status = "disabled"; 704 clk-divider = <1>; 705 clk-source = <0>; 706 voltage-ref= <1>; 707 calibration-average = <128>; 708 power-level = <0>; 709 offset-value-a = <0>; 710 offset-value-b = <0>; 711 #io-channel-cells = <1>; 712 clocks = <&syscon MCUX_LPADC1_CLK>; 713 nxp,references = <&vref 1800>; 714 }; 715 716 lpadc1: lpadc@10e000 { 717 compatible = "nxp,lpc-lpadc"; 718 reg = <0x10e000 0x1000>; 719 interrupts = <46 0>; 720 status = "disabled"; 721 clk-divider = <1>; 722 clk-source = <0>; 723 voltage-ref= <0>; 724 calibration-average = <128>; 725 power-level = <1>; 726 offset-value-a = <0>; 727 offset-value-b = <0>; 728 #io-channel-cells = <1>; 729 clocks = <&syscon MCUX_LPADC2_CLK>; 730 }; 731 732 usb1: usbd@10b000 { 733 compatible = "nxp,ehci"; 734 reg = <0x10b000 0x1000>; 735 interrupts = <67 0>; 736 interrupt-names = "usb_otg"; 737 num-bidir-endpoints = <8>; 738 status = "disabled"; 739 }; 740 741 lpcmp0: lpcmp@51000 { 742 compatible = "nxp,lpcmp"; 743 reg = <0x51000 0x1000>; 744 interrupts = <109 0>; 745 status = "disabled"; 746 #io-channel-cells = <2>; 747 }; 748 749 lpcmp1: lpcmp@52000 { 750 compatible = "nxp,lpcmp"; 751 reg = <0x52000 0x1000>; 752 interrupts = <110 0>; 753 status = "disabled"; 754 #io-channel-cells = <2>; 755 }; 756 757 flexcan0: can@d4000 { 758 compatible = "nxp,flexcan"; 759 reg = <0xd4000 0x4000>; 760 interrupts = <62 0>; 761 interrupt-names = "common"; 762 clocks = <&syscon MCUX_FLEXCAN0_CLK>; 763 clk-source = <0>; 764 status = "disabled"; 765 }; 766 767 flexcan1: can@d8000 { 768 compatible = "nxp,flexcan"; 769 reg = <0xd8000 0x4000>; 770 interrupts = <63 0>; 771 interrupt-names = "common"; 772 clocks = <&syscon MCUX_FLEXCAN1_CLK>; 773 clk-source = <0>; 774 status = "disabled"; 775 }; 776 777 flexio0: flexio@105000 { 778 compatible = "nxp,flexio"; 779 reg = <0x105000 0x1000>; 780 status = "disabled"; 781 interrupts = <105 0>; 782 clocks = <&syscon MCUX_FLEXIO0_CLK>; 783 flexio0_lcd: flexio0-lcd { 784 compatible = "nxp,mipi-dbi-flexio-lcdif"; 785 status = "disabled"; 786 }; 787 }; 788 789 lptmr0: lptmr@4a000 { 790 compatible = "nxp,lptmr"; 791 reg = <0x4a000 0x1000>; 792 interrupts = <143 0>; 793 clock-frequency = <16000>; 794 prescaler = <1>; 795 clk-source = <1>; 796 resolution = <32>; 797 }; 798 799 lptmr1: lptmr@4b000 { 800 compatible = "nxp,lptmr"; 801 reg = <0x4b000 0x1000>; 802 interrupts = <144 0>; 803 clock-frequency = <16000>; 804 prescaler = <1>; 805 clk-source = <1>; 806 resolution = <32>; 807 }; 808 809 mrt0: mrt@13000 { 810 compatible = "nxp,mrt"; 811 reg = <0x13000 0x1000>; 812 interrupts = <30 0>; 813 num-channels = <4>; 814 num-bits = <24>; 815 clocks = <&syscon MCUX_MRT_CLK>; 816 resets = <&reset NXP_SYSCON_RESET(1, 0)>; 817 #address-cells = <1>; 818 #size-cells = <0>; 819 820 mrt0_channel0: mrt0_channel@0 { 821 compatible = "nxp,mrt-channel"; 822 reg = <0>; 823 status = "disabled"; 824 }; 825 mrt0_channel1: mrt0_channel@1 { 826 compatible = "nxp,mrt-channel"; 827 reg = <1>; 828 status = "disabled"; 829 }; 830 mrt0_channel2: mrt0_channel@2 { 831 compatible = "nxp,mrt-channel"; 832 reg = <2>; 833 status = "disabled"; 834 }; 835 mrt0_channel3: mrt0_channel@3 { 836 compatible = "nxp,mrt-channel"; 837 reg = <3>; 838 status = "disabled"; 839 }; 840 }; 841 842 rtc: rtc@4c000 { 843 compatible = "nxp,irtc"; 844 reg = <0x4c000 0x1000>; 845 status = "disabled"; 846 interrupts = <52 0>; 847 prescaler = <1>; 848 clock-frequency = <16384>; 849 clock-src = <0>; 850 alarms-count = <1>; 851 }; 852}; 853 854&systick { 855 /* 856 * MCXN23X relies by default on the OS Timer for system clock 857 * implementation, so the SysTick node is not to be enabled. 858 */ 859 status = "disabled"; 860}; 861 862&nvic { 863 arm,num-irq-priority-bits = <3>; 864}; 865
