1/*
2 * Copyright 2017,2023 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <arm/armv7-m.dtsi>
9#include <zephyr/dt-bindings/adc/adc.h>
10#include <zephyr/dt-bindings/clock/imx_ccm.h>
11#include <zephyr/dt-bindings/gpio/gpio.h>
12#include <zephyr/dt-bindings/i2c/i2c.h>
13#include <zephyr/dt-bindings/pwm/pwm.h>
14#include <zephyr/dt-bindings/memory-controller/nxp,flexram.h>
15
16/ {
17	aliases {
18		die-temp0 = &tempmon;
19	};
20
21	chosen {
22		zephyr,entropy = &trng;
23	};
24
25	cpus {
26		#address-cells = <1>;
27		#size-cells = <0>;
28
29		cpu0: cpu@0 {
30			device_type = "cpu";
31			compatible = "arm,cortex-m7";
32			d-cache-line-size = <32>;
33			reg = <0>;
34			cpu-power-states = <&idle &suspend>;
35			#address-cells = <1>;
36			#size-cells = <1>;
37
38			mpu: mpu@e000ed90 {
39				compatible = "arm,armv7m-mpu";
40				reg = <0xe000ed90 0x40>;
41			};
42
43			itm: itm@e0000000 {
44				compatible = "arm,armv7m-itm";
45				reg = <0xe0000000 0x1000>;
46				swo-ref-frequency = <132000000>;
47			};
48		};
49
50		power-states {
51			idle: idle {
52				compatible = "zephyr,power-state";
53				power-state-name = "runtime-idle";
54				exit-latency-us = <4000>;
55				min-residency-us = <5000>;
56			};
57			suspend: suspend {
58				compatible = "zephyr,power-state";
59				power-state-name = "suspend-to-idle";
60				exit-latency-us = <5000>;
61				min-residency-us = <10000>;
62			};
63		};
64	};
65
66	sysclk: system-clock {
67		compatible = "fixed-clock";
68		clock-frequency = <600000000>;
69		#clock-cells = <0>;
70	};
71
72	xtal: clock-xtal {
73		compatible = "fixed-clock";
74		clock-frequency = <24000000>;
75		#clock-cells = <0>;
76	};
77
78	rtc_xtal: clock-rtc-xtal {
79		compatible = "fixed-clock";
80		clock-frequency = <32768>;
81		#clock-cells = <0>;
82	};
83
84	/* USB PLL (selected to be FLEXSPI clock source) will be left unchanged */
85	usbclk: usbpll-clock {
86		compatible = "fixed-clock";
87		clock-frequency = <480000000>;
88		#clock-cells = <0>;
89	};
90
91	soc {
92		flexram: flexram@400b0000 {
93			compatible = "nxp,flexram";
94			reg = <0x400b0000 0x4000>;
95			interrupts = <38 0>;
96
97			#address-cells = <1>;
98			#size-cells = <1>;
99
100			status = "okay";
101
102			flexram,bank-size = <32>;
103
104			itcm: itcm@0 {
105				compatible = "zephyr,memory-region", "nxp,imx-itcm";
106				reg = <0x00000000 DT_SIZE_K(128)>;
107				zephyr,memory-region = "ITCM";
108			};
109
110			dtcm: dtcm@20000000 {
111				compatible = "zephyr,memory-region", "nxp,imx-dtcm";
112				reg = <0x20000000 DT_SIZE_K(128)>;
113				zephyr,memory-region = "DTCM";
114			};
115
116			ocram: ocram@20200000 {
117				compatible = "zephyr,memory-region", "mmio-sram";
118				reg = <0x20200000 DT_SIZE_K(256)>;
119				zephyr,memory-region = "OCRAM";
120			};
121		};
122
123		flexspi: spi@402a8000 {
124			compatible = "nxp,imx-flexspi";
125			reg = <0x402a8000 0x4000>;
126			interrupts = <108 0>;
127			#address-cells = <1>;
128			#size-cells = <0>;
129			ahb-bufferable;
130			ahb-cacheable;
131			status = "disabled";
132			clocks = <&ccm IMX_CCM_FLEXSPI_CLK 0x0 0x0>;
133		};
134
135		flexspi2: spi@402a4000 {
136			compatible = "nxp,imx-flexspi";
137			reg = <0x402a4000 0x4000>;
138			interrupts = <107 0>;
139			#address-cells = <1>;
140			#size-cells = <0>;
141			ahb-bufferable;
142			ahb-cacheable;
143			status = "disabled";
144			clocks = <&ccm IMX_CCM_FLEXSPI2_CLK 0x0 0x0>;
145		};
146
147		semc: semc0@402f0000 {
148			compatible = "nxp,imx-semc";
149			reg = <0x402f0000 0x4000>;
150			interrupts = <109 0>;
151			#address-cells = <1>;
152			#size-cells = <1>;
153		};
154
155		/* GPT1 is used for the hardware timer, not as a standard counter */
156		gpt_hw_timer: gpt@401ec000 {
157			compatible = "nxp,gpt-hw-timer";
158			reg = <0x401ec000 0x4000>;
159			interrupts = <100 0>;
160			status = "disabled";
161		};
162
163		gpt2: gpt@401f0000 {
164			compatible = "nxp,imx-gpt";
165			reg = <0x401f0000 0x4000>;
166			interrupts = <101 0>;
167			gptfreq = <25000000>;
168			clocks = <&ccm IMX_CCM_GPT_CLK 0x68 24>;
169		};
170
171		qtmr1: qtmr@401dc000 {
172			compatible = "nxp,imx-qtmr";
173			reg = <0x401dc000 0x7a>;
174			interrupts = <133 0>;
175			clocks = <&ccm IMX_CCM_QTMR_CLK 0 0>;
176			qtmr1_timer0: timer0 {
177				compatible = "nxp,imx-tmr";
178				channel = <0>;
179				status = "disabled";
180			};
181			qtmr1_timer1: timer1 {
182				compatible = "nxp,imx-tmr";
183				channel = <1>;
184				status = "disabled";
185			};
186			qtmr1_timer2: timer2 {
187				compatible = "nxp,imx-tmr";
188				channel = <2>;
189				status = "disabled";
190			};
191			qtmr1_timer3: timer3 {
192				compatible = "nxp,imx-tmr";
193				channel = <3>;
194				status = "disabled";
195			};
196		};
197
198		qtmr2: qtmr@401e0000 {
199			compatible = "nxp,imx-qtmr";
200			reg = <0x401e0000 0x7a>;
201			interrupts = <134 0>;
202			clocks = <&ccm IMX_CCM_QTMR_CLK 0 0>;
203			qtmr2_timer0: timer0 {
204				compatible = "nxp,imx-tmr";
205				channel = <0>;
206				status = "disabled";
207			};
208			qtmr2_timer1: timer1 {
209				compatible = "nxp,imx-tmr";
210				channel = <1>;
211				status = "disabled";
212			};
213			qtmr2_timer2: timer2 {
214				compatible = "nxp,imx-tmr";
215				channel = <2>;
216				status = "disabled";
217			};
218			qtmr2_timer3: timer3 {
219				compatible = "nxp,imx-tmr";
220				channel = <3>;
221				status = "disabled";
222			};
223		};
224
225		qtmr3: qtmr@401e4000 {
226			compatible = "nxp,imx-qtmr";
227			reg = <0x401e4000 0x7a>;
228			interrupts = <135 0>;
229			clocks = <&ccm IMX_CCM_QTMR_CLK 0 0>;
230			qtmr3_timer0: timer0 {
231				compatible = "nxp,imx-tmr";
232				channel = <0>;
233				status = "disabled";
234			};
235			qtmr3_timer1: timer1 {
236				compatible = "nxp,imx-tmr";
237				channel = <1>;
238				status = "disabled";
239			};
240			qtmr3_timer2: timer2 {
241				compatible = "nxp,imx-tmr";
242				channel = <2>;
243				status = "disabled";
244			};
245			qtmr3_timer3: timer3 {
246				compatible = "nxp,imx-tmr";
247				channel = <3>;
248				status = "disabled";
249			};
250		};
251
252		qtmr4: qtmr@401e8000 {
253			compatible = "nxp,imx-qtmr";
254			reg = <0x401e8000 0x7a>;
255			interrupts = <136 0>;
256			clocks = <&ccm IMX_CCM_QTMR_CLK 0 0>;
257			qtmr4_timer0: timer0 {
258				compatible = "nxp,imx-tmr";
259				channel = <0>;
260				status = "disabled";
261			};
262			qtmr4_timer1: timer1 {
263				compatible = "nxp,imx-tmr";
264				channel = <1>;
265				status = "disabled";
266			};
267			qtmr4_timer2: timer2 {
268				compatible = "nxp,imx-tmr";
269				channel = <2>;
270				status = "disabled";
271			};
272			qtmr4_timer3: timer3 {
273				compatible = "nxp,imx-tmr";
274				channel = <3>;
275				status = "disabled";
276			};
277		};
278
279		ccm: ccm@400fc000 {
280			compatible = "nxp,imx-ccm";
281			reg = <0x400fc000 0x4000>;
282			clocks = <&xtal>, <&rtc_xtal>;
283			clock-names = "xtal", "rtc-xtal";
284
285			arm-podf {
286				compatible = "fixed-factor-clock";
287				clock-div = <1>;
288				#clock-cells = <0>;
289			};
290
291			ahb-podf {
292				compatible = "fixed-factor-clock";
293				clock-div = <1>;
294				#clock-cells = <0>;
295			};
296
297			ipg-podf {
298				compatible = "fixed-factor-clock";
299				clock-div = <1>;
300				#clock-cells = <0>;
301			};
302
303			sys-pll {
304				compatible = "nxp,imx-ccm-fnpll";
305				loop-div = <22>;
306				numerator = <0>;
307				denominator = <1>;
308				src = <0>;
309				#clock-cells = <0>;
310			};
311
312			#clock-cells = <3>;
313		};
314
315		snvs: snvs@400d4000 {
316			compatible = "nxp,imx-snvs";
317			reg = <0x400d4000 0x4000>;
318
319			snvs_rtc: rtc {
320				compatible = "nxp,imx-snvs-rtc";
321				interrupts = <46 0>;
322			};
323		};
324
325		gpio1: gpio@401b8000 {
326			compatible = "nxp,imx-gpio";
327			reg = <0x401b8000 0x4000>;
328			interrupts = <80 0>, <81 0>;
329			gpio-controller;
330			#gpio-cells = <2>;
331		};
332
333		gpio2: gpio@401bc000 {
334			compatible = "nxp,imx-gpio";
335			reg = <0x401bc000 0x4000>;
336			interrupts = <82 0>, <83 0>;
337			gpio-controller;
338			#gpio-cells = <2>;
339		};
340
341		gpio3: gpio@401c0000 {
342			compatible = "nxp,imx-gpio";
343			reg = <0x401c0000 0x4000>;
344			interrupts = <84 0>, <85 0>;
345			gpio-controller;
346			#gpio-cells = <2>;
347		};
348
349		gpio4: gpio@401c4000 {
350			compatible = "nxp,imx-gpio";
351			reg = <0x401c4000 0x4000>;
352			interrupts = <86 0>, <87 0>;
353			gpio-controller;
354			#gpio-cells = <2>;
355		};
356
357		gpio5: gpio@400c0000 {
358			compatible = "nxp,imx-gpio";
359			reg = <0x400c0000 0x4000>;
360			interrupts = <88 0>, <89 0>;
361			gpio-controller;
362			#gpio-cells = <2>;
363		};
364		/*
365		 * Note: interrupts for GPIO6-9 are not currently supported
366		 * by the gpio driver.
367		 */
368		gpio6: gpio@42000000 {
369			compatible = "nxp,imx-gpio";
370			reg = <0x42000000 0x4000>;
371			gpio-controller;
372			#gpio-cells = <2>;
373		};
374
375		gpio7: gpio@42004000 {
376			compatible = "nxp,imx-gpio";
377			reg = <0x42004000 0x4000>;
378			gpio-controller;
379			#gpio-cells = <2>;
380		};
381
382		gpio8: gpio@42008000 {
383			compatible = "nxp,imx-gpio";
384			reg = <0x42008000 0x4000>;
385			gpio-controller;
386			#gpio-cells = <2>;
387		};
388
389		gpio9: gpio@4200c000 {
390			compatible = "nxp,imx-gpio";
391			reg = <0x4200c000 0x4000>;
392			gpio-controller;
393			#gpio-cells = <2>;
394		};
395
396		lpi2c1: i2c@403f0000 {
397			compatible = "nxp,lpi2c";
398			clock-frequency = <I2C_BITRATE_STANDARD>;
399			#address-cells = <1>;
400			#size-cells = <0>;
401			reg = <0x403f0000 0x4000>;
402			interrupts = <28 0>;
403			clocks = <&ccm IMX_CCM_LPI2C_CLK 0x70 6>;
404			status = "disabled";
405		};
406
407		lpi2c2: i2c@403f4000 {
408			compatible = "nxp,lpi2c";
409			clock-frequency = <I2C_BITRATE_STANDARD>;
410			#address-cells = <1>;
411			#size-cells = <0>;
412			reg = <0x403f4000 0x4000>;
413			interrupts = <29 0>;
414			clocks = <&ccm IMX_CCM_LPI2C_CLK 0x70 8>;
415			status = "disabled";
416		};
417
418		lpi2c3: i2c@403f8000 {
419			compatible = "nxp,lpi2c";
420			clock-frequency = <I2C_BITRATE_STANDARD>;
421			#address-cells = <1>;
422			#size-cells = <0>;
423			reg = <0x403f8000 0x4000>;
424			interrupts = <30 0>;
425			clocks = <&ccm IMX_CCM_LPI2C_CLK 0x70 10>;
426			status = "disabled";
427		};
428
429		lpi2c4: i2c@403fc000 {
430			compatible = "nxp,lpi2c";
431			clock-frequency = <I2C_BITRATE_STANDARD>;
432			#address-cells = <1>;
433			#size-cells = <0>;
434			reg = <0x403fc000 0x4000>;
435			interrupts = <31 0>;
436			clocks = <&ccm IMX_CCM_LPI2C_CLK 0x80 24>;
437			status = "disabled";
438		};
439
440		iomuxc: iomuxc@401f8000 {
441			compatible = "nxp,imx-iomuxc";
442			reg = <0x401f8000 0x4000>;
443			status = "okay";
444			pinctrl: pinctrl {
445				status = "okay";
446				compatible = "nxp,mcux-rt-pinctrl";
447			};
448		};
449
450		lcdif: display-controller@402b8000 {
451			compatible = "nxp,imx-elcdif";
452			reg = <0x402b8000 0x4000>;
453			interrupts = <42 0>;
454			status = "disabled";
455			nxp,pxp = <&pxp>;
456		};
457
458		lpspi1: spi@40394000 {
459			compatible = "nxp,lpspi";
460			reg = <0x40394000 0x4000>;
461			interrupts = <32 3>;
462			status = "disabled";
463			clocks = <&ccm IMX_CCM_LPSPI_CLK 0x6c 0>;
464			rx-fifo-size = <16>;
465			tx-fifo-size = <16>;
466			#address-cells = <1>;
467			#size-cells = <0>;
468		};
469
470		lpspi2: spi@40398000 {
471			compatible = "nxp,lpspi";
472			reg = <0x40398000 0x4000>;
473			interrupts = <33 3>;
474			status = "disabled";
475			clocks = <&ccm IMX_CCM_LPSPI_CLK 0x6c 2>;
476			rx-fifo-size = <16>;
477			tx-fifo-size = <16>;
478			#address-cells = <1>;
479			#size-cells = <0>;
480		};
481
482		lpspi3: spi@4039c000 {
483			compatible = "nxp,lpspi";
484			reg = <0x4039c000 0x4000>;
485			interrupts = <34 3>;
486			status = "disabled";
487			clocks = <&ccm IMX_CCM_LPSPI_CLK 0x6c 4>;
488			rx-fifo-size = <16>;
489			tx-fifo-size = <16>;
490			#address-cells = <1>;
491			#size-cells = <0>;
492		};
493
494		lpspi4: spi@403a0000 {
495			compatible = "nxp,lpspi";
496			reg = <0x403a0000 0x4000>;
497			interrupts = <35 3>;
498			status = "disabled";
499			clocks = <&ccm IMX_CCM_LPSPI_CLK 0x6c 6>;
500			rx-fifo-size = <16>;
501			tx-fifo-size = <16>;
502			#address-cells = <1>;
503			#size-cells = <0>;
504		};
505
506		lpuart1: uart@40184000 {
507			compatible = "nxp,lpuart";
508			reg = <0x40184000 0x4000>;
509			interrupts = <20 0>;
510			clocks = <&ccm IMX_CCM_LPUART_CLK 0x7c 24>;
511			dmas = <&edma0 1 2>, <&edma0 2 3>;
512			dma-names = "tx", "rx";
513			status = "disabled";
514		};
515
516		lpuart2: uart@40188000 {
517			compatible = "nxp,lpuart";
518			reg = <0x40188000 0x4000>;
519			interrupts = <21 0>;
520			clocks = <&ccm IMX_CCM_LPUART_CLK 0x68 28>;
521			dmas = <&edma0 3 66>, <&edma0 4 67>;
522			dma-names = "tx", "rx";
523			status = "disabled";
524		};
525
526		lpuart3: uart@4018c000 {
527			compatible = "nxp,lpuart";
528			reg = <0x4018c000 0x4000>;
529			interrupts = <22 0>;
530			clocks = <&ccm IMX_CCM_LPUART_CLK 0x68 12>;
531			dmas = <&edma0 5 4>, <&edma0 6 5>;
532			dma-names = "tx", "rx";
533			status = "disabled";
534		};
535
536		lpuart4: uart@40190000 {
537			compatible = "nxp,lpuart";
538			reg = <0x40190000 0x4000>;
539			interrupts = <23 0>;
540			clocks = <&ccm IMX_CCM_LPUART_CLK 0x6c 24>;
541			dmas = <&edma0 7 68>, <&edma0 8 69>;
542			dma-names = "tx", "rx";
543			status = "disabled";
544		};
545
546		lpuart5: uart@40194000 {
547			compatible = "nxp,lpuart";
548			reg = <0x40194000 0x4000>;
549			interrupts = <24 0>;
550			clocks = <&ccm IMX_CCM_LPUART_CLK 0x74 2>;
551			dmas = <&edma0 9 6>, <&edma0 10 7>;
552			dma-names = "tx", "rx";
553			status = "disabled";
554		};
555
556		lpuart6: uart@40198000 {
557			compatible = "nxp,lpuart";
558			reg = <0x40198000 0x4000>;
559			interrupts = <25 0>;
560			clocks = <&ccm IMX_CCM_LPUART_CLK 0x74 6>;
561			dmas = <&edma0 11 70>, <&edma0 12 71>;
562			dma-names = "tx", "rx";
563			status = "disabled";
564		};
565
566		lpuart7: uart@4019c000 {
567			compatible = "nxp,lpuart";
568			reg = <0x4019c000 0x4000>;
569			interrupts = <26 0>;
570			clocks = <&ccm IMX_CCM_LPUART_CLK 0x7c 26>;
571			dmas = <&edma0 13 8>, <&edma0 14 9>;
572			dma-names = "tx", "rx";
573			status = "disabled";
574		};
575
576		lpuart8: uart@401a0000 {
577			compatible = "nxp,lpuart";
578			reg = <0x401a0000 0x4000>;
579			interrupts = <27 0>;
580			clocks = <&ccm IMX_CCM_LPUART_CLK 0x80 14>;
581			dmas = <&edma0 15 72>, <&edma0 16 73>;
582			dma-names = "tx", "rx";
583			status = "disabled";
584		};
585
586		adc1: adc@400c4000 {
587			compatible = "nxp,mcux-12b1msps-sar";
588			reg = <0x400C4000 0x1000>;
589			interrupts = <67 0>;
590			clk-divider = <1>;
591			sample-period-mode = <0>;
592			status = "disabled";
593			#io-channel-cells = <1>;
594		};
595
596		adc2: adc@400c8000 {
597			compatible = "nxp,mcux-12b1msps-sar";
598			reg = <0x400C8000 0x1000>;
599			interrupts = <68 0>;
600			clk-divider = <1>;
601			sample-period-mode = <0>;
602			status = "disabled";
603			#io-channel-cells = <1>;
604		};
605
606		flexpwm1: flexpwm@403dc000 {
607			compatible = "nxp,flexpwm";
608			reg = <0x403dc000 0x4000>;
609			interrupts = <106 0>;
610
611			flexpwm1_pwm0: flexpwm1_pwm0 {
612				compatible = "nxp,imx-pwm";
613				index = <0>;
614				interrupts = <102 0>;
615				#pwm-cells = <3>;
616				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
617				nxp,prescaler = <128>;
618				status = "disabled";
619			};
620
621			flexpwm1_pwm1: flexpwm1_pwm1 {
622				compatible = "nxp,imx-pwm";
623				index = <1>;
624				interrupts = <103 0>;
625				#pwm-cells = <3>;
626				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
627				nxp,prescaler = <128>;
628				status = "disabled";
629			};
630
631			flexpwm1_pwm2: flexpwm1_pwm2 {
632				compatible = "nxp,imx-pwm";
633				index = <2>;
634				interrupts = <104 0>;
635				#pwm-cells = <3>;
636				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
637				nxp,prescaler = <128>;
638				status = "disabled";
639			};
640
641			flexpwm1_pwm3: flexpwm1_pwm3 {
642				compatible = "nxp,imx-pwm";
643				index = <3>;
644				interrupts = <105 0>;
645				#pwm-cells = <3>;
646				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
647				nxp,prescaler = <128>;
648				status = "disabled";
649			};
650		};
651
652		flexpwm2: flexpwm@403e0000 {
653			compatible = "nxp,flexpwm";
654			reg = <0x403e0000 0x4000>;
655			interrupts =  <141 0>;
656
657			flexpwm2_pwm0: flexpwm2_pwm0 {
658				compatible = "nxp,imx-pwm";
659				index = <0>;
660				interrupts = <137 0>;
661				#pwm-cells = <3>;
662				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
663				nxp,prescaler = <128>;
664				status = "disabled";
665			};
666
667			flexpwm2_pwm1: flexpwm2_pwm1 {
668				compatible = "nxp,imx-pwm";
669				index = <1>;
670				interrupts = <138 0>;
671				#pwm-cells = <3>;
672				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
673				nxp,prescaler = <128>;
674				status = "disabled";
675			};
676
677			flexpwm2_pwm2: flexpwm2_pwm2 {
678				compatible = "nxp,imx-pwm";
679				index = <2>;
680				interrupts = <139 0>;
681				#pwm-cells = <3>;
682				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
683				nxp,prescaler = <128>;
684				status = "disabled";
685			};
686
687			flexpwm2_pwm3: flexpwm2_pwm3 {
688				compatible = "nxp,imx-pwm";
689				index = <3>;
690				interrupts = <140 0>;
691				#pwm-cells = <3>;
692				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
693				nxp,prescaler = <128>;
694				status = "disabled";
695			};
696		};
697
698		flexpwm3: flexpwm@403e4000 {
699			compatible = "nxp,flexpwm";
700			reg = <0x403e4000 0x4000>;
701			interrupts =  <146 0>;
702
703			flexpwm3_pwm0: flexpwm3_pwm0 {
704				compatible = "nxp,imx-pwm";
705				index = <0>;
706				interrupts = <142 0>;
707				#pwm-cells = <3>;
708				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
709				nxp,prescaler = <128>;
710				status = "disabled";
711			};
712
713			flexpwm3_pwm1: flexpwm3_pwm1 {
714				compatible = "nxp,imx-pwm";
715				index = <1>;
716				interrupts = <143 0>;
717				#pwm-cells = <3>;
718				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
719				nxp,prescaler = <128>;
720				status = "disabled";
721			};
722
723			flexpwm3_pwm2: flexpwm3_pwm2 {
724				compatible = "nxp,imx-pwm";
725				index = <2>;
726				interrupts = <144 0>;
727				#pwm-cells = <3>;
728				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
729				nxp,prescaler = <128>;
730				status = "disabled";
731			};
732
733			flexpwm3_pwm3: flexpwm3_pwm3 {
734				compatible = "nxp,imx-pwm";
735				index = <3>;
736				interrupts = <145 0>;
737				#pwm-cells = <3>;
738				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
739				nxp,prescaler = <128>;
740				status = "disabled";
741			};
742		};
743
744		flexpwm4: flexpwm@403e8000 {
745			compatible = "nxp,flexpwm";
746			reg = <0x403e8000 0x4000>;
747			interrupts = <151 0>;
748
749			flexpwm4_pwm0: flexpwm4_pwm0 {
750				compatible = "nxp,imx-pwm";
751				index = <0>;
752				interrupts = <147 0>;
753				#pwm-cells = <3>;
754				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
755				nxp,prescaler = <128>;
756				status = "disabled";
757			};
758
759			flexpwm4_pwm1: flexpwm4_pwm1 {
760				compatible = "nxp,imx-pwm";
761				index = <1>;
762				interrupts = <148 0>;
763				#pwm-cells = <3>;
764				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
765				nxp,prescaler = <128>;
766				status = "disabled";
767			};
768
769			flexpwm4_pwm2: flexpwm4_pwm2 {
770				compatible = "nxp,imx-pwm";
771				index = <2>;
772				interrupts = <149 0>;
773				#pwm-cells = <3>;
774				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
775				nxp,prescaler = <128>;
776				status = "disabled";
777			};
778
779			flexpwm4_pwm3: flexpwm4_pwm3 {
780				compatible = "nxp,imx-pwm";
781				index = <3>;
782				interrupts = <150 0>;
783				#pwm-cells = <3>;
784				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
785				nxp,prescaler = <128>;
786				status = "disabled";
787			};
788		};
789
790		enet: enet@402d8000 {
791			compatible = "nxp,enet";
792			reg = <0x402D8000 0x628>;
793			clocks = <&ccm IMX_CCM_ENET_CLK 0 0>;
794			enet_mac: ethernet {
795				compatible = "nxp,enet-mac";
796				interrupts = <114 0>;
797				interrupt-names = "COMMON";
798				nxp,mdio = <&enet_mdio>;
799				nxp,ptp-clock = <&enet_ptp_clock>;
800				status = "disabled";
801			};
802			enet_mdio: mdio {
803				compatible = "nxp,enet-mdio";
804				status = "disabled";
805				#address-cells = <1>;
806				#size-cells = <0>;
807			};
808			enet_ptp_clock: ptp_clock {
809				compatible = "nxp,enet-ptp-clock";
810				interrupts = <115 0>;
811				status = "disabled";
812				clocks = <&ccm IMX_CCM_ENET_PLL 0 0>;
813			};
814		};
815
816		src: reset-controller@400f8000 {
817			compatible = "nxp,imx-src";
818			reg = <0x400f8000 0x4000>;
819			status = "okay";
820		};
821
822		trng: random@400cc000 {
823			compatible = "nxp,kinetis-trng";
824			reg = <0x400cc000 0x4000>;
825			status = "okay";
826			interrupts = <53 0>;
827		};
828
829		usb1: usbd@402e0000 {
830			compatible = "nxp,ehci";
831			reg = <0x402E0000 0x200>;
832			interrupts = <113 1>;
833			interrupt-names = "usb_otg";
834			clocks = <&usbclk>;
835			num-bidir-endpoints = <8>;
836			status = "disabled";
837		};
838
839		usb2: usbd@402e0200 {
840			compatible = "nxp,ehci";
841			reg = <0x402E0200 0x200>;
842			interrupts = <112 1>;
843			interrupt-names = "usb_otg";
844			clocks = <&usbclk>;
845			num-bidir-endpoints = <8>;
846			status = "disabled";
847		};
848
849		usbphy1: usbphy@400d9000 {
850			compatible = "nxp,usbphy";
851			reg = <0x400D9000 0x1000>;
852			status = "disabled";
853		};
854
855		usbphy2: usbphy@400da000 {
856			compatible = "nxp,usbphy";
857			reg = <0x400DA000 0x1000>;
858			status = "disabled";
859		};
860
861		usdhc1: usdhc@402c0000 {
862			compatible = "nxp,imx-usdhc";
863			reg = <0x402c0000 0x4000>;
864			status = "disabled";
865			interrupts = <110 0>;
866			clocks = <&ccm IMX_CCM_USDHC1_CLK 0 0>;
867			max-current-330 = <1020>;
868			max-current-180 = <1020>;
869			max-bus-freq = <208000000>;
870			min-bus-freq = <400000>;
871		};
872
873		usdhc2: usdhc@402c4000 {
874			compatible = "nxp,imx-usdhc";
875			reg = <0x402c4000 0x4000>;
876			status = "disabled";
877			interrupts = <111 0>;
878			clocks = <&ccm IMX_CCM_USDHC2_CLK 0 0>;
879			max-current-330 = <120>;
880			max-current-180 = <45>;
881			max-bus-freq = <198000000>;
882			min-bus-freq = <400000>;
883		};
884
885		csi: csi@402bc000 {
886			compatible = "nxp,imx-csi";
887			reg = <0x402BC000 0x4000>;
888			interrupts = <43 1>;
889			status = "disabled";
890		};
891
892		edma0: dma-controller@400e8000 {
893			#dma-cells = <2>;
894			compatible = "nxp,mcux-edma";
895			nxp,version = <2>;
896			dma-channels = <32>;
897			dma-requests = <128>;
898			nxp,mem2mem;
899			nxp,a_on;
900			reg = <0x400E8000 0x4000>,
901				<0x400EC000 0x4000>;
902			interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
903				<4 0>, <5 0>, <6 0>, <7 0>,
904				<8 0>, <9 0>, <10 0>, <11 0>,
905				<12 0>, <13 0>, <14 0>, <15 0>;
906			irq-shared-offset = <16>;
907			clocks = <&ccm IMX_CCM_EDMA_CLK 0x7C 0x000000C0>;
908			status = "disabled";
909		};
910
911		flexcan1: can@401d0000 {
912			compatible = "nxp,flexcan";
913			reg = <0x401d0000 0x1000>;
914			interrupts = <36 0>;
915			interrupt-names = "common";
916			clocks = <&ccm IMX_CCM_CAN_CLK 0x68 14>;
917			clk-source = <2>;
918			status = "disabled";
919		};
920
921		flexcan2: can@401d4000 {
922			compatible = "nxp,flexcan";
923			reg = <0x401d4000 0x1000>;
924			interrupts = <37 0>;
925			interrupt-names = "common";
926			clocks = <&ccm IMX_CCM_CAN_CLK 0x68 18>;
927			clk-source = <2>;
928			status = "disabled";
929		};
930
931		flexcan3: can@401d8000 {
932			compatible = "nxp,flexcan-fd", "nxp,flexcan";
933			reg = <0x401d8000 0x1000>;
934			interrupts = <154 0>;
935			interrupt-names = "common";
936			clocks = <&ccm IMX_CCM_CAN_CLK 0x84 6>;
937			clk-source = <2>;
938			status = "disabled";
939		};
940
941		wdog0: wdog@400b8000 {
942			compatible = "nxp,imx-wdog";
943			reg = <0x400b8000 0xA>;
944			status = "disabled";
945			interrupts = <92 0>;
946		};
947
948		wdog1: wdog@400d0000 {
949			compatible = "nxp,imx-wdog";
950			reg = <0x400d0000 0xA>;
951			status = "disabled";
952			interrupts = <45 0>;
953		};
954
955		anatop: anatop@400d8000 {
956			compatible = "nxp,imx-anatop";
957			reg = <0x400d8000 0x4000>;
958			#clock-cells = <4>;
959			#pll-clock-cells = <3>;
960		};
961
962		iomuxcgpr: iomuxcgpr@400ac000 {
963			compatible = "nxp,imx-gpr";
964			reg = <0x400AC000 0x4000>;
965			#pinmux-cells = <2>;
966		};
967
968		pxp: pxp@402b4000 {
969			compatible = "nxp,pxp";
970			reg = <0x402b4000 0x4000>;
971			interrupts = <44 0>;
972			status = "disabled";
973			#dma-cells = <0>;
974		};
975
976		sai1: sai@40384000 {
977			compatible = "nxp,mcux-i2s";
978			#address-cells = <1>;
979			#size-cells = <0>;
980			#pinmux-cells = <2>;
981			reg = <0x40384000 0x4000>;
982			clocks = <&ccm IMX_CCM_SAI1_CLK 0x7C 18>;
983			/* Source clock from Audio PLL */
984			clock-mux = <2>;
985			/* Audio PLL Output Frequency is determined by:
986			 * (Fref * (DIV_SELECT + NUM/DENOM)) / POST_DIV
987			 * = (24MHz * (32 + 77 / 100)) / 1 = 786.48 MHz
988			 */
989			pll-clocks = <&anatop 0x70 0xC000 0>,
990				      <&anatop 0x70 0x7F 32>,
991				      <&anatop 0x70 0x180000 1>,
992				      <&anatop 0x80 0x3FFFFFFF 77>,
993				      <&anatop 0x90 0x3FFFFFFF 100>;
994			pll-clock-names = "src", "lp", "pd", "num", "den";
995			/* The maximum input frequency into the SAI mclk input is 300MHz
996			 * Based on this requirement, pre-div must be at least 3
997			 * The pre-div and post-div are one less than the actual divide-by amount.
998			 * A pre-div value of 0x1 results in a pre-divider of
999			 * (1+1) = 2
1000			 */
1001			pre-div = <0x3>;
1002			podf = <0x0F>;
1003			pinmuxes = <&iomuxcgpr 0x4 0x80000>;
1004			interrupts = <56 0>;
1005			dmas = <&edma0 0 19>, <&edma0 0 20>;
1006			dma-names = "rx", "tx";
1007			/* This translates to SAIChannelMask (fsl_sai.c) and
1008			 * cannot be 0
1009			 */
1010			nxp,tx-channel = <1>;
1011			nxp,tx-dma-channel = <0>;
1012			nxp,rx-dma-channel = <1>;
1013			status = "disabled";
1014		};
1015
1016		sai2: sai@40388000 {
1017			compatible = "nxp,mcux-i2s";
1018			#address-cells = <1>;
1019			#size-cells = <0>;
1020			#pinmux-cells = <2>;
1021			reg = <0x40388000 0x4000>;
1022			clocks = <&ccm IMX_CCM_SAI2_CLK 0x7C 20>;
1023			/* Source clock from Audio PLL */
1024			clock-mux = <2>;
1025			pre-div = <0>;
1026			podf = <63>;
1027			pll-clocks = <&anatop 0x70 0xC000 0x0>,
1028					<&anatop 0x70 0x7F 32>,
1029					<&anatop 0x70 0x180000 1>,
1030					<&anatop 0x80 0x3FFFFFFF 77>,
1031					<&anatop 0x90 0x3FFFFFFF 100>;
1032			pll-clock-names = "src", "lp", "pd", "num", "den";
1033			pinmuxes = <&iomuxcgpr 0x4 0x100000>;
1034			interrupts = <57 0>;
1035			dmas = <&edma0 0 21>, <&edma0 0 22>;
1036			dma-names = "rx", "tx";
1037			nxp,tx-channel = <0>;
1038			nxp,tx-dma-channel = <3>;
1039			nxp,rx-dma-channel = <4>;
1040			status = "disabled";
1041		};
1042
1043		sai3: sai@4038c000 {
1044			compatible = "nxp,mcux-i2s";
1045			#address-cells = <1>;
1046			#size-cells = <0>;
1047			#pinmux-cells = <2>;
1048			reg = <0x4038C000 0x4000>;
1049			clocks = <&ccm IMX_CCM_SAI3_CLK 0x7C 22>;
1050			/* Source clock from Audio PLL */
1051			clock-mux = <2>;
1052			pre-div = <0>;
1053			podf = <63>;
1054			pll-clocks = <&anatop 0x70 0xC000 0>,
1055				   <&anatop 0x70 0x7F 32>,
1056				   <&anatop 0x70 0x180000 1>,
1057				   <&anatop 0x80 0x3FFFFFFF 77>,
1058				   <&anatop 0x90 0x3FFFFFFF 100>;
1059			pll-clock-names = "src", "lp", "pd", "num", "den";
1060			pinmuxes = <&iomuxcgpr 0x4 0x200000>;
1061			interrupts = <58 0>, <59 0>;
1062			dmas = <&edma0 0 83>, <&edma0 0 84>;
1063			dma-names = "rx", "tx";
1064			nxp,tx-channel = <0>;
1065			nxp,tx-dma-channel = <5>;
1066			nxp,rx-dma-channel = <6>;
1067			status = "disabled";
1068		};
1069
1070		qdec1: qdec@403c8000 {
1071			compatible = "nxp,mcux-qdec";
1072			reg = <0x403c8000 0x4000>;
1073			interrupts = <129 0>;
1074			status = "disabled";
1075		};
1076
1077		qdec2: qdec@403cc000 {
1078			compatible = "nxp,mcux-qdec";
1079			reg = <0x403cc000 0x4000>;
1080			interrupts = <130 0>;
1081			status = "disabled";
1082		};
1083
1084		qdec3: qdec@403d0000 {
1085			compatible = "nxp,mcux-qdec";
1086			reg = <0x403d0000 0x4000>;
1087			interrupts = <131 0>;
1088			status = "disabled";
1089		};
1090
1091		qdec4: qdec@403d4000 {
1092			compatible = "nxp,mcux-qdec";
1093			reg = <0x403d4000 0x4000>;
1094			interrupts = <132 0>;
1095			status = "disabled";
1096		};
1097
1098		xbar1: xbar1@403bc000 {
1099			compatible = "nxp,mcux-xbar";
1100			reg = <0x403bc000 0x4000>;
1101			interrupts = <116 0>, <117 0>;
1102			status = "disabled";
1103		};
1104
1105		xbar2: xbar2@403c0000 {
1106			compatible = "nxp,mcux-xbar";
1107			reg = <0x403c0000 0x4000>;
1108			status = "disabled";
1109		};
1110
1111		xbar3: xbar3@403c4000 {
1112			compatible = "nxp,mcux-xbar";
1113			reg = <0x403c4000 0x4000>;
1114			status = "disabled";
1115		};
1116
1117		dcp: dcp@402fc000 {
1118			compatible = "nxp,mcux-dcp";
1119			reg = <0x402fc000 0x4000>;
1120			interrupts = <50 0>, <51 0>;
1121			status = "okay";
1122		};
1123
1124		tempmon: tempmon@400d8000 {
1125			compatible = "nxp,tempmon";
1126			reg = <0x400d8000 0x2a0>;
1127			status = "disabled";
1128		};
1129
1130		pit0: pit@40084000 {
1131			compatible = "nxp,pit";
1132			reg = <0x40084000 0x1000>;
1133			clocks = <&ccm IMX_CCM_PIT_CLK 0x0 0>;
1134			interrupts = <122 0>;
1135			max-load-value = <0xffffffff>;
1136			status = "disabled";
1137			#address-cells = <1>;
1138			#size-cells = <0>;
1139
1140			pit0_channel0: pit0_channel@0 {
1141				compatible = "nxp,pit-channel";
1142				reg = <0>;
1143				status = "disabled";
1144			};
1145
1146			pit0_channel1: pit0_channel@1 {
1147				compatible = "nxp,pit-channel";
1148				reg = <1>;
1149				status = "disabled";
1150			};
1151
1152			pit0_channel2: pit0_channel@2 {
1153				compatible = "nxp,pit-channel";
1154				reg = <2>;
1155				status = "disabled";
1156			};
1157
1158			pit0_channel3: pit0_channel@3 {
1159				compatible = "nxp,pit-channel";
1160				reg = <3>;
1161				status = "disabled";
1162			};
1163		};
1164
1165		flexio1: flexio@401ac000 {
1166			compatible = "nxp,flexio";
1167			reg = <0x401ac000 0x4000>;
1168			status = "disabled";
1169			interrupts = <90 0>;
1170			clocks = <&ccm IMX_CCM_FLEXIO1_CLK 0 0>;
1171		};
1172	};
1173};
1174
1175&nvic {
1176	arm,num-irq-priority-bits = <4>;
1177};
1178
1179&systick {
1180	/*
1181	 * RT10xx relies by default on the GPT Timer for system clock
1182	 * implementation, so the SysTick node should not be enabled.
1183	 */
1184	status = "disabled";
1185};
1186