1/*
2 * Copyright (c) 2019 Intel Corporation.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6#include <mem.h>
7#include <freq.h>
8#include <xtensa/xtensa.dtsi>
9#include <zephyr/dt-bindings/adc/adc.h>
10#include <zephyr/dt-bindings/gpio/gpio.h>
11#include <zephyr/dt-bindings/i2c/i2c.h>
12#include <zephyr/dt-bindings/clock/esp32_clock.h>
13#include <zephyr/dt-bindings/interrupt-controller/esp-xtensa-intmux.h>
14#include <dt-bindings/pinctrl/esp32-pinctrl.h>
15#include <zephyr/dt-bindings/pwm/pwm.h>
16
17/ {
18	chosen {
19		zephyr,canbus = &twai;
20		zephyr,entropy = &trng0;
21		zephyr,flash-controller = &flash;
22		zephyr,bt-hci = &esp32_bt_hci;
23	};
24
25	cpus {
26		#address-cells = <1>;
27		#size-cells = <0>;
28
29		cpu0: cpu@0 {
30			device_type = "cpu";
31			compatible = "espressif,xtensa-lx6";
32			reg = <0>;
33			cpu-power-states = <&light_sleep &deep_sleep>;
34			clock-source = <ESP32_CPU_CLK_SRC_PLL>;
35			clock-frequency = <DT_FREQ_M(240)>;
36			xtal-freq = <DT_FREQ_M(40)>;
37		};
38
39		cpu1: cpu@1 {
40			device_type = "cpu";
41			compatible = "espressif,xtensa-lx6";
42			reg = <1>;
43			clock-source = <ESP32_CPU_CLK_SRC_PLL>;
44			clock-frequency = <DT_FREQ_M(240)>;
45			xtal-freq = <DT_FREQ_M(40)>;
46		};
47
48		power-states {
49			light_sleep: light_sleep {
50				compatible = "zephyr,power-state";
51				power-state-name = "standby";
52				min-residency-us = <200>;
53				exit-latency-us = <60>;
54			};
55
56			deep_sleep: deep_sleep {
57				compatible = "zephyr,power-state";
58				power-state-name = "soft-off";
59				min-residency-us = <2000>;
60				exit-latency-us = <212>;
61			};
62		};
63	};
64
65	wifi: wifi {
66		compatible = "espressif,esp32-wifi";
67		status = "disabled";
68	};
69
70	esp32_bt_hci: esp32_bt_hci {
71		compatible = "espressif,esp32-bt-hci";
72		status = "disabled";
73	};
74
75	eth: eth {
76		compatible = "espressif,esp32-eth";
77		interrupts = <ETH_MAC_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
78		interrupt-parent = <&intc>;
79		clocks = <&rtc ESP32_EMAC_MODULE>;
80		status = "disabled";
81	};
82
83	mdio: mdio {
84		compatible = "espressif,esp32-mdio";
85		clocks = <&rtc ESP32_EMAC_MODULE>;
86		status = "disabled";
87		#address-cells = <1>;
88		#size-cells = <0>;
89	};
90
91	pinctrl: pin-controller {
92		compatible = "espressif,esp32-pinctrl";
93		status = "okay";
94	};
95
96	soc {
97		sram0: memory@40070000 {
98			compatible = "zephyr,memory-region", "mmio-sram";
99			reg = <0x40070000 DT_SIZE_K(192)>;
100			zephyr,memory-region = "SRAM0";
101		};
102
103		sram1: memory@3ffe0000 {
104			compatible = "zephyr,memory-region", "mmio-sram";
105			reg = <0x3ffe0000 DT_SIZE_K(128)>;
106			zephyr,memory-region = "SRAM1";
107		};
108
109		sram2: memory@3ffae000 {
110			compatible = "zephyr,memory-region", "mmio-sram";
111			reg = <0x3ffae000 DT_SIZE_K(200)>;
112			zephyr,memory-region = "SRAM2";
113		};
114
115		dcache0: dcache0@3f400000 {
116			compatible = "zephyr,memory-region", "mmio-sram";
117			reg = <0x3f400000 DT_SIZE_M(4)>;
118			zephyr,memory-region = "DCACHE0";
119		};
120
121		dcache1: dcache1@3f800000 {
122			compatible = "zephyr,memory-region", "mmio-sram";
123			reg = <0x3f800000 DT_SIZE_M(4)>;
124			zephyr,memory-region = "DCACHE1";
125
126			psram0: psram0 {
127				compatible = "espressif,esp32-psram";
128				size = <0x0>;
129			};
130		};
131
132		icache0: icache0@400d0000 {
133			compatible = "zephyr,memory-region", "mmio-sram";
134			reg = <0x400d0000 DT_SIZE_K(11456)>;
135			zephyr,memory-region = "ICACHE0";
136		};
137
138		ipmmem0: memory@3ffe5230 {
139			compatible = "mmio-sram";
140			reg = <0x3ffe5230 0x400>;
141		};
142
143		shm0: memory@3ffe5630 {
144			compatible = "mmio-sram";
145			reg = <0x3ffe5630 0x4000>;
146		};
147
148		ipm0: ipm@3ffe9630 {
149			compatible = "espressif,esp32-ipm";
150			reg = <0x3ffe9630 0x8>;
151			status = "disabled";
152			shared-memory = <&ipmmem0>;
153			shared-memory-size = <0x400>;
154			interrupts =
155				<FROM_CPU_INTR0_SOURCE IRQ_DEFAULT_PRIORITY 0>,
156				<FROM_CPU_INTR1_SOURCE IRQ_DEFAULT_PRIORITY 0>;
157			interrupt-parent = <&intc>;
158		};
159
160		mbox0: mbox@3ffe9638 {
161			compatible = "espressif,mbox-esp32";
162			reg = <0x3ffe9638 0x8>;
163			status = "disabled";
164			shared-memory = <&ipmmem0>;
165			shared-memory-size = <0x400>;
166			interrupts =
167				<FROM_CPU_INTR0_SOURCE IRQ_DEFAULT_PRIORITY 0>,
168				<FROM_CPU_INTR1_SOURCE IRQ_DEFAULT_PRIORITY 0>;
169			interrupt-parent = <&intc>;
170			#mbox-cells = <1>;
171		};
172
173		intc: interrupt-controller@3ff00104 {
174			#interrupt-cells = <3>;
175			#address-cells = <0>;
176			compatible = "espressif,esp32-intc";
177			interrupt-controller;
178			reg = <0x3ff00104 0x114>;
179			status = "okay";
180		};
181
182		rtc: rtc@3ff48000 {
183			compatible = "espressif,esp32-rtc";
184			reg = <0x3ff48000 0x0D8>;
185			fast-clk-src = <ESP32_RTC_FAST_CLK_SRC_RC_FAST>;
186			slow-clk-src = <ESP32_RTC_SLOW_CLK_SRC_RC_SLOW>;
187			#clock-cells = <1>;
188			status = "okay";
189
190		};
191
192		rtc_timer: rtc_timer@3ff48004 {
193			reg = <0x3ff48004 0xC>;
194			compatible = "espressif,esp32-rtc-timer";
195			clocks = <&rtc ESP32_MODULE_MAX>;
196			interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
197			interrupt-parent = <&intc>;
198			status = "okay";
199		};
200
201		flash: flash-controller@3ff42000 {
202			compatible = "espressif,esp32-flash-controller";
203			reg = <0x3ff42000 0x1000>;
204			#address-cells = <1>;
205			#size-cells = <1>;
206
207			flash0: flash@0 {
208				compatible = "soc-nv-flash";
209				erase-block-size = <4096>;
210				write-block-size = <4>;
211				/* Flash size is specified in SOC/SIP dtsi */
212			};
213		};
214
215		ipi0: ipi@3f4c0058 {
216			compatible = "espressif,crosscore-interrupt";
217			reg = <0x3f4c0058 0x4>;
218			interrupts = <FROM_CPU_INTR0_SOURCE IRQ_DEFAULT_PRIORITY 0>;
219			interrupt-parent = <&intc>;
220		};
221
222		ipi1: ipi@3f4c005c {
223			compatible = "espressif,crosscore-interrupt";
224			reg = <0x3f4c005c 0x4>;
225			interrupts = <FROM_CPU_INTR1_SOURCE IRQ_DEFAULT_PRIORITY 0>;
226			interrupt-parent = <&intc>;
227		};
228
229		uart0: uart@3ff40000 {
230			compatible = "espressif,esp32-uart";
231			reg = <0x3ff40000 0x400>;
232			interrupts = <UART0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
233			interrupt-parent = <&intc>;
234			clocks = <&rtc ESP32_UART0_MODULE>;
235			status = "disabled";
236		};
237
238		uart1: uart@3ff50000 {
239			compatible = "espressif,esp32-uart";
240			reg = <0x3ff50000 0x400>;
241			interrupts = <UART1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
242			interrupt-parent = <&intc>;
243			clocks = <&rtc ESP32_UART1_MODULE>;
244			status = "disabled";
245		};
246
247		uart2: uart@3ff6e000 {
248			compatible = "espressif,esp32-uart";
249			reg = <0x3ff6E000 0x400>;
250			interrupts = <UART2_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
251			interrupt-parent = <&intc>;
252			clocks = <&rtc ESP32_UART2_MODULE>;
253			status = "disabled";
254		};
255
256		pcnt: pcnt@3ff57000 {
257			compatible = "espressif,esp32-pcnt";
258			reg = <0x3ff57000 0x1000>;
259			interrupts = <PCNT_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
260			interrupt-parent = <&intc>;
261			clocks = <&rtc ESP32_PCNT_MODULE>;
262			status = "disabled";
263		};
264
265		ledc0: ledc@3ff59000 {
266			compatible = "espressif,esp32-ledc";
267			#pwm-cells = <3>;
268			reg = <0x3ff59000 0x800>;
269			clocks = <&rtc ESP32_LEDC_MODULE>;
270			status = "disabled";
271		};
272
273		mcpwm0: mcpwm@3ff5e000 {
274			compatible = "espressif,esp32-mcpwm";
275			reg = <0x3ff5e000 0x1000>;
276			interrupts = <PWM0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
277			interrupt-parent = <&intc>;
278			clocks = <&rtc ESP32_PWM0_MODULE>;
279			#pwm-cells = <3>;
280			status = "disabled";
281		};
282
283		mcpwm1: mcpwm@3ff6c000 {
284			compatible = "espressif,esp32-mcpwm";
285			reg = <0x3ff6c000 0x1000>;
286			interrupts = <PWM1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
287			interrupt-parent = <&intc>;
288			clocks = <&rtc ESP32_PWM1_MODULE>;
289			#pwm-cells = <3>;
290			status = "disabled";
291		};
292
293		gpio: gpio {
294			compatible = "simple-bus";
295			gpio-map-mask = <0xffffffe0 0xffffffc0>;
296			gpio-map-pass-thru = <0x1f 0x3f>;
297			gpio-map = <
298				0x00 0x0 &gpio0 0x0 0x0
299				0x20 0x0 &gpio1 0x0 0x0
300			>;
301			#gpio-cells = <2>;
302			#address-cells = <1>;
303			#size-cells = <1>;
304			ranges;
305
306			gpio0: gpio@3ff44000 {
307				compatible = "espressif,esp32-gpio";
308				gpio-controller;
309				#gpio-cells = <2>;
310				reg = <0x3ff44000 0x800>;
311				interrupts = <GPIO_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
312				interrupt-parent = <&intc>;
313				/* Maximum available pins (per port)
314				 * Actual occupied pins are specified
315				 * on part number dtsi level, using
316				 * the `gpio-reserved-ranges` property.
317				 */
318				ngpios = <32>;   /* 0..31 */
319			};
320
321			gpio1: gpio@3ff44800 {
322				compatible = "espressif,esp32-gpio";
323				gpio-controller;
324				#gpio-cells = <2>;
325				reg = <0x3ff44800 0x800>;
326				interrupts = <GPIO_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
327				interrupt-parent = <&intc>;
328				ngpios = <8>;   /* 32..39 */
329			};
330		};
331
332		touch: touch@3ff48858 {
333			compatible = "espressif,esp32-touch";
334			reg = <0x3ff48858 0x38>;
335			interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
336			interrupt-parent = <&intc>;
337			status = "disabled";
338		};
339
340		i2c0: i2c@3ff53000 {
341			compatible = "espressif,esp32-i2c";
342			#address-cells = <1>;
343			#size-cells = <0>;
344			reg = <0x3ff53000 0x1000>;
345			interrupts = <I2C_EXT0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
346			interrupt-parent = <&intc>;
347			clocks = <&rtc ESP32_I2C0_MODULE>;
348			status = "disabled";
349		};
350
351		i2c1: i2c@3ff67000 {
352			compatible = "espressif,esp32-i2c";
353			#address-cells = <1>;
354			#size-cells = <0>;
355			reg = <0x3ff67000 0x1000>;
356			interrupts = <I2C_EXT1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
357			interrupt-parent = <&intc>;
358			clocks = <&rtc ESP32_I2C1_MODULE>;
359			status = "disabled";
360		};
361
362		trng0: trng@3ff75144 {
363			compatible = "espressif,esp32-trng";
364			reg = <0x3FF75144 0x4>;
365			status = "disabled";
366		};
367
368		wdt0: watchdog@3ff5f048 {
369			compatible = "espressif,esp32-watchdog";
370			reg = <0x3ff5f048 0x20>;
371			interrupts = <TG0_WDT_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
372			interrupt-parent = <&intc>;
373			clocks = <&rtc ESP32_TIMG0_MODULE>;
374			status = "okay";
375		};
376
377		wdt1: watchdog@3ff60048 {
378			compatible = "espressif,esp32-watchdog";
379			reg = <0x3ff60048 0x20>;
380			interrupts = <TG1_WDT_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
381			interrupt-parent = <&intc>;
382			clocks = <&rtc ESP32_TIMG1_MODULE>;
383			status = "disabled";
384		};
385
386		spi2: spi@3ff64000 {
387			compatible = "espressif,esp32-spi";
388			reg = <0x3ff64000 DT_SIZE_K(4)>;
389			interrupts = <SPI2_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
390			interrupt-parent = <&intc>;
391			clocks = <&rtc ESP32_HSPI_MODULE>;
392			dma-clk = <ESP32_SPI_DMA_MODULE>;
393			dma-host = <0>;
394			status = "disabled";
395		};
396
397		spi3: spi@3ff65000 {
398			compatible = "espressif,esp32-spi";
399			reg = <0x3ff65000 DT_SIZE_K(4)>;
400			interrupts = <SPI3_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
401			interrupt-parent = <&intc>;
402			clocks = <&rtc ESP32_VSPI_MODULE>;
403			dma-clk = <ESP32_SPI_DMA_MODULE>;
404			dma-host = <1>;
405			status = "disabled";
406		};
407
408		twai: can@3ff6b000 {
409			compatible = "espressif,esp32-twai";
410			reg = <0x3ff6b000 DT_SIZE_K(4)>;
411			interrupts = <TWAI_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
412			interrupt-parent = <&intc>;
413			clocks = <&rtc ESP32_TWAI_MODULE>;
414			status = "disabled";
415		};
416
417		timer0: counter@3ff5f000 {
418			compatible = "espressif,esp32-timer";
419			reg = <0x3ff5f000 DT_SIZE_K(4)>;
420			clocks = <&rtc ESP32_TIMG0_MODULE>;
421			group = <0>;
422			index = <0>;
423			interrupts = <TG0_T0_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
424			interrupt-parent = <&intc>;
425			status = "disabled";
426		};
427
428		timer1: counter@3ff5f024 {
429			compatible = "espressif,esp32-timer";
430			reg = <0x3ff5f024 DT_SIZE_K(4)>;
431			clocks = <&rtc ESP32_TIMG0_MODULE>;
432			group = <0>;
433			index = <1>;
434			interrupts = <TG0_T1_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
435			interrupt-parent = <&intc>;
436			status = "disabled";
437		};
438
439		timer2: counter@3ff60000 {
440			compatible = "espressif,esp32-timer";
441			reg = <0x3ff60000 DT_SIZE_K(4)>;
442			clocks = <&rtc ESP32_TIMG1_MODULE>;
443			group = <1>;
444			index = <0>;
445			interrupts = <TG1_T0_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
446			interrupt-parent = <&intc>;
447			status = "disabled";
448		};
449
450		timer3: counter@3ff60024 {
451			compatible = "espressif,esp32-timer";
452			reg = <0x3ff60024 DT_SIZE_K(4)>;
453			clocks = <&rtc ESP32_TIMG1_MODULE>;
454			group = <1>;
455			index = <1>;
456			interrupts = <TG1_T1_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
457			interrupt-parent = <&intc>;
458			status = "disabled";
459		};
460
461		dac: dac@3ff48800 {
462			compatible = "espressif,esp32-dac";
463			reg = <0x3ff48800 0x100>;
464			interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
465			interrupt-parent = <&intc>;
466			clocks = <&rtc ESP32_SARADC_MODULE>;
467			#io-channel-cells = <1>;
468			status = "disabled";
469		};
470
471		adc0: adc@3ff48800 {
472			compatible = "espressif,esp32-adc";
473			reg = <0x3ff48800 10>;
474			clocks = <&rtc ESP32_SARADC_MODULE>;
475			unit = <1>;
476			channel-count = <8>;
477			#io-channel-cells = <1>;
478			status = "disabled";
479		};
480
481		adc1: adc@3ff48890 {
482			compatible = "espressif,esp32-adc";
483			reg = <0x3ff48890 10>;
484			clocks = <&rtc ESP32_SARADC_MODULE>;
485			unit = <2>;
486			channel-count = <10>;
487			#io-channel-cells = <1>;
488			status = "disabled";
489		};
490
491		sdhc: sdhc@3ff68000 {
492			compatible = "espressif,esp32-sdhc";
493			reg = <0x3ff68000 0x1000>;
494			interrupts = <SDIO_HOST_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
495			interrupt-parent = <&intc>;
496			clocks = <&rtc ESP32_SDMMC_MODULE>;
497			#address-cells = <1>;
498			#size-cells = <0>;
499
500			sdhc0: sdhc@0 {
501				compatible = "espressif,esp32-sdhc-slot";
502				reg = <0>;
503				status = "disabled";
504			};
505
506			sdhc1: sdhc@1 {
507				compatible = "espressif,esp32-sdhc-slot";
508				reg = <1>;
509				status = "disabled";
510			};
511		};
512	};
513};
514