1/*
2 * Copyright (c) 2021 Sateesh Kotapati
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/armv8-m.dtsi>
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/i2c/i2c.h>
10#include <dt-bindings/pinctrl/gecko-pinctrl.h>
11#include <dt-bindings/adc/adc.h>
12#include <freq.h>
13
14/ {
15	chosen {
16		zephyr,flash-controller = &msc;
17		zephyr,entropy = &trng;
18	};
19
20	clocks {
21		sysclk: sysclk {
22			#clock-cells = <0>;
23			compatible = "fixed-factor-clock";
24			clocks = <&hfrcodpll>;
25		};
26		hclk: hclk {
27			#clock-cells = <0>;
28			compatible = "fixed-factor-clock";
29			clocks = <&sysclk>;
30			/* Divisors 1, 2, 4, 8, 16 allowed */
31			clock-div = <1>;
32		};
33		pclk: pclk {
34			#clock-cells = <0>;
35			compatible = "fixed-factor-clock";
36			clocks = <&hclk>;
37			/* Divisors 1, 2 allowed */
38			clock-div = <2>;
39		};
40		lspclk: lspclk {
41			#clock-cells = <0>;
42			compatible = "fixed-factor-clock";
43			clocks = <&pclk>;
44			/* Fixed divisor of 2 */
45			clock-div = <2>;
46		};
47		hclkdiv1024: hclkdiv1024 {
48			#clock-cells = <0>;
49			compatible = "fixed-factor-clock";
50			clocks = <&hclk>;
51			/* Fixed divisor of 1024 */
52			clock-div = <1024>;
53		};
54		traceclk: traceclk {
55			#clock-cells = <0>;
56			compatible = "fixed-factor-clock";
57			clocks = <&sysclk>;
58			/* Divisors 1, 2, 3, 4 allowed */
59			clock-div = <1>;
60		};
61		em01grpaclk: em01grpaclk {
62			#clock-cells = <0>;
63			compatible = "fixed-factor-clock";
64			clocks = <&hfrcodpll>;
65		};
66		em01grpbclk: em01grpbclk {
67			#clock-cells = <0>;
68			compatible = "fixed-factor-clock";
69			clocks = <&hfrcodpll>;
70		};
71		iadcclk: iadcclk {
72			#clock-cells = <0>;
73			compatible = "fixed-factor-clock";
74			clocks = <&em01grpaclk>;
75		};
76		em23grpaclk: em23grpaclk {
77			#clock-cells = <0>;
78			compatible = "fixed-factor-clock";
79			clocks = <&lfrco>;
80		};
81		em4grpaclk: em4grpaclk {
82			#clock-cells = <0>;
83			compatible = "fixed-factor-clock";
84			clocks = <&lfrco>;
85		};
86		rtccclk: rtccclk {
87			#clock-cells = <0>;
88			compatible = "fixed-factor-clock";
89			clocks = <&lfrco>;
90		};
91		wdog0clk: wdog0clk {
92			#clock-cells = <0>;
93			compatible = "fixed-factor-clock";
94			clocks = <&lfrco>;
95		};
96		systickclk: systickclk {
97			#clock-cells = <0>;
98			compatible = "fixed-factor-clock";
99			clocks = <&hclk>;
100		};
101	};
102
103	cpus {
104		#address-cells = <1>;
105		#size-cells = <0>;
106		cpu0: cpu@0 {
107			device_type = "cpu";
108			compatible = "arm,cortex-m33";
109			reg = <0>;
110			/*
111			 * EM1 is enabled by default because it is
112			 * unconditionally safe.
113			 *
114			 * EM2/3 can be enabled by the board code if proper
115			 * timing configuration is ensured:
116			 * - for EM2, EM3: BURTC used as sys_clock
117			 * - for EM3: BURTC clocked from ULFRCO
118			 * Using BURTC as sys_clock instead of SysTick
119			 * has implications on system performance. Read
120			 * KConfig documentation entry before enabling it.
121			 *
122			 * The minimum residency and exit latency is
123			 * managed by sl_power_manager on S2 devices.
124			 */
125			cpu-power-states = <&pstate_em1 &pstate_em2 &pstate_em3>;
126		};
127
128		power-states {
129			/*
130			 * EM1 is a basic "CPU WFI idle", all high-freq clocks remain
131			 * enabled.
132			 */
133			pstate_em1: em1 {
134				compatible = "zephyr,power-state";
135				power-state-name = "runtime-idle";
136				/* HFXO remains active */
137			};
138
139			/*
140			 * EM2 is a deepsleep with HF clocks disabled by HW, voltages
141			 * scaled down, etc.
142			 */
143			pstate_em2: em2 {
144				compatible = "zephyr,power-state";
145				power-state-name = "suspend-to-idle";
146			};
147
148			/*
149			 * EM3 seems to be exactly the same as EM2 except that
150			 * LFXO & LFRCO should be disabled, so you must use ULFRCO
151			 * as BURTC clock for the system to not lose track of time and
152			 * wake up.
153			 */
154			pstate_em3: em3 {
155				compatible = "zephyr,power-state";
156				power-state-name = "standby";
157			};
158		};
159	};
160
161	sram0: memory@20000000 {
162		compatible = "mmio-sram";
163	};
164
165	soc {
166		cmu: clock@50008000 {
167			compatible = "silabs,series-clock";
168			reg = <0x50008000 0x4000>;
169			interrupt-names = "cmu";
170			status = "okay";
171			#clock-cells = <2>;
172		};
173
174		fsrco: fsrco@50018000 {
175			#clock-cells = <0>;
176			compatible = "fixed-clock";
177			reg = <0x50018000 0x4000>;
178			clock-frequency = <DT_FREQ_M(20)>;
179		};
180
181		clk_hfxo: hfxo: hfxo@5000c000 {
182			#clock-cells = <0>;
183			compatible = "silabs,hfxo";
184			reg = <0x5000c000 0x4000>;
185			clock-frequency = <DT_FREQ_K(38400)>;
186			ctune = <140>;
187			precision = <50>;
188			status = "disabled";
189		};
190
191		lfxo: lfxo@50020000 {
192			#clock-cells = <0>;
193			compatible = "silabs,series2-lfxo";
194			reg = <0x50020000 0x4000>;
195			clock-frequency = <32768>;
196			ctune = <63>;
197			precision = <50>;
198			timeout = <4096>;
199			status = "disabled";
200		};
201
202		hfrcodpll: hfrcodpll@50010000 {
203			#clock-cells = <0>;
204			compatible = "silabs,series2-hfrcodpll";
205			reg = <0x50010000 0x4000>;
206			clock-frequency = <DT_FREQ_M(19)>;
207		};
208
209		lfrco: lfrco@50024000 {
210			#clock-cells = <0>;
211			compatible = "silabs,series2-lfrco";
212			reg = <0x50024000 0x4000>;
213			clock-frequency = <32768>;
214		};
215
216		ulfrco: ulfrco@50028000 {
217			#clock-cells = <0>;
218			compatible = "fixed-clock";
219			reg = <0x50028000 0x4000>;
220			clock-frequency = <1000>;
221		};
222
223		msc: flash-controller@50030000 {
224			compatible = "silabs,series2-flash-controller";
225			reg = <0x50030000 0xC69>;
226			interrupts = <49 0>;
227
228			#address-cells = <1>;
229			#size-cells = <1>;
230		};
231
232		usart0: usart@5005c000 {
233			compatible = "silabs,usart-spi";
234			reg = <0x5005C000 0x400>;
235			interrupt-names = "rx", "tx";
236			#address-cells = <1>;
237			#size-cells = <0>;
238			status = "disabled";
239		};
240
241		usart1: usart@50060000 {
242			compatible = "silabs,usart-uart";
243			reg = <0x50060000 0x400>;
244			interrupt-names = "rx", "tx";
245			status = "disabled";
246		};
247
248		burtc0: burtc@50064000 {
249			compatible = "silabs,gecko-burtc";
250			reg = <0x50064000 0x3034>;
251			status = "disabled";
252		};
253
254		rtcc0: stimer0: rtcc@58000000 {
255			compatible = "silabs,gecko-stimer";
256			reg = <0x58000000 0x3054>;
257			clock-frequency = <32768>;
258			prescaler = <1>;
259			status = "disabled";
260		};
261
262		trng: trng@4c021000 {
263			compatible = "silabs,gecko-trng";
264			reg = <0x4C021000 0x1000>;
265			status = "disabled";
266			interrupts = <0x1 0x0>;
267		};
268
269		i2c0: i2c@5a010000 {
270			compatible = "silabs,gecko-i2c";
271			clock-frequency = <I2C_BITRATE_STANDARD>;
272			reg = <0x5a010000 0x3044>;
273			#address-cells = <1>;
274			#size-cells = <0>;
275			status = "disabled";
276		};
277
278		i2c1: i2c@50068000 {
279			compatible = "silabs,gecko-i2c";
280			clock-frequency = <I2C_BITRATE_STANDARD>;
281			reg = <0x50068000 0x3044>;
282			#address-cells = <1>;
283			#size-cells = <0>;
284			status = "disabled";
285		};
286
287		gpio: gpio@5003c000 {
288			compatible = "silabs,gecko-gpio";
289			reg = <0x5003C000 0x440>;
290			ranges;
291			#address-cells = <1>;
292			#size-cells = <1>;
293		};
294
295		pinctrl: pin-controller@5003c440 {
296			compatible = "silabs,dbus-pinctrl";
297			reg = <0x5003c440 0xbc0>, <0x5003c320 0x40>;
298			reg-names = "dbus", "abus";
299		};
300
301		dma0: dma@40040000{
302			compatible = "silabs,ldma";
303			reg = <0x40040000 0x4000>;
304			#dma-cells = <1>;
305			dma_channels = <8>;
306			status = "disabled";
307		};
308
309		wdog0: wdog@4a018000 {
310			compatible = "silabs,gecko-wdog";
311			reg = <0x4A018000 0x3028>;
312			peripheral-id = <0>;
313			interrupts = <43 0>;
314			status = "disabled";
315		};
316
317		adc0: adc@5a004000 {
318			compatible = "silabs,gecko-iadc";
319			reg = <0x5a004000 0x4000>;
320			interrupts = <48 0>;
321			status = "disabled";
322			#io-channel-cells = <1>;
323		};
324
325		dcdc: dcdc@50094000 {
326			compatible = "silabs,series2-dcdc";
327			reg = <0x50094000 0x4000>;
328			status = "disabled";
329		};
330
331		radio: radio@b0000000 {
332			compatible = "silabs,series2-radio";
333			reg = <0xb0000000 0x1000000>;
334			pa-initial-power-dbm = <10>;
335			pa-ramp-time-us = <2>;
336			pa-voltage-mv = <3300>;
337			pa-2p4ghz = "highest";
338
339			bt_hci_silabs: bt_hci_silabs {
340				compatible = "silabs,bt-hci-efr32";
341				status = "disabled";
342			};
343		};
344	};
345};
346
347&nvic {
348	arm,num-irq-priority-bits = <4>;
349};
350