1 /*******************************************************************************
2 * File Name: cyhal_clock_impl.h
3 *
4 * Description:
5 * CAT1 specific implementation for clocks API.
6 *
7 ********************************************************************************
8 * \copyright
9 * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
10 * an affiliate of Cypress Semiconductor Corporation
11 *
12 * SPDX-License-Identifier: Apache-2.0
13 *
14 * Licensed under the Apache License, Version 2.0 (the "License");
15 * you may not use this file except in compliance with the License.
16 * You may obtain a copy of the License at
17 *
18 * http://www.apache.org/licenses/LICENSE-2.0
19 *
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an "AS IS" BASIS,
22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
25 *******************************************************************************/
26
27 #pragma once
28
29 #include "cyhal_hw_resources.h"
30
31 #if (CYHAL_DRIVER_AVAILABLE_CLOCK)
32
33 #if defined(__cplusplus)
34 extern "C"
35 {
36 #endif
37
38 #if !defined(SRSS_NUM_PLL)
39
40 #if defined(COMPONENT_CAT1D)
41 #define SRSS_NUM_PLL SRSS_NUM_TOTAL_DPLL
42 #elif defined(COMPONENT_CAT1B)
43 #define SRSS_NUM_PLL (SRSS_NUM_PLL200M + SRSS_NUM_PLL400M)
44 #endif
45
46 #endif /* !defined(SRSS_NUM_PLL) */
47
48 #if defined(COMPONENT_CAT1C)
49 #define _CYHAL_SRSS_NUM_PLL (SRSS_NUM_PLL + SRSS_NUM_PLL400M)
50 #else
51 #define _CYHAL_SRSS_NUM_PLL SRSS_NUM_PLL
52 #endif /* defined(COMPONENT_CAT1C) or other */
53
54 #if defined(CY_SRSS_ILO_PRESENT)
55 #define _CYHAL_SRSS_ILO_PRESENT (CY_SRSS_ILO_PRESENT)
56 #elif ((CY_SRSS_ILO_COUNT) > 0) || defined(COMPONENT_CAT1A)
57 #define _CYHAL_SRSS_ILO_PRESENT (1)
58 #else
59 #define _CYHAL_SRSS_ILO_PRESENT (0)
60 #endif /* (CY_SRSS_ILO_PRESENT) */
61
62
63 /**
64 * \addtogroup group_hal_impl_clock Clocks
65 * \ingroup group_hal_impl
66 * \{
67 * Implementation specific interface for using the Clock driver. These items, while usable
68 * within the HAL, are <b>not</b> necessarily portable between devices. The diagrams below
69 * show how the clocks relate to each other. This is a superset of what is available. See
70 * the device specific Data Sheet for the exact set of clocks that are available on a
71 * specific device.
72 * \section section_clock_snippets_impl Code snippets
73 * \note Error handling code has been intentionally left out of snippets to highlight API usage.
74 *
75 * \subsection subsection_clock_snippet_5_impl Snippet: System initialization
76 * The following snippet shows the clock driver can be used to initialize all clocks in the system.
77 * \note This example is device specific.
78 * \snippet hal_clock.c snippet_cyhal_clock_system_init_p6
79 * \addtogroup group_hal_impl_clock_psoc6_01 PSoC™ 6S1 Clocks
80 * \{
81 * <b>PSoC™ 6S1 Clock Tree:</b>
82 * \image html psoc6able2_clock_tree.png
83 * \}
84 * \addtogroup group_hal_impl_clock_psoc6_02 PSoC™ 6S2 Clocks
85 * \{
86 * <b>PSoC™ 6S2 Clock Tree:</b>
87 * \image html psoc6a2m_clock_tree.png
88 * \}
89 * \addtogroup group_hal_impl_clock_psoc6_03 PSoC™ 6S3 Clocks
90 * \{
91 * <b>PSoC™ 6S3 Clock Tree:</b>
92 * \image html psoc6a512k_clock_tree.png
93 * \}
94 * \addtogroup group_hal_impl_clock_psoc6_04 PSoC™ 6S4 Clocks
95 * \{
96 * <b>PSoC™ 6S4 Clock Tree:</b>
97 * \image html psoc6a256k_clock_tree.png
98 * \}
99 * \addtogroup group_hal_impl_clock_xmc7100 XMC7100/T2G-B-H-4M Clocks
100 * \{
101 * <b>XMC7100/T2G-B-H-4M Clock Tree:</b>
102 * \image html xmc7100_clock_tree.png
103 * \}
104 * \addtogroup group_hal_impl_clock_xmc7200 XMC7200/T2G-B-H-8M Clocks
105 * \{
106 * <b>XMC7200/T2G-B-H-8M Clock Tree:</b>
107 * \image html xmc7200_clock_tree.png
108 * \}
109 */
110
111 /** \cond INTERNAL */
112 #define SRSS_MFO_PRESENT (SRSS_VER1P3)
113 /** \endcond */
114
115 /** Internal Main Oscillator: This is a fixed-frequency clock that is commonly used as a general purpose source for clocks that do not require specific frequencies or very high accuracy. This clock is stopped in the deep sleep and hibernate power modes. */
116 extern const cyhal_clock_t CYHAL_CLOCK_IMO;
117 /** Internal Main Oscillator: This is a fixed-frequency clock that is commonly used as a general purpose source for clocks that do not require specific frequencies or very high accuracy. This clock is stopped in the deep sleep and hibernate power modes. */
118 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_IMO;
119
120 /** External Clock: This is an off-chip clock (not an oscillator). This clock is stopped in the deep sleep and hibernate power modes. */
121 extern const cyhal_clock_t CYHAL_CLOCK_EXT;
122 /** External Clock: This is an off-chip clock (not an oscillator). This clock is stopped in the deep sleep and hibernate power modes. */
123 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_EXT;
124
125 #if defined(COMPONENT_CAT1C)
126 /*!< CLK MEM */
127 extern const cyhal_clock_t CYHAL_CLOCK_MEM;
128 /*!< CLK MEM */
129 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_MEM;
130 #endif
131
132 #if (_CYHAL_SRSS_ILO_PRESENT)
133 #if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1B)
134 /** Internal Low Speed Oscillator: This is a low accuracy fixed-frequency clock in the kilohertz range that is available in sleep, deep sleep and hibernate power modes. */
135 extern const cyhal_clock_t CYHAL_CLOCK_ILO;
136 /** Internal Low Speed Oscillator: This is a low accuracy fixed-frequency clock in the kilohertz range that is available in sleep, deep sleep and hibernate power modes. */
137 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_ILO;
138 #elif defined(COMPONENT_CAT1C)
139 /** Internal Low Speed Oscillator: This is a low accuracy fixed-frequency clock in the kilohertz range that is available in sleep, deep sleep and hibernate power modes. */
140 extern const cyhal_clock_t CYHAL_CLOCK_ILO[_CYHAL_SRSS_NUM_ILO];
141 /** Internal Low Speed Oscillator: This is a low accuracy fixed-frequency clock in the kilohertz range that is available in sleep, deep sleep and hibernate power modes. */
142 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_ILO[_CYHAL_SRSS_NUM_ILO];
143 #endif
144 #endif /* (_CYHAL_SRSS_ILO_PRESENT) */
145
146 #if SRSS_ECO_PRESENT
147 /** External Crystal Oscillator: This is an off-chip clock source that is used when specific frequencies and/or very high accuracy is required. This clock is stopped in the deep sleep and hibernate power modes. */
148 extern const cyhal_clock_t CYHAL_CLOCK_ECO;
149 /** External Crystal Oscillator: This is an off-chip clock source that is used when specific frequencies and/or very high accuracy is required. This clock is stopped in the deep sleep and hibernate power modes. */
150 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_ECO;
151 /** External Crystal Oscillator Prescaler. */
152 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_ECO_PRESCALER;
153 #endif
154 #if SRSS_ALTHF_PRESENT
155 /** Alternate High Frequency Clock: A high speed clock input provided by a subsystem outside the clocking system. This clock is stopped in the deep sleep and hibernate power modes. */
156 extern const cyhal_clock_t CYHAL_CLOCK_ALTHF;
157 /** Alternate High Frequency Clock: A high speed clock input provided by a subsystem outside the clocking system. This clock is stopped in the deep sleep and hibernate power modes. */
158 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_ALTHF;
159 #endif
160 #if SRSS_ALTLF_PRESENT
161 /** Alternate Low Frequency Clock: A low speed clock input provided by a subsystem outside the clocking system. This clock is the hibernate power mode. */
162 extern const cyhal_clock_t CYHAL_CLOCK_ALTLF;
163 /** Alternate Low Frequency Clock: A low speed clock input provided by a subsystem outside the clocking system. This clock is the hibernate power mode. */
164 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_ALTLF;
165 #endif
166 #if SRSS_PILO_PRESENT
167 /** Precision ILO: An additional source that can provide a much more accurate 32.768kHz clock than ILO when periodically calibrated using a high-accuracy clock such as the ECO. This clock is stopped in the hibernate power mode. */
168 extern const cyhal_clock_t CYHAL_CLOCK_PILO;
169 /** Precision ILO: An additional source that can provide a much more accurate 32.768kHz clock than ILO when periodically calibrated using a high-accuracy clock such as the ECO. This clock is stopped in the hibernate power mode. */
170 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_PILO;
171 #endif
172 #if SRSS_BACKUP_PRESENT || SRSS_WCO_PRESENT
173 /** Watch Crystal Oscillator: This source is driven from an off-chip watch crystal that provides an extremely accurate source. This clock is stopped in the hibernate power mode. */
174 extern const cyhal_clock_t CYHAL_CLOCK_WCO;
175 /** Watch Crystal Oscillator: This source is driven from an off-chip watch crystal that provides an extremely accurate source. This clock is stopped in the hibernate power mode. */
176 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_WCO;
177 #endif
178 #if SRSS_S40E_LPECO_PRESENT
179 /** Low Power External Crystal Oscillator: This source is driven from an off-chip external crystal that provides an extremely accurate source. This clock is stopped in the hibernate power mode. */
180 extern const cyhal_clock_t CYHAL_CLOCK_LPECO_PRESCALER;
181 /** Low Power External Crystal Oscillator: This source is driven from an off-chip external crystal that provides an extremely accurate source. This clock is stopped in the hibernate power mode. */
182 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_LPECO_PRESCALER;
183 #endif
184 #if defined(COMPONENT_CAT1B) || (SRSS_MFO_PRESENT)
185 /** Medium Frequency Oscillator: This source produced by dividing the IMO by 4. The MFO works down to DeepSleep, and the IMO does not turn off if this clock requires it. */
186 extern const cyhal_clock_t CYHAL_CLOCK_MFO;
187 #endif
188 /** Medium Frequency Oscillator: This source produced by dividing the IMO by 4. The MFO works down to DeepSleep, and the IMO does not turn off if this clock requires it. */
189 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_MFO;
190 #if defined(COMPONENT_CAT1B) || (SRSS_MFO_PRESENT) || defined(CY_IP_MXS22SRSS)
191 /** Medium Frequency Clock: This clock is a medium frequency, between the Low Frequency Clock (LF) and High Frequency Clock (HF). */
192 extern const cyhal_clock_t CYHAL_CLOCK_MF;
193 /** Medium Frequency Clock: This clock is a medium frequency, between the Low Frequency Clock (LF) and High Frequency Clock (HF). */
194 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_MF;
195 #endif
196
197 /** Low Frequency Clock: This clock is the source for the multi-counter watchdog timers (MCWDT), and can also be a source for the RTC. */
198 extern const cyhal_clock_t CYHAL_CLOCK_LF;
199 /** Low Frequency Clock: This clock is the source for the multi-counter watchdog timers (MCWDT), and can also be a source for the RTC. */
200 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_LF;
201
202 /* PUMP clock is only available on CAT1A and CAT1B devices */
203 #if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1B)
204 /** Analog Pump Clock: This clock ensures precision analog performance in low voltage applications. */
205 extern const cyhal_clock_t CYHAL_CLOCK_PUMP;
206 /** Analog Pump Clock: This clock ensures precision analog performance in low voltage applications. */
207 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_PUMP;
208 #endif /* defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1B) */
209
210 /** Backup Clock: This clock is available to the backup domain. Typically useful if an external WCO is not available. */
211 extern const cyhal_clock_t CYHAL_CLOCK_BAK;
212 /** Backup Clock: This clock is available to the backup domain. Typically useful if an external WCO is not available. */
213 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_BAK;
214
215 /** AltSysTickClk: Provides an optional external source for the CM4/CM0+ SysTick timers. */
216 extern const cyhal_clock_t CYHAL_CLOCK_ALT_SYS_TICK;
217 /** AltSysTickClk: Provides an optional external source for the CM4/CM0+ SysTick timers. */
218 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_ALT_SYS_TICK;
219
220 #if (SRSS_NUM_CLKPATH > 0)
221 /** Path mux selection: A clock source for high frequency clocks. */
222 extern const cyhal_clock_t CYHAL_CLOCK_PATHMUX[SRSS_NUM_CLKPATH];
223 /** Path mux selection: A clock source for high frequency clocks. */
224 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_PATHMUX[SRSS_NUM_CLKPATH];
225 #endif
226
227 #if defined(COMPONENT_CAT1A)
228 /** Fast Clock: This clock is used for the CM4 and associated AHB-Lite bus infrastructure. */
229 extern const cyhal_clock_t CYHAL_CLOCK_FAST;
230 /** Fast Clock: This clock is used for the CM4 and associated AHB-Lite bus infrastructure. */
231 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_FAST;
232
233 /** Peripheral Clock: This is the source clock for any divided clock in the design. */
234 extern const cyhal_clock_t CYHAL_CLOCK_PERI;
235 /** Peripheral Clock: This is the source clock for any divided clock in the design. */
236 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_PERI;
237 #endif
238
239 #if defined(COMPONENT_CAT1C)
240 /** Fast Clock: This clock is used for the CM4 and associated AHB-Lite bus infrastructure. */
241 extern const cyhal_clock_t CYHAL_CLOCK_FAST[_CYHAL_SRSS_NUM_FAST];
242 /** Fast Clock: This clock is used for the CM4 and associated AHB-Lite bus infrastructure. */
243 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_FAST[_CYHAL_SRSS_NUM_FAST];
244
245 #endif
246
247 #if defined(COMPONENT_CAT1A)
248 /** Timer Clock: This clock is intended as a source for high-frequency timers, such as the Energy Profiler and CPU SysTick clock. This clock is stopped in the hibernate power mode. */
249 extern const cyhal_clock_t CYHAL_CLOCK_TIMER;
250 /** Timer Clock: This clock is intended as a source for high-frequency timers, such as the Energy Profiler and CPU SysTick clock. This clock is stopped in the hibernate power mode. */
251 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_TIMER;
252 #endif
253
254 #if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1C)
255 /** Slow Clock: This clock is used for the CM0+ CPU, Datawire and CRYPTO components and the associated CPUSS slow infrastructure. */
256 extern const cyhal_clock_t CYHAL_CLOCK_SLOW;
257 /** Slow Clock: This clock is used for the CM0+ CPU, Datawire and CRYPTO components and the associated CPUSS slow infrastructure. */
258 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_SLOW;
259 #endif
260 #if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(COMPONENT_CAT1D)
261 #if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1D)
262 /** Internal High-Speed Oscillator: This is a fixed-frequency clock that is commonly used as a general purpose source for clocks that do not require specific frequencies or very high accuracy. This clock is stopped in the deep sleep and hibernate power modes. */
263 extern const cyhal_clock_t CYHAL_CLOCK_IHO;
264 /** Internal High-Speed Oscillator: This is a fixed-frequency clock that is commonly used as a general purpose source for clocks that do not require specific frequencies or very high accuracy. This clock is stopped in the deep sleep and hibernate power modes. */
265 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_IHO;
266 #endif
267
268 /** Peripheral Clock: This is the source clock for any divided clock in the design. */
269 extern const cyhal_clock_t CYHAL_CLOCK_PERI[CY_PERI_GROUP_NR];
270 /** Peripheral Clock: This is the source clock for any divided clock in the design. */
271 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_PERI[CY_PERI_GROUP_NR];
272 #endif
273
274 #if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1C) || (SRSS_FLL_PRESENT)
275 /** Frequency-Locked Loop: This is a high-frequency clock suitable for most on-chip purposes. It is similar to a PLL, but starts up much faster and consumes less current. This clock is stopped in the deep sleep and hibernate power modes. */
276 extern const cyhal_clock_t CYHAL_CLOCK_FLL;
277 /** Frequency-Locked Loop: This is a high-frequency clock suitable for most on-chip purposes. It is similar to a PLL, but starts up much faster and consumes less current. This clock is stopped in the deep sleep and hibernate power modes. */
278 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_FLL;
279 #endif
280
281 #if (_CYHAL_SRSS_NUM_PLL > 0) && defined(COMPONENT_CAT1A)
282 /** Phase-Locked Loop: A high-frequency clock able to generate a wide range of clock frequencies making it suitable for most on-chip purposes. This clock is stopped in the deep sleep and hibernate power modes. */
283 extern const cyhal_clock_t CYHAL_CLOCK_PLL[_CYHAL_SRSS_NUM_PLL];
284 /** Phase-Locked Loop: A high-frequency clock able to generate a wide range of clock frequencies making it suitable for most on-chip purposes. This clock is stopped in the deep sleep and hibernate power modes. */
285 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_PLL[_CYHAL_SRSS_NUM_PLL];
286 #endif
287 #if (SRSS_NUM_PLL > 0) && defined(COMPONENT_CAT1C)
288 /** 200MHz Phase-Locked Loop: A high-frequency clock able to generate a wide range of clock frequencies making it suitable for most on-chip purposes. This clock is stopped in the deep sleep and hibernate power modes. */
289 extern const cyhal_clock_t CYHAL_CLOCK_PLL200[SRSS_NUM_PLL200M];
290 /** 200MHz Phase-Locked Loop: A high-frequency clock able to generate a wide range of clock frequencies making it suitable for most on-chip purposes. This clock is stopped in the deep sleep and hibernate power modes. */
291 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_PLL200M[SRSS_NUM_PLL200M];
292 #endif
293 #if (SRSS_NUM_PLL400M > 0) && defined(COMPONENT_CAT1C)
294 /** 400MHz Phase-Locked Loop: A high-frequency clock able to generate a wide range of clock frequencies making it suitable for most on-chip purposes. This clock is stopped in the deep sleep and hibernate power modes. */
295 extern const cyhal_clock_t CYHAL_CLOCK_PLL400[SRSS_NUM_PLL400M];
296 /** 400MHz Phase-Locked Loop: A high-frequency clock able to generate a wide range of clock frequencies making it suitable for most on-chip purposes. This clock is stopped in the deep sleep and hibernate power modes. */
297 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_PLL400M[SRSS_NUM_PLL400M];
298 #endif
299
300 #if (SRSS_NUM_PLL200M > 0) && defined(COMPONENT_CAT1B)
301 /** 200MHz Phase-Locked Loop: A high-frequency clock able to generate a wide range of clock frequencies making it suitable for most on-chip purposes. This clock is stopped in the deep sleep and hibernate power modes. */
302 extern const cyhal_clock_t CYHAL_CLOCK_PLL[SRSS_NUM_PLL200M];
303 /** 200MHz Phase-Locked Loop: A high-frequency clock able to generate a wide range of clock frequencies making it suitable for most on-chip purposes. This clock is stopped in the deep sleep and hibernate power modes. */
304 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_PLL[SRSS_NUM_PLL200M];
305 #endif
306 #if (SRSS_NUM_PLL400M > 0) && defined(COMPONENT_CAT1B)
307 /** 400MHz Phase-Locked Loop: A high-frequency clock able to generate a wide range of clock frequencies making it suitable for most on-chip purposes. This clock is stopped in the deep sleep and hibernate power modes. */
308 extern const cyhal_clock_t CYHAL_CLOCK_PLL[SRSS_NUM_PLL400M];
309 /** 400MHz Phase-Locked Loop: A high-frequency clock able to generate a wide range of clock frequencies making it suitable for most on-chip purposes. This clock is stopped in the deep sleep and hibernate power modes. */
310 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_PLL[SRSS_NUM_PLL400M];
311 #endif
312
313 #if (SRSS_NUM_DPLL250M > 0) && defined(COMPONENT_CAT1D)
314 /** 250MHz Digital Phase-Locked Loop: A high-frequency clock able to generate a wide range of clock frequencies making it suitable for most on-chip purposes. This clock is stopped in the deep sleep and hibernate power modes. */
315 extern const cyhal_clock_t CYHAL_CLOCK_DPLL250[SRSS_NUM_DPLL250M];
316 /** 250MHz Digital Phase-Locked Loop: A high-frequency clock able to generate a wide range of clock frequencies making it suitable for most on-chip purposes. This clock is stopped in the deep sleep and hibernate power modes. */
317 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_DPLL250M[SRSS_NUM_DPLL250M];
318 #endif
319 #if (SRSS_NUM_DPLL500M > 0) && defined(COMPONENT_CAT1D)
320 /** 500MHz Digital Phase-Locked Loop: A high-frequency clock able to generate a wide range of clock frequencies making it suitable for most on-chip purposes. This clock is stopped in the deep sleep and hibernate power modes. */
321 extern const cyhal_clock_t CYHAL_CLOCK_DPLL500[SRSS_NUM_DPLL500M];
322 /** 500MHz Digital Phase-Locked Loop: A high-frequency clock able to generate a wide range of clock frequencies making it suitable for most on-chip purposes. This clock is stopped in the deep sleep and hibernate power modes. */
323 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_DPLL500M[SRSS_NUM_DPLL500M];
324 #endif
325
326 /** High Frequency Clock: A high-frequency clock output driving specific peripherals. */
327 extern const cyhal_clock_t CYHAL_CLOCK_HF[SRSS_NUM_HFROOT];
328 /** High Frequency Clock: A high-frequency clock output driving specific peripherals. */
329 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_HF[SRSS_NUM_HFROOT];
330
331 /** \} group_hal_impl_clock */
332
333 cy_rslt_t _cyhal_clock_allocate_channel(cyhal_clock_t *clock, cyhal_clock_block_t block, const void* funcs);
334
335 const void* _cyhal_clock_get_funcs_pathmux(void);
336 #if (_CYHAL_SRSS_NUM_PLL > 0)
337 const void* _cyhal_clock_get_funcs_pll(void);
338 #endif
339 const void* _cyhal_clock_get_funcs_hf(void);
340 const void* _cyhal_clock_get_funcs_peripheral(void);
341
342
_cyhal_clock_get_funcs(cyhal_clock_block_t block)343 static inline const void* _cyhal_clock_get_funcs(cyhal_clock_block_t block)
344 {
345 switch (block)
346 {
347 case CYHAL_CLOCK_BLOCK_PATHMUX:
348 return _cyhal_clock_get_funcs_pathmux();
349 #if (_CYHAL_SRSS_NUM_PLL > 0)
350 #if defined(COMPONENT_CAT1C)
351 case CYHAL_CLOCK_BLOCK_PLL200:
352 case CYHAL_CLOCK_BLOCK_PLL400:
353 #elif defined(COMPONENT_CAT1D)
354 case CYHAL_CLOCK_BLOCK_DPLL250:
355 case CYHAL_CLOCK_BLOCK_DPLL500:
356 #else
357 case CYHAL_CLOCK_BLOCK_PLL:
358 #endif
359 return _cyhal_clock_get_funcs_pll();
360 #endif
361 case CYHAL_CLOCK_BLOCK_HF:
362 return _cyhal_clock_get_funcs_hf();
363 default:
364 return (block < 4 * _CYHAL_CLOCK_PERI_GROUPS)
365 ? _cyhal_clock_get_funcs_peripheral()
366 : NULL;
367 }
368 }
_cyhal_clock_allocate(cyhal_clock_t * clock,cyhal_clock_block_t block)369 static inline cy_rslt_t _cyhal_clock_allocate(cyhal_clock_t *clock, cyhal_clock_block_t block)
370 {
371 CY_ASSERT(NULL != clock);
372
373 const void* funcs = _cyhal_clock_get_funcs(block);
374 return (NULL == funcs)
375 ? CYHAL_CLOCK_RSLT_ERR_NOT_SUPPORTED
376 : _cyhal_clock_allocate_channel(clock, block, funcs);
377 }
_cyhal_clock_allocate_peri(cyhal_clock_t * clock,cyhal_clock_block_t block)378 static inline cy_rslt_t _cyhal_clock_allocate_peri(cyhal_clock_t *clock, cyhal_clock_block_t block)
379 {
380 CY_ASSERT(NULL != clock);
381
382 const void* funcs = _cyhal_clock_get_funcs_peripheral();
383 return _cyhal_clock_allocate_channel(clock, block, funcs);
384 }
385
386 #define cyhal_clock_allocate(clock, block) _cyhal_clock_allocate(clock, block)
387
388 #if defined(__cplusplus)
389 }
390 #endif
391
392 #endif // CYHAL_DRIVER_AVAILABLE_CLOCK
393
