1/* 2 * Copyright (c) 2024 Renesas Electronics Corporation 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <mem.h> 8#include <arm/armv8.1-m.dtsi> 9#include <freq.h> 10#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h> 11#include <zephyr/dt-bindings/clock/ra_clock.h> 12#include <zephyr/dt-bindings/pwm/ra_pwm.h> 13 14/ { 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu@0 { 20 device_type = "cpu"; 21 compatible = "arm,cortex-m85"; 22 reg = <0>; 23 #address-cells = <1>; 24 #size-cells = <1>; 25 26 mpu: mpu@e000ed90 { 27 compatible = "arm,armv8.1m-mpu"; 28 reg = <0xe000ed90 0x40>; 29 }; 30 }; 31 }; 32 33 soc { 34 interrupt-parent = <&nvic>; 35 36 sram0: memory@22000000 { 37 compatible = "mmio-sram"; 38 reg = <0x22000000 DT_SIZE_K(896)>; 39 }; 40 41 system: system@4001e000 { 42 compatible = "renesas,ra-system"; 43 reg = <0x4001e000 0x1000>; 44 status = "okay"; 45 }; 46 47 pinctrl: pin-controller@40400800 { 48 compatible = "renesas,ra-pinctrl-pfs"; 49 reg = <0x40400800 0x3c0>; 50 status = "okay"; 51 }; 52 53 ioport0: gpio@40400000 { 54 compatible = "renesas,ra-gpio-ioport"; 55 reg = <0x40400000 0x20>; 56 port = <0>; 57 gpio-controller; 58 #gpio-cells = <2>; 59 ngpios = <16>; 60 status = "disabled"; 61 }; 62 63 ioport1: gpio@40400020 { 64 compatible = "renesas,ra-gpio-ioport"; 65 reg = <0x40400020 0x20>; 66 port = <1>; 67 gpio-controller; 68 #gpio-cells = <2>; 69 ngpios = <16>; 70 status = "disabled"; 71 }; 72 73 ioport2: gpio@40400040 { 74 compatible = "renesas,ra-gpio-ioport"; 75 reg = <0x40400040 0x20>; 76 port = <2>; 77 gpio-controller; 78 #gpio-cells = <2>; 79 ngpios = <16>; 80 status = "disabled"; 81 }; 82 83 ioport3: gpio@40400060 { 84 compatible = "renesas,ra-gpio-ioport"; 85 reg = <0x40400060 0x20>; 86 port = <3>; 87 gpio-controller; 88 #gpio-cells = <2>; 89 ngpios = <16>; 90 status = "disabled"; 91 }; 92 93 ioport4: gpio@40400080 { 94 compatible = "renesas,ra-gpio-ioport"; 95 reg = <0x40400080 0x20>; 96 port = <4>; 97 gpio-controller; 98 #gpio-cells = <2>; 99 ngpios = <16>; 100 vbatts_pins = <2 3 4>; 101 status = "disabled"; 102 }; 103 104 ioport5: gpio@404000a0 { 105 compatible = "renesas,ra-gpio-ioport"; 106 reg = <0x404000a0 0x20>; 107 port = <5>; 108 gpio-controller; 109 #gpio-cells = <2>; 110 ngpios = <16>; 111 status = "disabled"; 112 }; 113 114 ioport6: gpio@404000c0 { 115 compatible = "renesas,ra-gpio-ioport"; 116 reg = <0x404000c0 0x20>; 117 port = <6>; 118 gpio-controller; 119 #gpio-cells = <2>; 120 ngpios = <16>; 121 status = "disabled"; 122 }; 123 124 ioport7: gpio@404000e0 { 125 compatible = "renesas,ra-gpio-ioport"; 126 reg = <0x404000e0 0x20>; 127 port = <7>; 128 gpio-controller; 129 #gpio-cells = <2>; 130 ngpios = <16>; 131 status = "disabled"; 132 }; 133 134 ioport8: gpio@40400100 { 135 compatible = "renesas,ra-gpio-ioport"; 136 reg = <0x40400100 0x20>; 137 port = <8>; 138 gpio-controller; 139 #gpio-cells = <2>; 140 ngpios = <16>; 141 status = "disabled"; 142 }; 143 144 ioport9: gpio@40400120 { 145 compatible = "renesas,ra-gpio-ioport"; 146 reg = <0x40400120 0x20>; 147 port = <9>; 148 gpio-controller; 149 #gpio-cells = <2>; 150 ngpios = <16>; 151 status = "disabled"; 152 }; 153 154 ioporta: gpio@40400140 { 155 compatible = "renesas,ra-gpio-ioport"; 156 reg = <0x40400140 0x20>; 157 port = <10>; 158 gpio-controller; 159 #gpio-cells = <2>; 160 ngpios = <16>; 161 status = "disabled"; 162 }; 163 164 ioportb: gpio@40400160 { 165 compatible = "renesas,ra-gpio-ioport"; 166 reg = <0x40400160 0x20>; 167 port = <11>; 168 gpio-controller; 169 #gpio-cells = <2>; 170 ngpios = <16>; 171 status = "disabled"; 172 }; 173 174 iic0: iic0@4025e000 { 175 compatible = "renesas,ra-iic"; 176 channel = <0>; 177 reg = <0x4025E000 0x100>; 178 status = "disabled"; 179 }; 180 iic1: iic1@4025e100 { 181 compatible = "renesas,ra-iic"; 182 channel = <1>; 183 interrupts = <91 1>, <92 1>, <93 1>, <94 1>; 184 interrupt-names = "rxi", "txi", "tei", "eri"; 185 reg = <0x4025E100 0x100>; 186 status = "disabled"; 187 }; 188 189 sci0: sci0@40358000 { 190 compatible = "renesas,ra-sci"; 191 interrupts = <4 1>, <5 1>, <6 1>, <7 1>; 192 interrupt-names = "rxi", "txi", "tei", "eri"; 193 reg = <0x40358000 0x100>; 194 clocks = <&sciclk MSTPB 31>; 195 status = "disabled"; 196 uart { 197 compatible = "renesas,ra8-uart-sci-b"; 198 channel = <0>; 199 status = "disabled"; 200 }; 201 }; 202 203 sci1: sci1@40358100 { 204 compatible = "renesas,ra-sci"; 205 interrupts = <8 1>, <9 1>, <10 1>, <11 1>; 206 interrupt-names = "rxi", "txi", "tei", "eri"; 207 reg = <0x40358100 0x100>; 208 clocks = <&sciclk MSTPB 30>; 209 status = "disabled"; 210 uart { 211 compatible = "renesas,ra8-uart-sci-b"; 212 channel = <1>; 213 status = "disabled"; 214 }; 215 }; 216 217 sci2: sci2@40358200 { 218 compatible = "renesas,ra-sci"; 219 interrupts = <12 1>, <13 1>, <14 1>, <15 1>; 220 interrupt-names = "rxi", "txi", "tei", "eri"; 221 reg = <0x40358200 0x100>; 222 clocks = <&sciclk MSTPB 29>; 223 status = "disabled"; 224 uart { 225 compatible = "renesas,ra8-uart-sci-b"; 226 channel = <2>; 227 status = "disabled"; 228 }; 229 }; 230 231 sci3: sci3@40358300 { 232 compatible = "renesas,ra-sci"; 233 interrupts = <16 1>, <17 1>, <18 1>, <19 1>; 234 interrupt-names = "rxi", "txi", "tei", "eri"; 235 reg = <0x40358300 0x100>; 236 clocks = <&sciclk MSTPB 28>; 237 status = "disabled"; 238 uart { 239 compatible = "renesas,ra8-uart-sci-b"; 240 channel = <3>; 241 status = "disabled"; 242 }; 243 }; 244 245 sci4: sci4@40358400 { 246 compatible = "renesas,ra-sci"; 247 interrupts = <20 1>, <21 1>, <22 1>, <23 1>; 248 interrupt-names = "rxi", "txi", "tei", "eri"; 249 reg = <0x40358400 0x100>; 250 clocks = <&sciclk MSTPB 27>; 251 status = "disabled"; 252 uart { 253 compatible = "renesas,ra8-uart-sci-b"; 254 channel = <4>; 255 status = "disabled"; 256 }; 257 }; 258 259 sci9: sci9@40358900 { 260 compatible = "renesas,ra-sci"; 261 interrupts = <24 1>, <25 1>, <26 1>, <27 1>; 262 interrupt-names = "rxi", "txi", "tei", "eri"; 263 reg = <0x40358900 0x100>; 264 clocks = <&sciclk MSTPB 22>; 265 status = "disabled"; 266 uart { 267 compatible = "renesas,ra8-uart-sci-b"; 268 channel = <9>; 269 status = "disabled"; 270 }; 271 }; 272 273 flash: flash-controller@40100000 { 274 compatible = "renesas,ra-flash-hp-controller"; 275 reg = <0x40100000 0x20000>; 276 #address-cells = <1>; 277 #size-cells = <1>; 278 interrupts = <49 1>, <50 1>; 279 interrupt-names = "frdyi", "fiferr"; 280 }; 281 282 adc0: adc@40332000 { 283 compatible = "renesas,ra-adc"; 284 interrupts = <38 1>; 285 interrupt-names = "scanend"; 286 reg = <0x40332000 0x100>; 287 #io-channel-cells = <1>; 288 vref-mv = <3300>; 289 channel-count = <12>; 290 channel-available-mask = <0xf01f7>; 291 status = "disabled"; 292 }; 293 294 adc1: adc@40332200 { 295 compatible = "renesas,ra-adc"; 296 interrupts = <39 1>; 297 interrupt-names = "scanend"; 298 reg = <0x40332200 0x100>; 299 #io-channel-cells = <1>; 300 vref-mv = <3300>; 301 channel-count = <13>; 302 channel-available-mask = <0x7f0077>; 303 status = "disabled"; 304 }; 305 306 trng: trng { 307 compatible = "renesas,ra-rsip-e51a-trng"; 308 }; 309 310 spi0: spi@4035c000 { 311 compatible = "renesas,ra8-spi-b"; 312 #address-cells = <1>; 313 #size-cells = <0>; 314 channel = <0>; 315 clocks = <&pclka MSTPB 19>; 316 clock-names = "spiclk"; 317 interrupts = <28 1>, <29 1>, <30 1>, <31 1>; 318 interrupt-names = "rxi", "txi", "tei", "eri"; 319 reg = <0x4035c000 0x100>; 320 status = "disabled"; 321 }; 322 323 spi1: spi@4035c100 { 324 compatible = "renesas,ra8-spi-b"; 325 #address-cells = <1>; 326 #size-cells = <0>; 327 channel = <1>; 328 clocks = <&pclka MSTPB 18>; 329 clock-names = "spiclk"; 330 interrupts = <32 1>, <33 1>, <34 1>, <35 1>; 331 interrupt-names = "rxi", "txi", "tei", "eri"; 332 reg = <0x4035c100 0x100>; 333 status = "disabled"; 334 }; 335 336 pwm0: pwm0@40322000 { 337 compatible = "renesas,ra-pwm"; 338 divider = <RA_PWM_SOURCE_DIV_1>; 339 channel = <RA_PWM_CHANNEL_0>; 340 clocks = <&pclkd MSTPE 31>; 341 reg = <0x40322000 0x100>; 342 #pwm-cells = <3>; 343 status = "disabled"; 344 }; 345 346 pwm1: pwm1@40322100 { 347 compatible = "renesas,ra-pwm"; 348 divider = <RA_PWM_SOURCE_DIV_1>; 349 channel = <RA_PWM_CHANNEL_1>; 350 clocks = <&pclkd MSTPE 30>; 351 reg = <0x40322100 0x100>; 352 #pwm-cells = <3>; 353 status = "disabled"; 354 }; 355 356 pwm2: pwm2@40322200 { 357 compatible = "renesas,ra-pwm"; 358 divider = <RA_PWM_SOURCE_DIV_1>; 359 channel = <RA_PWM_CHANNEL_2>; 360 clocks = <&pclkd MSTPE 29>; 361 reg = <0x40322200 0x100>; 362 #pwm-cells = <3>; 363 status = "disabled"; 364 }; 365 366 pwm3: pwm3@40322300 { 367 compatible = "renesas,ra-pwm"; 368 divider = <RA_PWM_SOURCE_DIV_1>; 369 channel = <RA_PWM_CHANNEL_3>; 370 clocks = <&pclkd MSTPE 28>; 371 reg = <0x40322300 0x100>; 372 #pwm-cells = <3>; 373 status = "disabled"; 374 }; 375 376 pwm4: pwm4@40322400 { 377 compatible = "renesas,ra-pwm"; 378 divider = <RA_PWM_SOURCE_DIV_1>; 379 channel = <RA_PWM_CHANNEL_4>; 380 clocks = <&pclkd MSTPE 27>; 381 reg = <0x40322400 0x100>; 382 #pwm-cells = <3>; 383 status = "disabled"; 384 }; 385 386 pwm5: pwm5@40322500 { 387 compatible = "renesas,ra-pwm"; 388 divider = <RA_PWM_SOURCE_DIV_1>; 389 channel = <RA_PWM_CHANNEL_5>; 390 clocks = <&pclkd MSTPE 26>; 391 reg = <0x40322500 0x100>; 392 #pwm-cells = <3>; 393 status = "disabled"; 394 }; 395 396 pwm6: pwm6@40322600 { 397 compatible = "renesas,ra-pwm"; 398 divider = <RA_PWM_SOURCE_DIV_1>; 399 channel = <RA_PWM_CHANNEL_6>; 400 clocks = <&pclkd MSTPE 25>; 401 reg = <0x40322600 0x100>; 402 #pwm-cells = <3>; 403 status = "disabled"; 404 }; 405 406 pwm7: pwm7@40322700 { 407 compatible = "renesas,ra-pwm"; 408 divider = <RA_PWM_SOURCE_DIV_1>; 409 channel = <RA_PWM_CHANNEL_7>; 410 clocks = <&pclkd MSTPE 24>; 411 reg = <0x40322700 0x100>; 412 #pwm-cells = <3>; 413 status = "disabled"; 414 }; 415 416 pwm8: pwm8@40322800 { 417 compatible = "renesas,ra-pwm"; 418 divider = <RA_PWM_SOURCE_DIV_1>; 419 channel = <RA_PWM_CHANNEL_8>; 420 clocks = <&pclkd MSTPE 23>; 421 reg = <0x40322800 0x100>; 422 #pwm-cells = <3>; 423 status = "disabled"; 424 }; 425 426 pwm9: pwm9@40322900 { 427 compatible = "renesas,ra-pwm"; 428 divider = <RA_PWM_SOURCE_DIV_1>; 429 channel = <RA_PWM_CHANNEL_9>; 430 clocks = <&pclkd MSTPE 22>; 431 reg = <0x40322900 0x100>; 432 #pwm-cells = <3>; 433 status = "disabled"; 434 }; 435 436 pwm10: pwm10@40322a00 { 437 compatible = "renesas,ra-pwm"; 438 divider = <RA_PWM_SOURCE_DIV_1>; 439 channel = <RA_PWM_CHANNEL_10>; 440 clocks = <&pclkd MSTPE 21>; 441 reg = <0x40322a00 0x100>; 442 #pwm-cells = <3>; 443 status = "disabled"; 444 }; 445 446 pwm11: pwm11@40322b00 { 447 compatible = "renesas,ra-pwm"; 448 divider = <RA_PWM_SOURCE_DIV_1>; 449 channel = <RA_PWM_CHANNEL_11>; 450 clocks = <&pclkd MSTPE 20>; 451 reg = <0x40322b00 0x100>; 452 #pwm-cells = <3>; 453 status = "disabled"; 454 }; 455 456 pwm12: pwm12@40322c00 { 457 compatible = "renesas,ra-pwm"; 458 divider = <RA_PWM_SOURCE_DIV_1>; 459 channel = <RA_PWM_CHANNEL_12>; 460 clocks = <&pclkd MSTPE 19>; 461 reg = <0x40322c00 0x100>; 462 #pwm-cells = <3>; 463 status = "disabled"; 464 }; 465 466 pwm13: pwm13@40322d00 { 467 compatible = "renesas,ra-pwm"; 468 divider = <RA_PWM_SOURCE_DIV_1>; 469 channel = <RA_PWM_CHANNEL_13>; 470 clocks = <&pclkd MSTPE 18>; 471 reg = <0x40322d00 0x100>; 472 #pwm-cells = <3>; 473 status = "disabled"; 474 }; 475 476 option_setting_ofs: option_setting_ofs@300a100 { 477 compatible = "zephyr,memory-region"; 478 reg = <0x0300a100 0x18>; 479 zephyr,memory-region = "OPTION_SETTING_OFS"; 480 status = "okay"; 481 }; 482 483 option_setting_sas: option_setting_sas@300a134 { 484 compatible = "zephyr,memory-region"; 485 reg = <0x0300a134 0xcc>; 486 zephyr,memory-region = "OPTION_SETTING_SAS"; 487 status = "okay"; 488 }; 489 490 option_setting_s: option_setting_s@300a200 { 491 compatible = "zephyr,memory-region"; 492 reg = <0x0300a200 0x100>; 493 zephyr,memory-region = "OPTION_SETTING_S"; 494 status = "okay"; 495 }; 496 497 agt0: agt@40221000 { 498 compatible = "renesas,ra-agt"; 499 channel = <0>; 500 reg = <0x40221000 0x100>; 501 interrupts = <83 1>, <84 1>; 502 interrupt-names = "agti", "agtcmai"; 503 renesas,count-source = "AGT_CLOCK_LOCO"; 504 renesas,prescaler = <0>; 505 renesas,resolution = <16>; 506 status = "disabled"; 507 508 counter { 509 compatible = "renesas,ra-agt-counter"; 510 status = "disabled"; 511 }; 512 }; 513 514 agt1: agt@40221100 { 515 compatible = "renesas,ra-agt"; 516 channel = <1>; 517 reg = <0x40221100 0x100>; 518 interrupts = <85 1>, <86 1>; 519 interrupt-names = "agti", "agtcmai"; 520 renesas,count-source = "AGT_CLOCK_LOCO"; 521 renesas,prescaler = <0>; 522 renesas,resolution = <16>; 523 status = "disabled"; 524 525 counter { 526 compatible = "renesas,ra-agt-counter"; 527 status = "disabled"; 528 }; 529 }; 530 531 canfd_global: canfd_global@40380000 { 532 compatible = "renesas,ra-canfd-global"; 533 interrupts = <40 1>, <41 1>; 534 interrupt-names = "rxf", "glerr"; 535 clocks = <&pclka 0 0>, <&pclke 0 0>; 536 clock-names = "opclk", "ramclk"; 537 reg = <0x40380000 0x4000>; 538 status = "disabled"; 539 540 canfd0: canfd0 { 541 compatible = "renesas,ra-canfd"; 542 channel = <0>; 543 interrupts = <43 12>, <44 12>, <45 12>; 544 interrupt-names = "err", "tx", "rx"; 545 clocks = <&canfdclk MSTPC 27>; 546 clock-names = "dllclk"; 547 status = "disabled"; 548 }; 549 550 canfd1: canfd1 { 551 compatible = "renesas,ra-canfd"; 552 channel = <1>; 553 interrupts = <46 1>, <47 1>, <48 1>; 554 interrupt-names = "err", "tx", "rx"; 555 clocks = <&canfdclk MSTPC 26>; 556 clock-names = "dllclk"; 557 status = "disabled"; 558 }; 559 }; 560 561 eth: ethernet@40354100 { 562 compatible = "renesas,ra-ethernet"; 563 reg = <0x40354100 0xfc>; 564 interrupts = <42 0>; 565 local-mac-address = [00 11 22 33 44 55]; 566 phy-connection-type = "rmii"; 567 status = "disabled"; 568 }; 569 570 mdio: mdio { 571 compatible = "renesas,ra-mdio"; 572 #address-cells = <1>; 573 #size-cells = <0>; 574 status = "disabled"; 575 }; 576 577 port_irq0: external-interrupt@40006000 { 578 compatible = "renesas,ra-external-interrupt"; 579 reg = <0x40006000 0x1>; 580 channel = <0>; 581 renesas,sample-clock-div = <64>; 582 #port-irq-cells = <0>; 583 status = "disabled"; 584 }; 585 586 port_irq1: external-interrupt@40006001 { 587 compatible = "renesas,ra-external-interrupt"; 588 reg = <0x40006001 0x1>; 589 channel = <1>; 590 renesas,sample-clock-div = <64>; 591 #port-irq-cells = <0>; 592 status = "disabled"; 593 }; 594 595 port_irq2: external-interrupt@40006002 { 596 compatible = "renesas,ra-external-interrupt"; 597 reg = <0x40006002 0x1>; 598 channel = <2>; 599 renesas,sample-clock-div = <64>; 600 #port-irq-cells = <0>; 601 status = "disabled"; 602 }; 603 604 port_irq3: external-interrupt@40006003 { 605 compatible = "renesas,ra-external-interrupt"; 606 reg = <0x40006003 0x1>; 607 channel = <3>; 608 renesas,sample-clock-div = <64>; 609 #port-irq-cells = <0>; 610 status = "disabled"; 611 }; 612 613 port_irq4: external-interrupt@40006004 { 614 compatible = "renesas,ra-external-interrupt"; 615 reg = <0x40006004 0x1>; 616 channel = <4>; 617 renesas,sample-clock-div = <64>; 618 #port-irq-cells = <0>; 619 status = "disabled"; 620 }; 621 622 port_irq5: external-interrupt@40006005 { 623 compatible = "renesas,ra-external-interrupt"; 624 reg = <0x40006005 0x1>; 625 channel = <5>; 626 renesas,sample-clock-div = <64>; 627 #port-irq-cells = <0>; 628 status = "disabled"; 629 }; 630 631 port_irq6: external-interrupt@40006006 { 632 compatible = "renesas,ra-external-interrupt"; 633 reg = <0x40006006 0x1>; 634 channel = <6>; 635 renesas,sample-clock-div = <64>; 636 #port-irq-cells = <0>; 637 status = "disabled"; 638 }; 639 640 port_irq7: external-interrupt@40006007 { 641 compatible = "renesas,ra-external-interrupt"; 642 reg = <0x40006007 0x1>; 643 channel = <7>; 644 renesas,sample-clock-div = <64>; 645 #port-irq-cells = <0>; 646 status = "disabled"; 647 }; 648 649 port_irq8: external-interrupt@40006008 { 650 compatible = "renesas,ra-external-interrupt"; 651 reg = <0x40006008 0x1>; 652 channel = <8>; 653 renesas,sample-clock-div = <64>; 654 #port-irq-cells = <0>; 655 status = "disabled"; 656 }; 657 658 port_irq9: external-interrupt@40006009 { 659 compatible = "renesas,ra-external-interrupt"; 660 reg = <0x40006009 0x1>; 661 channel = <9>; 662 renesas,sample-clock-div = <64>; 663 #port-irq-cells = <0>; 664 status = "disabled"; 665 }; 666 667 port_irq10: external-interrupt@4000600a { 668 compatible = "renesas,ra-external-interrupt"; 669 reg = <0x4000600a 0x1>; 670 channel = <10>; 671 renesas,sample-clock-div = <64>; 672 #port-irq-cells = <0>; 673 status = "disabled"; 674 }; 675 676 port_irq11: external-interrupt@4000600b { 677 compatible = "renesas,ra-external-interrupt"; 678 reg = <0x4000600b 0x1>; 679 channel = <11>; 680 renesas,sample-clock-div = <64>; 681 #port-irq-cells = <0>; 682 status = "disabled"; 683 }; 684 685 port_irq12: external-interrupt@4000600c { 686 compatible = "renesas,ra-external-interrupt"; 687 reg = <0x4000600c 0x1>; 688 channel = <12>; 689 renesas,sample-clock-div = <64>; 690 #port-irq-cells = <0>; 691 status = "disabled"; 692 }; 693 694 port_irq13: external-interrupt@4000600d { 695 compatible = "renesas,ra-external-interrupt"; 696 reg = <0x4000600d 0x1>; 697 channel = <13>; 698 renesas,sample-clock-div = <64>; 699 #port-irq-cells = <0>; 700 status = "disabled"; 701 }; 702 703 port_irq14: external-interrupt@4000600e { 704 compatible = "renesas,ra-external-interrupt"; 705 reg = <0x4000600e 0x1>; 706 channel = <14>; 707 renesas,sample-clock-div = <64>; 708 #port-irq-cells = <0>; 709 status = "disabled"; 710 }; 711 712 port_irq15: external-interrupt@4000600f { 713 compatible = "renesas,ra-external-interrupt"; 714 reg = <0x4000600f 0x1>; 715 channel = <15>; 716 renesas,sample-clock-div = <64>; 717 #port-irq-cells = <0>; 718 status = "disabled"; 719 }; 720 721 sdhc0: sdhc@40252000 { 722 compatible = "renesas,ra-sdhc"; 723 channel = <0>; 724 bus-width = <4>; 725 sd-support; 726 mmc-support; 727 card-detect; 728 max-bus-freq = <DT_FREQ_M(52)>; 729 clocks = <&pclkb MSTPC 12>; 730 reg = <0x40252000 0x0400>; 731 interrupt-names = "accs", "card", "dma-req"; 732 interrupts = <57 12>, <58 12>, <59 12>; 733 status = "disabled"; 734 }; 735 736 sdhc1: sdhc@40252400 { 737 compatible = "renesas,ra-sdhc"; 738 channel = <1>; 739 bus-width = <4>; 740 sd-support; 741 mmc-support; 742 card-detect; 743 max-bus-freq = <DT_FREQ_M(52)>; 744 clocks = <&pclkb MSTPC 11>; 745 reg = <0x40252400 0x0400>; 746 status = "disabled"; 747 }; 748 }; 749}; 750 751&nvic { 752 arm,num-irq-priority-bits = <4>; 753}; 754