1/*
2 * Copyright (c) 2024 Renesas Electronics Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/renesas/ra/ra8/ra8x1.dtsi>
8#include <zephyr/dt-bindings/clock/ra_clock.h>
9
10/ {
11	clocks: clocks {
12		#address-cells = <1>;
13		#size-cells = <1>;
14
15		xtal: clock-main-osc {
16			compatible = "renesas,ra-cgc-external-clock";
17			clock-frequency = <DT_FREQ_M(24)>;
18			#clock-cells = <0>;
19			status = "disabled";
20		};
21
22		hoco: clock-hoco {
23			compatible = "fixed-clock";
24			clock-frequency = <DT_FREQ_M(48)>;
25			#clock-cells = <0>;
26		};
27
28		moco: clock-moco {
29			compatible = "fixed-clock";
30			clock-frequency = <DT_FREQ_M(8)>;
31			#clock-cells = <0>;
32		};
33
34		loco: clock-loco {
35			compatible = "fixed-clock";
36			clock-frequency = <32768>;
37			#clock-cells = <0>;
38		};
39
40		subclk: clock-subclk {
41			compatible = "renesas,ra-cgc-subclk";
42			clock-frequency = <32768>;
43			#clock-cells = <0>;
44			status = "disabled";
45		};
46
47		pll: pll {
48			compatible = "renesas,ra-cgc-pll";
49			#clock-cells = <0>;
50			clocks = <&xtal>;
51			div = <2>;
52			mul = <80 0>;
53
54			pllp: pllp {
55				compatible = "renesas,ra-cgc-pll-out";
56				div = <2>;
57				freq = <DT_FREQ_M(480)>;
58				status = "disabled";
59				#clock-cells = <0>;
60			};
61
62			pllq: pllq {
63				compatible = "renesas,ra-cgc-pll-out";
64				div = <2>;
65				freq = <DT_FREQ_M(480)>;
66				status = "disabled";
67				#clock-cells = <0>;
68			};
69
70			pllr: pllr {
71				compatible = "renesas,ra-cgc-pll-out";
72				div = <2>;
73				freq = <DT_FREQ_M(480)>;
74				status = "disabled";
75				#clock-cells = <0>;
76			};
77			status = "disabled";
78		};
79
80		pll2: pll2 {
81			compatible = "renesas,ra-cgc-pll";
82			#clock-cells = <0>;
83
84			div = <2>;
85			mul = <96 0>;
86
87			pll2p: pll2p {
88				compatible = "renesas,ra-cgc-pll-out";
89				div = <2>;
90				freq = <DT_FREQ_M(0)>;
91				status = "disabled";
92				#clock-cells = <0>;
93			};
94
95			pll2q: pll2q {
96				compatible = "renesas,ra-cgc-pll-out";
97				div = <2>;
98				freq = <DT_FREQ_M(0)>;
99				status = "disabled";
100				#clock-cells = <0>;
101			};
102
103			pll2r: pll2r {
104				compatible = "renesas,ra-cgc-pll-out";
105				div = <2>;
106				freq = <DT_FREQ_M(0)>;
107				status = "disabled";
108				#clock-cells = <0>;
109			};
110			status = "disabled";
111		};
112
113		pclkblock: pclkblock@40203000 {
114			compatible = "renesas,ra-cgc-pclk-block";
115			reg = <0x40203000 4>, <0x40203004 4>, <0x40203008 4>,
116			      <0x4020300c 4>, <0x40203010 4>;
117			reg-names = "MSTPA", "MSTPB","MSTPC",
118				    "MSTPD", "MSTPE";
119			#clock-cells = <0>;
120			clocks = <&pllp>;
121			status = "okay";
122
123			cpuclk: cpuclk {
124				compatible = "renesas,ra-cgc-pclk";
125				clock-frequency = <480000000>;
126				div = <1>;
127				#clock-cells = <2>;
128				status = "okay";
129			};
130
131			iclk: iclk {
132				compatible = "renesas,ra-cgc-pclk";
133				div = <2>;
134				#clock-cells = <2>;
135				status = "okay";
136			};
137
138			pclka: pclka {
139				compatible = "renesas,ra-cgc-pclk";
140				div = <4>;
141				#clock-cells = <2>;
142				status = "okay";
143			};
144
145			pclkb: pclkb {
146				compatible = "renesas,ra-cgc-pclk";
147				div = <8>;
148				#clock-cells = <2>;
149				status = "okay";
150			};
151
152			pclkc: pclkc {
153				compatible = "renesas,ra-cgc-pclk";
154				div = <8>;
155				#clock-cells = <2>;
156				status = "okay";
157			};
158
159			pclkd: pclkd {
160				compatible = "renesas,ra-cgc-pclk";
161				div = <4>;
162				#clock-cells = <2>;
163				status = "okay";
164			};
165
166			pclke: pclke {
167				compatible = "renesas,ra-cgc-pclk";
168				div = <2>;
169				#clock-cells = <2>;
170				status = "okay";
171			};
172
173			bclk: bclk {
174				compatible = "renesas,ra-cgc-pclk";
175				div = <4>;
176				bclkout: bclkout {
177					compatible = "renesas,ra-cgc-busclk";
178					clk-out-div = <2>;
179					sdclk = <1>;
180					#clock-cells = <0>;
181				};
182				#clock-cells = <2>;
183				status = "okay";
184			};
185
186			fclk: fclk {
187				compatible = "renesas,ra-cgc-pclk";
188				div = <8>;
189				#clock-cells = <2>;
190				status = "okay";
191			};
192
193			clkout: clkout {
194				compatible = "renesas,ra-cgc-pclk";
195				#clock-cells = <2>;
196				status = "disabled";
197			};
198
199			sciclk: sciclk {
200				compatible = "renesas,ra-cgc-pclk";
201				#clock-cells = <2>;
202				status = "disabled";
203			};
204
205			spiclk: spiclk {
206				compatible = "renesas,ra-cgc-pclk";
207				#clock-cells = <2>;
208				status = "disabled";
209			};
210
211			canfdclk: canfdclk {
212				compatible = "renesas,ra-cgc-pclk";
213				#clock-cells = <2>;
214				status = "disabled";
215			};
216
217			i3cclk: i3cclk {
218				compatible = "renesas,ra-cgc-pclk";
219				#clock-cells = <2>;
220				status = "disabled";
221			};
222
223			uclk: uclk {
224				compatible = "renesas,ra-cgc-pclk";
225				#clock-cells = <2>;
226				status = "disabled";
227			};
228
229			u60clk: u60clk {
230				compatible = "renesas,ra-cgc-pclk";
231				#clock-cells = <2>;
232				status = "disabled";
233			};
234
235			octaspiclk: octaspiclk {
236				compatible = "renesas,ra-cgc-pclk";
237				#clock-cells = <2>;
238				status = "disabled";
239			};
240
241			lcdclk: lcdclk {
242				compatible = "renesas,ra-cgc-pclk";
243				#clock-cells = <2>;
244				status = "disabled";
245			};
246		};
247	};
248};
249
250&ioport0 {
251	port-irqs = <&port_irq6 &port_irq7 &port_irq8
252	&port_irq9 &port_irq10 &port_irq11
253	&port_irq12 &port_irq13 &port_irq14>;
254	port-irq-names = "port-irq6",
255			 "port-irq7",
256			 "port-irq8",
257			 "port-irq9",
258			 "port-irq10",
259			 "port-irq11",
260			 "port-irq12",
261			 "port-irq13",
262			 "port-irq14";
263	port-irq6-pins = <0>;
264	port-irq7-pins = <1>;
265	port-irq8-pins = <2>;
266	port-irq9-pins = <4>;
267	port-irq10-pins = <5>;
268	port-irq11-pins = <6>;
269	port-irq12-pins = <8>;
270	port-irq13-pins = <9 15>;
271	port-irq14-pins = <10>;
272};
273
274&ioport1 {
275	port-irqs = <&port_irq0 &port_irq1 &port_irq2>;
276	port-irq-names = "port-irq0",
277			 "port-irq1",
278			 "port-irq2";
279	port-irq0-pins = <5>;
280	port-irq1-pins = <1 4>;
281	port-irq2-pins = <0>;
282};
283
284&ioport2 {
285	port-irqs = <&port_irq0 &port_irq1 &port_irq2
286	&port_irq3>;
287	port-irq-names = "port-irq0",
288			 "port-irq1",
289			 "port-irq2",
290			 "port-irq3";
291	port-irq0-pins = <6>;
292	port-irq1-pins = <5>;
293	port-irq2-pins = <3 13>;
294	port-irq3-pins = <2 8 12>;
295};
296
297&ioport3 {
298	port-irqs = <&port_irq4 &port_irq5 &port_irq6
299	&port_irq8 &port_irq9>;
300	port-irq-names = "port-irq4",
301			 "port-irq5",
302			 "port-irq6",
303			 "port-irq8",
304			 "port-irq9";
305	port-irq4-pins = <0>;
306	port-irq5-pins = <2>;
307	port-irq6-pins = <1>;
308	port-irq8-pins = <5>;
309	port-irq9-pins = <4>;
310};
311
312&ioport4 {
313	port-irqs = <&port_irq0 &port_irq4 &port_irq5
314	&port_irq6 &port_irq7 &port_irq8
315	&port_irq9 &port_irq14 &port_irq15>;
316	port-irq-names = "port-irq0",
317			 "port-irq4",
318			 "port-irq5",
319			 "port-irq6",
320			 "port-irq7",
321			 "port-irq8",
322			 "port-irq9",
323			 "port-irq14",
324			 "port-irq15";
325	port-irq0-pins = <0>;
326	port-irq4-pins = <2 11>;
327	port-irq5-pins = <1 10>;
328	port-irq6-pins = <9>;
329	port-irq7-pins = <8>;
330	port-irq8-pins = <15>;
331	port-irq9-pins = <14>;
332	port-irq14-pins = <3>;
333	port-irq15-pins = <4>;
334};
335
336&ioport5 {
337	port-irqs = <&port_irq1 &port_irq2 &port_irq3
338	&port_irq14 &port_irq15>;
339	port-irq-names = "port-irq1",
340			 "port-irq2",
341			 "port-irq3",
342			 "port-irq14",
343			 "port-irq15";
344	port-irq1-pins = <8>;
345	port-irq2-pins = <9>;
346	port-irq3-pins = <10>;
347	port-irq14-pins = <12>;
348	port-irq15-pins = <11>;
349};
350
351&ioport6 {
352	port-irqs = <&port_irq7>;
353	port-irq-names = "port-irq7";
354	port-irq7-pins = <15>;
355};
356
357&ioport7 {
358	port-irqs = <&port_irq7 &port_irq8 &port_irq10
359	&port_irq11>;
360	port-irq-names = "port-irq7",
361			 "port-irq8",
362			 "port-irq10",
363			 "port-irq11";
364	port-irq7-pins = <6>;
365	port-irq8-pins = <7>;
366	port-irq10-pins = <9>;
367	port-irq11-pins = <8>;
368};
369
370&ioport8 {
371	port-irqs = <&port_irq0 &port_irq11 &port_irq12
372	&port_irq14 &port_irq15>;
373	port-irq-names = "port-irq0",
374			 "port-irq11",
375			 "port-irq12",
376			 "port-irq14",
377			 "port-irq15";
378	port-irq0-pins = <6>;
379	port-irq11-pins = <0>;
380	port-irq12-pins = <1>;
381	port-irq14-pins = <4>;
382	port-irq15-pins = <8>;
383};
384
385&ioport9 {
386	port-irqs = <&port_irq8 &port_irq9 &port_irq10
387	&port_irq11>;
388	port-irq-names = "port-irq8",
389			 "port-irq9",
390			 "port-irq10",
391			 "port-irq11";
392	port-irq8-pins = <5>;
393	port-irq9-pins = <6>;
394	port-irq10-pins = <7>;
395	port-irq11-pins = <8>;
396};
397
398&ioporta {
399	port-irqs = <&port_irq4 &port_irq5 &port_irq6>;
400	port-irq-names = "port-irq4",
401			 "port-irq5",
402			 "port-irq6";
403	port-irq4-pins = <10>;
404	port-irq5-pins = <9>;
405	port-irq6-pins = <8>;
406};
407
408&dac_global {
409	has-internal-output;
410	has-output-amplifier;
411};
412