1/*
2 * Copyright (c) 2023 Antmicro <www.antmicro.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <dt-bindings/pinctrl/ambiq-apollo4-pinctrl.h>
8#include "apollo4p_evb_connector.dtsi"
9
10&pinctrl {
11	uart0_default: uart0_default {
12		group1 {
13			pinmux = <UART0TX_P60>;
14		};
15		group2 {
16			pinmux = <UART0RX_P47>;
17			input-enable;
18		};
19	};
20	i2c0_default: i2c0_default {
21		group1 {
22			pinmux = <M0SCL_P5>, <M0SDAWIR3_P6>;
23			drive-open-drain;
24			drive-strength = "0.5";
25			bias-pull-up;
26		};
27	};
28	i2c1_default: i2c1_default {
29		group1 {
30			pinmux = <M1SCL_P8>, <M1SDAWIR3_P9>;
31			drive-open-drain;
32			drive-strength = "0.5";
33			bias-pull-up;
34		};
35	};
36	i2c2_default: i2c2_default {
37		group1 {
38			pinmux = <M2SCL_P25>, <M2SDAWIR3_P26>;
39			drive-open-drain;
40			drive-strength = "0.5";
41			bias-pull-up;
42		};
43	};
44	i2c3_default: i2c3_default {
45		group1 {
46			pinmux = <M3SCL_P31>, <M3SDAWIR3_P32>;
47			drive-open-drain;
48			drive-strength = "0.5";
49			bias-pull-up;
50		};
51	};
52	i2c4_default: i2c4_default {
53		group1 {
54			pinmux = <M4SCL_P34>, <M4SDAWIR3_P35>;
55			drive-open-drain;
56			drive-strength = "0.5";
57			bias-pull-up;
58		};
59	};
60	i2c5_default: i2c5_default {
61		group1 {
62			pinmux = <M5SCL_P47>, <M5SDAWIR3_P48>;
63			drive-open-drain;
64			drive-strength = "0.5";
65			bias-pull-up;
66		};
67	};
68	i2c6_default: i2c6_default {
69		group1 {
70			pinmux = <M6SCL_P61>, <M6SDAWIR3_P62>;
71			drive-open-drain;
72			drive-strength = "0.5";
73			bias-pull-up;
74		};
75	};
76	i2c7_default: i2c7_default {
77		group1 {
78			pinmux = <M7SCL_P22>, <M7SDAWIR3_P23>;
79			drive-open-drain;
80			drive-strength = "0.5";
81			bias-pull-up;
82		};
83	};
84
85	spi0_default: spi0_default {
86		group1 {
87			pinmux = <M0SCK_P5>, <M0MISO_P7>, <M0MOSI_P6>;
88		};
89		group2 {
90			pinmux = <NCE72_P72>;
91			drive-push-pull;
92			ambiq,iom-nce-module = <0>;
93		};
94	};
95	spi1_default: spi1_default {
96		group1 {
97			pinmux = <M1SCK_P8>, <M1MISO_P10>, <M1MOSI_P9>;
98		};
99		group2 {
100			pinmux = <NCE11_P11>;
101			drive-strength = "0.5";
102			drive-push-pull;
103			ambiq,iom-nce-module = <4>;
104		};
105	};
106	spi2_default: spi2_default {
107		group1 {
108			pinmux = <M2SCK_P25>, <M2MISO_P27>, <M2MOSI_P26>;
109		};
110		group2 {
111			pinmux = <NCE37_P37>;
112			drive-push-pull;
113			ambiq,iom-nce-module = <8>;
114		};
115	};
116	spi3_default: spi3_default {
117		group1 {
118			pinmux = <M3SCK_P31>, <M3MISO_P33>, <M3MOSI_P32>;
119		};
120		group2 {
121			pinmux = <NCE85_P85>;
122			drive-push-pull;
123			ambiq,iom-nce-module = <12>;
124		};
125	};
126	spi4_default: spi4_default {
127		group1 {
128			pinmux = <M4SCK_P34>, <M4MISO_P36>, <M4MOSI_P35>;
129		};
130		group2 {
131			pinmux = <NCE79_P79>;
132			drive-push-pull;
133			ambiq,iom-nce-module = <16>;
134		};
135	};
136	spi5_default: spi5_default {
137		group1 {
138			pinmux = <M5SCK_P47>, <M5MISO_P49>, <M5MOSI_P48>;
139		};
140		group2 {
141			pinmux = <NCE60_P60>;
142			drive-push-pull;
143			ambiq,iom-nce-module = <20>;
144		};
145	};
146	spi6_default: spi6_default {
147		group1 {
148			pinmux = <M6SCK_P61>, <M6MISO_P63>, <M6MOSI_P62>;
149		};
150		group2 {
151			pinmux = <NCE30_P30>;
152			drive-push-pull;
153			ambiq,iom-nce-module = <24>;
154		};
155	};
156	spi7_default: spi7_default {
157		group1 {
158			pinmux = <M7SCK_P22>, <M7MISO_P24>, <M7MOSI_P23>;
159		};
160		group2 {
161			pinmux = <NCE88_P88>;
162			drive-push-pull;
163			ambiq,iom-nce-module = <28>;
164		};
165	};
166	mspi0_default: mspi0_default{
167		group1 {
168			pinmux = <MSPI0_0_P64>,
169				 <MSPI0_1_P65>,
170				 <MSPI0_8_P72>;
171		};
172		group2 {
173			pinmux = <NCE57_P57>;
174			drive-push-pull;
175			drive-strength = "0.5";
176			ambiq,iom-nce-module = <32>;
177		};
178	};
179	mspi1_default: mspi1_default{
180		group1 {
181			pinmux = <MSPI1_0_P37>,
182				 <MSPI1_1_P38>,
183				 <MSPI1_8_P45>;
184		};
185		group2 {
186			pinmux = <NCE56_P56>;
187			drive-push-pull;
188			drive-strength = "0.5";
189			ambiq,iom-nce-module = <34>;
190		};
191	};
192	mspi2_default: mspi2_default{
193		group1 {
194			pinmux = <MSPI2_0_P74>,
195				 <MSPI2_1_P75>,
196				 <MSPI2_8_P82>;
197		};
198		group2 {
199			pinmux = <NCE0_P0>;
200			drive-push-pull;
201			drive-strength = "0.5";
202			ambiq,iom-nce-module = <36>;
203		};
204	};
205};
206