1 /****************************************************************************** 2 * Filename: hw_ddi.h 3 * Revised: 2020-02-14 11:30:20 +0100 (Fri, 14 Feb 2020) 4 * Revision: 56760 5 * 6 * Copyright (c) 2015 - 2017, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_DDI_H__ 38 #define __HW_DDI_H__ 39 40 //***************************************************************************** 41 // 42 // This file contains macros for controlling the DDI master and 43 // accessing DDI Slave registers via the DDI Master. 44 // There are 3 categories of macros in this file: 45 // - macros that provide an offset to a register 46 // located within the DDI Master itself. 47 // - macros that define bits or bitfields 48 // within the DDI Master Registers. 49 // - macros that provide an "instruction offset" 50 // that are used when accessing a DDI Slave. 51 // 52 // The macros that that provide DDI Master register offsets and 53 // define bits and bitfields for those registers are the typical 54 // macros that appear in most hw_<module>.h header files. In 55 // the following example DDI_O_CFG is a macro for a 56 // register offset and DDI_CFG_WAITFORACK is a macro for 57 // a bit in that register. This example code will set the WAITFORACK 58 // bit in register DDI_O_CFG of the DDI Master. (Note: this 59 // access the Master not the Slave). 60 // 61 // HWREG(AUX_OSCDDI_BASE + DDI_O_CFG) |= DDI_CFG_WAITFORACK; 62 // 63 // 64 // The "instruction offset" macros are used to pass an instruction to 65 // the DDI Master when accessing DDI slave registers. These macros are 66 // only used when accessing DDI Slave Registers. (Remember DDI 67 // Master Registers are accessed normally). 68 // 69 // The instructions supported when accessing a DDI Slave Regsiter follow: 70 // - Direct Access to a DDI Slave register. I.e. read or 71 // write the register. 72 // - Set the specified bits in a DDI Slave register. 73 // - Clear the specified bits in a DDI Slave register. 74 // - Mask write of 4 bits to the a DDI Slave register. 75 // - Mask write of 8 bits to the a DDI Slave register. 76 // - Mask write of 16 bits to the a DDI Slave register. 77 // 78 // Note: only the "Direct Access" offset should be used when reading 79 // a DDI Slave register. Only 8- and 16-bit reads are supported. 80 // 81 // The generic format of using this marcos for a read follows: 82 // // read low 16-bits in DDI_SLAVE_OFF 83 // myushortvar = HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR); 84 // 85 // // read high 16-bits in DDI_SLAVE_OFF 86 // // add 2 for data[31:16] 87 // myushortvar = HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + 2 + DDI_O_DIR); 88 89 // // read data[31:24] byte in DDI_SLAVE_OFF 90 // // add 3 for data[31:24] 91 // myuchar = HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + 3 + DDI_O_DIR); 92 // 93 // Notes: In the above example: 94 // - DDI_MASTER_BASE is the base address of the DDI Master defined 95 // in the hw_memmap.h header file. 96 // - DDI_SLAVE_OFF is the DDI Slave offset defined in the 97 // hw_<ddi_slave>.h header file (e.g. hw_osc_top.h for the oscsc 98 // oscillator modules. 99 // - DDI_O_DIR is the "instruction offset" macro defined in this 100 // file that specifies the Direct Access instruction. 101 // 102 // Writes can use any of the "instruction macros". 103 // The following examples do a "direct write" to DDI Slave register 104 // DDI_SLAVE_OFF using different size operands: 105 // 106 // // ---------- DIRECT WRITES ---------- 107 // // Write 32-bits aligned 108 // HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR) = 0x12345678; 109 110 // // Write 16-bits aligned to high 16-bits then low 16-bits 111 // // Add 2 to get to high 16-bits. 112 // HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR + 2) = 0xabcd; 113 // HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR) = 0xef01; 114 // 115 // // Write each byte at DDI_SLAVE_OFF, one at a time. 116 // // Add 1,2,or 3 to get to bytes 1,2, or 3. 117 // HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR) = 0x33; 118 // HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR + 1) = 0x44; 119 // HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR + 2) = 0x55; 120 // HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR + 3) = 0x66; 121 // 122 // // ---------- SET/CLR ---------- 123 // The set and clear functions behave similarly to eachother. Each 124 // can be performed on an 8-, 16-, or 32-bit operand. 125 // Examples follow: 126 // // Set all odd bits in a 32-bit words 127 // HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_SET) = 0xaaaaaaaa; 128 // 129 // // Clear all bits in byte 2 (data[23:16]) using 32-bit operand 130 // HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_CLR) = 0x00ff0000; 131 // 132 // // Set even bits in byte 2 (data[23:16]) using 8-bit operand 133 // HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + 2 + DDI_O_CLR) = 0x55; 134 // 135 // // ---------- MASKED WRITES ---------- 136 // The mask writes are a bit different. They operate on nibbles, 137 // bytes, and 16-bit elements. Two operands are required; a 'mask' 138 // and 'data'; The operands are concatenated and written to the master. 139 // e.g. the mask and data are combined as follows for a 16 bit masked 140 // write: 141 // (mask << 16) | data; 142 // Examples follow: 143 // 144 // // Write 5555 to low 16-bits of DDI_SLAVE_OFF register 145 // // a long write is needed (32-bits). 146 // HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B) = 0xffff5555; 147 148 // // Write 1AA to data bits 24:16 in high 16-bits of DDI_SLAVE_OFF register 149 // // Note add 4 for high 16-bits at DDI_SLAVE_OFF; mask is 1ff! 150 // HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B + 4) = 0x01ff01aa; 151 // 152 // // Do an 8 bit masked write of 00 to low byte of register (data[7:0]). 153 // // a short write is needed (16-bits). 154 // HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B) = 0xff00; 155 // 156 // // Do an 8 bit masked write of 11 to byte 1 of register (data[15:8]). 157 // // add 2 to get to byte 1. 158 // HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B + 2) = 0xff11; 159 // 160 // // Do an 8 bit masked write of 33 to high byte of register (data[31:24]). 161 // // add 6 to get to byte 3. 162 // HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B + 6) = 0xff33; 163 // 164 // // Do an 4 bit masked write (Nibble) of 7 to data[3:0]). 165 // // Byte write is needed. 166 // HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B) = 0xf7; 167 // 168 // // Do an 4 bit masked write of 4 to data[7:4]). 169 // // Add 1 for next nibble 170 // HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B + 1) = 0xf4; 171 // 172 //***************************************************************************** 173 174 //***************************************************************************** 175 // 176 // The following are defines for the DDI master instruction offsets. 177 // 178 //***************************************************************************** 179 #define DDI_O_DIR 0x00000000 // Offset for the direct access instruction 180 #define DDI_O_SET 0x00000080 // Offset for 'Set' instruction. 181 #define DDI_O_CLR 0x00000100 // Offset for 'Clear' instruction. 182 #define DDI_O_MASK4B 0x00000200 // Offset for 4-bit masked access. 183 // Data bit[n] is written if mask bit[n] is set ('1'). 184 // Bits 7:4 are mask. Bits 3:0 are data. 185 // Requires 'byte' write. 186 #define DDI_O_MASK8B 0x00000300 // Offset for 8-bit masked access. 187 // Data bit[n] is written if mask bit[n] is set ('1'). 188 // Bits 15:8 are mask. Bits 7:0 are data. 189 // Requires 'short' write. 190 #define DDI_O_MASK16B 0x00000400 // Offset for 16-bit masked access. 191 // Data bit[n] is written if mask bit[n] is set ('1'). 192 // Bits 31:16 are mask. Bits 15:0 are data. 193 // Requires 'long' write. 194 195 196 197 #endif // __HW_DDI_H__ 198
