1 /*
2 * Copyright (c) 2018, NXP
3 *
4 * Forked off the spi_mcux_lpi2c driver.
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 */
8
9 #define DT_DRV_COMPAT openisa_rv32m1_lpspi
10
11 #include <errno.h>
12 #include <zephyr/drivers/spi.h>
13 #include <zephyr/drivers/clock_control.h>
14 #include <fsl_lpspi.h>
15 #include <zephyr/drivers/pinctrl.h>
16
17 #define LOG_LEVEL CONFIG_SPI_LOG_LEVEL
18 #include <zephyr/logging/log.h>
19 #include <zephyr/irq.h>
20 LOG_MODULE_REGISTER(spi_rv32m1_lpspi);
21
22 #include "spi_context.h"
23
24 #define CHIP_SELECT_COUNT 4
25 #define MAX_DATA_WIDTH 4096
26
27 struct spi_mcux_config {
28 LPSPI_Type *base;
29 const struct device *clock_dev;
30 clock_control_subsys_t clock_subsys;
31 clock_ip_name_t clock_ip_name;
32 uint32_t clock_ip_src;
33 void (*irq_config_func)(const struct device *dev);
34 const struct pinctrl_dev_config *pincfg;
35 };
36
37 struct spi_mcux_data {
38 const struct device *dev;
39 lpspi_master_handle_t handle;
40 struct spi_context ctx;
41 size_t transfer_len;
42 };
43
spi_mcux_transfer_next_packet(const struct device * dev)44 static void spi_mcux_transfer_next_packet(const struct device *dev)
45 {
46 const struct spi_mcux_config *config = dev->config;
47 struct spi_mcux_data *data = dev->data;
48 LPSPI_Type *base = config->base;
49 struct spi_context *ctx = &data->ctx;
50 lpspi_transfer_t transfer;
51 status_t status;
52
53 if ((ctx->tx_len == 0) && (ctx->rx_len == 0)) {
54 /* nothing left to rx or tx, we're done! */
55 spi_context_cs_control(&data->ctx, false);
56 spi_context_complete(&data->ctx, dev, 0);
57 return;
58 }
59
60 transfer.configFlags = kLPSPI_MasterPcsContinuous |
61 (ctx->config->slave << LPSPI_MASTER_PCS_SHIFT);
62
63 if (ctx->tx_len == 0) {
64 /* rx only, nothing to tx */
65 transfer.txData = NULL;
66 transfer.rxData = ctx->rx_buf;
67 transfer.dataSize = ctx->rx_len;
68 } else if (ctx->rx_len == 0) {
69 /* tx only, nothing to rx */
70 transfer.txData = (uint8_t *) ctx->tx_buf;
71 transfer.rxData = NULL;
72 transfer.dataSize = ctx->tx_len;
73 } else if (ctx->tx_len == ctx->rx_len) {
74 /* rx and tx are the same length */
75 transfer.txData = (uint8_t *) ctx->tx_buf;
76 transfer.rxData = ctx->rx_buf;
77 transfer.dataSize = ctx->tx_len;
78 } else if (ctx->tx_len > ctx->rx_len) {
79 /* Break up the tx into multiple transfers so we don't have to
80 * rx into a longer intermediate buffer. Leave chip select
81 * active between transfers.
82 */
83 transfer.txData = (uint8_t *) ctx->tx_buf;
84 transfer.rxData = ctx->rx_buf;
85 transfer.dataSize = ctx->rx_len;
86 transfer.configFlags |= kLPSPI_MasterPcsContinuous;
87 } else {
88 /* Break up the rx into multiple transfers so we don't have to
89 * tx from a longer intermediate buffer. Leave chip select
90 * active between transfers.
91 */
92 transfer.txData = (uint8_t *) ctx->tx_buf;
93 transfer.rxData = ctx->rx_buf;
94 transfer.dataSize = ctx->tx_len;
95 transfer.configFlags |= kLPSPI_MasterPcsContinuous;
96 }
97
98 if (!(ctx->tx_count <= 1 && ctx->rx_count <= 1)) {
99 transfer.configFlags |= kLPSPI_MasterPcsContinuous;
100 }
101
102 data->transfer_len = transfer.dataSize;
103 status = LPSPI_MasterTransferNonBlocking(base, &data->handle,
104 &transfer);
105 if (status != kStatus_Success) {
106 LOG_ERR("Transfer could not start");
107 }
108 }
109
spi_mcux_isr(const struct device * dev)110 static void spi_mcux_isr(const struct device *dev)
111 {
112 const struct spi_mcux_config *config = dev->config;
113 struct spi_mcux_data *data = dev->data;
114 LPSPI_Type *base = config->base;
115
116 LPSPI_MasterTransferHandleIRQ(base, &data->handle);
117 }
118
spi_mcux_master_transfer_callback(LPSPI_Type * base,lpspi_master_handle_t * handle,status_t status,void * userData)119 static void spi_mcux_master_transfer_callback(LPSPI_Type *base,
120 lpspi_master_handle_t *handle,
121 status_t status, void *userData)
122 {
123 struct spi_mcux_data *data = userData;
124
125 spi_context_update_tx(&data->ctx, 1, data->transfer_len);
126 spi_context_update_rx(&data->ctx, 1, data->transfer_len);
127
128 spi_mcux_transfer_next_packet(data->dev);
129 }
130
spi_mcux_configure(const struct device * dev,const struct spi_config * spi_cfg)131 static int spi_mcux_configure(const struct device *dev,
132 const struct spi_config *spi_cfg)
133 {
134 const struct spi_mcux_config *config = dev->config;
135 struct spi_mcux_data *data = dev->data;
136 LPSPI_Type *base = config->base;
137 lpspi_master_config_t master_config;
138 uint32_t clock_freq;
139 uint32_t word_size;
140
141 if (spi_context_configured(&data->ctx, spi_cfg)) {
142 /* This configuration is already in use */
143 return 0;
144 }
145
146 if (spi_cfg->operation & SPI_HALF_DUPLEX) {
147 LOG_ERR("Half-duplex not supported");
148 return -ENOTSUP;
149 }
150
151 LPSPI_MasterGetDefaultConfig(&master_config);
152
153 if (spi_cfg->slave > CHIP_SELECT_COUNT) {
154 LOG_ERR("Slave %d is greater than %d",
155 spi_cfg->slave,
156 CHIP_SELECT_COUNT);
157 return -EINVAL;
158 }
159
160 word_size = SPI_WORD_SIZE_GET(spi_cfg->operation);
161 if (word_size > MAX_DATA_WIDTH) {
162 LOG_ERR("Word size %d is greater than %d",
163 word_size, MAX_DATA_WIDTH);
164 return -EINVAL;
165 }
166
167 master_config.bitsPerFrame = word_size;
168
169 master_config.cpol =
170 (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPOL)
171 ? kLPSPI_ClockPolarityActiveLow
172 : kLPSPI_ClockPolarityActiveHigh;
173
174 master_config.cpha =
175 (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPHA)
176 ? kLPSPI_ClockPhaseSecondEdge
177 : kLPSPI_ClockPhaseFirstEdge;
178
179 master_config.direction =
180 (spi_cfg->operation & SPI_TRANSFER_LSB)
181 ? kLPSPI_LsbFirst
182 : kLPSPI_MsbFirst;
183
184 master_config.baudRate = spi_cfg->frequency;
185
186 if (!device_is_ready(config->clock_dev)) {
187 LOG_ERR("clock control device not ready");
188 return -ENODEV;
189 }
190
191 if (clock_control_get_rate(config->clock_dev, config->clock_subsys,
192 &clock_freq)) {
193 return -EINVAL;
194 }
195
196 LPSPI_MasterInit(base, &master_config, clock_freq);
197
198 LPSPI_MasterTransferCreateHandle(base, &data->handle,
199 spi_mcux_master_transfer_callback,
200 data);
201
202 LPSPI_SetDummyData(base, 0);
203
204 data->ctx.config = spi_cfg;
205
206 return 0;
207 }
208
transceive(const struct device * dev,const struct spi_config * spi_cfg,const struct spi_buf_set * tx_bufs,const struct spi_buf_set * rx_bufs,bool asynchronous,spi_callback_t cb,void * userdata)209 static int transceive(const struct device *dev,
210 const struct spi_config *spi_cfg,
211 const struct spi_buf_set *tx_bufs,
212 const struct spi_buf_set *rx_bufs,
213 bool asynchronous,
214 spi_callback_t cb,
215 void *userdata)
216 {
217 struct spi_mcux_data *data = dev->data;
218 int ret;
219
220 spi_context_lock(&data->ctx, asynchronous, cb, userdata, spi_cfg);
221
222 ret = spi_mcux_configure(dev, spi_cfg);
223 if (ret) {
224 goto out;
225 }
226
227 spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, 1);
228
229 spi_context_cs_control(&data->ctx, true);
230
231 spi_mcux_transfer_next_packet(dev);
232
233 ret = spi_context_wait_for_completion(&data->ctx);
234 out:
235 spi_context_release(&data->ctx, ret);
236
237 return ret;
238 }
239
spi_mcux_transceive(const struct device * dev,const struct spi_config * spi_cfg,const struct spi_buf_set * tx_bufs,const struct spi_buf_set * rx_bufs)240 static int spi_mcux_transceive(const struct device *dev,
241 const struct spi_config *spi_cfg,
242 const struct spi_buf_set *tx_bufs,
243 const struct spi_buf_set *rx_bufs)
244 {
245 return transceive(dev, spi_cfg, tx_bufs, rx_bufs, false, NULL, NULL);
246 }
247
248 #ifdef CONFIG_SPI_ASYNC
spi_mcux_transceive_async(const struct device * dev,const struct spi_config * spi_cfg,const struct spi_buf_set * tx_bufs,const struct spi_buf_set * rx_bufs,spi_callback_t cb,void * userdata)249 static int spi_mcux_transceive_async(const struct device *dev,
250 const struct spi_config *spi_cfg,
251 const struct spi_buf_set *tx_bufs,
252 const struct spi_buf_set *rx_bufs,
253 spi_callback_t cb,
254 void *userdata)
255 {
256 return transceive(dev, spi_cfg, tx_bufs, rx_bufs, true, cb, userdata);
257 }
258 #endif /* CONFIG_SPI_ASYNC */
259
spi_mcux_release(const struct device * dev,const struct spi_config * spi_cfg)260 static int spi_mcux_release(const struct device *dev,
261 const struct spi_config *spi_cfg)
262 {
263 struct spi_mcux_data *data = dev->data;
264
265 spi_context_unlock_unconditionally(&data->ctx);
266
267 return 0;
268 }
269
spi_mcux_init(const struct device * dev)270 static int spi_mcux_init(const struct device *dev)
271 {
272 int err;
273 const struct spi_mcux_config *config = dev->config;
274 struct spi_mcux_data *data = dev->data;
275
276 CLOCK_SetIpSrc(config->clock_ip_name, config->clock_ip_src);
277
278 config->irq_config_func(dev);
279
280 data->dev = dev;
281
282 err = spi_context_cs_configure_all(&data->ctx);
283 if (err < 0) {
284 return err;
285 }
286
287 err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
288 if (err != 0) {
289 return err;
290 }
291
292 spi_context_unlock_unconditionally(&data->ctx);
293
294 return 0;
295 }
296
297 static const struct spi_driver_api spi_mcux_driver_api = {
298 .transceive = spi_mcux_transceive,
299 #ifdef CONFIG_SPI_ASYNC
300 .transceive_async = spi_mcux_transceive_async,
301 #endif
302 .release = spi_mcux_release,
303 };
304
305 #define SPI_RV32M1_INIT(n) \
306 PINCTRL_DT_INST_DEFINE(n); \
307 \
308 static void spi_mcux_config_func_##n(const struct device *dev); \
309 \
310 static const struct spi_mcux_config spi_mcux_config_##n = { \
311 .base = (LPSPI_Type *) DT_INST_REG_ADDR(n), \
312 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
313 .clock_subsys = (clock_control_subsys_t) \
314 DT_INST_CLOCKS_CELL(n, name), \
315 .irq_config_func = spi_mcux_config_func_##n, \
316 .clock_ip_name = INST_DT_CLOCK_IP_NAME(n), \
317 .clock_ip_src = kCLOCK_IpSrcFircAsync, \
318 .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
319 }; \
320 \
321 static struct spi_mcux_data spi_mcux_data_##n = { \
322 SPI_CONTEXT_INIT_LOCK(spi_mcux_data_##n, ctx), \
323 SPI_CONTEXT_INIT_SYNC(spi_mcux_data_##n, ctx), \
324 SPI_CONTEXT_CS_GPIOS_INITIALIZE(DT_DRV_INST(n), ctx) \
325 }; \
326 \
327 DEVICE_DT_INST_DEFINE(n, &spi_mcux_init, NULL, \
328 &spi_mcux_data_##n, \
329 &spi_mcux_config_##n, \
330 POST_KERNEL, \
331 CONFIG_SPI_INIT_PRIORITY, \
332 &spi_mcux_driver_api); \
333 \
334 static void spi_mcux_config_func_##n(const struct device *dev) \
335 { \
336 IRQ_CONNECT(DT_INST_IRQN(n), \
337 0, \
338 spi_mcux_isr, DEVICE_DT_INST_GET(n), 0); \
339 irq_enable(DT_INST_IRQN(n)); \
340 }
341
342 DT_INST_FOREACH_STATUS_OKAY(SPI_RV32M1_INIT)
343
