1 /*
2 * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
3 * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution.
4 * Copyright 2016-2021 NXP. Not a Contribution.
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 *
8 * Licensed under the Apache License, Version 2.0 (the License); you may
9 * not use this file except in compliance with the License.
10 * You may obtain a copy of the License at
11 *
12 * http://www.apache.org/licenses/LICENSE-2.0
13 *
14 * Unless required by applicable law or agreed to in writing, software
15 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
16 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
17 * See the License for the specific language governing permissions and
18 * limitations under the License.
19 */
20
21 #include "fsl_i2c_cmsis.h"
22
23 /* Component ID definition, used by tools. */
24 #ifndef FSL_COMPONENT_ID
25 #define FSL_COMPONENT_ID "platform.drivers.i2c_cmsis"
26 #endif
27
28 #if ((defined(RTE_I2C0) && RTE_I2C0 && defined(I2C0)) || (defined(RTE_I2C1) && RTE_I2C1 && defined(I2C1)) || \
29 (defined(RTE_I2C2) && RTE_I2C2 && defined(I2C2)) || (defined(RTE_I2C3) && RTE_I2C3 && defined(I2C3)))
30
31 #define ARM_I2C_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR((2), (2))
32
33 /*
34 * ARMCC does not support split the data section automatically, so the driver
35 * needs to split the data to separate sections explicitly, to reduce codesize.
36 */
37 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
38 #define ARMCC_SECTION(section_name) __attribute__((section(section_name)))
39 #endif
40
41 typedef const struct _cmsis_i2c_resource
42 {
43 I2C_Type *base; /*!< I2C peripheral base address. */
44 uint32_t (*GetFreq)(void); /*!< Function to get the clock frequency. */
45
46 } cmsis_i2c_resource_t;
47
48 typedef union _cmsis_i2c_handle
49 {
50 i2c_master_handle_t master_handle; /*!< master Interupt transfer handle. */
51 i2c_slave_handle_t slave_handle; /*!< slave Interupt transfer handle. */
52 } cmsis_i2c_handle_t;
53
54 typedef struct _cmsis_i2c_interrupt_driver_state
55 {
56 cmsis_i2c_resource_t *resource; /*!< Basic I2C resource. */
57 cmsis_i2c_handle_t *handle;
58 ARM_I2C_SignalEvent_t cb_event; /*!< Callback function. */
59 uint8_t flags; /*!< Control and state flags. */
60 } cmsis_i2c_interrupt_driver_state_t;
61
62 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
63 typedef const struct _cmsis_i2c_dma_resource
64 {
65 DMA_Type *i2cDmaBase; /*!< DMA peripheral base address for i2c. */
66 uint32_t i2cDmaChannel; /*!< DMA channel for i2c. */
67 DMAMUX_Type *i2cDmamuxBase; /*!< DMAMUX peripheral base address for i2c. */
68 uint16_t i2cDmaRequest; /*!< i2c DMA request source. */
69
70 #if FSL_FEATURE_DMA_MODULE_CHANNEL != FSL_FEATURE_DMAMUX_MODULE_CHANNEL
71 uint32_t i2cDmamuxChannel; /*!< DMAMUX channel for i2c. */
72 #endif
73 } cmsis_i2c_dma_resource_t;
74
75 typedef struct _cmsis_i2c_dma_driver_state
76 {
77 cmsis_i2c_resource_t *resource; /*!< i2c basic resource. */
78 cmsis_i2c_dma_resource_t *dmaResource; /*!< i2c DMA resource. */
79 i2c_master_dma_handle_t *master_dma_handle; /*!< i2c DMA transfer handle. */
80 dma_handle_t *dmaHandle; /*!< DMA i2c handle. */
81 uint8_t flags; /*!< Control and state flags. */
82 } cmsis_i2c_dma_driver_state_t;
83 #endif
84
85 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
86 typedef const struct _cmsis_i2c_edma_resource
87 {
88 DMA_Type *i2cEdmaBase; /*!< EDMA peripheral base address for i2c. */
89 uint32_t i2cEdmaChannel; /*!< EDMA channel for i2c. */
90 DMAMUX_Type *i2cDmamuxBase; /*!< DMAMUX peripheral base address for i2c. */
91 uint16_t i2cDmaRequest; /*!< i2c EDMA request source. */
92 } cmsis_i2c_edma_resource_t;
93
94 typedef struct _cmsis_i2c_edma_driver_state
95 {
96 cmsis_i2c_resource_t *resource; /*!< i2c basic resource. */
97 cmsis_i2c_edma_resource_t *edmaResource; /*!< i2c EDMA resource. */
98 i2c_master_edma_handle_t *master_edma_handle; /*!< i2c EDMA transfer handle. */
99 edma_handle_t *edmaHandle; /*!< EDMA i2c handle. */
100 uint8_t flags; /*!< Control and state flags. */
101 } cmsis_i2c_edma_driver_state_t;
102 #endif /* FSL_FEATURE_SOC_EDMA_COUNT */
103
104 static const ARM_DRIVER_VERSION s_i2cDriverVersion = {ARM_I2C_API_VERSION, ARM_I2C_DRV_VERSION};
105 static const ARM_I2C_CAPABILITIES s_i2cDriverCapabilities = {
106 0, /*< supports 10-bit addressing */
107 };
108
109 static const clock_ip_name_t s_i2cClocks[] = I2C_CLOCKS;
110
I2Cx_GetVersion(void)111 static ARM_DRIVER_VERSION I2Cx_GetVersion(void)
112 {
113 return s_i2cDriverVersion;
114 }
115
I2Cx_GetCapabilities(void)116 static ARM_I2C_CAPABILITIES I2Cx_GetCapabilities(void)
117 {
118 return s_i2cDriverCapabilities;
119 }
120
121 #endif
122
123 #if ((defined(RTE_I2C0_DMA_EN) && RTE_I2C0_DMA_EN) || (defined(RTE_I2C1_DMA_EN) && RTE_I2C1_DMA_EN) || \
124 (defined(RTE_I2C2_DMA_EN) && RTE_I2C2_DMA_EN) || (defined(RTE_I2C3_DMA_EN) && RTE_I2C3_DMA_EN))
125
126 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
KSDK_I2C_MASTER_DmaCallback(I2C_Type * base,i2c_master_dma_handle_t * handle,status_t status,void * userData)127 static void KSDK_I2C_MASTER_DmaCallback(I2C_Type *base,
128 i2c_master_dma_handle_t *handle,
129 status_t status,
130 void *userData)
131 {
132 uint32_t event = 0;
133
134 if (status == kStatus_Success) /* Occurs after Master Transmit/Receive operation has finished. */
135 {
136 event = ARM_I2C_EVENT_TRANSFER_DONE;
137 }
138
139 if (status == kStatus_I2C_Addr_Nak)
140 {
141 event = ARM_I2C_EVENT_ADDRESS_NACK;
142 }
143
144 if (userData != NULL)
145 {
146 ((ARM_I2C_SignalEvent_t)userData)(event);
147 }
148 }
149
I2C_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event,cmsis_i2c_dma_driver_state_t * i2c)150 static int32_t I2C_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event, cmsis_i2c_dma_driver_state_t *i2c)
151 {
152 if (0U == (i2c->flags & (uint8_t)I2C_FLAG_INIT))
153 {
154 /* Configure DMAMUX channel */
155 #if FSL_FEATURE_DMA_MODULE_CHANNEL != FSL_FEATURE_DMAMUX_MODULE_CHANNEL
156 DMAMUX_SetSource(i2c->dmaResource->i2cDmamuxBase, i2c->dmaResource->i2cDmamuxChannel,
157 (int32_t)i2c->dmaResource->i2cDmaRequest);
158 DMAMUX_EnableChannel(i2c->dmaResource->i2cDmamuxBase, i2c->dmaResource->i2cDmamuxChannel);
159 #else
160 DMAMUX_SetSource(i2c->dmaResource->i2cDmamuxBase, i2c->dmaResource->i2cDmaChannel,
161 (int32_t)i2c->dmaResource->i2cDmaRequest);
162 DMAMUX_EnableChannel(i2c->dmaResource->i2cDmamuxBase, i2c->dmaResource->i2cDmaChannel);
163 #endif
164 /* Creat dmahandle */
165 DMA_CreateHandle(i2c->dmaHandle, i2c->dmaResource->i2cDmaBase, i2c->dmaResource->i2cDmaChannel);
166 /* Create master_dma_handle. */
167 I2C_MasterTransferCreateHandleDMA(i2c->resource->base, i2c->master_dma_handle, KSDK_I2C_MASTER_DmaCallback,
168 (void *)cb_event, i2c->dmaHandle);
169 i2c->flags = (uint8_t)I2C_FLAG_INIT;
170 }
171 return ARM_DRIVER_OK;
172 }
173
I2C_Master_DmaUninitialize(cmsis_i2c_dma_driver_state_t * i2c)174 static int32_t I2C_Master_DmaUninitialize(cmsis_i2c_dma_driver_state_t *i2c)
175 {
176 i2c->flags = (uint8_t)I2C_FLAG_UNINIT;
177 return ARM_DRIVER_OK;
178 }
179
I2C_Master_DmaTransmit(uint32_t addr,const uint8_t * data,uint32_t num,bool xfer_pending,cmsis_i2c_dma_driver_state_t * i2c)180 static int32_t I2C_Master_DmaTransmit(
181 uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending, cmsis_i2c_dma_driver_state_t *i2c)
182 {
183 int32_t status;
184 int32_t ret;
185 i2c_master_transfer_t masterXfer;
186
187 /* Check if the I2C bus is idle - if not return busy status. */
188 if (i2c->master_dma_handle->state != 0U)
189 {
190 return ARM_DRIVER_ERROR_BUSY;
191 }
192
193 masterXfer.slaveAddress = (uint8_t)addr; /*7-bit slave address.*/
194 masterXfer.direction = kI2C_Write; /* Transfer direction.*/
195 masterXfer.subaddress = 0U; /* Sub address */
196 masterXfer.subaddressSize = 0U; /* Size of command buffer.*/
197 masterXfer.data = (uint8_t *)data; /* Transfer buffer.*/
198 masterXfer.dataSize = num; /* Transfer size.*/
199 masterXfer.flags = (uint32_t)kI2C_TransferDefaultFlag; /* Transfer flag which controls the transfer.*/
200
201 if ((i2c->resource->base->S & 0x20U) != 0U)
202 {
203 masterXfer.flags |= (uint32_t)kI2C_TransferRepeatedStartFlag;
204 }
205
206 if (xfer_pending)
207 {
208 masterXfer.flags |= (uint32_t)kI2C_TransferNoStopFlag;
209 }
210
211 status = I2C_MasterTransferDMA(i2c->resource->base, i2c->master_dma_handle, &masterXfer);
212 switch (status)
213 {
214 case kStatus_Success:
215 ret = ARM_DRIVER_OK;
216 break;
217 case kStatus_I2C_Busy:
218 ret = ARM_DRIVER_ERROR_BUSY;
219 break;
220 case kStatus_I2C_Timeout:
221 ret = ARM_DRIVER_ERROR_TIMEOUT;
222 break;
223 default:
224 ret = ARM_DRIVER_ERROR;
225 break;
226 }
227
228 return ret;
229 }
230
I2C_Master_DmaReceive(uint32_t addr,uint8_t * data,uint32_t num,bool xfer_pending,cmsis_i2c_dma_driver_state_t * i2c)231 static int32_t I2C_Master_DmaReceive(
232 uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending, cmsis_i2c_dma_driver_state_t *i2c)
233 {
234 int32_t status;
235 int32_t ret;
236 i2c_master_transfer_t masterXfer;
237
238 /* Check if the I2C bus is idle - if not return busy status. */
239 if (i2c->master_dma_handle->state != 0U)
240 {
241 return ARM_DRIVER_ERROR_BUSY;
242 }
243
244 masterXfer.slaveAddress = (uint8_t)addr; /*7-bit slave address.*/
245 masterXfer.direction = kI2C_Read; /* Transfer direction.*/
246 masterXfer.subaddress = 0U; /* Sub address */
247 masterXfer.subaddressSize = 0U; /* Size of command buffer.*/
248 masterXfer.data = data; /* Transfer buffer.*/
249 masterXfer.dataSize = num; /* Transfer size.*/
250 masterXfer.flags = (uint32_t)kI2C_TransferDefaultFlag; /* Transfer flag which controls the transfer.*/
251
252 if ((i2c->resource->base->S & 0x20U) != 0U)
253 {
254 masterXfer.flags |= (uint32_t)kI2C_TransferRepeatedStartFlag;
255 }
256
257 if (xfer_pending)
258 {
259 masterXfer.flags |= (uint32_t)kI2C_TransferNoStopFlag;
260 }
261
262 status = I2C_MasterTransferDMA(i2c->resource->base, i2c->master_dma_handle, &masterXfer);
263 switch (status)
264 {
265 case kStatus_Success:
266 ret = ARM_DRIVER_OK;
267 break;
268 case kStatus_I2C_Busy:
269 ret = ARM_DRIVER_ERROR_BUSY;
270 break;
271 case kStatus_I2C_Timeout:
272 ret = ARM_DRIVER_ERROR_TIMEOUT;
273 break;
274 default:
275 ret = ARM_DRIVER_ERROR;
276 break;
277 }
278
279 return ret;
280 }
281
I2C_Master_DmaGetDataCount(cmsis_i2c_dma_driver_state_t * i2c)282 static int32_t I2C_Master_DmaGetDataCount(cmsis_i2c_dma_driver_state_t *i2c)
283 {
284 size_t cnt; /* The number of currently transferred data bytes */
285
286 (void)I2C_MasterTransferGetCountDMA(i2c->resource->base, i2c->master_dma_handle, &cnt);
287 return (int32_t)cnt;
288 }
289
I2C_Master_DmaControl(uint32_t control,uint32_t arg,cmsis_i2c_dma_driver_state_t * i2c)290 static int32_t I2C_Master_DmaControl(uint32_t control, uint32_t arg, cmsis_i2c_dma_driver_state_t *i2c)
291 {
292 uint32_t baudRate_Bps = 0;
293 volatile uint8_t dummy = 0;
294 int32_t result = ARM_DRIVER_OK;
295 /* Add this to avoid warning. */
296 dummy++;
297
298 switch (control)
299 {
300 /* Not supported */
301 case ARM_I2C_OWN_ADDRESS:
302 return ARM_DRIVER_ERROR_UNSUPPORTED;
303
304 /* Set Bus Speed; arg = bus speed */
305 case ARM_I2C_BUS_SPEED:
306 switch (arg)
307 {
308 case ARM_I2C_BUS_SPEED_STANDARD:
309 baudRate_Bps = 100000;
310 break;
311
312 case ARM_I2C_BUS_SPEED_FAST:
313 baudRate_Bps = 400000;
314 break;
315
316 case ARM_I2C_BUS_SPEED_FAST_PLUS:
317 baudRate_Bps = 1000000;
318 break;
319
320 default:
321 result = ARM_DRIVER_ERROR_UNSUPPORTED;
322 break;
323 }
324 if (result == ARM_DRIVER_OK)
325 {
326 I2C_MasterSetBaudRate(i2c->resource->base, baudRate_Bps, i2c->resource->GetFreq());
327 }
328 break;
329
330 /* Not supported */
331 case ARM_I2C_BUS_CLEAR:
332 result = ARM_DRIVER_ERROR_UNSUPPORTED;
333 break;
334
335 /* Aborts the data transfer when Master for Transmit or Receive */
336 case ARM_I2C_ABORT_TRANSFER:
337 if ((i2c->resource->base->C1 & (uint8_t)I2C_C1_MST_MASK) != 0U)
338 {
339 /* Disable dma */
340 I2C_MasterTransferAbortDMA(i2c->resource->base, i2c->master_dma_handle);
341 /* If master receive */
342 if (i2c->master_dma_handle->transfer.direction == kI2C_Read)
343 {
344 i2c->resource->base->C1 |= (uint8_t)I2C_C1_TXAK_MASK;
345 while (0U == (i2c->resource->base->S & I2C_S_TCF_MASK))
346 {
347 }
348 i2c->resource->base->C1 &=
349 ~((uint8_t)I2C_C1_MST_MASK | (uint8_t)I2C_C1_TX_MASK | (uint8_t)I2C_C1_TXAK_MASK);
350 dummy = i2c->resource->base->D;
351 }
352 /* If master transmit */
353 else
354 {
355 while (0U == (i2c->resource->base->S & (uint8_t)I2C_S_TCF_MASK))
356 {
357 }
358 i2c->resource->base->C1 &=
359 ~((uint8_t)I2C_C1_MST_MASK | (uint8_t)I2C_C1_TX_MASK | (uint8_t)I2C_C1_TXAK_MASK);
360 }
361
362 i2c->master_dma_handle->transferSize = 0;
363 i2c->master_dma_handle->transfer.data = NULL;
364 i2c->master_dma_handle->transfer.dataSize = 0;
365 }
366 break;
367
368 default:
369 result = ARM_DRIVER_ERROR_UNSUPPORTED;
370 break;
371 }
372 return result;
373 }
374
I2C_Master_DmaPowerControl(ARM_POWER_STATE state,cmsis_i2c_dma_driver_state_t * i2c)375 static int32_t I2C_Master_DmaPowerControl(ARM_POWER_STATE state, cmsis_i2c_dma_driver_state_t *i2c)
376 {
377 int32_t result = ARM_DRIVER_OK;
378 switch (state)
379 {
380 /* Terminates any pending data transfers, disable i2c moduole and i2c clock and related dma */
381 case ARM_POWER_OFF:
382 if ((i2c->flags & (uint8_t)I2C_FLAG_POWER) != 0U)
383 {
384 (void)I2C_Master_DmaControl(ARM_I2C_ABORT_TRANSFER, 0, i2c);
385 I2C_MasterDeinit(i2c->resource->base);
386 #if FSL_FEATURE_DMA_MODULE_CHANNEL != FSL_FEATURE_DMAMUX_MODULE_CHANNEL
387 DMAMUX_DisableChannel(i2c->dmaResource->i2cDmamuxBase, i2c->dmaResource->i2cDmamuxChannel);
388 #else
389 DMAMUX_DisableChannel(i2c->dmaResource->i2cDmamuxBase, i2c->dmaResource->i2cDmaChannel);
390 #endif
391 i2c->flags = (uint8_t)I2C_FLAG_INIT;
392 }
393 break;
394
395 /* Not supported */
396 case ARM_POWER_LOW:
397 result = ARM_DRIVER_ERROR_UNSUPPORTED;
398 break;
399
400 /* Enable i2c moduole and i2c clock */
401 case ARM_POWER_FULL:
402 if (i2c->flags == (uint8_t)I2C_FLAG_UNINIT)
403 {
404 return ARM_DRIVER_ERROR;
405 }
406
407 if ((i2c->flags & (uint8_t)I2C_FLAG_POWER) != 0U)
408 {
409 /* Driver already powered */
410 break;
411 }
412 CLOCK_EnableClock(s_i2cClocks[I2C_GetInstance(i2c->resource->base)]);
413 i2c->resource->base->C1 = I2C_C1_IICEN(1);
414 i2c->flags |= (uint8_t)I2C_FLAG_POWER;
415 break;
416
417 default:
418 result = ARM_DRIVER_ERROR_UNSUPPORTED;
419 break;
420 }
421
422 return result;
423 }
424
I2C_Master_DmaGetStatus(cmsis_i2c_dma_driver_state_t * i2c)425 static ARM_I2C_STATUS I2C_Master_DmaGetStatus(cmsis_i2c_dma_driver_state_t *i2c)
426 {
427 ARM_I2C_STATUS stat = {0};
428 uint32_t ksdk_i2c_master_status = I2C_MasterGetStatusFlags(i2c->resource->base);
429
430 stat.busy = (uint32_t)((ksdk_i2c_master_status & (uint32_t)kI2C_BusBusyFlag) != 0U); /* Busy flag.*/
431
432 stat.mode = 1UL; /* Mode: 0=Slave, 1=Master.*/
433
434 stat.direction = (uint32_t)((ksdk_i2c_master_status & (uint32_t)kI2C_TransferDirectionFlag) !=
435 0U); /* Direction: 0=Transmitter, 1=Receiver.*/
436
437 stat.arbitration_lost = (uint32_t)((ksdk_i2c_master_status & (uint32_t)kI2C_ArbitrationLostFlag) !=
438 0U); /* Master lost arbitration (cleared on start of next Master operation)*/
439
440 return stat;
441 }
442 #endif
443
444 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
KSDK_I2C_MASTER_EdmaCallback(I2C_Type * base,i2c_master_edma_handle_t * handle,status_t status,void * userData)445 static void KSDK_I2C_MASTER_EdmaCallback(I2C_Type *base,
446 i2c_master_edma_handle_t *handle,
447 status_t status,
448 void *userData)
449 {
450 uint32_t event = 0;
451
452 /* Occurs after Master Transmit/Receive operation has finished. */
453 if (status == kStatus_Success)
454 {
455 event = ARM_I2C_EVENT_TRANSFER_DONE;
456 }
457
458 if (status == kStatus_I2C_Addr_Nak)
459 {
460 event = ARM_I2C_EVENT_ADDRESS_NACK;
461 }
462
463 if (userData != NULL)
464 {
465 ((ARM_I2C_SignalEvent_t)userData)(event);
466 }
467 }
468
I2C_Master_EdmaInitialize(ARM_I2C_SignalEvent_t cb_event,cmsis_i2c_edma_driver_state_t * i2c)469 static int32_t I2C_Master_EdmaInitialize(ARM_I2C_SignalEvent_t cb_event, cmsis_i2c_edma_driver_state_t *i2c)
470 {
471 if (0U == (i2c->flags & (uint8_t)I2C_FLAG_INIT))
472 {
473 /* Configure DMAMUX channel */
474 DMAMUX_SetSource(i2c->edmaResource->i2cDmamuxBase, i2c->edmaResource->i2cEdmaChannel,
475 (int32_t)i2c->edmaResource->i2cDmaRequest);
476 DMAMUX_EnableChannel(i2c->edmaResource->i2cDmamuxBase, i2c->edmaResource->i2cEdmaChannel);
477 /* Creat edmahandle */
478 EDMA_CreateHandle(i2c->edmaHandle, i2c->edmaResource->i2cEdmaBase, i2c->edmaResource->i2cEdmaChannel);
479 /* Create master_edma_handle. */
480 I2C_MasterCreateEDMAHandle(i2c->resource->base, i2c->master_edma_handle, KSDK_I2C_MASTER_EdmaCallback,
481 (void *)cb_event, i2c->edmaHandle);
482 i2c->flags = (uint8_t)I2C_FLAG_INIT;
483 }
484 return ARM_DRIVER_OK;
485 }
486
I2C_Master_EdmaUninitialize(cmsis_i2c_edma_driver_state_t * i2c)487 static int32_t I2C_Master_EdmaUninitialize(cmsis_i2c_edma_driver_state_t *i2c)
488 {
489 i2c->flags = (uint8_t)I2C_FLAG_UNINIT;
490 return ARM_DRIVER_OK;
491 }
492
I2C_Master_EdmaTransmit(uint32_t addr,const uint8_t * data,uint32_t num,bool xfer_pending,cmsis_i2c_edma_driver_state_t * i2c)493 static int32_t I2C_Master_EdmaTransmit(
494 uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending, cmsis_i2c_edma_driver_state_t *i2c)
495 {
496 int32_t status;
497 int32_t ret;
498 i2c_master_transfer_t masterXfer;
499
500 /* Check if the I2C bus is idle - if not return busy status. */
501 if (i2c->master_edma_handle->state != 0U)
502 {
503 return ARM_DRIVER_ERROR_BUSY;
504 }
505
506 masterXfer.slaveAddress = (uint8_t)addr; /*7-bit slave address.*/
507 masterXfer.direction = kI2C_Write; /* Transfer direction.*/
508 masterXfer.subaddress = 0U; /* Sub address */
509 masterXfer.subaddressSize = 0U; /* Size of command buffer.*/
510 masterXfer.data = (uint8_t *)data; /* Transfer buffer.*/
511 masterXfer.dataSize = num; /* Transfer size.*/
512 masterXfer.flags = (uint32_t)kI2C_TransferDefaultFlag; /* Transfer flag which controls the transfer.*/
513
514 if ((i2c->resource->base->S & 0x20U) != 0U)
515 {
516 masterXfer.flags |= (uint32_t)kI2C_TransferRepeatedStartFlag;
517 }
518
519 if (xfer_pending)
520 {
521 masterXfer.flags |= (uint32_t)kI2C_TransferNoStopFlag;
522 }
523
524 status = I2C_MasterTransferEDMA(i2c->resource->base, i2c->master_edma_handle, &masterXfer);
525 switch (status)
526 {
527 case kStatus_Success:
528 ret = ARM_DRIVER_OK;
529 break;
530 case kStatus_I2C_Busy:
531 ret = ARM_DRIVER_ERROR_BUSY;
532 break;
533 case kStatus_I2C_Timeout:
534 ret = ARM_DRIVER_ERROR_TIMEOUT;
535 break;
536 default:
537 ret = ARM_DRIVER_ERROR;
538 break;
539 }
540
541 return ret;
542 }
543
I2C_Master_EdmaReceive(uint32_t addr,uint8_t * data,uint32_t num,bool xfer_pending,cmsis_i2c_edma_driver_state_t * i2c)544 static int32_t I2C_Master_EdmaReceive(
545 uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending, cmsis_i2c_edma_driver_state_t *i2c)
546 {
547 int32_t status;
548 int32_t ret;
549 i2c_master_transfer_t masterXfer;
550
551 /* Check if the I2C bus is idle - if not return busy status. */
552 if (i2c->master_edma_handle->state != 0U)
553 {
554 return ARM_DRIVER_ERROR_BUSY;
555 }
556
557 masterXfer.slaveAddress = (uint8_t)addr; /* 7-bit slave address.*/
558 masterXfer.direction = kI2C_Read; /* Transfer direction.*/
559 masterXfer.subaddress = 0U; /* Sub address */
560 masterXfer.subaddressSize = 0U; /* Size of command buffer.*/
561 masterXfer.data = data; /* Transfer buffer.*/
562 masterXfer.dataSize = num; /* Transfer size.*/
563 masterXfer.flags = (uint32_t)kI2C_TransferDefaultFlag; /* Transfer flag which controls the transfer.*/
564
565 if ((i2c->resource->base->S & 0x20U) != 0U)
566 {
567 masterXfer.flags |= (uint32_t)kI2C_TransferRepeatedStartFlag;
568 }
569
570 if (xfer_pending)
571 {
572 masterXfer.flags |= (uint32_t)kI2C_TransferNoStopFlag;
573 }
574
575 status = I2C_MasterTransferEDMA(i2c->resource->base, i2c->master_edma_handle, &masterXfer);
576
577 switch (status)
578 {
579 case kStatus_Success:
580 ret = ARM_DRIVER_OK;
581 break;
582
583 case kStatus_I2C_Busy:
584 ret = ARM_DRIVER_ERROR_BUSY;
585 break;
586
587 case kStatus_I2C_Timeout:
588 ret = ARM_DRIVER_ERROR_TIMEOUT;
589 break;
590
591 default:
592 ret = ARM_DRIVER_ERROR;
593 break;
594 }
595
596 return ret;
597 }
598
I2C_Master_EdmaGetDataCount(cmsis_i2c_edma_driver_state_t * i2c)599 static int32_t I2C_Master_EdmaGetDataCount(cmsis_i2c_edma_driver_state_t *i2c)
600 {
601 size_t cnt; /* The number of currently transferred data bytes */
602
603 (void)I2C_MasterTransferGetCountEDMA(i2c->resource->base, i2c->master_edma_handle, &cnt);
604
605 return (int32_t)cnt;
606 }
607
I2C_Master_EdmaControl(uint32_t control,uint32_t arg,cmsis_i2c_edma_driver_state_t * i2c)608 static int32_t I2C_Master_EdmaControl(uint32_t control, uint32_t arg, cmsis_i2c_edma_driver_state_t *i2c)
609 {
610 uint32_t baudRate_Bps = 0;
611 volatile uint8_t dummy = 0;
612 int32_t result = ARM_DRIVER_OK;
613 /* Add this to avoid warning. */
614 dummy++;
615
616 switch (control)
617 {
618 /* Not supported */
619 case ARM_I2C_OWN_ADDRESS:
620 result = ARM_DRIVER_ERROR_UNSUPPORTED;
621 break;
622
623 /* Set Bus Speed; arg = bus speed */
624 case ARM_I2C_BUS_SPEED:
625 switch (arg)
626 {
627 case ARM_I2C_BUS_SPEED_STANDARD:
628 baudRate_Bps = 100000;
629 break;
630
631 case ARM_I2C_BUS_SPEED_FAST:
632 baudRate_Bps = 400000;
633 break;
634
635 case ARM_I2C_BUS_SPEED_FAST_PLUS:
636 baudRate_Bps = 1000000;
637 break;
638
639 default:
640 result = ARM_DRIVER_ERROR_UNSUPPORTED;
641 break;
642 }
643 if (result == ARM_DRIVER_OK)
644 {
645 I2C_MasterSetBaudRate(i2c->resource->base, baudRate_Bps, (i2c->resource->GetFreq)());
646 }
647
648 break;
649 /* Not supported */
650 case ARM_I2C_BUS_CLEAR:
651 result = ARM_DRIVER_ERROR_UNSUPPORTED;
652 break;
653
654 /* Aborts the data transfer when Master for Transmit or Receive */
655 case ARM_I2C_ABORT_TRANSFER:
656
657 if ((i2c->resource->base->C1 & (uint8_t)I2C_C1_MST_MASK) != 0U)
658 {
659 /* Disable edma */
660 I2C_MasterTransferAbortEDMA(i2c->resource->base, i2c->master_edma_handle);
661 /* If master receive */
662 if (i2c->master_edma_handle->transfer.direction == kI2C_Read)
663 {
664 i2c->resource->base->C1 |= (uint8_t)I2C_C1_TXAK_MASK;
665 while (0U == (i2c->resource->base->S & (uint8_t)I2C_S_TCF_MASK))
666 {
667 }
668 i2c->resource->base->C1 &=
669 ~((uint8_t)I2C_C1_MST_MASK | (uint8_t)I2C_C1_TX_MASK | (uint8_t)I2C_C1_TXAK_MASK);
670 dummy = i2c->resource->base->D;
671 }
672 /* If master transmit */
673 else
674 {
675 while (0U == (i2c->resource->base->S & (uint8_t)I2C_S_TCF_MASK))
676 {
677 }
678 i2c->resource->base->C1 &=
679 ~((uint8_t)I2C_C1_MST_MASK | (uint8_t)I2C_C1_TX_MASK | (uint8_t)I2C_C1_TXAK_MASK);
680 }
681
682 i2c->master_edma_handle->transferSize = 0;
683 i2c->master_edma_handle->transfer.data = NULL;
684 i2c->master_edma_handle->transfer.dataSize = 0;
685 }
686 break;
687 default:
688 result = ARM_DRIVER_ERROR_UNSUPPORTED;
689 break;
690 }
691 return result;
692 }
693
I2C_Master_EdmaPowerControl(ARM_POWER_STATE state,cmsis_i2c_edma_driver_state_t * i2c)694 static int32_t I2C_Master_EdmaPowerControl(ARM_POWER_STATE state, cmsis_i2c_edma_driver_state_t *i2c)
695 {
696 int32_t result = ARM_DRIVER_OK;
697 switch (state)
698 {
699 /* Terminates any pending data transfers, disable i2c moduole and i2c clock and related edma */
700 case ARM_POWER_OFF:
701 if ((i2c->flags & (uint8_t)I2C_FLAG_POWER) != 0U)
702 {
703 (void)I2C_Master_EdmaControl(ARM_I2C_ABORT_TRANSFER, 0, i2c);
704 I2C_MasterDeinit(i2c->resource->base);
705 DMAMUX_DisableChannel(i2c->edmaResource->i2cDmamuxBase, i2c->edmaResource->i2cEdmaChannel);
706 i2c->flags = (uint8_t)I2C_FLAG_INIT;
707 }
708 break;
709 /* Not supported */
710 case ARM_POWER_LOW:
711 result = ARM_DRIVER_ERROR_UNSUPPORTED;
712 break;
713 /* Enable i2c moduole and i2c clock */
714 case ARM_POWER_FULL:
715 if (i2c->flags == (uint8_t)I2C_FLAG_UNINIT)
716 {
717 return ARM_DRIVER_ERROR;
718 }
719
720 if ((i2c->flags & (uint8_t)I2C_FLAG_POWER) != 0U)
721 {
722 /* Driver already powered */
723 break;
724 }
725
726 CLOCK_EnableClock(s_i2cClocks[I2C_GetInstance(i2c->resource->base)]);
727 i2c->resource->base->C1 = I2C_C1_IICEN(1);
728 i2c->flags |= (uint8_t)I2C_FLAG_POWER;
729 break;
730 default:
731 result = ARM_DRIVER_ERROR_UNSUPPORTED;
732 break;
733 }
734
735 return result;
736 }
737
I2C_Master_EdmaGetStatus(cmsis_i2c_edma_driver_state_t * i2c)738 static ARM_I2C_STATUS I2C_Master_EdmaGetStatus(cmsis_i2c_edma_driver_state_t *i2c)
739 {
740 ARM_I2C_STATUS stat = {0};
741 uint32_t ksdk_i2c_master_status = I2C_MasterGetStatusFlags(i2c->resource->base);
742
743 stat.busy = (uint32_t)((ksdk_i2c_master_status & (uint32_t)kI2C_BusBusyFlag) != 0U); /* Busy flag.*/
744
745 stat.mode = 1UL; /* Mode: 0=Slave, 1=Master.*/
746
747 stat.direction = (uint32_t)((ksdk_i2c_master_status & (uint32_t)kI2C_TransferDirectionFlag) !=
748 0U); /* Direction: 0=Transmitter, 1=Receiver.*/
749
750 stat.arbitration_lost = (uint32_t)((ksdk_i2c_master_status & (uint32_t)kI2C_ArbitrationLostFlag) !=
751 0U); /* Master lost arbitration (cleared on start of next Master operation)*/
752
753 return stat;
754 }
755 #endif
756
757 #endif
758
759 #if ((defined(RTE_I2C0) && RTE_I2C0 && !(defined(RTE_I2C0_DMA_EN) && RTE_I2C0_DMA_EN)) || \
760 (defined(RTE_I2C1) && RTE_I2C1 && !(defined(RTE_I2C1_DMA_EN) && RTE_I2C1_DMA_EN)) || \
761 (defined(RTE_I2C2) && RTE_I2C2 && !(defined(RTE_I2C2_DMA_EN) && RTE_I2C2_DMA_EN)) || \
762 (defined(RTE_I2C3) && RTE_I2C3 && !(defined(RTE_I2C3_DMA_EN) && RTE_I2C3_DMA_EN)))
763
KSDK_I2C_SLAVE_InterruptCallback(I2C_Type * base,i2c_slave_transfer_t * xfer,void * userData)764 static void KSDK_I2C_SLAVE_InterruptCallback(I2C_Type *base, i2c_slave_transfer_t *xfer, void *userData)
765 {
766 uint32_t event = 0;
767
768 switch (xfer->event)
769 {
770 case kI2C_SlaveCompletionEvent: /* Occurs after Slave Transmit/Receive operation has finished. */
771 event = ARM_I2C_EVENT_TRANSFER_DONE;
772 break;
773
774 case kI2C_SlaveGenaralcallEvent:
775 event = ARM_I2C_EVENT_GENERAL_CALL;
776 break;
777
778 default:
779 event = ARM_I2C_EVENT_TRANSFER_INCOMPLETE;
780 break;
781 }
782
783 if (userData != NULL)
784 {
785 ((ARM_I2C_SignalEvent_t)userData)(event);
786 }
787 }
788
KSDK_I2C_MASTER_InterruptCallback(I2C_Type * base,i2c_master_handle_t * handle,status_t status,void * userData)789 static void KSDK_I2C_MASTER_InterruptCallback(I2C_Type *base,
790 i2c_master_handle_t *handle,
791 status_t status,
792 void *userData)
793 {
794 uint32_t event = 0;
795
796 switch (status)
797 {
798 case kStatus_Success: /* Occurs after Master Transmit/Receive operation has finished. */
799 event = ARM_I2C_EVENT_TRANSFER_DONE;
800 break;
801
802 case kStatus_I2C_Addr_Nak: /* Occurs in master mode when address is not acknowledged from slave.*/
803 event = ARM_I2C_EVENT_ADDRESS_NACK;
804 break;
805
806 case kStatus_I2C_ArbitrationLost: /* Occurs in master mode when arbitration is lost.*/
807 event = ARM_I2C_EVENT_ARBITRATION_LOST;
808 break;
809
810 default:
811 event = ARM_I2C_EVENT_TRANSFER_INCOMPLETE;
812 break;
813 }
814
815 /* User data is actually CMSIS driver callback. */
816 if (userData != NULL)
817 {
818 ((ARM_I2C_SignalEvent_t)userData)(event);
819 }
820 }
821
I2C_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event,cmsis_i2c_interrupt_driver_state_t * i2c)822 static int32_t I2C_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event, cmsis_i2c_interrupt_driver_state_t *i2c)
823 {
824 if (0U == (i2c->flags & (uint8_t)I2C_FLAG_INIT))
825 {
826 i2c->cb_event = cb_event; /* cb_event is CMSIS driver callback. */
827 i2c->flags = (uint8_t)I2C_FLAG_INIT;
828 }
829
830 return ARM_DRIVER_OK;
831 }
832
I2C_InterruptUninitialize(cmsis_i2c_interrupt_driver_state_t * i2c)833 static int32_t I2C_InterruptUninitialize(cmsis_i2c_interrupt_driver_state_t *i2c)
834 {
835 i2c->flags = (uint8_t)I2C_FLAG_UNINIT;
836 return ARM_DRIVER_OK;
837 }
838
I2C_Master_InterruptTransmit(uint32_t addr,const uint8_t * data,uint32_t num,bool xfer_pending,cmsis_i2c_interrupt_driver_state_t * i2c)839 static int32_t I2C_Master_InterruptTransmit(
840 uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending, cmsis_i2c_interrupt_driver_state_t *i2c)
841 {
842 int32_t status;
843 int32_t ret;
844 i2c_master_transfer_t masterXfer;
845
846 /* Check if the I2C bus is idle - if not return busy status. */
847 if (i2c->handle->master_handle.state != 0U)
848 {
849 return ARM_DRIVER_ERROR_BUSY;
850 }
851
852 /* Create master_handle */
853 I2C_MasterTransferCreateHandle(i2c->resource->base, &(i2c->handle->master_handle),
854 KSDK_I2C_MASTER_InterruptCallback, (void *)i2c->cb_event);
855
856 masterXfer.slaveAddress = (uint8_t)addr; /*7-bit slave address.*/
857 masterXfer.direction = kI2C_Write; /* Transfer direction.*/
858 masterXfer.subaddress = 0U; /* Sub address */
859 masterXfer.subaddressSize = 0U; /* Size of command buffer.*/
860 masterXfer.data = (uint8_t *)data; /* Transfer buffer.*/
861 masterXfer.dataSize = num; /* Transfer size.*/
862 masterXfer.flags = (uint32_t)kI2C_TransferDefaultFlag; /* Transfer flag which controls the transfer.*/
863
864 if ((i2c->resource->base->S & 0x20U) != 0U)
865 {
866 masterXfer.flags |= (uint32_t)kI2C_TransferRepeatedStartFlag;
867 }
868
869 if (xfer_pending)
870 {
871 masterXfer.flags |= (uint32_t)kI2C_TransferNoStopFlag;
872 }
873
874 status = I2C_MasterTransferNonBlocking(i2c->resource->base, &(i2c->handle->master_handle), &masterXfer);
875
876 switch (status)
877 {
878 case kStatus_Success:
879 ret = ARM_DRIVER_OK;
880 break;
881
882 case kStatus_I2C_Busy:
883 ret = ARM_DRIVER_ERROR_BUSY;
884 break;
885
886 case kStatus_I2C_Timeout:
887 ret = ARM_DRIVER_ERROR_TIMEOUT;
888 break;
889
890 default:
891 ret = ARM_DRIVER_ERROR;
892 break;
893 }
894
895 return ret;
896 }
897
I2C_Master_InterruptReceive(uint32_t addr,uint8_t * data,uint32_t num,bool xfer_pending,cmsis_i2c_interrupt_driver_state_t * i2c)898 static int32_t I2C_Master_InterruptReceive(
899 uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending, cmsis_i2c_interrupt_driver_state_t *i2c)
900 {
901 int32_t status;
902 int32_t ret;
903 i2c_master_transfer_t masterXfer;
904
905 /* Check if the I2C bus is idle - if not return busy status. */
906 if (i2c->handle->master_handle.state != 0U)
907 {
908 return ARM_DRIVER_ERROR_BUSY;
909 }
910
911 /* Create master_handle */
912 I2C_MasterTransferCreateHandle(i2c->resource->base, &(i2c->handle->master_handle),
913 KSDK_I2C_MASTER_InterruptCallback, (void *)i2c->cb_event);
914
915 masterXfer.slaveAddress = (uint8_t)addr; /*7-bit slave address.*/
916 masterXfer.direction = kI2C_Read; /* Transfer direction.*/
917 masterXfer.subaddress = 0U; /* Sub address */
918 masterXfer.subaddressSize = 0U; /* Size of command buffer.*/
919 masterXfer.data = data; /* Transfer buffer.*/
920 masterXfer.dataSize = num; /* Transfer size.*/
921 masterXfer.flags = (uint32_t)kI2C_TransferDefaultFlag; /* Transfer flag which controls the transfer.*/
922
923 if ((i2c->resource->base->S & 0x20U) != 0U)
924 {
925 masterXfer.flags |= (uint32_t)kI2C_TransferRepeatedStartFlag;
926 }
927
928 if (xfer_pending)
929 {
930 masterXfer.flags |= (uint32_t)kI2C_TransferNoStopFlag;
931 }
932
933 status = I2C_MasterTransferNonBlocking(i2c->resource->base, &(i2c->handle->master_handle), &masterXfer);
934
935 switch (status)
936 {
937 case kStatus_Success:
938 ret = ARM_DRIVER_OK;
939 break;
940
941 case kStatus_I2C_Busy:
942 ret = ARM_DRIVER_ERROR_BUSY;
943 break;
944
945 case kStatus_I2C_Timeout:
946 ret = ARM_DRIVER_ERROR_TIMEOUT;
947 break;
948
949 default:
950 ret = ARM_DRIVER_ERROR;
951 break;
952 }
953
954 return ret;
955 }
956
I2C_Slave_InterruptTransmit(const uint8_t * data,uint32_t num,cmsis_i2c_interrupt_driver_state_t * i2c)957 static int32_t I2C_Slave_InterruptTransmit(const uint8_t *data, uint32_t num, cmsis_i2c_interrupt_driver_state_t *i2c)
958 {
959 int32_t status;
960 int32_t ret;
961
962 /* Create slave_handle */
963 I2C_SlaveTransferCreateHandle(i2c->resource->base, &(i2c->handle->slave_handle), KSDK_I2C_SLAVE_InterruptCallback,
964 (void *)i2c->cb_event);
965
966 status = I2C_SlaveTransferNonBlocking(i2c->resource->base, &(i2c->handle->slave_handle),
967 (uint32_t)kI2C_SlaveCompletionEvent);
968
969 i2c->handle->slave_handle.transfer.data =
970 (uint8_t *)data; /* Pointer to buffer with data to transmit to I2C Master */
971 i2c->handle->slave_handle.transfer.dataSize = num; /* Number of data bytes to transmit */
972 i2c->handle->slave_handle.transfer.transferredCount =
973 0; /* Number of bytes actually transferred since start or last repeated start. */
974
975 switch (status)
976 {
977 case kStatus_Success:
978 ret = ARM_DRIVER_OK;
979 break;
980
981 case kStatus_I2C_Busy:
982 ret = ARM_DRIVER_ERROR_BUSY;
983 break;
984
985 default:
986 ret = ARM_DRIVER_ERROR;
987 break;
988 }
989
990 return ret;
991 }
992
I2C_Slave_InterruptReceive(uint8_t * data,uint32_t num,cmsis_i2c_interrupt_driver_state_t * i2c)993 static int32_t I2C_Slave_InterruptReceive(uint8_t *data, uint32_t num, cmsis_i2c_interrupt_driver_state_t *i2c)
994 {
995 int32_t status;
996 int32_t ret;
997
998 i2c->resource->base->C2 = I2C_C2_GCAEN(1); /* Enable general call */
999
1000 /* Create slave_handle */
1001 I2C_SlaveTransferCreateHandle(i2c->resource->base, &(i2c->handle->slave_handle), KSDK_I2C_SLAVE_InterruptCallback,
1002 (void *)i2c->cb_event);
1003
1004 status = I2C_SlaveTransferNonBlocking(i2c->resource->base, &(i2c->handle->slave_handle),
1005 (uint32_t)kI2C_SlaveCompletionEvent);
1006
1007 i2c->handle->slave_handle.transfer.data = data; /* Pointer to buffer with data to transmit to I2C Master */
1008 i2c->handle->slave_handle.transfer.dataSize = num; /* Number of data bytes to transmit */
1009 i2c->handle->slave_handle.transfer.transferredCount =
1010 0; /* Number of bytes actually transferred since start or last repeated start. */
1011
1012 switch (status)
1013 {
1014 case kStatus_Success:
1015 ret = ARM_DRIVER_OK;
1016 break;
1017
1018 case kStatus_I2C_Busy:
1019 ret = ARM_DRIVER_ERROR_BUSY;
1020 break;
1021
1022 default:
1023 ret = ARM_DRIVER_ERROR;
1024 break;
1025 }
1026
1027 return ret;
1028 }
1029
I2C_InterruptGetDataCount(cmsis_i2c_interrupt_driver_state_t * i2c)1030 static int32_t I2C_InterruptGetDataCount(cmsis_i2c_interrupt_driver_state_t *i2c)
1031 {
1032 uint32_t cnt; /* The number of currently transferred data bytes */
1033
1034 if ((i2c->handle->slave_handle.transfer.transferredCount) != 0U)
1035 {
1036 cnt = i2c->handle->slave_handle.transfer.transferredCount;
1037 }
1038 else
1039 {
1040 cnt = (uint32_t) & (i2c->handle->master_handle).transferSize - (uint32_t) &
1041 (i2c->handle->master_handle).transfer.dataSize;
1042 }
1043
1044 return (int32_t)cnt;
1045 }
1046
I2C_InterruptControl(uint32_t control,uint32_t arg,cmsis_i2c_interrupt_driver_state_t * i2c)1047 static int32_t I2C_InterruptControl(uint32_t control, uint32_t arg, cmsis_i2c_interrupt_driver_state_t *i2c)
1048 {
1049 uint32_t baudRate_Bps = 0;
1050 int32_t result = ARM_DRIVER_OK;
1051 switch (control)
1052 {
1053 /* Set Own Slave Address; arg = slave address */
1054 case ARM_I2C_OWN_ADDRESS:
1055 i2c->resource->base->A1 = (uint8_t)(arg << 1U);
1056 break;
1057 /* Set Bus Speed; arg = bus speed */
1058 case ARM_I2C_BUS_SPEED:
1059 switch (arg)
1060 {
1061 case ARM_I2C_BUS_SPEED_STANDARD:
1062 baudRate_Bps = 100000;
1063 break;
1064
1065 case ARM_I2C_BUS_SPEED_FAST:
1066 baudRate_Bps = 400000;
1067 break;
1068
1069 case ARM_I2C_BUS_SPEED_FAST_PLUS:
1070 baudRate_Bps = 1000000;
1071 break;
1072
1073 default:
1074 result = ARM_DRIVER_ERROR_UNSUPPORTED;
1075 break;
1076 }
1077 if (result == ARM_DRIVER_OK)
1078 {
1079 I2C_MasterSetBaudRate(i2c->resource->base, baudRate_Bps, i2c->resource->GetFreq());
1080 }
1081 break;
1082 /* Not supported */
1083 case ARM_I2C_BUS_CLEAR:
1084 result = ARM_DRIVER_ERROR_UNSUPPORTED;
1085 break;
1086
1087 /* Aborts the data transfer between Master and Slave for Transmit or Receive */
1088 case ARM_I2C_ABORT_TRANSFER:
1089 if ((i2c->resource->base->C1 & (uint8_t)I2C_C1_MST_MASK) != 0U)
1090 {
1091 /* Disable master interrupt and send STOP signal */
1092 (void)I2C_MasterTransferAbort(i2c->resource->base, &(i2c->handle->master_handle));
1093
1094 i2c->handle->master_handle.transferSize = 0;
1095 i2c->handle->master_handle.transfer.data = NULL;
1096 i2c->handle->master_handle.transfer.dataSize = 0;
1097 }
1098 /* If slave receive */
1099 else if (0U == (i2c->resource->base->S & (uint32_t)kI2C_TransferDirectionFlag))
1100 {
1101 i2c->resource->base->C1 |= (uint8_t)I2C_C1_TXAK_MASK;
1102
1103 while (i2c->handle->slave_handle.isBusy)
1104 {
1105 }
1106 /* Disable slave interrupt */
1107
1108 I2C_SlaveTransferAbort(i2c->resource->base, &(i2c->handle->slave_handle));
1109
1110 i2c->handle->slave_handle.transfer.data = NULL;
1111 i2c->handle->slave_handle.transfer.dataSize = 0;
1112 }
1113 else
1114 {
1115 ; /* Intentional empty */
1116 }
1117 break;
1118 default:
1119 result = ARM_DRIVER_ERROR_UNSUPPORTED;
1120 break;
1121 }
1122 return result;
1123 }
1124
I2C_InterruptPowerControl(ARM_POWER_STATE state,cmsis_i2c_interrupt_driver_state_t * i2c)1125 static int32_t I2C_InterruptPowerControl(ARM_POWER_STATE state, cmsis_i2c_interrupt_driver_state_t *i2c)
1126 {
1127 int32_t result = ARM_DRIVER_OK;
1128 switch (state)
1129 {
1130 /* Terminates any pending data transfers, disable i2c moduole and i2c clock */
1131 case ARM_POWER_OFF:
1132 if ((i2c->flags & (uint8_t)I2C_FLAG_POWER) != 0U)
1133 {
1134 (void)I2C_InterruptControl(ARM_I2C_ABORT_TRANSFER, 0, i2c);
1135
1136 I2C_MasterDeinit(i2c->resource->base);
1137
1138 i2c->flags = (uint8_t)I2C_FLAG_INIT;
1139 }
1140 break;
1141
1142 /* Not supported */
1143 case ARM_POWER_LOW:
1144 result = ARM_DRIVER_ERROR_UNSUPPORTED;
1145 break;
1146
1147 /* Enable i2c moduole and i2c clock */
1148 case ARM_POWER_FULL:
1149 if (i2c->flags == (uint8_t)I2C_FLAG_UNINIT)
1150 {
1151 return ARM_DRIVER_ERROR;
1152 }
1153
1154 if ((i2c->flags & (uint8_t)I2C_FLAG_POWER) != 0U)
1155 {
1156 /* Driver already powered */
1157 break;
1158 }
1159
1160 CLOCK_EnableClock(s_i2cClocks[I2C_GetInstance(i2c->resource->base)]);
1161 i2c->resource->base->C1 = I2C_C1_IICEN(1);
1162 i2c->flags |= (uint8_t)I2C_FLAG_POWER;
1163 break;
1164
1165 default:
1166 result = ARM_DRIVER_ERROR_UNSUPPORTED;
1167 break;
1168 }
1169
1170 return result;
1171 }
1172
I2C_InterruptGetStatus(cmsis_i2c_interrupt_driver_state_t * i2c)1173 static ARM_I2C_STATUS I2C_InterruptGetStatus(cmsis_i2c_interrupt_driver_state_t *i2c)
1174 {
1175 ARM_I2C_STATUS stat = {0};
1176 uint32_t ksdk_i2c_status = I2C_SlaveGetStatusFlags(i2c->resource->base);
1177 uint32_t dataSize;
1178
1179 if (0U == (i2c->resource->base->A1))
1180 {
1181 dataSize = i2c->handle->master_handle.transfer.dataSize;
1182 stat.direction = (uint32_t)((ksdk_i2c_status & (uint32_t)kI2C_TransferDirectionFlag) !=
1183 0U); /* Direction: 0=Transmitter, 1=Receiver.*/
1184 stat.mode = 1UL; /* Mode: 0=Slave, 1=Master.*/
1185 }
1186 else
1187 {
1188 dataSize = i2c->handle->slave_handle.transfer.dataSize;
1189 stat.direction = (uint32_t)(
1190 0UL == (ksdk_i2c_status & (uint8_t)kI2C_TransferDirectionFlag)); /* Direction: 0=Transmitter, 1=Receiver.*/
1191 stat.mode = 0; /* Mode: 0=Slave, 1=Master.*/
1192 }
1193
1194 if (dataSize != 0U)
1195 {
1196 stat.busy = 1; /* Busy flag.*/
1197 }
1198 else
1199 {
1200 stat.busy = 0; /* Busy flag.*/
1201 }
1202
1203 stat.arbitration_lost = (uint32_t)((ksdk_i2c_status & (uint32_t)kI2C_ArbitrationLostFlag) !=
1204 0U); /* Master lost arbitration (cleared on start of next Master operation)*/
1205
1206 return stat;
1207 }
1208
1209 #endif
1210
1211 #if (defined(I2C0) && defined(RTE_I2C0) && RTE_I2C0)
1212 /* User needs to provide the implementation for I2C0_GetFreq/InitPins/DeinitPins
1213 in the application for enabling according instance. */
1214 extern uint32_t I2C0_GetFreq(void);
1215
1216 static cmsis_i2c_resource_t I2C0_Resource = {I2C0, I2C0_GetFreq};
1217
1218 #if (defined(RTE_I2C0_DMA_EN) && RTE_I2C0_DMA_EN)
1219
1220 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
1221
1222 static cmsis_i2c_dma_resource_t I2C0_DmaResource = {RTE_I2C0_Master_DMA_BASE, RTE_I2C0_Master_DMA_CH,
1223 RTE_I2C0_Master_DMAMUX_BASE, (uint16_t)RTE_I2C0_Master_PERI_SEL
1224 #if FSL_FEATURE_DMA_MODULE_CHANNEL != FSL_FEATURE_DMAMUX_MODULE_CHANNEL
1225 ,
1226 RTE_I2C0_Master_DMAMUX_CH
1227 #endif
1228 };
1229
1230 static i2c_master_dma_handle_t I2C0_DmaHandle;
1231 static dma_handle_t I2C0_DmaTxRxHandle;
1232
1233 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1234 ARMCC_SECTION("i2c0_dma_driver_state")
1235 static cmsis_i2c_dma_driver_state_t I2C0_DmaDriverState = {
1236 #else
1237 static cmsis_i2c_dma_driver_state_t I2C0_DmaDriverState = {
1238 #endif
1239 &I2C0_Resource,
1240 &I2C0_DmaResource,
1241 &I2C0_DmaHandle,
1242 &I2C0_DmaTxRxHandle,
1243 };
1244
I2C0_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event)1245 static int32_t I2C0_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event)
1246 {
1247 #ifdef RTE_I2C0_PIN_INIT
1248 RTE_I2C0_PIN_INIT();
1249 #endif
1250 return I2C_Master_DmaInitialize(cb_event, &I2C0_DmaDriverState);
1251 }
1252
I2C0_Master_DmaUninitialize(void)1253 static int32_t I2C0_Master_DmaUninitialize(void)
1254 {
1255 #ifdef RTE_I2C0_PIN_DEINIT
1256 RTE_I2C0_PIN_DEINIT();
1257 #endif
1258 return I2C_Master_DmaUninitialize(&I2C0_DmaDriverState);
1259 }
1260
I2C0_Master_DmaPowerControl(ARM_POWER_STATE state)1261 static int32_t I2C0_Master_DmaPowerControl(ARM_POWER_STATE state)
1262 {
1263 return I2C_Master_DmaPowerControl(state, &I2C0_DmaDriverState);
1264 }
1265
I2C0_Master_DmaTransmit(uint32_t addr,const uint8_t * data,uint32_t num,bool xfer_pending)1266 static int32_t I2C0_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
1267 {
1268 return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C0_DmaDriverState);
1269 }
1270
I2C0_Master_DmaReceive(uint32_t addr,uint8_t * data,uint32_t num,bool xfer_pending)1271 static int32_t I2C0_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
1272 {
1273 return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C0_DmaDriverState);
1274 }
1275
I2C0_Master_DmaGetDataCount(void)1276 static int32_t I2C0_Master_DmaGetDataCount(void)
1277 {
1278 return I2C_Master_DmaGetDataCount(&I2C0_DmaDriverState);
1279 }
1280
I2C0_Master_DmaControl(uint32_t control,uint32_t arg)1281 static int32_t I2C0_Master_DmaControl(uint32_t control, uint32_t arg)
1282 {
1283 return I2C_Master_DmaControl(control, arg, &I2C0_DmaDriverState);
1284 }
1285
I2C0_Master_DmaGetStatus(void)1286 static ARM_I2C_STATUS I2C0_Master_DmaGetStatus(void)
1287 {
1288 return I2C_Master_DmaGetStatus(&I2C0_DmaDriverState);
1289 }
1290
1291 #endif
1292
1293 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
1294
1295 static cmsis_i2c_edma_resource_t I2C0_EdmaResource = {RTE_I2C0_Master_DMA_BASE, RTE_I2C0_Master_DMA_CH,
1296 RTE_I2C0_Master_DMAMUX_BASE, (uint16_t)RTE_I2C0_Master_PERI_SEL};
1297
1298 static i2c_master_edma_handle_t I2C0_EdmaHandle;
1299 static edma_handle_t I2C0_EdmaTxRxHandle;
1300
1301 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1302 ARMCC_SECTION("i2c0_edma_driver_state")
1303 static cmsis_i2c_edma_driver_state_t I2C0_EdmaDriverState = {
1304 #else
1305 static cmsis_i2c_edma_driver_state_t I2C0_EdmaDriverState = {
1306 #endif
1307 &I2C0_Resource,
1308 &I2C0_EdmaResource,
1309 &I2C0_EdmaHandle,
1310 &I2C0_EdmaTxRxHandle,
1311 };
1312
I2C0_Master_EdmaInitialize(ARM_I2C_SignalEvent_t cb_event)1313 static int32_t I2C0_Master_EdmaInitialize(ARM_I2C_SignalEvent_t cb_event)
1314 {
1315 #ifdef RTE_I2C0_PIN_INIT
1316 RTE_I2C0_PIN_INIT();
1317 #endif
1318 return I2C_Master_EdmaInitialize(cb_event, &I2C0_EdmaDriverState);
1319 }
1320
I2C0_Master_EdmaUninitialize(void)1321 static int32_t I2C0_Master_EdmaUninitialize(void)
1322 {
1323 #ifdef RTE_I2C0_PIN_DEINIT
1324 RTE_I2C0_PIN_DEINIT();
1325 #endif
1326 return I2C_Master_EdmaUninitialize(&I2C0_EdmaDriverState);
1327 }
1328
I2C0_Master_EdmaPowerControl(ARM_POWER_STATE state)1329 static int32_t I2C0_Master_EdmaPowerControl(ARM_POWER_STATE state)
1330 {
1331 return I2C_Master_EdmaPowerControl(state, &I2C0_EdmaDriverState);
1332 }
1333
I2C0_Master_EdmaTransmit(uint32_t addr,const uint8_t * data,uint32_t num,bool xfer_pending)1334 static int32_t I2C0_Master_EdmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
1335 {
1336 return I2C_Master_EdmaTransmit(addr, data, num, xfer_pending, &I2C0_EdmaDriverState);
1337 }
1338
I2C0_Master_EdmaReceive(uint32_t addr,uint8_t * data,uint32_t num,bool xfer_pending)1339 static int32_t I2C0_Master_EdmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
1340 {
1341 return I2C_Master_EdmaReceive(addr, data, num, xfer_pending, &I2C0_EdmaDriverState);
1342 }
1343
I2C0_Master_EdmaGetDataCount(void)1344 static int32_t I2C0_Master_EdmaGetDataCount(void)
1345 {
1346 return I2C_Master_EdmaGetDataCount(&I2C0_EdmaDriverState);
1347 }
1348
I2C0_Master_EdmaControl(uint32_t control,uint32_t arg)1349 static int32_t I2C0_Master_EdmaControl(uint32_t control, uint32_t arg)
1350 {
1351 return I2C_Master_EdmaControl(control, arg, &I2C0_EdmaDriverState);
1352 }
1353
I2C0_Master_EdmaGetStatus(void)1354 static ARM_I2C_STATUS I2C0_Master_EdmaGetStatus(void)
1355 {
1356 return I2C_Master_EdmaGetStatus(&I2C0_EdmaDriverState);
1357 }
1358
1359 #endif
1360
1361 #else
1362
1363 static cmsis_i2c_handle_t I2C0_handle;
1364
1365 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1366 ARMCC_SECTION("i2c0_interrupt_driver_state")
1367 static cmsis_i2c_interrupt_driver_state_t I2C0_InterruptDriverState = {
1368 #else
1369 static cmsis_i2c_interrupt_driver_state_t I2C0_InterruptDriverState = {
1370 #endif
1371 &I2C0_Resource,
1372 &I2C0_handle,
1373
1374 };
1375
I2C0_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event)1376 static int32_t I2C0_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event)
1377 {
1378 #ifdef RTE_I2C0_PIN_INIT
1379 RTE_I2C0_PIN_INIT();
1380 #endif
1381 return I2C_InterruptInitialize(cb_event, &I2C0_InterruptDriverState);
1382 }
1383
I2C0_InterruptUninitialize(void)1384 static int32_t I2C0_InterruptUninitialize(void)
1385 {
1386 #ifdef RTE_I2C0_PIN_DEINIT
1387 RTE_I2C0_PIN_DEINIT();
1388 #endif
1389 return I2C_InterruptUninitialize(&I2C0_InterruptDriverState);
1390 }
1391
I2C0_InterruptPowerControl(ARM_POWER_STATE state)1392 static int32_t I2C0_InterruptPowerControl(ARM_POWER_STATE state)
1393 {
1394 return I2C_InterruptPowerControl(state, &I2C0_InterruptDriverState);
1395 }
1396
I2C0_Master_InterruptTransmit(uint32_t addr,const uint8_t * data,uint32_t num,bool xfer_pending)1397 static int32_t I2C0_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
1398 {
1399 return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C0_InterruptDriverState);
1400 }
1401
I2C0_Master_InterruptReceive(uint32_t addr,uint8_t * data,uint32_t num,bool xfer_pending)1402 static int32_t I2C0_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
1403 {
1404 return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C0_InterruptDriverState);
1405 }
1406
I2C0_Slave_InterruptTransmit(const uint8_t * data,uint32_t num)1407 static int32_t I2C0_Slave_InterruptTransmit(const uint8_t *data, uint32_t num)
1408 {
1409 return I2C_Slave_InterruptTransmit(data, num, &I2C0_InterruptDriverState);
1410 }
1411
I2C0_Slave_InterruptReceive(uint8_t * data,uint32_t num)1412 static int32_t I2C0_Slave_InterruptReceive(uint8_t *data, uint32_t num)
1413 {
1414 return I2C_Slave_InterruptReceive(data, num, &I2C0_InterruptDriverState);
1415 }
1416
I2C0_InterruptGetDataCount(void)1417 static int32_t I2C0_InterruptGetDataCount(void)
1418 {
1419 return I2C_InterruptGetDataCount(&I2C0_InterruptDriverState);
1420 }
1421
I2C0_InterruptControl(uint32_t control,uint32_t arg)1422 static int32_t I2C0_InterruptControl(uint32_t control, uint32_t arg)
1423 {
1424 return I2C_InterruptControl(control, arg, &I2C0_InterruptDriverState);
1425 }
1426
I2C0_InterruptGetStatus(void)1427 static ARM_I2C_STATUS I2C0_InterruptGetStatus(void)
1428 {
1429 return I2C_InterruptGetStatus(&I2C0_InterruptDriverState);
1430 }
1431
1432 #endif
1433
1434 ARM_DRIVER_I2C Driver_I2C0 = {I2Cx_GetVersion,
1435 I2Cx_GetCapabilities,
1436 #if (defined(RTE_I2C0_DMA_EN) && RTE_I2C0_DMA_EN)
1437 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
1438 I2C0_Master_EdmaInitialize,
1439 I2C0_Master_EdmaUninitialize,
1440 I2C0_Master_EdmaPowerControl,
1441 I2C0_Master_EdmaTransmit,
1442 I2C0_Master_EdmaReceive,
1443 NULL,
1444 NULL,
1445 I2C0_Master_EdmaGetDataCount,
1446 I2C0_Master_EdmaControl,
1447 I2C0_Master_EdmaGetStatus
1448 #else
1449 I2C0_Master_DmaInitialize,
1450 I2C0_Master_DmaUninitialize,
1451 I2C0_Master_DmaPowerControl,
1452 I2C0_Master_DmaTransmit,
1453 I2C0_Master_DmaReceive,
1454 NULL,
1455 NULL,
1456 I2C0_Master_DmaGetDataCount,
1457 I2C0_Master_DmaControl,
1458 I2C0_Master_DmaGetStatus
1459 #endif
1460 #else
1461 I2C0_InterruptInitialize,
1462 I2C0_InterruptUninitialize,
1463 I2C0_InterruptPowerControl,
1464 I2C0_Master_InterruptTransmit,
1465 I2C0_Master_InterruptReceive,
1466 I2C0_Slave_InterruptTransmit,
1467 I2C0_Slave_InterruptReceive,
1468 I2C0_InterruptGetDataCount,
1469 I2C0_InterruptControl,
1470 I2C0_InterruptGetStatus
1471 #endif
1472 };
1473
1474 #endif
1475
1476 #if defined(I2C1) && defined(RTE_I2C1) && RTE_I2C1
1477
1478 /* User needs to provide the implementation for I2C1_GetFreq/InitPins/DeinitPins
1479 in the application for enabling according instance. */
1480 extern uint32_t I2C1_GetFreq(void);
1481
1482 static cmsis_i2c_resource_t I2C1_Resource = {I2C1, I2C1_GetFreq};
1483
1484 #if (defined(RTE_I2C1_DMA_EN) && RTE_I2C1_DMA_EN)
1485
1486 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
1487
1488 static cmsis_i2c_dma_resource_t I2C1_DmaResource = {RTE_I2C1_Master_DMA_BASE, RTE_I2C1_Master_DMA_CH,
1489 RTE_I2C1_Master_DMAMUX_BASE, RTE_I2C1_Master_PERI_SEL
1490 #if FSL_FEATURE_DMA_MODULE_CHANNEL != FSL_FEATURE_DMAMUX_MODULE_CHANNEL
1491 ,
1492 RTE_I2C1_Master_DMAMUX_CH
1493 #endif
1494 };
1495
1496 static i2c_master_dma_handle_t I2C1_DmaHandle;
1497 static dma_handle_t I2C1_DmaTxRxHandle;
1498
1499 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1500 ARMCC_SECTION("i2c1_dma_driver_state")
1501 static cmsis_i2c_dma_driver_state_t I2C1_DmaDriverState = {
1502 #else
1503 static cmsis_i2c_dma_driver_state_t I2C1_DmaDriverState = {
1504 #endif
1505 &I2C1_Resource,
1506 &I2C1_DmaResource,
1507 &I2C1_DmaHandle,
1508 &I2C1_DmaTxRxHandle,
1509 };
1510
I2C1_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event)1511 static int32_t I2C1_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event)
1512 {
1513 #ifdef RTE_I2C1_PIN_INIT
1514 RTE_I2C1_PIN_INIT();
1515 #endif
1516 return I2C_Master_DmaInitialize(cb_event, &I2C1_DmaDriverState);
1517 }
1518
I2C1_Master_DmaUninitialize(void)1519 static int32_t I2C1_Master_DmaUninitialize(void)
1520 {
1521 #ifdef RTE_I2C1_PIN_DEINIT
1522 RTE_I2C1_PIN_DEINIT();
1523 #endif
1524 return I2C_Master_DmaUninitialize(&I2C1_DmaDriverState);
1525 }
1526
I2C1_Master_DmaPowerControl(ARM_POWER_STATE state)1527 static int32_t I2C1_Master_DmaPowerControl(ARM_POWER_STATE state)
1528 {
1529 return I2C_Master_DmaPowerControl(state, &I2C1_DmaDriverState);
1530 }
1531
I2C1_Master_DmaTransmit(uint32_t addr,const uint8_t * data,uint32_t num,bool xfer_pending)1532 static int32_t I2C1_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
1533 {
1534 return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C1_DmaDriverState);
1535 }
1536
I2C1_Master_DmaReceive(uint32_t addr,uint8_t * data,uint32_t num,bool xfer_pending)1537 static int32_t I2C1_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
1538 {
1539 return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C1_DmaDriverState);
1540 }
1541
I2C1_Master_DmaGetDataCount(void)1542 static int32_t I2C1_Master_DmaGetDataCount(void)
1543 {
1544 return I2C_Master_DmaGetDataCount(&I2C1_DmaDriverState);
1545 }
1546
I2C1_Master_DmaControl(uint32_t control,uint32_t arg)1547 static int32_t I2C1_Master_DmaControl(uint32_t control, uint32_t arg)
1548 {
1549 return I2C_Master_DmaControl(control, arg, &I2C1_DmaDriverState);
1550 }
1551
I2C1_Master_DmaGetStatus(void)1552 static ARM_I2C_STATUS I2C1_Master_DmaGetStatus(void)
1553 {
1554 return I2C_Master_DmaGetStatus(&I2C1_DmaDriverState);
1555 }
1556
1557 #endif
1558
1559 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
1560
1561 static cmsis_i2c_edma_resource_t I2C1_EdmaResource = {RTE_I2C1_Master_DMA_BASE, RTE_I2C1_Master_DMA_CH,
1562 RTE_I2C1_Master_DMAMUX_BASE, (uint16_t)RTE_I2C1_Master_PERI_SEL};
1563
1564 static i2c_master_edma_handle_t I2C1_EdmaHandle;
1565 static edma_handle_t I2C1_EdmaTxRxHandle;
1566
1567 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1568 ARMCC_SECTION("i2c1_edma_driver_state")
1569 static cmsis_i2c_edma_driver_state_t I2C1_EdmaDriverState = {
1570 #else
1571 static cmsis_i2c_edma_driver_state_t I2C1_EdmaDriverState = {
1572 #endif
1573 &I2C1_Resource,
1574 &I2C1_EdmaResource,
1575 &I2C1_EdmaHandle,
1576 &I2C1_EdmaTxRxHandle,
1577 };
1578
I2C1_Master_EdmaInitialize(ARM_I2C_SignalEvent_t cb_event)1579 static int32_t I2C1_Master_EdmaInitialize(ARM_I2C_SignalEvent_t cb_event)
1580 {
1581 #ifdef RTE_I2C1_PIN_INIT
1582 RTE_I2C1_PIN_INIT();
1583 #endif
1584 return I2C_Master_EdmaInitialize(cb_event, &I2C1_EdmaDriverState);
1585 }
1586
I2C1_Master_EdmaUninitialize(void)1587 static int32_t I2C1_Master_EdmaUninitialize(void)
1588 {
1589 #ifdef RTE_I2C1_PIN_DEINIT
1590 RTE_I2C1_PIN_DEINIT();
1591 #endif
1592 return I2C_Master_EdmaUninitialize(&I2C1_EdmaDriverState);
1593 }
1594
I2C1_Master_EdmaPowerControl(ARM_POWER_STATE state)1595 static int32_t I2C1_Master_EdmaPowerControl(ARM_POWER_STATE state)
1596 {
1597 return I2C_Master_EdmaPowerControl(state, &I2C1_EdmaDriverState);
1598 }
1599
I2C1_Master_EdmaTransmit(uint32_t addr,const uint8_t * data,uint32_t num,bool xfer_pending)1600 static int32_t I2C1_Master_EdmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
1601 {
1602 return I2C_Master_EdmaTransmit(addr, data, num, xfer_pending, &I2C1_EdmaDriverState);
1603 }
1604
I2C1_Master_EdmaReceive(uint32_t addr,uint8_t * data,uint32_t num,bool xfer_pending)1605 static int32_t I2C1_Master_EdmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
1606 {
1607 return I2C_Master_EdmaReceive(addr, data, num, xfer_pending, &I2C1_EdmaDriverState);
1608 }
1609
I2C1_Master_EdmaGetDataCount(void)1610 static int32_t I2C1_Master_EdmaGetDataCount(void)
1611 {
1612 return I2C_Master_EdmaGetDataCount(&I2C1_EdmaDriverState);
1613 }
1614
I2C1_Master_EdmaControl(uint32_t control,uint32_t arg)1615 static int32_t I2C1_Master_EdmaControl(uint32_t control, uint32_t arg)
1616 {
1617 return I2C_Master_EdmaControl(control, arg, &I2C1_EdmaDriverState);
1618 }
1619
I2C1_Master_EdmaGetStatus(void)1620 static ARM_I2C_STATUS I2C1_Master_EdmaGetStatus(void)
1621 {
1622 return I2C_Master_EdmaGetStatus(&I2C1_EdmaDriverState);
1623 }
1624
1625 #endif
1626
1627 #else
1628
1629 static cmsis_i2c_handle_t I2C1_Handle;
1630
1631 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1632 ARMCC_SECTION("i2c1_interrupt_driver_state")
1633 static cmsis_i2c_interrupt_driver_state_t I2C1_InterruptDriverState = {
1634 #else
1635 static cmsis_i2c_interrupt_driver_state_t I2C1_InterruptDriverState = {
1636 #endif
1637 &I2C1_Resource,
1638 &I2C1_Handle,
1639 };
1640
I2C1_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event)1641 static int32_t I2C1_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event)
1642 {
1643 #ifdef RTE_I2C1_PIN_INIT
1644 RTE_I2C1_PIN_INIT();
1645 #endif
1646 return I2C_InterruptInitialize(cb_event, &I2C1_InterruptDriverState);
1647 }
1648
I2C1_InterruptUninitialize(void)1649 static int32_t I2C1_InterruptUninitialize(void)
1650 {
1651 #ifdef RTE_I2C1_PIN_DEINIT
1652 RTE_I2C1_PIN_DEINIT();
1653 #endif
1654 return I2C_InterruptUninitialize(&I2C1_InterruptDriverState);
1655 }
1656
I2C1_InterruptPowerControl(ARM_POWER_STATE state)1657 static int32_t I2C1_InterruptPowerControl(ARM_POWER_STATE state)
1658 {
1659 return I2C_InterruptPowerControl(state, &I2C1_InterruptDriverState);
1660 }
1661
I2C1_Master_InterruptTransmit(uint32_t addr,const uint8_t * data,uint32_t num,bool xfer_pending)1662 static int32_t I2C1_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
1663 {
1664 return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C1_InterruptDriverState);
1665 }
1666
I2C1_Master_InterruptReceive(uint32_t addr,uint8_t * data,uint32_t num,bool xfer_pending)1667 static int32_t I2C1_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
1668 {
1669 return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C1_InterruptDriverState);
1670 }
1671
I2C1_Slave_InterruptTransmit(const uint8_t * data,uint32_t num)1672 static int32_t I2C1_Slave_InterruptTransmit(const uint8_t *data, uint32_t num)
1673 {
1674 return I2C_Slave_InterruptTransmit(data, num, &I2C1_InterruptDriverState);
1675 }
1676
I2C1_Slave_InterruptReceive(uint8_t * data,uint32_t num)1677 static int32_t I2C1_Slave_InterruptReceive(uint8_t *data, uint32_t num)
1678 {
1679 return I2C_Slave_InterruptReceive(data, num, &I2C1_InterruptDriverState);
1680 }
1681
I2C1_InterruptGetDataCount(void)1682 static int32_t I2C1_InterruptGetDataCount(void)
1683 {
1684 return I2C_InterruptGetDataCount(&I2C1_InterruptDriverState);
1685 }
1686
I2C1_InterruptControl(uint32_t control,uint32_t arg)1687 static int32_t I2C1_InterruptControl(uint32_t control, uint32_t arg)
1688 {
1689 return I2C_InterruptControl(control, arg, &I2C1_InterruptDriverState);
1690 }
1691
I2C1_InterruptGetStatus(void)1692 static ARM_I2C_STATUS I2C1_InterruptGetStatus(void)
1693 {
1694 return I2C_InterruptGetStatus(&I2C1_InterruptDriverState);
1695 }
1696
1697 #endif
1698
1699 ARM_DRIVER_I2C Driver_I2C1 = {I2Cx_GetVersion,
1700 I2Cx_GetCapabilities,
1701 #if (defined(RTE_I2C1_DMA_EN) && RTE_I2C1_DMA_EN)
1702 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
1703 I2C1_Master_EdmaInitialize,
1704 I2C1_Master_EdmaUninitialize,
1705 I2C1_Master_EdmaPowerControl,
1706 I2C1_Master_EdmaTransmit,
1707 I2C1_Master_EdmaReceive,
1708 NULL,
1709 NULL,
1710 I2C1_Master_EdmaGetDataCount,
1711 I2C1_Master_EdmaControl,
1712 I2C1_Master_EdmaGetStatus
1713 #else
1714 I2C1_Master_DmaInitialize,
1715 I2C1_Master_DmaUninitialize,
1716 I2C1_Master_DmaPowerControl,
1717 I2C1_Master_DmaTransmit,
1718 I2C1_Master_DmaReceive,
1719 NULL,
1720 NULL,
1721 I2C1_Master_DmaGetDataCount,
1722 I2C1_Master_DmaControl,
1723 I2C1_Master_DmaGetStatus
1724 #endif
1725 #else
1726 I2C1_InterruptInitialize,
1727 I2C1_InterruptUninitialize,
1728 I2C1_InterruptPowerControl,
1729 I2C1_Master_InterruptTransmit,
1730 I2C1_Master_InterruptReceive,
1731 I2C1_Slave_InterruptTransmit,
1732 I2C1_Slave_InterruptReceive,
1733 I2C1_InterruptGetDataCount,
1734 I2C1_InterruptControl,
1735 I2C1_InterruptGetStatus
1736 #endif
1737 };
1738
1739 #endif
1740
1741 #if (defined(I2C2) && defined(RTE_I2C2) && RTE_I2C2)
1742
1743 /* User needs to provide the implementation for I2C2_GetFreq/InitPins/DeinitPins
1744 in the application for enabling according instance. */
1745 extern uint32_t I2C2_GetFreq(void);
1746
1747 static cmsis_i2c_resource_t I2C2_Resource = {I2C2, I2C2_GetFreq};
1748
1749 #if (defined(RTE_I2C2_DMA_EN) && RTE_I2C2_DMA_EN)
1750
1751 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
1752
1753 static cmsis_i2c_dma_resource_t I2C2_DmaResource = {RTE_I2C2_Master_DMA_BASE, RTE_I2C2_Master_DMA_CH,
1754 RTE_I2C2_Master_DMAMUX_BASE, RTE_I2C2_Master_PERI_SEL
1755 #if FSL_FEATURE_DMA_MODULE_CHANNEL != FSL_FEATURE_DMAMUX_MODULE_CHANNEL
1756 ,
1757 RTE_I2C2_Master_DMAMUX_CH
1758 #endif
1759 };
1760
1761 static i2c_master_dma_handle_t I2C2_DmaHandle;
1762 static dma_handle_t I2C2_DmaTxRxHandle;
1763
1764 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1765 ARMCC_SECTION("i2c2_dma_driver_state")
1766 static cmsis_i2c_dma_driver_state_t I2C2_DmaDriverState = {
1767 #else
1768 static cmsis_i2c_dma_driver_state_t I2C2_DmaDriverState = {
1769 #endif
1770 &I2C2_Resource,
1771 &I2C2_DmaResource,
1772 &I2C2_DmaHandle,
1773 &I2C2_DmaTxRxHandle,
1774 };
1775
I2C2_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event)1776 static int32_t I2C2_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event)
1777 {
1778 #ifdef RTE_I2C2_PIN_INIT
1779 RTE_I2C2_PIN_INIT();
1780 #endif
1781 return I2C_Master_DmaInitialize(cb_event, &I2C2_DmaDriverState);
1782 }
1783
I2C2_Master_DmaUninitialize(void)1784 static int32_t I2C2_Master_DmaUninitialize(void)
1785 {
1786 #ifdef RTE_I2C2_PIN_DEINIT
1787 RTE_I2C2_PIN_DEINIT();
1788 #endif
1789 return I2C_Master_DmaUninitialize(&I2C2_DmaDriverState);
1790 }
1791
I2C2_Master_DmaPowerControl(ARM_POWER_STATE state)1792 static int32_t I2C2_Master_DmaPowerControl(ARM_POWER_STATE state)
1793 {
1794 return I2C_Master_DmaPowerControl(&I2C2_DmaDriverState);
1795 }
1796
I2C2_Master_DmaTransmit(uint32_t addr,const uint8_t * data,uint32_t num,bool xfer_pending)1797 static int32_t I2C2_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
1798 {
1799 return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C2_DmaDriverState);
1800 }
1801
I2C2_Master_DmaReceive(uint32_t addr,uint8_t * data,uint32_t num,bool xfer_pending)1802 static int32_t I2C2_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
1803 {
1804 return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C2_DmaDriverState);
1805 }
1806
I2C2_Master_DmaGetDataCount(void)1807 static int32_t I2C2_Master_DmaGetDataCount(void)
1808 {
1809 return I2C_Master_DmaGetDataCount(&I2C2_DmaDriverState);
1810 }
1811
I2C2_Master_DmaControl(uint32_t control,uint32_t arg)1812 static int32_t I2C2_Master_DmaControl(uint32_t control, uint32_t arg)
1813 {
1814 return I2C_Master_DmaControl(control, arg, &I2C2_DmaDriverState);
1815 }
1816
I2C2_Master_DmaGetStatus(void)1817 static ARM_I2C_STATUS I2C2_Master_DmaGetStatus(void)
1818 {
1819 return I2C_Master_DmaGetStatus(&I2C2_DmaDriverState);
1820 }
1821
1822 #endif
1823
1824 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
1825
1826 static cmsis_i2c_edma_resource_t I2C2_EdmaResource = {RTE_I2C2_Master_DMA_BASE, RTE_I2C2_Master_DMA_CH,
1827 RTE_I2C2_Master_DMAMUX_BASE, RTE_I2C2_Master_PERI_SEL};
1828
1829 static i2c_master_edma_handle_t I2C2_EdmaHandle;
1830 static edma_handle_t I2C2_EdmaTxRxHandle;
1831
1832 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1833 ARMCC_SECTION("i2c2_edma_driver_state")
1834 static cmsis_i2c_edma_driver_state_t I2C2_EdmaDriverState = {
1835 #else
1836 static cmsis_i2c_edma_driver_state_t I2C2_EdmaDriverState = {
1837 #endif
1838 &I2C2_Resource,
1839 &I2C2_EdmaResource,
1840 &I2C2_EdmaHandle,
1841 &I2C2_EdmaTxRxHandle,
1842 };
1843
I2C2_Master_EdmaInitialize(ARM_I2C_SignalEvent_t cb_event)1844 static int32_t I2C2_Master_EdmaInitialize(ARM_I2C_SignalEvent_t cb_event)
1845 {
1846 #ifdef RTE_I2C2_PIN_INIT
1847 RTE_I2C2_PIN_INIT();
1848 #endif
1849 return I2C_Master_EdmaInitialize(cb_event, &I2C2_EdmaDriverState);
1850 }
1851
I2C2_Master_EdmaUninitialize(void)1852 static int32_t I2C2_Master_EdmaUninitialize(void)
1853 {
1854 #ifdef RTE_I2C2_PIN_DEINIT
1855 RTE_I2C2_PIN_DEINIT();
1856 #endif
1857 return I2C_Master_EdmaUninitialize(&I2C2_EdmaDriverState);
1858 }
1859
I2C2_Master_EdmaPowerControl(ARM_POWER_STATE state)1860 static int32_t I2C2_Master_EdmaPowerControl(ARM_POWER_STATE state)
1861 {
1862 return I2C_Master_EdmaPowerControl(state, &I2C2_EdmaDriverState);
1863 }
1864
I2C2_Master_EdmaTransmit(uint32_t addr,const uint8_t * data,uint32_t num,bool xfer_pending)1865 static int32_t I2C2_Master_EdmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
1866 {
1867 return I2C_Master_EdmaTransmit(addr, data, num, xfer_pending, &I2C2_EdmaDriverState);
1868 }
1869
I2C2_Master_EdmaReceive(uint32_t addr,uint8_t * data,uint32_t num,bool xfer_pending)1870 static int32_t I2C2_Master_EdmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
1871 {
1872 return I2C_Master_EdmaReceive(addr, data, num, xfer_pending, &I2C2_EdmaDriverState);
1873 }
1874
I2C2_Master_EdmaGetDataCount(void)1875 static int32_t I2C2_Master_EdmaGetDataCount(void)
1876 {
1877 return I2C_Master_EdmaGetDataCount(&I2C2_EdmaDriverState);
1878 }
1879
I2C2_Master_EdmaControl(uint32_t control,uint32_t arg)1880 static int32_t I2C2_Master_EdmaControl(uint32_t control, uint32_t arg)
1881 {
1882 return I2C_Master_EdmaControl(control, arg, &I2C2_EdmaDriverState);
1883 }
1884
I2C2_Master_EdmaGetStatus(void)1885 static ARM_I2C_STATUS I2C2_Master_EdmaGetStatus(void)
1886 {
1887 return I2C_Master_EdmaGetStatus(&I2C2_EdmaDriverState);
1888 }
1889
1890 #endif
1891
1892 #else
1893
1894 static cmsis_i2c_handle_t I2C2_Handle;
1895
1896 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1897 ARMCC_SECTION("i2c2_interrupt_driver_state")
1898 static cmsis_i2c_interrupt_driver_state_t I2C2_InterruptDriverState = {
1899 #else
1900 static cmsis_i2c_interrupt_driver_state_t I2C2_InterruptDriverState = {
1901 #endif
1902 &I2C2_Resource,
1903 &I2C2_Handle,
1904
1905 };
1906
I2C2_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event)1907 static int32_t I2C2_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event)
1908 {
1909 #ifdef RTE_I2C2_PIN_INIT
1910 RTE_I2C2_PIN_INIT();
1911 #endif
1912 return I2C_InterruptInitialize(cb_event, &I2C2_InterruptDriverState);
1913 }
1914
I2C2_InterruptUninitialize(void)1915 static int32_t I2C2_InterruptUninitialize(void)
1916 {
1917 #ifdef RTE_I2C2_PIN_DEINIT
1918 RTE_I2C2_PIN_DEINIT();
1919 #endif
1920 return I2C_InterruptUninitialize(&I2C2_InterruptDriverState);
1921 }
1922
I2C2_InterruptPowerControl(ARM_POWER_STATE state)1923 static int32_t I2C2_InterruptPowerControl(ARM_POWER_STATE state)
1924 {
1925 return I2C_InterruptPowerControl(state, &I2C2_InterruptDriverState);
1926 }
1927
I2C2_Master_InterruptTransmit(uint32_t addr,const uint8_t * data,uint32_t num,bool xfer_pending)1928 static int32_t I2C2_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
1929 {
1930 return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C2_InterruptDriverState);
1931 }
1932
I2C2_Master_InterruptReceive(uint32_t addr,uint8_t * data,uint32_t num,bool xfer_pending)1933 static int32_t I2C2_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
1934 {
1935 return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C2_InterruptDriverState);
1936 }
1937
I2C2_Slave_InterruptTransmit(const uint8_t * data,uint32_t num)1938 static int32_t I2C2_Slave_InterruptTransmit(const uint8_t *data, uint32_t num)
1939 {
1940 return I2C_Slave_InterruptTransmit(data, num, &I2C2_InterruptDriverState);
1941 }
1942
I2C2_Slave_InterruptReceive(uint8_t * data,uint32_t num)1943 static int32_t I2C2_Slave_InterruptReceive(uint8_t *data, uint32_t num)
1944 {
1945 return I2C_Slave_InterruptReceive(data, num, &I2C2_InterruptDriverState);
1946 }
1947
I2C2_InterruptGetDataCount(void)1948 static int32_t I2C2_InterruptGetDataCount(void)
1949 {
1950 return I2C_InterruptGetDataCount(&I2C2_InterruptDriverState);
1951 }
1952
I2C2_InterruptControl(uint32_t control,uint32_t arg)1953 static int32_t I2C2_InterruptControl(uint32_t control, uint32_t arg)
1954 {
1955 return I2C_InterruptControl(control, arg, &I2C2_InterruptDriverState);
1956 }
1957
I2C2_InterruptGetStatus(void)1958 static ARM_I2C_STATUS I2C2_InterruptGetStatus(void)
1959 {
1960 return I2C_InterruptGetStatus(&I2C2_InterruptDriverState);
1961 }
1962
1963 #endif
1964
1965 ARM_DRIVER_I2C Driver_I2C2 = {I2Cx_GetVersion,
1966 I2Cx_GetCapabilities,
1967 #if (defined(RTE_I2C2_DMA_EN) && RTE_I2C2_DMA_EN)
1968 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
1969 I2C2_Master_EdmaInitialize,
1970 I2C2_Master_EdmaUninitialize,
1971 I2C2_Master_EdmaPowerControl,
1972 I2C2_Master_EdmaTransmit,
1973 I2C2_Master_EdmaReceive,
1974 NULL,
1975 NULL,
1976 I2C2_Master_EdmaGetDataCount,
1977 I2C2_Master_EdmaControl,
1978 I2C2_Master_EdmaGetStatus
1979 #else
1980 I2C2_Master_DmaInitialize,
1981 I2C2_Master_DmaUninitialize,
1982 I2C2_Master_DmaPowerControl,
1983 I2C2_Master_DmaTransmit,
1984 I2C2_Master_DmaReceive,
1985 NULL,
1986 NULL,
1987 I2C2_Master_DmaGetDataCount,
1988 I2C2_Master_DmaControl,
1989 I2C2_Master_DmaGetStatus
1990 #endif
1991 #else
1992 I2C2_InterruptInitialize,
1993 I2C2_InterruptUninitialize,
1994 I2C2_InterruptPowerControl,
1995 I2C2_Master_InterruptTransmit,
1996 I2C2_Master_InterruptReceive,
1997 I2C2_Slave_InterruptTransmit,
1998 I2C2_Slave_InterruptReceive,
1999 I2C2_InterruptGetDataCount,
2000 I2C2_InterruptControl,
2001 I2C2_InterruptGetStatus
2002 #endif
2003 };
2004
2005 #endif
2006
2007 #if (defined(I2C3) && defined(RTE_I2C3) && RTE_I2C3)
2008
2009 /* User needs to provide the implementation for I2C3_GetFreq/InitPins/DeinitPins
2010 in the application for enabling according instance. */
2011 extern uint32_t I2C3_GetFreq(void);
2012
2013 static cmsis_i2c_resource_t I2C3_Resource = {I2C3, I2C3_GetFreq};
2014
2015 #if (defined(RTE_I2C3_DMA_EN) && RTE_I2C3_DMA_EN)
2016
2017 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
2018
2019 static cmsis_i2c_dma_resource_t I2C3_DmaResource = {RTE_I2C3_Master_DMA_BASE, RTE_I2C3_Master_DMA_CH,
2020 RTE_I2C3_Master_DMAMUX_BASE, RTE_I2C3_Master_PERI_SEL
2021 #if FSL_FEATURE_DMA_MODULE_CHANNEL != FSL_FEATURE_DMAMUX_MODULE_CHANNEL
2022 ,
2023 RTE_I2C1_Master_DMAMUX_CH
2024 #endif
2025 };
2026
2027 static i2c_master_dma_handle_t I2C3_DmaHandle;
2028 static dma_handle_t I2C3_DmaTxRxHandle;
2029
2030 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
2031 ARMCC_SECTION("i2c3_dma_driver_state")
2032 static cmsis_i2c_dma_driver_state_t I2C3_DmaDriverState = {
2033 #else
2034 static cmsis_i2c_dma_driver_state_t I2C3_DmaDriverState = {
2035 #endif
2036 &I2C3_Resource,
2037 &I2C3_DmaResource,
2038 &I2C3_DmaHandle,
2039 &I2C3_DmaTxRxHandle,
2040 };
2041
I2C3_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event)2042 static int32_t I2C3_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event)
2043 {
2044 #ifdef RTE_I2C3_PIN_INIT
2045 RTE_I2C3_PIN_INIT();
2046 #endif
2047 return I2C_Master_DmaInitialize(cb_event, &I2C3_DmaDriverState);
2048 }
2049
I2C3_Master_DmaUninitialize(void)2050 static int32_t I2C3_Master_DmaUninitialize(void)
2051 {
2052 #ifdef RTE_I2C3_PIN_DEINIT
2053 RTE_I2C3_PIN_DEINIT();
2054 #endif
2055 return I2C_Master_DmaUninitialize(&I2C3_DmaDriverState);
2056 }
2057
I2C3_Master_DmaPowerControl(ARM_POWER_STATE state)2058 static int32_t I2C3_Master_DmaPowerControl(ARM_POWER_STATE state)
2059 {
2060 return I2C_Master_DmaPowerControl(&I2C3_DmaDriverState);
2061 }
2062
I2C3_Master_DmaTransmit(uint32_t addr,const uint8_t * data,uint32_t num,bool xfer_pending)2063 static int32_t I2C3_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
2064 {
2065 return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C3_DmaDriverState);
2066 }
2067
I2C3_Master_DmaReceive(uint32_t addr,uint8_t * data,uint32_t num,bool xfer_pending)2068 static int32_t I2C3_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
2069 {
2070 return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C3_DmaDriverState);
2071 }
2072
I2C3_Master_DmaGetDataCount(void)2073 static int32_t I2C3_Master_DmaGetDataCount(void)
2074 {
2075 return I2C_Master_DmaGetDataCount(&I2C3_DmaDriverState);
2076 }
2077
I2C3_Master_DmaControl(uint32_t control,uint32_t arg)2078 static int32_t I2C3_Master_DmaControl(uint32_t control, uint32_t arg)
2079 {
2080 return I2C_Master_DmaControl(control, arg, &I2C3_DmaDriverState);
2081 }
2082
I2C3_Master_DmaGetStatus(void)2083 static ARM_I2C_STATUS I2C3_Master_DmaGetStatus(void)
2084 {
2085 return I2C_Master_DmaGetStatus(&I2C3_DmaDriverState);
2086 }
2087
2088 #endif
2089
2090 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
2091
2092 static cmsis_i2c_edma_resource_t I2C3_EdmaResource = {RTE_I2C3_Master_DMA_BASE, RTE_I2C3_Master_DMA_CH,
2093 RTE_I2C3_Master_DMAMUX_BASE, RTE_I2C3_Master_PERI_SEL};
2094
2095 static i2c_master_edma_handle_t I2C3_EdmaHandle;
2096 static edma_handle_t I2C3_EdmaTxRxHandle;
2097
2098 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
2099 ARMCC_SECTION("i2c3_edma_driver_state")
2100 static cmsis_i2c_edma_driver_state_t I2C3_EdmaDriverState = {
2101 #else
2102 static cmsis_i2c_edma_driver_state_t I2C3_EdmaDriverState = {
2103 #endif
2104 &I2C3_Resource,
2105 &I2C3_EdmaResource,
2106 &I2C3_EdmaHandle,
2107 &I2C3_EdmaTxRxHandle,
2108 };
2109
I2C3_Master_EdmaInitialize(ARM_I2C_SignalEvent_t cb_event)2110 static int32_t I2C3_Master_EdmaInitialize(ARM_I2C_SignalEvent_t cb_event)
2111 {
2112 #ifdef RTE_I2C3_PIN_INIT
2113 RTE_I2C3_PIN_INIT();
2114 #endif
2115 return I2C_Master_EdmaInitialize(cb_event, &I2C3_EdmaDriverState);
2116 }
2117
I2C3_Master_EdmaUninitialize(void)2118 static int32_t I2C3_Master_EdmaUninitialize(void)
2119 {
2120 #ifdef RTE_I2C3_PIN_DEINIT
2121 RTE_I2C3_PIN_DEINIT();
2122 #endif
2123 return I2C_Master_EdmaUninitialize(&I2C3_EdmaDriverState);
2124 }
2125
I2C3_Master_EdmaPowerControl(ARM_POWER_STATE state)2126 static int32_t I2C3_Master_EdmaPowerControl(ARM_POWER_STATE state)
2127 {
2128 return I2C_Master_EdmaPowerControl(state, &I2C3_EdmaDriverState);
2129 }
2130
I2C3_Master_EdmaTransmit(uint32_t addr,const uint8_t * data,uint32_t num,bool xfer_pending)2131 static int32_t I2C3_Master_EdmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
2132 {
2133 return I2C_Master_EdmaTransmit(addr, data, num, xfer_pending, &I2C3_EdmaDriverState);
2134 }
2135
I2C3_Master_EdmaReceive(uint32_t addr,uint8_t * data,uint32_t num,bool xfer_pending)2136 static int32_t I2C3_Master_EdmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
2137 {
2138 return I2C_Master_EdmaReceive(addr, data, num, xfer_pending, &I2C3_EdmaDriverState);
2139 }
2140
I2C3_Master_EdmaGetDataCount(void)2141 static int32_t I2C3_Master_EdmaGetDataCount(void)
2142 {
2143 return I2C_Master_EdmaGetDataCount(&I2C3_EdmaDriverState);
2144 }
2145
I2C3_Master_EdmaControl(uint32_t control,uint32_t arg)2146 static int32_t I2C3_Master_EdmaControl(uint32_t control, uint32_t arg)
2147 {
2148 return I2C_Master_EdmaControl(control, arg, &I2C3_EdmaDriverState);
2149 }
2150
I2C3_Master_EdmaGetStatus(void)2151 static ARM_I2C_STATUS I2C3_Master_EdmaGetStatus(void)
2152 {
2153 return I2C_Master_EdmaGetStatus(&I2C3_EdmaDriverState);
2154 }
2155
2156 #endif
2157
2158 #else
2159
2160 static cmsis_i2c_handle_t I2C3_Handle;
2161
2162 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
2163 ARMCC_SECTION("i2c3_interrupt_driver_state")
2164 static cmsis_i2c_interrupt_driver_state_t I2C3_InterruptDriverState = {
2165 #else
2166 static cmsis_i2c_interrupt_driver_state_t I2C3_InterruptDriverState = {
2167 #endif
2168 &I2C3_Resource,
2169 &I2C3_Handle,
2170 };
2171
I2C3_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event)2172 static int32_t I2C3_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event)
2173 {
2174 #ifdef RTE_I2C3_PIN_INIT
2175 RTE_I2C3_PIN_INIT();
2176 #endif
2177 return I2C_InterruptInitialize(cb_event, &I2C3_InterruptDriverState);
2178 }
2179
I2C3_InterruptUninitialize(void)2180 static int32_t I2C3_InterruptUninitialize(void)
2181 {
2182 #ifdef RTE_I2C3_PIN_DEINIT
2183 RTE_I2C3_PIN_DEINIT();
2184 #endif
2185 return I2C_InterruptUninitialize(&I2C3_InterruptDriverState);
2186 }
2187
I2C3_InterruptPowerControl(ARM_POWER_STATE state)2188 static int32_t I2C3_InterruptPowerControl(ARM_POWER_STATE state)
2189 {
2190 return I2C_InterruptPowerControl(state, &I2C3_InterruptDriverState);
2191 }
2192
I2C3_Master_InterruptTransmit(uint32_t addr,const uint8_t * data,uint32_t num,bool xfer_pending)2193 static int32_t I2C3_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
2194 {
2195 return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C3_InterruptDriverState);
2196 }
2197
I2C3_Master_InterruptReceive(uint32_t addr,uint8_t * data,uint32_t num,bool xfer_pending)2198 static int32_t I2C3_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
2199 {
2200 return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C3_InterruptDriverState);
2201 }
2202
I2C3_Slave_InterruptTransmit(const uint8_t * data,uint32_t num)2203 static int32_t I2C3_Slave_InterruptTransmit(const uint8_t *data, uint32_t num)
2204 {
2205 return I2C_Slave_InterruptTransmit(data, num, &I2C3_InterruptDriverState);
2206 }
2207
I2C3_Slave_InterruptReceive(uint8_t * data,uint32_t num)2208 static int32_t I2C3_Slave_InterruptReceive(uint8_t *data, uint32_t num)
2209 {
2210 return I2C_Slave_InterruptReceive(data, num, &I2C3_InterruptDriverState);
2211 }
2212
I2C3_InterruptGetDataCount(void)2213 static int32_t I2C3_InterruptGetDataCount(void)
2214 {
2215 return I2C_InterruptGetDataCount(&I2C3_InterruptDriverState);
2216 }
2217
I2C3_InterruptControl(uint32_t control,uint32_t arg)2218 static int32_t I2C3_InterruptControl(uint32_t control, uint32_t arg)
2219 {
2220 return I2C_InterruptControl(control, arg, &I2C3_InterruptDriverState);
2221 }
2222
I2C3_InterruptGetStatus(void)2223 static ARM_I2C_STATUS I2C3_InterruptGetStatus(void)
2224 {
2225 return I2C_InterruptGetStatus(&I2C3_InterruptDriverState);
2226 }
2227
2228 #endif
2229
2230 ARM_DRIVER_I2C Driver_I2C3 = {I2Cx_GetVersion,
2231 I2Cx_GetCapabilities,
2232 #if (defined(RTE_I2C3_DMA_EN) && RTE_I2C3_DMA_EN)
2233 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
2234 I2C3_Master_EdmaInitialize,
2235 I2C3_Master_EdmaUninitialize,
2236 I2C3_Master_EdmaPowerControl,
2237 I2C3_Master_EdmaTransmit,
2238 I2C3_Master_EdmaReceive,
2239 NULL,
2240 NULL,
2241 I2C3_Master_EdmaGetDataCount,
2242 I2C3_Master_EdmaControl,
2243 I2C3_Master_EdmaGetStatus
2244 #else
2245 I2C3_Master_DmaInitialize,
2246 I2C3_Master_DmaUninitialize,
2247 I2C3_Master_DmaPowerControl,
2248 I2C3_Master_DmaTransmit,
2249 I2C3_Master_DmaReceive,
2250 NULL,
2251 NULL,
2252 I2C3_Master_DmaGetDataCount,
2253 I2C3_Master_DmaControl,
2254 I2C3_Master_DmaGetStatus
2255 #endif
2256 #else
2257 I2C3_InterruptInitialize,
2258 I2C3_InterruptUninitialize,
2259 I2C3_InterruptPowerControl,
2260 I2C3_Master_InterruptTransmit,
2261 I2C3_Master_InterruptReceive,
2262 I2C3_Slave_InterruptTransmit,
2263 I2C3_Slave_InterruptReceive,
2264 I2C3_InterruptGetDataCount,
2265 I2C3_InterruptControl,
2266 I2C3_InterruptGetStatus
2267 #endif
2268 };
2269
2270 #endif
2271
