Searched full:xf (Results 1 – 25 of 236) sorted by relevance
12345678910
20 net_buf_simple_add_u8(buf, (tx->seg_int_step & 0xf) | in bt_mesh_sar_tx_encode()23 0xf) | (tx->unicast_retrans_int_step << 4)); in bt_mesh_sar_tx_encode()24 net_buf_simple_add_u8(buf, (tx->unicast_retrans_int_inc & 0xf) | in bt_mesh_sar_tx_encode()26 net_buf_simple_add_u8(buf, tx->multicast_retrans_int & 0xf); in bt_mesh_sar_tx_encode()34 net_buf_simple_add_u8(buf, (rx->discard_timeout & 0xf) | in bt_mesh_sar_rx_encode()35 ((rx->rx_seg_int_step & 0xf) << 4)); in bt_mesh_sar_rx_encode()45 tx->seg_int_step = (val & 0xf); in bt_mesh_sar_tx_decode()48 tx->unicast_retrans_without_prog_count = (val & 0xf); in bt_mesh_sar_tx_decode()51 tx->unicast_retrans_int_inc = (val & 0xf); in bt_mesh_sar_tx_decode()54 tx->multicast_retrans_int = (val & 0xf); in bt_mesh_sar_tx_decode()[all …]
17 crc ^= ((src[i] >> (4 * (1 - j))) & 0xf); in crc4()37 return crc & 0xF; in crc4()47 index = seed ^ ((src[i] >> (4*(1-j))) & 0xf); in crc4_ti()48 seed = (lookup[index >> 1] >> (1 - (index & 1)) * 4) & 0xf; in crc4_ti()
11 #define XMC4XXX_DMA_REQUEST_SOURCE_MASK 0xf14 #define XMC4XXX_DMA_LINE_MASK 0xf
29 #define DMA_SMARTBOND_TRIG_MUX_NONE 0xF
13 #define XMC4XXX_PORT_MASK 0xf16 #define XMC4XXX_PIN_MASK 0xf19 #define XMC4XXX_ALT_MASK 0xf
13 #define RP2_PINCTRL_GPIO_FUNC_NULL 0xf
18 (((((port) - 'A') & 0xF) << 28) | \
19 #define PSR_VER (0xf << PSR_VER_BIT)24 #define PSR_PIL (0xf << PSR_PIL_BIT)
11 #define XMC4XXX_INTC_PORT_MASK 0xf14 #define XMC4XXX_INTC_PIN_MASK 0xf
15 #define IRQ_DEFAULT_PRIORITY 0xf
44 #define PM1_MASK (0xf << PM1_OFFSET)45 #define PM2_MASK (0xf << PM2_OFFSET)46 #define PM3_MASK (0xf << PM3_OFFSET)47 #define PM4_MASK (0xf << PM4_OFFSET)48 #define PM5_MASK (0xf << PM5_OFFSET)49 #define PM6_MASK (0xf << PM6_OFFSET)50 #define PM7_MASK (0xf << PM7_OFFSET)
32 #define MUX_SEL0_MASK (0xf << MUX_SEL0_OFFSET)33 #define MUX_SEL1_MASK (0xf << MUX_SEL1_OFFSET)34 #define MUX_SEL2_MASK (0xf << MUX_SEL2_OFFSET)35 #define MUX_SEL3_MASK (0xf << MUX_SEL3_OFFSET)36 #define MUX_SEL4_MASK (0xf << MUX_SEL4_OFFSET)37 #define MUX_SEL5_MASK (0xf << MUX_SEL5_OFFSET)38 #define MUX_SEL6_MASK (0xf << MUX_SEL6_OFFSET)39 #define MUX_SEL7_MASK (0xf << MUX_SEL7_OFFSET)
174 default: [0xF, 0xF, 0xFF, 0xF, 0x0] # reset state181 Reset state: 15 (0xF).183 Reset state: 15 (0xF).187 Reset state: 15 (0xF).
26 crc = (crc >> 4) ^ rtable[(crc ^ (data[i] >> 0)) & 0xf]; in lfs_crc()27 crc = (crc >> 4) ^ rtable[(crc ^ (data[i] >> 4)) & 0xf]; in lfs_crc()
11 #define RA_PORT_NUM_MASK 0xf14 #define RA_PIN_NUM_MASK 0xf
46 #define NVME_CAP_HI_REG_DSTRD_MASK (0xF)56 #define NVME_CAP_HI_REG_MPSMIN_MASK (0xF)58 #define NVME_CAP_HI_REG_MPSMAX_MASK (0xF)87 #define NVME_CC_REG_MPS_MASK (0xF)93 #define NVME_CC_REG_IOSQES_MASK (0xF)95 #define NVME_CC_REG_IOCQES_MASK (0xF)125 #define NVME_PMRCAP_REG_PMRWBM_MASK (0xf)300 #define NVME_CTRLR_DATA_SQES_MIN_MASK (0xF)302 #define NVME_CTRLR_DATA_SQES_MAX_MASK (0xF)306 #define NVME_CTRLR_DATA_CQES_MIN_MASK (0xF)[all …]
29 #define SPSR_DAIF_MASK (0xf << SPSR_DAIF_SHIFT)36 #define SPSR_MODE_MASK (0xf)115 #define ID_AA64PFR0_ELX_MASK (0xf)117 #define ID_AA64PFR0_SEL2_MASK (0xf)176 #define SGIR_INTID_MASK (0xf)
16 (((dir & 0x1) << 12) + ((group & 0xf) << 8) + (index & 0xff))20 #define ESPI_NPCX_VW_EX_GROUP_NUM(e) (((e) >> 8) & 0xf)
35 #define MAX_BURST_LEN 0xf /* 16byte data */67 #define CH_STATUS_MASK 0xf68 #define DATA_MASK 0xf
34 tar xf html-output/html-output.tar.xz -C html-output36 tar xf api-coverage/api-coverage.tar.xz -C api-coverage
17 #define MAX44009_MANTISSA_LOW_NIBBLE_MASK 0xf
77 #define ADP5585_DEVICE_ID_MASK 0xF78 #define ADP5585_MAN_ID_MASK 0xF
30 DMA_SMARTBOND_TRIG_MUX_NONE = 0xF
10 #define XMC4XXX_GPIO_DS_MASK 0xf
42 - CONFIG_PLIC_IRQ_AFFINITY_MASK=0xf
