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Searched +full:wkpu +full:- +full:interrupts (Results 1 – 6 of 6) sorted by relevance

/Zephyr-latest/dts/bindings/gpio/
Dnxp,s32-gpio.yaml1 # Copyright 2022-2023 NXP
2 # SPDX-License-Identifier: Apache-2.0
7 The GPIO controller provides the option to route external input pad interrupts
9 the WKPU interrupt controller. By default, GPIO interrupts are routed to the
12 To route external interrupts to the WKPU interrupt controller, the GPIO
15 to route the interrupt from pin 9 of `gpioa` to the WKPU interrupt controller:
17 #include <zephyr/dt-bindings/gpio/nxp-s32-gpio.h>
25 priorities according to application-specific requirements. This is owing to
27 To illustrate, it is plausible to allocate the board's button interrupts to
29 designated for the data-ready interrupt originating from a sensor. This
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/Zephyr-latest/include/zephyr/drivers/interrupt_controller/
Dintc_wkpu_nxp_s32.h2 * Copyright 2023-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
8 * @brief Driver for Wake-up interrupt/event controller in NXP S32 MCUs
14 /** NXP WKPU callback */
18 * @brief NXP WKPU pin activation type
30 * @brief Unset WKPU callback for line
32 * @param dev WKPU device
33 * @param irq WKPU interrupt number
38 * @brief Set WKPU callback for line
40 * @param dev WKPU device
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/Zephyr-latest/dts/arm/nxp/
Dnxp_s32k344_m7.dtsi2 * Copyright 2023-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/clock/nxp_s32k344_clock.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "arm,cortex-m7";
25 compatible = "arm,cortex-m7";
30 compatible = "arm,armv7m-mpu";
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/Zephyr-latest/drivers/interrupt_controller/
DKconfig.nxp_s323 # Copyright 2022-2024 NXP
4 # SPDX-License-Identifier: Apache-2.0
22 Number of SIUL2 external interrupts per controller. This is a SoC
29 Number of SIUL2 external interrupts grouped into a single core
35 bool "Wake-up Unit interrupt controller driver for NXP S32 MCUs"
39 Wake-up Unit interrupt controller driver for NXP S32 MCUs
48 Number of WKPU external and internal sources per controller. This is
/Zephyr-latest/drivers/gpio/
Dgpio_nxp_s32.c2 * Copyright 2022-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/gpio/nxp-s32-gpio.h>
33 #define GPIO_READ(r) sys_read16(config->gpio_base + (r))
34 #define GPIO_WRITE(r, v) sys_write16((v), config->gpio_base + (r))
35 #define PORT_READ(p) sys_read32(config->port_base + SIUL2_MSCR(p))
36 #define PORT_WRITE(p, v) sys_write32((v), config->port_base + SIUL2_MSCR(p))
86 const struct gpio_nxp_s32_config *config = dev->config; in nxp_s32_gpio_configure()
91 return -ENOTSUP; in nxp_s32_gpio_configure()
95 struct gpio_nxp_s32_data *data = dev->data; in nxp_s32_gpio_configure()
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/Zephyr-latest/boards/nxp/mr_canhubk3/doc/
Dindex.rst6 `NXP MR-CANHUBK3`_ is an evaluation board for mobile robotics applications such
8 features an `NXP S32K344`_ general-purpose automotive microcontroller based on
9 an Arm Cortex-M7 core (Lock-Step).
14 - NXP S32K344
15 - Arm Cortex-M7 (Lock-Step), 160 MHz (Max.)
16 - 4 MB of program flash, with ECC
17 - 320 KB RAM, with ECC
18 - Ethernet 100 Mbps, CAN FD, FlexIO, QSPI
19 - 12-bit 1 Msps ADC, 16-bit eMIOS timer
21 - `NXP FS26 Safety System Basis Chip`_
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