| /hal_espressif-3.5.0/components/soc/esp32/include/soc/ |
| D | emac_dma_struct.h | 26 …uint32_t sw_rst : 1; /*When this bit is set the MAC DMA Controller resets the logic and a…
28 …tarts from the end of current descriptor to the start of next descriptor. When the DSL(DESC_SKIP_L…
29 …uint32_t alt_desc_size : 1; /*When set the size of the alternate descriptor increases to 32 byte…
31 …obin arbitration between the Rx DMA and Tx DMA. These bits are valid only when Bit 1 (DA) is reset…
32 …ransfers or not. When set the AHB interface uses only SINGLE INCR4 INCR8 or INCR16 during star…
33 …ue results in undefined behavior. This field is valid and applicable only when USP(USE_SEP_PBL) is…
34 …When set high this bit configures the Rx DMA to use the value configured in Bits[22:17] as PBL. T…
35 …uint32_t pblx8_mode : 1; /*When set high this bit multiplies the programmed PBL value (Bits[2…
36 …uint32_t dmaaddralibea : 1; /*When this bit is set high and the FIXED_BURST bit is 1 the AHB int…
37 …uint32_t dmamixedburst : 1; /*When this bit is set high and the FIXED_BURST bit is low the AHB m…
[all …]
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| D | emac_mac_struct.h | 25 …the beginning of every Transmit frame. The preamble reduction occurs only when the MAC is operatin…
26 …rx : 1; /*When this bit is set the receiver state machine of the MAC is enabled for re…
27 …_t tx : 1; /*When this bit is set the transmit state machine of the MAC is enabled for…
30 …When this bit is set the MAC strips the Pad or FCS field on the incoming frames only if the value…
32 …When this bit is set the MAC attempts only one transmission. When a collision occurs on the MII i…
33 …When this bit is set the MAC calculates the 16-bit one's complement of the one's complement sum o…
34 …uint32_t duplex : 1; /*When this bit is set the MAC operates in the full-duplex mode where…
35 …uint32_t loopback : 1; /*When this bit is set the MAC operates in the loopback mode MII. The…
36 …n : 1; /*When this bit is set the MAC disables the reception of frames when the TX_EN is …
39 …When set high this bit makes the MAC transmitter ignore the MII CRS signal during frame transmiss…
[all …]
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| D | rmt_struct.h | 31 …uint32_t idle_thres: 16; /*In receive mode when no edge is detected on the input si…
36 …uint32_t clk_en: 1; /*This bit is used to control clock.when software config…
50 …ter_thres: 8; /*in receive mode channel0-7 ignore input pulse when the pulse width is …
64 …; /*The interrupt raw bit for channel 0 turns to high level when the transmit proces…
65 …; /*The interrupt raw bit for channel 0 turns to high level when the receive process…
66 …; /*The interrupt raw bit for channel 0 turns to high level when channel 0 detects s…
67 …; /*The interrupt raw bit for channel 1 turns to high level when the transmit proces…
68 …; /*The interrupt raw bit for channel 1 turns to high level when the receive process…
69 …; /*The interrupt raw bit for channel 1 turns to high level when channel 1 detects s…
70 …; /*The interrupt raw bit for channel 2 turns to high level when the transmit proces…
[all …]
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| D | uart_struct.h | 33 …fifo_full: 1; /*This interrupt raw bit turns to high level when receiver receives m…
34 …fifo_empty: 1; /*This interrupt raw bit turns to high level when the amount of data …
35 …rity_err: 1; /*This interrupt raw bit turns to high level when receiver detects th…
36 …m_err: 1; /*This interrupt raw bit turns to high level when receiver detects da…
37 …fifo_ovf: 1; /*This interrupt raw bit turns to high level when receiver receives m…
38 …r_chg: 1; /*This interrupt raw bit turns to high level when receiver detects th…
39 …s_chg: 1; /*This interrupt raw bit turns to high level when receiver detects th…
40 …k_det: 1; /*This interrupt raw bit turns to high level when receiver detects th…
41 …fifo_tout: 1; /*This interrupt raw bit turns to high level when receiver takes more…
42 …_xon: 1; /*This interrupt raw bit turns to high level when receiver receives x…
[all …]
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| D | uhci_struct.h | 32 …uint32_t out_auto_wrback: 1; /*when in link's length is 0 go on to use the next…
44 … /*Set this bit to enable receiver''s ability of crc calculation when crc_en bit in head …
45 …le_eof_en: 1; /*Set this bit to enable to use idle time when the idle time after…
46 … /*Set this bit to enable to use packet_len in packet head when the received data i…
47 …1; /*Set this bit to enable crc calculation for data frame when bit6 in the head pa…
56 …uint32_t rx_start: 1; /*when a separator char has been send it will prod…
57 …uint32_t tx_start: 1; /*when DMA detects a separator char it will produce…
58 …uint32_t rx_hung: 1; /*when DMA takes a lot of time to receive a data …
59 …uint32_t tx_hung: 1; /*when DMA takes a lot of time to read a data from …
60 …uint32_t in_done: 1; /*when a in link descriptor has been completed it w…
[all …]
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| D | timer_group_struct.h | 28 uint32_t alarm_en: 1; /*When set alarm is enabled*/
29 …uint32_t level_int_en: 1; /*When set level type interrupt will be generated during al…
30 …uint32_t edge_int_en: 1; /*When set edge type interrupt will be generated during ala…
32 … uint32_t autoreload: 1; /*When set timer 0/1 auto-reload at alarming is enabled*/
33 …uint32_t increase: 1; /*When set timer 0/1 time-base counter increment. When clea…
34 … uint32_t enable: 1; /*When set timer 0/1 time-base counter is enabled*/
50 uint32_t flashboot_mod_en: 1; /*When set flash boot protection is enabled*/
53 … uint32_t level_int_en: 1; /*When set level type interrupt generation is enabled*/
54 … uint32_t edge_int_en: 1; /*When set edge type interrupt generation is enabled*/
59 uint32_t en: 1; /*When set SWDT is enabled*/
[all …]
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| D | mcpwm_struct.h | 36 * Configure the divisor of PT0_clk, takes effect when PWM timer stops and starts
63 * here and below means the event that happens when the timer equals to period
82 * When set, timer reloading with phase on sync input event is enabled.
91 * generate when toggling the reg_timer_sync_sw bit
99 * Configure the PWM timer's direction at the time sync event occurs when timer mode
201 * Update method for PWM generator time stamp A's active register. When all bits are
202 * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
203 * bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
207 * Update method for PWM generator time stamp B's active register. When all bits are
208 * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
[all …]
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| D | mcpwm_reg.h | 33 * Configure the divisor of PT0_clk, takes effect when PWM timer0 stops and starts
64 * here and below means the event that happens when the timer equals to period
84 * When set, timer reloading with phase on sync input event is enabled.
99 * generate when toggling the reg_timer0_sync_sw bit
113 * Configure the PWM timer0's direction at the time sync event occurs when timer0 mode
145 * Configure the divisor of PT1_clk, takes effect when PWM timer1 stops and starts
176 * here and below means the event that happens when the timer equals to period
196 * When set, timer reloading with phase on sync input event is enabled.
211 * generate when toggling the reg_timer1_sync_sw bit
225 * Configure the PWM timer1's direction at the time sync event occurs when timer1 mode
[all …]
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| D | i2c_struct.h | 49 …uint32_t slave_rw: 1; /*when in slave mode 1：master read slave 0: master write…
50 …uint32_t time_out: 1; /*when I2C takes more than time_out_reg clocks to receive …
51 …uint32_t arb_lost: 1; /*when I2C lost control of SDA line this register changes…
53 …uint32_t slave_addressed: 1; /*when configured as i2c slave and the address send by ma…
54 …uint32_t byte_trans: 1; /*This register changes to high level when one byte is tra…
75 …uint32_t addr: 15; /*when configured as i2c slave this register is used to c…
94 …uint32_t tx_fifo_empty_thrhd:5; /*Config tx_fifo empty threhd value when using apb fifo ac…
96 …uint32_t fifo_addr_cfg_en: 1; /*When this bit is set to 1 then the byte after address re…
97 …uint32_t rx_fifo_rst: 1; /*Set this bit to reset rx fifo when using apb fifo access…
98 …uint32_t tx_fifo_rst: 1; /*Set this bit to reset tx fifo when using apb fifo access…
[all …]
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| /hal_espressif-3.5.0/components/soc/esp32h2/include/soc/ |
| D | uart_struct.h | 29 …_full: 1; /*This interrupt raw bit turns to high level when receiver receives m…
30 …_empty: 1; /*This interrupt raw bit turns to high level when the amount of data …
31 …_err: 1; /*This interrupt raw bit turns to high level when receiver detects a …
32 …r: 1; /*This interrupt raw bit turns to high level when receiver detects a …
33 …_ovf: 1; /*This interrupt raw bit turns to high level when receiver receives m…
34 …g: 1; /*This interrupt raw bit turns to high level when receiver detects th…
35 …g: 1; /*This interrupt raw bit turns to high level when receiver detects th…
36 …t: 1; /*This interrupt raw bit turns to high level when receiver detects a …
37 …_tout: 1; /*This interrupt raw bit turns to high level when receiver takes more…
38 … 1; /*This interrupt raw bit turns to high level when receiver recevies Xon char when uar…
[all …]
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| /hal_espressif-3.5.0/components/soc/esp32c3/include/soc/ |
| D | uart_struct.h | 29 …_full: 1; /*This interrupt raw bit turns to high level when receiver receives m…
30 …_empty: 1; /*This interrupt raw bit turns to high level when the amount of data …
31 …_err: 1; /*This interrupt raw bit turns to high level when receiver detects a …
32 …r: 1; /*This interrupt raw bit turns to high level when receiver detects a …
33 …_ovf: 1; /*This interrupt raw bit turns to high level when receiver receives m…
34 …g: 1; /*This interrupt raw bit turns to high level when receiver detects th…
35 …g: 1; /*This interrupt raw bit turns to high level when receiver detects th…
36 …t: 1; /*This interrupt raw bit turns to high level when receiver detects a …
37 …_tout: 1; /*This interrupt raw bit turns to high level when receiver takes more…
38 … 1; /*This interrupt raw bit turns to high level when receiver recevies Xon char when uar…
[all …]
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| /hal_espressif-3.5.0/components/soc/esp32s3/include/soc/ |
| D | spi_mem_struct.h | 28 … : 1; /*User define command enable. An operation will be triggered when the bit is set. The…
31 … : 1; /*Drive Flash into power down. An operation will be triggered when the bit is set. The…
32 … : 1; /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The…
33 …1; /*Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The…
34 … 1; /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The…
35 …4 bytes data to be programmed). Page program operation will be triggered when the bit is set. The…
36 …Write status register enable. Write status operation will be triggered when the bit is set. The…
37 … 1; /*Read status register-1. Read status operation will be triggered when the bit is set. The…
38 … : 1; /*Read JEDEC ID . Read ID command will be sent when the bit is set. The…
39 … : 1; /*Write flash disable. Write disable command will be sent when the bit is set. The…
[all …]
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| D | mcpwm_struct.h | 36 * Configure the divisor of PT0_clk, takes effect when PWM timer stops and starts
63 * here and below means the event that happens when the timer equals to period
82 * When set, timer reloading with phase on sync input event is enabled.
91 * generate when toggling the reg_timer_sync_sw bit
99 * Configure the PWM timer's direction at the time sync event occurs when timer mode
201 * Update method for PWM generator time stamp A's active register. When all bits are
202 * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
203 * bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
207 * Update method for PWM generator time stamp B's active register. When all bits are
208 * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
[all …]
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| D | mcpwm_reg.h | 33 * Configure the divisor of PT0_clk, takes effect when PWM timer0 stops and starts
64 * here and below means the event that happens when the timer equals to period
84 * When set, timer reloading with phase on sync input event is enabled.
99 * generate when toggling the reg_timer0_sync_sw bit
113 * Configure the PWM timer0's direction at the time sync event occurs when timer0 mode
145 * Configure the divisor of PT1_clk, takes effect when PWM timer1 stops and starts
176 * here and below means the event that happens when the timer equals to period
196 * When set, timer reloading with phase on sync input event is enabled.
211 * generate when toggling the reg_timer1_sync_sw bit
225 * Configure the PWM timer1's direction at the time sync event occurs when timer1 mode
[all …]
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| D | uart_struct.h | 57 * when hardware flow control works.
62 * receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver
87 * This interrupt raw bit turns to high level when receiver receives more data than
92 * This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
97 * This interrupt raw bit turns to high level when receiver detects a parity error in
102 * This interrupt raw bit turns to high level when receiver detects a data frame error
107 * This interrupt raw bit turns to high level when receiver receives more data than
112 * This interrupt raw bit turns to high level when receiver detects the edge change of
117 * This interrupt raw bit turns to high level when receiver detects the edge change of
122 * This interrupt raw bit turns to high level when receiver detects a 0 after the stop
[all …]
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| /hal_espressif-3.5.0/components/bt/host/bluedroid/api/include/api/ |
| D | esp_hidh_api.h | 89 ESP_HIDH_INIT_EVT = 0, /*!< When HID host is inited, the event comes */
90 ESP_HIDH_DEINIT_EVT, /*!< When HID host is deinited, the event comes */
91 ESP_HIDH_OPEN_EVT, /*!< When HID host connection opened, the event comes */
92 ESP_HIDH_CLOSE_EVT, /*!< When HID host connection closed, the event comes */
93 ESP_HIDH_GET_RPT_EVT, /*!< When Get_Report command is called, the event comes */
94 ESP_HIDH_SET_RPT_EVT, /*!< When Set_Report command is called, the event comes */
95 ESP_HIDH_GET_PROTO_EVT, /*!< When Get_Protocol command is called, the event comes */
96 ESP_HIDH_SET_PROTO_EVT, /*!< When Set_Protocol command is called, the event comes */
97 ESP_HIDH_GET_IDLE_EVT, /*!< When Get_Idle command is called, the event comes */
98 ESP_HIDH_SET_IDLE_EVT, /*!< When Set_Idle command is called, the event comes */
[all …]
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| D | esp_hidd_api.h | 112 ESP_HIDD_INIT_EVT = 0, /*!< When HID device is inited, the event comes */
113 ESP_HIDD_DEINIT_EVT, /*!< When HID device is deinited, the event comes */
114 ESP_HIDD_REGISTER_APP_EVT, /*!< When HID device application registered, the event comes */
115 ESP_HIDD_UNREGISTER_APP_EVT, /*!< When HID device application unregistered, the event comes */
116 ESP_HIDD_OPEN_EVT, /*!< When HID device connection to host opened, the event comes */
117 ESP_HIDD_CLOSE_EVT, /*!< When HID device connection to host closed, the event comes */
118 ESP_HIDD_SEND_REPORT_EVT, /*!< When HID device send report to lower layer, the event comes */
119 …ESP_HIDD_REPORT_ERR_EVT, /*!< When HID device report handshanke error to lower layer, the even…
120 …ESP_HIDD_GET_REPORT_EVT, /*!< When HID device receives GET_REPORT request from host, the event…
121 …ESP_HIDD_SET_REPORT_EVT, /*!< When HID device receives SET_REPORT request from host, the event…
[all …]
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| D | esp_spp_api.h | 58 … ESP_SPP_MODE_CB = 0, /*!< When data is coming, a callback will come with data */
68 …ESP_SPP_INIT_EVT = 0, /*!< When SPP is inited, the event comes */
69 …ESP_SPP_UNINIT_EVT = 1, /*!< When SPP is uninited, the event comes…
70 …ESP_SPP_DISCOVERY_COMP_EVT = 8, /*!< When SDP discovery complete, the even…
71 …ESP_SPP_OPEN_EVT = 26, /*!< When SPP Client connection open, the …
72 …ESP_SPP_CLOSE_EVT = 27, /*!< When SPP connection closed, the event…
73 …ESP_SPP_START_EVT = 28, /*!< When SPP server started, the event co…
74 …ESP_SPP_CL_INIT_EVT = 29, /*!< When SPP client initiated a connectio…
75 …ESP_SPP_DATA_IND_EVT = 30, /*!< When SPP connection received data, th…
76 …ESP_SPP_CONG_EVT = 31, /*!< When SPP connection congestion status…
[all …]
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| D | esp_gattc_api.h | 28 …ESP_GATTC_REG_EVT = 0, /*!< When GATT client is registered, the event comes…
29 …ESP_GATTC_UNREG_EVT = 1, /*!< When GATT client is unregistered, the event com…
30 …ESP_GATTC_OPEN_EVT = 2, /*!< When GATT virtual connection is set up, the eve…
31 …ESP_GATTC_READ_CHAR_EVT = 3, /*!< When GATT characteristic is read, the event com…
32 …ESP_GATTC_WRITE_CHAR_EVT = 4, /*!< When GATT characteristic write operation comple…
33 …ESP_GATTC_CLOSE_EVT = 5, /*!< When GATT virtual connection is closed, the eve…
34 …ESP_GATTC_SEARCH_CMPL_EVT = 6, /*!< When GATT service discovery is completed, the e…
35 …ESP_GATTC_SEARCH_RES_EVT = 7, /*!< When GATT service discovery result is got, the …
36 …ESP_GATTC_READ_DESCR_EVT = 8, /*!< When GATT characteristic descriptor read comple…
37 …ESP_GATTC_WRITE_DESCR_EVT = 9, /*!< When GATT characteristic descriptor write compl…
[all …]
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| D | esp_gatts_api.h | 28 … ESP_GATTS_REG_EVT = 0, /*!< When register application id, the event comes */
29 …ESP_GATTS_READ_EVT = 1, /*!< When gatt client request read operation, the eve…
30 …ESP_GATTS_WRITE_EVT = 2, /*!< When gatt client request write operation, the ev…
31 …ESP_GATTS_EXEC_WRITE_EVT = 3, /*!< When gatt client request execute write, the even…
32 ESP_GATTS_MTU_EVT = 4, /*!< When set mtu complete, the event comes */
33 ESP_GATTS_CONF_EVT = 5, /*!< When receive confirm, the event comes */
34 …ESP_GATTS_UNREG_EVT = 6, /*!< When unregister application id, the event comes …
35 … ESP_GATTS_CREATE_EVT = 7, /*!< When create service complete, the event comes */
36 …ESP_GATTS_ADD_INCL_SRVC_EVT = 8, /*!< When add included service complete, the event co…
37 …ESP_GATTS_ADD_CHAR_EVT = 9, /*!< When add characteristic complete, the event come…
[all …]
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| /hal_espressif-3.5.0/components/bt/common/api/include/api/ |
| D | esp_blufi_api.h | 26 …ESP_BLUFI_EVENT_INIT_FINISH = 0, /*<! When BLUFI init complete, this event hap…
27 …ESP_BLUFI_EVENT_DEINIT_FINISH, /*<! When BLUFI deinit complete, this event h…
28 …ESP_BLUFI_EVENT_SET_WIFI_OPMODE, /*<! When Phone set ESP32 wifi operation mode…
29 …ESP_BLUFI_EVENT_BLE_CONNECT, /*<! When Phone connect to ESP32 with BLE, th…
30 …ESP_BLUFI_EVENT_BLE_DISCONNECT, /*<! When Phone disconnect with BLE, this eve…
31 …ESP_BLUFI_EVENT_REQ_CONNECT_TO_AP, /*<! When Phone request ESP32's STA connect t…
32 …ESP_BLUFI_EVENT_REQ_DISCONNECT_FROM_AP, /*<! When Phone request ESP32's STA disconnec…
33 …ESP_BLUFI_EVENT_GET_WIFI_STATUS, /*<! When Phone get ESP32 wifi status, this e…
34 …ESP_BLUFI_EVENT_DEAUTHENTICATE_STA, /*<! When Phone deauthenticate sta from SOFTA…
36 …ESP_BLUFI_EVENT_RECV_STA_BSSID, /*<! When Phone send STA BSSID to ESP32 to co…
[all …]
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| /hal_espressif-3.5.0/components/driver/ |
| D | Kconfig | 10 be shut off when it is not working leading to lower power consumption. However
14 bool "Disable DAC when ADC2 is used on GPIO 25 and 26"
30 If this option is not selected, the MCPWM interrupt will be deferred when the Cache
46 can work without the flash when interrupt is triggered.
48 miss when running inside and out of SPI functions, which may increase
62 access, by add ESP_INTR_FLAG_IRAM when initializing the driver.
70 can work without the flash when interrupt is triggered.
72 miss when running inside and out of SPI functions, which may increase
84 access, by add ESP_INTR_FLAG_IRAM when initializing the driver.
96 (such as when writing to SPI Flash).
[all …]
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| /hal_espressif-3.5.0/components/xtensa/include/ |
| D | xtensa-debug-module.h | 33 #define TRAXCTRL_CNTU (1<<9) //Post-stop-trigger countdown units; selects when DelayCoun…
38 #define TRAXCTRL_PTOWT (1<<16) //Processor Trigger Out (OCD halt) enabled when stop trigge…
39 #define TRAXCTRL_PTOWS (1<<17) //Processor Trigger Out (OCD halt) enabled when trace stop …
40 #define TRAXCTRL_CTOWT (1<<20) //Cross-trigger Out enabled when stop triggered
41 #define TRAXCTRL_CTOWS (1<<21) //Cross-trigger Out enabled when trace stop completes
44 #define TRAXCTRL_ITATV (1<<24) //replaces ATID when in integration mode: ATVALID output
71 …MATCHCTRL_PCMS (1<<31) //PC Match Sense, 0 - match when procs PC is in-range, 1 - match when
90 #define PMCTRL_INTEN (1<<0) // Enables assertion of PerfMonInt output when over…
91 #define PMCTRL_KRNLCNT (1<<3) // Enables counting when CINTLEVEL* >
93 // counts only when CINTLEVEL >TRACELEVEL;
[all …]
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| /hal_espressif-3.5.0/components/wpa_supplicant/src/common/ |
| D | defs.h | 185 * start looking for an access point. This state is entered when a
212 * This state is entered when wpa_supplicant starts scanning for a
220 * This state is entered when wpa_supplicant has found a suitable BSS
230 * This state is entered when wpa_supplicant has found a suitable BSS
232 * with this BSS in ap_scan=1 mode. When using ap_scan=2 mode, this
233 * state is entered when the driver is configured to try to associate
241 * This state is entered when the driver reports that association has
251 * This state is entered when WPA/WPA2 4-Way Handshake is started. In
252 * case of WPA-PSK, this happens when receiving the first EAPOL-Key
254 * when the IEEE 802.1X/EAPOL authentication has been completed.
[all …]
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| /hal_espressif-3.5.0/components/esp_phy/ |
| D | Kconfig | 15 … 2.Because of your board design, each time when you do calibration, the result are too unstable.
23 When using a custom partition table, make sure that PHY data
69 bool "Terminate operation when PHY init data error"
73 If enabled, when an error occurs while the PHY init data is updated,
75 If not enabled, the PHY init data will not be updated when an error occurs.
91 bool "Power down MAC and baseband of Wi-Fi and Bluetooth when PHY is disabled"
96 down when PHY is disabled. Enabling this setting reduces power consumption
101 bool "Reduce PHY TX power when brownout reset"
105 When brownout reset occurs, reduce PHY TX power to keep the code running.
108 bool "Enable USB when phy init"
[all …]
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