Lines Matching full:when
29 …_full: 1; /*This interrupt raw bit turns to high level when receiver receives m…
30 …_empty: 1; /*This interrupt raw bit turns to high level when the amount of data …
31 …_err: 1; /*This interrupt raw bit turns to high level when receiver detects a …
32 …r: 1; /*This interrupt raw bit turns to high level when receiver detects a …
33 …_ovf: 1; /*This interrupt raw bit turns to high level when receiver receives m…
34 …g: 1; /*This interrupt raw bit turns to high level when receiver detects th…
35 …g: 1; /*This interrupt raw bit turns to high level when receiver detects th…
36 …t: 1; /*This interrupt raw bit turns to high level when receiver detects a …
37 …_tout: 1; /*This interrupt raw bit turns to high level when receiver takes more…
38 … 1; /*This interrupt raw bit turns to high level when receiver recevies Xon char when uar…
39 … 1; /*This interrupt raw bit turns to high level when receiver receives Xoff char when ua…
40 …_det: 1; /*This interrupt raw bit turns to high level when receiver detects a …
41 …_done: 1; /*This interrupt raw bit turns to high level when transmitter complet…
42 …_idle_done: 1; /*This interrupt raw bit turns to high level when transmitter has kep…
43 …e: 1; /*This interrupt raw bit turns to high level when transmitter has sen…
44 …parity_err: 1; /*This interrupt raw bit turns to high level when receiver detects a …
45 …frm_err: 1; /*This interrupt raw bit turns to high level when receiver detects a …
46 …clash: 1; /*This interrupt raw bit turns to high level when detects a clash bet…
47 …_char_det: 1; /*This interrupt raw bit turns to high level when receiver detects th…
48 …: 1; /*This interrupt raw bit turns to high level when input rxd edge chan…
55 …l: 1; /*This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena…
56 … 1; /*This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_en…
57 …r: 1; /*This is the status bit for parity_err_int_raw when parity_err_int_ena …
58 …r: 1; /*This is the status bit for frm_err_int_raw when frm_err_int_ena is …
59 …f: 1; /*This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena …
60 …g: 1; /*This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is …
61 …g: 1; /*This is the status bit for cts_chg_int_raw when cts_chg_int_ena is …
62 …t: 1; /*This is the status bit for brk_det_int_raw when brk_det_int_ena is …
63 …t: 1; /*This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena…
64 …n: 1; /*This is the status bit for sw_xon_int_raw when sw_xon_int_ena is s…
65 …f: 1; /*This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is …
66 …t: 1; /*This is the status bit for glitch_det_int_raw when glitch_det_int_ena …
67 …e: 1; /*This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena…
68 …e: 1; /*This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_in…
69 …e: 1; /*This is the status bit for tx_done_int_raw when tx_done_int_ena is …
70 …r: 1; /*This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_en…
71 …r: 1; /*This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_en…
72 …h: 1; /*This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena…
73 …ar_det: 1; /*This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int…
74 … 1; /*This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena…
142 …uint32_t glitch_filt: 8; /*when input pulse width is lower than this value the…
171 … 1; /*Set this bit to enbale transmitter to send NULL when the process of send…
188 … /*1'h1: Force clock on for register. 1'h0: Support clock only when application writes …
189 …mask: 1; /*1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0…
198 …o_full_thrhd: 9; /*It will produce rxfifo_full_int interrupt when receiver receives m…
199 …_empty_thrhd: 9; /*It will produce txfifo_empty_int interrupt when the data amount in …
201 …t_flow_dis: 1; /*Set this bit to stop accumulating idle_cnt when hardware flow contr…
243 …eshold:10; /*The uart is activated from light sleeping mode when the input rxd edge …
250 …uint32_t xoff_threshold: 9; /*When the data amount in Rx-FIFO is more than this re…
258 …uint32_t xon_threshold: 9; /*When the data amount in Rx-FIFO is less than this re…
266 …r of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1…
273 …uint32_t rx_idle_thrhd:10; /*It will produce frame end signal when receiver takes…
284 … 1; /*Set this bit to enable receiver could receive data when the transmitter is …
285 …_tx_en: 1; /*1'h1: enable rs485 transmitter to send data when rs485 receiver line…
326 …ter is used to configure the maximum amount of data that can be received when hardware flow contr…
327 … takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes …
336 …0; /*This register stores the offset address in Tx-FIFO when software writes Tx-…
338 …0; /*This register stores the offset address in Tx-FIFO when Tx-FSM reads data v…
345 …0; /*This register stores the offset address in RX-FIFO when software reads data…
347 …0; /*This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes…