Searched full:vm0 (Results 1 – 14 of 14) sorted by relevance
36 * VM0 | |42 * If the size of VM0 and VM1 are larger than 64KiB, the size of BL1 code/data51 * VM0 | BL2_CODE |57 * If the size of VM0 and VM1 are larger than 64KiB, the size of BL2 code can be59 * of S_DATA, so under non-XIP mode it will not start at the beginning of VM0.67 * VM0 | S_DATA |81 * VM0 | S_CODE | S_DATA |130 /* Secure Code executes from VM0, or XIP from flash via the SIC */140 /* Secure Data stored in VM0. Size defined in flash layout */
98 #define MPC_VM0_BASE_S 0x50083000 /* VM0 Memory Protection Controller Secure base…194 /* VM0 -- 8 MB */
11 vm0:94 execution_location: "vm0"
29 VM0 + an offset the size of the OTP DMA ICS (usually 0x400). This bundle83 On non-virgin boot in CM lifecycle state, RSE checks the start of VM0 for the97 FVP. The preferred solution is to preload to the provisioning bundles into VM0
176 base of VM0, and ``encrypted_dm_provisioning_bundle.bin`` to the base of VM1.181 wait for provisioning bundles to be loaded to VM0 and VM1 in the same way as
8 # This command copies the entire OTP DMA ICS section into VM0.
8 # This command reads 8 words from the OTP TRNG to VM0
8 # This command reads 8 words from VM0 into KMU key slot 8
8 # This command reads 8 words from VM0 into the TRAM key registers
8 # This command reads 8 words from the OTP TRNG to VM0, overwriting the TRAM
8 # This command reads 8 words from the OTP TRNG to VM0, overwriting the TRAM key
55 ICEVA: 'vm0_base_address' # The first (8-byte) word in VM0 is the integrity value
291 /* Enable cacheing, particularly to avoid ECC errors in VM0/1 */ in Reset_Handler()296 /* Set MSP to be in VM0 to start with */ in Reset_Handler()
231 ERROR_MSG("Failed to Enable MPC interrupt for VM0!"); in nvic_interrupt_enable()
