Searched full:usb1 (Results 1 – 25 of 35) sorted by relevance
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| /Zephyr-Core-3.6.0/soc/arm/nxp_imx/rt/ |
| D | soc_rt10xx.c | 188 CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); /* Set I2C source as USB1 PLL 480M */ in clock_init()
193 CLOCK_SetMux(kCLOCK_LpspiMux, 1); /* Set SPI source to USB1 PFD0 720M */ in clock_init()
227 #if DT_NODE_HAS_STATUS(DT_NODELABEL(usb1), okay) && CONFIG_USB_DC_NXP_EHCI in clock_init()
229 DT_PROP_BY_PHANDLE(DT_NODELABEL(usb1), clocks, clock_frequency)); in clock_init()
231 DT_PROP_BY_PHANDLE(DT_NODELABEL(usb1), clocks, clock_frequency)); in clock_init()
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| D | lpm_rt1064.c | 219 /* Init USB1 PLL. This will disable the PLL3 bypass. */ in clock_full_power()
293 /* Deinit USB1 PLL PFD 1 2 3 */ in clock_low_power()
382 /* Read configuration values for usb1 pll */ in imxrt_lpm_init()
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| D | soc_rt11xx.c | 492 #if DT_NODE_HAS_STATUS(DT_NODELABEL(usb1), okay) && CONFIG_USB_DC_NXP_EHCI in clock_init()
494 DT_PROP_BY_PHANDLE(DT_NODELABEL(usb1), clocks, clock_frequency)); in clock_init()
496 DT_PROP_BY_PHANDLE(DT_NODELABEL(usb1), clocks, clock_frequency)); in clock_init()
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| /Zephyr-Core-3.6.0/boards/arm/da1469x_dk_pro/doc/ |
| D | index.rst | 70 via USB1 port on motherboard.
76 * UART RX, via USB1 on motherboard = P0.08
77 * UART TX, via USB1 on motherboard = P0.09
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| /Zephyr-Core-3.6.0/boards/arm/tdk_robokit1/doc/ |
| D | index.rst | 133 Both west flash and west debug commands should correctly work with both USB0 and USB1
155 USB debug port (USB1), USB2 for a serial console, and remaining micro USB for
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| /Zephyr-Core-3.6.0/boards/arm/mimxrt1160_evk/ |
| D | mimxrt1160_evk_cm7.dts | 96 zephyr_udc0: &usb1 {
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| /Zephyr-Core-3.6.0/boards/arm/cyclonev_socdk/ |
| D | cyclonev_socdk.dts | 92 zephyr_udc0: &usb1 {
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| /Zephyr-Core-3.6.0/dts/arm/intel_socfpga_std/ |
| D | socfpga.dtsi | 20 usb = &usb1;
233 usb1: usb@ffb40000 { label
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| /Zephyr-Core-3.6.0/boards/arm/mm_feather/ |
| D | mm_feather.dts | 160 &usb1 {
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| /Zephyr-Core-3.6.0/boards/arm64/nxp_ls1046ardb/doc/ |
| D | index.rst | 37 - One USB1 3.0 port is connected to a Type A host connector.
38 - One USB1 3.0 port is configured as On-The-Go (OTG) with a Micro-AB connector.
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| /Zephyr-Core-3.6.0/boards/arm/mimxrt1170_evk/ |
| D | mimxrt1170_evk_cm7.dts | 144 zephyr_udc0: &usb1 {
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| /Zephyr-Core-3.6.0/soc/arm/nxp_imx/rt5xx/ |
| D | soc.c | 150 /* Make sure USBHS ram buffer and usb1 phy has power up */ in usb_device_clock_init()
182 /* enable usb1 host clock */ in usb_device_clock_init()
192 /* disable usb1 host clock */ in usb_device_clock_init()
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| /Zephyr-Core-3.6.0/boards/arm/teensy4/ |
| D | teensy40.dts | 60 zephyr_udc0: &usb1 {
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| /Zephyr-Core-3.6.0/boards/arm/mm_swiftio/ |
| D | mm_swiftio.dts | 174 &usb1 {
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| /Zephyr-Core-3.6.0/soc/arm/nxp_imx/rt6xx/ |
| D | soc.c | 168 /* enable usb1 host clock */ in usb_device_clock_init()
178 /* disable usb1 host clock */ in usb_device_clock_init()
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| /Zephyr-Core-3.6.0/boards/arm/mimxrt1024_evk/ |
| D | mimxrt1024_evk.dts | 177 zephyr_udc0: &usb1 {
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| /Zephyr-Core-3.6.0/soc/arm/nxp_lpc/lpc55xxx/ |
| D | soc.c | 252 /* enable usb1 host clock */ in clock_init()
261 /* disable usb1 host clock */ in clock_init()
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| /Zephyr-Core-3.6.0/boards/arm/mimxrt1010_evk/ |
| D | mimxrt1010_evk.dts | 149 zephyr_udc0: &usb1 {
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| /Zephyr-Core-3.6.0/boards/arm/mimxrt1015_evk/ |
| D | mimxrt1015_evk.dts | 146 zephyr_udc0: &usb1 {
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| /Zephyr-Core-3.6.0/boards/arm/da14695_dk_usb/doc/ |
| D | index.rst | 68 via USB1 port on motherboard.
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| /Zephyr-Core-3.6.0/dts/bindings/pinctrl/ |
| D | xlnx,pinctrl-zynq.yaml | 141 "usb0", "usb1"]
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| /Zephyr-Core-3.6.0/boards/arm/mimxrt1020_evk/ |
| D | mimxrt1020_evk.dts | 176 zephyr_udc0: &usb1 {
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| /Zephyr-Core-3.6.0/boards/arm/mimxrt1050_evk/ |
| D | mimxrt1050_evk.dts | 270 zephyr_udc0: &usb1 {
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| /Zephyr-Core-3.6.0/boards/arm/mimxrt1064_evk/ |
| D | mimxrt1064_evk.dts | 252 zephyr_udc0: &usb1 {
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| /Zephyr-Core-3.6.0/boards/arm/mimxrt1060_evk/ |
| D | mimxrt1060_evk.dts | 234 zephyr_udc0: &usb1 {
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