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/Zephyr-latest/drivers/ethernet/eth_nxp_enet_qos/
DKconfig2 # SPDX-License-Identifier: Apache-2.0
27 int "Number of tx buffer descriptors"
31 Number of TX buffer descriptors.
34 int "Number of rx buffer descriptors"
38 Number of RX buffer descriptors.
Deth_nxp_enet_qos_mac.c4 * SPDX-License-Identifier: Apache-2.0
43 struct nxp_enet_qos_mac_data *data = dev->data; in eth_nxp_enet_qos_iface_init()
45 net_if_set_link_addr(iface, data->mac_addr.addr, in eth_nxp_enet_qos_iface_init()
46 sizeof(((struct net_eth_addr *)NULL)->addr), NET_LINK_ETHERNET); in eth_nxp_enet_qos_iface_init()
48 if (data->iface == NULL) { in eth_nxp_enet_qos_iface_init()
49 data->iface = iface; in eth_nxp_enet_qos_iface_init()
57 const struct nxp_enet_qos_mac_config *config = dev->config; in eth_nxp_enet_qos_tx()
58 struct nxp_enet_qos_mac_data *data = dev->data; in eth_nxp_enet_qos_tx()
59 enet_qos_t *base = config->base; in eth_nxp_enet_qos_tx()
61 volatile union nxp_enet_qos_tx_desc *tx_desc_ptr = data->tx.descriptors; in eth_nxp_enet_qos_tx()
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/Zephyr-latest/dts/arm/xilinx/
Dzynqmp.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-r.dtsi>
9 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
10 #include <zephyr/dt-bindings/ethernet/xlnx_gem.h>
16 compatible = "xlnx,pinctrl-zynqmp";
19 compatible = "soc-nv-flash";
24 compatible = "mmio-sram";
29 compatible = "zephyr,memory-region", "xlnx,zynq-ocm";
31 zephyr,memory-region = "OCM";
40 interrupt-names = "irq_0";
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Dzynq7000.dtsi3 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-a.dtsi>
8 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
9 #include <zephyr/dt-bindings/ethernet/xlnx_gem.h>
13 interrupt-parent = <&gic>;
16 compatible = "zephyr,memory-region", "xlnx,zynq-ocm";
18 zephyr,memory-region = "OCM_LOW";
22 compatible = "zephyr,memory-region", "xlnx,zynq-ocm";
24 zephyr,memory-region = "OCM_HIGH";
28 compatible = "arm,armv8-timer";
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/Zephyr-latest/dts/bindings/ethernet/
Dsnps,dwcxgmac.yaml2 # SPDX - License - Identifier : Apache - 2.0
9 - name: reset-device.yaml
10 - name: ethernet-controller.yaml
17 max-frame-size:
23 means that normally xgmac will reject any frame above max-frame-size
27 max-speed:
30 - 10
31 - 100
32 - 1000
33 - 2500
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Dxlnx,gem.yaml3 # SPDX-License-Identifier: Apache-2.0
10 include: ethernet-controller.yaml
19 clock-frequency:
23 Specifies the base clock frequency from which the GEM's TX clock
25 clock control register in the CRL_APB. The GEM's TX clock frequency
27 which it will be adjusted at run-time. Therefore, the value of this
29 respective GEM's TX clock - by default, this is the IO PLL.
31 mdc-divider:
42 init-mdio-phy:
45 Activates the management of a PHY associated with the controller in-
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/Zephyr-latest/drivers/ethernet/
Deth_sam_gmac_priv.h3 * SPDX-License-Identifier: Apache-2.0
31 /** Memory alignment of the RX/TX Buffer Descriptor List */
35 #define GMAC_PRIORITY_QUEUE_NUM (GMAC_QUEUE_NUM - 1)
37 BUILD_ASSERT(ARRAY_SIZE(GMAC->GMAC_TBQBAPQ) + 1 == GMAC_QUEUE_NUM,
42 #define GMAC_ACTIVE_PRIORITY_QUEUE_NUM (GMAC_ACTIVE_QUEUE_NUM - 1)
44 /** RX descriptors count for main queue */
46 /** TX descriptors count for main queue */
49 /** RX/TX descriptors count for priority queues */
91 * Receive buffer descriptor bit field definitions
94 /** Buffer ownership, needs to be 0 for the GMAC to write data to the buffer */
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Deth_cyclonev.c2 * SPDX-License-Identifier: Apache-2.0
5 * 3504-0 Universal 10/100/1000 Ethernet MAC (DWC_gmac)
9 * https://github.com/altera-opensource/intel-socfpga-hwlib
71 * /us/en/pdfs/literature/hb/cyclone-v/cv_54001.pdf p. 1252
135 sys_write32(tmpreg, EMAC_GMAC_MAC_ADDR_HIGH_ADDR(p->base_addr, n)); in eth_cyclonev_set_mac_addr()
142 sys_write32(tmpreg, EMAC_GMAC_MAC_ADDR_LOW_ADDR(p->base_addr, n)); in eth_cyclonev_set_mac_addr()
156 return -1; in eth_cyclonev_get_software_reset_status()
158 return EMAC_DMA_MODE_SWR_GET(sys_read32(EMAC_DMAGRP_BUS_MODE_ADDR(p->base_addr))); in eth_cyclonev_get_software_reset_status()
167 * @retval 0 if Reset was successful, -1 otherwise
175 return -1; in eth_cyclonev_software_reset()
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Deth_xlnx_gem_priv.h7 * SPDX-License-Identifier: Apache-2.0
22 #define ETH_XLNX_BUFFER_ALIGNMENT 4 /* RX/TX buffer alignment (in bytes) */
24 /* Buffer descriptor (BD) related defines */
26 /* Receive Buffer Descriptor bits & masks: comp. Zynq-7000 TRM, Table 16-2. */
29 * Receive Buffer Descriptor address word:
30 * [31 .. 02] Mask for effective buffer address -> excludes [1..0]
39 * Receive Buffer Descriptor control word:
47 * [23 .. 22] These bits have different semantics depending on whether RX check-
54 * [15] End-of-frame bit
55 * [14] Start-of-frame bit
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Deth_sam_gmac.c6 * SPDX-License-Identifier: Apache-2.0
12 * This is a zero-copy networking implementation of an Ethernet driver. To
18 * - one shot PHY setup, no support for PHY disconnect/reconnect
19 * - no statistics collection
67 dcache_enabled = (SCB->CCR & SCB_CCR_DC_Msk); in dcache_is_enabled()
76 uint32_t start_addr = addr & (uint32_t)~(GMAC_DCACHE_ALIGNMENT - 1); in dcache_invalidate()
77 uint32_t size_full = size + addr - start_addr; in dcache_invalidate()
89 uint32_t start_addr = addr & (uint32_t)~(GMAC_DCACHE_ALIGNMENT - 1); in dcache_clean()
90 uint32_t size_full = size + addr - start_addr; in dcache_clean()
119 #if CONFIG_NET_BUF_DATA_SIZE * (CONFIG_NET_BUF_RX_COUNT - \
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Deth_xlnx_gem.c5 * SPDX-License-Identifier: Apache-2.0
8 * - Only supports 32-bit addresses in buffer descriptors, therefore
9 * the ZynqMP APU (Cortex-A53 cores) may not be fully supported.
10 * - Hardware timestamps not considered.
11 * - VLAN tags not considered.
12 * - Wake-on-LAN interrupt not supported.
13 * - Send function is not SMP-capable (due to single TX done semaphore).
14 * - Interrupt-driven PHY management not supported - polling only.
15 * - No explicit placement of the DMA memory area(s) in either a
18 * with the Cortex-R5 QEMU target or an actual R5 running without the
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Deth_numaker.c4 * SPDX-License-Identifier: Apache-2.0
64 /* Delay execution for given amount of ticks for SDK-HAL */
74 synopGMAC_write_phy_reg((u32 *)gmacdev->MacBase, addr, reg, data); in mdio_write()
81 synopGMAC_read_phy_reg((u32 *)gmacdev->MacBase, addr, reg, &data); in mdio_read()
108 return -EIO; in reset_phy()
116 gmacdev->LinkState = LINKUP; in reset_phy()
119 gmacdev->LinkState = LINKDOWN; in reset_phy()
121 return -EIO; in reset_phy()
135 return -EIO; in reset_phy()
141 gmacdev->DuplexMode = FULLDUPLEX; in reset_phy()
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Deth_ivshmem_queue.c4 * SPDX-License-Identifier: Apache-2.0
44 q->desc_max_len = vring_desc_len; in eth_ivshmem_queue_init()
45 q->vring_data_max_len = shmem_section_size - vring_header_size; in eth_ivshmem_queue_init()
46 q->vring_header_size = vring_header_size; in eth_ivshmem_queue_init()
47 q->tx.shmem = (void *)tx_shmem; in eth_ivshmem_queue_init()
48 q->rx.shmem = (void *)rx_shmem; in eth_ivshmem_queue_init()
51 vring_init(&q->tx.vring, vring_desc_len, q->tx.shmem, ETH_IVSHMEM_VRING_ALIGNMENT); in eth_ivshmem_queue_init()
52 vring_init(&q->rx.vring, vring_desc_len, q->rx.shmem, ETH_IVSHMEM_VRING_ALIGNMENT); in eth_ivshmem_queue_init()
58 struct vring_used *tmp_used = q->tx.vring.used; in eth_ivshmem_queue_init()
60 q->tx.vring.used = q->rx.vring.used; in eth_ivshmem_queue_init()
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Deth_dwmac.c6 * SPDX-License-Identifier: Apache-2.0
27 * This driver references network data fragments with a zero-copy approach.
30 * and subsequent fragments have to be buswidth-aligned anyway.
38 /* size of pre-allocated packet fragments */
42 * Grace period to wait for TX descriptor/fragment availability.
51 #define DEC_WRAP(idx, size) ({ idx = (idx + size - 1) % size; })
59 #define TXDESC_PHYS_H(idx) hi32(p->tx_descs_phys + (idx) * sizeof(struct dwmac_dma_desc))
60 #define TXDESC_PHYS_L(idx) lo32(p->tx_descs_phys + (idx) * sizeof(struct dwmac_dma_desc))
61 #define RXDESC_PHYS_H(idx) hi32(p->rx_descs_phys + (idx) * sizeof(struct dwmac_dma_desc))
62 #define RXDESC_PHYS_L(idx) lo32(p->rx_descs_phys + (idx) * sizeof(struct dwmac_dma_desc))
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Deth_gecko.c5 * SPDX-License-Identifier: Apache-2.0
12 * - no link monitoring through PHY interrupt
54 eth->NETWORKCTRL &= ~(ETH_NETWORKCTRL_ENBTX | ETH_NETWORKCTRL_ENBRX); in link_configure()
57 val = eth->NETWORKCFG; in link_configure()
61 eth->NETWORKCFG = val; in link_configure()
64 eth->NETWORKCTRL |= (ETH_NETWORKCTRL_ENBTX | ETH_NETWORKCTRL_ENBRX); in link_configure()
69 const struct eth_gecko_dev_cfg *const cfg = dev->config; in eth_gecko_setup_mac()
70 ETH_TypeDef *eth = cfg->regs; in eth_gecko_setup_mac()
74 /* PHY auto-negotiate link parameters */ in eth_gecko_setup_mac()
75 result = phy_gecko_auto_negotiate(&cfg->phy, &link_status); in eth_gecko_setup_mac()
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Deth_stm32_hal.c5 * SPDX-License-Identifier: Apache-2.0
54 #error DTCM for DMA buffer is activated but zephyr,dtcm is not present in dts
73 #define IS_ETH_DMATXDESC_OWN(dma_tx_desc) (dma_tx_desc->DESC3 & \
86 #define IS_ETH_DMATXDESC_OWN(dma_tx_desc) (dma_tx_desc->Status & \
115 BUILD_ASSERT(ETH_STM32_RX_BUF_SIZE % 4 == 0, "Rx buffer size must be a multiple of 4");
159 * so we can compute the index of the given buffer in HAL_ETH_RxLinkCallback()
161 size_t index = (RxBufferPtr)buff - &dma_rx_buffer[0]; in HAL_ETH_RxLinkCallback()
166 header->size = Length; in HAL_ETH_RxLinkCallback()
175 ((struct eth_stm32_rx_buffer_header *)*pEnd)->next = header; in HAL_ETH_RxLinkCallback()
188 &dma_tx_buffer_header[ctx->first_tx_buffer_index]; in HAL_ETH_TxFreeCallback()
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/Zephyr-latest/kernel/
Dmailbox.c4 * SPDX-License-Identifier: Apache-2.0
36 /* stack of unused asynchronous message descriptors */
52 * Do run-time initialization of mailbox object subsystem.
56 /* array of asynchronous message descriptors */ in init_mbox_module()
60 * Create pool of asynchronous message descriptors. in init_mbox_module()
89 z_waitq_init(&mbox->tx_msg_queue); in k_mbox_init()
90 z_waitq_init(&mbox->rx_msg_queue); in k_mbox_init()
91 mbox->lock = (struct k_spinlock) {}; in k_mbox_init()
101 * @brief Check compatibility of sender's and receiver's message descriptors.
103 * Compares sender's and receiver's message descriptors to see if they are
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/Zephyr-latest/drivers/ethernet/dwc_xgmac/
Deth_dwc_xgmac_priv.h7 * SPDX-License-Identifier: Apache-2.0
404 * @brief TX DMA memory area buffer descriptor ring management structure.
406 * The DMA memory area buffer descriptor ring management structure
407 * is used to manage either the TX buffer descriptor array.
411 * or evaluated for the next TX operation.
417 /* Index of the next BD to be used for TX */
419 /* Address of the first descriptor in the TX descriptor ring. This field will be
420 * updated in TX descriptor initialization and consumed by channel initialization.
423 /* Address of the last descriptor in the TX descriptor ring. This field will be
424 * updated in TX descriptor initialization and consumed by channel initialization.
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Deth_dwc_xgmac.c4 * SPDX-License-Identifier: Apache-2.0
19 #define UPDATE_ETH_STATS_TX_PKT_CNT(dev_data, incr) (dev_data->stats.pkts.tx += incr)
20 #define UPDATE_ETH_STATS_RX_PKT_CNT(dev_data, incr) (dev_data->stats.pkts.rx += incr)
21 #define UPDATE_ETH_STATS_TX_BYTE_CNT(dev_data, incr) (dev_data->stats.bytes.sent += incr)
22 #define UPDATE_ETH_STATS_RX_BYTE_CNT(dev_data, incr) (dev_data->stats.bytes.received += incr)
23 #define UPDATE_ETH_STATS_TX_ERROR_PKT_CNT(dev_data, incr) (dev_data->stats.errors.tx += incr)
24 #define UPDATE_ETH_STATS_RX_ERROR_PKT_CNT(dev_data, incr) (dev_data->stats.errors.rx += incr)
25 #define UPDATE_ETH_STATS_TX_DROP_PKT_CNT(dev_data, incr) (dev_data->stats.tx_dropped += incr)
37 * @brief Run-time device configuration data structure.
40 * controller instance which is modifiable at run-time, such as
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/Zephyr-latest/drivers/dma/
Ddma_xilinx_axi_dma.c7 * SPDX-License-Identifier: Apache-2.0
29 /* length of the associated buffer in main memory */
40 /* internal DMA error, e.g., 0-length transfer */
59 /* interrupt timeout - trigger interrupt after X cycles when no transfer. Unit is 125 * */
62 /* irqthreshold - this can be used to generate interrupts after X completed packets */
76 /* DMA ignores completed bit in SG descriptor and overwrites descriptors */
78 /* use AXI fixed burst instead of incrementing burst for TX transfers, e.g., useful for reading a */
84 /* run-stop */
118 /* RS (run-stop) in DMACR is 0 and operations completed; writing tail does nothing */
147 /* in-memory descriptor, read by the DMA, that instructs it how many bits to transfer from which */
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Ddma_mcux_lpc.c2 * Copyright (c) 2020-2023 NXP
4 * SPDX-License-Identifier: Apache-2.0
71 ((DMA_Type *)((const struct dma_mcux_lpc_config *const)(dev)->config)->base)
74 ((struct channel_data *)(&(((struct dma_mcux_lpc_dma_data *)dev->data)->channel_data[ch])))
77 ((dma_handle_t *)(&(DEV_CHANNEL_DATA(dev, ch)->dma_handle)))
79 #define EMPTY_OTRIG -1
84 int ret = -EIO; in nxp_lpc_dma_callback()
86 uint32_t channel = handle->channel; in nxp_lpc_dma_callback()
96 data->busy = DMA_ChannelIsBusy(data->dma_handle.base, channel); in nxp_lpc_dma_callback()
98 if (data->dma_callback) { in nxp_lpc_dma_callback()
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/Zephyr-latest/tests/drivers/ethernet/eth_ivshmem_queue/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
63 zassert_equal_ptr(q1.tx.shmem, shmem_buff[0]); in ZTEST()
65 zassert_equal_ptr(q2.tx.shmem, shmem_buff[1]); in ZTEST()
111 zassert_equal(eth_ivshmem_queue_rx(&q1, &rx_message, &rx_len), -EWOULDBLOCK); in ZTEST()
114 zassert_equal(eth_ivshmem_queue_rx_complete(&q1), -EWOULDBLOCK); in ZTEST()
116 /* TX commit without getting buffer */ in ZTEST()
117 zassert_equal(eth_ivshmem_queue_tx_commit_buff(&q1), -EINVAL); in ZTEST()
119 /* Getting a buffer (without committing) should not modify/overflow the queue */ in ZTEST()
129 /* Fill queue descriptors */ in ZTEST()
137 zassert_equal(queue_tx(&q1, &x, sizeof(x)), -ENOBUFS); in ZTEST()
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/Zephyr-latest/drivers/i2s/
Di2s_mcux_sai.c2 * Copyright 2021,2023-2024 NXP Semiconductor INC.
5 * SPDX-License-Identifier: Apache-2.0
22 #include <zephyr/dt-bindings/clock/imx_ccm.h>
48 * Transfer Control Descriptors (TCDs) in list, and manages the tcdpool.
52 * This indicates the Tx/Rx stream.
56 * application provided buffer is queued to in_queue until loaded to DMA.
57 * when DMA channel is idle, buffer is retrieved from in_queue and loaded
58 * to DMA and queued to out_queue. when DMA completes, buffer is retrieved
62 * driver allocates buffer from slab and loads DMA buffer is queued to
63 * in_queue when DMA completes, buffer is retrieved from in_queue
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/Zephyr-latest/doc/connectivity/usb/device_next/
Dusb_device.rst18 high-speed device controllers are supported. It also provides support for
20 or changing the configuration later. It has built-in support for several USB
29 * :zephyr:code-sample:`usb-hid-keyboard`
31 * :zephyr:code-sample:`uac2-explicit-feedback`
33 * :zephyr:code-sample:`uac2-implicit-feedback`
36 ----------------------------------------
39 configuration ``-DCONF_FILE=usbd_next_prj.conf`` either directly or via
42 * :zephyr:code-sample:`bluetooth_hci_usb`
44 * :zephyr:code-sample:`usb-cdc-acm`
46 * :zephyr:code-sample:`usb-cdc-acm-console`
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/Zephyr-latest/doc/connectivity/networking/
Dnet_config_guide.rst13 Network Buffer Configuration Options
16 The network buffer configuration options control how much data we
28 length data buffer. The :kconfig:option:`CONFIG_NET_BUF_DATA_SIZE`
30 This is the default setting. The default size of the buffer is 128 bytes.
37 the size of the fixed buffer by setting :kconfig:option:`CONFIG_NET_BUF_DATA_SIZE`, and
47 network buffer size is set to 128 bytes.
49 The variable size data buffer feature is marked as experimental as it has not
53 that is needed when dynamically allocating the buffer from the memory pool.
63 as the receive buffer count but for sending.
79 5-tuple that is used when listening or sending network traffic. Each BSD socket in the
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