Home
last modified time | relevance | path

Searched +full:stabilization +full:- +full:time (Results 1 – 8 of 8) sorted by relevance

/Zephyr-latest/dts/bindings/clock/
Drenesas,ra-cgc-subclk.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Renesas RA Sub-Clock
6 compatible: "renesas,ra-cgc-subclk"
8 include: fixed-clock.yaml
11 drive-capability:
15 - 0
16 - 1
17 - 2
18 - 3
20 Sub-Clock Oscillator Drive Capability Switching
[all …]
/Zephyr-latest/doc/project/
Drelease_process.rst6 The Zephyr project releases on a time-based cycle, rather than a feature-driven
10 A time-based release process enables the Zephyr project to provide users with a
12 roughly 4-month release cycle allows the project to coordinate development of
19 - Release tagging procedure:
21 - linear mode on main branch,
22 - release branches for maintenance after release tagging.
23 - Each release period will consist of a development phase followed by a
24 stabilization phase. Release candidates will be tagged during the
25 stabilization phase. During the stabilization phase, only stabilization
29 - Development phase: all changes are considered and merged, subject to
[all …]
/Zephyr-latest/drivers/ieee802154/
DKconfig.b912 # SPDX-License-Identifier: Apache-2.0
21 int "Tx/Rx modes switching delay time (us)"
24 Delay time needed for PLL stabilization during Tx/Rx modes switching.
28 default -50
/Zephyr-latest/drivers/bluetooth/hci/
Dh4_ifx_cyw43xxx.c5 * SPDX-License-Identifier: Apache-2.0
32 /* BT settling time after power on */
36 /* Stabilization delay after FW loading */
60 * This function executes vendor-specific commands sequence to
62 * bt_h4_vnd_setup function must be implemented in vendor-specific HCI
79 /* Re-configure UART */ in bt_hci_uart_set_baudrate()
96 * - To speed up application downloading, the MCU host commands the CYWxxx device in bt_update_controller_baudrate()
100 * In the above command, the xx xx xx xx bytes specify the 32-bit little-endian in bt_update_controller_baudrate()
105 * - The host switches to the new baud rate after receiving the response at the old in bt_update_controller_baudrate()
127 return -ENOMEM; in bt_update_controller_baudrate()
[all …]
/Zephyr-latest/drivers/serial/
Duart_pl011_ambiq.h4 * SPDX-License-Identifier: Apache-2.0
22 get_uart(dev)->cr |= PL011_CR_AMBIQ_CLKEN; in pl011_ambiq_enable_clk()
43 return -EINVAL; in pl011_ambiq_clk_set()
46 get_uart(dev)->cr |= FIELD_PREP(PL011_CR_AMBIQ_CLKSEL, clksel); in pl011_ambiq_clk_set()
95 if (!pRegisterStatus->bValid) { in uart_ambiq_pm_action()
96 return -EPERM; in uart_ambiq_pm_action()
99 /*The resume and suspend actions may be executed back-to-back, in uart_ambiq_pm_action()
100 * so we add a busy wait here for stabilization. in uart_ambiq_pm_action()
110 UARTn(ui32Module)->ILPR = pRegisterStatus->regILPR; in uart_ambiq_pm_action()
111 UARTn(ui32Module)->IBRD = pRegisterStatus->regIBRD; in uart_ambiq_pm_action()
[all …]
/Zephyr-latest/drivers/adc/
Dadc_ite_it8xxx2.c4 * SPDX-License-Identifier: Apache-2.0
32 /* ADC sample time delay (Unit:us) */
38 #define ADC_CHANNEL_OFFSET(ch) ((ch)-CHIP_ADC_CH13-ADC_CHANNEL_SHIFT)
85 * this config will be used at initial time
98 uint8_t channel_id = channel_cfg->channel_id; in adc_it8xxx2_channel_setup()
100 if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) { in adc_it8xxx2_channel_setup()
101 LOG_ERR("Selected ADC acquisition time is not valid"); in adc_it8xxx2_channel_setup()
102 return -EINVAL; in adc_it8xxx2_channel_setup()
109 return -EINVAL; in adc_it8xxx2_channel_setup()
114 channel_id -= ADC_CHANNEL_SHIFT; in adc_it8xxx2_channel_setup()
[all …]
/Zephyr-latest/doc/contribute/
Dcontributor_expectations.rst1 .. _contributor-expectations:
10 - Reviewed more quickly and reviewed more thoroughly. It's easier for reviewers
12 to allocate large blocks of time to review a large PR.
14 - Less wasted work if reviewers or maintainers reject the direction of the
17 - Easier to rebase and merge. Smaller PRs are less likely to conflict with other
20 - Easier to revert if the PR breaks functionality.
32 - Smaller PRs should encompass one self-contained logical change.
34 - When adding a new large feature or API, the PR should address only one part of
38 - PRs should include tests or samples under the following conditions:
40 - Adding new features or functionality.
[all …]
/Zephyr-latest/drivers/clock_control/
Dclock_control_mchp_xec.c4 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
30 * 32KHz period counter minimum for pass/fail: 16-bit
31 * 32KHz period counter maximum for pass/fail: 16-bit
32 * 32KHz duty cycle variation max for pass/fail: 16-bit
33 * 32KHz valid count minimum: 8-bit
99 uint32_t RSVD4[(0x00c0 - 0x0094) / 4];
192 uint8_t core_clk_div; /* Cortex-M4 clock divider (CPU and NVIC) */
208 pcr->SYS_SLP_CTRL = 0U; in pcr_slp_init()
209 SCB->SCR &= ~BIT(2); in pcr_slp_init()
[all …]