Searched full:spi1 (Results 1 – 25 of 516) sorted by relevance
12345678910>>...21
| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/src/ |
| D | test_stm32_clock_configuration.c | 38 static const struct stm32_pclken pclken[] = STM32_DT_CLOCKS(DT_NODELABEL(spi1)); in ZTEST()
49 zassert_true(__HAL_RCC_SPI1_IS_CLK_ENABLED(), "SPI1 gating clock should be on"); in ZTEST()
50 TC_PRINT("SPI1 gating clock on\n"); in ZTEST()
52 if (IS_ENABLED(STM32_SPI_DOMAIN_CLOCK_SUPPORT) && DT_NUM_CLOCKS(DT_NODELABEL(spi1)) > 1) { in ZTEST()
58 TC_PRINT("SPI1 domain clk configured\n"); in ZTEST()
105 zassert_true(!__HAL_RCC_SPI1_IS_CLK_ENABLED(), "SPI1 gating clock should be off"); in ZTEST()
106 TC_PRINT("SPI1 gating clock off\n"); in ZTEST()
|
| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/src/ |
| D | test_stm32_clock_configuration.c | 38 static const struct stm32_pclken pclken[] = STM32_DT_CLOCKS(DT_NODELABEL(spi1)); in ZTEST()
50 zassert_true(__HAL_RCC_SPI1_IS_CLK_ENABLED(), "SPI1 reg_clk should be on"); in ZTEST()
51 TC_PRINT("SPI1 reg_clk on\n"); in ZTEST()
53 if (IS_ENABLED(STM32_SPI_DOMAIN_CLOCK_SUPPORT) && DT_NUM_CLOCKS(DT_NODELABEL(spi1)) > 1) { in ZTEST()
61 TC_PRINT("SPI1 domain_clk on\n"); in ZTEST()
136 TC_PRINT("SPI1 clock freq: %d MHz\n", spi1_actual_clk_freq / (1000*1000)); in ZTEST()
143 zassert_true(!__HAL_RCC_SPI1_IS_CLK_ENABLED(), "SPI1 reg_clk should be off"); in ZTEST()
144 TC_PRINT("SPI1 reg_clk off\n"); in ZTEST()
|
| /Zephyr-latest/boards/shields/buydisplay_2_8_tft_touch_arduino/boards/ |
| D | nrf52840dk_nrf52840.overlay | 7 /* NOTE: spi1 MISO pin is used by the display for the cmd/data line */
8 &spi1 {
|
| /Zephyr-latest/boards/shields/buydisplay_3_5_tft_touch_arduino/boards/ |
| D | nrf52840dk_nrf52840.overlay | 7 /* NOTE: spi1 MISO pin is used by the display for the cmd/data line */
8 &spi1 {
|
| /Zephyr-latest/include/zephyr/dt-bindings/pinctrl/ |
| D | ch32v003-pinctrl.h | 121 #define SPI1_NSS_PC1_0 CH32V003_PINMUX_DEFINE(PC, 1, SPI1, 0)
122 #define SPI1_NSS_PC0_1 CH32V003_PINMUX_DEFINE(PC, 0, SPI1, 1)
123 #define SPI1_SCK_PC5_0 CH32V003_PINMUX_DEFINE(PC, 5, SPI1, 0)
124 #define SPI1_SCK_PC5_1 CH32V003_PINMUX_DEFINE(PC, 5, SPI1, 1)
125 #define SPI1_MISO_PC7_0 CH32V003_PINMUX_DEFINE(PC, 7, SPI1, 0)
126 #define SPI1_MISO_PC7_1 CH32V003_PINMUX_DEFINE(PC, 7, SPI1, 1)
127 #define SPI1_MOSI_PC6_0 CH32V003_PINMUX_DEFINE(PC, 6, SPI1, 0)
128 #define SPI1_MOSI_PC6_1 CH32V003_PINMUX_DEFINE(PC, 6, SPI1, 1)
|
| /Zephyr-latest/tests/drivers/spi/spi_loopback/boards/ |
| D | nucleo_f207zg.overlay | 7 &spi1 {
13 &spi1 {
|
| D | nucleo_f411re.overlay | 7 &spi1 {
13 &spi1 {
|
| D | nucleo_f429zi.overlay | 7 &spi1 {
13 &spi1 {
|
| D | nucleo_h723zg.overlay | 13 /* Define PLL1_Q as SPI1 kernel clock source */
14 &spi1 {
|
| D | adp_xc7k_ae350.overlay | 7 &spi1 {
|
| D | stm32f3_disco.overlay | 7 &spi1 {
|
| D | apard32690_max32690_m4.overlay | 7 arduino_spi: &spi1 {
|
| D | ek_ra2a1.overlay | 6 &spi1 {
|
| D | ek_ra4w1.overlay | 6 &spi1 {
|
| D | emsdp_emsdp_em11d.overlay | 7 &spi1 {
|
| D | fpb_ra6e1.overlay | 6 &spi1 {
|
| /Zephyr-latest/boards/bbc/microbit/ |
| D | board.h | 28 #define EXT_P13_GPIO_PIN 23 /* P13, SPI1 SCK */
29 #define EXT_P14_GPIO_PIN 22 /* P14, SPI1 MISO */
30 #define EXT_P15_GPIO_PIN 21 /* P15, SPI1 MOSI */
|
| /Zephyr-latest/samples/sensor/veaa_x_3/boards/ |
| D | nucleo_h563zi.overlay | 7 /* spi1 sck conflicts with dac1 channel 3 */
8 /delete-node/ &spi1;
|
| /Zephyr-latest/include/zephyr/devicetree/ |
| D | spi.h | 34 * spi1: spi@... {
46 * DT_SPI_HAS_CS_GPIOS(DT_NODELABEL(spi1)) // 1
59 * spi1: spi@... {
71 * DT_SPI_NUM_CS_GPIOS(DT_NODELABEL(spi1)) // 2
86 * spi1: spi@... {
161 * spi1: spi@... {
191 * spi1: spi@... {
|
| /Zephyr-latest/boards/particle/argon/dts/ |
| D | mesh_feather_spi_spi1.dtsi | 7 /* Add SPI support on Particle Mesh via nRF52840 SPI1
31 feather_spi: &spi1 { /* feather SPI */
|
| /Zephyr-latest/boards/particle/xenon/dts/ |
| D | mesh_feather_spi_spi1.dtsi | 7 /* Add SPI support on Particle Mesh via nRF52840 SPI1
31 feather_spi: &spi1 { /* feather SPI */
|
| /Zephyr-latest/tests/boards/nrf/dmm/boards/ |
| D | nrf5340dk_nrf5340_cpuapp.overlay | 3 dut-cache = &spi1;
40 &spi1
|
| /Zephyr-latest/boards/google/icetower/ |
| D | google_icetower.dts | 54 /* SPI1: communication with the AP */
55 &spi1 {
|
| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/ |
| D | spi1_pclk2.overlay | 12 &spi1 {
|
| D | spi1_sysclk.overlay | 12 &spi1 {
|
12345678910>>...21
