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/Zephyr-latest/dts/bindings/spi/
Dnxp,s32-spi.yaml1 # Copyright 2022-2023 NXP
2 # SPDX-License-Identifier: Apache-2.0
4 description: NXP S32 SPI controller
6 compatible: "nxp,s32-spi"
8 include: [spi-controller.yaml, pinctrl-device.yaml]
17 num-cs:
26 pinctrl-0:
29 pinctrl-names:
35 Select if the SPI module is intended to be used in slave mode.
37 spi-sck-cs-delay:
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Dmicrochip,xec-qmspi.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "microchip,xec-qmspi"
8 include: [spi-controller.yaml, pinctrl-device.yaml]
17 description: SPI Port 0 or 1.
19 pinctrl-0:
22 pinctrl-names:
48 description: Delay in system clocks from CS# assertion to first clock edge
53 description: Delay in system clocks from last clock edge to CS# de-assertion
58 description: Delay in system clocks from CS# de-assertion to driving HOLD# and WP#
63 description: Delay in system clocks from CS# de-assertion to CS# assertion
Dmicrochip,xec-qmspi-ldma.yaml3 # SPDX-License-Identifier: Apache-2.0
7 compatible: "microchip,xec-qmspi-ldma"
9 include: [spi-controller.yaml, pinctrl-device.yaml]
30 pinctrl-0:
33 pinctrl-names:
39 QMSPI data lines 1, 2, or 4. 1 data line is full-duplex
40 MOSI and MISO or half-duplex on MOSI only. Lines set to 2
42 Defaults to 1 for full duplex driver's support for full-duplex spi.
44 - 1
45 - 2
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/Zephyr-latest/drivers/fpga/
Dfpga_ice40_bitbang.c5 * SPDX-License-Identifier: Apache-2.0
22 * Note: When loading a bitstream, the iCE40 has a 'quirk' in that the CS
25 * CS polarity is normal (active low). Zephyr's SPI driver model currently
28 * The logical alternative would be to put the CS into GPIO mode, perform 3
29 * separate SPI transfers (inverting CS polarity as necessary) and then
30 * restore the default pinctrl settings. On some higher-end microcontrollers
34 * However, on lower-end microcontrollers, the amount of time that elapses
35 * between SPI transfers does break the iCE40 timing requirements. That
36 * leaves us with the bitbanging option. Of course, on lower-end
40 * in order to bitbang on lower-end microcontrollers, we actually require
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Dfpga_ice40_spi.c4 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/drivers/spi.h>
30 struct fpga_ice40_data *data = dev->data; in fpga_ice40_load()
32 const struct fpga_ice40_config *config = dev->config; in fpga_ice40_load()
35 memcpy(&bus, &config->bus, sizeof(bus)); in fpga_ice40_load()
37 * Disable the automatism for chip select within the SPI driver, in fpga_ice40_load()
41 bus.config.cs.gpio.port = NULL; in fpga_ice40_load()
45 if (data->loaded && crc == data->crc) { in fpga_ice40_load()
46 LOG_WRN("already loaded with image CRC32c: 0x%08x", data->crc); in fpga_ice40_load()
49 key = k_spin_lock(&data->lock); in fpga_ice40_load()
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/Zephyr-latest/dts/bindings/flash_controller/
Drenesas,smartbond-flash-controller.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "renesas,smartbond-flash-controller"
8 include: flash-controller.yaml
11 read-cs-idle-delay:
15 instructions to the flash memory, the SPI bus stays
19 erase-cs-idle-delay:
/Zephyr-latest/include/zephyr/drivers/
Dspi.h4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Public API for SPI drivers and applications
16 * @brief SPI Interface
17 * @defgroup spi_interface SPI Interface
27 #include <zephyr/dt-bindings/spi/spi.h>
39 * @name SPI operational mode
47 /** Get SPI operational mode. */
52 * @name SPI Polarity & Phase Modes
73 * Whatever data is transmitted is looped-back to the receiving buffer of
81 /** Get SPI polarity and phase mode bits. */
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/Zephyr-latest/tests/drivers/spi/spi_loopback/boards/
Dnrf52840dk_nrf52840.overlay4 * SPDX-License-Identifier: Apache-2.0
8 overrun-character = <0x00>;
9 rx-delay = <1>;
10 cs-gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
11 zephyr,pm-device-runtime-auto;
13 compatible = "test-spi-loopback-slow";
15 spi-max-frequency = <500000>;
18 compatible = "test-spi-loopback-fast";
20 spi-max-frequency = <16000000>;
/Zephyr-latest/dts/bindings/memory-controllers/
Drenesas,smartbond-nor-psram.yaml2 # SPDX-License-Identifier: Apache-2.0
8 compatible: "renesas,smartbond-nor-psram"
14 is-ram:
19 dev-size:
25 dev-type:
31 dev-density:
40 dev-id:
46 reset-delay-us:
52 read-cs-idle-min-ns:
56 Min. time, in nanoseconds, the #CS line should remain inactive between
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/Zephyr-latest/samples/drivers/spi_bitbang/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/drivers/spi.h>
23 struct spi_cs_control *cs) in test_basic_write_9bit_words() argument
30 config.cs = *cs; in test_basic_write_9bit_words()
50 struct spi_cs_control *cs) in test_9bit_loopback_partial() argument
57 config.cs = *cs; in test_9bit_loopback_partial()
67 {.buf = buff + (2), .len = (datacount - 2)*stride}, in test_9bit_loopback_partial()
71 {.buf = rxdata, .len = (datacount - 2) * stride}, in test_9bit_loopback_partial()
89 void test_8bit_xfer(const struct device *dev, struct spi_cs_control *cs) in test_8bit_xfer() argument
96 config.cs = *cs; in test_8bit_xfer()
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/Zephyr-latest/samples/drivers/spi_flash_at45/boards/
Dnrf9160dk_nrf9160.overlay4 * SPDX-License-Identifier: Apache-2.0
21 low-power-enable;
27 pinctrl-0 = <&spi3_default_alt>;
28 pinctrl-1 = <&spi3_sleep_alt>;
29 pinctrl-names = "default", "sleep";
30 cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>,
36 spi-max-frequency = <15000000>;
37 jedec-id = [1f 24 00];
39 sector-size = <65536>;
40 block-size = <2048>;
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/Zephyr-latest/boards/shields/semtech_sx1262mb2das/
Dsemtech_sx1262mb2das.overlay3 * SPDX-License-Identifier: Apache-2.0
15 cs-gpios = <&arduino_header 13 GPIO_ACTIVE_LOW>;
20 spi-max-frequency = <16000000>;
22 reset-gpios = <&arduino_header 0 GPIO_ACTIVE_LOW>;
23 busy-gpios = <&arduino_header 9 GPIO_ACTIVE_HIGH>;
24 antenna-enable-gpios = <&arduino_header 14 GPIO_ACTIVE_HIGH>;
25 dio1-gpios = <&arduino_header 11 GPIO_ACTIVE_HIGH>;
26 dio2-tx-enable;
27 tcxo-power-startup-delay-ms = <5>;
/Zephyr-latest/boards/renesas/da1469x_dk_pro/dts/
Dda1469x_dk_pro_psram.overlay4 * SPDX-License-Identifier: Apache-2.0
9 sram-ext = &memc;
17 /* QSPIC settings for the APS6404L-3SQR QSPI PSRAM memory in QPI mode. */
20 is-ram;
21 dev-size = <DT_SIZE_M(64)>;
22 dev-type = <0x5D>;
23 dev-id = <0x0D>;
24 dev-density = <0xE040>;
25 reset-delay-us = <50>;
26 read-cs-idle-min-ns = <18>;
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/Zephyr-latest/tests/drivers/build_all/lora/
Dsx1262.overlay3 * SPDX-License-Identifier: Apache-2.0
8 #address-cells = <1>;
9 #size-cells = <1>;
13 gpio-controller;
15 #gpio-cells = <0x2>;
19 test_spi: spi@33334444 {
20 #address-cells = <1>;
21 #size-cells = <0>;
22 compatible = "vnd,spi";
26 cs-gpios = <&test_gpio 0 0>,
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/Zephyr-latest/drivers/flash/
DKconfig.nor1 # Copyright (c) 2018 Savoir-Faire Linux.
4 # SPDX-License-Identifier: Apache-2.0
7 bool "SPI NOR Flash"
15 select SPI
27 set by the page-size devicetree property) and
29 jedec-id properties in the devicetree jedec,spi-nor node.
35 sfdp-bfp property in devicetree. The size and jedec-id properties are
43 for all supported JESD216-compatible devices.
52 Device is connected to SPI bus, it has to
53 be initialized after SPI driver.
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/Zephyr-latest/tests/subsys/lorawan/frag_decoder/boards/
Dnative_sim.overlay4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/lora/sx126x.h>
13 zephyr,code-partition = &slot0_partition;
21 #address-cells = <1>;
22 #size-cells = <1>;
24 test_spi: spi@33334444 {
25 #address-cells = <1>;
26 #size-cells = <0>;
27 compatible = "vnd,spi";
30 clock-frequency = <2000000>;
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/Zephyr-latest/tests/subsys/lorawan/clock_sync/boards/
Dnative_sim.overlay4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/lora/sx126x.h>
13 zephyr,code-partition = &slot0_partition;
21 #address-cells = <1>;
22 #size-cells = <1>;
24 test_spi: spi@33334444 {
25 #address-cells = <1>;
26 #size-cells = <0>;
27 compatible = "vnd,spi";
30 clock-frequency = <2000000>;
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/Zephyr-latest/subsys/mgmt/ec_host_cmd/backends/
Dec_host_cmd_backend_spi_stm32.c4 * SPDX-License-Identifier: Apache-2.0
7 /* The SPI STM32 backend implements dedicated SPI driver for Host Commands. Unfortunately, the
8 * current SPI API can't be used to handle the host commands communication. The main issues are
9 * unknown command size sent by the host (the SPI transaction sends/receives specific number of
10 * bytes) and need to constant sending status byte (the SPI module is enabled and disabled per
11 * transaction), see https://github.com/zephyrproject-rtos/zephyr/issues/56091.
23 #include <zephyr/drivers/spi.h>
32 /* The default compatible string of a SPI devicetree node has to be replaced with the one
33 * dedicated for Host Commands. It disabled standard SPI driver. For STM32 SPI "st,stm32-spi" has
34 * to be changed to "st,stm32-spi-host-cmd". The remaining "additional" compatible strings should
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/Zephyr-latest/tests/drivers/spi/spi_controller_peripheral/boards/
Dnrf54l15dk_nrf54l15_cpuapp.overlay4 * SPDX-License-Identifier: Apache-2.0
21 low-power-enable;
40 low-power-enable;
52 pinctrl-0 = <&spi22_default_alt>;
53 pinctrl-1 = <&spi22_sleep_alt>;
54 pinctrl-names = "default", "sleep";
55 overrun-character = <0x00>;
56 cs-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
57 zephyr,pm-device-runtime-auto;
58 dut_spi_dt: test-spi-dev@0 {
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Dnrf54h20dk_nrf54h20_cpuapp_fast.overlay4 * SPDX-License-Identifier: Apache-2.0
21 low-power-enable;
40 low-power-enable;
54 compatible = "nordic,nrf-spim";
56 pinctrl-0 = <&spi121_default_alt>;
57 pinctrl-1 = <&spi121_sleep_alt>;
58 pinctrl-names = "default", "sleep";
59 overrun-character = <0x00>;
60 memory-regions = <&dma_fast_region>;
61 cs-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
[all …]
Dnrf54h20dk_nrf54h20_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
21 low-power-enable;
40 low-power-enable;
52 owned-channels = <7>;
56 compatible = "nordic,nrf-spim";
58 pinctrl-0 = <&spi130_default_alt>;
59 pinctrl-1 = <&spi130_sleep_alt>;
60 pinctrl-names = "default", "sleep";
61 overrun-character = <0x00>;
62 cs-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
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/Zephyr-latest/tests/drivers/spi/spi_error_cases/boards/
Dnrf54h20dk_nrf54h20_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
21 low-power-enable;
40 low-power-enable;
55 compatible = "nordic,nrf-spim";
57 pinctrl-0 = <&spi130_default_alt>;
58 pinctrl-1 = <&spi130_sleep_alt>;
59 pinctrl-names = "default", "sleep";
60 overrun-character = <0x00>;
61 cs-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
62 dut_spi_dt: test-spi-dev@0 {
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Dnrf54l15dk_nrf54l15_cpuapp.overlay4 * SPDX-License-Identifier: Apache-2.0
21 low-power-enable;
40 low-power-enable;
52 pinctrl-0 = <&spi22_default_alt>;
53 pinctrl-1 = <&spi22_sleep_alt>;
54 pinctrl-names = "default", "sleep";
55 overrun-character = <0x00>;
56 cs-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
57 dut_spi_dt: test-spi-dev@0 {
58 compatible = "vnd,spi-device";
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Dnrf54h20dk_nrf54h20_cpuapp_fast.overlay4 * SPDX-License-Identifier: Apache-2.0
21 low-power-enable;
40 low-power-enable;
54 compatible = "nordic,nrf-spim";
56 pinctrl-0 = <&spi121_default_alt>;
57 pinctrl-1 = <&spi121_sleep_alt>;
58 pinctrl-names = "default", "sleep";
59 overrun-character = <0x00>;
60 memory-regions = <&dma_fast_region>;
61 cs-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
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/Zephyr-latest/soc/atmel/sam0/common/
DKconfig.saml2x2 # SPDX-License-Identifier: Apache-2.0
11 These can be mitigated by inserting a small delay during the early boot
79 As detailed in DS70005356C, LoRa radio SPI pins do not have pull-ups,
80 so when the radio is not in use, it's important that CS is kept high,
83 keeping nRST pin low. When enabling this option, both CS and nRST will

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