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/Zephyr-Core-3.5.0/dts/bindings/spi/
Dnxp,s32-spi.yaml1 # Copyright 2022-2023 NXP
2 # SPDX-License-Identifier: Apache-2.0
4 description: NXP S32 SPI controller
6 compatible: "nxp,s32-spi"
8 include: [spi-controller.yaml, pinctrl-device.yaml]
17 num-cs:
26 pinctrl-0:
29 pinctrl-names:
35 Select if the SPI module is intended to be used in slave mode.
37 spi-sck-cs-delay:
[all …]
Dmicrochip,xec-qmspi.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "microchip,xec-qmspi"
8 include: [spi-controller.yaml, pinctrl-device.yaml]
17 description: SPI Port 0 or 1.
19 pinctrl-0:
22 pinctrl-names:
48 description: Delay in system clocks from CS# assertion to first clock edge
53 description: Delay in system clocks from last clock edge to CS# de-assertion
58 description: Delay in system clocks from CS# de-assertion to driving HOLD# and WP#
63 description: Delay in system clocks from CS# de-assertion to CS# assertion
Dmicrochip,xec-qmspi-ldma.yaml3 # SPDX-License-Identifier: Apache-2.0
7 compatible: "microchip,xec-qmspi-ldma"
9 include: [spi-controller.yaml, pinctrl-device.yaml]
30 pinctrl-0:
33 pinctrl-names:
39 QMSPI data lines 1, 2, or 4. 1 data line is full-duplex
40 MOSI and MISO or half-duplex on MOSI only. Lines set to 2
42 Defaults to 1 for full duplex driver's support for full-duplex spi.
44 - 1
45 - 2
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/Zephyr-Core-3.5.0/dts/bindings/flash_controller/
Drenesas,smartbond-flash-controller.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "renesas,smartbond-flash-controller"
8 include: flash-controller.yaml
11 read-cs-idle-delay:
15 instructions to the flash memory, the SPI bus stays
19 erase-cs-idle-delay:
/Zephyr-Core-3.5.0/drivers/fpga/
Dfpga_ice40.c4 * SPDX-License-Identifier: Apache-2.0
18 #include <zephyr/drivers/spi.h>
24 * Note: When loading a bitstream, the iCE40 has a 'quirk' in that the CS
27 * CS polarity is normal (active low). Zephyr's SPI driver model currently
30 * The logical alternative would be to put the CS into GPIO mode, perform 3
31 * separate SPI transfers (inverting CS polarity as necessary) and then
32 * restore the default pinctrl settings. On some higher-end microcontrollers
36 * However, on lower-end microcontrollers, the amount of time that elapses
37 * between SPI transfers does break the iCE40 timing requirements. That
38 * leaves us with the bitbanging option. Of course, on lower-end
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/Zephyr-Core-3.5.0/include/zephyr/drivers/
Dspi.h4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Public API for SPI drivers and applications
16 * @brief SPI Interface
17 * @defgroup spi_interface SPI Interface
25 #include <zephyr/dt-bindings/spi/spi.h>
37 * @name SPI operational mode
47 * @name SPI Polarity & Phase Modes
68 * Whatever data is transmitted is looped-back to the receiving buffer of
81 * @name SPI Transfer modes (host controller dependent)
89 * @name SPI word size
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/Zephyr-Core-3.5.0/boards/shields/x_nucleo_idb05a1/
Dx_nucleo_idb05a1.overlay4 * SPDX-License-Identifier: Apache-2.0
8 cs-gpios = <&arduino_header 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* A1 */
10 spbtle_rf_x_nucleo_idb05a1: spbtle-rf@0 {
11 compatible = "zephyr,bt-hci-spi";
13 reset-gpios = <&arduino_header 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* D7 */
14 irq-gpios = <&arduino_header 0 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* A0 */
15 spi-max-frequency = <2000000>;
16 controller-data-delay-us = <0>; /* No need for extra delay for BlueNRG-MS */
/Zephyr-Core-3.5.0/tests/drivers/spi/spi_loopback/boards/
Dnrf52840dk_nrf52840.overlay4 * SPDX-License-Identifier: Apache-2.0
8 overrun-character = <0x00>;
9 rx-delay = <1>;
10 cs-gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
12 compatible = "test-spi-loopback-slow";
14 spi-max-frequency = <500000>;
17 compatible = "test-spi-loopback-fast";
19 spi-max-frequency = <16000000>;
/Zephyr-Core-3.5.0/samples/drivers/spi_bitbang/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/drivers/spi.h>
23 struct spi_cs_control *cs) in test_basic_write_9bit_words() argument
30 config.cs = *cs; in test_basic_write_9bit_words()
50 struct spi_cs_control *cs) in test_9bit_loopback_partial() argument
57 config.cs = *cs; in test_9bit_loopback_partial()
67 {.buf = buff + (2), .len = (datacount - 2)*stride}, in test_9bit_loopback_partial()
71 {.buf = rxdata, .len = (datacount - 2) * stride}, in test_9bit_loopback_partial()
89 void test_8bit_xfer(const struct device *dev, struct spi_cs_control *cs) in test_8bit_xfer() argument
96 config.cs = *cs; in test_8bit_xfer()
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/Zephyr-Core-3.5.0/samples/drivers/spi_flash_at45/boards/
Dnrf9160dk_nrf9160.overlay4 * SPDX-License-Identifier: Apache-2.0
21 low-power-enable;
27 pinctrl-0 = <&spi3_default_alt>;
28 pinctrl-1 = <&spi3_sleep_alt>;
29 pinctrl-names = "default", "sleep";
30 cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>,
36 spi-max-frequency = <15000000>;
37 jedec-id = [1f 24 00];
39 sector-size = <65536>;
40 block-size = <2048>;
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/Zephyr-Core-3.5.0/boards/shields/semtech_sx1262mb2das/
Dsemtech_sx1262mb2das.overlay3 * SPDX-License-Identifier: Apache-2.0
15 cs-gpios = <&arduino_header 13 GPIO_ACTIVE_LOW>;
20 spi-max-frequency = <16000000>;
22 reset-gpios = <&arduino_header 0 GPIO_ACTIVE_LOW>;
23 busy-gpios = <&arduino_header 9 GPIO_ACTIVE_HIGH>;
24 antenna-enable-gpios = <&arduino_header 14 GPIO_ACTIVE_HIGH>;
25 dio1-gpios = <&arduino_header 11 GPIO_ACTIVE_HIGH>;
26 dio2-tx-enable;
27 tcxo-power-startup-delay-ms = <5>;
/Zephyr-Core-3.5.0/drivers/flash/
DKconfig.nor1 # Copyright (c) 2018 Savoir-Faire Linux.
2 # SPDX-License-Identifier: Apache-2.0
5 bool "SPI NOR Flash"
11 select SPI
24 jedec-id properties in the devicetree jedec,spi-nor node.
30 sfdp-bfp property in devicetree. The size and jedec-id properties are
38 for all supported JESD216-compatible devices.
47 Device is connected to SPI bus, it has to
48 be initialized after SPI driver.
51 int "Delay time in us"
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/Zephyr-Core-3.5.0/subsys/mgmt/ec_host_cmd/backends/
Dec_host_cmd_backend_spi_stm32.c4 * SPDX-License-Identifier: Apache-2.0
7 /* The SPI STM32 backend implements dedicated SPI driver for Host Commands. Unfortunately, the
8 * current SPI API can't be used to handle the host commands communication. The main issues are
9 * unknown command size sent by the host (the SPI transaction sends/receives specific number of
10 * bytes) and need to constant sending status byte (the SPI module is enabled and disabled per
11 * transaction), see https://github.com/zephyrproject-rtos/zephyr/issues/56091.
22 #include <zephyr/drivers/spi.h>
28 /* The default compatible string of a SPI devicetree node has to be replaced with the one
29 * dedicated for Host Commands. It disabled standard SPI driver. For STM32 SPI "st,stm32-spi" has
30 * to be changed to "st,stm32-spi-host-cmd". The remaining "additional" compatible strings should
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/Zephyr-Core-3.5.0/soc/arm/atmel_sam0/common/
DKconfig.saml2x2 # SPDX-License-Identifier: Apache-2.0
11 These can be mitigated by inserting a small delay during the early boot
81 As detailed in DS70005356C, LoRa radio SPI pins do not have pull-ups,
82 so when the radio is not in use, it's important that CS is kept high,
85 keeping nRST pin low. When enabling this option, both CS and nRST will
/Zephyr-Core-3.5.0/drivers/bluetooth/hci/
Dspi.c1 /* spi.c - SPI based Bluetooth driver */
8 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/drivers/spi.h>
50 /* Max SPI buffer length for transceive operations.
53 * required by the SPI slave, as the legacy spi_transceive requires both RX/TX
57 #define SPI_MAX_MSG_LEN 255 /* As defined by X-NUCLEO-IDB04A1 BSP */
65 #define MAX_MTU (SPI_MAX_MSG_LEN - H4_HDR_SIZE - BT_L2CAP_HDR_SIZE - BT_HCI_ACL_HDR_SIZE)
133 /* In case of BlueNRG-MS, it is necessary to prevent SPI driver to release CS,
134 * and instead, let current driver manage CS release. see kick_cs()/release_cs()
204 * All is done through its CS line:
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/Zephyr-Core-3.5.0/drivers/espi/
Despi_saf_mchp_xec.c5 * SPDX-License-Identifier: Apache-2.0
20 /* SAF EC Portal read/write flash access limited to 1-64 bytes */
44 * Delay before first Poll-1 command after suspend in 20 ns units
46 * Add delay between Poll STATUS1 commands in 20 ns units.
72 static inline void mchp_saf_cs_descr_wr(MCHP_SAF_HW_REGS *regs, uint8_t cs, in mchp_saf_cs_descr_wr() argument
75 regs->SAF_CS_OP[cs].OP_DESCR = val; in mchp_saf_cs_descr_wr()
78 static inline void mchp_saf_poll2_mask_wr(MCHP_SAF_HW_REGS *regs, uint8_t cs, in mchp_saf_poll2_mask_wr() argument
81 LOG_DBG("%s cs: %d mask %x", __func__, cs, val); in mchp_saf_poll2_mask_wr()
82 if (cs == 0) { in mchp_saf_poll2_mask_wr()
83 regs->SAF_CS0_CFG_P2M = val; in mchp_saf_poll2_mask_wr()
[all …]
Despi_saf_mchp_xec_v2.c5 * SPDX-License-Identifier: Apache-2.0
17 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
27 /* SAF EC Portal read/write flash access limited to 1-64 bytes */
61 * Delay before first Poll-1 command after suspend in 20 ns units
63 * Add delay between Poll STATUS1 commands in 20 ns units.
96 static inline void mchp_saf_cs_descr_wr(struct mchp_espi_saf *regs, uint8_t cs, in mchp_saf_cs_descr_wr() argument
99 regs->SAF_CS_OP[cs].OP_DESCR = val; in mchp_saf_cs_descr_wr()
102 static inline void mchp_saf_poll2_mask_wr(struct mchp_espi_saf *regs, uint8_t cs, in mchp_saf_poll2_mask_wr() argument
105 LOG_DBG("%s cs: %d mask %x", __func__, cs, val); in mchp_saf_poll2_mask_wr()
106 if (cs == 0) { in mchp_saf_poll2_mask_wr()
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/Zephyr-Core-3.5.0/boards/arm/mimxrt1062_fmurt6/
Dmimxrt1062_fmurt6.dts2 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include "mimxrt1062_fmurt6-pinctrl.dtsi"
11 #include <zephyr/dt-bindings/pwm/pwm.h>
25 telem4-gps2 = &lpuart5;
29 zephyr,flash-controller = &s26ks512s0;
31 zephyr,code-partition = &slot0_partition;
36 zephyr,shell-uart = &lpuart7;
41 compatible = "gpio-leds";
42 green_led: led-1 {
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/Zephyr-Core-3.5.0/tests/drivers/build_all/input/
Dapp.overlay4 * SPDX-License-Identifier: Apache-2.0
9 #address-cells = <1>;
10 #size-cells = <1>;
14 gpio-controller;
16 #gpio-cells = <0x2>;
20 gpio-keys {
21 compatible = "gpio-keys";
22 debounce-interval-ms = <30>;
29 qdec-gpio {
30 compatible = "gpio-qdec";
[all …]
/Zephyr-Core-3.5.0/drivers/spi/
Dspi_context.h4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Private API for SPI drivers
16 #include <zephyr/drivers/spi.h>
81 return !!(ctx->config == config); in spi_context_configured()
86 return (ctx->config->operation & SPI_OP_MODE_SLAVE); in spi_context_is_slave()
95 if ((spi_cfg->operation & SPI_LOCK_ON) && in spi_context_lock()
96 (k_sem_count_get(&ctx->lock) == 0) && in spi_context_lock()
97 (ctx->owner == spi_cfg)) { in spi_context_lock()
101 k_sem_take(&ctx->lock, K_FOREVER); in spi_context_lock()
102 ctx->owner = spi_cfg; in spi_context_lock()
[all …]
Dspi_nxp_s32.c2 * Copyright 2022-2023 NXP
4 * SPDX-License-Identifier: Apache-2.0
15 struct spi_context *ctx = &data->ctx; in spi_nxp_s32_last_packet()
17 if (ctx->tx_count <= 1U && ctx->rx_count <= 1U) { in spi_nxp_s32_last_packet()
18 if (!spi_context_tx_on(ctx) && (data->transfer_len == ctx->rx_len)) { in spi_nxp_s32_last_packet()
22 if (!spi_context_rx_on(ctx) && (data->transfer_len == ctx->tx_len)) { in spi_nxp_s32_last_packet()
26 if ((ctx->rx_len == ctx->tx_len) && (data->transfer_len == ctx->tx_len)) { in spi_nxp_s32_last_packet()
41 const struct spi_nxp_s32_config *config = dev->config; in spi_nxp_s32_transfer_next_packet()
42 struct spi_nxp_s32_data *data = dev->data; in spi_nxp_s32_transfer_next_packet()
48 data_cb = config->cb; in spi_nxp_s32_transfer_next_packet()
[all …]
/Zephyr-Core-3.5.0/boards/arm/efr32_thunderboard/
Dthunderboard.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/input/input-event-codes.h>
11 zephyr,bt-c2h-uart = &usart1;
13 zephyr,shell-uart = &usart1;
19 compatible = "gpio-leds";
27 compatible = "gpio-keys";
35 wake_up_trigger: gpio-wake-up {
36 compatible = "silabs,gecko-wake-up-trigger";
42 compatible = "regulator-fixed";
44 regulator-name = "sw_sensor_enable";
[all …]
/Zephyr-Core-3.5.0/boards/arm/vmu_rt1170/
Dvmu_rt1170.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include <zephyr/dt-bindings/led/led.h>
30 zephyr,shell-uart = &lpuart1;
32 zephyr,flash-controller = &mx25um51345g;
34 zephyr,code-partition = &slot0_partition;
38 reg-3v3-sdcard {
39 compatible = "regulator-fixed";
40 regulator-name = "reg-3v3-sdcard";
41 enable-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
[all …]
/Zephyr-Core-3.5.0/dts/x86/intel/
Dalder_lake.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/pcie/pcie.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "intel,alder-lake";
21 d-cache-line-size = <64>;
34 #address-cells = <1>;
[all …]
/Zephyr-Core-3.5.0/boards/arm/rddrone_fmuk66/
Drddrone_fmuk66.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include <zephyr/dt-bindings/pwm/pwm.h>
11 #include "rddrone_fmuk66-pinctrl.dtsi"
21 pwm-led0 = &red_pwm_led;
22 pwm-led1 = &green_pwm_led;
23 pwm-led2 = &blue_pwm_led;
25 red-pwm-led = &red_pwm_led;
26 green-pwm-led = &green_pwm_led;
27 blue-pwm-led = &blue_pwm_led;
[all …]

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