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/Zephyr-latest/tests/drivers/spi/spi_controller_peripheral/
DKconfig2 # SPDX-License-Identifier: Apache-2.0
5 int "SPI mode"
8 SPI mode value (clock polarity and phase) used in the test.
9 0: CPOL 0 (Active high), CPHA 0 (leading)
10 1: CPOL 0 (Active high), CPHA 1 (trailing)
11 2: CPOL 1 (Active low), CPHA 0 (leading)
12 3: CPOL 1 (Active low), CPHA 1 (trailing)
DREADME.txt1 In this test suite two instances of the SPI peripheral are connected together.
2 One SPI instance works as a controller, second one is configured as a peripheral.
3 In each test, both instances get identical configuration (CPOL, CPHA, bitrate, etc.).
6 1. spi22-SPIM_SCK connected with spi21-SPIS_SCK,
7 2. spi22-SPIM_MISO connected with spi21-SPIS_MISO,
8 3. spi22-SPIM_MOSI connected with spi21-SPIS_MOSI,
9 4. spi22-cs-gpios connected with spi21-SPIS_CSN.
/Zephyr-latest/boards/shields/x_nucleo_wb05kn1/
Dx_nucleo_wb05kn1_spi.overlay4 * SPDX-License-Identifier: Apache-2.0
9 zephyr,bt-hci = &hci_spi;
14 cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */
17 compatible = "st,hci-spi-v2";
19 reset-gpios = <&arduino_header 13 GPIO_ACTIVE_LOW>; /* D7 */
20 irq-gpios = <&arduino_header 0 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* A0 */
21 spi-cpol; /* CPOL=1 */
22 spi-cpha; /* CPHA=1 */
23 spi-hold-cs;
24 spi-max-frequency = <DT_FREQ_M(8)>; /* the maximum supported SPI speed */
[all …]
/Zephyr-latest/dts/bindings/wifi/
Dnordic,nrf70-qspi.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: This is a representation of the nRF70 Wi-Fi chip.
8 on-bus: qspi
11 qspi-frequency:
20 qspi-quad-mode:
24 SPI mode (2 IO lines - MOSI & MISO).
26 qspi-rx-delay:
30 Number of clock cycles from the rising edge of the SPI clock
33 qspi-cpha:
36 Set to indicate phase starts with asserted half-phase (CPHA=1).
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/Zephyr-latest/dts/bindings/sdhc/
Dzephyr,sdhc-spi-slot.yaml1 description: Generic Zephyr SPI based SDHC controller
3 compatible: "zephyr,sdhc-spi-slot"
5 include: [spi-device.yaml]
8 power-delay-ms:
12 Time in ms for SPI SDHC to delay when toggling power to the SD card. This
16 spi-clock-mode-cpol:
19 Clock polarity to use for SPI SDHC. Some cards respond properly
22 spi-clock-mode-cpha:
26 on the clock's polarity. When mode-cpol is set and this option as well,
30 pwr-gpios:
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/Zephyr-latest/dts/bindings/mtd/
Dnordic,qspi-nor.yaml2 # SPDX-License-Identifier: Apache-2.0
7 compatible: "nordic,qspi-nor"
9 include: [base.yaml, "jedec,spi-nor-common.yaml"]
11 on-bus: qspi
17 jedec-id:
23 The size in bits. Set this or size-in-bytes, but not both.
25 size-in-bytes:
31 quad-enable-requirements:
37 - "fastread" # Single data line SPI, FAST_READ (0x0B)
38 - "read2o" # Dual data line SPI, READ2O (0x3B)
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/Zephyr-latest/samples/subsys/fs/fs_sample/boards/
Dnucleo_f429zi.overlay2 * Copyright (c) 2023 Łukasz Hejnak (LeHack) <lehack-ghub@lehack.pl>
4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "zephyr,sdhc-spi-slot";
13 compatible = "zephyr,sdmmc-disk";
14 disk-name = "SD";
17 spi-max-frequency = <25000000>;
18 spi-clock-mode-cpol;
19 spi-clock-mode-cpha;
/Zephyr-latest/soc/microchip/mec/
DKconfig5 # SPDX-License-Identifier: Apache-2.0
16 which generates an SPI image with TAG, Header, and firmware binary. This
18 Boot-ROM. Use the full Microchip SPI image generator program for
19 authentication and all other Boot-ROM loader features. Refer to the MCHP
30 prompt "Clock rate to use for SPI flash"
33 This selects the SPI clock frequency that will be used for loading
37 bool "SPI flash clock rate of 12 MHz"
40 bool "SPI flash clock rate of 16 MHz"
43 bool "SPI flash clock rate of 24 MHz"
46 bool "SPI flash clock rate of 48 MHz"
[all …]
/Zephyr-latest/drivers/spi/
Dspi_sedi.c4 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/drivers/spi.h>
11 #include <zephyr/drivers/spi/rtio.h>
40 struct spi_sedi_data *data = dev->data; in spi_sedi_configure()
41 const struct spi_sedi_config *info = dev->config; in spi_sedi_configure()
42 uint32_t word_size, cpol, cpha, loopback; in spi_sedi_configure() local
44 if (spi_context_configured(&data->ctx, config) == true) { in spi_sedi_configure()
48 word_size = SPI_WORD_SIZE_GET(config->operation); in spi_sedi_configure()
49 sedi_spi_control(info->spi_device, SEDI_SPI_IOCTL_DATA_WIDTH, in spi_sedi_configure()
52 /* CPOL and CPHA */ in spi_sedi_configure()
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Dspi_numaker.c2 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/drivers/spi/rtio.h>
26 SPI_T *spi; member
42 * CPOL/CPHA = 0/0 --> SPI_MODE_0
43 * CPOL/CPHA = 0/1 --> SPI_MODE_1
44 * CPOL/CPHA = 1/0 --> SPI_MODE_2
45 * CPOL/CPHA = 1/1 --> SPI_MODE_3
58 struct spi_numaker_data *data = dev->data; in spi_numaker_configure()
59 const struct spi_numaker_config *dev_cfg = dev->config; in spi_numaker_configure()
62 if (spi_context_configured(&data->ctx, config)) { in spi_numaker_configure()
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Dspi_xec_qmspi.c4 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/drivers/spi.h>
16 #include <zephyr/drivers/spi/rtio.h>
58 REG8(&regs->TX_FIFO) = data8; in txb_wr8()
63 return REG8(&regs->RX_FIFO); in rxb_rd8()
87 qmode = regs->MODE & ~(MCHP_QMSPI_M_FDIV_MASK); in qmspi_set_frequency()
89 regs->MODE = qmode; in qmspi_set_frequency()
93 * SPI signalling mode: CPOL and CPHA
94 * CPOL = 0 is clock idles low, 1 is clock idle high
99 * SPI Mode nomenclature:
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Dspi_xec_qmspi_ldma.c4 * SPDX-License-Identifier: Apache-2.0
18 #include <zephyr/drivers/spi.h>
19 #include <zephyr/drivers/spi/rtio.h>
20 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
21 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
33 /* MEC172x QMSPI controller SPI Mode 3 signalling has an anomaly where
35 * data bytes will be left shifted by 1. Work-around for SPI Mode 3 is
123 return -ETIMEDOUT; in xec_qmspi_spin_yield()
133 * Some QMSPI timing register may be modified by the Boot-ROM OTP
144 taps[0] = regs->TM_TAPS; in qmspi_reset()
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Dspi_xmc4xxx.c4 * SPDX-License-Identifier: Apache-2.0
17 #include <zephyr/drivers/spi.h>
18 #include <zephyr/drivers/spi/rtio.h>
37 XMC_USIC_CH_t *spi; member
79 data->dma_status_flags |= SPI_XMC4XXX_DMA_ERROR_FLAG; in spi_xmc4xxx_dma_callback()
81 if (dev_dma == data->dma_tx.dev_dma && dma_channel == data->dma_tx.dma_channel) { in spi_xmc4xxx_dma_callback()
82 data->dma_status_flags |= SPI_XMC4XXX_DMA_TX_DONE_FLAG; in spi_xmc4xxx_dma_callback()
83 } else if (dev_dma == data->dma_rx.dev_dma && in spi_xmc4xxx_dma_callback()
84 dma_channel == data->dma_rx.dma_channel) { in spi_xmc4xxx_dma_callback()
85 data->dma_status_flags |= SPI_XMC4XXX_DMA_RX_DONE_FLAG; in spi_xmc4xxx_dma_callback()
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Dspi_npcx_spip.c4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/drivers/spi.h>
10 #include <zephyr/drivers/spi/rtio.h>
46 const struct spi_npcx_spip_cfg *const config = dev->config; in spi_npcx_spip_configure()
47 struct spi_npcx_spip_data *const data = dev->data; in spi_npcx_spip_configure()
48 struct spip_reg *const reg_base = config->reg_base; in spi_npcx_spip_configure()
49 spi_operation_t operation = spi_cfg->operation; in spi_npcx_spip_configure()
52 if (spi_context_configured(&data->ctx, spi_cfg)) { in spi_npcx_spip_configure()
59 return -ENOTSUP; in spi_npcx_spip_configure()
63 LOG_ERR("Only SPI controller mode is supported"); in spi_npcx_spip_configure()
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Dspi_rpi_pico_pio.c4 * SPDX-License-Identifier: Apache-2.0
17 #include <zephyr/drivers/spi.h>
56 /* ------------ */
58 /* ------------ */
71 /* ------------ */
73 /* ------------ */
88 /* ------------------- */
90 /* ------------------- */
105 /* ------------------------- */
107 /* ------------------------- */
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Dspi_max32.c4 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/drivers/spi.h>
16 #include <zephyr/drivers/spi/rtio.h>
23 #include <zephyr/drivers/spi/rtio.h>
86 const struct max32_spi_config *cfg = dev->config; in spi_configure()
87 mxc_spi_regs_t *regs = cfg->regs; in spi_configure()
88 struct max32_spi_data *data = dev->data; in spi_configure()
90 if (spi_context_configured(&data->ctx, config)) { in spi_configure()
94 if (SPI_OP_MODE_GET(config->operation) & SPI_OP_MODE_SLAVE) { in spi_configure()
95 return -ENOTSUP; in spi_configure()
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Dspi_sifive.c4 * SPDX-License-Identifier: Apache-2.0
38 return -ENOTSUP; in spi_config()
42 return -ENOTSUP; in spi_config()
46 return -ENOTSUP; in spi_config()
49 /* Set the SPI frequency */ in spi_config()
50 div = (SPI_CFG(dev)->f_sys / (frequency * 2U)) - 1; in spi_config()
55 /* If CPOL is set, then SCK idles at logical 1 */ in spi_config()
77 return -ENOTSUP; in spi_config()
87 return -ENOTSUP; in spi_config()
129 struct spi_context *ctx = &SPI_DATA(dev)->ctx; in spi_sifive_xfer()
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Dspi_grlib_spimctrl.c4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/drivers/spi.h>
10 #include <zephyr/drivers/spi/rtio.h>
35 #define SPI_DATA(dev) ((struct data *) ((dev)->data))
48 if (config->slave != 0) { in spi_config()
50 return -ENOTSUP; in spi_config()
53 if (SPI_WORD_SIZE_GET(config->operation) != 8) { in spi_config()
55 return -ENOTSUP; in spi_config()
58 if (config->operation & SPI_CS_ACTIVE_HIGH) { in spi_config()
60 return -ENOTSUP; in spi_config()
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Dspi_litex_litespi.c4 * SPDX-License-Identifier: Apache-2.0
44 const struct spi_litex_dev_config *dev_config = dev->config; in spi_litex_set_frequency()
46 if (!dev_config->phy_clk_divisor_exists) { in spi_litex_set_frequency()
52 uint32_t divisor = DIV_ROUND_UP(sys_clock_hw_cycles_per_sec(), (2 * config->frequency)) - 1; in spi_litex_set_frequency()
54 litex_write32(divisor, dev_config->phy_clk_divisor_addr); in spi_litex_set_frequency()
61 struct spi_litex_data *dev_data = dev->data; in spi_config()
63 if (config->slave != 0) { in spi_config()
64 if (config->slave >= SPI_MAX_CS_SIZE) { in spi_config()
66 return -ENOTSUP; in spi_config()
70 if (config->operation & SPI_HALF_DUPLEX) { in spi_config()
[all …]
Dspi_nxp_s32.c2 * Copyright 2022-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
15 struct spi_context *ctx = &data->ctx; in spi_nxp_s32_last_packet()
17 if (ctx->tx_count <= 1U && ctx->rx_count <= 1U) { in spi_nxp_s32_last_packet()
18 if (!spi_context_tx_on(ctx) && (data->transfer_len == ctx->rx_len)) { in spi_nxp_s32_last_packet()
22 if (!spi_context_rx_on(ctx) && (data->transfer_len == ctx->tx_len)) { in spi_nxp_s32_last_packet()
26 if ((ctx->rx_len == ctx->tx_len) && (data->transfer_len == ctx->tx_len)) { in spi_nxp_s32_last_packet()
41 const struct spi_nxp_s32_config *config = dev->config; in spi_nxp_s32_transfer_next_packet()
42 struct spi_nxp_s32_data *data = dev->data; in spi_nxp_s32_transfer_next_packet()
49 data_cb = config->cb; in spi_nxp_s32_transfer_next_packet()
[all …]
/Zephyr-latest/dts/bindings/mipi-dbi/
Dmipi-dbi-spi-device.yaml2 # SPDX-License-Identifier: Apache-2.0
4 # Common fields for MIPI DBI devices using Mode C (SPI)
6 include: [mipi-dbi-device.yaml]
13 SPI Duplex mode, full or half. By default it's always full duplex thus 0
15 Selecting half duplex allows to use SPI MOSI as a bidirectional line,
18 list (see dt-bindings/spi/spi.h)
21 mipi-cpol:
24 SPI clock polarity which indicates the clock idle state.
26 mipi-cpha:
29 SPI clock phase that indicates on which edge data is sampled.
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/Zephyr-latest/dts/bindings/spi/
Dspi-device.yaml1 # Copyright (c) 2018, I-SENSE group of ICCS
2 # SPDX-License-Identifier: Apache-2.0
4 # Common fields for SPI devices
8 on-bus: spi
13 spi-max-frequency:
16 description: Maximum clock frequency of device's SPI interface in Hz
24 list (see dt-bindings/spi/spi.h)
28 - 0
29 - 2048
30 frame-format:
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/Zephyr-latest/boards/segger/ip_k66f/
Dip_k66f.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
11 #include "ip_k66f-pinctrl.dtsi"
20 dsa-spi = &spi1;
26 zephyr,code-partition = &slot0_partition;
30 compatible = "gpio-leds";
44 clock-frequency = <120000000>;
48 pllfll-select = <KINETIS_SIM_PLLFLLSEL_MCGPLLCLK>;
49 er32k-select = <KINETIS_SIM_ER32KSEL_RTC>;
52 clock-div = <3>;
[all …]
/Zephyr-latest/boards/st/sensortile_box_pro/
Dsensortile_box_pro.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/u5/stm32u585aiixq-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
13 model = "STMicroelectronics SENSORTILE-BOX-PRO board";
14 compatible = "st,sensortile-box-pro";
19 zephyr,code-partition = &slot0_partition;
20 zephyr,bt-hci = &hci_spi;
24 compatible = "gpio-leds";
44 compatible = "gpio-keys";
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/Zephyr-latest/drivers/fpga/
Dfpga_ice40_bitbang.c5 * SPDX-License-Identifier: Apache-2.0
25 * CS polarity is normal (active low). Zephyr's SPI driver model currently
29 * separate SPI transfers (inverting CS polarity as necessary) and then
30 * restore the default pinctrl settings. On some higher-end microcontrollers
34 * However, on lower-end microcontrollers, the amount of time that elapses
35 * between SPI transfers does break the iCE40 timing requirements. That
36 * leaves us with the bitbanging option. Of course, on lower-end
40 * in order to bitbang on lower-end microcontrollers, we actually require
61 * lattice,ice40-fpga.yaml for details.
65 for (; n > 0; --n) { in fpga_ice40_delay()
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