Home
last modified time | relevance | path

Searched +full:spi +full:- +full:clock +full:- +full:mode +full:- +full:cpha (Results 1 – 25 of 29) sorted by relevance

12

/Zephyr-latest/tests/drivers/spi/spi_controller_peripheral/
DKconfig2 # SPDX-License-Identifier: Apache-2.0
5 int "SPI mode"
8 SPI mode value (clock polarity and phase) used in the test.
9 0: CPOL 0 (Active high), CPHA 0 (leading)
10 1: CPOL 0 (Active high), CPHA 1 (trailing)
11 2: CPOL 1 (Active low), CPHA 0 (leading)
12 3: CPOL 1 (Active low), CPHA 1 (trailing)
/Zephyr-latest/dts/bindings/wifi/
Dnordic,nrf70-qspi.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: This is a representation of the nRF70 Wi-Fi chip.
8 on-bus: qspi
11 qspi-frequency:
15 Maximum clock speed (in Hz) supported by the device.
20 qspi-quad-mode:
23 If specified, Use QSPI in quad mode (4 IO lines) otherwise in
24 SPI mode (2 IO lines - MOSI & MISO).
26 qspi-rx-delay:
30 Number of clock cycles from the rising edge of the SPI clock
[all …]
/Zephyr-latest/dts/bindings/sdhc/
Dzephyr,sdhc-spi-slot.yaml1 description: Generic Zephyr SPI based SDHC controller
3 compatible: "zephyr,sdhc-spi-slot"
5 include: [spi-device.yaml]
8 power-delay-ms:
12 Time in ms for SPI SDHC to delay when toggling power to the SD card. This
16 spi-clock-mode-cpol:
19 Clock polarity to use for SPI SDHC. Some cards respond properly
20 only when the clock goes low when not active.
22 spi-clock-mode-cpha:
25 Clock phase: this dictates when is the data captured, and depends
[all …]
/Zephyr-latest/samples/subsys/fs/fs_sample/boards/
Dnucleo_f429zi.overlay2 * Copyright (c) 2023 Łukasz Hejnak (LeHack) <lehack-ghub@lehack.pl>
4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "zephyr,sdhc-spi-slot";
13 compatible = "zephyr,sdmmc-disk";
14 disk-name = "SD";
17 spi-max-frequency = <25000000>;
18 spi-clock-mode-cpol;
19 spi-clock-mode-cpha;
/Zephyr-latest/dts/bindings/mipi-dbi/
Dmipi-dbi-spi-device.yaml2 # SPDX-License-Identifier: Apache-2.0
4 # Common fields for MIPI DBI devices using Mode C (SPI)
6 include: [mipi-dbi-device.yaml]
13 SPI Duplex mode, full or half. By default it's always full duplex thus 0
14 as this is, by far, the most common mode.
15 Selecting half duplex allows to use SPI MOSI as a bidirectional line,
18 list (see dt-bindings/spi/spi.h)
21 mipi-cpol:
24 SPI clock polarity which indicates the clock idle state.
25 If it is used, the clock idle state is logic high; otherwise, low.
[all …]
/Zephyr-latest/dts/bindings/spi/
Dspi-device.yaml1 # Copyright (c) 2018, I-SENSE group of ICCS
2 # SPDX-License-Identifier: Apache-2.0
4 # Common fields for SPI devices
8 on-bus: spi
13 spi-max-frequency:
16 description: Maximum clock frequency of device's SPI interface in Hz
21 Duplex mode, full or half. By default it's always full duplex thus 0
22 as this is, by far, the most common mode.
24 list (see dt-bindings/spi/spi.h)
28 - 0
[all …]
Dnxp,dspi.yaml2 # SPDX-License-Identifier: Apache-2.0
8 include: ["spi-controller.yaml", "pinctrl-device.yaml"]
20 pcs-sck-delay:
23 Delay in nanoseconds from the chip select assert to the first clock
26 sck-pcs-delay:
29 Delay in nanoseconds from the last clock edge to the chip select
32 transfer-delay:
38 pinctrl-0:
41 nxp,rx-tx-chn-share:
48 ctar register selection range form 0-1 for master mode, 0 for slave mode
[all …]
/Zephyr-latest/drivers/spi/
Dspi_numaker.c2 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/drivers/spi/rtio.h>
26 SPI_T *spi; member
29 /* clock configuration */
42 * CPOL/CPHA = 0/0 --> SPI_MODE_0
43 * CPOL/CPHA = 0/1 --> SPI_MODE_1
44 * CPOL/CPHA = 1/0 --> SPI_MODE_2
45 * CPOL/CPHA = 1/1 --> SPI_MODE_3
57 int mode; in spi_numaker_configure() local
58 struct spi_numaker_data *data = dev->data; in spi_numaker_configure()
[all …]
Dspi_bitbang.c2 * Copyright (c) 2021 Marc Reilly - Creative Product Design
4 * SPDX-License-Identifier: Apache-2.0
14 #include <zephyr/drivers/spi.h>
15 #include <zephyr/drivers/spi/rtio.h>
35 if (config->operation & SPI_OP_MODE_SLAVE) { in spi_bitbang_configure()
36 LOG_ERR("Slave mode not supported"); in spi_bitbang_configure()
37 return -ENOTSUP; in spi_bitbang_configure()
40 if (config->operation & (SPI_LINES_DUAL | SPI_LINES_QUAD | SPI_LINES_OCTAL)) { in spi_bitbang_configure()
42 return -ENOTSUP; in spi_bitbang_configure()
45 const int bits = SPI_WORD_SIZE_GET(config->operation); in spi_bitbang_configure()
[all …]
Dspi_xec_qmspi.c4 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/drivers/spi.h>
16 #include <zephyr/drivers/spi/rtio.h>
58 REG8(&regs->TX_FIFO) = data8; in txb_wr8()
63 return REG8(&regs->RX_FIFO); in rxb_rd8()
69 * mode register is defined as: 0=maximum divider of 256. Values 1 through
87 qmode = regs->MODE & ~(MCHP_QMSPI_M_FDIV_MASK); in qmspi_set_frequency()
89 regs->MODE = qmode; in qmspi_set_frequency()
93 * SPI signalling mode: CPOL and CPHA
94 * CPOL = 0 is clock idles low, 1 is clock idle high
[all …]
Dspi_xec_qmspi_ldma.c4 * SPDX-License-Identifier: Apache-2.0
18 #include <zephyr/drivers/spi.h>
19 #include <zephyr/drivers/spi/rtio.h>
20 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
21 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
33 /* MEC172x QMSPI controller SPI Mode 3 signalling has an anomaly where
35 * data bytes will be left shifted by 1. Work-around for SPI Mode 3 is
40 /* common clock control device node for all Microchip XEC chips */
123 return -ETIMEDOUT; in xec_qmspi_spin_yield()
133 * Some QMSPI timing register may be modified by the Boot-ROM OTP
[all …]
Dspi_npcx_spip.c4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/drivers/spi.h>
10 #include <zephyr/drivers/spi/rtio.h>
46 const struct spi_npcx_spip_cfg *const config = dev->config; in spi_npcx_spip_configure()
47 struct spi_npcx_spip_data *const data = dev->data; in spi_npcx_spip_configure()
48 struct spip_reg *const reg_base = config->reg_base; in spi_npcx_spip_configure()
49 spi_operation_t operation = spi_cfg->operation; in spi_npcx_spip_configure()
52 if (spi_context_configured(&data->ctx, spi_cfg)) { in spi_npcx_spip_configure()
58 LOG_ERR("Half duplex mode is not supported"); in spi_npcx_spip_configure()
59 return -ENOTSUP; in spi_npcx_spip_configure()
[all …]
Dspi_rpi_pico_pio.c4 * SPDX-License-Identifier: Apache-2.0
17 #include <zephyr/drivers/spi.h>
56 /* ------------ */
58 /* ------------ */
71 /* ------------ */
73 /* ------------ */
88 /* ------------------- */
90 /* ------------------- */
105 /* ------------------------- */
107 /* ------------------------- */
[all …]
Dspi_nxp_s32.c2 * Copyright 2022-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
15 struct spi_context *ctx = &data->ctx; in spi_nxp_s32_last_packet()
17 if (ctx->tx_count <= 1U && ctx->rx_count <= 1U) { in spi_nxp_s32_last_packet()
18 if (!spi_context_tx_on(ctx) && (data->transfer_len == ctx->rx_len)) { in spi_nxp_s32_last_packet()
22 if (!spi_context_rx_on(ctx) && (data->transfer_len == ctx->tx_len)) { in spi_nxp_s32_last_packet()
26 if ((ctx->rx_len == ctx->tx_len) && (data->transfer_len == ctx->tx_len)) { in spi_nxp_s32_last_packet()
41 const struct spi_nxp_s32_config *config = dev->config; in spi_nxp_s32_transfer_next_packet()
42 struct spi_nxp_s32_data *data = dev->data; in spi_nxp_s32_transfer_next_packet()
49 data_cb = config->cb; in spi_nxp_s32_transfer_next_packet()
[all …]
Dspi_gecko_usart.c4 * SPDX-License-Identifier: Apache-2.0
16 #include <zephyr/drivers/spi.h>
17 #include <zephyr/drivers/spi/rtio.h>
42 .clock = CLOCK_USART(DT_INST_PROP(n, peripheral_id)),
46 : -1)
50 : -1)
55 : -1)
61 : -1)
68 : -1)
76 : -1)
[all …]
Dspi_it8xxx2.c4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/drivers/spi.h>
105 const struct spi_it8xxx2_config *cfg = dev->config; in spi_it8xxx2_set_freq()
114 return -ENOTSUP; in spi_it8xxx2_set_freq()
118 sys_write8(sys_read8(cfg->base + SPI0D_CTRL5) | SCK_FREQ_DIV_1_EN, in spi_it8xxx2_set_freq()
119 cfg->base + SPI0D_CTRL5); in spi_it8xxx2_set_freq()
124 return -ENOTSUP; in spi_it8xxx2_set_freq()
127 sys_write8(sys_read8(cfg->base + SPI0D_CTRL5) & ~SCK_FREQ_DIV_1_EN, in spi_it8xxx2_set_freq()
128 cfg->base + SPI0D_CTRL5); in spi_it8xxx2_set_freq()
129 reg_val = sys_read8(cfg->base + SPI01_CTRL1); in spi_it8xxx2_set_freq()
[all …]
/Zephyr-latest/boards/espressif/esp32c3_rust/
Desp32c3_rust.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include "esp32c3_rust-pinctrl.dtsi"
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
12 #include <zephyr/dt-bindings/led/led.h>
16 model = "Espressif ESP32C3-RUST";
22 zephyr,shell-uart = &usb_serial;
24 zephyr,code-partition = &slot0_partition;
30 i2c-0 = &i2c0;
32 led-strip = &led_strip;
[all …]
/Zephyr-latest/boards/st/steval_stwinbx1/
Dsteval_stwinbx1.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/u5/stm32u585aiixq-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
13 model = "STMicroelectronics STEVAL-STWINBX1 Development kit";
19 zephyr,code-partition = &slot0_partition;
21 zephyr,bt-hci = &hci_spi;
25 compatible = "gpio-leds";
37 compatible = "pwm-leds";
41 label = "LED_1 - PWM5";
[all …]
/Zephyr-latest/boards/st/sensortile_box_pro/
Dsensortile_box_pro.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/u5/stm32u585aiixq-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
13 model = "STMicroelectronics SENSORTILE-BOX-PRO board";
14 compatible = "st,sensortile-box-pro";
19 zephyr,code-partition = &slot0_partition;
20 zephyr,bt-hci = &hci_spi;
24 compatible = "gpio-leds";
44 compatible = "gpio-keys";
[all …]
/Zephyr-latest/drivers/led_strip/
Dtlc5971.c4 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/drivers/spi.h>
13 #include <zephyr/dt-bindings/led/led.h>
34 /** SPI operation word constant, SPI mode 0, CPOL = 0, CPHA = 0 */
54 /** GS reference clock select bit in FC data (0 = internal oscillator clock, 1 = SCKI clock). */
57 /** GS reference clock edge select bit for OUTXn on-off timing control in FC data */
60 /** Constant-current output enable bit in FC data (0 = output control enabled, 1 = blank). */
63 /** Auto display repeat mode enable bit in FC data (0 = disabled, 1 = enabled). */
66 /** Display timing reset mode enable bit in FC data (0 = disabled, 1 = enabled). */
157 temp = pixel_data->r; in tlc5971_map_color()
[all …]
/Zephyr-latest/drivers/fpga/
Dfpga_ice40_bitbang.c5 * SPDX-License-Identifier: Apache-2.0
25 * CS polarity is normal (active low). Zephyr's SPI driver model currently
28 * The logical alternative would be to put the CS into GPIO mode, perform 3
29 * separate SPI transfers (inverting CS polarity as necessary) and then
30 * restore the default pinctrl settings. On some higher-end microcontrollers
34 * However, on lower-end microcontrollers, the amount of time that elapses
35 * between SPI transfers does break the iCE40 timing requirements. That
36 * leaves us with the bitbanging option. Of course, on lower-end
39 * achieve the minimum 1 MHz clock rate for loading the iCE40 bistream. So
40 * in order to bitbang on lower-end microcontrollers, we actually require
[all …]
/Zephyr-latest/drivers/mipi_dbi/
Dmipi_dbi_smartbond.c4 * SPDX-License-Identifier: Apache-2.0
22 #include <zephyr/drivers/spi.h>
100 struct mipi_dbi_smartbond_data *data = dev->data; in mipi_dbi_smartbond_send_single_frame()
108 k_sem_take(&data->sync_sem, K_FOREVER); in mipi_dbi_smartbond_send_single_frame()
111 LCDC->LCDC_INTERRUPT_REG |= LCDC_LCDC_INTERRUPT_REG_LCDC_VSYNC_IRQ_EN_Msk; in mipi_dbi_smartbond_send_single_frame()
114 LCDC->LCDC_MODE_REG |= LCDC_LCDC_MODE_REG_LCDC_SFRAME_UPD_Msk; in mipi_dbi_smartbond_send_single_frame()
117 k_sem_take(&data->sync_sem, K_FOREVER); in mipi_dbi_smartbond_send_single_frame()
119 if (data->underflow_flag) { in mipi_dbi_smartbond_send_single_frame()
121 data->underflow_flag = false; in mipi_dbi_smartbond_send_single_frame()
128 const struct mipi_dbi_smartbond_config *config = dev->config; in mipi_dbi_smartbond_reset()
[all …]
Dmipi_dbi_nxp_lcdic.c4 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/drivers/spi.h>
55 /* Dummy SCLK cycles between TX and RX (for SPI mode) */
58 /* Use auto repeat mode */
60 /* Tearing enable sync mode */
62 /* TRX command timeout mode */
143 * 5x the module clock before other registers are read
153 const struct mipi_dbi_lcdic_config *config = dev->config; in mipi_dbi_lcdic_reset_state()
154 LCDIC_Type *base = config->base; in mipi_dbi_lcdic_reset_state()
156 base->CTRL &= ~LCDIC_CTRL_LCDIC_EN_MASK; in mipi_dbi_lcdic_reset_state()
[all …]
/Zephyr-latest/doc/releases/
Drelease-notes-1.7.rst10 nano- and micro-kernel APIs found in the 1.5.0 release and earlier.
52 * Added NXP FRDM-KW41Z board
53 * Added ST Nucleo-F334R8, Nucleo-L476G, STM3210C-EVAL, and STM32373C-EVAL boards
62 * Added STM32F3x clock, flash, gpio, pinmux drivers
63 * Added stm32cube pwm and clock drivers
66 * Added mcux pinmux, gpio, uart, and spi drivers
67 * Added Beetle clock control and watchdog drivers
102 * Created net-shell module for interacting with network sub-system.
118 * Added SPI HCI driver
136 * Imported Segger J-Link RTT library
[all …]
Drelease-notes-3.6.rst12 * New :ref:`GNSS subsystem <gnss_api>` added, enabling geo-awareness in Zephyr applications.
13 * New API and drivers introduced for interfacing with :ref:`keyboard matrices <gpio-kbd>`.
16 * Integrated Trusted Firmware-M (TF-M) 2.0, including an update to Mbed TLS 3.5.2.
23 * Over 30 new supported boards, spanning all Zephyr-supported architectures.
37 * CVE-2023-5779 `Zephyr project bug tracker GHSA-7cmj-963q-jj47
38 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-7cmj-963q-jj47>`_
40 * CVE-2023-6249 `Zephyr project bug tracker GHSA-32f5-3p9h-2rqc
41 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-32f5-3p9h-2rqc>`_
43 * CVE-2023-6749 `Zephyr project bug tracker GHSA-757h-rw37-66hw
44 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-757h-rw37-66hw>`_
[all …]

12