Lines Matching +full:spi +full:- +full:clock +full:- +full:mode +full:- +full:cpha
4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/drivers/spi.h>
105 const struct spi_it8xxx2_config *cfg = dev->config; in spi_it8xxx2_set_freq()
114 return -ENOTSUP; in spi_it8xxx2_set_freq()
118 sys_write8(sys_read8(cfg->base + SPI0D_CTRL5) | SCK_FREQ_DIV_1_EN, in spi_it8xxx2_set_freq()
119 cfg->base + SPI0D_CTRL5); in spi_it8xxx2_set_freq()
124 return -ENOTSUP; in spi_it8xxx2_set_freq()
127 sys_write8(sys_read8(cfg->base + SPI0D_CTRL5) & ~SCK_FREQ_DIV_1_EN, in spi_it8xxx2_set_freq()
128 cfg->base + SPI0D_CTRL5); in spi_it8xxx2_set_freq()
129 reg_val = sys_read8(cfg->base + SPI01_CTRL1); in spi_it8xxx2_set_freq()
131 sys_write8(reg_val, cfg->base + SPI01_CTRL1); in spi_it8xxx2_set_freq()
143 const struct spi_it8xxx2_config *cfg = dev->config; in spi_it8xxx2_configure()
144 struct spi_it8xxx2_data *data = dev->data; in spi_it8xxx2_configure()
145 struct spi_context *ctx = &data->ctx; in spi_it8xxx2_configure()
149 if (spi_cfg->slave > (SPI_CHIP_SELECT_COUNT - 1)) { in spi_it8xxx2_configure()
150 LOG_ERR("Slave %d is greater than %d", spi_cfg->slave, SPI_CHIP_SELECT_COUNT - 1); in spi_it8xxx2_configure()
151 return -EINVAL; in spi_it8xxx2_configure()
154 LOG_DBG("chip select: %d, operation: 0x%x", spi_cfg->slave, spi_cfg->operation); in spi_it8xxx2_configure()
156 if (SPI_OP_MODE_GET(spi_cfg->operation) == SPI_OP_MODE_SLAVE) { in spi_it8xxx2_configure()
157 LOG_ERR("Unsupported SPI slave mode"); in spi_it8xxx2_configure()
158 return -ENOTSUP; in spi_it8xxx2_configure()
161 if (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_LOOP) { in spi_it8xxx2_configure()
162 LOG_ERR("Unsupported loopback mode"); in spi_it8xxx2_configure()
163 return -ENOTSUP; in spi_it8xxx2_configure()
166 if (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPHA) { in spi_it8xxx2_configure()
167 LOG_ERR("Unsupported cpha mode"); in spi_it8xxx2_configure()
168 return -ENOTSUP; in spi_it8xxx2_configure()
171 reg_val = sys_read8(cfg->base + SPI01_CTRL1); in spi_it8xxx2_configure()
172 if (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPOL) { in spi_it8xxx2_configure()
177 sys_write8(reg_val, cfg->base + SPI01_CTRL1); in spi_it8xxx2_configure()
179 if (SPI_WORD_SIZE_GET(spi_cfg->operation) != 8) { in spi_it8xxx2_configure()
180 return -ENOTSUP; in spi_it8xxx2_configure()
184 (spi_cfg->operation & SPI_LINES_MASK) != SPI_LINES_SINGLE) { in spi_it8xxx2_configure()
185 LOG_ERR("Only single line mode is supported"); in spi_it8xxx2_configure()
186 return -EINVAL; in spi_it8xxx2_configure()
189 ret = spi_it8xxx2_set_freq(dev, spi_cfg->frequency); in spi_it8xxx2_configure()
194 reg_val = sys_read8(cfg->base + SPI0C_INT_STS); in spi_it8xxx2_configure()
196 sys_write8(reg_val, cfg->base + SPI0C_INT_STS); in spi_it8xxx2_configure()
198 ctx->config = spi_cfg; in spi_it8xxx2_configure()
209 struct spi_it8xxx2_data *data = dev->data; in spi_it8xxx2_complete()
210 struct spi_context *ctx = &data->ctx; in spi_it8xxx2_complete()
213 if (spi_cs_is_gpio(ctx->config)) { in spi_it8xxx2_complete()
216 /* Permit to enter power policy and idle mode. */ in spi_it8xxx2_complete()
223 struct spi_it8xxx2_data *data = dev->data; in spi_it8xxx2_tx()
224 struct spi_context *ctx = &data->ctx; in spi_it8xxx2_tx()
227 if (ctx->tx_count > 1) { in spi_it8xxx2_tx()
228 data->cmdq_data.command.fields.cs_active = 1; in spi_it8xxx2_tx()
230 data->cmdq_data.command.fields.cs_active = 0; in spi_it8xxx2_tx()
232 data->cmdq_data.command.fields.cmd_end = 1; in spi_it8xxx2_tx()
233 data->cmdq_data.command.fields.read_write = 0; in spi_it8xxx2_tx()
234 if (ctx->tx_len <= SPI_CMDQ_WR_CMD_LEN_MAX) { in spi_it8xxx2_tx()
235 data->cmdq_data.spi_write_cmd_length = ctx->tx_len; in spi_it8xxx2_tx()
236 memcpy(data->cmdq_data.write_data, ctx->tx_buf, ctx->tx_len); in spi_it8xxx2_tx()
237 data->cmdq_data.data_length_lb = 0; in spi_it8xxx2_tx()
238 data->cmdq_data.data_length_hb = 0; in spi_it8xxx2_tx()
239 data->cmdq_data.data_addr_lb = 0; in spi_it8xxx2_tx()
240 data->cmdq_data.data_addr_hb = 0; in spi_it8xxx2_tx()
242 data->cmdq_data.spi_write_cmd_length = SPI_CMDQ_WR_CMD_LEN_MAX; in spi_it8xxx2_tx()
243 memcpy(data->cmdq_data.write_data, ctx->tx_buf, SPI_CMDQ_WR_CMD_LEN_MAX); in spi_it8xxx2_tx()
244 data->cmdq_data.data_length_lb = BYTE_0(ctx->tx_len - SPI_CMDQ_WR_CMD_LEN_MAX); in spi_it8xxx2_tx()
245 data->cmdq_data.data_length_hb = BYTE_1(ctx->tx_len - SPI_CMDQ_WR_CMD_LEN_MAX); in spi_it8xxx2_tx()
246 mem_address = (uint32_t)(ctx->tx_buf + SPI_CMDQ_WR_CMD_LEN_MAX) - SRAM_BASE_ADDR; in spi_it8xxx2_tx()
247 data->cmdq_data.data_addr_lb = BYTE_0(mem_address); in spi_it8xxx2_tx()
248 data->cmdq_data.data_addr_hb = BYTE_1(mem_address); in spi_it8xxx2_tx()
249 data->cmdq_data.check_bit_mask |= ((BYTE_2(mem_address)) & 0x03); in spi_it8xxx2_tx()
251 data->transfer_len = ctx->tx_len; in spi_it8xxx2_tx()
256 struct spi_it8xxx2_data *data = dev->data; in spi_it8xxx2_rx()
257 struct spi_context *ctx = &data->ctx; in spi_it8xxx2_rx()
259 if (ctx->rx_count > 1) { in spi_it8xxx2_rx()
260 data->cmdq_data.command.fields.cs_active = 1; in spi_it8xxx2_rx()
262 data->cmdq_data.command.fields.cs_active = 0; in spi_it8xxx2_rx()
264 data->cmdq_data.command.fields.cmd_end = 1; in spi_it8xxx2_rx()
265 data->cmdq_data.command.fields.read_write = 1; in spi_it8xxx2_rx()
266 data->cmdq_data.spi_write_cmd_length = 0; in spi_it8xxx2_rx()
267 data->cmdq_data.data_length_lb = BYTE_0(ctx->rx_len); in spi_it8xxx2_rx()
268 data->cmdq_data.data_length_hb = BYTE_1(ctx->rx_len); in spi_it8xxx2_rx()
269 data->cmdq_data.data_addr_lb = 0; in spi_it8xxx2_rx()
270 data->cmdq_data.data_addr_hb = 0; in spi_it8xxx2_rx()
271 data->receive_len = ctx->rx_len; in spi_it8xxx2_rx()
276 struct spi_it8xxx2_data *data = dev->data; in spi_it8xxx2_tx_rx()
277 struct spi_context *ctx = &data->ctx; in spi_it8xxx2_tx_rx()
280 data->cmdq_data.command.fields.cmd_end = 1; in spi_it8xxx2_tx_rx()
281 if (ctx->tx_len <= SPI_CMDQ_WR_CMD_LEN_MAX) { in spi_it8xxx2_tx_rx()
282 data->cmdq_data.command.fields.cs_active = 0; in spi_it8xxx2_tx_rx()
283 data->cmdq_data.command.fields.read_write = 1; in spi_it8xxx2_tx_rx()
284 data->cmdq_data.spi_write_cmd_length = ctx->tx_len; in spi_it8xxx2_tx_rx()
285 memcpy(data->cmdq_data.write_data, ctx->tx_buf, ctx->tx_len); in spi_it8xxx2_tx_rx()
286 if (ctx->rx_buf == ctx->tx_buf) { in spi_it8xxx2_tx_rx()
287 spi_context_update_tx(ctx, 1, ctx->tx_len); in spi_it8xxx2_tx_rx()
288 spi_context_update_rx(ctx, 1, ctx->rx_len); in spi_it8xxx2_tx_rx()
291 data->cmdq_data.data_length_lb = BYTE_0(ctx->rx_len); in spi_it8xxx2_tx_rx()
292 data->cmdq_data.data_length_hb = BYTE_1(ctx->rx_len); in spi_it8xxx2_tx_rx()
293 data->cmdq_data.data_addr_lb = 0; in spi_it8xxx2_tx_rx()
294 data->cmdq_data.data_addr_hb = 0; in spi_it8xxx2_tx_rx()
295 data->transfer_len = ctx->tx_len; in spi_it8xxx2_tx_rx()
296 data->receive_len = ctx->rx_len; in spi_it8xxx2_tx_rx()
298 data->cmdq_data.command.fields.cs_active = 1; in spi_it8xxx2_tx_rx()
299 data->cmdq_data.command.fields.read_write = 0; in spi_it8xxx2_tx_rx()
300 data->cmdq_data.spi_write_cmd_length = SPI_CMDQ_WR_CMD_LEN_MAX; in spi_it8xxx2_tx_rx()
301 memcpy(data->cmdq_data.write_data, ctx->tx_buf, SPI_CMDQ_WR_CMD_LEN_MAX); in spi_it8xxx2_tx_rx()
302 data->cmdq_data.data_length_lb = BYTE_0(ctx->tx_len - SPI_CMDQ_WR_CMD_LEN_MAX); in spi_it8xxx2_tx_rx()
303 data->cmdq_data.data_length_hb = BYTE_1(ctx->tx_len - SPI_CMDQ_WR_CMD_LEN_MAX); in spi_it8xxx2_tx_rx()
305 mem_address = (uint32_t)(ctx->tx_buf + SPI_CMDQ_WR_CMD_LEN_MAX) - SRAM_BASE_ADDR; in spi_it8xxx2_tx_rx()
306 data->cmdq_data.data_addr_lb = BYTE_0(mem_address); in spi_it8xxx2_tx_rx()
307 data->cmdq_data.data_addr_hb = BYTE_1(mem_address); in spi_it8xxx2_tx_rx()
308 data->cmdq_data.check_bit_mask |= ((BYTE_2(mem_address)) & 0x03); in spi_it8xxx2_tx_rx()
309 if (ctx->rx_buf == ctx->tx_buf) { in spi_it8xxx2_tx_rx()
310 spi_context_update_tx(ctx, 1, ctx->tx_len); in spi_it8xxx2_tx_rx()
311 spi_context_update_rx(ctx, 1, ctx->rx_len); in spi_it8xxx2_tx_rx()
313 data->transfer_len = ctx->tx_len; in spi_it8xxx2_tx_rx()
314 data->receive_len = 0; in spi_it8xxx2_tx_rx()
320 const struct spi_it8xxx2_config *cfg = dev->config; in spi_it8xxx2_next_xfer()
321 struct spi_it8xxx2_data *data = dev->data; in spi_it8xxx2_next_xfer()
322 struct spi_context *ctx = &data->ctx; in spi_it8xxx2_next_xfer()
331 if (spi_cs_is_gpio(ctx->config)) { in spi_it8xxx2_next_xfer()
336 return -EINVAL; in spi_it8xxx2_next_xfer()
339 memset(&data->cmdq_data, 0, sizeof(struct spi_it8xxx2_cmdq_data)); in spi_it8xxx2_next_xfer()
352 cmd_address = (uint32_t)(&data->cmdq_data) - SRAM_BASE_ADDR; in spi_it8xxx2_next_xfer()
353 mem_address = (uint32_t)ctx->rx_buf - SRAM_BASE_ADDR; in spi_it8xxx2_next_xfer()
354 if (ctx->config->slave == 0) { in spi_it8xxx2_next_xfer()
355 sys_write8(BYTE_0(cmd_address), cfg->base + SPI05_CH0_CMD_ADDR_LB); in spi_it8xxx2_next_xfer()
356 sys_write8(BYTE_1(cmd_address), cfg->base + SPI06_CH0_CMD_ADDR_HB); in spi_it8xxx2_next_xfer()
357 sys_write8(BYTE_2(cmd_address), cfg->base + SPI21_CH0_CMD_ADDR_HB2); in spi_it8xxx2_next_xfer()
360 sys_write8(BYTE_0(mem_address), cfg->base + SPI0E_CH0_WR_MEM_ADDR_LB); in spi_it8xxx2_next_xfer()
361 sys_write8(BYTE_1(mem_address), cfg->base + SPI0F_CH0_WR_MEM_ADDR_HB); in spi_it8xxx2_next_xfer()
362 sys_write8(BYTE_2(mem_address), cfg->base + SPI23_CH0_WR_MEM_ADDR_HB2); in spi_it8xxx2_next_xfer()
365 sys_write8(BYTE_0(cmd_address), cfg->base + SPI12_CH1_CMD_ADDR_LB); in spi_it8xxx2_next_xfer()
366 sys_write8(BYTE_1(cmd_address), cfg->base + SPI13_CH1_CMD_ADDR_HB); in spi_it8xxx2_next_xfer()
367 sys_write8(BYTE_2(cmd_address), cfg->base + SPI25_CH1_CMD_ADDR_HB2); in spi_it8xxx2_next_xfer()
370 sys_write8(BYTE_0(mem_address), cfg->base + SPI14_CH1_WR_MEM_ADDR_LB); in spi_it8xxx2_next_xfer()
371 sys_write8(BYTE_1(mem_address), cfg->base + SPI15_CH1_WR_MEM_ADDR_HB); in spi_it8xxx2_next_xfer()
372 sys_write8(BYTE_2(mem_address), cfg->base + SPI27_CH1_WR_MEM_ADDR_HB2); in spi_it8xxx2_next_xfer()
376 sys_write8(sys_read8(cfg->base + SPI01_CTRL1) | INTERRUPT_EN, cfg->base + SPI01_CTRL1); in spi_it8xxx2_next_xfer()
378 reg_val = sys_read8(cfg->base + SPI0D_CTRL5); in spi_it8xxx2_next_xfer()
379 reg_val |= (ctx->config->slave == 0) ? CH0_SEL_CMDQ : CH1_SEL_CMDQ; in spi_it8xxx2_next_xfer()
380 sys_write8(reg_val | CMDQ_MODE_EN, cfg->base + SPI0D_CTRL5); in spi_it8xxx2_next_xfer()
388 struct spi_it8xxx2_data *data = dev->data; in transceive()
389 struct spi_context *ctx = &data->ctx; in transceive()
394 /* Configure spi */ in transceive()
403 * policy during the transactions with the CQ mode. in transceive()
404 * Otherwise, the EC processor would be clock gated. in transceive()
439 struct spi_it8xxx2_data *data = dev->data; in it8xxx2_release()
441 spi_context_unlock_unconditionally(&data->ctx); in it8xxx2_release()
448 const struct spi_it8xxx2_config *cfg = dev->config; in it8xxx2_spi_isr()
449 struct spi_it8xxx2_data *data = dev->data; in it8xxx2_spi_isr()
450 struct spi_context *ctx = &data->ctx; in it8xxx2_spi_isr()
454 reg_val = sys_read8(cfg->base + SPI0C_INT_STS); in it8xxx2_spi_isr()
455 sys_write8(reg_val, cfg->base + SPI0C_INT_STS); in it8xxx2_spi_isr()
461 reg_val = sys_read8(cfg->base + SPI0D_CTRL5); in it8xxx2_spi_isr()
462 if (ctx->config->slave == 0) { in it8xxx2_spi_isr()
467 sys_write8(reg_val, cfg->base + SPI0D_CTRL5); in it8xxx2_spi_isr()
469 spi_context_update_tx(ctx, 1, data->transfer_len); in it8xxx2_spi_isr()
470 spi_context_update_rx(ctx, 1, data->receive_len); in it8xxx2_spi_isr()
480 const struct spi_it8xxx2_config *cfg = dev->config; in spi_it8xxx2_init()
481 struct spi_it8xxx2_data *data = dev->data; in spi_it8xxx2_init()
484 ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); in spi_it8xxx2_init()
490 /* Enable one-shot mode */ in spi_it8xxx2_init()
491 sys_write8(sys_read8(cfg->base + SPI04_CTRL3) & ~AUTO_MODE, cfg->base + SPI04_CTRL3); in spi_it8xxx2_init()
493 irq_connect_dynamic(cfg->spi_irq, 0, it8xxx2_spi_isr, dev, 0); in spi_it8xxx2_init()
494 irq_enable(cfg->spi_irq); in spi_it8xxx2_init()
496 ret = spi_context_cs_configure_all(&data->ctx); in spi_it8xxx2_init()
501 spi_context_unlock_unconditionally(&data->ctx); in spi_it8xxx2_init()
505 static DEVICE_API(spi, spi_it8xxx2_driver_api) = {