Searched full:smc (Results 1 – 25 of 47) sorted by relevance
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| /Zephyr-Core-3.5.0/dts/bindings/memory-controllers/ |
| D | atmel,sam-smc.yaml | 5 Atmel Static Memory Controller (SMC).
7 The SMC allows to interface with static-memory mapped external devices such as
10 The SMC is clocked through the Master Clock (MCK) which is controlled by the
13 The SMC controller can have up to 4 children defining the connected external
17 &smc {
25 atmel,smc-write-mode = "nwe";
26 atmel,smc-read-mode = "nrd";
27 atmel,smc-setup-timing = <1 1 1 1>;
28 atmel,smc-pulse-timing = <6 6 6 6>;
29 atmel,smc-cycle-timing = <7 7>;
[all …]
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| /Zephyr-Core-3.5.0/include/zephyr/drivers/sip_svc/ |
| D | sip_svc_agilex_smc.h | 13 * SMC protocol.
16 /* @brief SMC return status
26 /* @brief SMC Intel Header at a1
50 /* @brief SYNC SMC Function IDs
60 /* @brief ASYNC SMC Function IDs
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| D | sip_svc_proto.h | 16 * when requesting SMC/HVC service via 'send' function.
18 * Service to fill in the SMC/HVC return value in struct sip_svc_response
62 * return the result immediately during SMC/HVC call.
66 * separate SMC/HVC call. Use this method if the request requires longer
80 * - Unrecognized SMC/HVC Function ID.
116 * SMC/HVC
158 * - SMC/HVC return value
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| /Zephyr-Core-3.5.0/dts/bindings/sip_svc/ |
| D | intel,agilex-socfpga-sip-smc.yaml | 5 description: SiP SVC driver instance on Intel Agilex SOC FPGA for SMC call
7 compatible: "intel,socfpga-agilex-sip-smc"
14 const: smc
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| /Zephyr-Core-3.5.0/tests/arch/arm64/arm64_smc_call/src/ |
| D | main.c | 10 /* SMC function IDs for Standard Service queries */
34 zassert_true(res.a0 > 0, "Wrong smc call count"); in ZTEST()
38 "Wrong smc call version"); in ZTEST()
41 zassert_true(res.a0 == SMC_UNK, "Wrong return code from smc call"); in ZTEST()
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| /Zephyr-Core-3.5.0/tests/arch/arm64/arm64_smc_call/ |
| D | testcase.yaml | 2 arch.arm64.smc_call.smc:
6 - smc
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| D | Kconfig | 5 bool "Set smc call method to hvc"
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| /Zephyr-Core-3.5.0/boards/arm/sam4s_xplained/ |
| D | sam4s_xplained.dts | 215 &smc {
223 atmel,smc-write-mode = "nwe";
224 atmel,smc-read-mode = "nrd";
225 atmel,smc-setup-timing = <1 1 1 1>;
226 atmel,smc-pulse-timing = <6 6 6 6>;
227 atmel,smc-cycle-timing = <7 7>;
233 atmel,smc-write-mode = "nwe";
234 atmel,smc-read-mode = "nrd";
235 atmel,smc-setup-timing = <1 1 1 1>;
236 atmel,smc-pulse-timing = <6 6 6 6>;
[all …]
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| /Zephyr-Core-3.5.0/arch/arm64/core/ |
| D | smccc-call.S | 9 * Monitor Call (SMC) and Hypervisor Call (HVC).
30 * The SMC instruction is used to generate a synchronous exception that is
35 SMCCC smc
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| /Zephyr-Core-3.5.0/include/zephyr/sip_svc/ |
| D | sip_svc.h | 15 * SMC/HVC call from kernel running at EL1 to hypervisor/secure
18 * Only allow one SMC and one HVC per system.
26 * The service will return the SMC/HVC return value to the client
69 * @param ctrl Pointer to controller instance whose service provides ARM SMC/HVC
101 * SMC/HVC to hypervisor/secure monitor firmware running at EL2/EL3.
138 * @brief Client requests to send a SMC/HVC call to EL3/EL2
149 * @param cb Callback. SMC/SVC return value will be passed to client via
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| /Zephyr-Core-3.5.0/include/zephyr/arch/arm64/ |
| D | arm-smccc.h | 11 * Result from SMC/HVC call
47 * @brief Make SMC calls
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| /Zephyr-Core-3.5.0/soc/arm/nxp_kinetis/kv5x/ |
| D | soc.c | 86 SMC->PMPROT |= SMC_PMPROT_AHSRUN_MASK; in kv5x_init()
87 SMC->PMCTRL = (SMC->PMCTRL & ~SMC_PMCTRL_RUNM_MASK) | in kv5x_init()
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| /Zephyr-Core-3.5.0/soc/arm/nxp_kinetis/ke1xf/ |
| D | power.c | 36 SMC->STOPCTRL = SMC_STOPCTRL_PSTOPO(substate_id); in pm_state_set()
44 if (SMC->PMCTRL & SMC_PMCTRL_STOPA_MASK) { in pm_state_set()
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| /Zephyr-Core-3.5.0/dts/arm64/intel/ |
| D | intel_socfpga_agilex5.dtsi | 86 method = "smc";
164 sip_smc: smc{
165 compatible = "intel,socfpga-agilex-sip-smc";
166 method = "smc";
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| D | intel_socfpga_agilex.dtsi | 114 sip_smc: smc{
115 compatible = "intel,socfpga-agilex-sip-smc";
116 method = "smc";
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| /Zephyr-Core-3.5.0/drivers/memc/ |
| D | memc_sam_smc.c | 26 Smc *regs;
39 /* Enable SMC clock in PMC */ in memc_smc_init()
96 .regs = (Smc *)DT_INST_REG_ADDR(inst), \
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| D | Kconfig.sam | 5 bool "Atmel Static Memory Controller (SMC)"
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| /Zephyr-Core-3.5.0/soc/arm/nxp_kinetis/k6x/ |
| D | soc.c | 159 SMC->PMPROT |= SMC_PMPROT_AHSRUN_MASK; in k6x_init()
160 SMC->PMCTRL = (SMC->PMCTRL & ~SMC_PMCTRL_RUNM_MASK) | in k6x_init()
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| /Zephyr-Core-3.5.0/dts/bindings/pm_cpu_ops/ |
| D | arm_psci.yaml | 17 - smc
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| /Zephyr-Core-3.5.0/drivers/sip_svc/ |
| D | sip_smc_intel_socfpga.c | 35 /* Synchronous SMC Function IDs */ in intel_sip_smc_plat_func_id_valid()
50 /* Asynchronous SMC Function IDs */ in intel_sip_smc_plat_func_id_valid()
93 /* Assign the trans id into intel smc header a1 */ in intel_sip_smc_plat_update_trans_id()
124 /* Fill in SMC parameter to read mailbox response */ in intel_sip_smc_plat_async_res_req()
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| D | Kconfig.sip_smc_agilex | 10 Support for SDM mailbox fifo in Intel SoC FPGA Agilex via SMC calls.
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| /Zephyr-Core-3.5.0/tests/drivers/memc/ram/ |
| D | testcase.yaml | 19 filter: dt_compat_enabled("atmel,sam-smc")
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| /Zephyr-Core-3.5.0/boards/arm64/mimx8mm_evk/ |
| D | mimx8mm_evk_a53_smp.dts | 33 method = "smc";
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| /Zephyr-Core-3.5.0/boards/arm64/mimx8mn_evk/ |
| D | mimx8mn_evk_a53_smp.dts | 33 method = "smc";
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| /Zephyr-Core-3.5.0/boards/arm64/mimx8mp_evk/ |
| D | mimx8mp_evk_a53_smp.dts | 33 method = "smc";
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