| /Zephyr-latest/tests/subsys/dsp/utils/src/ |
| D | f32.c | 37 "Conversion failed: %f shifted by %d = %d (expected %d)", (double)data, shift, in test_shift_f32_to_q7()
47 "Conversion failed: %f shifted by %d = %d (expected %d)", (double)data, shift, in test_shift_f32_to_q15()
57 "Conversion failed: %f shifted by %d = %d (expected %d)", (double)data, shift, in test_shift_f32_to_q31()
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| D | f64.c | 36 "Conversion failed: %f shifted by %d = %d (expected %d)", data, shift, in test_shift_f64_to_q7()
46 "Conversion failed: %f shifted by %d = %d (expected %d)", (double)data, shift, in test_shift_f64_to_q15()
56 "Conversion failed: %f shifted by %d = %d (expected %d)", (double)data, shift, in test_shift_f64_to_q31()
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| D | q15.c | 35 "Conversion failed: 0x%08x shifted by %d = %f (expected %f)", data, shift, in test_shift_q15_to_f32()
44 "Conversion failed: 0x%08x shifted by %d = %f (expected %f)", data, shift, in test_shift_q15_to_f64()
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| D | q31.c | 36 "Conversion failed: 0x%08x shifted by %d = %f (expected %f)", data, shift, in test_shift_q31_to_f32()
45 "Conversion failed: 0x%08x shifted by %d = %f (expected %f)", data, shift, in test_shift_q31_to_f64()
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| D | q7.c | 34 "Conversion failed: 0x%08x shifted by %d = %f (expected %f)", data, shift, in test_shift_q7_to_f32()
43 "Conversion failed: 0x%08x shifted by %d = %f (expected %f)", data, shift, in test_shift_q7_to_f64()
|
| /Zephyr-latest/dts/bindings/i3c/ |
| D | i3c-device.yaml | 23 ID left-shifted by 1, where the manufacturer ID is
26 the part ID (bits 16-31 of the Provisioned ID) left-shifted
28 left-shifted by 12. Basically, this is the lower 32 bits
|
| /Zephyr-latest/soc/microchip/mec/common/reg/ |
| D | mec_tfdp.h | 26 /* Number of AHB clocks between each byte shifted out */
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| /Zephyr-latest/soc/nxp/imxrt/imxrt118x/ |
| D | pinctrl_soc.h | 36 * pue_pus_lpsr: in low power state retention domain, shifted ode field
37 * pue_pus_snvs: in SNVS domain, shifted ode field
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| /Zephyr-latest/samples/drivers/i2s/output/src/ |
| D | main.c | 26 /* Fill buffer with sine wave on left channel, and sine wave shifted by
37 /* Right channel is same sine wave, shifted by 90 degrees */ in fill_buf()
|
| /Zephyr-latest/doc/build/version/ |
| D | index.rst | 80 | APPVERSION | Numerical | ``VERSION_MAJOR`` (left shifted by 24 bits), |b…
81 | | | ``VERSION_MINOR`` (left shifted by 16 bits), |b…
82 | | | ``PATCHLEVEL`` (left shifted by 8 bits), |br| …
85 | APP_VERSION_NUMBER | Numerical | ``VERSION_MAJOR`` (left shifted by 16 bits), |b…
86 | | | ``VERSION_MINOR`` (left shifted by 8 bits), |br…
158 | APPVERSION | Numerical (hex) | ``VERSION_MAJOR`` (left shifted by 24 bits), |br|…
159 | | | ``VERSION_MINOR`` (left shifted by 16 bits), |br|…
160 | | | ``PATCHLEVEL`` (left shifted by 8 bits), |br| …
163 | APP_VERSION_NUMBER | Numerical (hex) | ``VERSION_MAJOR`` (left shifted by 16 bits), |br|…
164 | | | ``VERSION_MINOR`` (left shifted by 8 bits), |br| …
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| /Zephyr-latest/dts/bindings/spi/ |
| D | nxp,dspi.yaml | 67 is also ignored. If ROOE = 1, the incoming data is shifted to the
|
| /Zephyr-latest/soc/nxp/imxrt/imxrt11xx/ |
| D | pinctrl_soc.h | 38 * pue_pus_lpsr: in low power state retention domain, shifted ode field
39 * pue_pus_snvs: in SNVS domain, shifted ode field
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| /Zephyr-latest/arch/riscv/ |
| D | Kconfig.isa | 122 shifted index is added to a base address.
|
| /Zephyr-latest/doc/hardware/peripherals/ |
| D | i3c.rst | 225 which contains the manufacturer ID left-shifted by 1. This is
229 which is a combination of the part ID (left-shifted by 16,
230 bits 16-31 of the PID) and the instance ID (left-shifted by 12,
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| /Zephyr-latest/soc/microchip/mec/mec172x/reg/ |
| D | mec172x_i2c_smb.h | 70 * Data to be shifted out or shifted in.
|
| /Zephyr-latest/include/zephyr/audio/ |
| D | dmic.h | 201 * Returns the map of PDM controller and LEFT/RIGHT channel shifted to
244 * Returns the bit-map of clock skew value shifted to the bit position
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| /Zephyr-latest/samples/subsys/usb/uac2_explicit_feedback/src/ |
| D | feedback_nrf53.c | 212 * USB host SOF clock) to fake sample clock shifted by P values. in update_sof_offset()
310 * Manually tweaking the constants so the regulator output is shifted in pi_update()
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| /Zephyr-latest/include/zephyr/dsp/ |
| D | basicmath.h | 279 * These are multiplied to yield a 2.14 intermediate result and this is shifted with saturation to
296 * These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to
313 * These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to
487 * If <code>shift</code> is positive then the elements of the vector are shifted to the left.
488 * If <code>shift</code> is negative then the elements of the vector are shifted to the right.
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| /Zephyr-latest/drivers/adc/ |
| D | adc_ite_it8xxx2.c | 112 /* Channels 13~16 should be shifted by 5 */ in adc_it8xxx2_channel_setup()
287 /* Channels 13~16 should be shifted to the right by 5 */ in adc_it8xxx2_start_read()
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| /Zephyr-latest/soc/nordic/nrf54l/ |
| D | soc.c | 85 * offset_k should be divided by 2^6, but to add it to value shifted by 2^9 we have to in nordicsemi_nrf54l_init()
|
| /Zephyr-latest/subsys/mgmt/mcumgr/grp/img_mgmt/ |
| D | Kconfig | 102 NOTE: When direct upload is used the image numbers are shifted by + 1, and the default
|
| /Zephyr-latest/drivers/clock_control/ |
| D | clock_control_r8a7795_cpg_mssr.c | 229 /* 1,2,4,8,16 have to be converted to 0,1,2,3,4 and then shifted */ in r8a7795_set_rate_helper()
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| D | clock_control_r8a779f0_cpg_mssr.c | 229 /* 1,2,4,8,16 have to be converted to 0,1,2,3,4 and then shifted */ in r8a779f0_set_rate_helper()
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| /Zephyr-latest/soc/intel/intel_adsp/cavs/ |
| D | multiprocessing.c | 117 * available, so it's sent shifted). The write to ITC in soc_start_core()
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| /Zephyr-latest/scripts/build/ |
| D | elf_parser.py | 163 # Relocatable data does not appear to be shifted
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