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/hal_espressif-latest/components/soc/esp32/include/soc/
Di2c_struct.h33 …sda data 0: exchange the function of sda_o and sda_oe (sda_o is the original internal output sda…
51 …uint32_t arb_lost: 1; /*when I2C lost control of SDA line this register changes…
197 …his register is used to configure the clock num I2C used to sample data on SDA after the posedge o…
212 … /*This register is used to configure the clock num between the negedge of SDA and negedge of SCL …
219 …ed to configure the clock num between the posedge of SCL and the negedge of SDA for restart mark.*/
233 …is register is used to configure the clock num between the posedge of SCL and the posedge of SDA.*/
249 uint32_t en: 1; /*This is the filter enable bit for SDA.*/
Di2c_reg.h79 /*description: 1: normally ouput sda data 0: exchange the function of sda_o
80 …da_oe (sda_o is the original internal output sda signal sda_oe is the enable bit for the internal …
133 /*description: when I2C lost control of SDA line this register changes to high level.*/
617 sample data on SDA after the posedge of SCL*/
634 negedge of SDA and negedge of SCL for start mark.*/
643 posedge of SCL and the negedge of SDA for restart mark.*/
660 posedge of SCL and the posedge of SDA.*/
683 /*description: This is the filter enable bit for SDA.*/
Drtc_i2c_reg.h68 /*description: SDA is push-pull (1) or open-drain (0) */
241 /*description: Number of FAST_CLK cycles SDA will switch after falling edge of SCL */
Drtc_io_struct.h275 … sda_sel: 2; /*�0� using TOUCH_PAD[1] as i2c sda �1� using TOUCH_PAD[3] as i2c sda*/
/hal_espressif-latest/components/soc/esp32c6/include/soc/
Dlp_i2c_struct.h51 * This register is used to configure for how long SDA is sampled, in I2C module clock
81 * Configures the delay between the SDA and SCL negative edge for a start condition
87 * of SDA and the negative edge of SCL for a START condition, in I2C module clock
98 * edge of SCL and the negative edge of SDA
104 * edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module
130 * Configures the delay between the SDA and
137 * of SCL and the positive edge of SDA, in I2C module clock cycles.
191 * 1: sample SDA data on the SCL low level.
192 * 0: sample SDA data on the SCL high level.
300 * SCL and SDA filter configuration register
[all …]
Di2c_struct.h51 * This register is used to configure for how long SDA is sampled, in I2C module clock
81 * Configures the delay between the SDA and SCL negative edge for a start condition
87 * of SDA and the negative edge of SCL for a START condition, in I2C module clock
98 * edge of SCL and the negative edge of SDA
104 * edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module
130 * Configures the delay between the SDA and
137 * of SCL and the positive edge of SDA, in I2C module clock cycles.
191 * 1: sample SDA data on the SCL low level.
192 * 0: sample SDA data on the SCL high level.
338 * SCL and SDA filter configuration register
[all …]
Dlp_i2c_reg.h48 * 1: sample SDA data on the SCL low level.
49 * 0: sample SDA data on the SCL high level.
777 * This register is used to configure for how long SDA is sampled, in I2C module clock
807 * Configures the delay between the SDA and SCL negative edge for a start condition
812 * of SDA and the negative edge of SCL for a START condition, in I2C module clock
822 * edge of SCL and the negative edge of SDA
827 * edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module
850 * Configures the delay between the SDA and
856 * of SCL and the positive edge of SDA, in I2C module clock cycles.
864 * SCL and SDA filter configuration register
[all …]
Di2c_reg.h48 * 1: sample SDA data on the SCL low level.
49 * 0: sample SDA data on the SCL high level.
950 * This register is used to configure for how long SDA is sampled, in I2C module clock
980 * Configures the delay between the SDA and SCL negative edge for a start condition
985 * of SDA and the negative edge of SCL for a START condition, in I2C module clock
995 * edge of SCL and the negative edge of SDA
1000 * edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module
1023 * Configures the delay between the SDA and
1029 * of SCL and the positive edge of SDA, in I2C module clock cycles.
1037 * SCL and SDA filter configuration register
[all …]
/hal_espressif-latest/components/soc/esp32c2/include/soc/
Di2c_struct.h51 * This register is used to configure for how long SDA is sampled, in I2C module clock
81 * Configures the delay between the SDA and SCL negative edge for a start condition
87 * of SDA and the negative edge of SCL for a START condition, in I2C module clock
98 * edge of SCL and the negative edge of SDA
104 * edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module
130 * Configures the delay between the SDA and
137 * of SCL and the positive edge of SDA, in I2C module clock cycles.
191 * 1: sample SDA data on the SCL low level.
192 * 0: sample SDA data on the SCL high level.
309 * SCL and SDA filter configuration register
[all …]
Di2c_reg.h48 * 1: sample SDA data on the SCL low level.
49 * 0: sample SDA data on the SCL high level.
793 * This register is used to configure for how long SDA is sampled, in I2C module clock
823 * Configures the delay between the SDA and SCL negative edge for a start condition
828 * of SDA and the negative edge of SCL for a START condition, in I2C module clock
838 * edge of SCL and the negative edge of SDA
843 * edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module
866 * Configures the delay between the SDA and
872 * of SCL and the positive edge of SDA, in I2C module clock cycles.
880 * SCL and SDA filter configuration register
[all …]
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Di2c_struct.h60 * This register is used to configure for how long SDA is sampled, in I2C module clock
90 * Configures the delay between the SDA and SCL negative edge for a start condition
96 * of SDA and the negative edge of SCL for a START condition, in I2C module clock
107 * edge of SCL and the negative edge of SDA
113 * edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module
139 * Configures the delay between the SDA and
146 * of SCL and the positive edge of SDA, in I2C module clock cycles.
200 * 1: sample SDA data on the SCL low level.
201 * 0: sample SDA data on the SCL high level.
347 * SCL and SDA filter configuration register
[all …]
Di2c_reg.h57 * 1: sample SDA data on the SCL low level.
58 * 0: sample SDA data on the SCL high level.
931 * This register is used to configure for how long SDA is sampled, in I2C module clock
961 * Configures the delay between the SDA and SCL negative edge for a start condition
966 * of SDA and the negative edge of SCL for a START condition, in I2C module clock
976 * edge of SCL and the negative edge of SDA
981 * edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module
1004 * Configures the delay between the SDA and
1010 * of SCL and the positive edge of SDA, in I2C module clock cycles.
1018 * SCL and SDA filter configuration register
[all …]
/hal_espressif-latest/components/soc/esp32h2/include/soc/
Di2c_struct.h51 * This register is used to configure for how long SDA is sampled, in I2C module clock
81 * Configures the delay between the SDA and SCL negative edge for a start condition
87 * of SDA and the negative edge of SCL for a START condition, in I2C module clock
98 * edge of SCL and the negative edge of SDA
104 * edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module
130 * Configures the delay between the SDA and
137 * of SCL and the positive edge of SDA, in I2C module clock cycles.
191 * 1: sample SDA data on the SCL low level.
192 * 0: sample SDA data on the SCL high level.
338 * SCL and SDA filter configuration register
[all …]
Di2c_reg.h48 * 1: sample SDA data on the SCL low level.
49 * 0: sample SDA data on the SCL high level.
950 * This register is used to configure for how long SDA is sampled, in I2C module clock
980 * Configures the delay between the SDA and SCL negative edge for a start condition
985 * of SDA and the negative edge of SCL for a START condition, in I2C module clock
995 * edge of SCL and the negative edge of SDA
1000 * edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module
1023 * Configures the delay between the SDA and
1029 * of SCL and the positive edge of SDA, in I2C module clock cycles.
1037 * SCL and SDA filter configuration register
[all …]
/hal_espressif-latest/components/hal/include/hal/
Di2c_types.h41 uint16_t sda_sample; /*!< I2C sda sample time */
91 int sda_hold; /*!< sda hold time */
/hal_espressif-latest/components/hal/esp32s2/include/hal/
Di2c_ll.h109 //sda sample in i2c_ll_set_bus_timing()
308 * @param sda_sample The SDA sample time (in APB cycle)
309 * @param sda_hold The SDA hold time (in APB cycle)
376 * @brief Get I2C sda timing configuration
379 * @param sda_sample Pointer to accept the SDA sample timing configuration
380 * @param sda_hold Pointer to accept the SDA hold timing configuration
666 …* If internal open-drain of the I2C module is disabled, scl and sda gpio should be configu…
/hal_espressif-latest/components/hal/esp32/include/hal/
Di2c_ll.h121 //sda sample in i2c_ll_set_bus_timing()
318 * @param sda_sample The SDA sample time (in APB cycle)
319 * @param sda_hold The SDA hold time (in APB cycle)
386 * @brief Get I2C sda timing configuration
389 * @param sda_sample Pointer to accept the SDA sample timing configuration
390 * @param sda_hold Pointer to accept the SDA hold timing configuration
/hal_espressif-latest/components/hal/esp32c2/include/hal/
Di2c_ll.h140 //sda sample in i2c_ll_set_bus_timing()
324 * @param sda_sample The SDA sample time (in core clock cycle)
325 * @param sda_hold The SDA hold time (in core clock cycle)
392 * @brief Get I2C sda timing configuration
395 * @param sda_sample Pointer to accept the SDA sample timing configuration
396 * @param sda_hold Pointer to accept the SDA hold timing configuration
/hal_espressif-latest/components/hal/esp32s3/include/hal/
Di2c_ll.h140 //sda sample in i2c_ll_set_bus_timing()
340 * @param sda_sample The SDA sample time (in core clock cycle)
341 * @param sda_hold The SDA hold time (in core clock cycle)
408 * @brief Get I2C sda timing configuration
411 * @param sda_sample Pointer to accept the SDA sample timing configuration
412 * @param sda_hold Pointer to accept the SDA hold timing configuration
/hal_espressif-latest/components/hal/esp32c3/include/hal/
Di2c_ll.h141 //sda sample in i2c_ll_set_bus_timing()
340 * @param sda_sample The SDA sample time (in core clock cycle)
341 * @param sda_hold The SDA hold time (in core clock cycle)
408 * @brief Get I2C sda timing configuration
411 * @param sda_sample Pointer to accept the SDA sample timing configuration
412 * @param sda_hold Pointer to accept the SDA hold timing configuration
/hal_espressif-latest/components/hal/esp32h2/include/hal/
Di2c_ll.h144 //sda sample in i2c_ll_set_bus_timing()
343 * @param sda_sample The SDA sample time (in core clock cycle)
344 * @param sda_hold The SDA hold time (in core clock cycle)
411 * @brief Get I2C sda timing configuration
414 * @param sda_sample Pointer to accept the SDA sample timing configuration
415 * @param sda_hold Pointer to accept the SDA hold timing configuration
/hal_espressif-latest/zephyr/port/pincfgs/
Desp32s2.yml98 sda:
108 sda:
Desp32c3.yml74 sda:
Desp32c6.yml146 sda:
/hal_espressif-latest/components/hal/esp32c6/include/hal/
Di2c_ll.h144 //sda sample in i2c_ll_set_bus_timing()
343 * @param sda_sample The SDA sample time (in core clock cycle)
344 * @param sda_hold The SDA hold time (in core clock cycle)
411 * @brief Get I2C sda timing configuration
414 * @param sda_sample Pointer to accept the SDA sample timing configuration
415 * @param sda_hold Pointer to accept the SDA hold timing configuration

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