| /hal_espressif-latest/components/hal/ |
| D | i2s_hal.c | 28 * @brief Calculate the precise mclk division by sclk and mclk
30 * @param sclk system clock
36 void i2s_hal_calc_mclk_precise_division(uint32_t sclk, uint32_t mclk, i2s_ll_mclk_div_t *mclk_div) in i2s_hal_calc_mclk_precise_division() argument
43 uint32_t div_inter = sclk / mclk; in i2s_hal_calc_mclk_precise_division()
44 uint32_t freq_diff = sclk % mclk; in i2s_hal_calc_mclk_precise_division()
88 i2s_hal_calc_mclk_precise_division(clk_info->sclk, clk_info->mclk, &mclk_div); in i2s_hal_set_tx_clock()
101 i2s_hal_calc_mclk_precise_division(clk_info->sclk, clk_info->mclk, &mclk_div); in i2s_hal_set_rx_clock()
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| D | uart_hal.c | 11 void uart_hal_get_sclk(uart_hal_context_t *hal, uart_sclk_t *sclk) in uart_hal_get_sclk() argument
13 uart_ll_get_sclk(hal->dev, sclk); in uart_hal_get_sclk()
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| /hal_espressif-latest/components/hal/include/hal/ |
| D | uart_hal.h | 46 * @param sclk The UART source clock type.
50 #define uart_hal_set_sclk(hal, sclk) uart_ll_set_sclk((hal)->dev, sclk); argument
205 * @param sclk The poiter to accept the UART source clock type
209 void uart_hal_get_sclk(uart_hal_context_t *hal, uart_sclk_t *sclk);
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| D | i2s_hal.h | 101 uint32_t sclk; /*!< I2S module clock */ member
124 * @brief Helper function for calculating the precise mclk division by sclk and mclk
126 * @param sclk system clock
130 void i2s_hal_calc_mclk_precise_division(uint32_t sclk, uint32_t mclk, i2s_ll_mclk_div_t *mclk_div);
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| /hal_espressif-latest/zephyr/port/pincfgs/ |
| D | esp32s2.yml | 55 sclk:
84 sclk:
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| D | esp32c2.yml | 51 sclk:
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| D | esp32c3.yml | 51 sclk:
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| D | esp32c6.yml | 56 sclk:
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| D | esp32.yml | 70 sclk:
90 sclk:
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| D | esp32s3.yml | 142 sclk:
171 sclk:
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| /hal_espressif-latest/components/driver/deprecated/ |
| D | i2s_legacy.c | 654 /* In APLL mode, there is no sclk but only mclk, so return 0 here to indicate APLL mode */ in i2s_config_source_clock()
685 clk_info->sclk = i2s_config_source_clock(i2s_num, p_i2s[i2s_num]->use_apll, clk_info->mclk); in i2s_calculate_adc_dac_clock()
687 clk_info->mclk_div = clk_info->sclk / clk_info->mclk; in i2s_calculate_adc_dac_clock()
690 …ESP_RETURN_ON_FALSE(clk_info->sclk / (float)clk_info->mclk > 1.99, ESP_ERR_INVALID_ARG, TAG, "samp… in i2s_calculate_adc_dac_clock()
714 clk_info->sclk = i2s_config_source_clock(i2s_num, p_i2s[i2s_num]->use_apll, clk_info->mclk); in i2s_calculate_pdm_tx_clock()
716 clk_info->mclk_div = clk_info->sclk / clk_info->mclk; in i2s_calculate_pdm_tx_clock()
719 …ESP_RETURN_ON_FALSE(clk_info->sclk / (float)clk_info->mclk > 1.99, ESP_ERR_INVALID_ARG, TAG, "samp… in i2s_calculate_pdm_tx_clock()
741 clk_info->sclk = i2s_config_source_clock(i2s_num, p_i2s[i2s_num]->use_apll, clk_info->mclk); in i2s_calculate_pdm_rx_clock()
743 clk_info->mclk_div = clk_info->sclk / clk_info->mclk; in i2s_calculate_pdm_rx_clock()
746 …ESP_RETURN_ON_FALSE(clk_info->sclk / (float)clk_info->mclk > 1.99, ESP_ERR_INVALID_ARG, TAG, "samp… in i2s_calculate_pdm_rx_clock()
[all …]
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| /hal_espressif-latest/components/driver/spi/include/driver/ |
| D | spi_master.h | 75 …elay_ns; /**< Maximum data valid time of slave. The time required between SCLK and MISO
371 * @param input_delay_ns Input delay from SCLK launch edge to MISO data valid.
389 * @param input_delay_ns Input delay from SCLK launch edge to MISO data valid.
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| D | spi_common.h | 58 #define SPICOMMON_BUSFLAG_SCLK (1<<3) ///< Check existing of SCLK pin. Or indicates CL…
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| /hal_espressif-latest/components/hal/esp32s2/include/hal/ |
| D | i2s_ll.h | 285 * mclk = sclk / (mclk_div + b/a)
288 * @param mclk_div integer part of the division from sclk to mclk
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| /hal_espressif-latest/components/driver/uart/ |
| D | uart.c | 203 esp_err_t uart_get_sclk_freq(uart_sclk_t sclk, uint32_t *out_freq_hz) in uart_get_sclk_freq() argument
205 …return esp_clk_tree_src_get_freq_hz((soc_module_clk_t)sclk, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED… in uart_get_sclk_freq()
1619 uart_sclk_t sclk = 0; in uart_driver_delete() local
1620 uart_hal_get_sclk(&(uart_context[uart_num].hal), &sclk); in uart_driver_delete()
1621 if (sclk == UART_SCLK_RTC) { in uart_driver_delete()
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| /hal_espressif-latest/components/hal/esp32/include/hal/ |
| D | i2s_ll.h | 294 * mclk = sclk / (mclk_div + b/a)
297 * @param mclk_div integer part of the division from sclk to mclk
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| /hal_espressif-latest/components/driver/spi/gpspi/ |
| D | spi_common.c | 515 SPI_CHECK_PIN(bus_config->sclk_io_num, "sclk", sclk_need_output); in spicommon_bus_initialize_io()
576 ESP_LOGE(SPI_TAG, "sclk pin required."); in spicommon_bus_initialize_io()
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| D | spi_master.c | 368 …peed_hz > 0) && (dev_config->clock_speed_hz <= clock_source_hz), "invalid sclk speed", ESP_ERR_INV… in spi_bus_add_device()
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| /hal_espressif-latest/components/driver/include/esp_private/ |
| D | spi_common_internal.h | 167 …* Make sure SCLK/MISO/MOSI is/are set to a valid GPIO. Also check output capabili…
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