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/hal_espressif-latest/components/soc/esp32c6/include/soc/
Di2c_struct.h15 * Configures the low level width of the SCL
21 * This register is used to configure for how long SCL remains low in master mode, in
31 * Configures the hold time after a negative SCL edge.
37 * edge of SCL, in I2C module clock cycles.
46 * Configures the sample time after a positive SCL edge.
61 * Configures the high level width of SCL
66 * This register is used to configure for how long SCL remains high in master mode, in
71 * This register is used to configure for the SCL_FSM's waiting period for SCL high
81 * Configures the delay between the SDA and SCL negative edge for a start condition
87 * of SDA and the negative edge of SCL for a START condition, in I2C module clock
[all …]
Dlp_i2c_struct.h15 * Configures the low level width of the SCL
21 * This register is used to configure for how long SCL remains low in master mode, in
31 * Configures the hold time after a negative SCL edge.
37 * edge of SCL, in I2C module clock cycles.
46 * Configures the sample time after a positive SCL edge.
61 * Configures the high level width of SCL
66 * This register is used to configure for how long SCL setup to high level and remains
71 * This register is used to configure for the SCL_FSM's waiting period for SCL high
81 * Configures the delay between the SDA and SCL negative edge for a start condition
87 * of SDA and the negative edge of SCL for a START condition, in I2C module clock
[all …]
Di2c_reg.h15 * Configures the low level width of the SCL
20 * This register is used to configure for how long SCL remains low in master mode, in
48 * 1: sample SDA data on the SCL low level.
49 * 0: sample SDA data on the SCL high level.
112 * This register is used to reset the scl FMS.
167 * When the I2C controller loses control of SCL line, this register changes to 1.
196 * The cause of stretching SCL low in slave mode. 0: stretching SCL low at the
197 * beginning of I2C read data state. 1: stretching SCL low when I2C Tx FIFO is empty
198 * in slave mode. 2: stretching SCL low when I2C Rx FIFO is full in slave mode.
221 * This field indicates the states of the state machine used to produce SCL.
[all …]
Dlp_i2c_reg.h15 * Configures the low level width of the SCL
20 * This register is used to configure for how long SCL remains low in master mode, in
48 * 1: sample SDA data on the SCL low level.
49 * 0: sample SDA data on the SCL high level.
103 * This register is used to reset the scl FMS.
129 * When the I2C controller loses control of SCL line, this register changes to 1.
166 * This field indicates the states of the state machine used to produce SCL.
760 * Configures the hold time after a negative SCL edge.
765 * edge of SCL, in I2C module clock cycles.
773 * Configures the sample time after a positive SCL edge.
[all …]
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Di2c_struct.h24 * Configures the low level width of the SCL
30 * This register is used to configure for how long SCL remains low in master mode, in
40 * Configures the hold time after a negative SCL edge.
46 * edge of SCL, in I2C module clock cycles.
55 * Configures the sample time after a positive SCL edge.
70 * Configures the high level width of SCL
75 * This register is used to configure for how long SCL remains high in master mode, in
80 * This register is used to configure for the SCL_FSM's waiting period for SCL high
90 * Configures the delay between the SDA and SCL negative edge for a start condition
96 * of SDA and the negative edge of SCL for a START condition, in I2C module clock
[all …]
Di2c_reg.h24 * Configures the low level width of the SCL
29 * This register is used to configure for how long SCL remains low in master mode, in
57 * 1: sample SDA data on the SCL low level.
58 * 0: sample SDA data on the SCL high level.
121 * This register is used to reset the scl FMS.
176 * When the I2C controller loses control of SCL line, this register changes to 1.
205 * The cause of stretching SCL low in slave mode. 0: stretching SCL low at the
206 * beginning of I2C read data state. 1: stretching SCL low when I2C Tx FIFO is empty
207 * in slave mode. 2: stretching SCL low when I2C Rx FIFO is full in slave mode.
230 * This field indicates the states of the state machine used to produce SCL.
[all …]
Drtc_i2c_struct.h24 * configure low scl period
29 * time period that scl =0
116 * configure high scl period
121 * time period that scl = 1
135 * time period for SDA to toggle after SCL goes low
144 * configure scl start period
149 * time period for SCL to toggle after I2C start is triggered
158 * configure scl stop period
163 * time period for SCL to stop after I2C end is triggered
260 * scl last status
Drtc_i2c_reg.h24 * configure low scl period
28 * time period that scl =0
171 * scl last status
210 * configure high scl period
214 * time period that scl = 1
226 * time period for SDA to toggle after SCL goes low
234 * configure scl start period
238 * time period for SCL to toggle after I2C start is triggered
246 * configure scl stop period
250 * time period for SCL to stop after I2C end is triggered
/hal_espressif-latest/components/soc/esp32h2/include/soc/
Di2c_struct.h15 * Configures the low level width of the SCL
21 * This register is used to configure for how long SCL remains low in master mode, in
31 * Configures the hold time after a negative SCL edge.
37 * edge of SCL, in I2C module clock cycles.
46 * Configures the sample time after a positive SCL edge.
61 * Configures the high level width of SCL
66 * This register is used to configure for how long SCL remains high in master mode, in
71 * This register is used to configure for the SCL_FSM's waiting period for SCL high
81 * Configures the delay between the SDA and SCL negative edge for a start condition
87 * of SDA and the negative edge of SCL for a START condition, in I2C module clock
[all …]
Di2c_reg.h15 * Configures the low level width of the SCL
20 * This register is used to configure for how long SCL remains low in master mode, in
48 * 1: sample SDA data on the SCL low level.
49 * 0: sample SDA data on the SCL high level.
112 * This register is used to reset the scl FMS.
167 * When the I2C controller loses control of SCL line, this register changes to 1.
196 * The cause of stretching SCL low in slave mode. 0: stretching SCL low at the
197 * beginning of I2C read data state. 1: stretching SCL low when I2C Tx FIFO is empty
198 * in slave mode. 2: stretching SCL low when I2C Rx FIFO is full in slave mode.
221 * This field indicates the states of the state machine used to produce SCL.
[all …]
/hal_espressif-latest/components/soc/esp32c2/include/soc/
Di2c_struct.h15 * Configures the low level width of the SCL
21 * This register is used to configure for how long SCL remains low in master mode, in
31 * Configures the hold time after a negative SCL edge.
37 * edge of SCL, in I2C module clock cycles.
46 * Configures the sample time after a positive SCL edge.
61 * Configures the high level width of SCL
66 * This register is used to configure for how long SCL setup to high level and remains
71 * This register is used to configure for the SCL_FSM's waiting period for SCL high
81 * Configures the delay between the SDA and SCL negative edge for a start condition
87 * of SDA and the negative edge of SCL for a START condition, in I2C module clock
[all …]
Di2c_reg.h15 * Configures the low level width of the SCL
20 * This register is used to configure for how long SCL remains low in master mode, in
48 * 1: sample SDA data on the SCL low level.
49 * 0: sample SDA data on the SCL high level.
112 * This register is used to reset the scl FMS.
145 * When the I2C controller loses control of SCL line, this register changes to 1.
182 * This field indicates the states of the state machine used to produce SCL.
776 * Configures the hold time after a negative SCL edge.
781 * edge of SCL, in I2C module clock cycles.
789 * Configures the sample time after a positive SCL edge.
[all …]
/hal_espressif-latest/components/soc/esp32/include/soc/
Di2c_struct.h26 …_t period:14; /*This register is used to configure the low level width of SCL clock.*/
34 …scl clock 0: exchange the function of scl_o and scl_oe (scl_o is the original internal output scl…
35 …vel: 1; /*Set this bit to sample data in SCL low level. clear this bit to sample data in…
61 … 3; /*This register stores the value of state machine to produce SCL. 3'h0: SCL_IDLE 3'…
190 …s register is used to configure the clock num I2C used to hold the data after the negedge of SCL.*/
197 …gister is used to configure the clock num I2C used to sample data on SDA after the posedge of SCL*/
204 … 14; /*This register is used to configure the clock num during SCL is low level.*/
212 … is used to configure the clock num between the negedge of SDA and negedge of SCL for start mark.*/
219 … /*This register is used to configure the clock num between the posedge of SCL and the negedge of …
233 … /*This register is used to configure the clock num between the posedge of SCL and the posedge of …
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Di2c_reg.h24 /*description: This register is used to configure the low level width of SCL clock.*/
65 /*description: Set this bit to sample data in SCL low level. clear this bit
66 to sample data in SCL high level.*/
72 /*description: 1: normally ouput scl clock 0: exchange the function of scl_o
73 …l_oe (scl_o is the original internal output scl signal scl_oe is the enable bit for the internal …
88 /*description: This register stores the value of state machine to produce SCL.
608 hold the data after the negedge of SCL.*/
617 sample data on SDA after the posedge of SCL*/
625 /*description: This register is used to configure the clock num during SCL is low level.*/
634 negedge of SDA and negedge of SCL for start mark.*/
[all …]
Drtc_i2c_reg.h30 /*description: number of cycles that scl == 0 */
62 /*description: SCL is push-pull (1) or open-drain (0) */
76 /*description: state of SCL state machine */
241 /*description: Number of FAST_CLK cycles SDA will switch after falling edge of SCL */
249 /*description: Number of FAST_CLK cycles for SCL to be high */
/hal_espressif-latest/components/hal/esp32/include/hal/
Di2c_ll.h99 /* SCL period. According to the TRM, we should always subtract 1 to SCL low period */ in i2c_ll_set_bus_timing()
103 * if SCL filter is enabled, we have to subtract: in i2c_ll_set_bus_timing()
104 * 8 if SCL filter is between 0 and 2 (included) in i2c_ll_set_bus_timing()
105 * 6 + SCL threshold if SCL filter is between 3 and 7 (included) in i2c_ll_set_bus_timing()
106 * to SCL high period */ in i2c_ll_set_bus_timing()
160 * @brief Configure I2C SCL timing
163 * @param hight_period The I2C SCL hight period (in APB cycle)
164 * @param low_period The I2C SCL low period (in APB cycle)
495 * @brief Get I2C SCL timing configuration
498 * @param high_period Pointer to accept the SCL high period
[all …]
/hal_espressif-latest/components/hal/esp32c2/include/hal/
Di2c_ll.h87 //SCL in i2c_ll_cal_bus_clk()
134 * The SCL frequency would be a little higher than expected. Therefore, the solution in i2c_ll_set_bus_timing()
180 * @brief Configure I2C SCL timing
183 * @param hight_period The I2C SCL hight period (in core clock cycle, hight_period > 2)
184 * @param low_period The I2C SCL low period (in core clock cycle, low_period > 1)
524 * @brief Get I2C SCL timing configuration
527 * @param high_period Pointer to accept the SCL high period
528 * @param low_period Pointer to accept the SCL low period
621 * master can controls the SCL bus to generate 9 CLKs.
634 // hardward will clear scl_rst_slv_en after sending SCL pulses, in i2c_ll_master_clr_bus()
[all …]
/hal_espressif-latest/components/soc/esp32s2/include/soc/
Drtc_i2c_struct.h17 uint32_t period: 20; /*time period that scl = 0*/
50 uint32_t scl_state_last: 3; /*scl last status*/
72 uint32_t period: 20; /*time period that scl = 1*/
79 … uint32_t sda_duty_num:20; /*time period for SDA to toggle after SCL goes low*/
86 …uint32_t scl_start_period:20; /*time period for SCL to toggle after I2C start is trigger…
93 … uint32_t scl_stop_period:20; /*time period for SCL to stop after I2C end is triggered*/
/hal_espressif-latest/components/soc/esp32c3/include/soc/
Drtc_i2c_struct.h16 uint32_t period: 20; /*time period that scl = 0*/
49 uint32_t scl_state_last: 3; /*scl last status*/
71 uint32_t period: 20; /*time period that scl = 1*/
78 … uint32_t sda_duty_num:20; /*time period for SDA to toggle after SCL goes low*/
85 …uint32_t scl_start_period:20; /*time period for SCL to toggle after I2C start is trigger…
92 … uint32_t scl_stop_period:20; /*time period for SCL to stop after I2C end is triggered*/
/hal_espressif-latest/components/hal/esp32s2/include/hal/
Di2c_ll.h81 //SCL in i2c_ll_cal_bus_clk()
105 //scl period in i2c_ll_set_bus_timing()
148 * @brief Configure I2C SCL timing
151 * @param hight_period The I2C SCL hight period (in APB cycle, hight_period > 2)
152 * @param low_period The I2C SCL low period (in APB cycle, low_period > 1)
508 * @brief Get I2C SCL timing configuration
511 * @param high_period Pointer to accept the SCL high period
512 * @param low_period Pointer to accept the SCL low period
606 * master can controls the SCL bus to generate 9 CLKs.
666 …* If internal open-drain of the I2C module is disabled, scl and sda gpio should be configu…
[all …]
/hal_espressif-latest/components/hal/esp32c3/include/hal/
Di2c_ll.h88 //SCL in i2c_ll_cal_bus_clk()
135 * The SCL frequency would be a little higher than expected. Therefore, the solution in i2c_ll_set_bus_timing()
181 * @brief Configure I2C SCL timing
184 * @param hight_period The I2C SCL hight period (in core clock cycle, hight_period > 2)
185 * @param low_period The I2C SCL low period (in core clock cycle, low_period > 1)
540 * @brief Get I2C SCL timing configuration
543 * @param high_period Pointer to accept the SCL high period
544 * @param low_period Pointer to accept the SCL low period
639 * master can controls the SCL bus to generate 9 CLKs.
652 // hardward will clear scl_rst_slv_en after sending SCL pulses, in i2c_ll_master_clr_bus()
[all …]
/hal_espressif-latest/components/hal/esp32h2/include/hal/
Di2c_ll.h87 //SCL in i2c_ll_cal_bus_clk()
138 * The SCL frequency would be a little higher than expected. Therefore, the solution in i2c_ll_set_bus_timing()
184 * @brief Configure I2C SCL timing
187 * @param hight_period The I2C SCL hight period (in core clock cycle, hight_period > 2)
188 * @param low_period The I2C SCL low period (in core clock cycle, low_period > 1)
543 * @brief Get I2C SCL timing configuration
546 * @param high_period Pointer to accept the SCL high period
547 * @param low_period Pointer to accept the SCL low period
640 * master can controls the SCL bus to generate 9 CLKs.
653 // hardward will clear scl_rst_slv_en after sending SCL pulses, in i2c_ll_master_clr_bus()
[all …]
/hal_espressif-latest/components/hal/include/hal/
Di2c_types.h37 uint16_t scl_low; /*!< I2C scl low period */
38 uint16_t scl_high; /*!< I2C scl hight period */
39 uint16_t scl_wait_high; /*!< I2C scl wait_high period */
40 uint16_t sda_hold; /*!< I2C scl low period */
/hal_espressif-latest/components/hal/esp32s3/include/hal/
Di2c_ll.h87 //SCL in i2c_ll_cal_bus_clk()
134 * The SCL frequency would be a little higher than expected. Therefore, the solution in i2c_ll_set_bus_timing()
180 * @brief Configure I2C SCL timing
183 * @param high_period The I2C SCL hight period (in core clock cycle, hight_period > 2)
184 * @param low_period The I2C SCL low period (in core clock cycle, low_period > 1)
540 * @brief Get I2C SCL timing configuration
543 * @param high_period Pointer to accept the SCL high period
544 * @param low_period Pointer to accept the SCL low period
636 * master can controls the SCL bus to generate 9 CLKs.
762 * @brief Get I2C SCL timing configuration
[all …]
/hal_espressif-latest/components/hal/esp32c6/include/hal/
Di2c_ll.h87 //SCL in i2c_ll_cal_bus_clk()
138 * The SCL frequency would be a little higher than expected. Therefore, the solution in i2c_ll_set_bus_timing()
184 * @brief Configure I2C SCL timing
187 * @param hight_period The I2C SCL hight period (in core clock cycle, hight_period > 2)
188 * @param low_period The I2C SCL low period (in core clock cycle, low_period > 1)
543 * @brief Get I2C SCL timing configuration
546 * @param high_period Pointer to accept the SCL high period
547 * @param low_period Pointer to accept the SCL low period
640 * master can controls the SCL bus to generate 9 CLKs.
653 // hardward will clear scl_rst_slv_en after sending SCL pulses, in i2c_ll_master_clr_bus()
[all …]

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