Lines Matching full:scl
24 /*description: This register is used to configure the low level width of SCL clock.*/
65 /*description: Set this bit to sample data in SCL low level. clear this bit
66 to sample data in SCL high level.*/
72 /*description: 1: normally ouput scl clock 0: exchange the function of scl_o
73 …l_oe (scl_o is the original internal output scl signal scl_oe is the enable bit for the internal …
88 /*description: This register stores the value of state machine to produce SCL.
608 hold the data after the negedge of SCL.*/
617 sample data on SDA after the posedge of SCL*/
625 /*description: This register is used to configure the clock num during SCL is low level.*/
634 negedge of SDA and negedge of SCL for start mark.*/
643 posedge of SCL and the negedge of SDA for restart mark.*/
660 posedge of SCL and the posedge of SDA.*/
668 /*description: This is the filter enable bit for SCL.*/
674 /*description: When input SCL's pulse width is smaller than this register value
689 /*description: When input SCL's pulse width is smaller than this register value