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/Zephyr-latest/drivers/dma/
DKconfig.dw_common4 # SPDX-License-Identifier: Apache-2.0
20 bool "hardware supports scatter gather"
23 The hardware is by default expected to support hardware LLI (scatter gather).
24 When not enabled the driver will still perform scatter gather but using software
25 to run through the scatter gather list.
DKconfig.nios2_msgdma1 # Nios-II mSGDMA driver configuration options
4 # SPDX-License-Identifier: Apache-2.0
7 bool "Nios-II Modular Scatter-Gather DMA(MSGDMA) driver"
11 Enable Nios-II Modular Scatter-Gather DMA(MSGDMA) driver.
DKconfig.xilinx_axi_dma4 # SPDX-License-Identifier: Apache-2.0
15 bool "Disable data cache while accessing Scatter-Gather Descriptors."
19 Disable dcache while operating on Scatter-Gather descriptors.
29 The Xilinx AXI DMA uses a ring of in-memory DMA descriptors which reference
43 prompt "IRQs to lock when manipulating per-channel data structures during dma_start."
76 On certain platforms (e.g., RISC-V), the DMA driver can sometimes miss interrupts.
82 worst-case latency.
101 This is useful in conjunction with DMA_XILINX_AXI_DMA_INTERRUPT_THRESHOLD - the DMA
Ddma_intel_adsp_hda.c4 * SPDX-License-Identifier: Apache-2.0
34 const struct intel_adsp_hda_dma_cfg *const cfg = dev->config; in intel_adsp_hda_dma_host_in_config()
39 __ASSERT(channel < cfg->dma_channels, "Channel does not exist"); in intel_adsp_hda_dma_host_in_config()
40 __ASSERT(dma_cfg->block_count == 1, in intel_adsp_hda_dma_host_in_config()
41 "HDA does not support scatter gather or chained " in intel_adsp_hda_dma_host_in_config()
43 __ASSERT(dma_cfg->channel_direction == cfg->direction, in intel_adsp_hda_dma_host_in_config()
47 blk_cfg = dma_cfg->head_block; in intel_adsp_hda_dma_host_in_config()
48 buf = (uint8_t *)(uintptr_t)(blk_cfg->source_address); in intel_adsp_hda_dma_host_in_config()
49 res = intel_adsp_hda_set_buffer(cfg->base, cfg->regblock_size, channel, buf, in intel_adsp_hda_dma_host_in_config()
50 blk_cfg->block_size); in intel_adsp_hda_dma_host_in_config()
[all …]
Ddma_xilinx_axi_dma.c7 * SPDX-License-Identifier: Apache-2.0
40 /* internal DMA error, e.g., 0-length transfer */
59 /* interrupt timeout - trigger interrupt after X cycles when no transfer. Unit is 125 * */
62 /* irqthreshold - this can be used to generate interrupts after X completed packets */
84 /* run-stop */
100 /* scatter gather decode error */
102 /* scatter gather slave error */
104 /* scatter gather internal error, i.e., fetched a descriptor with complete bit already set */
113 /* scatter/gather support enabled at build time */
118 /* RS (run-stop) in DMACR is 0 and operations completed; writing tail does nothing */
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Ddma_dw_common.c4 * SPDX-License-Identifier: Apache-2.0
29 const struct dw_dma_dev_cfg *const dev_cfg = dev->config; in dw_dma_isr()
30 struct dw_dma_dev_data *const dev_data = dev->data; in dw_dma_isr()
39 status_intr = dw_read(dev_cfg->base, DW_INTR_STATUS); in dw_dma_isr()
41 LOG_ERR("%s: status_intr = %d", dev->name, status_intr); in dw_dma_isr()
45 status_block = dw_read(dev_cfg->base, DW_STATUS_BLOCK); in dw_dma_isr()
46 status_tfr = dw_read(dev_cfg->base, DW_STATUS_TFR); in dw_dma_isr()
49 status_err = dw_read(dev_cfg->base, DW_STATUS_ERR); in dw_dma_isr()
51 LOG_ERR("%s: status_err = %d\n", dev->name, status_err); in dw_dma_isr()
52 dw_write(dev_cfg->base, DW_CLEAR_ERR, status_err); in dw_dma_isr()
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Ddma_si32.c4 * SPDX-License-Identifier: Apache-2.0
70 result = -EIO; in dma_si32_isr_handler()
73 __ASSERT(channel_descriptor->CONFIG.TMD == 0, "Result of success: TMD set to zero"); in dma_si32_isr_handler()
74 __ASSERT(channel_descriptor->CONFIG.NCOUNT == 0, in dma_si32_isr_handler()
77 __ASSERT((SI32_DMACTRL_0->CHENSET.U32 & BIT(channel)) == 0, in dma_si32_isr_handler()
141 return -EINVAL; in dma_si32_config()
149 return -EBUSY; in dma_si32_config()
156 return -EINVAL; in dma_si32_config()
159 if (cfg->complete_callback_en > 1) { in dma_si32_config()
161 return -ENOTSUP; in dma_si32_config()
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Ddma_xmc4xxx.c4 * SPDX-License-Identifier: Apache-2.0
14 #include <zephyr/dt-bindings/dma/infineon-xmc4xxx-dma.h>
54 int channel = find_lsb_set(channels_event) - 1; \
58 dma_channel = &dev_data->channels[channel]; \
60 /* dma_start() and re-enable the event */ \
62 if (dma_channel->cb) { \
63 dma_channel->cb(dev, dma_channel->user_data, channel, (ret)); \
72 struct dma_xmc4xxx_data *dev_data = dev->data; in dma_xmc4xxx_isr()
73 const struct dma_xmc4xxx_config *dev_cfg = dev->config; in dma_xmc4xxx_isr()
74 int num_dma_channels = dev_data->ctx.dma_channels; in dma_xmc4xxx_isr()
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Ddma_mcux_edma.c2 * Copyright 2020-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
117 ((const struct dma_mcux_edma_config *const)dev->config)
118 #define DEV_DATA(dev) ((struct dma_mcux_edma_data *)dev->data)
119 #define DEV_BASE(dev) ((DMA_Type *)DEV_CFG(dev)->base)
122 ((struct call_back *)(&(DEV_DATA(dev)->data_cb[ch])))
125 ((edma_handle_t *)(&(DEV_CHANNEL_DATA(dev, ch)->edma_handle)))
128 #define DEV_DMAMUX_BASE(dev, idx) ((DMAMUX_Type *)DEV_CFG(dev)->dmamux_base[idx])
129 #define DEV_DMAMUX_IDX(dev, ch) (ch / DEV_CFG(dev)->channels_per_mux)
132 (ch % DEV_CFG(dev)->channels_per_mux) ^ (DEV_CFG(dev)->dmamux_reg_offset)
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Ddma_nxp_edma.c4 * SPDX-License-Identifier: Apache-2.0
16 * 5) Ideally, HALFMAJOR should be set on a per-channel basis not through a
30 cfg = chan->dev->config; in edma_isr()
31 data = chan->dev->data; in edma_isr()
33 if (chan->state == CHAN_STATE_RELEASING || chan->state == CHAN_STATE_INIT) { in edma_isr()
38 if (!EDMA_ChannelRegRead(data->hal_cfg, chan->id, EDMA_TCD_CH_INT)) { in edma_isr()
44 EDMA_ChannelRegUpdate(data->hal_cfg, chan->id, in edma_isr()
47 if (chan->cyclic_buffer) { in edma_isr()
48 update_size = chan->bsize; in edma_isr()
51 update_size = chan->bsize / 2; in edma_isr()
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Ddma_iproc_pax_v1.c4 * SPDX-License-Identifier: Apache-2.0
33 return ring->pkt_id = 0x0; in reset_pkt_id()
41 ring->pkt_id = (ring->pkt_id + 1) % 32; in alloc_pkt_id()
42 return ring->pkt_id; in alloc_pkt_id()
47 return ring->pkt_id; in curr_pkt_id()
52 return ring->curr.toggle; in curr_toggle_val()
63 r->opq = opq; in rm_write_header_desc()
65 r->bdcount = bdcount; in rm_write_header_desc()
66 r->prot = 0x0; in rm_write_header_desc()
68 r->start = 1; in rm_write_header_desc()
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/Zephyr-latest/tests/boards/altera_max10/msgdma/
DREADME.txt2 Altera Nios-II Modular Scatter Gather DMA (MSGDMA) soft IP core.
/Zephyr-latest/tests/drivers/dma/scatter_gather/
DKconfig2 # SPDX-License-Identifier: Apache-2.0
4 mainmenu "DMA Scatter Gather Test"
/Zephyr-latest/tests/drivers/dma/scatter_gather/src/
Dtest_dma_sg.c4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Verify zephyr dma memory to memory transfer loops with scatter gather
11 * - Test Steps
12 * -# Set dma configuration for scatter gather enable
13 * -# Set direction memory-to-memory with two block transfers
14 * -# Start transfer tx -> rx
15 * - Expected Results
16 * -# Data is transferred correctly from src buffers to dest buffers without
118 if (i < XFERS - 1) { in test_sg()
124 TC_PRINT("Configuring the scatter-gather transfer on channel %d\n", chan_id); in test_sg()
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/Zephyr-latest/dts/bindings/dma/
Daltr,msgdma.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Altera mSGDMA (Modular Scatter-Gather DMA)
8 include: dma-controller.yaml
17 "#dma-cells":
Dsilabs,ldma.yaml2 # SPDX-License-Identifier: Apache-2.0
7 The Silabs LDMA is a general-purpose direct memory access controller
9 functions like scatter-gather.
15 include: dma-controller.yaml
/Zephyr-latest/lib/mem_blocks/
DKconfig3 # SPDX-License-Identifier: Apache-2.0
14 This is useful for operations such as scatter-gather DMA
27 events, such as memory allocation and de-allocation.
/Zephyr-latest/drivers/net/
Dnsos.h2 * Copyright (c) 2023-2024 Marcin Niestroj
4 * SPDX-License-Identifier: Apache-2.0
29 NSOS_MID_IPPROTO_IP = 0, /**< IP protocol (pseudo-val for setsockopt() */
79 uint16_t sll_protocol; /**< Physical-layer protocol */
84 uint8_t sll_addr[8]; /**< Physical-layer address, big endian */
123 struct nsos_mid_iovec *msg_iov; /* scatter/gather array */
/Zephyr-latest/doc/kernel/memory_management/
Dsys_mem_blocks.rst14 This is useful for operations such as scatter-gather DMA transfers.
43 The buffer must be aligned to an N-byte boundary, where N is a power of 2
54 Each buffer associated with an allocator is an array of fixed-size blocks,
109 to a 4-byte boundary:
111 .. code-block:: c
117 .. code-block:: c
121 A pre-defined buffer can also be provided to the allocator where
125 .. code-block:: c
135 .. code-block:: c
153 .. code-block:: c
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/Zephyr-latest/include/zephyr/drivers/
Ddma.h10 * SPDX-License-Identifier: Apache-2.0
118 /** Address adjustment at gather boundary */
120 /** Address adjustment at scatter boundary */
122 /** Continuous transfer count between scatter boundaries */
124 /** Continuous transfer count between gather boundaries */
137 * - 0b00 increment
138 * - 0b01 decrement
139 * - 0b10 no change
145 * - 0b00 increment
146 * - 0b01 decrement
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Di2c.h10 * SPDX-License-Identifier: Apache-2.0
65 /** Use 10-bit addressing. DEPRECATED - Use I2C_MSG_ADDR_10_BITS instead. */
160 * that follows a write, or vice-versa. Some drivers will merge
165 /** Use 10-bit addressing for this message.
199 * @param result Result code of the transfer request. 0 is success, -errno for failure.
271 /** Target device responds to 10-bit addressing. */
470 return device_is_ready(spec->bus); in i2c_is_ready_dt()
482 return (msg->flags & I2C_MSG_READ) == I2C_MSG_READ; in i2c_is_read_op()
494 return (msg->flags & I2C_MSG_STOP) == I2C_MSG_STOP; in i2c_is_stop_op()
588 CONTAINER_OF(dev->state, struct i2c_device_state, devstate); in i2c_xfer_stats()
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Di3c.h5 * SPDX-License-Identifier: Apache-2.0
42 * - BCR[7:6]: Device Role
43 * - 0: I3C Target
44 * - 1: I3C Controller capable
45 * - 2: Reserved
46 * - 3: Reserved
48 * - BCR[5]: Advanced Capabilities
49 * - 0: Does not support optional advanced capabilities.
50 * - 1: Supports optional advanced capabilities which
53 * - BCR[4]: Virtual Target Support
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/Zephyr-latest/doc/releases/
Drelease-notes-3.1.rst61 * Split CAN classic and CAN-FD APIs:
90 was moved from Kconfig to :ref:`devicetree <dt-guide>`.
91 See the :dtcompatible:`st,stm32f1-pinctrl` devicetree binding for more information.
182 * MIPI-DSI
184 * Added a :ref:`MIPI-DSI api <mipi_dsi_api>`. This is an experimental API,
196 * Added support for enabling/disabling CAN-FD mode at runtime using :c:macro:`CAN_MODE_FD`.
220 * Added support for Provisioners over PB-GATT
231 * Implemented ISO-AL TX unframed fragmentation
232 * Added support for back-to-back receiving of PDUs on nRF5x platforms
249 newly created informational-only callback struct :c:struct:`bt_conn_auth_info_cb`.
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Drelease-notes-1.12.rst12 - Asymmetric multiprocessing (AMP) via integration of OpenAMP
13 - Persistent storage support for Bluetooth Low Energy including Mesh
14 - 802.1Q - Virtual Local Area Network (VLAN) traffic on an Ethernet network
15 - Support multiple concurrent filesystem devices, partitions, and FS types
16 - Ethernet network management interface
17 - Networking traffic prioritization on a per-connection basis
18 - Support for Ethernet statistical counters
19 - Support for TAP net device on the native POSIX port
20 - Command-line Zephyr meta-tool "west"
21 - SPI slave support
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/Zephyr-latest/include/zephyr/net/
Dnet_ip.h10 * SPDX-License-Identifier: Apache-2.0
50 #define PF_LOCAL 6 /**< Inter-process communication */
51 #define PF_UNIX PF_LOCAL /**< Inter-process communication */
60 #define AF_LOCAL PF_LOCAL /**< Inter-process communication */
61 #define AF_UNIX PF_UNIX /**< Inter-process communication */
65 IPPROTO_IP = 0, /**< IP protocol (pseudo-val for setsockopt() */
94 /** @brief Convert 16-bit value from network to host byte order.
102 /** @brief Convert 32-bit value from network to host byte order.
110 /** @brief Convert 64-bit value from network to host byte order.
118 /** @brief Convert 16-bit value from host to network byte order.
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