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/Zephyr-latest/dts/bindings/mtd/
Dnordic,owned-partitions.yaml2 # SPDX-License-Identifier: Apache-2.0
5 Nordic Owned Partitions
7 Memory partition table with permission attributes common to its partitions.
11 listed partitions belong.
15 spanning the contained partitions will be recorded in the UICR. These regions
16 are allowed to contain gaps between the partitions, but this is discouraged.
25 rx-partitions {
26 compatible = "nordic,owned-partitions";
28 #address-cells = <1>;
29 #size-cells = <1>;
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/Zephyr-latest/boards/nordic/nrf54h20dk/
Dnrf54h20dk_nrf54h20-memory_map.dtsi4 * SPDX-License-Identifier: Apache-2.0
6 #include <zephyr/dt-bindings/memory-attr/memory-attr.h>
9 reserved-memory {
11 compatible = "nordic,owned-memory";
15 #address-cells = <1>;
16 #size-cells = <1>;
29 compatible = "nordic,owned-memory";
33 #address-cells = <1>;
34 #size-cells = <1>;
51 compatible = "nordic,owned-memory";
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/Zephyr-latest/boards/nordic/nrf9280pdk/
Dnrf9280pdk_nrf9280-memory_map.dtsi4 * SPDX-License-Identifier: Apache-2.0
6 #include <zephyr/dt-bindings/memory-attr/memory-attr.h>
9 reserved-memory {
15 compatible = "nordic,owned-memory";
19 #address-cells = <1>;
20 #size-cells = <1>;
33 compatible = "nordic,owned-memory";
37 #address-cells = <1>;
38 #size-cells = <1>;
55 compatible = "nordic,owned-memory";
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/Zephyr-latest/boards/intel/ish/doc/
Dindex.rst8 Intel Integrated Sensor Hub (ISH) is a lower-power/always-on co-processor
15 - LMT MinuteIA Core:
17 - 16KB instruction cache and 16KB data cache.
18 - 640KB SRAM space for code and data - implemented as L2 SRAM.
19 - 8KB AON RF space for code resident during deep D0i2/3 PG states.
21 - Interface-to-Sensor peripherals (I2C, SPI, UART, I3C, GPIO, DMA).
22 - Inter Process Communications (IPC) to core processor and other IP processors.
42 .. zephyr-app-commands::
43 :zephyr-app: samples/hello_world
55 - Power on the ADL RVP board.
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/Zephyr-latest/tests/arch/x86/pagetables/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
9 * x86-specific tests for MMU features and page tables
17 #include <zephyr/linker/linker-defs.h>
57 #include <zephyr/sys/libc-hooks.h>
71 "non-present RAM entry"); in get_entry()
126 * partitions within it would be active in in ZTEST()
128 * partitions) in ZTEST()
154 * guard pages will have RW cleared. We can relax this in ZTEST()
155 * once we start memory-mapping stacks. in ZTEST()
198 * We currently identity-map on x86, no conversion necessary other than a cast in ZTEST()
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/Zephyr-latest/arch/x86/core/
Dx86_mmu.c2 * Copyright (c) 2011-2014 Wind River Systems, Inc.
3 * Copyright (c) 2017-2020 Intel Corporation
5 * SPDX-License-Identifier: Apache-2.0
29 * when the mapping was made. This is used to un-apply memory domain memory
30 * partitions to page tables when the partitions are removed.
51 * - If the entire entry is zero, it's an un-mapped virtual page
52 * - If PTE_ZERO is set, we flipped this page due to KPTI
53 * - Otherwise, this was a page-out
87 /* How many bits to right-shift a virtual address to obtain the
105 * We want RW and US bit always set; actual access control will be
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/Zephyr-latest/arch/arm64/core/
Dmmu.c7 * SPDX-License-Identifier: Apache-2.0
22 #include <zephyr/linker/linker-defs.h>
63 unsigned int i = (pte - xlat_tables) / Ln_XLAT_NUM_ENTRIES; in table_index()
78 MMU_DEBUG("table [%d]%p: usage %#x -> %#x\n", i, table, prev_count, new_count); in table_usage()
101 table_usage(table, -ref_unit); in dec_table_ref()
175 bool aligned = (desc & PTE_PHYSADDR_MASK & (level_size - 1)) == 0; in is_desc_block_aligned()
200 MMU_DEBUG("---\n"); in debug_show_pte()
218 MMU_DEBUG("[paged-out] "); in debug_show_pte()
225 MMU_DEBUG((*pte & PTE_BLOCK_DESC_AP_RO) ? "-RO" : "-RW"); in debug_show_pte()
226 MMU_DEBUG((*pte & PTE_BLOCK_DESC_NS) ? "-NS" : "-S"); in debug_show_pte()
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/Zephyr-latest/doc/hardware/arch/
Darm_cortex_m.rst3 Arm Cortex-M Developer Guide
9 This page contains detailed information about the status of the Arm Cortex-M
11 developing Zephyr applications for Arm Cortex-M-based platforms.
17 Arm Cortex-M implementation variants.
20 …---------------------------------+-----------------------------------+-----------------+---------+…
22 …---------------------------------+-----------------------------------+-----------------+---------+…
23 … | Arm v6-M | Arm v7-M | Arm v8-M …
24 …---------------------------------+-----------------------------------+-----------------+---------+…
26 …---------------------------------+-----------------------------------+-----------------+---------+…
28 …---------------------------------+-----------------------------------+-----------------+---------+…
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/Zephyr-latest/doc/releases/
Drelease-notes-2.7.rst17 * Support for M-Profile Vector Extensions (MVE) on ARMv8.1-M
18 * Improved thread safety for Newlib and C++ on SMP-capable systems
20 * New Action-based Power Management API
23 * Linker Support for Tightly-Coupled Memory in RISC-V
25 * Support for extended PCI / PCIe capabilities, improved MIS-X support
33 * The kernel now supports both 32- and 64-bit architectures
36 * We added support for Point-to-Point Protocol (PPP)
37 * We added support for UpdateHub, an end-to-end solution for over-the-air device updates
38 * We added support for ARM Cortex-R Architecture
40 * Expanded support for ARMv6-M architecture
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