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/Zephyr-Core-3.5.0/drivers/sensor/icm42688/
Dicm42688_emul.c3 * SPDX-License-Identifier: Apache-2.0
22 uint8_t reg[NUM_REGS]; member
31 struct icm42688_emul_data *data = target->data; in icm42688_emul_set_reg()
34 memcpy(data->reg + reg_addr, val, count); in icm42688_emul_set_reg()
39 struct icm42688_emul_data *data = target->data; in icm42688_emul_get_reg()
42 memcpy(val, data->reg + reg_addr, count); in icm42688_emul_get_reg()
47 struct icm42688_emul_data *data = target->data; in icm42688_emul_handle_write()
53 memset(data->reg, 0, NUM_REGS); in icm42688_emul_handle_write()
54 /* Initialized the who-am-i register */ in icm42688_emul_handle_write()
55 data->reg[REG_WHO_AM_I] = WHO_AM_I_ICM42688; in icm42688_emul_handle_write()
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/Zephyr-Core-3.5.0/dts/arm64/ti/
Dti_am62x_a53.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 #include <arm64/armv8-a.dtsi>
10 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
11 #include <zephyr/dt-bindings/pinctrl/ti-k3-pinctrl.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "arm,cortex-a53";
24 reg = <0>;
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/Zephyr-Core-3.5.0/drivers/sensor/akm09918c/
Dakm09918c_emul.c3 * SPDX-License-Identifier: Apache-2.0
25 uint8_t reg[NUM_REGS]; member
34 struct akm09918c_emul_data *data = target->data; in akm09918c_emul_set_reg()
37 memcpy(data->reg + reg_addr, val, count); in akm09918c_emul_set_reg()
42 struct akm09918c_emul_data *data = target->data; in akm09918c_emul_get_reg()
45 memcpy(val, data->reg + reg_addr, count); in akm09918c_emul_get_reg()
50 struct akm09918c_emul_data *data = target->data; in akm09918c_emul_reset()
52 memset(data->reg, 0, NUM_REGS); in akm09918c_emul_reset()
53 data->reg[AKM09918C_REG_WIA1] = AKM09918C_WIA1; in akm09918c_emul_reset()
54 data->reg[AKM09918C_REG_WIA2] = AKM09918C_WIA2; in akm09918c_emul_reset()
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/Zephyr-Core-3.5.0/drivers/sensor/f75303/
Df75303_emul.c3 * SPDX-License-Identifier: Apache-2.0
22 uint8_t reg[NUM_REGS]; member
28 static void f75303_emul_set_reg(const struct emul *target, uint8_t reg, uint8_t val) in f75303_emul_set_reg() argument
30 struct f75303_emul_data *data = target->data; in f75303_emul_set_reg()
32 __ASSERT_NO_MSG(reg < NUM_REGS); in f75303_emul_set_reg()
33 data->reg[reg] = val; in f75303_emul_set_reg()
36 static uint8_t f75303_emul_get_reg(const struct emul *target, uint8_t reg) in f75303_emul_get_reg() argument
38 struct f75303_emul_data *data = target->data; in f75303_emul_get_reg()
40 __ASSERT_NO_MSG(reg < NUM_REGS); in f75303_emul_get_reg()
41 return data->reg[reg]; in f75303_emul_get_reg()
[all …]
/Zephyr-Core-3.5.0/include/zephyr/dt-bindings/clock/
Dstm32l1_clock.h4 * SPDX-License-Identifier: Apache-2.0
39 * - reg (1/2/3) [ 0 : 7 ]
40 * - shift (0..31) [ 8 : 12 ]
41 * - mask (0x1, 0x3, 0x7) [ 13 : 15 ]
42 * - val (0..7) [ 16 : 18 ]
44 * @param reg RCC_CCIPRx register offset
45 * @param shift Position within RCC_CCIPRx.
49 #define STM32_CLOCK(val, mask, shift, reg) \ argument
50 ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
51 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
Dstm32f1_clock.h4 * SPDX-License-Identifier: Apache-2.0
40 * - reg (1/2/3) [ 0 : 7 ]
41 * - shift (0..31) [ 8 : 12 ]
42 * - mask (0x1, 0x3, 0x7) [ 13 : 15 ]
43 * - val (0..7) [ 16 : 18 ]
45 * @param reg RCC_CFGRx register offset
46 * @param shift Position within RCC_CFGRx.
50 #define STM32_CLOCK(val, mask, shift, reg) \ argument
51 ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
52 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
Dstm32f4_clock.h4 * SPDX-License-Identifier: Apache-2.0
52 * - reg (1/2/3) [ 0 : 7 ]
53 * - shift (0..31) [ 8 : 12 ]
54 * - mask (0x1, 0x3, 0x7) [ 13 : 15 ]
55 * - val (0..7) [ 16 : 18 ]
57 * @param reg RCC_CFGRx register offset
58 * @param shift Position within RCC_CFGRx.
62 #define STM32_CLOCK(val, mask, shift, reg) \ argument
63 ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
64 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
Dstm32f0_clock.h4 * SPDX-License-Identifier: Apache-2.0
44 * - reg (1/2/3) [ 0 : 7 ]
45 * - shift (0..31) [ 8 : 12 ]
46 * - mask (0x1, 0x3, 0x7) [ 13 : 15 ]
47 * - val (0..7) [ 16 : 18 ]
49 * @param reg RCC_CFGRx register offset
50 * @param shift Position within RCC_CFGRx.
54 #define STM32_CLOCK(val, mask, shift, reg) \ argument
55 ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
56 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
Dstm32c0_clock.h4 * SPDX-License-Identifier: Apache-2.0
43 * - reg (1/2/3) [ 0 : 7 ]
44 * - shift (0..31) [ 8 : 12 ]
45 * - mask (0x1, 0x3, 0x7) [ 13 : 15 ]
46 * - val (0..7) [ 16 : 18 ]
48 * @param reg RCC_CCIPRx register offset
49 * @param shift Position within RCC_CCIPRx.
53 #define STM32_CLOCK(val, mask, shift, reg) \ argument
54 ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
55 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
Dstm32l0_clock.h4 * SPDX-License-Identifier: Apache-2.0
44 * - reg (1/2/3) [ 0 : 7 ]
45 * - shift (0..31) [ 8 : 12 ]
46 * - mask (0x1, 0x3, 0x7) [ 13 : 15 ]
47 * - val (0..7) [ 16 : 18 ]
49 * @param reg RCC_CCIPRx register offset
50 * @param shift Position within RCC_CCIPRx.
54 #define STM32_CLOCK(val, mask, shift, reg) \ argument
55 ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
56 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
Dstm32wba_clock.h4 * SPDX-License-Identifier: Apache-2.0
45 * - reg (1/2/3) [ 0 : 7 ]
46 * - shift (0..31) [ 8 : 12 ]
47 * - mask (0x1, 0x3, 0x7) [ 13 : 15 ]
48 * - val (0..7) [ 16 : 18 ]
50 * @param reg RCC_CCIPRx register offset
51 * @param shift Position within RCC_CCIPRx.
65 #define STM32_CLOCK(val, mask, shift, reg) \ argument
66 ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
67 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
Dstm32wb_clock.h4 * SPDX-License-Identifier: Apache-2.0
52 * - reg (1/2/3) [ 0 : 7 ]
53 * - shift (0..31) [ 8 : 12 ]
54 * - mask (0x1, 0x3, 0x7) [ 13 : 15 ]
55 * - val (0..7) [ 16 : 18 ]
57 * @param reg RCC_CCIPRx register offset
58 * @param shift Position within RCC_CCIPRx.
62 #define STM32_CLOCK(val, mask, shift, reg) \ argument
63 ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
64 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
Dstm32wl_clock.h4 * SPDX-License-Identifier: Apache-2.0
50 * - reg (1/2/3) [ 0 : 7 ]
51 * - shift (0..31) [ 8 : 12 ]
52 * - mask (0x1, 0x3, 0x7) [ 13 : 15 ]
53 * - val (0..7) [ 16 : 18 ]
55 * @param reg RCC_CCIPRx register offset
56 * @param shift Position within RCC_CCIPRx.
60 #define STM32_CLOCK(val, mask, shift, reg) \ argument
61 ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
62 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
Dstm32f3_clock.h4 * SPDX-License-Identifier: Apache-2.0
44 * - reg (1/2/3) [ 0 : 7 ]
45 * - shift (0..31) [ 8 : 12 ]
46 * - mask (0x1, 0x3, 0x7) [ 13 : 15 ]
47 * - val (0..7) [ 16 : 18 ]
49 * @param reg RCC_CFGRx register offset
50 * @param shift Position within RCC_CFGRx.
54 #define STM32_CLOCK(val, mask, shift, reg) \ argument
55 ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
56 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
/Zephyr-Core-3.5.0/include/zephyr/dt-bindings/adc/
Dstm32_adc.h4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/adc/adc.h>
25 * - reg (0..0xFF) [ 0 : 7 ]
26 * - shift (0..31) [ 8 : 12 ]
27 * - mask (0x1, 0x3, 0x7) [ 13 : 15 ]
28 * - reg_val (0..7) [ 16 : 18 ]
29 * - real_val (0..8191) [ 19 : 31 ]
31 * @param reg ADC_x register offset
32 * @param shift Position within ADC_x.
37 #define STM32_ADC(real_val, reg_val, mask, shift, reg) \ argument
[all …]
/Zephyr-Core-3.5.0/dts/arm/broadcom/
Dvalkyrie.dtsi1 /* SPDX-License-Identifier: Apache-2.0 */
6 #include <arm/armv7-m.dtsi>
7 #include <broadcom/valkyrie-irq.h>
11 #address-cells = <1>;
12 #size-cells = <0>;
16 compatible = "arm,cortex-m7";
17 reg = <0>;
18 #address-cells = <1>;
19 #size-cells = <1>;
22 compatible = "arm,armv7m-mpu";
[all …]
Dviper-common.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 reg = <0x00400000 0x80000>;
16 reg = <0x40020000 0x400>;
17 clock-frequency = <25000000>;
18 reg-shift = <2>;
24 reg = <0x48100000 0x400>;
25 clock-frequency = <100000000>;
26 reg-shift = <2>;
31 compatible = "arm,dma-pl330";
32 reg = <0x48300000 0x2000>,
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/Zephyr-Core-3.5.0/dts/arc/synopsys/
Darc_hs4xd.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
20 reg = <0>;
26 reg = <1>;
32 reg = <2>;
38 reg = <3>;
43 intc: arcv2-intc {
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Darc_hsdk.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
20 reg = <0>;
26 reg = <1>;
32 reg = <2>;
38 reg = <3>;
43 intc: arcv2-intc {
[all …]
/Zephyr-Core-3.5.0/dts/riscv/microchip/
Dmpfs-icicle.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
18 clock-frequency = <0>;
21 reg = < 0x0 >;
23 hlic0: interrupt-controller {
24 compatible = "riscv,cpu-intc";
[all …]
/Zephyr-Core-3.5.0/dts/arm64/broadcom/
Dviper-common.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 reg = <0x00400000 0x80000>;
16 reg = <0x40020000 0x400>;
17 reg-shift = <2>;
18 clock-frequency = <25000000>;
24 reg = <0x48100000 0x400>;
25 reg-shift = <2>;
26 clock-frequency = <100000000>;
31 compatible = "arm,dma-pl330";
32 reg = <0x48300000 0x2000>,
[all …]
/Zephyr-Core-3.5.0/dts/bindings/serial/
Dns16550.yaml5 include: [uart-controller.yaml, pcie-device.yaml, pinctrl-device.yaml, reset-device.yaml]
8 reg-shift:
11 description: quantity to shift the register offsets by
21 io-mapped:
/Zephyr-Core-3.5.0/boards/arc/qemu_arc/
Dqemu_arc.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
17 #address-cells = <1>;
18 #size-cells = <0>;
21 intc: arcv2-intc {
22 compatible = "snps,arcv2-intc";
23 interrupt-controller;
24 #interrupt-cells = <2>;
28 compatible = "snps,arc-timer";
30 interrupt-parent = <&intc>;
[all …]
/Zephyr-Core-3.5.0/drivers/gpio/
Dgpio_mcux_igpio.c4 * SPDX-License-Identifier: Apache-2.0
46 const struct mcux_igpio_config *config = dev->config; in mcux_igpio_configure()
47 GPIO_Type *base = config->base; in mcux_igpio_configure()
52 /* Some SOCs have non-contiguous gpio pin layouts, account for this */ in mcux_igpio_configure()
53 for (i = 0; i < config->gap_count; i++) { in mcux_igpio_configure()
54 if (pin >= config->pin_gaps[i].start) { in mcux_igpio_configure()
55 if (pin < (config->pin_gaps[i].start + in mcux_igpio_configure()
56 config->pin_gaps[i].len)) { in mcux_igpio_configure()
58 return -ENOTSUP; in mcux_igpio_configure()
60 cfg_idx -= config->pin_gaps[i].len; in mcux_igpio_configure()
[all …]
/Zephyr-Core-3.5.0/dts/x86/intel/
Delkhart_lake.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/pcie/pcie.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "intel,elkhart-lake";
20 d-cache-line-size = <64>;
21 reg = <0>;
28 reg = <0x0 DT_DRAM_SIZE>;
[all …]

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